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STM32L4 Seminars Fall 2015 - Rev13

1. 224 E r Y T 58 48 18 8 25 Lr pP t mE eee 42 2 qu 4 n nr E I T L T i 4 4 lite augmented Hands On Lab 2 printf debugging Adding to the existing CubeMX project we will add USART2 debug via the ST LINK Virtual COM port Set up additional GPIO Clocks PD5 USART2 VirtualCOM TX Alt Fn Push Pull PD6 USART2 VirtrualCOM RX Alt Fn Push Pull PAO GPIO EXTIO External Interrupt on Rising Edge Input USART2 Clock PCLK1 80MHz USART2 settings Asynchronous Mode 9600 N 8 1 No HW Flow control Tx Rx 16 sample oversampling No advanced features User Code HAL function calls required See lab2 printf debug c Lab2 Printf directory Also Need Terminal emulator Hyperterm etc USART2 is routed to the ST LINK s and brought via the USB Virtual COM port class SB13 16 have been soldered GPIO Configuration additions Expand the USART2 dialog and select Asynchronous mode USART2 Mode Asynchronous Control 85232 Disable Hardware Control RS485 F USR OTG FS e Use PDS amp PD6 for Tx Rx pins These are the alternate mapping pins PA2 3 are default Use PAO in External Interrupt Mode Rising edge trigger Configuration GPIO EXTIO 142 GPIO mode External Interrupt Mode with Rising edge trigger detection
2. 1262 MHz PLLSAT2P PLLP 18 285714 SAI1 MHz X 9 12C3 MHz PLLSATiP PLLSAI2P 18 285714 5 12 MHz SAI2 EXT DFSDM Clock Mux PCLKI gt LSCO Source Mux s DFSDM MHz Clock Tree feo Power MHz W HCLK to AHB bus core memory and DMA MHz Cortex System timer MHz 2248 peripheral clocks MHz ES Timer clocks MHz peripheral clocks MHz timer clocks MHz USART2 Clock Mux UART4 Clock Mux LPUART 1 Clock Mux re LPUART1 MHz LPTIM1 Clock Mux 151 LSE 74 LPTIM2 Clock Mux SWPMI1 Clock Mux fro swour lt Clocks MSI Multi Speed Internal e MSI clock at startup from Reset Standby or Shutdown modes e 12 Programmable frequency ranges 100 kHz 200 kHz 400 kHz 800 kHz 1 MHz 2 MHz 4 MHz reset value 8 MHz 16 MHz 24 MHz 32 MHz 48 MHz After Standby Frequency selected from 1 2 4 or 8 MHz with MSISRANGE in RCC_CSR register Normal mode and PLL mode auto calibration with LSE PLL mode allows USB FS device functionality 0 2596 accuracy e Factory and user trimmed Ly life augmented Clocks HSI High Speed Internal HSI 16MHz factory and user trimmed Selectable
3. 398 608 CoreMark 120 MHz 180 MHz 200 1 150 DMIPS 225 DMIPS 428 DMIPS I a Mainstream 106 CoreMark 177 CoreMark i 48 MHz 72 MHZ 1 90 DMIPS 61 DMIPS Hn BH gt Ultra low power 75 CoreMark 93 CoreMark 273 CoreMark 32 MHz 32 MHz 80 MHz 26 DMIPS 33 DMIPS 100 DMIPS Cortex MO Cortex M3 Cortex M4 7 Cortex MO Great investment 1 number of lines Ly life augmented S T M32L Ultra Low Power offering STM32L4 completes the ultra low power family Cost smart ULP Champion Cortex M0 32 MHz Operating range 1 65 to 3 6V 8 16 bit applications Numerous pin counts 3 product lines Cost effective smaller packages USB LCD Analog 16 to 192 Kbytes of Flash Up to 20 Kbytes of SRAM lite augmented Broad Range Foundation Cortex M3 32 MHz Operating range 1 65 to 3 6V Wide choice of memory sizes 3 product lines USB LCD AES Rich Analog True EEPROM Dual bank Flash RWW 32 to 512 Kbytes of Flash Up to 80 Kbytes of SRAM ULP with performance STM32 14 Cortex M4 w FPU 80 MHz Operating range 1 71 to 3 6V Advanced Peripheral Performance 3 product lines ADC 5 Msps Compar LCD AES 256 Kbytes to 1 Mbyte of Flash
4. STOP 1 full retention 7 3 7 6 Wake up sources all UART 6 cycles SLEEP 35 uA MHz sources any interrupt RUN at 24 MHz 100 MHz RUN at 80 MHz 112 uA MHz Note without RTC with RTC Ly ULP leader and performance booster life augmented O TM32L4 This ULPBench winner takes off like a rocket And shatters performance limits in ULP world Dhrystone ars 100 The higher the better From 0 to 48 MHz in less than 5 us From 0 80 MHz in less than 20 us 9 STM32L4 eT 9A 160 140 120 100 Voltage V On competition devices discontinuity due to lack of DC DC A functionality when voltage decreases No external coil and capacitor required for STM32L4 Providing more performance Do compromise performance with STM32L4 CoreMark Execution performance score from Flash 273 _ Up to 80 MHz 100 DMIPS with Linear performance thanks to ST ART Accelerator ART Accelerator floating point unit FPU Optimized DMA 14 channels upto 40 Mbit s USART 10 Mbit s Competitors impact of wait states Up to 273 CoreMark Result ARM 4 with DSP instructions and CPU frequency 80 MHz Ly e ULP leader and performance booster life augmented High integration High
5. Alf ge ike ii etin me E fide ail 1 grt sipasmi 11113111 ia e o S 1 Hello World for the TextLCD 407490 example 2 Function printf Print formatted output Default Program include mbed h lint printf const char DGWWebServer 4 include TextLCD h y HTTPClient_HelloWorld TextLCD lcd p15 16 p17 p18 p19 p20 rs 44 47 8 int 9 int 0 11 1 4 World n 12 SensorStream_MouseDemo 9 TextLCD HelloWorld y VodafoneUSBModemSMSTes Websocket Wifly HelloWorlc 2 WiFiTerminal wifi cc3000 Compile output for program TextLCD_HelloWorld Errors Warnings 1 Infos 1 xively jumpstart demo Description Error Number Resource In Folder Location Variable 7 was declared but never referenced int i 0 main cpp Line 9 Col 8 Success Build Details _ colts 13 NS STM382CubeMxX Partners IDEs SIMStudio Generate Code Compile amp Debug Monitor ARMKEIU
6. Create New Project e Select STM32L476VGTx LQFP100 1024KB Flash Boar GG 99 MCU Filters Click OK Series Lines STM3214 STM32L4x6 xj Flash gt 256 KBytes Eeprom 0 Bytes 256 1024 Peripheral Selection MCUs List 4 Items Peripherals Nb Max MCU Lines Package Flash Ram 10 12 bit 0 STM32L476VCTx STM32L4x6 LQFP100 256 128 ADC 16 bit 0 O STM32L476VETX LQFP100 TE NN can Joji rm aes ae DUE OSA 12 51057 STM32CubeMX Untitled File Project Window Help E fEthernet EY 17 Load Project Ly life augmented otep 2 Pin Configuration In this example we are going to use the LED s present on the STM32L476 Discovery board Left click PB2 amp and set to GPIO Output mode g T z g i 2 m a gt EL E oo amp n ju amp T amp aja amp a ran p us Reset State 1 INP IDFSDM CKINO STM32 I2C3 5 MD 10 pes pes pee pois PD uu pus 38 dincy code fy Ly life augmented Step 3 Generate Source Code File Proje
7. 1 DMA 1 SRAM SRAM1 or SRAM2 are configured with clock enable in Sleep mode Flash is in power down mode Enter either Sleep or Low power sleep mode 7 12 clock can be at 16 MHz allowing FM support life augmented e 4 Hands On Lab 4 communications to MEMS Gyro Ly lite augmented Hands On Lab 4 SPI communications to 3 axis Gyro ki m E gt 22008140 EE E a AR i NE a lt 2 MEL T p 1 a Adding to the existing CubeMX project we will add SPI communications to the 36020 MEMS gyroscope oet up additional GPIO Clocks PD1 SPI2 SCK Alt Fn Push Pull SPI2 MISO Alt Fn Push Pull PD4 SPI2 MOSI Alt Fn Push Pull PD7 nCS GPIO Output Push Pull mode 2 settings Full Duplex Master Motorola 8 bit MSB first Prescaler 16 CPOL Low CPHA 1 Edge No CRC Software NSS User Code HAL function calls required to be added to main c C STM32L4Seminar Labs lab4_spi_gyro c Gyro under LCD is routed 5 2 Regenerate Source Code for Configuration 47 Parameter Settings STM32CubeMX LabLioc STM32L476VGTx Configure the below parameters File Project Pinout Window Help Ros BE amp F Keep current Signals Placement El Basic Parameters Pinout ea ae
8. KEY message LPUART adds STOP2 wakeup but is a subset of USART however it is much lower power Ly life augmented amp Innovation STM32L4 USART Implementation e USART s 2x UART s and LPUART USART features USART1 2 3 4 5 LPUART Hardware Flow Control Continous communication using DMA Multiprocessor communication Synchronous mode Smartcard mode Single wire half duplex mode IrDA LIN Dual clock wake up from STOP 1 Dual clock wake up from STOP2 Receiver timeout Modbus Communication Autobaudrate detection RS 485 Driver enable Ly life augmented YES YES YES YES YES YES YES YES NO YES YES YES YES YES YES NO NO YES YES YES YES NO YES YES YES YES YES YES NO NO YES NO NO YES YES NO NO NO YES Smart peripherals STM32L4 Programmable frame from 4 to 16bit bit granularity 32 bit FIFO to optimize bus bandwidth performance amp power consumption e BUSY status bit IP fix e Up to 40 Mbits s in master mode 125 functionality no longer supported SPI Now in SAI peripheral Ly lite augmented e Innovation omart peripherals oensor Hub scenario Sensors lt STM32L4 STOP Host lt gt 53 Processor SPI UART 3x SPI 6x USART Batch Acquisition Mode BAM Optimized mode for transferring data while the system is in low power mode m Only the needed communication peripheral
9. Preemption Interruption of the exception handler Depending on the priority If higher priority exception request comes while another lower priority exception handler is executing the higher priority exception can preempt the lower priority exception handler e Such exceptions are called nested exceptions Exception Response Standard exception latency is 12 cycles The latency from processor clock cycle time when the exception is asserted to the first instruction of the exception handler execution 0 memory wait states e Can be reduced by the following two mechanisms Tail Chaining If exception request exists or occurs just as another exception handler returns Stacking process can be skipped Late arriving Late arrival If higher priority exception request occurs during lower prority exception stacking process Higher priority exception handler is called right after the stacking finishes life augmented Interrupt Response Tail Chaining 42 CYCLES k 26 16 26 k 16 Tail chaining S Interrupt handling in HW 2 16 Ly life augmented Interrupt Response Late Arriving IRQ2 Highest 7 Cortex MO STMS32Cube Introduction e STM32Cube M includes Aconfiguration tool STM32CubeMX generating initialization code from user choices Firmware offering delivered per series like S TM32CubeF4 wi
10. STM32L4 MCU series Excellence in ultra low power with performance bud f life augmented Ly ite augmented Agenda Presentation 8 00 9 00 9 00 12 00 12 00 1 00 1 00 3 00 oystem check for pre installed tools Tools handout 3214 Family amp Tools Overview Hands On Session Out of the box demos Cortex M4 core Hands On Lab 1 Getting Started with CubeMX and STM32L4 STM32L4 Overview Architecture Memory Clocks Power Hands On Lab 2 printf debugging via onboard ST LINK STM32L4 Low Power details Hands On Lab 3 STM32CubeMX Power Consumption Calculator Lunch 3214 Peripherals Details 1 2 Hands On Lab 4 3 axis MEMS Gyro communications 3214 Peripherals Details 2 2 Hands On Lab 5 Autonomous peripherals ADC TIM DMA app systems Check e Everyone should have ALaptop running Windows OS XP Vista Win7 Win8 or Win10 USB Cable e USB Flash Drive STM32L476G DISCO Discovery kit The following software tools installed STM382CubeMX v4 10 0 CubeL4 HAL Library v1 0 0 e ST LINK Utility v3 7 0 AR Embedded Workbench for ARM v7 40 5 9739 e Teraterm or equiv terminal emulator Ly life augmented STM32L4 Family amp Tools overview 11 life augmented Broadest 32 bit MCU product portfolio DMIPS Ultra low power Mainstream High Performance EE NN EE NN 375 EK NN E NN EN NN
11. 640 5 cycles Note The sampling time value depends on the type of channel fast or slow the resolution and outout impedance of the external signal source to be converted Ly lite augmented Total Conversion Time e Total conversion Time TSampling TConversion 18 75 us gt 5 33 Msps 16 25 us gt 6 15 Msps al 11 25 us gt 8 89 Msps Oversampler Oversampler performs data pre processing to offload the CPU Handles up to 256 conversions and averages them For Averaging Data rate reduction SNR improvement Basic filtering 12bit data 20 bit register 0 to 8 bit right shift 16 bit register Accumulation ADCx DR data register e Programmable oversampling ratio x2 4 x8 x16 x32 x64 x128 x256 e Programmable data shifting truncating e Right shift O to 8 bits Example Oversampling ratio x2 g g i Sampling Conversion Trigger for EOC Trigger End of conversion for y i oversampling channel oversampling channel ite augmented ADC Analog Watchdogs e ADC Analog Watchdog 1 e 12 bit programmable analog watchdog low and high thresholds e Enabled on one or all converted channels e Interrupt generation on low or high thresholds detection e ADC Analog Watchdog 283 Enabled on some selected channels by programming bits in AWDCHx 18 0 e Re
12. Application development environments support Demonstration firmware sources e Video available on YouTube and st com e Getting started with STM32L476 discovery kit for ultra low power amp performance applications httos www youtube com watch v UkTFORUS29Q Ly lite augmented Cortex M4 Core 11 life augmented Cortex M processors Forget traditional 8 16 32 bit classifications Seamless architecture across all applications Every product optimised for ultra low power and ease of use Cortex MO Cortex M3 Cortex MA 7 8 16 bit applications 16 32 bit applications 32 bit DSC apps Hi Performance apps Binary and tool compatible Cortex M processors binary compatible Ly life augmented QADD QADD16 QADD8 QASX QDADD QDSUB QSAX QSUB QSUB16 QSUB8 SADD16 008 SASX SHADD16 SHADD8 SHASX SHSAX SHSUB16 SHSUB8 SMLABB SMLABT SMLATB SMLATT SMLAD SMLALBB CEID OED OID D LOID HD D CMP LDMIA LDRBT LDREXH LDRSBT O A A SBFX SMULL STMDB STRD SUB BKPT BLX 79 o m lt REV16 iab SEV SXTB SXTH UXTB UXTH WFE WFI YIELD STREX 5 ADC CAND CSR C8 LDRH LDRSB LDRSH LSL LSR MOV o U o o 8 2 AR A m lt lt V z STM z STRH o lt TST 0 1 STREXB STREXH SXTH TBB LDC LORD
13. CooCox Microcoantraller Tools Free IDE EEGGERH Embedded Studio Conse TASKING KEELABS y life augmented STM32Cube Supporting all STM32 MCUs e Generate your configuration code with the STM32Cube and you can focus on your added value software Ly life augmented 4 configuration wizards pinout clock peripherals amp middleware power consumption Portable Hardware Abstraction layer from series to others e Middleware with RTOS USB TCP IP File System Graphics Touch sensing Open source TCP IP stack e USB Host and Device library from ST SlemWin graphical stack library from ST and SEGGER e Open source FAT file system FatFs STM32Cube e Open source real time OS FreeRTOS Middleware V e Dozens of examples e Abstraction of STM32 MCU through portable APIs STM32Cube e High coverage for most STM32 peripherals weet Production ready using CodeSonar static analysis tool e Hundreds of examples e Open source BSD license WWW St com stm32cube Comprehensive choice of STM32 free IDEs PCG gt tools Microcontroller Tools system 01011915 MDK ARM Microsoft ES Microsoft ES Microsoft ES Microsoft COMING COMING licenses for access to licenses i STM32 STM32F0 all STM32Nucleo amp STM32L0 users life aug
14. SMMUL SMMULR CM3 n a n a n a n a n a n a n a n a 5 7 5 7 n a n a n a e e FPP RP PP PP PP e e 111 Cortex M4 DSP instructions com Ly augmented CLASS Arithmetic Multiplication Division INSTRUCTION ALU operation not PC ALU operation to PC CEZ QADD QDADD QSUB QDSUB QADD8 QADD16 QSUB8 QSUB16 QDADD QDSUB QASX QSAX SASX SSAX SHASX SHSAX UHASX UHSAX SADD8 SADD16 SSUB8 SSUB16 SHADD8 SHADD16 5 5088 SHSUB16 UQADD8 UQADD16 UQSUB8 UQSUB16 UHADD8 UHADD16 UHSUB8 UHSUB16 UADD8 UADD16 USUB8 USUB16 UQASX UQSAX USAX UASX UXTAB UXTAB16 UXTAH USAD8 USADAS8 MUL MLA MULS MLAS SMULL UMULL SMLAL UMLAL SMULBB SMULBT SMULTB SMULTT SMLABB SMLBT SMLATB SMLATT SMULWB SMULWT SMLAWB SMLAWT SMLALBB SMLALBT SMLALTB SMLALTT SMLAD SMLADX SMLALD SMLALDX SMLSD SMLSDX SMLSLD SMLSLD SMMLA SMMLAR SMMLS SMMLSR SMMUL SMMULR SMUAD SMUADX SMUSD SMUSDX UMAAL SDIV UDIV Cycle counts CORTEX M3 Cortex M4 1 3 1 n a n a n a n a n a n a n a n a n a n a n a U e e NNN n a n a n a n a n a n a n a n a n a n a n a 2 12 H HB H H HB H H H i H P H PB H H H H H I H HB U 2 12 pared Single cycle MAC FPU arithmetic instructions Absolute value of float VABS F32 1 float VNEG F32 1 9 and multiply float VNMUL F32 1 Additio
15. end of conversion DMA interrupt break 2 analog watchdog control clock control 3 short circuit detection 4 averrun Block diagram Decode Filter Average Process Up to 8 Serial transceivers Receive and decode raw serial bitstreams providing data clock to filter stage e 1 wire Manchester coded mode or SPI clock data oinc filter performs input stream digital filtering e Sinc Sinc Sinc Sinc gt FastSinc No filter e Programmable Sinc oversampling ratio 1 to 1024 filter samples e Output filter resolution is 31 bit max Integrator stage performs data averaging from digital filter 1 256 samples Post processing e Offset compensation Programmable right bit shifting for data formatting Additional functions Min Max extremes detection e Analog watchdog to watch for final data boundaries overflow Break signal generation Ly life augmented MEMS microphone support PDM e Function e MEMS microphone provides pulse density modulated data signal like the XA modulator e microphone has stereo support if two connected in parallel e Rising clock Left audio data Falling clock Right audio data e Implementation into DFSDM transceivers Channels data left vs right are separated inside Each DFSDM channel transceiver inputs can be redirected to next channel inputs e Configuration of those 2 channels differs only in active sampling edge e Cloc
16. 1 i cade Sere decus 74 A 1 I 2 I to eee 1 7171 2 7 1 1 1 1 1 11 S W trigger EXTIO 3 P EXTH Analog Watchdog H W trigger High Threshold register 12bits EXTI15 XTSEL 3 0 bits J S W Low Threshold register JEXTIO trigger 12bits 2 0 e AE JEXTI15 lt JEXTSEL 3 0 bits ADC interrupt to NVIC TIMERs Ly life augmented ADC Clocks ADC1 ADC2 amp ADC3 HCLK AHB interface Analog ADC1 master ADC123 CK Analog ADC2 612115 0 11 Analog ADC3 single life augmented ADC Sequencer e Up to 16 regular and 4 injected conversions with programmable order and programmable sampling time Example Conversion of channels 0 2 8 4 7 3 and 11 Different sampling time MEM Ly life augmented ADC Sampling Time Tgampiing Three bits programmable sampling time channel by channel programmable 2 5 cycles 6 5 cycles 2 5 cycles 12 5 cycles 24 5 cycles e 47 5 cycles 92 5 cycles e 247 5 cycles 47 5 cycles 640 5 cycles 92 5 cycles 6 5 cycles 12 5 cycles 24 5 cycles 0 et 5 92 3 722 3 247 5 cycles
17. 10 0401 5 4 2 _ X5R_ 10 0603 12 AIN2B 27 3 ame AIN3B C58 7252 luF POL 10 Pu C59 C67 34 amu 252 luF X5R 10 0603 l UnF 1096 0402 PES C53 C54 2 19 150 NPO 5 0603 100nF X7E 1096 0402 38 ene MET C55 CAS fe Fumi 150 NPO 554 0603 100nF 10 0402 35 C62 C40 aui m REC TIT luF 10 0503 0 10 0402 EE n 5431 22 I2C address 0 54 Smart peripherals Fitness tracker application STM32L4 Sensors T a 3 nN PS All known I C limitations are corrected e Flag management improvements LO F3 like for easy use e Programmable filter on input pins analog amp digital filters Wake up on address matches STOP1 1201 2 3 STOP2 12C3 Fast mode Plus up to 1Mbits s 20mA Dual clock domain allows high baudrates and low CPU clocks to save power Ly life augmented Smart peripherals USART LPUART Fitness tracker application STM32L4 LPUART e Dual clock domain UART functionality and wake up from Stop mode Stop 1 and Stop 2 e Baudrate programming independent of PCLK e Four clock sources LSE 32 768KHz HSI PCLK System Clock e Supports up to 9600 baud 32 768KHz LSE e wakeup from STOP mode clock source must be LSE or HSI e 3 Wakeup events Address match START bit detection or RXNE receive buffer not empty
18. 250 us wake up Available Peripheral l Os be configured STM32 4 Power Mode w or w o pull up deri ane from Shutdown S h U td OWN e 64 nA 3 0V 30 nA 1 8V 1 Wake up Bol RTC Tamper Available Clock LSE Low power modes summary Peripherals Consumption Wakeup All 131 2 Yes ON ON Any All exce N A ot us OTG SDMMC RNG All except 1 H1 2 37 2 7 No ON Any IT or event 6 cycles 35 An All except LPR No OTG SDMMC RNG 40 6 cycles except PLL Any IT or event Reset pin all I Os BOR PVD PVM RTC LCD IWDG LPR No OFF ON LSE LSI COMPx DACx OPAMPx USARTx Al LPUART I2Cx LPTIMx OTG FS Pr n SWPMI Reset pin all I Os LPR No OFF ON LSE LS BOR PVD PVM RTC LCD IWDG Pp COMPx LPUART I2C3 LPTIM1 mg H LPR SRAM2 ON P 235 nA eset 5 pins OFF DOWN DOWN ESE ES BOR RTC IWDG 128 nA w o 14 US 433 nA Reset pin 5 WKUPx pins 30 nA w o RTC Shutdown OFF DOWN OFF DOWN LSE 256 us 1 Can be put in power down and clock can be gated off Ly 2 SRAM1 and SRAM2 can be gated off independently life augmented 5 8 3 3 Low power modes transitions LPSleep Shutdown Hands On Lab 3 Power Consumption Calculator 11 life augmented Power Consumption C
19. 49 152MHZ CK PLL SAI2 SAL CK 1 2 VCO 344MHz CK SAI3 N 43 EE PAD CK PLL ADC2 CK PLL USB1 6 CK PLL USB2 CK 48M MSI USB SDIO RNG CK PLL SA3 dee 11 2896 2 HSE 5 VCO 160MHz CK PLL USB2 CK PLL 192MHz 48 2 256MHz 288MHz CK PLL 80MHz ui bn desit PLL_System 48MHz CK PLL ADC2 ADC CK e64MHz SYS CK 72MHz ADC e iid PLLP from 2 to 31 in derivatives Clocks LSE Low Speed External e LSE programmable amplifier driving capability 4 modes Mode Crystal max Consumption Ultra low power 50kOhm 6pF 200 nA Medium low driving 80kOhm 6pF 260 nA Medium high driving 50kOhm 12 5pF 410 nA High driving 80kOhm 12 5pF 540 nA Available in all low power modes VBAT ugmented Clocks LSI Low Speed Internal e LSI 32kHz STM32Li5x STM32L4x Accuracy over parts 26 56KHz 8 Accuracy over temperature 10 4 o 0 85 C 2 40 125 C Consumption typ 400nA 110nA Available in all low power modes except Shutdown and VBAT Ly life augmented Power schemes 1 3 2 OPAMP USB transceivers VDDUSB mean 2 COMP 3 ADC 2 DAC VREF VREF buffer d Eu VLCD LCD Voltage Regulator VDD VDDIO2 Backup domain VBAT VDDIO2 LSE RTC backup registers Voltage Monitor By default independent powers are electrically
20. Clock Configuration e We will run the STM32L4 at 80MHz for this lab e Click on the Clock Configuration tab oet the PLL Source Mux to MSI MSI RC z 4000 KHz e Set the System Clock Mux to PLLCLK e Use PLLM 1 N x40 R 2 AHB Prescaler 1 80MHz e HCLK should equal 80MHz N AHB Prescaler HCLK MHz life augmented Parameter Settings tab 9600Bits s 8 bit word length No parity bit 1 Stop bit Rx amp Tx data 16 clock oversampling No advanced feature settings needed No NVIC or DMA settings used Ly lite augmented USART2 Configuration Click on the Configuration tab and select USART2 USART2 Configuration Parameter Settings Configure the below parameters Basic Parameters Baud Rate Word Length Parity Stop Bits Advanced Parameters Data Direction Over Sampling Single Sample l Advanced Features Auto Baudrate TX Pin Active Level Is Inverted RX Pin Active Level Is Inverted Data Are Inverted TX and RX Pins Are Swapped Overrun Disable DMA Disable on Error MSB Is Sent First 9600 Bits s 8 Bits including Parity None 1 Receive and Transmit 16 Samples Disable Disable Disable Disable Disable Disable Enable Enable Disable NVIC Configuration e Click on the Configuration tab and select NVIC 9 Configuration RN e Priority Group 41 its for pre emption priority 0 bits for subprio Sotb Premptio
21. LDREX LDRB LDREXB LDRH LDRHT LDRSB LDRSHT LDRSH LDRT o d o 2 p o a CEID a 79 2 SDIV SMLAL SSAT o STMIA STR STRBT STRH STRT TBH TEQ TST UBFX UDIV UMLAL UMULL USAT UXTB UXTH USAX USUB16 05088 UXTAB16 UXTAH UXTB16 CORTEX M3 SMLALBT SMLALTT SMLAWB SMLSD SMMLA SMMUL SMULBB SMULTB SMULWB SMUSD SSAX 55088 SXTAB16 SXTB16 8 UHADD16 UHASX UHSUB16 UMAAL UQADD8 UQSAX UQSUBS USADAS SMLALTB SMLALD SMLAWT SMLSLD SMMLS SMUAD SMULBT SMULTT SMULWT SSAT16 SSUB16 SXTAB SXTAH UADD16 UASX UHADDS UHSAX UHSUBS UQADD16 UQASX Cortex M4 VABS VADD VCMP VCMPE VCVT VCVTR VDIV VLDM VLDR VMLA VMLS VMOV VMRS VMSR VMUL VNEG VNMLA VNMLS VNMUL VPOP VPUSH VSQRT VSTM VSTR VSUB Cortex M4F Cortex m Low Power Leadership from ARM ARM Cortex M4 Core Single precision Ease of use Better code efficiency ARM m Faster time to market NH Cortex W E scaling era Low Power Leadership from ARM Easier support for meta language tools MCU DSP Harvard architecture single cycle Barrel shifter Ease of use of C programming Interrupt handling Ultra low power Cortex M4 Cortex M4 processor microarchitecure ARMv7ME Architecture Thumb 2 Technology e DSP and SIMD extensions Single cycle MAC Up to 32 x 32 64 gt 64 e Optional
22. Power and Flexibility FlexPowerControl STM32L4 is based platform optimized reduce power consumption and increase flexibility Down to 30 nA for I O wake up with additional Shutdown mode RTC available for all power modes External level shifter no longer needed from Active down to Vgar Separate Vpp supplies down to 1 08 V 4 nA Vga mode with charging capability Automatic switch to maintain power for RTC and backup registers Down to 360 nA keeping 32 Kbytes of SRAM active in Standby mode Wake up MCU with any peripheral USB capable with 32 kHz crystal Communication 1 oscillator analog circuits timers Dedicated crystal oscillator is no longer needed for USB function I O level kept in low power modes Optimization of system consumption Internal oscillator from 100 kHz to 48 MHz 0 25 int clock accuracy over voltage temperature with LSE Ly e ULP leader and performance booster life augmented Ultra low power modes Best power consumption numbers with full flexibility Wake u VBAT 4 300 Tamper 3 I Os RTC 250 us SHUTDOWN 30 nA 330 nA Wake up sources reset pin 5 I Os RTC 14 us STANDBY 130 430 Wake up sources BOR IWDG STANDBY 32 KB RAM 360 nA 660 nA Wake up sources all I Os PVD STOP 2 full retention 1 1 1 4 LCD COMPs LPUART LPTIM 14 us 4 us
23. Shared SPI Up 40 MHz speed Flash PSRAM controllers Differences FSMC Continuous FMC clock generation for synchronous and asynchronous modes Performance enhancement Removal of PCCard controller on new products Ly life augmented nnovation FMC Bank memory mapping For the FMC the external memory is divided into 4 fixed size banks of 4x64 MB each Ly life augmented e Bank 1 can be used to address NOR Flash OneNAND or PSRAM memory devices e Banks is used to address NAND Flash devices Bank2 amp 3 reserved Supported Memory Type 0x6000 0000 TUE 4x64 MB NOR PSRAM SRAM CRAM OneNAND Ox6FFF FFFF 0x7000 0000 2 7 0x8000 0000 3 Ox8FFF FFFF 256 NAND Flash 0x9000 0000 Bank4 Ox9FFF FFFF Reserved LPTIM Features Summary e Timeout function for wakeup from Stop 1 mode LPTIM1 amp LPTIM2 and stop 2 mode LPTIM1 only 5 8 X LP TIM Features e Up to 5 clock sources to achieve lowest power consumption LSI HSI External clock APB clock LSE e Internal External hardware triggers with digital glitch filter e Rising Falling or Both edges GPIO RTC events COMP1 2 e Up to 2 operation modes e Continuous mode free running mode many counter overruns are possible One Shot mode Counter stops counting when the overrun value is reached e Encoder
24. and complex Cosine transform etc e Matrix functions PID Controller e Support functions copy fill arrays data type conversions etc u Cortex Low Power Leadership from ARM Memory map overview 4GB linear memory space n 0 0000000 No paging banking pm Device region 0xA0000000 System components and debug Off chip peripherals Off chip memory All locations always accessible by the SW 0 60000000 Supports 8 16 32 bit data 0x40000000 0 20000000 Program flash 0 00000000 Peripherals Standard across all Cortex M implementations Ly ite augmented 2 5 3 Core Registers All registers are 32 bit wide e Instructions exist to efficiently support packed 8 16 32 bit data in memory 13 general purpose registers Lo e Registers rO r7 Low registers e Registers r8 r12 High registers e Only special registers urs e Stack Pointer SP r13 e Link Register LR r14 e Program Counter PC r15 e Program Status Register Application Interrupt Execution Register Usage Convention Return value Arguments to a callee scratch registers MOV RO 4 Local BL FUNC variables ADD RO RO 1 Non Scratch registers MOV 4 4 5512 ZUR Ta ARM Architecture Procedure Call Standard AAPCS lite augmented Stack Pointer and Stacks Only in Thread Mode CONTROL reg
25. integration with high memory size small packages Connectivity 1 SD SDIO MMC 3 x SPI 3 x IC 1 MPU 1 x Quad SPI p ackage size down Display ETM 5 x USART 1 x ULP LCD driver 8 x 40 DMA Digital ART Accelerator AES 256 bit TRNG 2 x SAI DFSDM 8 channels Parallel Interface FSMC 8 16 bit TFT LCD SRAM NOR Cortex M4 80 MHz FPU to 4 4 x 3 8 mm Timers 17 timers including 2 16 bit advanced motor control timers 2 ULP timers 7 x 16 bit timers 2 32 bit timers Up to 1 Mbyte Flash Analog with ECC Dual Bank 3 x 16 bit ADC 2 x DAC 2 comparators 128 Kbyte RAM 2 X op amps 1 x temperature sensor Up to 114 I Os Touch sensing controller Integration and safety lite augmented Safety and security Integrated safety and security features in SECURITY Anti tamper detection Memory Protection Unit Read and Write Protection Brown out Reset Clock Security System SRAM parity check Backup byte registers Unique ID Supply monitoring AES 256 Encryption Flash with ECC JTAG fuse Random Number Generator Software IP Protection Dual watchdog Integration and safety life augmented STM32L4 continuity in STM32 portfolio 9 product series 32 product lines STM32L4 benefits from pin to pin compatibility across the family o 11 000 CoreMark High performance
26. mode LPTIM1 only 6 interrupt sources c O Ly Qugmented LP TIM Features Up to configurable waveforms with configurable polarity e PWM waveform One Pulse waveform e Set Once waveform POL 0 LPTIMx _ARR Hands On Lab 5 Autonomous peripherals ADC TIM DMA 11 life augmented 69 Hands On Lab 5 ADC TIM DMA functionality 7 PD15 TIM4CH4 1KHz PWM JUL Rising Edge trigger DMA1CH1 trigger on Conv Complete DMA Destination incrementing DMA Source fixed DMA1CH1 Interrupt trigger after 10 transfers Interrupt Handler Calculate ADC Avg lite augmented Peripherals 1 Disable N3 Disable Disable ING Disable 1 7 Disable INB Disable 1 9 Disable IN10 Disable 1 14 Disable 21 15 Disable Ly life augmented 111 ADC1 GPIO Clock setup Set up ADC GPIO Clocks PA7 1 IN12 Analog Input Single Ended ADC Clock Source SYSCLK 80MHz ADC Clock 212025 ed PLLSATIR i 11 PUSAR _ B SYSCLK 19 Changes from default settings Synchronous clock mode divided by 4 DMA Requests Enabled End of Single conversion Enable Regular Oversampling 4 bit shift Oversampling ratio 16x External Trigger Conversion Edge Rising Edge External Trigger Conversi
27. 2 Firewall FW e The FIREWALL is made to protect parts of code data volatile and non volatile from access from the rest of the code executed outside of the protected area Code segment NVM Code 31 2 1 as Start Address___ Fw CSSA 22 21 8 7 1 31 Lenth FW_CSL Protection Code fetch Su ern Non Volatile Data Segment NVM Data 24 23 31 Start Address MED FW NVDSSA 31 22 21 8 7 1 Lenth _ _ NVDSL Ll code Protection Data NVM data AH AHB APB Volatile Data Volatile Data Segment SRAMI Data Reset event 31 17 16 __ Start Address FW_VDSSA 31 22 21 8 7 1 ___ 3 Segments may be protected E Length LLL FW_VDSL by the Firewall Protection Code fetch if SRAM1 is executable not shared Data 31 1 Ly FPA Pre alarm bit to control the exit point of the protected code VDS SRAM1 protected segment is sharable with non protected code VDE SRAM1 is executable into the protected volatile data segment lite augmented MHz MCO ow RTC LCD Source Mux HSE RTC PLLSAIL TOE 7 APB1 Prescaler cab MHz APB2 Prescaler 80 MHz mex SDMMC1 MHz 54 RNG MHz PLLSATIR PLLSAI1Q 64 12 1 MHz 64 ADC MHz PLLSATIP 18 285714 5 11 Clock Mux SYSCLK
28. 6 segments THT sa til 88 I 28 n29 30 LA PEL 8 push buttons and Joystick 2 5 hece Quad SPI NOR Flash 16 MB 2 Las WU in 55 o NM USB connector AUDIO JA sa BU y STM32L476 Discovery Audio and connector aN 22 2 Fis 1 msc se A Re 111 Ratt st L ur uM 2 81 358 514 4 y RJ R64 4 i 18 LE 13 O 741 TETTE B COM FO RIS x Ste 235111111111111113121111 44 Direct access to all MCU I Os Audio Codec 3 5 connector Y lite augmented 81M32L476 Discovery back side mL ee Flexible board power supply CR2032 battery or USB B AUDIO gt LI life augmented Out of the Box Demos Plug the USB cable into the top Mini B connector of the Discovery Board Use the blue joystick to scroll through the application menu IDD Measurement app e VDD Measurement app Record Playback app Compass app 7 Sound Meter app e Guitar Tuner app e Options The project is in the CubeL4 library Discovery Demonstrations folder C Users xxxx S TM32Cube Repository S
29. 76ZG 512 128 256 128 4451516 STM32L476VC LQFP64 WLCSP72 WLCSP81 LQFP100 UFBGA132 LQFP144 10 10 1 4 mm 4 4 3 8 0 585 mm 4 4 3 8 0 585 mm 14x14x1 4 mm 7 7 0 6 20 20 1 4 Pin count Legend With 128 256 bit AES hardware encryption Without encryption Ly Q Great investment life augmented S TM32L4 ecosystem HARDWARE TOOLS SOFTWARE TOOLS STM32 Nucleo mbed Discovery kit mbed Evaluation board Enabled SIM32CubeMX featuring code generation and power Key feature Full feature consumption calculation prototyping evaluation Flexible prototyping Ly Q Great investment life augmented SIM32 ODE Nucleo and X Nucleo Accelerometer gyroscope Inertial modules magnetometer DATA COLLECT DATA TRANSMIT DATA ACCESS Pressure temperature humidity UV Proximity microphone Bluetooth LE Sub GHz radio Wi Fi GNSS Audio amplifier Touch controller Translate Operation Amplifier DATA CREATE Stepper motor driver DC amp BLDC motor driver Move actuate DATA POWER Energy management amp battery General purpose microcontrollers DATA PROCESS STM32 Nucleo Nucleo Expansion Boards Secure microcontrollers Ly Software life augmented Hands On Session Out of the box demos 11 life augmented TM32L476 Discovery HMI USB ST LINK LCD 9
30. C Voltage scaling 2 modes Encryption AES 256 bit Control 2X ultra low power 16 bit timer 9x 16 bit timer 2x 32 bit timer Touch sensing controller ART Accelerator ARM Cortex M4 CPU 80 MHz Floating point unit FPU Nested vector interrupt controller NVIC Memory protection unit Connectivity MPU ore JTAG SW debug 3x SFI SX PG 2X SAI 5x USART LIN smartcard IrDA modem control 1x ULP UART 1x SDIO Master 1x USB 2 0 FS 1 CAN 1 SWP 1x DFSDM 8 channels True random number generator RNG 14 Jp to 14 channel D Display AHB bus matrix LCD driver 8x40 Analog 2x Op Amps 3x 12 bit ADC SAR 24 channels 5 MSPS 2x ultra low power comparators 2x 12 bit DAC Temperature sensor STM32L4 Bus matrix Cortex M4 with FPU 9 2 5 2 Q C N 1 SRAM2 32 KB 21220004 MER 04 a MEM AHB2 Periph 240200200 Note QuadSPI and SRAM1 1 6 amp D bus interfaces when remapped to 0 0000 0000 only ed FFFF 0xE010 0000 Cortex M4 internal peripherals 0xE000 0000 0 1 FFFF Ox1lFFF C008 0 000 0000 0x1FFF C000 Option Bytes System Memory 1 0000 FMC amp QUADSPI registers 0xA000 0000 0x1000 8000 QUADSPI bank SRAM2 0x1000 0000 0x9000 0000 FMC banks 0x6000 0000 Peripherals 0x4000 0000 Memory type depen
31. E SINE IUE Memory Clock SrcFreq CPU Bus Peripher Add Cu Step Cu Duration 5 aes NULL Part Number STMXNIURB Y e Creation of Parameter Selection consumption Ambient m 5 2 h Vdd Power Supply V 36 v Sequence Chart D S of Capacity 190010 mah 2 4 Self Discharge 0 08 month 2 eSI Nominal Voltage 3 6 V Max Cont Current 230 0 mA 5 2 i 2 iA consum pt on Pulse Current 500 0 mA Ave M P S Y Time ms Battery lifetime Results Total Sequence Time 5 0 ms Average Consumption 2 359 mA Battery Life Estimation 11 months 2 days amp 14 hours Average 10 15 DMIP S Ly life augmented STMS32Cube Firmware Components Evaluation boards Discovery boards Nucleo boards Board Demonstrations Middleware level Applications Networking LwIP TCP IP USB amp Polar SSL Graphics File system RTOS Host amp Device STemWin FATFS FreeRTOS HAL level Examples Hardware Abstraction Layer API Boards Support Packages STM32L471 STM32L475 STM32L476 STM32L486 Fx Lx Family Ly life augmented e 4 Hands On Lab 1 Getting Started with CubeMX LED Blinky in Five Easy Steps Run SIM32CubeMX Load Project Help Ly life augmented step 1 Create New Project
32. GPIO PIN 8 HAL Delay 100 Infinite loop USER CODE BEGIN WHILE while 1 HAL GPIO TogglePin GPIOB GPIO PIN 2 HAL 1 100 HAL GPIO TogglePin GPIOE GPIO PIN 8 1 100 USER CODE END WHILE Ly life augmented step 5 Build the Project e Click F7 or the Make button or use menu Project gt Make Project Tools Window Help Add Files p Add Group 15 Import File List 4 1 per Add Project Connection ibi Edit Configurations to sy R Remove nfig in Create New Project 34 Existing Project GIN Options Alt F C 75 2 e Click the Download and Debug Green Version Control System uL op Arrow button CTRL D Make F Compile Ctrl F Rebuild All logge e Click the Go button F5 Enjoy the flashing LED s Ly lite augmented STM32L4 Overview Architecture Memory Clocks Power 11 life augmented Ly lite augmented 1 321476 block diagram Up to 1 Mbyte Flash memory Up to 128 Kbyte SRAM System Power supply 1 2 V regulator POR PDR PVD BOR Xtal oscillators 32 kHz 4 48 MHz Internal RC oscillators 38 kHz 16 MHz Internal multispeed ULP RC oscillator 100 kHz to 48 MHz Clock control RTC AWU SysTick timer 2 watchdogs independent and window 51 82 109 114 1 08 Cyclic redundancy check CR
33. NN 428 DMIPS EE NN 150 EET NN 50 25 Me 7 3 3m MHz CoreMark 75 93 273 106 177 245 398 608 1000 4 life augmented Broad Range of Development Tools STM32 Discovery Evaluation 3rd parties Nucleo kits boards Flexible Key feature Full feature From full evaluation to prototyping prototyping evaluation open hardware www st com stm32nucleo www st com stm32discovery STM32 Nucleo expansion boards Specialized NI e amp 2 functionality 53 add on Connectivity Sensors www st com x nucleo Ly life augmented SIM32 Nucleo features Flexible board power supply Jmm Through USB or external source 212 94 0 mE ry ou Integrated ST Link V2 1 Mass storage device flash programming Virtual COM port for communications 2 push buttons 2 color LEDs Arduino M extension connectors Easy access for add ons SEE 24 4 One 51 32 MCU flavor with 64 pins Morpho extension headers direct access to all MCU I Os lite augmented Comprehensive choice of IDEs IAR Embedded Workbench IDE File Edit View Project Simulator Tools Window Help static Debug driverlib Debug gt Bbitband Debug gt a Debug Turn on the LED 5 GPIO_PORTE_DATA_R 0x02 La f startup ew x ca 17 Ree eet
34. PMCt device a digital signal processor range designed for energy measurement This device W Precision voltage reference 1 23 V with can be used in medium and high resolution programmable TC STPMS2L only measurement applications where single or double inputs must be monitored at the same time The STPMS2 are mixed signal ICs consisting of an analog and digital section The analog section W internal low drop regulator 3 V typ Applications consists of a programmable gain low noise choppered amplifier two second order Power metering modulator blocks a band gap voltage reference Motor control low drop voltage regulator and DC buffers while Industrial process control the digital section consists of a clock generator Weight scal and output multiplexer Pressure transducers life augmented Smart peripherals Serial Audio Interface Fitness tracker application serial Audio Interface supports a wide set of audio protocols thanks to its flexible architecture STM32L4 e 125 Philips standards Inter IC Sound 12S LSB or MSB justified 125 variant SPDIF Output Sony Philips Digital InterFace PCM Pulse Code Modulation TDM Time Division Multiplexing AC 97 Audio Codec 97 from Intel 6 e Innovation SAI 2x serial audio interfaces SAI Features Two independent audio sub blocks Transmitter and or receiver Master or Slave Synchron
35. SPS 7 LCD Display 8x40 or 4x44 NS with step up converter STM32L4 CAN Bus 2 0B Active 1 3 High temperature from 40 C up to 125 C IURI Kn SPI UART for Security SPIs 4x SPls with the 128 256 bit AES tdt e key encryption hardware accelerator 6x USARTS ISO 7816 LIN 27 N IrDA modem FSMC External memory interface 1 Mbit s SMBus PMBus for static memories supporting I Os SRAM PSRAM NOR and NAND Up to 114 GPIOs Ly e Innovation life augmented Digital Filter for Sigma omart peripherals gt Fitness tracker application N 71 TFT Display STM32L4 e Parallel interface to TFT Up to 40 MHz speed Le Sensors 126 Batch Acquisition 3 USB USB OTG 2 0 SPI UART full speed 3x SPls LPM and BCD Quad SPI OPAMP 6x USARTs 2x with built in PGA 2x serial audio interfaces Low power sample and hold SWP ADC C71 single wire protocol 3x 12 bit ADC 5 MSPS master interface SWPMI life augmented e Innovation DFSDM Introduction e External modulators on market This is external standalone device ADC converter on sigma delta principle Analog input usually differential and digital output Precision 16 bit resolution e Provides digital output as fast 1 bit data stream gt serial interface Up to 20MHz speed of serial data e Wide range o
36. Ss Battery charging detection BCD support USB Detect and identify the port type standard or charging USB OTG 2 0 full speed Attach Detection Protocol ADP support LPM and BCD Determines attachment status in the absence of bus power Suspend resume support e Wakeup from STOP lite cuprerted nnovation Analog Peripherals e 6 e Hail to rail inputs 1mV offset after calibration e Outputs sink source 100UA low power mode e 1MHz GBW normal mode 500kHz low power mode e 0 7V us slew rate normal 0 3V us low power Mode e Comparators e 2 Comparators Window mode Available in low power modes DAC s e 8 12 bit mode Lots of conversion triggers e Programmable output buffer to drive more current e Supply VDDA 1 8 V to 3 6 V e NEW Sample and hold low power mode ADC s e ADC1 ADC2 are tightly coupled ADCS is standalone e Consumption linear vs conversion rate 200 MSPS Dual clock architecture e Up to 5 3Ms s with 12 bit resolution in single mode Single ended or differential inputs e Internal channels Temp sensor VREF VBAT 3 DAC e NEW Hardware Oversampling Ly life augmented omart peripherals STM32L4 OPAMP 2x with built in PGA COMP 2x Low power DAC 2x Low power sample and hold ADC 3x 12 bit ADC 5 MSPS Innovation DAG1 DAC2 block diagram DAC Control Register TSELx 2 0 S
37. TM32Cube_FW_L4 V1 0 0 Projects S TM32L476G Discovery Demonstrations EWARM life augmented IDD VDD Measurement apps mr m Run 24Mhz voltage range 2 PLL off RTC LSE off Flash ART on im Sleep 24Mhz voltage range 2 PLL off RTC LSE off Flash ART on Low Power Run 2Mhz PLL off RTC LSE off Flash ART on The IDD Measure app uses the onboard STM32L151 as non intrusive auto ranging current measurement probe The target L4 will enter a low power state the MFX will measure the current wake the L4 up and report the measurement back over 2 J 44m Ly life augmented Audio demonstrations e RECORD application e Uses MP34DTO1 MEMS microphone LED5 toggling during record 16 bit audio samples 48 kHz stored in N25Q128A13 QuadSPI Flash LEFT key to exit PLAYER application Uses CS43L22 audio DAC and 3 5mm jack output e Audio playback either from internal or QuadSPI Flash after a RECORD Sub menus e FLASH Audio playback of any WAV binary file loaded 0x08020000 e QSPI Audio playback from QuadSPI Flash Options SEL key to pause resume playback e UP DOWN keys to control volume Audio is played back in loops until LEFT key is pressed Ly life augmented Compass and sound meter demonstrations COMPASS application Uses LSM303C eCompass MEMS device X Pat me 3D accelerometer 3D ma
38. USER CODE END 4 e Open a terminal emulator using USART2 settings Virtual COM port xx e Rebuild Program Debug Run On the rising edge of each TIM4 PWM cycle the ADC is triggered The ADC input is oversampled 16 times summed result is shifted right 4 places performing a hardware averaging e transfer moves this result into a data array and the array pointer is incremented 10 data elements are transferred and then the cycle repeats Add the Result to the Live Watch debug window to see updates Ly life augmented SUMMARY 4 Keys of SIM32 L4 series ULP leader and performance booster Innovation Integration and safety STM32 14 Great Investment 2 apps amp social media Find more about STM32 products and solutions ST MCU Finder mobile application ST Forums on microcontrollers n facebook com stm32 youtube com STonlineMedia twitter com ST World Mbed org ARM mbed FARM Connected Community WWW St com stmcufinder STM32 ARM connected communit Ly lite augmented Thank you 51 32 sT_World st com e2e WWW St com stm321l4
39. Up to 128 Kbytes of SRAM Great investment STM32L a complete offering STM32L4 completes the ultra low power family 100 DMIPS 273 CoreMark More erformance More memory and pin counts More packages Performance Flash size bytes STM32 L4 33 DMIPS 26 DMIPS 93 CoreMark 75 CoreMark 019 Ly Great investment lite augmented 720 28 36 32 48 100 132 144 bcr MHz 20 28 36 32 48 63 100 132 144 28 49 64 STM32L4 series ART Accelerator ak USART SPI PC Product Flash Memory 52 2 x e comen USB2 0 THER EM line KB VF Comp Soma OTGFS 00 128 256 bit 16 and 32 bit timers amps elta 5 Msps river SAI audio PLL Interface SWP 1x CAN STM32L471 Access 256 SDIO to 15 1024 256 USB amp to 128 5 Vea Mode LCD 1024 Unique ID STM32L486 SDIO Capacitive Touch USB amp 1024 128 FSMC sensing LCD amp AES Legend Available in Q4 2015 2x 12 bit DAC Temperature senso STM32L475 USB OTG Low voltage 1 71 STM32L476 Cortex M4 DSP FPU 80 MHz oc eo Ly Great investment life augmented STM32L4 portfolio Flash memory RAM size bytes STM32L486RG STM32L486JG STM32L486VG STM32L486QG STM32L486ZG 1M 128K STM32L476RG STM32L476JG STM32L476MG STM32L476VG STM32L476QG STM32L4
40. WTRIGx e e x TIM6 TRGO ol z 5 lt TIM8 TRGO m 3 5 TIM7_TRGO TIM2_TRGO TIM4_TRGO TIM5 TRGO Ext IT 9 DMA Request x NEN VREF VDDA Digital to Analog Converter x DAC OUTx VSSA Ly life augmented Sample amp Hold feature e Maintains DAC output voltage when the MCU is in a low power mode such as STOP1 mode In Sample amp Hold mode the DAC is able to hold its output voltage while all related analog and digital blocks are shut off e Up to 15x power savings in some configurations How it works Sampling phase During this phase the sample amp hold element is charged into the desired voltage e Holding phase During which the DAC s output is tri stated High Z to maintain the Sample amp Hold element s stored electrical charge e Refresh phase Due to leakage coming from several sources a refresh phase is essential to keep the output voltage at the desired value LSB DAC Sample amp Hold life augmented DC Block Diagram VREF VDDA E ADEN ADDIS DMA Request MIS ADCAL d VREFINT VBAT VINP 18 0 SAR ADC 245 3 Q ADC_IN 15 1 VINN 18 0 z Sample 0 VREF and hold i 2 Regular data register 5 16bits c I o 2 1 1 74 r i i 1 AUTDLY I 1 1 2 3 Analog watchdog 1 1
41. ad protection with Erased when RDP changed from Level 1 to Level 0 Software reset and optional Hardware reset when system reset Erased when setting SRAM2ER in SYSCFG SCSR SRAM control and status register Erased with system reset via SRAM2 RST user option bit Ly lite augmented 15 10 2015 Flash organization e Two 512KB User Flash banks Each bank is 256 pages of 2KB Information block system memory boot loader e 1 128 double word OTP for user data Option bytes for user configuration Bank 1 0 0800 0000 0x0800 07FF Page 0 Main memory 0 0807 F800 0x0807 FFFF 2K Page 255 Bank 2 0x0808 0000 0x0808 07FF 2K Page 256 0x080F F800 0x080F FFFF 2K Page 511 Bank 1 Ox1FFF 0000 0x1 FFF 6FFF 28K System Information Ban 0x1FFF 8000 0x1 FFF EFFF 28K block Bank 1 Ox1FFF 7000 Ox1FFF 73FF 1K OTP area Bank 1 Ox1FFF 7800 Ox1FFF 780F 16 Option bytes Ly Bank 2 Ox1FFF F800 Ox1FFF F80F 16 lite augmented Program Erase ECC Error Code Correction 8 bit for 64 bit word Single error correction Double error detection NMI e Programming granularity is 64 bit e Page granularity for erase is 2 Kbytes Parameter 64 bit programming time 82 us Page 2 KB erase time 22 ms One row 82 double word programming time Normal 2 6 ms Fast 1 9 ms One page 2 KB programming time Normal 20 9 ms Fast 15 3 ms One bank 512 KB programming time Nor
42. alculator Lab Click on the Power Consumption Calculator tab in CubeMX Select two AAA Alkaline batteries in series as our power source Battery 5election Select Battery Battery Alkaline LRO3 Capacity 1250 0 mAh Self Discharge 0 3 98 month Nominal Voltage 3 0 V Max Cont Current 400 0 mA Max Pulse Current 0 0 mA In Series 2 In Parallel 1 Ly life augmented Power Consumption Calculator Lab Add a step to our power sequence Click Step Add e Configure a 10ms step 4 0MHz Range2 RUN mode GPIOB GPIOE and USART2 peripherals enabled e Click Add e Resulting step consumption should be 762 8uA Ly ite augmented step Consumption Without Peripherals Peripherals Part 52 8 pA A 0 pA D 52 8 pA Power Consumption Calculator Lab Add three more additional power steps STOP2 mode Battery power source ALL Clocks OFF 100ms duration LPRUN mode FLASH fetch type Battery power source 2 0MHz freq 5ms duration GPIOB GPIOE active Duplicate Step 2 STOP2 mode using the DUPLICATE button Check the result Consumption Profile by Step amp LOWPOWER RUN 2 STOP2 o 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 Time ms Sequence Average Current Results Summary Total Sequence Time 21515 Average Consumption 45 34 pA y Battery Life Estimation 2 years 10 months amp 6 h
43. as wakeup clock from STOP1 STOP2 Can be automatically woken up when exiting Stop modes e Can be used as I2C USART LPUART source upon wakeup Ly lite augmented Ly life augmented HSI vs MSI design spec Accuracy max Consumption typ Startup time typ Normal mode PLL mode Over temperature 6 Over voltage Better than From 100 to 800 kHz 5196 0 25 0 3 after trim From 1 to 8 MHz 2 From 16 to 48 MHz 496 100 kHz 0 5 800 kHz 20A 1 MHz 5uA 8 MHz 20 uA 16 MHz 60 uA 48 MHz 160 uA 100 kHz 10 us 1 25 ms for 48 MHz 2 5 us 5 of final 0 9 us freq 130 Clocks HSE High Speed External e HSE 4 48MHz External source Bypass mode up to 40 MHz External Crystal Ceramic resonator 4 48MHz e Clock Security System CSS e Automatic detection of HSE failure with NMI generation Break input to TIM1 TIM8 TIM15 TIM16 TIM17 e Backup clock can be HSI or MSI PLL s Each with 3 independent outputs PLL input freq 4 16 MHz e PLL input can be MSI HSI or HSE f VCO clock f PLL clock input PLLM x PLLN f PLL P clock PLLP f PLL_Q f VCO clock PLLQ f PLL R f VCO clock PLLR PLLM from 1 to 8 Ly Clocks PLL HSI MSI _ _ HSE 2 11 2896MHZ VCO 192MHz yV3 3 CK 581 N 24 48MHZ CK_PLL_ADC1 CK PLL SAI CK PLL SAI2 SAL CK CK PLL CK SAI2 CK
44. ct Window Help Project gt Settings Alt P MNA rr Pi enerate Repo rl e Project Settings Set the project name Lab1 and the project location Project Settings C STM32L4Seminar Labs Project Location ASTM3 2L4Seminar La bs e Set the IDE Toolchain to EWARM Toolchain Folder Location STM32L4Seminar Labs L4_ Lab1 Toolchain IDE Click OK 2 Generate Report Ctrl R Mcu and Firmware Package P Generate sour m aiii Settings Alt P STM32L476VGTX Firmware Package Name and Version Generate Code Ctrl Shift STM32Cube FW_L4 1 0 0 Click Open Project Code Generation Lx Code is successfully generated under C STM32L4Seminar Labs Lab1 y pomum lite augmented step 4 Toggle The LED he IAR EWARM IDE should now be open aE Expand the file tree and open the main c file 122 Ha E stm3214dxx hal msp c Add the following code inside the while 1 loop Line 85 in main c Add within USER CODE BEGIN WHILE USER CODE END E Output WHILE section this will preserve your code after regeneration HAL GPIO TogglePin GPIOB GPIO PIN 2 HAL Delay 100 HAL GPIO TogglePin GPIOE
45. ding on boot CODE configuration 0x0810 0000 0x0800 0000 0x0010 0000 0x2000 0000 0x0000 0000 0x0000 0000 Ly ite augmented Memory Mapping FLASH up to 1 Mbytes dual bank MODE 0 SYSCFG MEMRMP gt Bank 1 0x0800 0000 gt Bank 2 0x0808 0000 MODE 1 SYSCFG_MEMRMP gt Bank 2 0x0800 0000 gt Bank 1 0x0808 0000 SRAM Up to 128 Kbytes SRAM split in 2 parts SRAM1 96 KBytes 2000 0000 SRAM2 32 KBytes 1000 0000 gt Access through D code and l code Physical remap at 0x0000 0000 selected by MEM_ MODE in SYSCFG_MEMRMP Flash Bank 1 or Bank 2 see FB MODE System flash bootloader FMC bank 1 SRAM1 QUADSPI Boot modes Boot mode selection 1 opposite of nBOOT1 Boot mode option bit User Flash Main Flash memory is selected as boot space 1 1 system system memory is memory selected as boot space 0 1 SRAM1 Embedded SRAM1 is selected as boot space e Flash Bank1 boot Option Bit BFB2 0 Flash Bank2 boot Option Bit BFB2 1 Bootloader supports USART1 2 8 I2C1 2 8 11 2 3 USB DFU CAN Ly life augmented 32KB SRAM2 features Access through D code and l code Code execution max performance without remap HW parity check 4 bit per word Enabled with SRAM2 PE user option bit e NMI Timer Break on parity check error Optional retention in Standby mode e Write protection with 1 Kbyte granularity Re
46. f suppliers ST and others e STM32 interface DFSDM Digital Filter for Sigma Delta Modulators Implements complete post processing from external XA modulators outputs Receiving of data streams from XA modulators in various serial data formats Digital filtering of data stream final 24 bit result Security emergency functions Ly life augmented not in L4 External modulator s Analog signal Ly life augmented Memory buffer data DMA CPU transfer parallel input data register 7 parallel input data register 0 DFSDM 1 0117 DFSDM CKOUT 1 DFSDM CKIN Integrator unit 3 DFSDM DATIN Ej s s Oversampling ratio Integrator unit 0 serial Sincx filter 3 serial transceiver 7 Clock contro Channels multiplexer transceiver 0 Oversampling ratio 1 Clock control Mode control L 8 watchdog filters 8 watchdog comparators short circuit Interrupt detector 0 1 s 0 s counter E threshold 83 Calibration data High threshold correction unit detector 7 filtero threshold contig Analog watchdog 0 5 1 s O s counter threshold Aig resnald DFSDM data 3 Low threshold Data output bus Control unit Extremes dete Configuration Extremes Interrupts and events 1
47. gnetometer IWMI e rotate board 360 on all axis s after scrolling message invitation 5 YL e RUN displays angle in degrees Ji LEFT key to exit vs SOUND meter application e Uses MP34DTO1 audio sensor to measure ambient noise Displays measurement value in dB on LCD screen LEFT key to exit Ly life augmented Guitar tuner demonstration Select guitar string e RIGHT SEL to start recording STR1 STR2 STR3 D STRA STR5 STRO e Output when string needs to be tightened when string needs to be slightly tightened close to correct tune OK when string is correctly tuned when string needs to be slightly loosened close to correct tune when string needs to be loosened low E thickest string closest to the ceiling A D T FH iii e high E thinnest string closest to the floor LEFT key to exit Ly lite augmented Option Select whether to enter STOP2 mode after few seconds of inactivity Display Firmware version bersion e ULP leader and performance booster 5 3 3 References Refer to www st com stm32l4 discovery Ordering information Getting Started Manual User s Manual and Application notes Board Schematics
48. igger Source Disable Clock Source Disable Channeli Disable 2 Disable Channel3 Disable Channel4 PWM Generation CH4 Ly lite augmented Hands On Lab 5 ADC TIM DMA functionality Set up additional GPIO Clocks 7 ADC1 IN12 Analog Input Single Ended ADC Clock SYSCLK 4 20MHz PD15 TIM4CH4 Alt Fn output PWM Generation CH4 ADC1 settings Clock Prescaler Synch 4 12 bit Right aligned No Scan Scan Continuous modes disabled x16 oversampling 4 bit shift continued mode Trigger on TIM4CC4 Rising edge Enable DMA 1 conversion Channel 12 Rank1 2 5 cycle sampling no offset DMA settings DMA1CH1 Circular mode Increment memory address Word data width DMA1CH 1 interrupt enabled preempt priority TIM4 settings Counting UP Prescaler 79 Counter Period 1000 No CKD PWM Mode 1 Pulse 200 Fast Mode enabled Polarity High User Code HAL function calls required C ASTM32L4Seminar Labs lab5 adc tim dma c Ly Internal L4 ADC TIM DMA peripherals lite augmented Lab 5 Autonomous Peripherals Needed code bits C STM32L4Seminar Labs lab5_adc_tim dma c into main c Add code bits between USER CODE BEGIN PV USER CODE END PV Add code bits between USER CODE BEGIN 2 USER CODE END 2 Add code bits between USER CODE BEGIN WHILE USER CODE END WHILE Add code bits between USER CODE BEGIN 4
49. iguration TT ef Parameter Settings f User Constants Settings DMA Settings Click Add button Select ADC1 DMA Request Direction Use Word Data Width for Peripheral and Memory Increment Memory Address Select NVIC Settings tab Make sure DMA1 channel1 global interrupt is Enabled Click OK ADC1 Configuration 2028 DMA1 Channel 1 Peripheral To Memory gt ADCI Configuration Interrupt Table DMA1 channell global interrupt ADC1 and ADC interrupts Enabled Preemption Priority TIM4 setup Set up GPIO PD15 TIM4CH4 Alt Fn output PWM Generation CH4 TIM4 settings for 1KHz 2096 duty cycle PWM output Prescaler 79 7941280 80 2 80 1MHz timer tick Counter Mode UP Counter Period 1000 1MHz 1000 1KHz No Internal Clock Division PWM Mode 1 is Pulse 200 of Parameter Sting Configure the below parameters Fast Mode Enabled CH Polarity High Counter Setti Prescaler PSC 16 bits value 79 User Code HAL function calls required _ Counter Period AutoReload Register 16 bits va 1000 C STM32L4Seminar Labs l ab5 ad c ti m dma c Internal Clock Division CKD No Division Trigger Output TRGO Parameters Clear Input El PWM Generation Channel 4 Mode PWM mode 1 Pulse 16 bits value 200 4 Fast Mode Enable Mode Disable CH Polarity High Tr
50. interface for single dual quad SPI flash memories 2 5 3 5 Innovation QuadSPI Overview e Three operating modes e Indirect All operations are performed through registers classical e Status polling Hardware polling of status registers interrrupt generation e Memory mapped External flash seen as internal for read operations 256MB limit SDR and DDR support DMA Interrupts amp Integrated FIFO for reception transmission and error handling 8 16 and 32 bit data accesses Registers Clock Control Management QSPI Flash BK1_lO0 SO 00 81 BK1 101 5 01 50 ift Register 3 BK1 02 Q2 nWP Q3 nHOLD BK1 nCS Ne QuadSPI Frame format Each of the 5 phases is fully configurable e Enabled or not Length e Number of lanes Example of Read configuration e Instruction on 1 lane Address Alternate amp Data on 4 lanes e 2 dummy cycles Instruction Address Alt eum Data A2316 158 70 M70 Byte1 Byte2 Ly switch from output to input Smart peripherals USB OTG FS 2 0 e USB 2 0 OTG 2 0 compliant e VDDUSB Dedicated 3 3V supply input 6 bidirectional endpoints STM32 L4 e MSI in PLL mode auto trimmed with LSE to reach 48MHz amp 0 25 accuracy HSE not needed eLink power management LPM support New power save state L1 Sleep with fast entry exit compared to traditional L2 state Suspend 50uS vs 10mS
51. isolated and the features powered by them are not available e The power isolation must be removed by SW Peripheral Voltage Monitor for VDDA VDDUSB VDDIO2 Power PVM threshold supply PVM1 VPVM1 1 2 V ugmented Power supply Supervisor BOR complies with all VDD rise fall time no constraint on power supply shape VDD falling edge lRsrTEMPO nReset Vcore Voltage Regulator e Dynamic Voltage Scaling optimizes performance vs power e Vcore Voltage Range 1 1 2V Up to 80 2 e Vcore Voltage Range 2 1 0V Up to 26MHz powered by main regulator MR or low power regulator LPR e MVR for Run and Sleep modes LPR for LP run LP sleep and STOP1 STOP2 modes Regulators OFF in Standby and Shutdown mode e However LPR remains ON to preserve SRAM2 content in Shutdown mode if required gt Run Sleep Range1 2 LPRun LPSleep Stop Main Regulator Low Power Regulator Von monitoring Y VBAT Ly life augmented Dynamic voltage scaling Run mode SYSCLK MHz 127 80MHz 6 L 1360A MHz G26MHz ows V Low power run 2 1 eae Vcore 1 1 Vcore 1 0 Vcore 1 2V ete lite augmented v 4 Hands On Lab 2 printf debugging nmm
52. ister Active stack pointer Processor modes Process Stack Main Stack default THUMB STATE Thread Mode Exception Normal code execution return Debug operations Handler Mode Exception handler execution Exception request LOCKUP STATE Exception request Main Stack Ly lite augmented Exception Model Types and Priorities lt Reset 3 Highest fixed Reset 2 NMI 2 fixed Non Maskable Interrupt Hard Fault 0004 m Seat taal ipa ire 4 10 Reserved N A N A 11 SVCall Programmable settable Supervisor call SVC 12 13 Reserved N A N A 14 PendSV Programmable settable Request for System Level Service 15 SYSTICK Programmable settable System Tick Timer 16 Interrupt 0 Programmable settable External Interrupt 0 settable X 97 1 81 Programmable settable External Interrupt 31 4 priority levels life augmented Interrupt Entry and Return Interrupt handling is micro coded No instruction overhead Entry Stacking Processor state automatically saved to the stack over the bus PC xPSR RO R3 R12 LR What about the other registers e Then ISR ready to start executing as soon as stack PUSH complete Exit Unstacking Processor state is automatically restored from the stack Then interrupted instruction is executed upon completion of stack POP Ly life augmented
53. k signal provided by DFSDM CKOUT microphones are slaves Ly life augmented MEMS microphone application schematic DFSDM peripheral Channel 7 Filter 3 Filter 2 Stereo microphone Filter 1 R DFSDM Channel 3 Filter O L DFSDM_DATIN2 Channel 2 DFSDM_DATIN1 a ain N Channel 1 falling edge sampling data MEMS microphone Left DFSDM_DATINO redirected from next channel Channel 0 rising edge sampling L data MEMS R data microphone DFSDM_CKOUT Right internal clock Ly lite augmented 6 Voice recognition Demonstration e STM82L4 with voice recognition algorithm controls an Android remote device thanks to Bluetooth Low Energy communication ws AA b EN Tm DM Bic Microphone Shield ST BlueNRG BLE RF C R2032 With Digitais MEMS Nucleo 51 3214 Arduino Shield MP34DT01 Ly lite augmented amp Voice recognition function blocks Always Voice Voice acquisition activity trigger detector detection Always on BLE connection augmented Voice recognition example 6 Low power audio DSP replacement Always Voice Voice acquisition activity trigger PDM to PCM amp signal conditioning detector detection Sub microwatt acquisition thanks to PDM to PCM HW processing with DFSDM and low power Batch Acquisition Mode BAM life augmented Hardware Software bloc
54. ks oignal POM ae FUG Conditioning Output Decimation 16kHz Digitals MEMS Decimation by 64 Gain control filtering MP34DT01 2MHz Voice Activity Voice Trigger Detector Detection indicator 16MHz BAM explained Voice recognition use case a a EE E a ee E rd STM32L476 Cortex M4 2 1024 KB Filtering Decimation Gain control done by HW with DFSDM Cortex M4 Flash fetch Algorithm Processing Cortex M4 ana RAM fetch Voice trigger Current Voice detection Voice consumption Detected Ly lite augmented mart perioherals DFSDM L N i 22 Meterin Hee ET iE ts STM32L4 R2 150k R4 150k _ 4H CLK HP Ampi x4 MS2 0 Volga channel ON DAT CLK bsV bsC MSG HardMode BST Moda OFF Electricity Meter ky STPMS2 Smart sensor dual channel 1 bit 4 MHz second order sigma delta modulator with embedded PGLNA Features Voc supply range 3 2V 55 V W Two second order sigma delta modulators Programmable chopper stabilized low noise 2 and low offset amplifier B Supports 50 60 Hz EN 50470 1 EN 50470 3 62053 21 IEC 62053 22 and IEC 62053 23 standards specs for class 1 class 0 5 and QFN16 4 x 4 class 0 2 AC watt meters STPMO2H less than 0 5 error over 1 10000 range or multi phase energy meters along with the STPMO L less than 0 5 error over 1 5000 ST
55. l COM port xx e Rebuild Program Debug Run Ly lite augmented STM32L4 Low Power details 11 life augmented Available Peripheral STM32L4 Power Mode Run mode Run Mode Range 1 Ex execution from Flash Range 1 131uA MHz at 80 MHz 10 2mA Range 2 112uA MHz at 26 MHz 2 9 mA Range 2 up to 26MHZ Available Clock Cell in power down Available Peripheral SIM32L4 Power Mode Low power run mode Low power run mode Ex execution from Flash Main regulator MR from Flash 135 pA MHz at 2 MHz Range 1 up to 80MHZ 269 uA Range 2 up to 26MHZ From SRAM1 112 2 at 2 MHz E ell in ee down Available Clock Available Peripheral STM32L4 Power Mode sleep mode Sleep Mode Range 1 Ex Flash ON SRAMs ON default Range 1 37 2 at 80 MHz 2 96 mA Range 2 up to 26MHZ 285 E Range 2 35 at 26 MHz Available Clock Cell in power down Available Peripheral STM32L4 Power Mode Low power sleep mode Low power sleep mode Ex Flash OFF SRAM1 OFF 23 Main regulator MR Flash ON SRAMs OFF 48 pA MHZz at 2 MHz Range 1 up to 80MHZ 96 uA Range 2 up to 26MHZ Flash OFF SRAMs OFF 40 5 2 at 2 MHz Ea Cell in power down Available Clock Available Peripheral 0 kept and configurable STM32 4 Power Mode stop 1 Mode Stop 1 w RTC on LSE
56. mal 5 35 s Fast 3 9 5 Mass erase time 1 or 2 banks 22 ms Ly Ife augmented Performances STM32L15x STM32L4x CPU CortexM3 CortexM4 FPU Flash I F Prefetch ART Frequency 32MHz 80 7 Performance 35 DMIPS 100 DMIPS no loss DMIPS 129 0 4 8 12162024 28 323640 44 485256 606468 727680 Ly life augmented ART overview e Instruction cache 32 lines of 4x64 bits 1KB e Data cache 8 lines of 4x64 bits 256 Best tradeoff between cache size Power Dhrystone CM performances Koth 4 32 4 75 32 Prefetch buffer 64 2 5 3 5 Flash protections Flexible Protections configurable with option bytes Readout protection RDP e Forbids access to Flash SRAM2 Backup registers by Debug interface JTAG SWD e Boot from SRAM 1 e Bootloader Proprietary Code Protection PCROP with 64 bit granularity Used to protect specific code area from any read or write access The code can only be executed e Write Protection WRP with 2 KByte granularity Used to protect specific code area from unwanted write erase Ly 1i1e augmented Readout Protections e Readout protection Level 0 No read protection All operations are possible in all boot configurations Readout protection Level 1 User mode Code executing in user mode can access main Flash memory option bytes RTC back
57. mented New ST MCU Finder Application Quickly find the right ST MCU e Easy access to technical materials Latest news from ST MCU world www st com stmcufinder 5 8 Birth of the STM32 L4 High performance ARM Cortex M4 FPU DSP Advanced analog New digital peripheral set Ultra low power e STM32L4 is a perfect fit in terms of ultra low power performances memory size and peripherals at a cost effective price Convergence between High performance and Ultra low power series lite augmented e o o Ly ite augmented Key messages of 5 2 L4 series ULP leader and performance booster ST has built a new architecture delivering best in class ultra low power ULP figures thanks to its high flexibility In addition the performance of the STM32L4 far exceeds the competition in the ultra low power world It delivers 100 DMIPS based on its ARM Cortex M4 core with FPU and ST ART Accelerator at 80 MHz Innovation Covering a large range of applications the STM32L4 features many architectural innovations and new smart embedded peripherals Integration and safety 1 MB of Flash and 128 KB of SRAM with safety and security features smart and numerous peripherals advanced and low power analog circuits in packages as small as 3 8 x 4 4 mm Great Investment This new STM32 member benefits from the pin to pin compatibility of the STM32 family and the STM32 Ecosystem Ultra Low
58. n Priority and Sub Prori GPIO v bits for pre emption priority 0 bits for subp d Sub Search Show only enabled interrupts v mmm Interrupt Table Enabled Preemption Priority Sub Priority nuce OL Non maskable interrupt Memory management fault Prefetch fault memory access fault Undefined instruction or illeg Debug monitor System tick timer 1 2 4 interrupts through EXTI lines 16 M Enable EXII lineO RCC global interrupt EXT lined interrupt USART2 global interrupt Set Preemption Priority to 2 e Click OK Enabled Preemption Priority Sub Priority Ly life augmented Regenerate Source Code for Window Help Generate Code Ctrl Shift 7 Generate Report Ctri R 1 Generate sou Open Project t Settings a 1 69 The Code is successfully generated under C STM32L4Seminar Labs Lab1 Open Folder Open Project Copy Paste needed code bits for Hands On Lab 2 into main c e C STM32L4Seminar Labs lab2_printf_debug c Add code bits between USER CODE BEGIN PV USER CODE END PV Add code bits between USER CODE BEGIN 2 USER CODE END 2 Add code bits between USER CODE BEGIN WHILE USER CODE END WHILE e Add code bits between USER CODE BEGIN 4 USER CODE END 4 e Open a terminal emulator using USART2 settings Virtua
59. n floating point VADD F32 1 Subtract float VSUB F32 1 float VMUL F32 1 then accumulate float VMLA F32 3 Multiply then subtract float VMLS F32 3 then accumulate then negate float VNMLA F32 3 the subtract the negate float VNMLS F32 3 then accumulate float VFMA F32 3 Multiply then subtract float VFMS F32 3 fused then accumulate then negate float VFNMA F32 3 then subtract then negate float VFNMS F32 3 Divide float VDIV F32 14 Square root of float VSQRT F32 14 Ly te augmented DSP lib provided for free by ARM e The benefits of software libraries for Cortex M4 Enables end user to develop applications faster Keeps end user abstracted from low level programming Benchmarking vehicle during system development e Clear competitive positioning against incumbent DSP DSC offerings Accelerate third party software development e Keeping it easy to access for end user Minimal entry barrier very easy to access and use One standard library no duplicated efforts ARM channels effort resources with software partner Value add through another level of software eg filter config tools life augmented Low Power Leadership from ARM DSP lib function list snapshot e Basic math vector mathematics e Fast math sin cos etc e Interpolation linear bilinear Complex math e Statistics max min RMS etc e Filtering IIR FIR LMS etc Transforms FFT real
60. on Source TIM4 CapCom 4 life augmented ADC1 Settings ADCI Configuration Configure the below parameters ADCs Common Settings Mode ADC Settings Clock Prescaler Resolution Data Alignment Scan Conversion Mode Continuous Conversion Mode Discontinuous Conversion Mode DMA Continuous Requests End Of Conversion Selection Overrun behaviour Low Power Auto Wait ADC Regular ConversionMode Enable Regular Conversions Enable Regular Oversampling Oversampling Right Shift Oversampling Ratio Regular Oversampling Mode Triggered Regular Oversampling Number Of Conversion External Trigger Conversion Edge External Trigger Conversion Source Rank Channel Sampling Time Offset Number Offset H ADC_Injected_ConversionMode Enable Injected Conversions Parameter Settings 7 User Constants lt 7 NVIC Settings DMA Settings GPIO Settings Independent mode Synchronous clock mode divided by 4 ADC 12 bit resolution Right alignment Disabled Disabled Disabled Enabled End of single conversion Overrun data preserved Disabled Enable Enable 4 bit shift for oversampling Oversampling ratio 16x Oversampling Continued Mode Single trigger for all oversampled conversions 1 Trigger detection on the rising edge Timer 4 Capture Compare 4 event 1 Channel 12 2 5 Cycles No offset Disable ADC1 DMA and interrupt Select DMA Settings tab in ADC1 Configuration 9 ADC Conf
61. ours Average S 4 17 DMIPS lite augmented VBAT backup domain e VBAT charging allows charging super cap on VBAT through internal resistor when VDD 1 present Battery charging is enabled by setting VBE bit in the PWR_CR4 register e VBRS bit value in the register selects the resistor value Backup domain VDD VDD domain Battery charging life augmented STM32L4 Peripheral details 1 2 omart peripherals Metering CT LCD Display 88x40 or 4x44 with step up converter Digital Filter for Sigma Delta Modulators 8 x parallel inputs with up to 24 bit data output resolution Vear With RTC for battery backup n 240 nA in Vgar mode for RTC and 32x 32 bit backup registers STM32L4 lt 18 Anti Tamper pin x tamper pins for battery domain TRNG amp AES for Security lt _ lt 128 256 bit AES key encryption hardware accelerator SPI UART SDIO for Wireless 5 4 SPIs with the Quad SPI 6x USARTs ISO 7816 LIN IrDA modem 1 x SDIO FSMC External memory interface for static memories supporting SRAM PSRAM NOR and NAND Ly e Innovation lite augmented Electricity Gas Water Smart Meter I Os Up to 114 fast I Os for buttons amp relays Motor Control Smart Peripherals 2x 16 bit advanced motor control timers Industrial Sensors 3x 12 bit ADCs 5 MSPS with up to 16 bit with hardware oversampling 200 uA M
62. ous or asynchronous modes between the audio sub blocks e Clock generator for each audio sub block to target independent audio frequencies 8 word integrated FIFOs for each sub block up to 16 slots available e Mute mode Stereo Mono and companding mode supporting u Law and A Law Configurable LSB MSB data slot sizes sampling edges of bits frame shape etc STM32L476 486 APB Interface SAMEXTCLK 7 1 Gen gt Sub Block A Cik Gen Sub BlockB mi APB Interface SYNC SD1_A CH T p N IOL Ine Management APB Interface 1 Clk Gen Sub Block i p SAIZEXTCLK 7 Clk Gen E Sub Block B 4 T SD2 B a MCLK2_B 1 y J APB Interface lite augmented o UJ Discovery oard Im omart peripherals lementation STM32L4 SAI 125 Philips mode Ly life augmented PRO FES PE PES PES PE4 R70 51 1 amp 0402 5 15 0402 C85 YaF 7 10 0603 nF X7R 10 0503 1713 2 CN6 io perse T IPIE CIS 1 5 R70 107 ICE um mie 0 5 0402 51 225 02 5217 SPER OUTA X 4 SD 39 S 5 50 SPER OUTA FS 40 bei li TAY a AUDIO RST 32 SPER ANAE J AUDIO RSI SPER OUTB p 10 1 0402 10 Ma C54 58 H lODuF XTR 10 0402 luF 10 0503 30 Cel L2 100 X7H
63. quartz 6 9 uA 1 8V Co c Wake up event Available Clock 6us wake from Flash 4us wake from Available Peripheral 0 kept and configurable STM32 4 Power Mode Stop 2 Mode 1 67 3 0V 1 43 WA 1 8V Wake up event Stop 2 w RTC on LSE quartz Main regulator MR D Available Clock MSI 5 wake up from Flash 5us wake up from RAM Available Peripheral vos canbe conigured T M32L4 Power Mode Standby Mode standby a05nA 3 0V WISRAM2 405 nA 3 0 w o RTC 3 Ea Available Clock Wake up event RTC Tamper 14 us wake up Available Peripheral www 1 3214 Power Mode Standby Mode Standby w RTC 650 nA 3 0V on LSE quartz 433 NA 1 8V Wake up event Available Clock Ea 14 us wake up Available Peripheral vos conigured 3214 Power Mode w or w o pull down Standby Mode _ 150 nA 3 0V 114 nA 1 8V Wake up event ca Available Clock RTC Tamper R 14 us wake up Available Peripheral vos canbe conigured T M32L4 Power Mode w or w o pull down But floating when exit from Shutdown S h U td OW Shutdown w RTC 550 nA 3 0V on LSE quartz 329 nA 1 8V lt gt 22 Cerc Available Clock zz
64. s Motorola 225 Data Size 8 Bits wee spn First Bit MSB First SPI Clock Parameters Pubs Prescaler for Baud Rate 16 Full Duplex Master U in 5 0 MBit 2 Se de Re S o Baud Rate 5 0 MBits s is Hardware NSS Signal x x Clock Polarity CPOL Low Clock Phase 1 Edge El Advanced Parameters CRC Calculation Disabled NSSP Mode Enabled NSS Signal Type Software Signal on Pin User Label SPE SCK SPD MISO PD4 MOSI Alternate Function Push Pull pull up and no pull do Maximum output speed Fast Mode Needed code bits from C STM32L4Seminar Labs lab4_spi_gyro c into main c Add code bits between USER CODE BEGIN PV USER CODE END PV Add code bits between USER CODE BEGIN PFP USER CODE END PFP Add code bits between USER CODE BEGIN 2 USER CODE END 2 Add code bits between USER CODE BEGIN WHILE USER CODE END WHILE Add code bits between USER CODE BEGIN 4 USER CODE END 4 e Open a terminal emulator using USART2 settings Virtual COM port xx Ly e Rebuild Program Debug Run life augmented cti 4 STM32L4 Peripherals details 2 2 Smart peripherals QuadSPl alim STM32L4 Micron Serial NOR Flash Memory Multiple 4KB Sector i A E QuadSPI e Communication
65. single precision e Integrated configurable NVIC e Compatible with Cortex M3 Microarchitecture 93 stage pipeline with branch speculation 3x AHB Lite Bus Interfaces e Configurable for ultra low power Deep Sleep Mode Wakeup Interrupt Controller Power down features for Floating Point Unit Flexible configurations for wider applicability e Configurable Interrupt Controller 1 240 Interrupts and Priorities e Optional Memory Protection Unit e Optional Debug amp Trace Ly life augmented ul B Cortex Low Power Leadership from ARM All the above operations are single cycle on the Cortex M4 processor lite Cortex M4 extended single cycle MAC 16 16 16 16 16 32 16 x 32 16 x 16 16 16 16 x 16 16 x 16 32 x 32 32 32 32 x 32 32 x 32 32 x 32 32 32 32 x 32 Ly augmented OPERATION 32 32 32 64 64 32 32 32 16 x 16 32 32 32 64 64 16 x 16 16 x 16 EE t 32 x 32 32 64 64 64 32 32 64 x 32 32 upper 32 upper INSTRUCTIONS SMULBB SMULBT SMULTB SMULTT SMLABB SMLABT SMLATB SMLATT SMLALBB SMLALBT SMLALTB SMLALTT SMULWB SMULWT SMLAWB SMLAWT SMUAD SMUADX SMUSD SMUSDX SMLAD SMLADX SMLSD SMLSDX SMLALD SMLALDX SMLSLD SMLSLDX MUL MLA MLS SMULL UMULL SMLAL UMLAL UMAAL SMMLA SMMLAR SMMLS SMMLSR
66. solution Limited to 8 bits and only the 8 MSBs of the thresholds can be programmed ADC INO ADC IN1 Status Register Low Threshold High Threshold ADC_IN1 Ly life augmented COMPx INPSEL COMPx INP ros 1 COMPx IMM I Os a DAC CH1 DAC CH2 VREFINT 3 4 1 2 VREFINT 1 4 Ly lite augmented COMPx _ INMSEL COMPx INP COMPx INIM COMPARATORS alternate function COMPx POL COMPx OUT COMPx VALUE Wakeup EXTI line nterrupt e Polarity selection TIMERS 2 ultra low power comparators COMP1 COMP2 Wake up from low power modes thru EXTI Sleep STOP1 STOP2 Multiplexed inputs GPIO DAC s VREFINT Programmable hysteresis and speed vs consumption Redirection of output to IO or timer inputs e g TIM Break event Outputs with blanking source Comparators can be combined in the window comparator COMP low power features Power consumption vs propagation delay can be adjusted PWRMODE propagation delay Consumption Typ 00 80 ns 70 uA 01 or 10 1 us 5 uA 11 12 us 350 nA Feature limitation Run LPRun no limitation state polling or interrupt thru Sleep LPSleep wakeup capability thru EXT stop 1 Stop 2 wakeup capability thru EXT Standby not available shutdown not available life augmented omart peripherals NOR Signals lt TFT Display i STM32L4 Parallel interface to TFT
67. th e An STM32 Abstraction Layer embedded software STM32Cube HAL Aconsistent set of Middleware RTOS USB TCP IP Graphics STM32CubeMX STM32CubeLO STM3 F4 gen bas eration STM32CubeF4 o 2 o A o lt STM32CubeF2 4 p SIMS2CubeFO amp Ory em g 99 v in STM32CubeF 1 ple y all Series Middleware stacks when applic life augmented 55 58 al 3 dgg 8 88844 Basic Parameters Word Length 8 Bits including Parity KB OTi F5 USD Parity None Ka E STM32CubeMX som Advanced Parameters som po Data Direction Receive and Transmit ATC REP Over Sampling 16 Samples BaudRate must be between 110 Bits s and 10 5 MBits s Peripherals amp Middleware Wizard wi n 849 Pinout Wizard Power Consumption Wizard Clock Tree wizard Tm EYSCLK DT 15 Consumption mA 0 00 0 25 0 509 0 75 100 1 25 1 20 1 75 2 00 Time ms 5 MainPLL Sequence Average Current Input trequenzy 4 2BM Hz Ly life augmented Power consumption calculator e Power step definitions GOS 9 Microcontroller Selection Family STM32L1 Batt lect selection cine M
68. up registers and SRAM2 with all operations Debug boot RAM and boot loader modes The main Flash memory backup registers and SHANM2 are totally inaccessible in these modes a simple read access generates bus error and a Hard Fault interrupt Un protection Level 1 to Level 0 Flash memory is mass erased RTC backup registers and SRAMe are cleared If Option bit PCROP_RDP is set the PCROP protected area is not erased e Readout protection Level 2 No debug Ly ite augmented All protections provided by Level 1 are active RAM boot System memory boot and all debug features are disabled Option bytes can no longer be changed in user mode Un protection is not possible It is an irreversible operation Proprietary Code PCROP Write Protections e When enabled PCROP area is protected against all D code bus accesses e The PCROP regions are execute only e 1 area per bank 64 bit granularity e PCROP area can be increased but never decreased e Only way to deactivate PCROP is to change RDP from Level 1 to Level 0 Option bit RDP e When DISABLED PCROP content is erased when RDP is changed from Level 1 to Level 0 PCROP RDP is locked in this state e When ENABLED PCROP content is preserved when RDP is changed from Level 1 to Level 0 e Flash Write Protection e Write protected area is protected against erasing and programming 2 areas per bank 2 KByte granularity Ly life augmented STM3

STM32L4 Seminars Fall 2015 - Rev13

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