R-IN32M3 Series User`s Manual
Contents
1. 1 Normal mode 2 Outside clock input mode Low level High level OSCTH OSCTH R IN32M3 R IN32M3 XT1 XT2 XT1 XT2 Rx Rd LT 0 R to Low level j Resona In some cases to use resonator user don t need Rd Outside clock input mode In some cases user don t need Rx an element set XT1 to low level suppresses vibration signal of resonator Figure 3 2 Configuration example of the oscillation circuit Caution R IN32M3 s input is fixed 25MHz Load of resonator should be 8pF or lower But it depends on the resonator and the design situation Please consult the design information given by the resonator manufacturer R18UZ0021EJ0204 TENESAS Page 7 of 51 Dec 25 2014 R IN32M3 Series 4 PLL power pins The PLL circuit is susceptible to noise 4 PLL power pins To reduce the influence of noise it is recommended to place filters in the power supply pin of the PLL Also if user avoid the interference noise of the PLL board and power supply the usage of user user ferrite beads FB 4 1 Recommended FILTER composition Figure 4 1 shows recommended FILTER composition GND C1 C2 FB 0 1 u F ceramic capacitor gt 4 7 UF capacitor Impedance 600 100MHz DC resistance ingredient 0 3 and under Reference FB TDK MPZ2012S601A MPZ1608S601A Figure 4 1 Recommended FILTER composition Caution Put C2. Analog power supply for built in regulator 3 3V AGND REG Analog GND potential for built in regulator GND Byppe Power supply for built in regulator 3 3V BGNDNE GND potential for built in regulator GND Feedback input for built in regulator Refer to 5 1 Built in regulator used Reference resistance joining pin for Ethernet PHY Connect AGND through 12 4k 196 POVDDARXTXN9e Analog power supply for Rx Tx pin 1 5V Port 0 Analog power supply P1VDDARXTX for pin 1 5V Port 1 VDDACBN2 Analog power suppuly for Ethernet PHY 3 3V AGND Analog GND potential for PHY 3 3V VDD15N99 Core voltage for Ethernet PHY 1 5V VDDAPLL Analog power supply for Ethernet PHY 1 5V VSSAPLLCBN e Analog GND potential for Ethernet PHY GND VDD33ESD Analog test power supply for Ethernet PHY 3 3V VDDQ Bo PECL buffer power supply 3 3V VDDQ PECL buffer power supply 3 3V Refer to 7 1 Ethernet PHY power supply pin Note1 R IN32M3 EC only 2 R IN32M3 CL only R18UZ0021EJ0204 Dec 25 2014 TENESAS Page 3 of 51 R IN32M3 Series 2 Power Reset pins 2 3 Reset pins Terminal name Feature Connection example RESETZ Reset input HOTRESETZ Hot reset input PONRZ Power on reset input for bui
3. R IN32M3 External MPU Notes HA2 HA20 HDO HD31 HCSZ Notes HPGCS HRD Z 2 WRZO BENZO Waza BENZ1 WRZ2 BENZ2 HWRZS HBENZ3 WRZ3 BENZ3 HWAITZ WAITZ Note3 HERROUTZ gt Interrupt port pin HBUSCLK Low level Figure 11 1 The connection example with external MPU 32bit bus asynchronous SRAM interface mode R18UZ0021EJ0204 TENESAS Page 26 of 51 Dec 25 2014 R IN32M3 Series 11 External MPU memory interface pins R IN32M3 External MPU Note6 HA1 HA20 S WRZO WRZ1 BENZ1 WAITZ BENZO Notes HERROUTZ Interrupt port pin HBUSCLK Low level Figure 11 2 The connection example with external MPU 16bit bus asynchronous SRAM interface mode Note1 The detail of signal connection is depend on the bus interface spec of the host MPU Please confirm the product spec of MPU which is connected to this LSI Note2 HWRZO HWRZ3 and HBENZO HBENZ3 is assigned to the same pin The function is decided by the signal level of HWRZSEL pin Note3 The connection of the HERROUTZ signal is not indispensable Please connect this signal to a interrupt or general port pin etc according to the need Note4 PGCSZ signal is a chip select signal which can do page access Please connect this signal according to the need Note5 HA2 pin should be connected to the signal which is as the 4 byte boundary address of the external MPU Note6 HA1 pin
4. 14 A 13 12 P OOOOOOOOOOOOOOOO00 t LIEB 000000000000000000 10 9 8 7 000000000000000000 OOOOOOOOOOOOOOOOOO 5 OOOOOOOOOOOOOOOOOO 4 000000000000000000 2 Y OOOOOOOOOOOOOOOOOO 1 VUTRPNMLKJHGFEDCBA INDEX MARK UNIT mm ITEM DIMENSIONS D 19 00 0 10 S E 19 00 0 10 1 030 1 00 1 83 0 12 Al 0 50 0 10 A2 1 33 d 0 60 0 10 0 10 0 15 yl 0 35 ZE 1 00 ZE 1 00 P324F1 100 HN4 1 Figure 19 1 Package informations R18UZ0021EJ0204 ESAS Page 45 of 51 Dec 25 2014 R IN32M3 Series 20 Mount pad informations 20 Mount pad informations Figure 20 1 shows mout pad informations 0 507 0 70mm 0 45 0 55mm O lt gt en 1 00mm 0 45 0 55mm Figure 20 1 Mount pad sizes R18UZ0021EJ0204 TENESAS Page 46 of 51 Dec 25 2014 R IN32M3 Series 21 BSCAN information 21 BSCAN information R IN32M3 are available with BSDL file Caution If an opposite device connects to a input pin which doesn t have pull up pull down clamp the devi
5. devices compliant with the SRAM interface can also be connected Asynchronous SRAM MEMC is carrying out the pin combination of the synchronous method burst access MEMC and the external microcomputer interface and when both a MEMCSEL pin and a MEMIFSEL pin are low levels it can use them as asynchronous SRAM MEMC 11 2 1 1 SRAM connection example An example of connection with SRAM is shown as follows R IN32M3 SRAM 256Kwordx16bit RDZ WRZ3 BENZ3 WRZ2 BENZ2 WRSTBZ SRAM 256Kwordx16bit WRZ1 BENZ1 WRZO BENZO n 0 3 Figure 11 7 Example of Connection with SRAM 32bit bus asynchronous SRAM MEMC R IN32M3 A1 A18 A0 A17 D0 D15 01 1 016 SRAM 256Kwordx1 6bit CSZn RDZ WRZ1 BENZ1 WRZO BENZO WRSTBZ 82 n 0 3 Figure 11 8 Example of Connection with SRAM 16bit bus asynchronous SRAM MEMC R18UZ0021EJ0204 TENESAS Page 32 of 51 Dec 25 2014 R IN32M3 Series 11 External MPU memory interface pins 11 2 1 2 Page ROM Connection Example An example of connection with page ROM is shown as follows R IN32M3 Page ROM 1Mwordx16bit Page ROM 1Mwordx 16bit R IN32M3 Page ROM 1Mwordx16bit Figure 11 10 Example of Connection with Page ROM 16bit bus asynchronous SRAM MEMC Caution The on page mode of page ROM is available only when the ROM is connected to
6. 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the cor
7. CCS MON1 P32 CCS 06 CCS RESOUT PO7 CCS FUSEZ P36 INTPxZ P00 CCS REFSTB P10 Figure 9 1 The connection example for CC Link Remote device station lt R gt Note1 CCS REFSTB P10 pin is needed to connect to the port pin which has external interrupt function INTPZ Note2 RZEN pin should be connected to a general output port R18UZ0021EJ0204 Dec 25 2014 TENESAS Page 23 of 51 R IN32M3 Series 10 Notes of CC Link IE Field use only R IN32M3 CL 10 Notes of CC Link IE Field use only R IN32M3 CL When user does boot with the external memory boot mode external serial flash ROM boot mode and instruction RAM boot mode please input high level to P33 and P34 pin during reset If you enter a low level to P33 P34 pin during reset you can not access the CC Link IE Field from the CPU of the R IN32M3 R18UZ0021EJ0204 RENESAS Page 24 of 51 Dec 25 2014 R IN32M3 Series 11 External MPU memory interface pins 11 External MPU memory interface pins This LSI is able to connect to an external MPU or memory The connection mode is decided as Table 11 1 by the signal level of the MEMIFSEL pin MEMCSEL pin and HIFSYNC pin Table 11 1 The mode selecton of external MPU memory connection MEMIFSEL MEMCSEL HIFSYNC Asynchronous SRAM MEMC High External memory interface Synchronous SRAM MEMC High Low Low External MPU interface Asynchronous SRAM interface High External MPU interface
8. Synchronous SRAM interface High Low Prohibition of a setup High External MPU interface Synchronous SRAM type transmission mode From the next section the connection example for each modes is shown R18UZ0021EJ0204 TENESAS Page 25 of 51 Dec 25 2014 R IN32M3 Series 11 External MPU memory interface pins 11 1 External MPU interface In order to use the internal resource of external host MPU to R IN32M3 the external microcomputer interface is established External MPU I F is interface to connect external MPU External MPU I F s signal is assigned same ports to both use with an external memory interface and can be used as External MPU interface in case of setting MEMIFSEL to High level The external microcomputer interface is equivalent to the asynchronous SRAM interface and the synchronous SRAM interface When the level of a HIFSYNC pin is high level it becomes a synchronous SRAM interface and when HIFSYNC is a low level it becomes an asynchronous SRAM interface Please refer the Table 11 1 Moreover an external microcomputer interface supports the synchronous SRAM type transmission of a clock synchronizer type so that mass data can be accessed at high speed MEMIFSEL pin and MEMCSEL pin can be used by making it high level 11 1 1 Asynchronous SRAM interface The following figure shows a general connection example with the asynchronous SRAM interface mode when the external MPU connects as the host
9. and thick as possible in PCB wiring If wires are long effects of Xtalk can easily occur because the LC portion of wiring increase R18UZ0021EJ0204 TENESAS Page 9 of 51 Dec 25 2014 R IN32M3 Series B Built in regulator pin R IN32M3 EC needs 1 5 supply to VDD15 VDDAPLL Px VDDARXTX pin as the inner power supply for Ethernet PHY Power supply generation at outside is equipped with a regulator inside R IN32M3 EC and unnecessary using a built in regulator refer to 5 2 Built in regulator unused and design 5 1 Built in regulator used Make wiring and layout as follows at the time of the built in regulator use 5 Built in regulator pin When not R IN32M3 EC Switching Regulator Input AVDD REG VDD 3 3V Switching Regulator Input BVDD C2 22uF Tantal Regulator Output 1 5V LX GND for Switching Regulator Feedback Regulator Supply 1 5V Input Low level Figure 5 1 Wiring example of the regurator unit internal regulator used R18UZ0021EJ0204 TENESAS Dec 25 2014 Page 10 of 51 R IN32M3 Series 5 Built in regulator pin R IN32M3 AVDD BVDD Pattern Switching Regulator Input BVDD witching Regulator Inpu LX Regulator Output 1 5V LX VOUT Pattern Connection to VDD15 Powerplane GND for Switching BGND Regulator AGND REG GND Pattern AVDD REG Feedback Regulator FB Figure 5 2 Layout example of the regulator section Use recomme
10. 1 as close as possible to the PLL_VDD and PLL_GND pins C2 placement is less critical and there is no problem even if it can t be arranged as close to the R IN32M3 as C1 R18UZ0021EJ0204 Dec 25 2014 TENESAS Page 8 of 51 R IN32M3 Series 4 PLL power pins 4 2 Notes on placement of FILTER components Figure 4 2 is a image seen from the back of the board and shows the recommended placement and layout for the PLL power supply components Ceramic capacitor 0 1uF should be placed in immediate vicinity of the PLL VDD and PLL GND pins A direct via connection from the related signal pads to the bottom layer of the board is recommended so that C1 can be placed below R IN32M3 The PLL VDD and PLL GND signals should then be routed to the C2 position and then connected to VDD respectively GND via the ferrite beads FB The coupling of the ferrite beads to VDD and GND should have as low resistance as possible We therefore propose connect the related FB pads to VDD and GND with several parallel vias as shown in Figure 4 2 It should be avoided to route high frequency signal lines parallel to the PLL_VDD and PLL_GND lines Power Supply Give attention to signals which run in parallel not to undergo influence of noises PLL 4 VDD P PLL_ GND 4 GND Figure 4 2 Image viewd from the back of the board Caution PLL VDD and PLL GND lines should be as short
11. 15 HWRZO HBENZO HWRZ1 HBENZ1 HWAITZ Note3 HERROUTZ HUE port pin HBUSCLK lt BUSCLK Note HWRZSEL Low level Figure 11 6 The connection example with external MPU 16bit bus synchronous SRAM type transmission mode lt R gt R18UZ0021EJ0204 TENESAS Page 30 of 51 Dec 25 2014 R IN32M3 Series 11 External MPU memory interface pins Note1 The detail of signal connection is depend on the bus interface spec of the host MPU Please confirm the product spec of MPU which is connected to this LSI Note2 In this mode the HWRZSEL pin has to be set to low level lt R gt Note3 The connection of the HERROUTZ signal is not indispensable Please connect this signal to a interrupt or general port pin etc according to the need Note4 HA16 pin should be connected to the signal which is as the 128 Kbyte boundary address of the external MPU lt R gt Note5 This access is with byte addressing lt R gt R18UZ0021EJ0204 TENESAS Page 31 of51 Dec 25 2014 R IN32M3 Series 11 External MPU memory interface pins 11 2 External memory interface This section describes about the connection to an external memory The connection mode of the external memory interface depends on the signal levels of the MEMCSEL pin and MEMIFSEL pin Please refer the Table 11 1 11 2 1 Asynchronous SRAM MEMC Asynchronous SRAM MEMC can connect Paige ROM ROM SRAM outside by a 16 bit or 32 bit bus Peripheral
12. 22uF GND VDD15 VDD33 Decoupling with and 22nF as close to the pins as possible R IN32M3 VDDAPLL VDDACB P1VDDARXTX P2VDDARXTX VDD33ESD VSSAPLLCB Figure 7 1 Wiring example of the regulator unit R18UZ0021EJ0204 RENESAS Page 14 of 51 Dec 25 2014 R IN32M3 Series 7 Ethernet PHY pins 7 2 100Base TX pins This is an example of connection using the pulse transformer 3 3 3 3 R IN32M3 EC RJ 45 w integrated magnetics RD CT RD Shield Remarkl x 0 or 1 10nF 2kV AGND AGND AGND AGND Frame GND Figure 7 2 Connection example R IN32M3 EC and RJ 45 connector pulse transformer built in R18UZ0021EJ0204 RENESAS Page 15 of 51 Dec 25 2014 R IN32M3 Series 7 Ethernet PHY pins x 0 or 1 10nF 2kV AGND AGND AGND AGND DGND DGND Figure 7 3 Connection example R IN32M3 EC and Pulse transformer and RJ 45 connector Table 7 1 Parts list 100Base TX interface Part Type Characteristics Recommended components R1 R2 R3 R4 Resistor 49 9 Q 1 1 16W R5 R6 Resistor 100 1 1 16W R7 R8 R9 R10 Resistor 75Q 1 1 16W Capacitor 10nF 100nF Capacitor 10nF 100nF Capacitor 10nF 22nF Capacitor 10nF 22nF Capacitor 4 7nF 10 Pulse Electronics H1012NL H1102NL Pulse Electronics H1270N HX1294 One channel Transformer Twochannel RJ4
13. 5 with integrated magnetics Two channel Pulse Electronics JG0 0031NL R18UZ0021EJ0204 RENESAS Page 16 of 51 Dec 25 2014 R IN32M3 Series 7 Ethernet PHY pins The wiring on the board note the following e Long wires should be avoided R IN32M3 and the transformer and the connector should be placed together as close as possible e Crossing of differential traces with other lines and among each other should be avoided components should be placed that way that crossing of differential pairs of TxP N and RxP N is not necessary e Differential lines should be routed straight and as short as possible e Lines should bend with 135 degree angle or more Figure 7 4 e Traces between R IN32M3 EC transformer and RJ 45 connector should be designed with a differential impedance of 100Q 10 and with an impedance of 500 related to GND e The traces of a differential pair should match in length 0 5mm is the maximum deviation Adjustments of the length should be done at the connector device or transformer e Additional to the length the single traces should be designed symmetrical They should be parallel and routed in the same layer with continuous width and a preferable fixed spacing Components vias and connections should also be symmetrical e Stubs should be avoided e Preferable is a large edge gap at differential pairs g in Figure 7 2 An empty space of five times of the trace width between differential pa
14. ARTJn connection pins 13 Asynchronous Serial Interface J UARTJn connection pins Figure 13 1 shows a connection example between R IN32M3 and Asynchronous Serial Interface J UARTJn device R IN32M3 UART device TXDO Port21 E TXD1 Port31 RXD1 Port30 Figure 13 1 Connection example with the UART device R18UZ0021EJ0204 TENESAS Page 37 of 51 Dec 25 2014 R IN32M3 Series 14 2 connection pins 14 connection pins Figure 14 1 shows a connection example between R IN32M3 and Slave device The serial clock line and the serial data line are a kind of N ch open drain output so user needs to connect a pull up register Slave device R IN32M3 RP00 P60 Clock output EL h Clock output Clock input Clock input RP01 P61 Data output EL h Data output Data input Data input Figure 14 1 Connection example with the Slave device R18UZ0021EJ0204 RENESAS Page 38 of 51 Dec 25 2014 R IN32M3 Series 15 EtherCAT EEPROM I2C connection pins only R IN32M3 EC 15 EtherCAT EEPROM C connection pins only R IN32M3 EC In the case of using the EtherCAT protocol user needs to connect to the external EEPROM with the dedicated EEPROM connection pins The pins for EEPROM FC connection are the following pins CATI2CCLK pin shared with the P22 function EtherCAT EEPROM clock output CATI2CDATA pin shared with the P23 function
15. C 0 m i LENESAS R IN32M3 Series User s Manual Board design edition R IN32M3 EC R IN32M3 CL All information of mention is things at the time of this document publication and Renesas Electronics may change the product or specifications that are listed in this document without a notice Please confirm the latest information such as shown by website of Renesas Document number R18UZ0021EJ0204 Issue date Dec 25 2014 R RM Renesas Electronics www renesas com Notice Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third pa
16. CSZO R18UZ0021EJ0204 TENESAS Page 33 of 51 Dec 25 2014 R IN32M3 Series 11 External MPU memory interface pins 11 2 2 Synchronous burst access MEMC The synchronous burst access MEMC can be used to connect external page ROM ROM SRAM PSRAM NOR Flash and peripheral devices with an interface similar to the SRAM interface via the 32 16 bit bus By setting the ADMUXMODE pin to high level the address signals can be multiplexed to be output from data pins The synchronous burst access MEMC and asynchronous SRAM MEMC share external microcontroller interface pins Using these pins for the synchronous burst access MEMC is selected when the MEMCSEL pin outputs a high level and the MEMIFSEL pin outputs a low level 11 2 2 1 SRAM connection example An example of connection with SRAM is shown as follows R IN32M3 BUSCLK A2 A19 Note D16 D31 SRAM CSZn 256Kword x1 6bit RDZ E WRZ3 BENZ3 WRZ2 BENZ2 WRSTBZ BUSCLK 0 17 Note 01 1 016 SRAM 256Kwordx16bit WRZ1 21 WRZO BENZO 82 n 0 3 Figure 11 11 Example of Connection with SRAM 32bit bus synchronous burst access MEMC 2 3 BUSCLK A1 A18 Note A0 A17 Note 00 015 1 1 016 SRAM CSZn 5 256Kwordx16bit RDZ WRZ1 BENZ1 WRZO BENZO WRSTBZ 82 n 0 3 Figure 11 12 Example of Connection with SRAM 16bit bus synchro
17. EtherCAT EEPROM data Figure 15 1 shows a connection example between R IN32M3 EC and EEPROM The serial clock line and the serial data line are a kind of N ch open drain output so user needs to connect a pull up register EVDD Slave device R IN32M3 CATI2CCLK Clock output 0 Clock input CATI2CDATA Data output EL Data output 7 7 Data input Data input Figure 15 1 Connection example with the EtherCAT EEPROM R18UZ0021EJ0204 TENESAS Page 39 of 51 Dec 25 2014 R IN32M3 Series 16 CAN pins 16 pins Figure 16 1 shows a connection example between R IN32M3 and CAN Transceiver R IN32M3 CAN Transceiver CAN Bus Port54 Port56 Port53 Port55 Txd Input Rxd Output Note 0 1 Figure 16 1 Connection example with the CAN Transceiver R18UZ0021EJ0204 Dec 25 2014 TENESAS Page 40 of 51 R IN32M3 Series 17 JTAG trace pins 17 JTAG trace pins A connection example with a connector of ICE In Circuit Emulator is indicated A connection example of the 20pin half pitch connector and the 20pin full pitch connector which are a standard connector is indicated 3 3V R IN32M3 ICE Connector 20pin half pitch RESETZ HOTRESETZ Wired OR Connection with Open Drain JTAGSEL R IN32M3 CL only Low level Figure 17 1JTAQ interface connection example 20pin half pitch w
18. J R IN32M3 CL User s Manual R18UZ0005EJ R IN32M3 Series User s Manual Peripheral functions R18UZ0007EJ R IN32M3 Series Programming Manual Driver edition R18UZ0009EJ R IN32M3 Series Programming Manual OS edition R18UZ0011EJ R IN32M3 Series User s Manual TCP IP stack R18UZ0019EJ R IN32M3 Series User s Manual Peripheral Board design edition This manual The document related to OS Document name Document number LITRON 4 0 Specification Ver 4 00 00 ITRON Committee TRON ASSOCIATION dil 4 0 Specification is the open real time kernel specification developed led by TRON ASSOCIATION The uITRON 4 0 specification of this document is the extract from uITRON 4 0 Specification Ver 4 00 00 Please refer to uITRON 4 0 Specification Ver 4 00 00 about the whole aspect of specifications In addition You can obtain ITRON 4 0 Specification from website of TRON ASSOCIATION 2 Notation of Numbers and Symbols Weight in data notation Left is high order column right is low order column Active low notation XXXZ capital letter Z after pin name or signal name or xxx capital letter after pin name or signal name or xxnx name or signal name contains small letter n Note explanation of Note in the text Caution Item deserving extra attention Remark Supplementary explanation to the text Numeric notation Binary lt lt xxxx xxxxB or n bxxxx n bi
19. aused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction When exporting the Renesas Electronics products or technology de
20. ce on the board or fix logic as opposite device There is a possibility that a floating current flows when 3st pin or others is Hi z state 211 BSCAN operating prevision Fix the level of the pins as follows e JTAGSEL high level TMODEO low level e TMODEI low level TMODE2 low level 21 2 Maximum operating frequency of TCK The maximum operating frequency of is 10MHz 21 3 IDCORE is as follows 1 R IN32M3 CL IDCODE 0x081A3447 breakdown version 0000 part number 10000001 1010001 1 Manufacturer number Renesas Electronics 0100010001 1 Fixed code 1 2 R IN32M3 EC IDCODE 0x081A4447 breakdown version 0000 part number 1000000110100100 Manufacturer number Renesas Electronics 0100010001 1 Fixed code 1 R18UZ0021EJ0204 RENESAS Page 47 of 51 Dec 25 2014 R IN32M3 Series 21 4 BSCAN non correspondence The following pin is not supported in BSCAN Table 21 1 List of pins which is not supported in BSCAN R IN32M3 CL 21 BSCAN information R IN32M3 EC XT1 XT2 PONRZ JTAGSEL TMODEO TMODE1 TMODE2 TMS TDI TDO TRSTZ TCK TMC1 TMC2 XT1 XT2 PONRZ JTAGSEL TMODEO TMODE1 TMODE2 TMS TDI TDO TRSTZ TCK TMC1 TMC2 PO RX P PO P1 RX P Pl RXN PO TX P PO TX N Pl TX P Pl TX TESTI TEST2 TEST3 ATP LX EXTRES R18UZ0021EJ0204 Dec 25 2014 TENESAS Page 48 of 51 R IN32M3 Series 21 BSCAN informa
21. ction example with an optical fiber module is indicated below Notes of the differential signal transmission line please refer to 7 2 100Base TX pins VDDQ Bx 3 3V R IN32M3 EC Optical Transceiver Px TD OUT P Px TD OUT N Px FX OUT Remark x 0 1 AFBR 5978Z QFBR 5978AZ Figure 7 7 Interface circuit with optical transceiver Table 7 2 Part list 100Base FX interface Part Type Characteristics Recommended components R1 R2 Resistor 150 1 R3 R4 R7 Resistor 1309 1 R5 R6 R9 Resistor 820 1 R8 Resistor 86 60 1 R10 Resistor 127 Q 1 Optical Transceiver One channel age AFBR 5978Z QFBR 5978AZ R18UZ0021EJ0204 RENESAS Page 19 of 51 Dec 25 2014 R IN32M3 Series 8 GMII pins R IN32M3 CL only 8 GMII pins R IN32M3 CL only Figure 8 1 shows a connection image of R IN32M3 CL and Gigabit Ethernet PHY The damping register value should be 33 ohm within a tolerance of 5 and the damping resistors should be put in the nearest point of R IN32M3 CL And wires of target pins which is GTXC TXDx TXEN and TXER are recommended to be short and the same length 3 3V ETH MDC ETH MDIO ETHm TXC ETHm GTXC ETHm TXDx RJ45 Connector Damping resistor 33 5 GND Shield ETHm COL ETHm CRS R IN32M3 CL Gigabit Ethernet PHY Remark 0 1 0 7 Figure 8 1 Connection image of R IN32M3 CL and PHY R18UZ0021EJ0204 TENESAS Pag
22. d modify Note2 4 5 description in 11 1 3 Synchronous SRAM type transmission mode Memo 2 5 1 lt SALES OFFICES Renesas Electronics Corporation http Avww renesas com Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 651 700 Fax 44 1628 651 804 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 204 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2886 9318 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronic
23. e 20 of 51 Dec 25 2014 R IN32M3 Series 8 GMII pins R IN32M3 CL only 8 1 Selection of GMII peripheral components Please select the parts with care to the following Selection of PHY Full duplex products IEEE802 3 1000BASE T Pe parts that has the auto negotiation function Parts with a GMII interface Parts that has the auto MDI MDIX negotiation function Operable parts at 125MHz about MDC clock frequency Selection of the crystal cscillator for PHY Regarding Jitter and frequency select the parts to adapt to the requirement of the PHY 8 2 Circuit design around GMII Please design the GMII peripheral circuits with care to the following Wiring of GMII Please put the damping resistor of overshoot undershoot protection For PHY address Please be set to the same address as the port mumber of the R IN32M3 CL and The PHY address Connect to the PHY assigned address1 to MAC portl And Connect to the PHY assigned address2 to MAC port2 8 3 Pattern desing around GMII Please design the GMII peripheral circuits pattern with care to the following And t he wiring pattern should be the shortest and choose width and layer thickness to be 50Q Do not bend at 45 degrees or less to signal pattern The power GND pattern please be wired with a thick pattern as much as possible R18UZ0021EJ0204 RENESAS Page 21 of 51 Dec 25 2014 R IN32MS Series 9 CC Link pins 9 CC Link pins The connection example for CC Link Remote device stat
24. each power supply 100ms or less time measurement is based on the period from 10 to 90 of each voltage range voltage VDD33 Note PHY voltage VDD15 Internal voltage VDD10 GND 0 1 VDD10 0 9 VDD33 0 1 VDD10 Figure 2 1 Recommended sequence of Power on off Note The timing for PHY power supply voltage VDD15 only needs to be observed when the internal regulator in the R IN32M3 EC device is not used R18UZ0021EJ0204 Dec 25 2014 TENESAS Page 2 of 51 R IN32M3 Series 2 2 Power supply pins This is a power supply pins list of R IN32M3 2 Power Reset pins Please connect these pins according to the description given in the Connection example column Terminal name PLL VDD Feature PLL voltage VDD 1 0V Connection example Refer to 4 PLL power pins PLL GND VDD33 PLL GND potential GND I Os voltage 3 3V Refer to 4 PLL power pins Supply a power supply from the power unit such as a regulator or DC DC converter VDD10 Internal voltage 1 0V Supply a power supply from the power unit such as a regulator or DC DC converter GND GND potential GND Connect GND of system board VDDQ MIjN9e Ethernet I Os voltage 3 3V Supply a power supply from the power unit such as a regulator or DC DC converter LxNotet Built in regulator 1 5V output
25. ed for being used by engineers that work on a circuit and PCB design that is equipped with an Ethernet communication LSI from the R IN32MG series made by Renesas Electronics Target devices are the R IN32M3 EC and R IN32M3 CL devices It is recommended to study this manual carefully and to follow the recommendations during the circuit and board design R18UZ0021EJ0204 TENESAS Page 1 of 32 Dec 25 2014 R IN32M3 Series 2 Power Reset pins 2 1 Power on off sequence 2 Power Reset pins Power structure of R IN32M3 series is internal power VDD10 1 0V and I O power VDD33 3 3V and PHY power supply VDD15 1 5V PHY power is subject only R IN32M3 EC Power is recommended to put the I O power after switching on the internal power supply recommend internal power off after cut off of I O power In the case of supplying internal power after I O power In addition power off is Please note that I O value becomes an indefinite due to uncertain mode while I O is powered on but internal power isn t regardless of an input output mode supply voltages Also 3 3 V must be applied to the I O pins only after applying the power Power on off time difference that regardless of the power on sequence it does not matter which power supply is applied to or removed from the device first VDDI IVDD or VDD3 EVDD but it is recommended to ensure 100ms or less time difference between the application or removal of
26. his LSI Note2 HWRZO HWRZ3 and HBENZO HBENZ3 is assigned to the same pin The function is decided by the signal level of HWRZSEL pin Note3 The connection of the HERROUTZ signal is not indispensable Please connect this signal to a interrupt or general port pin etc according to the need Note4 PGCSZ signal is a chip select signal which can do page access Please connect this signal according to the need Note5 HA2 pin should be connected to the signal which is as the 4 byte boundary address of the external MPU Note6 HA1 pin should be connected to the signal which is as the 2 byte boundary address of the external MPU R18UZ0021EJ0204 TENESAS Page 29 of 51 Dec 25 2014 R IN32M3 Series 11 External MPU memory interface pins 11 1 3 Synchronous SRAM type transmission mode The following figure shows a general connection example with the synchronous SRAM type transmission mode when the external MPU connects as the host When user uses this mode please enable address data multiplex function ADMUXMODE pin should be set to high level R IN32M3 External MPU HWRZ1 HBENZ1 HWRZ2 HBENZ2 HWRZ3 HBENZ3 HWAITZ Notes HERROUTZ Interrupt port pin HBUSCLK BUSCLK Note2 HWRZSEL Low level Figure 11 5 The connection example with external MPU 32bit bus synchronous SRAM type transmission mode lt R gt R IN32M3 External MPU Note HA16 HA19 17 20 Notes HDO HD
27. ii Boon prO DOR UI UR Aida 15 7 3 100Base FX pins Optical fiber etre mette HH vaka CHR ERE GE er Pe Reti 19 8 GMII pins R INS2M3 CL 20 8 1 Selection of peripheral components nennen nennen eene rennen 21 8 2 Circuit design around cage PEN E PE PEPPER SO Ska al silkon SE EE EEAS 21 8 3 Pattern desing around epe ete pis 21 Contents 1 GO INK pilis sui Lit bte oe ber eee eia erp een n ead denote ep a HU taeda 22 10 Notes of CC Link IE Field use only 2 3 24 11 External MPU memory interface 25 11 1 rei ER eR gn 26 11 1 1 Asynchronous SRAM interface rerien ne e a nennen enne rennen 26 11 1 2 Synchronous SRAM interface mode 222221 0 1 00000000000 nennen trennen nene 28 11 1 3 Synchronous SRAM type transmission 30 11 2 External memory interface iine perg eco te pierden tto 32 11 2 1 Asynchronous SRAM 22 02 2020 1 000 00000000000 32 11 2 2 Synchronous burst access MEMC 34 12 Serial flash ROM connection pins 2 0 40000000 cnn 36 13 A
28. ion is shown in Figure 9 1 lt R gt Notes on the implementation of the CC Link so be found in the CC Link Association issued CC Link specification implementation defined Edition in BAP 05027 please look there Please contact CLPA CC Link Association about the claim of the material http www cc link org jp support material index html For document requests contact CC Link Partner Association CLPA TEL 052 919 1588 FAX 052 916 8655 Email info cc link org R18UZ0021EJ0204 TENESAS Page 22 of 51 Dec 25 2014 R IN32M3 Series 9 CC Link pins SN75ALS181SN 14 35605 5153 B00 PE MC177050 n dpa A 2 Zs Ua B C p sto T sov I re LH 8 1 HZU6 2ZTRF E gt N STATIONNO X10 STATION NO XI B RATE WV WV p rs p gt Y T H 3 3 0 1uF R IN32M3 CCS RD P53 RDENI Pxxi 1 Note2 CCS SDGATEON P5 2 CCS SD P54 CCS STATION NO 7 P COS STATION NO 6 P U amp S STATION NO 5 P C8 S STATION NO 4 P 74 CCS STATION NO 3 P 2 5 STATION NO 2 P TX S STATION NO P COS STATION NO 70 CCS BS 8 RP05 CCS BS 4 RP04 CCS BS 2 RP03 CCS BS 1 RP02 CCS ERRZ P25 CCS RUNZ P26 CCS LNKRUNZ P50 CCS RDZ P51 CCS SDZ RP00 CCS IOTENSU P22 CCS SENYU1 P24 CCS CLK80M CCS WDTZ P13 CCS MON7 P05 CCS MONG P04 CCS MONS P03 CCS 11 CCS MON3 P34 CCS MON2 P33
29. ir and other signals planes or components is recommended e Differential lines should not cross edges of the GND supply plane other planes or voids in the layer below For continuous impedance a GND plane in the layer below is preferable e Beneath the magnetics no lines or planes should be routed e Preferable differential pairs should be routed via as little vias as possible If vias are necessary please note the following a Vias of the related plane e g AGND should be placed near the signal vias The distance between signal via and GND via should be equal to the distance between the layers to avoid a discontinuity of the impedance See Figure 7 6 b Void and no planes between and around the signal vias see Figure 7 3 Metal of planes close to the differential vias could influence the impedance c The diameter of the vias should be almost equal to the trace width See w in Figure 7 3 Figure 7 4 Wiring example of the differential signal transmission line 1 R18UZ0021EJ0204 TENESAS Page 17 of 51 Dec 25 2014 R IN32M3 Series 7 Ethernet PHY pins 5 W 8 Figure 7 5 Wiring example of the differential signal transmission line 2 Figure 7 6 Wiring example of the differential signal transmission line 3 R18UZ0021EJ0204 TENESAS Page 18 of 51 Dec 25 2014 R IN32M3 Series 7 Ethernet PHY pins 7 3 100Base FX pins Optical fiber Conne
30. ithout trace As long as nRESET is input to RESETZ nRESET is not required to input to HOTRESET RESRTZ resets the entire LSI but the internal PLL is not reset in the case of only HOTRESETZ Please use it to meet your needs And nRESET should not connect to PONRZ R18UZ0021EJ0204 RENESAS Page 41 of 51 Dec 25 2014 R IN32M3 Series 17 JTAG trace pins 3 3V R IN32M3 4 7kQ 10k Q ICE Connector 20pin half pitch RESETZ HOTRESETZ nRESET Wired OR Connection with Open Drain TRSTZ TOK TCK TMS TMS TDI TDI TDO TDO TRACECLK TRACECLK TRACEDATAO TRACEDATAO TRACEDATA1 TRACEDATA1 TRACEDATA2 TRACEDATA2 TRACEDATA3 TRACEDATA3 220 33Q The wires should be the same length JTAGSEL and 50mm 100mm length R IN32M3 CL only Low level Figure 17 2JTAG interface connection example 20pin half pitch with trace R18UZ0021EJ0204 RENESAS Page 42 of 51 Dec 25 2014 R IN32M3 Series 17 JTAG trace pins 3 3 R IN32M3 4 7kQ 10k Q ICE Connector 20pin full pitch RESETZ HOTRESETZ ired OR Connection with Open Drain TRSTZ TCK TMS TDI TDO O JTAGSEL R IN32M3 CL only AL Low level Figure 17 3JTAG interface connection example 20pin full pitch R18UZ0021EJ0204 RENESAS Page 43 of 51 Dec 25 2014 R IN32MS Series 18 Implementation conditions 18 Implementatio
31. lt in RAM TRSTZ JTAG reset signal Refer to 17 JTAG trace pins RSTOUTZ Reset output to outside note R IN32M3 CL only R18UZ0021EJ0204 RENESAS Page 4 of 51 Dec 25 2014 R IN32M3 Series 3 Clock input pins 3 Clock input pins 3 1 Features of pins The following table shows the pin functions for clock supply to the device Pin name yo Features XT1 IN External resonator connection pin When external clock input mode is used OSCTH 1 please set XT1 to the low level XT2 IN OUT External resonator connection pins When OSCTH 0 this pin is the output When external clock input mode is used OSCTH 1 please input the clock from an external oscillator to XT2 OSCTH IN Select the clock source to be connected to the clock pin Low level Connect the resonator XT2 and XT1 High level Connect the oscillator XT2 R18UZ0021EJ0204 TENESAS Page 5 of51 Dec 25 2014 R IN32M3 Series 3 Clock input pins 3 2 Note the oscillation circuit configuration The R IN32M3 devices have an internal oscillator and the user can build the required clock supply simply from an external crystal and some fixed components or alternatively with an external oscillator driving XT2 As the oscillation circuit operates at high frequencies is should be designed according to the rules for analog circuits To achieve stable operation of the oscillation circuit it may be required to try several combinations
32. n conditions Figure 18 1 and Figure 18 2 show implementation conditions Open the aluminum dry pack Storage period is 7 days and under Baking 1251 201 75h Storage conditions 30 degrees or less Infrared reflow within 3 times temperature and less than 7096 humiditv Figure 18 1 Implementation flow Maximum temperature package surface temperature 260 C and under Time of Maximum temperature 10s and under Time which temperature is more than 220 C 60s and under Time of p reheat temperature 160 180 C 60 120s Number of maximum reflow times 3times The chloric content of the rosinous flux the weight parcentage 0 2 and under Safekeeping restriction period after opening the dry pack 7 days and under 60 120s preheat Package surface temperature C Time s Figure 18 2 Infrared reflow temperature profile R18UZ0021EJ0204 RENESAS Page 44 of 51 Dec 25 2014 R IN32M3 Series 19 Package informations 19 Package informations Figure 19 1 shows Package informations 324 PIN PLASTIC BGA 19x19 D ZE ZD gt 4 18 000000000000000000 16 15 000000000000000000
33. nded parts DI Schottky diode STPSIL30UPBF Vishay LI Inductor 10 u H VLCF5028T provided by TDK CI C2 Capacitor 22 ESR 300m PSLB21A226M NEC Tokin R18UZ0021EJ0204 RENESAS Page 11 of 51 Dec 25 2014 R IN32M3 Series 5 Built in regulator pin 5 2 Built in regulator unused The built in regulator when not in user wiring as follows R IN32M3 EC Switching Regulator Input AVDD REG VDD 3 3V Switching Regulator Input BVDD Regulator Output 1 5V LX Unused open GND for Switching BGND Regulator AGND REG Feedback Regulator FB VDD 1 5V Supply 1 5V Input VDD15 Supply stable power supply High level Low level Figure 5 3 Wiring example of the regulator unit internal regulator is not used R18UZ0021EJ0204 RENESAS Page 12 of 51 Dec 25 2014 R IN32M3 Series 6 GPIO port pins 6 GPIO port pins GPIO is general purpose IO port Regarding internal structure please refer below document R IN32M3 EC User s Manual R IN32M3 EC 2 3 5 Port Signals R IN32M3 CL User s Manual R IN32M3 CL 2 5 5 Port Signals R18UZ0021EJ0204 TENESAS Page 13 of 51 Dec 25 2014 R IN32M3 Series 7 Ethernet PHY pins 7 Ethernet PHY pins 7 1 Ethernet PHY power supply pins Analog power supply pin for the built in Ethernet PHY of R IN32M3 EC recommends power separation by ferrite beads FB filters and configuration as follows Decoupling with 0 1uF and
34. nous burst access MEMC Note When the address data multiprexing mode is enable the ADMUZMODE pin is high level the connection of the address buses don t need R18UZ0021EJ0204 RENESAS Page 34 of 51 Dec 25 2014 R IN32M3 Series 11 External MPU memory interface pins 11 2 2 2 Page ROM Connection Example An example of connection with page ROM is shown as follows R IN32M3 BUSCLK A2 A21 Note D16 D31 CSZ0 RDZ BUSCLK A0 A19 Note Page ROM 1Mwordx 16bit Page ROM 1Mwordx 16bit R IN32M3 BUSCLK A1 A20 Note 0 19 Note 00 015 Page ROM 1Mwordx 16bit Figure 11 14 Example of Connection with Page ROM 16bit bus synchronous burst access MEMC Caution The on page mode of page ROM is available only when the ROM is connected to CSZO Note When the address data multiprexing mode is enable the ADMUZMODE pin is high level the connection of the address buses don t need R18UZ0021EJ0204 Dec 25 2014 RENESAS Page 35 of 51 R IN32M3 Series 12 Serial flash ROM connection pins 12 Serial flash ROM connection pins R IN32M3 is connected with the serial flash ROM as shown below R IN32M3 Serial flash ROM IS ICS C CLK D 100 Q IO1 Figure 12 1 Connection with Serial Flash ROM R18UZ0021EJ0204 TENESAS Page 36 of 51 Dec 25 2014 R IN32M3 Series 13 Asynchronous Serial Interface J U
35. ns 34 Add a description of 13 Asynchronous Serial Interface J UARTJ connection pins 35 Add a description of 14 connection pins 36 Add a description of 15 EtherCAT EEPROM connection pins 37 Add a description of 16 CAN pins 38 Add a description of 17 JTAG trace pins Feb 07 2014 Modify the mode description of the case of MEMCSEL High and HIFSYNC Low Delete HBCYSTZ pin connection of Fig 11 1 and Fig 11 2 Modifiy the width of data bus of Fig 11 2 Add the description of Note4 6 of Fig 11 1 and Fig 11 2 Delete HBCYSTZ pin connection of Fig 11 3 and Fig 11 4 Modifiy the width of data bus of Fig 11 4 Modifiy the width of address bus of Fig 11 4 Add the description of Note4 6 of Fig 11 3 Fig 11 4 Separete and add the description about synchronous SRAM type transmission mode May 30 2014 Add a notes of 2 1 Power on off sequence Modify Eglish expression about capter 1 4 Sep 30 2014 Modify part name of inductor VLC5028T to VLCF5028T in 5 1Built in regulator used Modify ESR value of condenser 300 ohm to 300 mohm in 5 1Built in regulator used 25 29 Fig 11 1 11 6 Modify signal name BUSCLK to HBUSCLK 40 Add a description in 17 JTAG trace pins Dec 25 2014 22 23 Add Fig 9 1 in 9 CC Link pins 29 30 Modify Fig 11 5 11 6 to add HBCYSTZ connection modify Adress bus number and delete HHPGCSZ connection An
36. of fixed components based on the recommendations of the crystal or resonator manufacturer Generally the following points should be observed The clock supply circuit including the fixed components should be placed near to the clock input pins of the R IN32M3 XT1 XT2 All clock related connections should be as short as possible Ground connections of the load capacitors should be as short and wide as possible The clock supply circuit should be separated from other sensitive signal and communication lines Preferably the clock supply circuit is surrounded with a DGND pattern The used devices for the external clock may have their own design recommendations They should also be considered OSCTH R IN32M3 XT1 XT2 Boar GND pattern Figure 3 1 GND pattern example of external constant part The values for the external components should be evaluated based on the actual PCB design and on the actually used oscillator respectively resonator Typically a safe operation area can be found over several boards and different combinations of external components then component selection for production should be done in such a way that operation is always safe R18UZ0021EJ0204 TENESAS Page 6 of 51 Dec 25 2014 R IN32M3 Series 3 Clock input pins 3 3 Oscillation circuit configuration example The following figure shows typical examples of oscillation circuits
37. rect operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable ARM AMBA ARM Cortex Thumb and ARM Cortex M3 are a trademark or a registered trademark of ARM Limited in EU and other countries Ethernet is a registered trademark of Fuji Zerox Limited IEEE is a registered trademark of the Institute of Electrical and Electronics Engineers Inc EtherCAT is a registered trademark of Beckhoff Automation GmbH Germany CC Link and CC Link IE Field are a registered trademark of CC Link Partner Association CLPA Additionally all product names and service names in this document are a trademark or a registered trademark which belongs to the respective owners Real Time OS Accelerator and Hardware Real Time OS is based on Hardware Real Time OS of ARTESSO made in KERNELON SILICON Inc How to use this manual 1 P
38. rties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster Systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implanta
39. s Singapore Pte Ltd 80 Bendemeer Road Unit 06 02 Hyflux Innovation Centre Singapore 339949 Tel 65 6213 0200 Fax 65 6213 0300 Renesas Electronics Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jin Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2013 2014 Renesas Electronics Corporation All rights reserved R IN32M3 Series User s Manual Board design edition RENESAS Renesas Electronics Corporation
40. scribed in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations 10 It is the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products 11 This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics Instructions for the use of product In this section the precautions are described for over whole of CMOS device Please refer to this manual about individual precaution When there is a mention unlike the text of this manual a mention of the text takes first priority
41. should be connected to the signal which is as the 2 byte boundary address of the external MPU R18UZ0021EJ0204 TENESAS Page 27 of 51 Dec 25 2014 R IN32M3 Series 11 External MPU memory interface pins 11 1 2 Synchronous SRAM interface mode The following figure shows a general connection example with the synchronous SRAM interface mode when the external MPU connects as the host R IN32M3 External MPU Notes HA2 HA20 HDO HD31 HCSZ Notes HPGCSZ HRDZ HWRSTBZ HWRZO HBENZO WRZO0 BENZO HWRZ1 HBENZ1 Wire BENZ1 HWRZ HBENZ2 WRZ2 BENZ2 HWRZS HBENZ3 WRZ3 BENZ3 HWAITZ WAITZ Notes HERROUTZ Interrupt port pin HBUSCLK BUSCLK Figure 11 3 The connection example with external MPU 32bit bus synchronous SRAM interface mode R IN32M3 External MPU Note6 HA1 HA20 A1 A20 HDO HD15 DO D15 HCSZ CSZ Notes HPGCSZ PGCSZ RDZ WRSTBZ 20 BENZO HWRZ1 21 21 21 HWAITZ WAITZ Note3 HERROUTZ Interrupt port pin HBUSCLK BUSCLK Figure 11 4 The connection example with external MPU 16bit bus synchronous SRAM interface mode R18UZ0021EJ0204 TENESAS Page 28 of 51 Dec 25 2014 R IN32M3 Series 11 External MPU memory interface pins Note1 The detail of signal connection is depend on the bus interface spec of the host MPU Please confirm the product spec of MPU which is connected to t
42. synchronous Serial Interface J UARTJn connection pins sss 37 Sonnet ort epu 38 15 EtherCAT EEPROM connection pins only R INS2M3 EC cscscessssessessssessesscsessesscsecsessteesseaneeeeeeaes 39 16 GAN PINS ds 40 d o TPAGIACOIDS d rs sk vaks eee c ptt IM ekas rece 41 18 Implementation conditions 44 19 Package Informations ss ses ede EE eene EO IO de I A A 45 20 Mount pad A 46 21 BSGAN informations x decet cete e HR eie e o Rei eti det Ge ete etd 47 21 1 BSCAN operating prevision ie eU e eb REMISE ss suse ee Eae I C oie ko Veko e ELLO 47 21 2 Maximum operating Trequency Of TOK ue DI re a luo biete 47 21 3 IDIO DI TT E e rer pr enpo p ron prp p e ero o o rn o o rn t ERR 47 21 4 BSCAN non correspondence 48 21 5 Howto get BSDE Aesthetic ca atte et Ae ete Ra 49 Contents 2 22 IBIS Information esses n nennen nana 50 23 Impress INTO MALO s s eere rect veo ede eee a eleo ru elaaj 51 232 RINI MEC en EENS ia DIN 51 232222 2 3 oseo oasis usas uas sid 51 Contents 3 24 NESAS R IN32M3 Series User s Manual Board design edition R18UZ0021EJ0204 Dec 25 2014 1 Outline This manual is intend
43. tion 21 5 Howto get BSDL With regard to obtain BSDL file please contact your sales representative R18UZ0021EJ0204 TENESAS Page 49 of 51 Dec 25 2014 R IN32M3 Series 22 IBIS Information 22 IBIS Information Please obtaion from the following website IBIS information http japan renesas com products soc assp fa_lsi multi_protocol_communication r in32m3 peer documents jsp R18UZ0021EJ0204 TENESAS Page 50 of 51 Dec 25 2014 R IN32M3 Series 23 Impress information 23 Impress information 23 1 R IN32M3 EC Product name MC 10287F1 HN4 M1 A MC 10287 Figure 23 1 R IN32M3 EC Impress information 23 2 R IN32M3 CL Product name UPD60510F1 HN4 M1 A HEA Figure 23 2 R IN32M3 CL Impress information R18UZ0021EJ0204 RENESAS Page 51 of 51 Dec 25 2014 REVISION HISTORY R IN32M3 Series User s Manual Board design edition Rev Date Description Page Summary 1 00 Jul 26 2013 E First edition issued 1 01 Dec 02 2013 10 12 Add the TEST pin processing 22 Add 9 Notes of CC Link IE Fleld user only R IN32M3 CL 2 00 Dec 26 2013 11 Add a description of 6 GPIO port pins 20 Adda description of 8 GMII pins 23 Modify a description of 10 Notes of CC Link IE Field use 24 Add a description of 11 External MPU memory interface pins 33 Add a description of 12 Serial Flash ROM memory connection pi
44. tions etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage c
45. ts Decimal 22 xxxx Hexadecimal gt lt xxxxH or n hxxxx n bits Prefixes representing powers of 2 address space memory capacity kilo 2 1024 M mega 2 1024 giga 2 10243 Data Type Word 32 bits Halfword gt lt 16 bits Byte 8 bits Contents PEE TD 1 2 Power Beset PINS uie a nie ie A E Ea Talao 2 2 1 Power on off sequence nnper iR ORO e REGIT IER TO DIR ED re D RR EE e SEEDERS Ee Ere IRURE 2 22 Powersupply pins eene peo EH ERU a e i UE e DII ee 3 2 3 Reset PINS Goin het teta dt ate eet et lahore 4 82 Glock INDUt PINS 4 EE 5 3 1 Features Of pins raciocinio 2 32 Note the oscillation circuit CONFIgUTAtlON e eren enne 6 3 3 Oscillation circuit configuration example 7 4 HNIC NJ 8 4 1 Recommended FILTER composition 5 o oie tete cp dpi ii 8 4 2 Notes on placement of FILTER enne enne enne nennt trennen trennen entente 9 5 regulator pin amp A AM ae 10 5 1 Built in regulator Used ORE T Datan sno IRR ORG t URS ee rene 10 5 2 Builtin regulator unused sorier o SS SG Re eR EE Reihe 12 6 OPIO POFEDIAS A A e E 13 Ethernet PRY sa e oet in a it vs ele t a ph s 14 7 1 Ethernet PHY power supply DINS eee dee ee 14 7 2 LOO Base PX pins si
46. urpose and target readers This manual is intended for users who wish to understand the functions of Industrial Ethernet network LSI R IN32M3 EC CL for designing application of it It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering logic circuits and microcontrollers Particular attention should be paid to the precautionary notes when using the manual These notes occur within the body of the text at the end of each section and in the Usage Notes section The revision history summarizes the locations of revisions and additions It does not list all revisions Refer to the text of the manual for details The mark lt R gt means the updated point in this revision The mark lt R gt let users search for the updated point in this document Related The related documents indicated in this publication may include preliminary versions However Documents preliminary versions are not marked as such Please be understanding of this beforehand In addition because we make document at development planning of each core the related document may be the document for individual customers Last four digits of document number described as indicate version information of each document Please download the latest document from our web site and refer to it The document related to R IN32M3 Series R IN32M3 Series Datasheet R18DS0008EJ R IN32M3 EC User s Manual R18UZ0003E
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