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1. Signal Pin Signal Pin LD 0 W7 LD 16 AB13 LD 1 V7 LD 17 11 LD 2 10 LD 18 LD 3 5 LD 19 LD 4 10 LD 20 L3 LD 5 M4 LD 21 4 LD 6 W10 LD 22 M3 LD 7 K3 LD 23 Y9 LD 8 M5 LD 24 AB10 LD 9 N6 LD 25 AA9 LD 10 V11 LD 26 P4 LD 11 AB15 LD 27 T5 LD 12 AA14 LD 28 AB9 LD 13 U10 LD 29 V6 LD 14 W11 LD 30 Y7 LD 15 U9 LD 31 8 Figure 5 3 Pin Assignment Local Bus Data Signals TCP630 User Manual Issue 1 0 Page 25 of 46 TEWS S TECHNOLOGIES 5 2 3 Pin Assignment of Local Bus Address Signals Signal Pin Signal Pin LA 2 P3 LA 13 V4 LA 3 W6 LA 14 AB5 LA 4 T4 LA 15 R3 LA 5 AAT LA 16 T3 LA 6 U4 LA 17 U3 LA 7 AB7 LA 18 V3 LA 8 AAG LA 19 W3 LA 9 W5 LA 20 AB3 LA 10 AB6 LA 21 11 5 22 W2 LA 12 AA5 LA 23 2 Figure 5 4 Pin Assignment Local Bus Address Signals 5 2 4 Pin Assignment of Clock Signals Signal Pin Description Default values BCLK 12 PCI Clock PCI Clock from Carrier CLK1 AB12 CLK1 Output of Clock Generator 50 MHz CLK2 A11 CLK2 Output of Clock Generator 20 MHz CLK3 C11 CLK3 Output of Clock Generator 10 MHz CLK4 AB21 CLK4 Output of Clock Generator 1 MHz CLK5 W22 CLK5 Output of Clock Generator 200 kHz CLK6 U21 CLK6 Output of Clock Generator Off
2. Figure 5 5 Pin Assignment Clock Inputs TCP630 User Manual Issue 1 0 Page 26 of 46 TEWS S TECHNOLOGIES 5 2 5 Pin Assignment of FPGA Input Lines Signal Pin Signal Pin FPGA IN 0 F1 FPGA IN 32 E19 FPGA IN 1 C1 FPGA 33 E20 FPGA IN 2 D2 FPGA IN 34 F11 FPGA IN 3 D3 FPGA IN 35 F19 FPGA IN 4 G3 FPGA IN 36 N18 FPGA IN 5 C5 FPGA IN 37 N19 FPGA IN 6 F5 FPGA IN 38 J4 FPGA IN 7 B7 FPGA IN 39 M18 FPGA IN 8 A9 FPGA IN 40 M20 FPGA IN 9 C8 FPGA IN 41 J5 FPGA IN 10 A14 FPGA IN 42 L18 FPGA IN 11 C12 FPGA IN 43 H4 FPGA IN 12 C9 FPGA IN 44 U13 FPGA IN 13 B10 FPGA IN 45 V15 FPGA IN 14 C15 FPGA IN 46 U14 FPGA IN 15 D15 FPGA IN 47 V16 FPGA IN 16 E10 FPGA IN 48 V20 FPGA IN 17 E13 FPGA IN 49 L6 FPGA IN 18 M19 FPGA IN 50 U20 FPGA IN 19 L20 FPGA IN 51 T18 FPGA IN 20 A15 FPGA IN 52 AA13 FPGA IN 21 B14 FPGA IN 53 V12 FPGA IN 22 L22 FPGA IN 54 AB17 FPGA IN 23 K22 FPGA IN 55 U12 FPGA IN 24 J22 FPGA IN 56 AB18 FPGA IN 25 A18 FPGA IN 57 Y16 FPGA IN 26 R21 FPGA IN 58 W15 FPGA IN 27 R22 FPGA IN 59 AB20 FPGA IN 28 E16 FPGA IN 60 8 FPGA IN 29 E17 FPGA IN 61 N3 FPGA IN 30 V21 FPGA IN 62 W9 FPGA IN 31 V22 FPGA IN 63 V9 Figure 5 6 Pin Assignment FPGA Input Lines TCP630 User Manual Issue 1 0 Page 27 of 46 5
3. Dainese ip ie 11 OUTPUT REGISTER 1 _ 12 INPUT REGISTER IN REGO ico sh Ren euenire 13 INPUT REGISTER 1 IN 14 OUTPUT ENABLE REGISTER 0 _ 15 OUTPUT ENABLE REGISTER 1 REG1 sse 16 INTERRUPT STATUS REGISTER 17 POSITIVE EDGE INTERRUPT ENABLE REGISTER PIER 17 NEGATIVE EDGE INTERRUPT ENABLE REGISTER 17 ADDRESS MAP REGISTER RAMR 18 DEFAULT PCI9030 HEADER 19 PCI9030 PCI BASE ADDRESS USAGE sse nennen 20 PCI9030 LOCAL CONFIGURATION REGISTER n naa 21 CONFIGURATION EEPROM TCP690 22 DEFAULT VALUES OF SPACE 0 REGION 23 FPGA SIGNALS BLOCK L I L rennen nennen entere 24 PIN ASSIGNMENT LOCAL BUS CONTROL SIGNALS sse 25 PIN ASSIGNMENT LOCAL BUS DATA SIGNALS 25 PIN ASSIGNMENT LOCAL BUS ADDRESS SIGNALS sse 26 PIN ASSIGNMENT CLOCK INPUTS 26 PIN ASSIGNMENT FPGA INPUT LINES sese n n nana 27 PIN ASSIGN
4. 43 FIGURE 8 6 PIN ASSIGNMENT J2 CONNECTOR TCP630 20 44 FIGURE 8 7 PIN ASSIGNMENT J2 CONNECTOR 630 21 45 FIGURE 8 8 PIN ASSIGNMENT J2 CONNECTOR 630 22 46 TCP630 User Manual Issue 1 0 Page 7 of 46 TEWS S TECHNOLOGIES 1 Product Description The TCP630 is a standard 3U 32 bit CompactPCI module providing a user configurable FPGA with 300 000 system gates All local signals from the PCI controller are routed to the FPGA The TCP630 x0 has 64 ESD protected TTL lines the TCP630 x1 provides 32 differential I O lines using EIA 422 EIA 485 compatible ESD protected line transceivers The TCP630 x2 provides 32 TTL and 16 differential I Os All lines are individually programmable as input output or tri state The receivers are always enabled which allows determining the state of each I O line at any time This be used as read back function for lines configured as outputs Each TTL line has a pull up resistor The pull up voltage is selectable to be either 3 3V or 5V The differential I O lines are terminated by 1200 resistors The FPGA is configured by a serial Flash The Flash device is in system programmable via driver software over the PCI bus An in circuit debugging option is available via an optionally mountabl
5. 25 5 2 3 Pin Assignment of Local Bus Address Signals aa 26 5 2 4 Pin Assignment of Clock 1 eee emen 26 5 2 5 Pin Assignment of FPGA Input Lines essem emm emm 27 5 2 6 Pin Assignment of FPGA Output Lines I n a 28 5 2 7 Pin Assignment of FPGA Output Enable Lines essem 29 6 CONFIGURATION HINTS 30 6 1 Big Little 30 6 2 Glock u 32 6 2 1 Default Clock Programming essem nennen enne 32 f INSTALLATION 34 7 1 6 34 7 2 UO 34 24 TILEI O Interface inei gi 34 7 2 2 Differential VO Interface eren eco ear 35 7 3 Back VO 36 7 4 FPGA Debug Connector J U U U u u u u J J J 37 7 5 Bee 38 TCP630 User Manual Issue 1 0 Page 4 of 46 TEWS S TECHNOLOGIES 8 PIN ASSIGNMENT CONNECTOR 39 8 1 PIM Slot 40 8 1 1 mre 40 8 1 2 Assignment TCP630 X0 41 8 1 3 Assignment TCP6302X1 42 8 1 4 J14 Assignm
6. 16 3 2 7 Interrupt Status Register ISR 0x18 u U U eene eene 17 3 2 8 Positive Edge Interrupt Enable Register PIER 0 1 17 3 2 9 Negative Edge Interrupt Enable Register NIER 0 20 17 3 2 10 RAM Address Map Register 0 24 emen 18 3 2 11 TRAM e tud eee 18 A PCI9030 TARGET CHIP l 19 4 1 PCI Configuration Registers U u u u u u u u J 19 4 1 1 9030 Header ener ihren ensi nnns nnne nnns 19 4 1 2 PCI Base Address Initialization U U enn n eene 20 4 2 Local Configuration Register _ 21 4 3 Contiguration EEPROM 22 4 4 Local Software ss 23 4 9 Local 23 5 FPGA PROGRAMMING HINTS J 24 5 1 FPGA DESI pec 24 5 2 FPGA Pin Assignment 24 5 2 1 Pin Assignment of Local Bus Control Signals 24 5 2 2 Pin Assignment of Local Bus Data Signals
7. 2 6 Pin Assignment of Output Lines TEWS S TECHNOLOGIES Signal Pin Signal Pin FPGA OUT 0 E2 FPGA OUT32 B19 FPGA OUT 1 E3 FPGA OUT33 614 FPGA OUT 2 B5 FPGA OUT34 C17 FPGA OUT 3 B3 FPGA OUT35 014 FPGA OUT 4 A4 FPGA OUT 36 21 FPGA OUT 5 F4 FPGA OUT37 J17 FPGA OUT 6 A6 FPGA OUT38 J19 FPGA OUT 7 C6 FPGA OUT39 20 FPGA OUT 8 A8 FPGA_OUT 40 G5 FPGA OUT 9 B8 FPGA_OUT 41 F9 FPGA OUT 10 010 FPGA_OUT 42 G18 FPGA OUT 11 17 FPGA_OUT 43 G20 FPGA OUT 12 A10 FPGA_OUT 44 17 FPGA OUT 13 D8 FPGA_OUT 45 U18 FPGA OUT 14 D13 FPGA OUT 46 019 FPGA OUT 15 D16 FPGA OUT47 K4 FPGA OUT 16 D21 FPGA OUT 48 20 FPGA OUT 17 E15 FPGA OUT 49 FPGA OUT 18 117 FPGA OUT 50 J3 FPGA OUT 19 K17 FPGA OUT 51 18 FPGA OUT20 D9 FPGA OUT 52 Y15 FPGA OUT21 B12 FPGA OUT 53 W14 FPGA OUT22 G21 FPGA OUT 54 AA17 FPGA OUT23 E21 FPGA OUT 55 AB19 FPGA OUT24 22 FPGA OUT 56 Y17 FPGA OUT25 022 FPGA OUT 57 W16 FPGA OUT26 N21 FPGA OUT 58 W17 FPGA OUT27 N22 FPGA OUT 59 Y19 FPGA OUT28 B15 FPGA OUT 60 W8 FPGA OUT29 17 FPGA OUT 61 V8 FPGA OUT30 T21 FPGA OUT 62 V10 FPGA OUT31 T22 FPGA OUT 63 AB14 TCP630 User Manual Issue 1 0 Figure 5 7 Pin Assignment F
8. 46 4 PCI9030 Target Chip 4 1 PCI Configuration Registers PCR 4 1 1 PCI9030 Header TEWS 2 TECHNOLOGIES PCI CFG Write 0 to all unused Reserved bits Initial Values Register writeable Hex Values Address 34 24 23 16 115 8 7 0 0 00 Device ID Vendor ID N 2276 1498 0x04 Status Command Y 0280 0000 0x08 Class Code Revision ID N 118000 00 0x0C BIST Header PCI Latency Cache Line Y 7 0 00 00 00 00 Timer Size 0x10 PCI Base Address 0 for MEM Mapped Config Registers Y FFFFFF80 0x14 PCI Base Address 1 for I O Mapped Config Registers Y FFFFFF81 0x18 PCI Base Address 2 for Local Address Space 0 Y FF000000 0 1 PCI Base Address 3 for Local Address Space 1 Y 00000000 0x20 PCI Base Address 4 for Local Address Space 2 Y 00000000 0x24 PCI Base Address 5 for Local Address Space 3 Y 00000000 0x28 PCI CardBus Information Structure Pointer N 00000000 0 2 Subsystem ID Subsystem Vendor ID N s b 1498 0x30 PCI Base Address for Local Expansion ROM Y 00000000 0x34 Reserved New Cap Ptr N 000000 40 0x38 Reserved N 00000000 0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y 7 0 00 00 01 00 0x40 PM Cap PM Nxt Cap PM Cap ID N 4801 00 01 0x44 PM Data PM CSR EXT PM CSR Y 00 00 0000 0x48 Reserved HS CSR HS Nxt Cap HS Cap ID Y 23 16 0000 00 06 0 4 VPD Address VPD Nxt VPD Cap ID Y 31 16 0
9. 6A 6B lO 7A 10 GND 7B 8A 8B 9A 9A 9 GND 10A IO 10B IO 11A IO 11B IO 12A 8 GND 12B IO 13A IO 13B IO 14 IO 14A 7 GND 15A IO 15B IO 16A IO 16B IO 17A 6 GND 17B IO 18A IO 18B IO 19A IO 19A 5 GND 20A IO 20B IO 21 IO 21B IO 22 4 GND 22B IO 23 IO 23B IO 24 IO 24A 3 GND 25A IO 25 IO 26A IO 26B IO 27 2 GND 27B IO 28A IO 28B IO 29A IO 29A 1 GND 30A IO 30B IO 31A IO 31B TCP630 User Manual Issue 1 0 Figure 8 7 Pin Assignment 2 I O Connector TCP630 21 Page 45 of 46 8 2 3 Backl O Assignment TCP630 22 TEWS 2 TECHNOLOGIES Pos F E D C B A 22 GND not used not used not used not used not used 21 GND not used not used not used not used not used 20 GND not used not used not used not used not used 19 GND not used not used not used not used not used 18 GND not used not used not used not used not used 17 GND not used not used not used not used not used 16 GND not used not used not used not used not used 15 GND not used not used not used not used not used 14 GND 5V 5V 3 3V 3 3V 3 3V 13 GND 0 IO_0B 1A 1B 2A 12 GND 2B 3A 3B 4A 4A 11 GND 10 5A 5
10. O NI O O Figure 3 7 Output Enable Register 0 OE REGO TCP630 10 Output Enable Bits 0 31 control Output 0 Output 31 TTL TCP630 11 Output Enable Bits 0 31 control Output 0 Output 31 Differential TCP630 12 Output Enable Bits 0 15 control Output 0 Output 15 Differential Output Enable Bits 16 31 are not used TCP630 User Manual Issue 1 0 Page 15 of 46 TEWS S TECHNOLOGIES 3 2 6 Output Enable Register 1 OE REG 1 0x14 Bit Symbol Description Access Reset Value 63 OE REG BIT 63 62 OE REG BIT 62 61 OE REG BIT 61 60 OE REG BIT 60 59 OE REG BIT 59 58 OE REG BIT 58 57 OE REG BIT 57 56 OE REG BIT 56 55 OE REG BIT 55 54 OE REG BIT 54 53 OE REG BIT 53 52 OE REG BIT 52 51 OE REG BIT 51 50 OE REG BIT 50 49 OE REG BIT 49 Output Enable Bit 63 32 48 OE REG BIT 48 see notes below 47 OE REG BIT 47 0 disables the output transceiver 46 OE REG 46 1 enables the output transceiver 45 OE REG BIT 45 44 OE REG BIT 44 43 OE REG BIT 43 42 OE REG BIT 42 41 OE REG BIT 41 40 OE REG BIT 40 39 OE REG BIT 39 38 OE REG BIT 38 37 OE REG BIT 37 36 OE REG BIT 36 35 OE REG BIT 35 34 OE REG BIT 34 33 OE REG BIT 33 32 OE REG BIT 32 R W 0 Figure 3 8 Output Enable Register 1 OE REG1 TCP630 10 Output Enable Bits 32 63 control Output 32 Output 63 TTL
11. TCP630 11 Output Enable Bits 32 63 are not used TCP630 12 Output Enable Bits 32 63 control Output 32 Output 63 TTL TCP630 User Manual Issue 1 0 Page 16 of 46 3 2 7 Interrupt Status Register ISR 0x18 TEWS S TECHNOLOGIES Bit Symbol Description Access Reset Value 31 8 Reserved 0 for reads 0 7 INT 7 6 INT 6 Line 7 0 Interrupt Request Status 5 INT 5 The Interrupt Status Register signals the lines on which an interrupt event 4 INT 4 occurred The example design supports R W 0 3 INT_3 interrupts only for line 0 to 7 2 INT_2 0 no active interrupt request 1 INT 1 1 7 active interrupt request 0 INT 0 Figure 3 9 Interrupt Status Register ISR 3 2 8 Positive Edge Interrupt Enable Register PIER 0x1C Bit Symbol Description Access Reset Value 31 8 Reserved 0 for reads 0 7 PIE 7 PIE 6 PIE 5 PIE 4 Line 7 0 Rising Edge Interrupt Enable 0 disabled PIE 3 1 enabled PIE 2 PIE 1 O NI O R W Figure 3 10 Positive Edge Interrupt Enable Register PIER 3 2 9 Negative Edge Interrupt Enable Register NIER 0x20 Bit Symbol Description Access Reset Value 31 8 Reserved 0 for reads 0 7 NIE 7 6 5 4 Line 7 0 Falling Edge Interrupt Enable 0 disabled N
12. scale Figure 4 3 PCI9030 Local Configuration Register TCP630 User Manual Issue 1 0 Page 21 of 46 TEWS S TECHNOLOGIES 4 3 Configuration EEPROM After power on or PCI reset the PCI9030 loads initial configuration register data from the on board configuration EEPROM The configuration EEPROM contains the following configuration data Address 0x00 to 0x27 PCI9030 PCI Configuration Register Values Address 0x28 to 0x87 PCI9030 Local Configuration Register Values e Address 0x88 to OxFF Reserved See the PCI9030 Manual for more information The following table shows the default content of the EEPROM Address Offset 0x00 0x02 0x04 0x06 0x08 0 0 0 00 0 0276 0 1498 0 0280 0 0000 0x1180 0 0000 8 0 0 10 0 0000 0x0040 0x0000 0x4801 0x0001 0x0000 0 0000 0 20 0x0000 0 0006 0 0000 0 0003 0x0000 0x0000 0 30 0 40 0 50 0 60 0 70 0 80 0x0000 0 0000 0x0000 0x0000 OxFFFF OxFFFF OxFFFF OxFFFF 0x90 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxBO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF 0 0 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxDO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxEO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxF
13. the SRAM as it is done at power up The CLK1 output of the CY27EE16 must never be switched off Off or Hi Z and the frequency has to be within 0 60 MHz When the local clock is switched off the PCI9030 will not work and the CY27EE16 can t be reprogrammed any more The board would have to be sent to the manufacturer for repair A detailed register description and the exact programming timing can be found in the datasheet of the CY27EE16 This is part of the TCP630 ED Engineering Documentation and is also available at www cypress com as well as the CyberClocks software tool which helps calculating the register values The drivers available from TEWS TECHNOLOGIES provide routines for easy setting of the CY27EE16 registers 6 2 1 Default Clock Programming Description Default values CLK1 Output of Clock Generator 50 MHz CLK2 Output of Clock Generator 20 MHz CLK3 Output of Clock Generator 10 MHz CLK4 Output of Clock Generator 1 MHz CLK5 Output of Clock Generator 200 kHz CLK6 Output of Clock Generator Off Figure 6 2 Default values of clock outputs at delivery TCP630 User Manual Issue 1 0 Page 32 of 46 Offset Description Default values 0x09 CLKOE control 0x6F 0x0C DIV1SRC mux and DIV1N divider 0x64 0x10 Input Pin Control Registers 0x50 0x11 Write Protect Registers 0x04 0x12 Input crystal oscillator drive control 0x20 0x13 Inpu
14. transceiver and a 1200 termination resistor See the following figure for more information of the differential I O circuitry MAX3078bE FPGA OUTx FPGA OEx 120R 1 Differential Line RENY X1 P14 FPGA Figure 7 3 Differential I O Interface TCP630 User Manual Issue 1 0 Page 35 of 46 TEWS S TECHNOLOGIES 7 3 Back I O Configuration The configuration of J2 Back I O connector lines 57 64 be changed to ground instead of port 7 signals by change of zero ohm resistors For removing mounting zero ohm resistors work on a grounded static free work surface 12 Figure 7 4 Jumper positions for ground option Back I O Line Signal Jumper Position 57 ground R70 56 10 28 default R72 58 ground R66 57 IO_28B default R67 59 ground R74 _58 IO 29A default R76 60 ground R71 1 59 IO_29B default R73 61 ground R78 60 IO 30A default R80 62 ground R75 61 1O 30B default R77 63 ground R82 0_62 IO_31A default R83 64 ground R79 63 1O 31B default R81 Figure 7 5 Jumper positions for Back options Caution Never make simultaneous connections on both jumper positions of one 1 line Serious damage of the module is possible TCP630 User Manual Issue 1 0 Page 36 of 46 7 4 FPGA Debug Connector The FPGA debug connector X2 is not populated
15. 0 19 IN REG BIT 19 18 IN REG BIT 18 17 IN REG BIT 17 16 IN REG 16 Input Port Bit 31 0 Data Read directly from the 1 lines 31 to 0 R m see notes below 14 IN_REG_BIT_14 13 IN_REG_BIT_13 12 IN REG BIT 12 11 IN REG BIT 11 10 IN REG BIT 10 9 IN REG BIT 9 8 IN REG BIT 8 7 IN REG BIT 7 6 IN REG BIT 6 5 IN REG BIT 5 4 IN REG BIT 4 3 IN REG BIT 3 2 IN REG BIT 2 1 IN REG BIT 1 0 IN REG 0 Figure 3 5 Input Register 0 IN REGO TCP630 10 Input Port Bits 0 31 are read from IO 0 IO 31 TTL TCP630 11 Input Port Bits 0 31 are read from IO 0 IO 31A B Differential TCP630 12 Input Port Bits 0 15 are read from IO 0 IO 15A B Differential Input Port Bits 16 31 are not used TCP630 User Manual Issue 1 0 Page 13 of 46 TEWS S TECHNOLOGIES 3 2 4 Input Register 1 IN REG1 0 0 Bit Symbol Description Access Reset Value 63 IN REG BIT 63 62 IN REG BIT 62 61 IN REG BIT 61 60 IN REG BIT 60 59 IN REG BIT 59 58 IN REG BIT 58 57 IN REG BIT 57 56 IN REG BIT 56 55 IN REG BIT 55 54 IN REG 54 53 IN REG BIT 53 52 IN REG BIT 52 51 IN REG BIT 51 50 IN REG BIT 50 49 IN REG BIT 49 48 IN REG BIT 48 Input Port Bit 63 32 Data Read directly from the 1 lines 63 to 32 R gs RES BITE see notes below 4
16. 000 00 03 0x50 VPD Data Y 00000000 Subsystem ID Value Offset 0x2E TCP630 10 Figure 4 1 Default PCI9030 Header TCP630 User Manual Issue 1 0 0x200A TCP630 11 0x200B TCP630 12 0x200C TCP630 20 0x2014 TCP630 21 0x2015 TCP630 22 0x2016 Page 19 of 46 TEWS S TECHNOLOGIES 4 1 2 PCI Base Address Initialization PCI Base Address Initialization is scope of the PCI host software PCI9030 PCI Base Address Initialization 1 Write OxFFFF_FFFF to the PCI9030 PCI Base Address Register 2 Read back the PCI9030 PCI Base Address Register 3 For PCI Base Address Registers 0 5 check bit 0 for PCI Address Space Bit 0 requires PCI Memory Space mapping Bit 1 requires PCI I O Space mapping For the PCI Expansion ROM Base Address Register check bit 0 for usage Bit 0 Expansion ROM not used Bit 1 Expansion ROM used 4 For PCI I O Space mapping starting at bit location 2 the first bit set determines the size of the required PCI I O Space size For PCI Memory Space mapping starting at bit location 4 the first bit set to 1 determines the size of the required PCI Memory Space size For PCI Expansion ROM mapping starting at bit location 11 the first bit set to 1 determines the required PCI Expansion ROM size For example if bit 5 of a Base Address Register is detected as the first bit set to 1 the PCI9030 is requesting a 32 byte space address bits 4 0 are not part of base address de
17. 3 3V 13 GND 0 1 2 3 4 12 GND 5 6 lO 7 10 8 9 11 GND 10 11 12 13 14 10 GND 15 16 17 18 19 9 GND 20 21 22 23 24 8 GND 10 25 26 27 28 29 7 GND 30 31 32 33 34 6 GND 35 36 37 38 39 5 GND 40 41 42 43 44 4 GND 10 45 46 47 48 49 3 GND 50 51 52 53 54 2 GND 10 55 56 57 58 59 1 GND 60 61 62 63 TCP630 User Manual Issue 1 0 Figure 8 6 Pin Assignment 2 I O Connector TCP630 20 Page 44 of 46 8 2 2 Backl O Assignment TCP630 21 TEWS 2 TECHNOLOGIES Pos F E D C B A 22 GND not used not used not used not used not used 21 GND not used not used not used not used not used 20 GND not used not used not used not used not used 19 GND not used not used not used not used not used 18 GND not used not used not used not used not used 17 GND not used not used not used not used not used 16 GND not used not used not used not used not used 15 GND not used not used not used not used not used 14 GND 5V 5V 3 3V 3 3V 3 3V 13 GND 0 IO_0B 1A 1B 2A 12 GND 2B 3A 3B 4A 4A 11 GND 10 5A 5B 10
18. 6 8 1 2 414 Assignment TCP630 x0 TEWS S TECHNOLOGIES Pin Signal Level 0 Pin Signal Level 2 1 TTL e m s or TTL TTL o os m TTL Figure 8 3 Pin Assignment J14 Connector TCP630 x0 TCP630 User Manual Issue 1 0 Page 41 of 46 8 1 3 414 Assignment TCP630 x1 TEWS S TECHNOLOGIES 63 31A Pin Signal Level 0A Diff Diff e ow s oa 2985 Figure 8 4 Pin Assignment J14 Connector TCP630 x1 TCP630 User Manual Issue 1 0 Page 42 of 46 8 1 4 414 Assignment TCP630 x2 TEWS S TECHNOLOGIES Pin Signal Level Diff e ow s oa os Figure 8 5 Pin Assignment J14 Connector TCP630 x2 TCP630 User Manual Issue 1 0 Page 43 of 46 8 2 Back 2 Connector 8 2 1 Back I O Assignment TCP630 20 TEWS S TECHNOLOGIES Pos F E D C B A 22 GND not used not used not used not used not used 21 GND not used not used not used not used not used 20 GND not used not used not used not used not used 19 GND not used not used not used not used not used 18 GND not used not used not used not used not used 17 GND not used not used not used not used not used 16 GND not used not used not used not used not used 15 GND not used not used not used not used not used 14 GND 5V 5V 3 3V 3 3V
19. 6 IN REG BIT 46 45 IN REG BIT 45 44 IN REG BIT 44 43 IN REG BIT 43 42 IN REG BIT 42 41 IN REG BIT 41 40 IN REG BIT 40 39 IN REG BIT 39 38 IN REG BIT 38 37 IN REG BIT 37 36 IN REG BIT 36 35 IN REG BIT 35 34 IN REG BIT 34 33 IN REG BIT 33 32 IN REG BIT 32 Figure 3 6 Input Register 1 IN REG1 TCP630 10 Input Port Bits 32 63 are read from 32 63 TTL TCP630 11 Input Port Bits 32 63 are not used TCP630 12 Input Port Bits 32 63 are read from IO 32 IO 63 TTL TCP630 User Manual Issue 1 0 Page 14 of 46 TEWS S TECHNOLOGIES 3 2 5 Output Enable Register 0 OE REGO 0x10 Bit Symbol Description Access Reset Value 31 OE REG BIT 31 30 OE REG BIT 30 29 OE REG BIT 29 28 OE REG BIT 28 27 OE REG BIT 27 26 OE REG BIT 26 25 OE REG BIT 25 24 OE REG BIT 24 23 OE REG BIT 23 22 OE REG BIT 22 21 OE REG BIT 21 20 OE REG BIT 20 19 OE REG BIT 19 18 OE REG BIT 18 17 OE REG BIT 17 Output Enable Bit 31 0 16 OE REG 16 see notes below 15 OE REG BIT 15 0 disables the output transceiver 14 OE REG 14 1 enables the output transceiver 13 OE REG BIT 13 12 OE REG BIT 12 11 OE REG BIT 11 10 OE REG BIT 10 OE REG BIT 9 OE REG BIT 8 OE REG BIT 7 OE REG BIT 6 OE REG BIT 5 OE REG BIT 4 OE REG BIT 3 OE REG BIT 2 OE REG BIT 1 OE REG BIT 0 R W 0
20. 62 OUT REG BIT 62 61 OUT REG BIT 61 60 OUT REG BIT 60 59 OUT REG BIT 59 58 OUT REG BIT 58 57 OUT REG BIT 57 56 OUT REG BIT 56 55 OUT REG BIT 55 54 OUT REG BIT 54 53 OUT REG BIT 53 52 OUT REG BIT 52 51 OUT REG BIT 51 50 OUT REG BIT 50 49 OUT REG BIT 49 48 OUT REG 48 Output Port Bit 63 32 Data 47 OUT REG BIT 47 see notes below 46 OUT REG BIT 46 45 OUT REG BIT 45 44 OUT REG BIT 44 43 OUT REG BIT 43 42 OUT REG BIT 42 41 OUT REG BIT 41 40 OUT REG BIT 40 39 OUT REG BIT 39 38 OUT REG BIT 38 37 OUT REG BIT 37 36 OUT REG BIT 36 35 OUT REG BIT 35 34 OUT REG BIT 34 33 OUT REG BIT 33 32 OUT REG BIT 32 R W 0 Figure 3 4 Output Register 1 OUT_REG1 TCP630 10 Output Port Bits 32 63 are written to IO_32 IO 63 TTL TCP630 11 Output Port Bits 32 63 are not used TCP630 12 Output Port Bits 32 63 are written to 32 IO 63 TTL TCP630 User Manual Issue 1 0 Page 12 of 46 TEWS S TECHNOLOGIES 3 2 3 Input Register 0 IN REGO 0x08 Bit Symbol Description Access Reset Value 31 IN REG BIT 31 30 IN REG BIT 30 29 IN REG BIT 29 28 IN REG BIT 28 27 IN REG BIT 27 26 IN REG BIT 26 25 IN REG BIT 25 24 IN REG BIT 24 23 IN REG BIT 23 22 IN REG BIT 22 21 IN REG BIT 21 20 IN REG BIT 2
21. B 10 6A 6B lO 7A 10 GND 7B 8A 8B 9A 9A 9 GND 10A IO 10B IO 11A IO 11B IO 12A 8 GND 12B IO 13A IO 13B IO 14 IO 14A 7 GND 15A IO 15B 32 33 34 6 GND 35 36 37 38 39 5 GND 10 40 41 42 43 44 4 GND 45 46 47 48 49 3 GND 50 51 52 53 54 2 GND 10 55 56 57 58 59 1 GND 60 61 62 63 TCP630 User Manual Issue 1 0 Figure 8 8 Pin Assignment 2 I O Connector TCP630 22 Page 46 of 46
22. Endian Byte 0 AD 7 0 Byte 1 AD 15 8 Byte 2 AD 23 16 Byte 3 AD 31 24 Big Endian Little Endian 32 Bit 32 Bit Byte 07 0 Bye 1 0116 8 Byte 2 0023 16 Bytes 0131 24 16 16 Bit Byte 0 070 Bye 1 015 8 16 Bit lower lane 8 Bit upper lane 8 Bit Byte 0 or 8 Bit lower lane bo DIT 0 Figure 6 1 Local Bus Little Big Endian TCP630 User Manual Issue 1 0 TEWS S TECHNOLOGIES Every Local Address Space 0 3 and the Expansion ROM Space can be programmed to operate in Big or Little Endian Mode Page 30 of 46 TEWS S TECHNOLOGIES Standard use of the TCP630 example design Local Address Space 0 Local Address Space 1 Local Address Space 2 Local Address Space 3 Expansion ROM Space 32 bit bus in Big Endian Mode not used not used not used not used To change the Endian Mode use the Local Configuration Registers for the corresponding Space Bit 24 of the according register sets the mode A value of 1 indicates Big Endian and a value of 0 indicates Little Endian For further information please refer to the PCI9030 manual which is also part of the TCP630 ED Engineering Documentation Use the PCI Base Address 0 Offset or PCI Base Address 1 Offset Short cut LASOBRD LAS1BRD LAS2BRD LAS3BRD EROMBRD Offset Name 0x28 Local Address Space 0 Bus Region Description Register Ox2C Local Address Space 0 Bus Region Descriptio
23. FFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF 0x0000 0x0000 0x0000 0x0000 Figure 4 4 Configuration EEPROM TCP630 Subsystem ID Value Offset 0 0 TCP630 10 0x000A TCP630 11 0x000B TCP630 12 0x000C TCP630 20 0x0014 TCP630 21 0x0015 TCP630 22 0x0016 Highlighted values can be modified by the driver software TCP630 User Manual Issue 1 0 Page 22 of 46 TEWS S TECHNOLOGIES 4 4 Local Software Reset The PCI9030 Local Reset Output LRESETo is used to reset the on board local logic The PCI9030 local reset is active during PCI reset or if the PCI Adapter Software Reset bit is set in the PCI9030 local configuration register CNTRL offset 0x50 30 PCI Adapter Software Reset Value of 1 resets the PCI9030 and issues a reset to the Local Bus LRESETo asserted The PCI9030 remains in this reset condition until the PCI Host clears this bit The contents of the PCI9030 PCI and Local Configuration Registers are not reset The PCI9030 PCI Interface is not reset 4 5 Local Bus The PCI9030 Local Bus is a 32 bit non multiplexed bus Many parameters of the local interface can be configured such as wait states delays etc see PCI9030 Data Book The default values of the Local Address Space 0 Bus Region Descriptor LASOBRD 0x28 for the example design are Bit RE Description Local Address Space 0 Burst Enable 0 Bursting dis
24. IE 3 1 enabled NIE 2 NIE 1 NI O 011 NIE 0 R W TCP630 User Manual Issue 1 0 Figure 3 11 Negative Edge Interrupt Enable Register NIER Page 17 of 46 TEWS S TECHNOLOGIES 3 2 10 RAM Address Map Register RAMR 0x24 The RAM Address Map Register determines at which address the 256 x 32 bit RAM space begins within the 16 MByte address space If RAMR is set to 0x0 the addresses from 0 0 to 0x24 occupied by the registers Only 32 bit accesses are possible Bit Symbol Description Access Reset Value 31 24 Reserved 0 for reads 0 23 RAM ADD MAP BIT 23 0 22 RAM ADD MAP BIT 22 0 21 RAM ADD MAP BIT 21 0 20 RAM ADD MAP BIT 20 0 19 RAM ADD MAP BIT 19 0 18 RAM ADD MAP BIT 18 0 17 RAM ADD MAP BIT 17 0 Address Map Bit 23 10 R W 16 RAM_ADD_MAP_BIT_16 0 15 RAM_ADD_MAP_BIT_15 0 14 RAM_ADD_MAP_BIT_14 0 13 RAM ADD MAP 13 0 12 RAM ADD MAP BIT 12 0 11 RAM ADD MAP BIT 11 0 10 RAM ADD MAP BIT 10 1 9 0 Reserved 0 for reads 0 Figure 3 12 Address Map Register RAMR 3 2 11 RAM Space There is a 256 x 32 bit RAM space available it is accessed if the address bits match to the content of the RAM Address Map Register see description of RAMR Only 32 bit accesses are possible TCP630 User Manual Issue 1 0 Page 18 of
25. MENT FPGA OUTPUT eee ee tener rae eras etcetera nnne nnne 28 PIN ASSIGNMENT FPGA OUTPUT ENABLE LINES esse 29 LOCAL BUS LITTLE BIG enm een een rennen nennen terrens 30 DEFAULT VALUES OF CLOCK OUTPUTS 32 DEFAULT REGISTER VALUES AT 33 PULL UP VOLTAGE JUMPER SETTING 4 34 TTEJ OINTEREFAQGE interi aee 35 DIFFERENTIAL VO INTERFACE 35 JUMPER POSITIONS FOR GROUND OPTION naa 36 JUMPER POSITIONS FOR BACK I O OPTIONS ene enne ener 36 DEBUG CONNECTOR BOTTOM VIEW 37 DEBUG CONNECTOR sese eene 37 A PIMMODULE uuu rettet iecit tu etae iq teas Eta dax 38 CONNECTOR POSITIONS etre tfe rre entere diceret dre rente e e 39 PIN ASSIGNMENT J10 40 Page 6 of 46 TEWS S TECHNOLOGIES FIGURE 8 3 PIN ASSIGNMENT J14 CONNECTOR 6 0 41 FIGURE 8 4 PIN ASSIGNMENT J14 CONNECTOR TCP630 X1 u rennes 42 FIGURE 8 5 PIN ASSIGNMENT J14 CONNECTOR 2
26. PGA Output Lines Page 28 of 46 TEWS S TECHNOLOGIES 5 2 7 Pin Assignment of FPGA Output Enable Lines Signal Pin Signal Pin FPGA OE 0 D1 FPGA OE 32 B18 FPGA OE 1 A3 FPGA OE 33 C13 FPGA OE 2 A5 FPGA OE 34 C16 FPGA OE 3 F2 FPGA OE 35 D12 FPGA OE 4 F3 FPGA OE 36 K18 FPGA OE 5 B4 FPGA OE 37 G4 FPGA OE 6 D5 FPGA OE 38 J18 FPGA OE 7 B6 FPGA OE 39 F20 FPGA OE 8 C7 FPGA_OE 40 J21 FPGA_OE 9 D7 FPGA_OE 41 H18 FPGA_OE 10 B13 FPGA_OE 42 F10 FPGA_OE 11 A16 FPGA_OE 43 G19 FPGA_OE 12 B9 FPGA OE 44 W18 FPGA OE 13 E7 FPGA OE 45 V19 FPGA OE 14 C18 FPGA OE 46 K6 FPGA OE 15 E8 FPGA OE 47 P19 FPGA OE 16 E12 FPGA OE 48 T19 FPGA OE 17 E14 FPGA OE 49 R18 FPGA OE 18 J6 FPGA OE 50 P17 FPGA OE 19 L21 FPGA OE 51 N20 FPGA OE 20 C10 FPGA OE 52 V13 FPGA OE 21 A13 FPGA OE 53 AA16 FPGA OE 22 H21 FPGA OE 54 Y18 FPGA OE 23 F21 FPGA OE 55 AA20 FPGA OE 24 H22 FPGA OE 56 V14 FPGA OE 25 E22 FPGA OE 57 AA19 FPGA OE 26 P21 FPGA OE 58 M6 FPGA OE 27 M21 FPGA OE 59 L5 FPGA OE 28 A19 FPGA OE 60 R5 FPGA OE 29 B16 FPGA OE 61 W13 FPGA OE 30 P20 FPGA OE 62 Y14 FPGA OE 31 U22 FPGA OE 63 AA15 Figure 5 8 Pin Assignment FPGA Output Enable Lines TCP630 User Manual Issue 1 0 Page 29 of 46 6 Configuration Hints 6 1 Big Little Endian PCI Bus Little
27. TEWS lt The Embedded I O Company TECHNOLOGIES TCP630 Reconfigurable FPGA with 64 TTL I O 32 Differential I O Lines Version 1 0 User Manual Issue 1 0 November 2006 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 Phone 49 0 4101 4058 0 9190 Double Diamond Parkway Phone 1 775 850 5830 25469 Halstenbek Germany Fax 49 0 4101 4058 19 Suite 127 Reno NV 89521 USA Fax 1 775 201 0347 www tews com e mail info tews com www tews com e mail usasales tews com TCP630 10 64 TTL I O Lines TCP630 11 32 Differential 1 Lines TCP630 12 32 TTL I O and 16 Differential I O Lines TCP630 20 64 TTL I O Lines J2 I O TCP630 21 32 Differential Lines J2 TCP630 22 32 TTL I O and 16 Differential I O Lines J2 TCP630 User Manual Issue 1 0 TEWS lt TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e Ox029E that means hexadecimal value 029E For signals
28. abled Local Address Space 0 READY Input Enable 0 READY input disabled Local Address Space 0 BTERM Input Enable 0 input disabled Prefetch Count 00 Do not prefetch disable Prefetch Counter Enable 1 Set to 1 disabled by Prefetch Count 0 NRAD Wait States 00010 Read Address to Data wait states NRDD Wait States 00 Read Data to Data wait states NXDA Wait States 01 Read Write Data to Address wait states NWAD Wait States 00010 Write Address to Data wait states NWDD Wait States 00 Write Data to Data wait states Local Address Space 0 Local Bus Width 10 32 bit bus width Byte Ordering 1 Big Endian Big Endian Byte Lane Mode 0 Use lanes 15 0 7 0 in non 32 bit modes Read Strobe Delay 01 Delay until assertion of RD Write Strobe Delay 01 Delay until assertion of WR Write Cycle Hold 00 Hold data after Figure 4 5 Default values of Space 0 Region Descriptor TCP630 User Manual Issue 1 0 Page 23 of 46 5 FPGA Programming Hints 5 1 FPGA Design Custom FPGA designs can be developed using a commercial version like Xilinx ISE Foundation or the ISE WebPACK downloadable free of charge at www xilinx com ise Taking the VHDL example provided with the Engineering Documentation would be a good basis After implementing the logic the resulting xsvf file can be downloaded to the configuration flash by the driver A detailed description of the example files and how to generate the configuration bit stream file is part of the Engineering Doc
29. by default It lets the user directly connect JTAG interface cable to the JTAG pins of the FPGA for readback and real time debugging of the FPGA design using Xilinx ChipScope The Platform Flash is not part of this JTAG chain it is only programmable via the PCI9030 GPIO TEWS S TECHNOLOGIES A through hole vertical connector with 7 x 2 pins and 2 mm pitch e g Molex 87831 1420 or others can be mounted Pin 1 is marked by a squared pad see next figure The connector pinning is compatible for the Xilinx cables e g Parallel Cable IV or others D 1 Figure 7 6 Debug Connector Bottom View Short Description 1 3 5 7 9 11 13 GND Digital Ground 2 VREF Target Reference Voltage 3 3V 4 TMS Test Mode Select 6 TCK Test Clock 8 TDO Test Data Out 10 TDI Test Data In 12 14 TCP630 User Manual Issue 1 0 Figure 7 Debug Connector Pinout Page 37 of 46 TEWS TECHNOLOGIES 7 5 PIM Module Slot Instead of a front I O Connector the TCP630 offers a PIM module slot This allows a wide range of connectors to be used with the TCP630 and special 1 solutions can be easily applied with the TCP630 The standard is described in Module Standard Vita 36 available at www vita com A PIM module is a 74mm x 69mm module with a PMC bezel and two EIA E700 AAAB connectors as on PMCs One of these conne
30. coding 5 Determine the base address and write the base address to the PCI9030 PCI Base Address Register For PCI Memory Space mapping the mapped address region must comply with the definition of bits 3 1 of the PCI9030 PCI Base Address Register After programming the PCI9030 PCI Base Address Registers the software must enable the PCI9030 for PCI and or PCI Memory Space access in the PCI9030 PCI Command Register Offset 0x04 To enable PCI I O Space access to the PCI9030 set bit 0 to 1 To enable PCI Memory Space access to the PCI9030 set bit 1 to 1 Offset in Config Description Usage 0x10 PCI9030 LCR s MEM Used 0x14 PCI9030 LCR s I O Used 0x18 PCI9030 Local Space 0 Used 0 1 PCI9030 Local Space 1 Not used 0x30 Expansion ROM Not used Figure 4 2 PCI9030 PCI Base Address Usage TCP630 User Manual Issue 1 0 Page 20 of 46 TEWS S TECHNOLOGIES 4 2 Local Configuration Register LCR After reset the PCI9030 Local Configuration Registers are loaded from the on board serial configuration EEPROM The PCI base address for the PCI9030 Local Configuration Registers is PCI9030 PCI Base Address 0 PCI Memory Space Offset 0x10 in the PCI9030 PCI Configuration Register Space or PCI9030 PCI Base Address 1 PCI Space Offset 0x14 in the PCI9030 PCI Configuration Register Space Please be very careful when changing any hardware dependent bit settings in the PCI9030 Local Configurat
31. ctors provides the power supply 3 3V 5V amp 12V for the PIM module the other connector provides the 1 signals to the host board Figure 7 8 A PIM Module The PIM module can adapt the TCP630 to various 1 standards either mechanical connector or electrical A collection of PIM modules with standard 1 connectors are available from TEWS Example A TPIMOOS with an HD68 connector would offer all 64 FPGA I O lines at the connector with a pin assignment that is compatible to a TPMC630 TCP630 User Manual Issue 1 0 Page 38 of 46 TEWS lt gt TECHNOLOGIES 8 Pin Assignment l O Connector The TCP630 does not provide a direct front panel I O but it offers a PIM module slot This allows very versatile I O solutions with a wide range of connectors The TCP630 2x also offer rear I O via the J2 connector 1 OH Figure 8 1 Connector Positions TCP630 User Manual Issue 1 0 Page 39 of 46 TEWS S TECHNOLOGIES 8 1 PIM Slot Connectors 8 1 1 10 Assignment e Ca o T lt O zit Co R O z 9 N 46 1 O 01 1 a a C 8 N AINJ O Figure 8 2 Pin Assignment 10 Connector TCP630 User Manual Issue 1 0 Page 40 of 4
32. e JTAG header for readback and real time debugging of the FPGA design using Xilinx ChipScope A programmable clock generator provides up to six different clock output frequencies between 200 kHz and 166 MHz All outputs are available at the FPGA one clock source is in addition used as the local clock signal for the PCI controller The clock generator settings are stored in an EEPROM and can be changed by the driver software through the PCI Target Controller The configuration EEPROM of the PCI Target Controller can also be modified by the driver software to adapt address spaces etc User applications can be developed using the design software 5 WebPACK which can be downloaded free of charge from www xilinx com The TCP630 does not provide a direct front panel 1 but it offers a PIM module slot This allows very versatile 1 solutions with a wide range of connectors The TCP630 2x also offer rear 1 via the J2 connector For First Time Users the Engineering Documentation is recommended it includes schematics data sheets of the components and well documented sample VHDL source code Program Serial Flash Clocks PIM Slot O CGE jn Figure 1 1 Block Diagram TCP630 User Manual Issue 1 0 Page 8 of 46 TEWS S TECHNOLOGIES 2 Technical Specification PMC Interface Mechanical Interface Standard 30 32 CompactPCI module confor
33. ent TCP0630 X2 verd eade 43 8 2 Back 42 Connector u eise u uu uu u u u J 44 8 2 1 Back Assignment 30 20 44 8 2 2 Back I O Assignment 630 21 nnne nnne 45 8 2 3 Back Assignment 630 22 46 TCP630 User Manual Issue 1 0 Page 5 of 46 FIGURE 1 1 FIGURE 2 1 FIGURE 3 1 FIGURE 3 2 FIGURE 3 3 FIGURE 3 4 FIGURE 3 5 FIGURE 3 6 FIGURE 3 7 FIGURE 3 8 FIGURE 3 9 FIGURE 3 10 FIGURE 3 11 FIGURE 3 12 FIGURE 4 1 FIGURE 4 2 FIGURE 4 3 FIGURE 4 4 FIGURE 4 5 FIGURE 5 1 FIGURE 5 2 FIGURE 5 3 FIGURE 5 4 FIGURE 5 5 FIGURE 5 6 FIGURE 5 7 FIGURE 5 8 FIGURE 6 1 FIGURE 6 2 FIGURE 6 3 FIGURE 7 1 FIGURE 7 2 FIGURE 7 3 FIGURE 7 4 FIGURE 7 5 FIGURE 7 6 FIGURE 7 7 FIGURE 7 8 FIGURE 8 1 FIGURE 8 2 TCP630 User Manual Issue 1 0 TEWS lt gt TECHNOLOGIES Table of Figures DIAGRAM RR 8 TECHNICAL SPECIFICATION 9 PCI9030 LOCAL SPACE I n n nana 10 FPGA EXAMPLE DESIGN REGISTER SPACE sese 10 OUTPUT REGISTER 0 OQUT_REG0
34. ion Registers Offset from Register Default Value Description PCI Base Address 0x00 Local Address Space 0 Range 0000 Defines size of space 0x04 Local Address Space 1 Range 0 0000 0000 0 08 Local Address Space 2 Range 0 0000 0000 0 0 Local Address Space 3 Range 0x0000_0000 0x10 Local Exp ROM Range 0x0000_0000 0x14 Local Re map Register Space 0 0x0000 0001 Defines local address of space 0x18 Local Re map Register Space 1 0x0000_0000 0x1C Local Re map Register Space 2 0 0000 0000 0x20 Local Re map Register Space 3 0 0000 0000 0x24 Local Re map Register ROM 0x0000_0000 0x28 Local Address Space 0 Descriptor 0x1581_20A0 Defines properties of space 0 2 Local Address Space 1 Descriptor 0x0000 0000 0x30 Local Address Space 2 Descriptor 0x0000 0000 0x34 Local Address Space 3 Descriptor 0 0000 0000 0x38 Local Exp ROM Descriptor 0x0000_0000 0 3 Chip Select 0 Base Address 0x0080 0001 Defines range for Chip Select 0x40 Chip Select 1 Base Address 0x0000 0002 0x44 Chip Select 2 Base Address 0x0000_0002 0x48 Chip Select 3 Base Address 0x0000_0002 0 4 Interrupt Control Status 0x0041 0 4 EEPROM Write Protect Boundary 0x0030 0x50 Miscellaneous Control Register 0x0078 0000 0x54 General Purpose 1 Control 0x0000 0240 0x70 Hidden1 Power Management data 0 0000 0000 select Ox74 Hidden 2 Power Management data 0x0000 0000
35. le Design Register Space TCP630 User Manual Issue 1 0 Page 10 of 46 TEWS S TECHNOLOGIES 3 2 1 Output Register 0 OUT REGO0 0x00 Bit Symbol Description Access Reset Value 31 OUT REG BIT 31 30 OUT REG BIT 30 29 OUT REG BIT 29 28 OUT REG BIT 28 27 OUT REG BIT 27 26 OUT REG BIT 26 25 OUT REG BIT 25 24 OUT REG BIT 24 23 OUT REG BIT 23 22 OUT REG BIT 22 21 OUT REG BIT 21 20 OUT REG BIT 20 19 OUT REG BIT 19 18 OUT REG BIT 18 17 OUT REG BIT 17 16 OUT REG BIT 16 Output Port Bit 31 0 Data 15 OUT REG 15 see notes below 14 OUT REG BIT 14 13 OUT REG BIT 13 12 OUT REG BIT 12 11 OUT REG BIT 11 10 OUT REG BIT 10 OUT REG BIT 9 OUT REG BIT 8 OUT REG BIT 7 OUT REG BIT 6 OUT REG BIT 5 OUT REG BIT 4 OUT REG BIT 3 OUT REG BIT 2 OUT REG BIT 1 OUT REG BIT 0 R W 0 011 O Figure 3 3 Output Register 0 OUT REGO TCP630 10 Output Port Bits 0 31 are written to lO 0 IO 31 TTL TCP630 11 Output Port Bits 0 31 are written to lO OA B IO 31A B Differential TCP630 12 Output Port Bits 0 15 are written to OA B IO 15A B Differential Output Port Bits 16 31 are not used TCP630 User Manual Issue 1 0 Page 11 of 46 TEWS S TECHNOLOGIES 3 2 2 Output Register 1 OUT 0x04 Bit Symbol Description Access Reset Value 63 OUT REG BIT 63
36. ming to PICMG 2 0 R3 0 Electrical Interface PCI Rev 2 2 compliant 33 MHz 32 bit PCI 3 3V and 5V PCI Signaling Voltage On Board Devices PCI Target Chip PCI9030 PLX Technology Local Control Logic FPGA Spartan lIIE 25300 6 FG456 Xilinx Line Transceivers 74LVT126 TTL I O TTL signaling voltage level with maximum current 32 mA MAX3078E Differential I O EIA 422 485 signaling level Interface Number of Channels 64 TTL I O TCP630 10 32 differential I O TCP630 11 or 32 TTL and 16 differential I O TCP630 12 Connectors The TCP630 provides a PIM slot instead of a front I O connector TCP630 2x additional 110 pol CompactPCI back I O 72 Physical Data Power Requirements Without PIM amp with Example Design TCP630 x0 160 mA typical no load 3 3V DC TCP630 x1 110 mA typical no load 3 3V DC TCP630 x2 120 mA typical no load 3 3V DC TCP630 x0 10 mA typical 5 DC when used as pull up voltage TCP630 x1 5V DC not used TCP630 x2 10 mA typical 5 DC when used as pull up voltage Temperature Range Operating 40 C to 85 Storage 40 to 85 TCP630 10 381 000 h TCP630 11 522 000 h TCP630 12 439 000 h TCP630 10 359 000 h TCP630 11 482 000 h TCP630 12 410 000 h Humidity 5 95 96 non condensing Weight 124 g TCP630 User Manual Iss
37. n Register 0x30 Local Address Space 0 Bus Region Description Register Ox34 Local Address Space 0 Bus Region Description Register 0x38 Expansion ROM Bus Region Description Register You could also use the PCI Base Address 1 I O Mapped Configuration Registers TCP630 User Manual Issue 1 0 Page 31 of 46 TEWS S TECHNOLOGIES 6 2 Clock Programming The CY27EE16 is programmed over a serial 2 wire programming interface with the serial clock signal SCLK and the serial data signal SDAT These two signals are directly controlled by the PLX PCI9030 the SDA signal by GPIO7 and SCL by EESK Because of the shared EESK signal the serial configuration EEPROM and the CY27EE16 cannot be accessed simultaneously The CY27EE16 is addressed as a group of ten slave devices on the 2 wire bus The address of the clock configuration EEPROM is 0x68 Changes of the clock configuration by writing to the SRAM at address 0x69 should only be done with caution as these changes take immediately effect at the clock outputs This could cause problems by the occurrence of glitches Especially the LCLK input of the PCI9030 which is the CLK1 signal on the board should never be changed during operation recommendation by PLX For the same reason a soft reset of the device should not be activated after reprogramming the CY27EE16 clock configuration EEPROM Soft reset is generated by setting the MSB in the SRAM space at offset 0x00 followed by an I2C stop This will update
38. on hardware products an Active Low is represented by the signal name with following i e RESET Access terms are described as W Write Only R Read Only RW Read Write R C Read Clear R S Read Set 2006 by TEWS TECHNOLOGIES GmbH Page 2 of 46 TEWS TECHNOLOGIES Issue Description Date 1 0 First Issue November 2006 TCP630 User Manual Issue 1 0 Page 3 of 46 TEWS S TECHNOLOGIES Table of Contents 1 PRODUCT DESCRIPTION 8 2 TECHNICAL SPECIFICATION u u u l i dE uU U U uu 9 LOCAL SPACE ADDRESSINGQ kd au 10 3 1 PCI9030 Local Space Configuration 10 3 2 FPGA Example Design Register Space U U u u u u 10 3 2 1 Output Register 0 OUT REGO 0 0 nenne A 11 3 2 2 Output Register 1 OUT REG1 OXQ ccinn nennen 12 3 2 3 Input Register 0 IN REGO 0 08 nennen nnne 13 3 24 Input Register 1 IN 14 3 2 5 Output Enable Register 0 OE REGO 0x10 U u u 15 3 2 6 Output Enable Register 1 OE REG1 0x14 nens
39. state This means instead of toggling the corresponding bit of the output register the output enable register bit is set to 0 for an output high level or 1 to pull the output low the OUT_REG bit is 0 For example when connecting to a standard 5V CMOS logic input not TTL compatible levels a high level of minimum 3 5V is required Please note that the pull up resistor can only drive high impedance inputs A TVS array protects against ESD shocks See the following figure for more information of the TTL I O circuitry Please note that the length and consequently the capacitance of a flat cable connected to the TCP630 module should be kept as short as possible to prevent large cross talk To reduce the cross talk on the TCP630 not all 64 I O lines should be switched at the same time The output lines could be switched in 8 groups of 8 signals in steps of 12 5ns 40 MHz clock as shown in the VHDL example After about 100ns the switching process is completed TCP630 User Manual Issue 1 0 Page 34 of 46 TEWS S TECHNOLOGIES 5V or 3 3V FPGA OEx FPGA_OUTx 3 1 TTL Line X1 P14 XILINX FPGA MSMF05 Protection FPGA INx 7ALVT126 Figure 7 2 TTL I O Interface 7 2 2 Differential Interface Each of the 32 TCP630 11 or 16 TCP630 12 differential 1 line pairs is realized with an input output and output enable pin at the XILINX FPGA connected to a MAX3078E an ESD protected RS485 RS422
40. t load capacitor control 0x00 0x14 ADC Register 0x00 0x40 Charge Pump and PB counter 0xC0 0x41 Charge Pump and PB counter 0x03 0x42 PO counter Q counter 0x81 0x44 Crosspoint switch matrix control 0x42 0x45 Crosspoint switch matrix control 0x9F 0x46 Crosspoint switch matrix control 0x3F 0x47 DIV2SRC mux and DIV2N divider OxE4 Figure 6 3 Default register values at delivery TCP630 User Manual Issue 1 0 TEWS S TECHNOLOGIES Page 33 of 46 TEWS S TECHNOLOGIES 7 installation 7 1 Pull Up Voltage The voltage of the pull up resistors can be 3 3V or alternatively 5V specified by jumper J1 The default pull up voltage is 3 3V J1 Jumper Position Pull Up Voltage 1 2 3 3V default 2 3 5V Figure 7 1 Pull Up Voltage Jumper Setting 7 2 Interface 7 2 1 TTL I O Interface Each of the 64 TCP630 10 or 32 TCP630 12 TTL I O lines is realized with two 74LVT126 bus buffers as an interface to the FPGA pins The logic levels of the buffers are TTL compatible meaning that the minimum high level is 2 0V and the maximum low level is 0 8V The nominal output high voltage is 3 3V The buffer outputs are followed by 47Q serial resistors for signal integrity reasons The 4 7kQ pull up resistors guaranty a high level when outputs are tristate and not driven externally As an option the pull up voltage can be set to 5V by jumper J1 to weakly drive a higher voltage than 3 3V by setting the output to tri
41. ue 1 0 Figure 2 1 Technical Specification Page 9 of 46 Local Space Addressing 3 1 PCI9030 Local Space Configuration The local on board addressable regions are accessed from the PCI side by using the PCI9030 local TEWS S TECHNOLOGIES spaces PCI9030 PCI9030 PCI Size Port Endian Description Local PCI Base Address Space Byte Width Mode Space Offset in PCI Mapping Bit Configuration Space 0 2 0x18 MEM 16 32 BIG FPGA Example Design Register Space 1 3 0x1C Not Used 2 4 0x20 Not Used 5 0x24 Not Used Figure 3 1 PCI9030 Local Space Configuration 3 2 FPGA Example Design Register Space The TCP630 is delivered with a FPGA example design in the configuration memory PCI Base Address PCI9030 PCI Base Address 2 Offset 0x18 in PCI Configuration Space Offset to PCI Register Name Size Base Address 2 Bit 0x00 Output Register 0 OUT REGO 32 0x04 Output Register 1 OUT REG1 32 0x08 Input Register 0 IN REGO 32 0 0 Input Register 1 IN_REG1 32 0x10 Output Enable Register 0 OE_REG0 32 0x14 Output Enable Register 1 OE_REG1 32 0x18 Interrupt Status Register ISR 32 0x1C Positive Edge Interrupt Enable Register PIER 32 0x20 Negative Edge Interrupt Enable Register NIER 32 0x24 RAM Address Map Register RAMR 32 0x28 OXFFFFFF 256 x 32 bit RAM Space 32 Figure 3 2 FPGA Examp
42. umentation 5 2 FPGA Pin Assignment PCI Controller 5 2 1 Pin Assignment of Local Bus Control Signals TEWS 2 TECHNOLOGIES Programmable Clock Clock Control Signals Input Lines FPGA Data Signals Output Lines SpartanllE Address Signals XC2 S300E utput Enable Lines Local Bus I O Signals Figure 5 1 FPGA Signals Block Diagram I O Circuit Signal Pin Description LRESET T2 Local Reset LRD W1 Local Read LWR P1 Local Write LADS L1 Local Address Strobe LBEO 18 Local Enable 0 LBE1 AB16 Local Byte Enable 1 LBE2 13 Local Enable 2 LBE3 11 Local Enable 3 LCS0 R1 Local Chip Select 0 LCS1 R2 Local Chip Select 1 TCP630 User Manual Issue 1 0 Page 24 of 46 Signal Pin Description LCS2 L2 Local Chip Select 2 LCS3 U1 Local Chip Select 3 LINT1 T1 Local Interrupt 1 LINT2 U2 Local Interrupt 2 LBLAST 1 Local Burst Last LRDY N2 Local Ready LW_R Y2 Local Write Read low active for reads high for writes LBTERM P2 Local Burst Terminate Figure 5 2 Pin Assignment Local Bus Control Signals In the VHDL example code low active signals have an n as last character instead of the 5 2 2 Pin Assignment of Local Bus Data Signals TEWS S TECHNOLOGIES

TCP630 - powerbridge.de

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