Tamarisk 640 Electrical Interface Control Document
Contents
1. BDS _FSYNC Figure 18 YUV SuperFrame Line Format Over Parallel Digital Video Interface lt One Video Frame gt BDSI_FSYNC EN H Blanking BDSI LSYNC o _ LN _ Es E Line Line Line He Line Line H Line H Line BDSI_DATA 13 6 480 2 3 5 477 478 479 480 lt 480 Lines gt LE Figure 19 YUV Sperframe Frame Format Over Parallel Digital Video Interface Table 10 YUV SuperFrame Video Timino Parameter i Units BDSI PCLK clock frequency for 30 Hz frame rate or 9Hz MHz Clock to Data Fsync Lsync valid after the rising edge of the clock 0 5 Clock period 10 ns Note Data will be valid for 10 ns before the rising edge of the next clock 3 3 ANALOG VIDEO INTERFACE The camera provides an analog video output which follows the RS 170 standard base feature only The analog video output signal is transmitted at 1v Peak to Peak Following are the nominal output signal levels when terminated with 75 Ohms 5 21 i RR E Tamarisk 640 Electrical ICD DRS Technologies Sync tip 0 284 V Blank OV Black 0 051 V White 0 714 V Frame timing parameters are shown in Table 11 Table 11 Analog Video Timing RS 170 Out ma O j e PT e E active video 640 active pixels 47 400 us 262 5 lines 2250052. i Row Row Row Row Row BDSI DATA 9 0 480 141 3 5 7 lt 240 gt lt 240 BDSI PCLK 27MHz Figure 15 Parallel RS 170 PAL Video Vertical Timing Diagram a 1716 Clocks per Line gt 37 a pI nS BDSI PCLK 27MHz AN SN BDSI DATA 9 0 1716 1716 1 2 3 4 5 6 7 9 1407 1408 1409 1410 1714 1715 i716 gt lt 308 Clocks of Horizontal Blanking lt 1408 Clocks of Pixels per line Figure 16 Parallel RS 170 NTSC Video Horizontal Timing Diagram 22 5 Lines 22 5 Lines Vertical gt lt Odd Field Lines p lt Vertical gt lt Even Field Lines gt Blanking Blanking H Blanking H Blanking E NA UTN aen AN Row Row 477 479 Ci p ow Row Row Row Row Row Row Row Row BDSI DATA 9 0 480 11 3 5 7 2 4 6 8 240 gt lt 240 BDSI PCLK 27MHz Figure 17 Parallel RS 170 NTSC Video Vertical Timing Diagram In YUV_SuperFrame mode the Parallel Digital Video Interface is formatted with 2560 bytes per line and 480 lines per frame The format of Parallel Digital Video
3. 1 14 8 bit Gray Scale 2 24 bit RGB 3 YUV Superframe 16 iy 10 me Tamarisk 640 Electrical ICD DRS Technologies The 14bit Gray Scale format is used to support the 14bit and 8bit gray scale data modes The 14bit and 8bit Gray Scale mapping follows the Camera Link standard and maps as shown in Table 8 Table 8 Camera Link Gray Scale and YUV_Superframe Mapping to 24 bit color map Camera Link l l YUV Superframe 14bit data mode 8bit data mode 24 Bit color Mode G7 Not Used Not Used Bit 15 G6 Not Used Not Used Bit 14 G5 Bit 13 Bit 7 Bit 13 G4 Bit 12 Bit 6 Bit 12 G3 Bit 11 Bit 5 Bit 11 G2 Bit 10 Bit 4 Bit 10 G1 Bit 9 Bit 3 Bit 9 GO Bit 8 Bit 2 Bit 8 R7 Bit 7 Bit 1 Bit 7 R6 Bit 6 Bit O Bit 6 R5 Bit 5 Not Used Bit 5 R4 Bit 4 Not Used Bit 4 R3 Bit 3 Not Used Bit 3 R2 Bit 2 Not Used Bit 2 R1 Bit 1 Not Used Bit 1 RO Bit O Not Used Bit O The 24bit RGB format is used to support the colorization data mode and uses the standard Camera Link 24bit RGB format In YUV Superframe mode a 16 bit video stream is mapped into the Camera Link Interface as shown in Table 8 The YUV Superframe consists of 480 lines with each line containing 1280 values The first 640 values contain YCbCr generated values for the pixels of that line with the second 640 values containing the pre AGC values for that line currently the pre AGC values are from the frame before the current YCbCr frame this allows time for anal
4. 11 15 2013 Prepared for Public Release Camera Link is a registered trademark of the Automated Imaging Association 10 Tamarisk 640 Electrical ICD DRS Technologies TABLE OF CONTENTS Table of Contents 2 Acronyms and Abbreviations 3 Reference Documentation 4 Safety Instructions 5 1 Scope 6 2 Electrical Interfaces 7 2 1 Base Configuration Electrical Interface eee errar 7 2 2 Base Configuration Input Power Specification errar 9 2 3 Base Feature Board Configuration Electrical Interface i iii 10 2 4 Base Feature Board Configuration Input Power Specification cccccccseeeseeees 12 MT CIN AC Cera ctor cece tease done nie gas adegas A A tect eus canes iso set gia caiga del 13 RO SOUCY CONTO usinas nee sens anesocitusenen neve ancvaseedsiedentnentnrannuecienaeneern dente meaminenaeuts 14 2 I eerren e cheese Daiid E 14 20 USE DELES Dois usa E 14 3 Interfaces and Timing 15 dd JENDS TS 1G Se ccsstrcditaceng E EA O 15 32 PARALLEL DIGITAL VIDEO INTERFACE eres ea 18 3 3 Analog Video Interface cccccccccceccecceeeceeeseeeceeeceeecseeceeeceeseusseusseeeseueseeessesseessaeees 21 3 4 USB Interface base feature only eee erre ne rrreanena 23 3 5 RS 232 Interface base feature only erre eee erre 23 IO SOUS MAT ONG A A 23 4 Electrical Connectors 24 Tamarisk e40 Electrical ICD ACRONYMS AND ABBREVIATIONS Abbreviation
5. Description Celsius Fahrenheit automatic gain control bad pixel replacement circuit card assembly center line communication Computer Software Component Computer Software Configuration Item Computer Software Unit decibels digital signal processor electrostatic discharge electronic zoom field of view Focal Plane Array feet gravitational force gram graphical user interface height horizontal field of view input output Interface Control Document Image Contrast Enhancement identification infrared Interface Requirements Specification kilometer lower right long wave infrared Abbreviation mm ms MSB MTU MWIR NETD NTSC NUC NVTHERM OEM OLA P POL psi Rev ROI SC SWIR TBD TCR TIM UART UAV UFPA USB V VDC VGA VOx W um da DRS Technologies Description millimeter milliseconds Most Significant Bit Maximum Transfer Unit Mid wave infrared noise equivalent temperature difference National Television System Committee non uniformity correction Night Vision Thermal Analysis Tool original equipment manufacturer Optical Lens Adapter probability polarity pound per square inch revision region of interest split configuration Short wave infrared To Be Determined Temperature coefficient of resistance Thermal Imaging Module Universal Asynchronous Receiver Transmitter unmanned aerial vehicle Un cooled Focal Plane Array Universal Serial Bus Vertical or Voltage
6. Tamarisk 64o 17 um 640x480 Long Wave Infrared Camera Electrical Interface Control Document Document No 1014845 Revision C N OOO 7 DRS Technologies A Finmeccanica Company mm Tamarisk s4o Electrical ICD l E DRS Technologies Copyright 2013 DRS TECHNOLOGIES Inc All rights reserved 13532 N Central Expressway Dallas TX 75243 8 7 3117 4 783 www drsinfrared com The contents of this document may not be reproduced in whole or in part without the written consent of the copyright owner NOTICE ALL STATEMENTS INFORMATION AND RECOMMENDATIONS IN THIS MANUAL ARE BELIEVED TO BE ACCURATE BUT ARE PRESENTED WITHOUT WARRANTY OF ANY KIND NOTWITHSTANDING ANY OTHER WARRANTY HEREIN ALL DOCUMENT FILES AND SOFTWARE ARE PROVIDED AS IS WITH ALL FAULTS DRS DISCLAIMS ALL WARRANTIES EXPRESSED OR IMPLIED INCLUDING WITHOUT LIMITATION THOSE OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OR ARISING FROM A COURSE OF DEALING USAGE OR TRADE PRACTICE IN NO EVENT SHALL DRS BE LIABLE FOR ANY INDIRECT SPECIAL CONSEQUENTIAL OR INCIDENTAL DAMAGES INCLUDING WITHOUT LIMITATION LOST PROFITS OR LOSS OR DAMAGE TO DATA ARISING OUT OF THE USE OR INABILITY TO USE THIS MANUAL EVEN IF DRS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Rev History Revision Number Release Date Description A 01 24 2013 Initial Release Updated timing tables 07 16 2013 descriptions IAW CR 76432
7. outlined in Table 2 Table 2 Base Configuration Inout Power Specification Parameter VIN Icc Icc with Shutter active Vou LVDX_XXX VoL LVDS XXX Vou UART TX Vo UART TX Vin UART RX GENLOCK Vi UART RX GENLOCK Von BDSI xx USB DETECT SHUTTER DRIVE SHUTTER EVENT WE TEST amp GENLOCK Vo BDSI xx USB DETECT SHUTTER DRIVE Description Input Voltage Input Current VIN 5 0 Input Current RMS during transition VIN 5 0 Von High Level Output 2 5V output lox MA VoL Low Level Output 2 5V output loL ImA Von High Level Output 1 8V output VoL Low Level Output 1 8V output Vin High Level Input 1 8V input Vi Low Level Input 1 8V input Von High Level Output 1 8V output lox 2mA Vo Low Level Output 1 8V output lot 2mA Min Typ 3 0 5 0 230 350 2 0 1 35 1 17 0 3 1 35 Max 95 295 650 0 4 0 45 2 25 0 63 0 45 Units mA mA lt lt Ll lt lt da 1 O Tamarisk 640 Electrical ICD DRS Technologies Parameter Description Typ SHUTTER EVENT WE_TEST GENLOCK The shutter is typically active for 100 mS closing and 100ms opening NOTE Shutter current demand is instantaneous care should be taken to provide bypass capacitance to prevent voltage regulator sag The module also provides a 1 8V output that can be used to supply some circuitry on the feature board for the system This supply is used to drive
8. Interface 1s shown in Figure 18 and Figure 19 Each line contains 640 Y values one per pixel interleaved with 320 Cb and 320 Cr values Cb and Cr are calculated over 2 adjacent pixels followed by the Pre AGC data for the 20 Tamarisk s4 Electrical ICD gt DRS Technologies same line The Pre AGC data is the pixel data before any non linear gains are applied The format of the Pre AGC data is 16 bits sent 8 bits at a time The 8 bits occupy the bits 13 down to 6 of the BDSI bus with the most significant bit in bit 13 and the other bits filled in respectively The lower 8 bits of a pixel are sent on one clock with the upper 8 bits being sent on the next clock The 14 bits of raw data is converted to 16 bits that are LSB aligned that is bits 15 14 will always be low The lower byte of the 14bit raw data is sent first followed by the upper byte The clock rate while in YUV SuperFrame mode is 40 5MHz The amount of blanking time between lines and frames will vary based on camera mode and revision The pre AGC values are from the frame before the current YCbCr frame This allows for signal processing on the pre AGC values prior to enhancements being added to the YCbCr displayed to a user BDSI_FSYNC BDSI LSYNC Y Y Pre Pre Pre Pre Pre Pre Pre Pre y C C 6 C 6 C aGc AGC AGC AGE ___ AGE acc acc acc SPSL DATAS P ee SG 3 b 4 r 1 1 2 2 639 639 640 640 9 0 b ub tb ub b ub b ub
9. Low Level Output Single Ended Rx Threshold Differential Common Mode Differential Input Sensitivity Driver Output Impedance The shutter is typically active for 100 mS closing and 100ms opening 12 O SN Tamarisk 640 Electrical ICD DRS Technologies NOTE Shutter current demand is instantaneous care should be taken to provide bypass capacitance to prevent voltage regulator sag Figure 6 illustrates the Feature Board s different power inputs on the left and the 5 Volt output on the right which is an input to the Processor Board By design the Feature Board accommodates a range of DC input voltage from 5 to 18V on EXTPWR However only one power input should be used at a time The 5V to 18V regulator utilizes a Texas Instruments TPS61170DRVR p ee ewe ee ee hl ee hl ll EXTPWR J19 1 5VDC J3 1 8 Power Switch 4 5to 18V Regulator 12V_CL J19 6 OEAX Power Block Diagram USB_5V J19 13 Figure 6 OEAX Board Power Block Diagram 2 5 UART INTERFACE Command amp Control for the module is handled through a standard UART The interface to the UART is through the connectors described in Table 2 and Table 6 For base configuration the UART interface uses 1 8V CMOS logic levels for base feture board configuration the full RS 232 voltage levels are supported Table 6 UART Signal Definition Configuration 1 and 2 Co
10. NA No Connection Reserved LVDS_D3p 2 LVDS V D LVDS D3n Output S Video output Data 3 LVDS D2p LVDS D2n Output LVDS Video output Data 2 LVDS D1p LVDS Vi Data 1 LVDS Din Output S Video output Data LVDS DOp LVDS Don Output LVDS Video output Data O LVDS_CLKp o LVDS Video Data output utput LVDS_CLKn Clock BDSI D11 Output Parallel Digital Data Output BDSI D10 Output Parallel Digital Data Output BDSI D9 Output Parallel Digital Data Output BDSI D8 Output Parallel Digital Data Output BDSI D7 Output Parallel Digital Data Output BDSI D6 Output Parallel Digital Data Output BDSI D5 Output Parallel Digital Data Output BDSI D4 Output Parallel Digital Data Output BDSI D3 Output Parallel Digital Data Output BDSI D2 Output Parallel Digital Data Output BDSI D1 Output Parallel Digital Data Output BDSI DO Output Parallel Digital Data Output Unused outputs can be no connects No connection should be left floating Signal Name NC USB_DETECT UART_TX UART_RX Reserved Reserved Reserved SHUTTER_DR IVE SHUTTER_EV ENT Reserved Reserved Reserved Reserved Reserved GENLOCK BDSI PCLK BDSI LSYNC BDSI FSYNC BDSI D13 BDSI D12 Output Input NA NA NA Output Output NA NA NA NA NA Input Output Output Output Output Output Output w DRS Technologies Description NA USB Control signal detection It is recommended that If communicating to the camera via a
11. all 1 8V outputs from the module Table 3 Base Configuration External 1 8V Drive Capability Parameter Description VCC IO I O Output Voltage lout Output Current 2 3 BASE FEATURE BOARD CONFIGURATION ELECTRICAL INTERFACE The Base Feature Board configuration supports RS170 NTSC and PAL Camera Link RS232 USB and various input power connection options Electrical interface is through a 30 pin connector located near the center of the Feature board See Figure 2 The electrical interface pin out for this connector is detailed in Table 4 below Table 4 Electrical Interface for Base and Base Feature Board Configurations Signal Name Function Description EXTPWR Power External Power input 5 18V EXTPWR_GND Power External Power input ground RS232_RX Input RS232 input signal RS232 TX Output RS232 output signal 12V CL Power 12V power input GND CL Power 12V power input ground USBDP USBDM Bi directional USB Interface 10 Tamarisk s4o Electrical ICD Signal Name Function LVDS DOn LVDS DOp LVDS Din LVDS Dip LVDS D2n LVDS D2p LVDS CLKn LVDS CLKp LVDS D3n LVDS D3p A VID OUT USB 5V Ground NC NC NC NC GENLOCK Ground Analog Video Ground Output Output Output Output Output Output Power Power NA NA Bi directional Power Power PIN 29 PIN ol 7 DRS Technologies Description LVDS Video Data output Data 0 LVDS Video Data output Data 1 LVDS Video Data
12. 16 683 ms vertical blanking 17 160 61 050 Hz 1 271 ms 525 lines 450 450 33 367 ms vertical blanking 34 320 30 525 Hz 2 542 ms Active video 485 lines 416 130 30 824 ms The camera s FPA outputs a 640 x 480 image but RS 170 specifies 485 lines of active video The module accommodates this by inserting black lines in line positions 481 through 485 as illustrated in Figure 20 FPA RS 170 Output output frame frame line 480 line 480 Figure 20 Analog Video Format 22 10 s Tamarisk 640 Electrical ICD DRS Technologies 3 4 USB INTERFACE BASE FEATURE ONLY The USB interface utilizes FTDI s FT232RQ The FT232RQ is a UART to USB Transceiver For specific timing information refer to the FTDI data sheet 3 5 RS 232 INTERFACE BASE FEATURE ONLY The RS 232 interface utilizes Linear Technologies TC2801IDE PBF The TC2801IDE PBEF is a UART to RS 232 Transceiver For specific timing information refer to the Linear Technologies data sheet 3 6 SHUTTER INTERFACE The shutter is not spring loaded The shutter is bi stable If the shutter is closed and the camera is powered down the shutter will remain closed until power is applied again If the shutter is open and the camera is powered down the shutter will remain open The shutter timing diagram is shown in Figure 6 When the SHUTTER_EVENT signal is high the camera s software is performing calibration As the camera warms or cools the camer
13. USB to serial converter tie this pin low If communicating to the camera via RS232 or another UART tie this pin high UART Control Output UART Control Input No Connection No Connection No Connection High when the shutter is driven High during a calibration event No Connection No Connection No Connection No Connection No Connection Video Genlock signal master or slave If not used leave floating Parallel Digital Video Clock Parallel Digital Video Line Sync Active High Parallel Digital Video Frame Sync Active High Parallel Digital Video Data Output Parallel Digital Video Data Output Tamarisk s4o Electrical ICD Signal Name VCC_IO Ground Figure 4 60 pin Connector J2 Func tion Power Description DRS Technologies 1 8V I O Supply Output Output Ground Figure 3 provides the board mounting hole and connector J2 dimensions All dimensions are in mils and all dimensions are show at the center of the connector or mounting holes please see mechanical ICD listed in reference documentation for all up to date dimensions and drawings 2 2 BASE CONFIGURATION INPUT POWER SPECIFICATION The primary voltage input VIN for this configuration requires the input voltage to be within the range from 3 0 to 5 5VDC There are many readily available commercial power supplies power adapters and or batteries battery packs meeting this voltage range with the current requirements
14. a MSB on BDSI D13 LSB on BDSI D6 from Table 1 Pre AGC selected video will be 14 bit For customers that require pre AGC video methods will be provided to select full 14 bit video data see Document No 1014844 Tamarisk 649 Software Interface Control Document Timing of the video interface is described in Table 9 and Figure 11 Table 9 Parallel Digital Video Timino Parameter BDSI_PCLK clock frequency for 30 Hz frame rate or 9Hz Clock to Data Fsync Lsync valid after the rising edge of the clock Period of BDSI_PCLK 100 0 5 Clock period 10 Note Data will be valid for 10 ns before the rising edge of the next clock Valid Data Frame Line Sync Figure 11 Parallel Digital Video Timing Diagram 18 O SM Tamarisk 640 Electrical ICD DRS Technologies Figure 12 illustrates the Parallel Digital Interface s horizontal timing The BDSI_LSYNC signal will go high for 640 clocks each line to indicate valid video data is available via the data bus BDSI DATA The BDSI LSYNC signal will go low for several BDSI_PCLKs between each line of data The number of clocks the BDSI LSYNC is low between valid lines horizontal blanking time can vary based on the operating mode and camera release Valid Video Data gt BDSI LSYNC Par BDSI PCLK 10MHz E AN PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PONT BDSI DATA 13 0 639 640 i 1 2 3 4 5 6 636 637 638 639 640 l
15. a may change operating ranges During these operating range changes the shutter is closed for a longer period of time Table 10 Shutter Timing Number Parameter 1 SHUTTER_DRV high time SHUTTER_EVENT high time without a range change SHUTTER_EVENT high time during a camera range change SHUTTER_DRV Closed Opening I I Figure 21 Shutter Timing 23 1 N Tamarisk 640 Electrical ICD DRS Technologies ELECTRICAL CONNECTORS There are two electrical connectors that support electrical interface to the Tamarisk 40 camera module with the connector type being dictated by the model configuration The connector manufacturer and part number shown below is the part number which is on the camera board The designer must interface to one of these connectors Please refer to the Tamarisk 640 Users Manual for more details Configuration 1 60 pin Samtec ST4 30 1 L D P TR http www samtec com Configuration 2 30 pin JST BM30B SRDS G TF http www jst com index html 24
16. e the frame rate can vary between gt 0 and 30Hz Calibration times will increase at lower frame rates A frame rate of O Hz is a special case and can cause unexpected behavior during calibration The GENLOCK input signal high time can be as low as 1 and us much as 99 of the 30Hz frame time of 33 33mS 333uS to 33 0mS When GENLOCK is configured in master mode the GENLOCK signal goes high for at least 50nS once a frame For more information on how to set GENLOCK mode please see Document No 1014844 Tamarisk 40 Software Interface Control Document 2 8 USB DETECT Active high signal to indicate USB connection NOT 5V tolerant in base configuration 14 10 Tamarisk 640 Electrical ICD DRS Technologies 3 INTERFACES AND TIMING Timing information for both the Base and Base Feature Board configurations are described in this section 3 1 LVDS INTERFACE The LVDS interface supports two modes of operation Camera Link mode and YUV Superframe mode Camera Link mode is typically used to interface to Camera Link frame grabbers The LVDS video interface supports 4 LVDS data pairs and the LVDS clock pair as outputs The LVDS timing is shown in Table 7 while the timing diagram is shown in Figure 7 and Figure 8 The LVDS Clock signal has a non fifty percent duty cycle It is based on a 7x internal clock The LVDS Clock is high for 4 of the 7x clock periods and low for 3 During each clock period 7 bits are transmitted on each data pa
17. eature Board Refer to the Tamarisk 640 Users Manual for more information In this section the electrical interfaces for the Base configuration and Base Feature Board configuration are described Retaining Ring Lens Processor Board 60 pin Connector Camera Housing with Integrated Lens Mount Figure 1 Tamarisk 49 Base Configuration The Base configuration provides digital outputs in the form of 8 bit 14 bit or YUV Superframe parallel digital video LVCMOS UART 8 bit 14 bit 24 bit RGB or YUV Superframe Camera Link video and supports shutter status through a 60 pin connector Advantages of the Base configuration include parallel digital video output reduced size weight and power requirements Retaining Ring Feature Board Lens Camera Housing with Integrated Lens Mount 30 pin Connector Figure 2 Tamarisk g49 Base Feature Board Configuration The Base Feature Board configuration supports RS232 and USB 2 0 serial control NTSC and PAL analog video outputs digital video output via Camera Link and accepts a range of input power voltages from 5 18V through a single 30 pin connector Advantages of this configuration 1s that it provides analog video output as well as full RS232 or USB 2 0 communication 10 Tamarisk 640 Electrical ICD DRS Technologies Y No UU io Vee INTERFACES 2 1 BASE CONFIGURATION ELECTRICAL INTERFACE This configuration has no Feature board the electrical
18. er Note This mode 1s not recommended for users that are not planning on driving a Digital to Analog converter The data will be contrived to generate a valid analog signal that conforms to the RS170 specifications The output analog signal adheres to requirements for RS170 NTSC or one of three PAL modes see Document No 1014844 Tamarisk 649 Software Interface Control Document for information on how to set PAL modes 19 10 Tamarisk 640 Electrical ICD DRS Technologies Data is driven on BDSI_D9 through BDSI DO 10 bits The data is binary format BDSI PCLK provides the single ended clock for the D A conversion at 27 MHz Example timing 1s shown in Figure 14 and Figure 15 for PAL mode and Figure 16 and Figure 17 for NTSC mode 1728 Clocks per Line gt 37 ns BDSI PCLK 27MHz nN SN asis EC CECCCECEN Feee EEE 324 Clocks of Horizontal Blanking lt 1404 Clocks of Pixels per line gt lt Figure 14 Parallel RS 170 PAL Video Horizontal Timing Diagram 25Lines 25Lines q Vertical gt lt Odd Field Lines gt lt Vertical gt lt Even Field Lines gt Blanking Blanking H Blanking H Blanking b BHEAN ROW ROW Row Row Row Row 573 575 2 4 6 8
19. interface is through a 60 pin connector located on the Processor board see Figure 1 Tamarisk 640 Base Configuration for location A Board layout is provided below For more dimesional information please refer to Document No 1010056 Tamarisk sao Mechanical Interface Control Document The Tamarisk Camera Link video digital video LVCMOS UART interface shutter status are supported See the electrical interface pin out listed in Table 1 BB i i wi 925 a 60 Pin Connector J2 993 T me L n m oo mn O ogg ur T a ee al oi E 005 R068 068 4083 Pe Os 940 Figure 3 Processor Board with Connector Location and Dimensions Table 1 Electrical Interface Pin Out for Base Configuration Description i Signal Name Description Ground Primary ground return for Primary voltage supply for the module power camera module 3 5 5V Camera Link serial control LVDS_RDp LVDS_RDn LVDS_TDp LVDS_TDn are NOT supported in any configuration serial control is always provided with the UART control for base configuration Pin J2 9 J2 11 J2 13 J2 15 J2 17 J2 19 J2 21 J2 23 J2 25 J2 27 J2 29 J2 31 J2 33 J2 35 J2 37 J2 39 J2 41 J2 43 J2 45 J2 47 J2 49 J2 51 J2 53 J2 55 J2 57 J2 59 J2 Tamarisk s4o Electrical ICD Signal Func cert Naima tion Description R Enn NA No Connection Reserved R neS
20. ir The bits are transmitted in the order shown in Figure 7 with each pixel value starting in the middle of the high clock period The LVDS data window timing is shown in Figure 8 The maximum delay for the data to become valid after clock and the minimum time data will go invalid before the clock are also described in Table 7 Table 7 LVDS Timing and Framing Parameter Clock Period 7x Internal Clock Freq Bit time Data no longer valid before clock Clock to data valid Data valid window LINES Lines per frame Pixels per line in Camera PIXELS CL Link Mode Pixels per line in YUV_SF mode 1 LVDS CLK woso SNORE SAAAOA EAS Figure 7 LVDS Format Diagram PIXELS_YUV 15 O N Tamarisk 640 Electrical ICD DRS Technologies Figure 9 Camera Link bit mapping for 24 bit RGB color Figure 9 shows the mapping of Camera Link serialized bit stream to 24 bit RGB color FVAL is low invalid between frames while LVAL is low invalid between lines DVAL is high to indicate that the data is valid A frame will consist of FVAL going high valid for an entire frame Blanking time is inserted between each frame while FVAL is low A line will consist of LV AL going high valid for an entire line Blanking time is inserted between each line while LVAL is low The amount of horizontal and vertical blanking can change based on operating modes and Camera revisions The LVDS Interface supports three interface formats
21. nfiguration Signal Description Base UART TX UART Transmit Data 1 8V LVCMOS output UART Receive Data 1 8V LVCMOS input 3 3V tolerant NOT 5V tolerant Base Feature RS232_TX UART Transmit Data Supports full 5V levels Base Feature RS232 RX UART Receive Data Supports full 25V input levels Base UART RX 13 da 1 O mely Tamarisk 640 Electrical ICD DRS Technologies 2 6 SHUTTER CONTROL If an external shutter is desired two external signals are provided via base configuration 60 pin connector and base configuration feature board s 30 pin connector The SHUTTER_DRYV signal is high when the shutter is being driven open or closed and low when the shutter is not driven The SHUTTER EVENT signal is high during a calibration event this signal is used to indicate that the shutter is blocking the FPA During normal operation the SHUTTER_EVENT signal is low Refer to the shutter timing diagram for timing information 2 7 GENLOCK The GENLOCK signal in both base and base feature board support frame linking to an external signal All frame data will start based on the rising edge of the GENLOCK signal Extra line syncs will be generated to avoid row burn out until the next rising edge of the GENLOCK signal GENLOCK will also support a master mode of operation where the camera system drives a frame sync to other components or subsystems via the GENLOCK pin When GENLOCK is configured in slave mod
22. output Data 2 LVDS Video Data output Clock LVDS Video Data output Data 3 Analog Video Output RS 170 or NTSC or PAL USB 5V input power Ground NA NA Video genlock signal master or slave Ground Dedicated Analog Video Ground PIN 1 Figure 5 30 pin Connector J19 Camera Link serial control LVDS RDp LVDS RDn LVDS_TDp LVDS_TDn are NOT supported in any configuration serial control is always provided with the UART control for base feature board 11 iy 10 A Tamarisk 640 Electrical ICD DRS Technologies 2 4 BASE FEATURE BOARD CONFIGURATION INPUT POWER SPECIFICATION There are three ways to supply input power to this configuration these are detailed in Table 5 below Table 5 Configuration 2 Inout Power Specification Input Parameter Description VIN Input Voltage lcc Input Current VIN 5 0 VIN Input Voltage EXTPWR 12V_CL lcc Input current VIN Input Voltage USB_5V Icc Input Current Icc with Input Current RMS Shutter lcc during transition active VIN 5 0 Von High Level Output 1 8V output GENLOCK VoL Low Level Output 1 8V output Vin High Level Input 1 8V GENLOCK input USB 5V Vi Low Level Input 1 8V input Von High Level Output VoL Low Level Output RS 232 I O Vin High Level Input Vi Low Level Input Vou High Level Output 2 5V output lon 1mA LVDS_ xxx VoL Low Level Output 2 5V output lo 1mA Von High Level Output VoL
23. r condition that if not strictly followed may result in personal injury or damage to the equipment that may impede product performance WARNING A warning is intended to alert the user to the presence of potentially harmful circumstances and provide precautionary guidance for mitigating risk of personal injury and or damage to the product NOTE A note is a statement that clarifies or is used to emphasize important information Read all instructions Keep these instructions for future reference Follow all instructions Heed all warnings Do not submerge this apparatus in liquid of any kind Clean per recommended instructions using dry non abrasive cloth Ss sor Do not install near any sources of intense heat such as radiators furnaces stoves or other apparatus that regulary produce excessive heat 8 Refer all servicing to qualified service personnel O N Tamarisk 640 Electrical ICD DRS Technologies ll Ge PE This document describes the electrical interfaces for the Tamarisk 40 line of 17um LWIR OEM Modules and unless otherwise noted this document describes all configurations of the module Software and mechanical support documentation are described in separate documents See Reference Documentation for a complete listing The Tamarisk 649 product name identifies a family of long wave infrared video cameras with a 17um pixel pitch 640 x 480 sensor array and comes in two basic configurations Base and Base F
24. t 640 Pixels gt Figure 12 Parallel Digital Video Horizontal Timing Diagram Figure 13 illustrates the Parallel Digital Interface s vertical timing The BDSI_FSYNC signal will go low between each frame of video data to indicate that the next line of video received while the BDSI FSYNC signal is high 1s the first line of the next video frame The BDSI_FSYNC signal will go high at least one clock before the BDSI_LSYNC signal goes high front porch The BDSI FSYNC signal will go low at least one clock after the BDSI LSYNC signal goes low for the last line of a frame back porch It is intended for the user to sample these signals with the BDSI PCLK signal The vertical blanking time will vary between operating modes and camera release a One Video Frame gt BDSI FSYNC SS H Blanking nel BDSI LSYNC Line Line Line Line Line Line Line Line Line Line BDSI DATA 13 0 480 141 2 3 4 5 477 478 479 480 lt 480 Lines gt Figure 13 Parallel Digital Video Vertical Timing Diagram The default mode on the base configuration will drive RS 170 digital encoding designed to drive a video codec for example AD9705 digital to analog convert
25. volts direct current video graphics array Vanadium Oxide width or Watt micron micrometer Tamarisk s4o Electrical ICD gt DRS Technologies REFERENCE DOCUMENTATION The following documents form part of this specification In the event of a conflict between documents referenced herein and the contents of this specification the contents of this specification shall be considered a superseding requirement Document No Document No Document No Document No 1014853 Tamarisk 649 User Manual 1014844 Tamarisk 649 Software Interface Control Document 1014846 Tamarisk 649 Camera Control Software User Guide 1010056 Tamarisk 649 Mechanical Interface Control Document O N Tamarisk 640 Electrical ICD DRS Technologies SAFETY INSTRUCTIONS NOTIFICATIONS CAUTION WARNING AND NOTE The following is a list of notifications and their accompanying symbol that may be found throught this document to alert the reader to potential risks and to minimize the potential for personal injury and or damage to the product When a notification is present it is important that the user review and understand all statements related to the notification before proceeding If questions arise please contact your authorized dealler or DRS Technologies Notifications are preceeded by a symbol and followed by highlighted text Three types of notifications are typically used and are defined below A CAUTION A caution is a procedure practice o
26. ytics to analyze the pre AGC data so additional overlays can be added to the YCbCr data stream by customer analytics Figure 10 depicts a YUV Superframe line The first Cb and Cr data is generated on the average of the first two pixels The second Cb and Cr data is generated on pixels 3 and 4 with all further Cb Cr pairs calculated in a relative manner The Pre AGC data is LSB aligned so if the Pre AGC data is only 14 bits it will only occupy the lower 14 bits of the data path respectively 17 iy 1 me a Tamarisk 640 Electrical ICD DRS Technologies 1 Line of Data y ly PTP ylyiy yyy y Y eaa EEE EEEE rr S AE E ae EAE E E RS ani 9 0 E ee Ee espe AJA m u AJA AJ A A unu GIG GIGIGIGIG CIC CAEC IRC IEC MEC IEC IEC IEC CIiCiclcleicic 6 6 Oya op em o os pl paola pas 314 910 Figure 10 YUV Line Format 3 2 PARALLEL DIGITAL VIDEO INTERFACE The digital video interface can operate in one of three modes 1 Parallel Video mode 2 RS 170 Video mode 3 YUV Superframe mode The Parallel Video mode provides a pixel output clock Line Sync Frame Sync and 14 bit data This mode is used to directly interface to another digital interface 1 e a processor such as https www leopardimaging com Thermal IP Camera Dev Ki html The parallel digital video interface supports 8 or 14 bit digital video data Any post AGC selected video will be 8 bit dat
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