PCI-1712 PCI
Contents
1. Conversion Time 500 ns 1 LSB monotonic Max Transfer Rate Counter Timer Channels Resolution 16 bit Compatibility TTL level Max Input Frequency 10 MHz BASE Clock 10 MHz 1 MHz 100 KHz 10 KHz Clock Input Low 0 8 V max High 2 0 V min Gate Input Low 0 8 V max High 2 0 V min Counter Low 10 5 V max 24 mA High 2 0 V min 15 mA Trigger Mode Digital Input Output Input Number of Channels 16 ports 2 8 ch port 0 8 V max High 2 0V min Power Consumption oino 0 5 V max 24 High 2 4 V min 15 mA Operation Temperature refer to IEC 68 2 1 2 mA sink Note The sampling rate depends on the computer hardware architecture and software environment The rates may vary due to programming language code efficiency CPU utilization and more 5 14 ENR source Storage 20 85 C 4 185 F Relative Humidity 5 95 RH non condensing refer to IEC 68 2 3 Certification CE certified PCI 1712 PCI 1712L Ordering Information PCI 1712 PCI 1712L PCLD 8712 PCL 10168 ADAM 3968 1MS s 12 bit High speed Multifunction Card user s manual and driver CD ROM cable not included 1MS s 12 bit High speed Multifunction Card w o AO user s manual and driver CD ROM cable not included Indu2. PCI 1712 maem PCI 17121L a PCl bus mastering for data transfer 16 single ended 8 differential or a combination of analog inputs 12 bit A D converter with up to 1 MHz sampling rate Pre post about and delay trigger data acquisition modes for analog input channels Programmable gain for each analog input channel Automatic channel SD BU scanning Onboard FIFO buffer storing up to 1K samples for A D and 32K samples for D A Two 12 bit analog output channels with continuous waveform output function Auto calibration of analog input and output channels 16 digital input and output channels Three 16 bit programmable multifunction counter timers on 10 MHz oN N The PCI 1712 1712L is a powerful high speed multifunction card for the PCI bus It features a 1 MHz 12 bit A D converter an onboard FIFO buffer storing up to 1 K samples for A D and up to 32 K samples for D A conversion The PCI 1712 provides a total of up to 16 single ended or 8 differential A D input channels or a mixed combination two 12 bit D A output c c functions for different user requirements Specifications Analog Output Channels 2 og Lah Resolution 12 bit FIFO Size 32 K samples Channels 16 Single Ended or 8 Differential or Combination Resolution 12 bit FIFO Size 1 K samples Multi channel single gain 1 MS s Multi channel multi gain 600 KS s Multi channel multi gain unipolar bipolar 400 KS s Common mode 11 V max
3. and pulse width measurement AD ANTECH IPPC amp AWS ATM DA amp C cPC ADAM 3000 eConnectivity ICOM Software UNO 2000 3000 VBOX ADAM 4000 ADAM 5000 ADAM 6000 ADAM 8000 2 15
4. voltage operational Gain 2 4 8 i Unipolar 0 10 0 5 0 25 0 125 Bipolar 5 2 5 1 25 0 625 Gain 1 2 4 8 Drift Zero p V C 30 30 30 30 Gain ppm C 30 30 30 30 Small Signal Gain 1 2 4 8 Bandwidth for PGA Bandwidth 4 0 MHz 4 0 MHz 2 0 MHz 1 5 MHz 0 65 MHz Max Input voltage 20 V Input Protect 30 Vp p Input Impedance 100W 10pF Off 100W 100pF On Software On board Programmable Pacer or External Pre trigger Post trigger Delay trigger About trigger DNLE 1LSB INLE 1LSB Offset error lt 1LSB Gain 0 5 1 2 4 8 Accuracy Gain Error crsa 2 15 003 003 0 05 o1 SNR 68 dB ENOB 11 bits THD 75 dB typical General 1 0 Connector Type 68 pin SCSI II female Dimensions 175 mm x 100 mm 6 9 x 3 9 Typical 5 V 850 mA 12 V 600 mA Max 5 V 1A 12 V 700 mA 0 60 C 32 140 F Operation mode Single output continuous output waveform output Using Internal Output Range e O 45V 0 10 V 5 5 V 10 10 V Internal amp External Reference Max Sampling Rate Using External 0 xV xV 10 lt x lt 10 Reference X X V xV 10 lt x lt 10 Relative 1 LSB Accuracy Differential Non linearity Offset lt 1 LSB Slew Rate 20 V us Drift 10 ppm C Driving Capability 10 mA Single Channel 1 MS s max for FSR Dual Channel 500 KS s max for FSR Output Impedance Max Digital Update Rate 5 MHz settling Time 2 us to 1 2 LSB of FSB
5. g action both in the available trigger modes and trigger events for analog input You can acquire data using post trigger pre trigger delay trigger and about trigger modes The trigger source could be either an analog or digital signal The analog trigger could originate from a dedicated input pin In fact you can designate any of the analog input channels as the analog trigger input You can set the analog trigger level within a voltage range from zero to A D FSR With the trigger signal being digital you can pace A D and D A conversion using software interrupt internal or external clock Continuous Analog Output PCI 1712 only The PCI 1712 provides two analog output channels Both of them can perform continuous waveform output The analog output can be up to 500 kS s for each analog output channel Or you can load a cyclic waveform into an onboard FIFO which will continuously output the cyclic waveform The onboard FIFO of the PCI 1712 can store 2 to 32K samples of the waveform On board Programmable Multifunction Counter Timer The PCI 1712 1712L is equipped with 3 programmable multifunction counter timers which can serve as a pacer trigger for A D conversion The counter chip is an 82054 Or equivalent which incorporates three 16 bit channels on a 10 MHz clock And then we enhance the gate and clock input function for more applications of event counting pulse generation duty cycle frequency generation one shot frequency measurement
6. put and analog output By setting aside a block of memory in the PC the PCI 1712 1712L performs bus mastering data transfers without CPU intervention setting the CPU free to perform other more urgent tasks such as data analysis and graphic manipulation The function allows users to run all 1 0 functions simultaneously at full speed without losing data Plug and play Function The PCI 1712 1712L is a Plug and Play device which fully complies with the PCI specification Rev 2 2 During card installation you have no need to set any jumpers or DIP switches Instead all bus related configurations such as base 1 0 address and interrupt are automatically done by the Plug and Play function On board FIFO Memory The PCI 1712 1712L provides an on board FIFO First In First Out memory buffer storing up to 1K samples for A D and 32K for D A conversion PCI 1712 only Automatic Channel Gain SD BU Scanning PCI 1712 1712L features an automatic channel Gain SD BU scanning circuit This circuit controls multiplexer switching during sampling in a way that is much more efficient than software implementation Onboard SRAM stores different gain SD and BU values for each channel This combination lets users perform multi channel high speed sampling with different gain SD and BU values for each channel SD Single Ended Differential BU Bipolar Unipolar Flexible Triggering and Clocking Capabilities The PCI 1712 1712L provides flexibility in triggerin
7. strial Wiring Terminal Board for DIN rail mounting cable not included 68 pin SCSI II cable with male connectors on both ends and special shielding for noise reduction 1 and 2 m 68 pin SCSI II Wiring Terminal Board for DIN rail Mounting Pin Assignment Alo Al2 Al4 Al6 Al8 Al10 Al12 Al14 AIGND AOQ0_REF AO0_OUT AOGND AI_CLK DGND AO_CLK CNTO_CLK CNTO_OUT CNT1_CLK CNT1_OUT CNT2_CLK CNT2_OUT DIOO DIO2 DIO4 DIO6 DGND DIO8 DIO10 DIO12 DIO14 DGND Al_TRG_OUT All Al3 Al5 Al7 Al9 Al11 Al13 Al15 ANA_TRG AQ1_REF AOQ1_OUT AOGND Al_TRG DGND AO_TRG CNTO_GA TE DGND CNT1_GA TE DGND CNT2_GA TE DGND DIO1 DIO3 DIO5 DIO7 DGND DIO9 DIO1 1 DIO13 DIO15 DGND Al_CLK_OUT Pin 20 22 25 54 56 59 are not defined on PCI 1712L Block Diagram Al_TRG 40MHz PCI9 54 OSC Trigger and PCI Interface Control Logic AO_TRG lt CLK 3 0 gt 8 bit D A Compare Analog Trigger 3 User 16 bit GATE 3 0 gt Timer Counter OUT 3 0 ANA_TRG 2 m lt Bidierctional S Al 15 0 DIO 7 0 gt and Latched k 8 bit DIO Al_CLK Bidierctional K ae DIO 15 8 lt gt bean tg FIFO 12 bit DIA gt 7 AO 1 0 A LO o AO_CLK Online Download PCl bus Mastering Data Transfer The PCI 1712 1712L supports PCl Bus mastering DMA for high speed data transfer and gap free analog in
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