NAMC-STM1_4_manual
Contents
1. Temux84 C 63 x E1 84 x T1 Mapper MUX Temux84 D 63 x E1 84 x T1 Mapper MUX Timing Reference Reference Clock Time ITDM H 110 TSI Lattice SCM FPGA Mangement local Bus Stratum 3 PLL Clock ZL30410 Master Version 1 3 N A T GmbH NAMC STM1 4 Technical Reference Manual 1 1 Board Features 1 1 1 FPGA The central component on the NAMC STM1 4 is a Lattice SCM FPGA SCM40 or SCM80 This device features built in SerDes units used to realize the physical layer of the PCIe and the GbE interfaces as well as a structured ASIC region used to implement the higher layers of the PCle interface The logic resources are used to realize the 1TDM engine along with the management interface and further functionality related to the SDH chipset 1 1 2 SDH Interfaces The STM1 4 OC3 12 interface consists of the Fiber Optic interface and the Sonet SDH framer The PMC Sierra device Arrow 155 is used as Sonet SDH framer for the STM1 option the Arrow 622 as framer for the STM4 option The Arrow 155 is a single port Sonet SDH framer supporting the OC 3 STM 1 data rates The Arrow 155 terminates section line and path overhead of both the STS n AU 4 level and the TU 3 level On the line side it incorporates a SERDES allowing it to mate directly to an optics module The system side interface is an 8 bit multi drop parallel Telecom bus allowing multiple de2. 5 3 Connector JP1 IPMI uC Programming Port Connector JP1 connects the programming port of the Atmel AVR uC device Table 6 Atmel AVR Programming Port Pin No Signal 6 GND 5 4 Connector JP2 Lattice FPGA programming port Connector JP2 connects the JTAG or programming port of the Lattice FPGA device Table 7 Lattice programming port PROGRA TCK 8 9 DONELAT JANITLAT 10 S me TMS J6 Version 1 3 N A T GmbH 25 NAMC STM1 4 Technical Reference Manual 5 5 Connector JP3 JTAG connector This JTAG port connects to the JTAG interfaces of the Arrow and Temux devices which are configured in a daisy chain Table 8 JTAG Connector Pinout me 6 ne 9 TDI GND 0 5 6 Hot Swap Switch SW1 Switch SW1 is used to support hot swapping of the module It conforms to PICMG AMC 0 5 7 The Front Panel Connectors S1 S2 The two optical front panel connectors have standard SC plugs and can be equipped with either singlemode or multimode transceivers Version 1 3 N A T GmbH 26 NAMC STM1 4 Technical Reference Manual 6 NAMC STM1 4 Programming Notes The FPGA on the NAMC STM1 4 realizes the interface to the onboard devices and an 1TDM to TDM conversion engine The table below shows the memory map for the logical sub blocks of the design Refer to the following sub chapters for detailed information All devices shown in this memory map can be accessed either via PCIe or v
3. It is also designed to meet the requirements of uTCA systems General features Dual Optical Interface for STM1 4 OC3 12 at 155 622 Mbit sec Add Drop Multiplexer for up to 4 63 252E 1 4 84 336T1 Channels 63 El Framers or 84 T1 Framers per Temux device up to 4 assembled Multiplexer cross connect between STM1 4 E1 T1 payload timeslots and TDM timeslots capacity limited to one STM4 1 Lane PCI Express Interface Rev 1 1 1000BaseBX 1TDM Interface H 110 alike Backplane TDM bus Configuration Control via PCle or via Ethernet Features of the Line Interface Circuits Clock recovery and jitter attenuation Line and path performance monitoring Features of the TDM circuit Options Version 1 3 Flexible routing of any time slot between each of the framers and the IDM controller Capacity of up to 8192 timeslots Single or Dual Optical Interface Single or Multi Mode optical Transceiver Monitoring Version dual add drop multiplexer for concurrent Rx Tx monitoring N A T GmbH 8 NAMC STM1 4 Technical Reference Manual Figure 1 shows a detailed block diagram of the NAMC STM 1 4 Figure 1 Rings A amp B 155 622 MBit Fiber Optic 0C3 12 Phy Arrow 155 Arrow 622 NAMC STM1 4 0C3 12 Phy Arrow 155 Arrow 622 Telecom Bus Temux84 A 63 x E1 84 x T1 Mapper MUX Temux84 B 63 x E1 84 x T1 Mapper MUX NAMC STM1 4 Block Diagram
4. The NAMC STM1 4 implements an IPMB interface which conforms to the AMCO O specification The NAMC STM1 4 implements an 8 bit TDM interface similar to H 110 The same throughput as with a complete H 110 bus is achieved by clocking the 8 backplane TDM lines with 32 768 MHz Thus every frame consists of 512 timeslots per line The purpose of this TDM backplane bus is to establish private TDM links to adjacent modules The TDM interface is implemented in FPGA logic The TDM interface connects to ports 12 13 data and port 14 Sync of the Common Options Region of the AMC connector N A T GmbH 11 NAMC STM1 4 Technical Reference Manual 1 2 Board Specification AMC Module Front I O Power consumption Environmental conditions Standards compliance Version 1 3 Table 2 NAMC STM1 4 Features standard Advanced Mezzanine Card single width double height Two optical 155 622Mbps OC 3 12 STM 1 line interfaces 12V 1 3A max Temperature operating 0 C to 50 C with forced cooling Temperature storage 40 C to 85 C Humidity 10 to 90 rh noncondensing PICMG AMC Rev 2 0 PICMG AMC 1 Rev 1 0 PCI Express Base Specification Rev 1 1 PICMG SFP 0 Rev 1 0 System Fabric Plane Format PICMG SFP 1 Rev 1 0 Internal TDM IPMI Specification v2 0 Rev 1 0 PICMG TCA 0 Rev 1 0 N A T GmbH 12 NAMC STM1 4 Technical Reference Manual 2 Installation 2 1 Safety Note To ensure proper functi
5. A A eee A A E A A A OS eee A A A A IO E OS Version 1 3 O N A T GmbH 37
6. clocking functionality concerning the AMC backplane clock ports Clock 1 Clock 3 AMC backplane clock port Clock 1 is connected to the FPGA in order to be used as a Telecom standard clock Clock 1 1s only received AMC backplane clock port Clock 2 is connected to the FPGA in order to be used as a Telecom standard reference Clock 2 may be received from or transmitted to the backplane in order to become the reference clock for the entire system AMC backplane clock port Clock 3 is connected to the PCIe interface in order to be used as a reference clock for PCI Express Clock 3 is only received Clock 3 is routed to a multiplexer which allows programming the clock source of the PCle line to be either Clock 3 or an internal differential 100 MHz reference clock In case clock 3 is to be used for a different functionality it also feeds the FPGA and may be used there for any suitable purpose Version 1 3 N A T GmbH 18 NAMC STM1 4 Technical Reference Manual 3 4 IPMB Interface The NAMC STM1 4 implements an IPMB interface consisting of an ATMegal68 microcontroller and a couple of I2C devices such as a temperature sensor and an EEPROM The IPMB controller manages also the hot swap functionality and the geographical address as requested by the AMC specification 3 4 1 FC Devices Three I C busses connect to the IPMI controller The first one is the IPMB bus of the AMC connector and the two other interface various local d
7. product or the documentation In particular N A T will not be responsible for any direct or indirect damages including lost profits lost savings delays or interruptions in the flow of business activities including but not limited to special incidental consequential or other similar damages arising out of the use of or inability to use this product or the associated documentation even if N A T or any authorized N A T representative has been advised of the possibility of such damages The use of registered names trademarks etc in this publication does not imply even in the absence of a specific statement that such names are exempt from the relevant protective laws and regulations patent laws trade mark laws etc and therefore free for general use In no case does N A T guarantee that the information given in this documentation is free of such third party rights Neither this documentation nor any part thereof may be copied translated or reduced to any electronic medium or machine form without the prior written consent from N A T GmbH This product and the associated documentation is governed by the N A T General Conditions and Terms of Delivery and Payment Note The release of the Hardware Manual is related to a certain HW board revision given in the document title For HW revisions earlier than the one given in the document title please contact N A T for the corresponding older Hardware Manual release Ver
8. written into the FPGA upon power up by the IPMI uC Table 31 AMC Site Number AMC LEDs Address 0x01e Default value 0x0000 faces ROR AMC Site Number Version 1 3 N A T GmbH 33 NAMC STM1 4 Technical Reference Manual 6 1 2 FPGA GbE TDM Configuration Figure 4 shows a block diagram of the 1TDM FPGA implemented on the NAMC STM1 4 For configuration and programming of the GbE ATDM block please refer to the N A T 1TDM FPGA Manual Appendix A 4 NDA required Organisation of the 1 TDM FPGA GbE l T DM Block Eth Tx Frame Tx FIFO A Assembly Connection Figure 6 Legacy TSI Conn eee Data Mem Mem SBI Par Ser bus Ser Par Control Ponie Y Eth Rx Frame Disassembly The TDM Channel ID for a certain El timeslot is calculated the following way Legacy TDM bus SBI bus ch_id E1_TS 63 El 4 STM GbE Interface PCle Interface PCle Port0 1 GbE Port4 8 PCIe If the SBI bus logic is configured for T1 mode the Channel ID for a certain T1 timeslot is calculated this way ch_id T1_TS 84 T1 4 STM Table 32 SBI bus Timeslot Parameter Number of the El Link Ranging from 0 to 62 N
9. 0 Version 1 3 N A T GmbH 16 NAMC STM1 4 Technical Reference Manual 3 Functional Blocks The NAMC STM1 4 can be divided into a number of functional blocks which are described in the following paragraphs 3 1 1 FPGA The FPGA implements the following functional blocks Logic to interface the SBI bus clock management for the SDH chipset 1TDM controller with GbE PCIe interface for management Management over GbE Legacy TSI between SBI timeslots and backplane TDM bus 3 1 2 PCI Express Interface The NAMC STM1 4 includes a 1 lane PCI Express interface This is implemented in the Lattice SCM FPGA The PCIe interface may receive its reference clock either from the Clock 3 port of the AMC backplane connector or from a local 100 MHz oscillator circuitry default The clock source is programmable 3 1 3 Backplane Ethernet The backplane Ethernet interface implemented within the FPGA can be switched to operate on AMC Port O or Port 1 for redundant operation Within FPGA logic the Type P Control Path data is multiplexed with the 1TDM data and transferred through the same physical port By default the LIU is programmed to connect to Port O of the Common Options Region of the AMC backplane connector It can also be programmed to connect to Port 1 in order to support a redundant uTCA system 3 1 4 TDM The 1TDM controller within the FPGA can be used to transfer any of the SDH timeslots via GbE packets It supports mixed oper
10. 2 6 1 1 15 AMC Clock Output RESSE ea Mahalia aon 33 6 1 1 16 AMC S te INGA A O nee II Dutch a test es dese bods 33 0 42 T PGA GOFATDM CONN BUTONO evs ch essen sassy hed Se iA 34 7 KNOWN BUGS TRES PRICTIONS os ida 35 APPENDIX A REFERENCE DOCUMENTA TION wissccedeccccccesscsscsscescdscccsusecedsaccoscesesceseecsssssossessssccescesscesestes 36 APPENDIX B DOCUMENTS HISTOR No A nes lee deteste tee 37 List of Tables Table 1 Liro rused AD DIC VIA ONS re Le nc dr ne 7 Table 2 NAME S TNT 1 4 Fedre S ini 12 Table 3 AMC PODEM a hoses eta 20 Table 4 LED Elmo Ros 21 Table 5 AMC COMMS COD Lena 23 Table 6 Atmel AVR Programmine PIO td i 25 ADI Lace PROS MAMIE DOC ne nn nt a oeil 25 Table 8 TLAG Connector PIONEER haha ais 26 Table9s EPGA Memory Di ets Senet eh She 24 Table 10 BOB Version Resio ii distante tait 28 Tables ERGA Version REISE ani a Ait ci dites 28 Table 127 PPGAID RES E dure a 28 Table 15 FPGA TDS Ree is 28 Table 147 FPGA BOARD TD Re Ri OA 29 Tabla USE Status Recio cio 29 Tableto TIRO Stages RE S UC 0 ua a 29 Table LE TIRO Enable Recien aca 29 Tables RPG A Reset RESISTEN aiii 30 Table 19 GREBDS Re er ini 30 Table 20 GALED Vanesa T cela 30 Version 1 3 N A T GmbH 5 NAMC STM1 4 Technical Reference Manual Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 AMC LEDSRE er a nement 30 AMC LEDS AU
11. DERNITION a oa a a a oe DE a a o a vues Un 20 4 2 ERONTRANELAND LEDS a a ea a a dde a aD Br ete 21 5 CONNECTORS un nn Mn nn canino eara 22 5 1 CONNECTOR OVERVIEW sad o oo 22 52 AMC CONNECTOR T ind A A 23 a2 CONNECTOR JP1 IPMI uC PROGRAMMING PORT ccccccceecccsecceccescceeceecceucseueceeeceeseseseseeceusesuees 25 5 4 CONNECTOR JP2 LATTICE FPGA PROGRAMMING PORT cccceccseccsccceccesceucccsccesceccesscuscescsesceussensees 25 Sa CONNECTOR JP3 JTAG CONNECTOR cuina ica 26 Version 1 3 N A T GmbH 4 NAMC STM1 4 Technical Reference Manual 5 6 HOT SWAPS WITCH OWL ula A dt date TAA 26 Dl THE FRONT PANEL CONNECTORS S1 S2 ia ca iso 26 6 NAMC STM1 4 PROGRAMMING NOTES cccssccccssscccsssscccsscccccsscccccsccccccsccccccscccceccccccscccceecccoss 21 Call PPGAIGP RRE STO TUS AA AA A A ant 28 6 1 1 1 PCB Version Register vais tr 28 6 1 1 2 FPO S Vernon ROSIE foal d E lidad 28 6 1 1 3 EPG ATID ERESSE aenea e E ecb eas moi 28 6 1 1 4 GARD Z RE SI EEE oleo 28 6 1 1 5 FPGA BOARD ID Register iii sn nan Nan nan nero lei 29 6 1 1 6 PUSAS Ty lore til secant wecmuay dane tater 29 6 1 1 7 EROS Cat SRG Strait idad 29 6 1 1 8 IRO Papi RE Gister a a A A ie 29 6 1 1 9 FEGA Reset REIS E A A E A O 30 6 1 1 10 GP LEDS Resiste E A A A des 30 6 1 1 11 AMC LEDS RE ta R ENEE lisent eee 30 6 1 1 12 PCE COMORES IST ennau AA A a nou 31 6 1 1 13 MSC CIO Connie RELSE Ee e da obli 32 6 1 1 14 SBFb s Mode Resister as 3
12. MB uC and the green and yellow one being controlled via FPGA registers Figure 4 Front Panel 4xgreen 4 O O yellow Port O Port green A B O red O Table 4 LED Functionality Function no default functionality can be controlled by software no default functionality can be controlled by software no default functionality can be controlled by software 4 Version 1 3 N A T GmbH 21 NAMC STM1 4 Technical Reference Manual 5 Connectors 5 1 Connector Overview Figure 5 Connectors of the NAMC STM1 4 GP LEDs LMS Please refer to the following tables to look up the connector pin assignment of the NAMC STM1 4 Version 1 3 N A T GmbH 22 NAMC STM1 4 Technical Reference Manual 5 2 AMC Connector J1 Version 1 3 Table 5 AMC Connector J1 AMC Signal AMC Signal 6 RESVD__ TCK i65 8 RESVD SPISEL 163 9 PWR SPICIK 162_ O N A T GmbH 23 NAMC STM1 4 Technical Reference Manual AMC Signal AMC Signal 52 53 4 117 5 116 6 115 7 114 58 113 112 111 110 109 108 107 106 105 104 103 102 0 101 71 100 2 3 4 5 6 TI Do GND GND 98 97 95 94 CLK_2_N 93 Version 1 3 N A T GmbH 24 NAMC STM1 4 Technical Reference Manual AMC Signal AMC Signal Pin No 80 CIK3P PETOPP8 9 81 CIK3N PETON_P8 90 82 GND___ GND__ 389 85 GND _ GND 36
13. NAMC STM1 4 Technical Reference Manual NAMC STM1 4 Telecom AMC Module Technical Reference Manual V1 3 HW Revision 1 4 NAMC STM1 4 Technical Reference Manual The NAMC STM1 4 has been designed by N A T GmbH Kamillenweg 22 D 53757 Sankt Augustin Phone 49 2241 3989 0 Fax 49 2241 3989 10 E Mail support nateurope com Internet http www nateurope com Version 1 3 N A T GmbH 2 NAMC STM1 4 Technical Reference Manual Disclaimer The following documentation compiled by N A T GmbH henceforth called N A T repre sents the current status of the product s development The documentation is updated on a regular basis Any changes which might ensue including those necessitated by updated speci fications are considered in the latest version of this documentation N A T 1s under no obli gation to notify any person organization or institution of such changes or to make these changes public in any other way We must caution you that this publication could include technical inaccuracies or typographi cal errors N A T offers no warranty either expressed or implied for the contents of this documentation or for the product described therein including but not limited to the warranties of merchant ability or the fitness of the product for any specific purpose In no event will N A T be liable for any loss of data or for errors in data utilization or processing resulting from the use of this
14. RefClock 0x0 Local 77 76MHz oscillator 0x1 77 76MHz from PLL 6 1 1 14 SBI bus Mode Register This register holds the configuration bits for the SBI bus interface within the FPGA Table 27 SBI bus Mode Register SBI bus Mode Address 0x10a Default value 0x0000 peat value 0000 PA Ee ee ee ee ee ee Pasos ESO E ESO ESA A EE A ER ESA EURE ES Func reserved Tir nable Table 28 SBI bus Mode Register Bits Bit Function 1 SBI_T1_Ena Writing this bit to l makes the SBI bus timeslot ble accessible that are used in T1 mode A 0 makes the El timeslots accessible Version 1 3 N A T GmbH 32 NAMC STM1 4 Technical Reference Manual 6 1 1 15 AMC Clock Output Register Each nibble within this register controls whether one of the four telecom AMC clocks is being driven and with which source Note the different naming schemes TCLKA equals AMC_CLK1 TCLKB equals AMC_CLK2 Table 29 AMC Clock Output Register ACM CIk Output Address 0x10e Default value 0x0000 EA A a AA RI TCLKB_OSEL TCLKA_OSEL AS IEEE URLS AMC_CLK2_OSEL AMC_CLK1_OSEL Table 30 AMC Clock Output Register Bits Name Function Selector for the respective clock output 0x0 do not drive clock Ox1 drive with 8kHz 0x2 drive with 19 44MHz 0x3 drive with 2 048 MHz others drive with 8kHz 6 1 1 16 AMC Site Number This register displays the AMC Site number the module is in This information is
15. S tia tada 31 PELEContolhke Se Eon 31 PELControls Register Bits cias 31 Mise Clock Conte Resist ii 32 Mise Clock Config Resister Blind id tic 92 SBI b s Mode RESISTE AA AAA 32 SBl b s Mode Resister BIS siii 32 AMCC lock Output ROIS ceara E AE 33 AMC Clock Output Resister Bits an e E ed a 33 AME Sue INU arde 33 S BI DUS Timneslot Parade 34 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Version 1 3 NAMC STM 1 4 Block Diaria it 9 Organisation of the TTDM FPGA uo is 17 PC Str ct re of the NAMC STM PA ido 19 Front Panel sn CS NS Se Pi di sn 21 Connectors of thes NAMES TM is ans an eu ane dre 22 Organisation of the TDM FPGA oooooocccnnncncncncnnonononcnonoconnnoconncnnnnnnnonaconnnncnonoss 34 N A T GmbH 6 NAMC STM1 4 Technical Reference Manual Conventions If not otherwise specified addresses and memory maps are written in hexadecimal notation identified by Ox Table gives a list of the abbreviations used in this document Table 1 List of used abbreviations DDR Dual Data Rate S Line Interface Unit Random Access Memory Time Division Multiplex Time Slot Interchange Version 1 3 N A T GmbH 7 NAMC STM1 4 Technical Reference Manual 1 Introduction The NAMC STM1 4 is a high performance standard Advanced Mezzanine Card single width double height for SDH Sonet applications It can be plugged onto any ATCA carrier board supporting AMC standards
16. ation in either 125us mode or lms mode The capacity is limited to 8192 timeslots due to the available bandwidth of the GbE link Figure 2 Organisation of the i TDM FPGA 7 Ethernet Tx 7 lt _ p M Tx Control E Tx State Beare i to z Memory Machine FIFO 16 a S 8 GbE Control Register Set E lt ciocking TDM Block T Block 7_ FIFO 8 Rx Control Rx State Sar Memor Machine 16 y a Ethernet Rx 1 Memory E Version 1 3 N A T GmbH 17 NAMC STM1 4 Technical Reference Manual 3 1 5 Backplane TDM The NAMC STM1 4 implements an 8 bit TDM interface similar to H 110 The same throughput as with a complete H 110 bus is achieved by clocking the 8 backplane TDM lines with 32 768 MHz Thus every frame consists of 512 timeslots per line The purpose of this TDM backplane bus is to establish private TDM links to adjacent modules The TDM interface is implemented in FPGA logic The TDM interface connects to ports 12 13 data and port 14 Sync of the Extended Options Region of the AMC connector 3 2 SDH Line Interfaces The two optical 155 622Mbps OC 3 12 STM 1 line interfaces are available on two standard OC 3 12 SDH STM 1 SC comnectors at the front panel 3 3 AMC Clock Interface The NAMC STM1 4 implements a very flexible
17. ck this section for installation prerequisites and requirements 2 2 1 Requirements The installation requires only e an ATCA carrier board or a uTCA backplane for connecting the NAMC STM1 4 e power supply e cooling devices 2 2 2 Power supply The power supply for the NAMC STM1 4 must meet the following specifica tions e required for the module 12V 1 3A max 3 3V 0 15A max 2 2 3 Automatic Power Up In the following situations the NAMC STM1 4 will automatically be reset and proceed with a normal power up Voltage sensors The voltage sensor generates a reset e when 12V voltage level drops below 8V e when 3 3V voltage level drops below 3 08V or when the carrier board backplane signals a PCIe Reset Version 1 3 N A T GmbH 14 NAMC STM1 4 Technical Reference Manual 2 3 Statement on Environmental Protection 2 3 1 2 3 2 Compliance to RoHS Directive Directive 2002 95 EC of the European Commission on the Restriction of the use of certain Hazardous Substances in Electrical and Electronic Equipment RoHS predicts that all electrical and electronic equipment being put on the European market after June 30th 2006 must contain lead mercury hexavalent chromium polybrominated biphenyls PBB and polybrominated diphenyl ethers PBDE and cadmium in maximum concentration values of 0 1 respective 0 01 by weight in homogenous materials only As these hazardous substances are currently used wi
18. ctions 6 1 1 12 PLL Control Register The PLL Control Register configures the main 77 76 MHz Telecom clock configuration The status of the PLL can be read on the PLL Status register Please refer to the ZL304010 manual for detailed information Table 23 PLL Control Register PLL Control Address 0x106 Default value 0x0028 EA AI A e A IA E SRE ee E E PEA ES AE ESA AAA RAE SEAS E nasa oo on res AY mu Table 24 PLL Control Register Bits Moll ame Function a 12 al 1_Sel Selectors for each PLL s Reference Input 0x0 77 76MHZ Oscillator 0x1 Arrow_0 11 8 Ref0_Sel 0x2 Arrow_ 1 0x3 AMC_Clk_3 FCLK_A 0x4 AMC_Clk_1 TCLK_A 0x5 AMC_CIk_2 TCLK_B 0x6 TCLK_C 0x7 TCLK_D 2 1 Mode Main PLL Mode Selection 0x0 Normal Mode 0x1 Holdover Mode 0x2 Free running Mode 0x3 reserved RefSel Select Reference Input of PLL Input 0 or 1 Version 1 3 N A T GmbH 31 NAMC STM1 4 Technical Reference Manual 6 1 1 13 Misc Clock Config Register This register holds the bits to select from which source the Arrow framer chips shall take its reference and the configuration bit for the AMC clock setup Table 25 Misc Clock Config Register Misc Clock Config Address 0x108 a za ae ja fre pa pa ff fm pa fa je yor F rved reserved ALTOW unc reserve RefClock Table 26 Misc Clock Config Register Bits 1 0 Arrow Select Reference Clock for Arrow devices
19. evices The local devices all powered by IPMB power are an EEPROM 24C08 for storage of board specific information and a temperature sensor which is capable of reading the FPGA s die temperature The third local PC device is the hotswap controller of the NAMC STM1 4 Figure 3 PC Structure of the NAMC STM1 4 NAMC STM1 4 HotSwap Controller local 12c bus 2 EEPROM 24C08 re me local ATMega168 IPMB L 12c bus 1 uC Temp Sens Max6642 Version 1 3 N A T GmbH 19 NAMC STM1 4 Technical Reference Manual 4 Hardware 4 1 AMC Port Definition Basic Connector Extended Connector Version 1 3 Table 3 AMC Port Definition CLKI CLK3 Port AMC Port Mapping No Strategy CLKI Clocks Common Options Region 10 11 12 13 14 Extended Options Region 15 CLK4 5 18 19 20 O N A T GmbH Ports used as Reference Clock 1 Reference Clock 2 Reference Clock 3 TDM and Type P default TDM and Type P redundant TDM Bus DO 3 H 110 extended TDM Bus D4 7 H 110 extended optional clock lines H 110 extended y unassigned 20 NAMC STM1 4 Technical Reference Manual 4 2 Front Panel and LEDs The NAMC STM1 4 module is equipped with 4 LEDs which are software programmable They are mounted between the SDH connectors Additionally it features the standard four AMC LEDs with the red and blue LED being controlled by the IP
20. ia the so called Ethernet Control Interface This Interface uses a N A T proprietary protocol based on Layer2 Ethernet frames to perform memory mapped accesses via Ethernet Please refer to the Ethernet Control Interface Technical Reference Manual for further information 9 The MAC address of the NAMC STM 1 4 is build with the following scheme 00 40 42 14 XX XX with XXXX being the boards serial number in hexadecimal representation Table 9 FPGA Memory Map TemuxO S Temux 0 The FPGA Design consists of four main blocks e Misc board control and status registers and a register interface to access the FPGA s PROM Ethernet Control Interface Interface to Arrow and Temux Devices GbE MAC and frame preprocessing block 1 DM block Version 1 3 N A T GmbH 27 NAMC STM1 4 Technical Reference Manual 6 1 1 FPGA GP Registers Status This chapter describes the basic board control registers implemented within the FPGA Further register description will follow up in future versions of this manual 6 1 1 1 PCB Version Register The Version Register holds the PCB Revision encoded in two nibbles Table 10 PCB Version Register PCB Version Address 0x00 Default value 0x0011 Bit pe TA ews OR OR dT OR 6 1 1 2 FPGA Version Register The Version Register holds the FPGA Revision encoded in two nibbles Table 11 FPGA Version Register EE RA ews RRR 6 1 1 3 FPGA ID_1 Register This read only register ca
21. n be used by the device driver to probe register access Table 12 FPGA ID_1 Register acess OSCR 6 1 1 4 FPGAID 2 Register This read only register can be used by the device driver to probe register access Table 13 FPGA ID_2 Register FPGA ID 2 Address 0x06 Default value 0xDEAD Version 1 3 N A T GmbH 28 NAMC STM1 4 Technical Reference Manual 6 1 1 5 FPGA BOARD ID Register This read only register can be used by the device driver to probe register access It holds the N A T internal board id of the NAMC STM1 4 Table 14 FPGA BOARD_ID Register FPGA BOARD ID Address 0x08 Default value 0x0B06 C 6 1 1 6 PLL Status Register The bits within this register show the logical value of the Zarlink ZL304010 PLL status outputs Please refer to the ZL304010 manual for detailed information Table 15 PLL Status Register PLL Status Address Offset 0x0A Default value 0x0000 eae D A 6 1 1 7 IRQ Status Register This register displays the interrupt status line of all interrupt capable devices on the NAMC STM1 4 A value of 1 means that the respective interrupt is pending An IRQ transmitted via ECI Ethernet Control Interface is acknowledged and re armed by writing a 1 to the corresponding bit Table 16 IRQ Status Register A IA a SA ea ees e R R RO R RA 6 1 1 8 IRQ Enable Register This register holds the bits to enable the interrupts being pre
22. oning of the NAMC STM1 4 during its usual lifetime take the following precautions before handling the board CAUTION Electrostatic discharge and incorrect board installation and uninstallation can damage circuits or shorten their lifetime Version 1 3 Before installing or uninstalling the NAMC STM1 4 read this installation section Before installing or uninstalling the NAMC STM1 4 read the Installation Guide and the User s Manual of the carrier board used or of the uTCA system the board will be plugged into Before installing or uninstalling the NAMC STM1 4 on a carrier board or both in a rack Check all installed boards and modules for steps that you have to take before turning on or off the power Take those steps Finally turn on or off the power if necessary Make sure the part to be installed removed is hot swap capable if you don t switch off the power Before touching integrated circuits ensure to take all require precautions for handling electrostatic devices Ensure that the NAMC STM1 4 is connected to the carrier board or to the uTCA backplane with the connector completely inserted When operating the board in areas of strong electromagnetic radiation ensure that the module is bolted the front panel or rack and shielded by closed housing N A T GmbH 13 NAMC STM1 4 Technical Reference Manual 2 2 Installation Prerequisites and Requirements IMPORTANT Before powering up e che
23. sent in the IRQ Status Register Table 17 IRQ Enable Register Version 1 3 N A T GmbH 29 NAMC STM1 4 Technical Reference Manual 6 1 1 9 FPGA Reset Register The Reset Register is used to trigger a reset to the whole FPGA logic FPGA blocks or external devices Writing a 1 to a bit triggers the reset After reset the bit is self cleared to O Table 18 FPGA Reset Register RW Rw RW RW RW pane l Board IPMI uC Eth Cntr Int SPI Interf SBI bus TDM AON global Temux 6 1 1 10 GP LEDs Register This register is used to control the four general purpose LEDs on the AMC module front panel between the optical connectors The GP LEDs can be configured to the functionality listed below Table 19 GP LEDs Register GP LEDs Address 0x102 Default value 0x0000 Func GPLED4 GPLED3 GPLED2 GPLED1 Table 20 GP LEDs Values Value GP LED Functions 0x0 0x1 on 0x2 slow blink 0x3 fast blink others reserved 6 1 1 11 AMC LEDs Register This register is used to control the AMC LEDs 3 most upper yellow and 2 second from top green on the AMC module front panel Note the other two AMC LEDs LED 1 and LED blue are controlled by the IPMI uC Table 21 AMC LEDs Register AMC LEDs Address 0x104 Default value 0x0054 LED AMC LED AMC Version 1 3 N A T GmbH 30 NAMC STM1 4 Technical Reference Manual Table 22 AMC LED Values AMC LED Fun
24. sion 1 3 N A T GmbH 3 NAMC STM1 4 Technical Reference Manual Table of Contents LIST OFTABLES ececcswedessccesscsnssssesezecsnctevesesssneadstecetassewacuscaiadetenseucceedsieseeasusccasdewecevaeveadcescseeusdeeseadensdassdsvaceuesaaocs 5 ICES TOE FIG URES 0 00 A a A AA ii 6 CONVENTIONS ii iia 7 1 INTRODUCTION Suit iio cateo S 1 1 BOARD FEATURES 5 a 10 1 1 1 LE A A E de cu 10 EEZ DIAS as 10 LDS BACKPLANEIA CITO COS sn Gba teat dieu 10 1 2 BOARD SP CIFICATION Se NS NUS AS a side 12 2 INSTALLATION Se Sn te 13 2 1 SAFET NOR ER a a a a ee de it a 13 2 2 INSTALLATION PREREQUISITES AND REQUIREMENTS cseccsccsccsscsccsccscesccsscsscescescessessessescuscescencs 14 Lh KCJ ETUS ASS AS SA A a idee Hi 14 Di WOWEP SUD DULY dd 14 22 AOC OWE UP dd 14 2 3 STATEMENT ON ENVIRONMENTAL PROTECTION cccccscccsccssccscccsccscenccescescenccessesseuscesseuscesscussenscs 15 2 31 Complianceto ROHS DUECUVE Dad 15 25 2 COMPUANCE to WELE DITOCNVE SSSR da en nn nd 15 2 Comphance to CE DIC CVC RL EO RE Ona Heroes 16 Dak POUR OO RE RU Re 16 3 FUNETTIONALE BLOCKS SR Sn nn ne 17 3 1 1 D e o do ER dia gt PEL EX PTESS ART ACELERA RES 17 HL Backplane ETERNO A A A dd 17 PT A O A E E O 17 Sel DOCRDIQNRE LME nu eat AAA A RNA A A EA 18 3 2 SDELULINE INTERFACE osar riot AR de 18 3 3 AMC CLOCK INTERFACE custodiada 18 3 4 PME INTER BC eased natos 19 Al TCD ea e a a a tion a 19 4 TARDWARE St Ne ou seueaOSS 20 4 1 AMOC PORT
25. ste of private persons and households has to be handled by the supplier manufacturer however it allows a greater flexibility in business to business relationships This pays tribute to the fact with industrial use electrical and electronical products are commonly integrated into larger and more complex environments or systems that cannot easily be split up again when it comes to their disposal at the end of their life cycles Version 1 3 N A T GmbH 15 NAMC STM1 4 Technical Reference Manual As N A T products are solely sold to industrial customers by special arrangement at time of purchase the customer agreed to take the responsibility for a WEEE compliant disposal of the used N A T product Moreover all N A T products are marked according to the directive with a crossed out bin to indicate that these products within the European Community must not be disposed with regular waste If you have any questions on the policy of N A T regarding the Directive 2002 95 EC of the European Commission on the Restriction of the use of certain Hazardous Substances in Electrical and Electronic Equipment RoHS or the Directive 2002 95 EC of the European Commission on Waste Electrical and Electronic Equipment WEEE please contact N A T by phone or e mail 2 3 3 Compliance to CE Directive Compliance to the CE directive is declared A CE sign can be found on the PCB 2 3 4 Product Safety The board complies with EN60950 and UL195
26. th semiconductors plastics 1 e semiconductor packages connectors and soldering tin any hardware product 1s affected by the RoHS directive if it does not belong to one of the groups of products exempted from the RoHS directive Although many of hardware products of N A T are exempted from the RoHS directive it is a declared policy of N A T to provide all products fully compliant to the RoHS directive as soon as possible For this purpose since January 31st 2005 N A T is requesting RoHS compliant deliveries from its suppliers Special attention and care has been paid to the production cycle so that wherever and whenever possible RoHS components are used with N A T hardware products already Compliance to WEEE Directive Directive 2002 95 EC of the European Commission on Waste Electrical and Electronic Equipment WEEE predicts that every manufacturer of electrical and electronical equipment which is put on the European market has to contribute to the reuse recycling and other forms of recovery of such waste so as to reduce disposal Moreover this directive refers to the Directive 2002 95 EC of the European Commission on the Restriction of the use of certain Hazardous Substances in Electrical and Electronic Equipment RoHS Having its main focus on private persons and households using such electrical and electronic equipment the directive also affects business to business relationships The directive is quite restrictive on how such wa
27. umber of the T1 Link Ranging from 0 to 83 EI_TS 9 Number of the Timeslot within a El Link Ranging from 0 to 31 T1_TS Number of the Timeslot within a T1 Link Ranging from O to 23 STM Version 1 3 O N A T GmbH Number of the four byte interleaved STM 1 Links present on the SBI bus Ranging from 0 to 3 34 NAMC STM1 4 Technical Reference Manual 7 Known Bugs Restrictions none Version 1 3 N A T GmbH 35 NAMC STM1 4 Technical Reference Manual Appendix A Reference Documentation 1 2 3 4 5 6 7 8 9 Atmel Atmega48 88 168 V Product Data Rev 2545G 06 06 Zarlink ZL30410 System Synchronizer Data Sheet 11 2005 Traco Power DC DC Converters TOS Series POL Converter Rev 10 05 N A T 1TDM FPGA Technical Reference Manual October 2006 Ver 1 0 PMC Sierra PM8316 TEMUX84 Register Description Issue March 2004 PMC Sierra PM8316 TEMUX84 Programmers Guide Issue No 4 Sep 2003 PMC Sierra PM5318 5320 Arrow622 155 Operation and Configuration Guide Issue No 2 Jul 2004 PMC Sierra PM5318 5320 Arrow155 Register Description Issue No 2 Jul 2004 N A T Ethernet Control Interface Technical Reference Manual Ver 1 0 Dez 2007 Version 1 3 N A T GmbH 36 NAMC STM1 4 Technical Reference Manual Appendix B Document s History te further register descriptions updated pin descriptions and locations for programming jumper A SE RES
28. vices to share a single bus The Arrow 155 maps demaps up to three channels of DS3 E3 or EC 1 with bi directional monitoring of traffic The traffic may be multiplexed either into the system side or line side interfaces For the STM4 option the board is equipped with an Arrow 622 device 1 1 3 Backplane Interfaces PCIe The NAMC STM1 4 includes a x1 PCI Express interface This is implemented in the Lattice FPGA The PCI Express interface connects to Port 4 8 of the Fat Pipe Region of the AMC backplane connector can be switched over to support redundant system setups The implementation of PCIe conforms to the AMC 1 specification GbE The NAMC STM1 4 implements a serial Type P Control Path the physical layer of which is 1000BaseX The Type P Control Path connects to Port 0 1 of the Common Options Region of the AMC backplane connector can be switched over to support redundant system setups The Control Path is connected to the TDM FPGA and shares the port with iTDM iTDM The NAMC STM1 4 implements a serial 1TDM backplane interface the physical layer of which is 1000BaseX The 1TDM interface connects to Port 0 1 of the Common Options Region of the AMC backplane connector and shares the port with the Type P Control Path The 1TDM Version 1 3 N A T GmbH 10 NAMC STM1 4 Technical Reference Manual IPMB TDM Version 1 3 interface is implemented in FPGA logic and conforms to the SFP 0 and SFP 1 specifications
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