Physical Layer Compliance Testing for HDMI 1.4a Using
Contents
1. Physical Layer Compliance Testing for HDMI 1 4a Using TDSHT3 HDMI Compliance Test Software Application Note Introduction Termed as the catalyst for the DTV revolution High Definition Multimedia Interface HDMI technology is on the threshold of mass adoption Content providers system operators and consumer electronics CE manufacturers are rallying behind this standard As a result the focus is now on demonstrating compliance to tests defined by HDMI standards Design and validation engineers need tools to improve efficiency by performing a wide range of standards required tests quickly and reliably This application note describes various tests that ensure validation the challenges faced while testing complex HDMI signals and how oscilloscope resident test software enables unprecedented efficiency improvements with reliable results and unprecedented automation to perform a wide range of tests including the Sink tests Tektronix Application Note Basics HDMI leverages on the successful transition minimized differential signaling TMDS technology The differential signals are 3 3 Volts terminated in 50 2 with nominal amplitude transitions of 500 mV 2 8 V to 3 3 V The voltage swing can vary from 150 mV to 800 mV The signals have rise times of the order of 100 ps The data rates on a single link can range from 25 Mpps to 340 Mpps Mpps Mega pixel per second Since each pixel is represented by 102. DATA iub dui n n on on dg e oma H Bi LL DAH T n x d LE m p za Al I i io m 1 i a Cable DUT UN 50 ohm termination or OO JP unused probe Figure 21 253 0 107 Owen TOGSNO TOT HHA h Tuum 9 zvatavta d Mma DATO 7 usw me Cable DUT ry pays Cable DUT Figure 22 Figure 23 f Test Setup for Cable Tests See Figure 18 for Direct Synthesis setup for Cable tests See Figure 21 for Data Eye Diagram Tests See Figure 22 for Intra pair Skew Test See Figure 23 for Inter pair Skew Test www tektronix com hdmi 17 Application Note TDSHT3 HDMI 1 4a Compliance ooftware Engineers designing or validating their HDMI physical layer need to perform thorough validation in house There are a wide number of tests that need to be made These tests have tight margins requiring precise measurement techniques and complex control of a variety of test instruments The standards also require many of the tests to be performed over various supported pixel resolutions multiplying the complexity TDSHT3 HDMI Compliance Test Software automates a comprehensive range of tests including Source Sink and Cable tests enabling unprecedented efficiency with reliable results Reliable and dependable results TDSHTS3 embeds the
3. Common mode 7 3 Receiver Peifoemance Worst Case Cable TekExpress launched successfully Tektronix Figure 28 The following is a Summary of the tests covered under HEAC Specification m Ethernet Transmitter Test Similar to normal 100Base TX test except for lower amplitude m Ethernet Receiver Test Generate test packets with stress using AWG 5K 7KB Capture and analyze response packets using oscilloscope Confirm compliant packet error rate m Audio Transmitter Test SPDIF audio stream in common mode 400mVp p amplitude 832k 44 1k 48k samples s rate up to 6 144Mbps Measure typical pulse parameters using oscilloscope m Audio Receiver Test Generate test stream with stress using AWG Listening test to regenerated audible sound m Device Impedance Test Measure impedance of HEAC lines using TDR m Cable Test Measure impedance of HEAC lines using TDR TDT Measure S Parameters of HEAC lines using TDT S W 22 www tektronix com hdmi Tektronix TekExpress Automation Framework ne HEAC Differential TX Signal Characteristics Test Report DUT ID DUTOOT Device Type HEAC Transmitter CTS Version CTS 1 4 Date Time 3 2 2010 12 30 Execution Time 13 Min Compliance Mode Yes Overall Test Result Pass Scope Model 0 072004 Scope Serial Number Q226 Scope FAN Version 5 1 0 BNSFEUILD 28 SPC FectoryCalbretion PASS PASS Probe Model P6248 Probe Serial Numb
4. Source Eye Diagram CK D2 5 v 01 Device Details HDM Resolution Refresh Rate Source Inter Pair Skew DO D1 6 Source Inter Pair Skew gt 01 02 i Report File Clock gt Cht Data0 Ch2 Datat gt Ch3 Physical Layer Compliance Testing for HDMI 1 4a Using TDSHT3 HDMI Pressing the Run Test button starts the test process and after performing all the tests relevant plots are presented and result summary is provided as shown below Pressing Result Details button provides more information on limits and measured values Report generation is instantaneous at the press of a button The reports can then be easily converted in to popular formats such as portable document files and others The TDSHTS3 Quick Start User Manual 6 provides examples of performing HDMI Sink tests A New Powerful Tool To Analyze ISI 1 0ns 50 0GS s IT 200fs pt Stopped 7 616 acqs RL 50 0k Auto August 22 2007 17 15 59 A Cer Serial 500 81606 50 0mV div CJTpat at 6 Gb s shown is 2640 bits Pattern can be up to 2 1 Gb s PRBS31 1 Engineers Valuating High speed Digital Serial Communication Who Need To m Isolate the particular bit sequences that cause mask violations m Remove noise and correlated Jitter on patterns as long as PRBS31 1 to evaluate det
5. is available on many Tektronix oscilloscopes to enable faster testing The Inter pair Skew test requires trigger on a specified serial pattern www tektronix com hdmi 7 Application Note Differential Probes For example two four Tektronix P7313SMA probes could be connected using ET HDMI TPA P adapter which enables connections through SMA for reliable results The HDMI TMDS signaling employs differential transmission system Differential probes with their high common mode rejection high sensitivity and response accuracy and low noise floor are well suited for this purpose Considering the high signaling rates and tight margins it is imperative to understand various aspects and options for probing The primer High speed Differential Signaling and Measurements provides in depth understanding of these aspects Because differential probes have two identical input pins making reliable connections is generally more challenging It is important to carefully plan the connections to the test adapters with square pins Although there is a long list of probe tip adapters each option must be weighed thoughtfully prior to employing any technique The Tektronix primer dwells into finer details of each of these options Variable spacing adapters for instance could result in excessive overshoot Though inconvenient soldering to the test points offers the best results The P7380 and P7360 probe from Tektronix offers a variety of probe
6. The standard prescribes a limit on skew not to exceed 2096 of the pixel time TPIXEL This test is also performed between data channels as well The next section on Data Data tests describes this test in more detail This test is not required as per CTS 1 3c but is needed if tested as per CTS 1 2a 2 Data Data Tests Inter pair Skew The inter pair skew test has several important aspects to be considered Firstly skew can be effectively measured only when both the pairs are transmitting a specific pattern Secondly the measurement paths probes and oscilloscope acquisition system could be introducing their own share of skew Thirdly the oscilloscope would need to trigger on specific serial patterns also referred as serial triggering capability Finally the margins are specified with respect to the pixel time Hence it is important to also determine the clock rate accurately 6 www tektronix com hdmi It is important to eliminate skew in the acquisition path This process is termed as the De skew process For accurate results it is better to perform de skew prior to making this test 3 Single Ended Tests These tests are performed on each pair using single ended probes a Intra pair Skew Intra pair skew test gains significance as the signals are differential and reveals several signaling artifacts Skew within a differential pair is tested and the standards specify a limit of 15 of the bit time T As in th
7. These tests are performed at the HDMI cable at both TP1 and TP2 The following sections will discuss these tests in more detail 1 Data Eye Diagram Tests The objective of this test is to ensure the cable relays the signal accurately from the Source to the Sink The cable is expected to cause a certain amount of degradation to the signal The test ensures the level of degradation is low enough to ensure interoperability between devices The signal is first characterized at TP1 prior to introducing the cable into the transmission system An HDMI Signal Generator is used to generate TMDS signals The HDMI Signal Generator parameters are adjusted to transmit signals carrying a specified amount of clock and data jitter The eye diagram and jitter tests ensure compliance to these test conditions and is performed similar to the Source tests Compliance Test Software Cable TP1 Data Eye Diagram 875m I Results Mask Test iw PASS Mask Hits 0 Voltage 175mV div Vswing 640 00mV Thit 1 3468ns Data Jitter 398ps Hist Pk Pk 398 0 0 gt Time 269ps div 2 69n Figure 19 Cable TP2 Data Eye Diagram 875m b Results Mask Test W PASS Mask Hits 0 Voltage 175mV div Vswing 885 48mV Thit 448 93ps Data Jitter 99 8ps 875m i HistPk Pk 99 8 gt Time 89 8ps div Figure 20 The cable is then connected and the data eye diagram is verified aga
8. bits of data the bit times popularly referred as TBIT can go down to 294 ps A typical HDMI data signal is depicted in Figure 1 Most of the margins are defined with respect to T i e bit times for data signal The TMDS transmission link comprises of three data channels and one clock channel Figure 2 depicts the logical links of the TMDS signaling Physical Layer HDMI Compliance otandards To ensure reliable information transmission and interoperability industry standards specify requirements for the network s physical layer The HDMI Specifications and more specifically the HDMI Compliance Test Specifications or CTS 21 define an array of compliance tests for HDMI physical layer Figure 3 illustrates the major elements of the HDMI transmission system source cable and sink The Source signals are characterized at TP1 while the sink devices are tested at TP2 to ensure that they are within standard margins For testing cables measurements need to be performed at both TP1 and TP2 Measuring at TP1 ensures measurements at TP2 are performed under known environments 2 www tektronix com hdmi 500 500 8y 12 5G 500 8y 13 0G 500mV div 500 8y 13 0G 500 8y 13 0G 1 0V div 1 0V div Figure 1 Figure 2 Figure 3 a Lc 20 0 Video Audio EDD HDCP CEC D DAMI HOM Ethernet Channel Ethernet up link Audio up link HEAC Cable Ethernet down lin
9. earlier min box approach is most appropriate for reliable data jitter measurement Data Timing Generator TMDS Signal Generator plays a pivotal role in the Cable tests Tektronix offers the DTG5334 with DIGMS3O modules that combines the power of a data generator with the capabilities of a pulse generator to enable the Cable tests with highly accurate test signals Sampling Oscilloscope The limits for the skew tests require ultra precision measurements The DSA8200 with 80E04 or 80 modules deliver the required measurement accuracy and resolution for making these tests Automation Tools Cable data eye diagram test brings the complexity of both oource as well as Sink tests Complexity of eye rendering accurate data jitter measurement techniques coupled with the tedium of controlling several tools make this test very complex TDSHTS discussed later in this document makes this test with relative ease The Digital Phosphor Oscilloscope connects to the DTG5274 using a GPIB cable and to the AWG using a GPIB USB B HS cable available from National Instruments LiTek from Taiwan offers a high speed cable test solution LT 4165 that automates several other tests Physical Layer Compliance Testing for HDMI 1 4a Using TDSHT3 HDMI Compliance Test Software E Nat E Nel ta GPIB comvertar Digital Oscilloscope A HDMI TPA FR TDR Mo Modules l ell
10. enables quick and reliable tests Authentic measurement techniques ensure results that are reliable and automation relieves users of laborious and tedious test processes C Test Setup for Source Tests See Figure 11 for Differential Tests oee Figure 12 for Single ended Tests Digital Oscilloscope a SS dae Dod O c D 5 n0n mp b aaa a See oo oo DATA LN b TPA 1 1 DATAS pull ap DATA M pull we DA Li tS AU 7 ARA E IR F H wp HEE Hl up Hune EN up Ns 90 1 mpi port eu dinero obe rE Figure 12 d Getting the test signals from DUT m Configure the EDID Emulator This emulates a Sink device to enable handshaking of signals Using a PC based software set the EDID Emulator to the desired resolution settings One can use the Efficere EDID PCB 8 Figure 10 m Provide external power supply Enables voltage across pull up resistors There are no specified test patterns required and hence any HDMI patterns generated by the Source DUT is adequate For example any DVD played on a DVD player would generate required test signals Refer to the test setups described above for connection details www tektronix com hdmi 9 Application Note oink Electrical Tests These tests are performed at the HDMI connector at the Sink Device at TP2 The follo
11. tips that allow soldering or holding the probe using a probe positioner or a handheld probe housing to allow for point to point probing Probe bandwidth is another important factor to be considered Again depending on signal rise times probes should be chosen to ensure its rise times are fast enough to ensure signal fidelity at the measuring instrument Tektronix Oscilloscopes and Probes offer recommended system bandwidths right up to the probe tip 8 www tektronix com hdmi Figure 10 Test Adapter Reliable connections are key to maintaining precision and signal integrity There are two types of test adapter sets available For most of the Source devices the plug type adapters TPA P are well suited for making the primary connection to the Device under test DUT Figure 10 shows a TPA P plug type test adapter from Wilder Technologies Physical Layer Compliance Testing for HDMI 1 4a Using TDSHT3 HDMI Compliance Test Software pn internal from DPCUDISA ssepe oo OO e eos p TPA P Figure 11 Automation Tools Compliance to Source tests implies performing a wide range of tests reliably Tight margins and complex test procedures makes these tests very time consuming Most of the tests need to be performed under optimal conditions and users need to be an expert in HDMI technology as well as usage of test equipment By any measure a daunting task TDSHTS8 discussed later in this document
12. 0 Tbit to 1 tbit in O 1 tbit steps to observe failure of the Sink device Step 5 Repeat steps 2 3 and 4 with the second cable emulator and find out if the Sink device fails software version 4 0 0 or above version now has limited margin test capability for Sink Jitter Tolerance test Users can now insert jitter up to O 5T 2 Min Max Differential Swing Tolerance This test has been very common for most serial standards The test confirms that the Sink properly supports interoperability even when the differential voltage swings are at their minimum levels 150 mV A TMDS signal generator with the ability to change amplitude is employed for this test Any Sink supported 27 MHz video format is generated that repeats the RGB gray ramp signals from O to 255 during each video period The testing starts from 170 mV V on all pairs and the differential swing is reduced in steps of 20 mV until the Sink device reports error If the minimum V to which the Sink responds without error is 150 mV the device has passed the test The test stops when minimum Vrp reaches 70 mV Another important element of this test is that it is performed at two different common mode voltage settings which are 3 0 V and 3 3 V The CTS 1 3c asks for the signal to be also tested with a differential swing of 1 2 V Compliance Test Software 3 Intra pair Skew The Sink devices also need to be tolerant to intra pair skew This test ensur
13. HDMI CTS 1 4a compliance test procedures including the software clock recovery SoftCRU ensuring dependable results Accurate eyerendering and precise violation testing deliver credible results Sink tests are performed accurately with closedloop measurements that eliminate non linearities of the test setup Authentic measurement techniques and automation eliminate errors to provide convincing results Faster Validation Cycles The unparalleled automation offered on the enables faster validation Test times for Sink devices shrink from hours to minutes with TDSHT3 remotely controlling the DTG AWG to automate the complex test process Its one button Select All feature demonstrates efficiency by performing multiple Source tests TDSHTS instantaneously generates csv format summaries or detailed reports at a press of a button Complete solution for validation TDSHTS offers a wide range of tests enabling thorough verification to standards Tests offered include Source Sink and Cable devices With TDSHTS convincing validation can be performed using a complete solution that includes oscilloscopes arbitrary waveform generators data timing generators test fixtures and TDR 18 www tektronix com hdmi Performing the tests using TDSHT3 User can select the entire range of tests by clicking on Select button and run the tests at a press of a button The Source tests are invoked when the Source tab is
14. detecting the HPD is active HEAC allows the combination as signals are MLT 3 signal only IEC 60958 signal MLT3 signal IEC 60958 signal alone So there was no need of synchronizing of TX and RX When an active Source and Sink are connected with a cable the differential voltage across the termination resistance into one device is the sum of the driving signal of that device and signal from the other device The device is able to detect with its sensor the MLT 3 signal and by subtracting the detected differential signal from its current driver s Signal In addition HDMI Source is able to detect with its sensor the IEC 60958 1 signal by summing the differential signals to extract the common mode signal www tektronix com hdmi 21 Application Note TekExpress HEAC Automated Solution Demo Version Untitled Tools Sees er Select Device Select Test Suite Version C HEAC Transmitter Differential Rx crs 1 x HEAC Receiver DUT IP Address 255 255 255 255 7 Auto Detect MAC Address Test Description This optional test verifies the receiver capability to respond to HEAC Receiver Differential Hx CTS 1 x x ai nominal amplitude clock frequency romance Nominal Response and common mode volatage lect Test 7 3 Receiver Performance Amplitude eee 7 3 Receiver Performance Clock Frequency 7 3 Receiver Performance
15. e case of Inter pair skew it is important to perform de skew prior to performing this test This ensures the error due to skew of the probing and acquisition system is minimized b Low level Output Voltage The V test is performed to ensure signal voltage levels are within prescribed limits The test checks for the DC voltage levels on the HDMI link for each TMDS signal The CTS specifies that the voltage of the low levels should fall within 2 7 V and 2 9 V In order to ensure compliance large numbers of waveforms are analyzed Standard prescribes a minimum of 10 000 waveforms FastAcq helps perform this test faster To determine the voltage level histogram method is employed The statistical maxima of the histogram the histogram peak is presented as the V and compared against standard limits Physical Layer Compliance Testing for HDMI 1 4a Using TDSHT3 HDMI Compliance Test Software Test Digital Differential Single ended TPA P Test DC Power Supply EDID Emulator Oscilloscope Probes Probes Adapter Set BeDagam e 00 00 o e es oe Coder e o e d 00 a s a Inter pair Skew Intra pair Skew Output Low VL Notes 16 MRL ST gt 2 nos Table 2 Preparing for Source Tests a The Test Suite Table 2 summarizes the equipment required to perform the wide range of Physical Layer tests discussed earlier Additionally Digital Multimeter Protocol Analyzer LCR Meter and 2 Analyzer are required to pe
16. e large number of parameters to be measured it is also very important to ensure the measurements are performed authentically It is important to maximize the size of the signal on the display in order to use as much A D range as possible without overdriving Figure 9 is a good example of accurate overshoot measurement technique Tight margins require such careful measures for dependable results This test is not required to be performed as per CTS 1 4a However if the devices are tested as per CTS 1 2a then this test is required www tektronix com hdmi 5 Application Note e Rise and Fall Time Hise and fall time tests have been a mainstay in most physical layer tests The limits ensure that signals deliver required signal speed and also that EMI is contained The CTS specifies the rise or fall times should be higher than 75 ps and lower than 0 4 value As in the case of clock duty cycle test this test also requires large number of acquisitions Once again trigger re arm rate becomes important The test can be easily performed using FastAcq mode on a Digital Phosphor Oscilloscope The maximum rise and fall time is not required to be performed as per CTS 1 4a However if the devices are tested as per CTS 1 2a then this is required f Clock Data Inter pair Skew Inter pair skew is an extremely important test to ensure interoperability This test confirms that skew between clock and any of the data pairs are within limits
17. e required for test purposes Trigger re arm rates of the oscilloscope take center stage Nominally oscilloscope trigger re arm rate are of the order of about 100 waveforms wfms per sec This can mean unacceptably long acquisition and test times Fortunately there are sophisticated techniques like FastAcq on Digital Phosphor Oscilloscopes DPO that enhance the trigger re arm rates and deliver over 250 000 wfms s Figure 8 demonstrates the clock duty cycle test using the FastAcq technology Notice the richness of information that ensures convincing measurements d Overshoot and Undershoot Overshoot and undershoot tests ensure that signals remain within prescribed limits These tests ensure that the transmitter does not overdrive the channel or drive the ESD structures to become non linear and start interfering It also ensures interoperability by testing signals for recoverability The CTS standard defines the limit for overshoot as 1596 and undershoot as 2596 of the entire steady state voltage swing The test is performed on the clock as well as the data pairs he test requires measurement of several parameters that includes accurate measurement of voltage swing VH and VL and overshoot and undershoots for both rising and falling edges In all this one test requires over six parameters before declaring results 2 5ns 25 0GS s 20 0ps pt Sample 132 096 acqs RL 1 0k March 13 2006 Figure 8 Figure 9 Besides th
18. er 011054 Te xpress Version HEAC 1 3558 Framework 13 4135 Low Measured High Test Compliance Analysis Limit value Limit Result Mode Time DC Voltage HEAC 36 44 0200 0598 Pass EN 5 1 Operating DC Voltage DC Vollace line 1539 02061 0559 V Pas Yes u O gt i Jitter Max Negative lt 14 057 Rise Time Positive Pulses gt 3 77 1 9251 0 0749 Pass 5 3 Rise Fall Time all Time Positive Pulses 3 5 1 7602 0 2398 Pass Yes i Rise Time Negative Pulses 3 19747 00253 Pas Fall Time Negative Pulses 47572 17572 0 2428 m High Level Voltage lt 200 119 4400 205551 Pass High Low Center Level Low Level Voltage 494 4681 25 5319 14 4691 Yes enter Level Voltay Pass otage gt 20 lt 20 230720 16 9268 55 Cycle Time Cycle Time Positive Pulses gt 7 875 BST TIN lt 8 125 0 1831 0 0669 Pass Yes 2Min adi e Time Negative Pulses gt 7 875 lt 8 125 0 1834 0 0665 Pass Test Name Measurement Details Margin Units Comments Figure 29 Figure 30 The HEAC Solution consists of the following m lest Fixture Kit TF HEAC TPA KIT MAIN 2 Plug AP CP 4 TDR 2 AR 2 CR Figure 30 m HEAC Software Ethernet Transmitter Test Software Figure 28 and 29 Ethernet Receiver Test Software Control AWG amp oscilloscope S
19. erministic effects such as Pattern Dependent Jitter and Inter Symbol Interference Specifications m Up to 6 25 GB s NRZ or 8b 10b with internal clock recovery m Up to 2 147 483 647 bits pattern length Compliance Test Software E TDSHT3v1 3 2 O JO Search 5 2 Favorites B e ee rel 33 Address nt Outlook LLJ1A10Q 20080529_155507_SE_Defect mht 7 10 20 20Source 20Eye 20Diagram 20 20CK 20 2000 v J Google G 7 10 Source Eye Diagram CK 00 Results Mask Test Mask Hits 0 Vswing 937 96mV Tbit 1 3481 5 199ps Voltage V 875m 0 0 Time s TES il Internet Unfortunately the longest patterns with the most stressful bit sequences including large numbers of Consecutive Identical Digits place severe demands on test equipment The problem is not only capture time but triggering capability Analysis methods that use data edges to trigger will ignore the Consecutive Identical Bits since there are no transitions Pattern Lock triggers on recovered data clocks not data transitions pattern lock enables you to average and analyze serial data patterns up to 2 1 Gbs in length PRBS31 1 By analyzing the digital data as a pattern you can isolate the particular bit sequences that are likely to cause mask violations Benefits The TDSHT3 HDMI Compliance Test Software cuts validation cycles fr
20. es the Sink device allows for timing skew within each TMDS pair The CTS standard defines a limit of O 4 T z for intra pair skew tolerance The test starts by setting clock and data pairs with no skew and then increasing the intra pair skew in each pair one pair at a time in steps of O 1 T until the Sink device outputs an error The maximum skew with error free Sink operation is defined as the Intra pair skew and is compared against the limit If greater than O 4 T the device is termed compliant TDSHT3 now supports 4 channel Intra pair Skew test 4 Differential Impedance Differential transmission lines used in achieving fast data rates are very sensitive to impedance matching Consequently impedance characterization is a very crucial test in compliance testing of HDMI The through connection impedance has a limit of 1596 variance to its 100 specification The impedance at termination needs to be tighter as the margins are only 1096 of its characteristic value of 100 Q This test is performed with the Sink device switched off The measurement distance to DUT input connector is first measured This is best determined using a method where the impedance curve rises sharply to gt 200 o denoting the distance to the connector Next differential impedance values 2 are determined for each pair from the input connector until the point where the impedance curve stabilizes to termination impedance The other non tested pai
21. etup signal sensitivity clock frequency modal rejection error rate Extract amp check response signal software HYBRID amp packet analysis Audio Transmitter Test Software HEAC Audio Receiver Test Pattern Suite AWG files format support modal rejection jitter tolerance Physical Layer Compliance Testing for HDMI 1 4a Using TDSHT3 HDMI Summary High Definition Multimedia Interface HDMI technology is witnessing rapid growth As a result the focus is now on demonstrating compliance to standards Engineers designing or validating the HDMI physical layer on their products need to perform a wide range of tests quickly reliably and efficiently The large number of severe tests coupled with unprecedented complexity impose several challenges to the test engineer Tight margins require careful measurements and thorough understanding of error contributors TDSHTS enables efficiency improvements by performing wide range of tests quickly and reliably Compliance Test Software Heferences 1 HDMI Specifications version 1 4a 2 Compliance Test Specifications CTS version 1 4a 3 High Speed Differential Data Signaling and Measurements Tektronix Primer 55W 16761 O 4 Differential Impedance Measurements with the Tektronix 8000B Series Instruments Tektronix Application Note 85W 16644 0 5 Measuring Controlled Boards with TDR Tektronix Application Note 85W 8531 0 TDSHT3 Quick S
22. g for HDMI 1 4a Using TDSHT3 HDMI TDR Sampling Oscilloscope Time Domain Reflectometry TDR is a powerful and accurate tool for measuring impedance and length in interconnects While fundamental concepts of TDR are relatively simple a number of issues must be considered to make accurate measurements the foremost being the ability to perform true differential TDR This is what makes the DSA8200 with the 80E04 module the tool of choice for making the Differential Impedance test If the TDR connection is to be probed to the circuit board the 80A02 module can be combined with P8018 If testing cables such as in manufacturing then the P8018 is not needed and just the the 80A02 with foot pedal actuator This protects from possible operator error in connecting cables DTG 58 ik BH DTGASI jk iho J el m rx Pie Cufinitions af Jt TE Ground E m 21 GEG E n pili DOC 301 SE DOC Das DY 3 P Grad 9 Bi Has Pla Figure 16 Compliance Test Software Figure 15 Test Adapter Just as in Source tests reliable connections are key to maintaining precision and signal integrity for Sink tests There are two types of test adapter sets available For most of the oink tests devices the plug type adapters ET HDMITPA P set and receptacle type adapters ET HDMI TPA R set are well
23. gineers working on the cutting edge of technology Please visit www tektronix com Copyright O 2010 Tektronix All rights reserved Tektronix products are covered by U S and foreign patents issued and pending Information in this publication supersedes that in all previously published material Specification and price change privileges reserved TEKTRONIX and TEK are registered trademarks of Tektronix Inc All other trade names referenced are the service marks trademarks or registered trademarks of their respective companies 10 10 EA WWW 61W 17974 6 Tektronix
24. he right equipment for your test setup it is important to understand important aspects that need to be addressed by this equipment Some of these aspects are Digital Storage Oscilloscope The jitter tolerance tests require a minimum of 16 Meg record length in the oscilloscope 12 www tektronix com hdmi Hardware TTC Filters Qty 32 needed for method Not required for DS method Data Timing Generator TMDS Signal Generator plays a pivotal role in the Sink tests The key challenge for a TMDS signal generator is to provide a full complement of highly accurate signals and the ability to precisely control their parameters For performing minimum differential sensitivity tests a resolution of 20 mV is required The intra pair skew test requires precise delay settings down to sub picosecond resolution Tektronix offers the DTG5334 with DTGM30 modules that combines the power of a data generator with the capabilities of a pulse generator to enable the Sink tests with highly accurate test signals Arbitrary Waveform Generator The jitter tolerance test assumes larger challenges as both clock and data jitter need to be varied Generating jitter frequencies of the order of 10 MHz requires a combination of signal generators Since margins are tight precise control is required on jitter amplitude Tektronix AWG7102 or AFG3000 is the platform of choice for generating such levels of performance Physical Layer Compliance Testin
25. ict discipline in violation detection Typically oscilloscope screens may have a pixel resolution of 500 x 400 or higher for the graticule and pass fail testing is based on mask hits resolved Source Eye Diagram CK DO ex ar 5m by the screen image While this can be acceptable for lower HDMI resolutions for 2 higher speeds results can often be misleading In such cases itis preferable to perform mask violation testing down to data sample resolution If this test were to be performed using 2 image resolution the results would have been incorrect 5 b Clock Jitter At the nerve center of any transmission system is the clock signal The jitter test checks to ensure that the clock signal is not carrying excessive jitter In order to perform this test the Brom clock is referenced to a recovered clock The standard defines the same clock recovery function as shown earlier in Figure 5 0 0 Time 270ps div 2 7 On Figure 5 The clock signal is plotted with respect to the recovered clock Histogram box is placed at the center of the edge and signal span determines the jitter present on the signal The measured jitter should be less than 25 for compliance Traditionally when measuring jitter using histogram box the box Is placed at the center of the rising edge and the height is kept at the minimum This technique can be termed for sake of convenience as min box approach It is imp
26. in at TP2 The standard clearly delineates the amount of degradation permitted at TP2 by testing against several conditions m Mask tests m Data Jitter is lt 0 67 ns equivalent to 0 5 T at 75 MHz The data jitter is measured using a histogram box Similar to Source jitter tests min box approach is highly recommended The data jitter measured using min box approach delivers reliable results Figures 19 TP1 and 20 at TP2 illustrate a cable eye diagram test being performed on the oscilloscope www tektronix com hdmi 15 Application Note Intra Pair Skew Data Eye Diagram Digital Storage Oscilloscope Differential Probes Data Timing Generator sampling Oscilloscope Efficere Fixture Set 50 Q terminations 14 nos SMA Cables 8 nos GPIB USB Controller GPIB Cable Table 4 2 Optional Parametric Tests These tests are a very good indicator of the signal integrity of the cable The tests are recommended but not required These tests are a Intra pair Skew b Inter pair Skew c Far end Crosstalk The Intra and Inter pair skew tests are performed using a sampling oscilloscope The Tektronix TDS8200 used for Sink Differential Impedance test can be used for these tests using plug in The Tektronix 80E04 used for TDR can also be used for this test as it is a dual channel sampler in addition to a dual differential TDR step generator While the Far end Crosstalk test is usually performed with a Network A
27. k 2 0ns acqs an April 09 2008 50 0GS s IT 4 0ps pt Single Seq RL 5 0k gt Audio pt ummy Physical Layer Compliance Testing for HDMI 1 4a Using TDSHT3 HDMI Compliance Test Software Electrical Signals Test CTS Test ID Test Point Source Clock and or Data Data Eye Diagram TP1 Clock Jitter TP1 Clock Duty Cycle TP1 Overshoot Undershoot TP1 Rise Fall Time 7 4 Data Data Inter pair Skew TP1 Single ended Intra pair Skew Low Level Output Voltage VL 7 2 Ethernet Transmitter Test HEACT 5 1 to 5 5 Audio Transmitter Test HEACT 5 6 to 5 10 TP2 HEACT 5 11 to 5 15 TP2 Sink Differential Jitter Tolerance TP2 Min Max Differential Swing Tolerance TP2 Differential Impedance TP2 Deep Color TP2 Audio Clock Regeneration TP2 Audio Sample Packet Jitter TP2 Audio Formats TP2 One Bit Audio TP2 DVI Interoperability TP2 3D Video TP2 4Kx2K Video libe Extended Colors and Contents TP2 Single ended Intra pair Skew 00000 2 HEAC Fthernet Transmitter Test HEACT 5 16 TP1 Audio Transmitter Test HEACT 5 17 to 5 20 TP1 Cable HEAC Data Eye Diagram 5 3 PA Inter pair Skew 5 5 Device Impedance Test HEACT 6 1 TP1 and TP2 Cable Test HEACT 6 2 to 6 3 TP1 and TP2 Table 1 While it is recommended to perform as many tests as possible the core tests are extremely critical for compliance Table 1 summarizes some of the core tests oource Electrical Tests These tests are performed
28. nalyzer use of TDR for crosstalk measurements is gaining favor as the measurements can be performed faster less expensively and far more intuitively with TDR TDA Systems has some informative application notes on measuring crosstalk with a TDR Preparing for Cable Tests d The Test Suite Table 4 summarizes the equipment required to perform the Sink tests discussed earlier A network analyzer can be used to perform the Far end Crosstalk tests Using a DSA8200 and l Connect software you can now perform the tests which needed Vector Network Analyzers This will provide a very good economical alternate test capability e Test Equipment Important Considerations While choosing the right equipment for your test setup it is 16 www tektronix com hdmi Inter pair Skew Los oot po Et o ol pw Lot oot LL DT65894 with 3 DTGMSO l s 4 DSA8200 with 80E03 80E04 Los e t t 242221020010 1015 10220 Los oot e 4242500 ee 740040 National Instruments GPIB USB B HS Far End Crosstalk Remarks important to understand important aspects that need to be addressed Some of these aspects are Digital Phosphor Oscilloscope The tests require a minimum of 16 M record length to ensure compliance to standards Data jitter needs to be measured It is also important to recognize that the jitter is measured with respect to the PLL recovered clock as described in the Source tests As recommended
29. om days to hours Authentic measurement techniques and closed loop measurements ensure reliable and dependable results Its unparalleled automation shrinks test times and minimizes human error Coupled with a wide range of test equipment it completes the solution for HDMI testing Reports can also be documented in comma separated variable format by pressing the Summary button This is very useful when testing multiple ports and documenting them as a summary The csv format allows easy documentation in popular tools like Excel and many others www tektronix com hdmi 19 Application Note Ralay Plug ole a a i 1 1 CE Source Device CE Assembly AutomotiveCable Assembly Automotiveink Device for Automobile Figure 24 Asuti Hirst Teri Marck Hits ri dme TIn nir Jitter AGL Summary Cenfiguritisn hore Deviga Detaily Device Ede cine Eye Darin ch 00 LUTTE Pate File CAT ekeit Toon Ch f Eye BI Au Can Dixi IE gt gt CAS PL gt 244 Meee DTG bameg TPI gt 182 True Figure 25 Figure 26 Automotive Type E and Mobile Type D The Type 2 cable emulators have been approved in CTS 1 4a The Direct Synthesis solution for Automotive HDMI has been approved in CTS1 4 DS solution f
30. on the clock and or data signals at TP1 Considering the test setups these can be further grouped as Clock Data Data Data and Single ended tests The following sections will discuss these tests in more detail 1 Clock Data Tests a Data Eye Diagram Test The objective of this test is to ensure the differential data has adequate eye opening to enable effective recovery at the sink device after transmission The data is clocked with respect to the recovered clock and presented in a window size of 1 0 Comparison to mask determines pass or fail and analysis of data jitter provides useful information on signal integrity Hija 2 1 1 Joas Where 2nF Fo 4 0MHz Figure 4 The standard clearly delineates the method for clock recovery The clock is recovered using a PLL function shown in Figure 4 To ensure adequate representation of signal characteristics the CTS specifies a minimum oscilloscope record length to acquire the data signal This ensures that at least 400 000 unit intervals or are accumulated for building the eye diagram With 16 M 20 M record length at least 400 000 unit intervals can be captured for lower resolution signals and over 2 6 M UI for higher resolution devices www tektronix com hdmi 3 Application Note Figure 5 shows a screen shot of eye diagram test being performed on the oscilloscope The mask is shifted left until a violation occurs Notice the tight margins which imply str
31. or Type 1 and Type 3 CE has been approved in CTS1 4 Direct Synthesis solution supports all Cable emulators using the path breaking DS method which removes the need for hardware cable emulators thus enhancing the test method Figure 24 shows the system components of the Automotive HDMI The HT3 DS software supports Automotive Type E HDMI testing as shown in Figure 25 The fixture for it is available from Tektronix and has been approved by the HDMI standards body Mobile companies will support the new Type D connectors as shown in Figure 27 20 www tektronix com hdmi Physical Layer Compliance Testing for HDMI 1 4a Using TDSHT3 HDMI HEAC HPD HEAC and reserved line forms full duplex balanced pair HEAC consist of MLT3 signal in differential mode and IEC 60958 1 in common mode oource and Sink exchange 100BASE TX data through a differential pair at the rate of 125 MSymbol s 100 MLT 3 signal which is simultaneously bidirectional full duplex The bidirectional signals do not necessarily have to be in synchronization with each other The HDMI Sink device can transmits a single IEC 60958 1 stream as a common mode component of HEAC differential pair signals to HDMI Source in reverse to the direction of the TMDS path with or without MLI 3 signals This signal does not necessarily have to be synchronized with the MLT 3 signals Compliance Test Software HEAC lanes are biased to 4V through resistor from the oink after
32. ortant to recognize that at clock rates of the order of 340 MHz number of samples on the edge might not be very high In order to overcome the challenge of fewer samples the size of histogram box could be increased vertically In essence it is no longer the min box approach This leads to higher jitter values as depicted in Figure 6 A better strategy is to interpolate samples and perform the Figure 7 measurement using the min box technique Figure 7 shows jitter measurement using interpolated samples using min box approach Comparing these values to those in Figure 6 demonstrates the effectiveness of interpolated min box approach 4 www tektronix com hdmi Physical Layer Compliance Testing for HDMI 1 4a Using TDSHT3 HDMI Compliance Test Software Another valuable jitter assessment technique is the Time Interval Error TIE method In this case the edge displacement is obtained for each cycle and the difference between minimum and maximum is presented as peak to peak jitter Here again interpolation lends higher resolution for precise analysis and testing c Clock Duty Cycle Duty cycle jitter is an excellent method of assessing deterministic jitter The CTS defines the margin to be 10 from the nominal 50 duty cycle Thus the measured should fall within 40 and 60 It is important that the variance in duty cycle is measured over large number of acquired signals As per CTS minimum 10 000 triggered waveforms ar
33. pressed The TDSHTS Quick Start User Manual provides examples of performing HDMI Source tests File Tests Results Utilities Help 10k Cine Rec Length UE 1096 Ch3 View Waveform Source gt Multiple Tests TDSHT3 Configure Source HoriziAcq of Acqs Units High 2 8096 Reference Levels Per Hysteresis Mid al Clock gt Ch1 Data gt Ch2 Data1 gt Ch3 Data2 gt Rec Length gt 8M CRU gt PLL High gt 80 Low gt 20 The user interface allows flexibility in setting up the tests and eliminates confusion File Tests Results Utilities Help TDSHT3 m x Configure Source Horiz Acq Reference Levels of Acqs 1 Units High 1 View Waveform Source gt Eye Diagram Per v Hysteresis 1 Rec Length Report ie 10 i 50 8 00M Summary E 6 Detail Clock gt Ch1 Data gt Ch2 Data gt Ch3 Data2 gt Rec Length gt 8M CRU gt PLL Source tests can be easily configured to various jitter parameters like amplitude and frequency while the software manages appropriate file transfer to DIG and AWG for automated testing Source Eye Diagram Pin quu Results Mask Test v PASS Mask Hits 0 Vewing 980 00 Thit 1 348 1ns Data Jitter Result Summary Source Report Configuration Mis Crock smer 7 10 Source Eye Mri Source Eye Diagram cK 01 1 10
34. rform some of the other tests prescribed by the CTS standard b Test Equipment Important Considerations While choosing the right equipment for your test setup it is important to understand various aspects that need to be addressed Some of these aspects are Digital Storage and Digital Phosphor Oscilloscopes System performance drives measurement accuracy It is important to consider the rise times of your HDMI signals while selecting the bandwidth required A quick calculation on resolution supported refresh rate and blanking period would provide a good indicator of the TBIT values The TBIT values can be used to approximate the rise time of the HDMI signal 0 2 to 0 37 5 STX from Wilder Technologies At 165 MHz clock rate the rise times can be between 75 ps to 250 ps Tektronix TDS7704B for example provides rise times of the order of 60 ps and can be effectively used for signals with rise times greater than 180 ps DPO70804 provides a rise time of the order of 33 ps and can also be used effectively for HDMI testing The eye diagram and clock jitter tests require a minimum of 16 Meg record length The eye diagram test is performed using two channels Data and Clock and 16 M should be available for both channels oeveral tests require large numbers of acquisitions over 10 000 waveforms and it is imperative to have fast trigger re arm rates to perform the tests faster FastAcq technology
35. rs are terminated to 50 Z rr values should fall within 85 to 115 for a device to pass the test To obtain a deeper understanding of TDR tests and measurement of controlled impedance Tektronix offers some very descriptive application notes 4 and 5 www tektronix com hdmi 11 Application Note Min Diff Sensitivity Jitter Tolerance Digital Storage Oscilloscope Differential Probes Data Timing Generator Arbitrary Waveform Generator TDR Sampling Oscilloscope Wilder Test Fixture 50 2 terminations 6 nos SMA BNC adapter Cable from DTG DC O P Pin to SMA at Bias Tee 2 nos Intra pair Skew Differential Remarks Impedance 16M RL gt 2 nos AWG7122 w Opt 01 06 08 or DTG5334 w DTGM30 AFG3000 Series or AWG7102C DSA8200 with 80E04 80E03 TF HDMI TPA S STX 015 1022 01 015 1018 00 012 1506 00 015 0671 00 015 1018 00 SMA Cables 12 nos 174 1428 00 SMA m SMA f Cables 2 1 below Mini Circuits Bias Tee 2 nos ZFBT 4R2GW 1 Third Party Cable Emulator 1 each TTC Filters DC Power Supply GPIB USB Controller GPIB Cable Table 3 Preparing for Sink Tests a The Test Suite Table 3 summarizes the equipment required to perform the oink tests discussed earlier Additionally Digital Multimeter Protocol Analyzer and LCR Meter are required to perform some of the other tests prescribed by the CTS standard b Test Equipments Important Considerations While choosing t
36. suited for making the primary connection to the Device under test DUT Figure 15 shows an ET HDMITPA R plug type test adapter AWGT102 VE 1 uis d Power Supply m m Tu Sink DUT www tektronix com hdmi 13 Application Note Sank DUT Figure 17 20 Figure 18 14 www tektronix com hdmi Physical Layer Compliance Testing for HDMI 1 4a Using TDSHT3 HDMI C Test Setup for Sink Tests Jitter Tolerance Tests See Figure 16 Minimum Differential Sensitivity See Figure 17 Intra pair Skew tests See Figure 18 Automation Tools Sink tests as in case of Source tests take a lot of time In case of Sink tests there is added complexity of controlling several tools to conclude a measurement Add to that the challenge of precisely setting jitter parameters All this makes automation an implicit requirement TDSHTS discussed later in this document de skills the entire test process and makes use of GPIB to remotely control various parameters The Digital Phosphor Oscilloscope connects to the DTG5334 using a GPIB cable and to the AWG using a GPIB USB B cable available from National Instruments The DPO DSA70000 series oscilloscopes connects to the DTG5334 using GPIB cable and to the AWG using a GPIB USB B HS cable or E Net to GPIB converter available from National Instruments Cable Electrical Tests
37. tart User Manual Tektronix Manual 071 1565 01 www tektronix com hdmi 23 Contact Tektronix ASEAN Australasia 65 6356 3900 Austria 00800 2255 4835 Balkans Israel South Africa and other ISE Countries 41 52 675 3777 Belgium 00800 2255 4835 Brazil 55 11 3759 7600 Canada 1 800 833 9200 Central East Europe Ukraine and the Baltics 41 52 675 3777 Central Europe amp Greece 41 52 675 3777 Denmark 45 80 88 1401 Finland 41 52 675 3777 France 00800 2255 4835 Germany 00800 2255 4835 Hong Kong 400 820 5835 India 000 800 650 1835 Italy 00800 2255 4835 Japan 81 3 6714 3010 Luxembourg 41 52 675 3777 Mexico Central South America amp Caribbean 52 55 56 04 50 90 Middle East Asia and North Africa 41 52 675 3777 The Netherlands 00800 2255 4835 Norway 800 16098 People s Republic of China 400 820 5835 Poland 41 52 675 3777 Portugal 80 08 12370 Republic of Korea 001 800 8255 2835 Russia amp CIS 7 495 7484900 South Africa 27 11 206 8360 Spain 00800 2255 4835 Sweden 00800 2255 4835 Switzerland 00800 2255 4835 Taiwan 886 2 2722 9622 United Kingdom amp Ireland 00800 2255 4835 USA 1 800 833 9200 If the European phone number above is not accessible please call 41 52 675 3777 Contact List Updated 25 May 2010 For Further Information Tektronix maintains a comprehensive constantly expanding collection of application notes technical briefs and other resources to help en
38. this test tends to be extremely complex and takes a very long time 10 www tektronix com hdmi Search for the worst skew point gt warst d D JITTER tolerance Start Ten Tbit i i TMDS DATA TMDS CLOCK skew Vee y 1 o DS CLOCK delay Adjustment by DTG Pattern E generator of i worst 2 1 2 isa amp end Figure 13 D JITTER Tolerance D JITTER margin Tbit 0 5 p JITTER 0 3 Tolerance Tbit Figure 14 1b Jitter Tolerance Test The Jitter Tolerance test in CTS 1 has been simplified to a great extent when compared to the test as per CTS 1 2a The test is performed with all the jitter profiles 600 KHz 10 MHz 1 MHz 7 MHz and at 27 MHz 74 25 MHz 148 5 MHz 222 25 MHz and if available at 297 MHz resolutions Physical Layer Compliance Testing for HDMI 1 4a Using TDSHT3 HDMI The jitter tolerance test in CTS 1 3c is performed in the following steps m Step 1 Create the worst case TP1 eye diagram by injecting 0 25 TBit clock jitter and 0 3 data jitter which results in a just pass P1 eye diagram Step 2 Insert the first cable emulator which emulates a worst case eye for the resolution under test m Step 3 Adjust the clock jitter so as to measure a 0 3 TBit clock jitter at TP2 eye diagram Step 4 Increase the skew between the lanes from
39. wing sections will discuss these tests in more detail 1a Jitter Tolerance Tests One of the most critical characteristics of a sink device is its tolerance to specified levels of jitter in the signals The standard defines the limit as OEC opecified amounts of jitter are injected in steps from low to high jitter into the transmitted TMDS signal until the sink device fails to recover the signal The amount of jitter which the sink device is able to tolerate is compared against limits for compliance The jitter tolerance testing is performed in the following broad Steps m Determining worst case Clock Data skew The skew in data is varied until the worst point is determined This test is performed over several iterations as described in Figure 13 The TMDS signal generator is then set to generate this worst case skew m Measuring Jitter Margins Several measurements are carried out by injecting specified amount of jitter Three measurements are performed over two test cases a Data Jitter Frequency at 500 KHz and Clock Jitter Frequency at 10 MHz and b Data Jitter Frequency at 1 MHz and Clock Jitter Frequency at 7 MHz The three measurements are 1 Data Jitter amplitude D 2 Worst Data Jitter Amplitude D_JITTER margin 3 Worst Clock Jitter Amplitude C_JIT TER margin Figure 14 helps understand measurement criteria for D_ JITTER and C_JITTER margins With various parameters to be adjusted and tight margins
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