CS800 Service Manual..
Contents
1.2. 2 3 4 5 6 7 8 KEE O ee ee ee AA E sc 0710 108 10701 Ppspieoq gt ER SKY72310 TAZ808F x sl rc E RF PLL_DAT Ip ame P arm PLL_CLK i o 25C4549 N P ssi gt PLL CS 09 aro DS DIO ES 10302 ne See 2805066 2505066 MA2SO77 RDOIMUS2 RAS0H40471101 1407008 ee gt 1x RE TR DRIVE POWER ANT cl E la Filter yA Spur e a e gt pone gt ks ur K gt ANT umcaaf gt 50 A gt 0714 lec er D i Ge Ee CO 107 T Tr D313 S XC6209B502P G FM sw XC62048332MR 10303 D314 q B 13 8V BSB e d Mg EEE Je ers EE m NM12904RB1 158372 Ka SW 25 243 UMC4 PETER gt 014 Ge 08 UMcsa gt DMR ver KTC4075E Y GR lapc Tv m 9 L 5 3 DMR SW japa a x3 VCO 2sk508 gt ou dee gt a Tan TA7808F MP2359DJ 0504 D906 i AT tem 0503 BF1212WR D505 0505 D508 a GT3196 KTO40R0E P en y D506 BF1212WR D509 gt se IF ist RF x Fp Krs Kuen JE BFP KH
3. LCD 901 SW ENCODER3 ap D913 D914 ZE LE eps E ka ba ES MC2850 _MC2850 Co To ween we D Olle a C5 tu ji pug I Add S EE ct C2 o C4 Gun f ju 0 1u 0 1u A G SPK C9 y tu gt Io 952 953 Le Las 0 047u 0 047u T 1000 oe SC Zen Sr Rio 4 1000p u Ou om Ke as mm R15 1008 ava XC6201P332MR am ES gt w E I ms SE E our IN ou I L R902 E Ris 100R CT 416 0417 m pd 901 925 20408 410 Da 1k au R903 Du otu f 10u 470p Ko 5 4 8 a al 8 a al N E 2 cais r 100p J902 A A Y 9 a d 100p SC CONB 1 3V3 diga 1 ra ire ra ira 0403 E 1409 C409 412 DTC144EE 1C400 n Is 1 l Unc wech A 28 Ey 902 am d 1 N our k af P BE 83 m p Jenvour t as R907 GND tj ES PST9124NR R400 E oR 330k al d el W25Q64FVSIG RESET rie d t dam 401 C400 601s 902 908 LE Gs ECH E EN D903 Mc2850 gt MC2850 D906 D907 a al ca L me 4 YA 2 ik u Nor dk dis HA 912 YA E D908 D909 1000p y EE 922 924 casa 4 x 1000p lou tu R917 100R OLED OLED 957 0959 C961 EN Dato D911 1009 100p 100p R14 ik a MICDEY ro Z 100R OLED OLED
4. 4 PLL Frequency Synthesizer DAT CLKICS To MCU 16 8MHz CTCSS DCS MOD IN Freq Adj From MUC Figure 7 Schematic Diagram for Frequency Synthesizer The DM6000 2 adopts PLL frequency synthesizer Frequency synthesizer consists of reference oscillator voltage controlled oscillator VCO programmable frequency divider PFD phase comparator and low pass filter LPF RX VCO Unit consists of Q4 D3 D5 L12 C45 C49 and C51 TX VCO Unit consists of Q6 D4 D6 D7 L11 C46 C50 and C52 D7 is the modulation circuit of VCO IC8 SKY72310 is PLL integrated circuit and contains programmable parametric frequency divider PPFD programmable frequency divider PFD phase comparator and charge pump etc Low pass filter consists of R7 R159 R160 C171an C196 Reference frequency is provided by X3 TCXO 16 8MHz Reference frequency of TCXO Temperature controlled Crystal Oscillator is divided by PPFD in IC3 to produce reference frequency of 5kHz or 6 25kHz controlled by MCU based on the set channel frequency The oscillation frequency of VCO is compared with reference frequency to produce error signal after divided by PFD in IC607 The error signal is filtered by low pass filter before changing the VCO frequency to the set value in VCO it is locking N Fyco Fr N Division Frequency Fyco VCO Oscillation Frequency Fr Reference Frequency Lock lost detection When PLL is out of lock IC pin4 will output low level signal to MCU
5. 6 S VBAT VBAT Connected to VDD 7 O PC13 NC 8 O PC14 NC 9 O PC15 NC 10 S VSS_5 VSS_5 Connected to VSSA 11 S VDD_5 VDD_5 Connected to 3 3V 12 OSC IN OSC IN 8MHz Crystal Input 13 O OSC_OUT OSC_OUT 8MHz Crystal Output 14 RESET RESET Reset Input Low Active TIME SLOT INTE 15 PCO EXTIO R DMR TIME_SLOT Interrupt 16 PC1 EXTI1 SYS_INTER DMR SYS Interrupt 17 PC2 EXTI2 RF_TX_INTER DMR RF_TX Interrupt PC3 EXTI3 18 2T 5T 2T 5T data input AD123_IN13 19 S VDD VDD Connected to 3 3V 20 S VSS VSS Connected to VSSA 21 S VREF VREF Connected to 3 3V 22 S VDDA VDDA Connected to 3 3V PAO 23 NC ADC123 INO PA1 24 BATT DC Input ADC123_IN1 PA2 25 QT DQT_IN CTCSS DCS Input ADC123_IN2 PA3 26 VOX VOX Input ADC123 IN3 27 S VSS_4 VSS_4 Connected to VSSA 28 S VDD 4 VDD 4 Connected to 3 3V PA4 29 O APC TV APC TV D A Output DAC OUT DAD 30 O MOD2_BIAS TCXO Frequency D A Adjust DAC_OUT2 PA6 31 POWER_DET Power Detect High Active ADC12_IN6 32 O PA7 POWER_C Power Control High Active 33 PC4 TEMP1 Temperature 1 input 34 PC5 TEMP2 Temperature 2 input PBO 35 RSSI RSSI Detect Input ADC12_IN8 PB1 36 BUSY Carrier Detect Input ADC12 IN9 37 1 0 PB2 BOOT1 FM_SW FM Receive IF Switch High Active 38 O PE7 FM_MUTE FM RX Mute High Active 39 O PE8 VCOVCC_SW RXVCO TXVCO Control High for RX 40 O PE9 DMR_SW DMR Receive IF Swi
6. Noise Amplification IC13 NJM2902V Receiver demodulated signal Amplification Filtering IC14 TA75W01FU MIC Amplification IC715 TDA2003 Audio Frequency Power Amplification IC15 W25080 FLASH Channel Frequency Data Storage Function Setting Parameter Debug Mode Parameter IC3 STM32F405VGT6 MCU 1C4 PST9124NR MCU Reset Circuit 1C1 HR_C5000 1 Base Band Processor 1C401 W25Q64FVSIG LCD board FLASH IC403 R5F212BCSNFP LCD board MCU 12 Table 5 Definition of the connector J4 Pin No Name Function Description 1 VOL_OUT Received audio output 2 EXT MIC External MIC signal input 3 IGN IN Ignition input 4 DEO Received signal demodulation output 5 EXT_PTT External PTT 6 Port1 Programmable auxiliary port 7 Port2 Programmable auxiliary port 8 GND Gnd 9 Port3 Programmable auxiliary port 10 5C DC 5V 11 USB_D USB 12 USB_D USB 13 DTMFIO DTMF signal input or output 14 GPS TXD GPS serial data output 15 GPS RXD GPS serial data input Table 6 Definition of the connector J5 and J902 Pin No Name Function Description 1 SPGND AF GND 2 SPOUT AF out 3 8M 8V DC supply 4 RXD RXD PC serial data 5 TXD TXD PC serial data 6 POWER Power key 7 MIC Microphone input 8 GND GND Table 7 Definition of the connector J901 Pin No Name Function Description 1 CM MIC data detection 2 HOOK RXD HOOK PC serial data 3 MIC MIC
7. and then MCU prohibit transmitter from transmitting with a warning tone Q8 the power filter can provide PLL with more purified power to reduce the noise of frequency synthesizer 5 Base Band Processor HR_C5000 1 IC1 is a low power high performance base band processor supporting Tier 1 and Tier 2 of the DMR protocol it completes the entire physical layer and data link layer and voice processing part of the call control layer of DMR compliant with ETSI TS 102 361 HO Lout IF_out C Bus O Lr Tierl Il Modulator LO Qout Mod1 McBSP O McBSP VoCoder Interface E SPI SPI O RF Control Pre E E CodeC 2 O Unit In a eo eee HP_out mp p ND Lo an Line out O CodeC user Power oe Interface Interface System PS SPI Manager Clock 6 6 606 SPI 3 3V CLKOUT XTALI Interupt Figure 8 Base Band Processor 6 Voice Circuit The station is equipped with Voice Prompt Function which is very useful during night or under dark condition The speaker will voice the current channel number when changing the channel every time because of the voice memory chip IC15 which stores channel voice prompts It will repeat the current channel number once pressing Voice Prompts The speaker will voice the current channel number under standby state if the Voice Prompt Function is set Press Voice Prompts for reset to switch voice types Press Voice Prompts repeat
8. E er je A T 7 49 95MHz an o WI fr E APCITV lar APC TV W 1098 450KHz CF501 CF502 CTC DCS_OUT AMP AMP gt Second To E gt sc en gt 023 RSSI ze ka a bas PBR951 gt BUSY Q 9 DMR sote E Me OS SSS SS SS SS SS SS SS SS SS SS Se SS REE il 29 4912MHz 3 Katzen sc a DMR ver si A an eS eS el EE 3 105 NJM2902V I em 8M i 1C75851F BAIS BAND ele AF PROCESSOR FOUT D400 AMP 10404 LED Leo 9401 l BCA gig i XC6201P332MR RED GREEN TA T Cap em ep DEG sm gt gt am ava HPF E HPF k LPF gt LPF gt ar DO WI a400 a401 I 0715 0716 10715 ve kr ix E A d s pronaee DO SW PO SW cu spout S12302 TDA2003 PT2257 aros aros 7 T 7 RLED GLED AR voL SW AMP I lt sw E T sel Tasa Te T T 3 i SPKSW MTE Y MIC LCD MODULE I z GND A Lop 1015 RESET d Cant LAMP PIT Ls FLASH fe S 1 VOX aen Em SS ENt i es BUSY 10403 RXDO ERDEROGESSSE MICROPROCESSOR x2 8 GLED De BRC gt I XQUT LED au ES HA Sj Gi XN GER xao x K 7 MR SW TXDO APCSW 9 8304MHz Ki 8 ava PLL cS i ava PLL_CLK aan 10148 Ge pan KEY BOARD WEN NM2900V pada me y we SE rey E an 4 E sPouT gt sp eni ZS o l Te sv i GND CG 2 Sad SL e SE a228L638 IE microw_c 3 EF lumcan S Det E 3 gE AAA AA ze OOO HON ir ri Te 2 25565 A PAD IR YA NA
9. R920 UDZVTE 6 28 BRI R909 o A E 1k a C R919 R921 Tai p ED TX LE IOUS Y Deos D912 id Se DM6000 LCD T MC2850 MC2850 10R D400 x D401 trio PS PN 019 4 1 RLED Q400 0401 DTC114EE DTC114EE GLED 0402 2R410 470p 8 2k Title DM6000LCD Size Number Revision D Date 12 Jun 2015 Sheet of File E DM6000ER Fr DM6000 2PCBDM6O0O 2VO1 ddb Drawn By o SO KOSCH 00000 9 00000 o 0 em 0 e a o o a e Hs ER E JD
10. Tile DM6000 2 DM6100 2 BLOCK DIAGRAM Size Number Revision As VER 1 0 Date Sheet d l File Drawn By 3 4 5 6 7 8
11. shall be made to the station technical data after changing the components during the maintenance The debugging introduction of some related circuits goes as follows Some parameters of the product can be adjusted Interphone Performance Tuning by use of ARDOO1 Programming Software of our company The adjustable parameters are as follows Frequency stability 2 Transmitting power 3 Alarm threshold for battery low voltage 4 Sguelch level 5 QT frequency offset 6 DCS frequency offset 7 Receiving sensitivity Steps for adjustment a Enter Computer Test Mode by selecting Test Mode in main menu of ARDOO1 Programming Software b Select the items to be adjusted in choice menus and then adjust the parameters by function keys on the computer keyboard c Exit Computer Test Mode after adjustment 3 Adjustment 3 1 VCO Adjustment Close Power saving Mode Set receiving frequency to low frequency point see Table 2 and in the receiving state test voltage of PD by DMM and adjust fine tuning capacitor TC1 TC2 to get CV voltage of 1 0V 0 2V Set transmitting frequency to high frequency point refer to Table 2 press PTT and test voltage of PD by DMM which shall less than 4 0V Table 2 High Intermediate Low Frequency Point of All Models Low Frequency Point Intermediate High Frequency Point Frequency Point DM6000 2 DM6100 2 400 100 MHz 435 100 MHz 469 975 MHz 3 2 PLL freq
12. signal input 4 ME MIC GND 5 PTT TXD PTT PC serial data 6 GND GND 7 PSB 8V DC supply for MIC 8 MBI Key detection 13 ADJUSTMENT 1 Required Test Equipment signal source Table 1 Number Name Parameter requirements 1 Computer Above P2 compatible IBM PC WINDOWS 98 ME 2000 XPOperating System 2 Programming CPS2015 software 3 Programming cable Dubbing cable CPL 02 DC regulator Output voltage 13 8V output electric current gt 20A 6 Test range 0 5 60W RF power Frequency range 100MHz 500MHz meter Resistance 500 SWR lt 1 2 Frequency range 0 1 600MHz Frequency ji ei 7 Frequency accuracy higher than 1x10 meter Sensitivity higher than 100mV 8 Frequency Frequency range DC 600MHz deviator Test range 0 5kHz 9 Input resistance above 10MQ V DC capable of measuring voltage electric current en and resistance 10 Audio signal Frequency range 2 3000Hz generator Output level 1 500mV 11 RF power Decrement 40db or 50db attenuator Receive power higher than 60W 12 Standard Frequency range 10MHz 1000MHz Output level 0 1uV 32mV 127dBm 17dBm 13 Frequency range DC 20MHz Oscillograph Test range 10mV 20V 14 Audio Test range 10mV 10V Frequency voltmeter Recommend how to use item 6 7 8 10 11 and 12 which listed in the table can be substituted by integrated tester HP8920 HP8921 14 2 Adjustment Items Some detection and adjustment
13. DM6000 2 DM6100 2 Circuit Description 1 Frequency configuration The reference frequency of frequency synthesizer is provided by 16 8MHz crystal oscillator X3 TCXO The receiver adopts quadric mixing mode The first IF is 49 95MHz and the second IF is 450kHz The first local oscillation signal of the receiver is produced by frequency synthesizer and the second local oscillation signal selects the 3 harmonics of 16 8MHz of crystal oscillator X3 TCXO The signal of transmitter is produced by frequency synthesizer directly ANT SW BASE BAND PROCESSOR Q303 IC302 Figure 1 Frequency configuration 2 Receiver Rx The receiver is double conversion superheterodyne designed to operate in the frequency range of 400 to 470MHz The frequency configuration in Fig 2 RF AMP BASE BAND PROCESSOR Figure 2 Receiver section configuration Front End of Receiver Signals from the antenna are filtered by BPF which consists of C570 C571 C573 C576 C574 L514 L515 D508 and D509 via RX TX switch D306 D307 and D309 D311 After being filtered out the useless out of band signals the signals are amplified by LNA consisting of Q505 and external components Signals from LNA are filtered again by BPF which consists of C557 C553 L510 L511 D505 D506 and 1 D906 before entering the 1st mixer Q504 The PWM wave is output by MCU composed of 29 foot and then commutated to adjustable voltage after filtering to change the capacity of varactor diod
14. ctified by a filter and an amplifier to produce a DC voltage corresponding to the noise level The DC signal from the FM IC goes to the analog port of the microprocessor IC3 IC3 determines whether to output sounds from the speaker by checking whether the input voltage is higher or lower than the preset value To output sounds from the speaker IC3 sends a high signal to the FM MUTE and SPKSW lines and turns IC715 on through Q704 Q705and Q716 Audio Power Amplification The audio power amplifying circuit consists of IC715 and the peripheral components The signals are amplified by audio power amplifier to drive the speaker after collecting the receiving audio signals voice signals and warning tone signals The warning tone has no volume limitation When SPKSW is high level Q716 is on IC715 begins to work and the speaker sounds Speaker Impedance 8ohm CTCSS Signal filtering The audio signals after demodulation in 1813 may contain CTCSS continuous tone control squelch system or DCS digital squelch signals The spectrum component of CTCSS DCS is 67 to 250Hz The filtering circuit composed of IC10 can filter out signals except CTCSS DCS spectrum which makes MCU decode the CTCSS DCS more accurately 3 Transmitter Tx Transmitter Power Amplifier Q10 Q303 IC302 D306 D307 POWER MODULE ANT TORX Figure 4 Schematic Diagram for Power Amplifier and Antenna Switch The modulated RF signals from VCO are amplified by Q10 Q303 bef
15. e D505 D506 D508 D509 and D906 to control the center frequency of BPF 1 mixer The first IF 49 95MHz signal is produced after mixing of the receiving signal from LNA and the 1 local oscillation signal from frequency synthesizer The first IF signal is filtered out adjacent channel and other useless signals by crystal filter XF501 IF Circuit The 1 IF signal from crystal filter is amplified by the first IF amplifier Q503 before processing of IC in IF 1C501 GT3136 IF IC consists of the 2 mixer 2 local oscillation IF amplifier limiter frequency discriminator and noise amplifier Frequency 16 8MHz produced by TCXO X3 is amplified and then selects 3 harmonics 51 4MHZ as the second local oscillator signal source The second IF signals 450kHz are generated after signals mixing of the second local oscillation 51 4MHz and the first IF 49 95MHz in IC501 Audio signals are demodulated and outputted by IC501 after the second IF signals are amplified and limited in IC501 and then filtered by ceramic filter 450kHz 450KHz Noise Amp 49 95MHz FM Demodulator Figure 3 Schematic Diagram for IF System 2 Receiving Audio Signal Processing The audio processing circuit of receiver consists of IC300 Voice signals from IC300 are sent to IC301 CTCSS signaling filter circuit Squelch Circuit Part of the AF signal from the IC501 enters the FM IC again and the noise component is amplified and re
16. edly for power connection then the voice types will be switched in circle in the order of Chinese male voice English male voice Chinese female voice English female voice no prompts 7 Power Supply The station use 13 8V power supply while transmitter amplifier circuit IC302 and receiver audio amplifier IC715 use directly for power supply and other circuits use regulated voltage 8V 5V and 3 3V 1C711 8C 8R 8T 8V LDO 1C713 8M 8V LDO IC710 5C 5V LDO IC21 3 3V DC DC IC7 3 3V LDO is the supply power of frequency synthesizer 8 MCU Unit MOD2 BIAS TO PLL CTC DCS OUT Tx Rx Control 1C15 OS eum FLASH POW_DET TOPC TO LCD BOARD Figure 9 Schematic Diagram for MCU Unit MCU Unit controls the operation of every unit to realize all functions of the DM6000 2 Communication with external PC State data access Control PLL for the generation receiving and transmitting of local oscillation frequency Access to the current channel state Control LED status indicator Control power supplied condition of every unit Detect action of every function key Produce CTCSS signal Produce DCS signal Produce power controlled signal Finish CTCSS decoding Finish DCS decoding Squelch detection and control Control voice prompt content Memory FLASH Channel data CTCSS DCS data and other function setting data and parameter adjustment data CTCSS DCS signal coding and decoding CTCSS DCS
17. elch RF OUT output 116dBm Computer jusiment Enable Test Mode y Sensitivity ama Level 1 squelch RF OUT output 123dBm opening after adjustment Table 5 Transmitting part Item Test condition Instrumentation Test point Correcting Reguirement Remarks member Frequency Counter Computer ai SES Integrated Tester Test Mode SZ Wes DES Oscillograph Computer Nearly waveform flat waveform Integrated Tester Test Mode balance Square wave SAWA SIETE Computer Within Power Hi Power 13 8V Integrated Tester Test Mode Adjust to 45W 0 2W Ammeter Power Tester Computer gt Within Power Lo Power 13 8V Integrated Tester Test Mode Adjust to 25W 0 2W Ammeter Max Ga Modulation on TUN Genel Computer Adjust to Frequency Point 200Hz Frequency Frequency Antenna Test Mode 4 2kHz AG 1kHz 120mV k A Offset deviator Integration Test CH Transmitting Center SR n Check Modulation Freguency ER Frequency Point Sensitivity AG 1kHz 12mV Offset s 2 2kHz 3 6kHz Frequency A CTCSS A Computer Adjust to DEV CTCSS 67Hz deviator Integration Test Mode 0 75kHz 50Hz Tester Frequency d Computer Adjust to DCS DEV DCS 023N oe Test Mode 0 75kHz 50Hz 18
18. formance Tuning Mode adjust potentiometer VR1 to observe demodulated signal the waveform shall be smooth and similar to square wave and then click Broadband to adjust all points including Lowest Low Mid High and Highest respectively for frequency offset of 0 8kHz After that click Narrowband to adjust the frequency offset to 0 4kHz 3 7 CTCSS frequency offset adjustment Double click to enter QT 67 frequency offset in Interphone Performance Tuning Mode and click Broadband to adjust the five frequency points including Lowest Low Mid High and Highest respectively to 0 75kHz and then click Narrowband to adjust the frequency offset to 0 35kHz Select QT 254 frequency offset in Interphone Performance Tuning Mode and the debugging method is the same as that of QT 670 frequency offset 3 8 Receiving Sensitivity Double click to enter Receiving Sensitivity in Interphone Performance Tuning Mode to adjust the five frequency points including Lowest Low Mid High and Highest respectively and the number from 0 to 255 for setting max sensitivity of all points 3 9 Receiver Squelch setting Double click to enter SQL9 open in Interphone Performance Tuning Mode and click Broadband to make the frequency of the transmitting signal corresponding to the receiving frequency level of 116dB
19. itor to Ground 74 S VSS_2 VSS_2 Connect to Ground 75 S VDD_2 VDD_2 Connect to 3 3V JTCK SWCL 76 1 0 K Port1 Programmable port 1 PA14 PA15 77 O DS FS DMR 128 FS 1253 WS PC10 78 O 2S CK DMR DS CK 1253_CK PC11 79 O I2S_RX DMR 12S_RX I2S3ext_SD PC12 80 DS TX DMR 128 TX 2S3 SD 81 1 0 PDO SPKSW Speaker Output Control High Active 82 1 0 PD1 Port2 Programmable port 2 83 1 0 PD2 Port3 Programmable port 3 84 UO PD3 MIC_MUTE MIC mute H MIC mute 85 UO PD4 EXT_SW EXT MIC SW 86 UO PD5 WIDE 25kHz 87 UO PD6 NARROW 12 5kHz 88 O PD7 V_CS DMR V_CS PB3 89 O V SCLK DMR V SCLK SPI3 SCK PB4 90 V SDO DMR V SDO SPI3 MISO PB5 91 O V SDI DMR V GD SPI3 MOSI 92 O PB6 SPM Audio Amplifier Control High Active 93 O PB7 NC 94 BOOTO BOOTO Connect a 10K resistor to Ground PB8 95 O SCL Software Control Watch Dog Serial Clock I2C1_SCL PB9 96 O SDA Software Control Watch Dog Serial Data I2C1 SDA 97 O PEO MICPWR_C MIC Power Switch High Active 98 O PE1 INT Interception 99 S VSS_3 VSS_3 Connect to Ground 100 S VDD_3 VDD_3 Connect to 3 3V Table 4 Functional description of semiconductor device Item Model Function Description 1C8 SKY72310 Frequency Synthesizer IC303 NJM12904RB1 APC Voltage Comparison Driving IC501 GT3136 Receiver 2 Local Oscillation 2nd F Amplification Limitation Demodulation
20. m modulation signal of 1kHz and frequency offset of 3kHz showed at each frequency point of the software Enter all points including Lowest Low Mid High and Highest respectively for automatic adjustment of software and then press next point after no big change to numbers After that adjust Narrowband the debugging method is the same as that of Broadband except the input modulation signal is changed to frequency of 1kHz and frequency offset of 1 5kHz Select SQL9 open in Interphone Performance Tuning Mode and click Broadband to make the frequency of the transmitting signal corresponding to the receiving frequency level of 118dBm modulation signal of 1kHz and frequency offset of 3kHz showed at each frequency point of the software Enter all points including Lowest Low Mid High and Highest respectively for automatic 16 adjustment of software and then press next point after no big change to numbers After that adjust Narrowband the debugging method is the same as that of Broadband except the input modulation signal is changed to frequency of 1kHz and frequency offset of 1 5kHz Select SQL1 open and SQL1 close respectively in Interphone Performance Tuning Mode and adjust by the same method except the open level of transmitting signal changed to 123dBm and the close level to 125dBm 4 Receiving Low voltage Alarm Adjust power
21. ore the power amplification in IC302 Gate bias of Q303 and IC302 is controlled by APC circuit so the output power of transmitter can be 3 controlled conveniently by changing the gate bias voltage APC Automatic Power Control D313 and D314 are power amplification current detector IC303 is power amplification current sampling amplifier and power comparison amplifier The power amplification current and IC303A output will increase with oversized output power of transmitter When the output voltage of IC303B decreases the bias voltage of Q303 and IC302 will decrease finally the output power of transmitter will decrease or vice versa Thus the output power of transmitter will keep stable under any different working condition MCU can set the power by changing the voltage input to IC303B Audio Signal Processing of Transmitter IC1 IC14 BASE BAND PROCESSOR TCXO CTC DCS Figure 6 Schematic Diagram for Audit Circuit of Receiver The audio signal processing circuit of Transmitter consists of IC14 and IC1 Voice signals from MIC are sent to VCO for modulation together with CTCSS DCS after amplification limitation and filtering IC1 is a bais band processor AGC circuit consists of D12 D13 and Q20 Q21 The signal amplitude is reduced to ensure no distortion in case of oversized MIC signal Q12 the power switch of voice processing circuit controlled by MCU will give power supply to IC 14 only during transmission
22. s set the speaker is available only when receiving the same DCS code to avoid the disturbance of useless signals The station has 83 kinds of standard codes including positive and inverse code for your selection such as Table 2 DCS signals produced by MCU PWM waveform are sent to TCXO for modulation CTCSS DCS signals from receiver are sent to MCU for decoding and then MCU test if there are DCS codes with the same setting of the station to decide whether open the speaker or not Table 2 DCS Coding Schedule 023 114 174 315 445 631 025 115 205 331 464 632 026 116 223 343 465 654 031 125 226 346 466 662 032 131 243 351 503 664 043 132 244 364 506 703 047 134 245 365 516 712 051 143 251 371 532 723 054 152 261 411 546 731 065 155 263 412 565 732 071 156 265 413 606 734 072 162 271 423 612 743 073 165 306 431 624 754 074 172 311 432 627 9 Description of Semiconductor Devices The distribution of each pin goes as the table 3 Table 3 Definition of CPU Base Pin Pin Type Pin Name Port Name Function 1 O PE2 FLASH CS SPI Flash Chip Select FLASH SCLK SPI Flash Serial Clock 2 O PE3 i LCD_DB6 LCD_DB6 multiplexing 3 PE4 FLASH SDO SPI Flash Serial Data S o See FLASH_SDI SPI Flash Serial Data Output MCU LCD_DB7 LCD_DB7 multiplexing 5 O PE6 DMR SLEEP DMR POWERDOWN High Active
23. signals from MCU are sent to TCXO for modulation respectively CTCSS DCS signals from receiver are sent to MCU pin 25 for decoding and then MCU test if there 7 are CTCSS DCS signals with the same setting of the station to decide whether open the speaker or not CTCSS continuous tone control squelch system hereinafter referred to as CTCSS is a kind of squelch control system with modulation on carrier and continuous sub audio signals as pilot tone If CTCSS function is set the call is available only at the same CTCSS frequency of both receiving and transmitting parties to avoid the disturbance of other signals The station has 39 groups of standard CTCSS frequency for your selection such as Table 1 CTCSS signals produced by MCU are sent to TCXO for modulation Table 1 CTCSS Frequency Table No Frequency No Frequency No Frequency No Frequency Hz Hz Hz Hz 1 67 0 11 94 8 21 131 8 31 186 2 2 69 3 12 97 4 22 136 5 32 192 8 3 71 9 13 100 0 23 141 3 33 203 5 4 74 4 14 103 5 24 146 2 34 210 7 5 77 0 15 107 2 25 151 4 35 218 1 6 79 7 16 110 9 26 156 7 36 225 7 7 82 5 17 114 8 27 162 2 37 233 6 8 85 4 18 118 8 28 167 9 38 241 8 9 88 5 19 123 0 29 173 8 39 250 3 10 91 5 20 127 3 30 179 9 DCS signaling DCS Digital code squelch is a kind of continuous digital code modulated on carrier with voice signal and used for squelch control If DCS function i
24. tch High Active 41 PE10 RF_APC_SW RF Amplifier Switch High Active 42 O PE11 8RC 8R Power Switch Control High Active 43 PE12 NC 44 PE13 ALARM KEY Top Key Input 45 PE14 NC 46 PE15 8TC 8T Power Switch Control High Active 47 PB10 TXD Serial data output 48 PB11 RXD Serial data input 49 S VCAP_1 VCAP_1 Connect a Capacitor to Ground 50 S VDD_1 VDD_1 Connected to 3 3V PB12 51 O DMR_CS C5000 Chip Select SPI2_NSS PB13 52 O DMR_SCLK C5000 Serial Clock Output From MCU SPI2_SCK PB14 E 53 DMR SDO C5000 Serial Data Input SPI2_MISO PB15 54 O DMR_SDI C5000 Serial Data Output SPI2_MOSI 55 PD8 PLL_LD PLL Lock Detect High Active 56 O PD9 PLL_CS PLL Chip Select 10 57 O PD10 PLL_DAT PLL DATA Output 58 O PD11 PLL_CLK PLL Clock Output 59 O PD12 NC 60 O PD13 PT2257 SDA To PT2257 61 O PD14 PT2257 SCL To PT2257 62 O PD15 FL_C Fast Lock Switch Control High Active PC6 TIM8_C 63 O H1 u FAST_LOCK Fast Lock PWM Output PC7 TIM8_C 64 O Ho u CTC DCS_OUT CTCSS DCS TCXO Output PC8 TIM8_C 65 H3 E BEEP BEEP ALARM DTMF Output 66 O PC9 EXT PTT Ext PTT Input Ignition Sense 67 O PA8 IGN H IGN Sense off L IGN Sense on PA9 68 GPS TXD i USARTI_TX GPS serial data output PA10 69 GPS RXD i USART1_RX GPS serial data input PA11 USBD 70 1 0 M USBD USB DM PA12 USBD 71 1 0 p USBD USB DP JTMS SWDI 72 1 0 O NC PA13 73 S VCAP_2 VCAP_2 Connect a Capac
25. uency calibration Double click to enter Frequency Stability in Interphone Performance Tuning to achieve the rated transmitting frequency by adjusting the number from 0 to 255 Error lt 200Hz 3 3 Transmitting frequency adjustment Double click to enter Transmitting High Power in Interphone Performance Tuning to adjust the five 15 o o nb frequency points including Lowest Low Mid High and Highest respectively and set transmitting power to over 45W by adjusting the number from 0 to 255 and observe the operating current lt 10A at the same time Double click to enter Transmitting Low Power in Interphone Performance Tuning to adjust the five frequency points including Lowest Low Mid High and Highest respectively and set transmitting power to over 25W by adjusting the number from 0 to 255 3 4 Transmitting low voltage alarm Adjust power voltage to 10V and double click to enter Transmitting Low Voltage in Interphone Performance Tuning Mode for automatic detection of the software and then click Save for exit after no or little variation in numbers 3 5 Frequency offset adjustment Input audio signal 12mV 1000Hz at MIC jack of interphone Adjust and set frequency offset to 4 2kHz 3 6 DCS transmitting signal waveform and frequency offset adjustment Double click to enter DCS frequency offset in Interphone Per
26. voltage to 10V and double click to enter Receiving Low Voltage in Interphone Performance Tuning Mode for automatic detection of the software and then click Save for exit after no or little variation in numbers 5 Adjusting explanation Table 3 Voltage controlled oscillator Item Test condition Instrumentation Test point leg Requirement Remarks member A Supply voltage battery Setting terminal 7 4V BMM er CH Receiving low A Locking equis point TC2 1 0V 0 2V Adjustment voltage T CH Transmitting high lt a 0V Gbsewaton frequency point Table 4 Receiving part Item Test condition Instrumentation Test point Correcting Remarks Requirement member Audio Test frequency RF signal Volume knob Power of Power Intermediate Frequency generator Speaker clockwise to the Point Interface the end Audio internal Antenna Interface Input Oscillograph Power gt 0 3W speaker RF OUT f gt 2W 53dBm 501uV Audio frequency MOD 1kHz voltmeter DEV 3 0kHz distortion test Audio load 160 ee 17 CH Low Frequency Computer SINAD Point Integrated tester Adjustment 12dB or higher CH Intermediate Frequency Point Sensitivity CH High Frequency Point RF OUT 119dBm 0 254V MOD 1kHz DEV 3 0kHz CH Receiving Center Normal Frequency Point squelch Level 9 opening after Squ
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