Home

BBC Microcomputer Service Manual Oct 1985 Section 2 BBC Micro

1. All graphics access is tra Shadow mode gives 32K nsparent in any screen mode The shadow scree mode 0 to 7 screens shadow program is free RAM In the The 12K bytes of 12K paged RA or non shadow Serial interface to b inter operabl selectable be An 8 bit input t out to RS423 s with RS232C equipment n 75 baud and 19200 baud Mode 0 640 x 256 2 colour graphics and 80 x 32 text 20K Mode 1 320 x 256 4 colour graphics and 40 x 32 text 20K Mode 2 160 x 256 16 colour graphics and 20 x 32 text 20K Mode 3 80 x 25 2 colour text only 16K Mode 4 320 x 256 2 colour graphics and 40 x 32 text 10K Mode 5 160 x 256 4 colour graphics and 20 x 32 text 10K Mode 6 40 x 25 2 colour text only 8K Mode 7 40 x 25 Teletext display 1K Mode 128 640 x 256 2 colour graphics and 80 x 32 text 20K Mode 129 320 x 256 4 colour graphics and 40 x 32 text 20K Mode 130 160 x 256 16 colour graphics and 20 x 32 text 20K Mode 131 80 x 25 2 colour text only 16K Mode 132 320 x 256 2 colour graphics and 40 x 32 text 10K Mode 133 160 x 256 4 colour graphics and 20 x 32 text 10K Mode 134 40 x 25 2 colour text only 8 Mode 135 40 x 25 Teletext display 1
2. IC3 4013 CMOS dual J K flip flop 8271 FDC only The two J Ks are used to detect disc speed When a drive is off pin 13 is set to logic 1 by the logic 1 notMOTOR signal fed through resistor R2 Pin 2 is held at 1 by the first J K Q19 of ICA pin 11 has no effect as Dl will always be biased off When a drive starts notMDTOR goes low allowing the first J K to be clocked by index pulses If an index pulse occurs when Q19 of ICA is at 1 then the first J K will stay set which means the disc is slow If 019 is 0 when an index pulse occurs the J K will reset and allow the second J K to be clocked The next index pulse will set the second J K pin 2 goes low indicating drive ready This state is inhibited if the disc speed is slow as the first J K will be immediately set and so force the second J K to reset pin 2 high ICA 4521 CMOS 24 stage binary divider 8271 FDC only Used as a 2 to the power 18 divider It counts cycles of 16 13 MHz to time a period of about 213ms 2 18 812ns The divider is reset by each index pulse so if Q19 goes high then the disc is slow If the disc is very slaw such that 019 goes law high low between index pulses the diode Dl ensures that the J K IC3 remains set IC5 7415244 Octal buffer Permanently enabled buffer for the CENTRONICS campatible printer interface data lines IC6 7415244 Octal buffer E Buffer
3. 34 way IDC 33 34 a MMioMiMiMMiMiMiMiMiMiMiMiii 1 0V 2 notS SEL 8 3 OV 4 notINX 8 5 OV 6 NC 7 OV 8 notINX 5 1 4 9 OV 10 50 11 OV 12 notsi 13 OV 14 NC 15 OV 16 notMOTOR 17 OV 18 notDIR 19 OV 20 notSTEP 21 22 notW DATA 23 OV 24 notWR EN 25 OV 26 notTKO 27 OV 28 notWR PCT 29 OV 30 notR DATA 31 OV 32 notS SEL 5 1 4 33 0 34 notRDY 8 PL9 printer 26 way IDC 25 1 26 9 1 STB 2 OV 3 PAO 4 0V 5 PAIL 6 OV 7 PA2 8 OV 9 10 OV 11 PM 12 OV 13 PA5 14 OV 15 PA6 16 OV 17 PAT 18 OV 19 20 OV 21 22 OV 23 NC 24 OV 25 NC 26 NC 60 PL10 user port 20 way IDC 1 20 2 1 5V 3 5 4 CB2 5 OV 6 PBO 7 OV 8 PBI 9 OV 10 PB2 11 OV 12 PB3 13 OV 14 4 159 OV 16 PB5 17 OV 18 PB6 19 OV 20 PB7 PL11 1MHz bus 34 way IDC 33 34 2 2 2_2 2 1 ___ 1 OV 2 R notW OV 4 1E 5 20M 6 notNMI 7 OV 8 notIRQ 9 OV 10 notPGFC 1i 0V 12 notPGFD 13 OV 14 notRS 15 OV 16 audio in out see S17 17 OV 18 DO 19 D1 20 D2 21 D3 22 D4 23 D5 24 D6 25 D7 26 OV 27 28 11 29 A2 30 31 4 32 5 7 w w gt PL12 TUBE I
4. prevent a single computer holding its driver on and thereby bringing the whole network down Receive data is decoded by a comparator circuit IC92 and fed into the 68B54 IC93 the collision detect ciruitry is not fitted because th software protocols should prevent any collision Before transmission the line is sampled to see if it is in use If it is the transmission is held up until a certain time after the line is first free again This time is dependent on the station ID and so will be different for every station on the lin When required collision detect may be installed by fitting components as shown on the circuit diagram and breaking the link 529 copper link 5 12 Cassette and RS423 ports For both the cassette SK5 RS423 SK4 interfaces 6850 asynchronous communications interface adaptor C82 is used to buffer and serialise or deserialise the data The serial processor IC85 contains two data clock separator programmable either RS423 or cassette operations the cassett a sinewave to be Note that the receive bit rate E fed out CO the FSK signal not from the serial processor control RS423 operation is selected used when baud switching to select and also a circuit to synthesise rate recorder generators a cassette or cassette operations is derived from regist
5. 1 0103 001 KEYBOARD ISS 2 1 INC SPEAKER 2 0201 233 CASE UPPER ISS 5 1 3 0201 232 CASE LOWER ISS 4 1 4 0201 098 REAR ACCESS LABEL ISS 6 5 0201 111 BOTTOM ACCESS LABL 1554 6 0201 096 KEYBOARD LABEL ISS 4 1 7 0800 600 BNC CONNECTOR 75R 1 8 0890 000 STICK ON FOOT 4 9 0882 988 4BA INT WASHER 2 10 0882 986 NYLON WASHER 1 D 5 5 11 0882 948 No 8 SPIRE NUT 2 12 0882 914 4BA NUT FULL 2 13 0882 712 No 4x7 16 PAN HD SUPER 2 14 0882 649 No 8x19 FL HI POSI 4 15 0882 644 No 8x9 5 FL HD POSI 5 16 0882 343 4BA x 5 8 PAN HD POSI 2 121 0882 122 M3 x 8 PAN HD POSI 3 18 0831 105 P S U 1 68 Glossary ACK ACKnowledge line on the printer port ACIA Asynchronous Communications Interface Adaptor serial to parallel and parallel to serial converter 6850 ADC Analogue to Digital Converter ADLC Advanced Data Link Controller ECONET control IC 68B54 ADSR Attack Decay Sustain Release defining the envelope of a sound ASC American Standard Code for Information Interchange binary code for representing alphanumeric characters BASIC Beginners All purpose Symbolic Inst
6. 12 35 ge Tor Tor a Tor nks on the PCB Bu 8 B disable NMI EOE Bn for removed for East for 32K S10 PCB track made East East enables keyboard BREAK key West forces permanent reset broken neither East nor West disables BREAK key S11 plug made West West for 8K 16K ROM EPROM in 44 East for 32K ROM EPROM in 1C44 S12 plug made West West for 8K 16K ROM EPROM in IC57 East for 32K ROM EPROM in IC57 S13 plug made South South causes BASIC to take high priority ROM numbers 14 15 North causes BASIC to take low priority ROM numbers 0 1 S14 plug made North North gives white on black video South gives black on white video Beware monitor performance in the latter configuration S15 plug made West West for 8K 16K ROM EPROM in IC62 East for 32K ROM EPROM in IC62 S16 test link not present on issue 2 or later PCB 51 Sout S18 plug ROM EPROM i n h for output made West IC68 West for 8K 16K ROM EPROM in 7 track made North North configures 1MH IC68 bus audio f or input for 32K 33 519 disabl es B track made BAS
7. 8114 SK3 AQ kakak Dv 4 9 7 32 ES GREEN E pou s jet R MZ mal 982 1984 953 RIOS Le eed UN EPIO 7 os Se 1586 94 58 12 e A 74590 lue ski jour 75 pte A 745 BEA n 8 ese FASTON 2 56 Tan TABS E 891 30V 10v 0 4 4 0 50 10v 5v SUPPLY TO EN 7 1029 1637 PIN av 1289 PINT T 196 PINS 2115 R133 RISO PLIS PINI 1047 tl R122 5 39 x2 ERA Dt 55 9154 17 734475 D 100pF va cag 4 5 65 3906 csi Q 52 116 100pF T low gt EL ARIZ E h 2 OPTION TO REPLACE OFF 4164 12 a m x SW31I 69868 SWILI EZ Seno p 23 gt E m rese E ess 1 124 6 Eres To amd ss E LEN E gt Ts Ni gt un os ITEM 163 902 Wall yoo 15 D 162 ITEM 154 154 ITEM 147 147 cre
8. 99 9 16 ET only be serviced properly by ECONET service centres who will have the necessary test equipment to check the system thoroughly However there are a few simple things which can Pe checked without the Chec test equipment k that all the ECONET components are installed and have been fitted correctly see 6 3 Chec 523 56 that notNMI on the CPU pin 6 IC42 is not being held low If the system will not give a correct ID number then use the shunts to find which track is broken or shorting Appendix 57 Connector pinouts SK1 out phono outer ground inner UHF SK2 video out BNC outer ground inner video SK3 RGB 6 pin DIN SK4 RS423 5 pin DIN Data in SK5 cassette 7 pin DIN 58 SK6 analogue 15 way D type 1 O O O O OOOO O O O 208 OO 5V OV OV CH3 analogue ground OV CH1 analogue ground SK7 5 pi ECONET n DIN p p nm o p light strobe digital switch input ltage reference vol CH2 digital switch input vol CHO tage reference notLPSTB VRE VRI 11 59 PL8 disc drive
9. The 1770 is expected to be the standard disc interface A 1770 operates in either single density FM or double density MFM mode and has data separator and disc speed decision logic built in A much timing of data S5 is availa controller i incorporates not2M into the chip select signals transfers betw n the disc controll nterrupts The disable unc 5 6 Display circ uitry Three display out tputs are provided RGB simpler disc interface results ICs 1 2 3 4 and 9 are not needed No drive select logic is incorporated a 1770 so is fitted for this function also latches two contol signals which are used to select between FM and MFM operation and to reset the 1770 both under program control The control register is a write only device which occupies the address space amp FE80 to amp FE83 IC23 gates the decoded address signal with notW IC27 pin 6 to form the control register clock All 1770 registers are addressed in the range amp FE84 to amp FE87 It can be seen that the 1770 controller and the 8271 controller address space has been swapped This is to allow the disc system software to distinguish between the two devices Two interrupt signals come from a 1770 pins 27 and 28 The two interrupts are
10. iv Insert the filing system ROM DNFS into a vacant sideways ROM Socket IC 35 44 57 62 or 68 v Make link S7 West with a shunt or tinned copper wire if molex pins not fitted vi Break link S8 by removing shunt if fitted vii Test using a PORT tester Note If an 8271 disc interface is being fitted as a replacement for an existing 1770 disc interface the following items must be removed from the PCB IC16 1770 17 15174 Link 58 must be broken 28 WEST mo 57 1C3 40136 1C 44 Jn 6 6 5 1 15 3x150 8271 PLO 34 WAY 8271 Disc interface components 29 6 3 Local area network interface Due to the complexity of this upgrade and the specialised test equipment required it should only be carried out by ACORN Approved ECONET Service Centres with the appropriate test equipment Upgrade procedures and requirements as notified by suppliers should also be adhered to and reference should be made to any available information updates for lates
11. These four ICs OS BASI The top hal contains bottom half is a paged RO slot Link S19 is permanently made 1415253 Dual 4 select the G lf addressed from C000 to amp FFFF the machine operating except System program M containing E number South priority East selects North selects slots 0 1 for CP DRAM address current display mode and RAS CAS state during the VDU RAM read phase CAS address signals MA MA 13 from the CRTC rom IC36 is 13 is low during all low for normal RS IC78 selects the graphics Screen modes IC76 7416283 The adder is used IC78 Take mode 0 amp 3000 to amp 7FFF If step of 681000 5 the display is scrol address from the CRTC will 4 bit adder Mode 0 to 1 data selector slots 14 15 low priorit an for The Link S13 selects standard y U address A14 to 27 of ROM ICs signals according to the Not2M enables the four the RAS led L drives pin 14 to select RSL low selects the row address Screen modes Screen nodes and high for all notRAS cloc The VDUS EL sig in hardware say amp 4000 The display memory must st keep the CRTC address ffset is conditionally added to the actual to amp 8FFF
12. If machine works ess lines are present ter if available see information manual suppl this runs then the CPU is functioning correctl Check following BREAK Replace the OS BAS sure that S19 is made East 10 romsel 20 INPUT romnumber 30 DIM P 40 50 start 60 LDA romnumber 70 STA romsel 80 RTS 90 amp FE30 100 100 CALL start but sideways ROM selection is faulty ollowing program to test the ROM select latch If ROM circuitry is not functioning then the CPU will not operate ly in their lied to y that the OS ROM is enabled and that notOE pulses low at 2MHz inverse of phi2 and not CS goes low and stays C ROM with a known good one Make then run the Run the program and type in a number between 0 and 15 50 and amp F Check using representation of this number appears on pins 11 of IC45 12 13 Results a logic probe Or and 14 least significant if the ROM numbers are no then alter line 80 of the program 80 JMP start and re run the program oscilloscope that the binary Check with an oscilloscope that notPGLD from pin 13 IC36 is FE replace not work then check decoder 46 not then check for shorted track IC45 If notPGLD is working most significant t getting through to the RO
13. M is available to the user in any screen mode to the user shadow C or a user nd amp 7FFF plus BASIC program RAM less workspace n mode offers equivalent display sizes to the standard but using an auxiliary memory area the display modes nudes 128 to 135 BAS to use all memory between OSHWM PAGE a sideways paged RAM shadow tandard The new standard has been designed Baud rates are software guaranteed up to 9600 baud tput port with 2 control bits Each channel has an input voltage range is 10 milliseconds bus for connection to a variety of external Four analogue input channels of OV to 1 8V The conversion time for each channel The resolution of the ADC chip is 10 bits MHz buffered extension hardware such as a TELETEXT acquisition unit VINCHESTER disc drive etc Buffered interface for connection via the TU processors CENTRONICS compatible printer interfac The basic model Also Finally generat a low cost network i B hav either an 8271 or 1770 controll IC er nterface the Acorn PP 488 BE to a range of ECON a speech upgrade is available using the 4 predefined words and sounds through the b 5220 speech interface second e added to it a floppy disc interface using ET may be added to uilt in speaker
14. S20 pl fitted S21 optional S225 ug 523 eight pl 524 wire lin Should not be fitted 525 wire lin Should made South number by user Only Ea and leaves just enables St East BAS C pari t of OS BAS C West Ct ct South gives full the operating sys volume on audio D ugs seven shunts ECONET umber se audio output prior to volume control itted if ECONET interface fitted c E not E ted optional termin Remove if VR2 t up as binary or correct operat not f not be fitted 526 wire link not f composite video outp 27 plug gives positive goi 528 PCI NTSC need c 529 PC detect 530 PC 34 No ha B B track te hardware AG itted made adds chrom made South ng CSYNC B link made ted optional termin ation resistor for RS423 tion of RS423 ation resistor for RS423 correct operat tion of RS423 Ut made North for NTSC operation nging for TVs which cannot receive ch inance component South gives negative going CSYNC for track made made for operating EC ut out annel 36 RGB North North for PAL video circuitry R92 must be c
15. 40 way IDC Be HT MM 1 1 OV 2 R notW OV 4 2E 5 OV 6 notIRQ 7 OV 8 not TUBE 9 OV 10 notRS 11 OV 12 DO 13 OV 14 D1 15 OV 16 D2 17 OV 18 D3 19 QV 20 D4 21 OV 22 D5 23 OV 24 D6 25 0V 26 D7 27 0V 28 AO 29 OV 30 1 31 5V 32 A2 33 5 34 A3 35 45V 36 4 37 5V 38 NC 39 5V 40 NC PL13 keyboard l7 pin molex il lt REAK eyboard enable D4 D5 D6 DO 01 02 03 07 cassette LE CA2 to generate In T5V shift lock LED caps lock LED 0 020202 0 0 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 62 Part NOTE TEM UJ list tems identified by are normally available as spare parts PART NO Ro hp p Ri 15 oO C NH 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 0502 100 0502 330 0502 680 0502 820 0502 101 0502 151 0502 180 0502 271 0502 331 0502 471 0502 681 0502 821 0502 102 0502 122 0502 152 0502 182 0502 222 0502 272 0502 332 0502 392 0502 472 0502 562 0502 822 0502 103 0502 123 0502 153 0502 223 III TI BC Microcomputer Mode DESCR ON B ES ES ES ES ES ES ES ES E
16. IC SOCKET DIL 28P CONNECTOR IDC 34 CONNECTOR IDC 40 CONNECTOR IDC 26 PLUG 2 WAY PLUG 3 WAY PLUG 5 WAY PLUG 8 WAY PLUG 10 WAY PLUG 17 WAY CONNECTOR IDC 20 WAY WAY WAY WAY TINNED COPPER WIRE FASTON TABS SOCKET 5 WAY SOCKET SOCKET SOCKET SOCKET N 6 WAY N 5 WAY N 7 WAY TYPE 15 DOMI WAY p r2 N W 16 A R 1 IC57 1770 ONLY IC44 1ES3 IC85 OPTION FOR 4 IC36 16 85 1 29 35 37 44 53 1 57 62 68 71 PL8 11 PL12 PL9 15 526 813 14 20 27 SK3 A S9 11 12 15 18 S23 FU PL14 PL13 PL10 so ties 18 20 S23 70ff 27 57 8 16 12 32 5 3 0 3 5 1 SK7 SK3 SK4 SK5 SK6 67 222 0825 000 MODULATOR UM 1233 E36 1 SK1 223 224 225 226 0705 220 IC TMS 5220 SPEECH 1 IC29 227 0201 608 C SPEECH PHROM V1 6100 1 TC34 228 NOTE SOT denotes Select On Test and therefore the value of the component will vary from machine to machine BBC Microcomputer Model General Assembly
17. OR 75415393 Wye 16 7 996 t gt Eo lt a is 6548 120 741524 Isv 5 20 7171418 amp 7 1 retornos 9 7 W 4500 120162 70 misim to 20 415245 14 0 20 74525 15 120 8277 15 Lu 16116 7453 7 14 245500 ta De tasa 22 7 1 xiss 43717 Tu 24 17 76 504 5 8 151509 26 w 16504 1717 17445020 a e ms 29 111 5 1 552720 s 16 74559 35 7114 145 20 1453 33 7 w 174502 34 7 7 4506 35 14 78 36 20 ral 137 ETE 16 09 SEE TOP RIGHT HAND FOR SUPPLY DETAL SS ger m ov 5 7 ca CASLED 0 e ty 41 zs to 252 ces ROC E 855 CS 5 foc tas DE Tam 27 x c34 5 MsR 5Y EM 228 C ov Ge 74574 an 7615132 BETTEN 7415253 745263 7445253 7415283 386 2 22001 os ICH 242502 338 1058 Em IT S A E 5 1500 TES 5 x 93 M E x 380 239 4 Fit
18. rate the phase shif clock 1E from 1C25 ted 1MHz Ta The CPU is normally clocked at 2MHz The 6512 IC42 requires a two phase non overlapping clock on inputs phil pin 3 and phi2 pin 37 See figure tag 2M 01 Figure 1 Non overlapping clock inputs phil and phi2 Phil and phi2 are generated by IC33 two gates of which are used to build an R S latch Not2M from IC26 is used to set and reset the R S latch which toggles at 2MHz unless a third gate from IC33 blocks the not2M signal During 2MHz operation the phi2 clock corresponds to not2M the inverse of 2M from the video processor When accessing slow devices 1MHz extension bus ADC VIAs 6845 ACIA and serial processor the clock is stretched to give a pseudo IMHz cycle The system 1MHz clock E is generated in half of IC25 from the 1 2 and 2MHz outputs of the video processor The other half of IC 25 is used to synchronise the transition from 2MHz to 1MHz clocking Each 1 MHz peripheral select line is connected to an input of NAND gate 41 If any input of this NAND gate is taken to logic 0 then a 1MHz CPU cycle will occur For 1MHz cycles phi2 is held at 1 p ogic 1 until the 1E signal is synchronised The cycle ends with both p ux hi2 and 1E falling together 12 There are two ways which the transition from 2MHz to 1 2 tak
19. PAL ACORN no 0201 880 This device generat 1 A15 are logic 1 2 A14 low AND A sideways ROM enable orced high while 1 3 A12 low OR A13 to form notPGRAM Noi SRAM 4 notPGLD is formed active The PAL contains two 1 VDUSEL is address is the hardware SHA emulates the standard model 2 SRAM is addressed latch and holds the flag The signal 14 and A15 are decoded to form notOS L5 S 4 enable signals high 2 OR A13 is low low AND A14 low AND The address decoded is ANDed with the sideways RAM enable bit active is logic 1 and the current address is between amp 8000 and amp AFFF tPGRAM will be low by decoding notROMSEL and when notROMSEL is law AND A2 is low addressable 1 bit latches ed at amp FE34 and latches DOW mode switch Logic O0 are decoded to form notPG If sideways RAM is enabled the value of D7 EPROMs ROMs to be access time less notCE IG which is low when A14 AND the current SRAM 1 then notPG is A15 high are decoded SRAM if sideways RAM enable A2 NotPGLD is low write only VDUSEL which is normal mode B microcomputer VD at amp FE30 SRAM is an exte value of D7 This bit is is labelled in the PAL spec 76 the sideways RAM sel U operation nsion to the ROM selec ct ct 0201
20. te or ntrol register bit 7 is f Bits O to 2 control the transmit bit rate ive bit rate ogue to digital convertor circuit is based on a uPD7002 ue inputs whi The voltage ref IC84 E ch gives a typical tible with the RS232 signals common in computer RS423 for input and output is by bit 6 of or cassette motor while bits 3 to 5 which can accept upto erence is set by three full scale 5 14 Audio circuitry the CP RQ U is interrupted C20 pin 21 IC38 is a four channel sound generator which can be programmed to vary the frequency and volume of thr independent tone generators and the amplitude of a single noise generator The sound signal is DC restored by mixing in a signal derived from the sound envelope An inverting peak detector IC47 D4 C15 etc derives the inverted sound envelope which is then summed with the sound signal in the ratio of 2 1 Part of IC47 forms a virtual earth summing amplifier which mixes the sound its envelope th xternal audio input and an optional speech signal into one audio channel The audio is then filtered through a second order low pass filter approximately 7kHz bandwidth and applied to the volume control optional before final amplification by IC77 an LM386 IC77 drives the internal keyboard mounted 8 ohm speaker via PL15 Plug 520 allows fitting of
21. the 5V being between 4 75V and 5 25V tch off the power supply and n the connectors marked OV the multimeter to a 10A DC scale and connect it between one of the all three red wires together to measure the current any tracks excessively The board g on its upgrade state power supply for each of the n tor is zero or very low then PCB track If all results are uit and the power supply has cut ely This can be checked by meas Zero voltage means short circui Repla VCC bl As a a few ce all the power supply leads in ack to OV and the purple lead final ICs around the board and check t their correct positions check measure the voltage across the power supply pins twork has gone open circuit uring the 45 voltage across the 5V means open circuit 7 red t hat it is in spec 39 9 3 Oscillator and divider circuitry Using the oscilloscope check that 8MHz 4MHz available from pins 7 6 5 and IC53 Results i these signals are the crystal controlled oscillat available at pin 8 IC53 If it is then replace 2MHz and 1MHz are respectively of the video processor not present then check that 16MHz is C53 If not then check or circuit formed by half of IC26 and Check that the CPU has two non overlapping 2MH phil and
22. ERPROC 1 o p pin 10 drives the notRTS control line with an RS423 compatible 5 slew limits the signal to reduce electromagnetic radiation 87 89 Final assembly 1YOd 43SN 19 553 0 Wd YOLVINGOW 90Yd 43 IHN 3HN 9894 55754 311355 0 3INQOTVNV 13NO93 91 Circuit block diagram E sv sv sy RI PLA PR 1 1 1 Max 52 07 O I SO D o g a 5 7 RATA r3 5 6 2a 3 2550 x te 5 E OE Hoc JOE 7 18098 1 O EMO gt x T EAT i z O 0 E 0 MO PEE i E TE 6 A Dic w GE o 7439 515 9 9 SEE RIGHT HANC FOR SUPPLY DETAL PRINTER 1MHz2 EXTENSION BU AAA AAA e rR ARS Et 7 j PCB circuit diagram f SUPPLY DETAIL FOR ICO ov sv pid 1615123 Lv ca gt 100 PI
23. South for The modulator may ONET without collision always made for 6512 CPU Collisions are detected by software protocols 8 Test equipment A PORT version I O ports on UHF tester video MOS BASIC ROM Full RAM working RGB RS423 cassette A to D and ECONET To use t the microcomputer must at least have the CPU running and tester is available for the microcomputer This is an uprated of the old FIT tester It will check the DRAMs and all the B the microcomputer disc printer user 1MHz bus TU working and sane of the Operatin g instructions are supplied with the equipment 17 is the 35 9 Fault finding This section goes step by step through fault finding in each section of hardware It should be studied in conjunction with the circuit diagram and block diagram in the Appendix Seu any part of the machine is suspected of being faulty the following points should always be checked first no loose connectors and broken cables 2 no broken or shorting tracks 3 ICs plugged into their sockets correctly 4 power supply working and reaching the components concerned 5 all digital signals are at clean TTL logic levels greater than 2 4V for 1 less than 5V for 0 On timed signals this must be true for the period 150ns before phi2 on read
24. correct or k the node 7 address group when high nal shadow to modify the natural display address from the CRTC uses 20Kbytes of RAM from then the assumes a scroll ill be amp 3000 to amp 7FFF as seen by the RAM multiplexer CRTC address TO an The offset is 12K As the address logic does not generate an address above amp 8000 there is no use for address scrolls above amp 8000 it appears to address amp 0000 upwards the RAM address becomes outputs an address outside the true address to remain in is used for all 12K the This principle 7 82 line A15 1 83000 upwards allowed RAM address the allowed range of amp 3000 to amp 7FFF graphic screen modes 3 Thus when the CRTC By adding So although the CRTC the adder causes ie all but mode K There are four different graphic screen sizes 8 10 16 20Kbytes adder therefor needs to add an offset of 24 22 16 12 respectively The operating system gives a 2 bit code labelled 0 1 which is decoded to give the adder offset for the current screen mode Cl CO Offset adder input B4 B3 B2 Bl 0 0 16K 0 1 1 1 0 1 8K 1 0 0 20K Oo aly oU 1 1 10K 1 9 gt E IC77 LM386 Audio power amplifier This IC is a low cost amplifier with a fixed voltage gain of about 26db C24 and R58 are needed
25. the VI A high then the buffer IC5 pins 2 3 4 5 6 7 8 9 t register nter connector PL9 should now be high If they are not all 1 then check them at 0 If these are all is faulty Otherwise check for short circuit tracks on data lines on both the printer side and the CPU side of the VIA A better test is to use outputs and then change values amp AA and amp 55 the wrong Connect printer check this p a kn ul own good prin strobe output from going pulse when the comp se at pin 1 This way short circuits are more lue in the tes 4 10101010 on These correspond to the the likely to give the binary configuration it to 01010101 CS ter to the microcomputer Check that the the VIA pin 39 0 gives 4us negative ter is instructed to print If it does then 1C13 If the printer interface is working correctly chen buffer is fu 142 there shoul If there i ld be S only a single pulse then check regular strobe pulses until the printer the printer ACK in per che fron fau n the pri ty a broken track or the VI put pin form the data co two signal the computer is ni 40 IC10 ntrol T n hese two lines together andshake and strobe and ACK on being instructed
26. 3 2 Power supply Input voltage 240V RMS 10 input frequency 47 53Hz 5V output voltage 5V DC 0 1V 5V output current 0 1 minimums 3 5A maximum 12V output voltage 12V DC 10 12V output current 1 25A maximum 5V output voltage 5V DC 10 5V output current 0 1 maximum Total output power 35W 3 3 Display outputs Modulated output marked UHF out Standard 625 line PAL A UHF colour television signal Channel E36 Vision carrier Nominal 591 25MHz RF output 1 0 to 2 5mV 6db bandwidth gt 8MHz RF output impedance 75 ohms Connector phono Composite video marked video out Output level Nominal 1V peak to peak Output impedance Nominal 75 ohms Option Chrominance information link selectable allows composite PAL monitors to be used Connector BNC Colour monitor marked RGB RGB signals TTL type levels CSYNC signal TTL type level ve ve going link selectable Connector 6 pin DIN 3 4 RS423 Line length 1200m maximum Input impedance gt 4k ohms Baud rate 19200 maximum guaranteed up to 9600 3 5 Cassett interfac Output impedance Input impedan Output level Motor control Baud rate Connector ce Dynamic input range Less than ohms Greater than 100k ohms Nominal 200mV peak to peak 70mV RMS Nominal 50mV to 5
27. 880 Th th VD Th is an by ge ra in e PAL monitors the state of VDUSI When VDUS de is active e address of each CPU U driver code space t e flag remains set un read While the flag hen a til is EL is high opcode fetch the an opcode outside set d amp 7FFF is redirected manipulating the nerated by the PAL nge amp 3000 to amp 7FFF paged ROM 15 15 same as the CPU A15 address tests each CPU address and forces CPUSEL h So in s screen RAM for VDU operations and normal VDU driver code is identified by its mem address C000 amp DFFF is treated as a V paged RAM between 684000 and amp AFFF is treated as VDU driver the shadow RAM RAM address line the signal CPUS signal When to hadow mode th temporary 1 bit flag is set the VDU driver all CPU access to memory between 3000 The redirection EL Norn e CPU will RAM for all EL to determine if a shadow display shadow active If the opcode address is in i PAL checks the n the PAL code space is achieved The RAM A15 address DU driver Also nally CPUSEL is the flag is set igh if the address is in access the shadow ther operatio 11 code between code in address is the PAL the the p ns the not but From the above it is apparent that
28. Acorn OS 64K 1770 DFS BASIC gt Results the CPU is running and is accessing the OS Use PET tester if available see information manual supplied to dealers If the banner message is fragmented then check the CRTC address lines for shorts If the message gives the prompt Language where BASIC is fitted in the example above check 513 and also check the Pg latch Language cannot occur when it is a badly fitted IC since the OS and the BASIC are in the same ROM A badly fitted OS ROM would prevent the machine powering up e The machine does a start up beep and the caps lock LED comes on but there is no display or no display on the UHF monitor Results the video circuitry is faulty see 9 7 f There is no fault on power up Results most I O faults will not stop the computer and display working Use a PORT tester to find out which I O circuit is faulty 38 9 2 Power suppl With th the power supply turned off unpl Connect pair insul thr red 5V leads and the single t a hat wer ting tape together on the board to stop measure the voltage across the resis voltage must be in the range 4 9V to 5 1 ING the resistor will peak ul Res of uni pair volta centr he leads is damaged If the 5V lines are good 5 ohm 5W resi
29. CO CO CO OO 0 NIS 01 4S COO FS O 0680 002 CAPACITOR 33 47nF DECUP 64 67 A 0640 473 CAPACITOR 47nF CERAMIC 1 C24 0640 104 CAPACITOR 100nF CERAMIC 5 5 7 9 23 0651 224 CAPACITOR 220nF CERAMIC 2 C38 41 0613 100 CAPACITOR luF TANT 1 C33 0635 047 CAPACITOR 4u7F 16V ELEC 1 C30 RADIAL 0635 100 CAPACITOR 10uF 16V ELEC 3 C27551 52 RADIAL 0621 047 CAPACITOR 4u7F 10V ELEC C15 AXIAL 0610 010 CAPACITOR 10uF 10V TANT 1 C57 0621 470 CAPACITOR 47uF 10V ELEC 6 C25 46 50 54 56 60 AXIAL 0610 047 CAPACITOR 47uF 10V TANT 1 C37 0620 100 CAPACITOR 10uF 6V3 ELEC 1 C14 AXIAL 0699 003 CAPACITOR TRIM 5 65pF 1 VC1 0860 005 CHOKE 33uH I 11 0820 160 CRYSTAL 16MHZ I X1 0820 177 CRYSTAL 17 734475MHZ 1 X2 0810 001 RELAY 5V 1 RL1 0780 239 TRANSISTOR 239 7 9 0780 309 TRANSISTOR BC309 2 06 8 0783 906 TRANSISTOR 2N3906 1 010 0794 148 DIODE 1N4148 14 D1 D2 4 8 18 0794 001 DIODE 4001 3 D5 7 0740 016 IC 7416 Bi IC8 0740 006 IC 7406 1 IC8 OPTION 0740 038 7438 1 0741 000 74500 1 IC52 0742 000 741500 5 1 9 19 27 87 9
30. R86 12 128 130 C53 ONLY 3 11 16 36 38 R63 68 73 84 104 R105 107 131 133 148 R89 R82 146 147 1 R50 52 R74 80 87 1 R120 124 1 R69 138 9 10 14 1 56 71 90 1 93 108 139 R4 23 43 48 R59 60 100 R103 B1235127 R2 22 26 27 29 R34 42 44 81 R111 126 144 151 R116 R115 R72 disc interface 63 37 0502 393 38 0502 563 39 0502 623 40 0502 823 41 0502 104 42 0502 154 43 0502 224 44 0502 274 45 0502 824 46 0505 103 47 0505 563 48 0505 104 49 50 0502 105 51 0502 155 52 53 0520 180 54 0581 103 55 0581 104 89 58 0590 223 59 0590 682 60 61 62 63 64 65 66 0631 010 67 0631 033 68 0631 039 69 0631 047 70 0631 068 71 0631 100 72 73 0631 150 74 0631 270 75 0630 039 76 0630 047 77 0630 082 78 79 80 0630 100 81 0630 150 82 0630 220 83 0630 330 84 0630 470 85 0629 010 86 0650 333 RESISTOR RESISTOR 56K 0 25W 5 RESISTOR 62K 0 25W 5 RESISTOR 82K 0 25W 5 RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR RESISTOR 39K 0 25W 5 2 10 15 22 21 82 10 56 10 25W 5 er 6 TE Ol 0 25W 2 0 25W 2 K 0 25W CR DN c C Cc LAO 0 25W 5 1M5 0 25W 5 18R 1WO
31. otCTS The terface si tes RPROC A tatus OAKES 85 83 741586 1 3 Ihree handshake signal Se can be tested by Two clock inpu to be set independently Quad two input is part of the TV colour EXORs is used r rence n colour 2 3 pin 8 is used the RGB connector SK generated 527 South 4 o p pin 11 this g four o p 6 see above EO 3 With o p pin 3 to select the polarity of the CSYNC signal on set North RQ is an open drain outpu the der cassette ls are availabl R59 is fit to allow a program to detect the network etwork data packet collisions ICG93 NotIRQ is used see IC81 is ted when interface circuit which can both The 6850 is used or parallel to serial interface le the RS423 notRTS and or notDCD EXOR link 527 is driven by t the normal setting PAL ur subcarrier gives alternat encoder circuit select the phase of the colour ded to synthesise the colo the controlling program to determine ts allow the transmit and receive bit The two clocks are generated in the One of subcarrier or a particular positve syncs are negative syncs line divider IC69 and shifts one of the master colour subcarri degrees be d
32. Port is connected directly to the B port of the same 6522 The 1MHz extension bus i S a fully buffered interface to the CPU operati address ng with lus transfer cycles The bus appears as a 512 byte block in the proce The TU BE interface provi ssor I O space at pages amp FC and amp FD des buffered address and data lines for connection to a second processor The TUBE itself is a fast parallel bidirec tional FIFO and is resident in the 2nd processor unit The keyboard is read through half the port of a 6522 versatile interfa ce adapter IC20 Sound is produced by the 76489 38 four channel sound generator chip Speech may be generated using an optional 5220 speech processor IC29 OZ CPU 16MHz 6100 word PHROM timing 2637 crystal controlled oscillator 1 and half of 26 generates clock pulses which are divided by circuitry within the video processor ULA IC53 Pins 4 5 6 2MHz 4MHz used to chip EC used di and 7 of the video processor provide 1 2 and 8MHz outputs respectively 8MHz 4MHz and 2MHz are generate RAS and CAS for the DRAMs and 6MHz for the TELETEXT 59 2MHz is used to generate the main system clock 2E 1MHz is rectly by the TELETEXT chip and also in conjunction with 2MHz to gen system
33. SIL sockets iii Except on early boards the resistors listed above will already be in position on the PCB Check each one and solder in any which are missing iv Insert the filing system ROM into a vacant sideways ROM socket IC 35 44 57 62 68 v Make link 57 East with a shunt probably already in this position or tinned copper wire if molex pins not fitted vi Make link S8 with a shunt probably already in this position or tinned copper wire if molex pins not fitted vii Test using a PORT tester Note the 1770 disc upgrade is usually carried out without soldering 21 6 2 8271 disc option i The following parts are required 7415123 IC2 7418393 IC3 4013B ICA 4521B IC7 7438 must not be 741538 8 7416 or 7406 IC15 8271 R1 150R R2 10k R3 k R5 150R R6 150R R7 150R R8 150R R9 3k3 R10 3k3 R14 3k3 XOA 1n plate ceramic 2 ADI 4148 16K ROM DNFS ii Insert the ICs listed above into the sockets which should be provided on the main circuit board If any sockets are missing then solder in the correct DIL socket for that IC Note 1015 uses two 14 pin SIL sockets iii Except on early boards the resistors capacitor arid diode listed above will already be in position on the PCB Check each one and solder in any which are missing
34. a remote volume control when no volume control is fitted a shunt is required on S20 The a operational before mixing i an optional south udio outpu to enable the audio t of the optional speec amplifier second order fili n with TMS5220 wi th TMS6100 cer h system is filtered by a cut off frequency of S the other audio signal or equival ent n 7kHz Speech is generated by vocabulary PHROM 25 5 15 Keyboard keyboard circuit is given in figure 9 6 of the Appendix keyboard connects to A 1MHz clock signal 1E counter decoder driver circuit the main PCB via PL13 matrix input NAND strobed and IC20 on the nter th each row being driven key readi is fed to 7415163 the outputs of which are decoded by a 7445 These outputs drive the rows of the keyboard turn If any key is depressed will ICA on keyboard this will main computer board ng software interrupt the CPU on keyboard binary IC3 on keyboard an 8 produce an output when that row is through terrupt The in pressed the CPU loads directly into the 7415163 address of a key matrix row the 74L8251 data selector 1 of a single key on the selected row turn Also with the Way column address the processor can interrogate each
35. and IC37 into their sockets on vi Turn the computer on and type REPEAT SOUND 1 GET 0 0 UNTILO and press the RETURN key A vii Adjust VR1 until the speech is at the correct pitch the loudspeaker thus the empty tween any of the edge the PCB ny key now pressed should cause the system to utter a word or sound This can be IC29 Adjust VR1 the case lid fit measured by connecting a frequency meter to pin 3 until the meter reads 160kHz 100H viii Remove the perforated section from the left of the ROM socket cover and reassemble the machine ix Test using a PORT tester 32 7 Selection links This section describes the function of each of the li the type of link and its position as standard 1 PCB track made West West for 5 1 4 disc drive East for S2 PCB track made North North for 5 1 4 disc drive South S3 PCB track made South South for 5 1 4 disc drive North S4 PCB track made South South for 5 1 4 disc drive North S5 wire link not fitted allows disc filing system to This feature is not supported by current disc software S6 PCB track made South South for 5 1 4 disc drive North 57 plug made East East for 1770 floppy disc controller West 8271 S8 plug fitted fitted for 1770 floppy disc controller 8271 S9 plug made West West for 8K 16K ROM EPROM in IC35 ROM EPROM i n
36. be the disc an index used to c A drive lock a binary al will be high IC3 is turned on by in twee Speed is pulse oc n to be almost right th e speed can be assum is take so a a ed within working n index pul ter one additional dex pulses and so lses is low If hen the too s curs limits pin 13 is c f IC3 pin low if 1C4 pin 11 is 11 low at the next 1 locked aU e ST go law indica that the drive is ready D ting OR that gen pin mig Communication between the 8271 disc controll urs at two levels OCC Commands to the MOTOR signal whenever eration sequence is ret 11 avoids a false RDY ht go high then low between two index pul and the state of IC4 pin low when an ndex pulse then IC3 pin 2 will pulse occurs iode an The OI ICA pin 11 goes high it will set turned to if the drive is ver IC3 pin y slow the disc controll LSES R func 137 the beginning Resetting when d resistor R2 tion means nd the RDY by ICA ICA pin 11 a ler and the microprocessor ler are made by normal program controlled accesses to the I O space between addre
37. by The machines the screen logic is set amp FE34 this a register at address and CPUSEL shadow RAM amp 000 to g between amp 0000 amp 9FFF in shadow mode will always cuting from sideways RAM between amp A000 amp AFFF will access when the operand address is between is not available to any other The 64K installed RAM is provided by eight 64K by 1 dynamic memory TCS devices 55 56 6D timing diagram 2E RAS CAS CPU 61 64 6 Figure 6 RAM timing diagram 18 5 66 67 VDU Figure 6 shows the RAM C PU 128 256 RAM control circuit is designed to work with either refresh cycle DRAMs refresh being provided by the 6845 CRTC 78 in conjunction with two ex OR gates of IC63 and an AND gate of IC34 The RAM is accessed at 4MHz the CPU and VDU each having 2MHz access The address multiplexers for the VDU cycle are ICs 72 73 74 75 Various combinations of the inputs of these ICs are used depending on the screen mode in use In particular TELETEXT mode 7 with its own character generator IC59 is markedly different from the other seven bit mapped modes 0 6 The address multiplexers for the CPU cycle are ICs 50 and 51 RAM is working being addressed and strobed the whole time both during CPU and VDU phas
38. from an ECONET line While the clock is present triggered o p pin 4 low then o p pin 4 will oscillate or stay set The s can be checked directly by the ECON notDCD signal ET controller notRTS signal At the end the monostable The real from permanently driving the component which generate control signals to als into the resistor matrix by 1 o p pin 3 buffers the colour reference oscillator to ensure TTL It drives the colour burst timing IC58 o p pin 13 two gates which drive the colour subcarrier t subcarrier components colour burst monostable the colour burst generator Input pin transmission period for an n is set to about 4 5s and which e triggered the of a transmission output pin 4 purpose of this ECONET line as Whil by the received clock the monostable remains If the clock is not present or is very slow ET filing system tes the monostable ting the 68B54 tate of 85 IC89 LM324 Quad operational amplifier 1 o p pins 1 8 14 give two stages of filtering and one limiting amplifier stage for the received cassette audio signal When the audio is present a 1 2 volt approx square wave will be presented to the SERPROC 2 o p pin 7 buffers the audio output to the cass
39. in figure 4 respectively 45 from B can either hold an 8K IC s are paged into the memory map from amp 8000 amp 9FFF a 32K device provides two 16K banks from amp 8000 amp BFFF required by 32K devi link t of the memory selection is the programmable array logic It selects which screen RAM is it controls the sideways ROM select latch normal or it selects in use 45 16 32 BYTE The extra ces is available is altered The ROM ROM select n umbers and their IC No ROM Nos Link No Notes 35 2 3 S9 Molex link made W as standard for 8K 16K use IC44 4 5 511 IC57 6 7 512 62 8 9 515 y q 68 10 11 518 71 0 1 519 cuttable link made E as standard for 32K 14 15 16K operating system and I O and 16K BASIC Figure 4 ROM socket IC numbers ROM numbers and device selection link numbers As can be seen from figure 4 ROM numbers range from 0 to 15 ROMs prioritised the highest ROM number language and filing system will be selected after a hard reset 15 has the highest priority 0 the lowest So if two or more sideways ROMs are language ROMs then the computer will start up in the language in the highest number ROM slot Similarly for filing system ROMS IC35 44 57 62 and 68 we shall call socket is functionally identical ROMs IC71 we
40. individual th the CPU drives line CA2 tells the computer to In order to discover which key was pin 39 of the on keyboard allowing it to interrogate each row in C2 on keyboard In this until Once key in turn it discovers which one was depressed and caused read the keyboard assumes its free running mode 26 interrupt 6 Upgrading the The following section gives instructions for adding extra hardware to upgrade the PCB for disc ECONET and speech Dealers and service centres performing these upgrades must also conform to upgrade procedures and requirements as notified by their supplier and should refer to any available information updates for latest details In the following section items marked may already be fitted to the board All ICs are inserted with their pin 1 facing the back of the computer 6 1 1770 disc option FM or MFM 5 1 4 inch floppy disc interface i The following parts are required IC7 7438 must not be 741538 8 7416 or 7406 IC16 1770 C17 1415174 150R R5 150R R6 150R R7 150R R8 150R R14 3k3 The appropriate filing system ROM ii Insert the ICs listed above into the sockets which should be provided on the main circuit board If any sockets are missing then solder in the correct DIL socket for that IC Note 6 uses two 14 pin
41. is nabled when either FRED or JIM is accessed two pages are decoded by notJIM appearing on pins 4 notFRED or notJIM goes low and takes low an input of t cycle NotFRED IC28 pin 4 IC22 and and notJIM IC28 IC28 with signals and 5 respect the 1MHz bus enable goes low NAND gate IC41 thus causing 1MHz CPU tively of pin 5 pin 10 and 1MHz bus enabl by latching them glitches occur on the 1MHz bus interface system clock 1 5 10 TUBE interface The TUBE interface signals present are the eight data lines R notW 2E notRS and notI and the address lines buffer 1C14 is enabled when a TUBE address amp F connect IC34 pin IC21 this enabl connector PL12 e signal pages amp FC and amp FD These notFRED and IC28 When either IC34 pinll along with R notW IC24 11 are synchronised to the 1MHz in 1632 This ensures that no ts to a second processor five address lines 0 to 4 V ia PL12 The RO The data lines are buff R notW and 2E X ered by 14 IC13 The data is decoded by notTUBE are buffered by I EE0 amp FEFF being fed also to the TUBE R11 is fitted so the computer OS can detec
42. notENM to k the display only when the signal causes a 2 raster space In modes 3 6 131 and 134 other modes have only 8 to 7 tCE tCE no acces nominal l y 132 B can be IC is the display data read from RAM and the pixel code to the 3 bit RGB translation represented in RAM by 1 20r 4 de of Screen bits It us IC which has long data setup ns before the 5 5050 IC59 The RAM appears as a 32Kbyte A further 20Kbytes are used for a SHADOW ED in under program control L pack may be supplied instead and 7 to be s time video display sync pulses HS and VS to form The HS pulse is nominally 4us long VS is us 2 rorm the S to form graphic the CRTC RA The o p 9 to form no 1 ct O not nterval he DW S EN does EN is D Screen lines raster lines per therefore RA3 only signal R76 is triggered at the end of to be ng the the HS The SAA5050 contains general control logic needed IC receives charac mode 7 The 1MHz maintain raster counter TV display 59 SAA5050 The Tele VS is used to reset the display Charac from the CRTC via text display generator the character look up ROM the raster co 1 in unter and ormation for to generate the pix ter data codes from synchronisation
43. p pin 1 mixes th long gates the buffered CPU R notW wit 96 64 1 ing 12Kbytes is a DRAM 51 memory 28K or 256Kbit paged ROM his socket appears in sideways co varies with latches the RAM data at the end of alternate VDU phases to hold the da The latch is clocked 500 55 56 60 61 64 65 66 67 4164 64Kx1 bit 120ns access DRAMs ROM slots 6 Link 512 West allows 8 or 16Kbyte EPROMs ROMs Quad 2 input NOR DRAM W signal 3 pin 10 gates notD signal DIS mode borders modes modes 3 count from 0 character row goes high thes EN high not affect mode 7 high for periods ou This signal tside and 134 The lines c 4 o p pin nables th nd C32 det rmin ulse 0 a in the range 4 to 6us HS pulse period 8 the pulse dura D The monostable EN and RA3 134 lour burst monostable uring the colour burst i tion which is set at manufacture 15 is used to discharge C32 quickly duri which is buffered and inverted by from the CRTC les the VIDPROC generated RGB signal is used to blan the display window and so blanks the graphic RA3 is only activ 6 131 between each text row EO 9 So the RA for modes 3 6 131 and is part of the co colour subcarrier d e for the text ount from O0 EPROM with a th
44. particularly w IC54 IC at the start of each TV ith IC24 field IC62 various A 32Kbyte device in this socket appears in sideways East This device can be any ROM or less than 250ns link S15 fitted IC63 74LS86 1 odd or even ter rounding is permanently on gives the SAA5050 information on the current to allow character rounding at a rate of field and so the internal The notRAO line 64K 128K or 256Kbit paged ROM Link S15 West allows 8 or 16Kbyte EPROM with a EX OR Quad 2 input o p pin 3 is part of the 6MHz clock circuit 2 these gates 3 IC68 various 11 link S18 be fitted time less than IC69 741 574 pin 6 1 flip f1 pulse form a circuit through the refresh address o p pin 11 is a spare gate A 32Kbyte device in East This device be any or 250ns this flip flop holds the R S latch When address amp FE18 is ECONET NMIs decoded address to give a glitch fr is used as an the latch is set gates not2E with the To enable the NM RO EP no Along with M slots 8 and 9 ROMs ROMs to be tCE access time o p pins 6 and 8 are used to modify the CRTC address during the unused read cycle of mode 7 VDU cycles IC34 o p pin 8 which sequenc inpu reduces th when in mode 7 ts tied to 5V 64K 12
45. pin 8 is used to drive the RAM notCAS clock NotCAS is timed from the system 4M clock notCAS is held high if the CPU cycle is a VIDPROC write by a logic low from IC23 pin 8 3 o p pin 11 is used to modify the duty cycle of the 16MHz clock to suit the needs of the Ferranti ULA IC53 Note the passives R36 R37 R38 C14 D5 D6 D7 may also be needed for the Ferranti IC 79 IC53 ULA 1MHz inverted i System clocks modes 0 to 6 and external link S14 Video processor This component contains a 4 bit divider which IC It also se from generates th 8 4 in ternal 2 and for lects the RGB signals mode 7 EC 59 for parallel to serial translation of the logical each resolution of data 54 7415273 This needed and hold times display pixel mode The Octal D type is made South conversion of A pixel may b The mai n function of t The RG ne process ta for the teletext giving equal setup and hold times of 500ns These eight ICs are the system block from 0 as ot these ICs 57 various A 32Kbyte device in t East This device Can be any ROM or link 512 fitted less than 250ns IC58 741502 1 notCSYNC TV rasters 2 o p pin 4 000 to amp Screen memory The remain a sideways RAM Note o
46. program given in the address decoding for the SI from the 6850 IC85 26827 IC85 is sending the transmit clock TXCK and These signals are on If these signals are inactive is faulty or cannot be addressed the cassette section above to check that ERPROC and 6850 is working Now press CTRL BREAK on each microcomputer Swap the configurations so that the good computer is the transmitter and the suspect computer is the receiver If U characters are output on to the monitor by the suspect computer then its RS423 is working as a receiver no output appears then test the suspect RS423 circuit as follows Check the Din line either side of the receiver pins 4 and 7 of IC94 Pin 4 should be oscillating at RS423 logic vels 5V 5V Pin 7 should be oscillating in phase with pin 4 but at normal TTL logic levels OV 5V If pin 4 is active but pin 7 is not then replace th receiver IC94 Check that the SERPROC IC85 is sending the receive clock RXCK and receive data RXD to the 6850 IC82 These signals are on pins 26 and 22 respectively of IC85 If these signals are inactive then it is likely that the SERPROC is faulty or cannot be addressed Use the test program given in the cassette section above to check that the address decodin The microcomputer is to connect alternative BAS C pr
47. pulse It is triggered at power on or by the keyboard BREAK key logic 1 active output pulse is generated and part of IC27 inverts RS to form notRS the CPU reset 1C44 various 64K 128K or 256Kbit paged ROM A 32Kbyte device in this socket appears in sideways ROM slots 4 and 5 link 511 East Link S11 West allows 8 or 16Kbyte EPROMs ROMs to be less than 250ns taken low active output fitted This device can be any ROM or EPROM with a notCE access time 45 7415163 Synchronous divide by 16 counter Used as a 4 bit latch which holds the paged ROM LD The IC is clocked by not2E When the latch is addressed at amp FE30 its LD enable is and the write data on the CPU data lines DO to D3 is latched The load event is effectively when phi2 falls The QA latched DO is used a pseudo address line for 32Kbyte ROMs EPROMs and so splits these devices into two 16Kbyte pages 46 7415138 3 to 8 line decoder This decoder is enabled by the notPG signal from the PAL 1C36 When nabled the decoder selects one of the RCM sockets according to the code held in LC45 the decoder uses th Each enable output is active for 2 paged ROM IDs as latched values of Dl to D3 513 is used to select the page number for the language half of normally BASIC Jes S13 North selects page 0 1 South
48. recovered A preamble tone is timed to fitted R66 and C30 are used to time of a cassette recorder is managed by IC controls the relay The is buffered by O7 which switches the relay coil 50 ohm IC86 741 586 2 3 4 IC87 741500 levels 2 components 3 o p pin 8 is one resistor matrix with the colour burst Quad two input EXO o p pin 6 is used as a R76 and C32 with notHS of R 1 pin 3 generates a colour subcarrier referenc according to the current displ o p pin 6 is one of three gate the subcarrier component sign enabling or disabling NAND gates in o p pin 8 see o p pin 6 o p pin 11 see o p pin 6 our ay col gates 90 Quad two input NAND n inverter see 10 receives an enable pulse from the 4 o p pin 11 is the second gate of 88 7416123 Dual monostable ECONET only 1 o p pin 5 determines the maximum allowed ECONET data packet The monostable s duratio is triggered by the inverted ECON previously directly enabled th line driver monostabl nables the line driver 91 the monostable is cleared Normally appears logically to follow the RTS signal circuit is to stop a micro result of say user program crash 2 o p pins 4 13 this monostable is triggered
49. running at 2MHz 64K of read write Random Access Memory RAM allowing a shadow screen mode and 12K paged RAM in any mode 32K Read Only Memory ROM integrated circuit containing the Machine Operating System a fast BASIC interpreter Th interpreter includes a 6502 6512 assembler which enables BASIC statements to be freely mixed with 6502 6512 assembly language Code generated using the BASIC assembler can be run on a machine with a 6512 microprocessor or a machine with a 6502 microprocessor Up to five 32K sideways ROMs may be plugged into the machine at any time having the effect of ten 16K ROM slots eleven including BASIC These ten 16K ROM slots are paged and may include Pascal word processing computer aided design software disc and ECONET and WINCHESTER filing systems or TELETEXT acquisition software The full colour Teletext display of 40 characters by 25 lines known as mode 7 has character rounding with double height flashing coloured background and text plus pixel graphics all to the Teletext standard The non Teletext display nodes modes 0 to 6 provide user definable characters in addition to the standard upper and lower case alpha numeric font In these modes graphics may be mixed freely with text The following screen modes are available
50. selects page 14 15 78 47 LM324 Quad operational amplifier The four parts of this and sound signals befor 1 o p pin 1 is the final they reach filter stage IC are used to filter and amplify the speech the volume control nominal bandwidth of 7kHz 2 o p pin 7 is the speech audio fil bandwidth 3 o p pin 8 is the summing stage envelope and user audio inputs in 4 o p pin 14 extracts the sound the sound signal and charges C slowly so C15 holds envelope is added to that is symmetric about 48 741 510 1 Triple 3 input NAND o p pins 6 a 5 mixes to one c channel tage approximately 7kHz sound hannel Speech speech 15 through D4 the sound envelope voltage the sound audio nvelop The op amp inverts R34 discharges C15 inverted When the the resulting signal is AC nd 8 are part of the hardware scroll wrap around logic With parts of IC19 they decode the screen size code CO and Cl from IC30 to drive the offset adder IC76 2 o p pin 12 enables the RAM data bus buffer 49 and the RAM write signal The logic 1 request input from 40 pin 8 is gated with not2M to form notENM the 0 active RAM enable signal Not2M is used to nsure th nable is only active during the CPU phase ie while phi2 is high This avoids bus conflicts dur
51. shall call the system ROM The system ROM conta always in the memory ins t map f user ROMs and can contain language or service he operating system rom amp C000 amp FFFF and must always be fitted in Each user ROM The operating system is 71 As standard the computer ones with 32K ROM for 1C71 t contains the operating system and the BASIC language For this reason link S19 is hard wired East in the 32K position The BASIC part of the system ROM occupies one of four sideways ROM numbers As standard any call made to ROM 14 or 15 selects BASIC and any call to ROM 0 or 1 is ignored Hence BASIC occupies the highest priority ROM slot and the computer will start up in BASIC If molex link 513 is moved from South to North then any call made to ROM 0 or 1 will select BASIC and any call to ROM 14 or 15 will be ignored This allows the user to select an alternative language at power on the language entered at start up will be the one with the highest socket number when more than one language ROM is fitted 15 Address decoding is carried out by the PAL IC36 and this then selects either the operating system if the address is in the range amp CO00 amp FFFF or the current sideways ROM if the address is in the range amp 8000 amp BFFF Part of ICA0
52. to print ht to sendin n th S oug th If the strobe pulse is not being sent then the fau A chip itself alternate until g a strobe pulse but no ACK is coming back rate A the printer buffer is full tor PL9 are lt is either connections to the edge connec 51 9 12 User port Use a PORT tester to check that the user port is faulty Test the VIA IC10 First configure al data direction register B DDRB by writing values to it and testing the outputs 1 the data lines as outputs by writing amp FF to the amp FE62 amp FF Then write amp 00 to the output register amp FE60 amp 00 All the data lines 6 8 10 12 14 to the user connector PL10 should now be low pins 16 18 and 20 If they are not all zero then check for open circuit tracks on data lines on both the printer side and the CPU side of the VIA Now write amp FF to the output register amp FE60 amp FF All the data lines they are not all 1 better test is utputs and then he wrong value 52 to the user connector PL10 should now be high If then check for short circuit tracks on data lines on both the printer side and the CPU side of the VIA to use the binary configuration 10101010 on the change it to 01010101 These correspond to the alues amp AA and amp 55 This way short
53. 0 0741 002 74502 1 1C33 Components marked are fitted only with 8271 disc interface 65 129 0742 002 741502 1 IC58 130 0741 004 74504 1 IC26 131 0742 004 74LS04 1 IC24 132 0742 008 741508 1 IC34 133 0742 010 741510 1 1C48 134 0742 020 741520 1 IC40 135 0742 030 741830 2 1022 41 136 0742 032 741832 1 IC23 137 0741 074 Ic 74574 2 1 31 79 138 0742 074 741874 1 IC69 139 0742 086 741586 3 1 63 83 86 140 0742 109 7415109 1 IC25 141 0742 123 7418123 2 1 1 88 142 0742 132 7415132 1 IC70 43 0742 138 IC 7415138 2 IC21 46 144 0742 139 7415139 2 1 28 39 145 0742 163 IC 7415163 2 IC18 45 146 0742 174 741517 1 17 1770 ONLY 47 0742 244 74152 4 105 243 40 48 0742 245 7415245 3 1C12 14 49 149 0742 253 7415253 4 1 72 75 150 0742 257 7415257 2 50 51 151 0742 259 7415259 1 IC30 152 0742 273 IC 7415273 1 IC54 153 0742 283 7415283 1 IC76 154 0742 374 7415374 2 11 32 155 0742 393 7415393 1 1024 156 0739 120 IC DS88LS120N 1 1094 157 0770 319 IC LM319 2 IC92 93 158 0770 324 IC LM324 2 1C47 89 159 0770 386 LM
54. 00 amp 7FFF normal RAM is on b amp 3000 Otherwise paged and amp FFF into the PAL causes pin in the PAL drivers will 17 pin 12 CPUS When the paged RAM is selected in is programmed by amp drivers Any code exe access normal Any code exe the shadow amp 3000 amp 7FFF sideways memory 5 4 4 RAM ci 6 logic 1 plus a parallel bank of 20K w RAM is able It selects access to th it detects a VDU driver and c the part of the it selects access to norm to shadow mode when is wri RAM can be thought of as 44K RAM from address As in n the memory when ormal mode required from address amp 0000 amp 3000 amp 7FFF which top 12K of normal the address range the In al RAM tten to D7 VDUSEL t and when D7 cause the PAL to swit In EL is low to access normal high RAM and h o go hig is set shadow n cutin RAM the PAL RAM if This rcuitry selected Special attribute ROM or RAM n a ode ig S IC ch in to access adow mode 36 to have amp FE34 is the address o y Screen access through the VDU the shadow memory by making VDUSEL is always set the top 4K the attributes of VDU to switch between shadow RAM and e shadow memory if a shadow mode the operand address is between memory map used
55. 10 Y Wr ds ds BE t POTENTIOMETER 10 205 100 20 RESISTOR PACK SIL 22 8 1 RESISTOR PACK SIL 6K8x9 1 CAPACI TOR 10pF CERAMIC 1 CAPACI CAPACI CAPACI CAPACI CAPACI TOR TOR TOR TOR TOR 33pF CERAMIC 2 39pF CERAMIC 4 CERAMIC 3 68pF CERAMIC 3 CAPACI TOR 1 CERAMIC 3 CERAMIC CAPACI TOR rj CERAMIC CAPACI CAPACI CAPACI CAPACI TOR TOR TOR TOR CERAMIC CERAMIC CERAMIC 2 mj Hj p p 390p p p 1n0F CERAMIC CAPACI TOR 1n5F CERAMIC CAPACI TOR 2n2F CERAMIC CAPACI CAPACI CAPACI TOR TOR TOR 3n3F CERAMIC 4n7F CERAMIC 10nF CERAMIC CAPACI TOR POLY R64 117 R1 R3 5 3 R66 R2 8 41 37 1 L 70 45 39 39 77 136 R R R R R R 06 1 95 96 98 99 10 125 134 R17 24 25 78 79 97 R3 7 VR2 RP2 RP1 C3 9 C12 16 C4 0 44 45 49 4 17 18 C207 532593 C3 C2 C4 C4 6 2 7 8 C58 59 C1 C1 C2 C8 C1 it 1 6 3 9 21 1 34 35 32 42 43 C3 13 28 C2 9 Components marked are fitted only with 8271 disc interface 64 95 96 97 98 99 X quie pni po pep p Ya BE RT
56. 37 phi2 of 42 as shown in clock inputs on pins 3 figure Check that lE is available at pin 6 IC25 This signal should be phase IC53 as shown in figure 8 shifted in relation to 1M at pin 4 1M 1E Figure 8 1 11 1 9 4 CPU Test pin 40 42 reset and check that it is high Press the again on release F BREAK key and make sure that pin 40 goes low for a reset and then high Results if pin 40 is stuck low then check for a short circuit on the main the keyboard BREAK key keyboard connectors or the resistors and capacitors of the 555 reset circuitry If it is stuck high then check the 555 timer circuit 1C43 cable and connectors and the BR EAK key itself Check that notIRQ pin 4 and processor is stalled R notW pin 34 the keyboard ribbon are wobbling If not then test SYNC pin 7 If SYNC is stuck either high or low then the Results if CPU is stalled then check that ROMs are plugged in their Sockets correctly Check for address and data bus short or open QUY 40 9 5 Check that all ROMs are inserted with all the pins correct Sockets Use a PET tes dealers If that all If the CPU ca addr nnot access the OS heck for a tim
57. 386 1 1077 160 0733 691 DS3691N 1 1095 161 0704 865 IC 4164 12 8 55 56 60 61 64 67 162 0706 511 IC 4164 8 12 1 96 OPTIONAL 163 706 502 1 02128 02 164 0206 05 158522 1 10 20 165 0406 850 72 02905 1078 165 707 002 15 7 82 167 0735 159 1C uPD7002 gt 84 168 706 490 15 Q9 ON IC91 6952 38 170 00560522 08201 1 15 171 0753 521 ne 5 IC81 1959 e 178 008 050 2 BOISE COR 174 0201 241 2 IC SAA 5050 x IC59 175 0201 666 IC OS BASIC ROM 2 IC DNFS 3 0 ROM 1 IC354 Conponents marked are fitted only with 8271 disc interface IC35 is also fitted for ECONET 66 QO C97 G6 uds CO NO NO NO PO PO PO PO PO N 00 10 01 4 YN 2201 113 0201 274 0201 647 0201 648 0201 602 0770 555 0201 880 0701 770 0800 114 0800 116 0800 128 0800 006 0800 007 0800 008 0800 050 0800 051 0800 052 0800 054 0800 055 0800 059 0800 009 0800 070 0870 420 0800 200 0800 004 0800 002 0800 001 0800 003 0800 304 X F 1770 DFS ROM IC ADFS ROM IC V10 V2 PROC C SERPROC IC 2C199 IC LM555 IC PAL 16R4 IC 1770 IC SOCKET DIL 14P IC SOCKET DIL 16P
58. 8K or 256Kbit paged ROM Dual D type flip flop ECON NM tim enable signal taken to cycle this socket appears in sideways ROM slots 10 and Link S18 West allows 8 or 16Kbyte EPROM with a notCE EPROMs ROMs to access The read written 6 low which disables 23 6 Is address amp FE20 is read preset signal appears as logic 0 on the D i p and is clocked rising edge of not2E and by the feedback action 6 high D to became set type in the reset state Note as notPR eg when phi2 falls ie notI pin 4 defeat the notCL i p and set the devic This clears the D of Q connected to notCL NTON high will not caus The decoded address through by the type pin locks the the D typ acts directly on the Q o p it can which is used by the The D type is clocked of each TV raster line nade with a PCB track for NTSC 2 o p pin 9 generates the alternate line signal PAL encoding logic to encode the chroma signal by HS and so changes state at the start divides the line frequency by two Link 528 allows the alternating line signal to be disconnected operation Note for NTSC R92 should be removed and an appropriate colour subcarrier crystal fitted X2 should be four times the colour subcarrier frequency destination c
59. EDs light up then check ET tester will work and some of the tests will Please refer to the information manual supplied to dealers for details of the operation of the PET tester when used with the If i HS and VS should be clean TTL voltage levels using an HS pulsing below If they are working then the CPU must have programmed the 6845 and so must have gained access to the OS ROM Check using PET see information manual supplied to dealers If the signals are there but are not pulsing at the correct intervals then fault to CRTC 4 Check that the notRS pin of the CPU computer is switched on BREAK key is pressed damaged components around the 555 pin 40 42 look for a data line is high when It should pulse low on power up and when If it is stuck low then the the look for shorts or 5 Check that there is activity on the SYNC 7 42 and the R notW pin 34 1C42 lines of the CPU If SYNC is stuck then the CPU has stalled and R notW won t be working anyway Check for address and data bus short or open circuit or a complete failure to select the OS ROM see 9 5 6 Check the CPU clocks Phil and phi2 should be as shown in figure 1 If not then check SYNC 1M at If SYNC 1M is high then check see section 5 2 If not then check the 2M circuitry from the vi
60. If not then either 54 is wrong or the disc drive is faulty If index pulses are reaching IC3 but RDY is not going low then the disc may not be reaching speed Measure the index pulse frequency It should be 5Hz 3 Use an oscilloscope to monitor data on the signal end of R7 The data should be negative going lus pulses with intervals of 4 or 8us between them If not then check connections to 8 1770 check all links are in correct position for 1770 operation S3 South PCB LINK S4 South PCB LINK 55 broken S7 East S8 made Check that all ICs and passives are fitted and inserted correctly see 1770 disc upgrade section 60 1 Use a PORT tester to check that the disc interface is the problem Check that a disc filing system Y4 has been fitted eg 1770 DFS or ADFS If the filing system is stored in an EPROM check that pin 27 of the EPROM is connected to 5V For tests that follow we shall assume the use of the 1770 DFS so fit this ROM if it is not already in place 49 Connect known working dual Turn the microcomputer on Check 80 track disc drive that the start up message indicates a filing system ROM is present Acorn OS 64K 1770 DFS BASIC gt Results if the message fails to say 1770 DFS then che
61. M latch to wobbling then If ROM latch contains correct ROM number but sideways ROMs still do 41 9 6 DRAMs Use a PORT tester to carry out a RAM check Check that RAS and CAS pins 4 and 15 respectively of the eight DRAM ICs are wobbling Results if RAS is stalled low then the DRAM ICs may be destroyed Check the circuitry for generating RAS and CAS the video processor IC53 8M 4M and 2M half of and various gates Check that RAS and CAS timing is as shown in figure 6 Check that RAM data lines are wobbling Check that the data bus buffer is being enabled 19 IC49 9 7 Video Look at the displays from the three monitors UHF video and RGB and see which of the following a b c or d best describes them a None of the monitors operate Results there are incorrect signals coming from the video processor Replace the video processor IC53 Run the following program and check that video processor is being selected pin 3 IC53 is wobbling 10 vidproc amp FE20 20 DIM P 100 30 40 start 50 STA vidproc 60 JMP start 70 80 CALL start b The RGB works but the UHF doesn t Test the UHF modulator input voltage using an oscilloscope Set th oscilloscope to 50mV per division 10 microseconds per division auto trigger and attach the probe to the wire running through the white p
62. R114 R120 bias Q9 and also offer a suitable termination to the filter Q9 then drives the signal mixing point to form the complete colour video signal used to drive modulator The impedance of C49 at 4 4336MHz fixes the voltage ratio C48 serves the sam of chroma to luma in the modulator drive signal purpose when link 526 is made in mixing chroma waveform available at SK2 22 the UHF into the video 5 7 CENTRONICS compatible printer interface The computer can drive centronics compatible printer through IC10 6522 VIA Port A of the VI is buffered by IC5 and fed to 9 by a program sequence which Strobe pulses are typically 4us wide ACK from the printer is conne or approximately 5us by E low character byte transfer 5 8 User port is configured as an 8 bit output port which toggles 2 0 pin 39 Printer strobe pulses are generated high low high cted to 1 IC10 pin 40 the printer when it is ready for the next ACK is pulsed Port B of 1C10 offers eight individually programmable input output lines and two programmable control lines 5 9 1MHz extension bus connecting to PL10 The 1MHz bus is a fully buffered interface to the CPU via PL11 which operates with lus transfer cycles IC12 bidirectional buffer
63. S 0 2 gt 4 4 8 32 45 av m P NE GON E n 1 N H 9 2 5 3301 D 1395 05 194 7 2 AO 3 6 g 3ovyodn Eu t E 1 390n1av2 4 4 4 4 4 4 4 4 4 eru ru re L n n ae 3 a 5 E 5 Y ZN REY A zoe F go N 63 83 93 3 ta 24 1 399253 pa Zi L ZA Z a Z y 874 A id 194 0 Dd uL ot 6 4 9 5 4 i 5 olo 158 AS 6 8 n 9 E 7 2 t 0 T arme MS 2 2 9 al El vu lao ave Eva 413 97 Keyboard circuit diagram AS NODO AS AGI 0 QOO a 02 Lou 9 619 X d 1905 7 10 6 08 2 1 BulmBip QUIASSE o uoreuuoo 84 0 S320N y 10981891 3snfpe 3nd3no AZI AS 084 92H SZU a AND QO ON 1 99 Power supply circuit diagram
64. S ES ES ES 29 J ES ES ES ES ES ES ES ES ES ES ES ES ES ES STO STO STO STO STO STO STO STO STOI STOI 3 uw uw Y STOI S TOI STO STO STO STO STO STO STO STO STO STO STO STO STO 5 J 9 70 39 DW R AM J 2 2101 4701 6801 8201 J 9 79 39 DW 1K2 1K5 1K8 2K2 2K7 3K3 3K9 4K7 5K6 8K2 10K 12K 15K 22K zoo N B Assembly 25W5 225 2 25 2259 225 25 25 225 25 225 25 25 25 0 25 0 25 gt O1 gt O1 3 lt oo gt gt ou E Nu Components marked fitted only with 8271 please contact your supplier for details of availability REMARKS R76 TYP 3k3 to 6k8 R58 121 122 153 R53 55 R94 109 1 R62 65 67 31 45 47 57 61 1 5 8 R37 FERRANT R20 21 40 R30 35 R49 75 88 102 R85 91 92
65. SECTION 2 BBC Microcomputer Model B BBC Microcomputer Model Service Manual Contents J CO CO CO WW WWW CO CO CO N 01010101 0101010101010101 A 200 JO I Introduction Packaging and installation Specification The microcomputer Power supply Video outputs RS423 Cassette interface Analogue to digital convertor ECONET CENTRONICS compatible printer interface Audio output Environment Dimensions wW e 200 010 0101014 AAAA 0 ho RO ONE Disassembly and assembly Circuit description General CPU timing Reset circuitry Address decoding and memory ROM operation Paged RAM operation RAM access RAM circuitry Disc interface 8271 FDC 1770 FDC Video circuitry RGB Composite video UHF CENTRONICS compatible printer interface User port 1MHz extension bus TUBE interface ECONET Cassette and RS423 ports Analogue to digital convertor Audio circuitry Keyboard Upgrading the PCB 1770 disc option 8271 disc option ECONET Speech Selection links 65 DUO 0 CO NR 2000 AAN O1 CO CO S OO Test equipment Fault finding Switch on Power supply Oscillator and divider circuitry CPU ROM DRAMs Video Cassette interface and RS423 Keyboard Disc interface Printer port User port 1MHz extension
66. Trsh COLUMN address switching Outputs 4 and 10 rates a non overlapping two phase clock Schottky is used for minimum gate delays and to allow low value pull up resistors to be used ure the MOS logic 1 voltages needed by the 6512A CPU inverts the RAS pull ups R20 and R21 the RAM timing signal he delayed RAS signal RSI to form notRAS is used to modify the NotRAS is held low for an extra 10 spec of The small dela 120ns DRAMs RSL y between notRAS and RSL helps ensure the minimum RAM RAS address hold time is exceeded IC34 74LS08 Quad 2 input AND 1 o p pin 3 combines the operating system enable with the BASIC language enable so either will select the 32Kbyte ROM IC71 Logic 0 active 2 o p pin 6 combines two NMI signals notNMI and notINT to form the complete notNMI interrupt for the CPU 3 o p pin 8 operates with 2 EX OR gates IC63 to reduce the refresh address cycle time when in display mode 7 4 o p pin 11 combines the JIM and FRED enables This signal active law indicates 1MHz bus cycle is in progress IC35 various 64K 128K or 256Kbit paged ROM A 32Kbyte device in this socket appears in sideways ROM slots 2 and 3 link S9 East fitted IC35 can be than 250ns IC36 16R4 Programmable array logic Link 59 West allows 8 or 16Kbyte any ROM or EPROM with a
67. U 42 IC78 have access to the RAM clock speed by 2MHz clock the RAM sufficiently to perform is provided encodin Screen display IC53 and various available g interleaving the accesses on alternat The RAM is thus bein each capable EPROM ICs 35 44 57 62 68 When each sideways ROM socket is decoded as two 16K 71 holds 32Kbyte ROM which C The number of the ROM 1645 BAS lled on the board in eight 64K by 1 bit DRAM 65 66 67 12Kbytes can be paged into the sideways ning 20Kbytes are used as screen memory in a Of this RAM 32Kbytes are always paged nd 6845 cathode ray tube controller Each can access the RAM at full 2MHz phases of the accessed at 4MHz The 6845 accesses the refresh function thro video processor outputs ugh the 6845 IC78 ircuits Three display RGB consists of CSYNC and R ED GR EN H BLUE m at TTL voltage levels Each colour is either on off or flashing giving sixteen displayable colour effects VID onl link 526 is made y EO output is a summation of RGB ie eight static colours and eight flashing colours luminance colour to give a grey scale the chrominance component is added to the V information D output UHF ou
68. V peak to peak 25 to 15dB 350mV RMS By miniature relay within computer Contact ratin g 1 at 24V DE 300 or 1200 b aud using standard CUTS tones 1200 and 2400 Hz tones 7 pin DIN 3 6 Analogue to digital convertor Resolution Full scale input voltage VREF Accuracy wit h respect to VREF full Scale error 0 5 zero scale error 0 5 Non linearity Input impedan 3 7 ECONET Line voltages Temp coefficient Conversion speed ce 10 bit VREF 1 8V typical typical typical 0 typical 6mV degree C 10 0ms per ch gt 1 ohms 0 25 3V typical annel typical typical into 50 ohms 3 8 CENTRONICS compatible printer interface Data strobe 3 9 Audio output Output power Speaker impedance 4us pulse 0 5W 8 ohms 3 10 Environment Air temperature system on 0 to 35 degrees C system off 20 to 70 degrees C Humidity system on 85 relative humidity at 35 degrees C system off 95 relative humidity at 35 degrees C Storage conditions air temperature 20 to 70 degrees humidity 95 relative humidity at 55 degrees C 3 11 Dimensions Height 73mm Width 415mm Depth 345mm including feet 4 Disassembly assembly To service the BBC Microcomputer B Plus first disconnect the power supply plug fr
69. a muc e iTEM147 q Lar itemise ITEM 161 4 4 ITEM 161 ww 212 WALT NOTE ITEM161 FIT EITHER 8x 4164 12 OR 1xTM4164EK8 12 64K x 120 5 64 1 1205 layout Ng ES MID G S ITEM 183 4 Eur os 504 79 dp vem d ITEM 173 N E ITEM 152 9 ITEM131 139 ITEM138 0 8 fitemts3 4 gt 1 150 d gt MEC IK gt ans 149 4 mn ITEM 181 OPTION gt o 602 5 202 211 gt T 1 181 ELISE piese 147 9 8 ITEM 154 2 2 gt Ez TEM144 RI E O 9 C 4 222341 ITEM149 ae o 93 e se Cy IE M 16 SI SULZ ZZ gt gt MEG z 5 ITEM 163 e gt 5 2 5 0 Gu 9 L 90 su su o 4 4 cov 5289 99998912716 SW31I 0647498 SW31I 179276212792 2 020217021888 SWILI 95 012 gan zan 5 o AO dur 3449 e ss as ASS Ast St WO zw 40130 dN 1491 ZMS t 2 7 5 i 9 4 9 1812 1995 7 4 4 4 4 J 4 AR AA AAN d T in B 199 SIT NI 9717 NI er Y Pony BI NI 9919 NI 9919 y 9719 9719 NF AJO OE oic Ye 8 90 a Y E
70. aces ar major components the UART or ACIA SERPROC IC85 If both the cassette interface and RS423 tester then it or its address decoding a Cassette interfac Use a PORT tester to verify that the cassett All tests on the cassett is likely that the fau interfac lt is with one of the above they share two C82 and the serial processor or fail shown up by the PORT ICs working cassett tape peak to peak Test pin 25 IC85 period is arriving at accurate If not TE the cassette fails to ttempting to LOAD a symetrical about IC89 IC89 pin 14 sh IC89 pin 1 should show a mark space ratio this is so recorder and tape cassette recorder and the azimuth adjustment recorder s volume control should be set for an output of 300mV the serial processor that pin the divide by 13 circuitry LOAD ould be similar to pin 8 This and ch sign interface is faulty must be carried out using a known The commonest fault is the user s should be checked The eck that 16MHz 13 812ns al must be stable and look at the IC89 pin 8 should show high and low tones of If there is a marked displacement then replac wi 1 4V peak to pea Reduce the volume of t Maximum 50mV displacement ormed by IC18 is faulty E gi lowing
71. also positively biased approximately 10 1 R147 w form has an open collector clock signal which is an attenuator R125 134 140 14 ith R148 set the compara 2 o p pin 12 n this comparat is a pull up and R79 gives the compara approxima rorm al cenuator tor input signals stay within or receive S a bias of about 2 vol the supply voltage S data from the tor hysteresis tS SO 5 volts R73 42 143 ECONET line R106 110 1 tely 10 1 Again to nominally 2 volts data signal to single ended 1 The comparator converts th L which is decoded ently sensitive to LM319 comparator is suffici tenuators to be used whil An idle line has a tate le still detecting differentia ECON mpressed on it by the ET line termination he micro 86 voltage the inputs are biased e differential ECONET in IC81 the ADLC The allow high impedance the ECONET idle line of about 0 6 volts networks not part of IC93 LM319 Dual analogue comparator not normally fitted This comparator circuit is not normally fitted When fitted its purpose is to detect data packet collisions on the ECONET Collisions are normally avoided by the network filing syst rare When a collision occurs it will resul detected by t
72. and SHEILA The decoder uses the I O enable from IC22 and A8 and A9 to detect the 256 byte I O blocks o p 4 is FRED amp FC o p 5 is JIM amp FD o p 6 is SHEILA amp FE 1C29 TMS5220 Speech synthesiser optional 1C30 7415259 Octal addressable latch This device expands the number of output bits available for system contol functions It is driven by the operating system through the system VIA IC20 1C31 74574 Dual D type flip flop ot IC30 2 contents half period of 8M This device is schottky to minimise device delay uncertainty 1C32 7415374 Octal D type This device is used to sychronise de glitch the 1MHz device control signals By using 1M to clock the register signal changes the system VI A 1 o p pin 6 disables the addressable latch to avoid VIA o p glitches disturbing the latch IC30 during a CPU access The function does not need schottky speed is low o p pins 8 and 9 generate timing for RAS clock RAS is a delayed 4M clock can only occur while 1E inactive the RAM row address the delay being nominally 62 5ns 75 IC33 74502 1 connected as an Quad 2 input NOR o p pins 1 4 and 10 form the CPU clock generator R S flip flop which gene The ens 2 o p pin 13 row address clock high low approx to meet controls the ROW T ratio of notRAS the longest known
73. any program code in the VDU code Spaces must not address RAM between 683000 and amp 7FFF unless it intends to write to the shadow RAM A serial ROM which contains the speech vocabulary data 37 TMS6100 screen Speech PHROM used by 1C29 IC38 5 76489 Sound generator This IC contains three sound channels and one noise channel The sound pitch attack sustain decay and releas ar independently programmable from BASIC or machine code Control is exercised through the system VIA IC20 IC39 7415139 Dual 2 to 4 line decoder 1 o p pins 4 5 6 and 7 This decoder is enabled by IC21 for I O address values between amp FEO0 and amp FEIF The IC uses address lines and 4 to complete the I O address decoding for the CRTC amp FEOO 1 amp FE08 9 SERPROC amp FE10 and the ECONET control signal notINTOFF notSTATID amp FE18 2 o p pins 9 10 11 and 12 decode address values amp FE20 to amp FE3F into 2 write only blocks and 2 read only blocks only one is used At amp FE20 WR is the VIDPROC amp FE20 RD is INTON an ECONET control amp FE30 to amp FE3F WR is ROMSEL space see PAL IC36 1C40 741520 Dual 4 input NAND 1 o p pin 6 controls the paged ROM notOE signal All pa
74. bus TUBE interface Analogue to digital conversion ECONET A p nt p LO LO XO LO Appendix Connector pinouts Parts list Glossary IC description Final assembly Circuit block diagram PCB circuit diagram PCB layout Keyboard circuit diagram Power supply circuit diagram Ss WW CO PS AB 1 O ag WN a al Dos 2 58 63 69 71 89 93 95 97 99 E I WARNING Green amp Blue Brown Th plac Th COMPUTER MUST The wires in the ma in accordance with the followi e moulded plug must be used with BE EARTH ED ins lead for the apparatus are coloured ng code Yellow arth Neutral Live the carrier is of the s fus the the necessarily the base of are not in moulded pl another replaceme of th with ug MU n TE th terchangeable conventional fuse carrier e fuse blowing it should be replaced a 3 amp fuse that is ASTA approved to e socket outlet available is n same shade of that col plug Different manufac use and fuse carrier firmly ame basic colo
75. circuits are more likely to give the tests 9 13 1MHz extension bus Use a PORT tester tester may show up all kinds of errors the 1MHz bus Use the following program to xercis th beca decoding 10 fred 20 jim 30 DIM 40 50 start 60 LDA amp 00 70 1 80 STA fred 90 STA jim 100 JMP loop 110 1 120 amp FCOO amp P 100 CALL start RU the program and test pins 4 and 5 low for If the 1MHz extension bus is faulty then the PORT use it is driven through FRED and JIM address lus or 1 5us CPU s synchronisation to 1M N signals which should be pulsing e g Check that the nals are good then test them at pins 16 and 14 40 If not then replace IC28 for the FRED and JIM depending on IC28 If the EC is high when either FRED or JIM is low 41 Check that SYNC 1M 8 Check that the ROM output enable pin 6 is high when either FR ROM disabled ED or JIM is low is when either FRED or JIM is low All the above thr data bus buffer enable pin 19 12 signals come indirectly rom 11 low Check that the data bus DO D7 goes some point after the buffer is enabl low both pin 19 ed enabled IC34 Sid
76. ck the ROM socket and the ROM If the ROM works OK then check that the data address and control signals are reaching the 1770 6 Check for pulses on pin 1 of 15 after a break If there are none check the address decoding logic Press SHIFT and BREAK then release BREAK while holding SHIFT down Drive 0 should start the LED on the front of the drive comes on Results if drive doesn t come on then check using an oscilloscope or logic probe that MO pin 20 IC16 is high notMOTOR pin 10 IC8 is law Check that SO pin 7 IC17 is high nots0 pin 8 IC7 is low If the above signals are correct then check the connection from IC7 and IC8 to connector PL8 If the above signals are wrong then try a good 1770 and check 17 Check that 1 17 is reset after a BREAK all outputs law Check function by poking values between 0 and 64 into location amp FE80 Check that the correct bit pattern appears on the outputs an Try CAT ch th eck that en check that 58 to get a catalog S7 is fitted is System has worked before Ch TE LO Use an oscilloscope to moni the signal end of R7 period 4us or 8us 50 eck that after a BR not If drive does come on with SH track disc into drive O0 d make sure that a write protect Use a disc ue East fit
77. cycles and 300ns before phi2 on write cycles The following items of test equipment are required for fault finding PORT tester 10A Multimeter logic probe 20MHz dual beam oscilloscope TV composite monitor colour monitor cassette player disc drive frequency counter 5 ohm 5W resistor 9 1 Switch on Connect the suspect microcomputer to a UHF TV and an RGB monitor Connect the mains supply and switch on both the monitors and the computer One of the following will happen a There is noise on the monitor screens no signal from computer There is no power on beep sound there may be a continuous noise and the LEDs do not light or light incorrectly Results either power supply is dead or there is a fault in the heart of the microcomputer 36 Follow the sequence of checks shown below 1 If there is no noise on power up the power supply see 9 2 2 If a PET tester is available then use it on the B providing the CPU is running and it can access the ROM although it may give strange screen output fail The PET will not work at all then either the CPU isn t running or cannot access the ROM 3 Check HS and VS signals 39 and 40 1 78 oscilloscope every 64 us and VS pulsing every 20ms Results if they are stuck or floating then carry on with the checks and no L
78. d fault finding section use for servicing A detailed description 4 which are new B of the BBC Microcomputer 5 1 General The microcomputer uses th timing of the requires two clock signals at respects it functions in the same way as 6512 CPU logic circuitry than did section 9 should prove to be of more is given of those features clocks X IC53 The computer oscillator circuit video processor ULA are and half of 42 which allows more accurate the 6502 see 5 2 The 6512 MOS voltage levels in all other the 6502 derived from 16MHz crystal controlled IC26 and divider circuitry in the The 6512 accesses 31 1 4Kbytes of ROM 3 4Kbyte of memory mapped input output and up to 44Kbytes of RAM 64Kbytes of RAM are installed on the PCB the extra 20Kbytes being used for the screen memory in shadow mode see 3 1 The memory mapped I O is located in pages amp FC amp FD and amp FE of the CPU address space Th are fiv of taking an 8 16 used with a 32K ROM Sideways ROM slots contains the operating r 64Kbytes of RAM are ins chips ICs 55 56 60 61 ccessible to the CPU ta 64 Sideways ROM sockets installed on the PCB or 32Kbyte ROM or A sixth ROM socket System and currently in use is held in the ROM select latch a ROM space and the remai shadow mode Both CP
79. de select signal are held in the latch Also the disc format mode single double density and a 1770 master reset signal are held in this latch All these signals are under direct program control The latch is addressed at amp FE80 IC18 7415163 Presettable 4 bit counter Configured as a divide by 13 to give 16MHz 13 clock for cassette and RS423 baud rate generation and disc speed detection IC19 741500 Quad 2 input NAND 1 o p pin 11 detects a count of 12 on IC18 and generates a synchronous load pulse so that LC18 divides by 13 2 o p pin 8 is used as an inverter to generate notW for the system RAM 3 o p pins 3 and 6 are part of the decoder that converts the 2 bit code for display RAM size from the addressable latch IC30 to the 4 bit code fed to the adder IC76 13 20 6522 System VIA This is a versatil interface adapter VIA C The A data lines are used for communication with the keyboard speech system and sound is VSYNC from the CRTC which interrupts the CPU every 20ms CA2 generates an interrupt when a key is pressed PBO PB3 drive the addressable latch IC30 4 and 5 are inputs from the joystick fire buttons PB6 and PB7 are inputs from the speech processor is the end of conversion signal from the analogue to digital convertor LC84 CB2 is the light pen strobe signal from pin 9 of the 15 D type connector SK6 used fo
80. deo processor IC53 IC33 pin 3 should be low pin 8 IC41 which should also be low IC25 If SYNC 1M is stuck high then find which one of the inputs to 41 is stuck low The 1MHz device attached to this input must be checked 7 Check activity on the CPU address lines If after a BREAK the the CPU cannot read Check activity starts and then stops this suggests that the OS ROM Check the OS ROM by replacing it with a known good one Check that it is enabled and that all address lines are present following BREAK that notOE pulses low at 2MH inverse of phi2 and notCS goes low and stays low for a time 8 Check all clocks from video processor 8M 4M 9 After BREAK check CRTC notCS pin pulses low 2M 1M pin 25 If all the above checks pass then the machine exhibit the symptoms stated in a see 9 3 IC78 should do more than 37 b The screen synchronises noise but there is only flashing cursor in the top left corner Results usually caused by a keyboard fault Check that the keyboard is connected correctly see 9 9 The banner message appears but is incorrect or incomplete d The correct banner message is Acorn OS 64K filing system language gt For example with a 1770 FM disc filing system and BASIC language the correct banner message is
81. derived by mixing cambinations of the two master chroma signals or their inverse with a bank of ex OR gates Phase Alternation by Line the chroma signal For PAL reference phase is shifted 90 degrees on alternate lines An exclusive OR gate 1083 driven from half of IC69 modifies one of the ring counter outputs to cause the required phase alternation For NTSC operation link 528 be changed to give a constant reference phase IC83 pin 13 to Ov R92 must be removed for NTSC and the crystal X2 must be 4 times the colour carrier frequency of the NTSC broadcast standard eg 14 318MHz for USA The chroma waveform phase and amplitude are selected by the red green RGB controls and blue RGB signals from the video processor the six ex OR gates 86 and 83 to direct the required phase s of 4 4336MHz to the NAND gate array IC87 and 90 and to ena ble the appropriate NAND gates Resistors R85 to R92 mix the NAND gate outputs to form a single chroma signal including the colour burst E R89 are used to match the DC level from the resistor mixing or all colours but not the colour burst A crude low Q tuned formed by Ll and C40 filters the chroma signal before it is buffered R86 and network with the emitter follower Q9
82. disables the ROM output drivers when an I O address occurs amp FC00 amp FEFF The currently selected ROM number 0 15 is held in the ROM select latch IC45 The ROM select latch is mapped into the memory at address amp FE30 via the PAL IC36 When writing to this address the four data lines D0 D3 provide the ROM number which is latched into IC45 see also 5 4 2 When the PAL decodes an address from amp 8000 amp BFFF IC36 pin 18 goes low and enables 46 46 is a thr lin to eight line decoder which selects the particular IC socket allocated to the ROM number in IC45 The least significant bit held in IC45 is fed to the relevant ROM Socket only if the link for that socket is made E for a 32K device The correct half of the 32K device is then selected to be placed in the memory map 5 4 2 Paged RAM operation The 12K paged RAM is selected with a ROM number between 128 and 255 D7 set The top bit of the data bus D7 is available to the PAL IC36 Writing to the ROM select latch at address amp FE30 as described in 5 4 1 will save D7 in the PAL DO D3 are stored as normal in IC45 If D7 is set logic 1 then the PAL selects the 12K paged RAM when the CPU address is in the range 58000 to amp AFFF is present then the top of that ROM wi map abo
83. e with connector headers in first and pulling it forwards as far as possible until the back edge drops in Be careful not to trap the composite video wire to the BNC connector if this was removed Replace the PCB fixing screws Reconnect the composite video and its connector Reconnect the power supply being careful to route the wires neatly and connect the wires seven to the push on connectors on the PCB being very careful to get the polarity right PCB connectors marked VCC must have a red wire attached three PCB connectors marked OV must have a black wire attached three The connector marked 5V has the purple wire attached one Replace the keyboard and reconnect the loudspeaker to the main PCB Be careful to reconnect the keyboard ribbon socket so that all the pins are engaged it is easy to displace the connector one pin to right or left Replace the 10 serial ROM connector if fitted Replace th nuts and bolts holding the keyboard in place Make final check that all reconnections have been made correctly especially the power supplies which will short circuit if two are reversed Replace the lid and press down at the rear whilst tightening the two rear fixing screws Finally replace the front two fixing screws 5 Circuit description This circuit description has been kept as simple as possible as the detaile
84. e the CPU data bus with the ECONET station ID The buffers ar nabled when the CPU reads address amp FE18 A write to amp FE18 will result in a data bus drive conflict and should not be attempted Link 523 sets the station ID Each link has a binary value with the largest 128 decimal at the North end of the row A broken link shunt removed adds the link value to the station ID eg all links fitted gives 0 83 81 681 54 This IC is an ADLC dva Each byte of an ECON ET trans Serial data link controller ECON ET only fer managed by a network fil ling syst softwar It enabl by a clock detection clock NotCTS is tes See comments on coll NMI interrupt which IC69 and IC70 A present as not IC82 6850 ACI A A UART is a transmit and receive data conversion for s th ECON nced data link controller or transmitting and receiving serial data to an is under interrupt control The notRTS signal is controlled ET line driver It is responsible from the ECONET and is d IC91 NotDCD is driven circuit ted to check for n ision det is enabled disabled under program control ection un k7 pull up resistor UART serial asyncronous data either nterface
85. ed lines notPAGEFC 1MHzE or the 1MHz extension bus to LA3 notPAGEFD Permanently enabled buffer are four address lines LAO RnotW 7d IC7 7438 1 pin 6 is drive sele from controller circuitry Quad 2 inpu able to drive a 150 ohm pull up resisi t o c NAND ee uds to form Gate th either disc interface s motor control and drive select e external drive select Must be tor hence cannot be LS TTL 2 o p pin 8 is drive select 0 see above 3 o p pin 11 is used to buffer and invert the disc controller interrupt signal on to the wire NOR notNMI interrupt line 4 o p pin 3 gates the 1770 DRQ on to the interrupt line Used only with 1770 hence link S8 used to select 1770 made or 8271 broken option f IC7 is fitted and the disc controller is not then IC7 pin 13 or pin 2 or R14 must be pulled low to avoid notNMI being held low permanently which would stop the ECONET hardware from working IC8 7416 Convert ts active high signals Hex o c inverter from disc control circuitry into the active signal drive capability 9 741500 Quad 2 inpu 1 2 window pulses is 8us high when the nex resets the latch then the latch stays reset 3 o p pin 3 is used as an pulses needed to reset the data 10 0 6522 o p pin 11 decode
86. er bits IC18 divides the 16MHz clock signal by 13 1 23 MHz and this signal is divided further within the serial processor to produce the synthesised 2400 1200H cassette record signal and the bit rate clocks Automatic motor control of an audio cassett recorder is achieved by using a serial processor 24 small relay driven by transistor Q7 from the 25V and 3V A a read of amp FE20 R66 and C30 provide the necessary timing elements for delay between receiving the high tone run in signal detect signal to Th sh Th RT 95 an RS re Se the serial processor co e signal caning the 6850 from the cassett aped by three s recorder is buffered and asserting the data carrier filtered and tages of the LM324 amplifier IC89 e RS423 data in and data out signals and the request to send output S and clear to send input CTS signals are i translate between TTL and standard RS423 signal which d 5V 423 sign ntrol set the RS423 rec als are compa lated equipment ection of the casset nterfaced by ICs 94 and levels 5V 5 The A to four analog licon diodes si VO vi 13 Anal D ltage of a CB1 of D9 the 6522 D10 from SK6 and 111 1 8V When a conversion is complete IC20 pin 18 which generates an
87. es place depending on which phase lE was on when the request was received from 41 see figure 2 2M 2E 1E Figure 2 2MHz to 1MHz transition 5 3 Reset circuitry The system has two reset circuits one is a general reset from a 555 timer 1C43 the other is an RC network which just resets the system VIA IC20 on power up This allows the software to detect the differenc between a power on reset and a BREAK key reset The keyboard BREAK key connects via S10 a PCB made link to the 555 timer The 555 generates reset pulse RS which is inverted to give the CPU notRS signal 5 4 Address decoding and memory Figure 3 shows the memory map 13 4 BACKGROUND Bog ROM 16 SIDEWAYS ROMS 2 11 12K SIDEWAYS 9006 gt SHADOW SCREEN RAM 3899 Figure 3 Memory map 14 FFFF Frog OPERATING COOD ROM 1 14 15 8020 NORMAL SCREEN RAM 3094 0 00 UPWARDS WORKSPACE 0009 At the hear PAL chip shadow the paged RAM IC36 5 4 1 ROM operation Any ROM socket on device 8K or 16K or from amp 8000 amp BFFF of memory paged address line A14 to each socket IC numbers corresponding link n the PCI into the memory map QA ROM slot when the appropriate molex their corresponding umbers are shown
88. es ven when not required except for the purpose of refresh But data to or from the RAM is only available to the CPU when the data buffer 49 is enabled This occurs when input to the NAND gate in half of 40 goes low that is when A15 is low address between amp 0000 amp 7FFF or if the paged RAM signal fran IC36 is low address between amp 8000 amp AFFF and paged RAM selected or if the video processor VIDPROC is enabled address amp FE20 RAM is disabled when the VIDPROC is written to by holding notCAS at logic 1 see IC23 5 5 Disc interface There are two floppy disc interfaces which can be fitted to the PCB based on either the 8271 floppy disc controller for FM only or the 1770 floppy disc controller for FM and MFM 5 5 1 8271 FDC Two open collector buffer ICs are used to drive the disc unit 7416 hex inverter IC8 is used to invert the true control signals output by the controller IC15 Two gates from a 7438 quad NAND gate controller s drive select lines with the load head signal motor control line IC7 generat th two drive select signals combining the used as a Each data pulse from the drive triggers retriggers a monostable pulse generator ICl The pulse clears an R S latch formed by two cross coupled NAND gates 9 and clears the bit interva
89. es of the buffer at IC12 goes low 53 9 14 TUBE interface Use a PORT tester to check that the TUBE interface is faulty Run the following test program 10 tube amp FEEO 20 DIM P 100 30 40 start 50 LDA4 6001 60 loop 70 STA tube 80 JMP loop 90 100 CALL start Test the enable pin 19 4 with an oscilloscope and check that the signal is wobbling If not then check the address decoding performed by IC21 and IC22 Check that all data lines both sides of the buffer pins 11 18 and pins 9 2 of 4 D0 D7 go low at some point after th nable pin 19 IC14 goes low Change line 50 of the program to 50 LDA amp FF and check that all the buffered data lines go high at some point after the enable 19 4 goes low If these tests do not give correct results then check the data bus buffer 4 and the PCB tracks and connections to PL12 50 50 LDA amp 55 can also be tried These correspond to output bit patterns 10101010 and 01010101 0 4 R notW and 2E be looked for on pins 12 9 7 5 3 16 and 18 of IC13 These signals should be the same as the system signals but delayed by 10 15ns 54 9 15 Analogue to digital conversion Use a PORT tester to verify that the ADC circuit is faulty Check VREF by measuring the voltage b
90. ette recorder IC90 741500 Quad two input NAND o p pins 3 6 8 11 are four gates which are selectively enabled to drive the colour subcarrier resistor mixing matrix to generate th colour subcarrier phase for the current display colour L1 C40 and R113 in parallel with R114 form a simple low Q band pass filter tuned to the colour subcarrier frequency 4 43MHz which reduces the harmonics of the chroma colour signal IC91 75159 Dual RS422 line driver ECONET only 1 o p pin 2 used as an inverter Forms a true RTS signal to trigger clear the ECONET timer monostable 2 pins 12 13 drive the data lines with RS422 differential signal An RS422 signal has nominal TTL logic levels two lines are driven to opposite logic states to give differential signal transmission The gate is capable of driving a 50 ohm load tied to 2 5 volts When the ECONET interface is inactive not transmitting the driver is in a high impedance state A logic 1 on pin 9 enables th driver IC92 LM319 Dual analogue comparator ECON ET only 1 o p pin 7 senses the ECON ET clock signal amount of hysteresis to avoi d self oscillation R78 introduces a small of the comparator when no signal is present which indication R63 is a pull output The comparator rece would resul in permanent clock preseni up the comparator ives an attenuated
91. etween pin 8 IC84 and ground This voltage should be approximately 1 8V Look for shorted or broken tracks if it is not Connect two known working 2 way joysticks to the D type connector SK6 used for the ADC Type in and RUN the following program 10 NDU 23 1l 020 0707 20 CLS 30 REPEAT 40 PRINT TAB 0 0 ADVAL 1 5 4 50 PRINT 0 2 ADVAL 2 SPC 4 60 PRINT TAB 0 4 ADVAL 3 SPC 4 70 PRINT 0 6 ADVAL 4 5 4 80 UNTIL 0 Move the joysticks and see if you can get numbers in the range 0 to 65520 on each of the 4 channels In practice it may well not be possible to get near either one or both of the end values but a good range of numbers on each channel is sufficient to show that the converter is working If this experiment does not work then check that the ADC IC can be accessed by running the following program 10 adc amp FECO 20 DIM P 100 30 40 start 60 JMP start 70 80 CALL start Check that pin 23 IC84 is active If not then check the address decoding and connections from pin 9 IC21 Press CTRL BREAK and look at the signal on pin 28 IC84 This line Signals the end of conversion and should be pulsing low approximately once every 10ms If it is but there is still a problem with A to D conversion then check that the EOC signal is reaching pin 18 20
92. ged ROMs are disabled during CPU write cycles by this gate R notW i p ROMs are also disabled for the I O address space FRED JIM and SHEILA The not2M clock ensures ROMs can only drive the data bus during phi2 which avoids bus drive conflicts during address changes o p pin 8 ORs three active low signals to form an active high RAM 2 data request signal enable the RAM data buffer A15 49 s low OR notPGRAM low OR notV 1C48 o p 12 DPROC low will 77 41 741530 8 input NAND ORs five I O enable signals to form the active high 1MHz cycle signal SYNC 1M This signal is used by IC25 to trigger 1 and phi2 clock syncronisation The five input signals correspond to the various I O devices which operate with 1MHz 1E interface timing 42 6512A CPU The 6512 is member of the NMOS 6500 processor family This is unctionally similar to 6502 the only significant difference being in the clock drive A 6512A uses MOS level clocks phil and phi2 and so gives more precise system timing than is possible with the TTL phi 1 clock of the 6502 THE TWO PROCESSOR TYPES ARE NOT INTERCHANGEABLE This microcomputer can use 2 3 or 4 MHz CPU parts 6512A B C IC43 NE555 Monostable IC The 555 is used as a monostable for generation of the microprocessor System reset
93. he fil hardware is not fitted then link fitted IC94 88151 compatible attenuated o p pin he risk of tem protocol t in data corruption ling system error checks when collision detection If collision detection should be required and so are S29 should be broken and IC93 and its associated components 20 Dual RS423 receiver circuit 1 o p pin 7 receives the RS423 port data sig nal This input is also with RS232 data To reduce the voltage swing the signal is bandwith and so reduces by 8124 118 C31 reduces the signal 9 receives the RS423 notCTS contro signal glitches in the received signal presented to the S 8149 152 E 2 attenuate 524 and 525 are optional links which connect interna resistors TC95 369T signal C4 2 efp pin limits the which might caus interferenc to other equipment Note in most applications this line can interface to an RS232 device 15 drives the data line of an RS423 interfac C44 slew signal K8 SIL pack 64Kbyte DRAM 120ns access IC96 4164E This devic the voltage levels while C35 filters the si gnal termination to ground These links should not be Dual RS423 line driver fqt beds e can be fitted as an alternative to 8 off 64Kx1 DRAM integrated circuits ICs 55 56 60 61 64 65 66 6 Y
94. ing phil Also it forces the RAM to be read only during VDU cycles Note the buffer is active for RAM or VLDPROC access During a VIDPROC write the RAM is disabled by holding notCAS at logic 1 see IC23 and 52 1C49 7415245 Octal buffer The RAM and VIDPROC data bus buffer This IC isolates the RAM data bus from the CPU data bus to allow VDU read cycles to occur without interference from the CPU data bus cycles data bus IC50 and These two ICs select address lines The CPU signal from the PAL IC36 high because IC50 and 51 law avoid loading the phi clocks IC52 74500 1 Quad 2 input NAND particularl Another important function of the buffer is to reduce the CPU loading by isolating the RAM and VIDPROC etc y during 1MHz device IC51 7415257 Quad two to one data selector the RAS and CAS address signals from the CPU 15 is not used The CPU address The A15 input is the CPUSEL are disabled phi2 low is the VDU RAM access period o p pins 3 and 6 connected as an R S flip flop is only valid during phi2 held tristate while phi2 is 2M is used as an enable to The set and reset signals are the inverted and delayed 4M and 8M clocks respectively The output signal on pin 3 is the precursor of the 6MHz clock used by the TELETEXT display circuit See 1063 3 2 o p
95. inverted and wire NORed on to the notNMI line by two parts of quad NAND gate Link S8 selects between the single interrupt of an 8271 and dual interrupt of a 1770 When a 1770 is fitted S8 must be made For the 1770 option link S7 is made East this and so defines the ler and the CPU Link ble to allow program controlled suppression of 1770 disc is not present when 5 6 1 RGB Red green and blue signals are produced by the are then buffered by 01 Q2 and Q3 to be fed to at TTL type levels The fourth signal required at composite SYNC sync of the 6845 CSYNC ge composite video nerated from horizontal CSYNC polarity can be altered using link S27 the 8271 is fitted tion is not used at present so 55 is not fitted and UHF video processor and the DIN socket SK3 the RGB output is a sync and vertical The OV and 5V power supply also appears on SK3 5 6 2 Composite video Composite video blue darkest to yellow whi 8104 and 8108 on BNC connector SK2 to give a grey scale lightest is is a summation of the three primari S red green and black blue red mixed with negative CSYNC green The grey scale is set by the resistor values 8101 The order from magenta cyan These feed 08 which produces a 1 peak to peak signal The chroma component described in 5 6 3 may be added to the compo
96. isabl IC84 upD7002 Analogue signals input via val to give the phase alternating line led by making S28 South SK6 are ue channel to a 12 bit a signal Three diodes reference which is temperature coefficient completed conversion by generated by the system digital 1 nterrupting r references by 180 converted The ADC informs the processor of 4 PAL subcarrier PAL can 4 channel analogue to digital converter about 10ms per IRO Interrupts are A D9 D10 11 C20 when it receives active notEOC S ar Note that typically 1 8 volts with a the accuracy of the ADC part is equivalent to a resolution of about 8 bits 84 used for the voltage 6mV per degree C IC85 ULA The SERPROC handles Serial processor the RS423 and cassett IC interfac circuits Built into the IC are programmable clock generators which set the serial bit rate Signals from t routed to from the 68 are demodulated in IC85 and a initialise the preambl the SERPROC control ton signal on pin he 50 bit clock sign data reception Motor control A control bit in 11 IC82 by this selected interfac RS423 or cassette TG When the The replay cassette signal are S al is
97. isio 454514 91 iv Insert 30 B Solder the 14 pin DIL sockets into positions and 92 into their sockets See below n detect circuitry is to be fitted the track link at 29 should be cut before proceeding see below IC91 and 92 v Solder all the remaining correct positions on the PC though this may degrade reliability ICs resistors and capacitors into their B C81 may be socketed as an option vi Solder the two 8 way wafer connectors into the PCB in their correct positions and then push the seven shunts onto all but the North most pins vii Solder the DIN socket into the PCB viii Insert the filing system ROM eg DNFS into a vacant sideways ROM socket Note DFS ROM already i that where nstalled a B machine is already fitted with the 1770 Disc Interface a DNFS ROM must be fitted in addition to the 1770 ix If collision detect circuitry is required the additional components given below must be fitted OTY DESCRIPTION CIRCUIT REFERENCE 1 RESISTOR 1K0 0 25W 5 R68 4 RESISTOR 56K 0 25W 2 895 96 98 99 1 RESISTOR 1M5 0 25W 5 R97 1 CAPACITOR 10nF CER PLT C28 1 IC LM319 IC93 2 SOCKET 14 PIN DIL FOR IC93 X In order to co using the approve 6 4 Speech Speech
98. l timer formed by two divide by sixteen circuits 2 NAND gate IC9 If the bit timer then interval exceeds the time determined by the bit interval window and the read data pulses to decode the serial data interprets the bit value as logic 1 conversely if DW data bit is a logic 0 Logic 0 bits are encoded as 8us pulses logic is as 4us and each bit interval is 8us the latch will be set DW 1 The 8271 monitors the latch the data stream If the latch is reset DW 0 when a data pulse occurs the 8271 1 then the between RD 19 The bit interval 5us Disc speed is measured by timing the interval bet which are nominally 200ms apart th RDYO and RDY1 ICA tor off forces both stages o high and bo counter off Mo pin 13 is One interval timer is designed to detect an in terval of approx 6 Lween timer 1C4 index pulses is used for 16 13 MHz 1 2307 When all drives are off MHz is IC3 pin 2 notRDY i when MOTO de f R C4 pin tect the state o clocked ICA goes law IC3 can now be f the digital timer S high then th int 11 4 11 greater than 2 2 18 812 5ns and 1 at logic 0 when 13ms is stil disc speed disc revolution th the MOTOR sign IC3 to predefined states 5 high rval
99. lastic boss in the centre of the left side of the modulator 42 Press the BREAK key and check that the PAL voltage waveform looks something like figure 9 Colour burst Figure 9 Black PAL voltage waveform Type in the following COLOUR 129 CLS and press RETURN The waveform should now look something like figure 10 3 3V Figure 10 White PAL voltage waveform 43 Results if the two waveforms are correct the UHF monitor does not give a display then the UHF modulator is faulty and should be replaced If any other part of temporarily and test the The waveforms should be including colour burst associated resistors inserted the correct way 10 but of reduced amplitude If the video output waveforms If the colour burst part of the wave lies in the chrominance circuitry El orms is missing then the fault see c the waveforms is incorrect make link 526 composite video output with an oscilloscope similar to If the composite output waveforms 1 peak to peak those indicated in figures 9 and are good with link 526 made but the UHF output does not work then the Check that round the ault lies in the UHF luminance circuitry Q6 D12 D13 D14 C36 and diodes D12 D13 and 14 are is marked are bad then th video luminance circuit
100. ltra High Frequency signal for input to a TV aerial Logic Array semi custom IC Variable Capacitor Visual Display Unit Versatile In terface Adaptor 6522 Variable Resistor A synchronous enable or clock peripheral or 65xx 68xx family ICs 1 is a continuous 1MHz square wave 1 MegaHertz A synchronous enable or clock peripheral rom video processor for 65xx 68xx family m ICs 2E may have two or three half cycles suppressed to synchronise it to 1E 2 MegaHertz 4 MegaHertz 8 MegaHertz x rom video processor from video processor from video processor IC description 7415123 Dual monostable one half used 8271 FDC only Required only by 8271 disc interface This monostable defines th pulse width of data pulses from the disc drive during disc read operations Pin 9 receives negative pulses from the disc drive the monostable triggers on falling edges and generates a negative pulse of about 0 9us on pin 12 2 7415393 Dual divide by 16 8271 FDC only This IC receives an 8MHz clock Along with a NAND gate part of IC9 this chip forms a digital timer monostable It is set to about 6 5us and gives the decision point between logic 0 and logic 1 data bits from the disc drive
101. mation phase is varied on alternate lines Henc Phase Alternate Lin PAL ii Abbreviation for a type of logic integrated circuit IC which is programmed by fusing microscopic links in the IC Programmable Array Logic circuits are used to reduce the number of ICs needed on a circuit board PB Port B The other port of a VIA PCB Printed Circuit Board Ol etc OWERTY RAM RAS RC RGB ROM ROMSEL RS423 RTS S1 30 SK TTL HU AS 70 Test devic Model B Will designed for use with BBC Microcomputer work on the B but with different results see information manual supplied to dealers CPU clock input non overlapping with PHI2 CPU clock input also called 2 Header PLug Test device for use with Microcomputer Model B Power Supply Unit Transistor numbers Signifies standard typewriter key layout Red Green Bl ROM SELect Random Access read write Memory Rae Address Strobe control line for the DRAM Resistor Capacitor network ue individual colour signals for the VDU Read Only Memory la tch PCB links Socket An internationally defined convention for serial transmissio Ready To Send control output on RS423 port n of data Tranistor Transistor Logic a standard type of digital socket Uncommitted IC 74 series U
102. n objects are inserted through any openings in the microcomputer Do not block 3 Specification 3 1 The microcomputer The microcomputer is contained in a rigid injection moulded thermoplastic case and provides the following facilities 73 key full travel QWERTY keyboard including 10 user definable function keys Keyboard has two key rollover and auto repeat Fully encased internal power supply manufactured to BS 415 Class 1 Internal loudspeaker driven from a 4 channel sound synthesis circuit with ADSR envelope control A colour television signal for connection to a normal domestic television aerial socket is available through a phono connector This signal is 625 line 50Hz interlaced ncoded PAL A and is modulated on UHF channel 36 A BNC connector supplies a composite video output to drive a black and white or PAL colour monitor 6 pin DIN connector provides separate RGB and sync outputs at TTL levels RGB are all high true and sync is link selectable as high or low true pulse duration 4 0 microseconds A standard audio cassette recorder can be used to record computer programs and data at 300 or 1200 baud using the Computer Users Tape Standard tones The cassette recorder is under automatic motor control and is connected to the computer via a 7 pin DIN connector An interrupt driven elapsed time clock user settable 6512A processor
103. ogram from the data connector and back again through the receivers RXD back to the 6850 This loop allows all the components of the RS423 for the SI ERPROC and 6850 is working way of testing RS423 without using another RTS to CTS and Dout to Din Then if the above is used to transmit data its path can be followed bus through the 6850 SERPROC drivers out through the circuit to be checked as above 9 9 Keyboard S ERPROC and through Keyboard problems either show up as a single key which won t work reliably or a whole group of keys which refuses to operate The single key fault is caused by that particular switch having worn out solder the track For multiple key problems connectors connector of T cab keyboard assem are lace the r or the track becoming broken by excess forc the first It th Replac thing to check is inserted correctly tions are good then c hasn t been broken wh ibbon cable with a bly with a good one the keyboard ribbon cable o the connect le itself ne pin to th heck that one of ere it is held by the ood one Try replacing is easy to displace either e left or right the wires in the key or that the connector the whole If it still doesn t work then there is probably a fault in the computer itself Use a PORT te
104. om the mains and remove all peripheral connections from the computer To disassemble The lid of the microcomputer case may be removed after undoing four fixing screws two on the rear panel and two underneath Take care not to lose the two spire clips pushed onto the case lid into which the rear fixing screws locate DO NOT remove the lid with the mains power connected Inside the microcomputer are thr main sub assemblies power supply unit keyboard and the main printed circuit board To remove the keyboard undo the two screws and nuts holding it to the case bottom taking care to note the positions of the associated washers Unplug the 17 way keyboard connector and the 2 way loudspeaker connector from the main printed circuit board and the 10 way serial ROM connector if fitted The power supply unit is connected to the main circuit board by seven push on connectors which may be unplugged Three screws on the underside of the case are undone allowing the unit to be removed On E reassembly ensure that the same type of screw is used M3x6mm The main printed circuit board can be removed after the two wires to SK2 composite video BNC socket have been disconnected Undo the Seven fixing screws and remove the circuit board from the case by sliding it forwards and then lifting it from the rear To reassemble Replace the main printed circuit board by putting the front edg
105. ountry The RF modulator must also be chosen to suit the 81 IC70 7415132 Note the cheaper 7 1 o p pin 3 fitted LS00 transition times 2 o p pin 6 forms collisions Input 5 inverts this gate buffers Its main purpose is to give clean TTL the notCTS signal u clock is not present 3 o p pin 8 gates to form notINT the CPU via IC34 ECONET interface 4 o p pin 13 in NotINT is the when collision detect is not used notRTS If th IC93 to giv Quad 2 input schmitt trigger NAND IC93 not fitted e collision det e a true level signals wit ECON ET only IC70 can ect circuit no colli sion ensures the signal the network NMI en ECONET verts notIRO from treated as an NMI by the system 81 sed always is notNMI to form IC81 to check for ne the networ able with th signal E alse if e true INT which is passed R56 is only needed on machines built without an IRQ This signal when enabled by signal be is signal th normal TTL twork to is IC69 NotINT is open drain o p so R59 is needed as a logic high pull up IC71 A 32Kbyte ROM 0 75Kbyte 1 0 the con BASIC ROM figuration high IC LCI 2
106. pins while equal amplitude th maximum 50mV displacement k square wave with an even he cassette recorder until ted by running the following IC85 These should Check that pins 2 and 3 of IC82 are wobbling Check that both IC82 and IC85 can be selec program 10 acia amp FEO8 20 serproc amp FE10 30 DIM P 100 40 50 start 60 LDA acia 70 LDA serproc 80 JMP start 90 100 CALL start Monitor the two chip selects pin 9 IC82 a be wobbling If one is fau lty then check the address decoding IC39 and the connections rom pin 5 and pin 6 nd pin 9 IC21 and 45 If the cassette fails to SAVE then SAVE a section of ROM and check that there is a synthesised sine wave signal from IC85 pin 27 of around 1 8V peak to peak If not then replace IC85 replace the LM324 89 b RS423 If there is then Use a PORT tester to verify that the RS423 is faulty One way of checking the operation of the RS423 is to connect the suspect microcomputer to a known working microcomput ports The connections must be made as follows er via their RS423 Din to Dout pin A to pin B Dout to Din pin B to pin A OV to OV pin C to pin C CTS to RTS pin D to pin E RTS to CTS pin E to pin D Once the two machines are connected switch on the power for both and configure the known working mic
107. r analogue in 21 7416138 3 to 8 line decoder This IC is enabled for address values amp FE page FE the Sheila L O Space It is enabled when A8 is low and A9 A15 are high The Sheila Space is decoded into 8 blocks of 16 bytes Each block is enabled when the corresponding decoder output is low LC22 741530 8 input NAND Detects address values of FC00 and greater It forms the first stage of the I O space address decoder logic LC23 741532 Quad 2 input OR 1 o p pin 3 gates notW with the notFDC enable address amp FE80 to form the disc control latch clock 2 o p pin 6 gates notINTOFF notSTATID with not2E to give a glitch free active low preset signal for the ECONET NML control latch 3 o p pin 8 gates the 2M clock with notVLDPROC to form CAS enable signal which can only be active high during CPU RAM access phi2 high 4 pin 11 gates notDEN with the latched D6 RAM data So D6 received by the teletext generator chip IC59 will be forced high during display blanking IC24 741504 Hex inverter Used for inverting various signals around the board IC25 7416109 Dual J notK flip flop i 1 o p pin 6 is a ip flop clocked at 2M and samples the 1M signal to form the internal 1E and notlE clocks 2 o p pin 10 is used as a state machine
108. red red 1 Introduction This manual is intended to provide the information required to diagnose and repair faults on the BBC Microcomputer Model B which was designed by ACORN Computers Ltd of Cambridge England The information contained in this manual is aimed at servic ngineers and ACORN dealers who will be servicing the BBC Microcomputer on behalf of ACORN Computers Ltd 2 ale p G g D 5 u f m T m D h V Packaging and installation isc Filing System User Guide and an Econet User Guid he microcomputer is supplied in a two part moulded polystyrene acking in a cardboard box Supplied with the microcomputer is a User uide an introductory cassette package a UHF TV uarantee registration card Disc and Econet versions also contain a lead and a he mains supply for UK models is 240V 50Hz The TE respectively nicrocomputer is this plug is Instructions for upplied with a moulded 13 amp square pin plug nsuitable then it must be cut off thrown away itting a replacement plug are given right at the front of this anual he microcomputer is turned on by a switch at the back of the icrocomputer next to the mains lead o not use the microcomputer in conditions of extreme heat cold umidity or dust or in places subject to vibration entilation under or behind the computer Ensure that no foreig
109. rocomputer to accept typing EX2 2 This command will cause the microcomputer to accept RS423 as input by input from both the keyboard and RS423 so keyboard commands will still work Now type the following BASIC program into the suspect microcomputer 10 FX3 5 20 REPEAT 30 PRINT U 40 UNTIL 0 This program configures the suspect microcomputer to give output to the RS423 and to the screen It then prints the character U whose ASC code is amp 55 amp 55 is a good number for testing it consists of alternating bits 01010101 RUN the program screen then the RS423 is working as a transmitter the RS423 becaus If the known working microcomputer starts printing etc across the If it works then go on to test it as a receiver If no output appears then test the suspect RS423 circuit as follows Check the Dout line either side of the driver pins 2 aud T5 of 95 Pin 2 should be oscillating at normal TTL logic levels V 5V Pin 15 should be oscillating in phase with pin 2 but at RS423 logic levels 5V 5V If pin 2 is active but 15 is not then replace the driver IC95 46 Check that receiving transmit data TXD th e SERPROC pins 26 and then it is 22 respectively likely that the SE of RPROC I Use the test
110. ruction Code BBC British Broadcasting Corporation BNC Bayonet Neill Concelman the type of bayonet connector used for the video output CA1 2 Control lines associated with the PA port on a VIA CAS Column Address Strobe control line for the DRAM CB1 2 Control lines associated with the PB port on a VIA CPU Central Processor Unit 6512 CR Capacitor Resistor network CRT Cathode Ray Tube CRTC Cathode Ray Tube Controller IC 6845 CSYNC Composite SYNChronisation pulse train for video TV display CTS Clear To Send control input on the 5423 port CUTS Computer Users Tape Standard DIN European standard connector family used for the cassette socket RGB socket etc DRAM Dynamic Random Access Memory EPROM Erasable Programmable Read Only Memory FIT Final Inspection Tester FDC Floppy Disc Controller 1770 or 8271 LC Integrated Circuit ID IDentity refers to the unique number of a given ECONET station or paged ROM IDC Insulation Displacement Connectors parallel cable connectors underneath the computer FEE488 A parallel interface usually associated with automatically controlled test instruments 1 0 Input Output IRQ Interrupt ReQuest control line on the 6512 processor MOS OS Machine Operating System or OS MPU Microprocessor Unit same as CPU NMI Non Maskable Interrupt control line on the 6512 processor PA Port A One of the two ports of a VIA PAL i A feature of the British television colour system where colour infor
111. ry Q8 and associated resistors may be faulty and possibly chrominance circuitry also see c A composite colour monitor can be used to test the video output with link 526 made If the composite colour monitor works in black and white only then the chrominance circuitry is aulty see c RGB works UHF works in black and white only Results the chrominance circuitry is faulty Test pin 3 of IC87 with a frequency counter Th measured frequency must be 17 7345MHz 400Hz and can be adjusted using If there is no signal on pin 3 scillator circuit formed by X2 010 and IC87 then check the o associated components IC79 is a 74874 741574 fail Check that there are signals in this position can cause the circuit to from pins 9 and 6 of 79 4 4336MHz and also a signal from pin 9 IC69 7 7kHz approximately Check that Ll has not gone open circuit and that C49 has not failed and check Q9 Failing all this check the logic circuit formed by ICs 83 86 87 and 90 and resistors R85 to R92 d The RGB picture is distorted Results either the DIN plug is incorrectly fitted to the monitor Socket or CSYNC must be inverted by altering S27 44 9 8 Cassette interface and RS423 xamined together becaus These two interf
112. s the 6 5 o p pins 6 and 8 form an R S latch for the 8271 disc con logic 0 data Printer user VI low signals required by the disc drive t NAND us time troller pulse then the data wi is received Also gives increased 8271 FDC only counted by IC2 This latch generates the data When the interval between data ndow latch is set pin 8 The data pulse always interval If the data pulse inverter to form t is 4us logic 1 data CMOS couni A This is a versatil int rf ac provides a CENTRONICS comp Handshaking is carried out 1 ACK input The called the User Port 11 7415374 Octal latch This 1MH peripherals B al adapter tible printer he positive going index ters used for disc speed timing or t interface buffered VIA it via ICS via CA2 half is IC latches the low address signals AO to A7 The main function of the 1 strobe output buffered connected directly to Pl in IC13 L10 and is These are used by tch is to buffer the lines only while 1E is inactive La but it also synchronises th low The TES2 2 7415245 Octal bi directional nes so that changes can occur tch is clocked by 1M see also a b
113. should start the LED on the front of the drive comes on Results if the drive fails to come on then test that pin 38 IC15 is high pin 10 IC8 low Results if pin 10 IC8 goes low then check the connection from IC8 to PL8 If pin 10 IC8 is high then first check that a DNFS ROM is fitted and is plugged in correctly Try fitting a good 8271 Then run the following program and check that the 8271 is being selected using an oscillosope on 5 pin 24 48 If the then see Check that the start up message indicates a 13 fdc amp FE80 20 100 30 40 start 50 LDA fdc 60 JMP start 70 80 CALL start uum drive does come on with SHIFT BREAK then insert a known good 80 track disc into drive 0 Use a disc which has a number of files on it and make sure that a write protect tab is fitted Shut the drive door Try CAT to get a catalogue of the disc If no catalogue appears then check that 7 is fitted West Check that notCS pulses low pin 24 IC15 If not then check decoder IC28 Check that after a BREAK a pulse occurs on pin 7 IC15 If not then check decoder IC28 Check that RDY pins 5 and 32 of IC15 are low If RDY is high then check 52 and for 2MHz at pin 3 IC15 If 2MHz is missing then link 56 is probably open circuit if 4MHz then 56 set incorrectly Check that index pulses are reaching IC3 pins 3 11
114. site video by making link 526 chroma to luminance is defined by C48 The voltage ratio of 21 5 6 3 UHF Red green and blue are summed by resistors R82 into Q6 to create a grey scaled luminance or R84 and R93 luma signal 012 D13 and D14 boost the luminance level for CSYNC respectively while 8139 and R146 trim the DC level of the video waveform fed to and fed Diodes colours to compress the grey scale Resistors R107 and R138 mix the luma and negative the UHF modulator Chroma is added through C49 The modulator generates an amplitude modulated UHF signal on TV channel E36 591 25MHz The chroma signal is an amplitude and phase modulated 4 4336MHz simulated sine wave which is added to the video colours white black grey the chroma amplitude signal For neutral is zero For other colours the phase of the chroma signal determines chroma amplitud fixes th colour strength The measured in the against referenc set the colour w by locking average colour burst A 17 734 475Hz 100Hz oscillator is generate the colour subcarrier master clock allows adjustment of the clock frequency Two D type registers form a ring counter which hile the chroma phase is to the used to generates two phase shifted 4 4336MHz signals 1C79 pins 6 9 11 chroma signals are
115. sses amp FE80 and amp FE83 Bytes of data transferred between the disc and the controller are processed using an NMI interrupt routine which demands immediate action from the CPU The interrupt program code accesses the 8271 at address amp FE84 this address is for DACK controlled transfers When a DACK controlled transfer is required the 8271 generates an interrupt by setting pin 11 high of IC15 The interrupt request is inverted by IC7 an open collector NAND gate to become notNMI NotNMI is a wire NUR signal which passes directly to the CPU notNMI input IC42 pin 6 via an AND gate 1C34 Address decoding for the disc controller is done by three ICs 22 8 goes low when the CPU address is greater than amp FC00 and so enables th is low for e th I O decoding logic IC21 generates address values amp FE80 to amp FE9F which spl address its IC28 pin the notFDC space into blocks 12 is low for amp FE80 to amp F address amp FE87 Pin for the 8271 disc controll er is held permanent 15 of IC28 Ly low interf signals ace timing is controlled by not2 from 20 NotDACK The final decode is by u of four notFDC signal which 28 E83 which is low sing the A2 is the notCl for amp FE84 to y E link S7 West as 8271 M through the notR and notW 9495 2 LO EDE
116. ster 47 9 10 Disc interface 8271 check all 61 North LINK S2 North PCB LINK S3 South PCB LINK 64 South LINK S6 South PCB LINK S7 West S8 open circuit Check that all 8271 disc upgrade section 6 links are in correct position for 8271 Lis ICs and passives are fitted and inserted correctly operation Use a PORT tester to check that the disc interface is the problem Check that a disc filing system ROM has been fitted eg DNFS filing system is stored in an that pin 27 is co make sure Connect a Turn the microcomputer on filing system ROM is present Acorn OS 64K Acorn DFS BAS C gt Results known working dual y E EPROM 80 track disc drive as opposed to a mask ROM nnected to 5V If the message does not report the Acorn DFS then check the IC socket by fitting a known good language ROM Check the DFS or DNFS Ram in another machine If both are OK then check the 8271 IC15 and the chip select logic check for correct data address RD and WR signals at 15 Check for 2MHz on pin 3 and for a reset pulse on pin 4 when break key used of 5 Press SHIFT and BREAK then release BREAK while holding SHIFT down Drive 0
117. stor across one pair of red and black leads them shorting ug the three black OV leads and purple 5V lead from the PCB a and tape the other leads with Turn on the power supply and tor using an oscilloscope The to peak WARN 1V with a maximum noise of 50mV get hot ts if any one pair measures zero If all are ou must be changed leave th Repeat the test with the other two pairs of red and black leads or a very low voltage then one t of spec then the power supply resistor and using the other ge Connect e of the CRT Connect one probe to 5V the other to When recon Set conne Turn lengt shoul 5V the purple lead T ite directions all the voltages are correct swi nect the black leads to the PCB o ctors on the PCB marked VCC a on the power sup h of time may heat up the PCB d draw from 1 5 to 2 2 dependin nd Repea three Resul look zero out unlik board the test after turning off the 5V connectors on the in tur Es for a broken lead then there is either a short circ likely or the whol power n connector trace on the oscilloscop ply just long enough if the current at any one connec or in place on the last measure th 5V both probes to OV and superimpose the traces in the and in across the resistor he two traces should deflect
118. synthesise In addition the track link at S29 should be cut mplete the ECONET upgrade the machine must be tested d ACORN ECON ET test kit r word PHROM and serial ROM socket i The following parts are required IC29 5220 IC37 6100 PHROM ROM socket cover ii Add component shown in figure 7 100n disc ceramic capacitor S other than 15 way single sided edgecard socket 2 off 10 right angle wafer plug 10 way connecting lead with sockets fitted 2 off ICs listed above to keyboard assembly as 31 10 WAY CONNECTING LEAD WITH SOCKETS 10 WAY RIGHT ANGLE WAFER PLUG md 15 WAY SINGLE SIDED ON v ERAS 0000000000000000 00000000000000 n DISC V NW 7 CERAMI em Gee eee e ei 200 NL IN N Figure 7 Keyboard assembly iii iv Test for continuity between the following connector in turn Edge connector pin number 6 7 8 9 10 11 12 13 Plug the other end of the ribbon cable into PL14 on the PCB points for each edge 14 IC37 pin number 13 4 5 6 7 10 11 13 14 Note on the edge connector pin 1 is nearest polarising key is pin 3 and pins 4 and 5 are Also check that there are no short circuits be connector pins Insert IC29
119. t details i The following items from the ECONET Hardware Upgrade Kit are required to upgrade model B OTY DESCRIPTION CIRCUIT REFERENCE 3 RESISTOR 1 0 0 25W 5 R63 73 148 1 RESISTOR 1 5 0 25W 5 R147 1 RESISTOR 4K7 0 25W 5 R59 4 RESISTOR 10K 0 25W 2 8140 141 142 143 1 RESISTOR 39K 0 25W 5 R64 4 RESISTOR 100 0 25W 2 8106 110 125 134 RESISTOR 220 0 25W 5 R77 2 RESISTOR 1 5 0 25W 5 R78 79 1 RESISTOR PACK 8 x 22K RP2 1 CAPACITOR 10 6V3 TANT Cay 1 47 10 ES 1 CAPACITOR 2n2 CER PL 2 C26 1 C 68B54 1C81 1 75159 91 1 IC 7415123 88 1 7415132 70 1 7415244 IC80 1 IC LM319 IC92 1 SOCKET DIN 5 PIN 180 DEGREE SK7 2 CONNECTOR 8 WAY WAFER 523 7 SHUNT FOR 523 2 SOCKET 14 PIN DIL FOR IC91 92 1 SOCKET 28 PINDIL FOR IC81 OPTION 1 CONNECTING LEAD ECONET 1 Current network filing system ROM eg DNFS IMPORTANT NOTE model ECONET upgrade It has tests that this feature is not operating within an ACORN ECONET required where an ECONET include the ACORN NFS software a Collision detect circuitry is not been found required when a environment machine is used with equipment which does not included in the following exhaustive BBC Microcomputer is However it may be nd provision is made for this circuitry to be fitted to the PCI ii If coll
120. t when there is no second or powered on processor present 23 Sil ECON 1081 is based around the 68 performs the conversions bel B54 C81 generates th transfer betw network and CPU n can be disabled half of 69 address returns the station ID number which is set nabled when pin Z2 23 In which Transmit circuit cable ICIL terrupts ar when cloc data from and The differe by making pin 4 TO23 tween serial and parallel interrupt requests which are connected is requested by an low thereby setting ked by not2E the 68B54 th nti al monostable half IC9j of IC88 is used en through 5 7 on drive voltages are which is achieved by a read of GFE advanced data link co Ex ntroller data and Each byte nterrupts the D type 8 Reading this to NM NM is fed to a differential IC69 goes low resets the D type up on the links line driver to the twis typically ted pair network 0 the F to time out ET line driver by taking pin 9 low after approximately 4 5s required to transmit a maximum length data packet longer than the time This is designed to
121. ted bu EAK a ET BREAK then insert a known good 80 which has a number of files on it tab is fitted Shut the drive door of the disc If no catalogue appears then If an incorrect catalogue is obtained This fault is unlikely if the disc likely after an upgrade hip select notCS pulse occurs on pin 1 then check decoder IC28 notRD 19 IC16 tor read data on pin or The data should be negative going pulses of If not then check connections to 8 Replace 1770 9 11 Prin ter port Use PORT tester to check that the printer port is faulty Test the VIA IC10 by writing values to it and testing the outputs First configure all the data lines as outputs by writing amp FF to the data direction register A DDRA T amp FE63 amp FF Then write amp 00 to the output register amp FE61 amp 00 11 the data lines to the printer connector PL9 should now be low pins 3 5 7 9 11 13 15 and 17 If they are not all zero then check them at the VIA itself pins 2 3 4 5 6 7 8 and 9 of IC10 If these are all low then the buffer 105 is faulty Otherwise check for open circuit tracks on data lines on both the printer side and the CPU side of the VI A Now write amp FF to the outpu amp FE61 amp FF 11 the data lines to the pri pins 3 5 7 9 11 13 15 and 17 itself
122. to give load independant output stability freedom from parasitic oscillation 78 6845 CRTC controller The CRTC is responsible for all VDU address generation It is programmable device which once set up independantly generates th RAM address sequence for a wide range of display formats The IC can Scroll the display by responding to a change in the value of the display start address A programmable cursor and the horizontal and vertical sync pulses are also generated by this IC Included in the IC is an address latch which is used with the light pen input to save the character address at the time of a trigger event on pin 3 of the The device is accessed at 1MHz by the CPU at amp FE00 1 A character clock of 1 or 2MHz is supplied by the VIDPROC depending on the VDU mode IC79 74874 Dual schottky D type flip flop The two parts of this IC are used in a ring counter which is clocked at four times the colour subcarrier frequency 17 734475MHz Each D type generates an output at the colour subcarrier frequency 4 43361875MHz The two signals are in phase quadrature 90 degrees apart and form the master signals for the PAL chroma encoding logic The signal on pin 8 is set to 4 4336MHz 100Hz by adjustment of IC80 7415244 Octal 3 state buffer The 8 buffers in this IC are used to driv
123. to process 1 MHz cycle requests When 10 is high it holds phi2 high until phi2 and 1E syncronise LC26 74504 Hex inverter Three parts are used in a ring of two plus buffer 16 MHz oscillator The remaining thr are used where inversion is needed on time critical signals 74 27 741500 1 o p pin 3 is syncronous read frtrted Quad NAND used to ga nable used by the used to ga te 2M wi te 2M with R notW ADC and 8271 disc controller to form notR a if th notR W to form notW a syncronous write signal used by the ADC and the 8271 disc controller 2 o p pin 6 is if fitted 3 master reset 4 28 7415139 o p pin 11 is a spare gate o p pin 8 is used as an inverter to generate notRS Dual 2 to 4 lin decoder the system Inputs are tied to 45 1 o p pins 10 and 12 split the FDC address space into two parts Uses A2 and notFDC so that o p 10 is low for address values FE84 to amp FE87 and o p 12 is low for amp FE80 to amp FE83 The o p s repeat in blocks of 4 up to address amp FE9F When 57 is East 1770 disc controller 2M is used to enable the device o p s so the enable signals are effectively synchronous with phi2 2 o p pins 4 5 and 6 decode the I O pages FRED JIM
124. tput 15 signals 10 obtained by mixing luminance and then feeding the result chrominance and SYNC to a UHF modulator Serial input output is provided by the cassette port and RS423 port adapter IC82 and a ULA c Both are controlled by the 6850 asynchronous communications interface alled the serial processor 85 Analogue input is fed to the four channel 10 bit ADC chip IC84 A local area network facility is provided by the ECONET circuitry centred on the 68B54 advan ced data link controller IC81 Two build options are available for the floppy disc circuitry One is based on the 8271 floppy disc controller 5 as used on all BBC Microcomputers issues 1 to 7 The second option is based on the 1770 floppy options density decisio disc controller IC16 Some components are common to both MFM mode and n logic The 1770 than the 8271 controller require The 1770 operates in either single density FM or double includes a data separator and disc speed controller interface is therefore simpler interface ICs 1 2 3 4 and 9 are not d with a 1770 The CENTRONICS compatible port of a 6522 versatil sent to The Use printer interface based on half the interface adapter IC10 IC5 buffers data the printer
125. uffer Used to buffer the 8 data lines from the Data direction is control expansion bus Signal 72 data bus to the 1MHz led by the de glitched R notW IC13 7415244 Octal buffer Used to buffer five address lines AO A4 R notW and not2M for the TUBE interface Also buffers the strobe handshake line for the CENTRONICS compatible printer interface 14 7415245 Octal bi directional buffer Used to buffer 8 data lines from the data bus to the TUBE interface Is enabled only when TUBE is addressed 5 8271 FM floppy disc controller 8271 FDC only Driven by the ACORN disc filing system software FM single density recording to control 40 track or 80 track disc drives Note the disc interface be changed for 8 inch drive operation IC16 1770 FM MFM floppy disc controller 1770 FDC only Driven by either the ACORN 1770 disc filing system software for FM single density recording or by the ACORN advanced disc filing system software for MFM double density recording to control 40 track or 80 track 5 25 inch disc drives or any compatible alternative The 1770 disc controller cannot be used in conjunction with 8 disc drives IC17 7415174 Hex D type 1770 FDC only This hex D type latch is used for the disc control signals not generated by the 1770 Motor on off two drive select signals and one si
126. ur though not our as the coloured insert in turers plugs and fuse carriers In the event o ST NOT be used Either f loss of the fuse carrier the replace the moulded plug with plug wired as from an author ot suitabl detailed below or obtain a ised ACORN dealer In the event after clearing any faults 51362 for the plug supplied the plug should be cut as previously noted off and The mould disposed of as it woul ld be a po the ed plug which was plugged in with the cut off end As the colours of the wires may if appropriate plug fitted and wired cut off mus t be tial shock hazard the mains cord exposed it were to be not correspond with the coloured markings identifying the termin The wire which als in your plug proceed as follows is coloured green and yellow must be connected to the terminal in the earth symbol plug which is marked by the letter E by the safety or coloured either gr The wire which is coloured blue must which is marked The wire which with the letter N or col n or green and yellow be connected to the terminal oured black which is marked with the letter L or c is coloured brown must be connected to the terminal olou
127. ve the 12K paged RAM from l BO allocated as standard it is BASIC if 51 3 If the ROM selected by DO D3 11 also appear in the memory 00 amp BFFF As ROM 0 is not is changed writing 128 to the ROM select latch will merely place Es memory map and amp B000 amp BFFF will be vacan 5 4 3 RAM access There is 64K of installed RAM the 12K paged RAM into the RAM access is dependent on whether the computer is in normal mode or shadow mode and the differences are shown in Figure 5 16 PAL C36 64K CPUSEL 1 CPUSEL O 32K 20K 44 NORMAL SHADOW NORMAL RAM RAM RAM Figure 5 RAM access in normal and shadow modes In normal mode the RAM can be thought of as 44K from address 50000 amp AFFF The top 12K of this RAM from address amp 8000 amp AFFF is paged into the memory map when required in place of the bottom 12K of the Sideways ROM space see 5 4 2 The remaining 20K of RAM is set aside for the shadow screen memory while it always exists it is not available to the system in normal mode The bank of 44K RAM we shall call normal RAM In normal mode VDUSEL IC36 pin 17 is always zero Any code executing anywhere within normal RAM in normal mode will always access normal RAM it cannot access shadow RAM 17 amp AFFF we shall cal In shadow mode the shado RAM is amp 30

BBC Microcomputer Service Manual Oct 1985 Section 2 BBC Micro

Contents

Download Pdf Manuals

Related Search

Related Contents