Home

Service Manual

Contents

1. Figure 3 1 2 Detailed Block Diagram of Ericsson DB 2000 24 3 Technical Brief B CPU Hardware Subsystem The CPU subsystem incorporates CPU Sub chip Backplane JTAG DMA Controller System Buffer RAM Boot ROM External Memory Interface EMIF for connection to external SRAM and Flash memories The bus architecture is built on the ARM AMBA standard with multi layer AHB Advanced High speed Bus and APB Advanced Peripheral Bus for the peripheral buses There are two AHB busses the CPU AHB and the DMA AHB Clocks to the CPU subsystem are distributed from the system control SYSCON backplane clocking The reset lines are all asynchronously asse
2. 10 11 12 3 8 8 1741 27K A KEY_LED_ONOFF FLASH A opem d vs vean 12 CPO LTC FLASH m E gt pg x E a B AO 3 E CPO LTC FLASH 1 A cm 22u A 2 LTC z 5 R738 1 LcDBL Sjo 3 24 R726 0 lt CIRES N MEGA FL704 a le 9 85 777 4 23 EN I LED 8 ma 2 1 our I2CCLK MEGA 5 Cibi 8 wal off lt mour asla I2CDAT MEGA 7 55555 44 o 2 mout SYSCLKI lt 2 4 our 018 8 mour 2 Keypad Backlight Control rds NEK2ISUISTKTAGSL FL w o
3. 10 11 12 vexris vexis w vean VCAM 28v vean 28v vean VCAM 18V voi vexris vois A A VDIG veat A 377 VBT VTF R502 R2237 n2238 cs RIT 8526 o 1 gt 5 R503 0 1 5 100P yusB pas A 21 00 vour 2 N502 N702 PWRRSTn gt OFF I 100K E E vour usto 12186 CAM28 EN 0 pae our our 777 CAM18 GND R2175 cen R504 z karqaku RATER 2 2 VBUS gt vour gt BTF_REG_EN 4 I p d 70 470 T0 47u R507 H is R514 100K s 1608 Ma s15 3 2239 R2177 1899 R1131N281DS TR F C1915 100K 1608 1608 gt USBSENSE inc 777 777 0512 AAT3218IGV 1 5 T1 csi 513 1917 AAT3218IGV 1 5 T1 16 1918 224 Bud 159 77 qu n Toon 1608 MEGA 2 8V Camera Analog Power VGA 2 8V Camera Analog Power C w 1608 1608 1 8V Camera power l p a 7 3 3V
4. 02 z 5 LEBE SiaH 0 8 p gt 85 5 LEBB S14H 9 515 125 219 s G 48 4 47 2 5 2 gt 4 CID3 05 2 490 CID7 10 2 4 IND SINK 11 40 SYSCLK1 14 o 37 12 DAT 15 36 12C_CLK 16 35 CIVSYNC 34 CIHSYNC 18 o0 33 CiPCLK gt 18 Saz 5 201 2 2131 DCIN 3 21 o 30 22 29 KEYIN2 23 28 24 27 LTC LCDBL 6 250 94 AXK8L50125BG LEFT HEADER Rig 10 IL Ri n o G ve 4 77 CENTER DL lt RIGHT 71 Lk m AXK720145G Fae p 777 LIF VGA Camera Connector Figure 3 2 5 Main Board to LCD FPCB Connector 50pin FPCB FPCB to VGA camera Connector 20pin FPCB 47 The 1 3M Camera module is connected to main board AXK7L26227 with Camera FPCB AXK8L26125 The VGA Camera module is connected to main board AXK7L50227 with Camera amp LCD FPCB AXK8L50125 1 3M Camera module is connected to FPCB with 24 pin Board to Board connector 14 5602 024 000 829 1 3M Camera VGA Camera module is connected to FPCB with 20 pin Board to Board connector AXK720145 VGA Camera Its interface is dedicated camer
5. 10 11 12 221 TMXU753 777 E 777 Lena 2200 C220 20 12 1207 B 10008 1608 1 gt 0 01u C229 1 gt 0 01u 228 Lez gt RXIA Tz 0 01u C226 T gt RXIB ps R201 caos A gt MCLK I 5 1 1208 1202 Tuh c221 Ten ji c 223 opiu 0010 L201 R202 777 cais 19 P 22 1 2p 1 1 AN VCXOCONT E 1 1K leno C25 498 mna di Em 27 58 81 irours 810 B201 pevse o2w NA vecux 616 RM MIXINA e rie 4 E tia vecaus Ji 33 D onosias IFLOA 510 13 em can SIIGNDEME IFLOB 910 a WCDMA RX gt P3 1 127 108 5323 GNDRPLO 22 T GNDBYP RFLOOA Kl vecrr 25 77 sl 08 77 m 93 DATA GNDREF 1203 GNDBUS 5 lt IFLO Y Y STROBE REFON SM _ lt IFLOBAR m 5 EK a 8855855592525069 gt RFLO 32 HEEHRHEHHEHEHEH T3 24 SEZESEEZEEE 7 C239 22p JH gt RFLOBAR gt SAFEH2G 4FAOFOOROS 777 gt 22 R221 if AA lt VDD_B
6. VBATI x R32 100K 5 D D 9 D D D i i i D o m m m PGOSDBTFC a a m m m Yves Vas Wak VAE Vie yes yas VES VES VED ves VES a Or aa Yas a a a E x x gt aag x x gt gt x x E E xm E E E E R33 100K _ mim wo e 258758 858 8 8 558 558 453 45 8 45 8 258 15 8 25 8 c lt tSr Se c tor esr ese R34 100K PGOSDBTFC KEY LED lt Y Figure 3 2 12 Keypad Backlight Circuit 53 3 Technical Brief r 3 3 LCD Module 40pin BtoB 50pin BtoB Connector Connector Camera amp LCD FPCB 20pin BtoB Connector Figure 3 3 1 LCD Module Block Diagram Figure 3 3 2 LCD Module Main amp Sub LCD 54 3 Technical Brief 3 4 Analog Baseband ABB Processor 3 4 1 Overview of Audio path MARITA Digital Baseband ASIC Voice Call RX Videp Telephony RX VINCENNE Audio and Power Management ASIC Receiver MIDI or WAVE C MIC lt lt O HEADSET AMP Voice Call TX HEADSET Videp Telephony TX 0 Analog S W Speaker AUDIO AMP Speaker Figure 3 4 1 Audio Path Block Diagram 55 3 Technical Brief 3 4 2 Audio Signal Processing amp Interface Audio signal processing is divided Uplink p
7. B201 3 Figure 4 17 2 Test Point Crystal Part C231 C230 R216 R212 lt VCXOCONT 47p 330p 10K 1K _Lc234 6232 R214 2 7p 4 7p v201 ZNBBY58 02W NA 1 2 C233 7 13MHz 56p B201 77 77 Figure 4 17 3 Schematic of the Crystal Part Run Sample Waki Lb tepedanmce C1 Mean 1 785 v rie AC A Low signal 4 m 2 amplio U UA A A 4 24 NE ONES 2 2249 5 4 I ETT M Mm Chl N andit Offset Desk ess Prode 146 dir ov 0 Functions Figure 4 17 4 13MHz at B201 3 141 4 TROUBLE SHOOTING Check 2 13MHz at TX part N304 B1 N304 C1 C331 C332 22 0 01u 77 TP303 TP304 TP305 1 mre is A4 N304 B1 N304 C1 Figure 4 17 6 Schematic of the Tx Part Run 500MS s Sample Chi Coupling Impedance C1 Mean 1 647 V D Freq i 12 99552M H2 AC v 4 Low signal litude 4 500 M Toons Chi X 620mV Q 50 Bandwidth scale position Deskew Probe Full pom 3 46 div 0s Functions Figure 4 17 7 13MHz at N304 B1 C1
8. cur case cao ootu Sp esop Fep Foou 77 77 77 H H Engineer LG ELECTRONICS INC Drawn Mobile Handsets R amp D Center JS Joo HW Group Development Lab 6 R amp D CHK TITLE ore U8550 spfy0106301 1 1 LE GSM DCS INGELA MEG CHK Page 4 of 7 RF Part 4 of 4 Changed by Date Changed Time Changed REV Drawing Number 5 doo 2004 May 16 7 25 06 pm 9 10 11 12 232 8 CIRCUIT DIAGRAM
9. Figure 4 21 4 GSM DCS PCS Tx Level at 1 Test Program Script 1 GSM Tx 2 DCS Tx 3 PCS Tx MODE 0 MODE 2 MODE 1 SWTX 1 64 5 1024 1 SWTX 1 699 0 1024 1 SWTX 1 661 0 1024 1 v Agilent 8960 Setting GSM BCH TCH Mode v Oscilloscope Setting Check GSM DCS PCS output power at Check if there is any Major difference No Refer to Figure 4 21 4 GSM gt 32dBm DCS gt 29dBm Ves PCS gt 29dBm GSM DCS PCS Tx path OK See Chapter 4 21 6 to check Rx path See Next page to check Tx path 170 4 TROUBLE SHOOTING NENNEN 5 Fa C GSM RF Transceiver IN OUT Signal Check DCS PCS Tx GSM Tx 8414 418 MODA R410 GSM Tx MODB T L406 2 R411 MODC R424 DCS PCS Tx MODD 1405 R423 404 LDB21897M15C R418 um 0 5 8 88 419 4 4 C429 1404 75 ILM15BB750SN1J L403 MODA gt _ 25 22 gt MODC gt 477 82283555555 Hluzzusamiuamcomgs sxsr gt MODD gt K 80225998225 Nos Tg MODA 2 RFHC 22 MODB 5 GNDRF Hag RFLB j RFLA 5 VCCPLL 405 VCCRF LZT 108 5325
10. maximum 2 maximum 3 Hom can lt lt lt Figure 4 19 7 WCDMA Mode No Each Mode Logic OK Yes Input Signal and Power to Check MARITA D601 Antenna Switch Block is OK See the Next Page 152 4 TROUBLE SHOOTING EE a 4 20 Checking WCDMA Block 1 Check VCXO Block 2 Check Ant SW Module Bottom View RF TX Level 6 Check RX IQ Top View Redownload SW Cal 153 4 TROUBLE SHOOTING 4 20 1 Checking VCXO Block Refer to 4 17 4 20 2 Checking Ant SW module Refer to 4 18 4 20 3 Checking Control Signal First of all you have to check control signal data clk strobe TP203 CLK TP202 DATA TP201 STROBE IIT 81 CT ceux Dr miana ET mnan apenas T em WCDMA RX gt 1 xam MUS tries AS cca a um Ej seni 777 11 5 9 FL201 Ce sAFEH2CI4FAOFGOROS 777 E 22p ji 777 1206 m R206 _Le216 TP202 TP203 Tw GPRFCTRL lt CLKREQ gt FROM MARITA SIDE FOR POWER SAVING Figure 4 20 2 Schematic Control Signal 154 4 TROUBLE SHOOTING BENE 22995 1 Seii TP201 STROBE
11. Does the sine wave appear at C584 C585 Change the U507 If the sine wave doesn t appear Does the sine wave appear at C592 C593 Change the U509 Resolder CN502 Pins or change the Headset Can you hear sine wave out of the receiver Change the main B d 125 4 TROUBLE SHOOTING 4 12 5 Headset MIC Voice call Video Telephony Insert Headset Does the Headset icon display on the main LCD Does the level of R2252 under 0 5Volt Check the signal level at R569 at the putting Audio signal in MIC Change the main B d Resolder C554 569 and try again If fail again Change the main B d A few hundred of mV of the signal measured at C575 Change the main B d Does it work properly Try again from the start 126 4 12 6 Headset 4 TROUBLE SHOOTING ia 127 4 TROUBLE SHOOTING 4 13 Charger Trouble GPA12 C532 1u D9 GPA13 7 E2 DCIN gt CHSENSE CHSENSE Q501 DCIN2 lt TV SI7411DN T1 E3 D2 D1 FGSENSE 53 52 S1 06 D5 04 03 2 R875 845 R847 6 85 a a FGSENSE D7 C599 C548 VSS B 10p 10p 55 VBATI VBAT
12. 201 4 19 1 Mode Logic by TP Command 146 201 4 19 2 Checking Switch Block 7 3 2 Calibration 5 201 SOUTICO ione 148 7 3 3 EGSM 900 Calibration Items 202 4 20 Checking WCDMA Block 153 7 3 4 DCS 1800 Calibration Items 207 7 3 5 WCDMA Calibration Items 210 7 3 6 Baseband Calibration Item 218 7 4 Program Operation 219 7 4 1 XCALMON Program Overview 219 7 4 2 XCALMON Icon Description 220 7 4 3 Calibration Procedure 223 7 4 4 Calibration Result Message 225 8 Circuit Diagram 229 9 pcb layout 239 10 EXPLODED VIEW amp REPLACEMENT PART LIST 248 10 1 EXPLODED 248 10 2 Replacement Parts Mechanic 251 Main component 255 10 3 282 Table Of Contents 1 INTRODUCTION 1 INTRODUCTION 1 1 Purpose This manual provides the information necessary to repair calibration description and download the features of this model 1 2 Regulatory Information A Security Toll fraud the unauthorized use of telecommunications system by an unauthorized part for example persons other than your
13. GNDRF2 m GNDIFPHD 55 1 un WDAT fae 5 5 pa NON 56r6869929865 WSTR mai 824822222252 9 C328 1310 D mai maie 7 680 Rata M Losa Leas V wivi BX NA 150p 3300p Engineer LG ELECTRONICS INC Brawn Mobile Handsets R amp D Center 26420 HW Group Development Lab 6 CHK mE Size DOCCTRLCHK U8550 spfy0106301 1 1 UMTS WIVI to ISOLATOR 1218A p Page 3 of 7 RF Part 3 of 4 Changed by Date Changed Time Changed Drawing Number SG Kang 2004 May 16 02 pm _ e i E nm 8 CIRCUIT DIAGRAM 10 11 12 vean A A 1401 NFM21PC105B1A3 iw 2 T T T T caza caza d 10u 22p 2012 2012
14. lt lt ans mas PASENSE lt BLMISABGDISNIJ 1401 PAREG gt C401 01 C402 IOUT 1 2 vois TPan TP403 9 7 _ I2CDAT 93 S I2CCLK mE accu anar 25 QDATA c SYSCLK2 SYSCLK2 MCLK IDATA c RESOUT3n RESETON RESETB DCLK DCLK K VDD_A cas caos cas AT mB e 22 AS is A3 lans 5 777 id RXON gt RXSTR BEARN 15 HE z 77 Pemut 10821897 15 5 88 mate Ecco gt VDIG_HERTA NA 5 E mce ww T i 8 E S cm GSM TX lt lt our DCS PCS IN End 9 t 88 DACO2 55 Joo Fra MEL k dp 28 55 Dacos DCS TX A M pes Pcs our IN 4 ore Zant 9 9 838 DM T lt pcs Rx cs c2 777 P War TX ENABLE Hi 42 d C8 pacer 2 NA 13 Jasvo ss 5 M 3 faas pacoar 9 2 77 95823885 2 bd 5477 29222228 DEC 25555555 DEC2 777 5 pemeLK DEC3 HS G8 PCMSYN Lons cas ADSTR Decs C413 T0 098u 415 0 068 7 T L 1508211680206 7 REXT 00
15. p lac VGA Teen CAM28 VGA EN 2 gt 79 CIRES N Grioos IRQ0n HS AMP EN 1006 Ds D 6 07 04 Avoa UARTAXO X 55 UARTTO a AUDIO EN Grot D7 ix HS SPK SEL V5 Gros ui m be S PULSESKIP gt we 6715 D10 MEM CS0 N a 2 e on MEM 1 N Ft cE MEGA en lt lt d EN s ose D14 00 619 67022 oot 015 1K M 15 MEM N pics UART3 UARTTX3 9 apio2s D751668A1ZZG MARITA MEM CS1 N EUSYO211101 UARTCTS3 GPIO26 CS2 N MEM CS2 N P MODE CRE Forthe Bluetooth W241 MEM CS3 N Ms 078 wen 68 MEM WE N MEM war EN GPIO31 OEN MEM OE N E wis 6 033 E5 REG EN 5 GPo34 MEMADV 89 MEM ADV ADV ADV pasa 199 2 voci 88 3D CTRL2 amp T 621036 MEMWAIT amp MEM WAIT N MEM OE F2 VCC2 TF DETECT 720 USBSENSE LB pd PoiRES N Lconesx on M 88 Grios LCDCSX SUB F1 AX LCDWRX LCD A A MEM
16. 1 531 V 1 ms pwns N Cni ONNN 3 lt lt lt lt 77 1 DC 2 16 V H oFF 1 evts ns 13 0 Mkz Ex Sx Sx Sx Figure 4 21 9 Herta IQ data and DCLK leCroy 2 t 3 T Dav HE 5 T Time 588 ps 1 DC 1 38 V 1 evts Figure 4 21 10 Ingela IQ signal 31 0 03 18 01 88 19 ps 4 100 HI AAA 2 ua 18 ps y y V 180 Ht 2 188 ps 1 sweeps average low high sigma pkpk 1 gt 203mV 283 203 200 857 kHz 197 616 205 023 1 680 pkpk 2 203mV 203 203 Freq 2 200 802 kHz 197 299 204 186 1 665 18 ps 0 mv 2 10 mv 3 20 mv DC 1 DC 1 300 V 428 mV 0 m 1 evts 0 Figure 4 21 11 Ingela IQ signal 178 25 5 5 STOPPED 258 kS s STOPPED v Agilent 8960 Setting CW Mode GSM 50dBm Ch65 948MHz DCS 50dBm Ch700 1842 8MHz PCS 50dBm ch700 1889 0MHz v Oscilloscope Setting Check GSM DCS PCS Rx IQ data at 1 Check if there is any Major difference Refer to Graph 4 21 9 Check GSM DCS PCS signal level at 2 Refer to Graph 4 21 10 No Redownload SW Cal Yes
17. 40 3113 Keypad edes 41 3 2 GAM Hardware Subsystem 43 3 2 1 General Description 43 3 2 2 Block Description 44 3 2 3 Camera amp Camera FPC Interface 46 3 2 4 Camera Regulator 49 3 2 5 Display amp LCD FPC Interface 50 3 2 6 Main amp Sub LCD Backlight Illumination 52 3 2 7 Camera Flash LED Illumination 52 3 2 8 Keypad Illumination 53 3 3 LCD 54 3 4 Analog Baseband ABB Processor 55 3 4 1 Overview of Audio 55 3 4 2 Audio Signal Processing 2 56 3 4 3 Audio 58 3 4 4 Voice 59 3 4 5 MIDI Ring Tone Play 62 3 4 6 Audio Player 63 3 4 7 Video Telephony 64 3 4 8 Audio Part Main Components 65 3 4 9 GPADC General Purpose ADC and AUTOAD C2 67 3 4 10 Charger Control 68 3 4 11 Fuel Gauge 69 3 4 12 Battery Temperature 70 3 4 13 Charging 71 3 5 Voltage Regulation 74 3 5 1 Internal Regulation 74 3 5 2 External Reg
18. dr 2 IFLOBUFQ IFLO BIAS CIRCUITS Figure 3 8 1 Block diagram of the IFLO section 85 3 Technical Brief B RFLO Section The VCO is a fully integrated balanced LC oscillator with on chip resonator An on chip varactor is used to control the frequency over the desired tuning range A separate external voltage regulator supplies the VCO with power to avoid frequency pushing and up conversion of low frequency noise A separate ground pin is also used as varactor ground reference to prevent DC voltage drop changes from affecting the VCO frequency Via the serial interface the VTUNE voltage can be set to VCC 2 to check the center frequency of the VCO The PLL consists of a programmable prescaler with multiple division ratios and a phase and frequency detector with a charge pump with programmable output current Channel frequency selection is set via the serial interface VCCVCO 9 5 __ RFVCO GNDVCO V VTUNE GNDTUNE gt VCCPHD MM RFLOO GNDPHD PHDOUT N div From XO R DIVIDER div GNDPLL BIAS CIRCUITS Figure 3 8 2 Block diagram of the RFLO section 86 3 Technical Brief C Reference Section The reference block consists of a balanced oscillator and a buffer amplifier The crystal unit and the feedback capacitors are external
19. 875 0000280 100 ohm 1 16W J 1005 R TP RES CHIP ERHYO0008601 10 05 ohm 1 4W J 2012 R TP ERE HIP ERHY0008601 0 05 ohm 1 4W J 2012 R TP 878 899 0501 0503 0506 ERI RES CHIP 0008602 0 1 ohm 1 4W J 2012 R TP IC EUSY0232802 0 23 5 5 PIN R TP 2 8V 150mA LDO IC EUSY0232802 0 23 5 5 PIN R TP 2 8V 150mA LDO SOT23 5 5 PIN R TP 150mA 2 4 80dB LDO PBFREE EUSY0275401 HY0000280 100 ohm 1 16W J 1005 R TP 270 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark 6 U510 U604 05 0232815 SOT23 5 5 PIN R TP 2 85V 300mA LDO PBFREE HVQFN 52 PIN R TP BLUETOOTH RADIO MODULE WITH BASEBAND CONTROLLER Pb free 05 0188103 24 PIN R TP MAIN FLASH UPTO400mAcontinuous 6 6 U701 6 201 501 DIODE TVS EDTY0007001 SOT23 6 9 V W R TP TVS DIODE ARRAY ODE VARIABLE CAP ODE SWITCHING EDVY0001801 SCD80 0 09 pF R TP 2 30 V 1 VF 1 5V IF 200mA EDSY0011901 o 30UA VR 10V 6 6 502 6 503 ODE SWITCHING 6 V701 DIODE TVS EDTY0006401 SC70 6L 5 V 100 W R TP PB FREE CONN RF SWITCH EMD2 30 V 1 A R TP VF 1 5V IF 200mA EDSY0011901 IR 30uA VR 10V ENWYO0003301 SMD 0 4 dB 6 W101 6 X502 CONN SOCKET 8 P
20. 10 200404029 FS Rec Kaly ssw 19271 S Ww vOSDB UBI 10 V09OB 2004040298100 phone wcc 11404 Remove Download All LGE GDFS map flash file Addi There are no flash fles to download into the target Log Messages Bytes sent to phone 7284 Prologue response Prologue done EbS Loading loader please wait Bytes sent to phone 47604 Payload response EdQ End time Thursday April 08 2004 23 48 07 Elapsed time 00 00 05 Error occurred during port chango 19 Model 3127 95232 v 0 44115200 8 1 197 6 DOWNLOAD 1 0 0 cn 6 3 1 U8XXX Download 6 Connect amp Download Progress Bar is running while downloading FlashRW for 08120 Version 4 0 0 Build 100 1 1 Global Serinas LG Electronics Inc G Handsets Lab LGE Signed Software ssw ilash tiles Pathname Size 0518100 5 ww VOSDBUS 10 20040407 drive media sew 3671 KB D 98100 S WH VOSUB US 10 V09OB 20040409 Birive c ssw 10488 KB Remove D 98100 5 WY VO9DB US 10 v090B 20040402 D WU8100_S WW VOSDB WUBI 10_ 090 20040402 S Rec Haly ssw 19271 6100_phone_wee 11404 Remove All c Dowrlgad LGE GDFS Addroce 0x22690000 Data longth 65536 Elapsed time 00 01 51 Log Messages Loader version inform
21. 9 1206 3 NA zz 208 R220 sans Tease Teas 8 55K pe 0 01u a TP202 TP203 201 390p 9 WDAT gt m209 y Y gt WRFLOOP F WCLK WSTR gt 5600 R207 GPRFCTRL lt n208 CLKREQ gt gt AN 100 FROM MARITA SIDE FOR POWER SAVING Engineer H Es LG ELECTRONICS INC Drawn by Mobilehandsets R amp D Center HW Group Development Lab 6 R amp D CHK TE E DOCCTRLCHK U8550 spfy0106301 1 1 UMTS RX WOPY 218A CHI Page 2 of 7 RF Part 2 of 4 Changed by Date Changed Time Changed CHK REV Drawing Number Page 56 Kang 2004 16 12 50 11 2 3 4 5 6 8 9 10 11 12 230 8 CIRCUIT DIAGRAM 231 10 11 12 WCDMA amp ES 8888 7 556 58 Z G G ESIaEARI 950G01 T Li 777 vean VCCWPA gt 2 Naot WDCDCREF gt RF9266 LM
22. Fig 4 20 7 Output Level at FL102 C111 Fig 4 20 8 Output Level at Isolator Output N303 Out Tieasurement Instrument Screen Measurement Instrument Screen Control Thermal I I Contro Thermal Power Pouer Cell Pouer Thermal Pouer 7500 Thermal Pouer 75 00 Thermal Pouer dBm 3 8u HHZ zi NN Thermal Pouer dBn 3 8u 17 15 um Channel 5 99 Channel Type 12 2k 12 2k Paging Service Paging Service RB Test Continuous Continuous RB Test Node DL Channel 10700 5 88 2 96 2 39 55 47 DL Channel 52 01 41 16 0 22 51 38 10700 Uplink Channel Uplink Channel Suap Hindou 9750 Suap Window Positions px rers 3750 10 5 fc 5 1 E m Background Active Cell E3Backoround active Cell Sus Type UTRA FDD Idle Idle 10f2 inthef Offset 1of3 1of2 Offset L 1073 Fig 4 20 9 Output Level at Isolator Input Fig 4 20 10 Output Level at PAM Input N303 In N302 C307 Neasurement Instrument Screen rj
23. 0000201 0 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP RHY0000201 0 ohm 1 16W J 1005 R TP eee pm pem R25 RES CHIP 0000233 470 ohm 1 16W J 1005 R TP R27 RES CH 0000233 470 ohm 1 16W J 1005 R TP 0000233 470 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 500 523 5 240 W R TP SINGLE LINE TVS DIODE FOR DIODE TVS EDTY0007301 ESD DIODE TVS EDTY0007301 2 9 240 W R TP SINGLE LINE TVS DIODE FOR 500 523 5 V 240 W R TP SINGLE LINE TVS DIODE FOR DIODE TVS EDTY0007301 ESD IC EUSYO200301 Leadless chip 6 PIN R TP S W Pb Free VARISTOR SEVY0000702 14V 10 SMD VARISTOR SEVY0000702 14V 10 SMD PCB ASSY KEYPAD SMT SAED0012901 ODE LED C EDLH0006001 Blue 1608 R TP Blue SMD LED ODE LED C EDLH0006001 Blue 1608 R TP SMD LED DIODE LED CHIP EDLHO0006001 Blue 1608 R TP SMD LED BEBE ODE LED C EDLH0006001 Blue 1608 R TP Blue SMD LED ODE LED C EDLH0006001 Blue 1608 R TP Blue SMD LED 6 LD15 DIODE LED CHIP EDLHO0006001 Blue 1608 R TP SMD LED 6 LD16 DIODE LED CHIP EDLH0006001 Blue 1608 R TP SMD LED 257 10 EXPLODED VIEW amp REPLACEMENT PART LIST Level pred Description Part Number Specification Co
24. VSSBUCK TEST Figure 4 13 1 Main Battery Charging Path Charging Procedure Connecting TA and Charger Detection Control the charging current by AB2000 Vincenne Charging current flows into the battery Check Point Connection of TA Charging current path Battery Trouble shooting setup Connect TA and battery to the phone Trouble Shooting Procedure Check the charger connecter Check the Charging current Path Check the battery 128 start Check the pin and battery connect terminals of connector Connection OK Is the TA voltage 4 6V Is it charging properly after changing Q501 NO Change the board L702 129 4 TROUBLE SHOOTING Change I O connector Change TA END 4 TROUBLE SHOOTING 4 14 RF Component N301 402 302 301 FL102 Figure 4 14 1 RF component Top Reference Description Reference Description N301 VOLTAGE REGULATOR N403 DCS_TX_BALUN N402 HERTA GSM ADC N404 GSM_TX_BALUN N302 WCDMA PAM FL402 DCS_RX_SAW N303 ISOLATOR FL403 PCS_RX_SAW B301 TEMP_SENSOR Z401 GSM RX SAW FL102 DUPLEXER N405 GSM TRANSCEIVER 130 4 TROUBLE SHOOTING wio1 401 FL401 FL301 V201 Z201 Figure 4 14 2 RF component Bottom Reference Description Reference Description W101 TEST CONNECTOR Z201 WCDMA RX IF SAW 401 G
25. 2 la Eile Edi View Window Help mc 219 OUTPUT STATUS INSTRUMENT UART Call Instrument TEST SET MODEL Agilent Technologies 8960 1 s GPIB ADDR INITIALIZE STATUS CABLE LOSS FORMAT SWITCH WCDMA DCS 053 GSM GPRS WCDMA WCDMA 0 5 dB 5 136 Power Instrument TEST SET INIT POWER MODEL 8 POWER OUTPUT SET Tektronix PS2521G COUT2 ADDR 8 VOLTAGE 37 OUT ON OFF CURRENT 2 B oworr DEFAULT 37 20 Ready ari aeri pong Figure 7 8 XCALMON Calibration Tree Window INSTRUMENT Tab 221 7 CALIBRATION a XCalMon Calibration x Eile Edit View Window Help x zu mc E Calibration E RF Calibration E EGSMS00 Delay Setting for MODA D RXVCO Varactor Operating Point TXVCO Varactor Operating Point Loop Bandwidth GSM amp WCDMA VCXO Tx Power RSSI amp AGC E DCS1800 RXVCO Varactor Operating Point TXVCO Varactor Operating Point Tx Loop Bandwidth Tx Power RSSI IPHD Temperature Compensation E W CDMA Center Frequency Tx Carrier Suppression Tx LPF Bandwidth Tx Maximum Output Power Tx Power Table Tx Open Loop Power Control Tx Power Sense Rx LPF Bandwidth Rx LNA Gain Switch amp AGC Hys
26. 1 of 3 10f2 offset 1of3 Fig 4 20 5 Output Level at RF test connector Fig 4 20 6 Output Level at Switch Output W101 FL101 C103 156 4 TROUBLE SHOOTING Neasurement Instrument Screen Neasurement Instrument Screen ontrol Pout I 1 hermal 1 Pouer Pouer Thermal Pouer 75 00 Thermal Pouer 75 00 EIU Thermal Power EARNE Pg Thermal Power 19 38 Channel 18 97 un Channel 12 2k 12 2k Paging Service Paging Service Continuous Test Tode Continuous Test DL Channel 10700 92 15 41 14 42 48 5712 IDL Channel 10700 53 26 41 42 40 30 54 20 Uplink Channel Uplink Channel Suap Suap Positions ma Positions Ez Backoround_ lactive Sus UTRA FDD Background Cell Sus UTRA FDD Idle Idle 10f2 IntRef offset 10f3 1of2 offset I 1063
27. 44 uant 16 UamrCTSS 11 Grios RIS UART E anra JS Goo 21 Gps Geol I Pos v Pior FSC IP 2 p5 y gt nese sap nens POMDATA 08 IP vano 2 dec 0683 poop 29 815 26008 laa 28 XTAL2 svs E C642 1 19 DE RICCLK gt gt 9842 I Leo gt pos N nos 24 Pon Bluetooth BGB202 S2 25 f 32 281 vonon E GND12 FEB POR DISABLE 8 4 usu 6 8 37 5 PGND C646 640 _ m 2012 s 3 H cml Less Bottom view VBT C646 MCLK C643 Bluetooth Antenna ANT601 RTCCLK C642 Bluetooth chip Output C647 BTF REG EN R599 VBT at Regulator output R2186 182 Checking Bluetooth Regulator Block TP Command pctr 3 4 1 pdin 23 4 pdou z 3 4 1 brts 21 Itcx 3 dacc 0 2 responsed value Btfa 1 1 Btfaz1 2 VBT at Regulator output R2186 BTF REG EN R599 Check voltage level at No BTF REG EN R599 5 Check 0601 with Oscilloscope PE No About Check voltage level 2 85 Change Regulator U510 At VBT R2186 with Oscilloscope Yes Check Next Stage 183 Checking Bluetooth Block E55
28. BST d 69 i 882 VWEFdSW1 4 x AS euuajuy Jem gt zi gt doo lt 10 2 xj MVS XH WSS WSO LEBER WSO K Am lt MYS XH 94 209 810 lt A lt liqo gt 5 Ry yams eigo O zor14 19 SOd SOd O O I soa SOd SOQ INSO AS9 1 19497 524 500 159 NO uigpos 66949 XH SOd SOG NO 9 XH INSO Figure 4 21 2 GSM DCS PCS Tx Path Level 175 4 TROUBLE SHOOTING 7 Ee FL402 FL403 Test Program Script 1 GSM Tx 2 DCS PCS Tx MODE 0 MODE 2 DCS 1 PCS SWTX 1 64 5 1024 1 SWTX 1 699 0 1024 1 v Agilent 8960 Setting CW Mode GSM 50dBm Ch65 948MHz DCS 50dBm Ch700 1842 8MHz PCS 50dBm ch700 1889 0MHz v Oscilloscope Setting 176 4 TROUBLE SHOOTING B GSM Signal Check Idata TP402 De TP403 Qdata TP404 QRB R428 QRA R429 2 R430 IRB R431 TP404 TP402 403 jalalalalalzlals 402 LZN 901 0536 R1A 9 ES I2CD
29. 26 3 Technical Brief 3 1 3 External memory interface There are four independent chip selects CSO CS1 CS2 CS3 provided for external memories and each has an address range of 256 Mb calibration data Audio parameters and battery calibration data etc are stored in flash memory area A U8550 1 MCP used 512Mb flash memory 128Mb PSRAM 4 CS Chip Select are used Interface Spec Read Access Time Write Device Part Name Maker Access Async Burst Time 85 14 ns 90 ix at 54MHz 85 10 ns 85 at 66MHz di RD38F4455LLYBQ1 Table 3 1 1 External Memory Interface Spec of U8550 Flash 256 Mb Top boot Flash 256 Mb Bottom boot MARITA Intel MCP Figure 3 1 3 External Memory Configuration of U8550 27 3 Technical Brief 3 1 4 RF Interface A MARITA Interface Marita controls GSM RF part using these signals through GSM chip Ingela RFCLK RFDAT RFSTR Control signals for Ingela TXON RXON PCTL BANDSELO e ANTSW 0 3 DCLK IDATA QDATA DIRMOD A D Control signals for TX and part of Ingela Control signal for GSM TX Band selection signal for GSM or DCS Control signals for antenna switch GSM DCS RX Data GSM DCS TX Data RXON RADCLK RADSTR RADDAT BSELO GPRFCTRL ANTSWO ANTSW1 ANTSW2 ANTSW3 e o 5 a N e e uuo I 5181
30. 6 6 FB702 FILTER BEAD CHIP SFBH0002302 120 ohm 1608 CHIP BEAD 2000mA 275 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark 6 FL102 DUPLEXER IMT 1950 MHz 2140 MHz 1 45 dB 1 60 dB 41 dB 50 SEMY0960701 dB 5 4 5 0 1 6 SMD 21402 FILTER SAW SFSY0024302 1842 5 MHz 1 4 1 1 0 6 SMD 5pin Unbal Bal 50 150 FILTER SAW SFSY0024303 1960 MHz 1 4 1 1 0 6 SMD 5pin Unbal Bal 50 150 VARISTOR SEVY0005501 18 V SMD R Varistor Array 1000hm 15pF FL703 VARISTOR SEVY0005501 18 V SMD R Varistor 100 15 18 V SMD 4ch R Varistor Array 1000hm 15pF FL704 VARISTOR SEVY0005501 L199 L301 L302 INDUCTOR CHIP LTER BEAD CHIP ELCH0005009 100 nH J 1005 R TP FILTER BEAD CHIP SFBH0002302 120 ohm 1608 CHIP BEAD 2000mA SFBH0002302 120 ohm 1608 CHIP BEAD 2000mA L303 L304 L403 LTER BEAD CHIP LTER BEAD CHIP SFBH0002302 120 ohm 1608 CHIP BEAD 2000mA INDUCTOR SMD POWER ELCP0009401 4 7 uH M 2 8 2 6 1 0 R TP SFBH0007103 75 1005 CHIP BEAD 300 L404 FILTER BEAD CHIP SFBH0007103 75 1005 CHIP BEAD 300 L405 INDUCTOR CHIP ELCH0001413 22 nH J 1005 R TP PBFREE Pt 6 L406 INDUCTOR CHIP ELCHO0005006 33 nH J 1005 R TP 1407 INDUCTOR CHIP ELCHO0005013 4 7 nH
31. GND2 PGND GND1 c Folder Detect FB3 END1 gt ONSWAn 01 o LEFT SPEAKER END G2 gt 21 ac RIGHT SPEAKER 22 21 GIGH CN3 7 KEYINO KEYOUT1 KEYIN1 KEYOUT2 KEYIN2 KEYOUT3 KEYOUT4 KEYIN3 KEYIN4 KEYOUTS ONSWAn KEY_LED gt P UCLAMP0501H INSTPAR 000000000000 AXK6F24345 P UCLAMP0501H INSTPAR gt KEYPAD B to B Connector lt FOLDER DET KEY LED lt 4 LEBB S14H LD13 PGOSDBTFC R34 100K PGOSDBTFC LGIC 42 A 5505 10 01 KEYIN2 gt gt SIDE KEY Keypad 2 EVL14K02200 1 827 470 lt lt KEYOUTO EVL14K02200 VA2 EVL14K02200 UCLAMPOSO1H INSTPAR 3 lt KEYOUT2 RIGHT RIGHT1 4 lt lt KEYOUT4 CLEAR CLEAR1 EX LEFT SEARCH SEARCH1 MULTI lt KEYOUTS 236 7 27 Di S 2004 a _____ LG Electronics Inc DRAWING NA
32. Off Cell Poner Channel Pouer 75 00 E Channel Pouer dBn 3 8u MHz 10 64 Channel Type 12 2k Continuous ae s DL Channel 0 00 51 25 41 72 PERSE Tleasurements 10700 Channel Suap Window Positions mi IN 8750 UL Scrambling Background FDD Test Sus UTRA FDD 1072 IntRef Offset 1063 Fig 4 20 11 Output Level at Wivi Output N304 C320 157 4 TROUBLE SHOOTING To verify that the phone fulfils requirments on maximum output power Set the FDD Test of the Agillent 8960 Set the Maximum Power Check output power at the W101 with antenna Cable Refer to Graph 4 20 5 RF TX Level is OK Check next stage Check the power at the FL101 C103 with probe Refer to Graph 4 20 6 Check 2 About 15dBm The W101 has any problem Change the W101 Check the power at the FL102 C111 with probe Refer to Graph 4 20 7 Check 3 About 19dBm The FL101 will be broken Change the FL101 Check the power at the N303 out with probe Refer to Graph 4 20 8 heck 4 chec The FL102 has any problem Change the FL102 Check the power at the N303 In with probe Refer to Graph 4 20 9 The N303 has any problem Change the 3
33. 1 0 RADIO STR 012 23 to BATT ID 013 UARTRXO cms cms MODE 04 Ai RIST 100K 3 ADC IN 014 UARTTX0 X 05 CFMS i CFMS e His VBACKUP Uu 5 DSR RXIB I IN INV EMIF 015 SERVICE N i VPPFLASH 1 VPPFLASH e Br 756 T 5 PWR 45V 1 RXQA ADC Q IN 016 ONSWBn Dil 181 BLMI8PGT2ISN1J E 45V 2 Q IN 017 DCIN 3 S5 pco i s 000 101 RXEXTREF 018 88885 0 IN Lx ADC RXEXTREF N 019 55655 ks PCM F ADCSTR lt AD STR 020 ne WEN PCM SYNC A D701 021 1 Rx TXIA DAC L EMIF 022 5 PCM TXA OUT OUT mv D751980C1ZPHR WANDA 023 777 5 PWR GND 1 TXQA U7 bac a our 024 7 E 52 our 025 1 DAC TXEXTRES 026 at E use ER 027 LE EI E use HSSLTX Aig HSSLRX D EMIF D28 BTSZ 12 HSSLRXCLK ATS HSSLTX 029 i HSSLRX HSSLTX D EMIF D30 zx PWR GND 2 HSSLTXCLK HSSLRX EMIF D31 2 RTS m 2 PWR 2N 1 N 2 PWR 2 ISSYNCn SYNC ARE z ISEVENTn 8121 is EVENT N EMIF AREADY VRAT 1 cre T MCLK 1 EXT MEM UBUS10 G RTCCLK mis CLK32 EXT MEM UBUS11 VBUS
34. 1200kHz 1800kHz Intermodulation attenuation 2 PERFORMANCE DCS PCS Frequency offset 800kHz Intermodulation product should be Less than 55dB below the level of Wanted signal Transmitter Output Power Power control Level Tolerance dB Power control Power Tolerance Level dBm dB 5 0 30 6 28 26 24 7 8 9 10 22 20 11 18 12 13 16 14 14 a GO N 12 15 16 o 10 17 18 19 0 Burst timing Mask IN 13 Mask IN 2 PERFORMANCE 2 Transmitter WCDMA Mode Item Specification Class3 24dBm 1 3dB Maximum Output Power Class4 21dBm 2dB Frequency Error 0 1ppm Open Loop Power control in uplink normal 12dB extreme Adjust output TPC commana cmd 1dB 2dB 3dB 1 0 5 1 5 1 3 1 5 4 5 Inner Loop Power control in uplink 0 0 5 0 5 0 5 0 5 0 5 0 5 1 0 5 1 5 1 3 1 5 4 5 group 10equal command group 1 8 12 416 424 Minimum Output Power 50dBm 3 84MHz Qin Qout DPCCH quality levels Out of synchronization handling of output power Toff DPCCH lor 22 gt 28dB 24 gt 189 Transmit OFF Power 56dBm 3 84M 25us Transmit ON OFF Time Mask PRACH CPCH uplink compressed mode 25us power varies acco
35. 2 gt gt m gt 2 T I 2 m c 2 A 24 25 26 Ea 28 29 30 TAPE WINDOW 32 34 35 36 EA 1 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 o m m 3 Q g r zz F r lt lt lt lt lt D D D D D z z z z z e e e e e 2 3 3 2 3 gt gt gt gt gt o z m u 249 250 10 EXPLODED VIEW amp REPLACEMENT PART LIST 10 2 Replacement Parts Note This Chapter is used for reference Part order Mechanic component is ordered by SBOM standard on GCSC Level NH Description Part Number Specification Color Remark 00 ADDITION 0128401 MCJA00 COVER BATTERY MCJA0021801 PC UV SPRAY 2 APEYOO PHONE 0224002 GREEN COLOR 00 COVER ASSY FOLDER ACGG0061902 Green Without 200 BRACKET ASSY ABFZ0005801 BUTTON SUPPORT BRACKET ASS Y Color Without Color 200 20083301 Without Color COVER ASSY ACGHO0 o DER LOWER ACGH0035502 Green 5 MCJHO0 COVER FOLDER LOWER MCJH0026901 PC DECO FOLDER LOWER MDAF0007402 Green MFBBOO FILTER RECEI
36. Ct here TP202 DATA 4 D TP203 CLK haw da feel Stet nhat Select Meses emit TP201 STROBE TP202 DATA 71 postive TP203 CLK 1 00 v Chi Figure 4 20 3 Control Signal Check 2011 202 TP208 Check shape and pk pk level Refer to Graph 4 30 Download the SW After downloading If signal is not OK Change the D701 Control Signal is O K Check next stage 155 4 TROUBLE SHOOTING 4 20 4 Checking RF TX Level Check 1 W101 Check 2 FL101 C103 Switch Output Check 6 N302 C307 PAM Input Check 3 FL102 C111 Check 5 Check 4 N303 Isolator Input N303 Isolator Output Figure 4 20 4 Test point RF TX Level Neasurement Instrument Screen Tleasurement Instrument Screen CBE gr meo pat E Thermal Pouer D lel Pouer Setup Thermal Pouer 23 53 Fu 14 82 con Was 12 2k RNC 12 2k Paging Service Continuous RB Test NUM E E ET ETET Uplink Channel Uplink Channel ede Em K sm UL Scrambling 0 Backoround Test Sus UTRA FDD Ei Backoround active Cell 1of2 mmerrse
37. DCIN 3 gt em GNE 2 0 8 R2205 F12 Name SI7411DN T1 E3 C548 10p VET GPA12 GPA13 DCIO CHREG CHSENSE CHSENSE FGSENSE FGSENSE VSS A B vss C 55 D SUB VSSBUCK TEST Figure 3 4 12 Schematic of charging control part ASIC PA Control DCIO K Control To GPADC gt CHSENSE gt To GPADC Figure 3 4 13 Battery charging block diagram Unused Description CHSENSE VBAT Current sensing input positive CHSENSE VBAT Current sensing input negative Table 3 4 6 Charger Control channel spec 68 3 Technical Brief 3 4 11 Fuel Gauge AB2000 VINCENNE supports the measurement of the current consumption charging current in the U8550 with a fuel gauge block By constantly integrating the current flowing into and out of the battery the fuel gauge block is used to determine the remaining battery capacity The function of the fuel gauge block is schematically described in Figure 3 4 15 A sense resistor FGSENSE is connected in series with the battery The voltage across the resistor equivalent to the current entering leavin
38. L lt ICVEETESETSGRTGTER T mains 20 LCDBL3 a Hi um LCDBLA m E ausos LTC3206EUF 2 10015 gt CIPCLK ane WA L susp BL 10 ennas Susa L 8 SUO onm LUCAM 8 TN 2 soa RED FLASH El oura mE BEE 2 GREEN 17 FLASH2 cine lows vid I 55 BLUE FLASH m 7 A 8 22 NFA21SL207XTA45L FL705 1 24 o of 2 23 LEFT P O4 SPK RIGHT P 777 un TN 1 3M CAMERA CONNECTOR KEYOUTO s KEYINO 4 KEYOUTI 5 2 KEYIN1 ai aaa 5 KEYOUT2 5 d KEYIN2 gt KEYOUTS i KEYIN3 EE 8 KEYOUT4 KEYING 8 5 EARP KEYOUTS i ONSWAn EARM i 4 14 2 KEY LED lt u gt FOLDER DET LCD BL and Cam Flash Driver LTC3206 2 2 FILTER 2 PDIDE 3 FITER23 FILTERI PDIDS c SS 2 5 FITERI 5 2003 FILTER2 6 FILTERI 6 PDID2 E om CI urea KEYPAD to Connector i FILTER ICVE21184E150R101FR 2 s 5885 SYSCLKI our Ai INOUT g aT I2CDAT VGA 2 sour mour E I2CCLK VGA 3 mour mour Bs Z 5 CIVSYNC as mour 5 rA 5 58 Must
39. 6 DOWNLOAD 6 3 U8XXX Download 6 3 1 08 Download 1 FlashRW configuaration A Execute FlashRW V200 Red exe B Press the Global Settings on the top menu to configure FlashRW environment far 18120 Version 400 Build 1005 t Global Settings LG Electronics Inc 3G Handsets Lab LGE Signed Software ssw flash files Pathname i Add There are no flash files to download into the target Remove Remove All Download All LGE GDFS flash file Addl Remoye Pathname There are no flash files to download into the target Log Messages AJi9 Model U8120 gt Pon 85232 gt 188 6 DOWNLOAD 11 LLL C Select Loader File for Product You can use browse button to select Loader File You must select only 1325414 u8550R for U8550 Loader File is provided with FlashRW D Select Port configurations for both RS232 Port and USB Port Baudrate should be 115200bps Global Settings X Loader File Product SCION RS232 Configuration Pot 5 Baudrate 115200 bps USB Port Configuration Port USB 1 You have to FlashRW configuration only at the first time of installation 189 6 DOWNLOAD ks 6 3 1 U8XXX Download 2 Phone Model Selection A Press Button for Model B Sele
40. 621013 GND8 Hr ed GND10 gt 3g VODIORF amp 9648 1 27 8 s Xy 40 POR DisABLE 8 22 VREG18 a 15 VDD18 PGND cei cmo a 10472012 77 C645 7 0 1 Figure 3 1 11 Schematic of Bluetooth module BGB202 S2 Clock Clock request Connected to CLKREQ of MARITA and VINCENNE input to WOPY Fast clock 13MHz Supplied MCLK from Frequency deviation 10ppm f level of MCLK is less than 400mVpp connect to 1 8V through R652 120K Slow clock 32 768kHz Supplied RTCCLK from MARITA Power Supplied 2 85V from external regulator U510 controlled by GPIO34 of MARITA NRESET PCM GPIO 2 9 1 8V is generated by internal regulator BGB202 S2 Baseband core GPIO 10 14 SysCIkReq JTAG Reset RESOUT2n signal of MARITA controls BGB202 S2 reset UART Connected to UART3 of MARITA interface between MARITA and BGB202 S2 PCM Audio signal interface between MARITA VINCENNE and BGB202 S2 ANT 2 4GHz 50 ohm matching Antenna switch CN601 is used for Bluetooth calibration 38 3 Technical Brief 3 1 11 TransFlash Interface U8550 supports the TransFlash interface as external memory card TransFlash has 4 data line but U8550 uses only 1 data line All control and data line is connected to MARITA
41. EM ar S laser coe a d mac MIC2N msan C 1827541 19 __ 2 T Mee Jusl gt gt ae 4 8 es layeass 0p BGND vaan Cris Es HS EN gt E HS SPK SEL 9988 10 ear m T gt SPK LEFT GUIDE HOLE y 2t gt SPK_LEFT_P 01801 04803 F m 1 EE M m wr cs caf 5 spk RIGHT vo gt gt SPK RIGHT P LG ELECTRONICS INC 144 uem Fee HW Group Development Lab 6 TRDCHK U8550 spfy0106301 1 1 Vincenne Regulators 7 MFGENGRCHK Page 5 of 7 Baseband 1 of 3 im icai Figure 3 4 3 Schematic of Audio Path 57 3 Technical Brief 3 4 3 Audio Mode Audio Mode includes three states Voice call Midi MP3 Each states is sorted by the tot
42. H3 m seo lt L u vopaur VssTH22 NT mm E12 PASENSE me Cse9 100K cigssr a PASENSE PASENSE VSSTH20 Bg vean 10p Rs76 PAREG Diy VSSTHI9 08 11 m IOUT VSSTHI8 07 m HS EN gt mss 77 RET 0505 fore zz P1 iN voo PCMSYN Pcusvw vss EZ V 5288 786 vob2 54 LM PEMCLK vssTH2 d R534 ci Nc 8 PCMDATB NM I VSSTH3 96 15 vaer 5 M 2012 GUIDE HOLE PCMDATA Pomi ES iono 55 6 vo gt SPK LEFT M VSSTH5 ve SR NrsPL kat ns mg 5 vssme ET 35 sray 5 33n sp gt SPK LEFT P 4500 0503 o 100K 100K VSSTH7 Lesrr z 5 d 1608 tu 8 T VSSTH9 58 523 590 4 SEIS 10K 82K 77 m He TII 777 VDDADC Hs Ti 3D OFF G5 R524 o L 5 VSSADC VSSTHI4 4700p VSSCODEC VSSTHIS 3D CTRL2 Pens 37 55 I LE A pe i voor 31 1
43. IN o gt gt gt OUT 1 INBAR o OUTBAR 2 BUFFGAIN 4 Bias amp o BUFFGAIN2 Logic 9 LOINTEXT 1 1 l l 1 l wH E E l l ad l dvoid HLAWNIVS Figure 3 8 5 Block Diagram of RF Mixer and Buffer 90 3 Technical Brief F Power Amplifier The N302 RF9266 is a high power high efficiency linear amplifier module targeting W CDMA transmitter ASIC The module is fully matched to 50BY for easy system integration and utilizes advanced GaAs HBT process technology The PA features an integrated RF power output detection network and is compatible with DC DC converter operation in DC power management applications Additionally a variable bias current allows the idle current to be adjusted for optimum performance at a given RF output power GND RFin GND 22 21 20 1 lt Vetri z 1 GND GND BIAS Vcc_bias 2 Vcc_bias 0 2 GND Detector GND network o Vccdet z GND 8 9 10 11 12 a 5 2 2 2 gt 5 Figure 3 8 6 Block Diagram W CDMA power amplif
44. 0000201 0 ohm 1 16W J 1005 R TP 0000261 10K ohm 1 16W J 1005 R TP 6 R2239 6 R2251 6 R309 RES CHIP 0000203 10 ohm 1 16W J 1005 R TP 0000201 0000201 0 ohm 1 16W J 1005 R TP ohm 1 16W J 1005 R TP 6 R310 6 R311 HY0000201 0 ohm 1 16W J 1005 R TP 6 R312 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 6 R313 6 R314 0000111 680 ohm 1 16W F 1005 R TP 6 R315 RES CHIP 0000111 1680 ohm 1 16W F 1005 R TP 0000201 ohm 1 16W J 1005 R TP 6 R316 6 R317 HY0000201 ohm 1 16W J 1005 R TP 6 R318 RES CHIP ERHY0000254 4 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP R319 R320 0000203 10 ohm 1 16W J 1005 R TP R401 RES CH RHY0000241 1 ohm 1 16W J 1005 R TP R402 RES CHIP MAKER RHZ0000459 3 Kohm 1 16W J 1005 R TP R403 RES CH 0000201 0 ohm 1 16W J 1005 R TP R407 RES CH 0008601 0 05 1 4 J 2012 R TP 267 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark 6 R408 RES C HIP 0000201 0 ohm 1 16W J 1005 R TP R413 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 6 6 R503 6 R504 0000280 100 ohm 1 16
45. 1 Ww tu 2700p 0525 nisi a Nc Bt 777 vo gt RIGHT M E gt SPK RIGHT P H 177 Engineer H R530 LG ELECTRONICS INC AUDIO AMP EN E ST Drawn by Mobile Handsets R amp D Center D acaso sa HW Group Development Lab 6 RED CHK TE 100K 77 A2 DOCCTRLCHK UB550 spfy0106301 1 1 Tm Vincenne Regulators MEG ENGR CHK pene 5 of 7 Baseband 1 of 3 233 8 CIRCUIT DIAGRAM 10 11 12 sos BGB202 52 A cuxnea e 8689 225 gion ner 120 nesouran _48 meer N Tok 82 Tus stac 57 UARTRTS3 gt 44 Uamr UARTCTSS 4T a UARTRXS 4S Gri Txo uant GPloo UARTTX3 gt GPIOS UART neos oy PCMDATB DA
46. 1 16 7 1005 6 508 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 0000241 1K ohm 1 16W J 1005 R TP 6 R509 6 R513 0000274 51K ohm 1 16W J 1005 R TP 6 R514 RES CHIP 0000261 10 ohm 1 16W J 1005 R TP 0000261 10K ohm 1 16W J 1005 R TP 6 R515 6 R524 0000241 1K ohm 1 16W J 1005 R TP 6 R525 RES CHIP ERHYO0000241 1 ohm 1 16W J 1005 R TP 0000280 100 ohm 1 16W J 1005 R TP 6 529 6 530 0000201 0 ohm 1 16W J 1005 R TP 6 R531 RES CHIP ERHY0000264 18 ohm 1 16W J 1005 R TP 0000264 18K ohm 1 16W J 1005 R TP 6 R532 6 R533 0000201 ohm 1 16W J 1005 R TP 6 R534 RES CHIP ERHY0000264 18 ohm 1 16W J 1005 R TP ERE HIP ERI 0000264 18K ohm 1 16W J 1005 R TP 6 R537 6 R539 H 0000201 0 ohm 1 16W J 1005 R TP ERI 6 R566 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 6 R567 RES CHIP ERHYO0000280 100 ohm 1 16W J 1005 R TP 6 R569 RES C 6 R572 RES C HIP ERI HIP ERI 0000236 0000201 0 ohm 1 16W J 1005 R TP 620 ohm 1 16W J 1005 R TP 278 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark R573 RES C HIP ERI 0000201 0 ohm 1 16W J 1005 R TP 574 RES CHIP 0000236 1620 ohm
47. 222 8 81 lt 80 5 PCMSYN 33 FSC IP 2 T ERE mm LN 328 5 PCMCLK 35 DCLK IP 37 HE 4 Net onswe lt A PCMDATA GPIO9 DB IP vano 22 Da MAC ANTE and c2101 close 3 777 C2100 and 62101 close to B2100 gt c eras svs pom s 32 768KH Wer 38 kraz svs GND2 77 77 Z gt gt 82 100 19 wrati Leo nos 5 B 229 28 xTAL2 LPO Gna 8 A nos 5 24 anon noe 7 9012 Bluetooth BGB202 S2 T B 9 i GPIO14 10 cupro SE ali vooionr 12 10 amp 2 5 GNDI4 5 8 8 52 amp 8 PGND ceas 218 ness L R634 C606 330p 100772012 SERVICE N ST merk gt A5 120K NA SYSCLKO A6 C641 C645 SYSCLKI SYSCLKI A 1 SERVICE N PWRRSTn gt T Fa RESPOW N eun RESOUTOn Fal RESOUTO N An RESOUTIn Lt Resour n RESOUTZn RESOUTZ N RESOUTSn 021 nesours N vues U3 RESOUT4 N ms 29151888 T0005 cuneo PWRREQn amp N AIT 88888 azs ES ISSYNCn 77 ISEVENTn ISEVENT N va IM tog CLKREQ 35 A22 VGA 5
48. B Calibration Tree Window Icon When you click the calibration window icon C then you should see the calibration tree window That will be shown all calibration items If you want to calibrate U8550 mobile phone for all calibration items you should select Calibration and push button in your keyboard Also there are four tap view in calibration window OUTPUT results of calibration STATUS Summary of calibration result INSTRUMENT Control and view instrument connection status UART Control and view UART connection status 220 7 CALIBRATION a 2 Eie Edit View Window Help 2 181 x RF Calibration 2 5 900 Delay Setting for MODA D RXVCO Varactor Operating Point TXVCO Varactor Operating Point Loop Bandwidth GSM amp WCDMA VCXO Tx Power RSSI amp AGC E DCS1800 RXVCO Varactor Operating Point TXVCO Varactor Operating Point Tx Loop Bandwidth Tx Power RSSI OUTPUT STATUS I INSTRUMENT I UART IPHD Temperature Compensation E W CDMA RF Center Frequency Tx Carrier Suppression Tx LPF Bandwidth Tx Maximum Output Power Tx Power Table Tx Open Loop Power Control Tx Power Sense Rx LPF Bandwidth Rx LNA Gain Switch amp AGC Hysteresis Rx AGC Gain Max amp RSSI WCDMA VCXO amp Calibration Battery Voltage Test Figure 7 7 Calibration Tree Window OUTPUT Tab
49. TAPE DECO MPBZ0101301 0095101 0095201 Without Color MTABOO TAPE PROTECTION MTABO1 TAPE PROTECTION WINDOW CAMERA 0089201 0089301 0009301 0 8 5 Color o 4 WINDOW FLASH ACGNOO ASSY CAMERA 0001601 0004501 CAMERA BRACKET ASS Y Transparent 4 SJMYOO VIBRATOR MOTOR SJMY0007007 3 V 08 A 5 12 4 Cylinder Motor Without Color o N ABFZ00 BRACKET ASSY MBFP00 BRACKET CAMERA MTAZOO TAPE 201 ABFZ0005701 MBFP0003001 20083001 20083201 MEGA CAMERA BRACKET ASS Y Without Color Without Color Without Color out Color MGADOO GASKET SHIELD FORM MCCF00 CAP MOBILE SWITCH MGAD0102701 MCCF0030501 3 GMEYOO SCREW MACHINE BIND GMEY0009201 1 4 mm 3 5 mm MSWR3 Bk HEAD D 2 7mm Without Black White 20 63 77 00 CAP SCREW 0054901 SILICON RUBBER MAIN LEFT Color White 3 MCCHO01 CAP SCREW MCCHO0055001 RUBBER MAIN RIGHT MFEAO0 FRAME SHIELD 007801 Without Color 73 71 2 7 MLAKOO LABEL MODEL 5 DOME ASSY METAL 5 200 0009001 ADCAO0035301 20022901 MAIN BUTTON DOM
50. et Build date 030506 Build number 1100 Loader name PRGCXC1325413 Release version R2L End time Friday April 09 2004 00 04 10 Elapsed timo 00 02 46 Total elapsed time 00 10 55 target shutdowned gt Model 08122 5232 1 Pon is not opened While Downloading Check this massage to confirm download for 118110 ersion 4 0 0 Build 100 Global Settings LG Electronics Inc Handsets Lab LGE Signed Software ssw flash files Pathname 1 ize Add Sww vnanBwel10 vosoe 20040402wWdrive medid ssw 3571 D WU8100 10_ 0908 20040402wdrive lt 4 ies D WU8100 Sw VOSDBYWUG1 10_V0S0B 200404099wFS Rec dl 19271 KB Swwwvn30Bwi 18110 0808 2004040294 08100 phdna wec 11404 Remove All 055711028 All LGE GDFS flash file Pathname Size Addl There are no llash files to download into the nemo _ j Log Messages Loader version information Build date 020506 Build number 1100 Loader name PRGCXC1325413 Release version R2L End time Friday Apri 09 2004 00 04 10 Elapsed time 00 02 46 Dsed time 00 10 55 target shutdownedtni aJi zl n 22 uu lt After Download
51. y GNDPHD y MODA MODB CHARGE MODC MODD PHASE From VCO DETECTOR PRESCALER F PULSE SKIP DETECTOR TBL NPS N VCCPRE offset DELAY PHD CP PRE BIAS CIRCUITS GNDPRE Figure 3 7 4 Block diagram of the PLL part 82 3 Technical Brief 3 7 2 Transmitter A 4 bit sigma delta bit stream comes from the Marita ASIC including both channel information and the GMSK phase information Via the 3 control bus also driven from Marita the selection of transmitter band is made The 4bits from the bit stream provides the fine tuning of the division ratio before going to the divider of the used VCO low band 900MHz or high band 1800 1900 The modulated VCO signal is fed to the output buffer One buffer is available for each of the low and high bands Trimming capability is included for best match versus the PA used The GSM GPRS transceiver Ingela output is passed to the dual band PA that after amplification feeds the signal via a low pass filter to the antenna switch and further to the antenna The transmit block consists of two differential high power transmit output buffers with controllable output power The modulated transmit signal from the VCO buffer is amplified to a level suitable to drive the external power amplifier The buffer outputs are of open collector type and must be terminated into a suitable load Figure 3 7 5 shows a block diagram of the transmitter blo
52. 0008701 10 22 ohm 1 4W J 2012 R TP 593 599 600 5 0000201 0 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 0001302 1 ohm 1 8W J 2012 R TP 648 650 651 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP RES CHIP HY0000266 22 ohm 1 16W J 1005 R TP 0000282 120 ohm 1 16W J 1005 R TP 652 656 0000186 33 pF 50V J NP0 1005 R TP R701 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP R702 R704 0000201 0 ohm 1 16W J 1005 R TP 706 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 708 714 0000201 0 ohm 1 16W J 1005 R TP 715 5 0000201 0 ohm 1 16W J 1005 R TP 716 RES CHIP ERHY0000214 51 ohm 1 16W J 1005 R TP R717 RES CH RHY0000201 0 ohm 1 16W J 1005 R TP R718 RES CH RHY0000214 51 ohm 1 16W J 1005 R TP 269 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark 6 R721 R724 725 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP RES CHIP ERHY0000261 10 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 726 730 731 0000201 0 ohm 1 16W J 1005 R TP
53. 1 16 7 1005 602 604 0000201 ohm 1 16W J 1005 R TP R606 RES CHIP ERHY0000213 47 ohm 1 16W J 1005 R TP 0000250 3 3K ohm 1 16W J 1005 R TP R608 R609 RHY0000250 3 3K ohm 1 16W J 1005 R TP R610 RES CH RHY0000243 1 2 ohm 1 16W J 1005 R TP R613 RES CHIP 0000280 100 ohm 1 16W J 1005 R TP 614 RES CH 0000233 470 ohm 1 16W J 1005 R TP 615 RES CH 0000283 130K ohm 1 16W J 1005 R TP 279 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark R616 RES C HIP 0000213 47 ohm 1 16W J 1005 R TP 617 RES CHIP ERHY0000275 56 ohm 1 16W J 1005 R TP 6 R618 6 R619 0000280 100 ohm 1 16W J 1005 R TP 0000280 100 ohm 1 16W J 1005 R TP 6 620 RES CHIP ERHYO0000275 56 ohm 1 16W J 1005 R TP 6 R621 6 R626 0000280 100 ohm 1 16W J 1005 R TP 0000241 1 ohm 1 16W J 1005 R TP 6 627 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP R628 R629 0000280 100 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 630 RES CH 0000250 3 3K ohm 1 16W J 1005 R TP 6 R631 RES CHIP 0000220 100 ohm 1 16W J 1005 R TP R634 RES CH RHY0000282 120 ohm 1 16W J 1005 R TP a R636 R641 RHY0000280 100 ohm 1 16W J 1005 R TP H
54. 5 0000261 10 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 732 733 735 0000201 0 ohm 1 16W J 1005 R TP RES CHIP 0000201 0 ohm 1 16W J 1005 R TP HIP 0000262 12 ohm 1 16W J 1005 R TP 736 737 738 739 740 RES CHIP E R 0000201 0 ohm 1 16W J 1005 R TP HZ0000459 3 Kohm 1 16W J 1005 R TP RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP RES CHIP HIP 0000201 0 ohm 1 16W J 1005 R TP ERI 0000201 0 ohm 1 16W J 1005 R TP 744 745 747 0000250 3 3K ohm 1 16W J 1005 R TP RES CHIP 0000249 2 ohm 1 16W J 1005 R TP 0000143 43 ohm 1 16W F 1005 R TP 748 749 752 0000280 100 ohm 1 16W J 1005 R TP RES CHIP 0000280 100 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 753 754 R755 0000201 0 ohm 1 16W J 1005 R TP RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 0000280 100 ohm 1 16W J 1005 R TP 756 757 758 0000201 0 ohm 1 16W J 1005 R TP RES CHIP 0000280 100 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 843 847
55. C307 CAP CERAMIC CH CAP CERAMIC CH 0000143 1 nF 50V K X7R HD 1005 R TP 0000186 33 pF 50V J NPO 1005 R TP 6 6 C308 CAP CERAMIC CH 0000155 10 nF 16V K X7R HD 1005 R TP 6 C309 CAP CERAMIC CHIP 0000115 22 pF 50V J NPO TC 1005 R TP EBEN 271 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark 6 C310 CAP CERAMIC CH P 0000167 0 1 uF 6 3V K X5R HD 1005 R TP C311 CAP CERAMIC CHIP 0000110 10 pF 50V D NPO TC 1005 R TP CAP CERAMIC CH 0000115 22 pF 50V J NPO TC 1005 R TP 6 6 C312 6 C413 CAP CERAMIC CH 0000165 68 nF 6 3V K X5R HD 1005 R TP 6 C414 CAP CERAMIC CHIP 0000155 10 nF 16V K X7R HD 1005 R TP CAP CERAMIC CH 0000165 68 nF 6 3V K X5R HD 1005 R TP 6 C415 6 C416 CAP CERAMIC CH 0000165 68 nF 6 3V K X5R HD 1005 R TP 6 C417 CAP CERAMIC CHIP 0000165 68 nF 6 3V K X5R HD 1005 R TP CAP CERAMIC CH 0000165 68 nF 6 3V K X5R HD 1005 R TP 6 C418 6 C419 6 C425 CAP CERAMIC CHIP CAP CERAMIC CH P 0000155 10 nF 16V K X7R HD 1005 R TP 0000115 22 pF 50V J NPO TC 1005 R TP 6 C426 CAP CERAMIC CHIP 0000115 22 pF 50V J NPO TC 1005 R TP 6 C427 CAP CERAMIC CH CAP CERAMIC CH P P 0000115 2
56. HY0000220 100 ohm 1 16W J 1005 R TP 6 R412 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP BERE 0000206 18 ohm 1 16W J 1005 R TP 6 R414 6 R415 HY0000228 270 ohm 1 16W J 1005 R TP 6 R416 RES CHIP ERHY0000228 270 ohm 1 16W J 1005 R TP EE 0000201 ohm 1 16W J 1005 R TP 6 R417 6 R418 HY0000201 0 ohm 1 16W J 1005 R TP 277 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Part Number No Level Description Specification Color Remark 6 R420 INDUCTOR CHIP ELCHO0005015 6 8 nH S 1005 R TP R421 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP INDUCTOR CHIP ELCHO0005015 6 8 1005 RES C HIP ERI 6 6 R422 6 R423 HY0000220 100 ohm 1 16W J 1005 R TP 6 R424 RES CHIP ERHY0000220 100 ohm 1 16W J 1005 R TP 0000235 560 ohm 1 16W J 1005 R TP 6 R425 6 R426 0000222 120 ohm 1 16W J 1005 R TP 6 R427 RES CHIP ERHY0000231 390 ohm 1 16W J 1005 R TP HIP ERI 0000201 ohm 1 16W J 1005 R TP 6 R428 6 R429 H HY0000201 ohm 1 16W J 1005 R TP IP ERI 6 R430 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 6 R431 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 6 R501 RES C HIP ERI HIP ERI 0000201 0000201 0 ohm 1 16W J 1005 R TP 0 ohm 1 16W J 1005 R TP 6 R502 6 R507 HIP ERI 0000280 100K
57. PDID6 PDID5 PDID4 PDID3 PDID2 PDID1 PDID0 LCDWRX LCDCSX MAIN LCDCSX SUB LCDRDX LCDRESX VGA IO OFF LCDRS MLED1 MLED2 MLED3 MLED4 MLED5 CIRES N SYSCLK1 I2C DAT CIVSYNC CIHSYNC CIPCLK gt lt lt KEYIN1 KEYIN2 6660060606000060000000000004 8 m KEYIN3 CPO LTC LCDBL 777 MAIN to LCD Connector 9QooooooQooQo AXK720145G 77 Camera Connector 6 060600000000000000 AXK8L40125G Header LCD Connector Sign amp Name Sheet Date Sign Name Eg U8550 GD32 Sheets 04 26 Designer Checked DRAWING U8550 LCD FPCB 1 0 NAME Approved DRAWING LG Electronics Inc enter draw number LGIC 42 A 5505 10 01 LG Electronics Inc 238 9 PCB LAYOUT 239 peso 9 PCB LAYOUT 1063 s 41 10441 240 U95990 9 PCB LAYOUT 0 8550 5 0035701 1 9 PCB LAYOUT 1 oT 8 8 8
58. X5R 1608 R TP C588 CAP CERAMIC CHIP 0005705 10 uF 6 3V X5R 2012 R TP CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP C591 C595 CAP CERAMIC CH 0005705 10 uF 6 3V X5R 2012 R TP C596 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP C597 C598 CAP CERAMIC CH 0000139 470 pF 50V K X7R HD 1005 R TP 599 0000110 10 pF 50V D NPO TC 1005 R TP 0005705 10 uF 6 3V X5R 2012 R TP C600 C640 CAP CERAMIC CHIP 0005705 10 uF 6 3V X5R 2012 R TP C641 CAP CERAMIC CHIP ECCH0000168 0 1 uF 16V Z Y5V HD 1005 R TP PT C642 CAP CERAMIC CHIP 0000128 100 pF 50V J NPO TC 1005 R TP C643 CAP CERAMIC CHIP 0000128 100 pF 50V J NPO TC 1005 R TP o CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP C645 C646 CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP C647 CAP CERAMIC CHIP 0000115 22 pF 50V J NP0 TC 1005 R TP 0000114 20 pF 50V J NPO TC 1005 R TP C705 C706 C708 CAP CERAMIC CHIP 0005801 2 2 uF 6 3V X5R 1608 R TP CAP CERAMIC CH 0000114 20 pF 50V J NPO TC 1005 R TP CAP CERAMIC C
59. all TX channels can be reached Procedure Proposal 1 Put the phone in static TX mode 2 Measure the loop voltage with the 2000 ADC for all CVCO settings that is 0 7 Find a CVCO value that fulfills the requirements on loop voltage for low and high channel 3 If there are several CVCO values that fulfill the loop voltage requirements then the optimum CVCO value is the one that centers the loop voltage within the specified limits 4 Store the selected CVCO in the memory GD BAND TX VCO Centre Frequency Adjustment 5 Reset the radio C TX Loop Bandwidth Calibration Purpose The loop bandwidth is calibrated to match the pre filtering of the modulation in DB 2000 by adjusting the phase detector current Note This also indirectly adjusts the VCO gain that can otherwise not be calibrated This will ensure a correct transfer function for the modulation and keep phase error to a minimum 207 7 CALIBRATION Procedure Proposal 1 Put the ME in switched TX mode on mid channel in frequency interval 11 for DCS with random modulation 2 Measure the RMS phase error at the RF connector 3 Tune the phase detector current IPHD until the phase error is minimized If two IPHD settings gave the same RMS choose the lowest value Measure 10 bursts for each value 4 Calculate and store the IPHD values in GDFS IPHD 8 and 24Channel Compensation 5 The offsets in the table are st
60. gt gt gt EGSM IPHD Cal Start lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt z Ready Figure 7 14 Calibration FAIL Message Window 81 File Edit w Window Help 18 Calibration OUTPUT STATUS INSTRUMENT RF Calibration 5 EGSM900 raurc vj nn nvrg UT TUgUUU n3SI TUU UUMTUU El Delay Setting for MODA D 1871 RXVCO Varactor Operating Point j Varactor Operating Point RX RSSI Calibration Loop Bandwidth RX Pur 95 Pur 95 Table 8 Rurg 75 306900 RSSI 95 013500 RSSI amp AGC Pur 88 DCS1800 Pur 88 Table 8 amp urg 61 963708 551 88 889488 Varactor Operating Point 91 Aurgs 1 TXVCO Varactor Operating Point RX Pur 68 Tx Loop Bandwidth Pur 46 Power RX Pur 25 IPHD Temperature Compensation Ak_Aurg_116 89 Pin_Corrected_116 1692 W CDMA RF VCO Center Frequency gt gt gt WCDMA RX AGC Gain Max and Rx RSSI Cal End lt lt lt lt lt lt lt lt lt lt lt Tx Carrier Suppression gt gt gt Total Fail Number in WCDMA Calibration 6 Tx LPF Bandwidth gt gt gt WCDMA 811 Items Calibration End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt l
61. o CENTER F RIGHT E CES 777 Figure 3 1 15 Schematic of MOD Keypad 42 3 Technical Brief 3 2 GAM Hardware Subsystem GAM PDID 7 0 GRAPHCON X PDI SSI ed PDIC 4 0 control PDIRES N CIRES Y GRAM GAMCON 160k byte CID 7 0 Camera CDI CIPCLK eg CIVSYNC Module AHB Slave Slave CIHSYNC M I ki AHB2 DMA AHB1 CPU Figure 3 2 1 GAM Subsystem Functional Block Diagram 3 2 1 General Description The Graphics Accelerator Module GAM subsystem provides hardware support in the creation of visual imagery and the transfer of this data to the display GAM also provides support for the camera module The visual data could be graphics still images or video The GAM subsystem consists of five modules GRAM graphics memory 160 kB GAMCON GAM controller GRAPHCON graphics controller PDI SSI programmable display interface for parallel serial displays CDI camera data interface 43 3 Technical Brief 3 2 2 Block Description Coniroller GAMCON The Controller GAMCON is responsible for clock gating and distribution within the module GAMCON receives the HCLK from SYSCON and distributes to GRAPHCON GRAM
62. 0000115 22 pF 50V J NPO TC 1005 R TP 6 541 6 542 0004903 1 uF 6 3V 7 5 1005 6 C543 CAP CERAMIC CHIP 0000115 22 pF 50V J NPO TC 1005 R TP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C544 6 C545 CAP CERAMIC CH 0004903 1 uF 6 3V Z Y5V 1005 R TP 6 C546 CAP CERAMIC CHIP 0005705 10 uF 6 3V X5R 2012 R TP 0004903 1 uF 6 3V 2 Y5V TC 1005 R TP 6 C547 6 C548 CAP CERAMIC CH ECCH0000110 10 pF 50V D NP0 TC 1005 R TP 6 C549 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP ERE CAP CERAMIC CH 0005705 10 uF 6 3V X5R 2012 R TP 6 C550 6 C551 6 C552 CAP CERAMIC CHIP CAP CERAMIC CH P 0005705 10 uF 6 3V X5R 2012 R TP 0000139 470 pF 50V K X7R HD 1005 R TP 6 C553 CAP CERAMIC CHIP 0000276 1 uF 10V Z YSV HD 1608 R TP 6 C556 6 C557 CAP CERAMIC CH CAP CERAMIC CH P P 0000143 1 nF 50V K X7R HD 1005 R TP 0000115 22 pF 50V J NPO TC 1005 R TP 262 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark C576 CAP CERAMIC CHIP 0005801 2 2 uF 6 3V
63. 20V 0 8 MOSFET SOT 363 27 W 20 66 A R TP Dual P channel PD 0 27W VDS 8V ID 0 57 Pb free SOT323 2 W R TP NPN SWITCHING TR Pb free 6 Q702 6 Q703 EQBP0003001 UMT6 15 W R TP 6 R101 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP 0000201 ohm 1 16W J 1005 R TP 6 R102 6 R103 HY0000201 ohm 1 16W J 1005 R TP 6 R104 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP Pt HY0000201 0 ohm 1 16W J 1005 R TP 6 R105 6 R106 HY0000201 0 ohm 1 16W J 1005 R TP 6 R201 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP RES CHIP 0000250 3 3K 1 16 1005 6 R202 6 R203 FILTER BEAD CHIP 5 0007103 75 1005 CHIP BEAD 300mA 6 R204 FILTER BEAD CHIP SFBH0007103 75 ohm 1005 CHIP BEAD 300 EE 0000201 0 ohm 1 16W J 1005 R TP 6 R205 6 R206 0000255 0000201 5 6K ohm 1 16W J 1005 R TP 0 ohm 1 16W J 1005 R TP 6 R207 6 R208 6 R209 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP 0000220 0000201 100 ohm 1 16W J 1005 R TP ohm 1 16W J 1005 R TP 6 R210 6 R212 HY0000241 1K ohm 1 16W J 1005 R TP 6 R2126 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 0000280 100K ohm 1 16W J 1005 R TP 6 R2127 6 R2129 ERHY0000280 100K ohm 1 16W J 1005 R TP 6 R2132 RES CHIP
64. 5 166 4 TROUBLE SHOOTING 29 0 03 CHANNEL 13 86 48 Trace 2 OFE E RADSTR eee x 200 13 Jan 84 11 38 20 Gs gt Ltt cmp p sen Eds 3 1 COFFsets in lo Volts I Divisions Gr ids Single 1 1 18 ps s Quad Octal 1290m DC DC B 19 mv AC 5 25 MS s 250 MS s 3 2 DC DC 1 00 V DC T DC 2 12 V 4 2 v STOPPED k 1 evts STOPPED lt lt lt lt 8 Figure 4 21 1 GSM RF Control signal Check TP406 TP408 TP407 Check if there is any Major difference Refer to left side of Figure 4 21 1 Yes Change the board the board Check R421 C448 Check if there is any Major difference Refer to right side of Figure 4 21 1 No No Resoldering VDD A block i 1416 1411 L414 R409 Yes Yes Control signal is OK Resoldering LPF block See next page to check 167 4 TROUBLE SHOOTING 4 21 5 Checking RF Tx Path A GSM Tx path Level Urgpor WSO 007 251044681947 uneg WSS SOd SOd 62 014 19940 XL 504 014 166940 XL SOG 9 XL INSS ITELLA
65. A device driver is software program that enables hardware device to work with e an operating system This wizard will complete the installation for this device c USB Flash Device A device driver is a software program that makes a hardware device work Windows needs driver files for your new device To locate driver files and complete the installation click Next What do you want the wizard to do lt gt for my d led Display list of the known drivers for this device so that can choose a specific driver lt Back Cancel 194 6 DOWNLOAD NENNEN ea D Select Specify a location in Found New Hardware Wizard E Push the Browse Button and then select USB driver Information file This File is provided with FlashRW Found New Hardware Wizard Locate Driver Files Where do you want Windows to search for driver files Search for driver files for the following hardware device gt gt USB Flash Device divor CORDERO On SOurcpmputes and in any of the following optional search locations that you To start the search click Next If you are searching on a floppy disk or CD ROM drive insert the floppy disk or CD before clicking N Optional search locations I Floppy disk drives CD ROM dives Specify a location Microsoft Windows Update ae ma ve Cancel Copy manufacturer s files from
66. No Follow the keypad Trouble shooting guide END key operates well ONSWAn C597 level is low when END key pressed Check the voltage VCORE R600 1 5V VDIG R560 2 8V VMEM 563 1 8V VRTC R551 1 5V VEXT15 M N502 Pin 5 1 5V VEXT15 W 702 5 1 5V VDD A R2250 2 8V VDD B R2251 2 8 No Change main board 94 EE 4 TROUBLE SHOOTING 2 Top view Bottom view 95 4 TROUBLE SHOOTING 4 2 USB Trouble START Measure during the state of USB module running Input power N501 Pin 1 is 5V Yes Output power N501 Pin 5 is 3 3V Yes USBSENSE level is 2 8V Yes No VUSB C623 is 3 3V Change main board Top view 96 Check host USB port or USB cable Resolder or change N501 Resolder R513or R514 Resolder C623 4 TROUBLE SHOOTING 4 3 SIM Detect Trouble SIM control path MARITA generates SIM interface signals 2 75V level to VINCENNE Vincenne converts SIM interface signals to 3V 5V Resolder X502 on main PCB and check the contact between X502 and SIM card Change main board 97 4 TROUBLE SHOOTING 4 4 TransFlash Trouble Re insert TransFlash Finish Check operation of TransFlash using other notebook or PDA ransFlash work well NS Change the T
67. Operating on 1 52GHz which is 4times the TX IF frequency 380MHz and 8 times the RX IF 190 2 this is a fully integrated balanced LC oscillator with on chip resonator On chip varactor are used to tune the VCO frequency Prescaler Phase detector with charge pump For maintaining check on the VCO center frequency the tuning voltage is set to Vcc 2 External DC blocking capacitors must be used on the IFLO IFLOBAR signals m o TBIFVCO TBIFSI 2 VTUNEIF 5 5 9 TBIFSO 2 x B 2 x VCCIFVCO 8 IF PLL GNDIFVCO 9 IFPLLON a IFLO IFLOBAR XO R GNDTUIF R PHD Charge PHDIFOUT Pump D DP E PIER RUNG TiddIlaN5 Figure 3 8 7 Block Diagram of Frequency Synthesizer Part IF PLL 93 4 TROUBLE SHOOTING 4 TROUBLE SHOOTING 4 1 Power ON Trouble START he voltage of main battery is higher than 3 2 2 No Charge or change main battery No Follow the Keypad backlight Trouble shooting guide Press END key Keypad LED ON
68. The current consumption when only the reference oscillator and the output buffer are activated must be kept to an absolute minimum To PLL XOOON XOIA MCLK XOIB REFON XOOA 4 XOOB XOOON XOOON REFON BIAS CIRCUITS Figure 3 8 3 Block diagram of the Reference section 87 3 Technical Brief 3 8 2 Transmitter Analogue differential signals currents representing and Q are sent to the radio ASCI Wivi W CDMA Transmitter ASIC from the D A converter in Wanda W CDMA digital base band coprocessor ASIC The signals are filtered in a reconstruction filter and then modulated up to 380MHz using the IFLO signal The signal is then amplified in a VGA and filtered in an external filter an LC filter After filtering the signal is mixed to its final frequency using the RFLO and amplified in a differential output RF buffer with two different gain settings high gain or low gain The differential RF signal is fed into a SAW filter with a single ended output and is then amplified in a stand alone RF buffer After the RF buffer the signal is filtered again in a SAW filter before it is fed to the PA Power Amplifier In the PA the signal is amplified for the last time before leaving the radio After the PA the signal is sent through an isolator and through the duplexer which directs the transmit signal to the antenna connector via the antenna switch The PA has variable supply voltage whic
69. gt gt gt BB Battery Voltage Cal Start lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt UBRTT 328 25 68 DAC 39 UBRTT 418 18607158 DAC 121 PASS gt gt gt BB Battery Voltage Cal End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt gt gt gt Total Fail Number in BB Calibration 6 gt gt gt BB fll Items Calibration End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt gt gt gt BB 11 Items Calibration End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt gt gt gt 811 Items Calibration End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt vl r A Figure 7 16 Calibration Result from STATUS Tab View 227 228 8 CIRCUIT DIAGRAM 1 2 3 4 5 6 2 8 9 10 11 12 22p 1 2 jus 3 FL102 DFYYGIGOSLENBC TT WCDMA m om WCDMA RX 588588 777 on 1101 R101 wy d ANT
70. lt lt lt BIS uc EXT MEM UBUSI2 CLKREQ lt 415 cLkna EXT FRAME STROBE USBPUEN lt lt 28 RESOUTin RESET N C NUF2221W1T2 3 al lt lt D ues TOT DACCLK MS DAC Slano 4 lars PE DACDAT 13 DAC 4 CPU USBDP lt 801 4 Tosa 5 8 556 DACSTR M5 pac sr Be i CPU urxo sur EM 8558 t CPU USB FILTER gnes L 1705 Eu 8824 8888 BER cPu moo 7 Enc wstm 8995 CPUCLKOUT VBAT 777 777 777 g H ln 8888 52323552 888888888888883888888888888888 s walas 8888 66500000 22222222222222222222222222222 Saci s SISSE TITTEN x pes 881187 2121278788121 SCP IP eee es es see cess Pose cere 3 BBB 8743 2 NA 1 8 UARTI 777 E E Engineer H SEM LG ELECTRONICS INC Drawn Mobile Handsets R amp D Center leongseok Lee HW Group Development Lab 6 RED CHK TE DOCCTRLCHK U8550 spfy0106301 1 1 2 _ WANDA Connector MEG ENGR CHK Page 7 of 7 Baseband Part 3 of 3 Changed by Date Changed Time Changed GA CHK FEV Drawing Number JS Lee 2004 May 16 7 25 29 pm es Se _____ a o a P C o 235 8 CIRCUIT DIAGRAM KEYOUTO R1 100K gt FOLDER DET 212 01 ourPur 5 2 4 7
71. lt lt lt lt lt lt lt lt lt lt gt gt gt Elapsed Time 00 00 02 Total 2sec gt gt gt BB fll Items Calibration End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt gt gt gt 811 Items Calibration End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt Figure 7 15 Calibration Result from OUTPUT Tab View 226 rr As Eile Edit View Window Help 7 CALIBRATION xl 1811 Et Calibration RF Calibration E 5 900 Delay Setting for 0 RXVCO Varactor Operating Point TXVCO Varactor Operating Point Loop Bandwidth GSM amp WCDMA VCXO Tx Power RSSI amp AGC DCS1800 RXVCO Varactor Operating Point TXVCO Varactor Operating Point Tx Loop Bandwidth Tx Power RSSI IPHD Temperature Compensation W CDMA RF VCO Center Frequency Tx Carrier Suppression Tx LPF Bandwidth Tx Maximum Output Power Tx Power Table Tx Open Loop Power Control Tx Power Sense LPF Bandwidth LNA Gain Switch amp AGC Hysteresis Rx AGC Gain Max amp RSSI WCDMA BB Calibration Test Ready Battery Voltage OUTPUT STATUS INSTRUMENT J UART gt gt gt WCDMA TX Open Loop Power Control Cal End lt lt lt lt lt lt lt lt lt lt lt lt gt gt gt WCDMA Low Pass Fi
72. will occupy 1 byte One value for TABLE OVERLAP 1 byte One value for UPPER LIMIT 1 byte 5 Calculate the actual compensation for maximum output power that each of these 24 tables will give Store this in GD RF TX FREC INT ID 3 Store data in GDFS UARFCN 9737 9763 9788 Table 10 6 The Complete Gain Compensation Table 213 7 CALIBRATION E TX Open Loop Power Control Calibration Purpose The purpose of the calibration of open loop power control is to store parameters for the Open Loop Power Control algorithm This is a pure off line calculation Use data positions and output power in dBm from table 0 Curve fitting should be done preferably with minimum square method System related requirements Open loop power control Maximum allowed UL TX Power UE Transmitted power Procedure proposal 1 Create a curve fitting for the low gain region use positions with power greater than 50 dBm Position Pout Extract A3 and B3 The power level output power at the highest position in the low gain region sets the parameter P2 Divide the high gain region into two regions at the split between mid gain and high gain The output power at this position sets the parameter P1 Do a curve fitting for the mid gain region where RFBias gt 0 of the highgain region use power levels from P2 Position B
73. 1 uF 16V Z Y5V HD 1005 R TP CAP CERAMIC CH 0000122 47 pF 50V J NPO TC 1005 R TP 6 6 C726 6 C727 CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C728 CAP CERAMIC CHIP ECCH0000168 0 1 uF 16V Z Y5V HD 1005 R TP CAP CERAMIC CH ECCH0000137 330 pF 50V X7R 1005 R TP 6 C729 6 C730 CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C731 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C732 6 C733 6 C734 CAP CERAMIC CHIP CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C735 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C736 CAP CERAMIC CHIP CAP CERAMIC CHIP ECCHO0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C737 6 C738 CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C740 CAP TANTAL CHIP MAKER ECTZ0000318 33 uF 10V M STD 3216 R TP CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C741 6 C742 CAP CERAMIC CH 0000276 1 uF 10V Z Y5V HD 1608 R TP 6 C743 CAP CERAMIC CHIP 0000155 10 nF 16V K X7R HD 1005 R TP CONN RF SWITCH ENWYO0000401 STRAIGHT SMD 0 1 dB 3 3 1 8 500 CYC
74. 1701 ASSY 8 ohm 90 dB 15 mm 14mm 3 7T gt 5 00 ASSY KEYPAD SMT 5 0013301 ASSY KEYPAD SMT 5 0012701 0000110 10 5 1005 0000122 0000182 47 pF 50V J NPO TC 1005 R TP 0 1 uF 10V X5R 1005 R TP CAP CERAMIC CH 0000122 C8 CAP CERAMIC CHIP 0000122 0000122 47 pF 50V J NPO TC 1005 R TP 47 pF 50V J NPO TC 1005 R TP EE 47 pF 50V J NPO TC 1005 R TP 0002107 ENBY0001803 0001803 24 PIN 5 mm STRAIGHT SILVER 2 PIN 1 27 mm STRAIGHT SILVER 2 PIN 1 27 mm STRAIGHT SILVER ODE SWITCHING FB1 FILTER BEAD CHIP SFBHO0007103 LTER BEAD CHIP 5 0007103 EDSY0010401 1 1G1A 40 V 300 A R TP Silicon Epitaxial Schottky Barrier Type Diode 75 ohm 1005 CHIP BEAD 300mA LTER BEAD CHIP 5 0007103 ERHY0000280 75 1005 CHIP BEAD 300mA 75 1005 CHIP BEAD 300mA 100K ohm 1 16W J 1005 R TP 256 10 EXPLODED VIEW amp REPLACEMENT PART LIST Level ned Description Part Number Specification Color Remark 6 R11 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP ____ porem _
75. 33 nF 16V K X7R HD 1005 R TP CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP CAP CERAMIC CH 0005705 10 uF 6 3V X5R 2012 R TP C117 C1899 C1915 CAP CERAMIC CH 0005705 10 uF 6 3V X5R 2012 R TP CAP CERAMIC CHIP 0006201 4 7 uF 6 3V X5R 1608 R TP 0006201 4 7 uF 6 3V X5R 1608 C1916 C1917 C1918 CAP CERAMIC CH 0000155 10 nF 16V K X7R HD 1005 R TP 0000276 1 uF 10V Z Y5V HD 1608 R TP ECZH0003501 1 uF 6 3V X5R 1608 R TP C201 C202 C203 CAP CERAMIC CH 0000117 27 pF 50V J NPO TC 1005 R TP CAP CERAMIC CHIP 0000155 10 nF 16V K X7R HD 1005 R TP BERE CAP CERAMIC CH 0000117 27 pF 50V J NPO TC 1005 R TP C204 C206 6 6 6 6 6 6 6 6 6 6 6 6 207 CAP CERAMIC CH 0000147 2 2 nF 50V K X7R HD 1005 R TP CAP CERAMIC CHIP 0000115 22 pF 50V J NPO TC 1005 R TP EE CAP CERAMIC CH 0000115 22 pF 50V J NPO TC 1005 R TP C208 CAP CERAMIC CH 0000115 22 pF 50V J NPO TC 1005 R TP C209 CAP CERAMIC CHIP 0000180 3 3 pF 50V NPO 1005 R TP 259 10 EXPLOD
76. 402 SKIP SYNC 458 2 28 COMP SHDN 7 gt VCCWPA R308 1 12 GNDS VDETECT our 62 0 R303 GND gt R301 M REF ix 9 gt WPOWERSENSE Lena mor 10 2012 R302 0306 75 VCC21 BIAS2 100K 1000p 0 77 IAs g anos not 7 3 7 Y Raos gs veen lt WPAREF ac 8 z 55 gt IFLOBAR 5 E 56 22 RFLO gt gt IFLO 7 77 RFLOBAR gt 238 V wivi T L305 BLM15BB750SN1J wm 75 R309 3 9 3 1 1 10 Loar j 1 2 0314 C322 ens 323 325 C324 J maie V_wivi_A TP301 TP302 Seni podia 2 c HR J B301 TP304 Wi iw 391 vo x RTEMP 777 T 1 598 2 a k s 3 m AES 1308 a 8358288 58 822 s 2 m 3 ime 82802822492 87 asser SAFEHIGOSFLOFDOROSFL3DT 3 34 OUTBARS Set A GNDRF INBAR ime m S uxor TXIA NA NA cr E 3 AT B E PHDIFOUT 7 22 id irapaAn vccireLL 28 ia 77 1 28 fis L cuonrLo2 vecirveo I B 22p GNDRF1
77. 4V LDO supply 2 4V for BIAS 2 8V LDO supply 2 8V for Mega Camera 2 8V LDO supply 2 8V for VGA Camera 2 85V LDO supply 2 8V for Bluetooth and TransFlash 3 3V LDO supply 3 3V for USB CHARGER PUMP supply up to 400mA continuous output current for LCD back light and Camera Flash LED 74 3 Technical Brief EE a Marita Vincenne VID LP 1 57 000006 VIOOLA VCORE 15 7 WecAZ 28m A 79547126 TX Fic 85 Figure 3 5 1 Power supply scheme Name Type Output voltage Description VDD A Power Supply 2 75V Supply output VDD_B Power Supply 2 75V Supply output VDD_D Power Supply 2 75V Supply output VDD_E Power Supply 1 8V Supply output VDDLP Power Supply 1 5V Low Power supply output VDDBUCK Power Supply Unused VBAT Buck converter switch supply VSSBUCK Power Supply GND Buck converter switch ground Table 3 5 1 LDO and BUCK 75 3 Technical Brief EE 5 5 Fa 3 6 General Description of RF Part The RF part includes a tri band GSM DCS PCS part 900 1800 and 1900MHz and W CDMA part for IMT 2000 UL 1900MHz dl 2100MH2 It also contains Antenna Switch WCDMA duplexer WCDMA Power Amplifier and GSM Power Amplifier The whole structure of Radio part is shown in Figure 3 6 1 577 Mem Crysta Test
78. 8 8 OG 399g Ju SE ARCHI pam 8 884055409 8550 5 00552701 1 0 9 PCB LAYOUT 401 0 1 106c8S800A2dS V4 JWV2 0668 243 9 PCB LAYOUT 01108 0 1 1068600429dS V3 JWV2 06G8f 244 9 PCB LAYOUT U8550 LCD FPCB 1 0 TOP 245 9 PCB LAYOUT U8550 LCD FPCB 1 0 BOTTOM 246 247 10 EXPLODED VIEW amp REPLACEMENT PART LIST 10 1 EXPLODED VIEW 59227 A 248 DRAWING NO 0022901 070301 MCJK00418 MSGY00111 MKAA001 26 021 2 MCCG00031 ADCAO0035301 MSGB0010901 SGEY0003707 DESCRIPTION QTY DRAWING NO REMARK SUB AWAZ00071 01 SILVER 02 GREEN 03 3 LOGO MDAY0006801 DESCRIPTION BUTTON SIDE PLATE FACE OVER FRON S m Q MDAE00304 01 SILVER 02 GREEN 03 4 01 SILVER 02 GREEN 03 ORANGE m o m 01 SILVER 02 GREEN 03 gt gt T m lt z STOPPER TAPE DECO 01 SILVER 02 GREEN ITI Q z gt 5 5 Q lt pas m 0 gt gt 210 m 2 lt m m 0 CINNECTOR STPPER HINGE LCD SUB MIKE 79 gt PAD SPEAKER 0022601 5 0044401 SUSY0017501 MFEA0007801 5 0134601 MBFP0003001 20083001
79. ANTSW1 i E nune jis s ae t 5 i 1 88 Hee HH ANTSW2 7 3 gh 3 i 3 t Mie ANTSW3 1 1 maximum 2 74 V m ximum 0 15 V m ximum 2 2 75 V maximum 2 2 75 V maximum 3 8 11 V maximum 3 8 11 V PCS Rx p y ANTSW1 E Fe High 1 ANTSW2 ANTSW3 Low Low me 146 4 TROUBLE SHOOTING Band ANTSWO ANTSW1 ANTSW2 ANTSW3 EGSM Tx H L H EGSM Rx DCS Tx PCS RX H L H H DCS Rx H H H L H L WCDMA Figure 4 19 1 Antenna Switch Module Logic 147 4 TROUBLE SHOOTING 4 19 2 Checking Switch Block power source Before Checking this part must check common power source through Vincenne part TP Command MODE 0 SWRX 64 1024 2 Check Soldering It is necessary to check short condition Using Tester Check 4 resistor ANTSWO L105 ANTSW1 L104 ANTSW2 L103 ANTSW3 R102 Check soldering L105 Resoldering Check ANTSWO L105 To check Switch input power source Check each mode By TP command Change the Board 148 A EGSM Rx mode ANTSW1 ANTSW2 ANTSW3 B EGSM Tx mode ANTSW1 ANTSW2 ANTSW3 4 TROUBLE SHOOTING MODE 0 SWRXz64 1024 2 t LOW i T LOW s d 1 lt 1 80 4 ee i 2 5 ps 3 1 00 V H
80. CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C631 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C632 6 C633 CAP CERAMIC CH ECCHO0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C634 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C635 6 C636 CAP CERAMIC CH ECCH0000276 1 uF 10V Z Y5V HD 1608 R TP 6 C637 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C638 6 C639 CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C644 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C739 6 CN502 6 CN703 CONN JACK PLUG EARPHO NE CONNECTOR BOARD TO BOARD DIODE SWITCHING ENJE0003603 112 12 PIN MMIC CONN 12P 0002103 24 5 mm STRAIGHT SILVER 2 30 V 1 VF 1 5V IF 200mA EDSY0011901 R 30UA VR 10V 6 D501 6 D601 u289 BGA 289 PIN R TP BASEBAND FUSY0155004 CONTROLLER MARITA 6 D702 DIODE TVS EDTY0006401 SC70 6L 5 V 100 W R TP PB FREE FB701 RES CHIP MAKER ERHZ0000608 10 ohm 1 10W 1608 R TP
81. CID1 CID1 a 18 100K CID2 CID2 CID3 8 CID4 cw DG3516DB T5 E1v 77 g g 9205 05 4 5 8 8 919 8 C616 gt 5 z Ts CAMERA wd ns NA NA gt gt I2CDAT MEGA gt gt IZCCLK MEGA VGA EN 618 ja o a s M ook a RUE DG3516DB T5 E1v 77 cand 8 NA NA i T 77 82246 R2247 77 NA NA gt gt I2CDAT VGA gt gt I2CCLK Figure 3 2 2 Camera Interface in Marita 3 zT mns Pm E m Ls w 25 E m RIR ayt K CIRES_N_MEGA 7 cipo on 11 Hours me Slo mour a 7 mour Houn m mouran wour 2 NEAISUATTXTATSL 71706 9 0 env ICVEPTISETSORTOIFR nre sre 1 ma st 5 gt gt 777 GEJ mal cum em 833 Houn m H7 HH NFA21SL207X1A45L 77 27 g A
82. Change Flash LED YES Camera Flash Works Check Flash LEDs NO TO Pin16 Pin17 Pin18 of U701 4 0V Direct Power Supply over 3 5V 2 NO NO Flash LED Works YES Change the U701 Resolder Flash LEDs or Camera Flash Works Change Camera amp LCD FPCB Change the Main Board Camera Flash Works YE S 111 4 TROUBLE SHOOTING cs D P e lt EJ 1901000000917 Over 3 5V 112 4 TROUBLE SHOOTING 4 12 Audio Trouble 4 12 1 Receiver Signals to the receiver Receiver signals are generated at Vincenne BEARP BEARM Receiver path Vincenne BEARP BEARM gt CN701 on main board gt LCD Module Receiver Note It is recommanded that engineer should check the soldering of L C along the corresponding path before every step 113 4 TROUBLE SHOOTING START Connect the phone to network Equipment and setup call Setup 1KHz tone out Does the sine wave appear at L501 L502 Change the main board YES The sine wave not appear Does the sine wave appear NO at Number 47 48 pin in the main B d CN701 Check R510 R511 YES NO Does the sine wave appear at EAR PAD in LCD Module Change the LCD module YES NO Is the soldering ot the receiver OK Resolder Receiver YES Can you hear sine
83. Coupling Impedance C3 Pk Pk 124mv 4 C3 Mean 163 7mV AC 0 d amplitude 100mV 1 Cuz ren ES Feed a CW signal at 2141MHz with a power level of 60dBm Bandwidth 264 6 Position offset Deskew Probe 250 MHz 7div 3 26 div ov 0s Functions Figure 4 20 17 1 signal CW 2141MHz 162 Tek 50 0 5 5 396 Acqs H w Measure FUF Frequency Select Measurement Fre 1 005868 Hz Ju w signal Period Width eu 100mv 100mV 1 0045 Ch3 170mV 100 Ch4 100 1018 Gating Statistics Level Setu OFF Measure Check the pk pk level at ees Remove rmn Measrmnt N201 A7 A10 with Oscilloscope Refer to Check the Mean level at N201 A7 A10 with Oscilloscope Refer to Check the frequency at N201 A7 A10 with Oscilloscope Refer to Verify whether the signal was similar as Graph at N201 A7 A10 with Oscilloscope OF Histogram Figure 4 20 18 RX I Q signal Set the CW Mode of the Agillent 8960 Feed a CW signal at 2141MHz Set the RX Continuous mode No About 120mVp p Yes About 160mV Yes D No Yes Ce No Yes Check Next Stage 163 201 7 227 N201 A8 RXQB C229 N201 A9 RXIA C228 _ N201 A10 RXIB C22
84. EXPLODED VIEW amp REPLACEMENT PART LIST 10 3 Accessory MHBYOO HANDSTRAP Note This Chapter is used for reference Part order is ordered by SBOM standard on GCSC SBPLOO BATTERY PACK LI ION MHBYO0000404 Hand Strap 135mm Black SBPLO072221 3 7 V 1400 mAh 1 CELL PRISMATIC U8130 BATTERY Li Silver Polymer 1400mA Typical SGDYOO DATA CABLE SGDY0005601 DK 40G K8000 24PIN I O USB TYPE EMEN SGEYOO EAR PHONE EAR MIKE SET SSADOO ADAPTOR AC DC SGEY0003707 0880 8550 GRAY AIR CAP 2 0TMMI12P SSADO0007848 50 Hz 4 6 0 8 A CE 3G 282
85. NI N NI N N N Table 10 2 IPHD Compensation for EGSM Band E VCXO Calibration Purpose This procedure aims to calibrate the value of DAC3 to establish a VCXO frequency that is sufficiently close to 13 MHz at room temperature It also ensures that the VCXO tuning range is sufficient and that the temperature compensation table for VCXO is completed accordingly Note The frequencies in this section are related to the 13 MHz VCXO frequency Depending on the calibration procedure the 13 MHz VCXO frequency can be acquired by first measuring an EGSM DCS or W CDMA RF frequency at the antenna and then translating the measured frequency to the 13 MHz VCXO frequency Procedure Proposal 1 Put the ME in switched low power TX mode with a modulated carrier on a mid channel Use the calibrated value of the cap array and phase detector current 2 Tune DAC3 in AB 2000 VCXOCONT to end and mid values and check tuning range 204 7 CALIBRATION Acquire the following VCXO 13 MHz frequencies fmin 13 MHz VCXO frequency DAC3 1 fmid 18 MHz VCXO frequency DAC3 1024 fmax 13 MHz VCXO frequency 9 DAC3 2047 Note that it is necessary to translate the measured RF frequency EGSM DCS or W CDMA to the 13 MHz VCXO frequency 3 Acquire the ME temperature TCal from the temperature sensor in ME 4 Store fmin fmid fmax and TCal for calculation 5
86. On the same channel now feed a modulated 50 dBm signal and measure the RSSI value 4 Switch off the LNA using the command FREC 3 0 1 and measure the RSSI value 206 7 CALIBRATION 5 Calculate the difference between on and off converting the result to dB attenuation and store the result MPH Parameters Band 7 3 4 DCS 1800 Calibration Items A RXVCO Varactor Operating Point Calibration Purpose To adjust the varactor diode to a pre determined operating point so that the loop voltage of the RXVCO measured with an ADC in AB 2000 is within the valid range This is necessary to secure that all RX channels can be reached Procedure Proposal 1 Put the ME in static RX mode 2 Measure the loop voltage with the 2000 ADC for all CVCO settings that is 0 7 Find a CVCO value that fulfills the requirements on loop voltage for low and high channel 3 If there are several CVCO values that fulfill the loop voltage requirements then the optimum CVCO value is the one that centers the loop voltage within the specified limits 4 Store the selected CVCO in the memory GD BAND RX VCO Centre Frequency Adjustment 5 Reset the radio B TXVCO Varactor Operating Point Calibration Purpose To adjust the varactor diode to a pre determined operating point so that the loop voltage of the TXVCO measured with an ADC in AB 2000 is within the valid range This is necessary to secure that
87. PDI and CDI GAMCON also distributes the GAM reset signal to GRAPHCON GRAM PDI and CDI The reset signals CIRES_N and PDIRES_N are distributed from GAMCON to the camera and display module respectively see Figure 2 28 The CIPCLK is used to clock the received data into the camera data interface The CIPCLK can be in the range of 100 kHz to 16 MHz B Graphics RAM GRAM Block GAM includes 160 kB of graphics memory GRAM in order to support display screen sizes of QCIF alfa display size and three frame buffers when decoding QCIF video The GRAM can be accessed in 8 16 or 32 bit mode Write access takes a single AHB clock cycle Non sequential read and the first access of a sequential read access takes two AHB clock cycles Subsequent sequential read access take a single AHB clock cycle The GRAM contains both frame buffer and temporary data There are three image areas with one used for normal MMI graphics and the other two areas used for still images video frames or camera frames The three image areas can be combined into one frame buffer GRAM is required to transfer a VGA 640 by 480 pixels image from the camera data interface CDI over DMA at 100 MBit s within a 50 ms timeframe The GRAM is used as a buffer but the average transfer bandwidth required is approximately 3 Mword s 32 bit word that is 12 MByte s C Graphics Controller GRAPHCON Block GRAPHCON is controlled by the application CPU and can perform operations on pixe
88. RF system is managed via the Wanda WCDMA digital base band coprocessor ASIC and its DSP processor 77 3 Technical Brief 3 7 GSM Mode 3 7 1 Receiver The received RF signal on the antenna connector arrives via antenna switch at external band pass filters for band selectivity One filter is required per supported GSM band The corresponding LNA amplifies the signal for optimum noise suppression The LNA output signal is mixed with the on channel LO generated by the proper VCO and transformed into a Q and an signal The and signals are low pass filtered with two parallel high dynamic range filters Finally the filtered and signals are converted by a sigma delta converter into two 13 Mbps digital bit streams by Herta A D converter then fed to the Marita baseband ASIC A Front end RF Front end consists of antenna antenna switch FL101 three RF SAWs FL402 FL403 7401 and triple band LNAs integrated in transceiver N405 The Received RF signals GSM 925MHz 960 2 DCS 1805MHz 1880MHz PCS 1930MHz 1990 2 are fed into the antenna or coaxial connector An antenna matching circuit is between the antenna and the coaxial connector The Antenna Switch FL101 is used to select the signal path which is one of WCDMA GSM RX GSM TX DCS RX DCS PCS TX and PCS Rx The control signals VC1 VC2 and VCG of antenna switch FL101 are connected to Marita baseband ASIC D601 to control the signal path For example when th
89. SFBH0007103 75 ohm 1005 CHIP BEAD 300mA 5 0007103 75 1005 BEAD 300 6 L501 FILTER BEAD CHIP 6 L502 FILTER BEAD CHIP SFBH0007103 75 ohm 1005 BEAD 300mA 6 L503 INDUCTOR SMD POWER ELCP0009402 22 uH M 2 8 2 6 1 0 R TP power inductor ELCHO0005005 27 nH J 1005 6 L601 INDUCTOR CHIP 6 L602 CAP CERAMIC CHIP 6 L701 0000186 33 pF 50V J NPO 1005 R TP SOT323 6L 6 PIN R TP EMI FILTER amp LINE F0SY0163501 TERMINATION for USB SFBH0002302 120 ohm 1608 CHIP BEAD 2000mA 6 L702 6 N101 05 0122502 LLP 6 6 PIN R TP 300mA CMOS LDO 2 8V Pb free 6 N201 IC 05 0133001 56 PIN R TP U8000 RF IC 304 EUSY0132901 56 56 WCDMA TXIC Wivi 6 6 401 dBm mA dBc dB 6 6 1 25 SMD for TRI SMP Y0007101 BAND EGSM GPRS 265 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark 6 N503 EUSY0132701 u143 BGA 143 PIN R TP ASIC POWER MANAGEMENT IC VINCENNE 6 N702 IC 05 0153001 SOT23 5 5 PIN R TP 150 mA LDO REGULATOR 1 5V THERMISTOR SETY0005701 NTC 47000 ohm SMD F Pb Free 6 PT501 6 Q501 6 Q502 TR FET P CHANNEL TR FET P CHANNEL TR BJT NPN EQFP0005601 EQFP0003601 EQBNO0014901 POWERPAK 1212 8 0 8 W 20 V 5 4 A R TP P CHANNEL
90. SVCY0007701 SACY0038101 20083201 0102701 MGAD0096701 SJMY0007007 GMEY0009201 014801 SNGFO001107 0072 0001601 0009301 095201 00130 0054901 055001 030501 0001401 MGAD0096901 037501 GMEY0009201 7 vs gt n lt m 0 w m 1 2 ASSY KEYPAD K S Alo lt 5 BE Elo FRAME SHILED gt m w z 1 1 1 gt 4 79 gt a 5782211 cre a HIER AE 7 E 1 UE WE PADICDMAIN o o i 1 WWAA008 COVERFOLDERLOWER 1 McJHoo2690 L um zm p cw e R 4 t MAIN xp cap screwrowoen ur 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 gt 2 4 CAMERA MEGA Q lt Ee m 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PCB ASSY FLEXIBLE CAMERA gt ID wn z 2 4 4 4 4 4 4 5 6 01 SILVER 02 GREEN 03 O
91. TX N304 LZT 108 5322 Transmitter TX FL301 SAFEH1G95FLOFOOROO TX RF Filter TX D701 ROP 101 3033 1 Analog Baseband TRX FL402 SAFEB1GB84FAOF00 DCS RX Filter Direct Conversion Z401 SAFEB942MFLOFOO GSM RX Filter Direct Conversion FL403 SAFEB1G96FAOF00 PCS RX Filter Direct Conversion N405 LZT 108 5325 Transceiver TRX 401 SKY77321 PAM GSM DCS PCS Tri N404 LDB21897M15C 003 GSM Balun TX N403 LDB211G8020C 001 DCS PCS Balun TX D601 ROP 101 3035 _1 Modem Bluetooth U604 BGB202_S2 Bluetooth Table 5 1 1 RF Part Component List 186 5 BLOCK DIAGRAM 6 DOWNLOAD 6 1 The Purpose of Downloading Software To make a phone operate at the first manufacturing A phone Hardware Software A phone cannot operate with hardware alone The hardware with the suitable software can operate properly upgrade the software of the phone The software of the phone may be changed to enhance the performance of the phone The older version software of the phone can be replaced to the newer version Download Tools FlashRW Download tool for UBXXO software 6 2 Download Environment Setup U8550 UART data cable furi USB cable Figure 6 2 1 08 0 Download can be done UART amp USB 187 6 DOWNLOAD
92. TX LPF Bandwidth Calibration TX Maximum Output Power Calibration TX Power Table Calibration TX Open Loop Power Control Calibration RX LPF Bandwidth Calibration RX LNA Gain Switch and AGC Hysteresis Calibration RX AGC Gain Max and Rx RSSI Calibration 201 7 CALIBRATION 7 3 3 EGSM 900 Calibration Items A MOD A MD bit Delay Calibration Purpose The procedure is designed to calibrate the timing alignment between the MODA D signals and the reference signal 13 MHz It also ensures that the MOD signals have stable values when they are clocked into the divider of the Phase Locked Loop PLL Procedure Proposal 9 Set the ME to mid channel in the GSM TX band Set the delay setting in default mode that is no delay Wait approximately 300 us to 400 us to allow the PLL to lock Measure the RMS phase error A threshold value of gt 20 deg indicates that the PLL is running in the forbidden time region Save the RMS phase error result locally Step up the delay setting according to Table 10 1 below Repeat from step 4 Choose delay setting that gives maximum distance to the consecutive field of corrupted RMS phase error values in the vector Store delay setting both to the Mod Delay and to the DirMod Mod Delay 10 Reset the radio Table 7 1 Delay Settings for the MOD A 202 7 CALIBRATION
93. Table 7 1 SUB_IF2 Sub Mode Select2 See Table 7 2 GND Ground BST Indicate the start of Vertical Blank D15 Bi Direction Data Bus D14 Bi Direction Data Bus D13 Bi Direction Data Bus D12 Bi Direction Data Bus D11 Bi Direction Data Bus D10 Bi Direction Data Bus D9 Bi Direction Data Bus D8 Bi Direction Data Bus _WR Write Strobe Signal Active low MAIN_CS Main Chip Select Active low RS Select Register High Control Low Index Status MAIN IF1 Main Mode Select1 See Table 7 1 ID MAKER Connected to Ground SUB 1 Sub Mode Select See Table 7 2 RD Read Strobe Signal Active low Table 3 2 5 Interface between LCD module and FPCB in FPCB 51 3 Technical Brief 3 2 6 Main amp Sub LCD Backlight Illumination There are 5 white LEDs for the Main LCD and the Sub LCD Backlight circuit which are driven by the Charge Pump LTC3206EUF I2C is used for the backlight brightness control GPIO 46 enables the Charge Pump IC VBATI R739 CPO LTC FLASH mes 711 2 2 C708 22u R740 0 2 CPO LTC LCDBL eb amp 38 8 Qu cele 58 GRO Pi 55555 VIN 22 MAIN1 21 LCDBL1 7 MAIN2 20 LCDBL2 Dvcc MAIN3 19 LCDBL3 U701 23 LCDBL4 LTC3206EUF AUX1 1 LCDBL5 10 SUB1 2 B
94. Two data signals are used for data one in each direction The PCM clock signal operates at frequencies as high as 1 MHz The word length of the audio data can be 8 or 16 bits Furthermore the PCM interface has a function known as which is an addressing scheme used to have more than two devices talking on the bus To add this function the data pins have to be bi directional Additionally the position of the audio data relative to the frame sync pulse must be selectable During the periods within a frame that a device is not transmitting audio data it must put both PCM data signals in a high impedance state to allow other devices access D Master Clock and Clock Request Interface The master clock MCLK is a 13 MHz signal used as the high precision clock signal for the Bluetooth module The signal can be switched on and off by the platform The master clock request CLKREQ is used by the Bluetooth module to ask for the master clock If the Bluetooth module asserts the signal high it gets the master clock The other alternative for the Bluetooth module is to set the clock request output to high impedance state indicating that it does not need the master clock The Bluetooth module receives the master clock if other parts of the chipset request it E Low Frequency Clock Interface The low frequency clock signal RTCCLK is used by the Bluetooth module as a low power clock The clock is used in different Bluetooth modes like sn
95. WE LN Fi vcc2 PDIC2 LCDRS 1 95 LCDCSX MAIN change to LCD_VSYNC_OUT TP601g 8903 NA PDIC4 LCDRDX 2725 D MEM BE1 NS F3 nus Wis BE BL SLEEP EN GPIO46 PDIDO PDIDO VDIG RLB las plod Pblbt A 18 PDID2 84 vesr DACCLK 28 DaccLK PDID3 PDID3 Ne gt LEH vsss vecao 13 DACDAT DACDAT PDID4 PDID4 2601 vsss DACSTR Q0 Pi pAcsTR poibs PDIDS uere bk s voc ADCSTR ADCSTR Pblb Poms ax 15 nei i 15 Pblb7 lt E vesz p vec ns 17 315 I2CCLK DRIVER USBDM I2CSDA I2CDAT vsso F_VPP USBPUEN USBPUEN x CIVSYNC HSSLRXCLK 0 08 CIHSYNC CIHSYNC lt 122 MEGA HSSL HSSLRX HSSLAX CIRES CIRES N VGA id HsSLTXCLK Nal cibo ies doc HSSLTX cibi jo 100K iu cm2 woa MERE Ea Em posses eem 8505 03552555229222255 i 35 5 n 333552500000 0 000008023333 00000100000 ins d 5 88882299990000000
96. Z Y5V HD 1608 R TP C512 C513 CAP CHIP MAKER ECZH0003501 1 uF 6 3V X5R 1608 R TP C517 CAP CERAMIC CHIP 0004903 1 uF 6 3V Z Y5V 1005 R TP CAP CERAMIC CH 0004903 1 uF 6 3V Z Y5V 1005 C519 C524 C525 CAP CERAMIC CHIP 0000126 68 pF 50V J NPO TC 1005 R TP CAP CERAMIC CH CAP CERAMIC CH ECCH0002003 33 nF 16V 1005 R TP 0002003 33 nF 16V 1005 R TP C526 C528 CAP CERAMIC CH 0002003 33 nF 16V 1005 R TP C529 CAP CERAMIC CHIP 0000126 68 pF 50V J NPO TC 1005 R TP 0004903 1 uF 6 3V Z Y5V 1005 R TP C554 C555 CAP CERAMIC CH 0000110 10 pF 50V D NP0 TC 1005 R TP C558 CAP CERAMIC CHIP 0000122 47 pF 50V J NPO TC 1005 R TP 0000122 47 pF 50V J NPO TC 1005 R TP 559 560 0002003 33 16 1005 561 0000168 0 1 uF 16V Z Y5V HD 1005 R TP CAP CERAMIC CH 0004903 1 uF 6 3V Z Y5V 1005 R TP C562 C563 CAP CERAMIC CHIP 0005705 10 uF 6 3V X5R 2012 R TP C564 CAP CERAMIC CHIP 0005705 10 uF 6 3V X5R 2012 R TP C566 CAP CER
97. ang AZ xooc A8 AS NCB IRB wd GNDBUF IRA NC3 REON 04 H cs ud PS 55 ONDPLL 8588 985 DATA 7 0 5222228 822852 zooooon 2900220 171 4 TROUBLE SHOOTING 2 Jan 84 Reading Floppy Disk Drive 11 34 16 lleCroy ps 80 k 1 i 2 ys 1 1 Os me 53 B 1 1 65 5 3 2 DOCK ju DC 1 52 V 4 2 005 amp 3 H oFF 1 evts STOPPED Figure 4 21 5 GSM DCS PCS Tx MODE signal Check Mode A B C D signal at 6 Resoldering MODE block R423 R424 R411 R410 Check if there is any Major difference Refer to Figure 4 21 5 Check GSM RF Transceiver Output power at Redownload SW Check GSM DCS Tx Balun Resoldering Tx Balun output power at 4 4 See Next page to check Tx path 172 4 TROUBLE SHOOTING GSM PAM Check gt 125222525 GSM Tx C410 Vapc C406 DCS Tx 5 C409 BLM15AB601SN1J L401 PAREG gt R402 C401 R401 _ 402 IOUT gt di 1K 100p 777 C406 C405 33p 100p la Jajo 7 _ 58 2 C410 i gt 5 GSM TX 3l EGSM OUT DCS PCS IN P C411 DCS TX lt Y Y Y 15 pcs cs our EGSM IN lt 2 2 R403 i 409 ia TX_ENA
98. change to Cb OUT FA 8 7 g 36 A A IND SINK lt m Bam L CT Rm2 12 2 35 UN S mour Leownx Bm RT 35 Q Nou INOUT LCDCSX MAIN 792 0 4 L our imour a2 t LCDCSX SUB I NA 0 17 RIO sia D I C735 CIHSYNC Y RISI 18 CANO ICVEZTTGAETSORTOIFR D I C736 19 8704770 m e wow en yam E 8 em LCDBL2 CIT X7 KEYIN2 LCDBL3 ers Lrc 9 180818 LCDBL gt 25 8 8 dr C731 014 ca C733 014 PMST3904 J WSTR lt lt X 777 777 8 8 218851888 58188 LCD CAMERA CONNECTOR L 22 92 NA RRBBBRBSRRBERBBBBBBEBBRIJD S 23522 E 888288888338898989989988 amp 54 E 18 222225255552 2498584 VCORE Gig 859888 918 Tae rus 58 D 8 02 81 ura xx 04 88 emuo EMIF DS b 06 07 Bar wanomir 5 KNATTE vora IO Connector 24Pin EE xm mr 09 8 WCLK BIZ RADIO EMIF 010 255 p z oo WDAT 1812 RADIO DAT 011 58 1 DTMS
99. company s employees agents subcontractors or person working on your company s behalf can result in substantial additional charges for your telecommunications services System users are responsible for the security of own system There are may be risks of toll fraud associated with your telecommunications system System users are responsible for programming and configuring the equipment to prevent unauthorized use The manufacturer does not warrant that this product is immune from the above case but will prevent unauthorized use of common carrier telecommunication service of facilities accessed through or connected to it The manufacturer will not be responsible for any charges that result from such unauthorized use B Incidence of Harm If a telephone company determines that the equipment provided to customer is faulty and possibly causing harm or interruption in service to the telephone network it should disconnect telephone service until repair can be done A telephone company may temporarily disconnect service as long as repair is not done C Changes in Service A local telephone company may make changes in its communications facilities or procedure If these changes could reasonably be expected to affect the use of the phones or compatibility with the network the telephone company is required to give advanced written notice to the user allowing the user to take appropriate steps to maintain telephone service D Maintenance Limitation
100. for Radio ASIC Vincenne Ingela N405 1503 201 77 es Check Point VDDB gt Check the Vincenne No Yes Common Input Power is OK See The Next Part 138 4 TROUBLE SHOOTING 4 16 5 Checking Regulator Part V wivi B EXTLDO R103 V wivi A R106 3 LP3981ILD 2 8 Regulator Figure 4 16 8 Regulator Block gt gt V TXTLDO gt gt VBATI gt gt M gt gt V B C113 114 10 112 T 0 033u Figure 4 16 9 Regulator Circuit Diagram Check Point 2 or 3 R106 R108 To Check Regulator Output Voltage Point 4 High Change the Board Check EXTLOD Point 4 To Check regulator enable signal Regulator Circuit is OK Change the Regulator See the next Page 139 4 TROUBLE SHOOTING 4 17 Checking VCXO Block The reference frequency 13MHz from B201 Crystal is used WCDMA TX part and BB part Therefore you have to check below 3 point pem NIA j L Check 2 ii S m m U T ENE R R I 1 L LJ LI LI L Check 1 Figure 4 17 1 Bottom Place 140 4 TROUBLE SHOOTING Check 1 Crystal part If you already check this crystal part you can skip check 1
101. gt D AUXO1 gt Decoder Volume N PCM 8 16 PCM 8 16 1 RX1 LP DAC1 RX PGA1 OG p ou PS E Sidetone Analog Loop Analog Loop Loop from TX2 from TX1 1 MIC1to Figure 3 4 4 Voice Call Downlink Scheme 59 gt Auxiliary Output 1 3 Technical Brief The voice decoder accepts a serial input stream of linear PCM coded speech The receive band pass filter is the next step in the CODEC receive path Following the filter is the DAC followed by a PGA enabling to adjust or trim the circuit in the product for different sensitivity of the earphone and spread in the RX path The final step in the receive path is the earphone amplifier and the auxiliary output The auxiliary audio amplifier is intended to drive low impedance headphones The earphone amplifier and the auxiliary audio outputs can be powered down muted via 12 Both the earphone driver and one of the auxiliary drivers can simultaneously provide an output signal during voice decoding Receiver Mode Earphone amplifier BEARP N Port Receiver 32Q Loud Speaker Video Telephony Mode Auxiliary audio amplifier gt AUXO1 2 SURROUND AUDIO PROCESSOR NJM2705 gt TJATTE2 Analog S W NLAS4684 gt AUDIO AMP TPA2005D1 Speaker 8Q Headset Mode Auxiliary audio amplifier AUXO1 2 gt SURROUND AUDIO PROCES
102. instruments and initializes them automatically The result of checking and initializing instruments was shown like Figure7 6 XCALMON supports three functions Calibration of EGSM 900 DCS 1800 and WCDMA band Instrument Agilent8960 Tektronix PS2521G control UART communication with U8550 mobile phone XCALMON has three windows and each window support different function TP Integrated Test Program starting window using production loader Calibration tree window Command window which supports interactive ITP commands like Hyper terminal XCalMon Window E 18 EW File Edit View Window Help 18 a m e mc r t Display program information version number and copyright Figure 7 5 XCALMON Window 219 7 CALIBRATION 7 4 2 XCALMON Icon Description A DOS Window Icon When you click the DOS window icon then you should see the ITP command window like DOS window of DOS operating system In ITP command window you should communicate with U8550 mobile phone which is running in ITP mode For example if you will enter command VERS and enter the return key you should get the response of the present running ITP version information from U8550 mobile phone EN File Edit View Window Help 18 xi oh vers VERS 831226 1357 INI17 125 77 7 PLATINUM TP 16H 2 MODE 0 6 0 2 OK Ready Figure 7 6 XCALMON ITP Command Window
103. potrt o Aster Arenes Seth T UM T TX Saw lt _ 8 Figure 3 6 1 Block diagram of RF part Starting at the antenna end an antenna switch provides switching capability needed for four frequency bands 900 1800 1900 and 2100MHz For the W CDMA part duplexer is included to facilitate the simultaneous transmission and reception required for the FDD mode The main components in the radio are Wopy W CDMA receiver ASIC Wivi W CDMA transmitter ASIC Ingela GSM GPRS transceiver and two power amplifiers The mixed signal circuit ASIC Vincenne provides power supply for the main RF components The control flow for the Radio is shown in Figure 3 6 2 76 3 Technical Brief WCDMA RF ASIC Ctrl Wopy WANDA WCDMA PA Wivi Antenna Antenna Switch Ctrl Switch Herta GSM RF asic ctrl A GSM DCS GSM DCS Band select PA Ctrl Vincenne Ctrl DAC Ctrl Indirect WCDMA PA Ct GSM PA Pwr Ctrl Vincenne VCXO Ctrl DAC Ctrl Indirect WCDMA PA Pwr Ctrl Figure 3 6 2 RF control signal flow diagram The MARITA the main processor controls the overall radio system In the GSM GPRS air interface mode this control is handled via direct interfaces to individual RF components The MARITA the main processor also handles the antenna switch mechanism for selection of mode In the W CDMA mode the
104. second position Ak 1 set to Oxffff to flag that the table is calibrated Position 2 to 5 should be set to zero 12 Perform the offline calculations and check the requirements A 217 7 CALIBRATION 7 3 6 Baseband Calibration Item A Battery Voltage Calibration Purpose Calibrates the voltage table for the power management functionality Some voltage measurements in the remaining test will be done with calculated voltage levels from this test Procedure Proposal Send the command LVBA 0 to reset local values in Test Program Set voltage on VBATT to 3 20 V Send the command LVBA 5 0x140 to read the low voltage level from ADC Set voltage on VBATT to 4 10 V Send the command LVBA 5 0x19A to read the high voltage level from ADC Send the command LVBA 1 to store local values into global data Send the command LVBA 3 to view and record values stored in global data O WD Voltage Level VBATT V Table 10 7 Battery Voltage Calibration Limits 218 7 CALIBRATION 7 4 Program Operation 7 4 1 XCALMON Program Overview When you try to calibrate the U8550 mobile phone you should make a configuration of calibration environment like Figure7 1 And if you finish making configuration please execute the XCALMON program Running the XCALMON program you should show XCALMON program window like Figure7 5 If XCALMON program would be executed it checks the connection of
105. the output of the LNA the signal is fed to the input of a RF SAW filter and then appears at the differential output of the filter The differential output of the RF SAW filter is connected to the differential mixer input and the received signal is down converted to a 190MHz IF frequency with the RFLO signal by the mixer At 190MHz the signal is filtered in a differential input and output IF SAW filter with the approximate bandwidth of 4MHz and then again the signal is fed to Wopy W CDMA Receive ASIC this time to the differential IF input which also has a LNA From the 190MHz the signal is mixed down to base band and which represented signals using the IFLO signal Finally the signals are filtered in low pass filters and amplified in baseband VGAs The and represented signals appear at the output of Wopy W CDMA Receive ASIC as differential voltages The large signal gain provided by the processing steps from the antenna down to base band gives a DC offset at the outputs of Wopy W CDMA Receive ASIC To eliminate this there are DC offset compensation loops included one in the of each of the and the signals A IFLO Section The balanced IFLO signal from an external IFVCO drives the divider to provide qaudrature LO signals to the RxIF mixers The LO buffers amplifies the signal to a suitable amplitude and DC level to drive the RxIF mixers IFLOBUFI To IFLOI DIVIDER From IFLO To IFLOQ
106. to the camera module but they are not part of the CDI block The I2C is used to set up and control the camera module The camera module 2 lines must go high impedance when the supply is removed from the camera The I2C commands needed to control the camera as well as the functional behavior of the module are also different for each implementation The ON signal GPIO is used to power on the camera from Standby or Off mode implementation dependent This signal must be held low when the mobile equipment is powered down and during the mobile equipment reset period The GPIO pin can also be an input or high impedance during mobile equipment reset and start In this case it must have pull down to ground The camera module reset signal is an output to the camera module 45 3 Technical Brief 3 2 3 Camera amp Camera FPC Interface PDIRES N LCDRESX LCDCSX SUB oe a LCDWRX LCD I F A PDIC2 LCDRS PDIC3 LCDCSX MAIN LCDRDX e PDIDO PDID1 PDID1 y A PDID2 PDID2 7 PDID3 PDID3 6 c lt gt gt PDID4 PDID4 R610 601 PDIDS PDIDS PDID6 PDD6 33K 1 2K PDID7 PDID7 lacscL I2CCLK DRIVER I2CSDA I2CDAT CIPCLK lt CIPCLK CiVSYNC CIVSYNC CIHSYNC CIHSYNC MEGA EN CIRES N CIRES N VGA Cibo usi nee
107. 00 uF 6 3V STD R TP 6 C585 6 C587 CAP CERAMIC CHIP 0000149 3 3 nF 50V K X7R HD 1005 R TP 6 C589 CAP CERAMIC CHIP 0000151 4 7 nF 25V K X7R HD 1005 R TP CAP CERAMIC CHIP 0005705 10 uF 6 3V X5R 2012 R TP 6 C590 6 C592 CAP TANTAL CHIP MAKER ECTZ0005501 100 uF 6 3V STD R TP 6 C593 CAP TANTAL CHIP MAKER ECTZ0005501 100 uF 6 3V STD R TP CAP CERAMIC CH 0000168 0 1 uF 16V Z YSV HD 1005 R TP 6 C601 6 C602 CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C603 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP o CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5SV HD 1005 R TP 6 C604 6 C605 CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5SV HD 1005 R TP 6 C606 CAP CERAMIC CHIP 0000137 330 pF 50V X7R 1005 R TP CAP CERAMIC CH 0000115 22 pF 50V J NPO TC 1005 R TP 6 607 6 608 0000115 22 pF 50V J NPO TC 1005 R TP 6 609 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z YSV HD 1005 R TP ERE CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5SV HD 1005 R TP C610 C611 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP C612 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C613 CAP CERAMIC CHIP
108. 0000143 1 nF 50V K X7R HD 1005 R TP C614 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP o C615 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 274 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark 6 C616 CAP CERAMIC CHIP 0000182 0 1 uF 10V X5R 1005 R TP C617 CAP CERAMIC CHIP 0000182 0 1 uF 10V X5R 1005 R TP CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 6 C618 6 C619 CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C620 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C621 6 C622 CAP CERAMIC CH ECCH0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C623 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C624 6 C625 6 C626 CAP CERAMIC CHIP CAP CERAMIC CHIP ECCH0000168 0 1 uF 16V Z Y5V HD 1005 R TP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 627 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 C628 CAP CERAMIC CHIP CAP CERAMIC CHIP ECCH0000168 0 1 uF 16V Z Y5V HD 1005 R TP o 6 C629 6 C630 CAP CERAMIC
109. 0000280 100 ohm 1 16W J 1005 R TP ERE 0000160 180K ohm 1 16W F 1005 R TP 6 R2135 6 R2138 ERHY0000280 100K ohm 1 16W J 1005 R TP 6 R215 RES CHIP ERHY0000203 10 ohm 1 16W J 1005 R TP HE ERHY00007 14 51 ohm 1 4W J 2012 R TP 6 R2150 6 R216 ERHY0000261 10K ohm 1 16W J 1005 R TP 266 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark R217 RES CHIP ERHY0000261 10K ohm 1 16W J 1005 R TP R2171 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP FILTER BEAD CHIP 5 0007103 75 ohm 1005 CHIP BEAD 300mA FILTER BEAD CHIP 5 0007103 75 1005 BEAD 300mA 2191 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP RES CHIP 0000280 100K ohm 1 16W J 1005 R TP RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 2196 5 0000226 220 ohm 1 16W J 1005 R TP 0000201 ohm 1 16W J 1005 R TP R2197 R220 HY0000203 10 ohm 1 16W J 1005 R TP 6 R2205 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 6 R221 RES CHIP 0000203 10 ohm 1 16W J 1005 R TP 6 R2225 RES CHIP ERHY0008701 10 22 ohm 1 4W J 2012 R TP EE 0000201 0 ohm 1 16W J 1005 R TP 6 R2236 6 R2237 0000201 1 16 1005 6 2238 5
110. 0002000 4040000000000000000000 58922000 gg 77 R2244 R2245 1 EHE CAMERA P 777 NA NA 88 JTAG gt meca jg 777 777 gt gt MEGA E E sm oh G 1 gt TF DETECT MARITATEMU1 T ia anon 8607 8608 TF 618 nm 5 s pat FEM 4 ma quud S C617 i 88 n NA NA 8 8 59 77 J R2246 R2247 77 m 77 Z 7 Trans Flash gt I2CCLK H 7 Engineer Jeongseok Lee LG ELECTRONICS INC Mobile Handsets R amp D Center HW Group Development Lab 6 RED UE Sus U8550 spfy0106301 1 1 DOC CTRL pry 1218A MARITA MEMORY BLUETOOTH Page 6 of 7 Baseband Part 2 of 3 Changed by Date Changer Drawing Ruman Ec Tuesday September 04 2003 1 12 234 8 CIRCUIT DIAGRAM
111. 02 UV COATING 5 MCCEO0 CAP RECEPTACLE 021202 URETHANE SPRAY 00 CAP MULTIMEDIA CARD MCCG0003102 UV COATING P um P reer MDAGOO DECO FRONT 012501 pos 37 38 45 46 42 MDANOO DECO SPEAKER 006802 Green Lt Meee MPFCOO PLATE FACE 0070301 5 MSGY00 STOPPER MSGYO0011102 00 TAPE DECO 0094801 5 TAPE DECO MTAA0094901 Without Color 5 FILM INMOLD BFAA0032102 BLACK Without Color N Without Color 4 AWAZ00 WINDOW ASSY AWAZ0007102 WINDOW 5 00 FILM INMOLD BFAA0029201 A Transparent NDOW LCD MWACO054301 PMMA INMOLD 5 NDOW LCD SUB MWAF0027901 PMMA TRANSPARENT INMOLD SILK Silver 4 GMEYOO SCREW MACHINE BIND GMEYO0009201 1 4 mm 3 5 mm MSWR3 BK HEAD D 2 7mm 20 63 77 252 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Part Number No Level Description Specification Color Remark CAP SCREW 0054501 SILICON RUBBER FOLDER LIGHT Gray 4 MCCHO01 CAP SCREW MCCHO0054601 SILICON RUBBER FOLDER LEFT MCCH02 CAP SCREW 0054702 21 CAP SCREW 0054802 MGAZO1 GASKET MGAZ0022702 MGAZO2 GASKET MGAZ0022703 Green Green 2
112. 03 Check the power at the N302 C307 with probe Refer to Graph 4 20 10 Check 6 About 6dBm The N302 has any problem You have to check PAM block The N304 will be not operated Change the board 158 4 TROUBLE SHOOTING 4 20 5 Checking PAM Block Top VCCWPA WDCDCREF C302 C310 from Rosaili Rosaili je Ul Comp R301 Wivi input WPAREF Duplexer Output C307 R306 C111 Figure 4 20 12 Test point 159 4 TROUBLE SHOOTING WCDMA TX 5888 8222 77 22 125 5 ESI 3EAR1 950G01 T 777 VCCWPA gt N302 RF9266 o GNDS VDETECT lt VBATI SND6 DET SND7 GND2 R307 7g VCC21 VCC BIAS2 VCC22 BIAS1 16 4 0 01 GND1 17 3 777 VCTRL2 R306 2 VCTRL1 WPAREF 19 oe 1 2 2z z cat C310 2 10p c 9 22 77 8 amp 777 777 VBATI N301 WDCDCREF gt 18202 sync 81 comp 77 gt A3 c2 3838 our L304 ca R303 R301 REF a gt WPOWERSENSE 33K 39K Bs GND PGND C304 1301 100 iou 2012
113. 04 GASKET MGAZ0022701 0011201 MIDZOO MIDZ0056801 Gold Gold Without Color Without Color MIDZO2 INSULATOR MIDZ0075001 4 00 KEYPAD DIAL 0012602 MLACOO LABEL BARCODE 0003401 EZ LOOKS user for mechanical Without Color Green B MSGB00 STOPPER HINGE MSGB0010901 0084901 01 0085001 AB ADCAO0 DOME ASSY METAL ADCAO0035201 GMEYOO SCREW GMEY0009201 FOLDER MOD BUTTON DOME ASSY 1 4 mm 3 5 mm MSWR3 BK B HEAD D 2 7mm Black 20 63 77 200 CAP MCCZ0008903 White 4 00 CONTACT ANTENNA MCIA0014801 PRESS 0 15 MCJNOO COVER REAR 0037501 White MDADOO DECO CAMERA 00013002 ki iiec di wawas d MGADOO GASKET SHIELD FORM MGAD0096701 MAIN CONNECTOR MGADO1 GASKET SHIELD FORM MGAD0096901 MHGB00 HOLDER CARD 0001401 MLABOO LABEL A S MLABO0000601 LCD RIGHT HUMIDITY STICKER Without Color Without Color MLANOO LABEL QUALCOMM 0000601 Black 95C Transparent 253 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark 4 200 PAD 00 TAPE DECO
114. 1 16W J 1005 R TP 0000201 ohm 1 16W J 1005 R TP R576 R577 HY0000201 ohm 1 16W J 1005 R TP R578 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP RES C HIP ERI 0000201 0 ohm 1 16W J 1005 R TP 579 580 581 RES CHIP RES C HIP EC ERI CH0002003 0000201 0000201 33 nF 16V 1005 R TP 0 ohm 1 16W J 1005 R TP ohm 1 16W J 1005 R TP R582 R583 CAP CERAMIC CHIP CCH0002003 33 nF 16V 1005 R TP R584 RES CH 0000201 0 ohm 1 16W J 1005 R TP PT R585 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP R586 RES CH 0000280 100 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 587 588 0000201 ohm 1 16W J 1005 R TP R589 RES CHIP ERHY0000280 100 ohm 1 16W J 1005 R TP 0000259 8 2K ohm 1 16W J 1005 R TP R590 R591 0000282 120 ohm 1 16W J 1005 R TP 592 RES CHIP 0000282 120 ohm 1 16W J 1005 R TP 0000254 4 7K ohm 1 16W J 1005 R TP R594 R595 HY0000261 10K ohm 1 16W J 1005 R TP R596 RES CHIP ERHY0000282 120 ohm 1 16W J 1005 R TP 0000282 120 ohm 1 16W J 1005 R TP R597 R598 0000254 4 ohm 1 16W J 1005 R TP 601 RES CHIP 0000254 4 7K ohm 1 16W J 1005 R TP 0000280 100K
115. 142 4 TROUBLE SHOOTING Check 3 13MHz at BB part Figure 4 17 8 Test point 13MHz at BB part gt MCLK L208 82 C223 0 01 777 8215 10 6225 T 22 77 C230 R216 R212 85 T lt VCXOCONT ux 47p 330p 10K 1K Sg _ 234 B10 pee VCCREF 10 XOIA 510 Figure 4 17 9 Schematic 13MHz at BB Part 500MS s Sample t 2 Coupling Impedance Mean 2 445V D ClFreq 12 90344MHz AC U Low signal GND t M Toons Chi X 620mv Q 5 50 Bandwidth Somy Position Offset Deskew Probe Full div 4 90 div 0s Functions Figure 4 17 10 13MHz at N201 C1 143 4 TROUBLE SHOOTING VCXO part has a problem Changing B201 Check B201 3 Refer to graph 4 17 4 Checking 1 13MHz at VCXO Check N304 B1 amp C1 Refer to graph 4 17 7 Checking 2 13MHz at TX part N304 has any problem Changing RF board Yes Check N304 C1 Refer to graph 4 17 10 Checking 3 13MHz at BB VCXO part is O K Check next stage N 304 has any problem Changing RF board 144 4 TROUBLE SHOOTING Gaz a 4 18 Checking Ant SW Module Block ANTSW2 ANTswo ANTSW1 LMSP43MA 288 ANTSW3 Figure 4 18 1 Antenna Switch Block Bottom FL101 LMSP
116. 15C 8960 setting TP Command pctr 3 4 1 pdin 2 3 4 pdou z 3 4 1 brst 1 VBT C646 Center Frequency gt 2441MHz 500kHz Itex 2 3 LTCXzresponse value OK dacc 0 2 response value 1 1 1 2 Btsr 2 MCLK C643 RTCCLK C642 Bluetooth chip Output C647 Check voltage level at No VBT C646 Check BT regulator Block with Oscilloscope Yes No Check frequency at Check VCXO block MCLK C643 with Oscilloscope Yes IE Check Marita Block D601 Check frequency at C RTCCLK C642 with Oscilloscope Yes No Over Check Power lever 40dBm Change BT Chip U604 at Bluetooth chip Output C647 with Oscilloscope Yes Check Next Stage 184 5 BLOCK DIAGRAM 5 1 GSM amp WCDMA RF Block UMTS PAM N302 GSM Bluetooth U604 Figure 5 1 1 RF Block Diagram 185 5 BLOCK DIAGRAM 5 BLOCK DIAGRAM Block Ref Name Part Name Function Comment Common FL101 LMSP43MA 288 Switch Band select W101 KMS 507 Test Connector Calibration etc B201 TSX 8A_13MHz Crystal Reference 13M FL102 DFYY61G95LBNBC TT1 Duplexer TRX N201 LZT 108 5323 Receiver RX FL201 SAFEH2G14FAOFOOROO RX PF Filter RX 2201 TMXU753 RX IF Filter RX N301 MAX1820ZEBC DC DC TX N302 RF9266 PAM TX N303 ESMI 3EAL1 95G01 T Isolator
117. 1G 12 75GHz 100k 880MHz 1710M 1785MHz 1785M 12 75GHz 100k 880MHz 880M 915MHz 880M 915MHz 915M 1000Mz Idle Mode 1G 1 71GHz 915M 1000MHz 1G 1 71GHz 1 71G 1 785GHz 1 71G 1 785GHz 1 785G 12 75GHz 11 1 785G 12 75GHz 2 PERFORMANCE MS allocated Channel Radiated GSM 1GHz 1G 4GHz DCS PCS 30M 1GHz 1G 1710MHz 1710M 1785MHz 1785M 4GHz Spurious Emission Idle Mode 30M 880MHz 880M 915MHz 30M 880MHz 880M 915MHz 915M 1000Mz 915M 1000MHz 1G 1 71GHz 1 71G 1 785GHz 1G 1 71GHz 1 71G 1 785GHz 1 785G 4GHz 1 785G 4GHz Frequency Error Phase Error 0 1ppm 5 RMS 0 1ppm 5 RMS 20 PEAK 20 PEAK Frequency Error Under Multipath and Interference Condition 3dB below reference sensitivity RA250 200Hz 3dB below reference sensitivity RA250 250Hz HT100 100Hz HT100 250Hz TU50 100Hz 150Hz TU50 150Hz TU1 5 x200Hz Due to modulation Output RF Spectrum Due to Switching transient 0 100kHz 0 100kHz 200kHz 250kHz 200kHz 250kHz 400kHz 400kHz 600 1800kHz 1800 3000kHz 600 1800kHz 1800 6000kHz 3000 6000kHz 26000kHz 26000kHz 400kHz 400kHz 600kHz 600kHz 1200kHz 1800kHz 24dB 12
118. 2 Pout 2 Extract A2 and B2 Do a curve fitting for the high gain region where RFBias 0 of the highgain region Position B1 Pout A1 Extract A1 and B1 Save 1 2 B1 B2 P1 and P2 TX GAIN ID 45 1 0028 54 919 y 0 090 20 401 40 35 30 HighGain Low Region HighGain Position HighRegion LowGain below dB Enea owGain T T T T T 60 50 40 30 20 10 0 10 20 30 Power dBm Figure 7 2 Example of Position versus Power and Calculated Equations 214 7 CALIBRATION F RX LPF Bandwidth Calibration Purpose This procedure calibrates the LPF bandwidth The bandwidth of the channel filters will affect system parameters as reception sensitivity and adjacent channel selectivity The procedure also verifies that the IF filter is properly matched AGC loop E power output1 ADC detector IIR y N 5 q In P controller no Figure 7 3 Block Diagram Parameter Ak Output1 and Pref Procedure Proposal Feed a CW carrier at 2140 MHz with a power of 60dBm into the antenna connector Set UE in RX mode on 10695ch Set the UL and LL to minimum GLNA is forced to high gain mode Set RF 2110 and LPBW to 8 that is LPQ LPBW 8 Get Ak output2 from N slots Calculate Average Ak Ak IB ac
119. 2 pF 50V J NP0 TC 1005 R TP 6 428 6 429 CAP CERAMIC CH 0000186 33 pF 50V J NPO 1005 R TP 0000111 12 pF 50V J NPO TC 1005 R TP 6 C430 CAP CERAMIC CHIP 0000901 2 2 pF 50V NPO 1005 R TP CAP CERAMIC CH 0000186 33 pF 50V J NPO 1005 R TP 6 C431 6 C432 CAP CERAMIC CH 0000901 2 2 pF 50V NPO 1005 6 C433 CAP CERAMIC CHIP 0000115 22 pF 50V J NPO TC 1005 R TP CAP CERAMIC CH 0000110 10 pF 50V D NPO TC 1005 R TP 6 C434 6 C435 CAP CERAMIC CH 0000175 2 7 pF 50V B NP0 TC 1005 R TP 6 C436 CAP CERAMIC CHIP 0000175 2 7 pF 50V NP0 1005 R TP o INDUCTOR CHIP ELCH0001033 1 5 nH S 1005 R TP PBFREE 6 C437 6 C438 CAP CERAMIC CH 0000110 10 pF 50V D NP0 TC 1005 R TP 6 C439 CAP CERAMIC CHIP 0000155 10 nF 16V K X7R HD 1005 R TP CAP CERAMIC CH 0000115 22 pF 50V J NP0 TC 1005 R TP 6 C440 6 C441 CAP CERAMIC CH ECCH0000143 1 nF 50V K X7R HD 1005 R TP 6 C442 CAP CERAMIC CHIP 0000143 1 nF 50V K X7R HD 1005 R TP ERE CAP CERAMIC CH 0000155 10 nF 16V K X7R HD 1005 R TP 6 C443 6 C444 6 C445 CAP CERAMIC CHIP CAP CERAMIC CH P 0000146 1 8 nF 50V K X7R HD 1005 R TP 0000144 1 2 nF 50V K X7R HD 1005 R TP 6 C447 CAP CE
120. 3 Technical Brief 3 4 7 Video Telephony This section provides a description of the Video Telephony functions MARITA Digital Baseband ASIC Videp Telephony RX VINCENNE Audio Mixer Audio and Power Management ASIC TJATTE2 C MIC 0 679 HEADSET Analog S W Speaker AUDIO AMP Speaker Videp Telephony TX By pass Figure 3 4 8 Video Telephony Scheme Video Telephony Mode has same paths with Loud Speaker Mode 64 3 4 8 Audio Part Main Components 3 Technical Brief There are 8 components in U8550 schematic Diagram Part Number marked on U8550 Schematic Diagram ITEM Part Name Part Number Speaker EMS1514TLW1P C MIC OBG 415844 X503 3D IC NJM2705 U507 Audio AMP TPA2005D1 U504 U505 Headset AMP LM4809LD U509 TJATTE2 4025 520 N504 Ear JACK C 1827541 CN502 A TJATTE2 Description Analog Switch NLAS4684 Table 3 4 5 Audio Component List U508 The TJATTE2 is a 6 channel RC low pass filter array that is designed to provide filtering of undesired signals in the 800 2700 MHz frequency band In addition the TJATTE2 incorporates diodes to provide protection to downstream components from Electrostatic Discharge ESD voltages as high as 8 kV DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION MICN GND CCO MICN int MICP GND A
121. 43MA 288 GSM900 RX 10 GSM1800 VDD GSM1900 M vci WCDMA 5 vc2 VCG 12 sa x 12 GSM900 TX ANTSWO gt 55555 serre ANTSW1 77 ANTSW2 D ANTSW3 gt C110 C107 C106 C109 C105 C108 C102 C104 0 01u T t0p 0 01 0 01u Figure 4 18 2 Schematic of Antenna Switch Block Bottom 145 4 TROUBLE SHOOTING ENS 4 19 Checking Antenna Switch Block input logic 4 19 1 Mode Logic by TP Command WCDMA amp EGSM Rx EGSM Tx 1 ANTSW1 102 Low ven l 15 s 1 ANTSW2 Y Nas 2 PSI S sq 4 ANTSW3 Lo en 1 1 maximum 8 12 V maximum 1 8 89 V maximum 2 8 09 V maximum 2 9 09 V maximum 3 8 11 V maximum 3 2 70 V DCS Tx DCS Rx D oS SSS 1 i 1 00
122. 50V K X7R HD 1005 R TP CAP CERAMIC CH 0000155 10 nF 16V K X7R HD 1005 R TP C337 C401 CAP CERAMIC CH ECCH0000130 150 pF 50V J SL TC 1005 R TP C402 CAP CERAMIC CHIP 0000128 100 pF 50V J NP0 TC 1005 R TP 0000115 22 pF 50V J NPO TC 1005 R TP C403 C404 CAP CERAMIC CH 0000115 22 pF 50V J NPO TC 1005 R TP C405 CAP CERAMIC CHIP 0000128 100 pF 50V J NPO TC 1005 R TP CAP CERAMIC CH 0000186 33 pF 50V J NPO 1005 R TP C406 C408 CAP CERAMIC CH 0000128 100 pF 50V J NPO TC 1005 R TP C410 CAP CERAMIC CHIP 0000186 33 pF 50V J NPO 1005 R TP INDUCTOR CHIP ELCH0005001 2 2 5 1005 R TP C411 C412 CAP CERAMIC CHIP 0000186 33 pF 50V J NP0 1005 R TP C420 CAP CERAMIC CHIP 0005705 10 uF 6 3V X5R 2012 R TP C422 CAP CERAMIC CHIP 0005705 10 uF 6 3V X5R 2012 R TP C423 CAP CERAMIC CHIP 0000115 22 pF 50V J NPO TC 1005 R TP C424 CAP CERAMIC CHIP 0000155 10 16 7 1005 261 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark 6 C507 CAP CERAMIC CH P 0000122 47 pF 50V J NPO TC 1005 R TP C514 CAP C
123. 513 DIRMODO DIRMOD1 DIRMOD2 DIRMOD3 RFCLK RFSTR RFDAT BANDSELO BANDSEL1 ANTSWO ANTSW1 ANTSW2 ANTSW3 PCTL Figure 3 1 4 Schematic of MARITA RF Interface 28 B WANDA Interface 3 Technical Brief Wanda controls WCDMA part using these signals through W CDMA RF chip Wopy amp Wivi WCLK WDAT WSTR RXIA RXIB RXQA RXQB TXIA TXIB TXQA TXQB HSSLRX D HSSLRX CLK HSSLTX D HSSLTX CLK Control signals for Wivi Wopy WCDMA Data WCDMA TX Data Marita amp Wanda Communication Signal Marita amp Wanda Communication Signal VDIG VCORE R745 2 7K R744 3 3K C726 7 WSTR lt lt R746 NA JTAG TRSTN VCORE JTAG TCK JTAG TMS JTAG TDI JTAG xx EMU1 EMUO WCLK 5 zu RADIO CLK WDAT RADIO DAT RADIO STR RXIA IN RXIB ADC IN RXQA ADC Q IN RXQB ADC Q IN INV ADC RXEXTREF P ADC RXEXTREF N ADCSTR lt AD STR TXIA DAC 1 OUT TXIB DAC 1 OUT DAC OUT TXQB DAC_Q_OUT_INV DAC_TXEXTRES HSSLTX HSSLRX_D 5 HSSLTX CLK HSSLR HSSLTX D HSSLTXCLK HSSLRX CLK ID BALL ISSYNCn IS SYNC N ISEVENTn IS EVENT N APLL ATEST1 Figure 3 1 5 Schematic of WANDA RF Interface 29 3 Technical Brief 3 1 5 SIM Interface SIM interface scheme is shown in Figure 3 1 6 SIMDATO SIMCLKO SIMRSTO ports are used to communicate DBB
124. 59 DCIN 2 lt lt mice a x oco 19 R574 620 CES 1000 04 R INT uk ge z gums F12 posense 282 eco mion als Wawa kay pa _ 61 eb eee eee 77 g m 8 csse acsi 8 B S91 120K pum vss ss 10 vss 18 wc INT ATMs 4 PES 5 vss D E H2 H3 sua m CVS s Di 8584 0 usos e oreari Mic2P 0 5 2 2 NLAS4684FCT1 777 777 590 Hs MIC2N armsa csa NA Hook pews 85 2012 0 B 8 102827 ala 3 ale BDATA apas 585 8 MOTOR BATT lt lt gt AUXO2 SES ee lel 5 Tsee GND4 77 Mmm 100 F E 9 FE NDS vouti DACDAT 109 oacoar 4 Lose Tar nos DACSTR B10 DACSTR VSSTH30 F 2 m ppm 3565 0825 DACCLK DACCLK vssTH29 64 TJATTE2 ELO RE VSSTH28 77 1930 15 du 35 R 10 Lets id 29 Lossa 21 3 Prso1 vean 57 2012 Tio SHDN BGND vean VSSPA VSSTH24 o Giz Hs xl eos 3300p A 1 412 vppPA
125. 6 pagi WOW 2 n zj car casn m 1402 d 5 48 MC PCS RX 531 4 3358 8s 1 Laos 5 5 ss it ee 1002 77 777 75 Rats S L vss3 87 77 C433 C446 LCaos 270 270 7854 004 NA 22 2 P sss vos 8 e Tum J 22 77 H7 n vsse vone lt VDIG HERTA 77 777 777 j vss7 las vsse 92 559 zan 77 RXON gt SAFEC942MFLOFOO E BSELO gt t b M 1403 ar 4 2 PCTL gt SM_RX 1 4 x d MODA gt 425 mn 77 22 MODB gt 777 ma 190 777 888852552555 MODD gt mes 10 VDD A 289555855825 RREFSQOQORS Saas At T VDD T pona Loa cas moos 5 48 ___ T22p 22 ke mre neta 45 cut VcCPLL VCCRF di gt 1 127 108 525 47 xy 208 ous Kid 00 Os A9 NIE 429 Lara MEE peers RES 65 PN S F RE gt it 8288 685 5 DATA 1000p H 99998u99g 5252258558263 2222222822852 2555585255225 BEBEBEBEHEHHEH GPRFCTRL PULSESKIP lt lt lt RADCLK lt RADDAT lt RADSTR mas VLOOP VDD A lt 12
126. 6 width Change Wopy N201 Change Wopy N201 Change Wopy N201 Change Wopy N201 4 TROUBLE SHOOTING 8 LLLI 4 21 Checking GSM Block 1 Check Regulator Circuit 2 Check VCXO Block 4 Check Control Signal 5 Check RF TX Path 6 Check RF RX Path Redownload SW Cal 164 4 TROUBLE SHOOTING 4 21 1 Checking Regulator Circuit Refer to 4 16 Checking Power Source block IF you already check this point while checking power source block You can skip this test 4 21 2 Checking VCXO Block Refer to 4 17 Checking VCXO block IF you already check this point while checking VCXO block You can skip this test 4 21 3 Checking Ant SW Module Refer to 4 18 Checking Ant SW Module IF you already check this point while checking Ant SW module You can skip this test 165 4 TROUBLE SHOOTING ENS LLLI 4 21 4 Checking Control Signal Test Program Script MODE 0 SWTX 1 64 7 1024 1 VDD_A M TXON 426 he R421 a 1 Bu VDD A YDB 1411 L416 RADDAT TP408 3 LPF block RADSTR 407 Vtune C448 RADCL K TP406 22 22p TXON gt RXON gt BSELO gt 427 gt gt k 28588 1413 100uH 8425 560 120 390 C439 _
127. A E EE om favour at mour m 35 o9 JaCDAT VGA 2 our mour me VCCLK VGA 3 mour ma 7 so olf 5 s 58 D s 9 2 w 9 9 4 IND SINK lt lt w os 77 e CIRES N VGA gt RI rr uje 9 37 rn s e YR em TINA 9 Lu 9 9 LM ois 200 Os ao Kev 16 o KEYINZ 08 o CPO LTC LCDBL gt aO Gi 875 20 TUA Pry 2 LCD VGA CAMERA CONNECTOR I2CCLK MEGA 12 CIVSYNC Figure 3 2 3 Main Board to FPCB Connector 50pin 26pin Main Board 46 3 Technical Brief EDLM0005801 D gt VCAM 2 8 DvDD gt VCAM 18 28 FLASH3 FLASH2 CIRES 12M FLASH Bc LTC FLASH DAT c cis CIHSYNC cos CIPCLK gt MAIN to FPCB Connector 8 54 33 8 DAT cips CIVSYNC gt CIHSYNC Cibi SS lt cires 1 3m FPCB to 1 3M Connector Figure 3 2 4 Main Board to camera FPCB Connector 26pin FPCB FPCB to 1 3M camera Connector 24pin FPCB
128. AMIC CHIP 0000115 22 pF 50V J NPO TC 1005 R TP C567 CAP CERAMIC CHIP 0000165 68 nF 6 3V K X5R HD 1005 R TP o C568 CAP CERAMIC CHIP 0000165 68 nF 6 3V K X5R HD 1005 R TP 273 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark C570 CAP CERAMIC CHIP 0000126 68 pF 50V J NPO TC 1005 R TP C571 CAP CERAMIC CHIP 0000126 68 pF 50V J NPO TC 1005 R TP CAP TANTAL CHIP 0002702 1 uF 16V STD 1608 R TP 6 C572 6 C573 CAP TANTAL CHIP 0002702 1 uF 16V STD 1608 R TP 6 C574 CAP CERAMIC CHIP 0000276 1 uF 10V Z YSV HD 1608 R TP CAP CERAMIC CH 0004903 1 uF 6 3V Z Y5V 1005 R TP 6 C575 6 C577 CAP CERAMIC CH 0004903 1 uF 6 3V Z Y5V 1005 R TP 6 C578 CAP CERAMIC CHIP 0000148 2 7 nF 50V K X7R HD 1005 R TP CAP CERAMIC CH 0000149 3 3 nF 50V K X7R HD 1005 R TP 6 C579 6 C580 CAP CHIP MAKER ECZH0003501 1 uF 6 3V X5R 1608 R TP 6 C581 CAP CERAMIC CHIP 0000122 47 pF 50V J NPO TC 1005 R TP 6 582 0000151 4 7 nF 25V K X7R HD 1005 R TP 6 C584 CAP TANTAL CHIP MAKER ECTZ0005501 100 uF 6 3V STD R TP CAP TANTAL CHIP MAKER ECTZ0005501 1
129. AS Ugpo Ie LOS SIAI YMS SOd lt 6 soq WSO Figure 4 21 2 GSM DCS PCS Tx Path Level 168 4 TROUBLE SHOOTING iammm s N404 1 y y 2 2 _ 2 405 Figure 4 21 3 Test Point of GSM DCS PCS Tx Path lalelo 8 w101 KMS 507 cios 1101 R101 0 6 ANTPAD101 33p 1 8nH FL101 L LMSP43MA 288 T ix 1 lt 5 0 nx 5 GSM1800_Rx VDD GSM1900 vci WCDMA 4 77 vca d GSM18001900 TX 13 8 8 8 8 GSM900 TX GSM RX gt DCS RX gt PCS 77 lt DCS TX lt GSM TX 169 4 TROUBLE SHOOTING B GSM Tx Output Level Check Tieasurenent Instrument Screen Tieasurenent Instrument Screen Full Dounlink Traffic Full Dounlink Traffic Pouer Traffic Band Rising Edge Traffic Band East Rising Edge E Traffic Channel Falling Edge Traffic channel Falling Edge 698 Useful nS TX Level TX Level 5 Useful ph p Control Pa peed A Return Return 651 intrer 1072
130. AT 2 QDAT QDATA SYSCLK2 MCLK IDAT IDATA RESETB DCLK DCLK 8 AT AUXO2 BEARP RXSTR BEARN PCMUL E AUXIT GPDAT EH cco GPCLK 8 Zz zizim mizini 8818 8 5 5 5 o 91 DAC01 585525553252 8 DACO2 R E SOODRROEED Ai B6 Nes BERORR ZS gt DACOS MODA 2 RFHC 22 s 24 MODC SPAS DACCLK MODD A5 SPAS DACDAT VCCPLL 405 vccnr 46 27 DACSTR LZT 108 5325 07 RA A DEC1 NC6 9 Fe PCMDL DEC2 GNDBUF ina A10 PCMCLK DEC3 NC3 reon 04 PCMSYN DEC4 PS 05 ADSTR DECS E C6 GNDPLL 28588 88 5 DATA c 77 XOOLA 39998980997 Sstrose 57 REXT 38888885888 458 2222222022852 A2 Zo0000a45560220 E gi vss VDD1 55 552 VOD gr Bom VSS3 VDD3 EZ VSS4 77 585 VDDS T 586 vone vss7 E vss 92 vsse Nc2 1 77 177 31 0 03 19 32 06 Reading Floppy Disk rive 31 Dec 83 9244 11 llecroy 1 ms 1 08 V 1 531 V 1 ms 1 00 1 468 V 1 00 V 8 13 V 1 468 V a pe ms B 1 00 V
131. ATION m If the calibration will be ended you will see several message window and the result of calibration through OUTPUT amp STATUS tab view The detail explanation of those will be described in chapter 7 4 4 7 4 4 Calibration Result Message If the calibration is over without error PASS message window will show up like Figure7 13 On the contrary if the calibration is over with some error FAIL message window will show up like Figure7 14 Additionally in all of the cases it is possible to check the calibration result with OUTPUT amp STATUS tab view XCalMon Calibration Q File Edit View Window Help 181 su Calibration amp RF Calibration 65 900 Delay Setting for 0 RXVCO Varactor Operating Point TXVCO Varactor Operating Point Tx Loop Bandwidth GSM amp WCDMA VCXO Tx Power RSSI amp E DCS1800 RXVCO Varactor Operating Point TXVCO Varactor Operating Point Loop Bandwidth Tx Power RSSI IPHD Temperature Compensatior E W CDMA RF Center Frequency Carrier Suppression Tx LPF Bandwidth Tx Maximum Output Power Tx Power Table Tx Open Loop Power Control Tx Power Sense Rx LPF Bandwidth Ax LNA Gain Switch amp AGC Hyst Rx AGC Gain Max amp RSSI WCDMA VCXO Calibration Ready Battery Voltage Figure 7 13 Calibration PASS Message Window OUTPUT STA
132. B RXVCO Varactor Operating Point Calibration Purpose To adjust the varactor diode to a pre determined operating point so that the loop voltage of the RXVCO measured with an ADC in AB 2000 is within the valid range This is necessary to secure that all RX channels can be reached Procedure Proposal 1 Put the ME in static RX mode 2 Measure the loop voltage with the 2000 ADC for CVCO settings that is 0 7 Find a CVCO value that fulfills the requirements on loop voltage for low and high channel 3 If there are several CVCO values that fulfill the loop voltage requirements then the optimum CVCO value is the one that centers the loop voltage within the specified limits 4 Store the selected CVCO in the memory VCO Centre Frequency Adjustment Band 5 Reset the radio C TXVCO Varactor Operating Point Calibration Purpose To adjust the varactor diode to a pre determined operating point so that the loop voltage of the TXVCO measured with an ADC in AB 2000 is within the valid range This is necessary to secure that all TX channels can be reached Procedure Proposal 1 Put the phone in static TX mode 2 Measure the loop voltage with the 2000 ADC for CVCO settings that is 0 7 Find a CVCO value that fulfills the requirements on loop voltage for low and high channel 3 If there are several CVCO values that fulfill the loop voltage requirements then the optimum CVCO value is the on
133. BLE TNA Bs 4 055655566 77 173 4 TROUBLE SHOOTING 29 Dec 83 13 26 37 LeCroy L B I TXON 1 80 V 4 femen GSM 1 RN i 1 ms 1 1 0 38 5 ps t 590 k 2 2 065 2 5 MS s v o nnn DC 2 12 V 4 10 1 evts STOPPED Figure 4 21 6 GSM Tx control signal Check Vapc level Check if there is any Major difference Refer to Graph 4 21 6 7 Check GSM DCS PAM output power 31 0 03 18 48 28 LeCroy j mA F 1 ms 1 1 00 V 1 1 BB ime V pc DCS PCS ER dm 2 w yankata a lms 1 pc 499 5 2 1 V DD 2 5 MS s 3 2 068 ll l 1 DC2 16 V 4 2 V 00 gt 1 evts STOPPED GSM 33 5dBm DCS 31 0dBm GSM Tx path OK See Next page to check Figure 4 21 7 DCS PCS Tx control signal Redownload SW Cal No Changing GSM PAM 401 174 4 TROUBLE SHOOTING 4 21 5 Checking RF Tx Path A GSM Tx path Level e eos gt
134. Bm Blocking Response Wanted Signal 101dBm Wanted Signal 101dBm TCH FS Class II RBER Unwanted Signal Depend on freq Unwanted Signal Depend on freq 15 2 PERFORMANCE 4 Receiver WCDMA Mode Item Reference Sensivitivity Level Maximum Input Level Adjacent Channel Selectivity ACS Specification 106 7dBm 3 84M 25dBm 3 84MHz 44dBm 3 84MHz DPCH Ec UE 20dBm output power class3 20dBm output power class3 In band Blocking Out band Blocking Spurious Response 56dBm 3 84MHz 10MHz UE 20dBm output power class3 44dBm 3 84MHz Q 15MHz 20dBm output power class3 44dBm 3 84MHz f 2050 2095 2185 2230MHz band 20dBm output power class3 30dBm 3 84MHz f 2025 2050 8 2230 2255MHz band 20dBm output power class3 15dBm 3 84MHz f 1 2025 8 2255 12500MHz band UE 20dBm output power class3 44dBm CW UE 20dBm output power class3 Intermodulation Characteristic 46dBm CW 10MHz amp 46dBm 3 84MHz 20MHz UE 20dBm output power class3 Spurious Emissions 16 57dBm f 9KHz 1GHz 100k BW 47dBm f 1 12 75GHz 1M 60dBm f 1920 1980MHz 3 84MHz 60dBm f 2110 2170MHz 3 84MHz 5 Bluetooth Mode 5 1 Transmitter Out Power 2 PERFORMANCE Class 2 6 4dBm Power Density Power density 20dBm per 100kHz EIRP Power Control Option 2dB s step size 8
135. CO Varactor Operating Point TXVCO Varactor Operating Point Loop Bandwidth Tx Power lt lt lt lt lt lt lt lt lt lt lt lt lt RSSI IPHD Ti iti W CDMA lt lt lt lt lt lt lt lt lt lt lt lt lt RF VCO Center Frequency Tx Carrier Suppression LPF Bandwidth Tx Maximum Output Power Tx Power Table Tx Open Loop Power Control Tx Power Sense Rx LPF Bandwidth LN Gain Switch 8 Hyst Gain 8 RSSI WCDMA VCXO BB Calibration Battery Voltage OUTPUT STATUS INSTRUMENT UART gt gt gt ITP Version lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt P m Test lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt gt gt gt EGSM RXUCO Cal End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt gt gt gt EGSM Cal Start lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt TXUCO Min 0 Max 7 Calibrated TXUC0 3 gt gt gt EGSM TXUCO Cal End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt
136. COs run on double frequency Different frequency ranges can be selected in the VCOs for GSM DCS and PCS band operation The VCOs are supplied from a separated external voltage regulator to avoid frequency pushing and up conversion of low frequency noise A separate ground pin is also used as varactor ground reference to prevent DC voltage drop changes from affecting the VCO frequency Figure 3 7 3 shows a block diagram of the VCO block GSM 850 EGSM 900 TX 1 GHz gt GSM 850 900 TXBUF m gt To GSM 850 900 LO section VTUNE m gt GNDVAR GSM 1800 1900 RX 4 GHz gt To GSM 1800 1900 LO section RX SYS TX To GSM 1800 1900 o gt TXBUF GSM 1800 1900 TX or GSM 850 EGSM 900 A VCOLR VCOHR VCOLT VCOH BIAS CIRCUITS 2 GHz Figure 3 7 3 Block diagram of the VCO part 81 3 Technical Brief E PLL Block The PLL consists of a programmable prescaler with multiple division ratios and a phase and frequency detector with a charge pump with programmable output current Channel frequency selection and transmitter modulation is controlled via the prescaler modulus inputs MODA MODD and the prescaler offset value offset The MODA MODD signals could be delayed 0 5 10 or 15 ns with MD bits to be synchronized with the XO signal Figure 3 7 4 shows a block diagram of the PLL block PHDOUT From XO PS VCCPHD
137. Calculate the DAC value VCXOCONTCal that gives zero frequency error at the mid channel using piecewise linear interpolation and store the value in the memory SYNT CONFIG ID VCXO 6 Calculate LO fmin 1023 K HI z fmax fmid 1023 Each value is then multiplied by 100 and rounded to nearest integer with the results stored in the memory GD RF SYNT CONFIG ID DAC STEP LO ROUND 100 K LO DAC STEP HI ROUND 100 K HI where ROUND x x rounded to the nearest integer F TX Power Calibration Purpose These procedures describe how to tune the different power levels of the power amplifier to output powers corresponding to values in GSM 05 05 and explain how to calculate intermediate power levels that will ensure a good power versus time performance Procedure Proposal 1 Reset the DIRMOD block and select a mid channel using the trimmed value on the capacity array for VCO tuning and a default IPHD value as phase detector current Turn on dummy burst modulation 2 Use the Multi burst method to characterize the relation between output power and the DACvalue Then store the DAC values that give the closest approximations to the power targets defined in Table 10 3 3 To avoid yield problems with the power template and switching transients spectrum a margin to the compression point of the PA should be observed However the output power must be kept within the tolerances specified in Tab
138. E ASSY Without Color Without Color MLABOO LABEL A S 5 MLACOO LABEL BARCODE MLABO0000601 0003401 HUMIDITY STICKER EZ LOOKS user for mechanical 254 N 10 EXPLODED VIEW amp REPLACEMENT PART LIST 10 2 Replacement Parts Note This Chapter is used for reference Part order Main com ponent is ordered by SBOM standard on GCSC Level MH Description Part Number Specification Color Remark o pree 5 0025501 Green 5 00 ASSY FLEXIBLE SMT SACE0033801 Silver SACCOO o SACCO018001 CAP CERAMIC CHIP 0000276 1 uF 10V Z Y5SV HD 1608 R TP CAP CERAMIC CHIP 0000276 1 uF 10V Z Y5V HD 1608 R TP TQ ENBY0019501 20 PIN 4 mm ETC H 1 5 Socket DIODE LED CHIP EDLHO0006001 Blue 1608 R TP Blue SMD LED DIODE LED CHIP EDLHO0006001 Blue 1608 R TP Blue SMD LED pese pem pomme R11 RES CHIP HY0000201 0 ohm 1 16W J 1005 R TP R12 RES CHIP 0000203 10 ohm 1 16W J 1005 R TP R4 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP R6 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP R7 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP 00 ASSY FLEXIBLESMT SACD0026201 Silver TOP BORD NEPOS 0020201 140 PIN 0 4 mm ETC 0 9 Header CONNECTOR BOARD TO BOARD 0022401 150 PIN 0 4 mm ETC 0 9 Header RES CHIP 0000280 100
139. ED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark C210 CAP CERAMIC CHIP 0000180 3 3 pF 50V NPO 1005 C211 CAP CERAMIC CHIP ECCHO0000115 22 pF 50V J NP0 TC 1005 R TP CAP CERAMIC CH 0000115 22 pF 50V J NPO TC 1005 R TP C212 C214 CAP CERAMIC CH 0000167 0 1 uF 6 3V K X5R HD 1005 R TP C215 CAP CERAMIC CHIP 0000115 22 pF 50V J NPO TC 1005 R TP CAP CERAMIC CH 0000138 390 pF 50V K X7R HD 1005 R TP C216 C217 CAP CERAMIC CH 0000152 5 6 nF 25V K X7R HD 1005 R TP C218 CAP CERAMIC CHIP 0000147 2 2 nF 50V K X7R HD 1005 R TP CAP CERAMIC CH 0000155 10 nF 16V K X7R HD 1005 R TP C219 C220 CAP CERAMIC CHIP 0000701 1 2 pF 50V NPO 1005 R TP C221 CAP CERAMIC CHIP 0000127 82 pF 50V J NPO TC 1005 R TP C222 CAP CERAMIC CHIP 0000147 2 2 nF 50V K X7R HD 1005 R TP C223 CAP CERAMIC CHIP 0000155 10 nF 16V K X7R HD 1005 R TP 0000155 10 nF 16V K X7R HD 1005 R TP C224 C225 CAP CERAMIC CH 0000115 22 pF 50V J NPO TC 1005 R TP C226 CAP CERAMIC CHIP 0000155 10 nF 16V K X7R HD 1005 R TP CAP CERAMIC CH 0000155 10 nF 16V K X7R HD 1005 R TP C227 C228 CAP CE
140. ERAMIC CHIP 0000115 22 pF 50V J NPO TC 1005 R TP CAP CERAMIC CH 0000122 47 pF 50V J NPO TC 1005 R TP 6 6 C515 6 C516 CAP CERAMIC CH 0000165 68 nF 6 3V K X5R HD 1005 R TP 6 C518 CAP CERAMIC CHIP 0000165 68 nF 6 3V K X5R HD 1005 R TP CAP CERAMIC CH 0000122 47 pF 50V J NPO TC 1005 R TP 6 C520 6 C521 CAP CERAMIC CH 0000115 22 pF 50V J NPO TC 1005 R TP 6 C522 CAP TANTAL CHIP 0002702 1 uF 16V STD 1608 R TP CAP CERAMIC CH 0000279 10 47 uF 10V Z Y5V 1608 R TP 6 C523 6 C527 CAP CHIP MAKER ECZH0026301 4 7 uF 6 3V Z 5 1608 R TP 6 C531 CAP CERAMIC CHIP 0000276 1 uF 10V Z YSV HD 1608 R TP 6 532 0000276 1 uF 10V Z Y5V HD 1608 R TP 6 C533 CAP CERAMIC CH CAP CERAMIC CH P P 0000276 1 uF 10V Z Y5V HD 1608 R TP 6 534 6 C535 CAP CERAMIC CH 0000165 68 nF 6 3V K X5R HD 1005 R TP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 6 536 0004903 1 uF 6 3V Z Y5V TC 1005 R TP CAP CERAMIC CH 0000122 47 pF 50V J NPO TC 1005 R TP 6 C537 6 C538 CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5SV HD 1005 R TP 6 C539 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP CAP CERAMIC CH
141. FlashRWw 031119 Multi R el lease EPACOMMSetu 195 6 DOWNLOAD Push Next Button in Found New Hardware Wizard G Push the Finish Button in Found New Hardware Wizard Found New Hardware Wizard 3 Driver Files Search Results The wizard has finished searching for driver files for your hardware device The wizard found a driver for the following device 257 USB Flash Device Windows found a driver for this device To install the driver Windows found click Next gt c flashrw 0311139 multi release epacommsetup epiusb inf Found New Hardware Wizard Completing the Found New Hardware Wizard gt USB Flash S Windows has finished installing the software for this device To close this wizard click Finish 196 6 DOWNLOAD i H Close FlashRW exe I Remove amp Insert Main battery to reset the phone This action for USB Driver Install is done only at the first time of installation If you want to download Software just do as same as U8XXX Download 4 Connect amp Download says FlashRW for 8120 v 4 0 0 x 1800 Global Settinas LG Electronics Inc 3G Handsets Lab LGE Signed Software ssw flash files Pathname Size Add D 9WU8100 S Ws VO9084 U81 10_ 0908 200404029 drive media ssw 3671 D U8100 S Wsevogoe se ust 10_ 0908 200404095 drive _c ssw 10488 Bemeve D UBI00
142. H 0005801 2 2 uF 6 3V X5R 1608 R TP C709 C710 CAP CERAMIC CH 0004903 1 uF 6 3V Z Y5V 1005 C711 CAP CERAMIC CHIP ECCHO0005801 2 2 uF 6 3V X5R 1608 R TP 0005801 2 2 uF 6 3V X5R 1608 C712 C713 CAP CERAMIC CH 0004903 1 uF 6 3V Z Y5V 1005 R TP C714 CAP CERAMIC CHIP 0004903 1 uF 6 3V Z Y5V 1005 R TP CAP CERAMIC CH 0004903 1 uF 6 3V Z Y5V 1005 C715 C716 CAP CERAMIC CH 0004903 1 uF 6 3V Z 5 1005 C717 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP CAP CERAMIC CH 0000168 0 1 uF 16V Z Y5V HD 1005 R TP C718 C719 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP C720 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP C721 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP C722 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP o C723 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP 263 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark 6 C724 CAP CERAMIC CHIP 0000168 0 1 uF 16V Z Y5V HD 1005 R TP C725 CAP CERAMIC CHIP 0000168 0
143. IN ETC SMD 2 54 mm 2 2T UIM CONNECTOR WITH 5 0009901 BRIDGE 6 X701 CONN RECEPTACLE 0004101 24 PIN 3 25 3 10 3 1 5 T 6 Z201 FILTER SAW SFSY0012502 190 MHz 3 8 3 8 1 2 SMD Bal Bal 1000 1000 5 SAFDOO 6 B301 PCB ASSY MAIN SMT TOP X TAL SAFD0064901 05 0067201 5 PIN R TP 2 4V 10uA TEMP SENSOR Pb Free 032768 MHz 20 PPM 12 5 pF 65000 ohm SMD 0004602 5 9141 3 6 B601 6 C111 6 C115 CAP CERAMIC CHIP 0005705 10 uF 6 3V X5R 2012 R TP CAP CERAMIC CH CAP CERAMIC CH 0000115 22 pF 50V J NPO TC 1005 R TP 0005705 10 uF 6 3V X5R 2012 R TP 6 C116 6 C1930 CAP CERAMIC CH 0000110 10 pF 50V D NPO TC 1005 R TP 6 C1931 CAP CERAMIC CHIP 0000110 10 pF 50V D NPO TC 1005 R TP CAP CERAMIC CH 0000110 10 pF 50V D NPO TC 1005 R TP 6 C1932 6 C1933 CAP CERAMIC CH 0000110 10 pF 50V D NPO TC 1005 R TP 6 C301 CAP CERAMIC CHIP 0000137 330 pF 50V X7R 1005 R TP CAP CERAMIC CH 0000115 22 pF 50V J NPO TC 1005 R TP 6 C302 6 C303 CAP CERAMIC CH 0005705 10 uF 6 3V X5R 2012 R TP 6 C304 CAP CERAMIC CHIP 0005705 10 uF 6 3V X5R 2012 R TP CAP CERAMIC CH 0005705 10 uF 6 3V X5R 2012 R TP 6 C305 6 C306
144. J 1005 R TP 6 R545 6 R546 H 0000261 10 ohm 1 16W J 1005 R TP IP ERI 6 R547 RES CHIP ERHY0000280 100 ohm 1 16W J 1005 R TP 6 R548 RES CHIP ERHYO0000202 4 7 ohm 1 16W J 1005 R TP 6 R549 RES C 6 R550 RES C HIP ERHYO0000280 100 ohm 1 16W J 1005 R TP o HIP ERHY0000280 100 ohm 1 16W J 1005 R TP 268 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark R551 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP R552 RES CHIP 0000280 100 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP R553 R554 0000201 0 ohm 1 16W J 1005 R TP 555 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 556 557 558 RES CHIP RES CHIP 0000280 100 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 0000266 22 ohm 1 16W J 1005 R TP 559 560 0000201 0 ohm 1 16W J 1005 R TP 561 RES CH 0000201 0 ohm 1 16W J 1005 R TP 563 RES CH 0000201 0 ohm 1 16W J 1005 R TP 0000401 0 ohm 1 16W J 1608 R TP R562 RES CHIP 0000280 100 ohm 1 16W J 1005 R TP R564 R565 HZ0000319 8200 ohm 1 16W F 1005 R TP R570 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP
145. L SLEEP EN gt ENRGB SUB2 24 AUX2 I2CDAT C 8 SDA RED E FLASH1 I2CCLK DRIVER R737 97 SCL GREEN 18 FLASH2 2 R734 NA 8 BLUE FLASH3 8 88 ae ae C712 x C709 22u 8 2 2u LCD BL and Cam Flash Driver LTC3206 Figure 3 2 8 Charge Pump Circuit for Main amp Sub LCD Backlight 3 2 7 Camera Flash LED Illumination Camera Flash is composed of one White LED module LEWW S35LA with 3 LEDs The Charge Pump LTC3206EUF control similarly the flash LED current respectively R739 0 CPO LTC FLASH C708 2 2u LTC LCDBL EDLM0005801 pun T H 55555 P 22 LCDBL1 5 P o 20 LCDBLS i z 2 LCDBL4 i pum 2 LCDBL5 2 15 SUB1 2 4 FLASH1 SUB2 24 CPO LTC FLASH AUX2 16 FLASH1 BEEN m 2 FLASH2 BLUE FLASH3 Figure 3 2 9 Camera Flash Figure 3 2 10 Camera Flash Charge Pump Circuit LEDs Circuit in FPCB 52 3 Technical Brief 3 2 8 Keypad Illumination There are 19 blue LEDs in key board backlight circuit which are driven by GPIO32 KEY_LED_ONOFF line form Marita R741 27K KEY LED ONOFF gt R742 Q701 EMX18 lt KEY LED 77 77 Keypad Backlight Control Figure 3 2 11 Keypad Backlight Blue LED Interface
146. LES 6 CN601 6 CN701 6 CN702 CONNECTOR BOARD TO BOARD CONNECTOR BOARD TO BOARD 0022501 50 PIN 0 4 mm ETC H 0 9 Socket 0025501 26 PIN 0 4 mm ETC 0 9 Socket u181 181 ASIC WCDMA AIR INTERFACE EUSY0135201 WANDA 6 D701 6 D703 6 FB501 FILTER BEAD CHIP SFBH0008901 30 ohm 2012 3000mA BEAD for LARGE CURRENT ODE SWITCHING LTER BEAD CHIP EDSY0009901 5 80 V 300 A R TP 1 6 0 8 0 6 t SFBH0008901 30 ohm 2012 3000mA BEAD for LARGE CURRENT 6 FB502 6 FB503 LTER BEAD CHIP SFBH0008901 30 ohm 2012 3000mA BEAD for LARGE CURRENT 6 28504 FILTER BEAD CHIP SFBH0008901 30 ohm 2012 3000mA BEAD for LARGE CURRENT EE LTER BEAD CHIP SFBH0002302 6 FB505 6 FL101 LTER SEPERATOR 5 0004601 120 1608 CHIP BEAD 2000mA dB dB dB ETC 16 PIN 4 2 3 5 1 4 GSM WCDMA 5 6 6 FL201 FILTER SAW SFSY0024402 2140 MHz 2 0 1 6 0 6 SMD Unbal Bal 50 200 LTER SAW SFSY0024401 1950 MHz 2 0 1 6 0 6 SMD Bal Unbal 200 50 6 6 LTER EMI POWER SFEY0006501 3 TERMINAL EMI FILTER 264 10 EXPLODED VIEW amp REPLACEMENT PART LIST Level Description Part Number Specification Color Remark 6 FL702 FILTER EMI PPOWER FL705 FILTER EMI POWER SFEY0006701 CSP 20 Ball 8ch EMI Filter ESD Pb free SMD 4ch 2 0 1 25 200MH
147. LG Service Manual LG Table of Contents INTRODUCTION rs 6 141 Purpose eniti 6 1 2 Regulatory Information 6 1 3 Abbreviations 2 8 10 2 1 System Overview 10 2 2 Usable environment 11 2 3 Radio Performance 11 2 4 Current 19 2 5 RSS ete 19 2 6 Battery 19 2 7 Sound Pressure 20 2 8 CHANGING cocci re teret 21 Technical Brief 22 3 1 Digital Baseband DBB amp Multimedia 4 444 24 2 22 3 1 1 General Description 22 3 1 2 Hardware Architecture 23 3 1 3 External memory interface 27 3 1 4 RF 28 3 1 5 SIM Interface 30 3 1 6 UART Interface 31 3 1 7 GPIO General Purpose Input Output mab m u 32 3 1 8 USB unn ahus aD ten 33 3 1 9 Folder ON OFF Detection 35 3 1 10 Bluetooth Interface 36 3 1 11 TransFlash Interface 39 3 1 12 Power On
148. M It should be kept 3 7V in all power level WCDMA It will not be kept 3 7V in some power level 21 3 Technical Brief 3 Technical Brief 3 1 Digital Baseband DBB amp Multimedia Processor 3 1 1 General Description A Features CPU ARM946 running at 104 MHz 32 kB Instruction Cache 16 kB Data Cache 128 kB Instruction TCM and 128 kB Data TCM 8 channel DMAC e DSP C55x LEADS Megastar MGS3_2 0B running at 170 MHz 144 kWord ROM 32 kWord DARAM 32 kWord SARAM 7 channel DMAC Dedicated channel to DSP memory not locked up to other channels UMTS Access Support for WCDMA GSM Dual Mode GSM GPRS network signaling from Layer 1 to 3 WCDMA Ciphering and Integrity High Speed Serial Link HSSL to the WCDMA Modem at Layer 1 GSM AMR Multislot Class 8 HSCSD 14 4 kb s MMI Keypad Interface Tone Generator Interface Camera Data and Programmable Display Interfaces Enhanced graphics support for QCIF display Operation and Services PC Interface SIM Interfaces General Purpose GPIO Interface External Memory Interface that supports FLASH SRAM and PSRAM JTAG RTC Data Communication IIDA 6 SIR UARTs EDB RS232 Bluetooth Slave USB Package 12 by 12 mm 289 pin FPBGA Production Package 22 3 Technical Brief NENNT RE 3 1 2 Hardware Architecture The hardware structure is delivered as five separate hardware macros to th
149. MARITA with ABB VINCENNE and filter SIM Interface between DBB and ABB SIMDATO SIM card bidirectional data line SIMCLKO SIM card reference clock SIMRSTO SIM card async sync reset Table 3 1 2 SIM Interface MARITA SIMVCC VINCENNE VDD SDAT DAT SCLK CLK CARD SRST RST Figure 3 1 6 SIM Interface Scheme 30 3 Technical Brief 3 1 6 UART Interface UART signals are connected to MARITA GPIO through IO connector and Bluetooth interface Resource Name Note GPIO10 UARTRXO Receive Data GPIO11 UARTTXO Transmit Data UARTS for the bluetoot GPIO24 UARTRXS Receive Data GPIO25 UARTTX3 Transmit Data GPIO26 Clear To Send GPIO27 UARTRTS3 Request To Send Table 3 1 3 UART Interface 31 3 Technical Brief 3 1 7 GPIO General Purpose Input Output map In total 40 allowable resources This model is using 22 resources GPIO Map describing application state and enable level are shown in below table 3 1 4 10 Application Resource Inactive State Active State GPIOOO VGA_IO_OFF GPIO GPIOO1 2 EN GPIO GPIOO2 28 EN GPIO PULSESKIP Not used GPIOO4 Not used GPIOO5 CIRES N MEGA GPIOO6 GPIOO7 Not used GPIO10 UARTRXO High GPIO11 UARTTXO High GPIO12 AUDIO AMP EN Low High GPIO13 HS SEL Low Headest High Speaker GPIO14 Not used GPIO15 Not used GPIO16 Not used GPI
150. ME DRAWING NO lt KEYOUT1 Sheets U8550 GD32 U8550 Keypad 1 0 enter draw number LG Electronics Inc 8 CIRCUIT DIAGRAM EDLMO0005801 VCAM 1 8V gt VCAM 2 8 DVDD gt 2 8 AVDD 59 n FLASH3 FLASH2 FLASH1 CPO LTC FLASH CID0 CID1 CID2 CID3 CID4 CID5 CID6 CID7 CIRES 1 3M 2 12 DAT SYSCLK CIVSYNC CIHSYNC 05000006000 560C CIPCLK gt TPI MAIN to FPCB Connector VCAM 1 8V gt VCAM 2 8 DVDD VCAM 2 8 AVDD gt gt 05 04 CIPCLK lt CIRES 1 3 12 DAT CIVSYNC CIHSYNC 50 50000 SYSCLK FPCB to 1 3M Connector Seaton 03 28 Di ui 2005 Checked DRAWING aa UC Approved DRAWING LG Electronics Inc N enter draw number LGIC 42 A 5505 10 01 LG Electronics Inc 237 8 CIRCUIT DIAGRAM 102 AA LEBB S14H LD1 LEBB S14H VCAM VGA 2 8V gt CID0 CID1 CID2 CID3 CID4 CID5 CID6 CID7 IND_SINK PDID7
151. O17 MEGA EN GPIO20 CAM28 EN GPIO 21 Not used GPIO22 30 OFF GPIO23 Not used GPIO24 UARTRX3 GPIO25 UARTTX3 GPIO26 UARTCTS3 GPIO27 UARTRTS3 GPIO30 Not used GPIO31 CAM18 EN High GPIO32 KEY LED ONOFF High GPIO33 Not used GPIO34 REG High GPIO35 Not used GPIO36 30 CTRL2 High GPIO37 TF DETECT High 40 USBSENSE High GPIO41 30 CTRL1 High GPIO42 Not used GPIO43 FOLDER DET High Open 44 Not used GPIO45 TP601 Not used 46 BL SLEEP EN High GPIO47 Not used Table 3 1 4 MARITA GPIO Map Table 32 3 Technical Brief 3 1 8 USB The USB block supports the implementation of a full speed device fully compliant to USB 2 0 standard It provides an interface between the CPU embedded local host and the USB wire and handles USB transactions with minimal CPU intervention The USB specification allows up to 15 pairs of endpoints Data for each endpoint is buffered in RAM within the USB block and is read written from the endpoint FIFO using DMA transfers or FIFO register access High speed high throughput endpoints can use DMA while slower endpoints can use FIFO register access The USB block can request up to six DMA channels three for IN endpoints and three for OUT endpoints USB Function Note USBDP USB differential lin
152. OM Echo Loss EL MAX 40dB over Sending Distortion SD refer to TABLE 30 3 Receiving Distortion RD refer to TABLE 30 4 NOM MAX NOM 47 under MAX under Sending Loudness Rating SLR MAX 8 3dB NOM 1 12 NOM Side Tone Masking Rating STMR MAX 25dB over NOM Echo Loss EL MAX 40dB over Sending Distortion SD refer to TABLE 30 3 Receiving Distortion RD refer to TABLE 30 4 NOM MAX NOM 45dBPA under MAX 40dBPA under Receiving Loudness Rating RLR Idle Noise Sending INS 64dBm0p under Idle Noise Receiving INR Receiving Loudness Rating RLR A C O U S T C Idle Noise Sending INS 55dBm0p under Idle Noise Receiving INR TDMA NOISE GSM Power Level 5 DCS Power Level 0 Cell Power 90 105dBm Acoustic Max Vol MS HEADSET SLR 8 3 MS HEADSET 13 1dB 15dB SLR RLR mid Value Setting 62dBm under 20 2 PERFORMANCE 2 8 Charging Normal mode Complete Voltage 4 2V Charging Current 800 Await mode In case of During a Call should be kept 3 9V GSM It should be kept 3 9V in all power level WCDMA It will not be kept 3 9V in some power level Extend await mode At Charging prohibited temperature 20C under or 60C over GS
153. PAD101 FL101 Liga LMSP43MA 288 z 2 GsMt800 2 10 GsM1900 Rx 3 ver weoma 4 7 vez 2 L105 GsMo00 gt GSM RX ANTSWO gt DCS PCS RX ANTSW1 gt E 777 DCS TX L103 ANTSW2 gt lt TX ANTSW3 gt gt D Leno _ lema T 10p 10 ootu 2250 VDD gt VDD A kd gt Lene i L Trou 10u 10u ate l 77 77 777 gt V_wivi_A R103 EXTLDO ANS NI0i LP3981D 28 bove gt V sl 6 ne wivi I wow G AN Bln syAss S len lena 10u 0 033u 2012 7 H 7 ro od LG ELECTRONICS INC Drawn by Mobile Handsets R amp D Center 38 HW Group Develpment Lab 6 R amp D U8550 spfy0106301 1 1 EK ANT SW to ANT BES RICH CHE Page 1 of 7 RF Part 1 of 4 Changed by Date Changed GA CHK Drawing Numb 1 Page 2004 May 16 1 10 11 12 229 8 CIRCUIT DIAGRAM
154. R EMP SOLUTION Pb free EUSY0171401 CSP 20 PIN R TP 7 CHANNEL ESD FILTER ARRAY KNATTE Pb free Q601 TR BJT NPN 0014901 SOT323 2 W R TP NPN SWITCHING TR Pb free TR BJT NPN 0013301 2 2H1A 1 W R TP VEBO 6V Pb free TR BJT NPN 0013701 6 150 mW R TP DUAL TRANSISTORS R2130 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 0000201 ohm 1 16W J 1005 R TP R2131 R2241 HY0000201 ohm 1 16W J 1005 R TP 6 R2248 RES CHIP ERHY0000216 68 ohm 1 16W J 1005 R TP Pt HY0000216 68 ohm 1 16W J 1005 R TP 6 R2249 6 R2250 HY0000201 0 ohm 1 16W J 1005 R TP 6 R2252 RES CHIP ERHY0000261 10 ohm 1 16W J 1005 R TP 0000261 10K ohm 1 16W J 1005 R TP 6 R2253 6 R301 RES CHIP 0000138 0000280 33K 1 16 1005 100K ohm 1 16W J 1005 R TP 6 R302 6 R303 6 R306 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP RES CHIP RES CHIP HY0000271 HY0000201 39K ohm 1 16W J 1005 R TP 0 ohm 1 16W J 1005 R TP 6 R307 6 R308 RES CHIP HY0000201 0 ohm 1 16W J 1005 R TP 6 R404 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP Pt HY0000280 100K ohm 1 16W J 1005 R TP 6 R405 6 R406 6 R409 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP HY0000201 HY0000220 0 ohm 1 16W J 1005 R TP 100 ohm 1 16W J 1005 R TP 6 R410 6 R411
155. RAMIC CH 0000155 10 nF 16V K X7R HD 1005 R TP C229 CAP CERAMIC CHIP 0000155 10 nF 16V K X7R HD 1005 R TP 0000137 330 pF 50V X7R 1005 R TP C230 C231 CAP CERAMIC CH 0000122 47 pF 50V J NPO TC 1005 R TP C232 CAP CERAMIC CHIP 0000181 4 7 pF 50V NPO 1005 R TP 0000124 56 pF 50V J NPO TC 1005 R TP C233 C234 CAP CERAMIC CH 0000175 2 7 pF 50V NPO 1005 R TP C235 CAP CERAMIC CHIP ECCHO0000115 22 pF 50V J NPO TC 1005 R TP CAP CERAMIC CH 0000115 22 pF 50V J NPO TC 1005 R TP C236 C237 CAP CERAMIC CH 0000155 10 nF 16V K X7R HD 1005 R TP C238 CAP CERAMIC CHIP 0000155 10 nF 16V K X7R HD 1005 R TP ERE CAP CERAMIC CH 0000115 22 pF 50V J NPO TC 1005 R TP C239 C240 CAP CERAMIC CHIP 0000115 22 pF 50V J NPO TC 1005 R TP C313 CAP CERAMIC CHIP 0000155 10 nF 16V K X7R HD 1005 R TP C314 CAP CERAMIC CHIP 0000155 10 nF 16V K X7R HD 1005 R TP C315 CAP CERAMIC CHIP 0000110 10 pF 50V D NPO TC 1005 R TP o C316 CAP CERAMIC CHIP 0000115 22 pF 50V J NPO TC 1005 R TP 260 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specif
156. RAMIC CHIP 0000140 560 pF 50V K X7R HD 1005 R TP 6 C448 6 C449 CAP CERAMIC CH CAP CERAMIC CH P P 0000137 330 pF 50V X7R 1005 R TP o 0000155 10 nF 16V K X7R HD 1005 R TP 272 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark C450 CAP CERAMIC CH P 0000115 22 pF 50V J NP0 TC 1005 R TP C451 CAP CERAMIC CHIP 0000115 22 pF 50V J NPO TC 1005 R TP CAP CERAMIC CH 0000155 10 nF 16V K X7R HD 1005 R TP C452 C453 CAP CERAMIC CH 0000186 33 pF 50V J NPO 1005 R TP C454 CAP CERAMIC CHIP 0000186 33 pF 50V J NPO 1005 R TP CAP TANTAL CHIP 0002702 1 uF 16V STD 1608 R TP C501 C502 CAP TANTAL CHIP 0002702 1 uF 16V STD 1608 R TP C503 CAP CERAMIC CHIP ECCH0000279 0 47 uF 10V Z Y5V 1608 R TP CAP CERAMIC CH ECCHO0005801 2 2 uF 6 3V X5R 1608 R TP C504 C508 CAP CERAMIC CHIP 0006201 4 7 uF 6 3V X5R 1608 R TP C509 CAP CERAMIC CHIP 0000128 100 pF 50V J NPO TC 1005 R TP C510 CAP CERAMIC CHIP ECCHO0005801 2 2 uF 6 3V X5R 1608 R TP C511 CAP CERAMIC CHIP 0000155 10 nF 16V K X7R HD 1005 R TP o CAP CERAMIC CHIP 0000276 1 uF 10V
157. RANGE 01 SILVER 02 GREEN 03 ORANGE 01 SILVER 02 GREEN 03 ORANGE 7 01 SILVER 02 GREEN 03 ORANGE 7 01 SILVER 02 GREEN 03 ORANGE 7 01 SILVER 02 GREEN 03 ORANGE 1 GASKET CONNECTOR gt m z 1 1 1 s gt 0 lt m gt r VIBRATOR MOTOR 70 gt o gt m 2 gt 1 gt lt m gt lt O gt m m lt m gt gt m m Q 01 GREEN 02 03 SILVER LOWER DECO REAR m E TAPE R DOWN FOLDER R DOWN WINDOW FLASH L DOWN 1 gt gt m z TAPE CAMERA FPCB WINDOW CAMERA TAPE DECO CAMERA DECO CAMERA T L CLE CAP SCREW MAIN L HINE BI gt T m FOLDER L DOWN MAIN LCD MAIN TAPE DECO SPEAKER TAPE BRACKET SPEAKER gt gt m z 1 z gt 5 z 5 bwwomeswr koomomp enserre T SCRE ND m Q o 5 m gt m gt A 7 m gt m 41 2 3 44 5 6 7 8 9 50 51 52 3 54 55 56 57 58 59 1 62 63 64 65 67 0 71 2 3 74 75 76 77 2 EYPAD DIA CAP RECPTA CAP MULTIMEDIA CARD DOME ASSY METAL PE P MAC R PAD REC AKER E ET W 7
158. Rx IQ No See Next page to check Rx path GSM Rx path OK See Next page to check 179 C GSM RF Level Check FL402 2444242544 te Figure 4 21 12 GSM DCS PCS Rx path C p 1 PCS RX un 4 ZZ 02 G2 1 5 02 G2 Z401 942 0 00 FL402 FL403 L 3 DCS_RX 4 5 4 5 J 77 v Agilent 8960 Setting CW Mode GSM 509 Ch65 948MHz DCS 5 9 Ch700 1842 8MHz PCS 50dBm ch700 1889 0MHz Check GSM DCS PCS Rx signal level at 3 GSM 51 5dBm DCS PCS 51 5dB Change Ant SW module N1000 GSM Rx path OK 180 GSM_RX 4 22 Checking Bluetooth Block 1 Check BT Regulator Block 2 Check BT Chip Block BT Bluetooth 181 VDIG VBT VTF EN R2171 100K 0 0510 R2186 vour GND R2179 599 0 3 4 75 BTF REG gt CE NC R2177 C1899 R1131N281D5 TR F C594 C1915 NaS 474 1608 NA 1608 and T Flash Regulator 2 85V BGB202 52 PCENA Nn ner euk 20 RESOUTAn gt gt S854 v2 45 srac 50 S 9
159. S 1005 R TP INDUCTOR CHIP ELCHO0001408 6 8 1005 R TP Free INDUCTOR CHIP ELCH0005013 4 7 nH S 1005 L410 INDUCTOR CHIP ELCH0001401 15 nH J 1005 R TP Free FILTER BEAD CHIP SFBH0007103 75 1005 CHIP BEAD 300 INDUCTOR CHIP ELCHO0007404 5 6 1608 R TP L413 INDUCTOR CHIP ELCH0007403 100 uH K 2012 Ft FILTER BEAD CHIP SFBH0007103 75 1005 CHIP BEAD 300 INDUCTOR CHIP ELCH0001402 18 nH J 1005 R TP Free L416 FILTER BEAD CHIP SFBH0007103 75 1005 CHIP BEAD 300 3 X4 UCSP 10 PIN R TP 600 mA BUCK REGULATORS FUSY01396004 DYNAMIC OUTPUT VOLTAGE PBFREE 5 0002801 26 dBm 40 83 58 dBc 23 5 dB 8 0 6 0 1 4 SMD N303 ISOLATOR IMT SQMY0001001 1950 MHz 3 2 3 2 1 5 SMD 1920 1980MHz ERE BGA 64 PIN R TP 6 6 mm lead free Analog Baseband EUSY0133103 ASIC TRANSFORMER MATCHING 5 0018401 6 PIN SMD DCS TX BALUN 5 0018402 16 PIN SMD GSM Tx Balun EUSY0132801 56 ball 56 PIN R TP RFIC 276 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark N501 05 0171302 SOT 23 5 PIN R TP 150mA 3 3V LDO Pb free N502 05 0153001 507 23 5 5 PIN R TP 150 mA LDO REGULATOR 1 5V ERE EUSY0171201 CSP 25 PIN R TP 6 CHANNEL ESD FILTE
160. SM 201 DIODE VARIABLE CAP FL401 EMI FILTER B201 CRYSTAL FL301 WCDMA TX RF SAW N201 WCDMA RX IC WOPY N304 WCDMA TX IC WIVI FL201 WCDA RX RF SAW N101 REGULATOR FL101 ANT SW MODULE 131 4 TROUBLE SHOOTING 4 15 Procedure to check Oscilloscope setting 1 Check Power Source Block 2 Check VCXO Block 3 Check Ant SW Module Agillent 8960 Test mode WCDMA Ch 9750 Uplink Ch 10700 Downlink 4 Check WCDMA Block Agillent 8960 Test mode GSM Ch 62 P L 7 level setting Ch 62 60dBm setting 5 Check GSM Block Redownload SW Cal 132 4 TROUBLE SHOOTING EE a 4 16 Checking Common Power Source Block Step 2 GSM PAM Block Step 1 Regulator Block Step 3 WCDMA PAM Block Bottom Top Figure 4 16 1 Common Source Block 133 4 TROUBLE SHOOTING 4 16 Checking Common Power Source Block Diagram 1 8V 100mA DCIO VDD_B VDD_A VDD D Ingela VCCA 134 4 16 1 Step 1 Check point C740 Check VBATI c 1111 ae ee R105 LP39811LD 2 8 4 TROUBLE SHOOTING R875 R847 Figure 4 16 3 Power Source Block 5 Step 1 Check Point C740 in Power Source Block 5 To Check Power Source to Check if main power source input or not See The Step 2 Check Point R847 in Power Source Block 5 To Check Power source Ch
161. SOR NJM2705 gt TJATTE2 Analog S W NLAS4684 HEADSET AMP LM4809LD gt Head Phone Loud Speaker Mode has four GPIO switching control ports It is 3D CTRL1 2 HS SEL and Audio EN HS SEL controls analog switch NLAS4684 and Audio EN controls shutdown of AUDIOAMP LM4809LD Video Telephony Mode has same paths with Loud Speaker Mode 3D IC Mode HS SPK SEL AUDIO AMP EN 3D 3D CTRL2 Receiver Headset amr Headset mp3 Loud Speaker VT 3D Speaker mp3 Table 3 4 2 Speaker Phone Mode GPIO Control State 60 3 Technical Brief B Voice call Uplink Mode Receiver Speaker Headset This section provides a detailed description of the Voice Call TX functions Audio Codec TX path Audio Mixer Analog Sidetone 4 AUXO Loop Loop Loop k 475 5 2 Ku Bluetooth Gs Module Microphone Input 1 gt 8 c bd ADC1 mateN TX PGA1 TXGC ee e gt gt AUXH 7 8 16 Auxiliary Input 1 a MIC2N Microphone Input 2 4 57 ADC2 Dor e TXPGA2 S PCM 8 16 Auxiliary Input 2 Voice Call TX Loudspeaker 1 FR Speech Signalfrom r r UU V ma Encoder
162. T22p 10u 2012 100K 1000p 330p 777 160 Figure 4 20 14 Schematic DC DC convertor Rosaili 4 TROUBLE SHOOTING TP Command mode z4 Wtxc 9750 1 1 43 0 0 255 68 Check Duplex MEO C111 Download the SW To bus amp Calibrate output PAM is the Next page N Check C307 2 Check the WCDMA RF Tx Chip Wivi To Check PAM Input level Yes Check R306 Check PAM control No Check the Vincenne signal from Vincenne to WCDMA PAM Signal line WPAREF Yes Check C310 lt gt lt gt Ch Lo ange s ne No the Rosaili from DC DC convertor Yes VCCWPA Check R301 To Check DC DC convertor COMP Change The PAM 161 4 20 6 Checking RX I Q To verify the RX path you have to check the pk pk level and the shape of the RX 1 0 N201 A7 RXQA C227 N201 A8 RXQB C229 N201 A9 RXIA C228 N201 A10 RXIB C226 Figure 4 20 15 WCDMA RF RX IC Bottom Tek 100 5 5 136 Acqs n I Coupling Impedance C3 Pk Pk 120mv C3 Mean 163 8 IC About 2 MHz amplitude LS Feed a CW signal at 2142MHz i M 300 170mV Q Hag 1 s I 50 with a power level of 60dBm Bandwidth Somy Position Offset Deskew Probe 250 MHz 26 ov 05 Functions Figure 4 20 16 1 0 signal CW 2142MHz Tek 50 0MS s 27
163. TMS AD MICP int ATMS GND GND ATMS int ATMS cap AFMS R GND AFMS AFMS L VDD GND Table 3 4 4 TJATTE2 Pin Description 65 AFMS L int 3 Technical Brief a a a lt a 2 cou 1 e 2 gt m 2 mo 0 gt z z 2 gd lt z z z lt T L 10 L ds eo Te a m 58 ee a X et 1450 Q 50 Q L R1 1 pF 50 Q R10 L 1 R12 R13 60K Q 1009 1 R15 47K Q 50 Q R7 P pF 1450 Q R3 200 pF 1KQ R6 2 7K Q 50 Q e lt lt lt lt m lt S m 0 2 5 5 2 lt lt lt lt Figure 3 4 9 TJATTE2 Block Diagram 66 3 Technical Brief 3 4 9 GPADC General Purpose ADC and AUTOADC2 The GPADC consists of a 14 input MUX and an 8 bit ADC The analog input signal is selected with the MUX and converted in the ADC The GPADC has a built in controller AUTOADC2 which is able to operate in the background without software intervention The AUTOADC2 periodically measures the battery voltage or current Fig 2 shows the schematic of GPADC part The GPADC channel
164. TUS INSTRUMENT UART 1871 RSSI Calibration RX Pur 95 RX Pur 95 Table 8 fk Rurg 75 306980 RSSI 95 013500 Pur 801 009508 UBATT 328 25 68 DAC 39 418 1887158 DAC 121 PASS gt gt gt BB Battery Voltage Cal End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt gt gt gt Total Fail Number in BB Calibration 6 gt gt gt BB fll Items Calibration End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt gt gt gt Elapsed Time 00 00 02 Total 2sec gt gt gt BB fll Items Calibration End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt gt gt gt 811 Items Calibration End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt 225 El TESI 7 CALIBRATION ______ File Edit View Window Help la xi RF Calibration 65 900 Delay Setting for MODA D RXVCO Varactor Operating Point VERS 8 831226 1357 INI17 CXC125477 7 PLATINUM TP 16M M P2 TXVCO Varactor Operating Point 5 1 CXC125469 ECSJHEE Fri Aug 22 13 41 36 2883 Loop Bandwidth GSM amp WCDMA VCXO VERS 2 CXC125495 R5B Power iride x c DCS1800 XI cecce e c RXV
165. TransFlash Interface TF DETECT Card detection connected to GPIO37 of MARITA TF CMD Command Response TF CLK Clock TF DAT Data line VTF Supply voltage from 2 85V external regulator U510 Table 3 1 6 TransFlash Interface Card detection When there are no card in TransFlash socket TF DETECT pin is Low If card is inserted in socket because TransFlash has internal pull up DETECT pin changes High VTF is always supply power If card is removed DETECT pin changes Low VTF x x E 2 2 500873 0802 o O e DAT2 RSV TF DETECT 2 CMD gt lt SCLK TF CLK a DATO DO ed lt gt DAT1_RSV 2 5 R653 8 7 EnB 470K C644 C636 1608 77 77 Trans Flash Figure 3 1 12 TransFlash and Schematic of TransFlash Interface 39 3 Technical Brief 3 1 12 Power On Sequence User presses END key and then ONSWAn signal is changed to Low VINCENNE initiates the internal oscillator and powers on the regulators VINCENNE generates a power for MARITA VINCENNE releases the power reset signal PWRRSTn and generates an interrupt IRQOn to MARITA VIN CENNE MARITA 3 Power for MARITA D Press END key 2 PWRRSTn 4 IRQOn D ONSWAn Figure 3 1 13 Power On Sequence 40 3 1 13 Keypad There are 26 buttons 3 s
166. Trouble 111 BLOCK DIAGRAM 185 4 12 Audio 113 5 1 GSM amp WCDMA a 185 4 12 1 1138 4 12 2 Speaker 117 6 2 442 187 4 12 3 121 6 1 The Purpose of Downloading 4 12 4 Headset 125 Software 187 4 12 5 Headset 126 6 2 Download Environment Setup 187 4 12 6 Headset 127 6 3 U8XXX 188 4 13 Charger 128 4 14 RF 130 7 CALIBRATION 200 4 15 Procedure to 132 7 1 General Description 200 4 16 Checking Common Power 7 2 XCALMON Environment 200 Source BIoCK 133 2 23 HN 200 4 17 Checking VCXO 149 7 2 2 S W Environment 200 4 18 Checking Ant SW Module Block 145 7 2 3 Configuration Diagram of 4 19 Checking Antenna Switch Block input Calibration Environment 200 146 7 3 Calibration Explanation
167. USB Regulator BT and T Flash Regulator 2 85V 1 5V Regulator for Marita PLL 1 5V Regulator for Wanda PLL vois B A B 82134 NA m m gt RESOUTON E 6 R547 p gt R WL93004CZQWR VINCENNE ONSWAn cil onswa resets 49 amp IND SINK ONSWBn 51 onswe mo wii oNswc PWRRST SPK MIC BIAS BT 46 Pe E QUESO B6 28 2 5 R570 2 RTCCLK gt lt M XTALI 86 REF2 REFI RR A E AUDIO EN gt simorr 62 3 sZ FI Mu R1312N241B TR F TPSO3 Teso T ex EZ 56 1K gt VBACKUP 22u 9 cess 3 7 100k 1608 1608 c SIMDATO HY 5 85218 30 77 im ml 2 SIMCLKO 58 E 8 SIMRSTO SRST smok GT R98 AM 15 enos 5 s 52 GND4 GND2 777 1K MCLK CDCDA 7 cuo KPD9D 85 2 54sF TIE I2CDAT SDA VDD A VDD BVBAT C VDIG VCORE MIC2P lt me Vg x501 I2CCLK B9 cocos 72 6553 Fes 100 CLKREQ m A 5 4 oT R521 PWRREQn SLEEP VDD 19 vean R506 5 o R522 0 8520 R519 0 12 vaer E MIC2N lt 1 T H e PECO ceu 8 777 n523 cur KS em
168. VER 012601 0001801 DIA3 0x2 0t Color 200 MBFZ0022101 505 0 5T PRESS NON COATING 0034601 MAIN LCD PAD Without Color MPBT0019601 Black MTADOO TAPE WINDOW MTAD0037101 N MTAZOO TAPE 20086801 N 4 20086901 COVER ASSY FOLDER UPPER ACGJ0046802 COVER FOLDER UPPER MCJJ0034201 5 MDAE00 DECO FOLDER UPPER MDAE0030402 MDAMOO DECO WINDOW SUB MDAMO0006901 AL DICASTING Silver Without MDAYOO DECO MDAYO0006801 0 2t Color MGADOO GASKET SHIELD FORM MGADO0096801 LCD LEFT 251 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark Without 5 MGADO01 GASKET SHIELD FORM 0097801 LCD UPPER CONTACT 2POINT Color PAD FLEXIBLE PCB 012401 MPBQOO PAD LCD SUB MPBQ0024101 IH 00 TAPE DECO 0094701 Without 00 TAPE WINDOW SUB 023901 Color Without Color Without Color MTAGOO 0001101 KEY FIX BRACKET SPEAKER 01901 PLATING MBJLOO BUTTON SIDE MBJL0022901 CHROME PLATING oed 40 5 0 CAP EARPHONE JACK 00252
169. Voice Call RX i Siem pec 1 Hard Limiter TX 1 Y J HR Speech Encoder Residual Linear Echo Noise Acoustic Band Pass Soft Limiter ti Filter TX Speech Coded Data to Host Echo DS OLE OTE Sets mm gt Encoder EFR Speech Encoder interdependency Figure 3 4 5 Voice Call Uplink Scheme The Uplink supports two microphones and two auxiliary inputs to the speech encoder blocks Both microphone inputs are compatible with an electric microphone The VINCENNE internal voltage source CCO provides the necessary drive current for the electric microphone The voltage source is via 2 programmable to supply 2 2V or 2 4V But the voltage source of our Model is to supply 2 4V The auxiliary audio inputs can be used as an alternative source of speech a source from an external microphone or as an analog loop connection Figure 3 4 4 2 shows that the audio inputs are fed to the transmit PGAs which enables to adjust the total gain in the product for different sensitivities of the microphones and spread in the transmit paths The ADCs are followed by the transmit band pass filters which accept the maximum output swing that the microphone preamplifiers can deliver without clipping and maintain a good signal to noise ratio The high pass filter in the TX paths can be di
170. W J 1005 R TP 6 505 RES CHIP ERHYO0000201 0 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 6 506 6 510 0000201 0 ohm 1 16W J 1005 R TP 6 R511 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 0000201 0 ohm 1 16W J 1005 R TP 6 R512 6 R516 H 0000220 1100 ohm 1 16W J 1005 R TP IP ERI 6 R517 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 6 518 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 6 R519 RES C 0000201 0 ohm 1 16W J 1005 R TP ERI HIP ERI 6 R520 6 R521 HIP ERHY0000266 22 ohm 1 16W J 1005 R TP 0000220 100 ohm 1 16W J 1005 R TP 6 522 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP 0000241 1 ohm 1 16W J 1005 R TP 6 R523 6 R526 0000201 0 ohm 1 16W J 1005 R TP 6 527 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 0000280 100 ohm 1 16W J 1005 R TP 6 528 6 535 0000241 1K ohm 1 16W J 1005 R TP 6 R536 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 0000280 100 ohm 1 16W J 1005 R TP 6 538 6 540 0000201 0 ohm 1 16W J 1005 R TP 6 541 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP 0000263 15 ohm 1 16W J 1005 R TP 6 542 6 R543 0000213 47 ohm 1 16W J 1005 R TP 6 544 RES CHIP ERHY0000201 0 ohm 1 16W J 1005 R TP ERE HIP ERHY0000201 0 ohm 1 16W
171. Y0000280 100 ohm 1 16W J 1005 R TP 6 R653 RES CHIP ERHY0000292 470 ohm 1 16W J 1005 R TP 6 R654 6 R655 0000280 100 ohm 1 16W J 1005 R TP 0000280 100 ohm 1 16W J 1005 R TP 6 727 RES CHIP ERHY0000204 12 ohm 1 16W J 1005 R TP 6 R741 6 R742 0000249 2 ohm 1 16W J 1005 R TP 0000204 12 ohm 1 16W J 1005 R TP 6 5601 CONN SOCKET 5 0014101 8 1 1 mm T Flash Memory Socket 6 U502 6 U504 6 U505 U507 05 0232807 sot 23 5 5 PIN R TP 1 8V 150mA LDO EUSY0160001 2 Junior 15 PIN R TP 1 1W Class D Mono Audio EUSY0160001 2 Junior 15 PIN R TP 1 1W Class D Mono Audio 0508 FFP16 16 PIN R TP 3D SURROUND AUDIO EUSY0175001 PROCESSOR EUSY0188601 10 Dual SPDT Analog switch Pb 6 U509 IC 05 0142501 8 PIN R TP Dual 105mW Headphone Amplifier EUSY0163901 uCSP 10 PIN R TP Dual Analog Switch 300MHz Bandwidth EUSY0163901 uCSP 10 PIN R TP Dual Analog Switch 300MHz Bandwidth SCSP 88 PIN ETC 512M 256 2 MLC NOR 128M 64 2 EUSY0211101 PS 1 8V PB FREE 280 10 EXPLODED VIEW amp REPLACEMENT PART LIST Level Description Part Number Specification Color Remark Z401 FILTER SAW SFSY0024301 942 5 MHz 1 4 1 1 0 6 SMD Unbal Bal 50 150 rpm em mem SUMYOO MICROPHONE 50 0010702 44 dB 4 1 5 spring type 281 10
172. a interface port in Marita The camera port supply 13MHz master clock to camera module and receive 17MHz pixel clock 15fps vertical sync signal horizontal sync signal reset signal and 8bits YUV data from camera module The camera module is controlled by 12C port Pin Name Description Analog Ground Digital video data bit 7 Digital video data bit 6 Digital video data bit 5 Digital video data bit 4 Digital video data bit 3 Digital video data bit 2 Digital video data bit 1 Digital video data bit 0 Clock for output data Reset Digital Ground Digital Ground Digital Core Voltage 1 8V Digital interface Voltage 2 8V Analog Voltage 2 8V Interface Ground System Clock Horizental sync signal Vertical sync signal Interface Ground Serial data I O for 12C bus Clock for output data Analog Ground D1 DO PCLK RESET STANDBY DGND VIS 5 o s o o o o ol ol Pin Description STANDBY In Stanby mode MCLK In System Clock Input GND Gnd Frame Synchronous Signal PCLK Out Pixel Clock DO Out Image data output D1 Out Image data output D2 Out Image data output D3 Out Image data output D4 Out Image data output D5 Out Image data output D6 Out Image data output D7 Out Image data output VSYNC Out Vertical Synchronization Reference HSYNC Out Horizontal Synchronization Reference GND Gnd G
173. ader Calibration start using XCALMON Verification of calibration result A Configuration of Calibration Configure to calibrated U8550 mobile phone like Figure7 1 If configuration will be accomplished start XCALMON program B Running ITP Using Production Loader If XCALMON will be executed you should run using L ITP starting icon at first Click the 1 icon then you will see the start window like Figure7 10 When you will turn on the U8550 mobile phone the production loader will be downloaded automatically like Figure7 11 and then it will execute the ITP at once If the ITP will operate normally you should see the characters TP OK in ITP command window like Figure7 12 223 7 CALIBRATION EXT x 18 x Send Production Loader File Send payload information Downloading payload 12 Elapsed time 00 00 02 Ready Figure 7 11 Production Loader Downloading Sa XCalMon ITP Window 5 8 x EM File Edit View Window Help x Ready A Figure 7 12 ITP Start Complete Window 224 C Calibration Start Using XCALMON If you want to calibrate U8550 mobile phone click the calibration icon C And then you will see the calibration tree window like Figure7 6 To start calibration you should select Calibration item and push button in your keyboard D Verification of calibration result 7 CALIBR
174. al 7 Modes according to external Devices Receiver Loud Speaker Headset Video Telephony Mode Operate on state of the WCDMA Call Mode VINCENNE In Out Port IN OUT Voice call Receiver Mode MIC1P MIC1N BEARP BEARN Loud Speaker Mode MIC2P MIC2N AUXO1 AUXO2 Headset Mode AUXI1 AUXO1 AUXO2 Video Telephony Mode MIC2P MIC2N AUXO1 AUXO2 Only Loud Speaker AUXO1 AUXO2 Loud Speaker Mode AUXO1 AUXO2 Headset Mode Table 3 4 1 Audio Mode 58 AUXO1 AUXO2 3 4 4 Voice Call A Voice call Downlink Mode Receiver Speaker Headset 3 Technical Brief This section provides a detailed description of the Voice Call RX functions Speech Coded Data from Host Audio Mixer Acoustic Voice Call RX FR Speech 659 Decoder HR Speech SHF Decoder 4 Compressor 8 AMR Speech OHF I Decoder Compressp Y EFR Speech AHF To Linear Echo Canceller in Decoder Voice Call TX Compress e Bluetooth Module Tone Generator Compensation Audio Codec RX path Decoder PCM 44 48 Volume PCM 44 48 o CO 14 DAC2 re RX PGA2 AUXO2 Auxiliary Output 2
175. amp REPLACEMENT PART LIST Location Level No Description Part Number Specification Color Remark SAFYOO PCB ASSY MAIN 5 0134601 Silver SBCLOO BATTERY CELL LITHIUM SBCL0001303 2 1 mAh COIN SOLDER TYPE BACKUP BATTERY ANT601 PCB ASSY MAIN SMT PCB ASSY MAIN SMT BOTTOM ANTENNA GSM FIXED SAFF0059401 T NI 065801 SNGF0008301 B201 C101 C102 X TAL 0016801 13 2 19 10 40 ohm SMD 5 3 20 0 7 3 0 2 0 bluetooth chip 9 0 3 0 1 5 0000173 1 2 pF 16V NPO 1005 R TP CAP CERAMIC CH 0000155 10 nF 16V K X7R HD 1005 R TP C103 C104 C105 CAP CERAMIC CH 0000186 33 pF 50V J NPO 1005 R TP CAP CERAMIC CHIP 0000110 10 pF 50V D NPO TC 1005 R TP ECCH0000110 10 pF 50V D NPO TC 1005 R TP C106 C107 C108 C109 C110 CAP CERAMIC CHIP 0000110 10 pF 50V D NPO TC 1005 R TP 0000110 10 pF 50V D NPO TC 1005 R TP 0000155 10 nF 16V K X7R HD 1005 R TP CAP CERAMIC CHIP 0000155 10 nF 16V K X7R HD 1005 R TP CAP CERAMIC CHIP 0000155 10 nF 16V K X7R HD 1005 R TP C112 C113 C114 CAP CERAMIC CH ECCHO0000161
176. ath and downlink path The uplink path amplifies the audio signal from MIC and converts this analog signal to digital signal and then transmit it to DBB Chip MARITA This transmitted signal is reformed to fit in GSM amp WCDMA Frame format and delivered to RF Chip The downlink path amplifies the signal from DBB chip MARITA and outputs it to Receiver or Speaker The audio interface consists of PCM encoding and decoding circuitry microphone amplifiers and earphone drivers The PCM encoder and decoder blocks are two channel 16 bit circuits with programmable gain amplifiers PGA The decoder has a receive volume control The audio inputs and outputs can be switched to normal or auxiliary ports PCMSYN PCMO d lt DECOD 8 16 kHz AUXO2 AUXILIARY OUTPUT 1 ER ONE CH 44 48 kHz EARPHONE TWO CH AUXO1 AUXILIARY OUTPUT 2 IC MIC1P ENCODER 4 8 16 2 TWO I AUXILIARY INPUT 1 2 4 2 In AUXILIARY INPUT 2 Figure 3 4 2 Audio Interface Detailed Diagram VINCENNE 56 3 Technical Brief 10K z a N oncor as WococREF pacon SH WPAREF Dacos e TXON eme eorr rg gt JACK DET FN panasar 77
177. c Random Access Memory Universal Mobile Telephony System 2 PERFORMANCE 2 PERFORMANCE 2 1 System Overview Item Shape Specification GSM900 1800 1900 amp WCDMA Folder Dual Mode Handset Size Weight 90 x 55 x 24 7mm 134g with Standard Battery Power 1400mA Li Polymer Talk Time Over 180 Min WCDMA Tx 12 dBm Voice Over 220 Min GSM Tx Max Voice Standby Time Antenna Over 165 hrs WCDMA DRX 1 28 Over 223 hrs GSM Paging period 9 Fixed Type Fixed Screw Main LCD 220 x 220 TFT LCD 262K Color Sub LCD Main Sub LCD BL 128 x 160 TFT LCD 262K Color White LED Backlight Vibrator Yes Cylinder Type LED Indicator C MIC Blue Yes Receiver Yes Earphone Jack SIM Socket Yes Yes 3 0V 1 8V Volume Key Push Voice Key External Memory Push Type Memo T Flash Socket Connect 24 Pin 10 2 2 Usable environment 1 Environment Voltage 4 0 Typ 3 4 Min Shut Down 3 2 2 PERFORMANCE Operating Temp 20 60 Storage Temp 30 85 Humidity max 85 2 Environment Accessory mem joo ee ee 38 Power CLA 12 24V DC 2 3 Radio Performance 1 Transmitter GSM Mode Conducted Spurious Emission 100k 1GHz MS allocated DCS PCS 9k 1GHz 1G 1710MHz Channel
178. channel spec 70 3 Technical Brief 3 4 13 Charging Part The charging block in AB2000 processes the charging operation by using VBAT voltage It is enabled or disabled by the assertion negation of the external signal DCIO Part of the charging block are activated and deactivated depending on the level of VBAT Figure 3 4 17 shows the schematic of charging part C532 7 777 DCIN 3 51 0010 CHREG 5 5 CHSENSE Q501 8 F11 EGSENSE DCN 2 lt 3 8 R899 fe FGSENSE SI7411DN T1 E3 5 2 2 91 Hi 63 55 C548 55 10p vss C p Vss_D SUB VSSBUCK 04 Test R2194 0 77 BDATA R548 47 B3 MOTOR lt lt VIBR DACDAT DACDAT nes les A10 DACCLK 8 2K HE78 paces 1 1 708 R2138 R843 vDIG 100K 501 77 47 VSSPA 1 VDDPA DAC 12 VODBUF TIL PASENSE PASENSE PASENSE PASENSE 512 PAREG IOUT Figure 3 4 17 Schematic of Charging Part When VBAT is below a certain value 3 2V a current generator take care of initial charging of the node and internal trickle charge signal is active This part of th
179. ck MUX To prescaler TXBUFH gt TXOHA From GSM 1800 1900 TX VCO e TXOHB PCTL gt TXOLA From GSM 800 900 TX VCO TXOLB TXBUFL VCCBUF GNDBUF gt TXBUFL Figure 3 7 5 Block diagram for the transmitter 83 3 Technical Brief A Power Amplifier The Power Amplifier 401 is intended for use in EGSM and DCS PCS mobile equipment It is module with two parallel amplifier chains with one chain for the EGSM transmitter section and one for the DCS PCS transmitter section Each chain amplifies the RF signal from the respective transmitter to the antenna The power amplifier supports class 10 Band selection and the output power level of the RF amplifier are controlled by discrete signals Vea respectively from the digital baseband controller ASIC Marita GND DCS PCS Pin GND EGSM Pin GND Vband GND Vapc 10pF 33pF GND DCS PCS Pout GND EGSM Pout GND Figure 3 7 6 Block diagram of the Power Amplifier with Two Parallel chains 84 3 Technical Brief 3 8 WCDMA Mode 3 8 1 Receiver The received signal on the antenna connector arrives via the antenna switch to the duplexer The duplexer directs the signal to the LNA which resides in Wopy W CDMA Receive ASIC as every other active part of the radio receiver The LNA has two different gain settings From
180. cklight 5 White LEDs simultaneously Table 3 2 3 Devices in LCD Module The LCD Module is connected to FPCB with the 40 pin Board to Board Connector AXK8L40125 and Receiver 2 blue Indicator backlight LEDs are connected by soldering in the Camera amp LCD FPCB The Main amp Sub LCD are controlled by 8 bit PDI Parallel Data Interface in Marita In case of power off mode if TA is inserted 2 blue Indicator LEDs are turned on Pin Name Pin Type Description Indicator LEDs 3 Indicator LEDs Power IND SINK Indicator LEDs Ground Receiver Terminal Receiver Minus Receiver Plus Table 3 2 4 Interface between Camera amp LCD FPCB and Receiver Vibrator Indicator LEDs and Camera Flash LEDs 50 3 Technical Brief Pin Name Pin Description Unused Pin The Logic Power Supply for LDI and VCI The Analogue Power Supply for LDI and LCM S RESET Sub Reset Pin Initialize the LSI at the low level RESET Main Reset Pin Initialize the LSI at the low level SUB CS Sub Chip Select Active low DO Bi Direction Data Bus D1 Bi Direction Data Bus D2 Bi Direction Data Bus D3 Bi Direction Data Bus 04 Bi Direction Data Bus D5 Bi Direction Data Bus D6 Bi Direction Data Bus D7 Bi Direction Data Bus MLED Anode of LEDS MLE1 Cathode of LED1 MLE2 Cathode of LED2 MLES3 Cathode of LED3 4 Cathode of LED4 GND Ground GND Ground MLED5 Cathode of LED5 MAIN_IF2 Main Mode Select2 See
181. clock crystal oscillator Low power crystal oscillator for a low frequency clock input System clock request signal for control of external clock source Microprocessor interfaces including UART I2C bus combined and general purpose PATCH mechanism for code updates and corrections Firmware Interface drivers Bluetooth controller driver Link Controller LC Link Manager LM Host Controller Interface 237 3 Technical Brief G U8550 Bluetooth Schematic 9604 BGB202 S2 CLKREQ 220 25 GP CLK REF RESOUT2n gt non RESET N TCK JTAG 9 TMS JTAG ag TDI JTAG UARTRTS3 44 Gpio2 cts JTAG S UARTCTS3 41 GPIO3 RTS UART UARTRX3 43 GPIO4 TXD UART 21 UARTTX3 42 GPIO5_RXD_UART 1 20 2 35 6 DA IP 2 B PCMSYN 3 GPIO7 Fsc iP ant 2 T S 7 R656 83 1602 33 PCMCLK GPIOB DCLK VANLI 27 3 8 PCMDATA GPIO9 DB IP VANLO 22 1601 vaar 16 27nH 77 C543 100p 29 MM8430 26008 MCLK za XTAL1 SYS XTAL2 SYS 5 GND2 77 RTCCLK gt C842 100p 19 XTAL1_LPO GND3 H 8 xraL2 LPO GND4 6 24 ane 7 31 8 25 P1012 din Bluetooth BGB202 S2 ver
182. cording to the equation below N should be as large as possible with respect to time consumption OQ Average o o M n l Equation 1 6 Set UE on 10705ch and get Ak output2 Calculate Average Ak Ak LB according to the Equation 1 7 Calculate IF filter symmetry using the following equation IF SYM Ak IB Ak LB 8 Set UE on 10685ch and get Ak output2 Calculate Ak according to the Equation 1 9 Calculate selectivity level using following equation SE OB Ak IB 10 If the requirement is not met decrease LPBW and LPQ one step and repeat from 8 11 Store the resulting LPBW and LPQ in GD RF RX CONFIG ID 215 7 CALIBRATION F RX LNA Gain Switch and AGC Hysteresis Calibration Purpose This procedure calibrates the gain correction parameter of Ak in the AGC algorithm between GLNA 0 and GLNA 1 that is it establishes the gain difference in the LNA between high gain mode and low gain mode It also calibrates UL and LL the upper and lower Ak values where the should switch between high and low LNA gain AGC hysteresis O Q GQ GVGA DEC Ak GVGA GLNA AGC_CR RF Input Lev el dBm 3 84 MHz RF Input Level dB m 3 84 MHz Figure 10 4 LNA Gain Switch and AGC Hysteresis Parameters Set the UE in RX mode on 10695ch Feed a CW carrier at 2140 MHz with a power level of 65dB
183. ct Model U8120 for U8550 4 0 0 Build 100 E 0 xj LG Electronics Inc Handsets Lab LGE Signed Software ssw flash files Add There are no flash files to download into the target Remove Remove All Download All LGE GDFS map flash file There are no flash files to download into the target Log Messages Model 08120 190 6 DOWNLOAD NN 6 3 1 U8XXX Download 3 Download file selection A 1 Press Add button to select LGE SSW files to download B Don t Press Add1 button to select LGE GDFS file to download If you download old released LGE GDFS file The phone will break down This Add1 button will be used for upgraded if needed Only When LGE propose this action you must press this button 7 FlashRW for U8 fersion 4 0 0 Build 100V Global Settings LG Electronics Inc 3G Handsets Lab r LGE Signed Software ssw flash files There are no flash files to download into the target Download A LGE GDFS flash file Pathname There are no flash files to download into the taret Remove Log Messages Click to select file Model 08120 5232 i lt Before Select gt ersion 4 0 0 Build 100 1 f fei Global Settings LG Electronics Inc 3G Handsets Lab LGE Signed Software ssw f
184. dB TX Output Spectrum Frequency range amp fmin below the level of 30dBm 100khz BW within 2 4GHz 2 4835GHz TX Output Spectrum 20dB Bandwidth lt 1MHz Tx Output Spectrum Adjacent channel Po 20dBm 2MHz lt 40dBm gt 3MHz Modulation Characteristics 140kHz s delta f1 avg x175kHz delta f2max 115kHz at least 99 9 of all deltaf2max delta f2avg deata f1avgz0 8 Init Carrier Freq Tolerance lt 75KHz Carrier Frequency Drift 1 slot lt 25kHz 3 slot x 40kHz 5 slot lt x 40kHz Maximum drift rate lt 20 2 50 Out of Band Spurious Emissions Freq Range Operating Standby 30MHz 1 GHz 36dBm 57dBm Above 1GHz 12 75GHz 30dBm 47dBm 1 8 1 9GHz 47dBm 47dBm 5 15 5 3GHz 47dBm 47dBm 17 2 PERFORMANCE 5 2 Receiver Sensitivity single slot packets Sensitivity multi slot packets lt 0 1 700 BERs0 1 70dBm performance BER x 0 1 Low Mid High Frequency 2405MHz 2441MHz 2477MHz Interference Co Channel interference co channel Adjacent 1MHz interference 1MHz Adjacent 2MHz interference 2MHz Adjacent 23MHz interference 3MHz Adjacent 3MHz interference to in band mirror frequency image 1MHz Blocking Characteristic BER x 0 1 Q wanted signal 67dBm interfering Signal Frequ
185. e USBDM USB differential line USBSENSE GPIO40 USB detection input USBPUEN USB Pull up control VDDUSB Power supply for MARITA USB block Table 3 1 5 USB Signal Interface of MARITA USB regulator input voltage is 5 and uses external USB device power through IO Connector Output voltage is 3 3V and supplies to MARITA USB block USB is detected by MARITA GPIO40 USBSENES e VUSB 10K 51K VUSBSENSE 51K N501 C509 PWRRSTn gt VBUS 1 5 LP29851M5X 3 3 C510 _ 508 2 2u 4 7u 1608 1608 77 3 3V USB Regulator Figure 3 1 7 Schematic of USB Regulator 33 3 Technical Brief USBDP a USBDP USB m 1 er USBPUEN USBPUEN Figure 3 1 8 Schematic of MARITA USB block VBUS lt lt USBPUEN lt NUF2221W1T2 USBDM C D2 GND 33V USBDP lt lt gt gt 1 21 5 L701 USB FILTER Figure 3 1 9 Schematic of USB filter l 34 3 1 9 Folder ON OFF Detection There is a magnet to detect the folder status opened or closed magnet is close to the hall effect switch U1 on Keypad the voltage at Pin 1 U1 goes to Otherwise 2 8V 3 Technical Brief This folder signal is delivered to MARITA GPIO43 FOLDER DET VDIG R1 100K 2 017 A3212EEH T U1 1 2 NC2 GND2 PGND 6 5 74 7 VDD OUTPUT NC1 GND1 C1 10p Folder D
186. e GSM RX path is turned on the received RF signal which has passed through the antenna switch is filtered by GSM RF SAW filter to suppress any unwanted signal except GSM RX band The filtered RF signal is amplified by an LNA integrated in the transceiver IC N405 and is passed to a direct conversion demodulator The process for DCS RX is also the same as GSM RX case The logic for antenna switch is given below Table 3 7 1 VCG GSM TX OV OV 2 8 3 0V GSM RX OV OV OV DCS PCS TX 2 8V 3 0 2 8V 3 0V OV DCS RX OV 2 8 3 0 OV PCS RX 2 8V 3 0V OV OV WCDMA OV OV OV Table 3 7 1 Antenna Switch logic 78 3 Technical Brief B Receiver Block The circuit contains one frequency down conversion section for each receive band and a common base band amplifier and filter section The GSM900 RF part consists of a low noise amplifier followed by high dynamic range mixers The DCS 1800 and PCS 1900 part also have low noise amplifier connected to the other mixers The amplified RF signal is mixed with the quadrature local oscillator signal to create in phase and quadrature phase Q baseband signals The and Q signals are then buffered and low pass filtered The same baseband circuitry is used for all bands Balanced signals are used for minimizing cross talk due to package parasitics An impedance level at RF of 150 ohms for the GSM 900 input and 50 ohms for the DCS 1800 PCS 1900 input is chose
187. e changing RECDCI from 3 to 5 Set TXON 1 wait 1 ms and continue with stepping from 5 to 7 4 Set to the value that minimizes the 1950 MHz carrier If this involves a change of sign the TXON switching and delay sequence in point 3 must be executed Jump to 6 if the requirement is met 5 Find and set to the value that minimizes the 1950 MHz carrier This can be made by stepping RECDCQ from 0 to 7 with the TXON switching and delay sequence in step 3 6 If the requirements are not met repeat steps 3 4 and if necessary 5 once with the new RECDCI and found in 4 and 5 as initial values Otherwise proceed with step 6 7 Save the final dBc value for statistics and Store the calibrated parameters in GD RF TX CONFIG ID C TX LPF Bandwidth Calibration Purpose The low pass filters within the Ericsson DB 2100 hereafter referred to as DB 2100 are designed to prevent spurious emissions output from the TX IQ D A Digital Analog converters amp without adversely affecting the signal or causing a deterioration of the modulation accuracy The objective of this calibration is to determine the values for LPQ and LPBW that offer the best trade off against the system related requirements These settings determine the cut off frequency and should always have the same value Procedure Proposal 1 Use typical TX settings Generate a 960 kHz square wave at baseband without pha
188. e charging block is powered on and active when DCIO is asserted The DCIO signal is asserted when its voltage is above the voltage at VBAT As soon as generator is turned off and all parts of the charging block are functional and active Battery block indication as shown in Figure 3 4 18 1 1 1 Li I 1 4 2 3 88 V 3 87 3 78 V 3 77 3 13 V 3 72 3 55 V 3 54 3 23 V 100 66 E 65 44 43 25 d 24 4 d 3 0 96 Figure 3 4 18 Battery Block Indication 71 3 Technical Brief A Trickle charging When the VBAT is below a certain value 3 2V a current generator take care of internal trickle charge signal is active The charging current is set to 50mA Parameter Trickle current Table 3 4 8 Trickle charging spec B Normal charging When the VBAT voltage is within limits or the internal regulators are turned on the current source for trickle charging is turned off and all parts of the charging block are active The charging method is CCCV Constant Current Constant Voltage This charging method is used for Lithium chemistry battery packs The CCCV method regulates the charge current and the VBAT voltage This charging method prevents the battery voltage to go above the charge set in the CCCV algorithm Figure 3 4 19 shows the charging voltage a and charging current change b a Charging voltage b Charging current Figure 3 4 19 CCCV cha
189. e that centers the loop voltage within the specified limits 4 Store the selected CVCO in the memory TX VCO Centre Frequency Adjustment 5 Reset the radio D TX Loop Bandwidth Calibration Purpose The loop bandwidth is calibrated to match the pre filtering of the modulation in DB 2000 by adjusting the phase detector current Note This also indirectly adjusts the VCO gain that can otherwise not be calibrated This will ensure a correct transfer function for the modulation and keep phase error to a minimum 203 7 CALIBRATION Procedure Proposal 1 Put the ME in switched TX mode on mid channel in frequency interval 11 for EGSM with random modulation 2 Measure the RMS phase error at the RF connector 3 Tune the phase detector current IPHD until the phase error is minimized If two IPHD settings gave the same RMS choose the lowest value Measure 10 bursts for each value 4 Calculate and store the IPHD values in GDFS GD IPHD 8Temperature and 24Channel Compensation Band 5 The offsets in the table are steps in the IPHD Table 10 2 and all offsets refer to the calibrated value Trim at mid channel in room temperature Frequency Interval 10 11 12 13 4 O Or Oo Oo OO Ory gt NI NI NI NI N N NI NI N NI N PY NI NI I NI N PY NI NI I
190. e top level design also depicted in Figure GAM Subsystem Peripheral Subsystem GSM Core Subsystem DPS Subsystem SYSCON Figure 3 1 1 Simplified Block Diagram of Ericsson DB 2000 23 3 Technical Brief GAM Sub System CPU Sub Chip 946 CPU Sub System y ETM data EC 5 3 HB Slave GRAPHCON PDI z Instruction ETMIF Data Boot ROM Z 40 gt SRAM RAM 16k bytes 2 pones N 128kB j l 128kB 4K x 32bit GRAM T RAM Control System 160k byte cpu x I BRAM CID 7 0 16k bytes 5 AS T DEG AHB Slave 4K x 32bit GAMGON CDI civsync gt 4 EG 5 14 mum D Cache Control Control Domum CIRES N Slave Slave 1 i 15 i id 16Rq 8Ch Slave I Cache H D Cache key unissa DAT 16 3j o csu tual Di f b Li weloe Zl onceptual Diagram of bus AHB Lite CPU AHB2 DMA MEMEIS Interconnect Matri AHB Bridge Bridge APB Bridge AHB Bridge Bridge AHB AHB Slave Asynchronous Slave Slow Slave Data Slave 4 Slave 2 Slave Slave 32 4 4 USB 3 5 ba RAM LU RG 5 7kB HSSL lt gt TS z 3 TH 55 v E 8 RXIF gt 32 16 11 9 8 9 5 Integri
191. eck C740 amp R847 in Block D 8 to check inner line connection From C740 to R847 Yes Soldering Check Component R847 amp R875 In Power Source Block No Check The PowerSupply Change Board 135 4 TROUBLE SHOOTING 4 16 2 Step 2 FL401 Figure 4 16 4 Step 2 GSM PAM Block 0 Step 2 Check VBATI R407 in GSM PAM Block 2 to Check if main power Source input or not See The Step 3 Check FL401 to check if power Source input or not Check FL401 amp R407 inner Line connection Change FL401 Check Point C740 in Power Source Block 5 nog ms Check The PowerSupply To Check Power source Yes Check C740 amp R105 Yes in Block 06 to check inner line connection Soldering Check Component R847 amp R875 Change Board From C740 to R105 In Power Source Block 5 136 4 TROUBLE SHOOTING 4 16 3 Step 3 VBATI R307 Check point R875 C740 R847 Step 3 Check VBATI R307 in WCDMA PAM Block 3 Check Point C740 No in Power Source Block 6 Check The PowerSupply To Check Power source Check C740 amp R105 No in Block 3 6 to check inner line connection Change Board From R307 to R105 Soldering Check Component R847 amp R875 In Power Source Block 137 4 TROUBLE SHOOTING VDDB R2251 Bottom Figure 4 16 7 Power
192. ency Power Level 30MHz 2000MHz 10dBm 2000MHz 2400MHz 27dBm 2500MHz 3000MHz 27dBm 3000MHz 12 75GHz 10dBm Intermodluation Performance BER lt 0 1 9 wanted signal 64dBm static sinwave signal at f1 39dBm a BT modulated signal f22 39dBm payload PRBS15 Maximum Input Level BER lt 0 1 20 18 2 4 Current Consumption VT test Speaker off LCD backlight On Stand by 165Hours 8 48mA DRX 1 28 Voice Call 180Min 467mA Tx 12dBm 2 PERFORMANCE 130Min 646mA Tx 12dBm 223 6 28 paging 9period 220 380 2 5 RSSI TBD WCDMA TBD 4 gt 3 91 x2dBm 87 x2dBm gt 2 96 x2dBm 97 x2dBm BAR 2 1 101 x2dBm 107 x2dBm BAR 1 0 106 x2dBm 112 x2dBm 2 6 Battery Bar Indication Voltage BAR 4 3 6596 3 87 0 05V BAR 3 gt 2 4396 3 77 0 05V BAR 2 1 24 3 72 0 05V 1 Icon Blinking 396 3 54 0 05V 3 54 0 03V Talk 1min interval 3 Low voltage warning message 3 50 0 03V Standby 3min Inverval 2 3 15 0 03 WCDMA Talk Power OFF 3 23 0 03 else 19 2 PERFORMANCE 2 7 Sound Pressure Level Test Item Specification Sending Loudness Rating SLR MAX 8 3dB NOM 143dB MAX 15x3dB Side Tone Masking Rating STMR MAX 17dB over N
193. eps in the IPHD Table 10 4 and all offsets refer to the calibrated value Trim at mid channel in room temperature Frequency Interval 10 11 13 0 0 0 0 0 0 0 0 Table 10 4 IPHD Compensation for DCS Band D TX Power Calibration Purpose To tune the different DCS power levels of the power amplifier to output powers corresponding to values in GSM 05 05 and calculate the intermediate levels that ensure a good power versus time performance Procedure Proposal 1 Reset the DIRMOD block and select a mid channel using the trimmed value on the capacity array for VCO tuning and a default IPHD value as phase detector current Turn on dummy burst modulation 2 Use the Multi burst method to characterize the relation between output power and the DACvalue Then store the DAC values that give the closest approximations to the power targets defined in Table 10 5 208 7 CALIBRATION To avoid yield problems with the power template and switching transients spectrum a margin to the compression point of the PA should be observed However the output power must be kept within the tolerances specified in Table 10 5 Store DAC values in memory FullPower Initiate the intermediate value calculation which calculates and store the values in memory GD IntermediatePower Up Down 1 7 Band The difference between the t
194. etect gt FOLDER_DET Figure 3 1 10 Folder ON OFF Detector 35 3 Technical Brief 3 1 10 Bluetooth Interface 08550 supports Bluetooth operation using Philips BGB202 S2 Bluetooth module A General Description The Bluetooth interface utilizes the UART interface for control signals going to and from the Bluetooth module The UART is also used for data transmissions It uses the PCM interface for transmitting audio to and from the Bluetooth module The Bluetooth module uses both the 18 MHz master clock signal and the 32 768 kHz low frequency clock signal for internal timing within the Bluetooth module The intention is to use the low frequency clock as a low power timing provider and to use the 13 MHz as a high precision timing reference used mainly by the Bluetooth radio during operation The clock request mechanism is used to minimize current consumption for the total system The intention is to use the CLKREQ signal to ask for the master clock when needed for example when the Bluetooth radio is operating B UART Interface The UART interface is a standard interface and it includes the handshake signals RTS and CTS The following speeds can be achieved 9600 19200 38400 57600 115200 230400 460800 921600 and 1843200 bauds s C PCM Interface The interface is used to send audio to and from the Bluetooth module The interface is a synchronous interface using a PCM clock and a PCM sync signal for synchronization
195. g the battery is integrated using an ADC block ASIC Accumulated charge FGSENSE FGSENSE Figure 3 4 14 The analog front end of the fuel gauge block 82236 Pil OM i 0 SS 2205 F12 EGSENSE parcus Sa VSS_A C599 C548 cd VSSB 10 Did 55 SUB VSSBUCK Figure 3 4 15 Schematic of the fuel gauge block Name Unused Description FGSENSE VBAT Fuel gauge current sensing input positive FGSENSE VBAT Fuel gauge current sensing input negative Table 3 4 7 Fuel Gauge channel spec 69 3 Technical Brief 3 4 12 Battery Temperature Measurement The BDATA node the constant current source feed the battery data output while monitoring the voltage at the battery data node with GPADC This battery data is converted to the battery temperature Figure 3 4 16 shows the schematic of battery temperature measurement part DA R548 47 MOTOR lt VIBR c9 DACDAT Bio DACDAT R565 R2135 DACSTR 82k 5 180 R878 DACCLK 1 1 16 R2138 R843 VDIG PT501 VBATI A 77 100K E 47K A VSSPA 196 Cig VDDPA DAC Figure 3 4 16 Battery Temperature Measurement Type Unused Description Digital Input Output Unconnected current output Table 3 4 7 BDATA
196. gh i 3 f maximum 8 12 V maximum 2 8 09 V maximum 3 8 11 V Figure 4 19 2 EGSM Rx Mode MODE 0 SWT X 1 64 7 1024 1 croy LO maximum maximum maximum 3 Goto lt lt lt 0 3 Figure 4 19 3 EGSM Tx Mode 149 4 TROUBLE SHOOTING C DCS Rx mode MODE 2 SWRX 699 1024 2 lbcroy ANTSW1 LOW reo ea B ANTSW2 l i g 77 3 ANTSW3 I 3 LOW 1 1 8 15 V maximum 2 2 75 V maximum 2 8 11 V Figure 4 19 4 DCS Rx Mode D PCS Rx mode MODE 1 SWRX 661 1024 2 H ANTSW1 High ANTSW2 LOW ANTSW3 LOW Figure 4 19 5 PCS Rx Mode 150 4 TROUBLE SHOOTING E DCS PCS Tx mode DCS PCS Tx MODE 2 SWTX 1 699 0 1024 1 rt cent ANTSW1 igh amp 1 ANTSW2 1 00 V 2 laus EE LOW ANTSW3 1 80 V 3 1 maximum 2 74 V maximum 2 2 15 V maximum 3 8 11 V Figure 4 19 6 DCS PCS Tx Mode 151 4 TROUBLE SHOOTING F WCDMA mode WCDMA Mode MODE 4 WTXC 9750 1 1 43 0 0 255 68 ANTSW1 LOW 5 i 5 ps A NTSW2 V SaaS GAAP Ae Re HHHH uas 3 F LOW ANTSW3 iov PEN
197. h adapts itself by means of a control loop so that the linearity of the PA is kept constant The variable supply voltage is provided from the battery through a DC DC converter and a signal linearity detector sits at the PA output The detected signal at the PA output is compared with a reference supplied by the Vincenne the mixedsignalcircuit ASIC and the error signal is used in a loop filter which provides the control signal to the DC DC converter Reconstruction Filters The reconstruction filters consist of input buffers that provide the correct DC biasing for the preceding DAC in the digital baseband controller and a low pass filter for removing the unwanted high frequency components from the baseband input waveform The filter inputs are adapted for use with a current source type of input signal B IQ modulator The IQ modulator receives the incoming and analog baseband signals at baseband frequency and converts them to an intermediate frequency of 380MHz 88 3 Technical Brief C Variable Gain Amplifier VGA Comprising two cascaded variable gain amplifiers the VGA together with the RF mixer controls the power of the transmitter The first of these two amplifiers the so called QVGA enables fine tuning of the transmitter by varying the gain in 0 25 steps that is 0 0 25 0 5 0 75dB The second amplifier provides a 54dB gain range in 1 dB steps 54steps 55 levels D IF Band Bass Filter IFBP The IF fi
198. he average of each step pair Interpolate the gain steps in between the averaged measured values 212 7 CALIBRATION 7 Size of step between LG MG and MG HG and between each setting of RFBIAS 1 7 The main purpose is to find the relative difference at different frequencies Distribute with equal frequency offset except if there are known worst case frequencies Measured at 5 channels maximum and minimum steps reported Average value of minimum and maximum should be used in following calculations 8 Measure properties Measure the following properties using a modulated signal WPA gain expansion versus output power on mid channel Compensation needed for maximum output power over the band 13 channels 2 Perform offline calculations 1 Calculate the compensation values for Table 10 6 Store these values in TB SEL ID 2 Extract the range of needed compensation tables minimum and maximum 3 Calculate the expected compensation for each table dB use table 0 for the table that is 0 dB or closest to 0 dB and spread out the rest to achieve equidistant compensations 4 Calculate and store the 24 sets of tables GD TX GAIN ID to RF TX TB23 ID Each set of tables shall include One High gain table 44 bytes One Low gain table 44 bytes One RFBias table 22 bytes One WDCDCRef table 44 bytes One WPABias table 44 bytes One value for IQ Gain 1 bit
199. ication Color Remark C317 CAP CERAMIC CH P 0000115 22 50 4 1005 318 0000128 100 pF 50V J NPO TC 1005 R TP CAP CERAMIC CH 0000181 4 7 pF 50V NPO 1005 R TP C319 C320 CAP CERAMIC CH 0000186 33 pF 50V J NPO 1005 R TP C321 CAP CERAMIC CHIP 0000186 33 pF 50V J NPO 1005 R TP CAP CERAMIC CH 0000155 10 nF 16V K X7R HD 1005 R TP C322 C323 CAP CERAMIC CH 00110 10 pF 50V D NPO TC 1005 R TP C324 CAP CERAMIC CHIP 0000110 10 pF 50V D NPO TC 1005 R TP CAP CERAMIC CH 0000155 10 nF 16V K X7R HD 1005 R TP C325 C326 CAP CERAMIC CHIP 0000110 10 pF 50V D NPO TC 1005 R TP C327 CAP CERAMIC CHIP 0000105 4 pF 50V C NPO TC 1005 R TP C328 CAP CERAMIC CHIP 0000122 47 pF 50V J NP0 TC 1005 R TP C330 CAP CERAMIC CHIP 0000115 22 pF 50V J NPO TC 1005 R TP o CAP CERAMIC CHIP ECCH0000115 22 pF 50V J NP0 TC 1005 R TP C331 C332 CAP CERAMIC CH 0000155 10 16 7 1005 C333 CAP CERAMIC CHIP 0000128 100 pF 50V J NP0 TC 1005 R TP CAP CERAMIC CH 0000130 150 pF 50V J SL 1005 R TP C334 C335 CAP CERAMIC CH ECCH0000115 22 pF 50V J NP0 TC 1005 R TP C336 CAP CERAMIC CHIP 0000149 3 3 nF
200. icrophone Signal Flow MIC is enable by MIC Bias MICBAS MICIP MICIN signals to ABB Vincenne Check Points Microphone bias Audio signal level of the microphone Soldering of components Signal from the MIC MIC gt N504 TJATTE2 on main board C567 C568 on main board Vincenne 121 4 TROUBLE SHOOTING START Check the MIC bias level at the pad of MIC X503 Check the signal level Is the level of MIC AND MIC at C568 at the putting 2 4Volt Audio signal in MIC Resolder C566 C567 C568 A few hundred of mV and try again of the signal measured 2 If fail again change the main B d Change the MIC Change the main B d Does it work properly 122 4 TROUBLE SHOOTING C566 123 4 TROUBLE SHOOTING V div OFFset r a Glotel BH 20MH2 2080MMHz Proba sensed x16 63 sweeps low n si 2 1 742 8 174 234 432 11 448 1 S s STOPPED Nie 3 ected 5888 _ 2 DC Measured Some Noise Signal 124 4 TROUBLE SHOOTING 4 12 4 Headset Receiver Voice call Video Telephony MP3 START Connect the phone to network Equipment and setup call Setup 1KHz tone out Insert Headset Does the Headset icon display on the main LCD Does the level of R2252 under 0 5 2 Does the sine wave appear at C572 C573 2 Change the B d
201. ide keys and 3 MOD keys END key is connected to ONSWAn for Vincenne KEYOUTO KEYINO SIDE1 KEYIN2 3 Technical Brief KEYINS KEYIN4 KEYOUT1 SEARCH KEYOUT2 KEYOUTS KEYOUT4 KEYOUTS5 77 gt ONSWAn Di END Table 3 1 7 Key Matrix Mapping Table gt gt gt gt gt x x A x x SIDE KEY Keypad 5 SIDE1 SIDE2 55 D REL KEYOUTO SIDE3 m 3 8 8 B 1 4 7 UP I 1 gt G o 9 o Q 9 77 lt KEYOUT2 2 5 8 0 DOWN 2 6 9 10 DOWNI mae L1 L1 L1 gt lt 3 6 9 L RIGHT 3 8 TJ SHARP1 RIGHT1 1 2 9 3 4 1 lt KEYOUTA SEND CLEAR BACK GAME LEFT E La gt lt KEYOUTS MENU SEARCH MULTI CAM OK MENU1 SEARCH1 MULTI I I gt lt Figure 3 1 14 Schematic of Keypad 41 3 Technical Brief 2 GND RIGHT CENTER LEFT Table 3 1 8 MOD Key Matrix Mapping Table DCIN 3 lt lt KEYINI 22 KEYIN2 KEYIN3 CPO_LTC_LCDBL lt lt INA LEFT
202. ier 91 3 Technical Brief 3 8 3 Frequency Generation The Wopy W CDMA Receive ASIC contains the active elements for a 13MHz VCXO which is designed to be the reference frequency of the UE There are two synthesizers in the W CDMA part of the radio an intermediate frequency IF synthesizer and a radio frequency RF synthesizer They generate the Intermediate Frequency Local Oscillator IFLO and Radio Frequency Local Oscillator RFLO signals Both synthesizers are used in both the transmitter and the receiver which gives the radio a fixed duplex distance of 190MHz The RF synthesizer is in the Wopy W CDMA Receive ASIC except for the loop filter which is external The 13MHz clock is used as the reference and the phase detector frequency is 200kHz The programmable divider makes the RF synthesizer cover the 2300 2360MHz band The IF synthesizer is in the Wivi W CDMA Transmitter ASIC except for the loop filter The 13MHz is used as the reference and the phase detector frequency is 1MHz The IF VCO runs at 1520MHz given that the programmable reference divider is set to 13 The synthesizers are controlled by Wanda W CDMA digital base band coprocessor ASIC via the serial bus to Wivi W CDMA Transmitter ASIC and Wopy W CDMA Receive ASIC 92 3 Technical Brief A IF PLL The IF LO frequency synthesis comprises the four following par is Input buffer A 13MHz input buffer with DC biasing provided at source VCO
203. iff and park to have a correct timing on the Bluetooth air interface without having the master clock running The low frequency clock is always present in some applications even when the chipset is powered down 36 3 Technical Brief F BGB202 S2 General Full module Only need to external antenna and reference clock Bluetooth Specification version 1 1 Dimensions 7 x 8 x 1 8 mm Power class 2 10m Radio Part Fully integrated near zero IF receiver with high sensitivity typical 82 Advanced DC offset compensation for improved reception quality RSSI with high dynamic range Programmable output pre amplifier Fully integrated low phase noise VCO operating in the 5 GHz frequency range Internal shielding for better EMI Electro Magnetic Interference immunity Baseband Part Embedded ARM7TDMI microprocessor 224 kBytes embedded ROM 32 kBytes SRAM and 8 kBytes internal RAM iRAM for BB controller Watchdog timer and Two 32 bit system timers Bluetooth controller including scrambling CRC generation checking FEC encoding decoding and ciphering according the Specification of the Bluetooth System Version 1 1 Bluetooth connections supporting Maximum 3 active connections ACL One voice connection SCO CVSD transcoder RF interface RSSI measurement On chip 1 8 V voltage regulator 8 bit D A and A D conversion for various purposes e g PA control Power on reset System
204. in 5 of U502 or C504 1 8V Pin 5 of U503 or C523 2 8 YES Change 1 3M Camera Change U502 or U503 1 NO NO 1 3M Camera Operation OK Change the Camera amp LCD FPCB gt O YES 1 3M Camera Works Change the Main Board 1 2 101 4 TROUBLE SHOOTING CN2 CN702 6805172472137 102 4 TROUBLE SHOOTING 4 7 VGA Camera Trouble Camera control signals are generated by Marita START Press END Key to turn on the power NO Is the circuit powered Follow the Power On Trouble Shooting 3 econnect the 50pin B to B connecto CN701 and VGA Camera Connector YES VGA Camera Operation OK NO Pin 5 of U501 or R721 2 8V YES Change VGA Camera Change U501 1 VGA Camera Operation OK YES VGA Camera Works Change the Main Board Change the Camera amp LCD FPCB z 103 4 TROUBLE SHOOTING HH wu LE BAR RAA kiri ee n ete 84444442444444444 4666858 a NEC 104 4 TROUBLE SHOOTING 4 8 Main LCD Trouble LCD control signals are generated by Marita START Press END Key to turn on the power NO Is the circuit powered Follow the Power On Trouble Shooting YES Disconnect and Reconnec
205. ing finished gt 198 6 DOWNLOAD 6 3 1 UBXXX Download 7 Trouble shooting Check these questions when trouble happens A Check if UART amp USB Port configuration is right B Do not change RS 232 baud rate 115200BPS It is fixed and never changed C Check if UART amp USB Cable is connected D You can t select any GDFS File If you do Trouble will happen in the phone E Don t disconnect downloading cable while downloading LGE SSW images into phone 199 6 DOWNLOAD 7 CALIBRATION 7 1 General Description This document describes the construction and the usage of the software used for the calibration of LG s GSM GPRS WCDMA Multimedia Mobile Phone U8550 The calibration menu and their results are displayed in PC terminal by Mobile phone This calibration software includes GSM DCS WCDMA Band parts calibration and Battery calibration This calibration software was called XCALMON eXtended CALibration and MONItor program From now on the calibration software will be called XCALMON in this document 7 2 XCALMON Environment 7 2 1 H W Environment PC with RS 232 Interface amp GPIB card installed GSM GPRS WCDMA Multimedia Mobile Set U8550 Agilent 8960 Series 10 E5515C Instrument E1985B ver 04 08 Tektronix PS2521G Power Supply ETC GPIB cable Serial cable RF cable Power cable Dummy battery 7 2 2 S W Environment National Instrument GPIB amp VISA ver 2 60 full drive
206. ipment and setup call Setup 1KHz tone out Does the sine wave appear at C572 C573 Change the main board The sine wave not appear Change U507 Change the main board The sine wave not appear Change U508 The sine wave appear Resolder CN703 num 22 23 The sine wave not appear The sine wave appear YES Change U504 U505 each The sine wave not appear NO Change the Key PCB NO Change each Speaker YES Does the sine wave appear at C584 C585 YES Does the sine wave appear at R582 R584 YES Does the sine wave appear at R533 R539 Does the sine wave appear at CN703 num22 23 Does the sine wave appear at CN3 CN4 YES Can you hear sine wave out of each speakers YES END 118 CN703 122 23 R533 R539 4 TROUBLE SHOOTING K R582 R584 C584 C585 119 4 TROUBLE SHOOTING CHANEL 2 Trace E Coupling wer bab le Mal ee a high OF Faste in Fraqi21 l 212 kHz 8 183 111 527 0 if 2 44B V Dr sure EE ceci 2 Measured 1khz Sine Wave Signal 120 4 TROUBLE SHOOTING 4 12 3 Microphone Voice call Voice Recorder Video Recorder M
207. lash files Pathname Add D WU8I00 SWw VOS0BWUSI 10 2004040 Wdrive 3671 D WU8100_S WW V090B 10 20040402 W drive c ss w _ Riec Italy ssw 19271 KB EE 00 404 Remove All Download Addl Remoye U81X0 download file is selected gt Model 18120 Pon RS232 After Select 191 6 DOWNLOAD 6 3 1 08 Download 4 Connect amp Download A Click on connector icon amp 58 to connect to the phone Check the Dialog Box that say Please switch on the target B Connect the phone to PC via Cable for Downloading Phone should be turned off C Turn the phone on to connect to PC Lg Global Settings LG Electronics Inc 3G Handsets Lab LGE Signed Software ssw flash files Pathname 2 D WU8100 SWWUBIS0WUSI80 100 SSWWUSI80 FileSystem Italy 26743 D WUS8100 SWWUSI80WUS180 100 SSWWdrive media ssw 4720 KB 2 D WU8100 SWwwUS8180WU8180 V100 SSWWdrive Rec ssw 2622 KB D WUBIO0 SWWUBI80WUST80 100 SSWWdrive ssw 14158 KB 2 D WU8100 SWWUBI80WUS180 100 SSWWUGT80 gsm wcdma 4m 15565 LGE GDFS lt flash file gt Please switch on the target Comer Log Messages all PRR SRE REELS RSE ER ERE ERE REE RRR ERE EG FlashRW for U8120 gt Versio
208. le 10 3 4 Store DAC values in memory FullPower 5 Initiate the intermediate value calculation which calculates and store the values in memory GD IntermediatePower Up Down 1 7 Band 6 The difference between the transmitter power at two adjacent power control levels measured at the same frequency shall not be less than 0 5 dB and not more than 3 5 dB 205 7 CALIBRATION Parameter Target Full Power dBm Tolerances dB Table 10 3 Target Power Levels for EGSM G RSSI and AGC Calibration Purpose This procedure satisfies the two following requirements Calibrate an absolute power level on the antenna to a corresponding RSSI value This value together with a pre defined slope figure is then used to calculate the RSSI value of an arbitrary received antenna power The formula y kx m is used Where is the slope value x the RSSI value y the actual level and m is an offset value Calculate the attenuation when the Low Noise Amplifier is switched off in the receiver branch The attenuation value is stored in the flash memory and used when very high input signals are fed into the ME Procedure Proposal 1 Select switched receiver on a mid EGSM Channel 2 Feed a modulated 68 5 dBm signal on the same mid EGSM Channel to the antenna input Measure the RSSI value calculate the RSSI table and store the value in GDFS as parameter GD RXLEVS DBM BURST M BAND 3
209. le controls the gain for all types of power change including the inner loop power control and maximum output power of the platform The purpose of this calibration is to complete the TX Power gain table with values for VGA QVGA RFBIAS WPABias and WDCDCREF that meet the specified requirements for innerloop power control and Maximum output power The size of hysteresis area must also be found These calibrations are designed to conform to the ME maximum output power inner loop power control change of TFC and PRACH preamble tolerances requirements specified in 3GPP Spec TS34 121 Procedure Proposal This calibration consists of two parts first measurements and then an off line calculation The measurement results are used for characterizing the hardware so that proper settings can be calculated for all tables Settings and limitations are also used from maximum output calibration 1 Perform measurements 1 VGA behavior in LG Low Gain mode PABias should not be offset and RFBIAS should be 1 2 VGA behavior in MG Medium Gain mode PABias should not be offset and RFBIAS should be 1 3 behavior in LG mode 4 IQ Gain behavior in LG mode 5 WPABias gain step size Every eighth setting is measured twice For better accuracy take the average of each step pair Interpolate the gain steps in between the averaged measured values 69 WDCDCREF gain step size Every fifth setting is measured twice For better accuracy take t
210. lor Remark 6 LD17 DIODE LED CHIP EDLH0006001 Blue 1608 R TP Blue SMD LED ODE LED C EDLHO0006001 Blue 1608 R TP Blue SMD LED ODE LED C EDLHO0006001 Blue 1608 R TP Blue SMD LED pese pene E ODE LED C EDLHO0006001 Blue 1608 R TP Blue SMD LED ODE LED C EDLHO0006001 Blue 1608 R TP Blue SMD LED pene pem ODE LED C EDLHO0006001 Blue 1608 R TP Blue SMD LED DIODE LED CH EDLHO0006001 Blue 1608 R TP Blue SMD LED gemmam O _ pene peer RHY0000223 150 ohm 1 16W J 1005 R TP 0000223 150 ohm 1 16W J 1005 R TP gt fae 1 a 0000223 1150 ohm 1 16W J 1005 R TP 0000223 150 ohm 1 16W J 1005 R TP pem _ 0000223 150 ohm 1 16W J 1005 R TP 0000223 150 ohm 1 16W J 1005 R TP 3 0000223 150 ohm 1 16W J 1005 R TP 0000223 150 ohm 1 16W J 1005 R TP N 1 0000223 150 ohm 1 16W J 1005 R TP 0000223 150 ohm 1 16W J 1005 R TP 1 0000223 1150 ohm 1 16W J 1005 R TP RHY0000223 150 ohm 1 16W J 1005 R TP KNEE NE 6 TVS5 DIODE TVS EDTY0008501 5 V 50 W R TP small size TVS6 DIODE TVS EDTY0008501 5 V 50 W R TP small size o SPEYOO PCB KEYPAD SPEY0035701 4 0 5 mm DOUBLE 258 10 EXPLODED VIEW
211. ls and image areas Images can be moved and merged with other images and text The GRAPHCON block receives graphical objects from GRAM and performers the appropriate graphical manipulation The resulting data is transfers to the display interface PDI GRAPHCON can receive images from the camera data interface CDI and send them to the PDI automatically GRAPHCON performs conversion from YUV to RGB and can scale zoom still or video images D Programmable Display Interface PDI Block The programmable display interface is designed to interface both parallel and serial display modules The display data is transferred from the 32 word FIFO on GAMCON to the display module via the PDI block The PDI block is built around a micro controller and executes 16 bit instruction words to individually control the ports It has a 128 byte program memory programmable by the CPU which can store up to 64 instructions The CPU transfers all set up and control data to the display Data is transferred to PDI as 32 bit words which in turn writes 8 bit data to the display The programmable PDI block is configured at the software build stage to support either parallel interface such as or serial interface such as SSI or 12 44 3 Technical Brief E Camera Data Interface CDI Block The camera data interface CDI block is designed to support a range of still image camera modules An 8 bit parallel bus supports data transfer from
212. lter Bandwidth Cal Start lt lt lt lt lt lt lt lt lt lt LPQ LPBU 5 Diff 25 525808 gt gt gt WCDMA Low Pass Filter Bandwidth Cal End lt lt lt lt lt lt lt lt lt lt gt gt gt WCDMA Rx LNA Gain Switch amp AGC Hysteresis Cal Start lt lt lt AGC_LL 36 AGC_UL 46 AGC_CR 28 gt gt gt WCDMA Rx LNA Gain Switch amp AGC Hysteresis Cal End lt lt lt gt gt gt WCDMA RX AGC Gain Max and Rx RSSI Cal Start lt lt lt lt lt lt lt lt lt lt lt RX AGC Gain Max Calibration RX RSSI Calibration gt gt gt WCDMA RX AGC Gain Max and Rx RSSI Cal End lt lt lt lt lt lt lt lt lt lt lt gt gt gt Total Fail Number in WCDMA Calibration 8 gt gt gt WCDMA 811 Items Calibration End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt gt gt gt RF 811 Items Calibration End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt gt gt gt ITP Uersion lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt UERS 8 831226 1357 INI17 CXC125577 7 PLATINUM TP 16H P2R VERS 1 CXC125469 ECSJHEE Fri fug 22 13 51 36 2003 UERS 2 CXC125495 R5B gt gt gt BB R11 Items Calibration Start lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt
213. lter suppresses spurious signals and eliminates unwanted frequency components generated in the IQ modulator and subsequently amplified in the VGA The filter is tuned using an external RLC load as shown in Figure 3 8 4 External tuned load lt a SHAE a 8 Figure 3 8 4 Principle Schematic of the IFBP 89 3 Technical Brief E RF Mixer and Buffer The RF mixer converts the signal output from the IF BP filter from an intermediate frequency IF to the final radio frequency RF The mixer can be switched between three different gain levels high gain HG medium gain MG and low gain LG The LO buffer provides the buffering for either an internal LO signal generated within the internal RFPLL or an external LO signal applied to the RFLO RFLOBAR pins External DC blocking is necessary for the external LO signal The RF buffer is used to drive an external PA stage The buffer is of an open collector design The gain switching together with the VGA amplifier at IF will enable an output power control in 0 25 dB Steps over no less than 80dB The programmable bias in the high and mid gain settings is specified as a reduction of bias current from the maximum bias condition It should achieve a reduction of bias current from the nominal value of 17mA to 3mA signal ended in 7 steps l
214. m Set the UL and LL to maximum GLNA is forced to low gain mode Get average Ak from Equation 1 and save it Ak LG Set the UL and LL to minimum GLNA is forced to high gain mode Get average Ak HG LG HG Correction Round off Correction to integer CR and store it in GDFS CONFIG ID CR is an algorithm parameter and is set to DB 2100 RFIF Calculate AGC_LL 8 AGC_CR and AGC_UL 18 AGC_CR and store them GDFS GD RF RX CONFIG ID AGC LL and AGC UL are AGC algorithm parameters and are set to DB 2100 RFIF 216 7 CALIBRATION G RX AGC Gain Max and RX RSSI Calibration Purpose To prevent wind up in AGC algorithm this procedure calibrates the absolute power levels at the antenna connector against RSSI values and the maximum gain setting for AGC Reference 6 specifies that the reporting range of the RSSI should be between 100 dBm to 25 dBm The specified accuracy requirement is applied to the received power from 94 through 50 dBm This is the last RX calibration LPBW CR LL and UL must be calibrated according to above calibrations respectively and applied to this calibration Initially the anti wind up is turned on using GMAX 127 Use the calibrated value after step 2 otherwise the AGC wind up occur at the beginning of the RSSI calibration Procedure P
215. mera data interface 25 3 Technical Brief F GSM Hardware Subsystem The GSM subsystem is a stand alone sub chip incorporating GSM modem and interface to GSM radio together with memory control MEMSYS and internal RAM IRAM The hardware peripheral blocks are RXIF FCHDET CRYPTO EQU NODI 4 x CHD GPRS CRYPTO GPRS CRC24 CHE DIRMOD CLKCON SERCON TIMGEN MEMSYS and IRAM The peripherals are accessible to the AHB CPU only an asynchronous bridge The dual port IRAM is accessible to the AHB CPU and DMA by a synchronous AHB slave interface G System Control Subsystem The system controller subsystem SYSCON is primarily responsible for generating clock signals and distributing the clock and reset signals within the ASIC and certain external devices The GSM core GAM and DSP subsystems include their own system controllers that are sourced from SYSCON SYSCON consists of analog and digital PLL clocks and a clock squarer The block is a slave peripheral on the slow APB bus under control of the CPU The programming of SYSCON controls the fundamental modes of operation within the ASIC Individual blocks can also be reset and their clocks held inactive by accessing the appropriate control registers SYSCON also controls the requesting protocol through which different subblocks in Ericsson DB 20000 can request clocks derived from the system clock The system controller also stores the chip ID number in a read only register
216. n 4 0 0 LLLI Waiting for Z from the target STEP For Downloading SSW w Z fFSEZ 192 6 DOWNLOAD 6 3 1 08 Download 5 USB Driver Install A If you use FlashRW Tool firstly Error will happen because of USB Driver uninstalled You have to do FlashRW USB Driver Installation only at the first time of installation lectronics Inc 1 Size D WU8100_S Ww VOS0B WU81 10_V090B_20040402Wdrive media ssw 3671 D WUBIOO SWW VOSOBWUGI 10 0908 _20040402Wdrive_c ssw 10488 KB 0 WU8100_SWWVOS0B WUBI 10 _20040402WFS_Rec Italy ssw 19271 D WU8100_S WW VOSOBWUSI 10_V090B _20040402WU8100_phone_wee 11404 KB Bytes sent to phone 7284 Prologue response EaT Prologue done EbS Loading loader please wait Bytes sent to phone 47604 Payload response EdQ End time Thursday April 08 2004 23 48 07 Elapsed time 00 00 05 Error occurred during port change 193 6 DOWNLOAD B Push the Next Button in Found New Hardware Wizard C Select Search for a suitable driver for my device in Found New Hardware Wizard Found New Hardware Wizard W elcome to the Found New Hardware Wizard This wizard helps you install device driver for hardware device To continue click Next Found New Hardware Wizard Install Hardware Device Drivers
217. n to minimmize current consumption at best noise performance The low gain mode in GSM 900 is used in high input signal mode There is no gain switch in DCS 1800 PCS 1900 Figure 3 7 1 shows a block diagram of the receiver block MIXHI RF1800p gt LNA RF1800n gt 1800 MHz LOHI LOHQ IRA gt RF1900p NT RF1900n gt e e 1900 MHz MIXHQ I QRA e RF850 900p gt LOLI RF850 900n ioia 850 900 MHz LNAL LNAHi LNAH2 BB GNDRF BIAS CIRCUITS Figure 3 7 1 Block diagram of receiver part 79 3 Technical Brief C LO Block The LO signals from the receive VCO section drive the dividers for GSM 900 DCS 1800 and PCS 1900 respectively to provide quadrature LO signals to the receive mixers The LO signal is also supplied to the prescaler and transmit output buffer Figure 3 7 2 shows a block diagram of the LO block LOLBUFI To MIXLI DIVIDER T From GSM 850 900 RX VCO To MIXLQ 90 LOLBUFQ 4 lt GNDLO To prescaler q 4 lt LOHBUFI To MIXH DIVIDER From GSM 1800 1900 RX VCO To MIXHQ 90 LOHBUFQ LOL LOH BIAS CIRCUITS Figure 3 7 2 Block diagram of the LO part 80 3 Technical Brief D VCO Block The VCOs are fully integrated balanced LC oscillators with on chip resonators The receive V
218. nnector 21 LCD Module 40 BtoB Connector 108 4 10 Keypad Backlight Trouble START Press END Key to turn on the power YES Keypad Backlight Works NO NO Backlight Control Signa is 2 8V at R741 2 Resolder or Change Q701 YES Keypad Backlight Works Change Keypad Keypad Backlight Works 109 4 TROUBLE SHOOTING 2 7K R741 2 KEY LED ONOFF 4 TROUBLE SHOOTING gt 85 E E 201 Dx ost A 081 201 X ost 901 rm nse ost 101 m ost x mee 091 vH 15 8 831 ost 92 HvIS 8 ost lt E o m m tn e 5 g b HvIS H831 D AR x Pi AA 091 224 091 d m ost pis HvLS 883 1 ost lt ul gt x 110 4 TROUBLE SHOOTING 4 11 Camera Flash Trouble START Press END Key to turn on the power NO Follow the Power On Troubl 15 the circuit powered YES Disconnect and Reconnect the 26pin BtoB connector FPCB and Main
219. o ________ gt gt exTLDo 88 8 8 3 539 D Vent VBAT C PEC a 22 22 1K A A REF D Liz A 100K von e 17 dia voorp 1 BATA R2150 0 51 77 i sk als E3 vear aR ZB ES D VDDBUCK B FP 88 RB T ieosisog D 21 5 VBAT C I T T zB e SE PBUCK A Rox 55 VBAT D m 77 MOTOR UMT2987A T106 77 T n e 0103 25 8 js Eme Um uma CARN sweucx 1 masona i4 ADCSTR apao 93 Lugar cal sran I iH 85 WPOWERSENSE Dacor 227 WDCDCREF i893 RS CN502 WRFLOOP j SPAS DACO2 WPAREF gt EARP JACK DET 311 DACOS VCXOCONT 1502 s VBACKUP gt EARM ose EIE AE 55 TXON UM qu pare 552 470p sunsemzoswi FIO T 1 cssa 0 3 2 ocio x R59 0 x 777 DH BEARP El E 02 CHSENSE R2253 CHSENSE BEARN gt JACK DET F m z N50 IP4025CX20 LF T at FUL raseNsE Tren C558 C5
220. ohm 1 16W J 1005 R TP R9 RES CHIP 0000201 0 ohm 1 16W J 1005 R TP SPCYOO PCB FLEXIBLE SPCYO0057801 0 5 mm MULTI 6 SURYOO RECEIVER SURYO0009501 55 107 dB 32 ohm 11 07 3T SVCYOO CAMERA SVCY0009101 CMOS MAIN M 220 220 S 128 160 M 46 5 52 3 4 3 5 7 4 3 SVLMOO LCD MODULE SVLMO0015201 262k SOURCE HD66781 GATE HD66783 SUB LCD DRIVE IC LGDP4511 3 0 2 0 dBd Green SNGF00 JANTENNAGSM EIXED 2979011001 GSM900 DCS1800 PCS1900 WCDMA2100 fixed SACYOO ASSY FLEXIBLE SACY0038101 Silver 255 T 10 EXPLODED VIEW amp REPLACEMENT PART LIST Location Part Number No Level Description Specification Color Remark SACEOO ASSY FLEXIBLE SMT 00 7 SACE0033901 PCB ASSY FLEXIBLE SMT SACD0026301 CONNECTOR BOARD TO 0025201 Silver a 26 PIN 0 4 mm ETC H 0 9 Header 0019101 DIODE LED MODULE EDLM0005502 RES CHIP ERHY0000214 24 PIN 0 4 mm STRAIGHT H1 5 MALE White 3 LED 3 5 2 8 1 8 R TP Flash LED 51 1 16W J 1005 R TP SPCYOO PCB FLEXIBLE 5 0058201 SVCYOO CAMERA SVCY0007701 SAEYOO PCB ASSY KEYPAD SAEY0044401 POLYI 0 5 mm BUILD UP 6 FPCB CAMERA CMOS MEGA 1 3M ESS Sensor PCB ASSY SAFB00 KEYPAD INSERT 5 SAKY00 PCB ASSY SIDEKEY 5 0005401 SUSYOO SPEAKER SUSY0017501 SAEBOO01
221. r install Agilent 8960 VXI driver E1960 install XCALMON EXE files OS Window98 Window2000 WindowXP Serial port configuration Baud rate 115200 Char length 8bit No Parity No Flow control Stop bits 1 bit 7 2 3 Configuration Diagram of Calibration Environment GPIB Cable Power Cable RF Cable NoteBook or PC Serial Cable Figure 7 1 Calibration Configuration Figure 200 7 CALIBRATION 7 3 Calibration Explanation 7 3 1 Overview In this section it is explained each calibration item in the XCALMON Also the explanation includes technical information such as basic formula of calibration and settings for key parameters in each calibration procedure At first when any of calibration is done the results are displayed in the XCALMON result window and the result of calibration will be stored in GDFS Global Data Flash Storage 7 3 2 Calibration Items A EGSM 900 Band MODA D MD bit Delay Calibration RXVCO Varactor Operating Point Calibration TXVCO Varactor Operating Point Calibration TX Loop Bandwidth Calibration VCXO Calibration TX Power Calibration RSSI and AGC Calibration B DCS 1800 Band RXVCO Varactor Operating Point Calibration TXVCO Varactor Operating Point Calibration TX Loop Bandwidth Calibration TX Power Calibration RSSI Calibration C WCDMA Band RF VCO Center Frequency Calibration TX Carrier Suppression Calibration
222. ransFlash Yes Re insert TransFlash VTF C636 is 2 857 No Check output of U510 Resolder C636 Yes TF DETECT R653 is 2 8517 No Resolder R653 Yes TransFlash work well Yes Finish Change main board 98 4 TROUBLE SHOOTING 4 5 Keypad Trouble Keypad singals to MARITA and VINCENNE through board to board connector START Press the Keypad YES Keypad operates well Resolder B to B connector CN703 Main Bid or CN1 Keypad Check B to B connector short CN703 Main Bid CN1 Keypad Keypad operates well Change Keypad Keypad operates well Change Main Board 99 4 TROUBLE SHOOTING Keypad signals to MARITA and VINCENNE through board to board connector Pin 16 21 m KEYOUT5 KEYIN0 KEYOUT4 KEYIN1 lt KEYOUTS 2 gt KEYOUT2 KEYIN3 gt KEYOUT1 KEYIN4 sa KEYOUTO OMSWAn M Pin 4 9 c KEYOUT5 Pin 16 21 KEYOUT4 KEYINO KEYOUTS KEYIN1 KEYOUT2 KEYIN2 KEYOUT1 KEYINS KEYOUTO KEYIN4 Pin 4 9 OMSWAn 100 4 TROUBLE SHOOTING 4 6 1 3M Camera Trouble Camera control signals are generated by Marita START Press END Key to turn on the power NO Is the circuit powered Follow the Power On Trouble _ econnect the 26pin B to B connector CN702 and 1 3M Camera Connector Shooting YES 1 3M Camera Operation OK NO P
223. ransmitter power at two adjacent power control levels measured at the same frequency shall not be less than 0 5 dB and not more than 3 5 dB Parameter Target Full Power dBm Tolerances dB Table 10 5 Target Power Levels for DCS 209 7 CALIBRATION E RSSI Calibration Purpose This procedure calibrates an absolute power level on the antenna against a corresponding RSSI value This value together with a pre defined slope figure is then used to calculate the RSSI value of an arbitrary received antenna power The formula is used Where k is the slope value x the RSSI value y the actual level and m is an offset value Procedure Proposal 1 Select switched receiver on a mid DCS Channel 2 Feed a modulated 68 5 dBm signal on the same mid DCS Channel to the antenna input Measure the RSSI value calculate the RSSI table and store it to the memory BAND RXLEVS DBM BURST 21 1 byte 7 3 5 WCDMA Calibration Items A RF VCO Center Frequency Calibration Purpose This procedure is designed to calibrate the RFVCO Radio Frequency Voltage Controlled Oscillator center frequency of the Ericsson RF 2110 hereafter referred to as the RF 2100 and ensure that all channels can be reached with sufficient margin The objective of the calibration is to determine a CVCO Center VCO value that guarantees the functionality of the RFLO Radio Frequency Local O
224. rding to the data rate DTX DPCH off Change of TFC minimize interference between UE Power setting in uplink compressed 3dB after 14slots transmission gap Occupied Bandwidth OBW 5MHz 99 35 15 Af 2 5 dBc Af 2 5 3 5MHz 30k 35 1 Af 3 5 dBc Af 3 5 7 5MHz 1M Spectrum emission Mask 39 10 Af 7 5 dBc Af 7 5 8 5MHz 1M 49 dBc Af 8 5 12 5MHz 1M 14 2 PERFORMANCE Specification 33dB 5MHz ACP gt 50dBm Adjacent Channel Leakage Ratio ACLR 43dB 10MHz ACP gt 50dBm 36dBm f 9 150KHz 1k BW 36dBm f 150KHz 30MHz 10k 36dBm f 30 1000MHz 100k Spurious Emissions 30dBm f 1 12 75GHz 1M additional requirement 41dBm 0 1893 5 1919 6MHz 300k 67dBm 9 925 935MHz 100k 79dBm 9 935 960MHz 100k 71dBm Q1805 1880MHz 100k 31dBc 2 5MHz Interferer 40dBc Transmit Intermodulation 41dBcQ 10MHz Interferer 40dBc 17 5 gt 20dBm Error Vector Magnitude EVM 12 2k 1DPDCH 1DPCCH 15dB SF 4 768kbps multi code Transmit OFF Power transmission Item GSM DCS PCS Sensitivity TCH FS Class 105dBm 105dBm Co Channel Rejection C Icz7dB C Icz7dB TCH FS Class RBER TUhigh FH Adjacent Channel 200kHz 1 1248 1 1248 Rejection 400 2 C la2 44dB C la2 44dB Wanted Signal 98dBm Wanted Signal 96dBm Intermodulation Rejection 1 st interferer 44dBm 1 st interferer 44dBm 2 st interferer 45dBm 2 st interferer 44d
225. rging method T2 Charging Method CCCV Constant Current Constant Voltage Maximum Charging Voltage 4 2V Maximum Charging Current 700mA Nominal Battery Capacity 1400 mAh Charger Voltage 4 6V Charging time Max 3 5h Full charge indication current icon stop current 80 Low battery POP UP Idle 3 50V Dedicated 3 54V Low battery alarm interval Idle 3 min Dedicated 1 min Cut off voltage WCDMA call 3 15V ELSE 3 23V C Charging of Extended Temperature 3 Technical Brief When the battery temperature is outside the normal charging specification the battery voltage VBAT is maintained at 3 7V Under 0 Extended temperature From 0 to 45 C Normal charging temperature Over 45 C Extended temperature 472 3 Technical Brief 3 5 Voltage Regulation 3 5 1 Internal Regulation There are LDO Low Drop Output regulators and BUCK converter in AB2000 Vincenne chip LDO regulators and BUCK converter generate the following voltages 1 5V 1 8V and 2 75V The output of these LDOs supply VDD A VDD B and VDIG with 2 75V BUCK converter steps down the VBAT to 1 5V for VCORE and and to 1 8V for VMEM voltage The output of these LDOs and BUCK converter are as following Table 1 Fig 1 shows the power supply of each module in 08550 3 5 2 External Regulation 1 5V LDO supply 1 5V for Wanda core 1 5V LDO supply 1 5V for Marita PLL 2
226. roposal 1 Set the ME in RX mode on channel 10695 2 Feed a CW carrier at 2140 MHz with a power level of 105 dBm Get average Ak output2 add 6 to the value and store it in GDFS as GMAX 20 ID rounded off to an integer Set the AGC parameter GMAX to the calibrated value 3 Clear Ak able 0 Change the CW carrier power level to 95 dBm 5 Read Ak value output2 and calculate Average Ak Equation 1 Store Pin Corrected Equation 2 at N in Equation 1 should as large as possible Pin Corrected Pin round Average Equation 2 6 Then increase the output level of the signal generator to 80 60 40 and 25 dBm and store the corrected RF input level and Ak to the memory respectively 7 Use the average Ak values and Pin Corrected from the two lowest power levels 95 and 80 dBm to extrapolate Ak and Pin Corrected for 110 dBm according to Average Ak 110 2 Average 95 Average 80 Pin Corrected 110 Pin Corrected 95 Pin Corrected 80 8 Store Average Ak 110 and Pin Corrected 110 according to step 4 9 Perform the interpolation AK BANK SEL in DB 2100 shall be set to 0 10 Measure the ME temperature T and save for offline calculations 11 Store the result to GDFS GD RF RX AK TBO ID When stored in GDFS the first position in the table 0 should be replaced with the table number 0 23 in bcd format and the
227. round SDA In Out Serial Bus Data SCL In Out Serial Bus Clock RESET In Reset DVDD 2 8 Power 2 8V Digital Power AVDD 2 8V Power 2 8V Analog Power Table 3 2 2 Interface between VGA Camera Module and FPCB in FPCB 48 3 2 4 Camera Regulator GPIO 31 enables the 1 8V Camera Regulator for the 1 3M Camera Digital Core GPIO 20 enables the MEGA 2 8V Camera GPIO 02 enables the 2 8V Camera Regulator VBATI VCAM 1 8V VBATI VCAM 2 8V 8501 0503 3 0 0502 R526 0 1 VOUT 1 VDD VOUT GND R508 GND 4 CAM28 EN wc 18 EN gt CE NC TR c501 R1114N181D TR F C504 R5285 C522 R1114N281D TR F ced P072 qu 2 2u 100K UL VEM 100K 1608 1608 1608 1808 4 477 777 MEGA 2 8V Camera Analog Power Figure 3 2 6 1 3M 2 8V and 1 8V Camera Regulator 28 VGA 1 8V Camera power 2 VCAM 2 8V U501 R503 9 vpp vour R505 0 e R504 6502 R1114N281D TR F 100K lt 1608 177 2 8V Camera Analog Power Figure 3 2 7 VGA 2 8V Camera Regulator 49 3 Technical Brief 3 2 5 Display amp LCD FPC Interface LCD module include device in table 3 2 3 Device Type Main LCD 220 X RGB X 220 262K Color TFT LCD Sub LCD 128 X RGB X 160 262K Color TFT LCD Main Sub LCD Ba
228. rted low and synchronously negated high The CPU subsystem has separate clocking and reset for the ARM946 AHB system EMIF and DMAC C Peripheral Hardware Subsystem There are 29 peripherals within the peripheral hardware subsystem With the exception of the USB all hardware peripheral blocks are APB slave peripherals From an architecturehierarchy perspective the SYSCON block is an APB slave on the slow APB bridge but resides at the top level of the ASIC The APB provides a simple interface to support low performance peripherals Within the peripheral subsystem there are four separate APB busses with AHB to APB AHB2APB bridges to the multi layer AHB D DSP Hardware Subsystem The DSP subsystem provides support for processor intensive activity such as voice coding and multimedia application support The DSP subsystem includes the standard C55xTM Core LEADS from Texas Instruments with associated memory system and peripherals E GAM Hardware Subsystem The Graphics Accelerator Module GAM subsystem provides hardware support in the creation of visual imagery and the transfer of this data to the display GAM also provides support for the camera module The visual data could be graphics still images or video The GAM subsystem consists of five modules GRAM graphics memory 160 kB GAMCON GAM controller GRAPHCON graphics controller PDI SSI programmable display interface for parallel serial displays CDI ca
229. s Maintenance limitations on the phones must be performed only by the manufacturer or its authorized agent The user may not make any changes and or repairs expect as specifically noted in this manual Therefore note that unauthorized alternations or repair may affect the regulatory status of the system and may void any remaining warranty 1 INTRODUCTION E Notice of Radiated Emissions This model complies with rules regarding radiation and radio frequency emission as defined by local regulatory agencies In accordance with these agencies you may be required to provide information such as the following to the end user F Pictures The pictures in this manual are for illustrative purposes only your actual hardware may look slightly different G Interference and Attenuation A phone may interfere with sensitive laboratory equipment medical equipment etc Interference from unsuppressed engines or electric motors may cause problems H Electrostatic Sensitive Devices ATTENTION Boards which contain Electrostatic Sensitive Device ESD are indicated by the sign Following information is ESD handling Service personnel should ground themselves by using a wrist strap when exchange system boards When repairs are made to a system board they should spread the floor with anti static mat which is also grounded Use a suitable grounded soldering iron Keep sensitive parts in these protective packages until these are
230. sabled via I2C still removing the DC offset from the signal For one of the two transmit paths a transmit gain control amplifier precedes the final encoding of the PCM output 61 3 Technical Brief 3 4 5 MIDI Ring Tone Play This section provides a detailed description of the MIDI and WAV file functions Digital Baseband ASIC MIDI or ES VINCENNE WAVE Audio Mixer Audio and Powe Management ASI TJATTE2 HEADSET AMP 970 HEADSET Analog S W Speaker AUDIO AMP Speaker Figure 3 4 6 MIDI Scheme In Figure 3 4 6 External MIDI path is the same as Voice Loudspeaker downlink Mode except source in MARITA DSP and Audio Mixer e MARITA PCM Decoder Auxiliary audio amplifier AUXO1 2 Port SURROUND AUDIO PROCESSOR NJM2705 TJATTE2 Analog SW NLAS4684 2 Mono AUDIO AMP TPA2005D1 2 Speaker 8Q 62 3 Technical Brief 3 4 6 MP3 Audio Player This section provides a detailed description of the MP3 file functions MARITA Digital Baseband ASIC VINCENNE 1 1 Audio and Power Badia Mixer Management ASI TJATTE2 HEADSET AMP HEADSET gt S 3D effect Analog S W Speaker SPEAKER AM Speaker Figure 3 4 7 MP3 Scheme MP3 function supports PCM 44 48KHz sampling rate The PCM44 48 RX path is intended to be used as a 3D surround music headphones and two speakers Analog switch NLAS4684 controls the audio path to the headset or two speakers 63
231. scillator Procedure Proposal 1 Start the VCXO and RFVCO VCXOCONT is set to its calibrated value Ericsson AB 2000 DAC3 2 Measure the loop voltage WRFLOOP with the AB 2000 ADC GPA4 for all CVCO settings that is 0 7 Find a CVCO value that fulfills the requirements on loop voltage for low and high channel If there are several CVCO values that fulfill the loop voltage requirements then the optimum CVCO value is that that centers the loop voltage within the specified limits 3 Store the calibrated CVCO value RF SYNT CONFIG ID B TX Carrier Suppression Calibration Purpose DC offset compensation the carrier to the wanted signal at the IQ modulator output The leakage is caused by imperfections in the baseband IQ path and inside the IQ modulator It impairs the modulation accuracy and results in a high vector magnitude EVM The outcome of the calibration is values for RECDCI and that minimize the carrier Procedure Proposal 1 Set the ME in TX mode on mid channel Use typical TX settings Generate 960 kHz squarewave on both and with amplitude 8 sine wave could be used instead Start with the best value from earlier calibrated units on RECDCI on 210 7 CALIBRATION 2 Measure the relative power between the 1950 MHz carrier and 1949 04 MHz at the antenna output Jump to step 6 if the requirement is met 3 Step from 0 to 3 Set TXON 0 and wait 1 ms befor
232. se shift between and Q The amplitude should be about 5096 of full scale 2 Measure the relative power between 1952 88 MHz 3 960 kHz and 1949 04 MHz fc 960 kHz in dB at the antenna output Find the setting of LPQ 2 LPBW between 3 and 15 that obtains the dBc value closest to the typical value Start with the best value from earlier calibrated units Spectrum analyzer settings example RBW 300 kHz Span 8 MHz 3 Set LPQ LPBW to the found value 2 Also save the dBc and the decided LPBW value for statistics Store the calibrated parameters TX CONFIG ID D TX Maximum Output Power Calibration Purpose These procedures verify that the ME can meet the requirements on maximum output power The calibration aims to establish WPABias and settings that fulfill ACLR requirements for maximum output power both in high medium and low gain mode These calibrations are designed to conform to the ME maximum output power and ACLR requirements specified in SGPP Spec TS34 121 Procedure Proposal 1 Use typical TX settings mid channel 2 Set gain to the best value based upon previous calibrated units 211 7 CALIBRATION 3 Measure output power as broadband power If the ACLR requirements described in Table 11 are not met calculate the test step necessary to achieve the correct power Use correlation from earlier calibrated units to calculate the new gain setting defaul
233. spec is as following Table 2 B4 MODI 8 77 ADSTR ADCSTR RTEMP VLOOP WPOWERSENSE WRFLOOP dn JACK DET Jg CPAS VBACKUP 79 551 2 GPA13 Figure 3 4 10 Schematic of GPADC and AUTOADC2 gt x c AUTOADC2 Controller ADSTROBI Figure 3 4 11 GPADC and AUTOADC2 Block diagram ADC 6 channels Resource Name Description GPA0 RTEMP Radio temperature sense GPA2 VLOOP Loop voltage sense GPAS3 WPOWERSENSE Reference voltage for PAM 4 WRFLOOP Lock inform GPA6 GPA6 Headset detect GPA7 VBACKUP Backup battery Table 3 4 5 GPADC channel spec 467 3 Technical Brief 3 4 10 Charger control A programmable charger in AB2000 is used for battery charging It is possible to set limits for the output voltage at CHSENSE and the output current from DCIO via the sense resistor to CHSENSE The voltage at CHSENSE and the current feed to CHSENSE cannot be measured directly by the GPADC Instead the two measuring amplifiers translate these inputs to a voltage proportional to the input and within the range of the GPADC Figure 3 4 12 shows the schematic of charging control part This section provides a detailed description of the Voice Call RX functions C532 09 Di D3 D2
234. t lt lt Tx Maximum Output Power 2 Tx Power Table gt gt gt Elapsed Time 88 81 38 Total 118sec n poen Loop Power Control gt gt gt RF 811 Items Calibration End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt Re LPF Bandwidth gt gt gt ITP Version lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt Rx LNA Gain Switch 8 AGC Hysteresis UERS 8 831226 1357 INI17 CXC125477 7 PLATINUM TP 16M M 2 Rx AGC Gain Max amp RSSI WCDMA VERS 1 CXC125469 ECSJHEE Fri Rug 22 13 41 36 2003 UERS 2 CXC125495 5 BB Calibration Battery Voltage Test Ready gt gt gt BB 811 Items Calibration Start lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt gt gt gt Elapsed Time 00 00 00 gt gt gt BB Battery Voltage Cal Start lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt UBRTT 328 25 68 DAC 39 UBRATT 418 18607158 DAC 121 PASS gt gt gt BB Battery Voltage Cal End lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt gt gt gt Total Fail Number in BB Calibration 6 gt gt gt BB fll Items Calibration End lt lt lt lt lt lt lt lt lt lt lt lt lt lt
235. t correlation between VGA and output power is 1 dB and for QVGA 0 25 Measure ACLR at this power level the ACLR requirement is not met reduce VGA and QVGA Measure and store the temperature at this point This provides the value for TPmax This power and gain setting is to be used in calibration of TX power table Set gain to maximum power in medium gain mode and measure ACLR at this power level RFBias should be set to 1 and WPABias should be set to the same value as for maximum output power 10 If the requirements are not met step the gain down and measure ACLR until the requirements are met The correlation between ACLR and output power is that 1 dB in power equals typical 3 dB in ACLR Use correlation from earlier calibrated units to calculate the new gain setting 11 This power Pmax meas MG is input to the calibration of TX power table 12 Set gain to maximum power in low gain mode and measure ACLR at this power level RFBias should be set to 1 and WPABias should be set to the same value as for maximum output power 13 If the requirements are not met step the gain down and measure ACLR until the requirements are met Use known correlation from earlier calibrated units to calculate the new gain setting 14 This power Pmax meas LG and gain setting provides input to the calibration of TX power table O ON O E TX Power Table Calibration Purpose The calibration data contained within the TX Power Tab
236. t the 50pin B to B connector FPCB and Main YES LCD Display OK Disconnect and Reconnect the 40 B to B connector LCD and FPCB LCD Display OK Change Camera amp LCD FPCB 6 Change LCD Module LCD Display OK YES The LCD Works NO Change the Main Board 105 4 TROUBLE SHOOTING a af Main Board 50 pin B to B Connector FPCB Board 50 pin B to B Connector 1 iilii 1 Board 40 pin BtoB Connector 21 LCD Module 40 BtoB Connector 106 4 TROUBLE SHOOTING 4 9 Sub LCD Trouble START Press END Key to turn on the power NO Is the circuit powered Follow the Power On Trouble u Disconnect and Reconnect the 50pin B to B connector FPCB and Main Shooting YES Sub LCD Display OK Disconnect and Reconnect the 40pin B to B connector LCD and FPCB Sub LCD Display OK Change Camera amp LCD FPCB Change LCD Module YES The LCD Works Sub LCD Display OK NO Change the Main Board 107 4 TROUBLE SHOOTING trtetrrre 2046664040400 R8488 E 2 s z Main Board 50 pin B to B Connector FPCB Board 50 pin B to B Connector i 3 FPCB Board 40 pin BtoB Co
237. teresis AGC Gain amp RSSI WCDMA VCXO BB Calibration Battery Voltage m Test OUTPUT STATUS INSTRUMENT UART UART Control 8 PORT SET s BAUD RATE 115200 PARITY CHECK 18 FLOW CONTROL NONE z NONE s CHANGE SETTING 2 SET s PRESENT SETTING VALUE COM 1 NO PARITY 115200 NO FLOWCTRL Ready Figure 7 9 XCALMON Calibration Tree Window UART Tab C ITP Starting Window Using Production Loader When you click the ITP starting window icon L then you should see the ITP starting window That dialog window just wait for power on of U8550 mobile phone When it will occur power on it automatically start ITP running If you want to change the start address of ITP you could change that address directly To change ITP start address is possible when we download Production loader previously 222 7 CALIBRATION i Select amp Send Loader File Production Loader CAPlatform AssistantiLoadersvCXC 132 Start Address 20490000 Present Start Address 0 CHANGE If you want to run please Turn On the ME Cancel Ready Figure 7 10 XCALMON ITP Starting Window Using Production Loader 7 4 3 Calibration Procedure Calibration procedure of XCALMON was the same as below procedure Configuration of calibration Running ITP using production lo
238. the camera module to the CDI The pixel clock is an output clock from the camera module to the CDI and qualifies the data on the parallel bus One byte of data is captured on each rising edge of the pixel clock CDI allows the pixel clock to be in the range of 100 kHz to 16 MHz The horizontal synchronization line is an input from the camera module and defines one scanline of image data The horizontal synchronization line can be programmed to be active high or low The vertical synchronization line is an input from the camera module and defines one image frame image height of data The vertical synchronization line can be programmed to be active high or low The frame rate can be adjusted by skipping frames and various interrupts are used to inform the application CPU regarding the progress of incoming images and potential errors The normal data format on the data bus is YUV 4 2 2 raw binary image data according to the CCIR 656 standard A function within the CDI can be programmed to reorder the YUV parameters as they pass through the CDI In addition the CDI is able to detect the end of an image and perform some truncation as well as overflow conditions There is nothing preventing the use of other data types such as JPEG or RGB as long as the timing is followed but only YUV data can be sent to the display Camera images can also be sent to a DMA channel to store the image in external memory The I2C interface and GPIO are part of the interface
239. ty KEYPAD gt 16 2 gt le 5 gt 2 9 432 32 1 Q al E DENT 3 E P TONGEN 5 5 144 z 5 32 gt 16 GAM CRYPTO 2 MPPCM gt UART5 us 16 S gt rei 5 5 DL ontrol 4 fe v iNr 4 1 49 2 E 16 2 2 SIMIF 1 4 dl 5 gt 3 419 UART2 a 4 40 5 GPS 16 lt gt nn Ru 2 GPIO 20 2 ui 2 MUX 4 L w 5 x Fm RO o lt E 4xCHD 2 lt GPIO MUX z gt 8 TIMER E gt GPRS Lu 6 SRYFTO JOGDIAL lt lt gt GPRS kH RHEA CRC24 ETX MGS3 2 0B MGS3 DL gt UL API RHEA peripherals DARAM SARAM 4 DL 32 kWords 32 kWords GPIO MUX SYSCON ER ens UART7 SYSGLKTI BRE BRE DSP debug gt 13 208 APLL DPLL gt RESOUT 5 CLKCON GSM Sub System v BPW 26 7 CLKREQ APLL SQR HPRTD C55x CPU ROM 4 5 gt 4 p SERCON 4PWRREQ N TRACE 8 xB KW BX Times 11 SERVICE 48 JTAG 4 5 TIMGEN i APLL RESPOW DSP Sub System A Block Diagram
240. ulation 74 3 6 General Description of RF Part 76 3 7 GSM 78 Sef Hecelvot tit 78 3 7 2 Transmitter exten 83 3 8 WCDMA 85 3 8 1 H666lv8r ues sie 85 3 9 2 Transmitter cnet 88 Table Of Contents 3 8 3 Frequency Generation 92 4 20 1 Checking VCXO Block 154 4 20 2 Checking Ant SW module 154 4 TROUBLE SHOOTING 94 4 20 3 Checking Control Signal 154 4 1 Power ON 94 4 20 4 Checking RF TX Level 156 4 2 USB Trouble nentes 96 4 20 5 Checking PAM Block 159 4 3 SIM Detect 97 4 20 6 Checking RX 1 9 162 4 4 TransFlash 98 4 21 Checking GSM 164 4 5 Keypad Trouble 99 185 4 6 1 3M Camera Trouble 101 153 4 7 VGA Camera Trouble 103 Kn a 4 21 4 Checking Control Signal 166 4 8 Main LCD Trouble 105 4 21 5 Checking RF Tx 168 4 9 Sub LCD Trouble 107 Bae scs 181 4 10 Keypad Backlight Trouble 109 4 11 Camera Flash
241. used When returning system boards or parts like EEPROM to the factory use the protective package as described 1 INTRODUCTION 1 3 Abbreviations For the purpose of this manual following abbreviations apply Automatic Power Control Baseband Bit Error Ratio CLA Constant Current Constant Voltage Cigar Lighter Adapter DAC Digital to Analog Converter DCS dBm Digital Communication System dB relative to 1 milliwatt DSP Digital Signal Processing DTC EEPROM DeskTop Charger Electrical Erasable Programmable Read Only Memory Electroluminescence Electrostatic Discharge Flexible Printed Circuit Board Gaussian Minimum Shift Keying General Purpose Interface Bus General Packet Radio Service Global System for Mobile Communications International Portable User Identity Intermediate Frequency Liquid Crystal Display Low Drop Output Light Emitting Diode Offset Phase Locked Loop Power Amplifier Module Printed Circuit Board Programmable Gain Amplifier Phase Locked Loop 1 INTRODUCTION I Introduction 1 3 Abbreviations For the purpose of this manual following abbreviations apply Public Switched Telephone Network Radio Frequency Receiving Loudness Rating Root Mean Square Real Time Clock Surface Acoustic Wave Subscriber Identity Module Sending Loudness Rating Stati
242. wave out of the receiver Change the Receiver YES END 114 4 TROUBLE SHOOTING Pin 47 48 L501 L502 a B SIDE H 1 115 4 TROUBLE SHOOTING zB Ian H4 2 42 RARA T HE 1 412 9 STOPPED Measured 1khz Sine Wave Signal 78 Jan 64 loppi Disk Or ise CbHhMEL 2 3 mca Trac m E mamapa lew high OP Paste in nn Ble ki B 5 1H 14 5359 H SE27 Disiabara F ID V STOPPED Measured 1khz Sine Wave Signal 116 4 TROUBLE SHOOTING 4 12 2 Speaker Voice Loud Speaker Midi MP3 Key Tone Signals to the speaker AUXO1 Right AUXO2 Left AUXO1 Right AUXO2 Left Speaker path Vincenne AUXO1 Right AUXO2 Left gt U507 Surround Audio Processor on the main board C584 C585 on the main board gt N504 ADG on the main board U508 Analog Switch on the main board U504 U505 Speaker Amp on the main board CN703 on the main board CN4 on the Key PCB gt Speaker Note It is recommanded that engineer should check the soldering of L along the corresponding path before every step 117 4 TROUBLE SHOOTING START Connect the phone to network Equ
243. z 1000Mohm 10V 100mA 5 0007801 29nH 47pF SMD 4ch 2 0 1 25 200MHz 1000Mohm 10V 100mA SFEY0007801 29nH 47pF 6 6 FL706 FILTER EMI PPOWER 6 L101 INDUCTOR CHIP ELCHO0005010 1 8 nH S 1005 R TP 6 L102 INDUCTOR CHIP ELCHO0001030 8 2 nH J 1005 R TP PB FREE 5 0007103 75 ohm 1005 BEAD 300 6 1103 FILTER BEAD CHIP 6 L104 FILTER BEAD CHIP 5 0007103 75 1005 BEAD 300mA 6 L105 FILTER BEAD CHIP 5 0007103 75 1005 BEAD 300mA ELCH0001425 82 nH J 1005 R TP PBFREE 6 L201 INDUCTOR CHIP 6 L202 INDUCTOR CHIP ELCH0001425 82 nH J 1005 R TP PBFREE 6 L203 INDUCTOR CHIP ELCHO0001407 5 6 nH S 1005 R TP PBFREE Pt ELCHO0005001 2 2 nH S 1005 R TP 6 L204 INDUCTOR CHIP 6 L207 INDUCTOR CHIP ELCH0001511 100 nH J 1608 R TP PBFREE 6 L208 INDUCTOR CHIP ELCHO0003811 1000 nH K 1608 R TP TYPE SFBH0007103 75 ohm 1005 CHIP BEAD 300 6 L305 FILTER BEAD CHIP 6 L307 INDUCTOR CHIP ELCH0001407 5 6 nH S 1005 R TP PBFREE ELCHO0001001 10 nH J 1005 R TP Free 6 L308 INDUCTOR CHIP 6 L309 INDUCTOR CHIP 6 L310 INDUCTOR CHIP ELCH0001401 15 nH J 1005 R TP Free ELCH0001407 5 6 nH S 1005 R TP PBFREE ELCH0001401 15 nH J 1005 R TP Free 6 L311 INDUCTOR CHIP 6 L401 FILTER BEAD CHIP SFBH0008101 600 1005 6 L402 FILTER BEAD CHIP

Download Pdf Manuals

Related Search

Related Contents

FPRS-S200 Service Manual  Focusrite  König HAV-SR40  Triarch 32454 User's Manual  取扱説明書 - 三菱電機  - Intellinet  AcPC4610 User`s Manual  販売パートナー契約書 - Next systems  VT TURBO MOP - M0S10720- 1T07_vers7:FEV 1000-950.qxd  Bedienungsanleitung User Instructions MultiSafe DSP 4  

Copyright © All rights reserved. Failed to retrieve file