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7. R694 HDMI 3V3 ok elc vu R723 Y SHEET3 1 OPNS I SHEET4 R692 Q656 SHEET3 ed m RESET IC p AKT BC848B C684 LLL C694 a 29 8652 Q651 R66
8. VSSD HW4 i E HEADPHONE AMPLIFIER i R605 mei CR i C817 AMPLIFIER R 100R AKT F d rd 470n gly 220 5 al 4 G 16V ER meis 615 ve 2 pMP DVD B AMPLIFIER Ak7 0855 i m e 470n S a e 16 5 n TO VCTP SHT3 88185 m VGA_DVDDMP_B_IN VCC_8Y_AUDIO VCC_5V_VIDEO gt ple 3
9. PL950 pussz Brus 0000 00000000 000000000000 o0 00 MIB PROTECT PL952 PL951 cleo aa ae 850 PL853 17 1007 n TPR PL602 PL601 PLg51 e R1043 amp C1025 00 OG 961 o E a S 2V5DIG m LEST 8 7 1956 oo B 5 a a nn HE go go E 5 O 9 1966 N C602 ooomm n C897 d Taaa e 88008 5888 2 BE snor 21100 n ox 895 og pid ned Q857 22 g Ros 08 4 R901 en 876 68 8 RoN 08 DU 6974 gt E 999 4 aa 18 OG Revo 0858 88 ag Rer B 518 5410 DD 965 5 8 8 e 2 C888
10. Z 9 a 20 d 5 8 5 2 KEYBOARD R494 R504 DMP_DVD_CVBS_IN 5 a a a 47R 47R gt gt m A E 1k 4 5V STBY Em 9 n a e R523 5 m lt lt lt E gt 5 2 m Soh a O 539 5 5 32 PC STANDB Y MODE PEE MES Y R486 9 V IKS lt pmi_vsync d A fomi vs d Y Y Y Y Y Y La g VSUP_3V3_COM HDMI_HSYNC SYNC DETECTION 4 51 za E ns y 4917 KEYBOARD CONN 9 z a gt L417 HSYNC 9 29 2 KEYBOARD sv cc OUT IN 2 7 a 5V_STBY a e T e gt A gt 2 Y P T 27 E 4 al E al 8 2 HE 43 as CE 9 7 BULL zt zz ag ex ag 3 2 Y3 COM_X_OUT_IN syne deteft U N 2 Y sy y 8 M74HC4052 me 2 ki Y d r4 2 oy S Y gl
11. ds 12106 C1144 C1145 DNI FERRITE gt ect m 22 x at M VDD ques zu 4 1C1002 DIG IF gt ar C1148 6 C1126 58 2 2 gez 00 pic 4 IC1000 53 47 5 8 2 RADD16 48 RADD17 DQI lt gt 2 Y gt C1146 SMD 40 T RADDIS 47 1127 C1129 55 MY 5 DQ3 71116 1122 100 100 R1123 p 4 H lov 3 100R o SCLK TUNER RADDIS pot 100 100 R1124 1149 100R DATA TUNER t ms 5 gt o RADD13 p 45 lt 4 RDATA15 E 7 Er Q pos n RADD12 p 44 lt 4 RDATA7 gt M 149 RADDII 43 lt RDATA14 N 50 us 8V pewop 2e 51 38 2 1 8 I RADDIO 24 RDATA6 xD LDQS gt 52 zx LE Hs C1151 9 RADD9 411 4 RDATA13 tz x o x a 15
12. 853 18 8 T mer Dus oo 0900 5 5 R563 00 ST nz a 54 8 amp 5 8 9068 rustes 588 0000000000080 eaten 5 Les m T c1131 C992 leeeeoeiuuwuuii _ 888188 48 3 nee 2 6 OS t 5 NS Oo ge AN 28 E MEE Cg 9 ER 5499 55 D 0646 _ R634 A N 00000 8559 E 5181558 P275 5 C1000 1069 R1070 PL952 eS 825 ns 0 0 018 58 8 Em UN NGA ojojo S 5 Xm a fa Ame R1000 R999 111111 galejo EE OS 388 mis E ip sys B 5 SE 0 0 4 75 ZU s BLZ ee 18 DOE t D
13. iio FOR THE USE OF EXTERNAL CLOCK gt 5124 Vecis gt gt C124 C134 IS 1 30012581 3V3 DRX R152 rou 430R_100MHZ_3A X100 AND C123 IS REMOVED Ag 519 819 319 ART S125 3 SV DR ge mS x mue 8V VIDEO R153 12V IF SVL ds az 487 05 e gt C113 uA d 5 Jw z 8 1 t 9 25 o X100 2 1 102 5 gt CHROMA SW a a a 10u 5 5127 205 a gt gt 3 R100 5104 Y Yvecavs gt o 3V3 DRX p 20 25Mhz 208 o AUDIO MUX W sv Tuner 3k3 N C 5V_TUNER DRX_CLK gt amp 50 Provo m E PTC RES C101 52 a 5 r Y 5 2 9 SHEET3 m S11 51 8 5 vi _ 8 1 5 LE AEE AS E gt 5 EZE 3 DRX POWER SUPPLY SHEET3 PINSO 5 8 VY ME N C i 9 p x 16V 123 mi L gt SM R114 R121 Ax e og R104 CC SV 9 1 1006 100R FP PIE 9 5 50 Q101 Q102 50V ace 51 SHORT I
14. 72 7s ur 9 979 C980 a e a E 8 100 1008 B o B 3 5 10vy gt gt Fed 5 Y 5 B 3 E AR 2 NG 5 R 38 lag A 2 5 5 A 16 TON 10V 10V 16 ioe wa 1005 1008 100n SE 1001 2525 28 100n H a8 EE 2 S ee as 5 5 a C954 Coss Cask 9 9 9 4 N e oo N t e e et e oc v vt e e oo N e oo Ko v e oc Ko N m m a e e e a a a a a a oo oo oc oo oc oo amp Ko Kol 6 amp al fal fal min al N 3 x N a N bof aki N 1 a T i 1 nD 1 lt lt B clc Uo gt m d a 3 i AA D Ja S nn SUB XE une A Bu B NR ONU B NR E Ld oe S on Bro s x xm 3 QR OR m Dos dB 2 2 2 8 2
15. R297 1k lu SC2_AUDIO_R_OUT 25V 330R 1228 lu e z gt 25 55 5 55 9 5 9 C269 16V 5 5 253 47R lu SCI AUDIO OUT C235 R271 25 27 1008 BC858B 50 0203 9 dg 1 3 ag AOUTIH n C254 vere_aouTit 18C1 AUDIO L OUT mm ml sg 25V 100E BC858B SA 8 r4 e a B 5 5 pa 4 n al 5 91 5 6 224 2 C234 C242 225 gt 46 4 27p sov amp 50V a 1 D226 RARE prester gt 47R H FAV CVBS e I R266 R278 ATR gt SVHS Y i R267 R276 476 47R o SVHS C I 1212 4 e E L213 o FAV AUDIO L Ij R289 x dis Fon Sea e a gt ub Guile as FAV VIDEO 254 2 4 D 20 D a 0 5 5 er R291 100R LHS OL E C248 C251 SES mm
16. TO SHT3 gt 21 5 TL 5 a ol 5 5 a 22 5 Y Yi en Na mem um n SIE Siu 4 xU x 2 WW 0951 BSN20 Pire 25 BSN20 0952 0953 E E BSN20 55 p A G I m c I 5 Q950 amp 2 BSN20 e E C1000 R1039 10p 4k7 d vcc av R1040 AKT m m 2 gt X950 27MHz SMU2 SMD IC861 C995 100n 10V NC 1 NC 2 E PI6CX100 27WE 8 I PWMOUT b VIN VDD C1007 100n 10V L uz i b VCXO CIRCUIT MT Senn an FS E C998 1 5 lt 3 3V_D pos a JTAG amp ETAG CONNECTOR i t E ES hr A ES 7 x a a 2 24 128 PM p 1 Q957 BC848B 1069 1k Q958 BC848B q h R1071 10k K R1070 10k 1 951
17. 5 5 yyw S um 7 E M 4 z 5 8 9 2 2 2 5 9 9 2 B B a 5 57 g 8 PE 2 5 5 B 8 E x Jz Jz 5 1200 hd e 5 VESTEL ELECTRONICS x 17MB12 1CI 120113 Date Author SADIK SEHIT 17 04 2007 ISMAIL YILMAZLAR ONUR KORHAN SAYI 8H
18. Edi rir 2825 fem tes y 8 5 al 2996 a ojo 0 Napa SAU As o UO amp 0 0 51510 5 To ole elo le DEB S654 Sa api A ojoo ojoo oo 5436 ola m 714 D vu __ nn n 9 ax o oo ojo S 229 a ala 0 00 00 00 0 8 R656 R693 A706 o 8 oo oa nu 528 ENTE 2 C707 o ef D E 5 2 CEST amp S 69 fo alm ojo 3853 gr mer Cer lt C JL P EE gees 07 50750 R694 55 9 5 104 Roe 8 rn Ol 11 266 B OFF 8 Bi e e amp o NEI 2838 D203 0200 0201 papa D202 0206 C716 R715 8696 8729 1694 SE C101 R104 1171 Ll 0105 c273 8 olla 3205 9211 2 848 550 0515 2288 C728 9215 R701 R710 BED Dados ES Quz EEO E C727 ppp C674 R712 065 asso nd Ke ere tm h Ti 5 440 SRrarb gt 98 C726 R718 R702 R713 e NRS arr 8 BS SERRE 83 00000 Gras no Seo WS Ww Due o gi Doles 0000000000 00000 TN Tle nl Qa nA QI cO S672 8 e Stale 58
19. SERVICE MANUA L TABLE OF CONTENTS 1 INTRODUCTION 5 2 INE Riess 5 2 1 General description 5 2 2 Features of DIT av 5 249 RS RE ME 6 3 AUDIO AMPLIFIER STAGE WITH 4 8932 22222 6 3 1 General TDS SCH OU edes eere e Aul 6 CMS unc cp LE 6 33 PRP UN CANO IRS 7 JA e NE 7 AS POWER STAGE itle mundi 7 3 MICROCONTROLLER VC ED vepren a ae 8 5 1 General as EE RE OE 8 5 1 1 CORBITFOLIBE ge Do EL bulo co taf amp 5 132 cos redu ridet 8 5 1 3 NV TUCO TENES amp 5 2 Multistandard Sound Processor MSP Features sess 9 Jer suceso tecta farbe teat ou Le fob ps res pa utu dodo 10 54 Controller Features m 10 5 5 Teletext TNR 11 2 0 Fort Allocation 11 DIRK SJOA see 20 6 1 General WWE SEL OMS o adeste 20 6 2
20. 5V6 e SES SOT gt 221 5 1002 16V ee 6 BLS STORY QA un aig a 9 oe sae 38 25 jx S Gu ae SCI B SC AV Ot 203 200 99 27p 50 75 R203 75 R206 75 C209 o 5 N gt 27 50 210 27p 50 C 0206 BAV99 6 2 DSUB VGA CONN D201 BAV99 aE m SHT7 RGB SW C R249 Y v vetpprog P es TO SHT3 o 5 1 CVBS IN SHT3 SHT7 TO VIDEO SW R269 18k 2 VOUT2 VOUTI vec si 47R C250 SV VIDEO R283 C261 100n zm 10 R30 lt 100R L CHROMA_SW gt ST24LC21 DDC_SDA J gt rc usyne
21. s Typ e 7 Led 1 Colour 1 Led 2 Colours 2 Led 2 Colours e PC PIP gt PC Stand By lt gt 16 5 Service Scan Tuning Setup Search for L L lt gt Pref Search Standard lt gt I L L Station Ident ATS Delay Time ms Value between 20 to 250 Color Killer Threshold lt Value between 0 to 255 Tuner Options Control Byte Value between 0 to 255 Low Mid Low Byte Value between 0 to 255 Low Mid High Byte Value between 0 to 255 Mid High Low Byte Value between 0 to 255 Mid High High Byte lt gt Value between 0 to 255 BSW1 gt Value between 0 to 255 BSW2 lt gt Value between 0 to 255 BSWS Value between 0 to 255 DVD FAV BAV PC 16 7Picture Mode Sources gt Tuner SVHS YPbPr PIP e Picture Mode gt Dynamic Natural Cinema Colour Temp lt gt Cool Normal Warm Contrast lt gt Value between 0 to 63 Brightness lt gt Value between 0 to 63 Sharpness lt gt Value between 0 to 15 ee gt Value between 0 to 63 Backlight Value between 0 to 255 lt gt Valu
22. d 0000p 8 gt B on v e 423 R462 C479 VL N org 3 ga 2 5 200 amp C864 S R464 00 d _ D402 T9 2 2 EE C1206 na LJ Zn o 110 88 e V na FR 61207 0 8 rv n e S fcn BE 2 ace ro e oo C457 1V5DIG 7 x PL403 paze n C458 psy 8 1908 e Hs eet 5 1414 8 C903 e d n 558 RE B o 1413 189 e 2 83 n PL1200 E C455 C456 TP14 unuu S R491 S407 T PL401 R904 poenae cime ga Dan ner 8v 00000000000000000 SU gogo 0 Ger mew cur Ls pt 0 0187 ma 0000000000000 0000 405 aa 1853 R726 0732 ua nn R138 7705 55 mw amp Too oo 5 an 136 gne Hass ooo S3 9 giaa L105 5 57 5 C435 gg uu cree do 1 as 254 po 7 nn 687 ea 3 id nn C122 S a sees E 55 oo 0132 99022229 80 8666 5 ou oo n __ 5855 8s 28 1650 E oo 2 95 1113 3 wo Um dcm ea uu ES Bu 5 n ES 8 GO 6814 R413 E 182 127 1109 222 n
23. C670 na ce Q651 8 o D pups 9 8 Reset C673 8 Pot 5n rest gai 49988 z A N EE C677 Z8uuuoGoc gt 8 2 0217 nn 2 13655 1 TP658 09000000000 4 6 9 d ozzze SD HU BAS ges Ox 22282 Ok oo _ 9992 50 6160 05 54 8 oo Be So av 000000000 667 Tae Q JK200 1 Ban OG 0o Rese 2000 06000000000 o o9 o o o o 00000 WI o 99000 00000000000 651 o o PL650 PL6S PL200 i e PL203 A S
24. LOW CROSSTALK BETWEEN SWITCHES HIGH ON OFF OUTPUT VOLTAGE RATIO WIDE OPERATING SUPPLY VOLTAGE RANGE VCC VEE 2V TO 12V LOW SINE WAVE DISTORTION 0 02 at VEE 9V HIGH NOISE IMMUNITY VNIH VNIL 28 96 MIN PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4052 15 8 3 Absolute Maximum Ratings ee LLLA SLE BASILIO OC NEM E Pp Power Dissipation F L EE mem Ratings are those values beyond which damage to the device may occur Functional operation under these conditions is not implie 500mW at 65 derate to 300mW by 10mW C from 65 C to 85 C Vec Suppi Vi 10 CK TL 15 8 4 Pinning VEE supply pin is provided for analog input signals It has an inhibit INH input terminal to disable al the switches when high For operation as digital multiplexer demultiplexer VEE is connected to GND A and B control inputs select one channel out of four in each section All inputs are equipped with protection circuits against static discharge and transient excess voltage Y s IN OUT 2 2 2 X CHANNELS COM Y OUT IN 1 IN OUT Y RET COM X OUT IN IN OUT 1 5 x CHANNELS INH z IN OUT Vee 7 A GND B 15 9 809 15 9 1 General Description The 809 and 810 are cost effective system supervisor circuits designed to mon
25. JNetComeed vss 4 4 4 4 2 Ground 4 5 5 5 5 JSenalAddessDataVO 6 6 6 6 1 7 we 7 7 7 7 5 WmrntPrtetinut vec 8 8 8 8 4 55 15 7uPA672T 15 7 1 General Description N channel Mos Fet array for switching The uPA672T is a super mini mold device provided with two MOS FET elements It achieves high density mounting and saves mounting costs 15 7 2 Features e Two MOS FET circuits in package the same size as SC 70 e Automatic mounting supported 15 7 3 Absolute Maximum Ratings ven 15 7 4 Pinning 8 5 4 1 Source 1 S1 2 Gate1 G1 3 Drain2 D2 4 Source 2 S2 5 Gate2 G2 6 Drain1 D1 1 2 3 Marking MA 15 8M74HC4052 15 8 1 General Description M74HC4052 is a dual four channel analog MULTIPLEXER DEMULTIPLEXER fabricated with silicon gate C2MOS technology and it is pin to pin compatible with the equiva control 15 8 2 lent metal gate CMOS4000B series It contains 8 bidirectional and digitally led analog switches Features LOW POWER DISSIPATION ICC 4mA MAX at 25 LOGIC LEVEL TRANSLATION TO ENABLE 5V LOGIC SIGNAL TO COMMUNICATE WITH 5V ANALOG SIGNAL LOW ON RESISTANCE 70W TYP VCC VEE 4 5V 50W VEE 9V WIDE ANALOG INPUT VOLTAGE RANGE 6V FAST SWITCHING tpd 15ns TYP at 25
26. gt IDTV 1 sum rz 16 299 x 5 5 14104 C1132 C1138 d 28 en E BER Pi gt DEMOD a L1102 gt 1141 2 gt 5 100 gt 3 ABCK DEM SCLK p n sv Ee karer gt 27 g 3 100 G8 E E CS4334 l 10V 9 11103 11107 2 C1131 C1134 gt E ALRCK AGND 10u i 1 FERRITE a DEO RADD3 2 4 R CHIP Bc BT FAST FLASH Cis R1118 CLA R1120 FERRITE T 560R 1k2 IDTV_R gt gt RADD2 25 lt RADDI 1 aac 1 1 gt 1000 1050 ev E 8 iev 1 Sz S IN pe e a VESTEL ELECTRONICS FLASH ROM 17MB12 1 MPEG RAM 90113 Date Author SADIK SEHIT 17 04 2007 ISMAIL YILMAZLAR AUDIO DAC ONUR KORHAN SAYIN IC1209 C1202 C1206 C1208 C1201 1 1201 100n IC1204 100n IC1205 100n 3 3V BUF IC1200 100n 10v 10 10 10 GCSBO SW CNTRL gt 3 3V BUF SW CNTRL gt 3 3V BUF CI POWER CNTRL 3 3V BUF SW CNTRL INV p 3 3V BUF idees T 7ALVX245 p e cbe gt Bes I p ox ss unos P p gt lt TSI RADDI TS2 RADD2 IORD 7
27. E na m 55 NOR E m m ORP DE B SNe 1760 Roos oo O A RRE 4 TIME 2 A R135 C627 S C 9 2 2 n IC4000 7 met N hn D R 813 2 22228 YI C129 oo iB 8 08 rne n C131 s og Efe e BS esos AB oe nn Tr e fg Ege OLX m Oos 8 5 g 55 DD 6600 9 57 B B rm 106 0 O 1653 00 2 I R318 _ _ oo Re24 22 a e 222 DOG R317 BB a NN R102 es s Lu z var cs SR p 0809 amp 2 Hg e HDMI1V8 R536 dis no R333 R332 0213 0208 m ox ros mi 0 628 r 98 8 p x DD R543 na CO Hon go es e ROS ame S 248 ser EM 9120 n o ons uy 50000 D211 Us og enon a Dedi n d CE n n Soo Suas B P e d eR 9 9417 R282 S EPA 55 ST S655 Zorro E S 5 HH cro og Sp R679 8g82828 n 8 9 226696 rn n ONrez4 og C653 00000000000 PL204 PL202 PL201 C684 00 Bossa 706 cess na R668 R658 nn R681 0000 I N c694 O7 R722
28. BALANCEDPROPAGATIONDELAYS tPHL OPERATINGVOLTAGERANGE 2V to 5 5V IMPROVEDLATCH UP IMMUNITY DESCRIPTION The 74V1G08 is an advanced high speed CMOS SINGLE 2 INPUT AND GATE fabricated with sub micron silicon gate and double layer metal wiring CZMOS technology 14 FMS6145 Low Cost Five Channel 4th Order Standard Definition Video Filter Driver Description The FMS6145 Low Cost Video Filter LCVF is intended to replace passive LC filters and drivers with a low cost integrated device Five 4th order filters provide improved image Quality compared to typical 2nd or 3rd order passive solutions The FMS6145 may be directly driven by a DC coupled DAC output or an AC coupled signal Internal diode clamps and bias circuitry may be used if AC coupled inputs are required The outputs can drive or DC coupled single 1500 or dual 75Q loads DC coupling the outputs removes the need for output coupling capacitors The input DC levels will be offset approximately 280 at the output Features Five fourth order 8 2 SD filters Transparent input clamping Dual video load drive 2 750 AC or DC coupled inputs AC or DC coupled outputs DC coupled outputs eliminate AC coupling capacitors 5V only Lead Pb Free TSSOP 14 package Applications Cable set top boxes Satellite set top boxes DVD players HDTV Personal video recorders PVR Video on demand VOD 15 DESCRIPTIONS AN
29. EN 5 2 50 n 55 rap 12 9 5 558 SS 8 5 iaa 8766 aq Noor 08 mmdz eE S ALIS e ane IN E a 3 S SAN olos oe Ok oo 8 EN gt AN 8 1 dele 9 e gt amp 8 28 R281 0_ Sen E a IN p BE fs Oo FO OG opm 88 EP p ps R273 888 r 18800 9 X JR 2 ST NI DT ato aooo aooaa DE o 45500 8420 R523 GO OPER HR op Bl s R132 RKOD R314 Big elelee Sooo 5 0 0 R522 8 jm 5426 rcHarP4qgg lloc 6355 C663 o cu 5888 0214 o m 0 g 9 mods g a 0 0 0 05 00 5 Dae oe 5 S5 a joo 5 4 uM aC 8078 i 8106 gt 50257 5 amp 5 amp 8 ros Bu PL204 EFE 55 5 rr Le eyes amp 11 NM 52 en au 12010 Eneu 5 E zm 8 8105 amp 30258 S 8 kt 3 7 sies 00000 05 ollele loka 9 3 8 B 8 0 EEE E o Rs JE moan nao 57511515 misi mes 8 CALE ag 2100 gt 0 00 0155 ola 2 2 BLE S e
30. ag mme BE Re ea ER ofal ER S450 aa E 8 3 ee T RH em 9568 nn 8 22 161002 aem Ree nez 8 5 Ress Mu 1865 ie NC _4 amp 98 ds E 8 9 si 8950 C956 nS SEER S g om oS id aese 98 654 C1008 Sal i 1111 E zm E e 2 T t ojojo a zm sj qu E Menes uu 8 d B DE ress b 5 2142 C82 8 gere veran 5 3 8 2 G8 0828 zi 8 zu ZN R1129 R1138 n 109 7 8 a A ee 250529 Qi 25 mu incus 5 5 frat LI 33 Bate 853 55 lt gt 58 C869 a R957 o RY 5 55 up is 4 R1048 R1054 esas dso Hae Hast Hager POLE mange 7 S io 55 C900 a ewe RUE Rr Hid ALI ndi do mes wb ND a EE MUMM Hinn cnoo n nn ou N 101202 R1056 R1050 mp 8111855 gt 5 5 5 cass 5 28555 Bars o IC850 9648 EE IM 11057 81051 a Z 559485 dg AD A 3 co
31. bte 46 15 2 Power Management dudes a ve eruat 48 18 3 DRX IF Demodulator Block Diagram eese nennen nennen 48 EEE RS 49 18 41 General Block a Dt deuten aded btt eoru 49 184 25 MSP san id Ripa 51 18 4 3 Video Processor of 7wxyP Block Diagram eee 51 1 INTRODUCTION 17MB12 Main Board is a single board IDTV project consists of Micronas and NEC concept VCT Pro and Emma2LL are used as controller for TV and IDTV side respectively VCT Pro is capable of handling Audio processing video processing motion adaptive upconversion MAU Scaling Display processing and FPD control DPS unified memory for audio video and Text 3D comb filter PC connectivity OSD and text processing Emma2LL is capable of handling MPEG1 and MPEG2 decoding and provide nearly all the functionality required to realise a high performance and cost effective digital set top box or integrated digital TV TV supports DVB T reception and following analog receptions PAL SECAM NTSC colour standards and multiple transmission standards as B G DIK and L L including German and NICAM stereo Sound system output is supplying 2x8W 1096 for stereo 80 speakers Supported peripherals are
32. e 200R YPBPR Y gt E L lt 8V AUDIO 2201 R846 16V 100k 8V L755 Q603 R643 C830 as ges 5k1 5 3 8V AUDIO MUTE DVB GREEN P 5 RET CJ YPBPR_PB L757 4 CHROMA SW 100k 5 5V VIDEO 9 1 je 104 7 BC848B S772 3 a 5 VCC 8V VIDEO 25V C8 5V VIDE R848 IDTV 100k BLUE S C C802 gt PB IDTV B IN C894 100n R886 10V R889 150k 160k C895 N C E 5 lon en PL850 12v gt IN 7 16 R892 ga 7 5 m 42 1 MP1593 DC DC FAN2012 ANEL 5V sale gt SW COMP 10n 8 as 9 5 55 R888 16 R890 AS PGND 5
33. encryption for premium contents pursuant to the High bandwidth Digital Content Protection HDCP standard The ANX9021 embeds the HDCP keys and key selection vectors to reduce manufacturing complexity and system cost 15 5 1 Features Dual channel HDMI receiver supporting link data rate up to 1 65 Gbps HDMI 1 1 HDCP 1 1 and DVI 1 0 compliant WideEye architecture for signal conditioning and equalization support cable length up to 20m better than 10 12 bit error rate Digital interface to video processor supporting 24 bit RGB YCbCr 4 4 4 16 20 24 bit YCbCr 4 2 2 8 10 12 bit YCbCr 4 2 2 ITU BT 656 12 bit double data rate interface Color space conversion RGB to from YCbCr both directions 601 and 709 standards Auto video mode configuration Analog RGB YPbPr output with 8 bit linearity Digital audio interface 32 to 192 kHz audio sampling rate Up to 4 DS interface for 8 channel audio S PDIF interface supporting PCM Dolby Digital DTS digital audio transmission using IEC 60958 and IEC61937 Configurable soft mute Integrated HDCP decryption engine and pre programmed keys Programmable power management with automatic shutdown for power conservation Supports automated link integrity checking 144 lead TQFP package supporting lead free and green requirements Pinout compatible with Silicon Image 15 6 24LC02 15 6 1 General Description 24AA02 24LCO2B 24XX02 is 2 Electrically Erasable PROM The dev
34. 0 UN DL Ww R995 C979 olol 5 amp Tmrdn sju o n II io R896 E 1855 4 INI Pee EE c A Amm R993 995 Imus 9555 1022 5 R1071 55 ERI Salo 8 E C862 L Li106 wien 2054 C1009 8882 R992 9928 mololol 9519102 ser ANI 8 3 GE o xc wa 2D 04 e ee pnra nea 8 Roe D eee 6 gu RE d 22 el ETE nM I 1001 Z 2 Ex S f pied 25 RC LUE DE 1 0 zaar 0977 I 7 8 8 del pa NE 6854 eni BU J AR 8 R983 106812 5 R986 8 d B C896 10776 J L603 amme Vooy 88 aoge Hs 1088 l 2m R981 E 9996 5 TE d AY pale 5 ma Rare 1968 1852 9 P Q 58 ges OG EEE 00000 de 6972 2151599 51515151 300 SOT C E 35 Rode 1 656 05 Loe gp n p gp n p pz 2 d AE LE AY DO joro leja M ae oo 8978 fool C824 o 5 NEE b 8 B Me EE BR Bn ices mea Ta 3 2 8 2 8775 5 3 1 175 oo e R972 RO71 C958 821 C830 tare 8848 EH 38 amp P 5
35. 0278 R321 5 Q a Bi NIB amp 276 SS Cog O X O a 00000 Ly do LI 0 3 jojjo 7 MW UL 9 1 1 E C239 IL o e e amp e o oa C251 C285 R319 2 V E lt gt HTa Sn 0 0 3 59 2 Sus amp C287 C281 2 amp 7 d E amp n Gao o VA S PCB PCBKE 5 8 IL tun FD20 e 888 15
36. 2 GND FB 10k IR FPGA SUPPLY ahd aso NG L863 Ds IDTV SI 10u 4 L850 gS 2 gt 858 1859 48 VCC 12V PANEL 5V gt J vec sv 22uH 3 94 SMD 851 VIN 24V 1 9 az 52 5 52 an 9 9 9 5 5 12uH 1 74 SMD 5 2 Ld 3 t lt 4 _ PANEL 5 E852 p14 10110 1855 gt STBY LMII7 A VCC BV 22uH 3 94 SMD NETS C867 I C809 5 3 9A 5 R907 SVL 100n 100u HDON Ik 107 mu at 5 i fn gt fe H 4195 E 5 E C902 1C001 30026025 od vs 1005 C903 TP16 D 100 N O 1 2 iow Lin 30032610 10 30032 FROM 850 100 VESTEL ELECTRONICS Y Orio 17MB12 1 POWER _ 80113 e e e Date Author m gt zc g Q854 m SADIK SEHIT 9 17 04 2007 ISMAIL YILMAZLAR E EMRAH AKKUS S868 R867 gt 3V3 STBY PANEL SVI 369 330R Vici zgllz Q856 ol 3 FDC642P BC848B p ee o 8 p 10k SN R869 pg R865 2 D 10k lt veu C880 SV STBY s85 5 PANEL ON OFF 50 5 BE 1 o 50 as TP17 1008 8 5 ea z e 1 5 3 R896 gt eS s not nn E 3 2 7 S8 ELIO 3V3_STBY 9 9 gt m gt gt 5854 ON OFF
37. 22k Xv 1065 22K R1048 ara 22K R1049 aras 22K R1050 aras 22K R1051 aras 22K R1052 aras 22K 1066 e 22K R1053 uar 22K R1067 aras e 22K R1054 22K R1055 Qroaraio 22K 1056 22K 1057 uariis e 22K R1058 aras 22K R1059 roaraa 22K R1060 aras e 22k R1061 x STRAP PIN JUMPERS PE ME EP pd 2 4 33V D 10K R1062 C1009 0955 R1047 S960 BC848B 10k R1064 BESS 10k RESET IC 10n 16V RSTOUT 9954 C848B RESET CIRCUITS 1958 SV IDTV gt sv Hog a cae C1008 5 S o o 1965 1 950 LM1117 L961 5 33 C1010 lu ram D950 22 sav gt Dici 55 134007 gt gt T L962 3V3 L963 C1014 TP2 sv 1 8 5958 3V3 5959 1013 5 950 VESTEL ELECTRONICS 17 12 1 MPEG _ 90113 Date Author SADIK SEHIT 17 04 2007 ISMAIL YILMAZLAR ONUR KORHAN SAY
38. 5 S651 4 113 VD20 7 Joc HDMI RA BUE buo 1 7 1652 60R 100MHZ Pin38 Pind2 Pins7 Pin99 jui gt HDMII DIN 66 lt a J usfovss 1 n el ms 91 AVDD33 11 65 ppc sro Pero AR 28 4 5 gt 5 8 5 7 nomes SE AVSS_13 64 HA 5 11 3 671 2 Eee r HDMI DoP 63 e B 3 6 118JvD17 189047 Pingo Pin109 Pin122 3 HDMI R3 33 12 UPA672T HDMESYS boN 62 i 4 5 119 VD16 g esci HDMI BO R4 5 8 AVDD33 10 61 ane H 120fDvss_12 C654 Co Avss 12 60 H 10p_R690 10p R655 T 50 io ars 121 gt x 3 i as are Em 15 56R 5 DVDD33 gt 122 33 SD 16 5 4 CLKNJ 58 S652 123 H 17 EEo spa Joc HDMI G7 4 AVDD33 9 57 124 vD14 HDMI 18 E21SUP lt Es Pin22 RSVDAJ 56 x 125 VD13 1 8 H 19 SEM Y 8 AVDD33 8 55 2 27 5 3 5 nomi gu AVSS 11 5 1 127 pvss 13 AVSS 1053 H PL651 UVDDIS p 1 128 18_8 R665 R685 10 D2P 52 TM is HA R666 in cec
39. E HEN HERE HEN DRI7 DRIG C C C om 57 Digital Video Green 2 Input Digital Video Green 1 Input VCTP Pin No Type Connection Short Description If not used ew fm oovan mm ee fom fm _ me fm ee mw fm ee mw fm povoam m me fm oo m fom fm om fm ee svev om vsurssom om Sup vtage iit Ram rcs sav svev gt rsson suer mum m fom onon fom fom sese ve faen so zona Sut Fond m fa mer ox _______ mer om m svev fom ms sese E fer meer mono rona ber maom Pona Strom res Pona esmo P2 4 IN OUT RtoGND Port 2 Bit4 Input Output TDI JTAG Interface Data Input IN OUT RtoGND Port 2 Bit5 Input Output JTAG Interface Mode Select Input OSDV IN OUT RtoGND Graphic Vertical Sync Input Output DBO2 0 Channel 2 Digital Blue Output LSB VCTP Pin N
40. of fey RISS 6 6 o o o 4 4 4 5 MW SE 22 201 m n t 719 M m 4 JTAG CONN GM MEG ME MN EEG sO DEED m mus ALAS DADOS ul VAS A AS ES LS odo do c lel EP NS EE m n E 7 7 Z e m a R428 9 8 5 5 3 9 6 6 eee TE Khoo eB eRe ee ee EG E e EE TCK 6 5 o o o 92 4 gt gt gt aa gt gt gt gt gt gt gt gt gt gt gt e am z e e Qr en EB 2 2 a NES 92 TDO O gt 2 gt 2 a 9 1 65606 gt 2 gt gt vSUP3 3LVDss 156 LvDs 5 E 2 3 g 8 2 65605 iw uiss 54 SA 4 5 NC SDA 5 3 65604 LVDSB IP 54 I 3 2 1 re RI 4 65603 GND3 3LVDS4 153 A 226 PE R417 Q412 10k avs st p 47R 5 65602 LvpsB_2N 152 3 6 NC ee R3 6 65601 LVDSB 2Pf151 FE 3V3 STBY gt 2 BC848B Rf 7 65600 VSUP3 3LVDS4f 150 4 VSUP 3V3 LVDS R536 R411 L NC MEUS 8 8 RESETO LVDSB CLKN 149 EE i R408 Q402 Ro ens R542 47k BC848B SC_AUDIO_R_IN gt 9 JAINIR LVDSB CLKP 14s
41. 12 1 TUNER DRX 10f13 IDE Date Author SIL E gt Q100 gm 82 BC848B 33k sync 17 04 2007 ISMAIL YILMAZLAR SADIK SEHIT 22 AUDIO R IN SC2 AUDIO L IN SC SC2 AUDIO OUT o SC2 AUDIO L OUT R218 330R _3V 5V VIDEO TV LINK TO SHT7 47R gt SC2 SVHS C R246 5 STBY 4 7 47R R247 L206 C203 In 50 121 iov alg 42140 LAGT 5 LA n 2 2 BSN20 o R234 AS GAR 9 100R BE 4 75R L D218 5 2 2 T pop gt 5 a 58 8 BC858B 0202 mM BC848B R270 1508 R260 75R A Bm 5 6 5 7 BC858B zt C200 50V PL203 L207 R225 330R R219 L IN SCI AUDIO IN SCI AUDIO p SC1 AUDIO L OUT 5 AUDIO R OUT BAV99 D205
42. 5 2 2 eu Le amp S 2 EN PC HSYNC R465 5 Ss 55 EE 9 9 2 KEYBOARD 0405 9 b E B 5 2 BC848B E 2 M e 2 lt 2 ae a TA a Y 1 NS v 9 ezg ez 2 ez 9 amp 2 ead Na 5 2 u 5 gt n a T A l Su z 5 str 27 36 Y 4 10k al SESS 3 GE R430 VSUP 3V3 2 9 HDMI DETECT gt mm 5 4 lt lk R513 3V3 Q404 gt ar 5 gt a BC8A8B ac 5409 Ak7 E R426 j m 9 m m 2 o R505 e LS 2 5 0407 Pu 2 ar 3 vo ow 95 es R492 BC848B 55 EE See 28 47 Sen S Sp Se 4 E Q3 d us v S408 a7 50 259 9 5 v alg 20 Bare R502 2 us BC848B 0425 9 mm o HDMI SCDT BC848B 2 a Z R506 B F 2 E n SHEET 5 SYNC SWITCH sync detect e Io fs fel fey lel x fel fey sl e 15 15 5 151 fay fay fal fay o
43. 5 5 5 5 5 E 5 5 3 a A 5 Jam UTE R517 n 8 8 a a 5 5 5 IRQ 0 79 3 M24C128 5 ATR 2 Z m gt gt 5 E 88 x m n 5 23 6 x 8 55 559 82 x 5 L sw 10k 5 6 m M gt a 9 9 d 2 zl R493 3V3 R518 5457 E 2 in e 4 5 5 8 as 47R sp lt PROTECT_DETECT SHEET 5 2 5 3 5 8 a Sasi zz gt 5 W PROTECT 44 Su ik 2 5 o VSUP 3V3 101 sre o VSUP 3V3 FL sva stp gt VSUP 3V3 103 sva sre Jo vo v v CT USED oi R548 4 lt gt 2 30021752 BEE En ME JE 3 8 5 2 3 14171416 SHOULD BE 30016659 SHORT CIRCUIT AND HEADPHONE DETECT S465 SOULD BE 82R COMMON I2C FROM 600 to 650 VESTEL ELECTRONICS 17MB12 AUDIO 40f13 Date Author 03 01 2006 ISMAIL YILMAZLA RASIT GOKALAN AKT S660
44. 7 Input Output TCLKFW JTAG Interface Clock Input FW Controller 1 TTL output version only 2 LVDS output version only 6 DRX 3961A 6 1 General Desription The DSP based Analog TV IF Demodulator DRX 396xA performs the entire multistandard Quasi Split Sound QSS TV IF processing AGC video demodulation and generation of the sound IF SIF requiring only one SAW filter The IC is designed for applications in TV sets VCRs PC cards and TV tuners The alignment free DRX 396xA does not need special external components All control functions and status registers are accessible via I2C bus interface 6 2 Features e Multistandard QSS IF processing with a single SAW e Highly reduced amount of external components no tank circuit no potentiometers no SAW switching e Programmable IF frequency 38 9 MHz 45 75 MHz 32 9 MHz 58 75 MHz 36 125 MHz etc Digital IF processing for the following standards B G D K L L and M N Standard specific digital post filtering Standard specific digital video audio splitting Standard specific digital picture carrier recovery Alignment free Quartz stable and accurate Stable frequency lock at 10096 modulation and overmodulation up to 15096 Quartz accurate AFC information Programmable standard specific digital group delay equalization Automatically frequency adjusted Nyquist slope therefore optimum picture and sound performance over complete lock in frequency range Standar
45. E Short Description Digital 656 Bit 1 Output Port 4 Bit 1 Input Output JTAG Interface Data Input TV Controller Digital 656 Bit 0 Output LSB Port 4 Bit 0 Input Output JTAG Interface Mode Select Input TV Contr Reset Input Output Analog Audio 5 Input Right Analog Audio 5 Input Left Test Input VSUP5 0 SUPPLY Supply Voltage Analog 5 0 V 2 e 3 VCTP Pin No Type Connection Short Description not used 208 1 on if SUPPLY Ground Analog Platform Ground GND3 3DIG SUPPLY Ground Digital Interfaces VSUP3 3DIG SUPPLY Supply Voltage Digital Interfaces 3 3 V 3 SPDIF OUT SPDIF Output 25 DA Audio Bus Data Input 25 CL N Jen Audio Bus Clock Input N Jen Audio Bus Word Strobe Input 125 DEL OUT OUT IN Audio Delay Line Bus Data Output Input 125 DEL IN OUT Audio Delay Line Bus Data Input Output 125 DEL CL OUT IN Audio Delay Line Bus Clock Output Input 125 DEL WS OUT IN Audio Delay Line Word Strobe VSUP3 3RAM SUPPLY Supply Voltage Ram 3 3 V SUPPL Digital or Analog Video VSYNC HD Input Digital Video Enable Input Digital Video Clock Input Digital Video Red 7 Input Digital Video Red 6 Input Digital Video Red 5 Input Digital Video Red 4 Input ND 7 47 DVS E a oax ER ry
46. H WAIT_CI gt GRDYB RADDI2 gt gt 12 DI tH gt TS VAL H IORD CI RADDI3 gt gt A13 D2 q roarai TS MERR E H IOWR p Jrowr e RADD14 gt gt A14 14 245 D3 tH koara _ TS STRT 4 H REG p prec I gt OE CI D tH 7ALVT245 OLACAK 4 lt 3 3V BUF lt 3 3V BUF lt 3 3V BUF lt 3 3V BUF 65 tH roarai D6 tH I duras R1208 D7 tH 3 3V BUF AKT o CARD DETECT EUM 5 5 CD 1 CI oper gt IE WI BC848B Y 3 TP SS sv z rann at e Pc A R1210 R1213 100 8 2 5 01202 25V 7 m A CD 2 AKT vs CI AKT BCSARB Ed fA E al mo lu c SW CNTRL INV S R1201 Io R1216 R1217 gt sw cure viped 10k 10k EM RESET R1215 Q1204 R1220 Os POWER 10K s CARD_RESEP gt 10k Bern L1201 pp o 3 3V BUF RE FERRITE ee gt st a zona I e e e 9 2 m C1200 H d 9 RN lt 5849 5555 9 55 gt 5 76 188 xs 98 E 5 a gt 2 9 tg o MDO E
47. NOT 4 gt Y PL853 DIM PWM BRT CNTL R893 E PDP GO BL ON OFF Su Ak7 CRASH 8863 3v3 alas 1 DIG DIM PWM 2 Kol 2 2 S864 2 sv e e S856 3 do 3v3 um 2 S857 9 ak 4 m ssuscr DIM SELECT sv 5 8 259 5850 DETECT 5858 Y 5 S852 as TPIS 1851 VCC 12V N OFF NOT 2454 DETEC 6 8853 R876 25 BC858B STBY_ON_OFF R900 BAW56 10k 7 AKT sv gt S872 BRT CNTL q ik 8865 4 e RS ET oo e gt 8 1 3 3 10k ta R898 gt 2 gt 5 gt 9 2 5 e pm BAWS6 oa 0863 AR BC848B Va 8V 3 10 0851 PANEL 5 gt 7 fram vor
48. O SHT3 i gt PC VSYNC Sw PC VSYNC JOANE R214 R216 10k BAV9 D204 99 D202 DDC SCL 3V3 Wye q BC848B R306 MTA CHROMA e 10k M al Sz s eo a BC858B Q207 BC848B R286 R296 150R 75R SC1_CVBS_OUT vj BC858B 8 206 gt 90 X 2 gt e gt SY 088 SW INV R304 14 Q212 gt 10k e 848 VCC 4 5 0 10k R312 10k R309 m SV EXT vec 5 n o euet 9 l Tus SW INV m PL206 gt DMP_DVD 5 DVD R332 75R o DMP DVD DMP DVD T R328 75R d DMP DVD_SWIT DMP_DVD_CVBS_IN SC2 SVHS C C277 x 100R 275 100n 10V 50V DMP AUDIO 1 I DMP DVD AUDIO R
49. SHEET 4 N TXCLKQUT AOUTIL 25 JHEADPHONER ON cC LVDSA CLKN 132 TXCLKOUT gt 26 HEADPHONEL LVDSA_CLKP 131 TxcLkour P 10k lt R416 TXCLKOUT R530 S419 47k 27 JSPEAKERR GND3 3LVDS1 130 10k lt VSUP_3V3_LVDS m 5399 8421 sg SHORT SPEAKERL LVDSA 3Nf 129 c pror TXOUT3 gt 3V3 9 gt i 29 SUBWOOFER LVDSA 3P i2s B M IR DETECT amp diues map ye E LED DRIVE CH NC R520 R 2 5 31 SIFIN LVDSA AN 126 10k M C454 3V3 E R415 56p SUP 3V3 I SHORT jov o gt 32 SIFIN LvpsA 4p iss LVDS OUTPUT a 3 3 5 56 VSUP 1V8 DIG NO SUBW M VSUP5 0 VSUP1 8DIG 124 ps VSUP SV SIF gt C418 Eas SHEET 34 GNDA2 GND1 8DIG 123 al au l a 9 AMPLIFIER NEG q Ak7 93 8 ny of afi 1 B 10n 35 GND3 3DIG PCLK1 4122 3 2 gt 16 audio ground R508 VSDP SVS COM PE gt Cais vsue 36 VSUP3 3DIG PCLK2121 10k 8 0418 R431 R495 R539 AMPLIFIER_L_NEG verp_sppir ART 37 SPDIF OUT PCSO 120 100R casus 1 4k7 sf 108 RA34 R512 522 il i 47R 38 I2S DA IN PCSI 119 10k L407 R435 VSUP_3V3_C
50. SMD 0402 SN 99 99 D229 5206 L M BAV99 Q214 BC848B 108 SPDIF MR CE gt L225 C272 R313 R314 1506 108 lt SPDIF FERRITE ais c 100n E 915 ER 16V 518 m Ik R293 C268 FROM 200 to 400 VESTEL ELECTRONICS 17MB12 1 PERIPHERAL 2of13 Date Author 13 01 2006 ISMAIL YILMAZLAR SADIK SEHIT
51. Teletext data as well as Video Programming System VPS Program Delivery Control PDC and Wide Screen Signalling WSS data used for PALplus transmissions line 23 The device also supports Closed Caption acquisition and decoding The TVT provides an integrated general purpose fully 8051 compatible microcontroller with television specific hardware features The microcontroller has been enhanced to provide powerful features such as memory banking data pointer additional interrupts shared memory access etc High performance 8 bit microcontroller 8051 instruction set compatible 81 MHz system clock two machine cycles per instruction On chip debug support OCDS Up to 512 kByte in system program Flash 256 byte on chip program RAM 128 byte on chip extended stack RAM 4 level 24 input interrupt controller Patch module for 16 ROM locations Two 16 bit reloadable timers Capture compare timer for infrared decoding Watchdog timer Uart Real time clock PWM units 2 channels 14 bit 6 channels 8 bit 8 bit ADC 4 channels 2 bus master slave interface Up to 32 programmable ports 5 5 OSD amp Teletext Features The on chip display unit for displaying Level 1 5 Teletext data can also be used for customer defined onscreen displays The TVT has an internal XRAM of 32 KB and a BOOT ROM of 4 KB For operation the code is fetched from a 16bit FLASH which can be addressed up to 1 MByte In combination with dedicated hardw
52. amp NZ Co ERER BE o TU100 CU nn 5 x EE 3 ns 8585 5 an fpi C626 2 5 5 Aor 9 os 859 6230 C231 Ole 5 3 8 4 R539 Q760 R686 R684 8682 C666 a TN J 48855 55 gt 8888 cor 55 mess 2 l amp 5768 5760 0000 80000 810000 AI ua IP 0955 E Be BR ONE logon I 88 L zi 58858 8 a 5 a Sersee 0000 0000 iq o camem s 5 reme 75 T 0000 S ZZ lam 5 BEL 8 588 858 5 0000 10000 0000 tl op 8 BE H 8558 herred 1756 888828 I Bae amp 55 io 9 T UO 00 00 0 58588 P 755 20 toe 8 88 8 lul n tmr ELI 5555 ES Siralelste als 996 E ag 2a BALIN 7 Oo 2 SN Qo 9 lo 10555 gs PO LE S H 1C1207 IC1205 5 Q 100 R289 N ras 5 0207 E 8 703 d 5655 ago 2 e N 7 8 ol B ale A zu 5 16 16 16 18 Ee te 507 Hug 30 556 I 2228 Dat 2 233 12 1 1 2 zx 5 5 gr
53. chassis side Step 3 Run a RS232 terminal tool like Hyper Terminal Step 4 Following settings of the terminal tool are necessary Protocol Xmodem Port COMx Baud Rate 115200 Data Bits 8 Parity none Stop Bits 1 Com Control none Step 5 Load the bin file from Browse and Click Send Step 6 Power off and on again TV set to produce hard reset 18 BLOCK DIAGRAMS 18 1 General Block Diagram SUAS SLASH X Me Z ISDS HO11MS 5 e T ZLYVOS 1 304 5 OS NAL YONISYNYTNDAN did GH GS 3A LNO O3GIA 2 1395 10N SONL ptg 2 4 SANL 1206 2045 JON 2u SH aiaa x 9 HOLIMS VON HOLIMS NI 893 1X3 XOIN xc ENG 2 aiaa YIMOd 1x3 Od 49 YdBdA NI SBAD v3 NI Olanv SHASIAV3 0 NI 58 0 1X3 NI FOH LX 74 NI Olanv HOLIMS 4 0 225 VNOMNHO 03103135 WNOHHD SHAS SHAS 3 e NI Olanv LAVOS 931997 I Olanv 114 26 sama 8 I SHAO AV3 85 4 RUM 1no 21 25 4dddA NI FREE Je som 25 g 4 m xx u
54. iini MER 20 7 SERIAL 64K DC EEPROM M24COAWBNO 2225254 ted eaae Fe 2 7 1 General Description denn teo des pog rc ebat iban ico GE 21 tocco EE EUR 21 7 3 Absolute Maximum S bu YES 22 y EMEN I o PDC 22 8 CLASS AB STEREO HEADPHONE DRIVER 7050 22 8 1 General Deserptlofi c qae cocer ice test bat Sande 22 8 2 FE RR 22 8 3 EEE ER EEE 23 97 SAW FILTER gne 23 9 1 Fe e E 23 92 os 23 9 3 Frequency response Gabe ea mesi 23 10 MPEG DECODER PDS 1D te eee ED 24 10 1 DESERPAION d d Y Prepaid E ug 24 FEATURES sara 25 11 CN 25 LE TONE 25 1122 25 113 Appleations eade test 26 12 6 100 27 3 3V VCXO for Set Top Box Applications 26 1221 Features eneretten 26 Ie EDI eura fo E 26 13 27 14 ENISO idee dor deo pte 21 15 IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM 28 ISE AM gs 28 Sell General c 28 BIE TRUS 20 ch
55. internal memory 3D comb filter for PAL NTSC with internal memory Optional Internal SDR RAM interface Powerful horizontal and vertical scaling inclusive Nonlinear horizontal scaling panorama vision picture adaptive image improvements DCE LSE CTI SCE NCE non linear colorspace enhancement NCE with 32 programmable slopes and sections per RGB component blue stretch static black stretch gamma correction Dynamic contrast enhancement DCE histogram based black stretch with peak black and activity detection and contrast adaption Luma sharpness enhancement LSE Color transient improvement CTI Selective color enhancement SCE for skin tone correction blue and green stretch 5 2 Multistandard Sound Processor MSP Features The MSP receives the analog Sound IF signal from the tuner and converts it to digital with its internal SIF AD converter The MSP is able to demodulate all TV sound standards worldwide including the digital NICAM system TV stereo sound standards that are unavailable for a specific VCTP version are processed in analog mono sound of the standard In that case stereo or bilingual processing will not be possible Sound IF input Worldwide FM AM mono sound demodulation FM stereo sound demodulation A2 EIA J BTSC SAP demodulation with DBX NICAM demodulation FM radio amp RDS RBDS demodulation Automatic standard detection automatic volume correction AVC Automatic sound select Baseband processing fo
56. symmetrical 4 5V supply voltage for loop through Ti g 3 AUDIO AMPLIFIER STAGE WITH TDA8932 3 1 General Description The TDA8932 device is the high power version that delivers an output power of 2 x 10 WRMS to 2 x 25 WRMS in a Single Ended SE configuration or 10 WRMS to 50 WRMS in a Bridge Tied Load BTL configuration The TDA8933 device is the low power version that delivers an output power of 2 x 5 WRMS to 2 x 15 WRMS in a Single Ended SE configuration or 10 WRMS to 20 WRMS in a Bridge Tied Load BTL configuration This high efficiency SMA device is designed to operate without a heat sink and has the flexibility to operate from either an asymmetrical supply or a symmetrical supply with a wide range 10 V to 36 V or 5 V to 18 V The TDA8932 33 device utilizes two advanced features respectively the thermal fold back and the cycle by cycle current limiting to avoid audio holes interruptions during normal operation 3 2 Features e High efficiency Class D audio amplifier due to a low RDS_ON Operates from a wide voltage range 10 V to 36 V asymmetrical or 5 V to 18 symmetrical Maximum power capability TDA8932 is 2 x 25 WRMS maximum in 4 O SE without heat sink TDA8933 is 2 x 15 WRMS maximum in 8 O SE without heat sink Cycle by cycle current limiting to avoid interruption during normal operation Unique Thermal Foldback TF to avoid interruption during normal operation Integr
57. 00 Latchup Current Maximum Rating Following Specification JESD78 Class ILatchup mA Positive 200 Negative 200 Maximum ratings are those values beyond which device damage can occur Maximum ratings applied to the device are individual stress limit values not normal operating conditions and are not valid simultaneously If these limits are exceeded device functional operation is not implied damage may occur and reliability may be affected 1 This based on 35 35 1 6 FR4 with 10mm of 1 oz copper traces under natural convention conditions and a single component characterization 2 The maximum package power dissipation limit must not be exceeded TJ max 150 D xp 15 9 4 Pinning MARKING DIAGRAM SOT 23 236 CONFIGURATION CASE 318 GND 1 Vea SC 70 H CASE 419 E RESET 2 11 RESET XXX Specific Device Code SOT 23 SC 70 M Date Code Top View Pb Free Package NOTE RESETis for MAX809 Note Microdot may be in either location RESET is for MAX810 15 1024LC21 15 10 1 General Description The 24LC21 is 1K bit electrically erasable programmable memory organized by 8 bits This device can operate in two modes Transmit Only mode and I2C bidirectional mode When powered the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK 15 10 2 Featur
58. 1 dx 2 x mi mE M EX 2 al 559 4 89 DO fioo 4 0 29 24 3203422 25 gt ram vor C96 gt 16 5 16 B 16V 1000 28 458181 43 S8 dS 48148 d 9 2 d Q 9 gt 5 ICI 1 Z a 6 5 5 5 a 527 5 B E 5 gt g 2 8 2 2 E E 0 9 967 4 5 38 E B 10u 11 8 4 eon wa ace h 2 5 a d 25V 5 2 E 1967 1968 885858 5 2544 C966 R986 1 220R 100n mn 5 5 0 8 5 MPEG DECODER
59. 1 RF input VHF1 VHF3 UHF 75Ohm 1 FAV input 2 SCART sockets 1 SVHS input 1 Stereo Headphone input 1 YPbPr 1 PC input 2 HDMI input 1 Stereo audio input for PC and YPbPr 1 Stereo audio output 1 Subwoofer 1 Spdif 2 TUNER Vertical mounted digital tuner is used in the product which is suitable for analog reception with DRX A The tuning is available through the digitally controlled 12 bus PLL Below you will find info on the Tuner in use 2 1 General description of DTT71307 The DTT 755 is designed for digital terrestrial reception VHFIII and UHF compliance with the European digital terrestrial standard ETS 300 744 In addition the tuner covers all analog channels from 44 25 MHz to 863 25 MHz It is a two band concept VHF and UHF with VHF switch between low I and high VHF 2 2 Features of DTT71307 e VHF UHF frequency range e _ Antenna loop through optional Low phase noise High level digital IF outputs RF Modulator input for loop through to TV output optional Wide band AGC Indoor Antenna power feed through optional 2 3 Pinning Symbol Description MOI RF modulator input or antenna power supply input RAG RF AGC output input Chip I2C address select SCL 2 serial clock SCL I2C serial data 5V supply voltage for tuner 4 2 crystal oscillator output GPIO VTS Open or 33V IF2 IF output symmetrical IF1 IF output
60. 2 lt D A a A AE Z 2 Z e 2 0 9 gt gt gt gt 0 a gt UO O gt 0 gt A A 9 1 GND 13 em z 2 PPORTI GNp 12 161 7 2 88 3 2 2 14160 von 100R R959 4 DQIOf 159 5 PPORTA4 11 158 6 5 12 157 7 PPoRT6 13 156 100R R960 8 PPoRT7 144155 aw PPORTS DQis 154 152 PPORT9 2 153 56 TS7 GND GND 11 152 GND 1 JrRST 151 VDD1 JTCK 150 pou 2 zs e JTCLK 14 1 129 JTDO 15 PPoRT 48 RDATAO 147 Dus RDATAO TXDIB 146 RDATAI RDATA2 RDATA2 RXDIB 145 RDATA3 RDATA3 NMI 144 RDATA4 RSTSWB 143 RDATA4 RDATAS RSTOUT 142 RDATAS RDATAG 141 7 RDATA7 vppa 3 140 RDATAS GND 10 139 RDATA8 RDATAS GND 9 138 RDATA9 O RDATA10 K RDATA RDATATO 00 CLK27IN 137 VDD3 136 GND 2 PAGND 135 RDATAII 1 3 134 R1015 RDATA12 PPORTA44f 133 12 4 RDATA13 PPORT43 132 F RDATA13 Ben RDATA14 2 131 BH RDATA15 R1017 RDATA15 30 lk RADDO 40 29 RADDO RADDI 28 RADDI RADD2 RADD2 8 27 RADD3 R1026 RADD3 PPORT37 126 1908 P ove 100R DVB RX RADD4 PPORT36 125 4 RADDS PPORT35 124 RADDS RADD6 RADD6 PPORT34f123 RADD7 9 RADD7
61. 29 15 3 Applicat ons 29 15 1 4 Absolute Maximum 29 515 JPIDIIDE Do iesu rekna 20 BAMBLE 29 1521 General Description etae rtr duae duo das du 29 ITA NEN Vu E 30 15 2 3 codes 30 15 24 Absolute Maximum edidere 30 T2256 30 15 35 MP tette Deui 31 15 31 General Description aeee a 31 T EE ion toulouse 3l 15 5 9 Applicat Ons erasa ote too Io 31 15 3 4 Absolute Maximum 32 1555 Electrical He Sedo Seide 32 15 50 a aaa aE a tE 32 194 uera ee endda Ea 33 ISAT General 33 lc AMI mre aS 33 15 4 3 Absolute Maximum Ratings 33 ISAAA PII Sic dha 34 lt 34 B51 Fess PA 34 15 60 TE 35 19 61 General DescrIpBIOB do ha Ma de 35 15 6 27 etn 35 15 6 3 SST 36 S
62. 2V Under Voltage Lockout Available in 8 Pin SOIC Package 15 3 3 Applications e Distributed Power Systems e Battery Chargers Pre Regulator for Linear Regulators Flat Panel TVs Set Top Boxes Cigarette Lighter Powered Devices DVD PVR Devices 15 3 4 Absolute Maximum Ratings Supply Voltage 0 3V to 30V Switch Voltage 0 5V to 0 Boost Voltage Vgs Vsy 0 3V to Vay 6V Al Other 0 3V to Junction 150 C Lead Temperature 260 Storage Temperature 65 C to 150 C 15 3 5 Electrical Characteristics Parameter Shutdown Supply Current Ven Supply Current 2 6V Vra LAV Feedback Voltage Ves Error Amplifier Voltage Gain Error Amplifier EN Transconductance Gea Alcowe 10 pA High Side Switch On Roson Resistance DS ON High Side Switch Leakage Current Current Limit Current Sense to COMP Transconductance Gc f 5 Minimum Duty Cycle EN Threshold Voltage 15 3 6 Pinning 1 85 High Side Gate Drive Boost Input BS supplies the drive for the high side N Channel MOSFET switch Connect a 10nF or greater capacitor from SW to BS to power the high side switch Pin2 IN Power Input IN supplies the power to the IC
63. 4 5 L 2 gt 1 Po 25 gt 40 4 RDATAS 5 me 5 36 IC1100 DWEB lt a NOTLCLK mm 5 ele enun 3305 5 EP mus 57 DRXD3973D j ux RADD21 39 4 RDATA12 DCASB gt 4 LCLK Hi 58 PMQFP64 E DRASB 4 DCKE ES gt MERR FILASH_WE gt 38 lt 4 RDATA4 DCSB 51104 ot RESET 37 m gt 4 DADDII 1 80 62 1 8V DEMOD 55 5 51100 85 rio d M29W160B a 5 1 E E 63 11 36 lt 4 RDATA11 DADDIO 4 DADD8 64 gt DADDO 4 DADD7 C1103 51102 ton a x 35 lt 4 RDATA3 DADDI 4 DADD6 16V n 4 0 0 0 9 a DADD2 4 DADDS 60 gt 5 2 2 2 2 2 gt gt 8 8 T m fe S lt 15 m RADD20p gt 0 0 34 RDATAIO DADD3 4 DADD4 x T ae T T T T T T T T Pa C1152 lt SDATA gt 4 7 e uon RESET b d 23 x 5 16V NES lt SCLK RADDI 32 RD 1008 St eg Dt 1 8V DEMOD SL 2 TE xU duse DDR SDRAM RAM OPTION 2 IC1003 RADDS 31 RADD7 30 RDATA8 74 1 8 C1130 121105 1 8 gt o 1 8V DEMOD C1114 En 1123 C1133 RADD6 291 1 RDATAO IC1102 8 5 100u m 4 560R
64. 41 245 14 245 TS5 RADDS TS5 MDO 5 gt TS6 MDO 6 gt TS7 MDO 7 gt 3 3V BUF R OUTPUT AO Al A2 A3 4 5 TS6 RADD6 A6 7 TS7 RADD7 3 3V BUF gt gt E gt D gt E Pisa J PD rs oe gt Db lt gt gt gt 14 245 gt gt 4 lt 4 3 3V BUF C1203 C1204 C1207 C1209 IC1202 100n IC1203 100n IC1206 100n IC1207 100n 10V 10V 10V 10V SW CNTRL INV p 3 3V BUF SW CNTRL p 3 3V BUF POWER 3 3V BUF POWER 3 3V BUF 10V MDI TS CLK INPACKB CI p gt RADDS p gt 8 IC1208 uvap MDI VAL TS VAL R WRITE WE CI RADD9 p gt A9 3 3V BUF CI DIR MSTR MDI_STRT TS MERR gt gt CE 1 CI RADDIO p gt A10 POWER CNTRL p RDATA8 TS STRT IREQ CI gt IREQ RADDI I p gt 11 7ALVX2AS 7ALVX2AS 7ALVX2AS 7ALVX2AS gt TS CLK 4
65. 55 c c gt 52 AMPLIFIER 1 C612 R601 R615 m E R802 R814 100R e sv auni 470n 16V 5 SC2 AUDIO R IN C613 R616 IC653 gt p 750 to 850 i e ane ation E VOR 100MHZ 200mA AMPLIFIER L NEG 4709 25 E VESTEL ELECTRONICS 8V AUDIO U ma amp z _8V_ gan 17MB 12 1 AUDIO amp SW 6of1 1799 VSSD HW3 Date Auth ia 25V SADIK SEHIT le SC_AUDIO_R_IN 17 04 2007 R804 R816 R821 ISMAIL YILMAZLAR vcc 100k 100k 12k R837 C809 NC 758 SC2 AUDIO L IN SC CVBS IN R838 z R817 BLUE e 758 o DVB BLUE S C Rue 25V 12k 75R 200R R839 220n Ne R828 R834 75R 600R 100MHZ 200m R989 IDTV YPbPr SW VAKT SV VIDEO 5 AUDIO L IN 1 1 135 100k 100k CC 8 VIDEO ENC_REDP gt P D gt 1908 R812 R818 C819 vec_sv_aupip gt 100k 100k 74HCT4053 SC2 CVBS IN 3008 R841 220n 9 C811 758 R987 C824 SCI AUDIO L IN gt A 1YO 16V Reiz R829 R835 3 OUT3 75R _ lu 25V 100k 100k CC 8V AUDIO R1041 220n C820 300R FMS6145 F lt SC1_CVBS_IN sv c GND im E gt 8 16 lt VPA s PR IDTV C825 D M F 49 R844 5 ENC GREEN S 75R gt DVB GREEN S Y MT be R979 220n C827 R836
66. 70 1 950 C1016 R1206 mRi214 C1205 C1200 6 204 1214 DE R443 F mar eal ioe fast estes 113 5 3 00108 OOO ban R438 Z 7 Ex ere OO OOO SOS SSS SO OO IN Og 3 Biokkr tee 3 3 E HAST 17MB12 1 1 Ren C701 qo DSR bi n QI SS S c Su EORR L gt 5107 4 Nt P SEIL HA En arm 290607 Rea 953255856 C669 IN nu uu 20 O s FOE s saps 290 Sent aa daa 919151515 able palolla 4 NL ESSE Sev 9 amp s mit n o 8 5 00 ale 215100100 ER Ex 45 668 ag R110 00000000000000000 56 Bekk oma 171454545550 Doo ore ses LF eee FEN 205 Bn em 88 ol 885 4 58858 Elola ole BE SOLD 888 C288 eet is 3 i Olea 8 2 CTS Ex e 000 io lollo P n 5 S r LJ n TEE LAC LSU SC ES NES Np E 05 iao cite 1210 R1212 5555 LE Stee Ri25 0119 E 4 ST S 100 Rid C118 R1200 3 C439 INE 52 85
67. 8 C976 en BL 8837 C970 8 8 ung LM C1122 C1116 O0 5873 mor AS 12302 8555 C1129 nn an vx 5863 R841 ao C973 E C1104 5 e T 2 3 r 8 gt gt 8843 B 0 01106 22 e e C1107 ot 9 3v3sTBY M 0 0 1105 g ES B o o n og zl ag 2 00 C1136 O e E oo o E 83 d 118 TP651 1V8STBY p 1114 35 1128 C C889 ratio oO 8 9 8 m m S 9 88 C432 ERE 22 5 Q nn 0867 gt R1065 om E pr R119 1121 ae 01203 1963 m T 1V8DIG C686 L405 40g 8 1410 9 C401 is 88 x i 8 81e ne om 81499 o 2 81102 1962 2 n 08 5 3 D412 5 C434 403 5 C1121 9980 B C410 I 2 o 0 99 oo C1147 D 208 9 g C413 SCB 0408 CRON 0 oo 01146 71019 IP C405 3077 09 amp 1400 R477 fot 98 1 opon JA QI Lapis 90489 e ggo 3 s 8475 R472 3 goo 0409 oo e ERG ER e 5 gn 2 Te 20000 dog C431 P C402 19 om R461 R473
68. 8 470 2 2 2 gt lt _ lt E lt lt lt HDMIO 19 ixl o IR 2 4 amp SDA A S pap psy SSS 515 5 SW ENABLEI RAMS PEIFEJIPEIPISPEIERS DVDD18 m OLT PIE a 1815 151815 ol CABLE_DETO E E 5 B Sx B 8 E CABLE 9 E 8 cese gt B cB E zo gt 4 lt C726 E E amp 4 A lt bs bu T i a 8 sH ov 8 gt 8 8 C707 18p 727 100n 2 Zi 2 Zi sov C657 10V 16V 16V 16 716 9 728 R727 4 682 lam C68 mmmn 4 18 Qe HE v mt n IC554 R673 10V 50 G UU v v 7 50V tak 4 VECON 8 4 9 g 150R 600mA lik ferit omo D650 2 gt 2 2 5 EN d L657 8 20k vec s s x A 4 8 AR 3v3 p 28 2 1N581 gt 3 UPA672T R678 D651 m Om eae 2 DMIO _ gt em E lk 4 5 gt E20SUP p lik ferit LM1117 b R677 HOTPLUG 145819 16 HDMI 3V3 sv gt d R688 DE 3 3 gt VOULSN 5 5v Ik 5 gt 10R C697 l 701 R724
69. 8 5 mE ea gS 36 18 BE dudo 3605 2N7002 7 10V AMP MUTE sy H rpm sp MG AER Sess R681 3 ELLE 100n 8 5930 ROO k CABLE DETI ES Pine e carte pero 0 9 10 Mb 9 mm E E Eg 44 85 248 99 5 C674 BD g R691 ZU A v 5 5 2630 sz 3v3 D ax 8 gs ES 95 a 5 D gt E 2 zs lt lt gt 2 2 5 uwyT4 L S653 T ft pd e pee 818 5 5 181 13 18 5 19 13 18 8 19 18 8 8 5 2 nd o d d a om ot me 5822 59 5 4 44 RE EI R669 QD Qu o Z a 0 5 gt 1 R653 P A a 7 9 Y gt 470K s r se 2 2 8888458 5 9 4 4 4 amp a a lt gt gt gt 2 gt 2 a 2 UPA672T a VE x lt 2 AVSS_15 72 H DUVDDSS p 1 109JDVDD33_5 5 3 HDMI HDMI R682 a _ 71 a Ie 70 R670 R654 2 111 vp22 5 sen 470k it me AVDD33_12 69 Javpps3 3 6 112pvD21 6 m Avss 14 68 HA
70. D 5 2 FF 4 272 sov Q423 R550 gt t 5 b 5 5 5 2 2 9 9 42 5 d d 7 A 9 8411 BC848B Le 6 6 6 A B o A A n A A A A 7 uo 5 A gt o o v M gt Belik gt gt B q H 9 4 18 im ix fol Jal lol a o 5 5 1919 5 4 PANEL VCC ON OFF BC848B 1559 v 5 amp co co cof cof o 5 fal 5 Rai 3 Rx Data Q421 2 Ak7 a 8 UART RX T ce 7 C499 9 2 gt VSUP 3V3 LVDS E QoS C496 1412 i i 4 E BC848B gt 10p a Jo vsur DIG 5 E 2 2 5 10p sov Q424 R551 Qv A mi 5 BC848B 47k 21245429464 de gg ge 5 21 71471 MU x 7 5 55 1 5 X400 A R489 2 lt gt 10k 41 sp 5 2025Mhz a E gv use 5 3 3 RSIS 2 a n AT gt 7 10k BIS M x x 2 2 SV3 COM VES OM 5 POWER ON OFF 2 3 DRI RAM 2 4 z 2 o 5 8 9 4 2 f E A 5 E d 25 s 12 24LC32A PORT SAVING 9 sre sre Jo 1vs 5 5 5 5 5
71. D INTERNAL BLOCK DIAGRAM LM1117 LM 1086 MP1593 FDC642P SIL9011 241 2 uPA672T M74HC4052 Max809 24LC21 15 1LM1117 15 1 1 General Description The LM1117 is a series of low dropout voltage regulators with a dropout of 1 2V at 800mA of load current It has the same pin out as National Semiconductor s industry standard LM317 The LM1117 is available in an adjustable version which can set the output voltage from 1 25V to 13 8V with only two external resistors In addition it is also available in five fixed voltages 1 8V 2 5V 2 85V 3 3V and 5V The LM1117 offers current limiting and thermal shutdown Its circuit includes a zener trimmed bandgap reference to as sure output voltage accuracy to within 1 The LM1117 series is available in SOT 223 TO 220 TO 252 D PAK packages A minimum of 10uF tantalum capacitor is required at the output to improve the transient response and stability 15 1 2 Features Available in 1 8V 2 5V 2 85V 3 3V 5V and Adjustable Versions Space Saving SOT 223 Package Current Limiting and Thermal Protection Output Current 800mA Line Regulation 0 296 Max Load Regulation 0 4 Max Temperature Range LM1117 0 to 125 LM11171 40 to 125 15 1 3 Applications 2 85V Model for SCSI 2 Active Termination Post Regulator for Switching DC DC Converter High Efficiency Linear Regulators 15 32 TFT TV Service Manual 10 01 2005 Battery Charger Battery Powered Instrumentat
72. DRO1 4 Channel 1 Digital 4 Red Output LVDSB 1N Dual LVDS Channel 2 bit 1 Negative Output LV DRO1 7 OUT Channel 1 Digital 7 Red Output DRO1 5 Channel 1 Digital 5 Red Output VSUP3 3LVDS SUPPLY OBL Supply Digital Voltage LVDS 3 3 V DRO1 8 OUT LV Channel 1 Digital Red Output DRO1_6 Channel 1 Digital 6 Red Output LVDSB_oP Dual LVDS Channel 2 bit 0 Positive Output DRO1_9 Channel 1 Digital Red Output MSB DRO1 7 Channel 1 Digital 7 Red Output MSB LVDSB Dual LVDS Channel 2 bit o Negative Output 7 IN OUT RtoGND Port 1 Bit 7 Input Output TDO JTAG Interface Data Output IN OUT RtoSUP Port 1 Bit 6 Input Output TCLK JTAG Interface Clock Input 5 IN OUT RtoGND Port 1 Bit 5 Input Output Pa IN OUT RtoGND Port 1 Bit 4 Input Output GND3 3DAC SUPPLY Ground DAC VSUP3 3DAC SUPPLY o Supply Voltage DAC 3 3V pe aS me EN perm D 1 VCTP Pin No PLOFP 208 1 PWM3 166 PWM2 5 IN OUT RtoGND PWM1 167 168 REV SUPPLY OBL SUPPLY OBL mr DHS w N n N 169 170 171 172 173 174 175 176 177 178 SUPPLY OBL GNDA SUPPLY OBL N 179 180 181 182 183 if LV LV LV LV LV LV LV LV LV LV LV LV LV LV 184 185 186 187 188 189 LV
73. EJ 8 scr 26 33p 100R JP sec sva ac L109 50 R149 2100 e e 5V DRX gt gt AVDD_FEAO SDA 25 1008 Jo sva svs ad R120 85 IN2 ouT2 5 U 3 1 el e 150R SE 10 IFINY RESETQ 24 SHEET 3 5 6 PTRRES 4 3V3 DRX 11 AVSS_FE402 TEST 23 2 A lt 8 4 n i A ia B B A y 2 25 5 42 o H SES lt lt 2 2 7 a arters 4 5 E S103 47 8 Q108 SN RD 5V_DRX gt VAN 82 BC848B 33k L112 g RESET IC IF2 GND 10 gem i is _ 9 E B SHEET3 8 5 d RC 2 C134 9 x x 105 100n g 10V Jacnve E 7 Q u Q103 PTC RES sv DRX z R129 1 5 330R 3k3 sv Tuner v gt 9 R134 2 D FDC642P IR o m g 3 R130 d e 10k e Q104 10k 15 2 R127 BC848B 1 R123 S121 s R137 10 sv_TUNEp gt 10k 4 shortcir 58 100R 169 C117 9 Bosh SHEET 3 ag m R143 hv 3 100n 18 7SR o 10V l TUNER CVBS IN IC101 100n shortcir t Ji 10V al X TUNER De 16 4 SV TUNER S z SCL gt antenna control DVB 14 101 1v1 13 TUNER 2 zi 74HCT4053 3YO 170 12 4 SDA SV IC D100 S102 IN4148 AGC DVB 11 107 FROM 100 to 150 VESTEL ELECTRONICS TV DVB_SWITCH 21 4 17
74. Em mee 4 hore AouraR i 50 50V SPRE i pit 1 i NCTP AOUT2L 1 C249 C252 I o E 4 our R sov 50 LS ar R292 N N do 100R gt a mo gt E 55 E LO HP OUT 29 o5 lt 5 HP ovr gt a 8 lu SC2 AUDIO L OUT LINE R OUT LINE L OUT 25V BC858B Q209 Di 6204 R303 330R VAA 1229 lu gt 25V 8 R 55 9 oo a BE C270 ES 150 S EI 50 E 2 SDA 3V3 IC 4 IRQ p SELECTED_C SCL_3V3_IC SW_ENAB E E 2 2 9 9 B og Ea m m d 4 a 9 5 I 9 Y e 330R o PC AUDIO IN L231 R326 330R gt PC AUDIO L IN 27 1232 3 338 1 R322 R329 le ner IK20 47R e 47R I I JACK RCA 9 YPBPR SPDIF LINIO prev gt wj a D Me Li E RE Te gt rav 1 x LIN R i i d R323 R330 e 476 47R FAV AUDIO IN SPDE LOUT L rel gt xg aller noU vy ne 47R Jav _ s PR i i R324 R331 47R 47R 1 R3 E 33 gt 9 23 ae em Re LA L230 o sv 4 sv FERRITE 58 D228 I D230 JUMPER
75. HDMIO D2N 51 2 24LCO2 470k 1 1 EE AVDD33 71 50 lt 3 e eu 3 131 f R667 HDMI AVSS 9 49 H 4 470k ME AS HDMIO_D1P 48 5 EEI_SDA 133 VD7 J m SWEBNABLE 4 HDMIO DIN 47 616 p 134fDVDD33 7 AVDD33 e 46 7 5 H 135 55 14 AVSS s 45 HA l 8 E E E 136 gt By EAR OE HDMI R7 HDMIO DoP 44 9 7 137 vps HDMI R6 4 20E HDMIO 43 10 E H 138 pvss 15 D EROM 650 to 750 lt J s 42 Qfavooss Jou IM p tisofpvonis SN74CB3Q3305 VESTEL ELECTRONICS _ AMD E20SUP 18 1 IC553 Y Mu E B 17 12 1 HDMI 50113 avss 7 12 55 140 VD4 Date Author R687 _ gs HIDMIO_CLKP 40 47R 2 4 E 4 17 04 2007 ISMAIL ao erg 114 S661 SADIK SE m 142 vp2 s AVDD33 16 38 sC 15 R662 2 3 6 143 e 47k BC848B HDMI RI 4 R3 B 16 R663 lt gt A 470k 4 5 144 EB onm 20 U t 24LCO2 Je P R deus M A 4H 5 223 H v S 2 A o B e SCL a a n d qn A 4 ROT 2 2 2 B E 5 2 5 5 2 gt 5 5 5 5 gt 5 g gt gt _5 1
76. LV LV LV 190 Short Description IN OUT RtoGND Port 1 Bit 3 Input Output Analog Red Output PWM Bit 3 Output Port 1 Bit 2 Input Output Analog Green Output PWM Bit 2 Output Port 1 Bit 1 Input Output Analog Blue Output PWM Bit 1 Output Port 1 Bit 0 Input Output Scan Velocity Modulation Output Digital Video H Sync Input IN OUT RtoGND IN OUT RtoGND VCTP Pin No Type Connection Short Description PLOFP If not used 208 1 m eerie cr TAG VSUP3 3V0 SUPPLY Supply Voltage Analog Video Output 3 3 V GND3 3103 SUPPLY Ground Digital Input Output Port 1 VSUP3 3103 SUPPLY Supply Voltage Input Output Port 1 3 3 V 198 65610 IN OUT RtoGND Digital 656 Bit 0 Input LSB P3_0 Port 3 Bit 0 Input Output 199 65611 IN OUT Digital 656 Bit 1 Input P3 1 Port 3 Bit 1 Input Output 65612 IN OUT RtoGND Digital 656 Bit 2 Input 2 Port 3 Bit 2 Input Output 201 6563 IN OUT RtoGND Digital 656 Bit 3 Input P3 3 Port 3 Bit 3 Input Output 65614 IN OUT Digital 656 Bit 4 Input P3_4 Port 3 Bit4 Input Output 65615 IN OUT RtoGND Digital 656 Bit 5 Input P3_5 Port Bit5 Input Output 65616 IN OUT RtoGND Digital 656 Bit 6 Input P3_6 Port 3 Bit 6 Input Output 65617 IN OUT Digital 656 Bit 7 Input P3 7 Port 3 Bit 7 Input Output me 656CLKO Digital 656 Clock Output LN four iv __ 65607 IN OUT Digital 656 Bit 7 Output P4 7 Port 4 Bit
77. MArchitecture These devices provide nearly all the functionality required to realise a high performance and cost effective digital set top box or integrated digital TV 10 2FEATURES MPEG1 and MPEG2 TS PS compliant High performance MIPS32 4Kc main CPU core High performance MIPS32 4Km sub CPU core Integrated DVB descrambling with family options for Irdeto and Multi2 36 PID filters 32 section filters Video Outputs 4 DACs for RGB Component video S video and composite output with support for PAL NTSC and SECAM 4 graphics planes Audio Output 2 channel PCM and SPDIF e Peripherals support two fast UARTs with 16byte FIFOs 2 interface infrared receiver three wire clocked serial interface e System timers and Watchdog timer Motorola Intel Bus 11 DRX 3973D Fourth Generation COFDM Demodulators 11 1Introduction The DRX 3973D and the DRX 3977D are fourth generation COFDM demodulators that offer today s highest level of front end integration resulting in ultimate DVB T digital reception compliant to ETS 300 744 DTG D Book EICTA E Book and Nordig Unified v1 0 2 The DRX 3973 77D applies cutting edge digital filtering techniques in combination with a high performance A D converter and PLL configuration resulting in superior performance figures in the presence of digitaland analog adjacent channels Progressive channel estimator algorithms provide exceptional performance in multipath and dynamicec
78. MPEG TS output PMQFP64 2 package footprint 10 10 mm DRX 39730 PQFNA8 1 package small footprint 7 7 mm DRX 39770 IEEE 1149 1 boundary scan fe fe fe 11 3Applications IDTV hybrid TV Set top boxes PVR DVDR Network interface modules NIM PC TV applications fe fe 4 fe 12 PI6CX100 27MHz 3 3V VCXO Set Top Box Applications 12 1 Features 3 3V operating voltage Uses an inexpensive external crystal On chip VCXO with pull range of 240ppm VCXO tuning voltage from 0 to 3 3V 10mA output drive at CMOS levels Available in SOIC package fe fe fe 12 2Description The PI6CX100 27 is a low cost high performance 3 3V VCXO designed to replace expensive VCXO modules The on chip Voltage Controlled Crystal Oscillator accepts a 0 to 3 3V input voltage to cause clocks to vary by 120 This device uses an inexpensive external pullable crystal at 27 MHz to produce the same output frequency The 100 27 is designed for Set Top Box applications 13 74V1G08 SINGLE 2 INPUT AND GATE HIGHSPEED 4 3 ns TYP atVCC 5V LOWPOWERDISSIPATION ICC 1 A at TA 225 oC HIGHNOISEIMMUNITY VNIH VNIL 28 VCC MIN POWERDOWN PROTECTIONON INPUTS SYMMETRICAL OUTPUT IMPEDANCE IOL 8 mA MIN
79. NI 84 908 15995 3 O3N gt 1 S8AD 18 265 LOS MS LOS 550 35330030 S849 HINNL H4 VW NIY 29 0 31095 ALGI 18 2Power Management 18 3 DRX IF Demodulator Block Diagram 18 4 VCT Pro 18 4 1 General Block Diagram LL 18 4 2 MSP Block Diagram 5 2 18 4 3 Video Processor of VCT 7wxyP Block Diagram jesay 25 usel4 20 2 OL E Til TVIX OWLE Del ina 1508 ul 1032029 Kiowan soiudeJc saiydessy a Aejdsig ide 9485 m WMd 2 ONUOD NH E NE REESE UN n no ui 894 sa 1 N ut q219A ut SQAD GE Bip va OL 993 gox ut 959 109 u 993 8 5 959 ou s dr 315 8108550013 SOBLISJU uod Sa 41095 3NOHdQV3H 5 5
80. OM R533 R561 VCTP POWER SUPPLIES veo p 1 1 sepa e 32 125 pcs2 118 ver ak7 220R R436 R568 HDMI1_HOTPLUG S430 ws 40 5 ws pcsafii7 gt 1k2 p R497 Ziso VSUP_3V3_COM NC 25 our 54 116 J LED2 R531 R562 sva sre o VSUP 3V3 DAC SHEETS R498 di gt 3k3 220R 42 125 DEL IN PCS5f115 CRANE STBY ON OFF 322 0426 10k BC848B JO sp Jo vsur sv av NC 125 per VSUP3 3IO1 26114 4 VSUP 3V3 IGT VSUP 3V3 3 i NC R514 VSUP 3V3 COM 44 25 DEL WS GND3 3IOI 26113 p 10k 3V3 45 JVSUP3 3RAM 05060 112 VSUP 3V3 R538 V Q428 gt 3k3 BC8A8B o VSUP 3V3 FE gt 46 GND3 3RAM OSDRI 111 R509 LEDI 2 a 10k 4 3V3 S z 2 gt 10 1406 OSDR3 109 m E 1V8 STB mu me An VSUP_IV8_DIG 10k 4 5465 R521 7 OSDGOf08 R510 vSUP 3V3 COM BC848B 4k7 vetpprog 1 2 122 51 ospai 107 R511 VSUP 3V3 COM C497 R547 ES AA i 8500 10k R565 OSDG2 106 47R 10p BC848B Jo cmm R501 50V mm yos los 105 47R TANTAL CASE E 5 n 5 9 4 0 E m cdm MLG A A o TV LINK 3V3 C495 SHEET 5 M 2 2 5 ES amp A d 3 U v 28 SHEET 5 10 x gt c 4 c g 4 BB S Sod 9 5 5 gt A
81. OSDGO IN OUT RtoGND Graphic Green 0 Input Output DGO2 5 Channel 2 Digital 5 Green Output OSDR3 IN OUT RtoGND Graphic Red 3 Input Output MSB P3 1 Port Bit 1 Input Output DGO2 6 Channel 2 Digital 6 Green Output OSDR2 IN OUT RtoGND Graphic Red 2 Input Output P3 0 Port 3 Bit 0 Input Output DGO2 7 Channel 2 Digital 7 Green Output MSB OSDR1 IN OUT RtoGND Graphic Red 1 Input Output DRO2 0 Channel 2 Digital Red Output LSB VCTP Pin No nection Short Description 208 1 OSDRO IN OUT RtoGND Graphic Red 0 Input Output LSB DRO2 1 Channel 2 Digital 1 Red Output GND33IO1 SUPPLY OBL Ground Digital Input Output Port 1 VSUP3 3101 SUPPLY OBL Supply Voltage Input Output Port 1 3 3 V PCS5 IN OUT RtoGND Panel Control Select 5 Output P2 7 Port 2 Bit 7 Input Output PCS4 IN OUT RtoGND Panel Control Select 4 Output P2 6 Port 2 6 Input Output PCS3 RtoGND Panel Control Select DE2 Output P4 1 Port 4 Bit 1 Input Output PCS2 IN OUT RtoGND Panel Control Select 2 DE1 Output P4 0 Port 4 Bit 0 Input Output PCS1 IN OUT RtoGND Panel Control Select 1 H Output P4 3 Port 4 Bit 3 Input Output PCSO IN OUT RtoGND Panel Control Select V Output P4 2 Port 4 Bit 2 Input Output PCLK2 OUT LV Panel Control Clock 2 Output PCLK1 OUT LV Flat Panel Control Clock 1 Output GND1 8DIG SUPPLY OBL Ground Digital Core VSUP1 8DIG SUPPLY OBL Supply Voltage Digital Cor
82. OUT LVDS Channel 1 bit 2 Positiva Output DBO1 8 Channel 1 Digital 8 Blue Output DBO1 2 Channel 1 Digital 2 Blue Output LVDSA 2N LVDS Channel 1 bit 2 Negative Output DBO1 9 Channel 1 Digital Blue Output MSB DBO1 3 Channel 1 Digital Blue Output GND3 3LVDS SUPPLY OBL Ground Digital LVDS 3 3 DGO1 0 Channel 1 Digital Green Output LSB DBO1 4 Channel 1 Digital 4 Blue Output LVDSA 1P LVDS Channel 1 bit 1 Positive Output DGO1 1 Channel 1 Digital 1 Green Output DBO1 5 LVDSA 1N DGO1 2 Channel 1 Digital 2 Green Output DBO1 6 Channel 1 Digital 6 Blue Output VSUP3 3LVDS SUPPLY OBL Supply Digital Voltage LVDS 3 3 V DGO1 3 Channel 1 Digital 3 Green Output DBO1 7 Channel 1 Digital 7 Blue Output MSB LVDSA LVDS Channel 1 bit 0 Positive Output Channel 1 Digital 5 Blue Output LVDS Channel 1 bit 1 Negative Output DGO1 4 Channel 1 Digital 4 Green Output DGO1 0 Channel 1 Digital o Green Output LSB LVDSA LVDS Channel 1 bit 0 Negative Output DGO1 5 Channel 1 Digital 5 Green Output DGO1 1 Channel 1 Digital 1 Green Output VSUP1 8LVDS SUPPLY OBL Supply Analog Voltage LVDS 1 8 V DGO1 6 Channel 1 Digital 6 Green Output DGO1_2 Channel 1 Digital 2 Green Output REXT LVDS External Resistor DGO1 7 Channel 1 Digital 7 Green Output DGO1 3 Channel 1 Digital 3 Green Output GND1 8LVDS SUPPLY OBL Ground Analog LVDS 1 8 V DGO1 8 DGO1 4 Channel 1 Digital 8 Green Out
83. PPORT33f122 gt 5 GND 3 PPORT32 121 Y GND 4 55 1 1 119 RADDS 18 100R sak R1030 RADD8 RADD9 117 1008 Jo svara R1031 8 18 RADO RADD10 PPORT29 116 4 7K wore RADDII m 5 R1021 AUTEUR MS RADDII 28 115 100R R1022 RADD12 PPORT27 114 RES RADD13 PPORT26f113 E T POWER CNTRL RADDI3 E1023 REDD RADD14 25 12 SR Prec RADDIS R1024 RADD15 PPORT24f 111 33R R1025 VDD3 1 GND 8 110 i 5 ap ss GND 5 VDD3 2 109 5 der PSs ALGER AR e m gt CET 2 20 xb o D m a A b b b amp ee amp amp amp B 808mm A Aq gt amp aa gt 8 Am ee oO BR x xk E xk X X 0040 OK OQ HRA Zz OH k 4242 0206 06 0 06 6 9 9 4 0 lt 6 gt 255 0 2 e le lo e Sl i a fo al le lal mis sS lt 4 21215 191 19 4 9 by 9 9 S S 9 ides dod 16V H 975 977 2
84. SCL 3V3 IC C442 i uwsci SC AUDIO L IN gt 16 10 JAINIL GND3 3LVDS3 147 C450 lu IDTV R 16 11 JAIN2R LvpsB NC R400 Mr lu NC EM e IDTV L p 16 12 amor LVDSB 3Pf145 Q400 C451 sa lu 5 BC848B FAV_AUDIO_R_IND 16 13 JAIN3R GNDI 8LVDS 144 C444 s R413 FAV_AUDIO_L_I 16 14 JAIN3L 143 6k2 0 04 10R C452 S412 DMPORPC AUD 16 15 JAIN4R VSUPI 8LVDS 142 4 1V8 LVDS lt PANEL_VCC 445 4 5410 5413 gt rH u Be 3 82 1 T6V 16 JAIN4L LVDSA ON 141 gt TXOUTO TXOUTO gt 5 9 Som FROM 400 V3 STB SHEET 17 vREFAU VESTEL ELECTRONICS LVDSA oPf140 gt roure sv 18 VSUP8 OAU 17MB12 1 TUNER DRX 30f13 VSUP3 3LVDs3 139 VSUP 3V3 LVDS 422 EN S439 Date Author 423 EXTERNAL AMP 19 GNDA1 LVDSA INf138 gt TXOUTI TXOUTI gt raner vec 3 Sp H 17 04 2007 ISMAIL VIEMAZLAR gt TXOUTI gt D lt 3V3 9 1 10k p E 20 SGND SADIK SEHIT LVDSA_1P 137 _3V2 in kic S425 STBY ON VCTP AOUT2R 21 JAOUT2R GND3 3LVDs2 136 A sv BC848B VCTP AOUT2L 22 JAOUT2L LVDSA 2N 135 gt TXOUT2 TXOUT2 gt 12 2 R546 al 23 JAOUTIR al LVDSA 2 134 TXOUT2 TXOUT2 gt 10k lt VSUP_3V3_COM VSUP 3V3 LVDS R507 AOUTIR 24 JAOUTIL VSUP3 3LVDS2 133 4 10k lt PANEL_VCC
85. TAA uoa lee MEN 36 15144 General eio ocio edem 36 DIS E 36 15 13 Absolute Maximum Ratings 36 37 5 87 NITAEICAUS2 uer 27 15 5 1 General Descrnptiono oe RO RS OF HER TORRE TECHN QURE T 37 Ir MEI PD E 97 15 8 3 Absolute Maximum 37 Bet AEE EE E 38 15 9 coo SOR roi M eta Ee ats EAE 38 1591 General Description e ae D Reuter 38 5 9 2 Features Pee 39 15 9 3 Absolute Maximum 39 15 94 eee eod E aenea 40 DIG beo 40 15 10 1 General etm 40 15 10 2 40 15 10 3 Absolute Maximum 40 15 10 4 icon sess 41 SERVICE MENU SETTINGS 41 VPN 41 62 Maps 42 SLN 42 CMS pL 43 16 5 Service Tuning Setup 44 16 6 External Source ns lest teens esu 44 Mode DS 44 16 8 1 Reset MAII TT 45 17 SOFTWARE UPDATE DESCRIPTION optet ane 45 17 1 Analog Software Update Via 45 17 2 Analog Software Update 46 18 BEOCK DIAGRAMS 46 ed General Bok Diagram
86. a 5 MENS A R689 NAIAS 5655 T 1000 1000 10k 4 HDON 888 B g e 10 16 H sj 10R e Jesu 8 20k 1N4148 72s R657 y Q661 3V3 BESTSE PAN gt BC848B BC848B ux lt POMII Q652 ATO 7392 10k lu 16V R799 R813 VCC_5V_VIDEO gt SHTI DRX R624 A Adpio sw a 52725 C600 R625 no xd BC848B 600R 100MHZ 200 sv VIDEO gt _ cos cos 487 4 SV 1766 10p 100n 100n 3 85 So 50V 50V 50 1 8 5 1 600 HEADPHQNE L C603 C623 ey R603 vin 2avp gt Jv rc 1 22uH 3 94 SMD 100R OUTB Soh P ur our 1 lu 100u 5 1 SMD CAP IC YE YAKIN OLACAK R645 100R 9 5 38558 Iv TDA1308T 16 L T ay 9 HEADPHQNE R R604 R646 1008 amp 1 H S gt 100R INB HP OUT R gm 82 JE 28 58 9 9 55 25 S R647 100R Cei im 1004 ST Sy V A DVDDMP IN R648 100R D 1 475 10 5 VIDEO R809 100k
87. alue between 8 1047 NTSC lt gt Value between 8 10 7 dB Value between 0 t0 8 16 2AudioSetup Equalizer If Yes selected Equalizer item is seen in Sound menu BBE SRS WOW Virtual Dolby Surround lt gt If Yes selected Virtual Dolby Surround feature is seen in Sound menu with selected Virtual Dolby Text Virtual Dolby Text The selected item is seen as Virtual Dolby Srround Text 305 Virtual Dolby 3D Panorama If Yes selected AVL item is seen in Sound menu Carrier Mute If Yes selected Carrier mute feature is active Audio Delay Offset Prescale FM Presc AVL On Value between 0 to 127 Presc AVL On gt Value between 0 to 127 NICAM Presc AVL On gt Value between 0 10 127 I2S Presc AVL On Value between 0 to 127 SCART AVL On gt Value between 0 to 127 FM Presc AVL Off gt Value between 0 to 127 Presc AVL Off lt Value between 0 to 127 NICAM Presc AVL Off Value between 0 to 127 2 Presc AVL Off gt Value between 0 to 127 SCART Presc AVL Off lt Value between 0 to 127 If Yes selected Dynamic Bass item is seen in Sound menu Subwoofer If Yes selected Subwoofer item is seen in Sound menu 16 3Options 1 VCTP Version lt Basic Basic Double Dig
88. are the slicer stores data a buffer of 1 KB The microcontroller firmware performs all the acquisition tasks hamming and parity checks page search and evaluation of header control bits once per field Additionally the firmware can provide high end Teletext features like Packet 26 handling FLOF TOP and list pages The interface to user software is optimized for minimal overhead 5 6 Port Allocation VCTP Pin No Pin Name Type Connection Short Description If not used IN OUT RtoGND Digital 656 Bit 6 Output Port 4 Bit 6 Input Output JTAG Interface Data Output FW Controller IN OUT RtoGND Digital 656 Bit 5 Output Port 4 Bit5 Input Output JTAG Interface Data Input FW Controller IN OUT RtoSUP Digital 656 Bit 3 Output Port 4 Bit 3 Input Output JTAG Interface Clock Input TV Controller IN OUT RtoGND Digital 656 Bit 4 Output Port 4 Bit4 Input Output JTAG Interface Mode Select Input FW Contr IN OUT RtoGND Digital 656 Bit 2 Output Port 4 Bit 2 Input Output JTAG Interface Data Output TV Controller VCTP Pin No PLOFP 65601 P4 1 TDI 65600 P4 0 TMS RESETQ VREFAU ul IN OUT IN OUT Connection If not used VSUP8 0AU SUPPLY OBL AOUT2R AINSR AOUT2L AINSL SPEAKERR SPEAKERL em VREFSIF SIFIN SIFIN Lr IN OUT IN OUT La oor La oor LN ep w CE em er CE GL 5 Kl C CE Es Ea
89. as well as the step down converter switches Drive IN with a 4 75V to 28V power source Bypass IN to GND with a suitably large capacitor to eliminate noise on the input to the IC Pin3 SW Power Switching Output SW is the switching node that supplies power to the output Connect the output LC filter from SW to the output load Note that a capacitor is required from SW to BS to power the high side switch Pin4 GND Ground Pin5 FB Feedback Input FB senses the output voltage to regulate that voltage Drive FB with a resistive voltage divider from the output voltage The feedback threshold is 1 222V Pin6 COMP Compensation Node COMP is used to compensate the regulation control loop Connect a series RC network from COMP to GND to compensate the regulation control loop In some cases an additional capacitor from COMP to GND is required Pin7 EN Enable Input EN is a digital input that turns the regulator on or off Drive EN high to turn on the regulator drive EN low to turn it off An Under Voltage Lockout UVLO function can be implemented by the addition of a resistor divider from VIN to GND For complete low current shutdown its needs to be less than 0 7 For automatic startup leave EN unconnected Pin8 SS Soft Start Control Input SS controls the soft start period Connect a capacitor from SS to GND to set the soft start period A capacitor sets the soft start period to 10ms To disable the soft start feature leave SS uncon
90. ated Half Supply Voltage HVP buffers for reference and SE output capacitance asymmetrical supply Internal logic for pop free power supply on off cycling Low standby current in SLEEP mode for power saving regulations 3 3 Applications Flat TV application Flat panel monitors Multimedia systems Wireless speakers Micro systems 3 4 Pinning Negative digital supply voltage and handle wafer connection heat spreader With an asymmetrical supply the Vasop 15 connected to the system ground With symmetrical supply the Vesnaa is connected to the negative supply INTP 2 j Posiiveaudio putforpowerstage 1 3 _ Negative audio input for power stage1 DIAG Input output to indicate the FAULT mode DIAG has an interna pull up and should left foating when un used ENGAGE 5 Input with internal pull up to switch between MUTE mode and OPERATING mode POWERUP 6 Input to switch between SLEEP mode and mute mode CGND 7 Control ground reference for POWERUP ENGAGE and DIAG This CGND is connected to the system ground OSCREF Input to set the frequency for the intemal osci stor master configuration In slave configuration this pin should be connected to Veo HVPREF 11 Decoup ing of the internal haf supply voltage reference asymmetrical supply Wh 5 i this pin should be connected to the supply g INREF Decoup ing for the reference voltage TEST 43 7 Negative digital supply vol
91. d ESD Latch Up Protection More than 1 Million Erase Write Cycles More than 40 Year Data Retention 7 3 Absolute Maximum Ratings E m Storage Temperature Lead Temperature during Soldering Input or Output range Vec Supply Voltage Electrostatic Discharge Voltage Human Body model 2 7 4 Pinning M24C32 8 CLASS AB STEREO HEADPHONE DRIVER TDA7050 8 1 General Description The TDA7050T is low voltage audio amplifier for small radios with headphones such as watch pen and pocket radios in mono bridge tied load or stereo applications 8 2 Features Limited to battery supply application only typ and 4 V Operates with supply voltage down to 1 6 V No external components required Very low quiescent current Fixed integrated gain of 26 dB floating differential input Flexibility in use mono BTL as well as stereo Small dimension of encapsulation see package design example 8 3 Pinning left channel input right channel input 9 SAW FILTER X6966M 9 1 Features F filter for digital cable TV Plastic package SIP5K 9 2 Pin configuration 1 Input 2 Input ground 3 Chip carrier ground 4 Output 5 Output 9 3 Frequency response 25 35 45 55 B5 75 85 95 105 115 125 f MHz 10 MPEG DECODER pPD61115 10 1 DESCRIPTION The 61115 device is a member of the second generation of multimedia processors based NEC s Enhanced MultiMedia Architecture EM
92. d specific digital and delayed tuner with programmable tuner take over point Fast AGC due to linear structure Adaptive back porch control therefore fast positive modulation AGC No sound traps needed at video output SIF output with standard dependent pre filtering and amplitude controlled output level Optimal sound SNR due to carrier recovery without quadrature distortions FM radio capability without external components and with standard TV tuner Prepared for digital TV DVB C DVB T ATSC 2 bus interface 7 SERIAL 64K 2 EEPROM M24C64WBN6 7 1 General Description M24C64WBNG is 64 Kbit Electrically Erasable PROM These I2C compatible electrically erasable programmable memory EEPROM devices are organized as 8192x8 bits supports 400kHz Protocol I2C uses a two wire serial interface comprising a bi directional data line and a clock line The M24C64WBNG is available the standard 8 pin Vcc WC SDA i2c data SCL i2c clock Vss EO E1 E2 WC pin is critcal pin If WP is high writing is not possible to EEPROM If WP is low writing is possible to EEPROM 7 2 Features Two Wire 2 Serial Interface Supports 400kHz Protocol Single Supply Voltage 4 5 to 5 5V for M24Cxx 2 5 to 5 5V for M24Cxx W 1 8 to 5 5V for 24 e Write Control Input BYTE and PAGE WRITE up to 32 Bytes RANDOM and SEQUENTIAL READ Modes Self Timed Programming Cycle Automatic Address Incrementing Enhance
93. e 1 8 V DBO1 0 OUT Channel 1 Digital Blue Output LSB DRO2 2 Channel 2 Digital 2 Red Output LVDSA 4P LVDS Channel 1 bit 4 Positive Output DBO1 1 OUT Channel 1 Digital 1 Blue Output DRO2 3 Channel 2 Digital Red Output LVDSA_4N LVDS Channel 1 bit 4 Negative Output DBO1_2 OUT Channel 1 Digital 2 Blue Output DRO2 4 Channel 2 Digital 4 Red Output VSUP3 3LVDS SUPPLY OBL Supply Digital Voltage LVDS Port 3 3 V DBO1 3 OUT DRO2 5 L Channel 1 Digital 3 Blue Output Channel 2 Digital 5 Red Output LVDSA 3P LVDS Channel 1 bit 3 Positive Output DBO1 4 OUT DRO2 6 V Channel 1 Digital 4 Blue Output LVDSA 3N 117 5 i 3 21 r r LV V Channel 2 Digital 6 Red Output LVDS Channel 1 bit 3 Negative Output DBO1 5 OUT V Channel 1 Digital 5 Blue Output DRO2 7 Channel 2 Digital 7 Red Output MSB GND3 3LVDS SUPPLY OBL Ground Digital LVDS DBO1 6 OUT V Channel 1 Digital 6 Blue Output DBO1 Channel 1 Digital Blue Output LSB LVDSA CLKP LVDS Channel 1 Clock Positive Outpu VCTP Pin No Type Connection Short Description If not used DBO1 7 OUT LV Channel 1 Digital 7 Blue Output DBO1 1 Channel 1 Digital 1 Blue Output LVDSA CLKN LVDS Channel 1 Clock Negative Output VSUP3 3102 SUPPLY Supply Digital Output Port 2 VSUP3 3LVDS Supply Digital Voltage LVDS 3 3 V GND3 3102 SUPPLY ues Ground Voltage Output Port 2 3 3 V LVDSA 2P
94. e between 63 to 63 lt gt Value between 63 to 63 gt Value between 63 to 63 e e e e e e e e 16 8 Reset TV Set Initialize NVM from ROM Press green button to reset the NVM from ROM 17 SOFTWARE UPDATE DESCRIPTION 17 1Analog Software Update Via Step 1 Short the second and third pins of PL 402 Power ON and keep shorting the pins 3 5 seconds Step 2 Then connect the update tool to parallel port of PC Step 3 Connect the other end of the tool to PL 402 Step 4 Run Cosima VCTP Visual software update program Step 5 When you click to box near 0 at Bootloader Version item you will see 42 If you couldn t see 42 or a No Acknowledge from Slave is appeared There may be a connection problem sourced from PC port or update tool Or you may forget to power ON Step 6 After 42 is seen Click Erase Flash Step 7 Select the bin file from near the Load Bin Step 8 Click Load Bin and load the required bin file Step 9 Unpick the IC cable from Chasis Step 10 Power off and on again TV set to produce hard reset Step 11 Initialize the NVM from Reset TV set item from service menu 17 2 Analog Software Update Via UART Step 1 Connect the serial cable from PC Com port to PL104 connector on 17PRGO1 1 module card Step 2 Connect the programming cable from SCART PL103 17PRGO01 1 module card to SCART1 connector on TV
95. es 1 MILLION ERASE WRITE CYCLES 40 YEARS DATA RETENTION 2 5V to 5 5V SINGLE SUPPLY VOLTAGE 400k Hz COMPATIBILITY OVER the FULL RANGE of SUPPLY VOLTAGE TWO WIRE SERIAL INTERFACE I2C BUS COMPATIBLE PAGE WRITE up to 8 BYTES BYTE RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD LATCH UP PERFORMANCES 15 10 3 Absolute Maximum Ratings Lead Temperature Soldering 508 package 40 sec 215 PSDIP8 package 10sec 260 Vio Input or Output Voltages 0 3 to 6 5 Supply Voltage 0 3 106 5 ES Electrostatic Discharge Voltage Human Body model 2 40 fv Electrostatic Discharge Voltage Machine model e 500 EA 15 10 4 Pinning SCL SDA ST24LC21 VCLK Seria Data Address Input Output ru Serial Clock ac mode Vss Ground 16 SERVICE MENU SETTINGS Al01483 In order to reach service menu e First Press MENU Then press the remote control code which is 4725 16 1 Video Setup e Panel Select lt MEI 16 9 32 inch 16 9 26 inch SAMSUNG 16 9 32 inch e Picture Mute If Yes selected Picture mute feature is active Blue Screen lt gt If Yes selected Blue Background item is seen in Feature menu YC Delay lt Tuner PAL Value between 8 10 7 Ext PAL Value between 8 10 7 SECAM V
96. gulator Power PC Supplies Powering VGA amp Sound Card 15 2 4 Absolute Maximum Ratings Supply Voltage Operating Junction Temperature Range Storage Temperature Range Thermal Resistance Junction to Case 263 Thermal Resistance Junction to Ambient 70 263 Lead Temperature Soldering 10 sec Maximum Output Current 15 2 5 Pinning SOT 223 PKG FRONT VIEW TO 263 D2 PKG FRONT VIEW PIN FUNCTION Adj Gnd Vout vin 15 3 1593 15 3 1 General Description The MP1593 is a step down regulator with an internal Power MOSFET It achieves 3A continuous output current over a wide input supply range with excellent load and line regulation Current mode operation provides fast transient response and eases loop stabilization Fault condition protection includes cycle by cycle current limiting and thermal shutdown Adjustable soft start reduces the stress on the input source at turn on In shutdown mode the regulator draws 20 of supply current The MP1593 requires a minimum number of readily available external components to complete a 3A step down DC to DC converter solution 15 3 2 Features 3A Output Current Programmable Soft Start 100mQ Internal Power MOSFET Switch Stable with Low ESR Output Ceramic Capacitors Up to 95 Efficiency 20 Shutdown Mode Fixed 385KHz Frequency Thermal Shutdown Cycle by Cycle Over Current Protection Wide 4 75 to 28V Operating Input Range Output Adjustable from 1 2
97. ho conditions an especially important feature for single frequency networks and indoor reception The state of the art impulsive noise cruncher suppresses interferences originating from sources such as cars electrical motors and household appliances 11 2Features Highest level of front end integration and flexibility Integrated PGA programmable gain amplifier 30 dB Single 8 MHz SAW filter operation 2 AGC control signals available for RF and IF amplifier control Flexible clock reference options Re use of 4 MHz tuner clock reference Pre SAW sense input for optimal RF AGC setting and RF level measurement Excellent digital reception performance Superior digital and analog adjacent channel performance gt 40dB for QEF Impulsive noise cruncher Multipath and dynamic echoes The input IF frequency ranging up to 44 MHz ensures upward compatibility for new tuner topologies Integrated microprocessor to perform autonomous detection and operation of all possible DVB T modes without interaction with the host processor Fully automatic and fast signal acquisition UHF and VHF band scan in 20 seconds Meets all international DVB T receiver specifications Nordig Unified DTG EICTA Comfortable software drivers for integration of tuner and COFDM demodulator Secondary serial interface for tuner control 5 V tolerant AGC and secondary serial protocol outputs 2 general purpose pins GPIO Configurable parallel or serial
98. ice is organized as one block of 256 x 8 bit memory with a 2 wire serial interface Low voltage design permits operation down to 1 8V with standby and active currents of only 1 1 respectively The 24 02 also has a page write capability for up to 8 bytes of data 15 6 2 Features Single supply with operation down to 1 8 Low power CMOS technology 1mA active current typical 1pA standby current typical I temp Organized as 1 block of 256 bytes 1 x 256 x 8 2 wire serial interface bus compatible Schmitt Trigger inputs for noise suppression Output slope control to eliminate ground bounce 100 kHz 24AA02 400 kHz 24LC02B compatibility Self timed write cycle including auto erase Page write buffer for up to 8 bytes 2ms typical write cycle time for page write Hardware write protect for entire memory Can be operated as a serial ROM Factory programming QTP available ESD protection 4 000V 1 000 000 erase write cycles Data retention gt 200 years 8 lead PDIP SOIC TSSOP and MSOP packages 5 lead SOT 23 package Pb free finish available Available for extended temperature ranges Industrial 40 C to 85 C Automotive E 40 C to 125 C 15 6 3 10 6 3 Pinning PDIP SOICITSSOP MSOP 501 23 5 Pins 0 A1 and A2 are not used by the 24XX02 No internal connections 1 1 1 Connected AD 2 2 2 NotComeced
99. ion 15 1 4 Absolute Maximum Ratings Lead Temperature Soldering 5 Seconds Storage Temperature Range Operating Junction Temperature Range 15 1 5 Pinning TO 252 SOT 223 n Vou x Your OUTPUT OUTPUT 4j GN GND ADJ GND 10001938 10001004 10201002 Top View Top View Top View 15 2LM1086 15 2 1 General Description The LM1086 is a low dropout three terminal regulator with 1 5A output current capability The output voltage is adjustable with the use of a resistor divider Dropout is guaranteed at a maximum of 500 mV at maximum output current It s low dropout voltage and fast transient response make it ideal for low voltage microprocessor applications Internal current and thermal limiting provides protection against any overload condition that would create excessive junction temperature 15 2 2 Features Low Dropout Voltage 500mV at 1 5A Output Current Fast Transient Response 0 015 Line Regulation 0 196 Load Regulation Current Limiting and Thermal Protecion Adjustable or Fixed Output Voltage 1 8 2 5 2 85 3 0 3 3 3 45 5 0V Surface Mount Package SOT 223 amp TO 263 D2 Package 100 Thermal Limit Burn in 15 2 3 Applications Battery Charger Adjustable Power Supplies Constant Current Regulators Portable Instrumentation High Efficiency Linear Power Supplies High Efficiency Green Computer Systems SMPS Post Re
100. it lt gt If Yes selected Double Digit button is active for channel selection TEA6415C Available lt gt If Yes selected video switch IC is active on hardware 642 Available lt gt If Yes selected audio switch IC is active on hardware Power Up Mode lt StandBy If selected TV opens in stand by mode State If selected TV opens in Last State mode TV Open Mode lt gt Source Ist TV Last TV e Select Languages lt gt Yes selected languages are seen as option under the Language item in Feature menu Language Set 1 French Spanish Italian E Danish Finnish Swedish Language Set 2 Greek lt 00000006 Dutch gt Portuguse lt gt Polish gt 000000 0 Language Set 3 Slovenian Romanian Bulgarian lt Croatian Serbian E Hebrew lt First APS lt gt If Yes selected first time TV opens by asking APS APS Volume lt gt value between 0 63 Burn In Mode lt gt If Yes selected TV opens with mode This mode is used in manufacturing APS Test HDMI WP If Yes selected EDID ROM is write protected 16 4 Options 2 e Autostore
101. itor VCC in digital systems and provide a reset signal to the host processor when necessary No external components are required The reset output is driven active within 10 sec of falling through the reset voltage threshold Reset is aintained active for a timeout period which is trimmed by the factory after VCC rises above the reset threshold The MAX810 has an active high RESET output while the MAX809 has an active low RESET output Both devices are available in SOT 23 and SC 70 packages 15 9 2 Features Precision VCC Monitor for 1 5 V 1 8 V 2 5 V 3 0 V 3 3 V and 5 0 V Supplies e Precision Monitoring Voltages from 1 2 V to 4 9 V Available 100 mV Steps Four Guaranteed Minimum Power On Reset Pulse Width Available 1 ms 20 ms 100 ms and 140 ms e RESET Output Guaranteed to VCC 1 0 V e Low Supply Current Compatible with Hot Plug Applications VCC Transient Immunity No External Components e Wide Operating Temperature 40 C to 105 C Pb Free Packages are Available 15 9 3 Absolute Maximum Ratings Symbol Value tng Reset oupa vorge emo 171 Thermal Resistance Junction to Air Note 1 Operating Junction Temperature Range 7809 Storage Temperature Range Lead Temperature Soldering 10 Seconds ESD Protection Human Body Mode HBM Following Specification JESD22 A114 2000 Machine Model MM Following Specification JESD22 A115 2
102. n BF799 799 In a 2 g g ER d EN 5 5 5 4 4 4 6 2 6 6 5 gU NC sov sov 4 E E R105 R108 119 lt o g 2 a gt 5 R115 In R122 e EB 2 a 9 5 22 5105 1 178 H 4 s 45 2 P Q I eu ciis CS 1 Avss Apc TUNER 33 S106 ex als rs NY SHEET 3 28 SR gt DP sync sw2 3 45 5 45 ES 5V DRX 10u 2 JAVDD ADC PORT 32 _ n 7 JANATSTX PORTO 31 o IDTV YPbPr SW R106 ner 100R ANATSTY DVSS CAP E C139 sv cas 8a 1 gt 5 JAVDD DVSS 29 100n 52 ni 10V R107 za zz 52 00 Uu 9 100R 48 z 10V 6 AVSS DVDD f 28 5 100n DRX3960A DER ee 7 AVSS 401 DVDD CAP 27 4 3V3 DRX n R119 C125 R148
103. nected 15 4 FDC642P 15 4 1 General Description This p channel 2 5V specified MOSFET is produced using Fairchild s advanced PowerTrench process that has been especially tailored to minimize on state resistance and yet maintain low gate charge for superior switching performance 15 4 2 Features 20 V Roson 0 065 2 Vog 2 45 OSION G Roson 0 100 Q Vz 2 5 V OSON Fast switching speed Low gate charge 7 2nC typical High performance trench technology for extremely low Roson SuperSOT 6 package small footprint 72 smaller than standard SO 8 low profile 1mm thick 15 4 3 Absolute Maximum Ratings Voss Drain Source Voltage Vess Gate Source Voltage Note 4 lp Drain Current Continuous Drain Current Pulsed Pp Power Dissipation for Single Operation Note 1 Note 15 Tag 15 4 4 Pinning G D 6 D 15 5 ANX9021 The ANX9021 is an advanced multimedia receiver compliant with High Definition Multimedia Interface HDMI Specification 1 1 HDMI is the first transport standard to unify digital video audio and control data overlow cost cables It connects digital television flat panel displays and project systems digitally to multimedia sources DVD players high definition set top boxes digital video tape recorders and personal computers Digital transmission in turn delivers an uncompromising multimedia experience HDMI also includes
104. o Type Connection Short Description PLOFP If not used OSDH IN OUT RtoGND Graphic Horizontal Sync Input Output DBO2 1 Channel 2 Digital 1 Blue Output LEE VSUP3 3101 SUPPLY Supply Voltage Input Output Port 1 3 3 V OSDCLK IN OUT RtoGND Graphic Clock Input Output Channel 2 Digital 2 Blue Output OSDFSW IN OUT RtoGND Graphic Fast Switch Input Output E Channel 2 Digital 3 Blue Output DBO2 3 OSDHCS1 Graphic Half Contrast 1 Input Output P3 6 0802 4 OSDHCS0 P3_7 DBO2_5 OSDB3 P3 5 DBO2 6 OSDB2 _4 DBO2 7 ERE Port 3 6 Input Output Channel 2 Digital 4 Blue Output Graphic Half Contrast 0 Input Output LSB Port 3 Bit 7 Input Output Channel 2 Digital 5 Blue Output Graphic Blue 3 Input Output MSB Port 3 Bit5 Input Output Channel 2 Digital 6 Blue Output Graphic Blue 2 Input Output Port 3 Bit4 Input Output Channel 2 Digital 7 Blue Output MSB OSDB1 IN OUT RtoGND Graphic Blue 1 Input Output DGO2 0 Channel 2 Digital 0 Green Output LSB OSDBo IN OUT RtoGND Graphic Blue 0 Input Output DGO2 1 Channel 2 Digital 1 Green Output OSDG3 IN OUT RtoGND Graphic Green 3 Input Output MSB P3 Port 3 Bit 3 Input Output DGO2 2 Channel 2 Digital 2 Green Output 106 05062 IN OUT RtoGND Graphic Green 2 Input Output P3 2 Port 3 Bit 2 Input Output DGO2 3 Channel 2 Digital 3 Green Output p OSDG1 IN OUT RtoGND Graphic Green 1 Input Output DGO2 4 Channel 2 Digital 4 Green Output
105. put Channel 1 Digital 4 Green Output LVDSB 3P Dual LVDS Channel 2 bit 3 Positive Output DGO1 9 Channel 1 Digital 9 Green Output MSB DGO1 5 LVDSB 3N Channel 1 Digital 5 Green Output Dual LVDS Channel 2 bit 3 Negative Output VCTP Pin No Connection Short Description If not used DRO1 0 OUT LV Channel 1 Digital Red Output LSB DGO1_6 Channel 1 Digital 6 Green Output GND3 3LVDS SUPPLY OBL Ground Digital LVDS 3 3 DRO1 1 OUT LV Channel 1 Digital 1 Red Output DGO1 7 Channel 1 Digital 7 Green Output MSB LVDSBCLKP Dual LVDS Channel 2 Clock Positiva Output GND3 3102 SUPPLY OBL Ground Digital Output Port 2 LVDSBCLKN OUT LV Dual LVDS Channel 2 Clock Negative Output VSUP3 3102 SUPPLY Supply Voltage Output Port 2 3 3 V VSUP3 3LVDS Supply Digital Voltage LVDS 3 3 V DRO1 2 Channel 1 Digital 2 Red Output DRO1 o Channel 1 Digital Red Output LSB LVDSB 2P Dual LVDS Channel 2 bit 2 Positive Output OUT LV DRO1 3 OUT LV Channel 1 Digital Red Output OUT LV gt 3 DRO1 1 Channel 1 Digital 1 Red Output LVDSB 2N Dual LVDS Channel 2 bit 2 Negative Output DRO1 4 Channel 1 Digital 4 Red Output DRO1 2 Channel 1 Digital 2 Red Output GND3 3LVDS SUPPLY OBL Ground Digital LVDS DRO1 5 Channel 1 Digital 5 Red Output DRO1 3 Channel 1 Digital Red Output LVDSB 1P Dual LVDS Channel 2 bit 1 Positive Output DRO1 6 OUT LV Channel 1 Digital 6 Red Output
106. r R645 up ES 5 cng Nl HILL d 1086 1055 ena cae 2 210000 8 R480 o lt 0 R646 BIG NET pc reg N 2 NE Saga en amp Ne 5 81042 BB eig Bujc480 0477 R476 wa L R64 War 82 S UNI S404 On C478 0474 NS 4 mies cen 8 ei DA 5 5 EE Bior 55 65 caso 58 reo ces aani f HARE 5 5 5959 M 5 IC1003 5 R468 C475 56 55 15 5 Gago mE 2 BOB e Dar aN EE Es 467 Sees ee 5407 L 7 EN C1020 HH 1000 mer cole o 5 C876 882429 agg o x Hy O gt R463 C470 ap gn R470 UU 882529 22 g flee 8 1 ses Un FEET LUI R1067 E 28 R469 re Fass NS e E _ 5 Bee e e olo IRL A 11108 1144 Ha cas 550 D PL402 ea 14 5 S 8 47 ER _ C461 r n 8mn 5 o N R457 9 o C465 2 C467 e AN 5 a sez 0 0 2 1 1204 3 18 R455 oojo To 58773 5 e EL IC1200 101201 amp L1201 Nap C459 9456 revs 0 5 PL403 F N ET 9 NN N N lt p pes S ete 5
107. r loudspeaker channel volume bass treble loudness balance spatial effect e g pseudo stereo Micronas AROUND Micronas BASS SRS WOW optional SRS TruSurround XT optional delayline for lipsync function shared memory Virtual Dolby Surround optional 1 12 input for external ATSC DVD decoder 1 12 interface for audio delayline 1 SPDIF output Audio i o switches 4 analog stereo line inputs and 2 analog stereo line outputs configurable 5 analog stereo line inputs and 1 analog stereo line output 1 analog stereo loudspeaker output 1 analog subwoofer output 1 analog stereo headphone output 5 3 Video Features The TVT is a Teletext decoder for decoding World System Teletext data as well as Video Programming System VPS Program Delivery Control PDC and Wide Screen Signalling WSS data used for PALplus transmissions line 23 The device also supports Closed Caption acquisition and decoding The TVT provides an integrated general purpose fully 8051 compatible microcontroller with television specific hardware features The microcontroller has been enhanced to provide powerful features such as memory banking data pointer additional interrupts shared memory access etc The TVT has an internal XRAM of 32 KB and a BOOT ROM of 4 KB For operation the code is fetched from a 16bit FLASH which can be addressed up to 1 MByte The controller with dedicated hardware does most of the internal TTX acquisition processing transfe
108. ration of features in LCD plasma TV and in all classes of double scan CRT TV sets The VCT 7wxyP family is based on approved functional blocks of existing Micronas products for audio and video Each member of the family contains the entire audio video up conversion processing for 4 3 and 16 9 50 60 Hz progressive or 100 120 Hz interlaced stereo TV sets and the control data interface for flat panel displays The integrated microcontroller is supported by a powerful OSD and graphics generator with integrated teletext acquisition 5 1 1 Controller High performance 8 bit microcontroller 8051 compatible Up to 512 kByte in system program Flash WST PDC VPS and WSS acquisition Closed caption and V chip acquisition Up to 10 page on chip teletext memory Up to 1000 pages with internal memory Up to 30 GPIO 5 1 2 Audio Multistandard TV sound demodulation All A2 NICAM standards BTSC SAP with DBX EIA J Baseband sound processing for loudspeaker channel Volume bass treble loudness balance Spatial effect e g pseudo stereo Micronas AROUND Virtual Dolby Surround optional Micronas BASS BBE SRS WOW SRS TruSurround XT Lipsync function 5 1 3 Video CVBS S VHS YCrCb and RGB inputs HDTV YPrPb and RGB inputs ITU656 input Linedoubling with vertical detail enhancement without internal memory State of the art motion adaptive up conversion with internal memory 4H adaptive comb filter for PAL NTSC without
109. rs data to from external memory interface and receives transmits data via I2C bus interface In combination with dedicated hardware the slicer stores data in a VBI buffer of 1 KB The microcontroller firmware performs all the acquisition tasks hamming and parity checks page search and evaluation of header control bits once per field Additionally the firmware can provide high end Teletext features like Packet 26 handling FLOF TOP and list pages The interface to user software is optimized for minimal overhead TVT is realized in deep submicron technology with 1 8 V supply voltage and 3 3 V I O TTL compatible 16 analog video inputs 4xCVBS Y C 3xRGB YCrCb YPrPb Video input switch matrix 3 analog video outputs integrated adder 24 bit RGB H V clk input e g ext decoder or 656 8bit input 656 8bit input output e g for external high end up conversion by FRCA Multi standard color decoder PAL NTSC SECAM including all substandards 2D adaptive comb filter for PAL NTSC with vertical peaking 3D comb filter for PAL NTSC Optional Macrovision compliant multi standard sync processing Trilevel sync slicer for HDTV Macrovision detection High quality soft mixer controlled by Fast Blank alpha blending Fastblank monitor via 2 Noise measurement Letterbox detection auto wide Split screen OSD and video side by side and AV PIP 5 4 Controller Features The TVT is a Teletext decoder for decoding World System
110. t Sz 25 3 PL601 8 oe ae 8 L602 R619 1 PC AUDIO R C804 100MHZ 200mA 22uH 3 94 SMD MUTE 47k 8V AUDIO SHT2 gt 2 8 2 lu L758 m ome 25 at 16V 2 9 PEZ Sz o 2 3 8 gt 2 28 R820 i 8 2 Ik el B 5 9 5 5 9 ol R807 3 cis E 315 X DMPORPC R AUDIO eoa C818 VPA STABI DMP DVD AUDIO L IN lt H 3428186 1 COM Y OUT IN e i E928 28 TDA8932 R808 R819 lu lt Y Ik 100k 16V a VSSA STAB2 EE ceo da 4 4 Y3 COM X OUT IN 13 gt 1 AUDIO 5 E E s 100k 5 1000 R798 M74HC4052 100k Auri SEG pr C805 R825 C815 E i F BC858B Y1 52601 DMP DVD AUDIO R IN Nm i Da R638 Ladd L603 16V 8 16V gS T BC848B 22uH_3 9A_SMD 2 2 g str 0 5 p di g EG 8 4 Rm 3 82 gaa a2 ES 8 1 R826 ga 5 9 9 e 2 4 a HR amp afr aig imm PL602 E Td e E 10k sv gt STI DRX as 5 0760 R833 M PE 10k 5 2
111. tage and handle wafer connection heat spreader Decoup ing of the internal 5 V regulator Hal supp y voltage buffer for the SE capacitor of output 2 asymmetrical supply With a symmetrical supp y this pin should be left floating n c Vasp Negative supp y voltage for tne power stage 2 STAB2 24 Decoupling of the internal 11 V regulator for power stage 2 ing of the internal 11 V reg D age 1 Negative supp y voltage for tne power stage 1 BOOT 28 Bootstrap for the high side driver channel 1 amp amp HVP1 OSCIO EA Oscillator input in the slave configuration or the oscillator output in the master configuraton 32 Negative digital supply voltage and handle wafer connection heat 4 POWER STAGE The DC voltages required at various parts of the chassis and inverters are provided by a main power supply unit and power interface board The main power supply unit is designed for 24V and 12V DC supply Power stage which is on chasis generates 24V HVP2 80072 T2 LINREF TEST LINQN 14 LIN2P Vase 16 DREF 18 20 BOOT2 21 123 for audio amplifier 1 8V and 3 3V stand by voltage and 8V 12V 5V and 3 3Vsupplies for other different parts of the chassis 5 MICROCONTROLLER VCTP 5 1 General Features The VCT 7wxyP is dedicated to high quality FPD and double scan TV sets Modular design and deep submicron technology allow the economic integ

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