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P69xx Series High-Density Logic Analyzer

1. Oooo 0 OO i o m ooo UU T ag ALAS d Ook Mra LLL oye ono F O oe d aR Bad contact Figure 12 Proper dressing of the probe cables 16 P69xx Series High Density Logic Analyzer Probes Instruction Manual Operating Basics Storing the Probe Heads To protect the interface clip it is important to properly store the probe heads when the probes are not in use See Figure 13 Gently slide the probe cover over the probe end and store the probe Protective cover Figure 13 Protecting the probe heads P69xx Series High Density Logic Analyzer Probes Instruction Manual 17 Operating Basics 18 P69xx Series High Density Logic Analyzer Probes Instruction Manual YY 4A ees Reference This section provides reference information for the P69xx Series High Density Probes with D Max probing technology Topics include the following m Designing an interface between the probe and a target system m Board design m Probe footprint dimensions m Probe pinout and channel assignment Designing an Interface Between the Probes and a Target System Once you have determined which probe is required use the following informa tion to design the appropriate connector into your target system board The following topics are in this section m Signal fixturing
2. P6964 High Density Logic Analyzer Probe Optimized for 4X Demultiplexing Labeling and Installation Instructions P6980 High Density Differential Logic Analyzer Probe Labeling and Installation Instructions m P6982 High Density Differential Logic Analyzer Optimized for 2X Demulti plexing Probe Labeling and Installation Instructions P69xx Series High Density Logic Analyzer Probes Instruction Manual 1 Operating Basics P6960 High Density Probe The P6960 Probe is a 34 channel high density connectorless probe with D Max probing technology see Figure 1 The probe consists of one probe head that has 34 channels 32 data and 2 clock qual P6960 Single ended probe Figure 1 P6960 High Density probe with D Max probing technology The following list details the capabilities and qualities of the P6960 Probe Differential or single ended clock and qualification inputs Single ended data inputs cLGA contact eliminates need for built in connector Footprint supports direct signal pass through Supports PCB thickness of 1 27 mm to 6 35 mm 0 050 in to 0 250 in Consists of one independent probe head of 34 channels 32 data and 2 clock quals Narrow 34 channel probe head makes for easier placement and layout 2X mode for example 1 2 demultiplexing uses one half of the probe head 4X mode for example 1 4 demultiplexing uses one quarter of the probe head Color coded keyed attachment 2 5 V to 5 V input operating range
3. 2 0 V to 4 5 V threshold range P69xx Series High Density Logic Analyzer Probes Instruction Manual Operating Basics 300 mV minimum single ended signal amplitude m 150 mV amplitude each side minimum differential signal m Minimal loading of 0 5 pF at 20 kQ to ground m Operation in normal or inverted polarity is acceptable clock only m Any common mode voltage is acceptable so long as the maximum positive voltage does not exceed 5 V and the maximum negative voltage does not exceed 2 5 V clock only NOTE Refer to Figure 20 on page 29 for P6960 probe routing and pinout information P6964 High Density Probe The P6964 Probe is a 34 channel high density connectorless probe with D Max probing technology see Figure 2 The probe consists of one probe head that has 34 channels 32 data and 2 clock qual distributed over 4 module end connec tors Figure 2 P6964 High Density probe with D Max probing technology P69xx Series High Density Logic Analyzer Probes Instruction Manual 3 Operating Basics The following list details the capabilities and qualities of the P6964 Probe Differential or single ended clock and qualification inputs Single ended data inputs cLGA contact eliminates need for built in connector Footprint supports direct signal pass through Supports PCB thickness of 1 27 mm to 6 35 mm 0 050 in to 0 250 in Consists of one independent probe head of 34 channels 32 data and 2 clock quals Narr
4. 53 probe calibration 53 repackaging instructions 55 service strategy 53 Mechanical considerations physical attachment requirements for P69xx Series Probes 30 Mechanical specifications 51 Merged module 21 Module x 0 Online Help viii Online Release Notes viii Ordering parts information 57 P69xx Series High Density Logic Analyzer Probes Instruction Manual 65 Index P P6960 pinout 34 P6964 pinout 37 P6980 pinout 40 P6982 pinout 45 Parts ordering information 57 using the replaceable parts list 57 PCB printed circuit board x Phone number Tektronix xi Probe Troubleshooting DUT connections 14 Probe Heads Handling the interface clips 12 Probes adapter definition of x calibration 53 cleaning the compression footprints 11 connecting probes to the logic analyzer 8 connecting probes to the target system 9 definition of x footprint dimensions 32 head definition of x labels 1 P6960 High Density Probe 2 P6964 High Density Probe 3 P6980 High Density Differential Probe 5 P6982 High Density Differential Probe 6 product description 1 returning 55 storing 55 Probing analog signals 24 Product description P6960 High Density Probe 2 P6964 High Density Probe 3 P6980 High Density Differential Probe 5 P6982 High Density Differential Probe 6 Product support contact information xi Q Qualifiers 20 66 Range recognition 24 Related documentation vii Release Notes online vi
5. Qualifier Inputs QUAL 2 QUAL 3 k oke ovalo quar auAL2 eee a a meo e e o p ay a a Z a a e Z ADS S E O S E o o o e Lele Aea ae Z All clock and qualifier channels are stored The analyzer always stores the logic state of these channels every time it latches data Since clock and qualifier channels are stored in the analyzer memory there is no need to double probe these signals for timing analysis When switching from state to timing analysis modes all of the clock and qualifier signals will be visible This allows you to route signals not needed for clocking to the unused clock and qualifier channels It is a good practice to take advantage of the unused clock and qualifier channels to increase your options for when you will latch data Routing several clocks and strobes in your design to the analyzer clock inputs will provide you with a greater flexibility in the logic analyzer clocking setup menus P69xx Series High Density Logic Analyzer Probes Instruction Manual Reference As an example look at a microprocessor with a master clock data strobe and an address strobe Routing all three of these signals to analyzer clock inputs will enable you to latch data on the processor master clock only when data is strobed or only when address is strobed Some forethought in signal routing can greatly expand the ways in which you can latch and analyze data A microprocessor also provides a good example of signals tha
6. This method pulls the probe mounting posts tightly against the circuit board surface Press down on the carrier ae Keying pin lt 45 Figure 7 Installing the retention posts in the PCB 10 P69xx Series High Density Logic Analyzer Probes Instruction Manual Operating Basics 4 Solder the posts to the PCB See Figure 8 on page 11 The posts can be soldered from the top or bottom of the circuit board but it is best to solder the bottom to avoid the heat sinking effects of the posts on top Remove the carrier Solder the wires ue wy Figure 8 Soldering the retention posts in the PCB 5 Pull off the carrier from the posts NOTE The posts may have a small amount of movement after you solder them to the circuit board This is normal and accounted for in the post design The probe should mate firmly to the board when the two screws are tightened to the mounting posts The screws have a mechanical stop on them to prevent over tightening the probe to the board After a probe has been installed and removed there may be slightly more play in the posts This is also normal and accounted for in the probe design Cleaning the The following procedure is recommended to obtain best performance Compression Footprints N CAUTION To avoid electrical damage always power off your target system before cleaning the compression footprint Prior to connecting the pr
7. 3 ND E2 6 E2 7 ND E3 0 E3 1 GND GND D12 E3 4 D13 N o o N a OQ N Q jw N E3 5 ND E1 7 D17 GND GND D20 E1 3 D2 E1 2 GND GND CK2 CK2 N D26 D27 GND GND D30 2 ND E0 5 OQ iil iil gt w a S il 68 Channel 102 Channel O 34 Channel GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND A25 GND GND GND GND GND D20 Doo coo Doo fazo D31 P69xx Series High Density Logic Analyzer Probes Instruction Manual Reference P6964 Single ended Probe Figure 25 shows the pad assignments pad numbers and signal names for the with D Max probing PCB footprint of the P6964 single ended data differential clock logic analyzer technology probe The P6964 probe has 32 data channels and two clocks for each footprint m Group E3 I Group A1 with CK1 G D16 D17 G D18 D19 G D20 D21 G D22 D23 G D24 D25 G D26 D27 G CK2 CK2 G D28D29 G D30 D31 O B O0QeocoO OO0C SOC SOO 0o00 000000 O O FB MOC COCOSCOCS eOCCSOCOCV FOFOS FOROS FOROR FOROR FMi DO Di G D2 D3 GCKi CKi G D4 D5 G D6 D7 G D8 D9 G D10 D11 G D12 D13 G D14 D15 G L_______ Group C3 with CK3 li Group A3 Figure 25 P6964 single ended PCB footprint pinout detail Table 5 on page 38 lists the channel mapping to a logic analyzer module for a P6964 single ended data differential clock logic analyzer probe P69xx Series High Density Logic Analyzer Probes Instructi
8. Logic Analyzer Probes Instruction Manual Mfr part number 010 6964 10 020 2622 00 200 4893 00 020 2539 00 346 0300 00 003 1890 00 071 1685 XX 071 1528 XX 335 1315 00 Replaceable Parts P6980 replaceable parts list Figure amp index Tektronix Serialno Serial no Mfr Mfr part number part number effective discon d Qty Name amp description code number P6980 STANDARD ACCESSORIES 31 1 010 6980 10 1 P6980 PROBE SET INCLUDES SHEET OF LABELS 80009 010 6980 10 2 020 2622 00 2 COMPONENT KIT CLGA INTERFACE CLIP 1 EA P69XX 80009 020 2622 00 SERIES PROBE SAFETY CONTROLLED 3 200 4893 00 2 COVER PROTECTIVE BLACK VINYL PLASTISOL WITH 80009 200 4893 00 STATIC DISSIPATIVE ADDITIVE 020 2539 00 1 KIT RETENTION P6960 P6980 80009 020 2539 00 346 0300 00 1 STRAP VELCRO ONE WRAP BLACK 0 500W X 8 00L QTY 2 80009 346 0300 00 BAGGED amp LABELED 003 1890 00 1 TOOL HAND USED TO TIGHTEN PROBE HEAD TO DUT 80009 003 1890 00 071 1542 XX 1 MANUAL TECH TRIFOLD INSTALLATION LABELING 80009 071 1542 XX INSTRUCTIONS FOR P6980 071 1528 XX 1 MANUAL TECH INSTRUCTION P69XX SERIES HIGH 80009 071 1528 XX DENSITY LOGIC ANALYZER PROBES 335 1209 00 1 P6980 PROBE SHEET OF LABELS 80009 335 1209 00 Figure 31 P6980 High Density Differential probe accessories P69xx Series High Density Logic Analyzer Probes Instruction Manual 61 Replaceable Parts P6982 replaceable parts list Figure amp index number 32 1 Tektron
9. P69xx Series High Density Logic Analyzer Probes Instruction Manual Preface This document provides information on using and servicing the P69xx Series logic analyzer probes Related Documentation In addition to these probe instructions the following documentation is available for your Tektronix Logic Analyzers The Tektronix Logic Analyzer Family User Manual provides overall user information for the TLA Series Logic Analyzer The TLA700 Series Logic Analyzer Installation Manual provides installation information for the TLA700 Series Logic Analyzer The TLA5000 Series Logic Analyzer Installation Manual provides installa tion information for the TLA5000 Series Logic Analyzer The TLA7Axx TLA7NAx Module Service Manual that provides module level service information for major components of the TLA Series Logic Analyzer The P6434 Mass Termination Probe Instructions provides instructions for using the P6434 Probes with older Tektronix logic analyzers The P6417 amp P6418 Logic Analyzer Probes Instructions provides instruc tions for using the P6417 and P6418 Probes The P6419 Logic Analyzer Probe Instructions provides instructions for using P6419 Probes P6810 General Purpose Logic Analyzer Probe Label Instructions P6860 High Density Logic Analyzer Probe Label Instructions P6864 High Density 4X Logic Analyzer Probe Label Instructions P6880 High Density Differential Logic Analyzer Probe Label Instructions P6960 High Density
10. Traditional layout techniques require vias to be located next to a pad and a signal routed to the pad causing a stub and more PCB board area to be used for the connection Many new digital designs require you to minimize the electrical effects of the logic analyzer probing that you design into the circuit board Using via in pad to route signals to the pads on the circuit board allows you to minimize the stub length of the signals on your board thus providing the smallest intrusion to your signals It also enables you to minimize the board area that is used for the probe footprint and maintain the best electrical performance of your design Figure 23 shows a footprint example where two pads use vias Detail A describes the recommended position of the via with respect to the pad o OFSEOLOLOEOACIOESESIOLOLSESEGESECAOIOESESISLSECIE K See detail A Max via dia 0 25 mm 0 010 in f 0 04 mm Dia 0 51 mm 0 002 in 0 020 in 0 32 mm 0 013 in ae Detail A Scale 50 000 Figure 23 Optional Via in Pad placement recommendation P69xx Series High Density Logic Analyzer Probes Instruction Manual 33 Reference Probe Pinout Definition and Channel Assignment This section contains probe pinout definitions and channel assignment tables for the P69xx Series Probes P6960 Single ended Probe Figure 24 shows the pad assignments pad numbers and signal names for the with D Max probing PCB footprint of the P6960 single ended data differe
11. a P6964 single ended data differential clock logic analyzer probe eeeeeees 38 Table 6 Channel assignment for a P6980 differential clock and data logic analyzer probe to a 136 or 102 channel logic analyzer module 41 Table 7 Channel assignment for a P6980 differential clock and data logic analyzer probe to a 68 or 34 channel logic analyzer module 43 Table 8 Channel assignment for a P6982 differential clock and data logic analyzer probe to a 136 or 102 channel logic analyzer module 46 Table 9 Channel assignment for a P6982 differential clock and data logic analyzer probe to a 68 or 34 channel logic analyzer module 48 Table 10 Mechanical and electrical specifications 51 Table 11 Environmental specifications c cee ee eens 52 P69xx Series High Density Logic Analyzer Probes Instruction Manual Table of Contents List of Figures Figure i Differential input amplitude Figure ii Flying Lead Set Figure iii Probe example Figure 1 P6960 High Density probe with D Max probing technology Figure 2 P6964 High Density probe with D Max probing technology Figure 3 P6980 High Density Differential probe with D Max probing technology Figure 4 P6982 High Density Differential probe with D Max probing technology Figure 5 Connecting the probes to the logic analyzer Figure 6 Replacing the wires on the retention posts Figure 7 Installing the retention posts in the PCB Figure
12. considerations m Signal connections signal names and footprints m Mechanical considerations m Electrical considerations Signal Fixturing This section contains the following information to consider for signal fixturing Considerations oe Clocks and qualifiers m Merged modules and source synchronous clocking Demultiplexing multiplexed buses m 2X and 4X high resolution timing modes Internal 2X and 4X m Probing analog signals m Range recognition P69xx Series High Density Logic Analyzer Probes Instruction Manual 19 Reference Clocks and Qualifiers Every logic analyzer has some special purpose input channels Inputs designated as clocks can cause the analyzer to store data Qualifier channels can be logically ANDed and ORed with clocks to further define when the analyzer should latch data from the system under test Routing the appropriate signals from your design to these inputs ensures that the logic analyzer can acquire data correctly Unused clocks can be used as qualifier signals Depending on the channel width each TLA7Axx and TLA7NAx Series logic analyzer module will have a different set of clock and qualifier channels Table 1 shows the clock and qualifier channels available for each module Table 1 Logic analyzer clock and qualifier availability TLA7Axx TLA7NAx 20 Module TLA7AA1 TLA7AA2 TLA7AA3 TLA7AA4 TLA7AB2 TLA7AB4 TLA7NA1 TLA7NA2 TLA7NA3 TLA7NA4 CLK 0 CLK 1 CLK 2 CLK 3 QUAL 0 QUAL 1 od
13. grounded cLGA contact eliminates need for built in connector m Footprint supports direct signal pass through Supports PCB thickness of 1 27 mm to 6 35 mm 0 050 in to 0 250 in P69xx Series High Density Logic Analyzer Probes Instruction Manual Operating Basics m Consists of one probe head supporting 17 channels m Optimized for 2X mode 1 2 demultiplexing to minimize required board real estate m Color coded keyed attachment m 2 5 V to 5 V input operating range m 2 0 V to 4 5 V threshold range 300 mV minimum single ended signal amplitude 5 V maximum m 150 mV each side minimum differential signal amplitude 2 5 V maximum Minimal loading of 0 5 pF at 20 kQ to ground m Operation in normal or inverted polarity is acceptable m Any common mode voltage is acceptable so long as the maximum positive voltage does not exceed 5 V and the maximum negative voltage does not exceed 2 5 V NOTE Refer to Figure 20 on page 29 for P6982 probe routing and pinout information P69xx Series High Density Logic Analyzer Probes Instruction Manual 7 Operating Basics Connecting the Probes to the Logic Analyzer Refer to Figure 5 and connect the probes to the logic analyzer according to the following steps 1 Identify the beveled edges of the connector inside the module end of the probe 2 Align the beveled edges of the connector to its mating connector on the logic analyzer module and press into place 3 Us
14. name may sometimes appear as incomplete Use the U S Federal Catalog handbook H6 1 for further item name identification This indicates the code of the actual manufacturer of the part This indicates the actual manufacturer s or vendor s part number Abbreviations conform to American National Standard ANSI Y1 1 1972 The table titled Manufacturers Cross Index shows codes names and addresses of manufacturers or vendors of components listed in the parts list Mfr code Manufacturer Address City state zip code 80009 TEKTRONIX INC 14150 SW KARL BRAUN DR BEAVERTON OR 97077 0001 PO BOX 500 58 P69xx Series High Density Logic Analyzer Probes Instruction Manual Replaceable Parts P6960 replaceable parts list Figure amp index Tektronix Serialno Serial no number part number effective discont d Qty Name amp description P6960 STANDARD ACCESSORIES 29 1 010 6960 10 1 P6960 PROBE INCLUDES SHEET OF LABELS 2 020 2622 00 1 COMPONENT KIT CLGA INTERFACE CLIP 1 EA P69XX SERIES PROBE SAFETY CONTROLLED 3 200 4893 00 1 COVER PROTECTIVE BLACK VINYL PLASTISOL WITH STATIC DISSIPATIVE ADDITIVE 020 2539 00 1 KIT RETENTION P6960 P6980 346 0300 00 1 STRAP VELCRO ONE WRAP BLACK 0 500W X 8 00L QTY 2 BAGGED amp LABELED 003 1890 00 1 TOOL HAND USED TO TIGHTEN PROBE HEAD TO DUT 071 1539 XX 1 MANUAL TECH TRIFOLD INSTALLATION LABELING INSTRUCTIONS FOR P6960 071 1528 XX 1 MANUAL TECH INSTRUCTION P69XX SERIES HIGH DE
15. retaining tab and lifting the wire away from the post 2 Place the new wire in the slot side without the tab and then wrap the wire over the tab side until it engages in the slot you will feel or hear a slight click Figure 6 Replacing the wires on the retention posts P69xx Series High Density Logic Analyzer Probes Instruction Manual 9 Operating Basics Installing the Retention Posts To install the retention posts on the PCB do the following 1 On the retention post carrier assembly locate the black retention post the post with the keying pin and align it to the keying pin hole on the PCB See Figure 7 2 Press the retention posts into the holes on the footprint on the PCB NOTE The following two steps bending and soldering the wires to the circuit board are the two most important steps in assuring that the probe retaining posts are correctly mounted Bending the wires before soldering them helps prevent long term cold solder flow 3 Press down on the carrier and bend the post wires out to anchor the posts to the PCB Ensure the assembly is perpendicular to the PCB when bending and soldering the post wires The bend point in the retaining wire should be as close to the circuit board surface as possible Grip the wire with a pair of needle nose pliers about 1 8 inch above the circuit board surface and let the side of the through hole not the pliers act as the fulcrum point for bending the wire
16. to remove loose debris m The connector should be placed onto the board pad array using the bosses or locator pins for alignment Care should be taken to prevent incidental contact with other surfaces or edges in the connector contact array area prior to board placement m Always store the probe head in the protective cover when not in use See Figure 13 on page 17 P69xx Series High Density Logic Analyzer Probes Instruction Manual Operating Basics Connect the Probe Refer to Figure 10 and connect the probes using the following steps 1 Align the black screw on the probe with the black post on the PCB Note Both the screws and retention posts are visually keyed one set is black and one set is silver Figure 10 Connecting the probes to the target system 2 Start both screws in the posts and tighten them evenly to ensure that the probe approaches and mates squarely to the PCB If access is limited use the adjustment tool that came with your probe The probe is completely fastened to the PCB when the screws stop in the posts 3 Verify that all of the channels are functional If any channels appear to be nonfunctional see Troubleshooting Probe Connections to the DUT on page 14 P69xx Series High Density Logic Analyzer Probes Instruction Manual 13 Operating Basics 14 Troubleshooting Probe Connections to the DUT The most obvious symptom of a problem with the mounting post installation is
17. 6 p14 fese Ae oe A27 GND GND GND GND GND 46 P69xx Series High Density Logic Analyzer Probes Instruction Manual Reference Table 8 Channel assignment for a P6982 differential clock and data logic analyzer probe to a 136 or 102 channel logic analyzer module Cont 136 Channel 102 Channel number name Bi B2 oe fez ad Bo B4 GND GND GND GND B5 B6 57 B8 B9 B13 GND GND GND GND B19 GND GND GND GND B20 pn fess o Jas A B22 GND GND GND GND B23 B24 B27 P69xx Series High Density Logic Analyzer Probes Instruction Manual 47 Reference 48 Table 9 lists the channel mapping to a 68 channel or 34 channel logic analyzer module for the P6982 differential data and clock logic analyzer probe Table 9 Channel assignment for a P6982 differential clock and data logic analyzer probe to a 68 or 34 channel logic analyzer module 68 Channel 34 Channel number name A3 GND GND GND A9 GND GND GND Mo 02 64 A12 GND GND GND Ai 3 04 A18 GND GND GND A25 03 64 A27 GND GND GND P69xx Series High Density Logic Analyzer Probes Instruction Manual Reference Table 9 Channel assignment for a P6982 differential clock and data logic analyzer probe to a 68 or 34 channel logic analyzer module Cont 68 Channel 34 Channel number name B1 GND GND GND B5 C23 B6 02 34 B8 C25 B9 02 54 B10 GND GND GND B16 GND GND GND B19 GND GND GND B23 03 5 B24 03 54 B25 GND GND GND B27 c3 74 P69xx Series High Density Logic
18. 7 0 A3 7 0 E3 7 0 CLK 3 CLK 1 Destination channels receiving target system test data TLA7AA4 C2 7 0 C1 7 0 C0 7 0 A0 7 0 D1 7 0 D0 7 0 A2 7 0 D3 7 0 D2 7 0 E2 7 0 E1 7 0 E0 7 0 CLK 2 QUAL 3 QUAL 2 CLK 0 QUAL 1 QUAL 0 TLA7AA3 TLA7AA2 TLA7AA1 TLA7AB4 TLA7AB2 H C2 7 0 A3 7 0 C1 7 0 A2 7 0 C0 7 0 C2 7 0 A0 7 0 A0 7 0 D1 7 0 D1 7 0 D0 7 0 D0 7 0 A2 7 0 D3 7 0 D2 7 0 E2 7 0 E1 7 0 E0 7 0 CLK 2 QUAL 3 QUAL 2 CLK 0 QUAL 1 QUAL 0 When demultiplexing data there is no need to connect the destination channels to the multiplexed bus Data from the source channels are routed to the destination channels internal to the logic analyzer Tables 2 and 3 show the mapping of source channels to destination channels Demultiplexing affects only the main memory for the destination channels This means that the MagniVu memory is filled with data from whatever is connected to the demultiplexing destination channel probe inputs This provides an opportunity to acquire high resolution MagniVu data on a few extra channels Connecting the demultiplexing destination channels to other signals will allow viewing of their activity in the MagniVu memory but not the main memory 2X and 4X High Resolution Timing Modes The 2X high resolution timing mode provides double the normal 500 MHz sample rate on one half of the channels By trading half of the analyzer s channels the remaining channels can be
19. 8 Soldering the retention posts in the PCB Figure 9 Proper handling of the interface clip Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Connecting the probes to the target system Using the flying lead set to connect to the target system Proper dressing of the probe cables 06 Protecting the probe heads ccceevcecees P6960 P6980 and P6982 probe dimensions P6964 probe dimensions cece cece ee ence Retention post dimensions ceeeeeeeeees Keepout area ccc ccc cece cere reece eee eee eens Side by side layout cc cece cece eee e ence End to end layout cc cece cece cece eee eee Signal routing on the target system 00 High Density probe load model e0000 Probe footprint dimensions on the PCB Optional Via in Pad placement recommendation P6960 single ended PCB footprint pinout detail P6964 single ended PCB footprint pinout detail P6980 differential PCB footprint pinout detail P6982 differential PCB footprint pinout detail Replacing the cLGA clip ccc cece eee ee P6960 High Density probe accessories P69xx Series High Density Logic Analyzer Probes Instructi
20. Analyzer Probes Instruction Manual 49 Reference 50 P69xx Series High Density Logic Analyzer Probes Instruction Manual EEE Specifications Mechanical and Electrical Specifications Table 10 lists the mechanical and electrical specifications for the P69xx Series Probes The electrical specifications apply when the probe is connected between a compatible logic analyzer and a target system Refer to the Tektronix Logic Analyzer Family Product Specifications document Tektronix part number 071 1344 xx available on the Tektronix Logic Analyzer Family Product Documentation CD or downloadable from the Tektronix Web site for a complete list of specifications including overall system specifications Table 10 Mechanical and electrical specifications Characteristic P6980 P6982 Threshold accuracy 35 mV 1 of setting 35 mV 1 of setting Input resistance 20 kQ 1 20 kQ 1 Input capacitance 0 5 pF 0 5 pF Minimum digital signal swing 300 mV single ended 150 mV differential each side Maximum nondestructive input signal to probe 15 V 15 V Delay from probe tip to module input connector 7 70 ns 60 ps 7 70 ns 60 ps Probe length 1 8 m 6 ft 1 8 m 6 ft Operating range 5 V to 2 5 V 5 V to 2 5 V NOTE Because the length of the probes are electrically similar they can be interchanged without problems P69xx Series High Density Logic Analyzer Probes Instruction Manual 51 Specifications 52 Table 11 shows the en
21. Do not drag the contacts against a hard edge or corner To maintain a reliable electrical contact keep the probes free of dirt dust and contaminants Remove dirt and dust with a soft brush Avoid brushing or rubbing the c spring contacts For more extensive cleaning use only a damp cloth Never use abrasive cleaners or organic solvents The P69xx Series Probes use replaceable c spring cLGA clips See page 54 for the replacement procedure If a probe failure other than the cLGA clip occurs return the entire probe to your Tektronix service center for repair P69xx Series High Density Logic Analyzer Probes Instruction Manual 53 Maintenance Replacing the cLGA Clip For replacement part number information refer to the Replaceable Parts List beginning on page 57 To replace the clip do the following 1 Gently pull one side of the clip away from the probe head as shown in Figure 28 and then remove the entire clip 2 Align the new clip with the probe head and gently snap it into place 3 Test the probe to confirm that all channels are functional Pull away Rotate out Figure 28 Replacing the cLGA clip 54 P69xx Series High Density Logic Analyzer Probes Instruction Manual Maintenance Legacy Probe and Attachment Support Nexus Technology a Tektronix Partner sells accessories that allow you to use the P6960 probe with legacy attachment connectors as well as utilize the P6960 probe footprint with select P68xx a
22. Instruction Manual Tektronix P69xx Series High Density Logic Analyzer Probes with D Max Probing Technology 071 1528 02 There are no current European directives that ap ply to this product This product provides cable and test lead connections to a test object of elec tronic measuring and test equipment Warning The servicing instructions are for use by qualified personnel only To avoid personal injury do not perform any servicing unless you are qualified to do so Refer to all safety summaries prior to performing service www tektronix com Copyright Tektronix Inc All rights reserved Tektronix products are covered by U S and foreign patents issued and pending Information in this publication supercedes that in all previously published material Specifications and price change privileges reserved Tektronix Inc P O Box 500 Beaverton OR 97077 TEKTRONIX and TEK are registered trademarks of Tektronix Inc Velcro is a registered trademark of Velcro Industries B V cLGA is a registered trademark of InterCon Systems MagniVu iView PatGenVu PowerFlex QuickStart TLAVu KlipChip and D Max are trademarks of Tektronix Inc Warranty 2 Tektronix warrants that this product will be free from defects in materials and workmanship for a period of one 1 year from the date of shipment If any such product proves defective during this warranty period Tektronix at its option either will repair the defective pro
23. Logic Analyzer Probe Labeling and Installation Instructions P6964 High Density Logic Analyzer Probe Optimized for 4X Demultiplexing Labeling and Installation Instructions P6980 High Density Differential Logic Analyzer Probe Labeling and Installation Instructions P69xx Series High Density Logic Analyzer Probes Instruction Manual vii Preface m P6982 High Density Differential Logic Analyzer Probe Optimized for 2X Demultiplexing Labeling and Installation Instructions m The online help provides information about the user interface the TLA700 Programmatic Interface TPI and the TLAScript interface To view the online help select Help Topics from the Help menu The TLAScript online help provides links to related topics in TPI m The online release notes provide last minute product and software informa tion not included in this manual To access the Probe Manual Release Notes click Start gt Programs gt Tektronix Logic Analyzer gt TLA Release Notes m A series of microprocessor support instruction manuals provide operating and service instructions for the individual microprocessor support packages Commonly Used Terms Refer to the following list of commonly used terms throughout the manual cLGA An acronym for compression Land Grid Array a connector that provides an electrical connection between a PCB and the probe input circuitry Compression Footprint A connectorless solderless contact between your PCB and the P69XX Serie
24. NSITY LOGIC ANALYZER PROBES 335 1208 00 1 P6960 PROBE SHEET OF LABELS Figure 29 P6960 High Density probe accessories P69xx Series High Density Logic Analyzer Probes Instruction Manual Mfr code 80009 80009 80009 80009 80009 80009 80009 80009 80009 Mfr part number 010 6960 10 020 2622 00 200 4893 00 020 2539 00 346 0300 00 003 1890 00 071 1539 XX 071 1528 XX 335 1208 00 59 Replaceable Parts P6964 replaceable parts list Figure amp index number 30 1 Tektronix Serialno Serial no part number effective discont d 010 6964 10 020 2622 00 200 4893 00 020 2539 00 346 0300 00 003 1890 00 071 1685 XX 071 1528 XX 335 1315 00 Mfr Qty Name amp description code P6964 STANDARD ACCESSORIES 1 P6964 PROBE INCLUDES SHEET OF LABELS 80009 1 COMPONENT KIT CLGA INTERFACE CLIP 1 EA P69XX 80009 SERIES PROBE SAFETY CONTROLLED 1 COVER PROTECTIVE BLACK VINYL PLASTISOL WITH 80009 STATIC DISSIPATIVE ADDITIVE 1 KIT RETENTION P69XX SERIES 80009 1 STRAP VELCRO ONE WRAP BLACK 0 500W X 8 00L QTY 2 80009 BAGGED amp LABELED 1 TOOL HAND USED TO TIGHTEN PROBE HEAD TO DUT 80009 1 MANUAL TECH TRIFOLD INSTALLATION LABELING 80009 INSTRUCTIONS FOR P6964 1 MANUAL TECH INSTRUCTION P69XX SERIES HIGH 80009 DENSITY LOGIC ANALYZER PROBES 1 P6964 PROBE SHEET OF LABELS 80009 Figure 30 P6964 High Density probe accessories 60 P69xx Series High Density
25. O OO C0000 oO O OOOOOVO VO OOOO OVO ON OOO000 0000 Figure 18 Side by side layout Figure 19 shows the dimensions for an end to end footprint layout 34 04 mm 34 04 mm or po t 1 340 in 1 340 in 4 70 mm O OOOOOO0O000000000000000000000 OOOOOO0O00O0000000000000000000 0 185 in OOOOOOQOOQOOOQOQOQOQOOQQQO0000000000 OOOOOOQOOQOOOQOQOQOQOOQQQO00QO00000000 i 0O0Q Q Figure 19 End to end layout 28 P69xx Series High Density Logic Analyzer Probes Instruction Manual Reference Signal Routing Figure 20 shows examples of pass through signal routing for a single ended data configuration and a differential data configuration O O Ground az Signal pads OCPOCOOOCGOOCOOCOO 0000000000 OCPOCOCOOO FoOOOO000 0000000000 eiren oOdoOooooo0ooPoooo0oo0o000000000000 OPFOOCOOOO POOOCOOCOO0OCOO C0000 ore eo Ground g Signal pads Single ended pinout Differential pinout Figure 20 Signal routing on the target system Mechanical This section provides information on compression footprint requirements and Considerations physical attachment requirements The PCB holes in general do not have an impact upon the integrity of your signals when the signals routed around the holes have the corresponding return current plane immediately below the signal trace for the entire signal path from driver to receiver NOTE For optimum signal integri
26. R KIT BAG OF 20 KLIPCHIP ADAPTER 40 TOTAL 80009 SMG50 Se OS A Figure 33 Optional accessories P69xx Series High Density Logic Analyzer Probes Instruction Manual 63 Replaceable Parts 64 P69xx Series High Density Logic Analyzer Probes Instruction Manual Index A Attaching Probe Labels 1 Adapters definition of x C Calibration probe 53 Cleaning compression footprints 11 inspection and 53 cLGA viii cLGA Interface Clip handling 12 replacing 54 Clocking Source Synchronous 21 Clocks 20 Commonly used terms viii Compression footprint viii 11 Connecting probes to logic analyzer 8 probes to target system 9 Contacting Tektronix xi D Designing an interface 19 electrical considerations 30 mechanical considerations 29 Differential input amplitude definition viii Documentation related vii E Electrical considerations P69xx Series Probes load model 31 Transmission lines 30 Electrical specifications 51 F Flying Lead Set ix Functional check x 53 H Help Online viii High Density Differential Probe P6980 5 High Density Differential Probe P6982 6 High Density Probe P6960 2 High Density Probe P6964 3 High resolution timing modes 23 Inspection and cleaning 53 Installing retention posts 10 K Keepout area x 27 L Load model P69xx Series Probes 31 Logic analyzer connecting probes 8 Maintenance 53 functional check 53 inspection and cleaning
27. al number Instrument modification number if applicable If you order a part that has been replaced with a different or improved part your local Tektronix field office or representative will contact you concerning any change in part number Using the Replaceable Parts List Replaceable Parts The P69xx Series Probes contain only the cLGA clip as a replaceable part If probe failure occurs return the entire probe to your Tektronix service representa tive for repair P69xx Series High Density Logic Analyzer Probes Instruction Manual 57 Replaceable Parts Parts list column descriptions Column Column name 1 Figure amp index number 2 Tektronix part number 3and4 Serial number 5 Qty 6 Name amp description 7 Mfr code 8 Mfr part number Abbreviations Mfr Code to Manufacturer Cross Index Manufacturers cross index Refer to the following list for replaceable items Description Items in this section reference figure and index numbers to the exploded view illustrations that follow Use this part number when ordering replacement parts from Tektronix Column three indicates the serial number at which the part was first effective Column four indicates the serial number at which the part was discontinued No entries indicates the part is good for all serial numbers This indicates the quantity of parts used An item name is separated from the description by a colon Because of space limitations an item
28. analyzer module Cont 68 Channel 34 Channel number name A27 enD GND GND GND__ GND __ __ _ B3 D1 A2 1 B20 pr fus for fes A3 3 B21 A3 3 B23 A3 5 B24 A3 5 B27 A3 T 44 P69xx Series High Density Logic Analyzer Probes Instruction Manual Reference P6982 Differential Probe Figure 27 shows the pad assignments pad numbers and signal names for the with D Max probing PCB footprint of the P6982 differential data and clock logic analyzer probe The technology P6982 probe has 16 data channels and one clock or qualifier for each footprint G Di Di G D3 D3 G D5 D5 G D7 D7 G CK CK G D9 D9 G D11 D11 G D13 D13 G D15 D15 O a oe T a ee ee NOCOCOOO0OO0OGCO0O000000000000 0000 0O00 ON O DoDo G D2 D2 G D4 D4 G D6 D6 G NC NC G D8 D8 G D10 D10 G D12 D12 G D14 D14 G O Figure 27 P6982 differential PCB footprint pinout detail Table 8 on page 46 lists the channel mapping to a 136 channel or 102 channel logic analyzer module for the P6982 differential data and clock logic analyzer probe P69xx Series High Density Logic Analyzer Probes Instruction Manual 45 Reference Table 8 Channel assignment for a P6982 differential clock and data logic analyzer probe to a 136 or 102 channel logic analyzer module 136 Channel 102 Channel number name A3 GND GND GND GND GND Ato C264 A12 GND GND GND GND GND M16 03 0 A17 p8 eso AOA ao A18 GND GND GND GND GND A21 GND GND GND GND GND A25 C3 6 12
29. duct Do not apply a potential to any terminal including the common terminal that exceeds the maximum rating of that terminal Avoid Exposed Circuitry Do not touch exposed connections and components when power is present Do Not Operate With Suspected Failures If you suspect there is damage to this product have it inspected by qualified service personnel Do Not Operate in Wet Damp Conditions Do Not Operate in an Explosive Atmosphere Keep Product Surfaces Clean and Dry Provide Proper Ventilation Refer to the manual s instructions for details on installing the product so it has proper ventilation P69xx Series High Density Logic Analyzer Probes Instruction Manual v General Safety Summary vi Symbols and Terms A A Terms in this Manual These terms may appear in this manual WARNING Warning statements identify conditions or practices that could result in injury or loss of life CAUTION Caution statements identify conditions or practices that could result in damage to this product or other property Terms on the Product These terms may appear on the product DANGER indicates an injury hazard immediately accessible as you read the marking WARNING indicates an injury hazard not immediately accessible as you read the marking CAUTION indicates a hazard to property including the product Symbols on the Product The following symbol may appear on the product A CAUTION Refer to Manual
30. duct without charge for parts and labor or will provide a replacement in exchange for the defective product Parts modules and replacement products used by Tektronix for warranty work may be new or reconditioned to like new performance All replaced parts modules and products become the property of Tektronix In order to obtain service under this warranty Customer must notify Tektronix of the defect before the expiration of the warranty period and make suitable arrangements for the performance of service Customer shall be responsible for packaging and shipping the defective product to the service center designated by Tektronix with shipping charges prepaid Tektronix shall pay for the return of the product to Customer if the shipment is to a location within the country in which the Tektronix service center is located Customer shall be responsible for paying all shipping charges duties taxes and any other charges for products returned to any other locations This warranty shall not apply to any defect failure or damage caused by improper use or improper or inadequate maintenance and care Tektronix shall not be obligated to furnish service under this warranty a to repair damage resulting from attempts by personnel other than Tektronix representatives to install repair or service the product b to repair damage resulting from improper use or connection to incompatible equipment c to repair any damage or malfunction caused by the use of non Tekt
31. e care to evenly tighten both screws on the module end of the probe until they are snug First slightly tighten both screws then snug each screw to 4 in lbs max NOTE All P69xx series Logic Analyzer probes can be connected to the logic analyzer when it is powered on In addition all P69xx series Logic Analyzer probes connect to the logic analyzer in exactly the same manner X xfuepya PA 2 JEJ Match color coded labels Figure 5 Connecting the probes to the logic analyzer 8 P69xx Series High Density Logic Analyzer Probes Instruction Manual Operating Basics Connecting the Probes to the Target System You can connect the P69xx Series Probes to the target system without turning off the power to the target system The target system must have the probe retention posts installed if your system does not have the posts see the procedure below Using the Correct Retention Post Wires If the PCB is lt 120 in thick use the wire that comes preattached to the posts If the PCB is gt 120 in thick use the longer wire that is included with the posts The longer wires are embedded in the protective foam of the retention post kit Make sure that you use the longer wires included in the kit when the PCB is gt 120 in thick To install the longer wires on the retention posts refer to Figure 6 and do the following 1 Remove the old wire by pulling the side of the wire over the
32. e the required five clock inputs By merging two 102 channel modules into a set you can obtain the needed number of clock inputs Route the address bus to one module in the set and route the data bus along with its four source synchronous clocks to the second module in the set Demultiplexing Multiplexed Buses TLA7Axx modules support both 2X and 4X demultiplexing TLA7NAx modules support 2X demultiplexing Each signal on a dual or quad multiplexed bus can be demultiplexed into its own logic analyzer channel See Tables 2 and 3 to determine the correct channel groups to use Table 2 2X Demultiplexing source to destination channel assignments Source connecting channel groups A3 7 0 A2 7 0 A1 7 0 A0 7 0 C3 7 0 C2 7 0 E3 7 0 E2 7 0 CLK 0 CLK 1 CLK 2 CLK 3 22 Destination channels receiving target system test data TLA7AA4 TLA7NA4 D3 7 0 D2 7 0 D1 7 0 DO 7 0 C1 7 0 C0 7 0 E1 7 0 E0 7 0 QUAL QUAL 0 QUAL 3 QUAL 2 TLA7AA3 TLA7AA2 TLA7AA1 TLA7NA3 TLA7NA2 TLA7NA1 TLA7AB4 TLA7AB2 D3 7 0 C3 7 0 C3 7 0 D3 7 0 C3 7 0 D2 7 0 C2 7 0 C2 7 0 D2 7 0 C2 7 0 D1 7 0 D1 7 0 D1 7 0 D1 7 0 D0 7 0 D0 7 0 D0 7 0 D0 7 0 C1 7 0 C1 7 0 C0 7 0 C0 7 0 E1 7 0 E0 7 0 QUAL 1 QUAL QUAL 0 QUAL 0 QUAL 3 QUAL 2 P69xx Series High Density Logic Analyzer Probes Instruction Manual Reference Table 3 4X Demultiplexing source to destination channel assignments Source connecting channel groups C3 7 0 A1
33. ferential Probe 00 0000 6 Connecting the Probes to the Logic Analyzer 00 0 0 00 ee eee 8 Connecting the Probes to the Target System 0 00 00 eee eee 9 Connecting the Flying Lead set 0 eee eee ee cee eee 15 Dressing the Probe Cables 0 0 cece eee eee een eee 16 Storing the Probe Heads 0 cece eee ce eee eee 17 References oes Sade rhe ie Gri ar se a dota lari fara ebro tetas or axed weve 19 Designing an Interface Between the Probes and a Target System 19 Signal Fixturing Considerations 00 0 cee cece eee eee eee 19 Board DESTE ua ci ob ate tol a Vea Mest Ne ee taupe nae aaa E ances Shave det nan 25 Prob DIMENSIONS ane aea keyi accra Ag asa apie Meath us pea viata E ane au 25 Retention Post Dimensions and Keepout 00 00 eee eee 27 Side by side and End to end Layout Dimensions 28 Sonal Routine 5 AF Sead atte esata shou inside oats sieeve aol tncn Raven vue 29 Mechanical Considerations 0 0 cece eee eee eee ee eee 29 Electrical Considerations ie ci Ang ote Maia eat eigenen aan vd 30 Probe Footprint Dimensions srr i en 00 eee eee eee eee eens 32 Other Design Considerations 00 00 EE E AE a eee nee ee 33 MAAS IMP as ar sabes tect ncaa ett Aa aE tee o a aay oaths ea ieee een sae 33 Probe Pinout Definition and Channel Assignment 2 04 34 P6960 Single ended Probe with D Max probing techno
34. ier probing Signals such as A D Converter inputs D A Converter outputs low voltage power supplies termination voltages and oscillator outputs are just a few examples Routing these signals to unused logic analyzer inputs provides a quick method of viewing their activity without ever picking up an oscilloscope probe Care must be taken to ensure that such signals are voltage limited and will not exceed the maximum nondestructive input voltage for the logic analyzer probes of 15 Vpeak Range Recognition When using range recognizers the probe groups and probe channels must be in hardware order Probe groups must be used from the most significant probe group to the least significant probe group based on the following order C3 C2 C1 C0 E3 E2 E1 E0 A3 A2 D3 D2 A1 A0 D1 DO Q3 Q2 Q1 Q0 CK3 CK2 CK1 CKO Probe channels must be from the most significant channel to the least significant channel based on the following order 76543210 The above examples assumes a 136 channel LA module The missing channels in LA modules with fewer than 136 channels are ignored With merged modules range recognition extends across the first three modules the master module contains the most significant channels P69xx Series High Density Logic Analyzer Probes Instruction Manual Reference Board Design Probe Dimensions 32 56 mm This section provides information that helps you design your PCB mechanically and electrically for use with the P69xx Ser
35. ies Probes Figure 14 shows the probe dimensions for the P6960 P6980 and P6982 probes Figure 15 on page 26 shows the probe dimensions for the P6964 probe 1 282 in P6960 y 182 88 mm 60 19 mm 72 00 in 2 37 in M 182 88 mm 60 19 mm 32 56 mm 1 282 in 7 f P6980 72 00 in 2 37 in 182 88 mm 60 19 mm 32 56 mm 1 282 in 7 f P6982 E 4 60 mm 0 181 in J 72 00 in 2 37 in Figure 14 P6960 P6980 and P6982 probe dimensions P69xx Series High Density Logic Analyzer Probes Instruction Manual 25 Reference 32 56 mm 182 88 mm 60 19 mm 1 282 in 72 00 in 2 37 in za A 4 60 mm 0 181 in il t Figure 15 P6964 probe dimensions 26 P69xx Series High Density Logic Analyzer Probes Instruction Manual Reference Retention Post The probes are attached to the PC board using two retention posts which ensures Dimensions and Keepout a reliable electrical and mechanical connection to your design p
36. ii Repackaging instructions 55 Replacing the cLGA interface clip 54 Requirements physical attachment for the P69xx Series Probes 30 Retention post wires using the correct retention post wires 9 Retention posts 10 installing retention posts 10 Returning probes 55 S Service strategy 53 Service support contact information xi Signal connections 19 Signal fixturing 19 SMT KlipChip x Specifications electrical 51 environmental 52 mechanical 51 Storing probes 17 55 T Target system connecting probes 9 Technical support contact information xi Tektronix contacting xi Terms commonly used viii Timing modes High resolution 23 Transmission Lines 30 Troubleshooting Probe DUT connections 14 U URL Tektronix xi Using the correct retention post wires 9 W Web site address Tektronix xi P69xx Series High Density Logic Analyzer Probes Instruction Manual
37. in to pad alignment and holds the probe securely to the board Board thicknesses that are supported include 1 27 mm 0 050 in to 6 35 mm 0 250 in Figure 16 shows the dimensions of the retention posts CAUTION To avoid solder creep bend the post wires out after you insert the posts in the board and then solder the post wires You can solder the retention wires from the top or bottom of the circuit board 4 57 mm 33 83 mm 0 180 in 1 322 in 10 92 mm 0 430 in ee i N Retention a post wires Figure 16 Retention post dimensions Figure 17 shows the keep out area required for the retention posts Vias must be placed outside of the keepout area Any traces routed on the top layer of the board must stay outside of the keepout area Traces may be routed on inner layers of the board through the keepout area e gt 3 51 mm 3 40 mm e 0 138 in 0 134 in O OOO OO OOO OOOO OOO OO OO CO 0O000 O OOD OOOO OOD OO OOO OO O00 OO OO000 O i Keepout area ee Figure 17 Keepout area P69xx Series High Density Logic Analyzer Probes Instruction Manual 27 Reference Side by side and Figure 18 shows the dimensions for side by side footprint layout End to end Layout Dimensions 34 04 mm 1 340 in i O OOOOOOOO0OOOQOOQO0OOQO0OQ00000000000 9 40 mm OOOOOOQOOQOOQOQOQOQOOQQ0QO0000000000 Q 0 370 in 2 OOOOOOOO OOOO O OO OC O
38. ix Serialno Serial no part number effective discon d 010 6982 10 020 2622 00 200 4893 00 020 2539 00 346 0300 00 003 1890 00 071 1684 XX 071 1528 XX 335 1313 00 Mfr Qty Name amp description code P6982 STANDARD ACCESSORIES 1 P6982 PROBE SET INCLUDES SHEET OF LABELS 80009 1 COMPONENT KIT CLGA INTERFACE CLIP 1 EA P69XX 80009 SERIES PROBE SAFETY CONTROLLED 1 COVER PROTECTIVE BLACK VINYL PLASTISOL WITH 80009 STATIC DISSIPATIVE ADDITIVE 1 KIT RETENTION P69XX SERIES 80009 1 STRAP VELCRO ONE WRAP BLACK 0 500W X 8 00L QTY 2 80009 BAGGED amp LABELED 1 TOOL HAND USED TO TIGHTEN PROBE HEAD TO DUT 80009 1 MANUAL TECH TRIFOLD INSTALLATION LABELING 80009 INSTRUCTIONS FOR P6982 1 MANUAL TECH INSTRUCTION P69XX SERIES HIGH 80009 DENSITY LOGIC ANALYZER PROBES 1 P6982 PROBE SHEET OF LABELS 80009 Figure 32 P6982 High Density Differential probe accessories 62 P69xx Series High Density Logic Analyzer Probes Instruction Manual Mfr part number 010 6982 10 020 2622 00 200 4893 00 020 2539 00 346 0300 00 003 1890 00 071 1684 XX 071 1528 XX 335 1313 00 Replaceable Parts P69xx Series Probes optional accessories Figure amp index Tektronix Serialno Serial no Mfr Mfr part number part number effective discon d Qty Name amp description code number P69XX SERIES PROBES OPTIONAL ACCESSORIES 33 1 196 3494 00 1 P69xx FLYING LEADSET 80009 196 3494 00 2 SMG50 1 ADAPTE
39. logy 34 P6964 Single ended Probe with D Max probing technology 37 P6980 Differential Probe with D Max probing technology 40 P6982 Differential Probe with D Max probing technology 45 Specifications sisses sossa ES ee ieee 6G os Sa SEs ek eS 51 Mechanical and Electrical Specifications 0 0 0 cee eee eee eee 51 Maintenance eisena a a a E a a 53 Probe Calibration ei erori n ea E AN pean eet EE bt 53 Functional Check moyso smeT raae a an gee eG ENE O E EEAS 53 Inspection and Cleaning e ear aea nE e E ee ohana EEES 53 SELVICE Strate Eyo dens e e a E T E Am ato E E NE A E E aby 53 Legacy Probe and Attachment Support 2 0 0 cece eee eee eee 55 Repackaging Instructions sro noriega eroe cece eee eens 55 Replaceable Parts 0 ccc ccc cece cee cree cere eee e neces 57 TIVO soars E See wa EE TE E rs atute E A TEE E 65 P69xx Series High Density Logic Analyzer Probes Instruction Manual i Table of Contents List of Tables Table 1 Logic analyzer clock and qualifier availability 20 Table 2 2X Demultiplexing source to destination channel assignments ccc cece ccc c cece cece cece cece 22 Table 3 4X Demultiplexing source to destination channel assignments cc cece cece cece cece eee eeeees 23 Table 4 Channel assignment for a P6960 single ended data differential clock logic analyzer probe 0eeeeees 35 Table 5 Channel assignment for
40. lude immersion gold immersion silver and hot air solder level NOTE Tektronix recommends using immersion gold surface finish for best performance Tektronix also recommends that the probe attachment holes float or remain unconnected to a ground plane This prevents overheating the ground plane and promotes quicker soldering of the retention posts to your PCB The probe retention posts are designed to allow you to solder the retention posts from either side of your PCB 34 04 mm al ean 1 340 in 0 033 in 31 95 mm Nonplated thru hole lt 1 258 in g L 26 mm sl 1 72 mm 1 024 in 0 068 in 4x dia 0 71 mm 2 35 mm 1 mm typical 0 028 in 0 0925 in 0 053937 in Plated thru hole 47mm y y 7 FO OOO OOO OOOO OOO CO OOOO OO0CO0 O 0 185 in A a ee ee E 1 72 mm etm 0 0881 0 025 in t 0 58 mm 4X dia 122mm 961m 1 04mm gt lt 0 023 in 0 048 in 0 041 in 9 71 mm Annular ring 0 028 in 298mm 0 117 in Figure 22 Probe footprint dimensions on the PCB 32 NOTE You must maintain a solder mask web between the pads when traces are routed between pads on the same layer The solder mask must not encroach onto the pads within the pad dimensions shown in Figure 17 on page 27 P69xx Series High Density Logic Analyzer Probes Instruction Manual Reference Other Design Considerations Via in pad
41. merica After office hours please leave a voice mail message Outside North America contact a Tektronix sales office or distributor see the Tektronix web site for a list of offices P69xx Series High Density Logic Analyzer Probes Instruction Manual xi Preface xii P69xx Series High Density Logic Analyzer Probes Instruction Manual SEE a Operating Basics This section provides a brief description of the Tektronix P69xx Series High Density Logic Analyzer Probes information on attaching color coded probe labels and probe and adapter connection instructions from the logic analyzer to the target system Product Description The P69xx Series Probes connect TLA7Axx and TLA7NAx Series Logic Analyzer modules to a target system m The P6960 probe consists of 34 single ended channels in one probe head m The P6964 probe consists of 34 single ended channels in one probe head distributed over 4 module end connectors m The P6980 probe consists of 34 channels in two probe heads with each head containing 17 differential channels m The P6982 probe consists of 17 differential channels in one probe head Attaching Probe Labels If you purchase probes for the logic analyzer module you will need to apply the color coded labels You will find instructions on how to attach the labels to the probes on a color reference card that is included with the probes P6960 High Density Logic Analyzer Probe Labeling and Installation Instructions
42. nd P64xx probe products Please contact Nexus Technology directly for more information Contact Information Nexus Technology Phone 877 595 8116 Fax 877 595 8118 Repackaging Instructions Use the original packaging if possible to return or store the probes If the original packaging is not available use a corrugated cardboard shipping carton Add cushioning material to prevent the probes from moving inside the shipping container Enclose the following information when shipping the probe to a Tektronix Service Center Owner s address Name and phone number of a contact person Type of probe Reason for return Full description of the service required P69xx Series High Density Logic Analyzer Probes Instruction Manual 55 Maintenance 56 P69xx Series High Density Logic Analyzer Probes Instruction Manual a E Replaceable Parts This chapter contains a list of the replaceable components for the P69xx Series Probes Use this list to identify and order replacement parts Parts Ordering Information Replacement parts are available through your local Tektronix field office or representative Changes to Tektronix products are sometimes made to accommodate improved components as they become available and to give you the benefit of the latest improvements Therefore when ordering parts it is important to include the following information in your order m Part number m Instrument type or model number Instrument seri
43. ng Transmission Lines Due to the high performance nature of the interconnect ensure that stubs which are greater than 1 4 length of the signal rise time are modeled as transmission lines P69xx Series High Density Logic Analyzer Probes Instruction Manual Reference P69xx Series Probes Load Model The following electrical model see Figure 21 includes a low frequency and high frequency model of the High Density Single Ended and High Density Differential Probes For the Differential Probes the load model is applied to both the side and the side of the signal Chi ae R1 0 5pF T 20k Q 77 77 Low frequency probe load ty 10 pS ty 6 pS Z0 85 Q Z0 70 Q pan pan 20k Q Pad_C 40 fF 160 fF 77 77 High frequency probe load Figure 21 High Density probe load model The differential load for the P6960 and P6964 clock inputs and the P6980 and P6982 probes can be modeled by attaching the single line model to each side and of the differential signal The and sides of the differential signal are well insulated in the probe head up to and including the differential input stage P69xx Series High Density Logic Analyzer Probes Instruction Manual 31 Reference Probe Footprint Dimensions Use the probe footprint dimensions in Figure 22 to lay out your circuit board pads and holes for attaching the retention posts Pad finishes that are supported inc
44. nt of this scheme is being applied to large microprocessor buses where the bus is split into smaller more easily managed groups that each have their own dedicated strobe Although the timing relationship between a particular clock and its associated data group is very tight the timing between the different groups can vary greatly and changes depending on which device has control of the bus Many source synchronous designs use wide buses It is not uncommon to require a set of merged logic analyzer modules to provide the channel count needed in probing larger source synchronous systems While all of the modules in a merged set can use their clock inputs independently if needed it must be remembered that there are a maximum of four clock inputs on a 136 channel wide module P69xx Series High Density Logic Analyzer Probes Instruction Manual 21 Reference To see the importance of this reminder we will once again use a microprocessor system as an example Tektronix logic analyzer processor has a 32 bit address bus and a 64 bit data bus The data bus is split into four 16 bit subgroups that have independent source synchronous clocks For the logic analyzer to correctly acquire data from this system it will need five clock inputs one for the address bus and one each for the four 16 bit data bus subgroups To acquire both buses the analyzer would need at least 96 channels 32 address and 64 data However a single 102 channel card doesn t hav
45. ntial clock logic analyzer technology probe The P6960 probe has 32 data channels one clock and one qualifier for each footprint G D2 D3 G D6 D7 G D8 D9 G D12D13G D16 D17 G D20 D21 GCK2 CK2 G D26D27 G D30 D31 O Ss We ae en as a MOOC OC B COC SOC SOCSBOOC SCV SOC EGO O Oa Do DI G D4 D5 GCKI CKI G D10 D11 G D14 D15 G D18 D19 G D22 D23G D24 D25 G D28 D29 G G Figure 24 P6960 single ended PCB footprint pinout detail Table 4 on page 35 lists the channel mapping to a logic analyzer module for a P6960 single ended data differential clock logic analyzer probe 34 P69xx Series High Density Logic Analyzer Probes Instruction Manual Reference Table 4 Channel assignment for a P6960 single ended data differential clock logic analyzer probe D oo O gt 2 3 5 R 34 Channel A9 GND GND GND GND GND GND GND ait jon fess fas fats Jos jas 033 M3 pia fese fase Jare ose fare cse A15 GND GND GND GND GND GND GND A18 GND GND GND GND GND GND GND A23 D25 eos fps Doe coe poe faze A24 GND GND GND GND GND GND GND A27 GND GND GND GND GND GND GND P69xx Series High Density Logic Analyzer Probes Instruction Manual 35 Reference Table 4 Channel assignment for a P6960 single ended data differential clock logic analyzer probe Cont Pin Number B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 36 Probe4 Signal name GND GND E2 2 E2
46. obe to the target system the compression footprints on the board should be properly cleaned according to the following steps 1 Usea lint free clean room cloth lightly moistened with electronic reagent grade isopropyl alcohol and gently wipe the footprint surface 2 Remove any remaining lint using a nitrogen air gun or clean oil free dry air P69xx Series High Density Logic Analyzer Probes Instruction Manual 11 Operating Basics 12 Handling the cLGA The cLGA interface clips in the probe heads should always be handled with care Interface Clips Keep the following points in mind when you handle the clips Probe Heads m The cLGA interface clips should always be handled by the outer edges being careful to avoid the contacts in the center Contacts should not be touched with fingers tools wipes or any other devices See Figure 9 Figure 9 Proper handling of the interface clip m The connector should not be exposed to liquids or dry chemicals m Ifthe board pad array needs to be cleaned only use isopropyl alcohol and lint free cloth as described above m Immediately following cleaning or immediately prior to placement of connector to circuit board the board pad array and connector contact array should be blown off with clean oil free dry air or nitrogen to remove loose debris First start the blowing process by aiming away from the array areas and then sweep across the pad and contact arrays in a repeated motion
47. of 1 27 mm to 6 35 mm 0 050 in to 0 250 in Consists of two probe heads supporting 17 channels each for a total of 34 channels 2X mode 1 2 demultiplexing and 4X mode 1 4 demultiplexing use one probe head to minimize required board real estate Color coded keyed attachment 2 5 V to 5 V input operating range 2 0 V to 4 5 V threshold range 300 mV minimum single ended signal amplitude 5 V maximum 150 mV each side minimum differential signal amplitude 2 5 V maximum P69xx Series High Density Logic Analyzer Probes Instruction Manual 5 Operating Basics P6982 High Density Differential Probe m Minimal loading of 0 5 pF at 20 kQ to ground m Operation in normal or inverted polarity is acceptable m Any common mode voltage is acceptable so long as the maximum positive voltage does not exceed 5 V and the maximum negative voltage does not exceed 2 5 V NOTE Refer to Figure 20 on page 29 for P6980 probe routing and pinout information The P6982 Probe is a 17 channel high density connectorless differential probe with D Max probing technology see Figure 4 The probe consists of one probe head of 17 differential channels 16 data and 1 clock qual Figure 4 P6982 High Density Differential probe with D Max probing technology The following list details the capabilities and qualities of the P6982 Probe m Differential data clock and qualification inputs single ended signals may be probed if negative input is
48. on Manual 10 u 12 13 15 16 17 25 26 27 27 28 28 29 31 32 33 34 37 40 45 54 59 Table of Contents Figure 30 P6964 High Density probe accessories 60 Figure 31 P6980 High Density Differential probe accessories 61 Figure 32 P6982 High Density Differential probe accessories 62 Figure 33 Optional accessories c cece cee eeceeceees 63 iv P69xx Series High Density Logic Analyzer Probes Instruction Manual a a General Safety Summary To Avoid Fire or Personal Injury Review the following safety precautions to avoid injury and prevent damage to this product or any products connected to it To avoid potential hazards use this product only as specified Only qualified personnel should perform service procedures While using this product you may need to access other parts of the system Read the General Safety Summary in other system manuals for warnings and cautions related to operating the system Connect and Disconnect Properly Connect the probe output to the measurement instrument before connecting the probe to the circuit under test Disconnect the probe input and the probe ground from the circuit under test before disconnecting the probe from the measurement instrument Observe All Terminal Ratings To avoid fire or shock hazard observe all ratings and markings on the product Consult the product manual for further ratings information before making connections to the pro
49. on Manual 37 Reference Table 5 Channel assignment for a P6964 single ended data differential clock logic analyzer probe Pin Number 136 Channel a2 or Ct A3 GND GND M 03 5 AS 03 4 AG GND GND A7 CK3 AB CK3 Mo pa joss A12 GND GND M3 e Ct A14 3 0 A16 s 7 A17 D9 6 aig pio BS A20 on Aaa A21 GND GND A22 D12 A3 3 A23 A3 2 A25 pua A26 D15 A3 0 A27 GND GND 38 P69xx Series High Density Logic Analyzer Probes Instruction Manual Reference Table 5 Channel assignment for a P6964 single ended data differential clock logic analyzer probe Cont Pin Number 136 Channel B2 D16 E80 B3 D17 E3 1 B6 pig 88 B7 GND GND B8 D20 E3 4 B9 E35 Bt E36 B12 D23 E3 7 B13 GND GND B16 GND GND B17 D26 A1 2 B18 A13 B20 CK1 B21 CK1 B22 GND GND B24 ALS B26 D30 A1 6 B27 D31 A1 7 P69xx Series High Density Logic Analyzer Probes Instruction Manual 39 Reference P6980 Differential Probe Figure 26 shows the pad assignments pad numbers and signal names for the with D Max probing PCB footprint of the P6980 differential data and clock logic analyzer probe The technology P6980 probe has 16 data channels and one clock or qualifier for each footprint There are two footprints associated with one P6980 probe Figure 26 P6980 differential PCB footprint pinout detail Table 6 on page 41 lists the channel mapping to a 136 channel or 102 channel logic analyzer module for the P6980 differential data and clock logic analyzer
50. ow 34 channel probe head makes for easier placement and layout Optimized for 4X mode 1 4 demultiplexing to minimize board real estate Color coded keyed attachment 2 5 V to 5 V input operating range 2 0 V to 4 5 V threshold range 300 mV minimum single ended signal amplitude 150 mV amplitude each side minimum differential signal Minimal loading of 0 5 pF at 20 kQ to ground Operation in normal or inverted polarity is acceptable clock only Any common mode voltage is acceptable so long as the maximum positive voltage does not exceed 5 V and the maximum negative voltage does not exceed 2 5 V clock only NOTE Refer to Figure 20 on page 29 for P6964 probe routing and pinout information P69xx Series High Density Logic Analyzer Probes Instruction Manual Operating Basics P6980 High Density The P6980 Probe is a 34 channel high density connectorless differential probe Differential Probe with D Max probing technology see Figure 3 The probe consists of two independent probe heads of 17 channels each 16 data and 1 clock qual Figure 3 P6980 High Density Differential probe with D Max probing technology The following list details the capabilities and qualities of the P6980 Probe Differential data clock and qualification inputs single ended signals may be probed if negative input is grounded cLGA contact eliminates need for built in connector Footprint supports direct signal pass through Supports PCB thickness
51. probe 40 P69xx Series High Density Logic Analyzer Probes Instruction Manual Reference Table 6 Channel assignment for a P6980 differential clock and data logic analyzer probe to a 136 or 102 channel logic analyzer module 136 Channel 102 Channel v fo A ERE PEP eee number name P69xx Series High Density Logic Analyzer Probes Instruction Manual M Reference Table 6 Channel assignment for a P6980 differential clock and data logic analyzer probe to a 136 or 102 channel logic analyzer module Cont 136 Channel 102 Channel EP Perr rre number name B8 D5 C0 5 B9 D5 C0 5 B27 c1 74 42 P69xx Series High Density Logic Analyzer Probes Instruction Manual Reference Table 7 lists the channel mapping to a 68 channel or 34 channel logic analyzer module for the P6980 differential data and clock logic analyzer probe Table 7 Channel assignment for a P6980 differential clock and data logic analyzer probe to a 68 or 34 channel logic analyzer module Pin number Al A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 68 Channel 34 Channel ske E name GND GND GND GND GND m fe no e wo me fe wo e he pu ars ore css A3 6 P69xx Series High Density Logic Analyzer Probes Instruction Manual 43 Reference Table 7 Channel assignment for a P6980 differential clock and data logic analyzer probe to a 68 or 34 channel logic
52. riginal location to be certain it was not a connection problem at the logic analyzer end Place another probe in the mounting posts of the original probe If the new probe acquires data then the old probe is probably at fault P69xx Series High Density Logic Analyzer Probes Instruction Manual Operating Basics Connecting the Flying The flying lead set Tektronix part number 196 3494 xx is an optional Lead set accessory for your probe The flying lead set allows you to connect to individual test points on your PCB However for general purpose probing the P6810 probe is recommended for best performance Refer to Figure 11 and connect the probe to the target system by performing the steps that follow You can connect the probe leads to the target system without turning off the power to the target system 1 Connect the probe leads to the square pins on the PCB 2 Connect the negative input to ground on the PCB 3 Connect the leadset to the probe Figure 11 Using the flying lead set to connect to the target system P69xx Series High Density Logic Analyzer Probes Instruction Manual 15 Operating Basics Dressing the Probe Cables Use the Velcro cable managers to combine the cables together or to help relieve strain on the probe connections Hang the probe cables so that you relieve the tension on the probes at the retention posts See Figure 12 Good N J Ve Cable hanger Probe cables Logic Analyzer FA
53. ronix supplies or d to service a product that has been modified or integrated with other products when the effect of such modification or integration increases the time or difficulty of servicing the product THIS WARRANTY IS GIVEN BY TEKTRONIX WITH RESPECT TO THE PRODUCT IN LIEU OF ANY OTHER WARRANTIES EXPRESS OR IMPLIED TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE TEKTRONIX RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES Se Table of Contents General Safety Summary 0 0 eee cece ce teen eens v Prefac sorana a E EE A E AN E A vii Related Documentation ceisia nee trai Banger oaa teea Oa A E ale ene ea Gs vii Gommonly Used Terms s aa a E a dace dara tito aR glace teat viii Contacting Tektronix sarera E EEO EEE OEN E bree eae xi Operating Basics 0 ccc cece cece cree ee E e eens 1 Product Description csc eee a Sot ce Soe ee aoe cae 1 P6960 High Density Probe 0 eee eee eee eee eee 2 P6964 High Density Probe 0 cece ee eee eee eee eee 3 P6980 High Density Differential Probe 00 00 0000 5 P6982 High Density Dif
54. s probes Connection is obtained by applying pressure between your PCB and the probe through a cLGA c spring Differential Input For differential signals the magnitude of the difference voltage Vmax Vmin Amplitude Definition and Vmin Vmax must be greater than or equal to 150 mV Refer to Figure i viii P69xx Series High Density Logic Analyzer Probes Instruction Manual Preface Differential input 150 mV minimum swing each side 2 5 V maximum Nmax 145V V _ V V V 0 V Difference 1V V min Differential equivalent signal input 300 mV swing as viewed by the logic analyzer and the analog probe output 150 mV y Ny 0 V Difference TH 0V oV 150 mV Note For differential inputs the module threshold should be set to 0 V assuming no common mode error Note See online help for further analog output details Figure i Differential input amplitude D Max probing technology Trademark name that describes the technology used in the P69xx Series high density logic analyzer probes A lead set designed to attach to a P6960 Probe to provide general purpose Flying Lead Set probing capability See Figure ii Figure ii Flying Lead Set P69xx Series High Density Logic Analyzer Probes Instruction Manual Preface Functional Check Procedure Keepout Area Module Module End PCB Probe Probe Adapter Probe Head SMT KlipChip Functional check procedures verify the basic functionali
55. sampled at a 1 GHz rate with double the memory depth Likewise 4X high resolution timing mode provides quadruple the normal 500 MHz sample rate on one fourth of the channels By trading three fourths of the analyzer s channels the remaining channels can be sampled at a 2 GHz rate with quadruple the memory depth P69xx Series High Density Logic Analyzer Probes Instruction Manual 23 Reference 24 Both of the high resolution timing modes use the same demultiplexing channel routing as shown in Tables 2 and 3 By taking care to assign critical signals to the demultiplexing source channels you can obtain extra timing resolution where it is most needed Since demultiplexing affects only the main memory you will still have the MagniVu data available for all of the signals that are disconnected from the main memory when you switch to the high resolution timing modes Probing Analog Signals The TLA7Axx module provides visibility of analog signals with Analog mux Analog mux routes the actual signal seen by each channel s probe through a high bandwidth path to an analog multiplexer inside of the logic analyzer module From the logic analyzer interface you can route any input channel to one of four output connectors on the module By connecting the analyzer analog outputs to your oscilloscope you can see the analog characteris tics of any signal probed by the logic analyzer Sometimes it is convenient to have analog signals accessible for eas
56. seeing incorrect data in the logic analyzer acquisition However the nature of the incorrect data has a very consistent characteristic the data from multiple channels go to a logic low and stay there Intermittent bad data or a single dead channel are not failures typically associated with probe mounting post installa tion problems 1 Slightly move the probe head to either side or press down on the probe head while making new acquisitions If good data is now being acquired then the probe mounting is most likely the cause If good data is not acquired then remove the probe and check the posts for too much play If there is significant play then the probe mounting is most likely the cause If the posts have minimal play and you cannot see a gap between the bottom of the posts and the circuit board surface then move the probe with bad data from one logic analyzer probe location to another If the problem follows the probe then the probe is the problem Visually inspect the cLGA interface clip on the probe for any damage or missing c spring metal contacts If there is damage to the interface clip or if any c spring metal contacts are missing replace the cLGA interface clip See Replacing the cLGA Clip on page 54 and Replaceable Parts beginning on page 57 for more information If the problem doesn t follow the probe it is either the logic analyzer or the probe connection at its previous location Move the probe back to the o
57. t can be useful as qualifiers There are often signals that indicate data reads versus data writes R W signals that show when alternate bus masters have control of the processor buses DMA and signals that show when various memory devices are being used ChipSel All of these signals are good candidates for assignment to qualifier channels By logically ANDing the clock with one of these qualifiers you can program the analyzer to store only data reads or data writes Using the DMA signal as a qualifier provides a means of filtering out alternate bus master cycles Chip selects can limit data latching to specific memory banks I O ports or peripheral devices Merged Module Sets and Source Synchronous Clocking TLA7Axx and TLA7NAx analyzer modules that are 102 channels or 136 channels wide can be merged together to act as a single logic analyzer with a larger channel count Up to five modules can be merged to provide up to a 680 channel analyzer A unique feature of the TLA7Axx module is that it supports source synchronous clocking Combining these two capabilities provide some additional considerations for signal routing Source synchronous clocking is a method that manages the skew between the system clock and the data bus by requiring the sending device to drive an actual clock or strobe signal along with the data that is very tightly coupled with it in terms of skew The receiving device then uses this strobe to capture the data A varia
58. ty there should be a continuous uninterrupted ground return plane along the entire signal path P69xx Series High Density Logic Analyzer Probes Instruction Manual 29 Reference Electrical Considerations 30 Physical Attachment Requirements for the P69xx Series Probes The P69xx Series Probe interconnects are designed to accommodate PCB thickness ranging from 1 27 mm to 6 35 mm 0 050 in to 0 250 in To accom modate this range there are two wire lengths in the design m For board thicknesses of 0 050 in to 0 120 in use the standard wire that comes mounted to the post in the retention kit included with each probe m For board thicknesses of 0 120 in to 0 250 in use the long wire supplied with the probe also included in the retention kit embedded in foam For more information see Using the Correct Retention Post Wires on page 9 This section provides information on transmission lines and load models for the P69xx Series Probes The low frequency model is typically adequate for rise and fall times of 1 ns or slower in a typical 25 Q source impedance environment 50 Q runs with a pass through connection For source impedance outside this range and or rise and fall times faster than 1 ns use the high frequency model to determine if a significant difference is obtained in the modeling result The compression land pattern pad is not part of the load model Make sure that you include the compression land pad in the modeli
59. ty of the probes by confirming that the probes recognize signal activity at the probe tips An area on a printed circuit board in which component trace and or via placement may be restricted The unit that plugs into a mainframe that provides instrument capabilities such as logic analysis The end of the probe that plugs into the module unit An acronym for Printed Circuit Board also known as Etched Circuit Board ECB The device that connects a module with a target system See Figure iii Probe head P6960 Single ended probe Figure iii Probe example A device that connects the LA module probe to a target system The end of the probe that connects to the target system or probe adapter An interface device for attaching logic analyzer probes to components with a maximum lead diameter of 2 413 mm 0 095 in and stackable on lead centers of 1 27 mm 0 050 in P69xx Series High Density Logic Analyzer Probes Instruction Manual Preface Contacting Tektronix Phone Address Web site Sales support Service support Technical support 1 800 833 9200 Tektronix Inc Department or name if known 14200 SW Karl Braun Drive P O Box 500 Beaverton OR 97077 USA www tektronix com 1 800 833 9200 select option 1 1 800 833 9200 select option 2 Email techsupport tektronix com 1 800 833 9200 select option 3 6 00 a m 5 00 p m Pacific time This phone number is toll free in North A
60. vironmental specifications for the probes The probes are designed to meet Tektronix standard 062 2847 00 class 5 Table 11 Environmental specifications Characteristic P69xx Temperature Operating 0 C to 50 C 0 F to 122 F Non operating 51 C to 71 C 60 F to 160 F Humidity 10 C to 30 C 50 F to 86 F 95 relative humidity 30 C to 40 C 86 F to 104 F 75 relative humidity 40 C to 50 C 104 F to 122 F 45 relative humidity Altitude Operating 10 000 ft 3 048 m Non operating 40 000 ft 12 192 m Electrostatic immunity 6 kV P69xx Series High Density Logic Analyzer Probes Instruction Manual Maintenance Probe Calibration Functional Check The P69xx Series High Density Logic Analyzer Probes do not require scheduled or periodic maintenance Refer to the Functional Check section below to verify the basic functionality of the probes To confirm that the probes meet or exceed the performance requirements for published specifications with a compatible logic analyzer module you must return the probes to your local Tektronix service center Connect the logic analyzer probes to a signal source start an acquisition and verify that the acquired data is displayed in either the listing or waveform windows Inspection and Cleaning A Service Strategy CAUTION To prevent damage during the probe connection process do not touch the exposed edge of the interface clip

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