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SERVICE TRAINING - Qariya Upload Center

1. UN NE 5V 1 MICROCOMPUTER 0830 gt 5V 2 for TUNER COMB etc T862 9831 45V 3 for PIP ESD C C RGB SW Main Su pply 0832 81 9V 2 for DSP CRT D etc 39 AUDIO OUT 5 5 9V OF gt Defl Vcc to V C D IC Q801 Q430 F470 B 125V VOLTAGE CONTROL HH TPW m nn gt F B T V M STR Z3201 R479 inn 32V TUNER Q843 1 2 Xy R101 sw 2 2801 13 F B T HEATER Q862 PROTECTOR C47im 0471 R472 Q830 PHOTO COUPLER H1C1019 14 200V L V P 35V O C P Sw 3 16 D802 D805 F850 30V R7782 n p 730V x O C P 0768 0802 sv R7750 VOLTAGE CONTROL El me RR EE STR57041 55 15V 8E LOW VOLTAGE PROTECTOR OCP Q853 0854 Q759 15V R7765 15V ANA e gt 0 0 P Sub Supply Figure 17 1 Power Supply Block Diagram 17 3 2 Rectifying circuit and standby power supply The rectifying circuit generates dc voltage sources from the 117 Vac input D899 is a metal oxide varistor used to absorb surges due to line spikes lightning etc The arrow in fig 17 2 indicates the path in which the surge is by passed C801 T801 and T802 are filters for abnormal ra diation or line noise For direct view sets the degaussing circuit using a thermistor is supplied after SR81 not shown R810 is used to suppress surge current during switch on D801 along with C810 output a rectified and smoothed DC voltage T840 is
2. 1401 EN Ed E 2 9 NN e 931 dr SA Sy po PY b Y 1 EA A A A Te U s Y T400 C477 e From v dynamic focus circuit 77 Fig 18 2 18 3 3 V DYNAMIC FOCUS CIRCUIT 3 1 Theory of Operation Fig 18 3 shows the circuit which develops the V parabola correction voltage Flyback pulse Integrated Amplifier Rectification Deflection circuit circuit block output efH efv Sawtooth wave gt aay Focus capacitor L EF electrode 77 Fig 18 3 Block diagram of V dyanamic focus circuit 18 4 3 2 Circuit Operation A sawtooth wave voltage developed across R305 in the V output circuit is cut in its DC component and the AC components of the voltage is integrated into a parabola form by a mirror integrator in the first stage and amplified with a specified gainlevelsetby R362 R361 The amplified parabola wave enters an op amplifier in the next stage and again amplified The op amplifier works as an inverting amplifier and the gain is determined by R368 R369 R366 The parabola voltage amplified in this way enters base of Q361 amplified in an inverted form and developed as the V focus parabola voltage 300 Vp p DC component 60V This voltage is mixed with the H focus parabola voltage in passing through R483 resulting in mixed parabora voltage consisting ofaH c
3. 9 3 SECTION X SYNC SEPARATION H AFC H OSCILLATOR CIRCUITS 1 SYNC SEPARATION CIRCUIT 10 2 1 1 Theory of Operation 10 2 2 H AFC Automatic Frequency Control CIRCUS 10 3 3 H OSCILLATOR CIRCUIT 10 4 3 1 QUIM e ei 10 4 3 2 Theory of Operation 10 4 SECTION XI VERTICAL OUTPUT CIRCUIT I COWDEN EE a en 11 2 1 1 Theory of Operation 11 2 2 V OUTPUT CIRCUIT 11 3 2 1 Actual EEC 11 3 2 2 Sawtooth Waveform Generation 11 3 DIE era 11 4 2 4 V Linearity Characteristic CCOETECHODPz S iesu nic 11 6 3 PROTECTION CIRCUIT FOR V DEFLECTION STOP 11 7 3 1 435V Over Current Protection Circ ni 11 8 SECTION XII HORIZONTAL DEFLECTION CIRCUIT ATINA a ud 12 2 2 HORIZONTAL DRIVE CIRCUIT 12 2 2 1 Theory of Operation 12 2 3 BASIC OPERATION OF HORIZONTAL DRIVE att 12 3 3 1 Theory of Operation 12 3 AAA p dor opes 12 4 3 3 Circuit Description 12 5 4 HORIZONTAL OUTPUT CIRCUIT 12 6 4 1 Theory of Operation 12 7 4 2 White Peak Bending Correction Circuit 12 11 4 3 H Blanking seien 12 12 4 4 200V Low Voltage Protection 12 13 5 HIGH VOLTAGE GENERATION CIRCO x items eedem 12 14 5 1 Theory of Operation 12
4. FAV DSP SUR SYC SBS These functions do not have duplicate locations on the TV They can be controlled only by the Remote Control L I S 1 314 4DYNAMC FOCUS En Mann 8 DIGITAL CONVER Gay FRONT SURROUND 81 DSP 4CH DOLBY PRO A DIGITAL COMB 68 3D Y C FRONT VET HOKURIKU AMP 2CH GA 7 2 8 78 2 EDS CC e e e e FEATURE 1 AUDIO FRONT SURROUND TP48E50 51 60 61 TP55E50 51 TREM 1pcs REAR CENTER AMP W O 73 DSP4CH TP55E80 81 TP61E80 SPK TERM 2pcs REAR AMP W CENTER AMP W O CENTER INPUT W DOLBY PRO 48 90 SPK TERM 2pcs REAR CENTER AMP W 2 COMB FILTER DIGITAL COMB TP48E50 51 60 61 90 TP55E50 51 3D Y C TP61E80 3 TUNER TP48E50 51 TP55E50 51 ONLY 1 TUNER OTHER 2 TUNER iff 5 1 CRT D R rom TUM CONV POW2 LNOAVT SISSVHO 9 7 CONSTRUCTION CHASSIS a 1 WOOD CABINET 2 LIGHT BOX 3 SPEAKER GRILLE 4 FRONT COVER 8 5 CRT MOUNTING 6 SHIELD FRONT pomme 7 SHIELD SIDE 8 SCREEN BEZEL 9 SCREEN BRACKETL 10 SCREEN BRACKET S 12 1 CONTROL PANE
5. Forward current Fig 12 2 t Base current c Reverse current i gt Falling DE time usus i time 3 2 Drive System 3 2 1 ON drive system When the drive transistor is on the horizontal output transistor also turns on Merit The base current can be precisely controlled without being affected by variation of pulse width which is caused by the horizontal oscillator circuit and the drive circuit Demerit 1015 difficult to flow a reverse bias currentto the horizontal output transistor to eliminate its storage carrier for transient period of on to off period for the horizontal output transistor H output H driver 12 4 3 2 2 OFF drive system When the drive transistoris on the horizontal output transistor is off Merit Energy balance between on and off periods of the drive circuit is better and the circuit can be simplified Reverse base current of the horizontal output transistor can be controlled easily Demerit Base emitter forward current flowing into the horizontal output transistor is susceptible to on period variation of the drive transistor H output H driver 3 3 Circuit Description In the N5SS chassis the off drive system is employed 1 2 3 When QI inside 0501 is turned 0402 base is forward biased through 9 V pin 22 of Q501 VCC pin 23 of Q501 Out gt R411 R410resistor divider and then
6. V TRIGGER WAVE GAIN PUMP UP CIRCUIT CIRCUIT DEFLECTION YOKE OUTPUT Fig 11 1 Block diagram of V deflection circuit 1 1 Theory of Operation The purpose of the V output circuit is to provide a sawtooth wave signal with good linearity in V period to the deflection yoke When a switch 5 is opened an electric charge charged up to a reference voltage VP discharges in an constant current rate and a reference sawtooth voltage generates at point a This voltage is applied to input non inverted input of an differential amplifier A As the amplification factor of A is sufficiently high deflection current flows so that the voltage V2 at point becomes equal to the voltage at point G S Switch Vp r Differential amplifier L Fig 11 2 11 2 2 V OUTPUT CIRCUIT 2 1 Actual Circuit C322 49V e 35V D301 L 5 C313 R329 8 R303 FEEDBACK 0501 I 64 6 L301 R336 C321 elVVY O 3 ew R320 R301 2307 L462 L463 1464 NN 3 R306 C314 C309 xf Q T m C306 R313 R330 77 ps MW C305 27V C319 R304 R305 77 77 Fig 11 3 2 2 Sawtooth Waveform Generation 2 2 1 Circuit Operation The sawtooth waveform generation circuit consists of as shown in Fig 11 4 When a trigger pulse enters 13
7. ABL signal from pin 8 12Vdc source is also derived via pin 7 and D408 to supply the SVM and DPC circuit boards In addition the 12Vdc source is used to develop the 9V 1 source via a 9 Volt regulator made up of 0420 Q421 and D427 High voltage is supplied from the sec ondary along with Focus and Screen voltage sources devel oped from a tap on the high voltage secondary of T461 AFC BLANKING 10 9V 1 Reg 49V 1 0420 421 D427 HEATER 29 30kV 4 to 2nd ANODE R448 0408 12V NN 4 7 C447 C307 Es R327 35V lt Hwy 6 2410 C310 D307 FOCUS X3 FOCUS 27V X3 C460 R469 2 TA R444 23 125Vde YW ml 2 C448 en D406 R443 Dynamic Focus T C446 Q404 ABL Collector T461 Figure 17 6 Scan Derived Sources 17 8 8 Protector Module Z801 Figure 17 7 shows the standardized protector module Z801 The following are the four different sections within the Protector Module Error Amp Switch Latch B OCP and X Ray Protect In addition the Over Current Protect OCP Over Voltage Protect OVP and Under Voltage Protect UVP circuits are routed through the internal Switch Latch circuit to trigger the unit off through the Pro tect output Pin 16 The Error Amp circuit monitors the B 125V line via Pin 1 The Error Amp controls the current through the photodiode of photocoupler Q862 When the B voltage decreases Q862 conducts less and when
8. GND 4 8V ROUT 4 1 105 42 gt lt 4 8V 3 0V 3 6V 4 1V Or m T 0 9V V 2 4 8V v d v B OUT AAVIN CHASSIS CHASSIS GND 4 8V PIP VIDEO Ue 9 2 5 6 PMUSO2H BLOCK DIAGRAM OF PIP MODULE 55 54 PIP VIDEO QYO01 QY03 QYO1 PC 1832GT TC9083F PC1832GT PIP V C D PIP PROCESSOR PIP V C D NOTES SECTION X SYNC SEPARATION H AFC H OSCILLATOR CIRCUITS 1 SYNC SEPARATION CIRCUIT The sync separation circuit separates a sync signal from a video signal and feeds it to an H and V deflection circuits The separation circuit consists of an amplitude separation H and V sync separation circuit and a frequency separation circuit V sync separation circuit which performs the separation by using a frequency difference between H and V In the N5SS chassis all these sync separation circuits are contained in a V C D IC TA1222N Fig 10 1 shows a block diagram of the sync separation circuit Sync input Q501 Composite H V SYNC video SEPARATION signal CIRCUIT WAVEFORM SHAPEING CIRCUIT Fig 10 1 Sync separation circuit block diagram 1 1 Theory of Operation 1 1 1 Auto slicer type synchronous separation circuit When a synchronizing signal is separated synchronous separation is made from the beginning with constant voltage in the conventional synchronous separatio
9. 1 BASIC OPERATION AND UNIT UNDERSTANDING As a servicer it is important now more than ever to fully understand the operation and functions of a television set before proceeding with a repair This is because many of the problems encountered by a customer today can be caused by an incorrect menu selection or improper setup Therefore the purpose of this lab is to familiarize you with menus and features of the television from the customer s point of view SECTION ONE BASIC OPERATION 1 Verify that the unit is connected to an AC supply and that a signal is connected to the ANT 1 input While verifying signal connections take time to examine all of the inputs on the rear and front behind door of the unit 2 Turn on the set with the remote control and tune to an active channel Refer to page 9 of the service manual provided and familiarize yourself with all of the keys on the remote paying particular attention to the following keys L EDS O TIMER O Functions Open the bottom door on the remote control by sliding it down Try each key starting with the upper row Each of these buttons brings up another menu and or sub menus 3 In the Picture Menu What is Color Temperature 4 In the Audio Menu Where can the speakers be turned off by the user 5 In the Setup Menu What is Favorite Channel What is Channel Lock 6 7 Refer to page 16 of the Service Manual and perform the User Conve
10. 2 2 Reduction of Parts Count The use of digital to analog converters built into the ICs allowing them to be controlled by software has eliminated or reduced the requirement for many discrete parts such as potentiometers and trimmers etc 2 3 Quality Control The central control of adjustment data makes it easier to understand analyze and review the data thus improving the quality of the product 1 2 3 COMPARISON DIFFERENCES OF TG 1 CHASSIS Toshiba s concept for the TG 1 chassis was to create a sort of universal chassis which with minimal changes could be used as a standard throughout the entire Toshiba color television lineup starting in 1995 TG 1 stands for Toshiba Global 1 The TG 1 chassis can be found in several different models and varies in both complexity and features TG 1 Chassis Picture and Features Root Chassis INES 2 2032 5 A2 LEM 2032 55 B 2532 Typical Sizes 27 32 N5SS 27 thru 35 ypical Chassis Examples 4 SPECIFICATIONS CHASSIS MODEL Nbr SPECIFICATION TP48E50 TP48E51 TP48E60 TP48E61 TP48E90 55 50 55 51 55 80 55 81 61 80 STEP UP 1 Picture Sizes 2 Channel Capacity 3 C Caption 4 MTS with dbx 5 Bass Tre Balance 6 Sub Audio Program 7 Remote Control 8 Picture in Picture 9 LED Indicator RED 10 Local Key 48 D S
11. Eb H002 H001 HY01 IF MTS A PR TUNER TUNER IF PROCESSING IMIS 9 KEYA 38 SDA1 28 21 20 ZEE 3 sap MICRO 37 9 10 25 24 44 43 COMPUTER 01 0701 CIRCUIT CONV TOIR SWITCHING PROCESSOR LED RMT OUT TRANS 11 12 7 01 SCLO SDAO DSP DOLBY PIP D PRO LOGIC CIRCUIT QA02 EEPROM MEMORY Figure 1 11 PC Communication Block Diagram 1 14 13 Digital Convergence The TG 1 model PTV s are equipped with a new digital convergence circuit shown in Figure 1 13 This circuit allows servicers to set the convergence with the remote control Q701 the Digital Convergence Processor aligns the convergence from data received from the remote and saves the settings in the 0713 The digital convergence signals are converted to analog by the D A Converters Q703 Q704 and Q705 Then they are amplified Q713 EEPROM CLK FROM QAO1 DIGITAL CONVERGENCE DATA PROCESSOR FROM IC501 FROM Q301 by the pre amps Q715 Q717 amp Q719 and power amps Q751 amp Q751 before being applied to the convergence yokes The Power Amps Q752 and Q751 dissipate allot of heat because of their current draw so the supplies to these amps have a number of sensors for over current conditions Most of the convergence circuit is on a shielded board but the power amps are easily accessible for service RH GH BH TO CONV YOKES RV GV BV Figure 1 13 Convergence Block Diagram
12. Electromagnetic Focus Electromagnetic focusing with magnets mounted around the CRT neck Light beams around the peripheral of the CRT screen are focused towards the center thus increasing the amount of light emitted towards the screens Electrostatic Focus High unipotential focus Eb oa ee ea G2 Screen ck Focus Fig 16 3 Since the deflection is carried out by using a magnetic field applied from the outside of the neck high deflection power 1s obtained and focusing quality is high Moreover since the coils are mounted on the outside of the neck the configuration of the deflection fields created inside the neck has less distortion thus the best beam pattern will be obtained The best beam pattern is obtained at screen center and screen edges by applying parabolic voltages for H and V periods to the focus terminals This also assures a flat focusing characteristic across the entire screen To obtain clearer pictures a velocity modulation circuit is also provided 2 FUNCTION KEY COMPONENTS 2 1 Outline The optical system of the TP48C60 61 consists of a screen mirror and lens assembly A description will be given for each block Mirror Screen e 2 Lens Projection gt tube 5 5 X Optical coupling system Fig 16 4 16 4 2 2 Theory of Operation Screen FRESNEL LENTI
13. 1 o e Fig 14 1 Line 21 waveform L lt gt 2 2 L 4 A o d d d c R a L 23456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 20 s 3 DISPLAY FORMAT The character display area of caption mode and text mode consists of 32 characters x 15 rows as shown in Fig 14 2 On the front and back of each row 1 character blank area is respectively added In caption mode up to 15 rows can be displayed at the same time Characters viewed while in text mode are displayed in a black rectangular box of 34 characters x 15 rows EDS display format is shown in Fig 14 3 or EDS be displayed only when data of that type has been transmitted SCREEN LINE 43 LINE 237 1 CHARACTER BLANK AREA 32 CHARACTERS 1 CHARACTER BLANK AREA Fig 14 2 Caption Text display area Green Network Name Call Letters White Slant Unerline Program Name Cyan Prog Length Prog Type Time In Show Cyan Yellow Program Description 4rows Character background black Fig 14 3 EDS display format 14 3 4 CIRCUIT OPERATION A block diagram of the CC EDS circuit is shown in Fig 14 4 and block diagram of 1 is shown in Fig 14 5 The video signal which is input to pin 9 of UMOI is changed to 1 Vp p signal which is band limited to 600k
14. 15 7 6 CONVERGENCE OUTPUT CIRCUM fado tias 15 8 Oct CDU C 15 8 6 2 Circuit Description 15 8 7 CONVERGENCE TROUBLESHOOTING 2 RECTIFYING CIRCUIT AND CHART UEM 15 10 STANDBY POWER SUPPLY 17 4 O 15 11 3 MAIN SUPPLY CIRCUIT 17 4 4 OUTLINE OF CURRENT RESONANT SECTION XVI TYPESUPPLY AAA on 17 4 OPTICAL SECTION 5 FUNDAMENTAL THEORY 17 5 1 NECK COMPONENTS 16 2 6 ACTUAL CIRCUIT en 17 6 1 1 Outline of Components Around 7 SCAN DERIVED VOLTAGES 17 8 Neck of The Projection Tube 16 2 8 PROTECTOR MODULE Z801 17 9 1 2 Theory of Operation 16 2 9 SUB POWER SUPPLY 17 10 1 3 Projection Tube 16 3 10 PROTECT CIRCUITS 17 11 2 FUNCTION OF KEY 17 15 COMPONENTS 16 4 A 16 4 2 2 Theory of Operation 16 4 DYNAMIC FOCUS CIRCUIT 2 4 Optical Coupling Effect 16 8 LALA 18 2 2 5 LES nee 16 9 2 H DYNAMIC FOCUS CIRCUIT 18 2 2 6 Focus Adjustment 16 10 2 1 Theory of Operation 18 2 2 2 Circuit Operation 18 3 SECTION XVII 3 V DYNAMIC FOCUS CIRCUIT 18 4 P
15. C306 R305 a Scanning period 6 7 8 9 basic operation is shown in Fig 11 8 Since pin 7 of a transistor switch inside Q301 is connected to the ground for the scanning period the power supply pin 3 of the output stage shows a voltage of VCC VE and C308 is charged up to a voltage of VCC VF VR for this period First half of flyback period Current flows into L462 gt D1 gt C308 gt D308 VCC 35V GND R305 gt C306 L462 L463 L464 in this order and the voltage across these is VP VCC VF VCC VF VR VF about 50V is applied to pin 3 In this case D301 is cut off Last half of flyback period Current flows into switch D309 7308 gt Q301 pin3 gt Q3 991 462 L463 L464 9 C306 9 R305 in this order and a voltage of VPZVCC VCE sat VF VCC VF VR VCE sat about 40V is applied to pin 3 In this way a power supply voltage of about 27V is applied to the output stage for the scanning period and about 50V for flyback period First half N L462 L463 L464 27 C306 R305 Last half b Flyback period 2 4 V Linearity Characteristic Correction 2 4 1 S character Correction Up and Down ward Extension Correction A parabola component developed across C306 is integrated by R306 and C305 and the voltage is applied to pin 6 of Q302 to perform S character correction 2 4 2 Up and Down ward Linearity Balan
16. OLI ZBEMLS 1081 A0 29 0 1nO ANOO H L I Ll LA ama 49990791 19 0 H 01 1 Z68ALS 0H eld 1MO ANOD lt SOA H3ANOO t MNI 6920 4 050 1 MH dina gt Il Y9 D 12229 0110 asi lL p Am a 992 9 20440 96 9 Bis t N6 gt o SG D NS AY 09 24 i 29 0 10440 nt KAS ANN 9 0 5280 eme gt 1 8 YOLOSLOWd H3ANOO TW LIDIA 15 9 7 CONVERGENCE TROUBLESHOOTING CHART Relay turns on Reray OFF Relay operation sound Reray ON No Convergence once but immediately at power on correction wave turns off Check screen modes of picture Convergence PCB pull out of P712 Protect 1 Reray ON Reray ON Check power Check Q751 Q752 supply circuit and repair Reray OFF Reray OFF Reray OFF Y Check P708 R G B correction wave Proceed to protection circuit diagnosis procedures Check voltage at Check power supply 15V 30V pump up circuit Convergence output signals correction wave Are output signals Pump u a applied to Vblk of P711 Check DEF PC13 30V Check voltage across Check Q754 Q755 9V 5V 0754 0755 0756 0756 and repair 15V Check signals of all and associ
17. PIN 14 PIN 15 PIN 16 RELAY CONTROL CIRCUIT MEASUREMENTS 2 Locate 0843 See FIG 17 16 2 Record the voltages on the following C B E 3 What does 0843 control and how does it control it OVER CURRENT OVER VOLTAGE AND UNDER VOLTAGE PROTECT CIRCUIT MEASUREMENTS 4 Connect the lead of the p h meter to the side of C882 See FIG 17 16 3 5 Measure the voltage on the anode side of D865 See FIG 17 16 4 Anode D865 17 15 10 11 Measure the voltage on the anode side of D860 See FIG 17 16 5 Anode D860 Measure the voltage on the collector of 0853 See FIG 17 16 6 Collector Q853 Measure the voltage on the anode side of D867 See FIG 17 16 7 Anode D867 Measure the voltage on the collector of 0757 See FIG 17 16 8 Collector Q757 Connect the lead of the p h meter to the side of C310 see FIG 17 16 9 Measure the voltage on the collector of Q370 See FIG 17 16 10 Collector Q370 SECTION 2 VOLTAGES UNDER SHUTDOWN CONDITION l 2 Locate the X pin P415 and the R pin P416 See FIG 17 16 11 While monitoring pins 13 and 16 of Z801 on the p h meter jumper pins X and R together After the shutdown record the voltages on pins 13 and 16 of Z801 See FIG 17 16 1 PIN 13 PIN 16 The above exercise allows you to see what happens when the X Ray protect circuit shuts down the set 4 How is this determ
18. The main amplifiers and woofer output amplifiers use bipolar IC 8256 and develop output powers of 10Wx2 13W 2 THEORY OF OPERATION 2 1 Operation of TA8256H The TA8256H is a modified version of the TA8128AH which was used in the N4SS chassis as an audio ouput IC In the TA8256H one channel has been added and up to 3 channels can be used Performance for each channel is the same as that of the TA8218H Fig 4 1 shows a block diagram of the IC 25 5V Fig 4 1 4 2 SECTION V DSP CIRCUIT 1 ORIGINS DOLBY SURROUND Dolby Stereo movies and Dolby Surround video and television programs include an additional sonic dimension over conventional stereo productions They are made using a Dolby MP Motion Picture Matrix encoder which combines four channels of audio into a standard two channel format suitable forrecording or transmitting the same as regular stereo programs To recapture the dimensional properties brought by the additional channels a Dolby Surround decoder is used In the theatre a professional decoder is part of the Dolby Stereo cinema processor used to play 35 mm stereo optical prints The decoder recovers the left center and right signals for playback over three front speakers and extracts the surround signal for distribution over an array of speakers wrapped around the sides and back of the theater These same speakers may also be driven from fou
19. PO PO PO PO PO VC Echo x M 10 GL1 M 2 P 4 P 6 M 10 Y P 6 M 6 M 10 8 P 12 TO Delay 19 4 1 12 9 19 4 22 6 29 0 6 5 9 7 25 3 8 Y 35 5 CO Filter 0 71875 0 59375 1 0 28125 0 40625 L S 9 5 ZCD27 RD32 029 2 MM D01 REFERENCE 3 i551 VOLTAGE CD22 GENERATION From Input LPF gt DIGITAL DELAY 2 T8 T7 T6 5 TA T3 T2 T1 gt To LPF Output For FRONT ch DC26 HH 4 To LPF Output MICROCOMPUTER I UNES REAR ch INTERFACE T SCI 5 A A A From Bus convert ICD04 NOTES SECTION A V SWITCHING CIRCUIT 6 1 1 OUTLINE The A V switching circuit selects the desired video and audio signals from the various inputs Itis controlled by the microcomputer through bus 2 IN OUT TERMINALS TUNER INPUT U V Tuner Main U V Tuner PIP EXTERNAL INPUT VIDEO 1 With S terminal VIDEO 2 VIDEO 3 Front With S terminal OUTPUT VIDEO OUTPUT V L R AUDIO ON SUB PICTURE 3 CIRCUIT OPERATION This circuit consists of A V SW IC TA1218N and selects signals from U V tuner Main U V tuner PIP E1 E2 and E3
20. Pin 14 is tied to ground for the negative phase of the MOS FET configuration The Primary winding of T862 and C870 are connected in series to form an LC Series Resonant Circuit The converter transformer which is driven by a push pull MOSFET configuration located in side Q801 operates in forward mode and very little noise In the case of a short on the load side of T862 the AUDIO OUTPUT Low B and B circuits are protected with F899 F890 and F470 respectively F860 is used to protect the primary side of T862 The automatic voltage control operation is performed by the detection of the B voltage 125V fed into the error amp Pin 5 of IC Z801 then output through Pin 3 to the photo coupler Next this signal is fed into the primary Os cillating OSC circuit located inside IC Q801 Pin 6 which controls the frequency of the ON OFF time via an internal logic IC for the MOS FET configuration 17 4 R861 AW Y 0862 0864 876 0876 1863 _ TAN F860 IC Q801 STR Z3201 17 4Vdc 89Vdc 78 0 78Vdc R871 4 R864 C862 R867 AW SG G H VIN 150 160Vdc F890 OUT F899 15 F470 72 6Vdc pp L 2 pao 38Vdc PE po Bs 125 FEA S C870 T862 14 7801 dc PHOTO AS COUPLER L864 Q862 Figure 17 3
21. Q404 ABL T401 I 1 E C463 2 deflection coil 77 L462 LA63 L464 412 Raat 1000 C423 1H 15 75KHz Fig 12 17 12 14 5 1 1 210V For the flyback period pulses are stacked up to DC 125V with FBT and the voltage is rectified by D406 and filtered by C446 5 1 2 35V 12V Pin 4 of the FBT is grounded and the shaded area of negative pulse developed for opposite period of the flyback period is rectified thus developing better regulation power supply 5 1 3 27V As a power for the DPC circuit a negative pulse signal is rectified by D460 and filtered with C460 thus developing the 27V 5 1 4 High voltage Singular rectification system which uses a harmonics non resonant type FBT is employed and a better high voltage regulation is obtained so amplitude variation of pictures becomes low Q 0 gt Picture tube anode Primary Picture tube capacitor Auxiliary ya 1222277 Fig 12 18 a T 35V Zr 0 6 For 12V Fig 12 19 yo Stacked gt pulse of 4 block 1H 15 735KHz Fig 12 20 12 15 5 2 Operation Theory of the Harmonic Non Resonant System and Tuned Waveforms The high voltage coil is of film multi layer winding type and the coils are isolated into seven blocks Each blockis connected through a diode The basic operation is described i
22. The lens system consists of a main lens 3 pieces of lens C lens and the face plate of inverted yCRT used as a lens and realizes a short focus optical lens system with less quantity of lens With the short focus optical system employed the depth of the unit is reduced by about 30 thus making the unit slim and compact Liquid coolant Plastic lens Negative radius phospher IN OM 7 High bright electrostatic focus CRT Glass lens Black coating Fig 16 12 LENSES TP48C60 61 DELTA 77 TW56D90 DELTA 79 2 5 1 Optical Coupling Effect Note When making adjustments on the neck components it is always best to use dedicated drivers made of non magnetic material to avoid any distortion while making adjuctments Optical focus will be made according to the procedures shown below After completion of the electrical and optical focus adjustments convergence adjustments should be made Loosen screws and adj ust the lens focus at the best position by moving lenses left and right Fig 16 13 Lens focus adjustment Projection tube Deflection yoke Mounted projection tube Velocity modulation coil V M Coil Fig 16 14 Mounting position of deflection yoke and V M coil 2 6 Focus Adjustment 1 Turn on the static convergence switch and receives cross character signal 2 For easy adjustment project one color to be adjusted atatime on the screen O
23. decoder 2 Reducing of DAC elements employment of rudder type DAC temperature compensation circuit 3 Deletion of chroma CW ACC employment of 90 degree shift phase circuit with automatic adjustment Newly employment NPN Tr area ratio to former gt Increasing of power consumption 22 power supply system 5V 9V Employment of new circuit 8 3 VCD BLOCK DIAGRAM TA1222N z z 5 n 7 V Sep YIN CHROMA IN GND 9v APC FILTER X tal 1 3 58MHz X tal 2 PAL X tal 3 PAL S AFC1 S 3 5 VCD 3 BLK AFC BENDING CORRECTION 5 8 I GND DEF VCC DEF QIN COLOR LIMITER pac 2 6 pac 2 6 SECAM CONTROL FOR SECAM CLAMP f CONTRAST 4 82 EN 85 RIN 87 OSD BIN OSD AMP 38 OSD G IN OSD RIN YS SW Ys IN PEAK ACL DET ABCL AMP ABL IN O Q COLOR IDENT 1H DL CONTROL CW OUT FOR PAL HD OUT EXT EFP IN SAND CASTLE HD OUT BLACK EXPAND MATRIX SCP OUT 8 4 VCC 98 GND SECTION IX PIP MODULE 9 1 PMUS 02H SN 23148232 B Y OFFSET R Y OFFSET TINT 4V YS OV NC
24. e a 12xA 14xB 2mm 48 inches 4 3 Screen size Horizontal 975mm Vertical 732mm Dimension A 80 9mm Dimension B 48 8mm Fig 15 4 15 6 5 KEY FUNCTION REMOTE CONTROL UNIT MOVES SLESORLNE TOGGLES CURSOR BETWEEN COLORS CURSOR LOCK UNLOCK MOVES CURSOR LINE MOVES CURSOR LINE RIGHT ENTER CONVERGENCE MODE amp SAVE MOVES CURSOR LINE RED CRT ON OFF GREEN CRT BLUE CRT ON OFF ON OFF j o I 00 gt Fig 15 5 6 CONVERGENCE OUTPUT CIRCUIT 6 1 Outline This circuit current amplifies digital convergence correction signal at output circuit and drives by convergence yoke to perform picture adjustment Digital convergence output signal 6ch adjustment is done V R G B 6 2 Circuit Description 6 2 1 Signal flow Signal which is corrected by digital convergence is output to P708 V H R G B is input to Q751 V R G B and is output to P713 P714 and P715 is input to Q752 H R G B and is output to P713 P714 and P715 6 2 2 Over current protection circuit currents of Power supply 15V 15V and 30V are detected to protect CONV OUT IC from damage due to output short of CONV OUT Current value Normal 15V approx 700mA 30V approx 200mA Detecting curren 15V approx 1 8 or more 30V approx 700mA or more protecting operation 6 2 3 Pump up source CONV OUT IC Q752 H Pin 10 15V H PV Pi
25. itis necessary to see how the MP Matrix encoder works Referring to the conceptual diagram in Fig 5 1 the encoder accepts four separate input signals left center right and surround L C R S and creates two final outputs left total and right total Lt and Rt The L and R inputs go straight to the Lt and Rt outputs without modification and the C input is divided equally to Lt and Rt with a 3 dB level reduction to maintain constant acoustic power The S input is also divided equally between Lt and Rt but it first undergoes three additional processing steps a Frequency bandlimiting from 100 Hz to 7 kHz b Encoding with a modified from of Dolby B type noise reduction c Plus and minus 90 degree phase shifting is applied to create a 180 degree phase differential between the components feeding Lt and Rt It is clear there is no loss of separation between the left and right signals they remain completely independent Not so obvious is that there is also no theoretical loss of separation between the center and surround signals Since the surround signal is recovered by taking the difference between Lt and Rt the identical center channel components in Lt and Rt will exactly cancel each other in the surround output Likewise since the center channel is derived from the sum of Lt and Rt the equal and opposite surround channel components will cancel each other in the center output The ability for this cancellation technique to
26. out 33 Q402 o i D461 R441 H drive Q1 23 83 ANN C463 R411 mure i R410 AR D443 L441 zus dd L461 x 413 1 To High Voltage Regulator Circuit C416 R416 C464 ZZ 17 77 DPC output SIGNAL DEF POWER PCB A 125 v Diode modulator circuit Fig 12 6 12 6 4 1 Theory of Operation 4 1 1 Operation of Basic Circuit 1 To perform the horizontal scanning a 15 734 kHz sawtooth wave current must be flown into the horizontal deflection coil Theoretically speaking this operation can be made with the circuit shown in Fig 12 7 a and b 2 Astheswitching operation of the circuit can be replaced with switching operation of a transistor and a diode the basic circuit of the horizontal output can be expressed by the circuit shown in Fig 12 7 a That is the transistor can be turned on or off by applying a pulse across the base emitter A forward switching current flows for on period and a reverse switching current flows through the diode for off period This switching is automatically carried out The diode used for this purpose is called a damper diode a H output basic circuit H output transistor D Co L O mec A 3 Deflection Damper Resonant yoke diode capacitor Vcc b H output equivalent circuit SW1 Sw2 Co L 3 L L T I e Vcc Fig
27. 12 7 Description of the basic circuit 1 t1 t2 A positive pulse is applied to base of the output transistor from the drive circuit and a forward base current is flowing The output transistor is turned on in sufficient saturation area As a result the collector voltage is almost equal to the ground voltage and the deflection current increases from zero to a value in proportionally The current reaches maximum att2 and a right half of picture is scanned up to this period 2 t2 The base drive voltage rapidly changes to negative at t2 and the base current becomes zero The output transistor turns off collector current reduces to zero and the deflection current stops to increase 3 t2 t3 The drive voltage turns off at t2 but the deflection current can not reduce to zero immediately because of inherent nature ofthe coil and continues to flow gradually decreasing by charging the resonant capacitor CO At the same time the capacitor voltage or the collector voltage is gradually increases and reaches maximum voltage when the deflection current reaches zero at t3 Under this condition all electro magnetic energy in the deflection coil at t2 1s transferred to the resonant capacitor in a form of electrostatic energy 4 t3 t4 Since the charged energy in the resonant capacitor discharges through the deflection coil the deflection current increases in reverse direction and voltage at the capacitor gradually reduces That is
28. 14 5 2 Operation Theory of the Harmonic Non Resonant System and Tuned Waveforms escitas 12 16 6 HIGH VOLTAGE CIRCUIT 12 17 6 1 High Voltage Regulator 12 17 7 X RAY PROTECTION CIRCUIT 12 20 qeL Outline as is 12 20 262 PALO iia 12 20 8 OVER CURRENT PROTECTION CIRCUIT Licencia 12 21 12 21 6 2 Op ration ae 12 21 SECTION XIII DEFLECTION DISTORTION CORRECTION CIRCUIT DPC Circuit 1 DEFLECTION DISTORTION CORRECTION TA8859P 13 2 1 1 Outline i ots 13 2 1 2 Functions and Features 13 2 1 3 Block Diagram 13 2 2 DIODE MODULATOR CIRCUIT 13 3 3 ACTUAL CIRCUIT use 13 4 3 1 Basic Operation and Current Path 13 5 SECTION XIV CLOSED CAPTION EDS CIRCUIT ee 14 2 2 DATA TRANSMISSION FORMAT 14 2 3 DISPLAY FORMAT 14 3 4 CIRCUIT OPERATION 14 4 SECTION XV DIGITAL CONVERGENCE CIRCUIT T OUTLINE ipeo u 15 2 2 CIRCUIT DESCRIPTION 15 2 2 1 2 2222 1 15 2 2 2 Circuit Operation 15 2 3 PICTURE ADJUSTMENT 15 4 3 1 Change of Memory E PROM 15 4 3 2 Service Mode sss iie 15 4 4 ADJUSTING PICTURE DIMENSION Green picture 15 6 5 KEY FUNCTION OF REMOTE CONTROL ornato
29. 181ch e e e e A Uni 42k ITN e P 8key 48 D S 181ch e e e e A Uni 42k O TN P 8key 48 D S 181ch e e e e Intelig EZ O TN P 8key 55 D S 181ch e e e A Univ 42k O ITN e P 8key 55 D S 181ch e A Univ 43k TN P 8key 61 D S 181ch A Univ 43k O TN P 8key 11 Dolby Surround 12 Dig Sound Processor 13 Front Surround 14 Cyclone ABX 15 Sub Bass System Prolo O DSP4ch O DSP4ch O DSP4ch 16 Audio Output 14Wx2 10Wx2 10Wx2 14Wx2 amp 10Wx2 14Wx2 10Wx2 17 Speaker Size amp Nbr 160Rx2 amp REAR SPK 160Rx2 amp REAR SPK 160Rx2 amp REAR SPK U R E 18 Comb Filter 19 Dynamic Focus 20 Scan Velocity Modu 2 Vert Contour Corre 22 Black Level Expand 23 Flesh Tone Correct 24 Dynamic Noise Reduc 25 Picture Preference 26 Digital Convergence DIG O RGB DIG O RGB O 3D Y C 27 Horiz Resolution 28 Parental Ch Lock 29 Channel Label 32ch 30 3 Language Display 31 Clock Off Timer 32 Favorite Channel 33 Extended Data Servi 34 Star Sight Decoder 35 S Video In Term 36 Audio Video In Out 37 Front AV Jack 38 Variable Audio Out 39 2 RF Input 40 Ext Speaker Term 41 PIP Audio Out Jack 42 Center Ch Aud Input e 1 1 1 2 1 e 1 1 1 2 1 O 1 1 1 2 1 43 Speaker
30. 3 1 Composite Video Signal The selected video signal is output to pin 38 of QVOI and separated by comb filter into Y an C The resulted signal is input to pins 30 and 32 of QVO1 and is output to pins 36 and 34 to be supplied to Q501 V C D Video signal for PIP is output to pin 42 of QVOI and is supplied to PIP unit 2 01 3 2 S Video Signal When a cable is connected to S VIDEO terminal inner switch of S VIDEO terminal is shorted to ground to turn off the transistor QV05 for VIDEO1 input for S VIDEO terminal detection Then chroma input terminal Pin 14 for VIDEO input of 01 turns on 6 2 SW CIRCUIT VIDEO 3 VIDEO 1 VIDEO 2 PIP AUDIO OUT JACK TP48E90 ONLY OUT JACK H002 IF MTS A PRO QV01 TA1218N SYNC OUT PIP TV in PIP Lin Y in PIP R in Cin PIP V out HYO1 PIP TUNER IF DSP L R in QA01 SYNC in Cin 0501 Fig 6 1 Vin NOTES SECTION VIDEO PROCESSING CIRCUIT 1 This circuit converts and amplifies video signal Luminance and chroma signals separated into Y C to original color signal and is supplied to CRT Drive circuit 2 SIGNAL FLOW Signal flow chart is shown in figure 6 1 Block diagram 1 2 3 Luminance signal is input to pin 15 of Q501 and enters into delayline inside Q501 to be output to pin
31. 8MHz pulse XOUT SYSTEM CLOCK System clock output 8MHz 8MHz pulse RESET SYSTEM RESET In System reset input In reset L 5V SW IN RMT IN SYNC AVI REMOTE CONTROL SIGNAL INPUT HSYNC INPUT IN In In remote control pulse inputzL External H sync signal input In reception of remote pulse Pulse SCLI IIC BUS CLOCK OUT Out IIC bus clock output 1 Pulse SDAI IIC BUS DATA IN OUT In Out IIC bus data input output 1 Pulse GND OV NC ACP NSYNC INPUT AC pulse input VDD POWER 5V 5 EEPROM QA02 EEPROM Non volatile memory has function which in spite of power off memorizes the such condition as channel selecting data last memory status user control and digital processor data The capacity of EEPROM is 8k bits Type name is 24LCO8BI P or ST24C08CB6 and those are the same in pin allocation and function and are exchangeable each other This IC controls through PC bus The power supply is common to the EEPROM and the main MICOM Pin function of EEPROM is shown in Fig 3 3 EEPROM QA02 1 8 Vcc 5V Device address GND 1 2 7 NC A2 3 6 SCL 12C BUS line Vss 4 5 SDA Fig 6 ON SCREEN FUNCTION 3 3 ON SCREEN FUNCTION indicates data like channel volume Formerly exclusive use of OSD IC was used but in N5SS the OSD function is within the main microcomputer Pin fun
32. Box O 55 5 94 O 55 5 94 O SS SR94 Cabinet NEW NEW NEW PARTS SUPPLY ISO 1 3 5 FRONT AND REAR CONTROL VIEWS 5 1 Front View POWER indicator Y Press to open the door Remote sensor location POWER button Behind the door Fig 1 1 ANT VIDEO button ADV button IN VIDEO 3 S VIDEO VIDEO AUDIO L MONO R CHANNEL VIDEO AUDIO INPUT MENU buttom jacks CHANNEL Y A DEMO button butttons S VIDEO INPUT jack VOLUME w a buttons buttons These buttons have dual functions Fig 1 2 5 2 Rear View S VIDEO INPUT jack 1 5 TV rear VARIABLE AUDIO OUTPUT jacks ox OUT A se d VIDEO 1 INPUT jacks EXTERNAL SPEAKER terminals VIDEO 2 INPUT MAIN jacks SPEAKER VIDEO AUDIO switch OUTPUT jacks Fig 1 3 5 3 Remote Control View Transmit indicator EDS TV CABLE VCR switch TV VIDEO Channel Number PIP function AUDio PICture RESET C CAPT ANT1 2 EXIT To operate buttons inside the cover slide the cover down and toward you P 7 STA d Fig 1 4 VEIHSOL TIMER Clock POWER RECALL MUTE CHANNEL V A RTN VOLUME w a VCR function SET UP OPTION
33. PROCEDURE 1 Press once MUTE key on the remote hand unit to indicate MUTE on screen of the television 2 Press the MUTE key of remote hand unit again and keep depressed while depressing the MENU key on the front of the unit During service mode indication S is displayed at upper right corner on screen 10 TEST SIGNAL SELECTION In OFF state of test signal SGA terminal Pin 20 and SGV terminal Pin 21 kept at a L condition Thefunction of VIDEO test signal selection is cyclically changed with each depression of the VIDEO key on the remote control unit Table 3 2 Test Signal No Name of Pattern 0 Signal OFF 1 All black signal R single color OSD 2 All black signal single color OSD 3 All black signal B single color OSD 4 black signal 5 white signal 6 WIB P Black cross bar 8 White cross bar 9 Black cross hatch 10 White cross hatch 11 White cross dot 12 Black cross dot 13 H signal bright area 14 H signal dark area 15 Black cross G 3 SGA audio test signal output should be square wave of 1kHz 3 9 Self check display 11 SERVICE ADJUSTMENT ADJUSTMENT MENU INDICATION ON OFF MENU key on TV set During display of the adjustment menu the following functions are possible a Selection of adjustment item POS UP DN key on TV remote unit b Adjustment of each item VOL UP DN key on TV r
34. Pd VLA 1 1 0 0 er IDC gt Alo VB 0 C4 IY1 IP1 C2 0 C2 IY2 IP2 1 1 1 1 V V N N A 4 C3 2 1 1 0 y Fig 13 10 3 1 3 Later Half of Flyback Period All energy in the coil has been transferred to the resonant capacitors at the center of the flyback period and the voltage shows the maximum value However during next half of the flyback period the energy of the resonat capacitor is discharged as a reverse current through respective coil When the discharge has been completed VA and VB becomes zero and the deflection current in reverse direction becomes the maximum VA L O P T Loy ly le von 1 2 mad Cs al N 4 A A y lv2 NIE 1 Y Uxor 111 1 VB VB js ym 3M X y A A m T Csm L e 2 Fig 13 11 P4 rdi i 7 ly 0 Pid 1 5 4 A A VA 0 o e VB 0 IU Y 1 1 IY1 IP1 1 E C2 0 i IY2 IP2 IP2 ly1 M 0 Fig 13 12 13 6 3 1 4 First Half of Scanning Period When the flyback period completes the damper diode DD and the modulation diode DM turn on and the Iy and Im proportionally decrease from the ma
35. Protect active high VA VW 4 To Pin 14 of Z801 R849 D860 D861 Figure 17 12 30V 15V Over Voltage Protect Circuit Located on Convergence Out Power2 Board 5 1V 412V o 14 e D854 15V Oo R877 D866 R873 ov P R879 0 7V Spes D867 gt R874 R880 Y R875 14 9V Protect active high 15V 15V 777 To Pin 14 of 7801 14 8V Q854 R876 Figure 17 13 15V 15V Under Voltage Protect Circuit Located on Convergence Out Power2 Board 17 13 9 4V e Q352 OV CRT PROTECT Protect active high To Pin 14 of Z801 Figure 17 14 200V Under Voltage Protect Circuit Located on Convergence Out Power2 Board D471 R472 To X RAY 4 AAA o Q757From X RAY Pin 13 Z801 n Pin 9 of T461 23V C471 Figure 17 15 X Ray Protect Circuit Located on Deflection Power Board 17 14 4 POWER SUPPLY SHUTDOWN CIRCUITS SECTION 1 VOLTAGES UNDER NORMAL CONDITIONS Place the unit in the service position by removing the chassis light box and place it on its side in an upright position with the power cord up See FIG 17 16 Connect a signal to the ANTI input You may want to refer to the actual schematic diagram for a clearer understanding of the circuitry PROTECT CIRCUIT MEASUREMENTS 1 Connect the lead of the peak hold meter to pin 17 of Z801 See FIG 17 16 1 and record the DC voltages on the following pins PIN 11 PIN 13
36. Some device may have no data or may have data with several bytes continuing Fig 3 1 3 3 GND BAL REM OUT MUTE SP MUTE NC POWER LED NC NC r SCLO BUS L SDAO SYNC VCD NC AFT2 AFT1 KEY A KEY B SGV SGA GND 10 11 12 13 14 15 16 17 18 19 20 21 4 MICROCOMPUTER TERMINAL FUNCTION 87 538 3152 01 GND P40 PWMO P41 PWM1 P42 PWM2 P43 PWM3 P44 PWM4 P45 PWM P46 PWM6 P47 PWM7 P50 PWM8 TC2 P51 SCL1 P52 SDA1 P53 AINO TC1 P54 AIN1 P55 AIN2 P56 AIN3 P60 AIN4 P61 AIN5 P62 P63 VSS Fig 3 2 VDD P57 P32 P57 SDAO SCLO TC3 P31 RXIN P30 P20 RESET XOUT XIN TEST 05 2 05 1 VD HD 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VDD ACP NC GND SDA1 uc BUS SCL1 SYNC AV1 RMT IN SW IN RESET XOUT XIN TEST 05 1 05 2 VSYNC HSYNC Ys BOUT GOUT ROUT lt lt MICROCOMPUTER TERMINAL AND OPERATION LOGIC gt gt Terminal Name Function In Out Logic Remarks GND OV BAL INPUT BALANCE Out PWM out REM OUT REMOTE CONTR
37. anus Fig 13 6 3 1 Basic Operation and Current Path 3 1 1 Later Half Scanning Period When the power is turned on the power supply voltage VB 1s applied to Cs and Csm and the Cs acts as a power source for a later half of the scanning period for which the H OUT transistor is turned on and the deflection current Iy flows in the path as shown below VA FBT 1 m yy VB DM H E H H H H H Fig 13 7 Voltage 8 current waveform in H period i 1 1 014 N 1 1 M Pd 1 M M Y VA o oT IDC 227 1 Moor WP VB 0 T 1 NA NA Fig 13 8 13 5 3 1 2 First Half Scanning Period When the base drive current decreases and the H OUT transistor is turned off each of the energies stored in LDY Lm Lp of FTB is transferred to C2 and respectively and the resonant current becomes zero at a center of the flyback period Then VA and VB pulses show a maximum amplitude VA FBT EE AE os 7 t E E m1 JY VR J um 2 ES Y 122 id ow Y D A DEN Ep VB VB 18 zum Y 1 lt D CSM L I Fig 13 9 t ly 0 i gt
38. band low band balance control Fig 2 3 shows a block diagram of the A PRO IC 3 Sound volume control cyclone level control 4 Cyclone ON OFF TA1217N Go 9 US BALANCE TONE CONTROL Center LEVEL VOLUME Woofer LEVEL SAP Ident STE Ident 7 Ey 2 22 9 le le 2 7 2 SCL1 SDA1 W out C out i Jed From From From to Q601 to Q641 to 0601 to Q601 AN Dolby AV SBS Via QS101 Fig 2 3 A PRO block diagram 2 4 Configuration of the audio circuit and signal flow given in Fig 2 4 VIF MTS S PRO MODULE FOR PIP IF MODULE O AUDIO Ly PIP OUT TP48E90 ONLY OUTPUT OR AUDIO R VIF MTS A PRO MODULE Fig 2 4 2 5 2 PIP TUNER Lable Name Lot No TUNER SAW VIF SIF SECTION FILTER CIRCUIT AFT VIDEO AUDIO OUTPUT OUTPUT OUTPUT Fig 2 5 Terminal No 32V S CLOCK S DATA NC ADDRESS 5V RF AGC 9V AUDIO GND AFT NC GND VIDEO 2 1 Outline The PIP tuner EL922L consists of a tuner and an IF block integrated into one unit The tuner receives RF signals induced on an antenna and develops an AFT output video output and audio output The tuner has receive channels of 18
39. current improves efficiency of the circuit That is about a half of deflection current one fourth in terms of power is sufficient for the horizontal output transistor 12 8 9 00060 base voltage TR base current TR collector current D damper current SW2 Switch current TR SW1 Resonant capacitor current Co Deflection current Lo TR collector voltage 01346 t6 Fig 12 8 Amplitude Correction To vary horizontal amplitude it is necessary to vary a sawtooth wave current flowing into the deflection coil These are two methods to vary the current a method which varies Luby connecting a variable inductance L in series with the deflection yoke and a method which varies power supply voltage across S character capacitor for the deflection yoke As the DPC circuits is used in the this chassis the later method which varies the deflection yoke power supply voltage by modifying the bus data is used 4 1 2 Linearity Correction LIN 1 S curve Correction S Capacitor Pictures are expanded at left and right ends ofthe screen even ifasawtooth current with good linearity flows in the deflection coil when deflection angle of a picture tube increases This is because projected image sizes on the screen are different at screen center area and the circumference area as shown in Fig 12 9 To suppress this expansion at the screen circumference it is necessary to
40. d SPEAKERS E REAR AMP Figure 1 8 Audio Signal Flow Block Diagram 1 11 10 The E model PTVs actually have three separate power supplies as shown in Figure 1 9 These supplies consist of the Standby Supply the Main Switch Mode Supply and the Sub Switch Mode Supply The Standby Supply provides the 5 VDC needed to run the microcomputer and the customer interface controls such as the key pad and the IR receiver When the set is turned on the switch closes to activate the two switch mode supplies and provide the numerous DC voltages needed to operate the set STANDBY REGULATOR POWER ON OFF FROM MICROCOMPUTER SENSING 5VDC RESET POWER SUPPLY AND PROTECTION BLOCK DIAGRAM The Control Protection circuit 7801 has two functions The first is to regulate the Main Switch Mode Supply and the second is to monitor over current over voltage and under voltage sensors throughout the set If any one of these sensors activates the protection circuit Z801 turns off the switch powering the two switch mode supplies thus turning off the set If this occurs a red LED on the front panel flashes at half second intervals and the set must be unplugged to reset Z801 MICROCOMPUTER 5VDC ac asc amo OVERCURRENT OVERVOLTAGE amp UNDER VOLTAGE SENSING Figure 1 9 Power Supply Protection Block Diagram 11 HORIZONTAL AND VERTICAL DEFLECTION Deflection circuitry in the
41. green cross hatch pattern the same way you aligned the green with the cross hatch pattern on the template BLUE CONVERGENCE 1 2 3 Push the 100 button to turn off the red tube RTN to turn on the blue tube Push the 3 button until the blue cursor appears Align the blue cross hatch pattern to the green cross hatch pattern in the same manner Push the 100 button to turn on the red tube and check the convergence with all three tubes on The cross hatch pattern should be white with no red green or blue present However depending on how much the blue tube is defocused a slight blue halo may show 15 11 5 Push the 7 button then the power button to save the settings and exit the service mode ELECTRICAL CENTERING 1 2 Disconnect all video cables in the video 1 input Put the set in the service mode Push the TV VIDEO button on the remote until the white cross hair pattern on a black background is displayed Check the centering of the cross hair pattern with the centering tabs in the bezel If the horizontal position is off push the channel up button until the HPOS register appears Use the volume button to center the pattern If the vertical position is off push the channel up button until the VPOS register appears Use the volume button to center the pattern Push the TV VIDEO button until the TV picture is displayed then turn the power off Turn the set on and check the pict
42. in combination with a V C D IC TA1222N which has a V pulse output performs correction for various deflection distortions and V output under PC bus control All the PC bus controls are carried out by a microcomputer and can be controlled with the remote control 1 2 Functions and Features The IC has functions of V RAMP voltage generation V amplitude automatic switching 50 60 Hz V linearity correction V amplification EHT correction side pincushion correction IC bus interface etc and controls following items through the I2C bus lines 1 V amplitude 2 V linearity V S character correction V picture position neutral voltage setting V M character correction V EHT correction H amplitude L and R pin cushion distortion correction I entire area L and R pin cushion distortion correction II corner portions at top and bottom 10 H trapezoid distortion correction 11 H EHT correction 12 V AGC time constant switching 3 4 5 6 7 8 9 1 3 Block Diagram Fig 13 1 shows a block diagram of the basic circuit Waveform Shape Trigger Det V Trigger in 3 V AGC Time Constant SW V M Character V Linearity Correction Correction Bus Control Signal SDA SCL Control Through Bus H Trapezoid Distortion Correction L R Pincushion Distortion Corre
43. in the set with the service registers via the remote control SECTION ONE VIDEO TEST SIGNALS 1 Verify that the unit is connected to an AC supply and that a signal is connected to the ANT 1 input 2 Enter the service mode by pressing mute on the remote Press and hold mute a second time while pressing menu on the control panel An S appears in the upper right corner of the screen indicating that the set is in the service mode Press menu and the RCUT register appears in the upper left corner of the screen 3 Push the TV VIDEO button on the remote once to enter the internal test pattern mode The screen should be red 4 Slowly cycle through the test signals with the TV VIDEO button until the white cross hairs on a black background appear If the TV VIDEO button is pushed in rapid succession the set will jump out of the test signal mode to one of the inputs ANT 1 VIDEO 1 VIDEO 2 or VIDEO 3 The set is still in the service mode so if this occurs push the menu button then the TV VIDEO button to get back into the test signal mode 5 Plug a video cable into the VIDEO 1 input jack make sure the other end of the cable is not plugged into a video source 6 What happened to the cross hairs 7 If something did happen to the cross hairs why did it happen 1 20 8 9 10 Is there video on the screen If there is video on the screen where does it come from Unplug the video cable SECTION TWO AUDIO
44. is dedicated for communication with the non volatile memory 2 OPERATION OF CHANNEL SELECTION CIRCUIT An 8 bit Toshiba microcomputer series TLCS 870 is used within the television as ICAOI TMP87CS38N 3152 or similar is employed With this microcomputer each IC and circuit shown below are controlled Part number 1 CONTROL OF AUDIO SIGNAL PROCESS IC QNO6 Toshiba TA1217N Adjustments for volume treble bass and balance Selection between surround mode and DSP mode and level adjustment Level adjustment of BAZOOKA Sub Bass system Audio muting during channel selection or no signal reception 2 CONTROL OF VIDEO CHROMA DEF SIGNAL PROCESS IC Q501 Toshiba TA1222N Adjustments for uni color brightness tint color gain sharpness and PIP uni color Setting of adjustment memory values for sub brightness sub color and sub tint etc 3 2 3 4 5 6 7 8 9 Setting of memory values for video parameters such as white balance RGB cutoff GB drive and ccorrection etc Setting of video parameters of video modes Standard Movie Memory CONTROL OF A V SWITCH 01 Toshiba TA1218N Preforms source switching for main screen and sub screen Performs source switching for TV and up to three video inputs CONTROL OF NON VOLATILE MEMORY IC 02 Microchip 24LCOSBI P Memorizes data for video and audio signal adjustment values volume and woofer adjustment values e
45. it is differentiated in the waveform shape circuit and only the falling part is detected by the trigger detection circuit to the waveform generation circuit is not susceptible to variations of input pulse width The pulse generation circuit also works to fix the V ramp voltage at a reference voltage when the trigger pulse enters so it can prevent the sawtooth wave start voltage from variations by horizontal components thus improving interlacing characteristics WAVEFORM SHAPE 5Vp DC 0V 11 3 2 3 V Output and supplies sawtooth waveform current to a deflection 2 3 1 Circuit Operation yoke Q3 turns on for first half of the scanning period The V output circuit consists of a V driver circuit Q302 and allows a positive current to flow into the deflection Pump up circuit and output circuit Q301 and external yoke Q3 gt C306 R305 gt GND and Q4 turns circuit components on for last half of the scanning period and allows a 1 Q2 amplifies its input fed from pin 4 of Q301 Q3 Q4 negative current to flow into the deflection yoke output stage connected in a SEPP amplifies the current R3059 C306 9 DY 04 These operations are shown in Fig 11 5 35V D301 0308 D308 l 0301 6 3 R308 d C306 R305 Q4 ON Fig 11 5 V output circuit 2 InFig 11 6 a the power is expressed as a fixed level and the positive and negative current flowing i
46. left side and effect of resistance of the deflection coil for later half period of scanning screen right side That is the deflection current becomes a sawtooth current with bad linearity resulting in reproducing of asymmetrical pictures at left and right sides ofthe screen left side expanded right side compressed When ahorizontal linearity oil L1 with acurrent characteristic as shownin figure cis used left side picture will be compressed and right side picture will be expanded because the inductance is high at the left side on the screen and low at the right side The left right asymmetrical correction is carried out in this way and pictures with good linearity in total are obtained a La FBT Deflection D od iH Vcc Li Cs S character capacitor b Deflection coil current Deflection coil current iH Resistance of Ly J lt Characteristic of D Left Right c Linearity coil characteristic Linearity coil characteristic Inductance AE Left Right gt Current A Fig 12 11 Linearity coil 3 LH E 3 b Sawtooth wave current Fig 12 12 4 2 White Peak Bending Correction Circuit 4 2 1 Outline White peak area in screen picture may sometimes cause bending in picture See figure below TP48E60 series correction signal which consists of video signal and video ripple in video output circuit power supply 200V is in
47. maintain high separation between center and surround signals requires the amplitude and phase characteristics of the two transmission channels to be as close as possible For instance if the center Left id Center Surround O DOLBY NR 90 DEG ENCORDER 90 DEG Right Fig 5 1 Conceptual Dolby Stereo Dolby Surround encoder channel components in Lt are not identical to the ones Rt as aresult of a channel balance error center information will come out of the surround channel in the form of unwanted crosstalk 3 THE DOLBY SURROUND DECODER This leads us to the original Dolby Surround decoder The block diagram in Fig 5 2 shows how the decoder works Exceptforlevel and channel balance corrections the Ltinput signal passes unmodified and becomes the left output The Rt input signal likewise becomes the right output Lt and Rt also carry the center signal so it will be heard as a phantom image between the left and right speakers and sounds mixed anywhere across the stereo soundstage will be presented in their proper perspective The center speaker is thus shown as optional since itis not needed to reproduce the center signal The L R stage in the decoder will detect the surround signal by taking the difference of Lt and Rt then passing it through a 7 kHz low pass filter a delay line and complementary Dolby noise reduction The surround signal will also be reproduced by the left and right speakers b
48. picture VLIN 8 Select the WID register and vary its value 8 steps above and below the recorded value Describe its effect on the picture WID 9 Select the STRH register and vary its value 8 steps above and below the recorded value Describe its effect on the picture STRH SUMMARY Now that you have completed Lab 2 you should be able to use the internal video and audio test signals the self diagnostic feature and the service registers for making adjustments END OF LAB 2 1 24 SECTION II TUNER IF MTS S PRO MODULE 1 CIRCUIT BLOCK H002 IF MTS A PRO Module MVUS34S EL466L SIF output Sound H90 d 1 Multiplex A PRO Circuit iter Circuit Main Tuner RF AGC BEEN R IN L IN TP12 TV TV Video output R OUT L OUT 2 Sa C OUT AFT output To A V switch circuit L OUT b Fig 2 1 Block diagram 1 1 Outline 1 RF signals sent from an antenna are converted into 5 VIF SIF circuit uses PLL sync detection system to intermediate frequency band signals video 45 75 MHz improve performances shown below audio 41 25 MHz in the tuner Hereafter these signals Telop buzz in video over modulation are called IF signals DP DG characteristics video high fidelity 2 The IF signals are band limited in passing through a reproduction SAW filter Cross color characteristic coloring phenomenon at 3 The IF signals band limited are detected in the VIF color less high frequency
49. set the deflection angle to alarge value rapidly deflecting the electron beam at the screen center area and to set the deflection angle to a small value scanning the electron beam slowly at the circumference area as shown in Fig 12 9 In the horizontal output circuit shown in Fig 12 10 capacitor CS connected in series with the deflection coil LH is to block DC current By properly selecting the value of CS and by generating a parabolic voltage developed by integrating the deflection coild currentacross the S capacitor and by varying the deflection yoke voltage with the voltage the scanning speed is decreased at beginning and end of the scanning and increased at center area of the screen The S curve correction is carried out in this way thereby obtaining pictures with good linearity 12 9 S character correction TR Qa t2 t1 t2 t1 t2 gt t1 25 1 2 1 6 Fig 12 9 Cs Deflection coil Vcc 8 H output circuit b Sawtooth wave current c Voltage across LH Fast deflection Si Slow deflection d Synthesized current Fig 12 10 2 Left right Asymmetrical Correction LIN coil In the circuit shown in Fig 12 11 a the deflection coil current 1H does not flow straight as shown by a dotted line in the figure b if the linearity coil does not exist by flows as shown by the solid line because of effect of the diode for a first scanning screen
50. signal objects circuit to develop video and AFT signals 6 HIC SBX1637A 22 is used in the audio multiplexer 4 The band limited IF signals are detected in the SIF circuitto minimizethe size with increased performance circuit and the detected output is demodulated by the 7 As a sound control processor TA1217N is used PC audio multiplexer developing R and L channel outputs bus data control the DAC inside the IC to perform These outputs are fed to the A V switch circuit switching of the audio multiplexer modes 5 sound processor S PRO is provided 1 2 Major Features 1 2 3 4 The VIF SIF circuit is fabricated into a small module by using chip parts considerably As the tuner EL466L that which contains an integrated PLL circuit is employed Wide band double SAW filter F1802R used FS frequency synthesizer type channel selection system employed 1 3 Audio Multiplex Demodulation Circuit The sound multiplex composite signal FM detected in the PIF circuit enters pin 12 of HIC hybrid IC in passing through the separation adjustment VR RV2 and amplified After the amplification the signal is splitinto two one enters a de emphasis circuit and only the main signal with the L R signal and a SAP signal removed enters the matrix circuit At the same time the other passes through various filters and trap circuits and the L R signalis AM demodulated and the SAP is FM demodulated MVUS34S Monito
51. the electrostatic energy in the resonant capacitor is converted into a electromagnetic energy in this process 5 t4 When the discharge is completed the voltage reduces to zero and the deflection current reaches maximum value in reverse direction The t2 t4 is the horizontal flyback period and the electron beam is returned from right end to the left end on the screen by the deflection current stated above The operation for this period is equivalent to a half cycle of the resonant phenomenon with L and CO and the flyback period is determined by L and CO 6 4 6 For this period CO is charged with the deflection current having opposite polarity to that of the deflection current stated in 3 and when the resonant capacitor voltage exceeds VCC the damper diode D conducts The deflection current decreases along to an exponential function approximately linear curve and reaches zero at t6 Here operation returns to the state described under 1 and the one period of the horizontal scanning completes For this period a left half of the screen is scanned In this way in the horizontal deflection scanning a current flowing through the damper diode scans the left half of the screen the current developed by the horizontal output transistor scans the right half of the screen and for the flyback period both the damper diode and the output transistor are cut off and the oscillation current of the circuit is used Using the oscillation
52. the left and right signals just before Q601 to increase the signals bass jumper is removed so a center signal can be switched in to replace the main left and right signals The amplified left and right audio signals are applied to the internal external speaker switch and routed to the desired speakers Sets equipped with Dolby or Dolby Pro Logic have a surround audio signal that is sent to the audio processor in H002 from the Dolby circuit The surround signal is then sent to the rear amplifier Q641 amplified and applied to the rear speakers In the TP48E90 the surround signal is routed through an amplifier in Q690 before it is applied to 0641 Also the TP48E90 is equipped with Dolby Pro Logic and has a center channel The center channel is amplified by the Center Amplifier Q621 and applied to the front speakers through the internal external speaker response In 55 80 81 and 61 80 models the switch L Le VIDEO 2 TEST SIGNAL VIDEO 1 L R gt R VIDEO 3 MONO AUDIO FROM HY01 L TOPIPOUT JACK PIP TUNER R TP48E90 ONLY QV14 FROM H001 gt gt A gt OUTJACK FRONT SURROUND SURROUND TP48E90 DSP DOLBY TP55E80 81 TP61E80 DOLBY PRO LOGIC CENTER AMP R TO VARIABLE AUDIO L OUT JACK TO FROM CENTER INPUT SWITCH amp JACK 55 80 81 8 61 80 TP48E90 ONLY gt 5 __TP48E90 ONLY 12 t REAR
53. the resonant capacitor in a form of current Iy In this case the current is split into two Iyl passing through C3 and Iy2 passing through C2 In the same way the energy stored in the primary winding of the FBT is transferred to the resonant capacitor in the form of Ip In this case the current path is also split into two passing through and Ip2 passing through C2 C3 Concequently the current differences between 1 and Ip2 1 1 1 2 passes through When the high voltage current IH reduces with a dark picture the current Ip in the primary circuit decreases so 1 1 and Ip2 also decrease However a current flowing into Iy1 Ip2 increases as Ip2 decreases As a result the pulse developing at the point B increases and the voltage Vm at Csm also increases as shown in Fig 13 8 That is when a dark picture appears the voltage across S curve capacitor Cs increases as shown in Fig 13 8 the high voltage rises and the horizontal amplitude is going to decrease But as Vs increases the deflection yoke current increases and this works to increase the horizontal amplitude Accordingly if the brightness of a picture changes the horizontal amplitude is maintained at a constant value rom FBT el gt y IH H Loy Qs 1 Cs ly AL Vs C2 VB NN Lm y 2 1 Fig 13 5 VB VS 0 Y
54. to 0501 where they are mixed with the main video signal 0 org LUSIS OPIA 0317 VIDEO 1 12 gt RED CRT DRIVE VIDEO 2 01 E032Z GREEN DRIVE PO e ISWITCHING E033Z gt BLUE CRT ANT 1 R G B DRIVE RF OUT ANT2 MAIN VIDEO INPUT CONTROL FROM VIDEO CHROMA DEFLECTION PROCESSING OUT JACK TEST SIGNAL DIGITAL NEU TO VIDEO 1 COMB FILTER QAOI OR 3D Y C DIGITAL MICRO u OSD EDS CC amp OSD EDS CC CONVERGENCE RGB SW VIDEO INPUT 9 AUDIO SIGNAL FLOW BLOCK DIAGRAM Audio Signal Flow Audio signals are applied to the AV Switcher from the three video jacks 002 and the PIP Tuner as shown Figure 1 8 Like the video signal there must not be a connector in the video 1 jack for the audio test signal to be applied to the AV Switcher In the 48 90 PIP audio is applied to the PIP output jack The main audio signals are applied to the audio output jacks and to the Front Surround circuit the DSP Dolby circuit or the Dolby Pro Logic circuit Afterprocessing the left and right audio signals are applied to the audio processor in H002 where the volume balance treble and bass are controlled Next the audio signals are amplified by QS101 and applied to the variable output jacks and Q601 If the sub bass system SBS is selected a signal is mixed with
55. type sync system However if the synchronization for the H oscillator is carried out with this method the H oscillator synchronizes with external noises and the H synchronization will be disturbed To prevent this an output of the H oscillator is compared with a reference H sync signal to detect deviations of frequency and phase The H oscillator is automatically controlled with the detected output averaged This circuit is called an AFC circuit In the N4SS chassis a conventional AFC circuit is not employedbutanew double AFC circuit built in the TA1222N is used Fig 10 3 shows the AFC circuit and the block diagram of the circuit SYNC SEPARATION CIRCUIT PHASE DETECTION CIRCUIT H COUNT DOWN DIVIDING AFC LOOP First phases of a 32 fH counted down signal and a H sync signal contained in broadcasting signal are compared in the AFCI loop and the loop develops an H pulse signal for the AFCII loop That is when a phase deference 01 exists in comparison of the phase of fH signal developed by counting down the 32 fH signal and the phase of H sync signal of the broadcasting signal an error signal corresponding to the phase different is detected and a correction voltage corresponding to the error output is generated With this correction voltage the 32 fH oscillator circuit is controlled The correction control voltage for the oscillator varies in direction of positive or negative corresponding to phase lead or lag of
56. voltage Ep and a 9V reference voltage developed by a 3 terminal regulator Q420 are compared When the Ep increases the voltage at pin 2 of Q483 differential amplifier also increases and the base current Is of the high voltage transistor Q480 increases As a result Q480 collector current increases and Q480 collector voltage at the point B decreases Then a peak value of C418 is clamped by the diode D443 at the collector voltage lowered and the collector voltage Vcr of Q404 H output transistor obtained as a sum ofthe voltage Vcr across C443 and 2 across L418 decreases Then the high voltage also decreases When the high voltage lowers the corrective operation is carried out in reverse order Resustors R451 R452 R453 and R455 are used to correct undersirable influence H amplitude increase at minimum In by the H amplidude regulator Horizontal ld C443 output Nr jus I c44 CSL R466 C467 D461W 3 L461 R461 R469 77 77 4 bns 5 0460 N Q483 777 777 D443 R451 R452 ou PTT C418 sl Q480 25222 ANN R492 777 487 Fig 12 25 Actual high voltage regulator circuit 12 19 7 PROTECTION CIRCUIT 7 1 Outline In case picture tube using high voltage when high voltage rises abnormally due to components failure and circuit malfunction there is possibl
57. 0 R371 C370 D421 UZ22BSD Q370 14 25493350 D370 RTS UZ11BSB 4 14 ANN To pin 14 GATE T R375 of Z801 C371 R374 77 Fig 11 11 11 8 SECTION XII HORIZONTAL DEFLECTION CIRCUIT 1 OUTLINE The H deflection circuit works to deflect a beam from left to right by flowing a sawtooth waveform of 15 734 kHz into the DY H deflection coil 2 HORIZONTAL DRIVE CIRCUIT The H drive circuit works to start the H output circuit by applying HVCC Q501 DEF power source to pin 22 of Q501 TA1222N and a bias to the H drive transistor Q402 at the main power on 2 1 Theory of Operation 1 When the power switch is on the main power supply of 125V starts to rise At the same time AF power supply 25V also rises 2 With 25V linerisen Q430 base voltage which is created by dividing the audio power with R433 and D430 also rises Then the transistor Q430 turns on and the HVCC is applied from the audio power line through R432 and D431 to pin 22 of Q501 R432 Q430 D431 ANN l ns R433 D430 T B fg 81 81 CY Y BB80 A L400 T SIGNAL 20 cun sy Fig 12 1 H drive circuit block diagram 12 2 Q501 22 H Vcc 3 BASIC OPERATION HORIZONTAL DRIVE A sufficient current must flow into base of the horizontal output transistor to rapidly make it into a saturated ON condition or a cut off OFF condition For this purpose a drive amplifier is provided between the oscillator circuit an
58. 1 as in the tuner for the main screen and it is also controlled through the I2C bus As the IC for the IF a PLL complete sync detection plus audio inter carrier system are employed N he gt Fig 2 6 Tuner terminal layout 2 6 SECTION III CHANNEL SELECTION CIRCUIT 1 OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM The channel selection circuit in the N5SS chassis employs bus system which performs central control by connecting a channel selection microcomputer to a control IC in each circuit block through control lines called a bus This bus system herin referred to as the bus system two line bus 1s licensed from and was developed by Philips Integrated circuits controlled by the PC bus system are QNO6 for audio signal processing Q501 for V C D signal processing QVO1 for A V switching 02 for non volatile memory main and sub U V tuners 001 01 Q302 for deflection distortion correction QY04 for PIP signal processing QMO1 for DSP and Q701 for closed caption control Differences from the previous N5SS chassis include 1 On screen display generation now originates within ICAO1 A separate IC is no longer used 2 The microcomputer does not perform the closed caption function but instead controls a separate IC for this purpose 3 The system uses two sperate channels of C bus One of these
59. 2 See FIG 17 16 13 and R7765 See FIG 17 16 14 R7750 R7782 R7765 List a procedure of how would you determine which one of the over current protect circuits were causing the shutdown 17 18 R7765 A 0757 8 0843 ES D865 4 H Q853 C882 6 Sada D867 D860 7 5 C310 2801 0370 E 1 L Figure 17 16 17 19 NOTES 17 20 SECTION XVIII DYNAMIC FOCUS CIRCUIT 1 OUTLINE In TP48C51 astatic focus systemis employed in the projection tube Degradation of the focus quality at peripheral screen is improved by applying focus correction voltages parabola voltages in H V periods The dynamic focus circuit creates this focus correction voltage and consists of an H and a V dynamic focus circuit To obtain a flat focus characteristics at center and peripheral of the screen the focus correction is carried out by applying the sync parabola correction voltage efH 700 Vp p and the V sync parabola correction voltage eifv 300 Vp p to the focus electrode in addition to the focus DC voltage of Ef 0 27 0 29 2 DYNAMIC FOCUS CIRCUIT 2 1 Theory of Operation Fig 18 1 shows a block diagram of the circuit which develops an H parabora correction voltage efy QE NEN AFC circuit transformer _ gt Copuling Focus capasi
60. 4 Chroma signal is input to pin 13 and I Q signal which is demodulated in color is output to pins 5 and 6 and next supplied to pins 51 and 52 The signal is processed on luminance and chroma signals andis converted to original color signal R G B by RGB matrix Next the signal is superimposed with OSD signal to be output to pins 41 42 and 43 and is supplied to CRT Drive circuit 4 The signal for Scan Modulation is processed with differential in Q501 to be output to pin 48 Besides at terminal for adjustment TP501 luminance and chroma signals are automatically output according to the selected items of service mode 3 CIRCUIT OPERATION processing operation of video signal are done inside Q501 The outline of Q501 TA1222N is explained in the next section Here major terminals excepting input output terminals of Q501 are described Table 7 1 Pin No Name Description Pin 1 CW output 3 58MHz synchronized with burst is output This is used for clock of comb filter Pin 10 Xtal 1 Terminal for 3 58MHz OSC crystal Pin 11 APC filter Terminal for phase detection of color sync OSC frequency control Pin 18 SYNC Sync separated sync signal is output It is used for detecting no signal in microcomputer Pin 30 HD Terminal for output of HD pulse syncronized with horizontal sync and for input of black expading mask pulse It is used for timing pulse of OSD C C Closed Caption in micro computer Pin 32 Ys OSD cha
61. 8 C847 C846 R859 I R860 I Q802 9 gt 15V ai R853 R854 D859 1857 Q851 1 7888 9852 Figure 17 8 Sub Supply 17 10 10 Protect Circuits D370 Protect active high To Pin 14 of Z801 R372 35V Q370 lt LOAD 3 9K 35 3V 5 6K 1 5 I O 35V C370 R371 R370 35V OVER CURRENT PROTECT CIRCUIT Located on Deflection Power board Figure 17 9 35V Over Current Protect Circuit Located on Deflection Power Board LOAD 30V R7782 0 0 82 e R7783 gt 7784 330 7770 470 29V Protect active high To Pin 14 of Z801 0758 0757 Figure 17 10 30V Over Current Protect Circuit Located on Convergence Out Power2 Board 17 11 15V LOAD R7750 0 33 87749 330 7760 5 16 1V R7751 470 Q758 Protect active high To Pin 14 of 7801 Q757 _ gt Figure 17 11 15V Over Current Protect Circuit Located on Convergence Out Power2 Board LOAD Ah R776 0 39 15V 5 O Ll 87764 330 7763 Il 16 2V Q762 16V 1 5V R7758 2 2K R7763 470 Q761 Q757 Protect active high To Pin 14 of 7801 Figure 17 11 15V Over Current Protect Circuit Located on Convergence Out Power2 Board 17 12 36V 30V O AAA 14 gt R848 D865 D863 24V
62. CULAR Sheet Sheet Projection tube Projection tube Refracting light beams running to screen peripheral area to the G axis direction screen center direction with effect of convex lenses Widening directional characteristic in horizontal direction Fig 16 5 2 3 1 Effect of Fresnel Sheet 2 3 2 Appearance of LENTICULAR Sheet The shape of the lens has been changed to reduce focal length This allows the product size to be reduced specifically in the distance from front to rear FRESNEL a d sheet Effect of lt FRENSNEL sheet Be Lens Without FRESNEL sheet Fig 16 6 LENTICULAR lens ise 3 3 p p Q E 5 IDSN f Viewer side Fig 16 7 16 5 LENTICULAR sheet TP4688J TP48C50 51 TP4880A TW56D90 Body diffusion Surface layer diffusion Diffuser Fig 16 8 Light beams will be effectively used by collecting the diffuser at surface of the layer thus increasing the brightness by about 10 SCREEN GAIN TP48C60 61 5 6 TW56D90 6 2 16 6 2 3 3 Effect by LENTICULAR Sheet If the light enters the front lenticular screen on the diagonal the light will be diffused in the same way as parallel light incidence when viewed from the front of the TV Projection tube side Viewer side F1 F2 Incident light When light
63. Current Resonant Supply Main 5 Fundamental Theory of LC Series Resonant Circuit The LC series resonant switch mode power supply is a fre quency regulated power supply operating above resonance see figures 17 3 and 17 4 The LC series resonant circuit is composed of the primary winding of T862 and C870 negative feedback circuit is used to control the output of the transformer The feedback circuit which monitors the 125Vdc source is composed of the error amp inside Z801 and the photo coupler Q862 This feedback is applied to the CONT input Pin 6 of IC801 to control the frequency of the internal oscillator OSC When the load increases on the secondary side of the transformer the frequency decreases operates closer to resonance and the current VL v increased decreased Sh load gt A CMM AA A gt F Nominal Operating frequency Resonant point 1 E 2n Fig 17 4 Resonance Curve f increases Conversely when the load decreases the fre quency increases and the current decreases Table 17 1 shows the voltages developed on T862 secondaries Table 17 1 T862 Voltage Chart Ground Ground Pin 11 12 15 Signal Side Reference Hot Side Ground T862 Pin 3 when measuring Pins 2 4 5 6 and 7 CAUTION USE ISOLATION TRANSFORMER 17 5 6 Main Supply Actual operation Refer to Figure 17 5 diagram and waveforms 1 Start up 5 Css terminal
64. E model PTV s is rather straight forward as show in Figure 1 10 The horizontal pulse from Q501 drives the horizontal drive circuitry which in turn drives the Horizontal Yokes and the Flyback Transformer T461 Numerous low voltage DC supplies are produced by the Flyback as well as the high voltages for the anode focus and screen drives To prevent excessive high voltages a sample X Ray protection voltage is monitored by the over voltage protection circuits Vertical drive VD is applied to the DPC circuit U421 to correct any distortions before it s sent to the Vertical Drive circuit Q301 Then the vertical drive circuit supplies the signals required by the yokes for deflection To enhance horizontal transitions between dark and light areas of the picture a Velocity Scan Modulation VSM signalis produced by Q501 This signal is sentto the SVM circuit E036Z which in turn drives the SVM coils on the CRTs R 30 7KV AC TO HEATERS T461 G TOCRT 23VDC TO X RAY ANODES FLYBACK 12VDC TRANSFORMER 2 FOCUSES 35VDC G SCREEN DRIVE 2TVDC B TO CRTs 200VDC 125VDC FROM 8 TOABL MAIN POWER CIRCUIT 0501 TO HORIZ YOKES VIDEO CHROMA DEFLECTION PROCESSING U421 0301 DOSE DPC VERTICAL YOKES CIRCUIT EO36Z SVM CIRCUIT DRIVE Figure 1 10 Horizontal and Vertical Deflection Block Diagram 12 Communications REG REG ADJUSTMENT PRESET The TG 1 chassis uses PC data communications t
65. Hz by the input circuit and it is supplied to pin 7 of QMOI Inside QAO1 line 21 signal information is extracted from the input video signal and is recovered on clock and data Recovered data is decoded by the command processor and converted to a display signal of R G B Ys in Output Logic section The display signal is output at pins 18 2 3 and 17 in the CMOS level of positive polarity The display output and OSD are switched by QRO1 in UMOI and the selected signal is sent to the V C D IC When CC EDS and OSD are displayed concurrently OSD has the highest priority H sync signal with negative CMOS level is input to pin 5 of QMO1 This signal becomes the standard signal of a PLL circuit in the IC The loop filter for the PLL circuit is connected to pin 9 QMOI is controlled by the PC bus connected to pins 14 and 15 14 4 42014 SAH II 814 0 01 A V MODULE V AV EH 01 uCOM 0 01 EDS CC RGB SW 01 CC EDS DECODER 144144 VD 01 RGB SWITCH Q89 PC BUFFER IN 3 Q501 V C D 5V Data MOD 8 XFR BUF Data Recovery NC 15 14 16 vas MOS N3S SWS 2 4 5V Command
66. L 12 BACK BOARD A EE 3 COUPLING R 14 COUPLING G 15 COUPLING B 16 CHASSIS FRAME MAIN pe 17 CHASSIS FRAME POWER gt 18 TERMINAL BOARD Fig 1 6 8 VIDEO SIGNAL FLOW BLOCK DIAGRAM Basic Circuit Operation The basic operation of the TG 1 chassis is illustrated in the block diagrams figures 1 7 through 1 12 Although these diagrams focus on the 48 60 the video and audio signal flow diagrams can be applied to any TG 1 chassis with minor modifications Video Signal Flow Figure 1 7 illustrates the video signal flow through the TG 1 chassis The Antenna 1 ANT 1 and Antenna 2 ANT 2 inputs allow two separate RF signals to be connected to the RF switcher When the switch which is controlled by the microcomputer QAOI is in the up position the ANT 1 signal is connected to the HYO1 PIP Tuner IF and the H001 Main Tuner Moving the switch down connects the ANT 2 signal to the H001 Tuner Due to the RF Switch the ANT 2 signal can t be used as the PIP source but when ANT 2 is selected the ANT 1 signal is available at RF OUT The PIP Tuner IF produces a composite video CV signal and sends it to the AV Switcher QVO1 An IF signal produced by the Main Tuner is sent to H002 which produces composite video signal and sends it to the AV Switcher Three video inputs video 1 through3 are applied to the AV Switcher The video 1 input can be composite video Y C video or the test signal fr
67. MODE 3 9 10 TEST SIGNAL SELECTION 3 9 11 SERVICE ADJUSTMENT 3 9 12 FAILURE DIAGNOSIS PROCEDURE 3 10 13 TROUBLE SHOOTING CHARTS 3 13 SECTION IV AUDIO OUTPUT CIRCUIT I OUTLINE a a 4 2 2 THEORY OF OPERATION 4 2 2 1 Operation of TA8256H 4 2 SECTION V DSP CIRCUIT 1 ORIGINS OF DOLBY SURROUND 5 2 2 THE DOLBY MP MATRIX 5 2 3 THE DOLBY SURROUND DECODER ne 5 3 DSPCIRCULIG ee uci dea 5 3 5 DSP Digital Surround Processor 5 6 SECTION VI SWITCHING CIRCUIT baton BD Cai diu oot 6 2 2 IN OUT TERMINALS 6 2 3 CIRCUIT OPERATION 6 2 3 1 Composite Video Signal 6 2 3 2 S Video Signal 4 6 2 SECTION VII VIDEO PROCESSING CIRCUIT OUTLINE a 7 2 2 SIGNAT FLOW ee 7 2 3 CIRCUIT OPERATION 7 2 SECTION VIII V C D IC i ead edd 8 2 2 LARGE SCALE EMPLOYMENT OF BUS CONTROL OF PARAMETER FOR PICTURE CONTROLS 8 2 3 EMPLOYMENT OF CONTAINING EACH VIDEO BAND FILTER INSIDE sei necia oo deceased 8 2 4 EMPLOYMENT OF CONTAINING EACH FILTER FOR S H INSIDE 8 2 S3 LOW COS POR IC ii 8 3 SECTION IX PIP MODULE 1 BOARDEA YOU Tasas diia 9 2 2 SIGNALS la atadas 9 2 3 BLOCK DIAGRAM
68. NTDPJTV04 TO e li BA SERVICE TRAINING Customer Satisfaction Through K nowledge SERVICING THE N5SS COLOR TELEVISION CHASSIS DIGITAL CONVERGENCE TOSHIBA AMERICA CONSUMER PRODUCTS INC NATIONAL SERVICE DIVISION TRAINING DEPARTMENT 1420 B TOSHIBA DRIVE LEBANON TENNESSEE 37087 PHONE 615 449 2360 FAX 615 444 7520 FOREWORD The material presented in this manual is provided for the technical training of TACP employees and qualified service personnel only The specific circuit reference designations pin numbers etc are taken from the TP48E50 60 Service Manual File Number 020 9508 The diagrams in this manual are simplified for training and should be used as areference guide only when servicing the N5SS Chassis Refer to the applicable service data for detailed adjustment and servicing procedures NTDPJTV04 SERVICING TOSHIBA S N5SS TELEVISION CHASSIS 1996 TOSHIBA AMERICA CONSUMER PRODUCTS INC National Service Division National Training Department 1420 Toshiba Drive Lebanon TN 37087 615 449 2360 No part of this manual may be reproduced in whole or in part without prior written consent from Toshiba America Consumer Products Inc Service Division CONTENTS SECTION I OVERALL UNIT CHARACTERISTICS BLOCK DIAGRAMS LABS 1 2 1 MAIN FEATURES une 1 2 2 MERITS OF BUS SYSTEM 1 2 2 1 Improved Servciceability 1 2 2 2 Reduction o
69. NU on the control panel to display the registers Push 9 to activate the self diagnostic feature Is the display different from the previous display If it is explain why Push the EXIT button to exit the self diagnostic feature Push MENU on the control panel to display the registers 1 22 SECTION FOUR SERVICE REGISTERS NOTE each of the following exercises write down the register s value before adjusting it Then restore the register to its original value before proceeding to the next exercise 1 Enter the internal test pattern mode and select the test signal that has white window in the upper center of a black background as shown below Increase the RCUT register value and describe its effect on the picture RCUT Change the test signal to the white on black cross hatch pattern as shown below Select the HPOS register and vary its value between 00 and 1F Describe its effect on the picture What happens if you increase the register to 207 HPOS Select the VPOS register and vary its value between 00 and 07 Describe its effect on the picture What happens if you increase the register to 08 VPOS 1 23 6 Select the HIT register and vary its value 5 steps above below the recorded value Describe its effect on the picture HIT 7 Select the VLIN register and vary its value 8 steps above and below the recorded value Describe its effect on the
70. O BE CONFIRMED BY SERVICER Check in self diagnosis mode Table 3 4 Contents of self diagnosis Display items and actual operation Contents of self diagnosis Display items and actual operation lt Countermeasure in case that phenomenon always arises gt B Detection of shortage in BUS line C Check of comunication status in BUS line Example of screen display D Check of signal line by sync signal detection oe SELF CHECK E Indication of part code of microcom QA01 TP As Par EGO art coce F Number of operation of power protection circuit BOWER 000000 Number of operatioi of power protection circuit BUS LINE OK Short check of bus line BUS CONT OK Communication check of 4 C BLOCK UV QVO01 0 015 3 EXECUTING SELF DIAGNOSIS FUNCTION CAUTION 1 When executing block diagnosis select first the desired input signal source U V BS VIDEO1 2 3 screen and then enter the self diagnosis mode 2 When diagnosing other input modes repeat the diagnosis routines after source selection The test signals and or routines apply only to the video source selected at the time of testing PROCEDURE 1 Place the unit in the service mode 2 Press the 9 key on the remote control will display the self diagnosis results on screen With each key press the mode will change as shown below ig SERVICE mode SELF DIAGNOSIS mode 7 3 To exit from the service mode turn the power off via the fro
71. OL SIGNAL OUT Out Remote control output MUTE SOUND MUTE OUT Out Sound mute output SP MUTE SPEAKER MUTE Out In muting H DEF POW Out POWER POWER ON OFF OUT Out Power control In ON H LED POWER LED OUTPUT Out Power LED on control LED lighting L POWER LNB Out LNB DET In SCLO IIC BUS CLOCK OUT Out bus clock output 0 SDAQ TIC BUS DATA IN OUT In Out bus data input output 0 SYNC VCD H SYNC INPUT In Main picture H sync signal input AFT2 IN In Sub tuner AFT S curve input UV MAIN S CURVE SIGNAL In Main tuner AFT S curve signal input KEY A LOCAL KEY INPUT In Local key detection O to 5V KEY B LOCAL KEY INPUT In Local key detection O to 5V SGV TEST SIGNAL OUT Test signal output In normal L OV SGA TEST AUDIO OUT Test audio output In normal L OV POWER GROUNDING OV Gounding voltage OV R Out At display on Pulse G Out At dispaly on Pulse B Out At dispaly on Pulse Y BL BL At dispaly on Pulse HSYNC In HSYNC for OSD display Pulse VSYNC In VSYNC for OSD display Pulse OSCI DISPLAY CLOCK 4 5MHz Pulse OSC2 DISPLAY CLOCK In Pulse TEST TEST MODE In GND fixed OV XIN SYSTEM CLOCK In System clock input
72. OWER CIRCUIT 3 1 Theory of Operation 18 4 V OVERVIEW ON 17 3 3 2 Circuit Operation 18 5 SECTION I OVERALL UNIT CHARACTERISTICS BLOCK DIAGRAMS LABS 1 amp 2 SECTION I OVERALL UNIT CHARACTERISTICS 1 MAIN FEATURES The main feature of Toshiba s projection television model TP48E60 is the use of the 555 TG 1C chassis This chassis utilizes a bus control system developed by PHILIPS Corporation called the PC or bus stands for Inter Integrated Circuit control This bus co ordinates the transfer of data and control between ICs inside the Television It is a bi directional serial bus consisting of two lines namely SDA Serial DATA and SCL Serial CLOCK Digital data which is passed along the bus is received by individual devices and can be either command or data Digital to analog converters are also found within some of the ICs allowing them to be addressed and controlled by strings of digital instructions replacing those functions which were previously implemented by external potentiometers 2 MERITS OF THE BUS SYSTEM 2 1 Improved Serviceability Most of the adjustments previously made by resetting variable resistors and or capacitors can be made on the new chassis by operating the remote control and seeing the results on the television screen This allows adjustments to be made without removing covers on the unit thus increasing servicing speed and efficiency
73. Pin 8 soft start When power is applied to the set a start up voltage of 16V is applied to pin 10 of IC 0801 At the same time charging of C869 pin 9 induces a delay to the internal latch circuit to prevent the Over Voltage Protect OVP circuit from shutting the set down Output switching element Two power MOSFETS operating in push pull mode are used for switching The on off timing of each is con trolled by the logic inside Q801 To avoid a short circuit from occuring a delay is used between the turn off of one MOSFET to the turn on of the next CT terminal Pin 5 basic oscillation The frequency of the internal oscillator is controlled by the Oscillator Control block The frequency is deter mined by the charge and discharge of capacitor C862 connected to CT terminal The oscillator generates a ramp waveform at Pin 5 The ramp waveform charges up to 4 V typical and discharges to about 2 5 V The charging time is the output on period and discharging time is the off period see OSC OUT SIGNAL waveform of Figure 17 5 The lowest oscillation frequency is determined by capacitor C862 and resistor R867 CONT Pin 6 frequency control Current flowing out of the CONT terminal Pin 6 varies the charging current of oscillator capacitor C862 which in turn controls the frequency of the Output Pin 15 sig nal The control current is determined by the Photocoupler The Photocoupler phototransister side cur rent is dete
74. Processor Decoder Control Sllced Data DLCK x S Ij Recovery Timing Logic Data Sllcer VCO DOT CLK COMP SYNC j Horizontal Vertical CTR And Control FIL SYNC Sllcer Loop IC XC144144P COMP Video 5 LPF PFD Slice Level Fig 14 5 144144 01 block diagram 14 6 HIN c SECTION XV DIGITAL CONVERGENCE CIRCUIT 1 OUTLINE The Digital Convergence circuit developes the correction signals to eliminate geometric distortions in the red green and blue CRTs This new digital design is smaller than previous convergence circuits more accurate and adjusted via the remote control Once adjusted the data is saved in an E PROM and retrieved every time the set is powered up Memory capacity for one full screen of data is 4k 2 CIRCUIT DESCRIPTION 2 1 Configuration Figure 15 1 shows the circuit block diagram for the digital convergence board The digital convergence circuit consists of the convergence processor Q701 the PLL circuit 0707 the EPPROM memory 0713 D A converters Q703 Q704 amp Q705 and pre amplifiers Q715 Q717 amp Q719 Convergence waveforms from the D A converters are amplified and shaped by 0715 Q717 and 0719 filtered and output from u
75. Q402 collector current flows through 125 416 401 In this case the output transistor Q404 turns on with the base emitter reverse biased because of the off drive system employed On the contrary when Q1 inside IC501 is off pin 8 is base emitter bias of Q402 becomes and 0402 turns off and a collector pulse as shown in Fig 12 5 develops at the collector The voltage is stepped down and Q404 is forward biased with this voltage thus turning on Q404 In this way by stepping down the voltage developed at primary winding ofthe drive transformer and by applying it to Q404 a sufficient base current flows into Q404 base thereby switching the Q404 T401 H drive transistor Q501 H Vcc 22 i l C431 e R411 23 ANN R410 Q402 H drive transistor A 9v Fig 12 5 Q404 H output transistor V1 VCP OV 0402 0402 OFF ON 4 HORIZONTAL OUTPUT CIRCUIT The horizontal output circuit applies a 15 734 kHz sawtooth wave current to the deflection coil with mutual action of the horizontal output transistor and the damper diode and deflects the electron beam from left to right in horizontal direction 461 5 capacitor Q404 H output With damper diode 1 Deflection yoke H coil IC501 3 H drive sales A 1462 1463 1464 R415 transformer H
76. Replace 01 NG Pulse output at pins 37 and 38 of QA01 Voltage check at pin 32 of QAO1 DC 5V Check reset circuit OK v Check relay driving circuit Replace 01 O A 3 13 2 NO ACCEPTION KEY IN Key on TV Voltage change at pins 17 18 of NG QAO1 5V to OV xn Check key in circuit Replace 01 Remote unit key NG Pulse input at pin 35 of QAO1 When remote unit key is pressed OK Replace 01 Check tuner power circuit 3 NO PICTURE SNOW NOISE No picture NG Voltage at pins of 5V and 32V OK Check H001 Check tuner power circuit 3 14 4 MEMORY CIRCUIT CHECK Memory circuit check T NG Voltage check at pin 8 of 02 5V Check power circuit Pulse input at pins 5 and 6 of QA02 in memorizing operation 01 02 Note Use replacement parts for 02 Adjust items of TV set adjustment 5 NO INDICATION ON SCREEN No indication on screen v Check of character signal at pin 23 of QA01 5V p NG OK Check V C D circuit Input of OSC waveform at pin 29 of QAO1 with indication key pressed Check OSC circuit Check of sync signal at pins 26 27 of QA01 OK Check sync circuit Replace 01 3 15 NOTES SECTION IV AUDIO OUTPUT CIRCUIT 4 1 1 OUTLINE
77. SP SDA SCL PIP CONTROL DATA CLK Fig 3 5 3 7 8 LOCAL KEY DETECTION METHOD F 15 1 ANN y 515 2 WV y S15 3 AM ie L 515 4 ANN yee S15 5 ANN Te 515 6 ANN ie y S15 7 NN y ol 816 1 T S16 2 OO T 516 3 y OO T 516 4 OO T 516 5 SH 516 6 516 7 Fig 3 6 Local key assignment Local key detection in the 555 chassis is carried out by using an analog voltage divider like method which detects a voltage appearing at the local key input terminals pins 17 18 of the microcomputer whenever a key is depressed Using this method a maximum of 14 keys can be interpreted The circuit diagram shown at the left is a representation of the local key circuit As can be seen from the diagram when one of keys among SA 01 to SA 08 is pressed each of two input terminals pins 17 18 develops a voltage Vin corresponding to the key pressed The voltage measurement and key identification are carried out by an A D converter inside the microcomputer along with interpreting software Table 3 1 Local key assinment Key No Function Key No Function SA 02 POWER SA 01 DEMO START STOP SA 03 CH UP SA 04 CH DN SA 05 VOL UP SA 06 VOL DN SA 07 ANT VIDEO ADV SA 08 MENU 3 8 9 ENTERING THE SERVICE MODE
78. TEST SIGNALS 1 10 Push the 8 button on the remote to activate the audio test signal NOTE The internal test pattern mode must be activated for this feature to work Push the mute button twice Now you can control the volume of the signal Select AUD on the remote control Select BALANCE and adjust it from left to right with the and buttons Select SPEAKERS and turn them off then on NOTE The speakers are turned off at Q601 refer to Figure 1 8 while the volume bass treble and balance are controlled in H002 This means you can troubleshoot most of the audio system with the speakers off Plug an audio cable into the left AUDIO 1 input jack make sure the other end of the cable is not plugged into an audio source What happened to audio If something did happen to the audio why did it happen Push the 8 button to turn off the audio test signal Cycle the video test signals back to the ANT 1 signal with the TV VIDEO button 1 21 SECTION THREE SELF DIAGNOSTICS 1 2 10 11 12 13 Push the 9 button to activate the self diagnostic feature What does POWER indicate What does BUS LINE indicate What does BUS CONT indicate What does BLOCK indicate Push the EXIT button to exit the self diagnostic feature Select the VIDEO 1 input with the TV VIDEO button Make sure there is no signal applied to VIDEO 1 Push ME
79. V deflection stops the voltage across R305 does not develop so Q350 turns off and both the Q351 and Q353 are turned off Then the picture blanking terminal pin 13 of ICAOS is set to high through R354 and D354 connected to 90V power line BLANKING CIRCUIT ON thus cutting off the projection tubes 11 7 gt Somer SIS ene Ee eek ed 12V 9V v R354 gt BLANKING 0354 CIRCUIT pa D353 777 V STOP Volttage Across R305 Q350 BASE 1 0340 VBE 12V VBE 0341 Q351 Collector Fig 11 10 3 1 35V Over Current Protection Circuit The over current protection circuit cuts off the power supply relay when it detects abnormal current increased in the 35 V power line due to failure of the vertical deflection circuit 3 1 1 Theory of operation Fig 11 11 shows the circuit diagram of the over current protection circuit When the load current of the 35V line increases the voltage across a resistor of T370 will also increase When the voltage increases across R370 and the voltage developed across R371 becomes higher than the Vbs of Q370 Q370 turns on and a voltage develops across R374 due to the collector current flowing When this voltage increases to a value higher than about 13V Z801 operates thus cutting off the power relay When the circuit operates a power LED provided will turn on and off in red C303 R370 R327 AAN 35 AAA FBT 1 e pin 6 R372 C31
80. and adjusted data 18 stored Since data in RAM of 0701 is eliminated with power OFF the RAM is set by soft command of microcomputer QAO1 at every power ON The adjusted data which is obtained from screen watching is once stored in RAM inside QAOI The whole data in RAM which is corrected on each adjusting point and is changed is saved into 2 0713 as a fixed data The data capacity per one screen requires 4k for 60Hz mode NTSC 3 2 Service Mode 3 2 1 Outline Service mode is controlled by software of microcomputer QAOI and is one of function of set MENU Service data display original picture Remote 7 key first picture 3 The second picture This mode is designed so that ordinary user cannot use this and special operation is required to use this Data change is done by direct shift cursor display of adjusting points 60Hz mode NTSC 8x8 1 color 3 2 2 To enter and to exit Press MUTE key on remote hand unit twice and keep pressing the key press MENU key of set console Then service data will be displayed on top left of screen Under the condition Press 7 key on remote hand unit and the screen shows crosshatch picture Later the first picture Press again 7 key and the screen changes to crosshatch data display Later second picture This time changed data are automatically saved Further press 7 key on remote the screen returns to original pic
81. ated cirduits R G B R G B 15 10 LAB 3 DIGITAL CONVERGENCE GREEN GEOMETRY 10 Put the set in the service mode and bring up the convergence cross hatch Push the 100 button to turn off the red tube and RTN to turn off the blue tube Place the convergence template on the screen and align the center cross hairs with the tabs in the bezel Use low tack masking tape to attach the template to the bezel Try to get the template flat against the screen to reduce parallax errors Push the 3 button on the remote until the blinking cursor in the upper left corner of the screen turns green Move the blinking cursor to the right with the 6 button then down with the 8 button until it s one line to the right of center The 4 button moves the cursor to the left and the 2 button moves it up Push the 5 button to lock the cursor in place Use the 2 6 8 and 4 buttons to align the intersection of the cross hairs with those on the template Push the 5 button to unlock the cursor Move the cursor to another location and repeat steps 7 and 8 Moving the cursor in a counter clockwise spiral to the various locations works best Normally you need to repeat the procedure a second time to make fine adjustments RED CONVERGENCE l 2 3 Remove the template and press the 100 button to turn the red tube Press the 3 button until the red cursor appears Align the red cross hatch pattern to the
82. beams enter LENTICULAR sheet in parallel BEST Outgoing When light beams enter LENTICULAR sheet diagonally Black stripe LENTICULAR lens Fig 16 9 2 4 Optical Coupling Effect An liquid with a refraction index near that of glass is filled between the projection tube and lens to suppress 1 total reflection from the tube thereby improving the contrast 2 interfacial reflection to reduce loss of light Moreover with the cooling effect of the liquid the power output of the projection tube can be safely increased Lens Liquid ethylene glycol glycerine Index of refraction 1 4 1 45 2 4 1 Optical Coupling Effect 1 Light beams 2 2 emitted from the fluorescent surface A advance up to the lens but light beam 3 returns to the fluorescent surface due to the total reflection 2 This extremely lowers the contrast at the fluorescent surface Assuming that the reflection index of air is 1 0 and that of glass 1 5 the angle which causes the total reflection is 41 8 That is the light beams with an angle of q higher than 41 8 can not exit from the projection tube The light beams returned to the fluorescent surface reaches 56 of the total beams coming out from A N Projection tube Projection tube fluorescene plane Fig 16 10 NT d 285 4 Air Projection tube face glass 1 lt Fluorenscene plane Projection tube Fig 16 11 2 5 Lens
83. ce A voltage developed at pin 2 of Q301 is divided with resistors R307 and 303 and the voltage is applied to pin 6 of Q301 to improve the linearity balance characteristic Moreover the S character correction up and down ward balance correction and M character correction are also performed through the bus control 11 6 3 PROTECTION CIRCUIT FOR V DEFLECTION STOP 0301 2 m L4624L4634L464 VERTICAL DEFLECTION COILS C306 V NF DE When the deflection current is not supplied to the deflection coils one horizontal line appears on the screen If this condition is not continued for a long time no trouble will occur in a conventional TV But in the projection TV all the electron beams are directly concentrated at the fluorescent screen because of no shadow mask used and burns out the screen instantly To prevent this the stop of the V deflection is detected when the horizontal one line occurs and the video signals are blanked out so that the electron beams are not emitted When the V deflection circuit is operating normally a sawtooth wave voltage is obtained across R305 so Q350 repeats on off operation in cycle of V sync In this case the collector voltage of Q35 is set to develop less than 12V Vse Q351 with R352 and C350 as shown in Fig 4 8 Accordingly Q351 and Q353 are continuously turned on As result diode D354 is turned off giving no influence on the blanking operation Next when the
84. ck level correction quantity External constant BUS control Each ABCL characteristic External constant BUS control 3 EMPLOYMENT OF CONTAINING EACH VIDEO BAND FILTER INSIDE Employment of automatic adjustment circuit by Fsc to absorb deviation Employment of deviation aborbing method by high S N filter and mask triming using fixed CR Table 8 2 Former TA8845N TA 1222N Y DL Apa con DL inside Inside Chroma TO BPF External Inside Velocity modulation processing circuit External Inside Esc trap for chroma demodulation output External Inside 4 EMPLOYMENT OF CONTAINING EACH FILTER FOR 5 INSIDE Circuit operation by extremely low current Employment of leak current cancel circuit Employment of detection circuit which does not suffer from influence of stray capacity Table 8 3 Former TA8845N TA1222N Chroma ACC killer filter External Inside Y color difference clamp filter External Inside Filter for filter automatic adjustment External Inside AFC 2 filter External Inside 8 2 5 LOW COST OF IC Involving peripheral components inside gt Down sizing of chip 25 of miniature process PLAS 1 S process nvolving peripheral components inside used Involving peripheral components inside Reducing of number of elements 1 Reducing of gate change of preset method of register for
85. cted sound which comes after collision with a wall as shown by dotted line or comes after several times of collision as shown by double dotted lines The listeners are determining that they are listing in what type of location by perceiving time difference and volume level difference between the direct sound and the reflected sound Direct Sound Initial Reflection Sound Reverberation Sound Fig 5 4 5 5 For more detail this situation can be expressed with the direct sound initial reflection sound coming after one time of reflection and trains of reverberation sound in later period as shown in Fig 5 5 The DSP circuit develops these initial reflection sound and the reverberation sound artificially and add them to the original sounds thereby creating rhe effect that allows the listeners in the home listening room to feel as if they are listening in an original location The DSP YM7128B has eight separate output taps and their delay time and the output levels can be specified separately so various sound fields can be selected by varying the initial reflection sound Moreover the IC has an internal feedback loop which controls the delay time and the output level in considering the later time reverberation sound Direct Sound Initial Reflection Sound r Sound Level Reverberation Sound g 7 Fig 5 5 5 Digital Surround Processor Input signal entered into analog in
86. ction Y V Amplitude V EHT Correction V Screen Position V Drive V Feedback EHT INPUT L R Pincushion Distortion Correction II Top amp Bottom Comer Section H EHT H Amplitude Adj 2 EW Drive EW Feedback Fig 13 1 2 DIODE MODULATOR CIRCUIT Fig 13 2 shows a basic circuit of the diode modulator used in the N5SS chassis A key point in the modulation circuit shown in Fig 13 2 is the development of a negative pulse at point B In this circuit a current loop of the resonant circuit for flyback period is shown by an arrow and the energy stored in LDY is transferred to resonant capacitors Cr Crm in passing through Cr Crm Cs when the scanning completes As a result a positive horizontal pulse as shown in Fig 13 3 will appear at Cr and the current flows into Crm with the direction as shown Then a pulse as shown in Fig 13 3 develops at the point B On the other hand since constant amplitude pulses across Pr 3Loy DD Cr oi Ti zCs Vs ve PEA DM Y Q460 Vm Crm ilo 77 77 Fig 13 2 as shown in Fig 13 3 are applied to the primary winding the high voltage of the FBT is also constant When the negative pulse developed at point B is integrated with Lm and Csm the average value appears at Csm as a negative voltag
87. ction concerning on screen data generation is shown in Fig 3 4 Oscillation clock of OSD is approx 4 5MHz 9MHz which becomes multiplied by two to become the dot clock i slocated within the microcomputer For oscillation a coil TRF1160D V QA01 OSC2 29 OSC1 28 VD 27 HD 26 25 LAO2 is used OSC2 OSCOUT OSC1 OSCIN VSYNC SYNC SIGNAL HSYNC SYNC SIGNAL Ys Ym HALF TONE SIGNAL O 24 BOUT 4 G O 23 GOUT COLOR SIGNAL R O 22 ROUT V Fig 3 4 3 6 7 SYSTEM BLOCK DIAGRAM QA01 TMP87CS38N 3152 QA02 H001 MEMORY 24LC08B1 P MAIN U V TUNER a REMOTE SENSOR EL446L UNIT SDA SCL SDA SCL HY01 SUB U V TUNER lt EL922L KEY SWITCH P SDA SCL H SYNC PULSE V SYNC PULSE VIDEO SIGNAL PROCESS CIRCUIT 0501 VCD TA1222N SDA SCL YS TM REMOTE CONTROL OUTPUT RMT OUT MUTE 8 2 IF MPX SP MUTE CLOCK MVUS345 lt 6 1MHz CLOCK SIGNAL OUTPUT H002 SOUND MUTE SPEAKER MUTE SDA SCL Q701 C C EDS XC144144P DATA CLK MAIN SCREEN SYNC AV1 SYNC DET avo1 AFT1 IN lt DET AV SW DPC UNIT TA1218N SUB SCREEN SDA SCL DATA CLK SYCN AV2 SYNC DET AFT2 IN lt DET QMO1 04 2 D
88. d the output circuit to amplify and to waveshape the pulse voltage 3 1 Theory of Operation 1 2 The horizontal drive circuit works as aso called switching circuit which applies a pulse voltage to the output transistor base and makes the transistor on when the voltage swings in forward direction and off in reverse direction To turn on the output transistor completely and to make the internal impedance low a sufficiently high forward drive voltage must be applied to the base and heavy base current ib must be flown On the contrary to completely 3 4 turn off the transistor a sufficiently high reverse voltage must be applied to the base When the transistoris on collector current is maximum condition with the sufficiently high forward voltage applied to the base the transistor can not be turned off immediately if a reverse base bias is applied to the base because minority carriers storaged in the base can not be reduced to zero instantly That is a reverse current flows through an external circuit and gradually reduces to zero The time lag required for the base current to disappear is called a storage time and falling time To shorten the storage time and the falling time a sufficiently high reverse bias voltage must be applied to allow a heavy reverse current to flow This operation also stabilizes operation of the horizontal output transistor On period OFF period a t Input waveform b
89. e By modulating this voltage to have a parabolic curve with 0460 waveform of Vm is obtained as shown in Fig 13 4 As a result the voltage Vs which is the sum of the power supply voltage VB and Vm is applied across the S curve capacitor Cs Vs becomes a power source for the deflection yoke and the modulated parabolic waveform as shown in Fig 13 3 B is applied to the horizontal deflection yoke and corrects the left right pin cushion distortion b Waveform at point Fig 13 3 MB 2 VS Fig 13 4 3 ACTUAL CIRCUIT In the actual circuit the resonant capacitor is split into two as shown in Fig 13 7 One C440 is inserted between the collector of the H OUT transistor and ground The second one C444 is inserted between the collector and emitter In Fig 13 5 C440 is expressed as and C444 as C2 and the resonant current path for the flyback period is shown by arrows a conventional circuit when the brightness of a picture tube varies high voltage current and high voltage also vary As a result horizontal amplitude is affected However in this circuit the horizontal amplitude variation can be suppressed to near zero if the high voltage current varies with variation of the high voltage When the scanning period completes the energy stored in the deflection yoke LDY is transferred to
90. e danger that X RAY leakage increases to affect human body To prevent it X RAY protection circuit is equipped 7 2 Operation Figure 10 18 shows the circuit diagram Supposing high voltage rises abnormally due to some reason pulse at pin 9 of T461 also rises and detection voltage Eb rectified by D471 and C471 in X RAY protection circuit rises When Eb rises emitter voltage of 10 divided by R25 and R26 in protector module becomes higherthan zener voltage 6 2V of ZD6 Tr10 VBE This causes Tr10 turns on to supply base current to Tr9 Then Tr9 turns on this Tr6 and Tr6 turn on to make ON OFF pulse at pin 7of QAOI inlow level QB30 and Q843 turns off then relay SR81 turns off Tr6 and Tr7 are in thyristor connection and 5V of power holds protection operation until main power switch is turned off During circuit operation power LED near main power switch blinks turn on and off in red Caution To restart TV set repair failure first 5V MICOM QA01 7 R25 _ R472 T461 Tr10 ED 4 MAINE O D471 R26 RELAY m SR81 R22 C471 ZD6 Q843 Fig 12 26 X RAY protection circuit 8 OVER CURRENT PROTECTION CIRCUIT 8 1 Outline If main power 125V current increases abnormally due to components failure there is possible danger ofthe secondary damage like failure getting involved in other part failure and abnormal heating To prevent this over current protection circuit is equip
91. emote unit c Direct selection of adjustment item R CUTOFF POS remote unit G CUTOFF 2 POS remote unit B CUTOFF 3 POS remote unit d Data setting for PC unit adjustment SUB CONTRAST 4 POS remote unit SUB COLOR 5 POS remote unit SUB TINT 6 POS remote unit e Horizontal line ON OFF VIDEO TV NOTE applies only to direct view f Test signal selection VIDEO remote unit n service mode serviceable items are limited Test audio signal ON OFF 8 POS remote unit Test audio signal 1kHz 9 POS remote unit Cyclic display including ON OFF Initialization of memory CALL remote unit POS UP TV Initialization of self check data CALL remote unit POS DN TV BUS OFF CALL remote unit VOL UP TV 12 FAILURE DIAGNOSIS PROCEDURE The 555 chassis is equipped with a self diagnosis function inside used for troubleshooting 1 CONTENTS TO BE CONFIRMED BY CUSTOMER BEFORE SERVICE CALL IS MADE Table 3 3 Contents of self diagnosis Display items and actual operation A DISPLAY OF FAILURE INFORMATION Power indicator lamp blinks and picture does not come IN NO PICTURE Condition of display 1 When power protection circuit operates 1 Power indicator red lamp blinks 0 5 seconds interval 2 When I2C BUS line is shorted 2 Power indicator red lamp blinks 1 seconds interval If these indication appears repairing work is required 2 CONTENTS T
92. ends This unit allows the users to adjust an horizontal amplitude adjustment so picture quality at screen ends will be improved This is one of the purposes of the blanking circuit lt gt 0487 period S A A D486 ov Slice level Approx 17V AFC Pulse Waveform at point A Fig 12 14 4 3 2 Theory of Operation The H blanking circuit determines the flyback period precisely from the AFC pulse in the FBT and applies the period to emitter of the video output stage transistor on the CRT D PC board 4 3 3 Circuit Operation As can be seen from Fig 12 14 the flyback period of the AFC pulse in the FBT starts at a negative side from detects this the DC component is cut with C493 This is C493 is always charged through D487 with a negative side about 17V of the AFC pulse As a result a voltage at point Ainthe waveformrises from the ground level This waveform is sliced in a circuit R410 C492 D486 to detect the flyback period Thus obtained voltage is applied to Q901 Q903 and Q905 through D912 D914 and cuts off them thereby blanking the resters 27V 0905 Point T461 FBT 487 C493 CRT D DCB 7 11 AWV 164 R410 NT P405 Deflection Power PCB R409 D486 R405 R417 0489 C449 D487 Q488 AFC R438 R445 AAN V blanking D441 Fig 12 15 12 12 4 4 200V Low Voltage Protection 4 4 2 Theory of Operation 4 4 1 Outline Fig 12 16 sho
93. esponse speed must be slowed by lowering the AFC sensitivity On the other hand to improve distortion due to the phase difference the response must be increased by increasing the AFC sensitivity In a conventional AFC circuit setting of the sensitivity is carried out at one part only so compromise point for both characteristics must be found However with the double AFC circuit employed this time for the jitter the AFCI loop works best with decreasing the sensitivity and for the phase distortion the AFCII loop works with increasing the sensitivity 3 H OSCILLATOR CIRCUIT 3 1 Outline 503 kHz 32 x fH voltage controlled type oscillator with a ceramic oscillation element is used to generate a clock pulse and the clock is counted down thereby obviating the need of adjustments for both the H and V deflection process circuit 3 2 Theory of Operation 1 The H sync signal used as a reference signal enters from the sync separation circuit to the AFCI circuit At the same time the fH pulse created by counting down the 32 x fH pulse generated in the ceramic oscillator enters AFCI circuit Phase difference between these two signals enters an integration circuit low pas 10 4 H Vcc SYNC SEPARATION CIRCUIT CIRCUIT H COUNT DOWN H AFC II CIRCUIT Fig 10 4 filter connected to 4 and converted into a DC voltage AFC voltage 2 The AFC voltage controls frequency 32 x of the
94. f Parts Count 1 2 2 3 Quality Control 1 2 3 COMPARISON DIFFERENCES TG 1 1 2 4 SPECIFICATIONS uses 1 3 5 FRONT AND REAR CONTROL MA e e 1 4 5 1 Front View sache 1 4 Ded Rear TOW sea seen 1 5 5 3 Remote Control View 1 6 6 95 PJ TV CHASSIS LAYOUT 1 7 7 CONSTRUCTION OF CHASSIS 1 8 8 VIDEO SIGNAL FLOW 1 9 9 AUDIO SIGNAL FLOW 1 11 10 POWER SUPPLY 1 12 11 Hand V DEFLECTION 1 13 12 PC COMMUNICATIONS 1 14 13 DIGITAL CONVERGENCE 1 15 1 16 SAAB 1 20 SECTION II TUNER IF MTS S PRO MODULE ICIBCUIT BLOCK dates 2 2 Pot reir 2 2 1 2 Major Features A 2 2 1 3 Audio Multiplex Demodulation CIPCUIE P 2 3 1 4 A PRO Section Audio Processor 2 4 2 PIP TUNER se 2 6 2 6 SECTION HI CHANNEL SELECTION CIRCUIT 1 OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM 3 2 2 OPERATION OF CHANNEL SELECTION CIRCUIT un 3 2 3 MICROCOMPUTPBR tide eter 3 3 4 MICROCOMPUTER TERMINAL FUNCTION 3 4 5 EEPROM QAU sauna 3 6 6 ON SCREEN FUNCTION 3 6 7 SYSTEM BLOCK DIAGRAM 3 7 8 LOCAL KEY DETECTION METHOD 3 8 9 ENTERING THE SERVICE
95. he cabinet and turn it on its side CAUTION the light box weighs about 85 pounds so get help if you need it SECTION THREE IDENTIFICATION 1 Identify each of the board assemblies and note their locations Use Figure 1 5 to help you identify the various boards Convergence Output Power Board Deflection Power Board Main PCB Front Surround Board Digital Comb Filter Board PIP Board EDS CC Board 0000000 2 Is there convergence board in this unit If so where 3 How does this convergence setup differ from previous models 4 Examine the Flyback and HV lead assemblies What is different about this area from earlier models 5 Is it possible for one technician to perform a service call on this type of unit 6 Put the lightbox in the cabinet but don t screw itin Then replace the screen and control panel Use a few screws to hold the screen and control panel in place SUMMARY In this lab the operation and function of the unit was determined and the unit was set up for service on the bench Common user type problems in addition to overall serviceability was also discussed END OF LAB 1 LAB 2 TEST SIGNALS SELF DIAGNOSTICS amp SERVICE REGISTERS OBJECTIVES After completing this lab you will be able to 1 Enter and exit the set s internal video and audio test signals 2 Use the test signals for troubleshooting 3 Use the set s self diagnostic feature 4 Make adjustments
96. ined NOTE SHUTDOWN OCCURS WHEN THE VOLTAGE INCREASES TO APPROXIMATELY 25V 17 16 10 While shorting the base of 0853 See FIG 17 16 6 to ground monitor and record the collector voltage using the p h meter Collector 0853 What have you simulated by shorting the base to ground Why does a change occur on the collector and where is this change sensed Look on the schematic diagram labeled Convergence Out Power2 in the upper right side Find D865 zener diode on the 30V supply line How would you determine what the peak voltage would be before the over voltage protect circuit would operate Look on the schematic diagram labeled Convergence Out Power2 in the upper right side Find D860 zener diode on the 15v supply line How would you determine what the peak voltage would be before the over voltage protect circuit would operate Remember when you measured the anode sides of D865 and D860 earlier Well if the set your working on is in shutdown mode how would you determine if it was caused by over voltage on the 430v or 15v lines 17 17 11 12 13 14 While shorting the base of Q757 See FIG 17 16 8 to ground monitor and record the collector voltage using the p h meter Collector Q757 What have you simulated by shorting the base to ground Measure the voltage drop across R7750 See FIG 17 16 12 R778
97. ing the self diagnosis results gt While the error count state is displayed upon the screen press the CHANNEL DOWN button on set pressing DISPLAY button on remote unit CAUTION All ways observe the following caution when in the service mode screen Do not press the CHANNEL UP button This will cause initialization of the memory IC Replacement of memory IC is required Do not initialize self diagnosis result This will change user adjusting contents to factory setting value Adjustment is required White Yellow Cyan Green Magenta Red Blue COLOR BAR SIGNAL Colorelements are positioned in sequence of high brightness Troubleshooting method utilizing internal test signal VIDEO INPUT 1 terminal should be open 1 With service mode screen press VIDEO button on remote unit If inner video signal can be received 01 and after are normal 2 With service mode screen press 8 button on remote unit If sound of 1kHz can be heard 01 and after are normal By utilizing signal of VIDEO input terminal each circuit can be checked Composite video signal audio signal 13 TROUBLE SHOOTING CHARTS 1 TV DOES NOT TURNED ON TV does not turned on YES Relay sound NO Y NG Check of voltage at pin 7 of QAO1 gt DC 5V OK Check power circuit Y NG 8 2 oscillation waveform at pin 32 of QAO1 OK Check OSC circuit
98. it increases Q862 conducts more The Switch Latch circuit is used to turn off SR81 relay in case of over current over voltage or under voltage In shut down mode Pin 16 Protect latches low which turns QB30 off When QB30 turns off Q843 turns off This causes the relay SR81 to open and thereby disconnect the power To SR81 Relay meo 5 1 RB30 4 From ICAO1 Power Pin QB30 sv 4 9V R470 R471 C472 HH In the B Over Current Protect OCP circuit the cur rent is being compared across R470 which is applied through Pins and 2 The resistance of R470 is so small that changes in voltage equate to larger changes in current When a large enough change in voltage occurs the internal latch circuit outputs a low on Pin 16 which shuts the unit down In the X Ray Protect circuit Pin 11 provides a reference voltage of 25V If the High Voltage increases abnormally Pin 9 of T461 senses the increase and increases the voltage through R472 This increased voltage is applied to D471 which rectifies AC to DC The increase in Vdc is applied to Pin 13 which will trigger the internal latch circuit and output a Low on Pin 16 As long as 5v 1 is applied to pin15 the remote control hand unit will not recover the power The AC power line must be disconnected to reset the latch See Protect Circuits starting on page 17 9 35V Over Current Protect 30V Over Current Protect 15V Over Curren
99. k detection TSD circuit This is to make the Latch circuit operate when the IC s internal temperature exceeds 150 C ono 12 oo 38Vdc 125 gt t D Red ZVIN C870 T862 PIN VOLTAGE PIN 1 1 150 160Vdc 1 15 14 f A N o oo a Ld 89Vdc D876 7 s 3vder OV R864 C862 R867 AW C876 17 4Vde Osc CT 5 2 f CONT 4 Ndc OSC CONTRO 6 IC Q801 STR Z3201 Css 4 7Vdc R863 0879 Figure 17 5 Current Resonant Supply with Wavefoms Ot C866 PIN 15 PUSH PULL OUT VOLTAGE PIN 15 PUSH PULL OUT CURRENT CT PIN VOLTAGE OSC OUT SIGNAL Internal GATE VOLTAGE GATE VOLTAGE PIN 5 PIN11 LOW SIDE PIN2 HIGH SIDE C867 R870 R865 C874 17 7 7 Scan Derived Voltages FBT Figure 17 6 shows the voltages derived from the FBT of the Horizontal Deflection circuit The FBT derives 200V for the Video Output circuit from pin 3 35V for the Fail Safe H V Regulator Blanking Dynamic Pin Cushion DPC and Vertical Deflection V D circuits from pin 6 and 27V for the side DPC circuit from pin 5 Heater volt age from pin 9 Automatic Frequency Control AFC and blanking signal from pin 10 and the Automatic Black Level
100. lector current The voltage at the point B decreases with the circuit impedance and finally lowers up to a saturation voltage of Q1 Then Vcr is not clamped by D2 with the voltage at the point B Since the Vceis expressed as a sum of and Vce as shown by equation 3 Vcedecreases by amount the Ver is decreased This varies the high voltage Q1 collector current is controlled by Q1 base current which isanoutput ofthe comparison inverted amplifier Thatis the base current is controlled by a voltage obtained by comparing a detection voltage of the top breeder of the FBT 9 1V and a DC voltage of 9V 12 18 bd Horizontal output C1 uf ded CS B D1 m a C2 1 4 T 4 Qt High voltage D re output amp 777 777 Fig 12 23 VCP VCP1 VCP2 VCP 1 BE 2 Fig 12 24 6 1 3 Actual Fig 12 25 shows the actual circuit used the unit A resonant capacitor CO is also splitinto two capacitors C443 and C444 in this circuit The high voltage regulator cirucits is structured by splitting the C443 to two capacitors of C443 and C448 Here assume a high voltage increases and the detection voltage obtained by dividing the high voltage also increases in proportional to the high voltage This makes the voltage E increase at pin 7 The voltage is impedance transformed by a voltage follower circuit consisting of op amplifier Q483 at pin 7 The
101. ltage output circuits using the 1 Stabilization by varying the power supply voltage 2 Stabilization by varying L value with a saturable reactance connected in series with the primary winding of the FBT 3 Stabilization by varying equivalent capacitance of the resonant capacitor CO 4 Stabilization by superimposing a DC or pulse this varies the high voltage on a lower voltage side of the high voltage winding of the FBT FBT ANODE Hotizonal t output 3 by PW output High voltage Reg T Ref 7 Fig 12 22 Basic circuit for high voltage regulator emplyed in the unit 12 17 6 1 2 Theory of Operation Fig 12 23 shows a basic circuit of the high voltage regulator used in the unit The high voltage regulator circuit splits a resonant capacitor COtoCl and C2 thereby dividing the collector voltage V cr of the H output transistor with C1 and C2 Here assume each voltage developed across C1 and C2 as Vcr and Vori respectively C2 Ve Ds CitC2 s O C2 cu Ve 1n as CitC2 ES Ver G each relation can be expressed by the above equations 0 0 The Vcr developed across C2 is DC clamped with a diode Dl and theresultant voltage is smoothed with a diode D2 and a capacitor C3 Thus processed voltage is obtained at the point B This voltage is usedto provide a base current for the transistor Q1 or to flow the col
102. n 5 30V By HD input signal pump up is done only in horizontal retracing time Horizontal correction wafeform 6 2 4 CONV OUT mute In power on operation transistors Q765 and Q766 are made turned ON and 15V is applied to pin 3 of CONV OUT IC These cause mute operation on CONV OUT 6 2 5 Operation of IC 1 Q764 TC74HC4050A P Sync signal which is input from P711 1 VD 2 HD is through buffer supplied to digital convergence P708 2 3 terminal source 0754 45V Q735 9V Q756 9V Source for digital convergence 3 0767 4066 P711 4 SDAM 5 microcomputer Busline through Q767 is input to Digital Convergence P709 and is controlled 4 To adjust from outside of digital convergence Put adjusting jig into 6P socket of P720 Iscs turns from H to L switch of Q767 is changed over Then busline from microcomputer is cut off P720 3 SCLU 4 SDAU Controlled by external adjusting jig Pump up Pump up source waveform 30V 15V ov 15V Horizontal correction waveform Fig 15 6 CONVERGENCE BLOCK DIAGRAM H 592841 Nvas WIOS OND Ivda GND SONI NTIS NYAS AND IND H Leer 4 26 5 59 N33u0 024d 9 05
103. n circuit The auto slider type circuit employed in this time makes synchronous separation at a constant rate against the synchronizing signal amplitude See Fig 10 2 In this method even if an abnormal signal with small amplitude is applied stable synchronizing performance can be obtained without separating pedestal 8 Corect Sync Signal Pedestal Level Sync Separation Level A B C D b Small Amplitude Sync Signal Fig 10 2 Synchronous separation by auto slider system H sync siganl V sync signal Reset pulse 1 1 2 V Sync Separation Circuit To separate a V sync signal from the composite sync signal consisting of V and H sync signals mixed two stages of integration circuits are provided inside the IC The circuit consists of a differential circuit and a Miller integration circuit and has following functions 1 Removes H sync signal component 2 Maintain stable V sync performance for a tape recorded with a copy guard 3 Stabilized V sync performance under special field conditions poor field ghost sync depressed adjacent channel best The V sync signal separated in this stage is processed in a waveform shape circuit and then used as a reset pulse in the V division circuit as stated later 2 H AFC Automatic Frequency Control CIRCUIT A sync system which performs synchronization with each waveform of the sync signal as performed in a sync system in the V circuit is called a direct
104. n the case of 4 blocks construction for simplification Positive or negative pulse determined by stray capacitance of each coil develops at terminal points B of each coil as shown in Fig 12 20 and these pulses are stacked as shown thus developing the high voltage Moreover a capacitance between the internal and external coatings of the picture tube works as a smoothing capacitor Focus voltage is obtained at point EO The FBT is turned to a harmonic of 15 times the fundamental frequency and the turned waveform is shown in Fig 12 21 Flyback Reference wave 45 KHz Harmonics 15 times 675 KHz Tuned waveform Becomes 45 KHz x 15 675KHz this is determined by coil inductance capacitance and stray of FBT In case of 3X In case of 15X Picture tube current Hight voltage 2 In case of 15 times the harmonics compared with 3 times the harmonics average conduction peiod of the high voltage diode is wider As a result high voltage variations are suppressed Fig 12 21 Tuned waveforms 12 16 6 HIGH VOLTAGE CIRCUIT 6 1 High Voltage Regulator In this unit pulse transformer is eliminated and the regulator 6 1 1 Outline circuit using the method 3 is employed The block diagram Generally four kinds of methods exist to stabilize a high is shown in Fig 12 22 voltage in high vo
105. ncreases to rapidly turn Q1 on As Q1 becomes saturated the current through the primary wind ing decreases This decrease in current through the primary winding re duces the electromagnetic inductance across the base drive winding which decreases the voltage to the base of Q1 and thereby rapidly turns Q1 off T888 uses a detection type winding through Pins 7 and 8 The secondary windings are proportional to the detection winding Subsequently any fluctuation in voltage across the secondary windings is sensed across the detection wind ing which is fed back through Vo sense Pin 1 This feed back is used to regulate the On Off time of the internal switching transistor Q1 R846 C845 R852 D848 create a voltage clamping circuit that allow the collector voltage of Q1 to stay within a specified level R847 C855 R848 and D849 filter the base voltage 0850 0851 0852 C856 0855 R857 and R859 create the Slow start circuit C856 determines the rate of the start up time 0857 1853 851 Bridge rectifier BER t I r 17 DEM gt 430V 0855 R846 T C845 oed x 1 R852 11858 ces7 C858 C859 163 7V R857 T E 850 I 849 D848 9 0 2V 851 858 855 DNA gt 15V Base Drive B 34l D850 a R847 D849 C880 C882 Zu 0 0V C853 R850 Vo Control pl O Vout Sense nd C84
106. nge over pulse input Ys of OSD is input Pin 45 ABL Terminal for ABL control input Pin 47 Ym Input of pulse for half tone control It is supplied from microcomputer Pin 49 APL DET Detecting average level of video signal for correction of DC transmission Pin 50 BLACK DET Detecting black area of video signal for black expading circuit Pin 54 COL Terminal for peak hold of color limiter Pin 55 DACI Test point TP501 Functioning test point in service mode 7 2 VELOCITY MODULATION EL PNI 8115592044 JO weaderp 1 1 From COLOR SIGNAL A V Board PROCESSING RGB CRT DRIVE MATRIX LUMINANCE SIGNAL PROCESSING SYNC DEF PROCESSING 0501 V C D 501 USED IN SUB COLOR amp SUB TINT ADJUSTMENTS OSD EDS CC CONVERGENCE FROM QB91 NOTES SECTION VIII V C D IC 1 OUTLINE This IC enables more precise picture setting than that of former TA8845N by means of large scale employment of bus and reduces many peripheral components by containing filters inside The main features comparing TA8845 are as follows 2 LARGE SCALE EMPLOYMENT OF BUS CONTROL OF PARAMETER FOR PICTURE CONTROLS Soft method of picture making Table 8 1 Former TA8845N 1222N Black expanding start point External constant BUS control DC transmission correction quantity point External constant BUS control Bla
107. nit The PLL clock is adjusted by L719 to a basic frequency of 32MHz with no sync signal 0701 generates a customer convergence test pattern and a service convergence test pattern and outputs them as R G B and YS signals 2 2 1 2 3 4 5 Circuit Operation When power is applied to the set C711 resets the unit Vertical VD and horizontal HD sync signals are applied to 0701 and 0707 These signals lock the PLL Q707 to 32 MHz which is counter down in Q701 to provided the clock Q701 down loads the data in Q713 to RAM 0701 processes the data and sends it in serial form to the D A converters Q703 Q704 Q705 Onced processed the comvergence wave forms are amplified by Q715 Q717 and Q719 Next the waveforms are filtered before they are output from the digital convergence board ST T ST SH TEST PATTERN 9999 0701 7 64 RAM 8x8x13bit x3 D A 0703 0715 9704 0717 D A 1 2048 Q705 Q719 COUNTER gt D A Q767 N QAO u CON 32MHz 0 005MHz MAIN BUS LINE Sub BUS LINE YY Yy FILTER FILTER FILTER FILTER FILTER FILTER DIGITAL CONV BOARD INVHOVIG 19014 3 PICTURE ADJUSTMENT The adjustment is done on 60Hz mode NTSC 3 1 Change of Memory E7PROM Memory of Q713 E PROM is nonvolatile
108. nt panel or remote control 3 10 4 UNDERSTANDING THE RESULTS OF THE SELF DIAGNOSIS FUNCTION See Fig 3 7 Example of screen display SELF CHECK NO 239XXXX POWER 000000 BUS LINE OK BUS CONT OK Part of QAO1 Short check of bus line E Number of operation of 4 F power protection circuit B Communication check of C busline displayed on screen Besides when 9 key on remote unit is pressed diagnosis operation is first executed once BLOCK UV V1 V2 D QVO1 QVO1S Fig 3 7 Table 3 5 Item Contents Instruction of results BUS LINE Detection of bus line short Indication of OK for normal result NG for abnormal Indication of OK for normal result Indication of failure place in abnormality Failure place to be indicated QA02 NG 001 NG 0501 NG H002 NG 01 NG 0302 NG 0 02 NG 0 NG QD04 NG 01 NG 0701 NG BUS CONT Communication state of bus line Note 1 The indication of failure place is only one placet though failure places are plural When repair of a failure place finishes the next failure place is indicated The order of priority of indication is left side BLOCK The sync signal part in each video signal Indication by color UV2 supplied from each block is detected Normal block Green Then by checking the existence non of Non diagnosis block Cyan V2 sync part the result of self diagnosis is lt Clear
109. nto the deflection yoke is a current d current b c in Fig 11 6 and the emitter voltage of Q3 and Q4 1s expressed as e 3 Q3 collector loss is 11 x Vcel and the value is equal to multiplication of Fig 11 6 b and slanted section of Fig 11 6 e and Q4 collector loss is equal to multiplication of Fig 11 6 c and dotted section of Fig Tee Power Vcc T Ym _ GND b Q3 Collector current i1 GND c Q4 Collector current i2 GND d Deflection yoke current i1 i2 a Basic circuit Fig 11 6 Output stage operation waveform 11 4 4 To decrease the collector loss of the power supply voltage is decreased during scanning period as shown in Fig 11 7 and decreases and the collector loss of Q3 also decreases Collector loss decreases a by amount of this area ER 4 Power supply i for flyback period L Power supply for scanning period Vcc i ing period Pie Scanning period a Flyback period Fig 11 7 Output stage power supply voltage 5 In this way the circuit which switches power supply circuit during scanning period and flyback period is called a pump up circuit The purpose of the pump up circuit is to return the deflection yoke current rapidly for a short period within the flyback period by applying a high voltage for the flyback period The ZR308 L462 L463 L464 Tos
110. o 40 control all customer features and most of the service GCUT GREEN CUTOFF adjustments that where previously done with discrete BCUT BLUE CUTOFF devices refer to Figure 1 11 All communications RDRV RED DRIVE are controlled by the Microcomputer QAO1 through BDRY BLUE DRIVE a SUB CONTRAST serial data lines SDA serial clock lines SCL BRTC SUB BRIGHT CENTER Memory settings for customer controls and service COLC SUB COLOR CENTER adjustments except convergence data are stored in TNTC SUB TINT CENTER the EPPROM Memory 02 and communicated SCOL SAP COLOR to QAO by the SCLO and SDAO lines Data and SCNT SUB CONTRAST clock lines SDA1 and SCL1 communicate with HPOS HORIZ POSITION is H th VPOS VERTICAL POSITION 00 most of the circui sin e set However there are VERTICAL HEIGHT three plug in circuits where the data and clock GMPS GMPS 00 signals are buffered by 90 to provide isolation VLIN VERTICAL LINEARITY VSC ASCORRECTON 068 customer functions and most services adjustments are implemented through the Key Pad and the Remote Sensor The RMT OUT signal on the microcomputer drives the IR Transmitter on the front panel but it s only used in the manufacturing process Figure 1 12 shows the Service Registers STRH HORIZ START POSITION andtheir default values used for making adjustments in the set Figure 1 12 Service Register Default Values KEY REMOTE PAD SENSOR
111. om QAOI Video 2 is composite video only and video 3 is either composite video or Y C video A mechanical switch on the video 1 input defaults to the test signal so a video connector must not be plugged 1 9 into the video 1 input jack when the internal test signals are used The selected video signal is output as composite video and applied to the video output jack the EDS CC RGB SW and the Digital Comb Filter or the 3D Y C circuit After processing the video signal is sent back to the AV Switcher as separate luminance Y and chrominance C signals The Y and C signals are then sent to Q501 the Video Chroma Deflection Processing IC A sync signal is tapped off the Y signal and applied to Q501 Q501 processes the video signal and sends separate R G and B signals to the CRT drives and the CRTs If the PIP feature is selected composite video from AV Switcher is sent to the PIP circuit ZY01 After processing the PIP signal is sent to 0501 as G B and YS where it 1s mixed with the main video On screen display OSD R G and B signals produced by the Microcomputer 01 are mixed with the Extended Data Service EDS and Closed Caption CC data in UMOI These new signals are applied to an OR gate QB91 and combined with the convergence signals from the digital convergence circuit The convergence signals can be either the customer convergence cross hairs or the service cross hatch pattern All of these signals are sent
112. omponent of 700 Vp p and a V component of 300 Vp p Thus obtained mixed output is fed to the focus electrodes of R G B projection tubes through the coupling capacitor stated under 2 2 The parabola level of the V focus parabola output voltage can be adjusted by varying R369 and the DC voltage level by varying R354 The power for Q361 is obtained by rectifying collector pulse of the deflection output circuit with the rectification circuit ZA70 The rectification circuit Z470 is assembled as a separate block in considering safety because of its high rectified output voltage of about 1000V 9 81 map yndyno A p 8T 214 Focus power supply lock H deflection output circuit H dynamic focus circuit Q360 V Coil C306 2470 D305 L R357 C361 e AAN l E R480 R361 2 Q301 D364 nae 5 paes Z Raes 12V AAN R360 C300 lt C364 D360 x 77 77 b 77 Q404 G 5 EROR du rs FE o 31 EF N o EE OS if Tok M 1 E F To RED DRIVE y es AAA NNN NNN NNN 9 i E O F To GREEN DRIVE Y ANN NNN NNN NNN d A 3 BLUE DRIVE i DES AAN NAN NNN NNN a eee
113. oscillator VCO Fig 10 5 shows the control characteristics ofthe VCO 3 The output is obtained by dividing the 32 x fH 503 kHz of the oscillator with flip flops Fig 10 6 shows the block diagram of this count down circuit 4 The V output is created by dividing the 32 x fH oscillator output into 1 8 and then by counting the 4 x fH pulse with a vertical counter which is reset with a V reset pulse V sync output signal stated under sync separation 5 Thatis the V output is not created by simply counting down the H by performing V synchronization with a V reset pulse entering within a window provided for V synchronization called direct type sync system thus the circuit can work for non standard signals 32fH 32 x fH VCO X 1 8 Reset V sync V WAVEFORM pulse signal SHAPE CIRCUIT High OSC frequency Hz o COUNTER Low High AFC voltage V Fig 10 5 fH X 1 4 H OUTPUT V OUTPUT Fig 10 6 Block diagram of H V count down circuits NOTES SECTION VERTICAL OUTPUT 1 OUTLINE As be seen from the block diagram the sync circuit and the V trigger circuit are contained in Q501 TA1222N and the sawtooth generation circuit and amplifier V drive circuit contained in Q302 TA8859AP The output circuit and pump up circuit circuits are included in Q301 TA8427K DPS CIRCUIT Q501 TA1222N Q302 TA8859AP Q301 TA8427K SYNC
114. ped which detects current of main B line to turn off power relay in abnormal situation 8 2 Operation Fig 12 27 shows over current protection circuit When the current of main B line increases abnormally due to the shortage in load of main B line voltage drop arises across R470 By this voltage drop when base emitter voltage of Tr 8 in protector module Z801 becomes appprox 0 7V or more Tr 8 turns on and the voltage by divided ratio of R15 and R16 is applied to cathode of ZD4 When this voltage becomes higher than zener voltage of ZD4 ZD4 turns on to supply base current to base of Tr 6 via R14 This causes Tr 5 ON and voltage at pin 16 of Z801 becomes Low Therefore QB30 and Q843 turns off to set SR81 OFF Tr 6 and Tr 7 in 7801 are in thyristor connection and power 5V 1 supplied at pin 15 keeps protection operation for standby power until main power switch is turned off During circuit operation power LED near main power switch blinks in red Caution To restart TV set repair failure first R470 F470 MAIN B Ate To T461 R479 R471 5V the c7 5 2 1 0187 RELAY SR81 Q843 Z801 PROTECTOR MODULE Fig 12 27 Over current protection circuit 12 21 NOTES 12 22 SECTION XIII DEFLECTION DISTORTION CORRECTION CIRCUIT DPC Circuit 1 DEFLECTION DISTORTION CORRECTION IC TA8859P 1 1 Outline The deflection distortion correction IC TA8859AP
115. put pin 4 of DSP IC YM7128B is converted to 14 bit digital signal with the sampling frequency 23 6 kHz by A D converter of 14 bit floating system and enters digital delay circuit through digital attenuator VM and doubler The digital delay circuit has nine output taps and the delay time of each tap can be controlled independently also each tap position can be switched by TO to T8 register In a minute the TO output passes through the primary FIR Finite Impulse Response type low pass filter and reduction processing is performed by VC then it feed backed to the delay input after it is added to the doubler described above The output of eight taps T1 to T8 is added after performing reduction processing by GL1 GL8 GR1 GR8 and reduction processing is performed by the digital attenuator VL or VR and an analog output is created by D A converter after passing through digital filter comes out from pin 7 or 8 The digital attenuated value delay time and the coefficient of FIR type low pass filter are set by writing the data on the register This process is performed by loading three data from sub microcomputer to microcomputer interface This unit has four modes as surround mode The setting values are described in Table 5 1 Table 5 1 DSP control factor Mode OFF DOLBY THEATER Control SURROUND STADIUM NIGHT CLUB HALL HALL CONCERT VM IN P 0 PO x PO PO PO VL LO Diss PO x VR RO
116. put to pin 24 Bending correction terminal of 0501 This corrects white peak bending 4 2 2 Operation theory Fig 12 13 shows circuit diagram From R G and B output pins 41 42 and 43 of 0501 video signal is taken in the dividing ratio of resistor R375 and R378 After that it suffers DC cut by C360 and integration by R369 and C415 then is input to pin 24 of Q501 On the other hand video ripple in video output circuit power supply 200V suffers DC cut by C475 and is inverted in Q470 then input to pin 24 of Q501 via C481 Pin 24 of Q501 is a bending correction terminal The voltage which is applied to this terminal controls phase of video signal to correct white peak bending 9v Q501 R375 Q361 Q362 R360 R367 OUT 43 ANN AN R364 G OUT 42 ANN Q360 R365 R378 B OUT 41 R368 R366 77 C360 R369 EHT 24 ae T AM Bending correction C415 Integration terminal L Receiving Board e Power Def board 200V SR481 p483 LEEND C481 Inversion R478 D406 Mm H 3 416 0470 475 D470 5 R482 484 D474 C466 0 White peak 77 77 77 Bending by white peak Fig 12 13 White peak bending correction circuit 12 11 4 3 H Blanking 4 3 1 Outline The H blanking circuit applies a blanking precisely for the horizontal flyback period so that undesirable pictures folding does not appear at screen
117. r of the six discrete tracks on 70 mm Dolby Stereo magnetic prints but in this case no decoder is needed Home viewing of movies on video has become extremely popular and with the advent of stereo VCR s stereo television and digital video discs the audio side of the video presentation has improved considerably inviting the use of full range sound reproduction The ability to deliver high quality audio in these formats made it easy to bring MP Matrix encoded soundtracks into the home as well thus establishing the foundation for Dolby Surround 2 THE DOLBY MP MATRIX One of the original goals of the MP Matrix was to enable Dolby Stereo soundtracks to be successfully played in theaters equiped for mono or two channel stereo sound This allows movies to be distributed in a single optical format and furtheremore results in complete compativility with home video media without requiring separate soundtrack mixes Since the three front channels of the MP Matrix are assembled in virtually the same way as a conventional stereo mix left into left center equally into left and right and right into right playing a Dolby Stereo soundtrack over two speakers reproduces the entire encoded soundtrack There is but one exception the surround signal though audible is not reproduced in its proper spatial perspective When the first home decoder was developed in 1982 its goal was to restore this lone missing dimension Before we discuss decoders
118. r the input pin for multiplex sound IC Stereo OV Other 5V Other 5V TV R Out SURR ON OFF L Out Then both are fed to the matrix circuit At the same time each of the stereo pilot signal fH and the SAP pilot signal 5fH is also demodulated to obtain an identification voltage With the identification voltage thus obtained and the user control voltage are used to control the matrix The audio signals obtained by demodulating the sound multiplex signal develop at pin 10 and 11 of HIC and develop the terminals of 12 and 14 of the module DAC out1 TV DAC out2 RFSW TV waveform detection TV waveform detection output R output L To AV select circuit Fig 2 2 Block diagram of MVUS34S Table 2 1 Matrix for broadcasting conditions and reception mode OSD display Broad casted Switching mode Stereo SAP STE SAP MONO STE SAP MONO STE SAP MONO STE SAP MONO Stereo Stereo SAP Mono SAP 227 lt lt lt 222 lt lt lt lt 2 2 3 Note Of the mode selection voltages switching voltages for STE SAP MONO do not output outside the module They are used inside the module to control the BUS 1 4 A PRO Section Audio Processor All these processing are carried out according to the BUS The S PRO section has following functions signals sent from a microcomputer 1 Woofer processing L R output 2 High
119. rgence Adjustments How is this different from previous Toshiba PJTVs In the Option Menu How many different languages are there What are they used for What is Channel Label Used for NOTES SECTION TWO DISASSEMBLY amp SERVICE POSITION Follow the procedure listed below to gain access to the tubes and circuit boards 1 2 Remove the speaker grill by holding the sides and pulling straight out Take out the four screws holding the plastic shield in place Then remove the shield Remove the control wires from the holder on the metal shield in front of the CRTs Remove the 4 screws holding the metal shield in place The shield is notched so slide it to the right then down to remove it Remove the two screws holding the front control panel Then release the tabs on either side and let it hang down out of the way Remove the 4 screws holding the bottom of the screen Then lift up on the top of the screen and pull it away from the cabinet 7 Remove the 5 screws holding the back panel Then remove the back panel 8 Reattach the control panel to the light box 9 Remove the six screws on the front of the light box 10 Remove the three screws on the back of the cabinet 11 Remove the one screw holding the back of the light box to the cabinet 12 From the front of the set lift the light box up just a little and pull it towards you 13 Pull the light box all the way out of t
120. rmined by the feedback current of the photo diode side The photodiode current is determined by the Error Amp inside of Z801 which is monitoring the 125V source Thus the terminal current CONT cor responds to the feedback from the 125V output 17 6 When power is first applied the switching frequency is set high by capacitor C866 and resistor R863 resulting in soft start of the switching supply Thus current surge in the POWER MOSFET output is limited to provide stable starting of the supply sources After initial start the circuit operates at its nominal frequency 70 80 kHz CD terminal Pin 9 Latch Delay The Latch circuit shuts the power supply off shut down when a fault is detected Shut down occurs by detecting errors from the following Over voltage protection OVP circuit Thermal shock detection TSD circuit Over current protection OCP circuit Loss of and no recovery of Main B The charging time of capacitor C869 connected to the CD terminal Pin 9 is used to delay the operation of the Latch circuit when power is initially applied If the unit goes into shut down temporarily remove ac power to reset the latch circuit OC terminal Pin 12 Over Current Detect This is to detect over current in the LC series resonant circuit Over voltage protection OVP circuit If the Vcc terminal Pin 10 exceeds 22V typical the Latch circuit is engaged shutdown Thermal shoc
121. sed Processing speed 0 5m s at 8MHz with Shortest PC has two channels One is for EEPROM only command A Self diagnosis function which utilizes the Package 42 pin shrink DIP function of PC is employed PC BUS two channels Function indication is added to service mode e PWM 14bitx 1 7bitx 9 Operation by remote control is possible and controls 8 bit x 6 Successive comparison system and adjustments can be made with no physical contact Conversion time 20ms is possible Bus connector in the conventional bus OSD chassis is deleted Character kinds 256 Substantial self diagnosis function Character display 24 characters x 12 lines 1 B W composite video signal generating function Character dot 14 18 dots inside micon green crossbar added Character size 3 kinds Selected by line 2 Generating function of audio signal equivalent Character color 8 colors Selected by character to IKHz inside micon Display position Horizontal 128 steps Vertical 3 Detecting function of power protection circuit 256 steps operation This microcomputer performs the functions of an Analog to 4 Detec rig function of abnormality in bus Digital converter reception of U V TV and OSD display in line 5 Functions of LED blink indication and OSD indication 6 Block diagnosis function which uses new VCD and AV SW Start Address R W Ack Data Ack DATA Ack Stop condition KK AA condition Approx 180 S
122. t Protect 15V Over Current Protect 30V Over Voltage Protect 15V Over Voltage Protect 15V Under Voltage Protect 15V Under Voltage Protect 200V Under Voltage Protect Active High 125V B R479 14 25V I C471 0471 R472 Protect X RAY Protect T461 OV 4 Switch Latch GATE terminal When the voltage at this Z801 1019 GND1 GND2 terminal becomes approx 1 5V or more protection circuit operates Figure 17 7 Protector Module Circuit 17 9 9 Sub Supply The Sub Supply is located on the Convergence Out Power2 board Figure 17 8 shows that the Sub Supply is a ringing choke converter using hybrid IC STR57041 Operation begins with a start up voltage that is applied through R852 This provides a trickle base current to Q1 internal to the IC Pin 2 of 0802 which causes it to turn on When Q1 turns on the collector current begins to flow During this start up time the current is flowing through the primary winding of T888 through Pins 2 and 5 At the same time current will flow through Pins 7 and 8 which create the detection winding as well as Pins 8 and 9 which create the base drive winding During the first half cycle of the AC pulse no current flows through the detection winding because of the reversed polarity of D856 Pin 9 however provides positive feedback for the base as the electromag netic inductance i
123. the fH pulse developed by counting down from the H sync signal As the H oscillator 32 x fH a voltage controlled oscillator VCO oscillation frequency and phase of which can be controlled with the control voltage is used Next an H pulse signal is created from the fH signal counted down and the pulse is used instead of the H sync signal in the AFCI circuit The AFCII circuit differs in the loop of the count down circuit and H output circuit The AFCII circuit compares phase of a H BLK pulse created by waveform shaping a AFC pulse from the FBT and a phase of the H pulse and detects an error component corresponding to the phase difference 02 if exist and develops a correction voltage V2 corresponding to the error thereby controlling the phase of Q501 H out The H output control voltage varies in a positive or negative direction corresponding to the phase lead or lag of the H BLK pulse from that of the H pulse The phase of H out is varied with the control voltage to make synchronization with the H pulse phase The purpose of the double AFC circuit employed this time AFC II LOOP H DRIVE H OUTPUT CIRCUIT PHASE DETECTION CIRCUIT FBT PULSE AFC PULSE Fig 10 3 H AFC circuit block diagram 18 to improve horizontal jitter under signal reception in a poor electrical field The jitter in the poor field strength and distortion due to phase difference are incompatible That 1s to improve the jitter under poor field strength r
124. the standby power trans former D840 along with C840 output a rectified and smoothed 12V signal for driving relay SR81 and for sup plying the 5V regulator 0840 Q840 supplies the standby 5V 1 and the reset signals for the microcomputer as well as other circuits When the power is switched on 01 ICAO1 the Main Microcomputer sends a high signal from pin 7 to the base of QB30 turning it on This causes the base of Q843 to go high and thereby turn it on When Q843 turns on current flows through the coil of SR81 activat ing the relay and thereby switching the main power on 160 Vdc N Rectified F801 D899 C801 Output ONO 1 D801 i Nae b 117Vac p C810 er I R810 fu de Surge 2501 ul 5 1 dise 0843 All voltages shown POWER during ON condition On 5V fee Off 0V SR81 to MICOM Reset 5Vdc ae T 0842 T840 D840 C840 C843 Figure 17 2 Standby Supply 3 Main Supply Circuit The circuit in fig 17 3 is a current resonant switching type power supply that incorporates a hybrid IC Q801 STR Z3201 The current resonant power circuit is highly effi cient in that it operates with very low power consumption 4 Outline of Current Resonant Type Supply Fig 17 3 shows the configuration for the Current Reso nant type power supply A start up voltage is sent to Pin 10 to begin operation VIN source voltage of 160V is applied to Pin 1
125. ther colors can be interrupted by putting caps on the lens 3 Turn the electrical focus volume for the color to be adjusted clockwise or counterclockwise so that the focus at center of the cross character shows the best 4 Loosen screws securing the lens and move the lens toward left and right until the best focus is obtained at center of the cross character 5 repeat steps 3 and 4 to obtain the best focus Finally secure the screws 6 Perform the convergence adjustment according to the convergence adjustment method controls Remove 4 screws and of the focus block Fig 16 15 16 9 Electrical focus and gun drive Focus pack take off the cover which is in front NOTES 16 10 Chapter XVII Power Supply Notes 17 2 1 Power Supply Overview A block diagram of the power circuit is shown in fig 17 1 The power circuit consists of the following 1 Standby Supply which supplies the 5V 1 Standby to the microcomputer and 12V Standby to the On Off Relay 5 81 2 Main Supply which supplies HORIZONTAL OUTPUT B 125V and AUDIO OUTPUT Vcc 38V The signal process circuits are supplied by 5V 3 5V 2 and 9V 2 via regulators from the 12V source of the Main Supply 3 Sub Supply which supplies 30V 15V and 15V for the convergence output board Standby Supply 12V 0840 F801 T801 802
126. tor electrode N NTN efy y V dynamic ANIA focus circuit or Fig 18 1 Block diagram of H dynamic focus circuit 18 2 2 2 Circuit Operation The H pulse developed at pin 10 of the pulse transformer T461 enters the integration circuit consisting of L450 and The Ci does not exist in the actual circuit as shown in a dotted line is an equivalent capacitance of the stray capacitance of Cs in secondary side ofthe step up transformer T405 converted into the primary side and can be expressed as Ci n Cs The pulse is integrated with L450 and and a sawtooth wave current of flows into Ci Accordingly a parabora voltage V integrated is developed across Ci and this is used as the input voltage primary side voltage for the step up transformer A parabora voltage V2 stepped up and inverted is obtained at secondary side F P terminals of T400 This parabola voltage is mixed with the V parabola voltage described under the V dynamic focus circuit and the mixed voltage is superimposed with the focus DC voltage about 9kV through a coupling capacitor Co and supplied to the focus electrodes of three R G B tubes gt gt a ra a a a 2 of gt 26 2 7 n 1 A 1 n 1 J From FBT O z 2 1V v2 y ME pmts 1 2 RAI code 4 L450
127. ture N i Remote 7 key Remote automatic save T key Fig 15 2 3 2 3 Picture 60Hz mode NTSC Correcting point Horizontal 8 x Vertical 8 Arrow marks denote correcting point The first picture The second picure Cusor red Screen center Blinking Fig 15 3 The first picture Crosshatch pattern Pattern colors are three color display Cursor is blinking in red When changed condition is last memory state Cursor is Data change mode in lighting Cursor shifting mode in blinking Display color shows the color that data change is possible The second picture When entering from the first picture to the second picture correcting wave of convergence is muted for one second During this period the changed data is transferred from RAM 0701 to 2 0713 and saved The second picture is indicated with data on top left of the first picture therefore convergence cannot be adjusted by this picture CAUTION Receive suitable signal for adjustment Decide the center by cross pattern of static convergence in menu and adjust convergence from center to circumference 4 ADJUSTING PICTURE DIMENSION Green picture 60Hz mode NTSC gt gt gt tt gt
128. ty suitable for the programs For example it aims to give the listeners a reality matching to each program they are enjoying in their home listening room so that they can obtain reality of big concert hall or feel as if they are watching a move at a reserved seat in a movie theater decoders INPUTS OUTPUTS L Left R MASTER INPUT LEVEL O Right BALANCE CONTROL O Center CONTROL C C Surround Rt Optional passive center signal ANTI ALIAS FILTER MODIFIED B TYPE NR DECODER 7 kHz LOW PASS FILTER Fig 5 2 Passive surround decoder block diagram 5 3 7 5 WM Sq Jo c s SH From QD01 DSP Q670 AN SW Input Balance Input Buffer Front Addition Circuit Front amp 12 14 L 5 L S gt IN 10 8 i R O en gt gt 10 R S QDO1 9004 From Micro computer QD03 DSP IC YM7128 B 5 d VVVVVN VL Buffer Loi 3NI 5 7 i QDOS 9005 VR Buffer 0906 RO D A ab 3f LPF i QDO6 1 Dolby NR SN A NS ue oe PS i QD07 DQ02 gt gt Audio Processor 002 0640 m Speaker nq R Super woofer Speaker RL As shown in Fig 5 4 sound emitted in a sound field can be classified as a direct sound which directly reaches ears of a listener and refle
129. ure quality with a live video signal END OF LAB 3 15 12 SECTION XVI OPTICAL SECTION 1 COMPONENTS 1 1 Outline of Components Around Neck of Projection Tube Fig 16 1 shows names and mounting locations of neck components around the projection tube LIE Deflection yoke Velocity modulation coil Projection tube Fig 16 1 1 2 Theory of Operation The neck components consist of adeflection yoke assembly D which consists of a main yoke a sub yoke and a centering magnet and a velocity modulation coil 2 The main yoke of the deflection yoke assembly consists of a horizontal and vertical deflection coil and deflects electron beams in horizontal and vertical directions The sub yoke is called a convergence yoke and also consists of a horizontal and vertical coils The sub yoke performs distortion correction and color registration according to correction currents supplied from the convergence output circuits Moreover a centering magnet consisting of two 2 pole magnets is provided at end of the deflection yoke to adjust the raster position 16 2 NOTES 1 3 Projection Tube TP4688J TP4880A Fluorescent screen flat rem 48 60 61 TW56D90 Fluorescent screen inverted R 350mm BT I Fig 16 2 Electrons around the peripheral of the CRT screen come into collision with the A B lenses and are not used thus lowering contrast etc
130. ut it will be heard out of phase which will diffuse the image Since the heart of the decoding process is a simple L R difference amplifier it is referred to generically as a passive decoder This is to distinguish it from decoders using active processes to enhance separation which are known as active 4 DSP CIRCUIT A surround component L R is extracted from L R audio signals coming through the AV SW in the matrix circuit as shown in Fig 5 3 The surround component enters the DSP circuit through the LPF The signal is A D converted delayed by an arbitrary time of 0 100 msec every 3 2 msec by digital process and then D A converted and outputs from the DSP IC The DSP IC develops two outputs LO for FRONT LO and RO for REAR and each output is controlled by the microcomputer for each surround mode The output signal LO for FRONT is added and subtracted with the input signal in a matrix circuit and output from the front speaker in passing through the audio processor and main amplifiers Atthe same time the output signal RO for REAR is fed to the Dolby NR circuit but switched to Dolby surround mode and then output from the rear speaker in passing through audio processors and rear main amplifiers In this case the DSP stands for not only a simple digital surround processor but also a digital surround field processor That is it works to give a simple surround effect but to give effect as if the listener can feel reali
131. ws a connection diagram CPT To prevents this a 200V low voltage protection circuit Under a normal condition Q340 is always on because of 1s provided about 210V supplied from the 200V line Accordingly 0340 collector is kept at about 6 2V or the zener voltage of D341 and Q341 is turned off If some abnormality occurs and 200V line voltage lowers by less than about 160V Q340 turns off and its collector voltage rises So Q341 turns on With Q341 turned on the voltage at pin 14 of Z801 expander exceeds a threshold voltage and pin 16 of Z80 is high level and makes the power relay turn off V circuit CRT D Circuit Defletion circuit 200V 14 GATE PROTECTOR Fig 12 16 12 13 5 HIGH VOLTAGE GENERATION CIRCUIT The high voltage generation circuit develops an anode voltage for the picture tube focus screen CRT heater video output 210V and so on by stepping up the pulse voltage developed for flyback period of the horizontal output circuit with the FBT and supplies the power to various circuit 5 1 Theory of Operation AFC D CRT blanking 4 anode Heater 9 12V ANN C303 Je o Auxiliary 27V iq C447 winding d D302 ER C310 7 R327 E s MN 6 Focus Pack T D460 R469 27 5V gt I ANN 5 D406 R443 210V lt 14 ANN 3 _ Primary 1258 O 2 winding R444 Ir C448
132. ximum value to zero The H OUT transistor is turned on just preceding at the center of the scanning period and repeats the steps 3 1 1 through 3 1 4 stated above FBT VB Fig 13 13 Voltage 8 current waveform in H period ly 0 x 27 P Ag 1 N n N VA 0 EY XT ES IM o IDC Y EE LL VB 0 h A 4 13 14 SECTION XIV CLOSED CAPTION EDS CIRCUIT 1 OUTLINE The CC Closed Caption and EDS Extended Data Services circuits extract data from from the incoming video signal and decode them to generate displayable text information Major features of the CC EDS circuit found in the TG1 C chassis are as follows 1 All decoding performed in 1 chip 2 Capable of processing field 2 data CAPTION 3 4 TEXT 1 2 EDS as well as field 1 data CAPTION 1 2 TEXT 1 2 3 Display of text mode extended from 8 rows to 15 rows 4 64 extended characters to handle Spanish and the like 5 Background attribute capability 8 colors transparent 2 DATA TRANSMISSION FORMAT The CC EDS data is transmitted having been superimposed on line 21 field 1 21H and field 2 284H Waveform of line 21 1s shown in Fig 14 1 Line 21 signal is composed of data of 7 cycle clock run in start bit and 16 bit Sbits x 2 bytes 10 5040 5 s 10 076 s 1 d c R 1 E
133. xternal input status etc Memorizes adjustment data for white balance RGB cutoff GB drive sub brightness sub color sub tint etc Memorizes deflection distortion correction value data adjusted for each unit CONTROL OF U V TUNER UNIT H001 Matsushita EL466L 01 Toshiba EL922L e A desired channel can be tuned by transferring a channel selection frequency data divided ratio data to the PC bus type frequency synthesizer equipped in the tuner and by setting a band switch which selects the UHF or VHF band CONTROL OF DEFLECTION DISTORTION CORRECTION IC Q302 Toshiba TA8859P Sets adjustment memory value for vertical amplitude linearity horizontal amplitude parabola corner trapezoid distortion CONTROL OF PIP SIGNAL PROCESS 04 Toshiba TC9083F Controls ON OFF and position shift of PIP CONTROL OF DIGITAL SOUND PROCESSOR IC QM04 Yamaha YSS238 D Performs mode switching of DSP CONTROL OF CLOSED CAPTION EDS 01 Motorola XC144144P Controls Closed Caption EDS 3 MICROCOMPUTER byte of ROM capacity and is equipped with an internal OSD main Microcomputer TMP87CS38N 3152 has 60k one chip TIC device controls through bus Timing chart See fig function 3 1 The specification is as follow Pin 8 LED is used to source current and is an output Type name TMP87CS38N 3152 only ROM 60k byte For clock oscillation an 8MHz ceramic oscillator is RAM 2k byte u

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