Service Manual - Basic Four Model 2460 Fixed Media Disk Drive
Contents
1. 8 7 3 133 74520 RSTA_A RST NEIGE UE i 5 IA 745240 0007 NA2 3 006 5 NA a PI AIO NAI 01 837 3 NAO 9 19 3 2 d ROM 39 2 p 71355 F7 dE E 7 3 3 4 8 10 11 12 5 T cin p R37 9 745240 5 STDC TIP Pi Bo 000 5 007 P 83 5 5 2006 prao 259 5 5 BOOS A E m 02s 5 L LOSTAT Pi A2 202 713 m IDO4 F3 PUI 9 TOACTV Fe IDO3 IDO a5 IDOI mo IDOO 32 i 9 745240 basic Four corporation OWG NO SCALE A Plis YON TIM TUQ 9I vV P PI P2 FS lt SA _ NO E 1 GND SV 1 5 MAOO 12 UNIT TAG 11 GNO 11 1 GND 2 5 1 SELG 52 SELI 1 GND 1 2 SCLKH 3 12 MAOI 53 12 3 USBO 3 SCLKL 4 72 MAOS 54 PRIN 4 GND 1 4 GND 5 1 55 MAOZ 2 5 USBI Qn 5 RDTAL 9 CHPI 6 7 GND So GND 1 b GND 1 7 2 2 12 DMACKIN 57 DMAIS 12 7 582 11 7 GND 8 13 Qpo7 S8 QDos 13 amp GND 1 8 RCLKH 12 MAOT 9 MA 4 12 59 IDOS 13 9 usB3 I 9 13 Qoos O 13 13 IDO 20 13 GND N O GND Z 02 13 IDO amp e IP3X 13 11 CLTAG WCLEL 12 MA O 2 13 IDOS3 02 IDO2 3 12 GND 12. VAA 4 RADO 4 RAD 4 RAD 2 4 RAD3 a 225 4 RAD5 4 RADG 5 4 RAD 2 3 820 2 745240 Ep Ag A7 A 5 4D 01 0405 Q4 03 02 0 35355599 0101 A Os aq 217 Y BE HL 6349 a la lle 191817 6349 9 TQ T RU m mI JOE SE 5D 970 Gs Q4 030 0 Qa G7 Q Q5 G4 Q5 Qo Qj EET EE 19 ho hs ie 5 12 flo fo He je 39 M23 R M 31 ROM 3 13 y y RUM 15 57 Een 5 RON PAR ROM 38 R MO 7 14 isu ROM 29 ROM 37 AMOS 6 7 ROM I3 R M2 55 7 345 R M 36 BMO4 27 12 ee RZMZ0 567 ROM 28 34 ROM 35 9 REMOS 0 RAMI i REMIS 51 7 ROM da Ram 34 27 RAM IO ROM 1B 5 7 ROM 26 3 TETI 0 7 5 0 9 ROM 25 4 ROMO fon ROM O9 6 6 un Sp PUI REM 24 5 ROM 32 4 REM OO 67 R MOB 7 ROM 16 5 27 4 5 2 PRLE PU 0 PU 9 PU I 0 903022 uM 24 YON ITIM ATUQ 9 24 419 4 8 SFLAG 2 8 DFLAG 2 DXX INSYNC 10 ZERO ROM 29 ROM 30 REM 31 REM 28 4 2 2 2 4 13 2 ROM 36 NAI 2 ROM 37 2 ROM 38 74525 4 WAY ye 20 4 13 903029 SCALE Dl REA peureiureWw eg YON ITIM ATUQ 9 YV imi
3. 2 2 Interrupt Logic e 2 2 Tople CRC Logic e e co c o o o o 2 3 Radial a y wc eee we aa ALSO Bus Logic e e e o 2 3 Interface Requirements e 2 3 Electrical Interface a e o o o 2 3 CPU Interface e 2 3 GLOSSARY OF SIGNAL NAMES Glossary A3 1 REFERENCE DATA LIST OF ILLUSTRATIONS Page System Interconnection e e e o Al 1 Disc Interface and Tag Bus Decode e e 4 Al 2 Block Diagram of Controller A2 1 A iii APPENDIX A SECTION 1 INTRODUCTION 1 1 GENERAL DESCRIPTION The Disc Controller provides the interface between the CPU and Disc Drive It interfaces the 2460 Fixed Media Disc Drive to a Basic Four data processor in a system configuration See Figure A 1 for a typical system interconnect diagram BUS CABLE CONTROLLER RADIAL CABLE TERMINATOR Figure A l System Interconnection Al 2 PHYSICAL DESCRIPTION Ihe Disc Controller hereafter referred to as the Controller is a single PCB plugged directy into the main card cage of the processor
4. 85 SEC TOR LE u nn ll FAULT 4 24 SEEK ERROR a3 y 4 57 ON CYL 5 1 2 READY 49 SEM AA 5 EI 5 V SOUF DIUF GV 5WV ezo A S 3 23 X 330 ATERIAL MAX MAX SCHEMATIC DIAGRAM B4 DETAIL e APPRO Y TERMINATOR 9 8 8 gt 2 9 0 SHEET or CEZAR APPENDIX DISC CONTROLLER FOR MODEL 2460 FIXED MEDIA DISC DRIVE SECTION 1 Al l Al 2 Al 3 Al 3 1 Al 3 2 Al 4 SECTION 2 A2 1 A2 1 1 2 1 2 2 1 3 2 1 4 2 1 5 2 1 6 2 1 7 42 1 8 2 2 25251 A2 2 2 SECTION 3 1 SECTION 4 TABLE OF CONTENTS Page INTRODUCTION General Description e e e Al 1 Physical Description gt o Al l Physical Requirements e gt Al 3 Physical Envelope e e 2 o ee e o Al 3 Mounting e e e e e Al 3 Data Reliability e 6 o Al 3 MAINTENANCE General Description e e 2 1 Controller o 2 1 Microprocessor e e e Ar DMA Logic e e e e 2 2
5. i i l 1 i uu o A gt AC WNOOT UD eem CONNECTOR CLINE FILTER P SOMH 504 H T MF CHASSIS GND QI NEUTRAL SAT Ls SED E eee SED eee ee _ rode ueque ee EAT a FILTERED POWER SUPPLY ae gl qs 22222 A mete A 121 330357 94 ION IIIA UQ 0776 ERE Ss 31 SEE TE ve BRS 526 227 OTHERWISE NOTED amp 4 TERMINA TOR 222 CY nn E ira a RE SURFACE uei comens outsor 83 13 00 IC 200 38 TREATMENT BROKEN apro CALER ION TUO PAS UNIT SEL TAG UNITSEL gt t UNIT SEL Z UNIT SEL 4 7 _ M 2 9 7AG n yia EEE TAG 2 gt n4 7AQ 15 yz 13 BUS 7 2 SAS JE AUS 19 E 14 2 BUS 2 27 oe ome 2257 AUS 3 23 I 1 i BUS 4 DIT 7 AUS lt 27 2 0 BUS 292 gt 42 5 7 SS BUS 8 SU INDEX gt
6. 07 VA A l BASE FLATE 2 o 5V 2 lt rp peu 2V Of C54 C78 C92 C94 96 cor Lever C109 CHS cred 24 m cas lt C124 CI80 417 9g JON UO HZ SV v I S See m 2 14 Reference Only Will Not Be Maintained eg ION ITIM ST S SHT 2 5 7 2 2 4 507 2 5 SPD CONTROL 24V 2 E in Ud IW 47 K N ZEV Osc BLACK 7 2 24 6259 1 52 GREEN 1 a REO U 6 75 u SAT 2 AS SHT2 OFF e 20 520 RI SWITCH MODE AA LED DYNAMIC BRAKE io a AOR mE SCHEMATIC DIAGRAM TOLERANCE UNLESS OTHERWISE NOTED 4 MOTOR CONTROL a C KR mann pre 3 254 7 gar edh 200084 24 ION TUO 31 6 2 2V pes 2 24 A C27 24 2 ae Or Em gt Y 95 R33 c33 A23 30 Sx F7QOPF 7 25 7 c23 77214 MO RSS ASY sur y e A T cer 44353 ony e e Ww ra js RPZ fe Q gt lt ex f ER 7
7. 8 9 11 12 13 HOM 01 ECT ROMO3 EG ME 8 9 11 12 13 ROMOS 4 ROMOGb F7 2 07 8 I3 2 ROM O8 gt REM 18 ROM 19 Ro 2 ROM 20 IK 2 ROM 14 2 ROM 15 Q 2 ROM 10 DEL FL e ROM 17 RAN SON 4 oy 2 5 CRY 3 pt G yy Buz gt Elan RST 2 RSTHA 4 13 a AR ER 5 Be c HFT EE cy AMO 2 BOM E MOTA ERDR SI 745182 gt 2 CRYSAV R7SAV Q7 SAV C 903029 Me SCALE ile 214 24 YON ITIM K UQ OI vV SERIN yi DCLK WRITE 4 0 name Pap a 2 to LDBREG 1 Put 5 LDDREG 7 F7 Q Elo DM7 FA 7 Q DMD 5 Wee DMA F2 x Q 9 DMO 5 0 12 40 p o 12 AOE 149195 10 READ 12 DMASTE 3 851 SFLAG 3 745374 303029 E SCALE peutejurew 24 30N ITIM TUO 92uo912j2W 13 2 CPH2 2 E 12 74504 5 15 lo 5 WCS 17 gt 3 1945 8 11 13 745240 745240 9 19 19 gt A fr lt 4 Tp2 2 2 TO 45 7 CPH2 2 18 PI B22 p 5745240 CPHI plo io lt lt A e Ul X RUM 2 gt 5 CHCLK 3 RST A nr Fo F2 6 E DECCNT 7 7415193 ZERG 3 IT 745240 basic Four co
8. EAE O zx zc a Bet ED s o ds Goes vp se TP m A des amp Reference Only Will Not Be Maintained 5 2 2 HAD 42 0 7 PREAMP PREAMP B SATZ SATZ eg ION UO 5 5 7 5 47 7 47 8 7 amp HEAD 2 4 2 47 9 7 10 477 7 HEAD Al 400 OK 294 4 722 8 ACT UNSAFE SHTO 1414 42778 70 SAT 9 SEC 2 PUT HAD SEL 00 E74 100 SWT 9 PND SEL f 7V 7225 MULTI SEL SHTIO 18 48 775 100 SAT Y FWET GATE SWT FWRT CLA WRT GATE SAT 3 0 9 2W22 7AN eva ZVA ION ITIM ATUO 99U919Jay 7 5 SHT I DPCAMP E ROO LARK c24 AMP A SHTI cial 56 DIGITIZED 757 READ DATA RIZ IK R22 4 70 77 fo 3 28 1 2 ES ON 1 tele AH 2 Z wv d z 5 e 2 RP 7 4 15 173 251 0 04 2 7 2 FHASE ERROR 0159 5 222 7 5 52 72 4 72 2 622 5 89 DATA 22 706 0 3 2 o enpi 5 RP2 7 e A Ar SAT 9 ACAD GATE 47 Sir SYNC RJE ZK PLO 8 MUE SATZ 28 Of 22369 REAL RAS 430 100 R37 Shes 5 02 tap cia OF 390RE C31 O CRE CIB 210 PE 40 pve 50 1K 2 7 5 ZEMBIEN 5 0 c29 27 27 725
9. Mg i vos ES ES i H H EE amo f E seven H x lt ern en VAT Vn te eret ER ANS E 2 Pe tro H RATTEN eg verres S Ve VIALE n PEN Mts AVE 5 lt amp i Lm eem Stt ves fe d zo IM 2 Fold and staple BUSINESS REPLY MAIL FIRST CLASS PERMIT NO 4388 SANTA ANA CA POSTAGE WILL BE PAID BY Basic Four Information Systems Division Management Assistance Inc 14101 Myford Road Tustin California 92680 Attention Manager Field Service Technical Publications Department NO POSTAGE NECESSARY IF MAILED IN THE UNITED STATES
10. must be removed from the system before the power supply can be removed for adjustment Once removed the power supply can be placed near to and recon nected to the Disc Drive To remove power supply for adjustments use the following procedure 10 11 12 13 3 4 NOTE There is no power switch located on the dc power supply Power will be applied when the power cord is connected Remove ac power from the host CPU Open host CPU cabinet to gain access to Disc Drive if required Remove ac power plug at rear of Disc Drive power supply Remove Disc Drive Disconnect dc power supply connector J3 from Main Logic PCB Remove six retaining screws securing power supply to deckplate Remove power supply Locate adjustments refer to Figure 3 3 or 3 4 With power supply removed reconnect power cable to J3 of the Main Logic PCB Reconnect ac power plug to power supply Apply power to host CPU Ad just voltages If power supply will not meet tolerance it must be replaced Turn OFF power at host CPU 14 Disconnect power supply from Main Logic PCB 215 Disconnect ac power plug from power supply 16 Reinstall new power supply in Disc Drive 17 Apply power to host CPU 18 Test voltages Measurements will be done at connector J3 at the right rear of the Main Logic PCB Ground meter at C186 on side with C186 designator Check voltage on J3 Pin 2 24VDC 1 2VDC Pin 5 5VDC 0 25VDC Pin 3 5VDC 0 25V
11. ved MAN esee ge ntt petens 3 n a i s 1 5 i 3 H i 3 H i 3 i i B i E S I eda etel TOS 3 MU an 4 PER EE RUTRUM 4 ce oot T E Rutas non Me nta e AR te VEA SAY vorge gv i f R3 il wer cde l f y H x i 4 E E i N i i 1 5 R 5 i i i E E i N er Ate A H usd vss Sco eo S sin conve esee EM wegen ip boe ux ines De Aum ovv h 3 x t E i E PO H N i i 5 2 3 5 5 i 3 Mas emen 90 fe SARI A na an i M diss ehe vemm T P orto AS HUNE OM i ad us E rs rer enne get tere denn N A i E x es conto a eM 4 MOIS e A OS tee na E i i AULAS MEAR LEE spr nahn cen denis TH 24 HH p 4 7 4 BAA a HARDI bud o i ee TTE TENER e rua H t F A nn ert rp ange aaa wets Pay SER Ze FERNER n aas e ANSA
12. 3 NAS 3 42 R 2 FI q 2842721 be 7 4 5 STDC 3 RST 745157 745 314 74500 gt 74508 C 903029 gt SCALE 4 14 24 ION IITM TUQ 4 L7 N TO 2 2 2 2 9 RON25 ROM 24 ROM23 ROM 22 TO 749138 DESTINATION CLOCKS 745138 13 13 13 13 13 LDUDB LDLDB CHCLK LDSTAT 3 z CLRCRC 10 A 410 11 13 13 LDDREG LDCMB 8 LDCLB LDADRL RESERVED 2 2 DO7 2006 DOA D03 002 _ 748240 259 dG 12 y 745139 je RDDMX 745253 DB7 7 DBO 7 DB5 7 DB3 DB2 e DBI 6 9 NO C 903029 QQ 7 PU2 7 Q7 SAV 0 CRYIN 7 2 ROM 13 7 R7 SAV RAMO 7 ROM OO 3 op 2 B 155 jo 745139 FO 89 10 11 12 13 0 ET B 10 112 13 6 FZ amp 9 10 II 12 13 6 ag ION ITIM UQ F3 B 9 10 11 1 12 0 ZER R 3 7 GNCRY 7 PRCRY 7 SHFT Q5 SHF T R3 v 8 VV basic rour corporation Fe OWG NO REV C 903029 5 __ Fifa 14 6 SHFTQ3 SHFTR3 9 21 29 5 084 5 DBS 36 89111213 5 S DB7 5 4 E TO F5 1 O
13. However several of FORMAP s options can be used for diagnostic purposes The six options are 1 Surface Read will read the full surface of the disc and report all exceptions to normal status which is 40 HEX 2 Fault Map Report will display the contents of the fault map which contains all flagged tracks and their assigned alternate tracks 3 Selected Track Certification will read original data of a track store it test the track and if found bad or manually reassigned copy that data to the alternate track and flag the original as bad REQUIRES OPTION 4 TO HAVE BEEN RUN PREVIOUSLY IN A FAULT MAP CREATED BY OPTION 4 4 Full Surface Certification will destroy the contents of the whole disc test it for flaws create a new map and write a bootstrap in sector zero The serial is kept in the map and once assigned cannot be changed REQUIRES AUTHORIZATION 5 Logical Sector to Sector Head Cylinder will convert the logical sector number to the location of the disc surface by physical sector head and cylinder 6 Sector Zero Recovery will rewrite the bootstrap in sector zero using the serial stored in the map REQUIRES OPTION 4 HAVE BEEN RUN PREVIOUSLY IN A FAULT MAP CREATED BY OPTION 4 3 3 3 4 ADJUSTMENT PROCEDURES 3 4 1 POWER SUPPLY ADJUSTMENTS One of two types of power supplies are found on the Disc Drive P N CP353 1 and Model 2981 Regardless of which type is found the Disc Drive
14. Remove Main Logic PCB located on top of HDA Remove Motor Control PCB located on bottom of HDA Remove dc power supply located on bottom of HDA Replace Disc Drve and reverse steps 8 thru l Ensure that all cables and connectors are secure 4 2 2 POWER SUPPLY ASSEMBLY Remove ac power from the host CPU Open host CPU cabinet to gain access to Disc Drive Remove ac power plug at rear of Disc Drive power supply Remove Disc Drive refer to paragraph 4 2 1 Disconnect dc power supply connector J3 from Main Logic PCB Remove six screws securing power supply to the deckplate Remove power supply Replace new power supply in Disc Drive and reverse steps thru l Apply power to host CPU 4 3 4 2 3 MAIN LOGIC PCB AND MOTOR CONTROL PCB When removing PCBs disconnect and tag all cables and connectors Ensure when replacing PCBs that all cables and connectors are secure NOTE When replacing Main Logic PCB remove and save terminator CHAPTER 5 REFERENCE DATA Title Main Logic PCB Schematic Motor Speed Control Schematic Power Supply CP353 1 Power Supply Model 2981 Filtered Power Supplies Terminator PCB Schematic Drawing Number 200098 200099 200083 200084 17048 2981 902 330357 200138 200139 Ep n C Mee eg 177 T e odo 10 FRE HU past PB eig puede 2 cm T 00 E NN
15. Y VELOCITY 7 45 VEL syrs SMF 056 TOLERANCE UNLESS TITLE ine SCHEMATIC DIAGRAM surs E 7 MAIN PC 8 6650 64 f seme 0 eende ______ L rem leer 20009 og ION TITM LS SERVO PREAMP e SHT 4 6 AGC CAOR SAT 2 SHT 4 Swz 4 SATS SMT S SHTI SA7 4 VELER POSITION PON TRA POS M BYTE CLOCK VEL 7 547 8 SAT 8 SATS SHT do SHT FEMD ODD MOV 2S2 72 2 5 RES IN TSOA GA D 2Y __ _ _ _ 2 i sE CS7 OFEN 225r LO 5 QZF PE eo D 58 wy lt d 41 452 SOK 2278 SERVO ERROR 8A Seen R277 C 28 K O82 80 2 CESS CESA cas 2200 PF Y TACH 1509 774705 AGCD SERVO DATA 7430 Cige JA w7 CARRIER AMP SHT 3 9 JS RSE SK C 7 i OPEN a 1 eno 300 2 C97 c 10006 2200 PF 223 yr eur gt 7 SHT 4 7458 LIL F238 1000PF VAS gt sure 574 TEK XING SNT 8 sure 3 LSOO VAS 3 SAT 4 fi 2 I Ama 5300 ee SCHEMATIC D AAGOAM RP234 2K ae A MAIN PC 6650 BF MAA o CEI e Ey ECO AE A pm 140 200099 peuleaurgq eg J
16. mounted on drive frame Figure 2 2 VOLTAGE SELECTOR WAFER SLIDING DOOR FREUE ent p E n FRONT VIEW REAR VIEW ET WAFER SLOT Ep c Y an p 2 FUSE PULLER Figure 2 2 Disc Drive Voltage Selection a Voltage is selected by the position of this small PCB The fuse pull lever situated above the PCB is pushed to the left to remove the fuse b With the fuse removed the selected voltage is read directly from the PCB If a change in voltage is required extract the PCB and reinsert it so that it is properly positioned for the required ac voltage designation 100 120 220 240 Ce Check the fuse value A four amp fuse is used with 100 and 120 volts ac a two amp fuse is used with 220 and 240 volts ac d Place the fuse pull lever in the extreme right hand position and insert the correct value fuse into the fuse holder e No power supply modification is required for changing from 60 cycle to 50 cycle sources 2 4 3 Locate the Main Logic Figure 2 3 and verify that connectors switch settings and jumpers are in their correct position The connectors are listed as follows for Switch Settings and Jumpers refer to paragraph 2 5 Connector Jl J2 J3 J4 J5 J6 17 18 19 2 3 2 INTERFACE CABLING Description Terminator connector or daisy chain cable connector from to another Disc Drive in system Bus cable connec
17. 12 WLLKH 1 GND 3 11 12 63 13 HTAG 13 GND 1 12 1 GND 0 5V 1 1 l WOTAH 12 MAOB 5 1 GND 65 S5V 1 IS 1 5 WOTAL 16 e GND Ct b GND 17 17 DEBSO 1 17 USLCT UN 0 GND 18 MAIZ 2 18 GAD 18 3 9 19 DKBS 1 1 19 20 RTXX 3 20 GND 1 20 3 2 2 DEBSZ 1 2 22 CHP2 9 22 GNO 22 USBO 23 MEAD 2 23 DKBS3 7 23 13 HSDMA 24 24 GND 24 USBI 1 DISC RDY 25 25 DKBS4 25 3 92002 26 002 20 GND 1 26 vsB2 1 27 MD 7 12 27 DKBS 5 1 28 MOD3 12 28 GND 1 29 22 DKBS 6 IN 30 MDS 727 30 GND 1 13 1 2 1 IQ x 5 3 DKBS57 11 3 IDO4 32 IDOO 13 32 GND 1 1 GND 33 MA lo 6 33 DKBSB N GND 34 MDPO 12 34 6ND 1 12 MOB 35 GND 1 35 DKBSI 2 MD 4 35 GND N 36 GND 37 dDpoae 13 37 INDEX 11 38 38 GND 7 349 QDOO 13 39 SCTE I 40 72 4 GND 1 4 MAIT 4 FAULT 7 42 2 GND 1 4 5 MDZ 2 43 SkEPEE I 12 DMAR 44 MRST 13 44 GND 45 45 QNWCLY 1 46 46 GND 1 97 MAIS 12 47 READY 11 48 ACKOUT 12 GND 1 49 DMAINT 13 49 OPNCBL 2 MAO3 50 50 asic Four corporation OWG NO REV 203029 D basic Four Information Systems service Manual Change Request Prepared By Name Title Address Date Manual No Equipment Covered __
18. 21 3 AULT 5 DBSO BSKERR 5 1 gsCu F BRDY 65 NR in 330 BSCTR 3 Gng i BINDX AAA AN 3 OPNCBL P2 49 DISC INTERFACE LOGIG amp 00305 gt SCALE Lo ES 2104 4 16 D O i RDY gt HHR 9 IL uc y E _ 5 DISCRO 5 25 pee re 438 24 ION TIIM TUO Tay 6 587 9 ZEN 3 DMACKIN gt ACKIN 74504 DMASTB 13 7 DMAIS 1 gt 857 5 745240 1 D MADO 51 5 LDADRL Laso Fi 74540 D 4 MAD Tpi B55 245240 8 D MAQ3 aZ 145240 15 D 5 MAM 145240 17 8 MAS 18 145240 13 7 25 Le 745240 T 9 In Le 745240 IDA 1 19 6 D MADE 5745240 8 2 09 n 145240 PIAL D 2 M pru E PEE 745240 2 I8 MAII 5 PI BI3 aZ 745240 5 D MAIZ VES 745240 17 3 MAS PI B9 gt T s gt 8 B E 9 gt Ui F7 BN 59 MaS 5 847 Ades 13 12 7415193 Le 24 S240 7 1 19 2 5 3 MASTB 6 DMASTB DTM2 3 A a 3 10 5 74500 74500 8 ACKOUT 8 DWG NO C 903029 SCALE A EST s 24 ION ITT adUdtazoy GI 9V
19. A pe a H H E E 1 i AA A Hay y sr t MATH Ae bem i kae erts AS tte je le M 4 Cab Ana TO H i gt e v bs an 1 penran IT 4 i aa Mfr f 5 A esee 1 E i d TINO vea D es A REM s ae do i i ds ide d MW rte L4 garen ge ete A AAA af qe NIN MAN pen m E E i t e i 1 H i 4 t t 1 H i 3 bad 55 DM AME NE i i 1 1 00d Mina TRUM P o 7 ay mS di abd voe 3 mde I ES Pel uy Allen a vati rn d beet stt allia seats ap dd PUO V Ve TIN FAM Vall APA AMA ade Au 7 H t i t 4 4 5 1 4 i i P P i 5 i 4 i S i 5 Reason for on ed 1 3 1 E h t 1 4 1 3 4 3 f 5 m siio try ta B gt D voi dp ee Ae Ay ri ra pere nra la erac P En A a bado 3 2 y 1 f d d E f 4 yr tee ae 4 m p Ae 1 PRI iaip AA A ame PM asai nies 4 zi VEN SA AS e
20. CABLE CO no Pro M Po DISC MAIN CONTROLLER PCB LOGIC gt gt 4 oN Y LE tO RADIAL CABLE WRITE CABLE SERVO CABLE READ DATA READ CLOCK WRITE CLOCK SEEK END UNIT SELECTED SECTOR INDEX o mt m TAG 1 TAG 2 TAG 3 BIT CYLINDER HEAD ADDRESS SELECT CONTROL WRITE GATE READ GATE NN ____ CLEAR TRE IN ang REZERO 2048 READ STATUS USED FOR HIGH ORDER CYLINDER ADDRESS DURING TAG 2 TIME EN Interface Cable Pin Assignments and Bus Tag Decode 2 7 2 3 3 DC VOLTAGE CHECK Power is applied to the Disc Drive from the host CPU control panel To apply power complete the following steps refer to system manual for detailed system information l Place power switch in ON position 2 When READY indicator comes on the dc voltage checks may be done using the following procedure Locate connector J3 on the Main Logic PCB of the Disc Drive b Test the following voltages Connector J3 Voltage Check Pin 1 GND Pin 2 24VDC 1 2VDC Pin 3 5VDC 0 25VDC Pin 4 12VDC 0 60VDC Pin 5 5VDC 0 25VDC Pin 6 GND 3 voltages are not within tolerance refer to paragraph 3 4 1 2 4 CONTROLS AND INDICATORS Controls for the Disc Drive are located on the host CPU control panel There are two indicator lamps LEDs mounted on the Main Logic PCB near
21. J8 A green lamp will indicate a READY status A red lamp will indicate a FAULT status Connector J8 is provided to test the following signals Connector J8 Function Pin 3 READY Pin 4 OND Pin 5 ON CYL Pin 6 FAULT Pin 7 PWR ON Pin 8 5V Note Pins 1 and 2 not used 2 8 2 5 SWITCHES AND JUMPERS Drive Address Write Enable and Diagnostic mode are selected on Switch 10N located on the Main Logic PCB see Table 2 1 for Switch selection Ihe Sector switch 12K is also located on the Main Logic PCB see Table 2 1 for Switch selection TABLE 2 1 SWITCH SELECTION Switch 10N Drive Select Address Bit Binary Weight 1 Drive Select Address Bit Binary Weight 2 Drive Select Address Bit Binary Weight 4 Reserved Diagnostic Mode Reserved ON Write Enable All Data Heads 8 OFF Not used switen 12r __ ___ Sector Number SW No Position Binary Weighted 1 1 32 64 Must be in off position SW5 must be placed in ON position when using Diagnostic mode A11 OFF Drive 0 2 9 Jumpers are preset at the factory and shall not be removed Verify all jumpers are in correct location Jumper contacts are listed as follows Three Pin Two Pin WA 1 2 m We 2 3 2 W7 1 2 W3 4 2 3 W5 W11 1 2 W6 W12 2 3 9 W16 1 2 W10 W13 2 10 CHAPTER 3 MAINTENANCE 3 1 GENERAL DESCRIPTION This chapter provides a block diagram functional description
22. ce 0 ya NN 3 ek 1 7229 V 7e K os 1 UN CIV 230 9A D P O 499 24 1 Y Ces O SV CR3 14 5499 C20 T 390 727 5 CONTROL VOLTAGE SV wieV Boss RPI Rit 5 FK 5 ca Of 7 2 la s iu 5 V 4 7D blo In werden i Of 14 I 5 X 1 5 DATA SHT 3 MG syr 3 RPB 4 PHASE WINDOW 7 3 SYACX SHT 3 m TME SCHEMATIC DIAGRAM 7 MAIN 2C 8 6650 584 10 38 40 D 200099 aq ON ITIM ATUQ xSyMcx SHT 2 sur 2 EE ZNDIES DATA WINDOW 4 HREAD CLOCK ur 9 v PHASE WINDOW 4 0 2 5772 13 READ DATA p SHT IO D PP 3 2 ai 7 6 2 3 WRITE CLOCK sure Er 414 SHT 7 CEK ey P CRO 544 9 P 10 wa IF 7 m wie 1 3d me JOOPF pz p C33 2 4 EAE M s 2 ik ees s DO OPF Zaun 76 A E PPLE lo 5V e32 S IK 23 C34 240 R254 c 37 Sy 240 i a TE sur g GATE WRT Sur 20776 rg R73 DE TAGE VOM Vi sur WRITE DATA IK un 7020 PHASE ERROR 470 ceea Ei WET CLOCK ___ 51544 CSS RIO SHT 7 OVS SAK en 10124 5 220PF e us gt RP2I S 57 C48 C47 675 R122 24 37 5 15 T e 7222 vn PHASE ERROR 6 23 lt l
23. less than 1 8 volts ac b Switch the source circuit breaker off Measure the resistance between the green and white wires at the wall outlet The resistance must be less than the value shown below for the applicable circuit breaker rating CB Rating Resistance 15 amperes 0 30 ohms 20 amperes 0 25 ohms 30 amperes 0 15 ohms If either measurement in steps a or b above is not less than the value given request the customer to provide a power source that meets these requirements Remove cabinet covers to gain access to the Disc Drive Disconnect and tag all cables from the Main Logic PCB connectors J2 bus and J9 radial Disconnect power supply plug at rear of cabinet Lock Spindle and Head Carriage locks Remove the four screws holding drive to host CPU cabinet Remove the Disc Drive from the cabinet Make pre power checks refer to paragraph 2 3 1 Replace Disc Drive in cabinet Unlock Spindle and Head Carriage locks Reconnect all tagged cables Reconnect power supply plug at rear of cabinet Replace covers Plug ac line into power source 2 3 2 3 1 PRE POWER CHECKS Verify that the input primary power voltage and the Disc Drive power supply are configured in the same range 1 The following ac voltage ranges are available in the Disc Drive 100 120 220 and 240 volts ac 2 To select the correct voltage range to match the ac input voltage locate the Voltage Selection PCB at the rear of the power supply
24. on or for the bootstrap This signal generated by the DMA transfer logic is used to indicate that the first third of a DMA transfer cycle is underway This output of the DMA control ROM is used to set the address enable flip flop on the next clock edge This is the received servo clock from the disc unit This clock is used to time the flow of data from the controller to the disc unit during a write data transfer The clock is also re transmitted to the disc unit 1 These are the differential balanced line signals for the disc servo clock This clock is always kept in sync with the servo pattern on the disc surface Sector This signal from the disc unit indicates that the heads are currently positioned over the beginning of any sector except sector Zeroe This signal is used to set the D flag any time that the D register is loaded from the processor Ihis signal is used by the processor to set the DMA request latch This output of the DMA control ROM is used to set the DMA strobe flip flop on the next clock edge This is serial data that has been read from the disc zero at all times when the read flag is not set This signal is Serial output of the parallel to serial shift register oet the S flag On the Count of 5 This term is used to set the S flag during read operations in anticipation of loading data into the S register so that by the time that the processor responds to the S flag the data will be ther
25. register onto the main frame memory data bus This signal is true throughout a DMA cycle only when the controller is performing a disc data read operation X O thru 7 This is the processor data input bus Disc Generated Clock This clock is either the disc servo clock or the disc read clock as the occasion demands This signal is used by the processor to decrement the general counter and test for zero result This is the synchronized output of the D flag The synchronization is necessary to prevent a metastable flip flop in the address logic for the processor This is the raw output of the D flag This flag is set at any time that the D register is loaded and cleared when data is read from the D register This signal in the I O control logic is true when IOACTV is true and the controller detects the DIXX command from the CPU This signal is used to transfer data from the controller to the CPU X 0 thru 9 These are the disc control bus signals The information on this bit is used by the disc unit as either control information head addresses or as a cylinder address thru 7 This is the outputs of the S register that are directed to the processor input This is the most significant address bit from the DMA address logic to the memory page control in the CPU This bit is converted to the appropriate page control bits in the CPU DMACK DMAINT DMAQ DMAR DMASTB DOXX DTAX E INSYC FAULT FX H
26. the CRC generator checker set Cylinder Tag This signal is used by the disc unit to determine that the information on the disc control bus in cylinder address information 1 2 These are timing clocks from the CPU The controller runs from these clocks during read data operations and at all other times except during a write data operation This signal switches the CRC data into the serial write data stream This signal is enabled by CRCENB CRCDTA CRCENB CRCERR CRY CRYIN CRYSAV CTTAG DATAEN DBX 14 DECCNT DFLAG DFLG DIXX DKBSX DMX DMA15 A3 2 This is the serial CRC information that is generated by the CRC chip for a write operation This signal is used during write data transfers to enable the writing of the CRC This signal is directly controlled by the processor This signal is generated by the CRC chip to indicate that the CRC that was read in was in error This is the raw carry output of the 2901 This signal is controlled by the ROM and is used to gate one zero or carry saved into the carry input of the 2901 This is the saved output of the carry output from the 2901 to be used for testing carries or shift operations in the next processor cycle Control Tag This signal is used by the disc unit to determine that the information on the disc control bus is control information This signal is used by the DMA control logic to gate the contents of the D
27. the DMA address counter Load the Buffer Register This signal is used during data trans to load the D register from either the memory or the disc deper on the direction of data flow This signal is used by the processor to load the contents of the processor output bus into the lower byte of the general counter This signal is used by the processor to load the contents of the processor output bus into the high byte of the general counter This is a strobe generated by the processor that is used to load contents of the processor into the D register Load Lower Disc Bus Control Register This strobe which is gene by the processor is used to clock the contents of the processor put bus into the lower disc bus control register This signal is used by the processor to control the contents of control ROM page control flip flop Load the Shift Register This signal is used during the write c ation to parallel load the shift register with data This signal is used by the processor to strobe the contents of t processor output bus into the status register Load Upper Disc Bus Control Register This strobe is generated the processor and is used to clock the contents of the processor output bus into the upper disc control bus register This signal is used by the processor to control the inputs to th shift registers in the 2901 for a left shift operation 00 thru 14 These are the main frame memory address lines This signal in th
28. to any of several destinations Set Head Tag This signal is used by the disc unit to determine that the data on the disc control bus is head address information X 0 thru This is the CPU input bus This bus is used to transfer information from the controller to the CPU This signal from the disc unit is used to indicate that the heads are currently positioned over the beginning of the track which is also the beginning of sector zero Literally In Sync The state of this flip flop is used to permit data flow when the bit counter is in sync with the data flow This signal in the DMA interrupt logic is used to interrupt the CPU any time this signal is true and MASK is also true N 1 thru 3 These are the I O control signals from the CPU decoding these bits the appropriate I O action can be determined A3 3 IOACTV LDADRH LDADRL LDBREG LDCLB LDCMB LDDREG LDLDB LDPC LDSR LDSTAT LDUDB LSHFT MASK MDOX A3 4 This signal in the I O control logic is true any time that the troller detects its address in conjunction with a COXX command signal remains true for the duration of the I O transfer Load the High Address Register This signal is used by the proc to strobe the contents of the processor output bus into the uppe byte of the DMA address counter Load Lower Address Register This strobe is used by the process to strobe the contents of the processor output bus into the lowe byte of
29. to the microprocessor when each process has been completed A2 1 8 BUS LOGIC The Disc Bus Interface Logic sends commands to the disc drive and receives FAULT SKERR READY ONCLY SCTR and INDEX from the drive A2 2 INTERFACE REQUIREMENTS A2 2 1 ELECTRICAL INTERFACE 1 Signal Levels All signals will be at standard TTL levels 0 1 to 04 VDC equals logical low 2 4 to VDC equals logical high The clock and data lines to the disc are differential balanced line drivers receivers 2 Termination All TTL signals that pass through lines exceeding 2 feet in length are terminated with 220 Ohm pull up and 330 Ohm pull down resistors 3 Drivers Receivers All TTL line drivers are 7438 or equivalent line drivers All interface receiver lines are standard TTL input A2 2 2 CPU INTERFACE The CPU Interface signals are as follows 1 Master Reset 2 Clock Phase 1 and 2 3 I O Control Registers 1 thru 3 4 Output Data Bits O thru 7 A2 3 5 Memory Address Bits 0 thru 14 and Memory Address Bit 15 6 Memory Data Bits O thru 7 7 DMA Acknowledge 8 DMA Request 9 DMA Interrupt 10 Read Enable A2 4 1 16WAY ADDEN BOX BINDX BRDY BSCTR BYTE CHCLK CLKEN CLRCRC CLTAG CPHX CRC SECTION 3 GLOSSARY OF SIGNAL NAMES GLOSSARY This output of the next address control ROM is used to indicate that a 16 way branch is required This signal is generated by the DMA contro
30. 4 ILLEGAL CYLINDER indicates that the disc file was commanded to seek to a cylinder address which does not exist in the drive 15 DIAGNOSTIC CYLINDER ERROR indicates that the positioner has not moved to one of the Diagnostic Cylinders Cylinder Address Register 2 to 7 CHAPTER 4 SPARE PARTS LIST REMOVAL REPLACEMENT PROCEDURES 4 1 INTRODUCTION This chapter contains the spare parts list Table 4 1 and removal replacement procedures Figure 4 1 shows component locations TABLE 4 1 SPARE PARTS LIST Item MM Part Number Number Number Description 1 290000 903028 01 Disc Controller 2 290010 200098 Main Logic PCB 3 290020 200083 Motor Control 4 290030 200138 Terminator 5 290100 400384 001 Power Supply Assy 6 293010 330410 Head Disc Assy 4 1 MAIN LOGIC PCB TERMINATOR PCB MOTOR CONTROL PCB POWER SUPPLY HEAD DISC ASSEMBLY Figure 4 1 Component Locations 4 2 REMOVAL REPLACEMENT PROCEDURES Removal Replacement procedures are given for spared parts 4 2 1 9 10 HEAD DISC ASSEMBLY HDA Remove ac power from host CPU Open host CPU cabinet to gain access to Disc Drive Remove ac power from Disc Drive power supply Remove four screws securing HDA to host CPU cabinet CAUTION When removing connectors J6 and J7 R W Heads and Servo Head be careful not to bend the pins Damage may occur to the printed wiring Disconnect and tag all cables and connectors from Main Logic PCB
31. 7 E 12 SWITCH MOD yd em LM 339 3p SHT C22 7406 LO 237 ts 330 00 PF SHT 7 ES s aid V WS 24 45V wie n I RAS RST AYS RSS FR 20k IZW E c CAY4 e P 7 gt gt 3 2 22 IN LMI 14339 GAN P 2 2 9 A53 he SV 10 247 97 EN S 5 8 24V HWT RIS RSS CEI 40 9 OK 241339 caza 249 0 A SPD CONTROL SHT SIR SAT 2440 y LOGIC 24 RTN v PWR AMP ev V3 Sy GND nt DIAGRAM 19 22 TOR CONTROL m E 2000 24 ION ITIM uQ LT S AD 26 C3 41 50 AWM ELECT CA 1 1120 10 25V CAPACITOR ALUM ELCT 1QOv __ CAPACITOR MYLAR 15v ALUM ELECT 700 255 4 330 25 HORNO NECE C 5 6 a S o ar 22071 V 0 15 4 8 330 35 ALUM ELECT OVicov CAPACHOR MYLAR BRIDGE CR2 197368 DIODE ZENER CR 49658 DODE ZENER A DODE 22A EAN 4003 2550 CT DIODE IOOV _______ TL DIODE TA 200 23 ______ _ CAPACITOR MAYLAR 216554 TARM amp STOR PNP 242907 TRANSISTO 854 1 20 3055 TRANSETOR T
32. AD SPINDLE ASM BRUSHLESS DC MOTOR SPEED CONTROL CIRCUITS SERIAL INTERFACE READ CLOCK pi mgd DATA HANDLING NRZ READ DATA CIRCUITS INDEX INDEX MARK WRITE DATA NRZ AND SECTOR MARK SECTOR MARK READ GATE SERVO CLOCK DESIGNATES DIFFERENTIAL SIGNALS Figure 3 1 Functional Block Diagram CYLINDER NUMBERING HEA DATA BAND en BAND 2 4 DATA BAND 0 SERVO BAND CYLINDER 1120 CYLINDER O HEAD ARM ASSEMBL HEAD 1 UPPER ARM HEAD 2 5 SP WAMZA 1 SERVO HEAD HEAD LOWER ARM SIDE VIEW OF DISC AND HEADS Figure 3 2 Data Head Positions 3 3 DIAGNOSTIC TESTS There are two types of diagnostic tests available for the Disc Drive Silver A5 and FORMAP For a complete functional description of Silver A5 and FORMAP refer to the appropriate User s Manual 3 3 1 GENERAL DESCRIPTION OF SILVER A5 Silver A5 is divided into two groups 1 Group 1 is designed to check most controller functions and the disc drive s ability to seek and read 2 Group 2 uses the Diagnostic Cylinders to write and format Checks are performed on the controller s ability to detect various errors such as ID Alternate Cylinder and CRC In order to run Group 2 the Manual Intervention option must be selected 3 3 2 GENERAL DESCRIPTION OF FORMAP FORMAP s basic function is to format the surface of the disc create a map of all flaws and to store the map on the subject disc
33. ATA A4 1 598 Id 92 v9 E 395 an 585 Fm 8291 SID lt gt Ly C920 p nar pum 4 II x 2s ra i 2 9 IE gt m ER 4 9 LIO e Jen IM Lom voco 5622 goc o e2oc o t tan aen faon E380 5 19 ZU on fe Pec 820 220 ID rg C43 Com oen osn foon Eon som LEID Dora gt gt lt a CAI Fuge Eon ns ren 214 101728 Std N A4 2 Reference Only Will Not Be Maintained 24 ION TITM ATUQ t7 BACK UP ALPE 5V 45V PROT PRIN SEL SELI 5V SV 5 RI 220 PUI R3 gt 220 PU 2 25 220 1 2 5 8 3 12 15 4 6 7 9 10 12 13 9 22 330 5V RS 220 u F ELT 9 10 11 12 lO RS 330 m f I TIT men basic Four corporation pec UNLESS see 1335 South Claudina Street Anaheim California 92805 X n DRAWN jy 77 mse exo LD FIXED DISC CONT MFG C SERERE MACHINED SURFACES E C 9 Q 3 0 2 03025 597 Next assy useoon OONOTSCALEORAWING T I 14 psautezutey 24 ION IIM TUO
34. Basic Four Model 2460 Fixed Media Disc Drive BFISD 8052 Service Manual Basic Four Information Systems The information contained herein is proprietary to and considered a a trade Secret of Assistance Inc pgs rights re No of this e publication may Had reproduced recorded or stored in a retrieval system or transmitted in any form or by o _ any means whether electronic mechanical photographic or otherwise without prior written permission of the Basic Four Information Systems Division of Assistance Inc T m Is E E Al Il Rights Reserved BFISD 8052 Copyright 1981 by Management Assistance All specifications are subject to change without notice Basic Four and MAI are registered trademarks of Management Assistance Inc a Printed in the United States of America Basic Four Information Systems Division Management Assistance Inc 14101 Myford Road Tustin California 92680 714 731 5100 gt CHAPTER 1 EM ES E GU BRO 63 62 NN PO Out E CHAPTER 2 e Un Go WH CO 0 Mm ND U N N orm N N NIN N KM PD HD PND CHAPTER 3 e e e e e e N 9 e wW N m ES e MN WOW CO CO Co UY UY DH Uy e Un g PPP F 9 9 e TABLE INTRODUCTION OF CONTENTS General Description Figure 1 1 Phy
35. CONTROLLER Page 4 1 4 3 4 3 4 3 4 4 LIST OF ILLUSTRATIONS Figure Model 2460 Fixed Media Disc Drive e Spindle and Head Carriage Lock e o Disc Drive Voltage Selection o Main Logic PCB 64 Interface Cable Pin Assignments and Bus Functional Block Diagram o Data Head Positions e e o Power Supply Adjustments P N CP353 1 Power Supply Adjustments Model 2981 Write Current Adjustment Data Window Adjustment e e e e o o Component Locations e e e gt dada dd e NV PU ho I WN LIST OF TABLES Irc Specifications o gt 2 1 Switch Selection e e e o o 3 1 Fault Isolation o 3 2 Status Bit Description e e o 4 1 Spare Parts List e e o Decode FO 09 b N Page 1 3 2 9 3 9 3 13 4 1 CHAPTER 1 INTRODUCTION 1 1 GENERAL DESCRIPTION FIGURE 1 1 The Model 2460 Fixed Media Disc Drive hereafter referred to as the Disc Drive is a fixed media mass memory device used for data storage with a maximum memory capacity of 66 Megabytes The Disc Drive contains a single linear voice coil head positioner with three data read write heads and one servo read only head It has a spindle assembly with a single 14 inch disc and br
36. DC Pin 4 12VDC 0 60VDC Pins 1 and 6 are ground Use only an insulated shank screwdriver Damage may occur to the power supply Adjusting of power supply will require a long five inch insulated shank screwdriver with 1 8 inch blade 3 4 1 1 Power Supply P N CP353 1 Three voltages 5 5 and 24 must be adjusted by reaching through holes inside the power supply chassis as shown in Figure 3 3 The 12 is not ad justable Voltage Ad justment Wire Color Leaving Supply 24V R20 Red return is Brown 45V RAO Black return is Grey 5V R38 Yellow return is Grey 12 Not Adj Orange return is Grey Su gt Y 5 VOLT ADJUSTMENT R38 24 VOLT ADJUSTMENT 5 VOLT ADJUSTMENT R20 RAO Figure 3 3 Power Supply Adjustments P N CP353 1 3 4 1 2 Power Supply Model 2981 On this power supply the adjustments are visible externally as shown in Figure 3 4 Voltage Ad justment Wire Color Leaving Supply 24V R3 Black with White Lettering return is Yellow 5V R14 Red return is Solid Black 5V R20 Brown return is Solid Black 12V Not Adj Orange return is Solid Black R20 5 VOLT ADJUSTMENT R14 5 VOLT ADJUSTMENT R3 24 VOLT ADJUSTMENT Figure 3 4 Power Supply Adjustments Model 2981 3 4 2 WRITE CURRENT ADJUSTMENT For this adjustment you must be writing all ones Do not use Head 2 Do not use any tracks which could contain customer data Write as many sectors on o
37. Drive is normally shipped as part of a data processing system and unpacking packing instructions are included in the appropriate system manual When the Disc Drive is shipped as a replacement unit the following procedures should be followed 1 Visually inspect the container for damage Report any damage immediately 2 Remove Disc Drive from container and place on work surface 3 Visually inspect for loose bent or broken parts Report any damage immediately 4 The head carriage and spindle locks refer to paragraphs 2 2 1 and 2 2 2 are in the locked position for shipment If received in the unlocked position DO NOT INSTALL THIS DISC DRIVE 5 When shipping a Disc Drive back to the factory ensure that the spindle lock and head carriage lock are properly installed locked and the Disc Drive is packed to prevent damage in shipment 2 2 1 HEAD CARRIAGE LOCK Power not being applied to the unit place the Disc Drive in a flat position with the Main Logic PCB facing up The head carriage lock is located at one end of the unit indicated by arrow on the mechanism Avoid manual rotation of the spindle or movement of the carriage Damage to the disc surface may occur 2 1 Pull up on the head carriage lock until free from its locked position Rotate the head carriage lock to the unlock position as shown in Figure 2 1 The head carriage lock must be placed back in its locked position when the Disc Drive is moved SPI
38. ED Channel 2 should NOT be inverted Time base 0 1 us with XIO mag TRIGGER SOURCE Channel 1 dc coupling NORMAL mode Adjust R32 so Positive Going edge of Data is in center of low going Window pulse Figure 3 6 NOTE It is normal for the display to jitter DURING READ FRONT REAR OF WINDOW OF WINDOW NOTE DURING WRITE DATA MOVES TO REAR OF WINDOW Figure 3 6 Data Window Adjustment 3 5 FAULT ISOLATION Table 3 1 lists the Fault Isolation procedures for the Disc Drive Table 3 2 lists the Status Bit information Both tables are designed as an aid in troubleshooting the Disc Drive TABLE 3 1 FAULT ISOLATION Spindle Rotation Possible Cause Suggested Action Rotation does Spindle lock Place in Unlock position not start Incorrect or missing Check power supply voltage at Main PCB connector J4 OFF signal J4 4 Check microprocessor reset signal is 5 VDC should be on Main Logic PCB should be volts for rotation false Check Power On reset POR should be false Check power reset PRST should be false Defective Motor Check J1 5 of Motor Control Assembly Control Assembly for 12 volts LED voltage Check fuse in Motor Control Assembly 3 9 TABLE 3 1 FAULT ISOLATION continued Spindle Rotation Possible Cause Suggested Action Rotation does Defective Photocell Check for open LED defective not start Circuit Board connector or phototransistor Defective Spindle
39. EL 3 GALZ GEC ERST 2275 DE A 287 77 28172 SER ETE 1 ARES 172152 ode pe 9 DEI ali pn Ut 061165 gt US DASA LES lps AE Ye TE AE 77 DB2A O 1 3 D Ki TL A LL lt are SHYT 10 DAC ST e DAC SN MC E SHT e DAC 3 oS Bact SHT 6 DAC SHT 6 DAT SHT HET SHT 2 24 SHT 10 LETS SHT 10 227 SHT 9 ADO m 577 9 SATS AD3 SHT 9 RDLB 0278 5777 9 aD SHT 9 TRA is SATS AGES SHT LAE J4 4 roDD SHr4 TEWD SHT S POSM WK SHTS 25 4 lo TR Spr HL CY SHT O spr O Ty of Ten SHT 9 15 4 SHT 3 IK ERE SHT 79 10 LOK PEO SHT9 T ERST A SHT cio me SCHEMATIC DIAGRAM MAIN P C 26577 BF 2000 99 C REND C39 547 7 SHT 7 SHT D ri D D gt r2 r2 SHT 7 rt SAT E SHUT 8 X sur 8 SAT 3 z 2 Su 8 SAT 8 D Wr pte Ke SHTES Qu Surg SAT 7 SHT amp SAT 10 SHT 8 6 __ 7 771 gt 2504 4 Me 2 gt sf a 3 0 RESET SK REQ lt 50 574 4 42 89 ADU5 ADEN ALD AD RD SECTOR RESET AD3 BVIE CLOCK 73 ERA 2 5023 C 63 A 33l SCOFF OK SV 2 S Vom 3 ETZ REQ ges SK REA SHT SK
40. Manually rotate spindle in clock Motor wise directly only viewed from bottom to ensure motor is not binding If motor is binding replaced Disc Drive NOTE Rotation in opposite directions may damage disc Spindle rotates Carriage Lock Place in Unlock position and stops after about one Defective Motor Replace Motor Control Assembly minute Control Assembly Defective Photocell Replace Disc Drive Circuit Board Speed Control not Defective Main Logic PCB being sensed by Microprocessor Spindle Motor has Replace Disc Drive excessive drag Spindle rotates Fault Condition being Check Fault Status but unit does sensed not come Ready or Ready condi Intermittent power Replace Power Supply tion comes and supply failure goes Defective Main Logic Replace Main Logic PCB PCB Defective Motor Replace Motor Control Assembly Control Assembly Defective Disc Drive Replace Disc Drive Incorrect state on Unit Selected J9 21 Selected unit does not issue status Select unit does not accept commands Select Unit issue Seek Error Select Unit fails to issue Index Symptom Fails to move to new Address Continuous Seek Error condition TABLE 3 1 FAULT ISOLATION continued wer Command Status Transfers Possible Cause Suggested Action Device address select switch 10N Open Cable Detect true Jl J2 pin 28 Unit Select Tag or Unit Address missing
41. NDLE LOCK Figure 2 1 Spindle and Head Carriage Lock 2 2 2 SPINDLE LOCK Power not being applied to the unit and the Disc Drive still in the flat posi tion locate the spindle lock near the center of the unit opposite the voice coil motor as shown in Figure 2 1 WARNING Ensure power has not been applied to the unit when the spindle lock is placed in its unlocked position The Spindle motor must not be manually rotated when unlocked At this time the fan is free to move and can present a hazard to the Service Representative Place the spindle lock lever in the unlocked position refer to Figure 2 1 The spindle lock must be placed back in its locked position when the Disc Drive is moved 2 2 2 3 INSTALLATION PROCEDURE The following procedures detail the necessary steps to be followed when installing a replacement Disc Drive l 2 3 10 11 12 13 14 15 Verify the power switch is OFF and the ac line cord is not connected Check that the ac line includes a third wire earth ground that meets or exceeds the requirements of the National Electrical Code This can be checked by the following procedures Locate the circuit breaker that is to supply power to the host system With a digital volt meter set to measure 20 volts ac and the circuit breaker turned on measure the drop between the green and white wires at the power source for the system wall outlet The measured voltage must be
42. ON TUO 92u28128jey 876 Sw7 a SNTE 3 SW7 8 597 778 SATS SNTE SA7 8 CESS SA7 SHT 4 SAT 3 740 CQ AGCC TA SAT 2 Zul ev 4 99 1 DAC 6 5 DA 5 va STE TOH 12 IrN o ai 10 ZA 3 8 exo 1 gt NT C2 7 343 aCe mer RACE POST 75044 CI 000 PrF 19 74 5V 53 gt 9 IQ CURVE DA swre E 1072 14 7772 gt 20K SUN v pex 26209 3 DW ex 2022 4509 n f4AGCC eur 4 Ten y 052 SATS CRS3 CRE INS 248A eee 4 RIBS 029 jos e 126 2 V 40 SA eec Be a CREI O28 10 d 2 pH 24 gt nr ZW Z2IIA g 9 ae CAR ur S 7 43393 EFV ER 2 7735 9 57 T 24 22 94 C e4 227 R13 C 43 575 AO 226 NY 13 z s V 132 24 ASV WK 27339 AV SV Y 2 47 5126 Rist 6S SAK Cea Sik 5 gt SAT 8 7 2 53 PISS lt RITI CRES lt 6 52 LIK 620 3 3K SAK 1413279 YEN 5 IN 72 94 Ber als A SCHEMATIC DiAGEAM MAIN B 6550 81 Ls CAREER 200099 ION UQ 99U919Jay ESAD CLOCK X BEER OPEN CABLE w v49 2 9 EL 7 77 9 amp 4 9 4 J2 2 une 27 579 805 5 22 27 SHT 9 10 21 27 Ja Jy C AUS 7 5979 10 7 3 sro LOPA
43. Pages effected Description of requested changes 2 4 tte m van i t Dee eue T AN ves Ti 52 S H 2 3 x i E 5 2 H n u d gt T f H H kg 2 7 E o re redes 9 wat E i H i i 2 2 i i p des cts t tege even tene TE vvv 3 j i H i i y i i tte ee bea eae MAGEN o ob reos tibt e tran i oy 4 H 5 Ze 2 TEAM A gt H 3 4 Wert ta v teen ren we ns Ly t te qae ter t i A 4 H 7 2 El e Meo hn v f i E d 2 4 E 7 2 i O ede npe AM nen 4 i t H y i Veto Ay entis ts tse s nue E d H E E Garra hme S erdt i 5 i 5 H S i i 4 di TUE VASA MANI A SR 1 1 E i H gt R E EE 1 i A Ven dn prev tu rtt en s 5 E H i 1 E i d 5 5 E 3 1 i p 2 A 5 H 1 gt edm gt ERREUR PS CR t Sit
44. RANSISTOR TRANSISTOR T C VOLTAGE REGULATOR IC VOLTAGE REGULATOR _ 33 RESISTOR vw 59 2 30 EI IL 3124 3 COOP ACI R I9 Re AA SIOR F Riz en Ann nn Bun Ris s esto ee RESISTOR 2 BWH EOI CARNERO SAITO 840 5940 an LE EOM E SUE 15 17 RESISTOR ZW BWH PAINE D HCARD Co ias firem DO NOT SCALE DRAG 75 LJ e al 01 RB 2N6055 R13 0 18 1N4004 02 anes 2N6055 CRI CR MR2001 LM7 23CN 1N4753 CR4 1N4004 m CR8 EG 1N4720 Q 2N6055 1N4739 SCRI 50563153 CR9 1N4720 CR10 1N4004 Reference Only Will Not Be Maintained 24V 5 AMP 7 AMP PECK 24V RETURN 5V 4 AMP 5V 12V RETURN 5V 2 AMP 12V 0 3 AMP 5 18 9 JON ATUO 39U91aJay 61 6 M VOLTAGE SELECTING TTRANSFORMER USE ASSEMBLY PECTIFIERS LINEAR OUTPUT aG a p ness ENVOI e md 24 Y Ns at 24V RIN c 44 FOR OOV amp INPUT E HEESE as SU 72 7 art eH a t i i _ 14 2 t
45. REQ cues AD SEL lt AMD SEL SAT 4D SEL 2 SHTI ARTE EE nm 282 287 SHT amp LINE SHT 7 READ GATE SHT 2 0 4 SYNE SHT ENG SHT 10 R322 80 FAT 2 X 5 z we xa 25 2 5024 Ce POWER ON ON CYLINDO DS R323 RN 2 780 5V gt CREO A320 130 2 7 GNO 1 75462 o 75 VOLTS 4 Y 97 12 ALR RES SHT gt CYL SHT 710 UF SAT TETA ______ Ke 2 PEE mamones i o Anon gt eg JON TIFM TUO Glo SH S47 E SAT SAT 9 SHT 1 SAT SAT 7 AT 7 577 7 577 JE 2 547 9 57 8 SHT 7 SAT 7 SHT 9 SHT 3 5977 3 SATS SATS SHT 8 577 8 USAFE 1K 7 5 0 SV WRITE PROTECT OFF TRK ON CYL 9 i AS WG 4504 2K MULTI SEL NE 2504 CEAD GATE DRALT 72 7 RIEZ REG READ CLOCK 4 READ DATA D AG 8 LL CYL 6502 SO ERR SK ERR FLT RD DATA SKF LT READ CLOCK X SAT 7 9 eup 7 SAT Y 724 MES 7 gt CA 220 35V sqrt 4 5 l 6 78 bd 52 3 135 141 150 CIG2 C IG4 CI72 C175 83 9 C198 GND 2 d 1 RETURN C53 C l C122 126 V 1 E TES eV 27 3 SV oar C79 C8 1 C93 C9S CIE CHO C120 1 25 1 ap C23 C1ZO 3 Cc
46. TA READ DATA 47 _ WRITE CLOCK READ DATA 32 181 TAG CYLINDER READ CLOCK 2 44 7 Hl READ CLOCK e J2 13 17773 e SERVO CLOCK 3 J2 87 7AG 3 CONTROL SERVO CLOCK Y amp 9 SUS 2 SHT 0 s 5 87 5 SAT 29 pd WRITE DATA SF HTO NS CWRITE DATA T NS WRITE CLOCK ee tSr 77 J9 2 CLOCK WRITE DATA uu J2 35 4059 i er RC vn en gt ve 122 RETD WRT CLOCK 42 29 are 497 3 2 29 y2 25 BUS4 Ji 25 J 23 nn 23 p UVIT SELECT TAG JI 7 TN SECTOR RESET Je 3 S 7 2 3 _ 2 2 SELECT 2 SELECTED v 5 2 SHTO pu UNIT SELECT 4 4 7 C INDEX 12 32 88 f f ba 262 zi SECTOR pe INDEX JU 9 pu SECT ZAULT ES SHT JI 9 SHTIO 7 SEEK ERROR runi FLY 27 99 5 7 0 CYLINDER ROY 2 45 SHT 9 pim READY p SELECTED nF SHTI UAT SELECTED YP sura EEE 2l SEEK END 19 y7 m lt 2 SEC TOR E 1 23 IUDEX 577 9 N 2 Euro ex TOLERANCE EP TE SCHEMATIC DIAGRAM gt __ MAIN P C E 6650 84 2222 C bw sone 2 _ 7 77 jD 9g JON ITIM ATUO OI S 7 SHT 5 SHT 9 SF 2 547 9 5479 SHTS SATS SAT 4 SAT 4 SAT SAT 2 5V TRK XING UP INDX SK REQ HTK ETK G
47. TAG IDOX INDEX INSYNC INT IONX DMA Acknowledge Th s signal from the CPU is used to determine that the current DMA request has been granted and the next memory cycle belongs to the DMA logic This is the DMA interrupt request line in the CPU backplane This is the output of the DMA request latch This signal is true any time that the processor wants to initiate a DMA cycle This is the DMA request bus signal on the CPU backplane DMA Strobe This signal is generated by the DMA interface control logic This signal is true during the last third of the DMA cycle and is used to strobe read data into the controller and to advance the address counter This signal in the I O control logic is true any time that the signal IOACTV is true and the DOXX command is detected from the CPU This signal is used to transfer data from the CPU to the controller X thru 7 This is the output from a multiplexer that can switch from either the shift register or the memory data bus into the S register Enable INSYNC This signal is controlled by the processor and is used by the processor to control the state of the INSYNC flip flop This signal from the disc unit is used to determine that the disc unit has detected a condition that could lead to the destruction of data The disc is therefore interlocked from further data transactions X 0 thru 7 This is the processor output bus The data on this bus is moved from the processor
48. ad justment procedures and troubleshooting procedures 3 2 BLOCK DIAGRAM FUNCTIONAL DESCRIPTION FIGURE 3 1 Ihe Parallel Interface communicates with all functional assemblies of the Disc Drive and the Controller Its major function is to control and monitor head positioning spindle speed and status information The Servo circuits head positioner assembly and Servo Head align the three Read Write heads over a specified track location The Servo circuits drive the heads to the landing zone upon detection of a low power condition or if both On Track and the Move modes are detected These circuits also monitor voice coil speed The Read Write heads and the Read Write circuits perform the reading and writing of flux changes onto the disc There are three data heads and one Servo head Head 1 and head 2 utilize the top surface head 0 and the Servo head utilize the bottom surface of the disc Figure 3 2 The Spindle Motor is a brushless permanent magnet dc motor The speed of the motor is controlled by a closed loop optical position encoder and a frequency to voltage converter The Serial Interface communicates with the Controller and handles the transfer of data and timing signals 3 1 PARALLEL INTERFACE HEAD POSITION SERVO CIRCUITS HEAD POSITIONER SEQUENCING STATUS AND OTHER CIRCUITS CIRCUITS LINEAR VOICE COIL MOTOR READ WRITE HEADS HD2 SERVO READ AND R W CIRCUITS SERVO HE
49. and it computes the next fetch address next address and stack logic The Microprocessor does the following 1 Translate I O commands issued by the CPU into commands that the Disc Drive recognizes 2 Performs error checking of information passed between Disc Drive and CPU 3 Detects particular conditions and then issues interrupt commands to the CPU 4 Provides Controller and Disc Drive status information to the CPU 5 Implements Direct Memory Access DMA transfer between Disc Drive and Main Memory 6 Sychronizes timing 2 1 3 LOGIC The DMA Logic consists of the following 1 Interface Logic 2 Read Write Cycle 3 DMA Priority 2 1 4 INTERRUPT LOGIC The Interrupt Logic consists of a mask F F and an interrupt F F If the mask F F is set and the interrupt F F is set an interrupt will be sent to the CPU DMAINT A2 1 5 I O LOGIC The I O interface logic provides flags used for branch offset by the micropro cessor These flags are part of the command word which comes from the CPU or flags which indicate valid data is on the output data lines A2 2 2 1 6 LOGIC The CRC Logic is responsible for generating and checking the cyclic redundancy check bytes for the header and data records on the disc A2 1 RADIAL LOGIC The Radial Interface Logic is responsible for the assembly disassembly of the disc serial DATAl It provides flags for branch offsets to indicate
50. e A3 7 SFLAG SFLG SGNSAV SIGN SINT SKERR SMDCY SRX SRTXX STDC SYNDET TO 1 W SD WCLKX WDATA A3 8 This is the synchronized and buffered output of the S flag The synchronization is necessary to prevent a metastable flip flop in the address logic for the processor This is the raw output of the S flag flip flop The S flag is set when data is loaded into the S register and cleared when data is read from the S register This is the saved output of the sign bit from the 2901 to be used for testing in the next processor cycle This is the raw sign bit from the 2901 Ihis signal is used by the processor to control the state of the signals MASK and INT Seek Error This signal from the disc unit is used to determine that the disc has not completed a seek within a specified time interval and therefore the servo is lost and needs to be re oriented by a rezero operation This output of the DMA control ROM is used to set the mid cycle signal flip flop on the next clock edge X 0 thru 7 Shift register parallel output bit This output of the DMA control ROM is used to set the RTXX flip flop on the next clock edge Set the Disc Control This signal is used to load the disc transfer control flags from the processor This signal is true when the sync pattern EE16 is found in the shift register This is the processor clock that is used to define the beginning and end of th
51. e DMA interrupt logic is used to enable the DMA interrupt request line to the CPU X 0 thru 7 memory This is the unbuffered memory bus from the main f This is a bi directional data bus MIDCY MRST MUXN NAX ODOX OFL OFLSAV ONCYL OUTEN POP QO QOSAV Q7 Q7SAV ROSAV R SAV This signal generated by the DMA control logic is used to indicate that the middle third of a DMA data transfer is now in progress This is the master reset signal from the CPU backplane N 1 2 These are the raw clocks that are used to generate the signals TO and During clock changeover these signals may con tain truncated clocks X 0 thru 3 These signals form the least significant four bits of the next processor address Since many different signals may be gated into these bus this forms the basis for N way branches X 20 thru 7 These are the output data lines from the CPU This information is used to determine the controller address or to transfer data from the CPU to the controller This is the raw overflow status bit from the 2901 This is the saved overflow bit form the 2901 to be used for testing in the next processor cycle This signal from the disc unit indicates that the disc unit is on a cylinder and not seeking Output Enable This signal is used to disable the disc bus output lines when the controller is first powered up This is to prevent the random control information contained
52. e data processing cycle in the processor On the rising edge of this clock all data from the current cycle is strobed into desti nations and the new instruction for the upcoming cycle is strobed into the instruction pipeline register This is one of the major clock signals that controls the processor This clock overlaps and lags TO This clock defines the loading of the next fetch address for the processor instruction Write or Sync Detected WRITE and SYNDET This signal is the logical OR of the signals X H or L This is the differential balanced line write clock to the disc unit This signal is the servo clock re transmitted by the controller This is done to absorb some of the cable and interface delays This is the serial data that is to be written on the disc during a write operation All data to the disc will pass through this line WDTAX WRITE ZERO ZEROR ZROSAV or 1 This is the differential balanced line write data signal to the disc unit This passes all data signals to be written to the disc This flag is controlled by the processor It is used to control the direction of data flow to move data from the memory to the disc This signal indicates that the general counter has counted down to zero This is the raw zero result flag from the 2901 This is the saved output of the zero results bit from the 2901 to be used for testing in the next processor cycle 9 SECTION 4 REFERENCE D
53. eady and on cylinder signals from the disc unit When this signal is true a data transfer may occur This flag is controlled by the processor It is used to control the flow of data from the disc unit to the memory This signal from the disc unit is used to determine that the disc unit is rotating and up to speed and no fault exists This signal is used by the processor to reset the MASK and INT flip flops XX 00 thru 25 These are the raw ROM outputs that feed the inputs of the instruction pipeline register These bits are not used any where else since it is the output of the pipeline register that is used while the next instruction fetch is in progress ROMXX ROMYY RSHFT RST RTXX SADDEN SCLK SCLKX SCTR SDFLAG SDMAQ SDMST SERIN SEROUT SETS5 This signal is the controller reset from the system XX 00 thru 25 These are the outputs of the ROM pipeline buffer that contains the instruction for the 2901 part of the processor This buffer is loaded on the rising edge of TO YY 26 thru 39 These are the raw ROM output bits that are used directly in the next address computation logic The results of the next address computation are strobed into the address register at the rising edge of TO This signal is used by the processor to control the inputs to the shift registers in the 2901 for a right shift operation It is used to reset all of the important functions in the controller for power
54. ight Width Depth Weight POWER Ac Power Dc Power 6 8 inches 17 3 cm 16 6 inches 42 2 cm 20 0 inches 50 8 cm 47 pounds 21 3 kg 100 VAC 120 VAC 220 VAC or 240 VAC 50 or 60 Hz 425 Watts Max 24 VDC 5 7A 5 VDC 5 2A 5 VDC 5 4A 24 VDC Return 12 VDC 5 0 7A 1 3 TABLE 1 1 SPECIFICATIONS continued Parameters Characteristics 1 4 Capacity formatted Number of discs Number of data heads Number of data cylinders Number of Diagnostic cylinders Bytes per cylinders Bytes per track Track density Recording density Data transfer rate Recording code Interface code Rotational speed Rotational latency average Rotational latency maximum Positioning speed Single cylinder Average Maximum Start Time Stop Time ENVIRONMENTAL Temperature 65 F to 75 F 18 C to 24 C Humidity 40 to 60 non condensing GENERAL 66 Megabytes 1 3 1116 0 1115 excluding diagnostic 5 2 6 with Switch 10N 5 ON 1118 1122 60 480 20 160 960 Tracks per inch double density 6 430 Bits per inch 1 04 Megabytes per second MFM NRZ 3 100 RPM 9 7 milliseconds 21 5 milliseconds Maximum Typical Milliseconds Milliseconds 10 8 48 45 90 85 30 seconds 60 seconds CHAPTER 2 INSTALLATION AND OPERATION 2 1 GENERAL This chapter contains complete installation and operation instructions for the Disc Drive 2 2 UNPACKING PACKING PROCEDURE The Disc
55. in the registers from cauing the disc unit to force a fault Once the registers assume a known state this signal can be enabled This signal is used to indicate that the next address for the pro cessor instruction will come from the contents of the address stack register This is the 1 0 line for bit 0 of the Q register in the 2901 Whether this line is an input or an output is determined by whether there is a right or left shift operation in progress This is the saved output of the QO bit in the 2901 to be used for right shift operations in the Q register This line is the I O for bit 7 of the Q register in the 2901 Whether this line is an input or an output is dependent on the type of shift operation in progress Ihis is the saved output of bit of the Q register to be used in left shift operations for the Q register in the 2901 in the next processor cycle This is the save output of RAM bit 0 in the 2901 to be used in left shift operations in the RAM This is the saved output of RAM bit 7 from the 2901 to be used in left shift operations in the next processor cycle RADX RAMO 7 RCLKX RDATA RDCLK RDDLB RDDMX RDDUB RDFLAG RDTAX RDY READ READY RINT ROXX X 0 thru 8 These are the ROM address bits used to fetch the next instruction from the control ROM for the processor This is the input output line for RAM bit 0 in the 2901 Whether this line is an input or an output is determ
56. indle rotational feedback from the Photocell PCB 1 2 4 PHOTOCELL PCB The Photocell PCB contains three infrared light emitting diodes and phototransistors used to monitor and control spindle motor rotation 1 2 5 FRAME ASSEMBLY The Frame Assembly is designed to contain the standard assemblies of the Disc Drive 1 2 6 POWER SUPPLY ASSEMBLY The Power Supply Assembly is an integrated power supply that will operate from 50 or 60 Hertz and at a selectable input voltage of 100 120 220 or 240 volts ac 1 2 1 2 7 TERMINATOR The Terminator is a signal line terminator for the last drive connected to a Controller 1 3 DISC DRIVE SPECIFICATIONS Table 1 1 list the Disc Drive specifications WARNING This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions manual may cause interference to radio communications as temporarily permitted by regulation It has not been tested for compliance with the limits for Class A Computing Devices pursuant to Subpart J of Part 15 of FCC Rules which are designed to provide reasonable protection against such interference Operation of this equipment in a residential area is likely to cause interference in which case the User at his own expense will be required to take whatever measures may be required to correct the interference SPECIFICATIONS Parameters Characteristics PHYSICAL He
57. ined by the type of shift oper ation that is in progress This is the I O line for RAM bit 7 in the 2901 Whether this line is an input or an output is determined by the type of shift operation that is in progress X Le These are the differential balanced line signals from the disc that carry the read data clock When the read gate is asserted this signal may be used to clock data in from the disc unit This is the received read data from the disc unit The data takes the form of serial NRZ data that is clocked in using the read clock This is the received read clock from the disc unit This clock is used to time the flow of data from the disc unit to the controller during a read data operation Read the Lower Disc Bus Control Register This strobe generated by the processor is used to gate the contents of the lower disc bus control register into the processor data input bus This signal is used in the data bus control logic to enable the out put of the data mux onto the processor data input bus Read Disc Upper Bus Control Register This strobe is generated by the processor and is used to gate the contents of the upper disc bus control register into the processor data input bus Reset the D flag necessary This signal is used to reset the D flag whenever or Le These are the differential balanced line signals that carry read data from the disc unit to the controller This signal is the logical OR of the r
58. l logic and is used to gate the contents of the DMA address counter onto the main frame memory address bus This signal is true throughout any DMA cycle X 0 to 7 These are the outputs of the D register The D register is used to buffer data until it can be written into its destination This signal is the synchronized and buffered version of the index signal from the disc This synchronization is necessary to prevent a metastable flip flop in the address logic for the processor This signal is the synchronized and buffered version of RDY This synchronization is necessary to prevent a metastable flip flop in the next address logic This signal is the synchronized and buffered version of the logical OR of the index and sector signals from the disc This synchroni zation is necessary to prevent a metastable flip flop in the address logic for the processor This signal is generated by the bit counter on each eighth bit during a data transfer to determine the byte boundaries This signal is used by the processor to control the clock changeover logic In addition to loading the least significant bit of the processor output bus into the clock control flip flop this signal initates the series of events necessary to insure a smooth changeover from one clock to another Ihis is a test signal that is used to gate the processor clocks on and off for testing and single cycle operation with the WCS This signal is used by the processor to reset
59. ne track as possible for best display With an oscilloscope use the following procedure refer to Figure 2 3 for adjustment location Scope Tektronix 465 or equivalent Probes Two 10 attenuation Channel 1 to side of R46 facing transistors Set input to 1 Volt Division 0 1 Volt Division with non indicating X10 probe Channel 2 to other side of R46 Set input to 1 Volt Division 0 1 Volt Division with non indicating probe Vertical display mode to ADD Channel 2 INVERTED Position trace near top of graticule Time base 0 2 ms TRIGGER SLOPE TRIGGER SOURCE Channel 2 dc coupled NOTE Adjust R351 near R46 for 5V Figure 3 5 ADJUSTING R351 Figure 3 5 Write Current Adjustment 3 4 3 DATA WINDOW ADJUSTMENT For this adjustment you must first write all ones then make the adjustments while reading all ones Do not use Head 2 Do not use any tracks which could contain customer data Write as many sectors on one track as possible for best display With an oscilloscope use the following procedure refer to Figure 2 3 for adjustment location Scope Tektronix 465 or equivalent Probes Two X10 attenuation Channel 1 to TP13 Window ground to TP2 Set input to display 0 5 Volt Division 50 MV Division with non indicating 10 probes Channel 2 to TP9 Data ground to TP2 Set input to display 0 5 Volt Division 50 MV Division with non indicating X10 probes Vertical display mode CHOPP
60. om opto trm PT b e P 1 4 1 A 3 H Wert v a a TE pe DR DR Ex ER vem c mess sce BR H ter Ata ry 2 3 1 5 H 1 2 DM rre nd O gt Us AMA dee AMA IA s t x 3 3 i i 3 E RAR TASA at iet 3 uus 34 po decenas D MERE un AA SR PR De v E vw M I A EI tyr Pr m 526 AAT 5 mn sal NOT Gere nese TE oe T tei UT i i rm i eter i N As RN cm ES AMEN Es MD TEM LN E H le d H i tor 3 1 E on aoe ee Zu a Siam EP abe sand fe i i dat Aen Ig eid as o ads 1 H 24 4 n Macs i zT i H Ea Da 220755 a I x Mae d tene der ne RE m i d 3 a 5 E S pee d Kran nu sorde y x Y i EPE E i t SER MARINA E BUN e NARA I d 2 i E 3 H 2 ARAM E T ET ND ventes 2 4 EN
61. or mistimed Device Not Ready Tag and bus data malfunction Defective servo action Defective circuit Servo Head fails to READ Refer to Table 2 1 for switch definition Check controller cable and connectors Check controller cable and connectors Replace Main Logic PCB Check controller cable and connectors Replace Main Logic PCB See Head Positioning Servo Replace Main Logic PCB See Head Positioning Servo Head Positioning Servo Possible Cause Command transfer circuitry defect Defective circuitry or connection Suggested Action Replace Main Logic PCB Defective servo circuitry on Main Logic PCB fault continues with operational spare installed and spindle speed and write cir cuits are not the source of the fault replacement of the disc drive is recommended Fault connection to servo read head check J6 Fault connection to voice coil actuator check J5 Incorrect voltage check J3 Carriage locked 3 11 TABLE 3 1 Symptom Seeks to incor rect cylinder address Symptom Fault is set with each attempt to write data Data is written incorrectly and faults does not set Symptom Reads header fields and data fields correct ly but will not read newly written data FAULT ISOLATION continued Head Positioning Servo Possible Cause Suggested Action Defective circuitry or servo system Defective signal from cont
62. roller or fault in the interface cable Defective circuitry on Main Logic If symptom continues with operational spare installed and controller and cable are not the source of the fault replacement of the disc drive is recommended Seek ma be correct and method of checking for correct seek locatio may be defective This could be caused by a read write fault Write Data Transfer Possible Cause Incorrect switch setting or circuit defect Reads data difficultly Suggested Action See Table 2 2 for switch definition Multiple heads selected can be checked at TP20 which will be high if more than one head is selected Act Unsafe condition is checked at TP1 which will be high if there are not write transitions with Write Gate true or write transitions with Write Gate false See following section Read Data Transfer Read Data Transfer Possible Cause Defect in write oper ation Suggested Action Replace Main Logic PCB TABLE 3 1 FAULT ISOLATION continued Read Data Transfer Symptom Possible Cause Suggested Action Fails to read Defect in Read cir Check all cable connections but will per cuitry Replace Main Logic PB Replace form a write terminator operation with out a Fault If read error persists after replacement of Main Logic PCB and terminator and if cable connections are correct it is possible that the format being used is erroneous If format is correct replacement of
63. rporation OwG NO 903029 14 94 11 9IUILIFIY 8 587 8 SRG 8 5 5 8 SR4 SR2 SRI B SRO 5 STOC 3 RST 8 SEROUT SERIN 5 CLRCRC DCLK 4 o DMASTB_ 3 WLDBREG 5 8 LOSR SET5G 18 INSYNC 3 WRITE 8 READ 11 12 READ S 11 12 DO R EKR 5 WDATA basic Four corporation 7903029 SCALE ______ 10 op 14 psutezutey 24 ION ITIM cI vv 3 Pool Ds 8 De E lo 201531 6 745240 5745240 5745240 oa 745240 SCLK 9 19 a 1 2 3 WCLKH UK 3g ee se_k3 1l 5 9 dL 9 WELK 55 7 9C4H NER ay 206 4 8 i2 READ a 0 e E RDCLK 5 DCLK To EE gt ES as ars DUK 10 WDTAH 12 5 7 NUTS RDT 4 ge ME l aD E RDATA DAS SERIN a 10 dH 220 535 100 74508 mp 5 LDUDB TNCS 2513 32 o r m a D Q D Q p 10D D Q D Q D Q Dx ER a pe 9 UNIT TAG P2 1 5 REECE p2 3 P3 22 LDLDB 5 UNIT RESS ADDRES EET USB2 P2 9 Eu 7 Eb EE LT s 0583 I a 7 10 CF OE HEC gn 212 Anr Na AS Q 220 o Q Inm 22
64. sical Description Head Disc Assembly Main Logic PCB Motor Control Photocell PCB e o Frame Assembly o e Power Supply Assembly Terminator e Disc Drive Specifications INSTALLATION AND OPERATION General gt e o o o o o Unpacking Packing Procedure Head Carriage Lock Spindle Lock e e Installation Procedure Pre Power Checks Interface Cabling Dc Voltage Check e Controls and Indicators Switches and Jumpers MAINTENANCE General Description Block Diagram Functional Diagnostic Tests e General Discription of General Description of Adjustment Procedures Power Supply Adjustment Description Silver A5 FORMAP S e e e e Power Supply P N CP353 1 Power Supply Model 2 981 Write Current Adjustment Data Window Ad justement Fault Isolation TETTETETT Go N NN N DN ho NH N FP Lal 2 1 2 1 2 2 2 5 2 4 2 2 8 2 8 2 9 3 1 3 1 3 3 3 3 3 3 3 4 3 4 3 5 3 6 377 3 8 3 9 iii CHAPTER 4 CHAPTER 5 APPENDIX A iv TABLE OF CONTENTS continued SPARE PARTS LIST REMOVAL REPLACEMENT Introduction e gt o Removal Replacement Procedures Head Disc Assembly HDA Power Supply Assembly PROCEDURES Main Logic PCB and Motor Control REFERENCE DATA DISC
65. system Two cables Radial Cable P N 902622 and Bus Cable P N 902687 connect the controller to the Disc Drive A complete pin to pin listing of these cables is given in Figure 2 1 1 Al 2 c n p2 BUS CABLE UNIT SELECT TAG TAG 1 CYLINDER ADDRESS TAG 2 HEAD SELECT TAG 3 CONTROL BUS BIT 0 BUS BIT 1 BUS BIT 2 BUS BIT 3 BUS BIT 4 BUS BIT 5 BUS BIT 6 BUS BIT 7 BUS BIT 8 BUS BIT 9 UNIT SELECT 1 UNIT SELECT 2 UNIT SELECT 4 UNIT READY INDEX SECTOR FAULT SEEK ERROR ON CYLINDER OPEN CABLE OW r2 iO OW WO c CO EA DISC MAIN CONTROLLER PCB LOGIC PCB 43 HL 0020 rm ps C CO r2 ON RADIAL CABLE WRITE CABLE SERVO CABLE READ DATA READ CLOCK WRITE CLOCK SEEK END UNIT SELECTED SECTOR INDEX m y ws T1 TAG 2 TAG 3 err EINER RUD CT ADDRESS SELECT CONTROL WRITE GATE READ GATE 12 NH EM 4 126 6 6 2048 READ STATUS USED FOR HIGH ORDER CYLINDER ADDRESS DURING TAG 2 TIME m lt gt Figure A 2 Disc Interface and Tag Bus Decode 1 3 PHYSICAL REQUIREMENTS Al 3 1 PHYSICAL ENVELOPE The Controller is housed on a standard Basic Four printed circuit board PCB with all connectors and components mounted thereon Al 3 2 MOUNTING The Controller is installed in the card cage of a standard Basic Four da
66. t 24 16349 C50 RIGO ci SK 50 FLO CARRIER AMO 3 9 3 la 07 SWIS 9 K 230 eV S WC DETECT Or SY RILI MS 3 9K 57 ppt C 9 2 v v sev 5 LV 5974 2758 SHTE SANS SHT 5 23 PLO LOCK SHT 6 TOLERANCE UNLESS OTHERWISE SCALE m 24 ION ITIM TUO 9 6 SV 4 s re D syra 1 9176 SHT 3 sra 25 6 5 ME 2 SHT E rada 3 4 5 SHTS 8 9 syra DETECT 6896 2 _ swre EST GE LATCHES SHT 8 SERVO A77 POSITION C8e6 87Q PF 510 PEAK E 7P36 GHEL SERVO TP33 TP32 POSITION 5 78 RITZ A 68 POSITION YN 10K DEMOD HASE pr MY 00 u PEAK A 173 34 AS E BYTE CLOCK gt TATEN REII g22 SAT 5 9 I MEC eNe9osa A13 y E EHE FOSI TION 0039 5 205 70 190 SATS 2 470 R240 4 138 3 K 2 RET C VOR 3 0039 R24 52 OK REM 10K 1 R220 43 9K CARRIER AMP SATS C102 0 1 AGE SHTS DIFFEREN TIA TOR OUTPUT POXA 547 R227 E NN SHT a sur FAGCC CURVE D A 0 g t POF R244 VELER swre surs SL FI z 2 09 2 TPAR gt R273 swrs 5 ID 106200 9 4 R230 5 7458 2 05K 4 58 SATS es yy 2275 gt 0 54K NJ
67. ta pro cessing system All clearances and airflow provisions normal to the Basic Four system are observed Al 4 DATA RELIABILITY The data reiiability of the Controller is subject to the data reliability limits of the disc unit These limits are 1 Soft Error Rate Recoverable Errors Not more than one error in 1010 of bits of data transferred 2 Hard Error Rate Non Recoverable Errors Not more than one error in 1013 pits 1 3 SECTION 2 MAINTENANCE 2 GENERAL DESCRIPTION Maintenance of the Controller is limited to replacement of the Controller This section will explain the Controller function only as an aid to the Service Representatives in troubleshooting A Functional Block Diagram is given in Figure 3 1 and described below CONTROL ROM FIRMWARE DMA LOGIC INTERRUPT LOGIC 1 0 LOGIC CRC LOGIC CPU MIROPROCESSOR RADIAL LOGIC DISC UNIT BUS LOGIC Figure A 3 Block Diagram of Controller A2 1 1 CONTROLLER ROM The Control ROM FIRMWARE automatically initiates the following 1 The Reset Routine 2 The Idle Loop 3 The Transfer Preparation Routine 4 Search ID Routine A2 1 A2 1 2 MICROPROCESSOR The Microprocessor initiates tests or controls the entire operations of the Controller as specified by firmware The Microprocessor does three things for each instruction cycle it executes the present instruction function it fetches the next instruction
68. the disc drive is recommended TABLE 3 2 STATUS BIT DESCRIPTION 0 MULTIPLE HEAD SELECT indicates that more than one head was selected 1 NO WRITE DATA indicates that transitions in write current failed to occur with WRITE GATE active 2 NO WRITE GATE indicates that write current was sensed when WRITE GATE was not active 3 OFF TRACK WRITE indicates that the R W heads were not within acceptable track following limits while WRITE GATE was active 4 READ ONLY indicates that WRITE GATE became active while the Disc Drive was not WRITE ENABLED 5 PLO LOCK ERROR indicates that the signal was not correctly synchronized 6 NOT USED always zero 7 POWER FAULT indicates that spindle was already spinning when power was applied 8 MULTI TAG indicates that two or more tag lines were simultaneously active 9 READ AND WRITE indicates that both READ GATE and WRITE GATE were simultaneously active 3 13 TABLE 3 2 STATUS BIT DESCRIPTION continued 10 OFF CYLINDER indicates that the positioner was not ON CYLINDER while WRITE GATE was active 11 SEEK TIMEOUT indicates that the positioner failed to return to track 0 with 900 msec or it failed to complete a seek operation within 130 msec 12 SPEED ERROR indicates that the disc failed to reach or failed to run at operating speed 13 GUARD BAND ERROR indicates that the positioner entered the inner or outer guard bands while performing a seek or restore operation 1
69. tor to the Controller Dc power supply connector Motor Control connector Voice Coil connector Servo head and Data head O connector Data heads 1 and 2 connector Control Panel connector used for LEDs in identifying malfunctions in Disc Drive Radial cable connector to the Controller The Bus cable J2 P N 902687 and Radial cable J9 P N 902622 are connected directly from the Disc Drive to the Controller in the host CPU Figure 2 4 gives Interface Cabling Pin assignments and Bus Tag Decode information 2 5 TO CONTROL PANEL SWITCH WRITE CURRENT ADJUSTMENT DATA WINDOW ADJUSTMENT RADIAL B e TP13 oo J9 Cc c _ 832 gt lt R462 2215 BUS VAM DRIVE ADDRESS TT SEL SWITCH SECTOR SWITCH 1 J5 Cs A HEAD 1 HEAD 2 SERVO HEAD HEAD 0 VOICE COIL TERMINATOR MOTOR CONTROL POWER SUPPLY DRIVE ADDRESS SELECTION 10N 1 THRU 10N 3 WRITE PROTECT 10N 7 DIAGNOSTIC MODE 10N 5 Figure 2 3 Main Logic PCB Figure 2 4 P2 BUS CABLE UNIT SELECT TAG TAG 1 CYLINDER ADDRESS TAG 2 HEAD SELECT TAG 3 CONTROL BUS BIT 0 ca m m be CO r3 oO UO CO Lr iO OF CO pa UJ UJ 4 4 Ha E BUS BIT 2 BUS BIT 3 BUS BIT 4 BUS BIT 5 BUS BIT 6 BUS BIT 7 BUS BIT 8 BUS BIT 9 UNIT SELECT 1 UNIT SELECT 2 UNIT SELECT 4 UNIT READY INDEX SECTOR FAULT SEEK ERROR ON CYLINDER OPEN
70. ushless dc drive motor It contains the necessary circuitry for positioning the heads and transferring data and status information via the Controller to a host CPU This manual contains physical and functional descriptions installation operation procedures spare parts lists and maintenance procedures Figure 1 1 Model 2460 Fixed Media Disc Drive 1 1 1 2 PHYSICAL DESCRIPTION The Disc Drive stores data on both sides of a single disc using two moving heads per surface A full head area is dedicated to servo information for track following seeking and timing A microprocessor controls positioning during track seeks provides interface control and monitors disc drive operation The major assemblies of the Disc Drive are Head Disc Assembly HDA Main Logic Printed Circuit Board PCB Motor Control PCB Photocell PCB Frame Assembly Power Supply Assembly and Terminator 1 2 1 HEAD DISC ASSEMBLY The Head Disc Assembly is a contamination resistant enclosure which contains the disc spindle assembly voice coil actuator head carriage read write heads and filter assemblies 1 2 2 MAIN LOGIC PCB The Main Logic PCB contains all the circuitry associated with read write data transfers interface transfers head positioning and control 1 2 3 MOTOR CONTROL PCB The Motor Control PCB contains all the circuitry associated with driving the spindle motor This circuitry receives On Off command from the Main Logic PCB and sp
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