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M230 N/B Maintenance - Downloaded from LpManual.com Manuals

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1. USB CTRL 5V From Page 21 U13 J10 RE32 0511 d 10K MIC2505 2545BM L524 2 RLS4148 120Z 100M m USB_CTRL Pos Pis lt lt INO 1 VOUTO 1 e e VBUSO e e us USB OC40 P26 C509 C596 C600 C610 5 FLG 100 F 1500A 10UF iG ar D306 0 1U 1500 qen 5 e m V gt USBP2 902 100 USB2 V c A A1 zi USBP2 USB2 R887 10K South Bridge 43V 0 R879 m 5V R670 0517 i Dale 10K MIC2505 2545BM L529 mo RLS4148 1202 100 USB CTRL4 NUS P26 INO VOUTO I e e 9 YY e e e USB_OC 2 VE 26 C638 C621 C643 C632 E ni C631 C622 0515 27 109 Oe IU T 1500 T EsDo0sA 9 a V gt USBP0 902 100 USBo V A USBP0 3 VY V2 USBO Downloaded from LpManual com Manuals 182 M230 N B Maintenance 8 9 USB Test Error 3 POGO An error occurs when a USB I O device is installed
2. 3V J13 R864 R876 USB_OC 6 ie O Vsys USB Pis 4 5V USBP3 _XBAY gt O 43V USBP3 XBAY 5VS la PCIE RXN2 O 43VS U522 PCIE RXP2 45VA 4 PCIE TXN2 12V gt 43VA PCIE TXP2 South Bridge le PCIE_WAKE PCI_RESET 7 SMBCLK RIS3 0 U523 SMBDATA R182 0 CLK_PCIE_XBAY 5 SUSB gt 5 CLK PCIE XBAY Clock XBAY GPIO 0 1 5 Generator PCIECLKREQI gt XBAY_ID 0 1 12591 310 TXD gt COM4_RXD D35 1010 P22 gt R1008 CL 155Y PG DT 330 XBAY LINK 0 3 DT gt ae R1011 U4 COM4_DCD gt 330 E COM4_RTS Super I O gt COM4_CTS SIO10N268 COMAS V gt RH gt 184 Downloaded from LpManual com Manuals M230 N B Maintenance 8 10 Audio Test Error 1 No sound from speaker after audio driver is installed Audio Test error 1 Check if speaker cables are connected properly 2 Make sure all the drivers are installed properly Board level Troubleshooting Check the following parts for cold solder or one of the following parts on the motherboard may be defective use an oscilloscope to check the following signal or replace parts one at a time and test after each replacement 1 If no sound cause 2 If no sound cause 3 If no
3. 1 L 5 8 8 777 3 616 2 5 5 1 526 FDS6679 M230 N B Maintenance 8 1 No Power 4 When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up PQ534 PD521 PD522 PO Discharge ABATT FDS6679 SIA835DY 4 l e EH 6 EE 5 za PF504 FUSE 10A PJ3 FUSE 10A VBATT1 e PWR_BATT Q PR57 DCHA 5 SMC A PR56 2 ts PUS06 SMD DCH B OZ864B0 PQ533 PD519 PD520 BBATT FDS6679 is 3 7 1 2 Hd gt ICHM na PF503 o PJ2 FUSE 10A Jm VBATT2 P31 Por E SMC A BAT DATA U13 c 4 Ex SMD A m Keyboard e PR554 PU4 SMC SMC B BIOS 5 548 4052 0 Suc suci H8S 2140 VAT B PD517 PD518 MMSZ5232B gt 165 Downloaded from LpManual com Manuals M230 N B Maintenance 8 2 No Display 1 There is no display on both LCD and monitor after power on although the LCD and monitor is known good No Display System Refer to port error
4. eon deta signal eon Recut send signal LE T CU LL E NE NNNM NN Lf J pope e pq pe PIO Auto Feed PIO Printer Error 74 M230 N B Maintenance gt I O Board 120 pin Connector Mitac 291000011229 2 Continue to the previous page 36 CRT DDCCLK CRT DDC Clock Signal 37 CRT DDCDATA Data Signal 38 CRT BLUE CRT BLUE Signal 39 CRT GREEN CRT GREEN Signal 40 CRT RED CRT RED Signal 4l USBP7 USB Differential Data Minus 42 USBP7 USB Differential Data Plus 43 0 Enable Backlight 44 BLADJ Adjust LCD Brightness Signal 3VS For LCD ___ __ __ __ S Oo S Ja ew 44 mA 4 4541 25 5 Oo 48 V EA Not Connect 2 Gouna 0 eer _____ J pu po 0 __ S L p E Lo S 2 9 50 TXCLK VS Sampling Clock Positive 51 TXCLK we Sampling Clock Positive 52 GND Ground 53 TXOUTO Transmission Data of Pixels 0 Negative 54 TXOUTO Transmission Data of Pixels 0 Positive 5
5. 5VA SI4435DY J503 8 R151 VDOCK_POGO 7 3 400K 2 o VDOCK Pis Q21 Pis USBP4 P_USBP4 C96 2 died WAPE Pos C A P DOCK U522 ESD0603 4 I USBP4 P_USBP4 e e 5 1 C145 0515 VoU USBPS P_USBP5 vm South Bridge P13USB20 T 8 DVMAIN 7 2 Vsys 100K USBPS P USBPs 1 o 1 oc gt Q23 ICH7 M USB_OC 5 D300 L C144 a Q26 DTCI44TKA P USB OCHs 1000PT psp24c 100 S R157 R165 ud AVV ane IM RI R881 NE 8 10K 3V 5 e 5 ON P DOCK IN o 3A 81230108 5VA_POGO E D 4 5 Poi P_SUSB Et HH Q4 22 C112 G Ri45 015 DTC144TKA Pos 22U 100K DOCK P DOCK e A 0522 XS d PWRON_CARKEY U12 P_PWRON_CARKEY V Q521 Q521 South Bridge H8 74CBTD3384 P_H8_SMB_CLK FDC625 FDC625 5V_POGO 5V 3V Pos Pos H8 SMB DATA P H8 SMB DATA CS DI D4 DI D4 us y G 12V_SW G ICH7 M Bock adi DOCK RI P DOCK SV 0 From Page 22 U4 C809 Q520 e 9 220 51230305 R1022 2 2 s oo ME 12 3 we e i R1025 f 100K V Q 1 Q523 054 DTCI44WK 2N7002 4 R1024 IM 9 183 Downloaded from LpManual com Manuals M230 N B Maintenance 8 9 USB Test Error 4 X BAY An error occurs when a USB I O device is installed
6. Umum 7 Cmm 796115060018 TF041 RUBBER DOCKING POGO M22 ae AA 796115050030 TF041 MYLAR PCMCIA M220 D 4469 796116000006 TF041 COPPER FOIL MYLAR M B M 796115040020 TF041 STANDOFE H 5 2mm M2 5 0 796115050082 041 5 00 3 71 797628422111 TF041 STANDOFE H 11 0mm M3 0 Cmm romaine recs wem mecmumassanue wes Downloaded from LpManual com Manuals 291000015058 796115040015 2268000200 2218000200 2 222672730002 523481614003 Zaye 565111820002 565111820003 796115100008 2426806000 338937010065 TF04 TF04 Part Number Description Location TF041 THERMAL PAD ICS A770 MEE GASKET 733GT A PART G TFO41 TH PWA PWA M230 CD RO MEN TH CON HDR MA 25P 2 8M J500 mami 208 M230 N B Maintenance 9 Spare Parts List 14 342120100001 342120100002 342120100003 342680600001 342680600002 342686000017 342687600003 342687600005 344680600003 344680600004 346687600005
7. YO 201 M230 N B Maintenance 9 Spare Parts List 7 Part Number Description 796115030019 TF041 RELEASE HANDLE DVD M220 796115000028 TF041 COVER ASSY LCD KEY CONN 796115050031 TF041 HOLDER PROTECT HOOK M2 796115060046 TF041 RUBBER DDR BOTTOM M220 796115060049 TF041 RUBBER LCD KEYBOARD CAB 796115050035 TFO4I PLATE ALPS M220 796115050034 TF041 MYLAR BATT SIDE WALL M2 796115070024 TF041 GASKET O 22 796115070026 TF041 GASKET C PART CD ROM TO 796115070019 041 5 BD CONDUCT P 796115050038 TF041 MYLAR 7 LED DISPLAY M22 796150063002 TF041 GRIP GROUP W150 796115070031 TF041 GASKET CAP TOUCH PAD 796115050033 TF041 MYLAR BATT M220 796115020017 TF041 BKT COVER SIM CARD M220 796115010018 TF041 SCR HANDLE M3L13 5 M220 796115050049 TF041 MYLAR HDD SIDE M220 796115050048 TF041 MYLAR HDD 220 796115060088 TF041 RUBBER ANTENNA 2 796115070058 TF041 CLOTH SPEAKER M220 796115060013 TF041 RUBBER RELEASE HANDLE M 796115070060 TF041 GASKET HDD W10 HI1 0 796116000004 TF041 BOTTOM COVER ASSY MAIN 796116000002 TF041 BOTTOM COVER PAINT M230 796115070070 TF041 AL FOIL TOUCH PAD BRAC Downloaded from LpManual com Manuals ocation s 796115070066 796
8. meum ____ TF041 BKT DC DOOR M220 SY menaces Downloaded from LpManual com Manuals Part Number Description Location s 796115050022 796115050026 796115050028 796115050029 796115060006 796115060007 796115060008 796115060009 796115060014 796115060015 796115060030 796115060031 796115060032 796115090002 411116000007 271071471308 291000151005 294011200523 316116000004 294011200504 242600000572 2268000200 221800020002 2266838101 222672730002 ___ 041 5470 1 16W 5 menm 199 M230 N B Maintenance 9 Spare Parts List 5 272071475403 272105102421 TF041 T H CAP 4 7U 6 3V 10 06 272030102414 041 1000 3 10 18 288105435001 Downloaded from LpManual com Manuals FN C520 C538 TF041 TH CAP 1000P CR 50V 1094 C500 C508 C509 C550 meme Part Number 331840010019 291000011228 291000020233 273000500182 297011000001 288200144034 288200144029 271061103114 271061472312 271061473502 271061104108 27100
9. Card Bus address data bus ACAD3 Card Bus address data bus 26 Card Bus address data bus cabs WM fF Card Bus address data bus cane Card Bus address data bus V 867 EN 71 Card Bus address data bus Card Bus address data bus Card Bus address data bus Card Bus address data bus Bus address data bus 9 ACAD Cart Bus address databus 5 __ ___ Cart Bus address databus J Bus address databus CADIT CADIS 135 131 129 130 127 128 125 105 104 103 102 Downloaded from LpManual com Manuals 70 M230 N B Maintenance Continue to the previous page 90 8 6 ___ 5 EN accom _ o __ 1 12 oo 17 17 __ 7 ACCKRUNM oo 8 Accom mm sow 132 101 A_CVS2 J 8 8 8 8 9 7 8 5 3 2 136 124 106 1 122 120 109 9 148 121 07 Downloaded from LpManual com Manuals Card Bus bus commands and byte Card Bus bus commands and byte Card Bus bus commands and byte Card Bus bus commands and byte enables Cars Bus voltage sense 1 and Card Bus detect 2 71 M230 N B Maintenance Continue to the previous page 98 6
10. TH RES 001 2W 595 2512 TF041 TH RES220 1 4W 5 1 PR507 PR568 Part Number Description Location s TF041 TH INDUCT OR 4 7UH D104C Po TF041 TH INDUCT OR 4 7UH FDV06 PLS13 PL518 PL519 S2N7002LT 1 N CH SIRF7832PBF N M TFO041 TH TRANSIRF7821P BF N M MEINE TF041 TH TRANSDTCIA4WK NPN S MEN SFDS6679 NL P M PQ523 014 022 PQ528 PUSOL 5 514835 1 S S14832DY N MOS 5403415 00K 1 16W 1 10 1 16W 196 0402 TF041 TH RESATOK 1 10W 196 0 MEN PR20 PR38 PR8 PR9 1 16W 0402 PR535 PR540 PR55 PR503 PR514 204 M230 N B Maintenance 9 Spare Parts List 10 271072118311 271071513102 271072113312 271071184103 271045029102 271071287114 271061220105 271061333304 271046257104 271072372101 271071121217 271071153105 271071150104 271071562309 271071152107 271071283105 271072822102 TF041 TH RES 02 1W 1 2512 TF041 TH RES287K 1 16W 196 TF041 TH RES22 1 16W 196 TF041 TH RES33K 1 16W 5 0 TF041 TH RES 025 2W 1 25 TF041 TH RES37 4K 1 10W 1 TF041 TH RESII5 1 16W 1 06 TF041 TH RES 5 6K 1 16W 5 041 51 5 1 16 1 TF041 TH RES28K 1 16 1 TF041 TH RES 8 2K 1 10W 196 Downloaded from LpManual com Manuals 286301485001 286300452001 PU2 288204800008 282574405205 TF041 TH IC 74HC4052MX_NL DUA 286302731001 TFO41 TH ICLM2731YME Boost 286000864002 TFO41 TH IC OZ864 DUAL BATT
11. South Bridge ICH7 M PCLIRDY PCI FRAME PCI PCI 2 PCI GNT42 PCI PCI PCI CLKRUN 2 R138 0 PCI AD22 R159 0 PCI AD 0 31 PCI_C BE 0 3 Downloaded from LpManual com Manuals 13948 HOST TSB82AA2 3V 0 0 PHY POWER L518 1202 100 C581 C562 C594 4 7U 0 1U PLLVDD3 3V 120Z 100M AVDD3 3V L517 120Z 100M V f Y Y PHY_D 0 7 PHY_CTL 0 1 R127 22 PHY_LCLK PHY_PCLK PHY_LREQ PHY_LINKON PHY_PINT PHY_LPS s 1394B PHY TSB81BA3 PHY_POWER PLLVDD1 8V 1 L525 1207 100 6 P29 M e e S ____ R612 s TT 100P U510 5 5 2 C604 C605 zazio 4 579301 12 Lome 13948 C21 270P 2 R36 R35 S MIN 562 562 a TPAO 1394B_GND TPAO 501 02008 6 5A 32VDC SSA34 TE Vsys o TPBO n TPBO 8 E 12010 1202 100M 13948 3 o f Y Y R610 100 29 OUT R611 133 X502 V 98 302MHzOSC 13948 GND 1394B 191 M230 N B Maintenance 8 13 Mini Express Wireless Socket Test Error 1 An error occurs when a wireless card device is installed ini Express Wireless Socket Test Error
12. SATACLKREQ GPS o TP I XBAY ID 07 1 CRTINN GMOR r usare I po I I I I USBOC 7 GPIO31 Downloaded from LpManual com Manuals M230 N B Maintenance 2 System View and Disassembly 2 1 System View 2 1 1 Front View Top Cover Latch Device Indicators Touch Screen Pen Handle oooce Kensington Lock 2 1 2 Left side View CD Combo DVD RW Drive Hard Disk Drive Downloaded from LpManual com Manuals 91 M230 N B Maintenance 2 1 3 Right side View Primary Battery Pack PC Card Slot USB Port 2 1394B Port 2 1 4 Rear View IR Port Power Connector Serial Port RJ11 Port RJ45 Port External VGA Port Parallel Port External Microphone Connector 0090000000 Line Out Connector Downloaded from LpManual com Manuals 92 2 1 5 Bottom View 2 1 6 Top open View M230 N B Maintenance SIM Card Slot Release Knob Docking Connector POGO Memory Slot Stereo Speaker Set Power Button LCD Screen Device Indicators Keyboard Touch Pad Downloaded from LpManual com Manuals 93 M230 N B Maintenance 2 2 Tools Introduction 1 Minus screw driver for notebook assembly amp disassembly 1 2mm gt 2mm gt 4 2 Auto screw driver for notebook assembly amp disassembly Bit Size gt 0 eese
13. 126 Mother Board akon tudes ae aa en EDI VIR Ida AU E IIS 126 5 Pm Description of Major Component ERE UE 128 Intel Processor M IU 128 5 2 Intel DAS North Bridge ___________ ______ 133 Downloaded from LpManual com Manuals M230 N B Maintenance Contents 5 3 Intel ICH7 M South Bridge lu DE EA DUK DN PAPER _ 139 6 System taranu 150 7 Mamtenance Di ghostitsS re deba pre ror p 151 7 1 Introduction 151 7 4 Maintenance Diagnostics Nee rto b NI eee Er ER HR ee 152 ymago PG V ILIUM 153 5 Trouble Shooting sisse PR PRPAUCHEREEE XR uM EXER EN 160 ING POWER EET S uU wm ATE 162 8 2 No Display 166 8 3 Graphic Controller Test Error LCD No Display 0 0 0 0 00707777 169 8 4 External Monitor No Display or Color Abnormal 2 2 000 0 171 5 2 Memory Test Err r coo Ae Roo iore rrr Rte ERR 173 8 6 Keyboard
14. 9 ACAUDO 81 12 13 113 114 CARD VA 139 JAmRSV DM O 76 77 84 9 2 100 108 118 126 13 4 142 149 150 Downloaded from LpManual com Manuals Switched output that delivers 0 V 3 3 V 5 V or high impedance to card Switched output that delivers 0 V3 3 V 5 V 12 V or high impedance to card Ground 72 M230 N B Maintenance gt I O Board 28 pin Connector Mitac 291000012806 Signal name Downloaded from LpManual com Manuals Power On default Purpose Direction S0 State S3 State S4 State Carrier detector signal a COMI Received data signal _____ _____ COMI Transmitted data signal COMI Data terminal ready signal COMI Ring indicator signal COMI Data set ready signal COMI Request to send signal COMI Clearto send fata Tansnitand Reve Pat p Lo 0 o 73 M230 N B Maintenance gt I O Board 120 pin Connector Mitac 291000011229 1 Pin Signal name 1 AGND DEVICE SPDIFOUT LCD SM DATA LCD SM DDCPCLK DDCPDATA COM3 RXD BY Ww 28 9 0 1 4 5 Downloaded from LpManual com Manuals LL Oe LLL pue 0
15. 533 MC 534 PF502 SMD A B PF503 BAT CLK DATA PF504 Try another known good I O board 162 Downloaded from LpManual com Manuals M230 N B Maintenance 8 1 No Power 2 When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up Main Voltage Map PQ527 5 PQ534 PD503 PD504 Charge gt PLSOS PUS06 PQ523 PQ528 VDOCK PLS18 PR562 PJ2 ee Discharge 0526 533 PD501 PD502 501 gt mm BBATT 0522 PL506 3 PD533 P31 ABATT BBATT so A D 9 Vsys E P33 m 10527 45V PD531 533 PQ514 PQ515 PU502 PL513 542 PL514 PD508 P33 052 E 5V m SVA SV l Gy 117 PQ516 PQ517 19337 PLS15 PLS16 PUSO3 PL517 233 1058 en a 33 3V P33 5VA PL524 PL525 PU507 PQ539 PQ540 PL523 2 105170518 SV 1 8V PUSH 3i P 10517 0518 P34 09V te 40 9 VS P33 3 3VA PLSO4 PLSOS PUI PQ501 PQ502 PL510 P35 305170518 52 1 5V 1 5VS 10540 ues m 10512 0516 P35 pP 1 05V VCCP PL520 PL521 PU508 PL507 PL508 PQ505 PQ510 PU2 PQ512 PQ513 PL509 PR503 PL512 PR514 NOTE P33 Page 33 on M B Board circuit diagram Downloaded from LpManual com Manuals P36 PQ535 PQ536 PL519 10532 P36 12V 1 2VS PQ537 PQ538 PL522 P36 105330534 P36 125V G3 VDD P
16. RX gt 1513 e PMDI2 PLP2168 MDI2 TRD ss U500 8 MDD PMDD MDD TRD2 s 5 1517 PMDI3 PLP3216S HN2426SG TRD3 3 D4 MDB PMDI3 2 1 MDI3 TRD3 MTC 0 3 R517 75 _ C550 1000P T RJ45 GND 189 M230 N B Maintenance 8 12 1394B Test Error 1 An error occurs when a 1394 device is installed 1394B Test Error 1 Check if the 1394B device is installed properly 2 Confirm 1394B driver is installed ok Board level Troubleshooting U6 U7 U9 Try another known ee Replace Motherboard 1394B ee Yes Re test Change the faulty Downloaded from LpManual com Manuals Parts Check the following parts for cold solder or one of the following parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement Signals 3V DVDD1 8V DVDD3 3V PLLVDD1 8V PHY POWER PHY DJ O 7 0 TPBO PCI AD 0 31 PCI C BE 0 3 PCI RESET PCI_INT C PCI_SERR PCI PERR 8 12 1394B Test Error 2 M230 N B Maintenance An error occurs when a 1394 device is installed 3V R136 2 7K R137 2 7K SDA C104 L 0 1U 7 SCL 0522 U7 AT24C02LM8 PCI PAR PCI SERR PCI PCI STOP4 PCI DEVSEL amp PCI
17. bus data input and output pins GPIO Software control device power MIC2545 on or off GPIO IGNITION signal power on GPIO Output power on signal PWM D A pulse output pin HDD heater PWM output 85 M230 N B Maintenance 1 3 1 Keyboard Controller GPIO Pin Definition 4 Power On default PB7 input and output pins Output e T IH NP PB6 input and output pins Output eee P VA Atways O oo POYAIS KOS Keyboard Keyboard Matrix KEY BD MATRIX Internal KEY BD MATRIX Internal KEY BD MATRIX Internal KEY BD MATRIX Internal KEY BD MATRIX Internal KEY BD MATRIX Internal Deu ____ ___ KEY BD MATRIX 67 P20 A8 KO8 68 ALERT wo f EN HE Internal Keyboard Matrix Battery PBS input and e exp ama vo faisable AC fonction ws ws 91 M yss _ 1 1 KEY BDMATRIX Internal m pms msn KEY BD MATRIX ea na Ru LIII 2 Downloaded from LpManual com Manuals 86 M230 N B Maintenance 1 3 1 Keyboard Controller GPIO Pin Definition 5 Power On default S0 S3 54 Signal name Direction State State State Connectto Description KEY BD MATRIX Internal wu ume KEY BD MATRIX Internal Dee imm KEY BD MATRIX Internal wp cee KEY BD MAT
18. 120Z 100M H8 VDD3 126 120Z 100M H8 AVREF L32 120Z 100M H8 VDD5 3VA O 3VS R752 i 82K SERIRQ 0522 ICH7 M South Bridge 4 e a KBD EN EL LFRAME LPC LADJ 0 3 EXTAL XTAL LL 4 654 503 Gea 22P 10MHz iS Downloaded from LpManual com Manuals Keyboard BIOS H8S 2140 J I O Board J2 R547 VOK LED_KB_PWRSV Ps Internal 5 Keyboard Connector KI 0 7 KI 0 7 KO 0 15 KO 0 15 Q500 KBD ENE 51230105 R546 2 i SW Board P J509 J500 P sy 17 J 1501 5VS VDD CLK DATA L560 SWR 45 1207 100M ow P2 R654 lt R653 e _ 4 7K 4 7K E TPD CLK L558 1202 100 TPD CLK E TPD DATA 1559 1202 100 TPD DATA 3 1 eirg v 4 SWI 3 1 4 97 7 SW2 3 1 9 19 0 2 176 M230 N B Maintenance 8 7 Hard Disk Drive Test Error 1 Either an error message is shown or the drive motor spins non stop while reading data from or writing data to hard disk Hard Disk Drive Test Error 1 Check if BIOS setup is OK 2 Try another working drive Board level Troubleshooting One of the following parts or signals on the mother
19. GND XCLKB TCCLKB ele Downloaded from LpManual com Manuals 64 M230 N B Maintenance gt KBD Connector MiTAC 291000003015 Power On default Pin Signal name Direction S0 State S3 State S4 State En uuu p mr mq gp dq Jj gs LL 9 Dp p Downloaded from LpManual com Manuals KBD matrix KBD matrix 65 M230 N B Maintenance Continue to the previous page Pin Signal name Power On default 50 State S3 State 54 State Direction seme f o LL x LL Oi ve ve avai ve 3 pore p ee 30 LED PWR LED keyboard power gt SATA HDD Connector MiTAC 291000025204 Power On default Signal name Direction 50 State S3 State 54 State Purpose T p poo s mer s me EL Jesse ressatFosiive ipa _ o 0 BS bees SATAHDD RXN I SATAHDD RXP I ___ 1 4 5 7 x SATARDD_TP 14 17 19 24 27 28 31 33 NC Downloaded from LpManual com Manuals M230 N B Maintenance gt RTC Battery Connector 2 pin Hirose DF13 2P MiTAC 291000020233 Power On default Signal name Direction p State m State EST State pm The charge function will not support for RTC battery The consumption of RTC CMOS memory will
20. GPIO Wakeup event DC bus clock input and output pins I2C bus clock output pin P85 IRQ4 RXD1 RSMRST E P86 IRQS SCK1 H8 SMB CLjK P84 IRQ2 TXD1 H8_WAKE_UP Downloaded from LpManual com Manuals 88 M230 N B Maintenance 1 3 2 ICH7 M GPIO Pin Definition 1 Power On Signal Name default m Multi Func Note Description Direction 50 State 3 State 54 State Power plane PM_BMBUSY GPIOO Low Low Core Low PPCL_REQSH Resered ume 1 rrr Gmowmmog 1 oseon cos 1 sm 1 cos 1 lt KU ff ff ff ff ff IP GMOB TI KBDENEL ___ 1 IDEHDD RST GPOIS 1 8 P Native Coe I I I I I I I I I I I I I I I I 0 XBAYIDO GPIOIJSTAIGP 1 0 Log Native EM EX gt Downloaded from LpManual com Manuals M230 N B Maintenance 1 3 2 ICH7 M GPIO Pin Definition 2 Power On Signal Name default Item Multi Func Note Description Direction S0 State S3 State S4 State 24 GPO_ENOVA 1 GPIO24 Defined Defined GPOENOVA2 o Resume TP Resume TP ____ Resume TP GPOOWELSTATED O Resume Resume Resume Resume P USBOC 6 GPIO30 PCI CLKRUN GPIO32 MINI PDA GPIO33 Zo 4 amp
21. Board level Troubleshooting 1 Check if the wireless card device is installed properly 2 Confirm wireless driver is installed ok Check the following parts for cold solder or one of the following parts on the mother board may be defective use an oscilloscope Y to check the following signal or replace the parts one at a time and i Correctit Replace test after each replacement Motherboard Signals 3VS MINI PD PCIE RXN3 SMBCLK PCIE RXP3 SMBDATA PCIE TXN3 SMB CLK PCIE TXP3 SMB DATA PCIECLKREQ2 WLAN LINK GRN CLK PCIE 81 CLK PCIE S14 PCIE WAKEZ Change the faulty part then end 192 Downloaded from LpManual com Manuals M230 N B Maintenance 8 13 Mini Express Wireless Socket Test Error 2 An error occurs when a wireless card device is installed Downloaded from LpManual com Manuals 3VS J17 R835 10K PCIECLKREQ2 U523 WE E IL R779 2 CLK_PCIE_S1 gt Clock R778 22 CLK_PCIE_S1 gt z Generator SMBDATA A A 0 SMBCLK 891 d ICS9LR310 43V 3VS al R233 R228 27002 2 R745 K 10K 10K ies IK b D 5 SMBCLK Qs _G E P15 SMB_DATA S ATs TOS e PCIE_WAKE R340 0 z e EP U522 J USBP6 _XBAY 2 PCIE RXN3 South Bridge PCIE RXP3 S OU PCIE_TXN3 gt 5 C700 1 0 1U PCIE TXP3
22. 156 M230 N B Maintenance 7 3 Error Codes 5 Tpoint 8ch 8th 90h 91h 92h 93h 95h 96h 97h 98h Post Routine Description Initialize both of the floppy disks and display an error message if failure was detected Check both drives to establish the appropriate diskette types in the TrustedCore data area Count the number of ATA drives in the system and update the number in bdaFdiskcount Initialize hard disk controller If the CMOS ram is valid and intact and fixed disks are defined call the fixed disk init routine to initialize the fixed disk system and take over the appropriate interrupt vectors Configure the local bus IDE timing register based on the drives attached to it Jump to UserPatch2 See The POST Component Build the MPTABLE for multi processor boards 1 Check CMOS for CD ROM drive present 2 Activate the drive by checking for media present 3 Check sector 11h 17 for Boot Record Volume Descriptor 4 Check the boot catalog for validity 5 Pick a boot entry 6 Create a Specification Packet Reset segment register addressibility from 4GB to normal 64K by generating a Shutdown 8 Create pointer to MP table in Extended BDA Search for option ROMs Rom scan the area from C800h for a length of ROM Scan Size or to E000h by default on every 2K boundary looking for add on cards that need initialization Downloaded from LpManual com Manuals Tpoint 99h Ja
23. CRT HSYNC CRT HSYNC CRT HSYNC IA LG 050 P24 s 2N7002 CRT VSYNC R596 0 CRT VSYNC C CRT VSYNC CRT VSYNC CRT e _5 D 5 s s GND e 3VS aonn 0508 lt Pis 0522 ua SN74LVC2G125 REM 10K gt CRT CRT IN CRT IN CRT South Bridge 5 1510 5 ICH7 M 120Z 100M e e a AGND CRT 5 R564 0 D CRT RED CRT RED L4 752100 CRT RED VGA CRT GREEN R590 0 CRT GREEN CRT GREEN L8 75Z 100M CRT_GREEN e e 2 L10 75Z 100M VGA_CRT_BLUE R60 0 CRT BLUE CRT BLUE 5 CRT BLUE 1515 12 13 14 R31 R30 R29 120Z 100M 3 3P 75 7 77 Downloaded from LpManual com Manuals GND AGND CRT AGND CRT 172 M230 N B Maintenance 8 5 Memory Test Error 1 Extend DDR2 SO DIMM is test error or system hangs up Memory Test Error 1 Check the extend SDRAM module is installed properly J504 J505 2 Confirm the SDRAM socket J504 J505 is One of the following components or signals on the motherboard may be defective use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement Board level Troubleshooting ok no band pins 3 Check if on board SDRAM chips are no cold solder Parts Signals 0521 1 8V SMBCLK J504 0 9VS SMBDATA J505 DDR2_VREF M DDR O 3 R205 DDRA B 0 131 M CLK DDRZ 0 3 R240 DDR CKEZ 0 3 DDRA B D
24. 041 5 30 1 1 16 1 0 272075680307 TF041 TH CAP 68P 50V 5 0 271061432102 TF041 TH RES4 3K 1 16W 195 04 271071333102 TF041 TH RES33K 1 16 1 271061196215 041 5 19 6 1 167 1 0 Downloaded from LpManual com Manuals Part Number 274012500430 271061490102 TF041 TH RES49 9 1 16W 1 284500007017 272433156506 041 150 25 20 60 286300320002 TF041 TL IC PIBUSB20 SWITCH 4 0515 284180786068 TFO41 TH IC CPU YONAH L V 1 66 U513 281307125007 TFO41 TH IC NC7SZ125 SINGLE S 272075471422 TF041 TH CAP 470P CR 50V 1096 PC534 2881040240 2881793010 7961160400 PRIS 2710613031 7961160700 27106115111 PC22 R761 2881033150 R631 R633 M M2X0AP M M2 0X0 4 16W 1 0 16W 1 06 TF041 TH RES 150 1 16W 1 Part Number 282574132012 TF041 TH IC 74AHCT1G32 SINGLE U2000 271061122107 TF041 TH RES 1 21K 1 16W 1 TF041 SPACER H 5 0 796115040005 TF041 SPACER H23 0 343114900045 TF041 SPACER H 2MM M3X0 5 ML9 MTGH7 MT GH8 TF041 TH RES33K 1 16W 196 PR545 PR599 TF041 TH RES30K 1 3 3 271071114104 TF041 TH RES 1 LOK 6 0 MTGH32 MTGH33 PR536 PR539 PR54 PR596 PR597 TF041 SPRING T CSBM46 6 10 GND 515 564 565 R1000 R1001 R1005 207 M230 N B Maintenance 9 Spare Parts List 13 Cnm
25. 1 Remove the battery pack Refer to sections 2 3 1 Disassembly 2 Remove nine screws fastening the DDR2 SDRAM cover Figure 2 16 3 Pull the retaining clips outwards and remove the SO DIMM 9 Figure 2 17 Figure 2 16 Remove nine screws Figure 2 17 Remove the SO DIMM Reassembly 1 To install the DDR2 match the DDR2 s notched part with the socket s projected part and firmly insert the SO DIMM into the socket at a 20 degree angle Then push down until the retaining clips lock the DDR2 into position 2 Replace the DDR2 SDRAM cover and secure with nine screws 3 Replace the battery pack Refer to section 2 3 1 Reassembly 105 Downloaded from LpManual com Manuals M230 N B Maintenance 2 3 7 LCD Assembly Disassembly 1 Remove the battery pack and keyboard Refer to section 2 3 1 and 2 3 4 Disassembly 2 Disconnect the LCD cable from the I O board And remove four screws to free the LCD assembly Figure 2 18 Figure 2 18 Free the LCD assembly Reassembly 1 Attach the LCD assembly to the base unit and secure with four screws 2 Replace the LCD cable to the I O board 3 Replace the keyboard and battery pack Refer to sections 2 3 4 and 2 3 1 Reassembly Downloaded from LpManual com Manuals 106 M230 N B Maintenance 2 3 8 LCD Panel Disassembly 1 Remove the battery pack and keyboard See sections 2 3 1 and 2 3 4 Disassembly 2 Remove sixteen screws to release four
26. 346801200001 361400004013 411114300129 331000005041 332100020023 332100020033 332100020034 332801500001 332100026021 332110020189 365350000009 411114300130 271002391102 271046407105 TF041 CO TF041 CO Part Number F041 CONTACT PLATE W5L58T0 1 TF041 CONTACT PLATE W5L80T0 1 TF041 CONTACT PLATE W5L11 5T0 TF041 CONTACT PLATE W5L24T0 1 F041 CONTACT PLATE WSL45T0 1 Po F041 TH CONTACT PLATE W4L30T Po TACT PLATE WS5L9T0 13 TACT PLATE WSLASTO 1 LO TF041 WIRE 220 UL 007 22mm BL TF041 WIRE 20 UL1007 22mm RE Q TF041 WIRE 26 UL1007 L18 BLUE TF041 T H RES 390 1 10W 1 08 TF041 T H RES 0 040 2W 1 2512 R9A1 R9B1 R9C1 Downloaded from LpManual com Manuals Eum 27 27 27 27 27 27 27 27 272003474403 2720034754 272005105402 2720052204 272072474403 272073104712 272073105403 272075151309 272075222407 272075680307 286002084002 286029312002 71071100103 071101107 071104114 071104310 071105312 071471103 071502304 0716131 07184210 288100056026 288104148022 288204409003 294112000001 TF04 TF04 TF04 TF04 TF04 TF04 TF04 TF04 TF04 TF04 TF04 TF04 TF04 TH RES 10 1 16W 196 TH RESI00 1 16W 196 TH RES 100K 1 16W 1 TH RES 100K 1
27. Description HTRDY GTL Host Target Ready This signal indicates that the target of the processor transaction is able to enter the data transfer phase HHITM GTL Hit Modified This signal indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line In addition HHITM is driven in conjunction with to extend the snoop window HRS 2 0 GTL Host Response Status These signals indicate the type of response as shown below 000 Idle state 001 Retry response 010 Deferred response 011 Reserved not driven by 100 Hard Failure not driven by G MCH 101 No data response 110 Implicit Write back 111 Normal data response HLOCK GTL Host Lock All processor bus cycles sampled with the assertion of HLOCK and HADS until the negation of HLOCK must be atomic i e no DMI or PCI Express accesses to DRAM are allowed when HLOCK is asserted by the processor BSEL 2 0 COMS Bus Speed Select At the de assertion of RSTIN the value sampled on these pins determines the expected frequency of the bus HRCOMP COMS Host RCOMP This signal is used to calibrate the Host GTL I O buffers This signal is powered by the Host Interface termination rail Vrr HPCREQ GTL 2X Precharge Request The processor provides a hint
28. S3 State Microphone Input 59 M230 N B Maintenance gt Parallel Port Connector MiTAC 331040009005 Power On Signal default name Direction 50 State S3 State 54 State Purpose 1 eem 8 0 E P LPD6 2 PIO Data bit7 signal vo 6 om 1 18 19 20 21 2 Shield 2232425 ground Ground PIO printer Select Input poo E d ub L 1 Ay gt Prt Printer Acknowledge WU eer T __ mr j JE 4 2 NEN ay 1 2 3 4 5 7 10 11 12 13 14 15 16 17 Downloaded from LpManual com Manuals M230 N B Maintenance gt VGA Port Connector Mitac 331040009005 Power On default Signal name Direction 80 State 3 State S4 State Purpose NC 6 Downloaded from LpManual com Manuals M230 N B Maintenance gt 1394B Port Connector MiTAC 291000000905 Power On default Pin Signal name mm ERN State n State S4 State Purpose __ __ _____ ao Yo 4 qo 1012 5 Shield eround _ _ _ Liam I nt 19V 9 Shield eround Ground gt Stereo Jack MiTAC 331840010019 Power On default Signal name Direction S0 State mm State 54 State Purpose pecTHP
29. gt nu ICH7 M annie gt D14 ee R2002 30 SL ios WLAN_LINK_GRN RESA 193 M230 N B Maintenance 8 14 PCMCIA Socket Test Error 1 An error occurs when a express card device is installed PCMCIA Socket Test Error Check the following parts for cold solder or one of the following Check if the PCMCIA device is installed properly parts on the mother board may be defective use an oscilloscope Y to check the following signal or replace the parts one at a time and i Correctit Replace test after each replacement Motherboard Parts Signals Board level Troubleshooting 0518 CARD 0520 0522 VPPA BOUT A B_CTRDY J15 A B CCLK A B_CIRDY L537 L541 PCI AD 0 31 A B_CPERR PCI C BEA 0 3 A B_CSERR CAD 0 31 A B_RST CCBEA 0 3 CPAR CCD 1 2 4 Change the faulty part then end 194 Downloaded from LpManual com Manuals M230 N B Maintenance 8 14 PCMCIA Socket Test Error 2 An error occurs when a express card device is installed 0522 South Bridge ICH7 M 42V 0 Pr L539 L538 0518 120Z 100M VPPA B 45V Power Switch yccA p 5V 3 0 4 VPPA BOUT L537 120Z 100M o 5 CARD_VA B R695 R732 L540 L541 3 1202 1001 a gt PCI AD 0 31 PCI_C BE 0 3 To ee PCI PAR PCI_FRAME PC
30. 4 39P 2 CLK V R797 0 STOP_PCI gt Pis P7 CLK R773 2 R803 0 STOP CPU gt 0522 CLK R774 22 CLK_USB48 4 R869 A 22 0521 4 CLK 3GPLL R840 22 R816 33 CLK_ICHI4 North Bridge cxMewscm rea 2 South Brid EP 14 R838 22 CLK PCIE ICH gt ou riage Intel 945GM PERS n te R839 22 CLK_PCIE_ICH gt ICH7 M BSEL1 s R863 33 PCLCLK R718 U523 R815 2 SATA_CLK MCH_BSELO IK R808 SATA CLK R778 22 Clock CLK PCIE 51 a JA7 R785 58782 Generator CLK PCIE S1 gt Mini Express IK IK E la PCIECLKREQ2 Connector Wireless P4 U513 PES 21 R870 22K FS A ICS9LR310 R790 2 T CPU BSELI R810 22K FS B R795 2 3 J13 CPU lt e e 52 CLK PCIE XBAY gt h ones 22 8 PCIECLKREQI X BAY ona lt Connector Pa U9 R847 33 PCI 1394 CLK gt 1394 Controller 0512 e PCICLK_FWH R821 33 R884 33 PCICLK_CARD SYS BIOS 7 gt 0520 R885 33 CLK PCIE CARD C d ar U13 k PCI H8 CLK R792 22 ENS CLK POE CARD Controller H8S 2140 mn 36 22 PCIE CLK_LAN us R837 22 PCIECLK LAN Giga LAN 167 Downloaded from LpManual com Manuals 8 2 No Display 3 U13 KBC H8S 2140 M230 N B Maintenance EEE Dower Good amp Reset Circuit Check Aud
31. 43VS LAN 33 VMAIN 3 3 MDI 0 3 PMDI 0 3 LAN_RST PCI LPC CLK SMBCLK SMBDATA PCIE R TXPI PCIE R TXNI Check if BIOS Check if BIOS setup is ok is ok Replace Motherboard Re test Yes 188 Downloaded from LpManual com Manuals 8 11 LAN Test Error 2 An error occurs when a LAN device is installed U522 South Bridge ICH7 M R539 3 200 XTALO XTALI e e C537 X501 L C540 27P 23MHZ ce V V LAN_3 3 R71 R72 1K PCIE_WAKE 9 PCIEWAKE 4 PCIE LAN RST amp 0 LAN_RST LPC LAD 0 3 R94 0 LPC LAD 0 3 LFRAME PCI SERIRQ R512 0 SMBCLK SMBDATA R579 0 PCIE_RXP1 PCIE RXNI PCIE_TXP1 PCIE TXNI PCI LPC CLK PCLLPC From page 6 U523 Downloaded from LpManual com Manuals LAN Controller BCM5789M M230 N B Maintenance 117 1207 100 VMAIN 3 3 Y Y 3VS cg 0 1U T 010 T V 112 Y 120Z 100M LAN_3 3 T 43V C49 0 1U T Pu J9 510 3 J505 1506 MDI0 PMDIO PLP32168 MDI0 J 3VAA Aa MDIO 2 NYCYWI MDIO Ps TX L516 i PLP3216S RX E 3 PMDII Y
32. 48 50 52 54 ag 51 515 Ss JE 5 JE alc a a w e 79 PLP 52 mx EC N EN igo Q 4 2 dg m Ee v 5 52 PCIE RXP2 Downloaded from LpManual com Manuals p p E NEN _ c a __ CNN ss NEN LE S3 State lt lt lt S4 State Not Connect 80 M230 N B Maintenance gt X Bay 84 pin Connector Mitac 291000018402 2 S0 State S3 State Microphone Input Signal m gum 1 1 49 60 64 68 72 s pa s pevam s mo Downloaded from LpManual com Manuals M230 N B Maintenance gt 84 pin Connector Mitac 291000018402 3 Power On default Signal name Direction 50 State S3 State S4 State Purpose m eo C LLL s wrowerseesersim s eon SC rey LUE LL Downloaded from LpManual com Manuals M230 N B Maintenance 1 3 Electrical Characteristic 1 3 1 Keyboard Controller GPIO Pin Definition 1 Power On default 50 53 54 Signal name Direction State State State Connect to Description Crys When pin low the chip is 1 RES H8 I Reset button reset H
33. BIOS writes code description error code to port by Mini section to find out PCI E debug which part is causing card the problem Make sure that CPU module DIMM memory are installed properly Board level Troubleshooting No One of the following parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement Replace Motherboard I Try another known good CPU module Parts Signals DIMM module 2 Remove all of I O device HDD CD ROM from motherboard except LCD or monitor SMBCLK HCPURST SMBDATA H8_RESET PCI CLK HPWRGD PCICLK_CARD ACZ_RST CLK_PCIE_ICH CD_RST CLK PCIE ICH PLT_RST CLK_USB48 PWR_ON 4 PCI RESET CLK MCH 3GPLL PCI 1394 CLK 3GPLL PCIE LAN RST 1 Replace faulty part Display 2 Connect the I O device to the M B OK one at a time to find out which part is causing the problem coc vede eee ie Downloaded from LpManual com Manuals M230 N B Maintenance 8 2 No Display 2 System Clock Check C765 vd CLK SMBDATA SMB DATA 1 xs SMBCLK SMB CLK C764 14 318MHz T gt
34. CUL CE CB CCC WHQL BSMI E Mark Easy changeable wireless modem in X BA Y EDGE EVDO GPS ODD devices Combo drive DVD dual Vehicle docking board Backward compatible with M220 Options HDD heater Full travel membrane keyboard with backlight Rubber keyboard with backlight Blue tooth class 1 TECOM Class I module BT3014 with Broadcom firmware v 1 2 Downloaded from LpManual com Manuals M230 N B Maintenance 1 2 System Architecture 1 2 1 Function Description 1 2 1 1 CPU gt Intel Mobile Yonah processor First dual core processor for mobile Yonah and Yonah low voltage skus 667 MT s 667 MHz FSB support On die primary 32 KB instruction cache and 32 KB write back data cache On die 2 MB L2 cache with advanced transfer cache architecture Streaming SIMD Extension 2 SSE2 and Streaming SIMD Extension 3 SSE3 Support Intel architecture with dynamic execution Advanced gunning transceiver logic AGTL bus driver technology Enhanced Intel SpeedStep technology to anable real time dynamic switching between multiple voltage and frequency points Data prefetch logic 479 ball Micro FCBGA package Downloaded from LpManual com Manuals M230 N B Maintenance 1 2 1 2 North Bridge amp 3D Graphics DDR2 Chipset Intel 945GM gt FSB Support AGTL bus driver technology with integrated GTL termination resister gated AGTL receivers for reduced power Supports 32 bit AGTL host bus a
35. Description SCAS B Column Address Strobe SSTL 1 8 This signal is used with SRAS and SWE along with SCS_B to define the SDRAM commands SWE_B Write Enable SSTL 1 8 This signal is used with SCAS_B and SRAS B along with SCS_B to define the SDRAM commands SDQ B 63 0 yo Data Lines SSTL 1 8 The SDQ B 63 0 signals interface to the SDRAM data bus 2X SDM B 7 0 Data Mask SSTL 1 8 When activated during writes the corresponding data groups in 2X the SDRAM are masked There is one SDM Bx bit for every data byte lane SDQS_B 7 0 VO Data Strobes SSTL 1 8 For DDR2 SDQS Bx and its complement SDQS_Bx signal 2X make up a differential strobe pair The data is captured at the crossing point of SDQS Bx and its complement SDQS_Bx during read and write transactions SDQS_B 7 0 Uo Data Strobe Complements SSTL 1 8 are the complementary DDR2 strobe signals 2X SCKE B 3 0 Clock Enable SSTL 1 8 1 per Rank Bx is used to initialize the SDRAMs during power up to power down SDRAM ranks and to place all SDRAM ranks into and out of self refresh during Suspend to RAM SODT B 3 0 On Die Termination SSTL 1 8 On die Termination Control signals for DDR2 devices PCI Express Interface Signals Signal Name Type Description EXP RXN I15 0 VO PCI Express Receive Differential Pair EXP_RXP 15 0 PCIE EXP_TXN 15 0 PCI Express Transmi
36. Name Type Description Platform LAN Connect Interface Signals SATA3GP GPIO37 I Serial ATA 3 General Purpose Same function as SATAOGP except for SATA Port 3 If interlock switches are not required this pin can be configured as GPIO37 Name Type Description LAN CLK I LAN I F Clock This signal is driven by the Platform LAN Connect component The frequency range is 5 MHz to 50 MHz SATALED OC Serial ATA LED This is an open collector output pin driven during SATA command activity It is to be connected to external circuitry that can provide the current to drive a platform LED When active the LED is on When tri stated the LED is off An external pull up resistor to Vcc3 3 is required NOTE An internal pull up is enabled only during PLTRST assertion LAN RXDI2 0 Received Data The Platform LAN Connect component uses these signals to transfer data and control information to the integrated LAN controller These signals have integrated weak pull up resistors LAN TXD 2 0 Transmit Data The integrated LAN controller uses these signals to transfer data and control information to the Platform LAN Connect component SATACLKREQ GPIO35 OD Native GP Serial ATA Clock Request This is an open drain output pin when configured as It is to connect to the system clock chip When active request for SATA Clock running is
37. No Display Definition Base on the digital IC three basic working conditions working power reset Clock We define no display as while system leave S5 status but can t get into SO status Judge condition gt Check which power will cause no display gt Check which reset signal will cause no display gt Check which Clock signal will cause no display Base on these three conditions to analyze the schematic and edit the no display chapter Keyword gt 5855 Soft Off gt 50 Working For detail please refer the ACPI specification 161 Downloaded from LpManual com Manuals M230 N B Maintenance 8 1 No Power 1 When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up Check following parts and signals Parts Signals 505 Vsys PF501 PF502 VDOCK PQ3 518 ADINP AC PQ519 521 LEARNING po boss ADENY ower gt PWR AC PD501 PD504 Bs PL501 PL503 PD519 PD522 CHG_B Board level Troubleshooting Is the notebook connected power either AC adapto or battery Where from power source problem first use AC to power it Connect AC adaptor or battery Try another known good battery or AC adapter Check following parts and signals Replace the Faulty AC battery Motherboard Parts Signals ABATT BBATT Battery PJ3 VBATTI 2 PWR_BATT PQ522 DCH_A B
38. PC card sockets These devices allow the controlled distribution of 3 3 V 5 V 12 V to each card slot The current limiting and thermal protection features eliminate the need for fuses Current limiting reporting helps the user isolate a system fault The switch Rds on and current limiting values have been set for the peak and average current requirements stated in the PC card specification key features Fast current limit response time Fully integrated VCC and VPP switching for 3 3 V 5 V and 12 V Meets current PC card standards VPP output selection independent of VCC 12 V and 5 V supplies can be disabled TTL Logic compatible inputs Short circuit and thermal protection 140 uA Typical quiescent current from 3 3 V input Break before make switching Power on reset 40 C to 85 C operating ambient temperature range 32 pin SSOP package 20 Downloaded from LpManual com Manuals M230 N B Maintenance 1 2 1 5 Read Only Memory Flash ROM FWH bus interface Single 3 3 V operations 3 3 V volt Read 3 3 V volt Erase 3 3 V program Fast program operation VPP 12 V Byte by Byte programming 9 typ Fast erase operation Fast read access time Tkg 11 ns Endurance 30 K cycles typ Twenty year data retention 16 even sectors with 64 K bytes Any individual sector can be erased Hardware protection TBL supports 64 Kbyte Boot Block hardware protection Downloaded from LpManual com Manua
39. Pis R197 8 2K U522 IDE_PDA 0 2 USBP1 _FDD IDE_PDA 0 2 USBP1 _FDD 4 IDE 18014 IDE 18014 IDE_PDDACK IDE_PDDACK IDE_PIORDY IDE_PIORDY J South Bridge 4 IDE_PDIOW IDE_PDIOW IDE PDDREQ IDE PDDREQ ICH7 M IDE_PDIOR IDE_PDIOR IDE_PDCS 1 3 IDE_PDCS 1 3 R1005 330 DAC A K CDACTP 45VS D34 PGI102W RI79 470 CD CDL C521 IU CDROM L R23 0 CDL 0502 CD GND C517 T 1U CDROM_COMM 4 R7 0 CD COMM 5 Audio Codec CDR C513 1U CDRPM_R R6 0 180 M230 N B Maintenance 8 9 USB Test Error 1 An error occurs when a USB I O device is installed USB Test Error Check if the USB device is installed properly Board level Check the following parts for cold solder or one of the following Troubleshooting parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time Yes and test after each replacement No Parts Signals U522 5V J10 SB_OC 0 JH SB OC 2 SBP0 0517 SBP2 Replace another known good USB device Re test OK No Replace Motherboard 122 0515 D506 D507 D515 D518 SB2 BUSO BUSI SB_CTRL U U U U L18 USBO U V V U Yes 181 Downloaded from LpManual com Manuals 8 9 USB Test Error 2 M230 N B Maintenance An error occurs when a USB I O device is installed 45V R634 10K 0515 DTCI44WK
40. Tpoint Post Routine Description 0 52h Verify keyboard reset 34h Initialize keystroke clicker if enabled in Setup 55h Enable USB devices Test for unexpected interrupts First do an STI for hot interrupts h h initialization data block h h h Secondly test the NMI for an unexpected interrupt Thirdly enable the parity checkers and read from memory checking for an unexpected interrupt POST Dispatch Manager Sbh i ch bh Disable CPU cache 5 Test RAM between 512K and 640K Determine and test the amount of extended memory available Determine if memory exists by writing to a few strategic locations and see if the data can be read back If so perform an address line test anda RAM test on the memory Save the total extended 155 M230 N B Maintenance 7 3 Error Codes 4 Perform an address test on A0 to the amount of memory available This test is dependent on the processor since the test will vary depending on the width of memory 16 or 32 bits This test will also use A20 as the skew address to prevent corruption 64h Jump to UserPatchl See The POST Component Set cache registers to their CMOS values if CMOS is valid unless auto configuration is enabled in which case load cache registers from the Setup default table Quick initialization of all Application Processors in a multi processor system Enable external cache and CPU cache if present Configure non 6h cach
41. standard W O battery pack gt 50 C 20 C to 60 C optional W O battery pack gt 50 C Storage 40 to 70 C According to IEC 68 2 30 MIL STD 810F Method 507 45 to 95 RH non condensing According to 68 2 13 MIL STD 810F Method 500 4 Operating 15 000 ft non operating 40 000 ft Altitude change rate 2 000 ft min According to IEC 68 2 27 MIL STD 810F Method 516 5 Operating 15 g 11 ms half sine wave Non operating 50 g 11 ms half sine wave According to IEC 68 2 6 MIL STD 810F Method 514 5 Operating 10 57 5 Hz 0 075 mm 57 5 500 Hz 1 0 g MIL STD 810F 514 5Cl high way truck vibration exposure Non operating 10 57 5 Hz 0 15 mm 57 5 500 Hz 2 0 g MIL STD 810F 514 5C 17 general minimum integrity exposure M230 N B Maintenance Continue to the previous page According to IEC 68 2 32 MIL STD 810F Method 516 5 Drop 3 foot high free drop on steel plate 4 foot high free drop on plywood plate 26 times one machine EUCH close Power off According to TEC1000 4 2 to IEC1000 4 2 Air Discharge 0 KV 8 KV included no any error 8 KV 15 KV allow soft error Contact data pin discharge 0 KV 6 KV included no any error 6 KV 8 KV allow soft error 5 Sodium Chloride NaCl during the entire exposure period measure the salt fog fallout Salt Fog rate and PH ofthe fallout solution at least at 48 hour intervals Ensure the fallout is between 1 and 3 ml 80 em hr FCC part 15 Subpart B C Class B UL
42. 0 VO LPC Multiplexed Command Address Data FWH 3 0 For LAD 3 0 internal pull ups are provided LFRAME LPC Frame FWH4 LFRAMEZ indicates the start of an LPC cycle or an abort LDRQ 0 I LPC Serial DMA Master Request Inputs LDRQ 1 LDRQ 1 0 are used to request DMA or bus master access These GPIO23 signals are typically connected to external Super I O device An internal pull up resistor is provided on these signals LDRQI may optionally be used as GPIO Vss Grounds 194 pins Downloaded from LpManual com Manuals 147 5 3 Intel ICH7 M South Bridge 10 Functional Strap Definitions M230 N B Maintenance Functional Strap Definitions Continued Signal Usage When Sampled Description ACZ SDOU XOR Chain Rising Edge of Allows entrance to Chain testing when T Entrance PCI PWROK pulled low at rising edge of PVROK See Express Port Chapter 25 for XOR Chain functionality Config bit 1 information When TP3 not pulled low at rising edge of PWROK sets bit 1 of RPC PC Chipset Config Registers Offset 224h See Section 7 1 34 for details This signal has a weak internal pull down ACZ SYNC PCI Express Rising Edge of This signal has a weak internal pull down Port Config bit PWROK Sets bit 0 of RPC PC Chipset Config 0 Registers Offset 224h See Section 7 1 34 for details GPIO25 Reserved Rising Edge of This signal has
43. 16W 5 TH RESIM 55 I 16W 56 TH RES61 9K 1 16W 196 TH RES8 45K 1 10W 196 TH CAP 47U TH CAP 4 7U 0 10 TH CAP 22U 0 10 25 10 25 10 080 50 10 10 50 25 10 060 RI2 R8 RI R18 R20 R3 TF04I TH RES470 1 16 1 R30 R31 R32 R33 116 5 R24 R5 R6 R10 R23 CLC C13 C14 C16 C21 041 0 470 16 10 06 C12 C4 C9 209 M230 N B Maintenance 9 Spare Parts List 15 Part Number Description Location s 294112000002 TH041 TH LED RED 12 21SURC SS LEDI 316683700021 TF041 PCB PWA ML900 BATT GAU Part Number Description Location s 221680850002 TFO41 PARTITION BATTERY MARLI E 221680850003 TF041 PARTITION TOP BTM BATTE MEN 361200003201 TF041 ADHESIVE SILICONE DOW C 242804400010 TF041 TH LABEL BAR CODE 20 5 MEN 288104024001 TF041 TH DIODE T VS ARRAY 40PF TVSI 310111103049 TF041 THERMIST OR 10K 1 RA DI 332100026031 TF041 WIRE 26 UL1007 115mm Y 6 225600020010 TF041 PE FILM SKIN PACKING MEI 225600020006 TF041 T APE CARTON 2 5W 30M RL EINE 225600020002 TF041 T APE I 2 WRINKLE 796115070064 TF041 LABEL 1 10MM 85MM PACKIN MEN 335612000006 TF041 THERMAL CUTOFFS378 8A V9 _ 798961150005 TF041 CARTON MAIN SYSTEM M220 MEE 346671600025 TF041 INSULATOR BATT ASSY W7L 335152000134
44. 272013475403 272023475402 272071105411 272071334404 272072105403 272073223408 272075101408 272075103415 272075471415 272075472703 272990100302 273001050263 281101010004 291000020229 291000911101 295000010248 316115000040 242804400010 361200003204 422116000002 411115100022 271002000312 TF041 TH RES 8 2K 1 10W 1 TF041 TH CAP IU 25 10 TF041 TH CAP 68P CR 2KV 10 TF041 TH CAP 4 7U 25V 10 1 TF041 TH CAP 4 7U 259 10 1 TF041 TH CAP 1U 10V 10 060 TF041 TH CAP 0 33U 10V 10 TF041 TH CAP 0 1U 16 10 TF041 T H CAP 0 022U CR 25V 1 TF041 TH CAP 100P 50V 10 0 TF041 TH CAP 0 01U 50 10 TF041 TH CAP 470P 50V 10 06 TH CAP 4700P 50V 20 TH CAP 10P 3000V 5 XFMR LH10 20 1720 270mH TF041 T H IC MP1010BEF LF CCF TF041 TH RESO 110 5 e oo rj Sj S Az 19 19 e gt Downloaded from LpManual com Manuals Part Number Description Location s RI4B C22 C7 gt gt C N gt e 2 C16 C6 5 20 21 1 C13 C3 C8 e 5 5 ssa Ul R107 Part Number 271071103108 272011226706 272075104710 284510321002 291000021410 291000033003 331040010023 242600000572 242600000676 3161160000 n 242804400010 361200003204 2261160100 221801220102 365350000009 242600000566 2266838101 222672730002 796115060052 796115060053 796
45. BNR Block Next Request is used to assert a bus stall by any bus agent that is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Downloaded from LpManual com Manuals Signal Name Type Description BPM 2 1 BPM 3 0 BPM 3 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 3 0 should connect the appropriate pins of all Intel Pentium M processor system bus agents This includes debug or performance monitoring tools BPRI BPRI Bus Priority Request is used to arbitrate for ownership of the processor system bus It must connect the appropriate pins of both processor system bus agents Observing BPRI active as asserted by the priority agent causes the other agent to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI BRO Io BRO is used by the processor to request the bus The arbitration is done between the Intel Pentium M processor Symmetric Agent and the Mobile Intel 945 Express chipset family High Priority Agent BSEL 2 0 BSEL 2 0 Bus SELECT are used to select the processor input clock
46. Bridge 8 General Purpose I O Signals M230 N B Maintenance General Purpose I O Signals Continued Name Type Tolerance Power Well Description GPIO1 vO 5 Multiplexed with 5 0 33V Core Unmultiplexed NOTES 1 GPI 15 0 can be configured to cause a SMI or SCI Note that a GPI can be routed to either an or an SCI but not both 2 Some GPIOs exist in the VccSus3 3 power plane Care must be taken to make sure GPIO signals are not driven high into powered down planes Some ICH7 GPIOs may be connected to pins on devices that exist in the core well If these GPIOs are outputs there is a danger that a loss of core power PWROK low or a Power Button Override event will result in the Intel ICH7 driving a pin to a logic 1 to another device that is powered down PCI Express Signals Name Type Description 1 4 PCI Express Differential Transmit Pair 1 4 PETn 1 4 PERp 1 4 I PCI Express Differential Receive Pair 1 4 PERn 1 4 5 6 PCI Express Differential Transmit Pair 5 6 PETn 5 6 Reserved ICH7 Intel ICH7R Only PERp 1 4 I PCI Express Differential Receive Pair 5 6 PERn 5 6 Reserved ICH7 ICH7R Only SM Bus Interface Signals Name Tolerance Power Well Description GPIO
47. DDRB RASA DDRB_WE DDRB MA 0 13 DDR_CKE 0 3 DDR_CS 0 3 DDR ODT 0 3 DDRB DQSI0 7 DDRB_DQS 0 7 DDRB MDJI0 7 DDRB MA 0 13 DDR B DQ 0 63 M CLK DDR 2 3 M CLK DDR 2 3 PM_EXTTS 1 174 M230 N B Maintenance 8 6 Keyboard K B or touch pad T P Test Error 1 Error message of keyboard or touch pad test error is shown or any key does not work Keyboard or touch pad Test Error Check J2 J501 for cold solder Yes gt Re soldering Is K B or T P cable connected to notebook properly Board level Troubleshooting Replace Motherboard No Mera Yes Try another known good Keyboard or touch pad One of the following parts or signals on the motherboard may be defective use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement Yes Yes Replace the faulty Keyboard or touch pad No Parts Signals U13 KI 0 7 U522 KO 0 15 2 SERIRQ 33 LFRAME J500 LPC_LAD O0 3 J501 1307 ue J509 x25 TPD CLK SW1 SWA TPD DATA Are all the connectors between boards connected properly as Reconnect Try one known it good board each time 175 Downloaded from LpManual com Manuals M230 N B Maintenance 8 6 Keyboard K B or touch pad T P Test Error 2 Error message of keyboard or touch pad test error is shown or any key does not work L31
48. ICH7 is prepared to latch data IRDY is an input to the ICH7 when the ICH7 is the target and an output from the ICH7 when the ICH7 is an initiator IRDY remains tri stated by the ICH7 until driven by an initiator Name Type Description AD 31 0 T O PCI Address Data AD 31 0 is a multiplexed address and data bus During the first clock of a transaction AD 31 0 contain a physical address 32 bits During subsequent clocks AD 31 0 contain data The Intel ICH7 will drive all 0s on AD 31 0 during the address phase of all PCI Special Cycles TRDY T O Target Ready TRDY indicates the Intel ICH7 s ability as a target to complete the current data phase of the transaction TRDY is used in conjunction with IRDY A data phase is completed when both TRDY and IRDY are sampled asserted During a read TRDY indicates that the ICH7 as a target has placed valid data on AD 31 0 During a write TRDY indicates the ICH7 as a target is prepared to latch data TRDYT is an input to the ICH7 when the ICH7 is the initiator and an output from the ICH7 when the ICH7 is a target TRDY is tri stated from the leading edge of PLTRST TRDY remains tri stated by the ICH7 until driven by a target STOP vo Stop STOP indicates that the ICH7 as a target is requesting the initiator to stop the current transaction STOP causes the ICH7 as an initiator to stop the current transaction STOP is an output when
49. LpManual com Manuals 152 M230 N B Maintenance 7 3 Error Codes 1 Following is a list of error codes in sequent display on the Mini PCI debug board Post Routine Description Post Routine Description Verify Real Mode If the CPU is in protected mode turn on A20 Och Set the initial POST values of the cache registers if not integrated and pulse the reset line forcing a shutdown 0 into the chipset NOTE Hook routine should not alter DX which holds the powerup Set the initial POST values for registers in the integrated I O chip CPU ID Enable the local bus IDE as primary or secondary depending on 03h Non Maskable Interrupts other drives detected Get CPU type from CPU registers and other methods Save CPU Initialize Power Management type in NVRAM General dispatcher for alternate register initialization Set initial NOTE Hook routine should not alter DX which holds the powerup llh POST values for other hardware devices defined in the register CPU ID tables Initialize system hardware Reset the DMA controllers disable the videos clear any pending interrupts from the real time clock and set reset up port B register Early reset of PCI devices required to disable bus master Assumes Disable system ROM shadow and start to execute ROMEXEC 13h the presence of a stack and running from decompressed shadow code from the flash part This task is pulled into the build only when memory the ROMEXEC relocation is inst
50. LpManual com Manuals 31 M230 N B Maintenance 2 88 MB Super I O Floppy Disk Controller Licensed CMOS 765B floppy disk controller Software and register compatible with SMSC s proprietary 82077AA compatible core Supports two floppy drives directly Configurable open drain push pull output drivers Supports vertical recording format 16 byte data FIFO 100 IBM compatibility Detects All overrun and under run conditions Sophisticated Power Control Circuitry PCC including multiple Power Down Modes for reduced power consumption DMA enable logic Data rate and drive control registers 480 addresses up to 15 IRQ and four DMA options gt Floppy Disk Available on Parallel Port Pins ACPI Compliant Enhanced digital data separator 2 Mbps Mbps 500 Kbps 300 Kbps 250 Kbps data rates Downloaded from LpManual com Manuals 32 M230 N B Maintenance Programmable precompensation Serial Ports Four full function serial ports High speed NS16C550 compatible UARTs with Send Receive 16 byte FIFOs Supports 230 K and 460 K baud Programmable baud rate generator Modem control circuitry 480 address and 15 IRQ options Downloaded from LpManual com Manuals 33 M230 N B Maintenance 1 2 1 8 1394B Controller TI TSB82AA2 Single 3 3 V supply 1 8 V internal core voltage with regulator 3 3 V and 5 V PCI signaling environments Serial bus data rates of 100M bits s 200M bits s 400M bits s an
51. M and operating under master mode the second is multi master Bus and connected from H8S 2140 The Master provides interface to synthesizer and to memory identification The multi master channel used for thermal sensor controller SMBus from LCD interface and SMBus from Docking A CODEC ALC260 with TI audio amplifier stereo analog audio to internal speakers audio jack and docking Digital audio PDIF standard also provided to audio jack and to docking System also provides LEDs to display system status such as power on battery state HDD Num Lock Caps Lock and Scroll Lock The system also provides a port to expand docking capability Input Output I O ports can include parallel port serial port VGA port USB line out video input The system also provides DVD ROM Bluetooth GPS X BAY radios A full set of software drivers and utilities are available to allow advanced operating systems such as Windows 2000 and Windows XP to take full advantage of the hardware capabilities Detailed specs as follow Downloaded from LpManual com Manuals M230 N B Maintenance Features Standard Intel Yonah processor LV dual core 1 66 GHz in package CPU Intel Yonah processor LV dual core 1 5 GHz in package a CPU thermal ceiling 15 W FSB 667 MHz Intel 945GM chipset Calistoga ICH7 M PCI Express x 6 channels L2 Cache on die 2 MB 1 MB flash EPROM Includes system BIOS Phoenixsolution Kernel core
52. Maintenance 2D Acceleration Features A highly optimized 128 bit engine capable of processing multiple pixels clock Hardware acceleration is provided for Bitblt line drawing polygon and rectangle fills bit masking monochrome expansion panning and scrolling scissoring and full ROP support including ROP3 Optimized handling of fonts and text using ATI proprietary techniques Game acceleration including support for Microsoft s DirectDraw Double Buffering Virtual Sprites Transparent Blit and Masked Blit Acceleration in 8 15 16 32 bpp modes Support for WIN 2000 amp WIN GDI extensions Alpha BLT Transparent BLT Gradient Fill Hardware cursor support up to 64x64x32 bpp with alpha channel for direct support of WIN 2000 amp WIN XP alpha cursor standard gt 3D Acceleration Features DirectX9 Shader Model 3 0 support Full DX9 conformance including floating point per component at full speed Support for 2X AA 4X AA and 6X AA subsamples with little performance loss in most cases Advanced AA quality algorithms generating visuals that are superior to other solutions with an equivalent number of samples 2X AX 8X 16X anisotropic filtering modes Adaptive algorithm with bi linear performance and tri linear quality options 39 Downloaded from LpManual com Manuals M230 N B Maintenance Dedicated geometry acceleration for Direct3D and OpenGL which incorporates 2 parallel Vector Scalar Engines perf
53. Maintenance PCI Express x1 port support One general purpose PCI Express port support External graphics using PCI Express architecture and SDVO are functional in this mode Direct Media Interface DMI Chip to chip interconnect between the GMCH and Intel 832801 GBM DMI X2 and DMI X4 configurations support Bit swapping is supported Lane reversal is supported Packing power 1466 ball micro FCBGA 37 5 mm x 37 5 mm with a 42 mil x 34 mil ball pitch VCC 1 05 core supply VCCSM DDR2 1 8 V I O supply VCCHV 3 3 V high voltage supply VCCA CRTDAC 2 5 V CRT analog supply VCC SYNC 2 5 V HSYNC VSYNC supply VCCD LVDS 1 5 V digital supply VCCTX LVDS 2 5 V Data CLK Tx power supply VCCA LVDS 2 5 V LVDS analog supply Downloaded from LpManual com Manuals M230 N B Maintenance VCCA TVBG 3 3 V TV DAC bnad gap supply VCCD TVDAC 1 5 V TV DAC supply VCCDQ TVDAC 1 5 V TV DAC quiet supply VCCA TVDACA 3 3 V TV out Channel A supply VCCA TVDACB 3 3 V TV out Channel B supply VCCA TVDACC 3 3 V TV out Channel C supply VCC3G 1 5 V PIC E DMI analog supply VCC3A GBG 2 5V PCI E DMI band gap supply VCCA HPLL 1 5 V host VCO supply VCCA MPLL 1 5 V system memory VCO VCCD HMPLL 1 5 V digital dividers supply VCCA 3GPLL 1 5 V PCI E PLL supply VCCA_DPLLA B 1 5 V Display PLL supply Downloaded from LpManual com Manuals M230 N B Maintenance 1 2 1 3 System Frequency Synthes
54. NOTE The ICH7 will ignore RCIN assertion during transitions to the S3 54 and 55 states A20GATE A20 Gate A20GATE is from the keyboard controller The signal acts as an alternative method to force the A20M signal active It saves the external OR gate needed with various other chipsets INIT Initialization INIT is asserted by the ICH7 for 16 PCI clocks to reset the processor ICH7 can be configured to support processor Built In Self Test BIST CPUPWRGD GPIO49 CPU Power Good This signal should be connected to the processor s PWRGOOD input to indicate when the CPU power is valid This is an output signal that represents a logical AND of the ICH7 s PWROK and VRMPWRGD signals This signal may optionally be configured as a GPIO INIT3_3V Initialization 3 3 V This is the identical 3 3 V copy of INIT intended for Firmware Hub Firmware Hub Interface Signals INTR Processor Interrupt INTR is asserted by the ICH7 to signal the processor that an interrupt request is pending and needs to be serviced It is an asynchronous output and normally driven low Downloaded from LpManual com Manuals Name Type Description FWH 3 0 Lo Firmware Hub Signals LAD 3 0 These signals are multiplexed with the LPC address signals FWH4 Firmware Hub Signals LFRAME This signal is multiplexed with the LPC LFRAME signal 145 5 3 Intel ICH7 M South
55. SIO FWH LAN G MCH IDE TPM etc The ICH7 asserts PLTRST during power up and when S W initiates a hard reset sequence through the Reset Control register I O Register CF9h The ICH7 drives PLTRST inactive a minimum of ms after both PWROK and VRMPWRGD are driven high The ICH7 drives PLTRST active a minimum of ms when initiated through the Reset Control register I O Register CF9h NOTE PLTRST is in the VccSus3 3 well WAKE PCI Express Wake Event Sideband wake signal on PCI Express asserted by components requesting wakeup SLP_S3 S3 Sleep Control SLP S37 is for power plane control This signal shuts off power to all non critical systems when in S3 Suspend To RAM S4 Suspend to Disk or S5 Soft Off states SYNC MCH SYNC This input is internally ANDed with the PVROK input Connected to the ICH SYNC output of G MCH THRM Thermal Alarm Active low signal generated by external hardware to generate an SMI or SCL SLP_S4 54 Sleep Control SLP_S4 is for power plane control This signal shuts power to all non critical systems when in the S4 Suspend to Disk or S5 Soft Off state NOTE This pin must be used to control the DRAM power to use the ICH7 s DRAM power cycling feature Refer to Chapter 5 14 10 2 for details THRMTRIP Thermal Trip When low this signal indicates that a thermal trip from the processor occurred and the ICH7 will immedi
56. Signals Continued A20M 20 2 will go active based on either setting the appropriate bit in the Port 92h register or based on the 20 input being active Name Type Description CPUSLP CPU Sleep This signal puts the processor into a state that saves substantial power compared to Stop Grant state However during that time no snoops occur The Intel ICH7 can optionally assert the CPUSLP signal when going to the 51 state NMI Non Maskable Interrupt NMLis used to force a non Maskable interrupt to the processor The ICH7 can generate an NMI when either SERR is asserted or IOCHK goes active via the SERIRQ stream The processor detects an NMI when it detects a rising edge on NMI is reset by setting the corresponding NMI source enable disable bit in the NMI Status and Control register I O Register 61h FERR Numeric Coprocessor Error This signal is tied to the coprocessor error signal on the processor FERRE is only used if the ICH7 coprocessor error reporting function is enabled in the OIC CEN register Chipset Config Registers Offset 31FFh bit 1 If FERRE is asserted the ICH7 generates an internal IRQI3 to its interrupt controller unit It is also used to gate the IGNNEZ signal to ensure that IGNNEZ is not asserted to the processor unless FERR is active FERR requires an external weak pull up to ensure a high level when the coprocessor error
57. Type II x 1 and built in smart card reader x 1 optional Azalia 32 bits 192 KHZ AC97 2 3 Audio digital controllerBuild in Stereo 2 W speakers Serial port x 1 USB 2 0 x2 USB power support maximum 1 A per port IrDA FIR x1 DC input x1 Docking Port POGO pin hot docking compatible with M220 CRT port x 1 1394B port x 1 Optional PS2 port x 1 Parallel port x 1 RJ 45 x1 RJ 11 x1 Microphone in x 1 Line out x 1 Integrated 10 100 1000 base T Ethernet with TPM security function Integrated 56 kbps Modem Integrated Wireless LAN 802 11 a b g with antenna Factory optional GPS module with antenna Factory optional wireless module for GSM GPRS CDMA with antenna Downloaded from LpManual com Manuals M230 N B Maintenance Continue to the previous page Communication AC Adaptor Altitude Downloaded from LpManual com Manuals Factory optional Bluetooth with antenna No any interface between 4 antennas in the same time No fan Main battery supports over 5 hours Second battery supports over 2 hours Based on system without M54 VGA controller 90 Watts universal or above auto sensing switching fully support all the functions Input 100 240 V 50 60 Hz AC 328 x272 1 x46 mm for M230 4 14 1 338 x 286 x 46 mm for M230 5 15 Same dimension as M220 xl Front side USB2 0 right side x2 rear side x2 IEC 68 2 1 2 14 MIL STD 810F Method 501 4 502 4 Operating 0 C to 55
58. a weak internal pull up RSMRST NOTE This signal should not be pulled low GPIO16 Reserved This signal has a weak internal pull down NOTE This signal should not be pulled high SATALED Reserved This signal has a weak internal pull up enabled only when PLTRST is asserted NOTE This signal should not be pulled low TP3 XOR Chain Rising Edge of See Chapter 25 for functionality information Entrance PWROK This signal has a weak internal pull up NOTE This signal should not be pulled low unless using XOR Chain testing Direct Media Interface Signals Signal Usage When Sampled Description GNT3 Top Block Rising Edge of The signal has a weak internal pull up If the Swap Override PWROK signal is sampled low this indicates that the system is strapped to the top block swap mode Intel ICH7 inverts A16 for all cycles targeting FWH BIOS space The status of this strap is readable via the Top Swap bit Chipset Config Registers Offset 3414h bit 0 Note that software will not be able to clear the Top Swap bit until the system is rebooted without GNT3 being pulled down GNT2 Reserved This signal has a weak internal pull up NOTE This signal should not be pulled low REQ 4 1 Chain Rising Edge of See Chapter 25 for functionality information Selection PWROK LINKALER Reserved This signal requires an external pull up resistor SPKR No Reboot Rising Edge of The signal has a weak internal pull down
59. adds wait states to PIO DD 15 0 VO IDE Device Data transfers These signals directly drive the corresponding signals on the IDE Disk Read Strobe Ultra DMA Reads from Disk When reading from connector There is a weak internal pull down resistor on DD7 disk ICH7 latches data on rising and falling edges of this signal from DDREQ I IDE Device DMA Request the disk This input signal is directly driven from the DRQ signal on the IDE Disk DMA Ready Ultra DMA Writes to Disk When writing to connector It is asserted by the IDE device to request a data transfer disk this is deasserted by the disk to pause burst data transfers and used in conjunction with the PCI bus master IDE function and are not associated with any AT compatible DMA channel There is a weak internal pulldown resistor on this signal DDACK IDE Device DMA Acknowledge This signal directly drives the DAK signal on the IDE connector i is asserted by the Intel ICH7 to indicate to IDE DMA System Mana Signals slave devices that a given data transfer cycle assertion of DIOR or DIOW is a DMA data transfer cycle This signal is used in INTRUDER I Intruder Detect conjunction with the PCI bus master IDE function and are not This signal can be set to disable system if box detected open associated with any AT compatible DMA channel This signal s status is readable so it can be used like a GPIO if the DIOR O DIOR Disk Read and Non Ult
60. amp Giga LAN Board Connector 119 Downloaded from LpManual com Manuals M230 N B Maintenance 3 Definition amp Location of Connectors Switches 3 2 I O Board Side B A A Lo _ LL gt LCD Cable Connector gt J2 Internal Keyboard Connector HSWI _ gt HSWI Power Button 120 Downloaded from LpManual com Manuals 3 Definition amp Location of Connectors Switches 3 3 LED Board M230 N B Maintenance HJ1 Downloaded from LpManual com Manuals HJ1 LED Board to MB Connector 121 M230 N B Maintenance 3 Definition amp Location of Connectors Switches 3 4 Touch Screen Board Side A gt J600 Presume Pin Assignment gt J601 Touch Screen Cable Connector J600 J601 122 Downloaded from LpManual com Manuals M230 N B Maintenance 3 Definition amp Location of Connectors Switches 3 4 Touch Screen Board Side B J100 Inverter Board to Touch Screen Board Connector 1101 gt J101 LCD Cable Connector J100 123 Downloaded from LpManual com Manuals M230 N B Maintenance 3 Definition amp Location of Connectors Switches 3 5 Switch Board Side A SWI SW2 SW3 SWA4 Downloaded from LpManual com Manuals gt SW1 SW4 Switch Button 124 M230 N B Maintenance 3 Definition amp Location of Connectors Switches 3 5 Switch Board Side B gt J500 Touch
61. and output pins GPIO 110 switch signal input pin ICH7 M GPIO Throttle signal Power switch GPIO Power button used py A Keyboard Keyboard Matrix Keyboard Keyboard Matrix Keyboard Keyboard Matrix _ Keyboard EN Touch Pad Touch Pad data ave ______ 38 P70 ANO Analog input pin Read main battery Battery 1 1 1 1 1 1 1 gt a m Downloaded from LpManual com Manuals 84 M230 N B Maintenance 1 3 1 Keyboard Controller GPIO Pin Definition 3 Power On default S0 S3 S4 Signal name Direction State State State N VBATT2 1 T T 2 N N PAO KEYINS ADEN 49 P40 TMCIO PWROK P41 TMO0 SPK OFF P42 TMRIO H8 SMB DATA I 52 P43 TMCI HIRQ SCI s pemonmos 54 PASTMRIUHIRO POWERON CARKEY 1 55 pawo 0 Lp ss dem Downloaded from LpManual com Manuals I I I I Analog input pin Read second battery Battery2 voltage Analog output pin output charger current Analog output pin LCD panel 1 input and output pins Modem EN PAO input and output pins input EN EN ICH7 M GPIO Power OK signal output GPIO Software control speaker on or DC bus data input and output pins I2C
62. are source synchronous to ADSTB 0 7 RESET Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications Downloaded from LpManual com Manuals CPU Pin Description Continued Signal Name Type Description RESET I On observing active RESET both system bus agents will deassert their outputs within two clocks All processor straps must be valid within the specified setup time before is deasserted There is a 55 normal on die pull up resistor on this signal RS 2 0 RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of both processor system bus agents RSVD Reserved No Connect These pins are RESERVED and must be left unconnected on the board However it is recommended that routing channels to these pins on the board be kept open for possible future use Please refer to the platform design guides for more details SLP SLP Sleep when asserted in Stop Grant state causes the processor to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PL
63. be 3 uA the calculated life cycle for the RTC battery is no less than 6 years gt PCMCIA Connector MiTAC 291000251504 HE He Fe 1 1 IEEE p p 2 Card Bus address data bus Ooo ENS _ __ Downloaded from LpManual com Manuals 67 Continue to the previous page B CADII Downloaded from LpManual com Manuals M230 N B Maintenance o _ CmdBesaddess daabus 4111 CadBesaddess daabus o Cod Busaddresssdatabus 4114 CadBesaddess databus o CmdBesaddess daabus 41142 CadBesaddess daabus o o CmdBusaddess daabus Lo Bus address itata bus o o Bus address itata bus Busaddresssdata bus 4114 bus Lo Busaddresssdata bus Card Busaddresssdatabus 4414 Bus address itata bus Car Busaddresssdatabus 4114 Bus address itata bus po Car bus Busaddresssdatabus ___ _ Car bus 1111 Cad Busaddress databus pT Ow Busaddss daabus O Card Bus bus commands and byte enables Card Bus bus commands and byte enables Card Bus bus commands and byte enables Card Bus bus commands and byte enables 68 M230 N B Maintenance Continue to the previous page 3 E 6 5 B CBLOC
64. combination of 16 bit and Card Bus PC cards in the two sockets powered at 5 V or 3 3 V as required The PCI1520 is compliant with the PCI local bus specification and its PCI interface can act as either a PCI master device or a PCI slave device The PCI bus mastering is initiated during Card Bus PC card bridging transactions The PCI1520 is also compliant with PCI bus power management interface specification Key Features 209 terminal MicroStar BGA ball grid array GHK ZHK package 2 5 V core logic and 3 3 V I O with universal PCI interfaces compatible with 3 3 V 5 V PCI signaling environments Integrated low dropout voltage regulator LDO VR eliminates the need for an external 2 5 V power supply Mix and match 5 V 3 3 V 16 bit PC cards and 3 3 V Card Bus cards Two PC card or Card Bus slots with hot insertion and removal Serial interface to TI TPS222X dual slot PC card power switch Burst transfers to maximize data throughput with Card Bus cards Interrupt configurations parallel PCI serialized PCI parallel ISA and serialized ISA Serial EEPROM interface for loading subsystem ID and subsystem vendor ID Pipelined architecture greater than 130 Mbps throughout from Card Bus to PCI and from PCI to Card Bus Downloaded from LpManual com Manuals M230 N B Maintenance gt TPS2224A PCMCIA and Card Bus Power Switch The TPS2224A Card Bus power interface switch provide an integrated power management solution for two
65. from LpManual com Manuals 129 5 1 Intel Yonah Processor CPU 3 M230 N B Maintenance CPU Pin Description Continued Signal Name Type Description DSTBP 3 0 Io Data strobe used to latch in D 63 0 Signals Associated Strobe D 15 0 DINV 0 DSTBP 0 D 31 16 DINV 1 DSTBP 1 D 47 32 DINV 2 DSTBP 2 D 63 48 DINV 3 DSTBP 3 FERR PBE FERR Floating point Error PBE Pending Break Event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel 80387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state When FERR PBE is asserted indicating a break event it will remain asserted until STPCLK is deasserted Assertion of PREQ when STPCLK is active will also cause FERR break event For additional information on the pending break event functionality including identification of support of the feature and enable disable information refer to Volume 3 of the Intel Architecture Software
66. function is disabled NOTE FERR can be used in some states for notification by the processor of pending interrupt events This functionality is independent of the OIC register bit setting SMI System Management Interrupt SMI is an active low output synchronous to PCICLK It is asserted by the ICH7 in response to one of many enabled hardware or software events STPCLK Stop Clock Request STPCLK is an active low output synchronous to PCICLK It is asserted by the ICH7 in response to one of many hardware or software events When the processor samples STPCLK asserted it responds by stopping its internal clock IGNNE Ignore Numeric Error This signal is connected to the ignore error pin on the processor IGNNEZ is only used if the ICH7 coprocessor error reporting function is enabled in the OIC CEN register Chipset Config Registers Offset 31 FFh bit 1 If FERR is active indicating a coprocessor error a write to the Coprocessor Error register I O register FOh causes the IGNNE to be asserted IGNNE remains asserted until FERR is negated If FERR is not asserted when the Coprocessor Error register is written the IGNNE signal is not asserted RCIN Keyboard Controller Reset CPU The keyboard controller can generate INIT to the processor This saves the external OR gate with the ICH7 s other sources of INIT When the ICH7 detects the assertion of this signal INIT is generated for 16 PCI clocks
67. o e SI2303DS e I O Board C985 R1026 C647 C811 R521 fe T G II 0 1U M P24 J3 J507 P3 200K d 0522 1 gt 7002 sy s 4 7 R522 R523 TXOUTCLK24 0512 TXOUTCLK14 TXCLK TXOUT 10 12 4 TXOUTI 0 2 4 North Bridge TXOUT 20 22 4 TXOUTB 0 2 NB DDCBCLK NB DDCBDATA DDCPCLK DATA Intel 945GM 3VS LCD_SM_DATA Q5 a ain d 3VS LCD_SM_CLK Inverter Board H8SMB_DATA D 2 s 47K 27002 BLADJ I R06 H8SMB D S 4 7K EN BKL Por 21013 LM R641 622 Touch Screen 0503 m Board H8S 2140 NC7S08 U2001 ENABKL_SB vec H NC7S08 From south bridge v 4 __ ENABKL NB EM 8 From north bridge PWROK GND V From north bridge V Downloaded from LpManual com Manuals 170 M230 N B Maintenance 8 4 External Monitor No Display or Color Abnormal 1 There is no display or picture abnormal on monitor External Monitor No Display or Color Abnormal Connect the I O device amp cable to the M B one P at a time to find out 1 Confirm monitor is good and check Motherboard which part is causing the cables are connected properly 2 Try another known good monitor Board level Troubleshooting Display OK Yes Display OK One of the following parts on the mother board may be defective use an oscillos
68. settings 1 Single mode 2 Address increment 3 Auto initialization disabled channel 4 Cascade 4 Verify transfer Initialize interrupt controllers for some shutdowns Verify that DRAM refresh is operating by polling the refresh bit in PORTB Reset the keyboard Set segment register addressibility to 4 GB Downloaded from LpManual com Manuals Tpoint Post Routine Description Using the table of configurations supplied by the specific chipset module test each DRAM configuration to see if that particular configuration is valid Then program the chipset to its autosized configuration Before autosizing disable all caches and all shadow RAM Initialize the POST Memory Manager 2 2 Zero the first 512K of RAM 2 ch Test 512K base address lines 2e Test first 512K of RAM a 3h Initialize the Phoenix Dispatch Manager 8 9 Y 2fh Initialize external cache before shadowing 3 3 36h Vector to proper shutdown routine 3 Shadow the system BIOS Autosize external cache and program cache size for enabling later in h h h h 2h Compute CPU speed h h h h If CMOS is valid load chipset registers with values from CMOS otherwise load defaults and display Setup prompt If Auto Configuration is enabled always load the chipset registers with the Load alternate registers with CMOS values Setup defaults Rel 6 0 3dh 4th Initialize extended memory for RomPilot 2h 4 Initialize
69. sound cause of line out check of MIC check of CD ROM check the following the following the following parts amp signals parts amp signals parts amp signals Try another known kcu Parts Signals Parts Signals Parts Signals kcu CD ROM Replace Motherboard U507 AOUT L R 0502 5VS U502 CDL 010 DEVICE 0522 43VS U522 CDR U11 DECT 13 MICI L J12 CD_COMM J503 SPDIFOUT 1503 MICI R CDROM L 1506 LINE OUT L R 1507 MICI VREFO R CDROM R 1507 SPKLOUT MICI VREFO L CDROM COMM J508 SPKROUT Re test OK Yes en 185 Downloaded from LpManual com Manuals M230 N B Maintenance 8 10 Audio Test Error 2 Audio In No sound from speaker after audio driver is installed 5VS 5V CODEC 120Z 100M Pis 7 AVDDI 2 C54 L C548 C554 U504 100 RT9167 47CB L508 120Z 100M DVDDI 2 43VS o YY C54 C548 C554 010 0 10 10u T iet Pus a ACZ_RST R888 39 R582 0 ACZ_RST Pis e U502 d ACZ SDOUT R330 39 ACZ SDOUT 0522 ACZ SDINO R556 39 ACZ SDINO Audio Codec ACZ SYNC R325 39 ACZ SYNC lt ACZ BITCLK R886 39 R583 0 ACES South Bridge 260 T 22 9 ICH7 M V C56 SB SPKR kou p Y PC BEEP 11 Pis PCBEEP C566 0 1U U2000 CARDSPK eS From Page 27 U520 NC7S32 R699 10K Downloaded from LpMan
70. the bus owner will drive the clock signal low 17 86 MHz Downloaded from LpManual com Manuals 141 M230 N B Maintenance 5 3 Intel ICH7 M South Bridge 4 IDE Interface Signals IDE Interface Signals Continued Name Type Description Name Type Description DCS1 IDE Device Chip Selects for 100 Range DIOW Disk I O Write PIO and Non Ultra DMA For ATA command register block This output signal is connected to DSTOP This is the command to the IDE device that it may latch data from the the corresponding signal on the IDE connector DD lines Data is latched by the IDE device on the deassertion edge DCS3 IDE Device Chip Select for 300 Range of DIOW The IDE device is selected either by the ATA register file For ATA control register block This output signal is connected to the chip selects DCS1 or DCS3 and the DA lines or the IDE DMA corresponding signal on the IDE connector acknowledge DDAK DA 2 0 IDE Device Address Disk Stop Ultra DMA ICH7 asserts this signal to terminate a burst These output signals are connected to the corresponding signals on IORDY I I O Channel Ready PIO the IDE connector They are used to indicate which byte in either the DRSTB This signal will keep the strobe active on reads DIOW on ATA command block or control block is being addressed WDMARDY writes longer than the minimum width It
71. 1 16W 196 TH RES27K 1 16W 1 R139 R2020 R67 R107 R129 R687 R715 R716 041 52 1 16W 1 R186 R555 TH RESA7K 1 16 1 TH RES255 1 16W 195 040 TH RES221 1 16W 195 040 R232 R769 205 M230 N B Maintenance 9 Spare Parts List 11 271061201107 271061560306 271061240102 271061334103 271061800101 271061390309 271061204104 271061331313 271061492102 271061750105 271061131109 271071101107 271061152502 271071100103 271061510306 271071000312 271061010102 271061470502 271061330311 271061222104 271061433306 271061106308 271071220308 297120100019 297040200013 Part Number Description TF041 TH RES 200 1 16W 1 TF041 TH RES56 1 16 5 p TF041 TH RES24 9 1 16W 1 6 0 MEN TF041 TH RES332K L 16W 196 04 ro TEES ew TF041 TH RES200K 1 16W 1 TF041 TH RES 330 1 16W 5 04 TFO041 TH RES4 99K 1 16W 1 TFO41 TH RES 75 1 16W 1 0402 5 TF041 TH RES 130 1 16W 1 41 100 1 16W 1 TF041 TH RES 51 1 16W 594 0 TFO4I TH RESO 1 16 5 AAS TF041 TH RES 1 1 16W 196 0402 TF041 TH RESA7_ 1 16W 5 TF041 TH RES 33 1 16W 5 MEE TF041 TH RES2 2K l 16W 196 04 MEN 041 522 1 16 5 Downloaded from LpManual com Manuals Part Number Description 288003602002 ITF041 TH FIR HSDL 3602 007 28451026800 TF041 T H IC SIO10N268 SMSC SU TF041 TH IC BCM5752 GIGA Bit TF041 TH IC 1394B PHY TSB8IBA 2
72. 115070027 796115070069 413000020737 413000020734 796116070001 TF04 TF04 TF04 TF04 TH RESIOK 1 16 1 TH CAP 22U CR 10V 1206 109 110 C114 TH CON HDR 5P 2 FM 1 27 J103 rican ____ TF041 LCD LTDI41ECGA 14 1 EH LCD LT D141ECGA 14 1 XG TF041 TEMPERED GLASS 14 1 POL EINE 197 M230 N B Maintenance 9 Spare Parts List 3 796115 796115 796115 225600 230000 242600 242600 796115160032 796115150021 422116000015 796115160011 796115070019 796119002016 332810018001 791921160005 565111600001 799001160001 70067 70068 10025 00421 30047 00650 00651 242600000652 POT 6115160026 796115160027 796115160028 796115160029 796115160036 796115160037 raion TF041 PORON SR S 32P 297 4 2T MEN Weowemwwmome mwawmmcwerp TF041 LABEL 3 5 DISKETTE BLAN Po Downloaded from LpManual com Manuals Part Number 242600000653 230000030048 79611907000
73. 115100009 796115100010 796115100011 796115100012 796115100013 796115100014 796115100016 796116060003 442802200003 796115160017 796115160018 346121200009 411116000052 331000005046 331040004039 796115000001 331000004089 331000007082 331000005033 481116000001 421118200001 411116000054 272101015402 272013106504 TF04 TF04 TF04 TF04 TF04 Pan Naber wear RAN S mau WAS CAP ASSY DC IN M220 TF041 CAP ASSY PHONE JACK M22 MEE 041 ASSY PRINT PORT M22 MEN CAP ASSY RJI 1 RJ45 M220 CAP ASSY CRT M220 RUBBER DDR M230 muse muse Ran museo e TH CAP 1U 6 3V 10 04 TF041 TH CAP 10U 25V 20 1 EN 202 M230 N B Maintenance 9 Spare Parts List 8 272101104415 272102104708 272071475403 272431157518 272011226706 272001106404 272105101313 272401107507 272431477003 272105470403 272102224401 272103103407 272101474703 272431227006 272105392502 272105102421 TF041 T H CAP 4 7U 6 3V 10 06 TF041 TH CAP 100P 50V 5 04 TF041 T H CAP 3900P 50V 20 272001106517 TF041 TH CAP 10U 10V 80 20 272073104712 041 0 10 25 10 060 272105270305 041 27 50 5 04 272071225406 TF041 TH CAP 2 2U 6 3 1 272072474403 272072473409 2
74. 192 KHz sample rate 2 stereo ADCs support 16 20 bit PCM format with 44 1 48 96 KHz sample rate Applicable for 2 Channel 192 KHz DVD Audio solutions LINE OUT HP OUT LINE1 LINE2 and MIC2 are stereo input and output re tasking MONO line level output to subwoofer speaker for 2 1 channel applications High quality differential CD analog input External PCBEEP input is applicable and internal BEEP generator is integrated Power Off CD mode supported Power management and enhanced power saving features Power support Digital 3 3 V Analog 3 3 V 5 0 V Selectable 2 5 V 3 75 V VREFOUT Two jack detection pins each designed to detect 4 jacks Supports 44 1 K 48 K 96 kHz 192 kHz S PDIF output Supports 44 1 K 48 K 96 KHz S PDIF input 48 pin LQFP packages lead Pb free package also available Downloaded from LpManual com Manuals 36 M230 N B Maintenance Supports external volume knob control Reserve analog mixer architecture is backwards compatible with AC 97 64 dB 30 dB with 1 dB mixer gain for fine volume control Impedance sensing capability for each re tasking jack Built in headphone amplifier for each re tasking jack Supports GPIOs General purpose input output for customized applications Hardware copyright protection for DVD Audio Meets Microsoft WHQL WLP 2 0 audio requirements EAX 1 0 amp 2 0 compatible Direct Sound 3D compatible A3D compatible I3DL2 compatible H
75. 2000312 271061750105 284501284006 288100006006 286303311001 273000610054 316116000016 242600000572 288200144030 291000012808 288115112001 286301117110 273001050206 273000500187 TF04 TF04 TF04 5 TH RESIOK 1 16 1 RLRS R514 R515 R545 TH RES 100K 1 16W 1 TH RESO 1 10W 5 R547 R25 R544 R546 me meer ___ 5 200 M230 N B Maintenance 9 Spare Parts List 6 272073104712 041 0 10 25 10 060 271071101107 271061100103 TF041 TH RESI00 1 16W 1 TF041 TH RES 10 1 16W 196 0402 272105390401 041 39 50 10 04 796116050003 Downloaded from LpManual com Manuals Part Number Description Location s 272101016401 TF041 TH CAP 1U CR 10V 10 C504 C506 C522 C523 222687630001 226687620001 222672730002 242600000566 365350000009 R549 R550 797726443194 C530 C532 C534 C536 796115020018 TF041 MYLAR 13nm 26mm 0 4mm 271071103310 272005105402 272011106714 291000151219 297040105039 316116000006 242600000572 226800020001 221800020002 222672130002 Part Number ____ _ 5
76. 284505752007 4 286374131002 TF041 TH IC SN74LVCIG3157 DCK 3 3 2 3 2845013940 28450139400 TF041 TH IC 1394B CONTROLLER 2820743380 TF041 TH IC 74CBT D3384 10 BIT 4811160000 TF041 F W ASSY KBD CTRL H8 M 28636922900 TF041 TH IC G692L293Tf RESET 281307085005 TF041 TH IC NC7SZ08P5 2 INPUT 286301022001 041 ICADMIO22ARQ QSOP 1 282000302001 TF041 TH IC LIS3L02DQ G SENSO 2861048900 TF041 T H IC AUDIO AMPLIFIER L 3 284500260006 TF041 TH IC ALC260 AUDIO CODE 286391674003 TF041 TH IC RT9167 47P B LDO S 286100212002 TF041 TH ICiTPA0212 AMPLIFIER 282074212002 TF041 TH IC SN74LVC2G125 DUAL 286302545003 TF041 TL IC MIC2545A 1YMTR US 291000613223 TF041 TH IC SOCKET 32P PLCC T 286301117110 TFO41 TH IC APL1117 VC TRL 1A 284510321002 TF041 TH IC ADMI032ARZ 1 TEMP 286302224001 TF041 TH IC TP S2224A CARDBUS 284501520004 TF041 TH IC PCI1520 PCI CARDB 284509310001 TF041 TH IC ICSOLPR310 LOW P 282574164008 TF041 TH IC 74 VHC164 SIPO REG Location s l 001 08 o 5 U16 U2001 U503 C 501 502 504 507 508 511 U517 512 514 c Le qr et 516 518 520 523 526 206 M230 N B Maintenance 9 Spare Parts List 12 271061223106 TF041 TH RES22 1K 1 16W 196 271071134102 041 5 130 1 16W 1 271071303105
77. 32 Vcore P32 CPU CORE 10508 10509 163 M230 N B Maintenance 8 1 No Power 3 When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up Charge PF502 E FUSE 10A PD503 PD504 2N7002 Vsys SSA34 PLS03 m VDOCK 1207 100 4 20501 20502 ADINP 519 518 523 SRA A FDS6679 FDS6679 SI4835DY PL506 USE 818 PR531 8 120Z 100M 9 5 3 717 3 0 02 3 7 5 2 6156 2 2 6 e e 9 2 1 1 55 1 n 1 5 POWER IN 501 pcso3 di HY PL518 PR562 502 P 504 2 47UH 0 025 7 1207 100 b 0 1U M PR529 2 0402 120 Y Y e DE s 470K D A IACM HDR En V PL501 e 1202 100M ig PR530 HACE s H 100K P3 VAD Ps PQ528 L PWR AC 14832DY _ LEARNING 2N7002 PUS06 1 Avene 07864 0 U13 ICHM CHG A PD521 PD522 CHG B Keyboard x pl SSA34 901 9 FDS6679 BIOS 70527 i 4 FDS6679 2 676 2 H8S 2140 ABATT 1 H 545 9 lun A T gel 51570520 CHG_A SSA34 oon FDS6679 5VA PR51 100K Downloaded from LpManual com Manuals
78. 49 Io V CPU 10 V CPU IO Multiplexed with CPUPWRGD GPIO48 VO 33V Core Multiplexed with GNT4 GPIO 47 40 N A 33V N A Not implemented GPIO 39 38 Lo 3 3V Core Unmultiplexed GPIO37 VO 33V Core Multiplexed with SATA3GP GPIO36 VO 33V Core Multiplexed with SATA2GP GPIO35 3 3 V Core Multiplexed with SATACLKREQ GPIO34 vO 33V Core Unmultiplexed GPIO33 Uo 33V Core Unmultiplexed GPIO32 vO 33V Core Unmultiplexed GPIO31 vO 33V Resume Multiplexed with OC7 GPIO30 vO 33V Resume Multiplexed with OC6 GPIO29 VO 3 3 V Resume Multiplexed with 5 GPIO28 vO 33V Resume Unmultiplexed GPIO27 VO 3 3 V Resume Unmultiplexed GPIO26 vo 33V Resume Unmultiplexed GPIO25 VO 33V Resume Unmultiplexed GPIO24 Io 33V Resume Unmultiplexed Not cleared by CF9h reset event GPIO23 Uo 33V Core Multiplexed with LDRQ1 GPIO22 3 3 V Core Multiplexed with REQ4 GPIO21 33V Core Multiplexed with SATAOGP GPIO20 vO 33V Core Unmultiplexed GPIO19 33V Core Multiplexed with SATAIGP GPIO18 vO 33V Core Unmultiplexed GPIO17 VO 33V Core Multiplexed with GNTS GPIO16 vO 33V Core Unmultiplexed GPIO 15 12 Lo 3 3 V Resume Unmultiplexed GPIO11 VO 33V Resume Multiplexed with SMBALERT GPIO 10 8 VO 3 3V Resume Unmultiplexed GPIO 7 6 IO 3 3V Core Unmultiplexed GPIO 5 2 VOD 5 Multiplexed with PIRQ H E Name Type Description SMBDATA VOD 5 Data External pull up resistor is required SMBCLK VOD SMBus Clock Extern
79. 54 System timer refresh request speaker tone output gt Power Management Logic ACPI 2 0 compliant e ACPI defined power states C1 C4 S1 M 53 55 ACPI power management timer Support for Intel SpeedStep technology processor power control Support for Deeper Sleep power state Downloaded from LpManual com Manuals 49 M230 N B Maintenance PCI CLKRUN and PME support SMI generation All registers readable restorable for proper resume from 0 V suspend states Support for APM based legacy power management for non ACPI Desktop and Mobile implementation gt External Glue Integration ntegrated pull up pull down and series termination resistors on IDE processor interface ntegrated Pull down and Series resistors on USB gt NEW Serial Peripheral Interface SPI for Serial and Shared Flash gt Firmware Hub FWH Interface supports BIOS memory size up to 8 MB gt Low Pin Count LPC Interface Supports two Master DMA devices Support for Security Device Trusted Platform Module connected to LPC Enhanced DMA Controller Two cascaded 8237 DMA controllers Supports LPC DMA 50 Downloaded from LpManual com Manuals M230 N B Maintenance Real Time Clock 256 byte battery backed CMOS RAM ntegrated oscillator components Lower Power DC DC Converter implementation gt System TCO Reduction Circuits Timers to generate SMI and Reset upon detection of syste
80. 6 TF041 TAPE25MM 45M CM34 MEE 799001212004 TF041 MANUAL BATTERY CAUTION MEN TF041 LABEL MODEL 5M MIT AC E TF041 RIBBON 11CM 300M PT800 MEN 523450283097 TF041 TH HDD DRIVE 120GB MK 1 MEN 7961 7961 7961 7961 7961 7961 7961 7961 7961 7961 7961 4111 6060007 6060008 6060009 6060010 6060011 6060012 4960029 5030029 5030003 5050051 5050055 6000065 TF041 SPONGE PORON SR S 32 a MEN TF041 SPONGE PORON H32 70 10 MEN TF041 SPONGE PORON H32 90 10 MEE TF041 SPONGE PORON SR S24P MEI TF041 SPONGE PORON H32 30 10 EN TF041 SPONGE PORON SR S 24P 5 MEN mwacwmeuen 198 M230 N B Maintenance 9 Spare Parts List 4 411116000031 332210000033 271001100301 294011200534 316116000010 242600000572 796115000071 796115000072 796115000073 796115000074 796115000006 796115010004 796115020001 796115020002 796115020003 796115020004 796115020005 796115020009 796115020010 796115020011 796115030002 796115030026 796115050001 796115050004 796115050005 Part Number Description Location s TF041 TH PCB PWA M230 KBD LED ROL TF041 LABEL 4 3MM HI TEMP 260 TF041 DOOR PCMCIA 200MP ASSY TF041 DOOR BATT 200MP ASSY M2 TF041 DOOR CD ROM 200MP ASSY TF041 DOOR HDD 200MP ASSY M22 TF041 ASSY SIM CARD MOUDLE M2 mercem
81. 6 TXOUTI bj Transmission Data of Pixels 1 Negative 57 TXOUTI fF Transmission Data of Pixels 1 Positive 5 GROUND 59 TXOUT2 Transmission Data of Pixels 2 Negative 60 TXOUT2 fF Transmission Data of Pixels 2 Positive ato ine oo iat orn aio ine ort signal amp More ims Downloaded from LpManual com Manuals lt M230 N B Maintenance gt I O Board 120 pin Connector Mitac 291000011229 3 Continue to the previous page 0 S eversum ton or EN AN Commision IET TEL LU C E gt am 1 1 p 1 1 poo o gt Z I I Transmission Data of Pixels 0 Positive T IT Transmission Data of Pixels 1 Negative Transmission Data of Pixels 1 Positive T IB GG B0 BO 1 TB2 Transmission Data of Pixels 2 Negative Transmission Data of Pixels 2 Positive Sampling Clock Positive Sampling Clock Positive Transmission Data of Pixels 0 Negative 120 PEE Q Ojo 2 Download
82. 72105222411 272105220404 041 22 50V 10 272101224702 Downloaded from LpManual com Manuals Part Number Description Location s TFO41 TH CAP 0 1U CR 10V 10 MEE TF041 TH CAP 0 1U 16V 480 2 MEINE TF041 TH CAP 150U TPC 6 3V 2 MEN 041 220 CR 10V 1206 EE TF041 TH CAP 10U 6 3V 10 08 EINE mecum n sen 07 A NENNEN C61 C612 C65 PC29 PC30 C377 C378 C808 C812 29 TF041 T H CAP 1000P CR 50V 1094 L t P 29 507 508 291 gt 5 537 540 29 29 28810 29500 29500 00 00 00 00 00 00 00 00 00 00 00 288100561004 288100054035 294011200536 294011200502 288105556002 288104148020 28810 099015 541004 010218 010206 010630 000905 011229 141004 012806 025038 018402 011227 251504 020233 255201 TF041 TH CAP 39P 50V 7 1096 04 TH DIODE BATS4ALTI COM gt T H FUSE FAST 24 63VDC TH FUSE NORMAL 6 5A 32 i gt le m ux c E E lt TH CON HDR FM 3P 2 2 0M TF041 TH CON MINI IEEE1394B R TF041 TH CON HDR FM 60P 2 0 8 TF041 TH CON FPC FFC 10P 1 MM TF041 TH CON HDR 14P 2 0 8MM TF041 TH CON HDR2S5P 2 FM 8M TF041 TH CON HDRA2P 2 0 8MM TF041 TL CON WFR MA I2P 1 25M TF041 TH CON IC CARD 75P 2 FM TF041 TL CON HDR MA 2P 1 1 25 TF041 TH CON MINI PCI EXPRESS Part Number 272102473404 2721053
83. 90401 272105180308 288100603003 oe p F2 PF501 lt 2 J13 203 M230 N B Maintenance 9 Spare Parts List 9 291000921202 297150100015 291000612036 291000150815 291000151219 273000500189 273000990296 272075102419 272075102424 272075101408 272043226507 272075152405 272075100404 272431336001 272003105402 288100540006 288105232007 288100034012 295000010243 273000990377 Pat Number TaN RAR TF041 T H CON FPC FFC 12P 0 5M TF041 T H CHOKE COIL 900HM 100 L18 L22 TF041 T H INDUCT OR 10UH 20 273000500184 TF041 TH FERRITE CHIP 6000HM L503 L505 TF041 T H CAP 1000P CR 50V 10 TF041 TH CAP 0 1U CR 50V 10 271071403101 TFO41 TH RES402K 1 16W 1 271061000003 TFO41 TH RESO TF041 TH RES7 5K 1 16W 195 06 041 510 1 16W 196 TF041 TH RESM 1 16W 196 040 TF041 TH RESI00 1 16W 1 TF041 TH CAP 22U 25V 20 TF041 T H CAP 1500P CR 50V 10 TF041 TH CAP 10P 50 10 0 TF041 T H CAP 330uF 6 3V 7343 TF041 TH CAP IU 25 10 288105252004 271072300331 TFO41 TH RES300K 1 10W 5 Downloaded from LpManual com Manuals 273000990374 273000990375 288227002024 TF041 TH TRA 288207832004 TFO41 TH TRA 288207821006 288200144029 288206679005 041 288204835008 TEO41 TH TRA 288204832002 TFO41 TH TRA 288203415002 TFO41 TH TRA 519 271071752
84. ACZ SDIN 2 0 AC 97 Intel High Definition Audio Serial Data In 2 0 Serial TDM data inputs from the three codecs The serial input is single pumped for a bit rate of 24 Mb s for Intel High Definition Audio These signals have integrated pulldown resistors which are always enabled VccRTC 3 3 V can drop to 2 0 V min in G3 state supply for the RTC well 1 pin This power is not expected to be shut off unless the RTC battery is removed or completely drained Note Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low Clearing CMOS in an Intel amp ICH7 based platform can be done by using a jumper on RTCRST or GPL LPC Interface Signals VccUSBPLL 1 5 V supply for core well logic 1 pin This signal is used for the USB PLL This power may be shut off in S3 S4 S5 or G3 states Must be powered even if USB not used VccDMIPLL 1 5 V supply for core well logic 1 pins This signal is used for the DMI PLL This power may be shut off in S3 S4 S5 or G3 states VecSATAPLL 1 5 V supply for core well logic 1 pins This signal is used for the SATA PLL This power may be shut off in S3 S4 S5 or G3 states Must be powered even if SATA not used V CPU IO Powered by the same supply as the processor I O voltage 3 pins This supply is used to drive the processor interface signals listed in Process Interface Signals Name Type Description LAD 3
85. Address Strobe The processor bus owner asserts HADS to indicate the first of two cycles of a request phase The G MCH can assert this signal for snoop cycles and interrupt messages HBNR Lo GTL Block Next Request is used to block the current request bus owner from issuing new requests This signal is used to dynamically control the processor bus pipeline depth HBPRI GTL Priority Agent Bus Request The G MCH is the only Priority Agent on the processor bus It asserts this signal to obtain the ownership of the address bus This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the HLOCK signal was asserted HBREQO vo GTL Bus Request 0 The G MCH pulls the processor s bus HBREQO signal low during HCPURST The processor samples this signal on the active toinactive transition of HCPURST The minimum setup time for this signal is 4 HCLKs The minimum hold time is 2 HCLKs and the maximum hold time is 20 HCLKs HBREQO should be tristated after the hold time requirement has been satisfied HCPURST GTL CPU Reset The HCPURST pin is an output from the G MCH The G MCH asserts HCPURST while RSTIN is asserted and for approximately 1 ms after RSTIN is de asserted The HCPURST allows the processors to begin execution in a known state Note that the Intel ICH7 must provide processo
86. Bus Port 1 0 Differential USBPON These differential pairs are used to transmit Data Address Command USBPIP signals for ports 0 and 1 These ports can be routed to UHCI USBPIN controller 1 or the EHCI controller NOTE No external resistors are required on these signals The Intel ICH7 integrates 15 pull downs and provides an output driver impedance of 45 which requires no external series resistor USBP2P Lo Universal Serial Bus Port 3 2 Differential USBP2N These differential pairs are used to transmit data address command USBP3P signals for ports 2 and 3 These ports can be routed to UHCI USBP3N controller 2 or the EHCI controller NOTE No external resistors are required on these signals The ICH7 integrates 15 KO pull downs and provides an output driver impedance of 45 which requires no external series resistor USBP4P Lo Universal Serial Bus Port 5 4 Differential USBPAN These differential pairs are used to transmit Data Address Command USBPSP signals for ports 4 and 5 These ports can be routed to UHCI USBPSN controller 3 or the EHCI controller NOTE No external resistors are required on these signals The ICH7 integrates 15 pull downs and provides an output driver impedance of 45 which requires no external series resistor USBP6P Lo Universal Serial Bus Port 7 6 Differential USBP6N These differential pairs are used to transmit Data Address Command USBP7P signals for ports 6 and 7 These ports can be r
87. C Far Number PR531 PR532 PR571 PR562 PR563 TF041 TH RES 12 1K 1 16W 196 PR564 TF041 TH RESISK 1 16W 196 PR567 PR576 PR520 PR525 PR582 PR586 PR588 PR594 TF041 TH IC SCI485 P WM T SSOP PUI PUS03 TF041 T H TRANS SI4800DY N MOS PU3 PU504 Q2 i Aef 0502 0506 Part Number Description Location 286300480001 286302951020 286300809025 286300055003 288200144030 288200069011 288200645001 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 611103305 621103306 621472306 071228306 0614713 06147231 0615601 oo 0613943 06122131 061632 061270 ml A a ay wv 061540 06127210 0618223 n 061202 061473 06125110 061221 TF04 TF041 TH IC SC480 P WM DDR2 ML PU507 TF041 TH IC LP2951ACM NOPB Vo PU509 TF041 TH IC ADM809SART REEL7 PU510 TH ICITC55 3 3V250mA R PUSII TF041 TH TRANSDDTCIAATKA N M MEE TF041 TH TRANS BCP69 PNP SOT 010 03 TF041 TH TRANSFDC645N NL 5 5 0519 0521 TF041 TH RP 10K 4 8P 1 l6W 501 TF041 TH RP 10K 8 10P 1 32W RP502 TF04 TF04 TF04 TF04 TF04 TF04 TF04 TF04 TF04 TF04 TF041 TH RP 4 7K 8 10P 1 32W TF041 TH RES2 2 1 16W 5 R2 R772 R866 TH RES470 1 16 5 RI LRI79 TF041 TH RES 56 2 1 16W 1 04 R35 R36 R37 R39 TH RES390K 1 16W 5 TH RES220 1 16W 5 TH RES6 34K 1 16W 196 TH RES27 4 1 16W 1 TH RES54 9
88. CIE j This signal is multiplexed with EXP TXPI5 SDVOB GREEN Serial Digital Video Channel B Green Complement PCIE This signal is multiplexed with EXP TXNI4 SDVOB GREEN Serial Digital Video Channel B Green PCIE _ This signal is multiplexed with 14 SDVOB BLUE Serial Digital Video Channel B Blue Complement PCIE This signal is multiplexed with EXP TXNI13 SDVOB_BLUE Serial Digital Video Channel B Blue PCIE j This signal is multiplexed with EXP TXP13 SDVOC RED Serial Digital Video Channel C Red Complement Channel SDVOB ALPHA PCIE Alpha Complement This signal is multiplexed with EXP TXNII SDVOC_RED Serial Digital Video Channel C Red Complement Channel SDVOB ALPHA PCIE Alpha This signal is multiplexed with 11 SDVOC_GREEN Serial Digital Video Channel C Green Complement PCIE This signal is multiplexed with EXP TXNIO SDVOC GREEN Serial Digital Video Channel Green PCIE This signal is multiplexed with _ 10 SDVOC BLUE Serial Digital Video Channel C Blue Complement PCIE This signal is multiplexed with EXP TXNO9 SDVOC_BLUE Serial Digital Video Channel C Blue PCIE This signal is multiplexed with EXP TXP9 SDVOC CLK Serial Digital Video Channel C Clock Complement PCIE This signal is multiplexed with EXP TXNS8 SDVOC_CLK Serial Digital Video Channel C Clock PCIE This signal is multiplexed with EXP 8 SDVO TVC
89. Developer s Manual and AP 485 For termination requirements please contact your Intel representative GTLREF GTLREF determines the signal reference level for AGTL input pins GTLREF should be set at 2 3 GTLREF is used by the AGTL receivers to determine if a signal is a logical 0 or logical I Plese contact your Intel representative for more information regarding GTLREF implementation HIT HITM HIT Snoop Hit and Hit Modified convey transaction snoop operation results Either system bus agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor system bus This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET Downloaded from LpManual com Manuals CPU Pin Description Continued Signal Name Type Description IGNNE I IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a
90. H7 This signal has an integrated pull up resistor EE_DOUT EEPROM Data Transfers data from the ICH7 to the EEPROM EE CS EEPROM Chip Select Chip select signal to the EEPROM Interrupt Signals Name Type Description SERIRQ Serial Interrupt Request This pin implements the serial interrupt protocol PIRQ D A VOD PCI Interrupt Requests In non APIC mode the PIRQx signals can be routed to interrupts 3 4 5 6 7 9 10 11 12 14 or 15 as described in the Interrupt Steering section Each PIRQx line has a separate Route Control register In APIC mode these signals are connected to the internal I O APIC in the following fashion PIRQA is connected to IRQ16 PIRQB to IRQ17 PIRQC to IRQ18 and PIRQD to 12 019 This frees the legacy interrupts PIRQ H E GPIO 5 2 VOD PCI Interrupt Requests In non APIC mode the PIRQx signals can be routed to interrupts 3 4 5 6 7 9 10 11 12 14 or 15 as described in the Interrupt Steering section Each PIRQx line has a separate Route Control register In APIC mode these signals are connected to the internal I O APIC in the following fashion PIRQE is connected to IRQ20 PIRQF to IRQ21 PIRQG to IRQ22 and PIRQH to IRQ23 This frees the legacy interrupts If not needed for interrupts these signals can be used as GPIO USB Interface Signals Name Type Description USBPOP Lo Universal Serial
91. HoPT dio and Optical Fiber Device detect Li pese 2 1 1 EL Downloaded from LpManual com Manuals 62 M230 N B Maintenance 1 2 1 19 Internal Connector Definition gt LCD Connector MiTAC 291000005017 1 S0 State 83 State _ x 3 2 2 2 8 8 NINI S j x Downloaded from LpManual com Manuals 63 M230 N B Maintenance Continue to the previous page 83 State ds 5 E 5 i 6 SBP7 29 31 33 DTR CD M DATA 0 GND 40 TBO 1 5 E z THOS gt gt N 5V 5V VMATN 3V 3V 3V 43 V 43V 43V CONG Data terminal ready signal For SM bus GPIO controller For SM bus GPIO controller 2 B 41 0 42 43 4 1 z 2 2 ya Transmission Data of Pixels 0 Negative BGG 46 TB2 Eo 47 ITB2 GND
92. I TRDY PCI IRDYs CCLK 798 d PCI PAR PCI FRAMEZ PCI TRDY PCI CAD 0 31 A B CCBEH 0 3 9 p 3 77 E 31 A B _ PCI_STOP PCI DEVSELA gt Fu A B_CFRAME A B_CTRDY A B_CIRDY A B_CSTOP 0520 lt PCI AD28 R747 0 5 A B_CPAR A B_CDEVSEL A B_CBLOCK e PCI PERRA PCI TYCO 1565338 A B_CPERR A B_SERR PCI REQ 0 PCI GNT40 4 A B_CSTSCHG A B_CCLKRUN eT PCI_RESET PCI PME M Ir A B_CINT A B_CRST CAUDIO M PWROK R734 0 A B_CCD 1 2 A B_CVS 1 2 S R722 R700 SERIRQ PCL_CLKRUN PCI LOCK 0 A B_RSVD D2 A B_RSVD D14 A B_RSVD A18 p Downloaded from LpManual com Manuals 195 M230 N B Maintenance 9 Spare Parts List 1 791901160015 796115030056 796115010024 796115000007 796115000008 796115000009 796115000010 796115010007 796115030022 796115050010 796115050025 796115060023 796115090003 796115090004 796115020020 796115050032 796115050087 342115000001 796115074004 796115050052 796115060109 796115070055 796115070079 796119070014 796115070071 Part Number ___
93. ICH7 SKUs gt Integrated IDE Controller ndependent timing of up to two drives Ultra ATA 100 66 33 BMIDE and PIO modes Tri state modes to enable swap bay USB2 0 Downloaded from LpManual com Manuals 47 M230 N B Maintenance Includes four UHCI host controllers that support eight external ports Includes one EHCI high speed USB 2 0 host controller that supports all eight ports Includes one USB 2 0 High speed debug port Supports wake up from sleeping states 51 55 Supports legacy keyboard mouse software gt Intel High Definition Audio Interface PCI Express endpoint Independent Bus Master logic for eight general purpose streams four input and four output Support three external Codecs Supports variable length stream slots Supports multichannel 32 bit sample depth 92 KHz sample rate output Provides mic array support Allows for non 48 KHz sampling output Support for ACPI device states NEW Docking support NEW Low voltage mode 48 Downloaded from LpManual com Manuals M230 N B Maintenance gt Interrupt Controller Support up to eight PCI interrupt pins Supports PCI 2 3 message signaled interrupts Two cascaded 82C59 with 15 interrupts ntegrated I O APIC capability with 24 interrupts Supports processor system bus interrupt delivery gt 1 05 V operation with 1 5 V and 3 3 V I O 5V tolerant buffers on IDE PCI USB over current and legacy signals Timers Based on 82C
94. If the PWROK signal is sampled high this indicates that the system is strapped to the No Reboot mode ICH7 will disable the TCO Timer system reboot feature The status of this strap is readable via the NO REBOOT bit Chipset Config Registers Offset 34 10h bit 5 INTVRMEN Integrated Always Enables integrated 50 1 05 VRM when VecSusl 05 sampled high VRM Enable Disable EE CS Reserved This signal has a weak internal pull down NOTE This signal should not be pulled high EE Reserved This signal has a weak internal pull up NOTE This signal should not be pulled low GNT5 Boot BIOS Rising Edge of This field determines the destination of accesses GPIO17 Destination PWROK to the BIOS memory range Signals have weak GNT4 Selection internal pull ups Also controllable via Boot GPIO48 BIOS Destination bit Chipset Config Registers Offset 3410h bit 11 10 5 is MSB 01 SPI 10 PCI 11 LPC Name Type Description DMI 0 3 TXP Direct Media Interface Differential Transmit Pair 0 3 DMI 0 3 TXN DMI 0 3 RXP I Direct Media Interface Differential Receive Pair 0 3 DMI 0 3 RXN DMI ZCOMP Impedance Compensation Input Determines DMI input impedance DMI IRCOMP I Impedance Compensation Compensation Output Determines DMI output impedance and bias current Downloaded from LpManual com Manuals 148 5 3 Intel ICH7 M South Bridge 11 Miscellaneous Signals M230 N B
95. Inversion are source synchronous and indicate the polarity of the D 63 0 signals DINV 3 0 signals are activated when the data on the data bus is inverted The bus agent will invert the data bus signals if more than half the bits within the covered group would change level in the next cycle DINV 3 0 Assignment To Data Bus Bus Signal Data Bus Signals DINV 3 D 63 48 DINV 2 D 47 32 DINV 1 D 31 16 DINV 0 D 15 0 DPRSTP I DPRSTP when asserted on the platform causes the processor to transition from the Deep Sleep State to the Deeper Sleep Stated In order to return to the Deep Sleep State DPRSTP must be deasserted DPRSTP is driven by the Intel ICH7M chipset DPSLP I DPSLP when asserted on the platform causes the processor to transition from the Sleep state to the Deep Sleep state In order to return to the Sleep state DPSLP must be deasserted DPSLP is driven by the ICH7M chipset DRDY DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of both processor system bus agents DSTBN 3 0 VO Data strobe used to latch in D 63 0 Signals Associated Strobe D 15 0 DINV O DSTBN 0 D 31 16 DINV 1 DSTBN 1 D 47 32 DINV 2 DSTBN 2 D 63 48 DINV 3 DSTBN 3 Downloaded
96. K Card Bus detect 1 Cars Bus voltage sense and Card Bus detect 2 Card Bus lock B_CSTOP B_CDEVSEL B_CTRDY Card Bus device select Card Bus target ready Card Bus clock Switched output that delivers 0 V 3 3 V 5 V or high impedance to card B_CSTSCHG 44 41 35 32 23 21 19 14 12 3 B CCD24 36 38 39 6 RSVD A18 Switched output that delivers 0 V 3 3 V 5 V 12 V or high impedance to card po p 7 de amp W 2 9 BCFRAME P CadBucydefam 26 Laer I po wm __ JJ E s y Downloaded from LpManual com Manuals 69 M230 N B Maintenance Continue to the previous page S3 State 84 State fam 46 ACAD J Jp CeBeseddessida bus ACAD Cart Bas address databus ACAD art Bs address databus e ACAD J _ art Bus address databus ACAD Cart Bus address databus 385 ACAD Cart Bus address databus 137 ACAD CeBeseddessidat bus 33 ACAD Cart Bus address databus A CADIO fF Card Bus address data bus WO Card address data bus
97. K B or Touch Pad T P Test Error 2 1 0 0 175 5 7 Hard Disk Drive Tes EDU iion EYE EX SRL 177 8 8 Erron T 179 S9 USB Port nu nes esis 181 8 10 Audio Test Mer 185 SILLAN Test err 188 9 12 1394B Test RTT em 190 8 13 Mini Express Wireless Socket Test 7 2 212141422 192 Downloaded from LpManual com Manuals M230 N B Maintenance Contents 8 14 PCMCIA Socket Test Error 194 9 Spare Parts Im 196 10 System Exploded Q 212 11 Reference Material A teer OR Neon o pn e haee 219 Downloaded from LpManual com Manuals M230 N B Maintenance 1 Hardware Engineering Specification 1 1 Introduction 1 1 1 General Description This document describes the system hardware engineering specification for M230 portable notebook computer system The M230 notebook computer is a new mainstream high performance thin and light notebook in the MiTAC notebook family 1 1 2 System Overview Marketing Requirement The new M230 is ruggedized notebook high portability industrial computer It can be used in the vehicle field and office The notebook computer also can conne
98. L still operating Processors in this state will not recognize snoops or interrupts The processor will recognize only assertion of the RESET signal deassertion of SLP and removal of the BCLK input while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core units DPSLP is asserted while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state SMI SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the deassertion of RESET the processor will tristate its outputs STPCLK STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the system bus and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus
99. LKI I Serial Digital Video TV OUT Synchronization Clock N PCIE Complement This signal is multiplexed with EXP RXNIS SDVO TVCLKI I Serial Digital Video TV OUT Synchronization Clock N PCIE __ This signal is multiplexed with EXP RXPI5 SDVOB INT I Serial Digital Video Input Interrupt Complement PCIE This signal is multiplexed with EXP RXNIA Downloaded from LpManual com Manuals Name Voltage Description VCC 1 5V Core Power VTT 1 2V Processor System Bus Power VCC EXP 1 5V PCI Express and DMI Power VCCSM 1 8V System Memory Power 2 2 5V 2 5V COMS Power VCCA EXPPL 1 5V PCI Express PLL Analog Power L VCCA DPLLA 1 5V Display PLL A Analog Power GMCH ONLY VCCA DPLLB 1 5V Display PLL B Analog Power GMCH ONLY VCCA HPLL 1 5V Host PLL Analog Power VCCA SMPLL 1 5V System Memory PLL Analog Power VCCA DAC 2 5V Display DAC Analog Power VSS OV Ground VSSA_DAC OV Ground 138 5 3 Intel ICH7 M South Bridge 1 PCI Interface Signals M230 N B Maintenance Signal Name Type Description PCI Interface Signals Continued IRDY vo Initiator Ready IRDY indicates the ICH7 s ability as an initiator to complete the current data phase of the transaction It is used in conjunction with TRDY A data phase is completed on any clock both IRDY and TRDY are sampled asserted During a write IRDY indicates the ICH7 has valid data present on AD 31 0 During a read it indicates the
100. M North Bridge 6 M230 N B Maintenance Intel amp Serial DVO SDVO Interface Intel amp 82945G GMCH Only Intel Serial DVO SDVO Interface Intel 82945G GMCH Only Continued Signal Name Voltage Description SDVOB_INT I Serial Digital Video Input Interrupt PCIE __ This signal is multiplexed with EXP_RXP14 SDVOC_INT I Serial Digital Video Input Interrupt Complement PCIE This signal is multiplexed with EXP_RXN10 SDVOC_INT I Serial Digital Video Input Interrupt PCIE signal is multiplexed with EXP_RXP10 SDVO_STALL I Serial Digital Video Filed Stall Complement PCIE _ This signal is multiplexed with EXP_RXN13 SDVO_STALL I Serial Digital Video Filed Stall PCIE _ This signal is multiplexed with EXP_RXP13 SDVO_CTRLCL Serial Digital Video Device Control Clock K COD SDVO CTRLDA vO Serial Digital Video Device Control Data TA COD Power and Ground Signal Name Type Description SDVOB CLK Serial Digital Video Channel B Clock Complement PCIE This signal is multiplexed with EXP TXNI2 SDVOB CLK Serial Digital Video Channel Clock Clock PCIE j This signal is multiplexed with EXP 12 SDVOB RED Serial Digital Video Channel C Red Complement PCIE This signal is multiplexed with EXP TXNI5 SDVOB_RED Serial Digital Video Channel C Red P
101. Maintenance Name Type Description INTVRMEN I Internal Voltage Regulator Enable This signal enables the internal 1 05 V Suspend regulator when connected to VccRTC When connected to Vss the internal regulator is disabled SPKR Speaker The SPKR signal is the output of counter 2 and is internally ANDed with Port 61h bit 1 to provide Speaker Data Enable This signal drives an external speaker driver device which in turn drives the system speaker Upon PLTRST its output state is 0 NOTE SPKR is sampled at the rising edge of PWROK as a functional strap See Function Straps for more details There is a weak integrated pull down resistor on SPKR pin RTCRST I RTC Reset When asserted this signal resets register bits in the RTC well NOTES 1 Unless CMOS is being cleared only to be done in the G3 power state the RTCRST input must always be high when all other RTC power planes are on 2 In the case where the RTC battery is dead or missing on the platform the RTCRST pin must rise before the RSMRST pin TPO I Test Point 0 This signal must have an external pull up to VecSus3_3 TP1 Test Point 1 Route signal to a test point TP2 Test Point 2 Route signal to a test point TP3 Vo Test Point 3 Route signal to a test point Real Time Clock Interface Name Type Description RTCXI Special Crystal Input 1 This signal is connected to the 32 768 KHz crystal If no exter
102. Maintenance PCI Interface Signals Continued Serial ATA Interface Signals Signal Name Type Description PERR vo Parity Error An external PCI device drives PERR when it receives data that has a parity error The ICH7 drives PERR when it detects a parity error The ICH7 can either generate an NMI or SMI upon detecting a parity error either detected internally or reported via the PERR signal 0 3 PCI Requests 4 The ICH7 supports up to 6 masters on the PCI bus The and GPIO22 5 pins can instead be used as GPIO 5 GNT 0 3 PCI Grants GNT 4 The ICH7 supports up to 6 masters on the PCI bus The GNT4 and GPIO48 GNT5 pins can instead be used as a GPIO Pull up resistors are not GNT 5 required on these signals If pull ups are used they should be tied to GPIO17 the Vcc3 3 power rail GNT5 GPIO17 has an internal pull up PCICLK I NOTE PCI Clock This is a 33 MHz clock PCICLK provides timing for all transactions on the PCI Bus PCIRST PCI Reset This is the Secondary PCI Bus reset signal It is a logical OR of the primary interface PLTRST signal and the state of the Secondary Bus Reset bit of the Bridge Control register D30 F0 3Eh bit 6 PLOCK vo PCI Lock This signal indicates an exclusive bus operation and may require multiple transactions to complete The ICH7 as
103. OR chain testing DDR2 DRAM Reference and Compensation Signal Name Type Description SRCOMP 1 0 vO System Memory RCOMP SOCOMP 1 0 vO DDR2 On Die DRAM Over Current Detection OCD Driver A Compensation SMVREF 1 0 I SDRAM Reference Voltage A These signals are reference voltage inputs for each SDQ x SDM x SDQS x and SDQS x input signals Direct Media Interface DMI Signal Name Type Description DMI RXP 3 0 Io Direct Media Interface DMI RXN 3 0 DMI These signals are receive differential pairs Rx DMI TXP 3 0 Direct Media Interface DMI TXN 3 0 DMI These signals are transmit differential pairs Tx Signal Name Type Description HCLKP I Differential Host Clock In HCLKN HCSL pins receive a differential host clock from the external clock synthesizer This clock is used by all of the G MCH logic that is in the Host clock domain Memory domain clocks are also derived from this source GCLKP I Differential PCI Express Clock In GCLKN HCSL pins receive a differential 100 MHz Serial Reference clock from the external clock synthesizer This clock is used to generate the clocks necessary for the support of PCI Express DREFCLKN I Display PLL Differential Clock In DREFCLKP HCSL RSTIN I Reset In HVIN When asserted this signal will asynchronously reset the G MCH logic This signal is connected to the PCIRST outpu
104. On default Pin Signal name EM mm State S3 State S4 State Purpose mE Poroy _ Eu e Ei Not Connect Lm 0 1 1 jPssedDignosis 2 0 J 3 mro O Ad es2 34 werpa 0 jOhipSelctsigna IDE_PDCS 1 Chip Setectsignat CDACTP Led driver 5 _____ Svoltspower 5 5 dS volts power 5 5 ______ USBPI FU Differential Data Minus USBPI us ifferential Data Plus 36 38 EM NEM EM a __ s EM EM 46 _ 48 EM Downloaded from LpManual com Manuals M230 N B Maintenance gt Speaker Left 2 pin Connector HIROSE MiTAC 291000020202 Power On default Pins Signal Direction S0 State S3State SA State Purpose or 2 woh ine outta speaker tet gt PS2 Board 6 pin Connector MiTAC 291000010630 as ate Cs koma iar Bate Downloaded from LpManual com Manuals 79 M230 N B Maintenance gt X Bay 84 pin Connector Mitac 291000018402 1 Power On default Pin Signal name Direction 50 State 1 3 5 7 9 11 13 15 17 19 21 23 29 31 33 35 37 5V tSVS 3VS 30 32 34 36 38 0 2 44 46
105. Pad Connector 1500 gt J501 Switch Board to MB Connector 1501 0 125 Downloaded from LpManual com Manuals M230 N B Maintenance 4 Definition amp Location of Major Components 4 1 Mother Board Side A gt Downloaded from LpManual com Manuals gt U U gt U U gt U512 System BIOS 513 Intel Yonah CPU Processor J520 PCMCIA amp CardBus Controller 521 Intel 945GM North Bridge J522 Intel ICH7 M South Bridge 126 M230 N B Maintenance 4 Definition amp Location of Major Components 4 1 Mother Board Side B gt 4 Super I O Controller gt 05 5789 Giga LAN Controller gt U6 TI 1394B PHY U9 TI 1394B HOST a 013 51 gt 013 H8S 2140 Keyboard Controller 127 Downloaded from LpManual com Manuals 5 Pin Descriptions of Major Components 5 1 Intel Yonah Processor CPU 1 CPU Pin Description M230 N B Maintenance Signal Name Type Description CPU Pin Description Continued A 31 3 Lo A 31 Address define a 2 32 byte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction Must connect the appropriate pins of both agents on the Intel Core TM Duo processor and the Intel Core TM Solo processor FSB A 31 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 Address signa
106. QS O 7 R250 DDR 5 0 3 DDRA B 0 7 Yes Toe If your system host bus clock running at 400 533 667 MHz then make sure that SO DIMM module meet require of PC3200 PC4200 PC5400 R242 DDR ODT O0 3 DDR DQ 0 63 R245 DDRA B CAS DDRA B 0 7 R299 DDRA B_RAS DDRA B BS 0 2 R304 DDRA B WEZ PM_EXTTS 0 1 R310 Replace Motherboard Replace the faulty DDR2 SO DIMM module 173 Downloaded from LpManual com Manuals M230 N B Maintenance 8 5 Memory Test Error 2 Extend DDR2 SO DIMM is test error or system hangs up 0 9VS R240 R250 56 DDRA B BS4 0 2 DDRA B_CAS DDRA B_RAS DDRA B_WE DDRA B MA 0 13 DDR_CKE 0 3 DDR_CS 0 3 DDR_ODT 0 3 DDRA B_DQS 0 7 DDRA B_DQS 0 7 DDRA B_MD 0 7 DDRA B_MA 0 13 DDR_A B_DQ 0 63 DDRA_BS 0 2 DDRA_CAS DDRA_RAS DDRA_WE DDRA MA 0 13 DDR_CKE 0 3 DDR_CS 0 3 DDR_ODT 0 3 DQS 0 7 DDRA_DQS 0 7 DDRA MDJ 0 7 DDRA MA 0 13 DDR A DQJ0 63 M CLK DDR 0 1 M CLK DDR Z 0 1 PM_EXTTS 0 J505 Pis v 0 9VREF DDR2_VREF R205 J504 A CLK DDR 0 3 M CLK DDRZ 0 3 PM_EXTTS 0 1 a SMBDATA SMBCLK 1 8V o U521 North Bridge SMBDATA 5 Intel 945GM SMBCLK SMBCLK SMBDATA Downloaded from LpManual com Manuals DDRB_BS 0 2 DDRB CASA
107. Quad Pumped Signal Groups Data Group DSTBN DSTBP DINV D 15 0 0 0 D 31 16 1 1 0 47 32 2 2 D 63 48 3 3 Furthermore the DINV pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DINV signal When the DINV signal is active the corresponding data group is inverted and therefore sampled active high CPU Pin Description Continued DBR DBR Data Bus Reset is used only in processor systems where no debug port is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect DBR is not a processor signal DBSY T O DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on both processor system bus agents DEFER DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or Input Output agent This signal must connect the appropriate pins of both processor system bus agents Signal Name Type Description DINV 3 0 vO DINV 3 0 Data Bus
108. R See 3 user es tow is USB Drei Data Mis gt Antenna Switch Connector MiTAC 297150100015 t passes antenna signal from system to docking for using vehicle dock Downloaded from LpManual com Manuals 57 M230 N B Maintenance gt Docking Port Connector MiTAC 796115000001 5 7 10 p pock R 1 Ring indicator 0 O u 0 SPIDFOUTSiml PUSBOCHS 1 USBovercurrentto USBHUB Low o _ pi x I c _ Ww e Ww USB Differential Data Plus m 3V_POGO Out 3 3 Out 3 3V Out 3 3V ut 3 3V 43 3V POWER low 10 1718 _ 5V_POGO 5V POWER POGO_DOCK_IN P PWRON CARKEY leu ________ J r j Microphone Input Signal bine Out Right Signal Downloaded from LpManual com Manuals 58 M230 N B Maintenance gt Serial Port Connector MiTAC 331040009005 Power On default Direction 50 State S3 State 54 State Purpose Oo d o 65 Downloaded from LpManual com Manuals CoMIDCD IN ____ IN IN Power On default Direction COMI Carrier detector signal COMI Received data signal COMA Transmitted data signal Shield ground Ground COMI Data set ready signal COMI Request to send signal COMI Clear to send signal COMI Ring indicator signal
109. R 0 TMR 1 Multiple interrupt sources for each channel Timer Connection Five input pins and four output pins all of which can be designated for phase inversion An edge detection circuit is connected to the input pins simplifying signal input detection TMR X can be used for PWM input signal decoding Downloaded from LpManual com Manuals 25 M230 N B Maintenance e X can be used for clamp waveform generation Watchdog Timer WDT Selectable from eight WDT 0 or 16 WDT 1 counter input clocks Switchable between watchdog timer mode and interval timer mode gt Serial Communication Interface SCI amp IrDA Choice of asynchronous or clocked synchronous serial communication mode Full duplex communication capability The on chip baud rate generator allows any bit rate to be selected Choice of LSB first or MSB first transfer except in the case of asynchronous mode 7 bit data Four interrupt sources gt Bus Interface IIC Selection of addressing format or non addressing format Conforms to Philips I2Cbus interface I2Cbus format Two ways of setting slave address I2Cbus format Start and stop conditions generated automatically in master mode I2C bus format Selection of the acknowledge output level in reception I2C bus format 26 Downloaded from LpManual com Manuals M230 N B Maintenance Automatic loading of an acknowledge bit in transmission I2C bus
110. R2 SO DIMM Socket gt 1506 SIM Interface gt 1507 Right Audio Channel Connector J508 Left Audio Channel Connector J509 Switch Board Cable Connector 1506 J507 J508 509 117 Downloaded from LpManual com Manuals M230 N B Maintenance 3 Definition amp Location of Connectors Switches 3 1 Mother Board Side B J18 19 Downloaded from LpManual com Manuals gt J15 a gt 16 gt JAT gt 18 gt J19 gt gt gt PJ3 gt J2 1394b Port IUB EU J3 VO Board Connector J8 LED Board Connector gt 19 COMI amp Giga LAN Board Connector gt J11 USB Port gt J12 gt CD ROM Connector X BAY Connector PC Card Slot CMOS Battery Connector PCI Express Connector SATA HDD Connector MDC Connector Power Jack Secondary Battery Connector Primary Battery Connector 118 M230 N B Maintenance 3 Definition amp Location of Connectors Switches 3 2 I O Board Side A 1502 1504 1505 1501 1500 1506 1503 O m Di gt J500 Parallel Port gt J501 External VGA Connector J507 gt J502 Serial Port J503 External Microphone Jack pin gt 1504 Connector J510 gt J505 RJ45 Connector J506 Line Out Phone Jack gt J507 I O Board to MB Connector gt J508 Modem Jump Wire Connector gt 1510 COM1
111. RIX Internal ___ nmn KEY BD MATRIX Internal Ro KEY BD MATRIX Internal PB3 input and output pins second D poms Jmm PB2 input and output pins Reset CPU P30 HDB0 DO LPC LADO EM 4 command address data input an P31 HDB1 D1 LEC TADI output pins LPC address and data P32 HDB2 D2 LPC 1402 input and output The start ofan LPC cycle or forced termination ofan abnormal LPC cycle LPC frame LPC reset LPC reset Clock LPC clock input pin LPC clock Input and output pin for LPC serialized host interrupts LPC serial host ICH7 M interrupts Nu P34 HDB4 D4 FRAME P35 HDB5 D5 PLT_RST P36 HDB6 D6 PCI H8 CLK N P37 HDB7 D7 SERIRQ Downloaded from LpManual com Manuals P33 HDB3 D3 LPC LAD3 8 87 M230 N B Maintenance 1 3 1 Keyboard Controller GPIO Pin Definition 6 Power On default 50 53 54 Signal name Direction State State State Connect to Description PBI XDBI DOCK IN LSCI output pin Dock in signal input PBO XDBO EXTSMI 7 LSMI output pin SMI output pin 9 PRUHAO HDD p d HDD GPIO HDD poweronoroff proso ad 94 81 20 A20GATE VO ICH7 M gate used the start of LCLK operation when 95 P82 CLKRUN PCI CLKRUN IO PCI device LCLK is stopped LCLK function used HEP IK po Input pin that controls module shutdown controls LPC module shutdown
112. RTF 3D positional audio Emulation of 26 sound environments to enhance gaming experience 10 band software equalizer Voice cancellation and key shifting in Karaoke mode Enhanced configuration panel and device sensing wizard to improve user experience Content copy protection for S PDIF interface Downloaded from LpManual com Manuals 37 M230 N B Maintenance Power management setting Microphone Acoustic Echo Cancellation AEC and Beam Forming BF technology for voice application Mono Stereo Microphone noise suppression 1 2 1 10 LAN Broadcom BCM5752 Integrates TPM 1 2 security functionality enabling OEMs to offer this high level of PC security as a standard feature Enables TPM ready security platforms for next Microsoft OS Longhorn ntegrates 10 100 1000 BASE T transceiver and media access controller 1 2 1 11 Mobility VGA Chipset ATI 54 5 128 The M54 M32 provides the fastest and most advanced 2D 3D and multimedia graphics performance for notebooks The 54 52 supports Shader Model 3 0 advanced memory interface technology a brand new display controller and a consumer electronics CE quality TV NTSC PAL encoder The M54 is based on PCI Express technology and leverages a brand new graphics architecture Based on 90 nm micron process technology the M54 will deliver a 16 lane PCI Express bus interface and lead free ASIC Features in Detail 38 Downloaded from LpManual com Manuals M230 N B
113. Remove four screws 101 Downloaded from LpManual com Manuals M230 N B Maintenance 5 Disconnect the keyboard cable Figure 2 12 Figure 2 12 Disconnect keyboard cable Reassembly 1 Reconnect the keyboard cable 2 Replace the bracket and secure with four screws 3 Replace the hinge cover and secure with five screws 4 Turn to back then secure the hinge cover with four screws 102 Downloaded from LpManual com Manuals M230 N B Maintenance 2 3 5 Wireless Card Disassembly 1 Remove the battery pack and keyboard Refer to section 2 3 1 and 2 3 4 Disassembly 2 Remove ten screws fastening the LED board cover Figure 2 13 3 Disconnect the LED board s cable Figure 2 14 Figure 2 13 Remove ten screws Figure 2 14 Disconnect the LED board s cable Downloaded from LpManual com Manuals 103 M230 N B Maintenance 5 Disconnect the wireless card s antennae first Then remove two screws and remove the wireless card Figure 2 15 Figure 2 15 Free the wireless card Reassembly 1 Replace the wireless card and secure with two screws Then sure that the antennae fully populated 2 Replace the LED board s cable and then secure the LED board cover with ten screws 4 Replace the keyboard and battery pack Refer to sections 2 3 4 and 2 3 1 Reassembly Downloaded from LpManual com Manuals 104 M230 N B Maintenance 2 3 6 DDR2 Disassembly
114. SERVICE MANUAL FOR M230 BY Sanny Gao Technical Maintenance Department GTK MTC Nov 2006 R01 AITAC Downloaded from LpManual com Manuals M230 N B Maintenance Contents 1 Hardware Engineering iins METTE S 4 1 2 System 10 13 Electrical Characteristic S VK ERE 83 2 System View and Disassembly 91 91 2 2 Tools Introduction 94 2 3 System Disassembly 4 95 3 Definition amp Location of Connectors Switches ccccccccccccccccccccccccccccccccccccccccccssscsccscess 117 31 Mother BMW 117 32 RE UD 8 Kd 119 121 3 4 Touch Screen Board RO ER d UR RU Qu RA OF ESI Ad GAS E dace 122 35 Switch Board cR M 124 4 Definition amp Location of Major Components
115. TF041 FUSE THERMAL FUSE G7F51 449 798961212013 041 5 210 MEN 796115070057 TF041 MYLAR TRANSPARENT 320 2 342114300002 041 PLATE W5L20 ANG 346114300017 TF041 INSULATOR FIBRE BATTERY 346116000001 TF041 INSULATOR L63W 14mm 1 0 346116000002 TF041 INSULATOR L60W26mm T 0 346116000003 TF041 INSULATOR L12W6mm T 0 8 225680620003 TF041 TAPE ADHESIVE DOUBLE FA 346685400025 TF041 INSULATOR FIBRE BATT 3 Downloaded from LpManual com Manuals 798961150012 TF041 END CAP SYSTEM UNIT 14 798961150009 041 BAGANTI STATIC 450 MEN 791911151252 TF041 INT ASSY GBLUETOOTH M 210 M230 N B Maintenance 9 Spare Parts List 16 2720711 2710711 2710711 412150 27107 242600 2730001 361200 242600 365350 411116 313002 316116 242600 422116 05412 291000020611 331840003017 271071241105 51107 03108 00004 00312 00572 50374 03204 222672130002 00566 00009 00004 00097 00001 00572 00005 226683830101 222672130003 Part Number Description Location s 316116000012 272075102424 TFO41 TH CAP 0 10 CR 50V 10 272013106504 TF041 TH CAP 10U 25V 20 1 C1 C2 C5 TF041 TH PCB PWA M230 BLUETOO 41 10 10 10 0603 TF041 TH RES 243 1 16W 1 060 TF041 TH RESI50 1 16W 1 041 510 1 16W 1 286301117114 TF041
116. TH IC AMSI 117 VOL REGUL 041 80 1 16W 5 ROFL Werne Downloaded from LpManual com Manuals Part Number Description Location s 365350000009 LF SOLDER WIRE SN96 5 AG3 0 C EI 211 11 Reference Material Intel Yonah CPU Intel 945GM North Bridge Intel ICH7 M South Bridge Hitachi H8S 2140 KBC M230 Hardware Engineering Specification Explode Views Downloaded from LpManual com Manuals Intel INC Intel INC Intel INC Hitachi INC Technology Corp MITAC Technology Corp MITAC SERVICE MANUAL FOR M230 Sponsoring Editor Ally Yuan Author Sanny Gao Publisher MiTAC Technology Corp Address No 269 Road 2 Export Processing Zone Kunshan P R C Tel 086 512 57367777 Fax 086 512 57385099 First Edition Nov 2006 E mail Ally Yuan mic com tw Web http www mitac com http www mtc mitacservice com Downloaded from LpManual com Manuals
117. _ memi Pw mama 0 5 mw wGaw 7 Downloaded from LpManual com Manuals Part Number 225600000422 346121200009 796121270051 796121270052 41211600000 22180092000 22611420000 22680090000 33211002019 34311150000 34611150000 365350000009 41 27 27 27 27 27 27 27 11500012 07110231 07110431 07113701 071163 0712023 071304 071470 07151131 071563 0717533 072433 072474 2 0 7 3 0 2 5 4 3 3 3 2 2 rr OCEANS TF041 GASKET w1 6 CA27 FT MEN TF041 INVERTER ASSY 15 1 DA MEN Feemmemumwaum TF041 Cu FOIL T 0 05mm 23mmx5 MEN TF041 TH RES 100K 1 16W 5 RO 041 5137 1 16W 1 TF041 TH RES 160K 1 16W 1 TFO41 TH RES2K 1 16W 5 TF041 TH RES301K 1 16W 1 TFO41 TH RES4 32K 1 16W 1 Ro TF041 TH RES 510 1 16W 5 Ris reo RGR neve TFO41 TH RES 75K 1 16W 5 8 TF04 TH RES43 2K 1 10W 1 Ro TF041 TH RESA70K 1 10W 1 196 M230 N B Maintenance 9 Spare Parts List 2 271072822103 272003105402 272010680402
118. al com Manuals M230 N B Maintenance 2 3 12 I O Board Disassembly 1 Remove the battery HDD CD ROM keyboard wireless card DDR2 LCD assembly and system board Refer to sections 2 3 1 2 3 7 2 3 11 Disassembly 2 Remove three screws Figure 2 33 3 Disconnect modem s cable then free the I O board Figure 2 34 Figure 2 33 Remove three screws Figure 2 34 Free the I O board Reassembly 1 Replace the modem card back into the system board and secure with two screws 2 Replace the system board LCD assembly DDR2 wireless card keyboard CD ROM HDD and battery pack Refer to previous sections Reassembly 115 Downloaded from LpManual com Manuals M230 N B Maintenance 2 3 13 Modem Card Disassembly 1 Remove the battery hard disk drive CD ROM keyboard wireless card DDR2 LCD assembly system board and board Refer to sections 2 3 1 2 3 7 2 3 11 and 2 3 12 Disassembly 2 Remove two screws then free the modem card Figure 2 35 Figure 2 35 Remove the modem card Reassembly 1 Replace the modem card back into the system board and secure with two screws 2 Replace the system board LCD assembly DDR2 wireless card keyboard CD ROM HDD and battery pack Refer to previous section Reassembly Downloaded from LpManual com Manuals 116 M230 N B Maintenance 3 Definition amp Location of Connectors Switches 3 1 Mother Board Side A POGO J504 J505 DD
119. al pull up resistor is required SMBALERT I SMBus Alert GPIO11 This signal is used to wake the system or generate SMI If not used for SMBALERT it can be used as a GPIO Downloaded from LpManual com Manuals 146 5 3 Intel ICH7 M South Bridge 9 M230 N B Maintenance AC 97 Intel High Definition Auto Link Signals Name Type Description Power and Ground Signals ACZ_RST AC 97 Intel High Definition Audio Reset Master hardware reset to external codec s Name Description ACZ SYNC AC 97 Intel High Definition Audio Sync 48 kHz fixed rate sample sync to the codec s Also used to encode the stream number 3 3 3 3 V supply for core well I O buffers 22 pins This power may be shut off in S3 54 S5 or G3 states 05 1 05 V supply for core well logic 20 pins This power may be shut off in S3 S4 S5 or G3 states ACZ BIT CLK 97 Bit Clock Input 12 288 MHz serial data clock generated by the external codec s This signal has an integrated pull down resistor see Note below Intel High Definition Audio Bit Clock Output 24 000 MHz serial data clock generated by the Intel High Definition Audio controller the Intel ICH7 This signal has an integrated pull down resistor so that ACZ BIT CLK doesn t float when an Intel High Definition Audio codec or no codec is connected but the signals are temporari
120. alled Verify that the 8742 keyboard controller is responding Send a self 08h Initialize chip set registers to the Initial POST Values 14h test command to the 8742 and wait for results Also read the switch 04h EN Set in POST flag in CMOS that indicates we are in POST If this bit inputs from the 8742 and write the keyboard controller command is not cleared postClearBootFlag AEh the TrustedCore on byte next boot determines that the current configuration caused POST to Verify that the ROM BIOS checksums to zero Initialize external cache before autosizing memory 09h fail and uses default values for configuration Clear the Oah Initialize CPU registers Obh Enable CPU cache Set bits in cmos related to cache 153 Downloaded from LpManual com Manuals M230 N B Maintenance 7 3 Error Codes 2 Tpoint 18h lah Ich 20h 22h 24h Post Routine Description Initialize all three of the 8254 timers Set the clock timer 0 to binary count mode 3 square wave mode and read write LSB then MSB Initialize the clock timer to zero Set the RAM refresh timer 1 to binary count mode 2 Rate Generator and read Initialize DMA command register with these settings 1 Memory to memory disabled 2 Channel 0 hold address disabled 3 Controller enabled 4 Normal timing 5 Fixed priority 6 Late write selection 7 DREQ sense active 8 DACK sense active low Initialize all 8 DMA channels with these
121. ardware reset button used XTAL XTAL Clock pulse generator Using 10MHz Always 5 Vsupply Set the operating mode Mode 3 choose single mode ICH7 M S3control standby mode Always pull high VDD3 Always supply PA7 input and output pins ps2 keyboard data PA6 input and output pins ps2 keyboard clock input and output pins DC bus clock input and output pins I2C bus clock output pin GPIO Software control charger to main or second battery charging GND Ground I2C data input and output pins I2C Battery data input and output 3 1 4 6 Mbo 8 8 H8_STBY 9 veci VCCI pnmum K DATA nee K_CLK prem BAT H8 PSI RXDO USE A PS0 TXDO USE B 554 VSS4 SDA BAT DATA H8 I I Downloaded from LpManual com Manuals 83 M230 N B Maintenance 1 3 1 Keyboard Controller GPIO Pin Definition 2 Power On default S0 S3 S4 Port Signal name Direction State State State Connectto Description P96 0 G SENSOR Gsensor_ GPI HDD drop sensor interrupt pin 8 P9S AS H8 SB PWRBTN ICH7 M GPIO ICH6 power button signal 9 P94 WR BAT SM SW GPIO Software control SMBus switch 1 1 N ee PA4 KEYIN12 M_CLK P S 2 clock input and output pins 3 24 5 9 PAS input and output pins ps2 mouse 0 PAS KEYINI3 M DATA P S2 data input
122. asserted When tri stated it tells the Clock Chip that SATA Clock can be stopped An external pull up resistor is required LAN RSTSYNC LAN Reset Sync The Platform LAN Connect component s Reset and Sync signals are multiplexed onto this pin Serial Peripheral Interface SPI Signals Other Clock Name Type Description CLK14 Oscillator Clock This clock is used for 8254 timers It runs at 14 31818 MHz This clock is permitted to stop during S3 or lower states CLK48 48 MHz Clock This clock is used to run the USB controller Runs at 48 000 MHz This clock is permitted to stop during S3 or lower states SATA_CLKP SATA_CLKN 100 MHz Differential Clock These signals are used to run the SATA controller at 100 MHz This clock is permitted to stop during S3 S4 S5 states DMI CLKP DMI CLKN 100 MHz Differential Clock These signals are used to run the Direct Media Interface Runs at 100 MHz Name Type Description SPI_CS Uo SPI Chip Select Also used as the SPI bus request signal SPI MISO I SPI Master IN Slave OUT Data input pin for Intel ICH7 SPI MOSI SPI Master OUT Slave IN Data output pin for ICH7 SPI ARB I SPI Arbitration SPI arbitration signal is used to arbitrate the SPI bus with Intel PRO 82573E Gigabit Ethernet Controller when Shared Flash is implemented SPI CLK SPI Clock SPI clock signal during idle
123. ately transition to a S5 state The ICH7 will not wait for the processor stop grant cycle since the processor has overheated SLP S54 S5 Sleep Control SLP S57 is for power plane control This signal is used to shut power off to all non critical systems when in the S5 Soft Off states SUS_STAT LPCPD Suspend Status This signal is asserted by the ICH7 to indicate that the system will be entering a low power state soon This can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered off planes This signal is called LPCPD on the LPC I F PWROK I Power OK When asserted PWROK is an indication to the ICH7 that core power has been stable for 99 ms and that PCICLK has been stable for 1 ms An exception to this rule is if the system is in S3HOT in which PWROK may or may not stay asserted even though PCICLK may be inactive PWROK can be driven asynchronously When PWROK is negated the ICH7 asserts PLTRST NOTE PWROK must deassert for a minimum of three RTC clock periods for the ICH7 to fully reset the power and properly generate the PLTRST output Downloaded from LpManual com Manuals 144 5 3 Intel ICH7 M South Bridge 7 M230 N B Maintenance Processor Interface Signals Name Type Description Processor Interface
124. attery d If GPRS module exist green LED on and amber green LED on ifthe Ethernet LAN active If Touch Pad disable LED on If AC exists Green LED on If HDD temperature Green Red below 2 C or ambient temperature over 60 C Red LED blinks 53 M230 N B Maintenance 1 2 1 16 Mini PCI E Interface Mechanical dimension support the Mini Card Mini PCI E Interface Pin out of System Connector Pin Signa Pi N AACTIVE BT 6 9 PCIECLKREQ2 8 GROU PCIE 51 4 O CLK PCIE SI Ayr GROU 16 y O TP 18 GROUND TP GROU PCIE PCIE 26 GROUND GROU 28 GROU PCIE PCIE GROUND GROU 36 Nece 37 40 GROUND 43 45 47 49 50 GROUND 51 52 33 OUND go Glas 2 e 2 o a 5 2 2 2 amp nN 55 gt amp D 012 121212 12121212 2 gt AB CA 5 N N Downloaded from LpManual com Manuals M230 N B Maintenance 1 2 1 17 Buttons e Power I O BD HSW1 Push button for power on and off control 1 2 1 18 I O Ports RJ 11 Modem Line Connect
125. board may be defective use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement 5 Yes E Replace the faulty parts No Parts Signals U13 5VA 014 5VS HDD U17 SATAHDD_RXP U522 SATAHDD RXN 18 SATAHDD TXP Fl SATAHDD TXN F2 IDE HDD PWR Q37 Q40 HDD_ HEAT PWM Check the system driver for proper Replace Motherboard installation Yes Re Test OK 177 Downloaded from LpManual com Manuals M230 N B Maintenance 8 7 Hard Disk Drive Test Error 2 Either an error message is shown or the drive motor spins non stop while reading data from or writing data to hard disk Pis L39 1202 100 IDE HDD PWR 5VA 0 0522 C378 3900P SATAHDD RXP C377 3900 SATAHDD RXN i C808 j 3900P SATAHDD TXP 2 South Bridge gt C812 3900P SATAHDD TXN z ICH7 M E Q39 F2 51230105 8 6 5A 32V DC 5 Vsys O S p END R350 E G R349 4 HDD 200K p gt 24 G ES U17 Pu C396 Poi HDD HEAT PWM 0 649 1002 imd D2 THERM DTC144WK ADMI022 4 gt VMON 4 P21 TT U13 R188 Ul4 R346 H8 RESET IK RESET M VGA_THERMAL IM 811 H 4 45VS HDD 5VS A H8S 2140 R343 2 QN C395 470K 51230158 1500 12 IDE HDD PWR DTC144WK 178 Downloaded from LpManual co
126. button override to the S5 state Override will occur even if the system is in the S1 S4 states This signal has an internal pullup resistor and has an internal 16 ms de bounce on the input Name Type Description SUSCLK Suspend Clock This clock is an output of the RTC generator circuit to use by other chips for refresh clock RSMRST I Resume Well Reset This signal is used for resetting the resume power plane logic Ring Indicate This signal is an input from a modem It can be enabled as a wake event and this is preserved across power failures VRMPWRGD I VRM Power Good This should be connected to be the processor s VRM Power Good signifying the VRM is stable This signal is internally ANDed with the PWROK input SYS RESET System Reset This pin forces an internal reset after being debounced The ICH7 will reset immediately if the SMBus is idle otherwise it will wait up to 25 ms 2 ms for the SMBus to idle before forcing a reset on the system LAN_RST LAN Reset When asserted the internal LAN controller will be put into reset This signal must be asserted for at least 10 ms after the resume well power VecSus3_3 and VecSus1_5 is valid When de asserted this signal is an indication that the resume well power is stable NOTE LAN RST should be tied to RSMEST PLTRST Platform Reset The Intel ICH7 asserts PLTRST to reset devices on the platform e g
127. ch provides high fault coverage through ATPG Automatic test pattern generation vectors Dedicated test logic for the on chip custom memory macros to provide complete coverage on these modules e A JTAG test mode which is largely compliant with the IEEE 1149 1 standard including internal scan chain for access to chip level test functions and for board level connectivity testing Integrated hardware diagnostic tests performed automatically upon initialization High quality components through built in scan and chip diagnostics Improved access to the analog modules and PLLs in the 54 52 in order to allow full evaluation and characterization of these modules Other Features 44 Downloaded from LpManual com Manuals M230 N B Maintenance Support for serial ROM video BIOS Support for 32 and 64 bit operating systems based on Intel AMD and PowerPC CPUs HW cursor support for monochrome color and alpha blended cursors GDI support for Alpha amp Transparent BLTs as well as Gradient Fills gt Compliance with Wassenaar Agreement 3D vector rate as defined by the Wassenaar Agreement is 58 78 M 10 pixel vectors sec 1 2 1 12 USB Bluetooth option TECOM BT3014 Bluetooth Specification V 1 2 compliant Bluetooth spec 1 1 compatible Bluetooth protocol stacks and profiles support is optional Indoor coverage range up to 50 m typically in general environments for the Class 1 output power with OdBi omni directional ante
128. clock STPCLK is an asynchronous input 131 5 1 Intel Yonah Processor CPU 5 M230 N B Maintenance CPU Pin Description Continued Signal Name Type Description TCK I TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI I TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support TDO TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TESTI I TESTI must have a stuffing option of separate pull down resistor to Vss TEST2 I TEST2 must have a 51 5 pull down resistor to Vss THERMDA Other Thermal Diode Anode THERMDC Other Thermal Diode Cathode THERMTRIP The processor protects itself from catastrophic overheating by use o an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The processor will stop all execution when the junction temperature exceeds approximately 125 C This is signalled to the system by the THERMTRIP Thermal Trip pin TMS I TMS Test Mode Select is a JTAG specification support signal used by debug tools TRDY I TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY m
129. cope to check the following Remove all the I O signal or replace the parts one at a time and test after each device amp cable from replacement motherboard except extended monitor Parts Signals Replace faulty monitor No gt Is motherboard and I O board connected properly Reconnect 5V CRT_IN 1t U512 CRT RED VGA CRT RED CRT GREEN VGA CRT GREEN CRT BLUE VGA CRT BLUE CRT HSYNC CRT HSYNC CRT VSYNC VGA CRT VSYNC CRT DDCCLK CRT DDCDATA AGND CRT Q509 512 VGA CRT DDCCLK FAI VGA CRT DDCDATA Replace the faulty I O board Try another known good I O board 171 Downloaded from LpManual com Manuals M230 N B Maintenance 8 4 External Monitor No Display or Color Abnormal 2 There is no display or picture abnormal on monitor P5 0521 North Bridge Intel 945GM I O Board R598 P24 J3 J507 f 5 E xii J501 051 R608 8599 1200HM 100MHZ 257002 CRT DDCCLK R607 0 D CRT DDCCLK CRT DDCCLK um CRT DDCCCK G Q512 Uu 2N7002 _CRT_DDCDATA R622 0 F s D 4 DDCDATA DDCDATA V CRT DDCDATA 1 un Q9 43VS 2N7002 2 17 VGA _CRT_HSYNC R605 0 4 5 5 2
130. corner rubbers Figure 2 19 3 Remove eight screws Figure 2 20 Figure 2 19 Remove four corner rubbers Figure 2 20 Remove eight screws 107 Downloaded from LpManual com Manuals M230 N B Maintenance 4 Remove six screws to free the LCD housing Figure 2 21 5 Open the LCD cover carefully Be careful with the touch screen cable Figure 2 22 Be careful with this touch screen cable Figure 2 21 Remove six screws Figure 2 22 Free the LCD cover 108 Downloaded from LpManual com Manuals M230 N B Maintenance 6 To disconnect the inverter cable lift the transparent plastic clip up firmly to remove it from the connector 9 Then disconnect the inverter cable Figure 2 23 7 Disconnect the LCD cable to free the panel Figure 2 24 Figure 2 23 Disconnect the inverter cable Figure 2 24 Disconnect the LCD cable Reassembly 1 Reconnect the LCD CABLE inverter cable and touch screen cable Then fit the panel 2 Replace LCD cover Secure the LCD housing with fourteen screws 3 Replace four corner rubbers and secure with sixteen screws 4 Replace the LCD assembly keyboard and battery pack Refer to sections 2 3 7 2 3 4 and 2 3 1 Reassembly Downloaded from LpManual com Manuals 109 M230 N B Maintenance 2 3 9 Touch Screen Board Disassembly 1 Remove the battery keyboard LCD assembly and LCD panel Refer to section 2 3 1 2 3 4 2 3 7 and 2 3 8 Disassemb
131. ct with a docking to extend the capability of I O devices The M230 will support the Intel Mobile Pentium M based on 65 nm technology Yonah 1 66 GHz processor or 1 5 GHz option processor via the 479 ball Micro FCBGA packages and an operating Front Side Bus speed of 667 MHz The Intel 945GM north bridge chipset supports host system bus at 667 MHz 2 slots of DDR2 SODIMM 400 533 MHz 256 MB to 2 GB total internal video controller support RGB TV out SDVO and LVDS video interfaces and hub interface to south bridge ICH7 M The Intel 82801GBM ICH7 M south bridge supports PCI 2 3 interface integrated IDE PATA controller integrated Serial ATA SATA controller integrated USB hub 2 0 up to 8 ports integrated LAN 10 100 Mbit s integrated Intel high definition controller Azalia LPC interface SMBus 2 0 interface FWH interface Real Time Downloaded from LpManual com Manuals M230 N B Maintenance Clock RTC IRQ controller and advance programmable interrupt controller APIC support On PCI Bus interface exist PCI1520 card bus controller and TSB82AA2 1394B controller that supports PC cards and 1394B device separately Wireless LAN on mini PCIE interface and X BAY radio interface On LPC interface exist super I O that is SIO10N268 It provides four serial ports and one parallel port The LPC will connect the Keyboard embedded controller H8S 2140 and flash memory for BIOS There are two SMBus interfaces one is connected from ICH7
132. d 800M bits s Physical write posting of up to three outstanding transactions Serial ROM or boot ROM interface supports 2 wire serial EEPROM devices 33 MHz 64 bit and 33 MHz 32 bit selectable PCI interface PCI burst transfers and deep FIFOs to tolerate large host latency Transmit FIFO 5 K asynchronous Transmit FIFO 2 K isochronous Receive FIFO 2 K asynchronous Receive FIFO 2 K isochronous DO D1 D2 and D3 power states and PME events per the PCI Bus power management interface specification Programmable asynchronous transmit threshold Isochronous receive dual buffer mode Out of order pipelining for asynchronous transmit requests Register access fail interrupt when the PHY SYSCLK is not active 34 Downloaded from LpManual com Manuals M230 N B Maintenance Initial bandwidth available and initial channels available registers Digital video and audio performance enhancements Fabricated in advanced low power CMOS process Multifunction terminal MFUNC terminal 1 PCI CLKRUN protocol per the PCI Mobile Design Guide General purpose I O e CYCLEIN CYCLEOUT for external cycle timer control for customized synchronization Packaged in 144 terminal LQFP PGE Downloaded from LpManual com Manuals 35 M230 N B Maintenance 1 2 1 9 Audio Codec Realtek ALC260 Single chip multi bit Sigma Delta converters with high S N ratio stereo DAC supports 16 20 24 bit PCM format with 44 1 48 96
133. ddressing 667 MT s 667 MHz and 533 MT s 533 MHz FSB support 2X address 4X data Host bus dynamic bus inversion HDINV support 12 deep in order queue gt Integrated System Memory DRAM Controller Supports up to two DDR2 SDRAM channels 64 bit wide per channel One SO DIMM connecter per channel Maximum of two double sided unbuffered SO DIMMs 4 rows populated Minimum amount of memory supported is 128 MB 16 MB x 16 b x 4 devices x 1 row 128 MB using 256 MB technology Serial ATA controller 256 MB 512 MB and 1 GB technology using X8 and X16 devices Three memory channel organization are supported for DDR2 Downloaded from LpManual com Manuals M230 N B Maintenance Single channel Dual channel symmetric Dual channel asymmetric Support DDR2 400 533 667 devices Supports On Die Termination ODT for DDR2 Supports fast chip select mode Supports partial writes to memory using Data Mask signals DM Supports high density memory package for DDR2 type devices Supports Reduced Power DDR2 RPDDR2 Supports Intel Rapid Memory Power Management gt External Graphics Using PCI Express Architecture Interface One X16 16 lanes PCI Express port intended for graphics attach fully compliant to the PCI Express base specification revision 1 0a Maximum theoretical realized bandwidth on interface of 4 GB s in each direction simultaneously for an aggregate of 8 GB s when X16 Automatic discovery negotiation and training o
134. e clock for all ICH7 initiated transactions PAR is an output during the data phase delayed one clock when the ICH7 is the initiator of a PCI write transaction and when it is the target of a read transaction ICH7 checks parity when it is the target of a PCI write transaction If a parity error is detected the ICH7 will set the appropriate internal status bits and has the option to generate an NMI SMI DEVSEL Io Device Select The ICH7 asserts DEVSEL to claim a PCI transaction As an output the ICH7 asserts DEVSEL when a PCI master peripheral attempts an access to an internal ICH7 address or an address destined DMI main memory or graphics As an input DEVSEL indicates the response to an ICH7 initiated transaction on the PCI bus DEVSEL is tri stated from the leading edge of PLTRST DEVSEL remains tri stated by the ICH7 until driven by a target device FRAME Lo Cycle Frame The current initiator drives FRAME to indicate the beginning and duration of a PCI transaction While the initiator asserts FRAME data transfers continue When the initiator negates FRAMEZ the transaction is in the final data phase is an input to the ICH7 when the ICH7 is the target and FRAME is an output from the ICH7 when the ICH7 is the initiator FRAME remains tristated by the ICH7 until driven by an initiator Downloaded from LpManual com Manuals 139 5 3 Intel ICH7 M South Bridge 2 M230 N B
135. eable regions if necessary NOTE Hook routine must preserve DX which carries the cache size to the DisplayCacheSizeJ routine Initialize the handler for SMM Display external cache size on the screen if it is non zero size from the cacheConfigureJ routine successful reboot Display the starting offset of the nondisposable segment of TrustedCore detected during POST Display error messages on the screen Downloaded from LpManual com Manuals Tpoint Post Routine Description 0 display error messages on the screen 7 Check status bits for keyboard related failures Display error messages on the screen 6h 7ch Initialize the hardware interrupt vectors from 08 to OF and from 70h to 77H Also set the interrupt vectors from 60h to 66H to zero 7dh Initialize Intelligent System Monitoring eh 7 The initialization test Use the floating point instructions to determine if a coprocessor exists instead of the ET bit in CRO 8 Disable onboard COM and LPT ports before testing for presence of external I O devices 8 Oh Ih Run late device initialization routines 82h Test and identify RS232 ports 83h Configure Fisk Disk Controller 84h Test and identify parallel ports 85h Display any ESCD read errors and configure all PnP ISA devices 86h Th 8h 9h l ah h Initialize onboard I O and BDA according to CMOS and presence of external devices 8 Initiahze motherboard configurable devices
136. ed from LpManual com Manuals M230 N B Maintenance gt IDE 50 Pin Connector MiTAC 291000025038 1 Power On default Signal name Direction S0 State S3 State S4 State Purpose CD ROM Audio right Output CD ROM Audio left Output __ Ground CDCOMM CD ROM Audio ground IDEPDDS 10 IDE Device data 8 1 Reset 10 IDE Device data 9 10 IDE Device data 7 IDEPDDOO VO IDE Device data 10 YO _ IDE Device data 6 VO IDE Device data 11 IDEPD IDE Device data 5 IDEPDD2 Vo IDE Device data 12 IDEPD4 104 IDE Device data 4 2090 IDE Device data 13 IDE Device data 3 a IDE Device data 14 o mro IDE Device data 2 OF IDE Device data 15 IDE Device data 1 21 DMA Request 22 10 IDE Device data 0 2 meroon r 25 round 2 mEPDOW 0 Write Strobe x mePDACC 0 MA Acknowledge EA EM 9 NUM NUM 6 EA EM 9 EM Uo I VO Uo Uo VO VO Uo Uo VO VO IO I 7 10 11 12 13 14 15 16 17 18 19 20 1 Downloaded from LpManual com Manuals M230 N B Maintenance gt IDE 50 Pin Connector MiTAC 291000025038 2 Continue to the previous page Power
137. efer to sections 2 3 1 2 3 7 Disassembly 2 Remove thirty four screws Figure 2 27 3 Remove six stand off screws Figure 2 28 Figure 2 28 Remove sis stand off screws Figure 2 27 Remove thirty four screws 112 Downloaded from LpManual com Manuals M230 N B Maintenance 4 Remove two speakers cables to free the bottom cover Figure 2 29 5 Remove eight screws and disconnect T P SW wire to free the system board Figure 2 30 Figure 2 29 Free the bottom cover Figure 2 30 Remove eight screws 113 Downloaded from LpManual com Manuals M230 N B Maintenance 6 Remove four screws fixing the PCMCIA socket Figure 2 31 7 Turn over lift the PCMCIA socket straightly to free it from the system board Figure 2 32 8 Turn over the base unit then lift up the system board from the housing E LI a2 ED 2 ran Figure 2 31 Remove four screws Figure 2 32 Free the PCMCIA socket Reassembly 1 Put the PCMCIA socket back to its place in the housing 2 Replace the system board back into the housing Reconnect the PCMCIA socket to the system board and secure with four screws 3 Secure the system board with eight screws 4 Turn over the base unit Secure with fifteen screws and reconnect one cable 5 Replace the LCD assembly DDR2 wireless card keyboard CD ROM HDD and battery pack Refer to the previous sections reassembly 114 Downloaded from LpManu
138. f link out of set Supports traditional PCI style traffic asynchronous snooped PCI ordering Supports traditional AGP style traffic asynchronous non snooped PCI X ordering Downloaded from LpManual com Manuals M230 N B Maintenance Hierarchical PCI compliant configuration mechanism for downstream devices i e normal PCI 2 3 configuration space as a PCI to PCI bridge Supports lane reversal and bit swapping gt Internal Graphics Controller Graphics core frequency 2D Display core frequency at 133 200 or 250 MHz 1 05 V depending on the host memory configurations 3D Render core frequency at 133 166 250 MHz Vcc 1 05 V depending on the host memory configurations Intel Smart 2D Display Technology Intel dual frequency graphics technology support Dynamic Video Memory Technology DVMT 3 0 support 3D graphics engine DirectX 9 0 support OpenGL 1 5 and 2 0 support Zone rendering 2 0 support Analog CRT DAC interface support Supports max DAC frequency up to 400 MHz Downloaded from LpManual com Manuals M230 N B Maintenance 24 bit RAMDAC support DDC2B compliant Up to 2048x1536 resolution support Analog TV out interface support Integrated TV out device supported on display pipes A and B NTSC PAL encoder standard formats supports 4801 480 5761 576 720 10801 1080 modes supported Tri level Sync signal Multiplexed output interface Com
139. format Wait function in master mode I2C bus format Wait function I2C bus format Interrupt sources Selection of 16 internal clocks in master mode Direct bus drive SCL SDA pin Automatic switching from formatless mode to I2C bus format IIC 0 only Host Interface X Bus Interface Control of the fast GATE A20 function Shutdown of the XBS module by the HIFSD pin Five host interrupt requests gt Keyboard Buffer Controller Conforms to PS 2 interface specifications Direct bus drive via the KCLK and KD pins Interrupt sources on completion of data reception and on detection of clock edge Error detection parity error and stop bit monitoring 27 Downloaded from LpManual com Manuals M230 N B Maintenance gt Host Interface LPC Interface LPC Supports LPC interface I O read cycles and I O write cycles Has three register sets comprising data and status registers Supports SERIRQ Eleven interrupt sources A D Converter 10 bit resolution Input channels eight analog input channels and 16 digital input channels Analog conversion voltage range can be specified using the reference power supply voltage pin AVref as an analog reference voltage Conversion time 13 4 us per channel at 10 MHz operation Two kinds of operating modes Four data registers Sample and hold function Three kinds of conversion start Interrupt request Downloaded from LpManual com Manuals 28 M230 N B Main
140. frequency The table defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency The processor operates at 667 MHz or 533 MHz system bus frequency 166MHz or 133MHz BCLK 1 0 frequency respectively BSE 2 0 Encoding for BCLK Frequency BSEL 2 BSEL 1 BSE 0 BCLK Frequency Reserved 133MHz Reserved 166MHz COMPP3 0 Analog COMP 3 0 must be terminated on the system board using precision 196 tolerance resistors Refer to the platform design guides for more implementation details 128 5 1 Intel Yonah Processor CPU 2 M230 N B Maintenance CPU Pin Description Continued Signal Name Type Description D 63 0 Lo D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor system bus agents and must connect the appropriate pins on both agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DINV
141. g point of SDQS and its complement SDQS_Ax during read and write transactions Signal Name Type Description SCLK 5 0 SDRAM Differential Clock SSTL 1 8 3 per DIMM SCLK Bx and its complement SCLK signal make a differential clock pair output The crossing of the positive edge of SCLK Bx and the negative edge of its complement SCLK_Bx are used to sample the command and control signals on the SDRAM SCLK B 5 0 SDRAM Complementary Differential Clock SSTL 1 8 3 per DIMM These are the complementary Differential DDR2 Clock signals SCS_B 3 0 Chip Select SSTL 1 8 1 per Rank These signals select particular SDRAM components during the active state There is one chip select for each SDRAM rank SMA B 13 0 Memory Address SSTL 1 8 These signals are used to provide the multiplexed row and column address to the SDRAM SBS B 2 0 Bank Select SSTL 1 8 These signals define which banks are selected within each SDRAM rank DDR2 1 Gb technology is 8 banks SRAS Row Address Strobe SSTL 1 8 This signal is used with SCAS B and SWE B along with SCS_B to define the SDRAM commands Downloaded from LpManual com Manuals 135 M230 N B Maintenance 5 2 Intel 945GM North Bridge 4 DDR2 DRAM Channel B Interface Continued Analog Display Signals Intel amp 82945G GMCH Only Signal Name Type
142. h Post Routine Description Check support status for Self Monitoring Analysis Reporting Technology disk failure warning Shadow miscellaneous ROMs if specified by Setup and CMOS is valid and the previous boot was OK Set up Power Management Initiate power management state machine Odh Initialze Security Engine 9eh Enable hardware interrupts 9fh Check the total number of Fast Disks ATA and SCSI and update the bdaFdiskCount Verify that the system clock is interrupting 0 ing Setup Numlock indicator Display a message if key switch is locked a4h Initialize typematic rate ash aah Overwrite the Press F2 for Setup prompt with spaces erasing it from the screen Scan the key buffer to see if the F2 key was struck after keyboard interrupts were enabled If an F2 keystroke is found set a flag 157 M230 N B Maintenance 7 3 Error Codes 6 Enter SETUP If F2 was pressed go to SETUP Else if errors were found display Press F1 or F2 prompt if F2 is pressed go to setup else if F1 1s pressed boot Else boot Clear ConfigFailedBit and InPostBit in CMOS Check for errors If errors were found beep twice display F1 or F2 message if F2 keystroke go to SETUP if Fl keystroke go to BOOT Inform RomPilot about the end of POST boh Change status bits n CMOS and or the TrustedCore data area to reflect the fact that POST 5 complete One quick beep Down
143. igh speed differential signals from Port 2 SATA3TXP Serial ATA 3 Differential Transmit Pair SATA3TXN These are outbound high speed differential signals to Port 3 SATA3RXP I Serial ATA 3 Differential Receive Pair SATA3RXN These are inbound high speed differential signals from Port 3 SATARBIAS Serial Resistor Bias These are analog connection points for an external resistor to ground SATARBIAS I Serial ATA Resistor Bias Complement These are analog connection points for an external resistor to ground SATAOGP I Serial ATA 0 General Purpose GPIO21 This is an input pin which can be configured as an interlock switch corresponding to SATA Port 0 When used as an interlock switch status indication this signal should be drive to 0 to indicate that the switch is closed and to 1 to indicate that the switch is open If interlock switches are not required this pin can be configured as GPIO21 SATAIGP I Serial ATA 1 General Purpose GPIO19 Same function as SATAOGP except for SATA Port 1 If interlock switches are not required this pin can be configured as 19 SATA2GP I Serial ATA 2 General Purpose GPIO36 Same function as SATAOGP except for SATA Port 2 If interlock switches are not required this pin can be configured as GPIO36 Downloaded from LpManual com Manuals 140 5 3 Intel ICH7 M South Bridge 3 M230 N B Maintenance Serial ATA Interface Signals Continued
144. interrupt vectors 0 thru 77h to the TrustedCore general interrupt handler 154 M230 N B Maintenance 7 3 Error Codes 3 45h all motherboard devices 4 Initialize support for 120 by initializing global variables used by the 47h 120 code Pause POST table processing if a CMOS bit is set for debugging Verify that the equipment specified in the CMOS matches the hardware currently installed If the monitor type is set to 00 then a video ROM must exist If the monitor type is 1 or 2 set the video switch to CGA If monitor type 3 set the video switch to m Perform these tasks 1 Size the PCI bus topology and set bridge bus numbers 2 Set the system max bus number 3 Write a 0 to the command register of every PCI device 4 Write a 0 to all 6 base registers in every PCI device 5 Write a 1 to the status register of every PCI device 6 Find all IOPs and initialize them dah Initialize QuietBoot if it is installed Enable both keyboard and timer interrupts IRQO and IRQ1 If your 4bh POST tasks require interrupts off preserve them with a PUSHF and CLI at the beginning and a POPF at the end If you change the PIC preserve the existing bits Shadow video BIOS ROM if specified by Setup and CMOS is valid and the previous boot was OK Downloaded from LpManual com Manuals 4 Display copyright notice fh Initialize MultiBoot Allocate memory for old and new MultiBoot history tables 1 ELIT 5
145. io 4 3 11507 Py R196 7 t HSWI la Moenum Ay POWERSW e 3 o x PWR ON DDR2 Power Board Module PWR ON Power gt Module R188 i H8_RESET K 2 4 RESET vec 3VA 1 P24 MN 2 219 10K T3V IMP811 R215 V 4 7K SB_PWRBTN PCI 0521 Po 0513 HCPURST HPWRGD North Bridge CPU Intel 945GM Yonah R889 J19 ACZ_RST _ M MDC Py Pis 0502 R582 R888 39 ACZ_RST ACZ_RST ALC260 Downloaded from LpManual com Manuals U522 South Bridge ICH7 M PCI U4 ra Super I O PCI_RESET R55 0 PCI e y U5 Giga LAN U520 gt PCMCIA Controller U9 PCI md 1394B Controller pu J13 PCI gt Connector U16 3VS NC7S08 JA7 lJa vec 5 Pig PLT_RST 2 v 4 BUF PLT RST 19 Mini Express SNe R335 Connector Wireless V 100K PLT_RST PLT_RST ST nap PLT_RST PLT_RST Controller T 65 100 PU US12 SYS BIOS 5VS J12 R176 CD_RST 1 CDROM R168 S 0 168 M230 N B Maintenance 8 3 Graphic Controller Test Error LCD No Display 1 There is no display or picture abnormal on LCD although power on
146. is 5 L Internal Speaker SPKLOUT e Connector C538 Pis 22U R542 33K J3 J507 P3 5VS Board RLINE IN C560 E lt 470 AOUT R C57 c62 10U 10U J506 Ps C552 R2 RI 12 220 R552 33K gt 10K 1202 100M J503 _ RHP IN DEVICE_DECT A 5 U11 1302 40084 111 E EAQUE 0507 LINE OUT L A PLP32168 2 Pos SN74LVC1G3157 TAA M25 LINE OUT R PNIS AV 3 145 _ LI 1207100 1 P L 3 U10 Audio S RIS RIA Col 120Z 100M M E SN74LVCIG3157 PITE eZ SPDIFOUT SPDIFOUT LED Amplifier 9 9 LH Drive y 8 Y POGO V V 9 IC Connector z 0212 _ DECT_HP OPT 4 SE T 8 92168 Line out Phone Jack C541 5 5 5 220 8553 LLINEIN 571 R578 L 47U 47K E 120Z 100M C557 220 R562 33K LHP IN 0513 DEVICE DECT DTCIA4TKA Downloaded from LpManual com Manuals M230 N B Maintenance 8 11 LAN Test Error 1 An error occurs when a LAN device is installed 1 Check if the driver is installed properly Check the following parts for cold solder or one of the following parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement 2 Check if the notebook connect with the LAN properly Board level Troubleshooting Parts Signals 05 43V
147. itecture which replaces conventional PCI and AGP buses in new PC platforms Refer to PCI SIG for specifications relating to PCI Express architecture Native X16 PCI Express bus interface Supports X1 X2 X4 X8 X12 and X16 lane widths Supports X16 lane reversal where the receiver on lanes 0 to 15 on the graphics endpoint are mapped to the transmitter on lanes 15 down to 0 on the root complex Supports X16 lane reversal where the transmitter on lanes 0 to 15 on the graphics endpoint are mapped the receiver on lanes 15 down to 0 on the root complex requires corresponding support on the root complex Supports X1 X2 X4 X8 X12 and X16 polarity inversion Supports Mobile Graphics Low Power Addendum to the PCI Express Base Specification 1 0 gt Memory Support Features e 256 128 64 bit memory interface using DDR1 or DDR2 SDRAM SGRAM or GDDR3 SDRAM except 52 to build 16 32 64 128 256 512 MB configurations e Support for SSTL 1 8 memory interface Downloaded from LpManual com Manuals 42 M230 N B Maintenance gt Power Management Features Single chip solution in 90 nm micron CMOS technology Full ACPI 1 0b OnNow and IAPC Instantly Available PC power management Static and Adynamic Power Management support APM as well as ACPI with full VESA DPM and energy star compliance Full PowerPlayTM 6 0 including enhanced Power on Demand support The chip power management support logic supports four device power s
148. izer ICS9LPR310 ICS9LPR310 is a low power CK410M compliant clock specification This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets ICS9LPR310 is driven with a 14 318 MHz crystal 667 MT s 667 MHz FSB support Supports tight ppm accuracy clocks for Serial ATA and PCIEX Supports programmable spread percentage and frequency Uses external 14 318 MHz crystal external crystal load caps are required for frequency tuning pins to support PCIEX power management Programmable watchdog safe frequency Low power differential clock outputs No 50 ohm resistor to GND needed 1 2 1 4 PCMCIA Controller TI PCI 15204 TPS2224A gt TI PCI 1520 Card Bus Controller The PCI1520 a dual slot Card Bus controller designed to meet the PCI Bus power management interface specification for PCI to Card Bus bridges is an ultra low power high performance PCI to Card Bus controller that supports two independent card sockets compliant with the PC card standard The PCI1520 provides features that make it the best choice for bridging between PCI and PC cards in both Downloaded from LpManual com Manuals M230 N B Maintenance notebook and desktop computers The 1997 PC card standard retains the 16 bit PC card specification defined in PCI local bus specification and defines the new 32 bit PC card Card Bus capable of full 32 bit data transfers at 33 MHz The PCI1520 supports any
149. l Speaker L Line out SPDIF m RJ 11 Jack 013 Keyboard BIOS Winbond H8 2140S Internal Keyboard Touch Pad Power Button ECO Button Cover Switch Quick Key 150 M230 N B Maintenance 7 Maintenance Diagnostics 7 1 Introduction Each time the computer is turned on the system BIOS runs a series of internal checks on the hardware This Power on Self Test post allows the computer to detect problems as early as the power on stage Error messages of post can alert you to the problems of your computer If an error is detected during these tests you will see an error message displayed on the screen If the error occurs before the display is initialized then the screen cannot display the error message Error codes or system beeps are used to identify a post error that occurs when the screen is not available The value for the diagnostic port is written at the beginning of the test Therefore if the test failed the user can determine where the problem occurred by reading the last value written to the port by the debug card plug at Parallel port Downloaded from LpManual com Manuals 151 M230 N B Maintenance 7 2 Maintenance Diagnostics 7 2 1 Diagnostic Tool for Mini PCI Slot x x a m 7 Figure 7 1 Mini PCI debug card P N 316664900030 R00 Description PWA 5027 DEBUG BD Downloaded from
150. ll the HDD out Figure 2 4 Figure 2 3 Open the HDD door Figure 2 4 Pull the HDD out Reassembly 1 Replace the HDD into the compartment 2 Push the HDD door inside slightly to close it Downloaded from LpManual com Manuals 97 M230 N B Maintenance 2 3 3 CD ROM Disassembly 1 Open the CD ROM door Figure 2 5 2 Put the notebook upside down and put the ejector direct Figure 2 6 an Figure 2 5 Open the CD ROM door Downloaded from LpManual com Manuals Figure 2 6 Put the ejector direct 98 M230 N B Maintenance 3 Turn the ejector counterclockwise to push the CD ROM out Figure 2 7 Figure 2 7 Turn the ejector counterclockwise Reassembly 1 Replace the CD ROM module into the compartment 2 Push the CD ROM door inside slightly to close it Downloaded from LpManual com Manuals 99 M230 N B Maintenance 2 3 4 Keyboard Disassembly 1 Open the top cover then remove five screws Figure 2 8 2 Turn to back then remove four screws Figure 2 9 Figure 2 8 Remove five screws Figure 2 9 Remove four screws 100 Downloaded from LpManual com Manuals M230 N B Maintenance 3 Open the top cover to 180 degree then slightly lift up the hinge cover Figure 2 10 4 Remove four screws and open the bracket Figure 2 11 Figure 2 10 Remove the hinge cover Figure 2 11
151. loaded from LpManual com Manuals Tpoint Post Routine Description Turn off Esc and F2 key checking IF VGA adapter is present IF OEM screen is still up Note OEM screen is gone Fade out OEM screen Reset video clear screen reset cursor reload DAC ENDIF ENDIF If password on boot is enabled a call is made to Setup to check password If the user does not enter a valid password Setup does not return 158 M230 N B Maintenance 7 3 Error Codes 7 Tpoint c2h c3h c4h ch coh c7h c8h cah cbh cch cdh ceh d2h eh elh e2h e3h e4h Initialize note dock Force check optional Extended checksum optional Redirect Int 15h to enable target board to use remote keyboard PICO BIOS Redirect Int 13h to Memory Technologies Devices such as ROM RAM PCMCIA and serial disk PICO BIOS Redirect Int 10h to enable target board to use a remote serial video PICO BIOS Remap I O and memory address space for PCMCIA PICO BIOS Initialize digitizer device and display installed message if successful Initialize note dock late following are for Boot Block in FlashROM Downloaded from LpManual com Manuals Tpoint e7h e8h e9h eah ebh ech edh eeh efh f h flh f2h f3h f4h f5h f h Post Routine Description Check force recovery boot Checksum BIOS ROM Go to TrustedCore Initialize Multi Processor Set Huge Segment Initialize OEM
152. ls 21 M230 N B Maintenance 7 WP supports the whole chip except boot block hardware protection Hardware features Latched address and data TTL compatible I O Automatic program and erase timing with internal VPP generation End of program or erase detection Toggle bit Data polling Low power consumption Read active current 15 mA typ for FWH mode VPP input pin Acceleration ACC function accelerates program timing Hardware reset pin Reset the internal state machine to the read mode Ready Busy output RY BY Detect program or erase cycle completion Dual BIOS function Full chip partition with 8 M bit or dual block partition with 4 M bit Downloaded from LpManual com Manuals 22 M230 N B Maintenance Available packages 32L PLCC 32L STSOP 40L TSOP 10x20 mm 32 PLCC lead free 32L STSOP lead free and 40L TSOP 10x20 mm lead free 1 2 1 6 Keyboard Controller The H8S 2140 is a high speed central processing unit with an internal 32 bit architecture that is upward compatible with the H8 300 and H8 300H CPUs The H8S 2000 CPU has sixteen 16 bit general registers can address a 16 Mbyte linear address space and is ideal for real time control Detail specification as below gt Bus Controller Basic bus interface Burst ROM interface dle cycle insertion Bus arbitration function gt Data Transfer Controller Transfer is possible over any number of channels Three transfer mode
153. ls are used as straps which are sampled before RESET is deasserted A20M If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 Mbyte boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction ADS T O ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 31 3 and REQ 4 0 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction ADSTB T O Address strobes are used to latch A 31 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 A 16 3 ADSTB 0 A 31 17 ADSTB 1 BCLK 1 0 The differential pair BCLK Bus Clock determines the system bus frequency All processor system bus agents must receive these signals to drive their outputs and latch their inputs BNR T O
154. ls of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured using BIOS programming of the APIC register space and used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LOCK Vo LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of both processor system bus agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction 130 5 1 Intel Yonah Processor CPU 4 M230 N B Maintenance CPU Pin Description Continued Signal Name Type Description LOCK vo When the priority agent asserts BPRI to arbitrate for ownership of the processor system bus it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock PRDY Probe Ready signal used by debug tools to determine processor debug readiness PREQ Probe Request signal used by debug tools to request debug operation of the processor PROCHOT TO As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the processor has reached it
155. ly 2 Remove three screws and disconnect two cables to free the touch screen board Figure 2 25 Figure 2 25 Free the touch screen board Reassembly 1 Fit the touch screen board back into place and secure with three screws Reconnect two cables 2 Replace the LCD panel into LCD housing Then reconnect the touch screen cable and inverter cable 3 Replace the LCD panel Refer to section 2 3 8 Reassembly 4 Replace the LCD assembly keyboard and battery pack Refer to sections 2 3 7 2 3 4 and 2 3 1 Reassembly Downloaded from LpManual com Manuals 110 M230 N B Maintenance 2 3 10 Inverter Board Disassembly 1 Remove the battery keyboard LCD assembly and LCD panel Refer to section 2 3 1 2 3 4 2 3 7 and 2 3 8 Disassembly 2 Remove two screws and disconnect one cable to free the inverter board Figure 2 26 Figure 2 26 Free the inverter board Reassembly 1 Fit the inverter board back into place and secure with three screws Reconnect one cable 2 Replace the LCD panel into LCD housing Then reconnect the touch screen cable and inverter cable 3 Replace the LCD panel Refer to section 2 3 8 Reassembly 4 Replace the LCD assembly keyboard and battery pack Refer to section 2 3 7 2 3 4 and 2 3 1 Reassembly Downloaded from LpManual com Manuals 111 M230 N B Maintenance 2 3 11 System Board Disassembly 1 Remove the battery HDD CD ROM keyboard wireless card DDR2 and LCD assembly R
156. ly configured as AC 97 5 A 1 5 V supply for Logic and I O 30 pins This power may be shut off in S3 S4 S5 or G3 states 5 B 1 5 V supply for Logic and 53 pins This power may be shut off in S3 S4 S5 or G3 states VSREF Reference for 5 V tolerance on core well inputs 2 pins This power may be shut off in S3 S4 S5 or G3 states VecSus3_3 3 3 V supply for resume well I O buffers 24 pins This power is not expected to be shut off unless the system is unplugged in desktop configurations ACZ_SDOUT AC 97 Intel High Definition Audio Serial Data Out Serial TDM data output to the codec s This serial output is double pumped for a bit rate of 48 Mb s for Intel High Definition Audio NOTE ACZ SDOUT is sampled at the rising edge of PWROK as a functional strap See Function Straps for more details There is a weak integrated pull down resistor on the ACZ SDOUT pin VecSus1 05 1 05 V supply for resume well logic 5 pins This power is not expected to be shut off unless the system is unplugged in desktop configurations This voltage may be generated internally see Function Straps for strapping option If generated internally these pins should not be connected to an external supply VSREF Sus Reference for 5 V tolerance on resume well inputs 1 pin This power is not expected to be shut off unless the system is unplugged in desktop configurations
157. m Manuals 1 Try another known good compact disk 2 Check install for correctly M230 N B Maintenance 8 8 CD ROM Test Error 1 An error message is shown when reading data from CD ROM CD ROM Test Error Board level Troubleshooting One of the following parts or signals on the motherboard may be defective use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement lt gt Replace the faulty parts the faulty parts Parts Signals U502 5VS CD_L U522 3VS CD_R J12 5V VCD CD COMM Q24 IDE PDDY 0 15 CDROM L Q27 CD_RST CDROM L29 IDE PDCS 1 3 CDROM COMM R168 IDE PDAPO 2 USBP1 FDD R175 IDE IRQ14 IDE PDIOW R176 IDE PDDACK IDE PDDREQ R184 IDE PIORDY PLT_RST Re Test R197 IDE_PDIOR OK No Replace Motherboard 2 the CD ROM for proper 2 179 Downloaded from LpManual com Manuals M230 N B Maintenance 8 8 CD ROM Test Error 2 An error message is shown when reading data from CD ROM 5VS R176 R168 PLT_RST 0 Q24 DTCI44TKA IDE PDDJO 15 5VS R175 10K Q27 DTC144TKA CD_RST J12 120Z 100M 5V VCD 45VSo e Y YN 1 C187 C212 C204 7195 1U 7 150U IU C174 V 0 CD_RST AC IDE PDD O0 15 WOU dI Downloaded from LpManual com Manuals 3VS
158. m hang Timers to detect improper processor reset ntegrated processor frequency strap logic Supports ability to disable external devices SMBus Flexible SMBus SMLink architecture to optimize for ASF Provides independent manageability bus through SM Link interface Supports SMBus 2 0 Specification Host interface allows processor to communicate via SMBus Slave interface allows an internal or external microcontroller to access system resources Compatible with most two wire components that are also I2C compatible Downloaded from LpManual com Manuals M230 N B Maintenance gt NEW 1 05 V Core Voltage gt Integrated 1 05 V Voltage Regulator INTVR for the Suspend and LAN wells gt GPIO TTL open drain inversion gt Package 31x31 mm 652 mBGA Downloaded from LpManual com Manuals 52 M230 N B Maintenance 1 2 1 15 LED Indicators There are 13 LED indicators locate on the system housing the detail shows on the follows table LED Number LED BD HDI LED BD HD2 LED BD HD4 LED BD HD5 LED BD HD3 M BD D34 M BD D33 M BD D32 M BD D35 M BD D36 M DB D37 M BD D836 Downloaded from LpManual com Manuals Functions Power on Suspend HDD Num Lock Caps Lock Scroll Lock CDROM Battery Low Battery Charge Status Wireless LAN XBA Y GPRS module LAN Touch Pad ON Off ACIN HDD Low Temp LED color If AC exist amber LED on when battery in charging Green LED on if b
159. m pe 1 M2 2025 94 Downloaded from LpManual com Manuals M230 N B Maintenance 2 3 System Disassembly The section discusses at length each major component for disassembly reassembly and show corresponding illustrations Use the chart below to determine the disassembly sequence for removing components from the notebook NOTE Before you start to install replace these modules disconnect all peripheral devices and make sure the notebook is not turned NOTEBOOK Downloaded from LpManual com Manuals on or connected to AC power Modular Components m LCD Assembly Components Base Unit Components 2 3 1 Battery Pack 2 3 2 HDD Module 2 3 3 CD ROM 2 3 4 Keyboard 2 3 5 Wireless Card 2 3 6 DDR2 SDRAM 2 3 7 LCD Assembly 2 3 8 LCD Panel 2 3 9 Touch Screen Board 2 3 10 Inverter Board 2 3 11 System Board 2 3 12 Modem Card 95 2 3 1 Battery Pack Disassembly 1 Open the battery door Figure 2 1 2 Pull the battery holder out Figure 2 2 pagent L 2 ot me M230 N B Maintenance Figure 2 1 Open the battery door Reassembly 1 Replace the battery pack into the compartment 2 Push the battery door inside slightly to close it Downloaded from LpManual com Manuals Figure 2 2 Pull the battery holder out 96 M230 N B Maintenance 2 3 2 HDD Module Disassembly 1 Open the HDD door Figure 2 3 2 Pu
160. nal crystal is used then RTCX1 can be driven with the desired clock rate RTCX2 Special Crystal Input 2 This signal is connected to the 32 768 KHz crystal If no external crystal is used then RTCX2 should be left floating Downloaded from LpManual com Manuals 149 M230 N B Maintenance 6 System Block Diagram TPS2224A IC Card Socket U520 PCI1520 PDV PCMCIA amp CardBus U9 TSB82AA2 1394B HOST U6 TSB81BA3 1394B PHY Downloaded from LpManual com Manuals Mini PCIE Wireless VGA TFT LCD PCI Bus SATA CDROM DVD US Giga LAN RJ 45 Jack RGB LVDS PCIE U513 Intel Pentium M CPU HD 0 63 HA 0 31 Control 0521 North Bridge Calistoga 945GM U523 Clock Generator ICS9LR310 ADM1032 Thermal Sensor MD 0 63 MAJ 0 14 DRAM Control 200 Pin DDR2 SO DIMM Socket 2 USB0 1 2 7 X BAY USB DMI Azalia U522 South Bridge ICH7 M LPC BUS Parallel U4 Port 510103268 Super I O COMI Touch X BAY Screen Line in POGO USB External Microphone U502 Audio Codec ALC260 J19 M D C Internal Microphone U507 Amplifier 0212 Interna
161. nna Outdoor coverage range up to 100 m typically in open site for the Class 1 output power with OdBi omni directional antenna Output power controllable Max data rate 720 kbps 45 Downloaded from LpManual com Manuals M230 N B Maintenance 1 2 1 13 Fax Modem Askey 1456VQL T1 INT LF HD audio AC 97 MC 97 2 2 compliant V 44 V 42 V 42bis and MNP Class 5 data compression Low power standby mode 3 3 V to5 V power supply Compliant with FCC CTR21 JATE and other PTTs Auto sensing host interface to select AC 97 or HD audio OperationtTemperature humidity 0 C 0 60 C 90 Storage temperature humidity 20 C 0 70 C 90 1 2 1 14 South Bridge ICH7 M PCI Bus Interface Supports PCI Revision 2 3 Specification at 33 MHz Supports up to 6 master devices on PCI NEW Six available PCI REQ GNT pairs Support for 64 bit addressing on PCI using DAC protocol Downloaded from LpManual com Manuals 46 M230 N B Maintenance gt PCI Express Interface 4 PCI Express root ports NEW 2 Additional PCI Express root ports Not available on all ICH7 SKUs Supports PCI Express 1 0a e Ports 1 4 can be statically configured as 4x1 or 1x4 Support for full 2 5 Gb s bandwidth in each direction per x1 lane Module based Hot Plug supported e g Express Card gt Integrated Serial ATA Host Controller two ports Mobile Only ntegrated AHCI controller Not available on all
162. noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT INIT nitialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal However to ensure recognition of this signal following an Input Output Write Instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT must connect the appropriate pins of both FSB agents If INIT is sampled active on the active to inactive transition of then the processor executes its Built in Selt Test BIST LINT 1 0 LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINTI becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signa
163. ol signals on the SDRAM SCLK A 5 0 SDRAM Complementary Differential Clock SSTL 1 8 3 per DIMM These are the complementary Differential DDR2 Clock signals SCS_A 3 0 Chip Select SSTL 1 8 1 per Rank These signals select particular SDRAM components during the active state There is one chip select for each SDRAM rank SMA A 13 0 Memory Address SSTL 1 8 These signals are used to provide the multiplexed row and column address to the SDRAM SBS A 2 0 Bank Select SSTL 1 8 These signals define which banks are selected within each SDRAM rank DDR2 1 Gb technology is 8 banks SRAS A Row Address Strobe SSTL 1 8 This signal is used with SCAS Az and SWE AZ along with SCS_A to define the SDRAM commands SCAS_A Column Address Strobe SSTL 1 8 This signal is used with SRAS_A and SWE AZ along with SCS_A to define the SDRAM commands SWE_A Write Enable SSTL 1 8 This signal is used with SCAS Az and SRAS along with SCS_A to define the SDRAM commands SDQ A 63 0 VO Data Lines SSTL 1 8 The SDQ A 63 0 signals interface to the SDRAM data bus 2X SDM A 7 0 Data Mask SSTL 1 8 When activated during writes the corresponding data groups in 2X the SDRAM are masked There is one SDM bit for every data byte lane SDQS A 7 0 Io Data Strobes SSTL 1 8 For DDR2 SDQS Ax and its complement SDQS_Ax signal 2X make up a differential strobe pair The data is captured at the crossin
164. or Power On Signal default Name Direction S0 State 83 State S4 State Description RJ 45 With LED Connector me f o 05 Downloaded from LpManual com Manuals 55 M230 N B Maintenance gt Infrared Interface Supporting IRDA Format HSDL 3602 288003602002 Fully compliant to IrDA 1 1 physical layer specifications 9 6 Kb s to 4 Mb s operation Typical link distance of 1 0 m Low power operation of 3 3 V Small module size of height 4 0 mm width 12 2 mm depth 5 1 mm Complete shutdown TXD RXD PIN Diode Low shutdown current of 10 nA typical Single Rx data output allowing speed select by FIR select pin Excellent noise immunity with integrated EMI Shield Edge detection input feature preventing the LED from long turn on time Interface to various super I O and controller devices Designed to accommodate light loss with Cosmetic Window 56 Downloaded from LpManual com Manuals M230 N B Maintenance Power On Signal default Name Direction 50 State 3 State S4 State TREC Pomerat V Cap Power off Poweroff Supply 3 Geud found ______ Analog Ground mes m ou Powrot _ L4 1 xl e Powerait Receiver ata s m erin ower ot Trnsmiterpui gt USB Ports FOXCONN USB113C MiTAC 331040004039 Pint Signal s3Stte sis scm L
165. or to ground will be 75 e g 75 Q resistor on the board in parallel with a 75 CRT load BLUE BLUEB Analog Output A This signal is an analog video output from the internal color palette DAC It should be shorted to the ground plane REFSET Resistor Set A Set point resistor for the internal color palette DAC A 255 1 resistor is required between REFSET and motherboard ground HSYNC CRT Horizontal Synchronization 2 5V This signal is used as the horizontal sync polarity is programmable CMOS Jor sync interval 2 5 V output VSYNC CRT Vertical Synchronization 2 5V This signal is used as the vertical sync polarity is programmable 2 5 CMOS V output DDC CLK Uo Monitor Control Clock 2 5V This signal may be used as the DDC_CLK for a secondary CMOS digital display connector DDC_DATA vO Monitor Control Data 2 5V This signal may be used as the DDC_Data for a secondary CMOS _ multiplexed digital display connector 136 M230 N B Maintenance 5 2 Intel 945GM North Bridge 5 Clock Reset and Miscellaneous Clock Reset and Miscellaneous Continued Signal Name Type Description XORTEST Test GTL This signal is used for Bed of Nails testing by OEMs to execute Chain test LLLZTEST Io All Z Test GTL As an input this signal is used for Bed of Nails testing by OEMs to execute XOR Chain test It is used as an output for X
166. orming HW transformation clipping and lighting 2 full vertex processors in the VAP Vertex Assembler amp Processor Motion Video Acceleration Features Video scaling and fully programmable Y CrCb to RGB color space conversion for full screen full speed video playback and fully adjustable color controls Hardware I2C VIP 2 0 with multi channel DMA transfer Front end scaler support for 8 15 16 and 32 bpp color depths Back end overlay scaler supports up to 8x4 tap filtering and always ensures at least 4x2 tap filtering even in extreme cases 4x4 tap 1s typical Back end scaler also supports upscaling and downscaling filtered scaling of all supported YUV formats RGB32 and RGB15 16 and filtered display of images up to 1536 pixels wide MPEG 4 simple profile suppor Adaptive de interlacing filter eliminates video artifacts caused by displaying interlaced video on non interlaced displays by analyzing image and using optimal de interlacing function on a per pixel basis gt Dual Display Features Improved 64 bit display controller with symmetric display capabilities Two triple 10 bit palette DACs DAC and DAC2 with gamma correction for true WYSIWYG color Pixel 40 Downloaded from LpManual com Manuals M230 N B Maintenance rates up to 400 MHz standard Dual RGB CRT output One C Y COMP output plus second RGB CRT output from second DAC Dual displays LCD DVI DVI CRT LCD TV CRT TV etc with completely independent re
167. outed to UHCI USBP7N controller 4 or the EHCI controller NOTE No external resistors are required on these signals The ICH7 integrates 15 pull downs and provides an output driver impedance of 45 which requires no external series resistor OC 4 0 I Overcurrent Indicators OCS5 GP1029 These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred OC7 GPIO31 7 4 may optionally be used as GPIOs NOTE OC 7 0 are not 5 V tolerant USBRBIAS USB Resistor Bias Analog connection point for an external resistor Used to set transmit currents and internal load resistors USBRBIAS I USB Resistor Bias Complement Analog connection point for an external resistor Used to set transmit currents and internal load resistors IDEIRQ IDE Interrupt Request This interrupt input is connected to the IDE drive Downloaded from LpManual com Manuals 143 5 3 Intel ICH7 M South Bridge 6 M230 N B Maintenance Power Management Interface Signals Name Type Description Power Management Interface Signals Continued PWRBTN I Power Button The Power Button will cause SMI or SCI to indicate a system request to go to a sleep state If the system is already in a sleep state this signal will cause a wake event If PWRBTN is pressed for more than 4 seconds this will cause an unconditional transition power
168. posite video with S Video S Video Component video Up to 1024x768 resolution supported for NTSC PAL Macrovision overscan scaling and flicker filtering support Serial Digital Video out Port SDVO interface support Two SDVO ports are muxed with a subset of the external graphics interface using PCI Express architecture signals Each SDVO port support display pixel rates up to 200 MP s 600 MB s Downloaded from LpManual com Manuals M230 N B Maintenance Supports a variety display devices such as DVI TV out LVDS etc Supports hot plug and display Support for HDCP SDVO devices Support for Macrovision on SDVO TV out devices Support for lane reversal Digital LVDS interface support Integrated dual channel LVDS interface supported on display pipe B only Compliant with ANSI TIA EIA 644 2001 spec Supports 25 MHz to 112 MHz single dual channel LVDS LCD interface with support for format of 1x18 bpp for TFT panels with single channel LVDS 2x18 bpp for TFT panels with dual channels LVDS Panel fitting panning and center mode supported Spread Spectrum Clocking SSC supported Panel power sequencing compliant with SPWG timing specification Integrated PWM or dedicated GMBus interface for LCD backlight inverter control Intel Display Power Savings Technology 2 0 support Maximum UXGA panel size supported Maximum WUXGA wide panel size supported Downloaded from LpManual com Manuals M230 N B
169. r frequency select strap setup and hold times around HCPURST This requires strict synchronization between G MCH HCPURST de assertion and the ICH7 driving the straps HDBSY Lo GTL Data Bus Busy This signal is used by the data bus owner to hold the data bus for transfers requiring more than one cycle HDEFER GTL Defer HDEFER indicates that the G MCH will terminate the transaction currently being snooped with either a deferred response or with a retry response Signal Name Type Description HDRDY yo Data Ready GTL This signal is asserted for each cycle that data is transferred HEDRDY Early Data Ready GTL signal indicates that the data phase of a read transaction will start on the bus exactly one common clock after assertion HDINV 3 0 7 yo Dynamic Bus Inversion GTL signals are driven along with the HD 63 0 signals They indicate if the associated signals are inverted or not HDINV 3 0 are asserted such that the number of data bits driven electrically low low voltage within the corresponding 16 bit group never exceeds 8 HDINV x Data Bits HDINV3 HD 63 48 HDINV2 HD 47 32 HDINV1 HD 31 16 HDINVO HD 15 0 HA 31 3 Uo Host Address Bus GTL 31 3 connect to the processor address bus During processor cycles the HA 31 3 are inputs The G MCH drives HA 31 3 during snoop cycles on behalf of DMI and PCI Express initiators HA 31 3 are t
170. ra DMA Intruder Detection is not needed DWSTB This is the command to the IDE device that it may drive data onto the SMLINK 1 0 VOD System Management Link RDMARDYZ DD lines Data is latched by the ICH7 on the deassertion edge of SMBus link to optional external system management ASIC or LAN DIOR The IDE device is selected either by the ATA register file controller External pull ups are required Note that SMLINKO chip selects DCS1 or DCS3 and the DA lines or the IDE DMA corresponds to an SMBus Clock signal and SMLINK1 corresponds acknowledge DDAK to an SMBus Data signal Disk Write Strobe Ultra DMA Writes to Disk This is the data write LINKALERT VOD SMLink Alert strobe for writes to disk When writing to disk ICH7 drives valid data Output of the integrated LAN and input to either the integrated ASF on rising and falling edges of DWSTB or an external management controller in order for the LAN s Disk DMA Ready Ultra DMA Reads from Disk This is the DMA SMLINK slave to be serviced ready for reads from disk When reading from disk ICH7 deasserts RDMARDY to pause burst data transfers Downloaded from LpManual com Manuals 142 5 3 Intel ICH7 M South Bridge 5 M230 N B Maintenance EEPROM Interface Signals Name Type Description EE SHCLK EEPROM Shift Clock Serial shift clock output to the EEPROM EE DIN I EEPROM Data In Transfers data from the EEPROM to the Intel IC
171. ransferred at 2x rate HADSTB 1 0 Host Address Strobe GTL signals are the source synchronous strobes used to transfer HA 31 3 and HREQ 4 0 at the 2x transfer rate HD 63 0 yo Host Data GTL signals are connected to the processor data bus Data HD 63 0 is transferred at 4x rate Note that the data signals may be inverted on the processor bus depending on the HDINV 3 0 signals HHIT yo Hit GTL This signal indicates that a caching agent holds an unmodified version of the requested line In addition HHIT is driven in conjunction with by the target to extend the snoop window Downloaded from LpManual com Manuals 133 M230 N B Maintenance 5 2 Intel 945GM North Bridge 2 Host Interface Signals Continued Signal Name Type Description Host Interface Signals Continued HDSTBP 3 0 HDSTBN 3 0 GTL Differential Host Data Strobes These signals are the differential source synchronous strobes used to transfer HD 63 0 and HDINV 3 0 at 4x transfer rate These signals are named this way because they are not level sensitive Data is captured on the falling edge of both strobes Hence they are pseudo differential and not true differential Strobe Data Bits HDSTBP3 HDSTBN3 HD 63 48 HDINV3 HDSTBP2 HDSTBN2 HD 47 32 HDINV2 HDSTBP1 HDSTBN1 HD 31 16 HDINV1 HDSTBPOZ HDSTBNO HD 15 00 HDINVO Signal Name Type
172. s One activation source can trigger a number of data transfers chain transfer Direct specification of 16 Mbyte address space is possible 23 Downloaded from LpManual com Manuals M230 N B Maintenance Activation by software is possible Transfer can be set in byte or word units A CPU interrupt can be requested for the interrupt that activated the DTC Module stop mode can be set gt 16 Bit Free Running Timer FRT Selection of four clock sources Two independent comparators Four independent input capture channels Counter clearing Seven independent interrupts Special functions provided by automatic addition function 8 Bit PWM Timer PWM Operable at a maximum carrier frequency of 625 KHz using pulse division at 10 MHz operation Duty cycles from 0 to 100 with 1 256 resolution 100 duty realized by port output Direct or inverted PWM output and PWM output enable disable control Downloaded from LpManual com Manuals 24 M230 N B Maintenance gt 14 Bit PWM Timer PWMX Division of pulse into multiple base cycles to reduce ripple Two resolution settings Two base cycle settings Four operating speeds Four operation clocks by combination of two resolution settings and two base cycle settings 8 Bit Timer TMR Selection of clock sources Selection of three ways to clear the counters Timer output controlled by two compare match signals e Cascading of TM
173. s maximum safe operating temperature This indicates that the processor Thermal Control Circuit has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled TCC will remain active until the system deasserts PRCCHOT By default PROCHOT is configured as an output only Bidirectional PROCHOT must be enabled via the BIOS This signal may require voltage translation on the motherboard Processor Power Status Indicator signal This signal is asserted when the processor is in a lower state HFM and LFM and lower state Deep Sleep and Deeper Sleep PWRGOOD PWRGOOD Power Good is a processor input The processor requires this signal as a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout the boundary scan operation REQ 4 0 TO REQ 4 0 Request Command must connect the appropriate pins both FSB agents They are asserted by the current bus owner to the currently active transaction type These signals
174. self test is passed Graphic Controller Test Error LCD No Display Connect the I O device amp cable to the M B one at a time to find out which part is causing the problem 1 Confirm LCD panel is good and check the cables are connected properly 2 Try another known good LCD module Replace Motherboard Board level Troubleshooting Yes Display OK One of following parts on the mother board may be defective use an oscilloscope to check the following Replace faulty Remove all the I O signal or replace the parts one at a time and test after each monitor device amp cable from replacement motherboard except LCD module Parts Signals U13 Vsys BLADJ U503 LCD DVMAIN BKL TXCLK LCD_SM_CLK TXCLKB LCD_SM_DATA Replace the faulty TXOUT 0 2 TXOUT 10 12 VO board TXOUTB 0 2 TXOUT 20 22 DDCPCLK TXOUTCLK1 DDCPDATA TXOUTCLK2 H8SMB CLK H8SMB DATA Is motherboard and I O board connected properly No b Reconnect it Try another known good I O board 169 Downloaded from LpManual com Manuals M230 N B Maintenance 8 3 Graphic Controller Test Error LCD No Display 2 There is no display or picture abnormal on LCD although power on self test is passed 0524 Vsys
175. serts PLOCK when it performs non exclusive transactions on the PCI bus PLOCK is ignored when PCI masters are granted the bus in desktop configurations SERR VOD System Error SERR can be pulsed active by any PCI device that detects a system error condition Upon sampling SERR active the ICH7 has the ability to generate an NMI SME or interrupt PME VOD PCI Power Management Event PCI peripherals drive PME to wake the system from low power states 51 55 PME assertion can also be enabled to generate an SCI from the SO state In some cases the ICH7 may drive PME active due to an internal wake event The ICH7 will not drive PME high but it will be pulled up to VecSus3_3 by an internal pull up resistor Name Type Description SATAOTXP Serial ATA 0 Differential Transmit Pair SATAOTXN These are outbound high speed differential signals to Port 0 SATAORXP I Serial ATA 0 Differential Receive Pair SATAORXN These are inbound high speed differential signals from Port 0 SATAITXP Serial ATA 1 Differential Transmit Pair SATAITXN These are outbound high speed differential signals to Port 1 SATAIRXP I Serial ATA 1 Differential Receive Pair SATAIRXN These are inbound high speed differential signals from Port 1 SATA2TXP Serial ATA 2 Differential Transmit Pair SATA2TXN These are outbound high speed differential signals to Port 2 SATA2RXP I Serial ATA 2 Differential Receive Pair SATA2RXN These are inbound h
176. solution refresh rates h w icon amp h w cursor and display data Hardware cursor up to 64x64 pixels in 2 bpp full color AND XOR mix and full color 8 bit alpha blend Primary display supports VGA and accelerated modes video overlay and hardware cursor Secondary display supports TV out or CRT It supports accelerated modes video overlay and hardware cursor however it does not support VGA Modes supported include 800x600 and 16 9 modes such as 848x480 with user flexibility for moving and sizing the screen MPEG 4 simple profile support Support for up to 4 K x 4 K resolution display gt Digital Display Support Support for fixed resolution displays e g panels from VGA 640x480 to wide UXGA 1920x1200 resolution with full ratiometric expansion ability for source modes up to 1400 x 1050 with standard display timing or up to 1920x1440 with reduced blanking timing Higher resolution panels and digital CRTs may be possibly supported contact ATI for details Improved auto expansion Optional auto centering mode to display desktop at native size without ratiometric expansion Support for VGA text modes in centering panel modes up to approximately 165 MHz pixel frequency 41 Downloaded from LpManual com Manuals M230 N B Maintenance Support for reduced blanking intervals as defined by VESA gt Bus Support Features PCI Express 1 0a and PCI Express 1 1 compliant PCI Express is the latest generation I O interconnect arch
177. special code Initialize PIC and DMA Initialize Memory type Initialize Memory size Shadow Boot Block System memory test Initialize interrupt vectors Initialize Run Time Clock Initialize video Initialize System Management Mode Output one beep Boot to Mini DOS Clear Huge segment Boot to Full DOS 159 M230 N B Maintenance 8 Trouble Shooting 8 1 No Power 1 8 2 No Display 2 8 3 VGA Controller Test Error LCD No Display 8 4 External Monitor No Display or Color Abnormal 8 5 Memory Test Error 8 6 Keyboard K B or Touch Pad T P Test Error 8 7 Hard Disk Drive Test Error 8 8 CD ROM Test Error 8 9 USB Port Test Error 8 10 Audio Test Error 8 11 LAN Test Error 8 12 1394B Test Error 8 13 Mini Express wireless Socket Test Error D O0 D D D D D D 8 14 PCMCIA Socket Test Error Downloaded from LpManual com Manuals 160 M230 N B Maintenance 1 No Power Definition Base on ACPI Spec We define no power as while we press the power button the system can t leave S5 status or none the PG signal send out from power supply Judge condition gt Check whether there are any voltage feedback control to turn off the power gt Check whether no CPU power will cause system can t leave S5 status If there are not any diagram match these condition we should stop analyzing the schematic in power supply sending out the PG signal If yes we should add the effected analysis into no power chapter 2
178. st Phase In the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request In the second half the signals carry additional information to define the complete transaction type Downloaded from LpManual com Manuals Note Unless otherwise noted the voltage level for all signals in this interface is tied to the termination voltage of the Host Bus VTT 134 M230 N B Maintenance 5 2 Intel 945GM North Bridge 3 DDR2 DRAM Channel A Interface DDR2 DRAM Channel A Interface Continued Signal Name Type Description SDQS_A 7 0 VO Data Strobe Complements SSTL 1 8 These are the complementary DDR2 strobe signals 2X SCKE_A 3 0 Clock Enable SSTL 1 8 1 per Rank SCKE Ax is used to initialize the SDRAMs during power up to power down SDRAM ranks and to place all SDRAM ranks into and out of self refresh during Suspend to RAM SODT A 3 0 On Die Termination SSTL 1 8 Active On die Termination Control signals for DDR2 devices DDR2 DRAM Channel B Interface Signal Name Type Description SCLK A 5 0 SDRAM Differential Clock SSTL 1 8 3 per DIMM SCLK and its complement SCLK_Ax signal make a differential clock pair output The crossing of the positive edge of SCLK Ax and the negative edge of its complement SCLK_Ax are used to sample the command and contr
179. t Differential Pair EXP TXP 15 0 PCIE EXP ICOMPO I PCI Express Output Current and Resistance Compensation A EXP COMPI I PCI Express Input Current Compensation A Unless otherwise specified PCI Express signals are AC coupled so the only voltage specified is a maximum 1 2 V differential swing Downloaded from LpManual com Manuals Signal Name Type Description RED RED Analog Video Output A This signal is a CRT Analog video output from the internal color palette DAC The DAC is designed fora 37 5 routing impedance however the terminating resistor to ground will be 75 e g 75 Q resistor on the board in parallel with a 75 Q CRT load RED REDB Analog Output A This signal is an analog video output from the internal color palette DAC It should be shorted to the ground plane GREEN GREEN Analog Video Output A This signal is a CRT Analog video output from the internal color palette DAC The DAC is designed for a 37 5 routing impedance however the terminating resistor to ground will be 75 e g 75 Q resistor on the board in parallel with a 75 O CRT load GREEN GREENB Analog Output A This signal is an analog video output from the internal color palette DAC It should be shorted to the ground plane BLUE BLUE Analog Video Output A This signal is a CRT Analog video output from the internal color palette DAC The DAC is designed fora 37 5 routing impedance however the terminating resist
180. t of the Intele ICH7 All PCI Express graphics attach output signals will also tri state compliant to PCI Express Specification Revision 1 0a This input should have a Schmitt trigger to avoid spurious resets This signal is required to be 3 3 V tolerant PWROK I Power OK HVIN When asserted PWROK is an indication to the G MCH that core power has been stable for at least 10 us EXTTS I External Thermal Sensor Input CMOS This signal may connect to a precision thermal sensor located on near the DIMMs If the system temperature reaches a dangerously high value then this signal can be used to trigger the start of system thermal management This signal is activated when an increase in temperature causes a voltage to cross some threshold in the sensor EXP EN I PCI Express SDVO Concurrent Select CMOS 0 Only SDVO or PCI Express operational 1 SDVO and PCI Express operating simultaneously via PCI Express port NOTES For the 82945P MCH this signal should be pulled low EXP SLR I PCI Express Lane Reversal Form Factor Selection CMOS GMCH s PCI Express lane numbers are reversed to differentiate Balanced Technology Extended BTX or ATX form factors 0 G MCH s PCI Express lane numbers are reversed BTX Platforms Normal operation ATX Platforms ICH SYNC Z ICH Sync HVCMOS This signal is connected to the signal on the ICH7 Downloaded from LpManual com Manuals 137 5 2 Intel 945G
181. tates on standby suspend and off defined for the OnNow architecture Each power state can be achieved by software control bits Clocks to every major functional block are controlled by a unique dynamic clock switching technique which is completely transparent to the software By turning off the clock to the block that is idle or not used at that point the power consumption is significantly reduced during normal operation gt Internal LVDS Spread Spectrum Support The M54 M32 spread spectrum controller is capable of generating a triangular frequency modulation profile The amount of spread and the modulation frequency is fully programmable Only the LVDS display is available to be spread i e 1 PLL gt External Spread Spectrum Support Memory and or core clock spread spectrum support via the GPIO16 pin External spread spectrum supported for TMDS or LVDS transmitters via the GENERICC GENERICD pin 43 Downloaded from LpManual com Manuals M230 N B Maintenance gt PC Design Guide Compliance Fully compliant with Windows Logo program requirements for all target Operating Systems This includes both the current Logo requirements and the future draft requirements that will be enforced during the lifespan of the product Fully compliant with Mobile PCI rev 1 0 Bi endian support for compliance on a variety of processor platforms gt Test Capability Features Full scan implementation on the digital core logic whi
182. tenance gt D A Converter 8 bit resolution Two output channels Conversion time Max 10 us when load capacitance is 20 pF Output voltage 0 V to AVref D A output retaining function in software standby mode gt ports Ten I O ports ports 1 to 6 8 9 A and B and one input only port port 7 gt Interrupt Controller Two interrupt control modes Priorities settable with ICR ndependent vector addresses Thirty one external interrupts DTC control Downloaded from LpManual com Manuals 29 M230 N B Maintenance Power Down Modes Medium speed mode Subactive mode Sleep mode Subsleep mode Watch mode Software standby mode Hardware standby mode Module stop mode Downloaded from LpManual com Manuals 30 M230 N B Maintenance 1 2 1 7 Super I O SMSC SIO10N268 gt 3 3 Volt Operation 5 Volt Tolerant gt 99 PCOI ACPI 1 0 Compliant gt LPC Interface Design X Bus Interface LPC Mode Only Three chip selects Two I O and one memory 8 Bit data transfers Support for up to 2 MB flash Interfaces with 3 V memory devices Support for up to two external I O components Offers three modes of operation for I O devices Provides FWH emulation gt Serial IRQ Compatible with Serialized IRQ Support for PCI Systems gt Programmable Wake up Event PME Interface gt 33 General Purpose Input Output Pins gt System Management Interrupt Downloaded from
183. the ICH7 is a target and an input when the ICH7 is an initiator C BE 3 0 T O Bus Command and Byte Enables The command and byte enable signals are multiplexed on the same PCI pins During the address phase of a transaction C BE 3 0 define the bus command During the data phase C BE 3 0 define the Byte Enables C BE 3 0 Command 0000b Interrupt Acknowledge 0001b Special Cycle 0010b TO Read 0011b I O Write 0110b Memory Read 01115 Memory Write 1010b Configuration Read 1011b Configuration Write 1100b Memory Read Multiple 1110b Memory Read Line 1111b Memory Write and Invalidate All command encodings not shown are reserved The ICH7 does not decode reserved values and therefore will not respond if a PCI master generates a cycle using one of the reserved values PAR vo Calculated Checked Parity PAR uses even parity calculated on 36 bits AD 31 0 plus 3 0 Even parity means that ICH7 counts the number of one within the 36 bits plus PAR and the sum is always even The ICH7 always calculates PAR on 36 bits regardless of the valid byte enables The ICH7 generates PAR for address and data phases and only guarantees PAR to be valid one PCI clock after the corresponding address or data phase The ICH7 drives and tristates PAR identically to the AD 31 0 lines except that the ICH7 delays PAR by exactly one PCI clock PAR is an output during the address phase delayed on
184. to the G MCH that it is OK to close the DRAM page of the memory read request with which the hint is associated The G MCH uses this information to schedule the read request to memory using the special AutoPrecharge attribute This causes the DRAM to immediately close Precharge the page after the read data has been returned This allows subsequent processor requests to more quickly access information on other DRAM pages since it will no longer be necessary to close an open page prior to opening the proper page is asserted by the requesting agent during both halves of Request Phase The same information is provided in both halves of the request phase HSCOMP Slew Rate Compensation This is the compensation signal for the Host Interface HSWING Host Voltage Swing This signal provides the reference voltage used by FSB RCOMP circuits HSWING is used for the signals handled by HRCOMP HDVREF Host Reference Voltage Voltage input for the data address and common clock signals of the Host GTL interface HACCVREF gt gt gt S un Host Reference Voltage Reference voltage input for the Address and Common clock signals of the Host GTL interface HREQ 4 0 GTL Host Request Command These signals define the attributes of the request HREQ 4 0 are transferred at 2x rate They are asserted by the requesting agent during both halves of Reque
185. ual com Manuals 13 J507 I O Board 106 B x 2 A 1 Ps 1505 lt 1207 100 1501 J503 8 Y Y 2165 1 MICI VREFO Ig L L504 2 2 i I CHE 010 1207100 2 MIC L505 MICE 600Z 100M 516 10 MIC T CY Ve MICI R C511 1U MIC N Y Y U8 B L503 J503 6002 100 SN74LVC1G3157 MIC MIC P25 P25 P 5 Connector 5V CODEC MIC MIC N 3 R531 P26 20K C505 X BAY Pie 0 LINE_IN_L R533 0 Pis R511 0 LINEIN_L lt e m e m Connector C504 LINE IN 8507 0 U501 R505 2K 0 LINEIN R IN VO2 LM4890 R506 100K AGND CDR 513 lU CDROM R R6 0 CDR 1 Dc C521 10 CD COMM CDROM L R7 0 CDL 2 CD ROM Connector CDL C517 10 CDROM COMM R23 0 CD COMM 4 R17 100K AGND M230 N B Maintenance 8 10 Audio Test Error 3 Audio Out No sound from speaker after audio driver is installed SPKROUT 150 Internal Speaker SPKROUT R Connector SPKLOUT 1505 T
186. ust connect the appropriate pins of both FSB agents TRST I TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset Vee I Processor core power supply Veca I provides isolated power for the internal processor core PLL s Processor Power Supply VID 6 0 VID 6 0 Voltage ID pins are used to support automatic selection ofl power supply voltages Vcc Unlike some previous generations of processors these are CMOS signals that are driven by the Intel Pentium M processor The voltage supply for these pins must be valid before the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID pins becomes valid The VID pins are needed to support the processor voltage specification variations The VR must supply the voltage that is requested by the pins or disable itself Downloaded from LpManual com Manuals CPU Pin Description Continued Signal Name Type Description Vsssense Vsssense together with Vccsense are voltage feedback signals to IMVP6 that control the 2 1m loadline at the processor die It should be used to sense ground near the silicon with little noise 132 M230 N B Maintenance 5 2 Intel 945GM North Bridge 1 Host Interface Signals Signal Name Type Description Host Interface Signals Continued HADS Lo GTL
187. version VGA BIOS plug amp play System BIOS ACPD 0 capability Boot from IDE amp SATA devices USB CD ROM USB FDD Standard 256 MB Options 512 1 2 GB Maxsystem memory of2 GB in 2 slots Supports 400 533 MHz DDR2 devices 2 DDR2 SO DIMM 200 pin Integrated in 945GM chipset Intel GMA 950 graphic controller VGA Controller Optional ATI M54 CSP VGA controller with 128 MB memory Dual view function LCD CRT simultaneous display capability 14 1 TFT XGA 1024 x 768 SPWGtype 14 1 LCD Display 15 0 TFT SXGA 1400 x 1050 SPWG type 15 0 LCD Optional Factory optional touch screen Factory option Hi Contrast solution for 14 panel only 3 spindle Video Memory Shared system memory 64 MB Standard Serial ATA 60 GB up to 120 GB 5400 or 7200 rpm Factory optional HDD heater for low temperature 20 C 55 C support Optional low temperature 20 GB HDD without HDD heater Downloaded from LpManual com Manuals M230 N B Maintenance Continue to the previous page Built in design to support operating mode free drop from 0 to 3 feet heigh 1 3 feet Protected by G sensor 0 1 foot Protected by special construction resistance design Water proof membrane keyboard Factory optional water proof rubber keyboard Factory optional back light rubber keyboard Pointing Device A sensitive control touch pad capacitance type Optional water proof resistance type Type II x2 Card Bus support

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