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MC-12/MC-12 Balanced Service Manual

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7. MC 12 MC 12 Balanced Service Manual Your Notes 8 26 Lexicon 8 27 D T e v 9 8 8 D mms 66 82 72 SX 3 Ir fe 659 T 090 sg e saco azts 66 92 44 5 T ISOH IXS 5 65 92 72 waa coi da NIVW WSHOS pi 886 E23 uM TES RSS REST WW ory HOO L X9 D 4 ara 14 SEL aasa 001 ava ssi wa Te SOS wT So
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10. koci T e v S L 8 5 2 cas rs ezocc oo et t ex 8 wo 090 g 00 et t ammo b NAAA TALS DNAS e6 t et HM m OO TXO E ymo SEA SSA T z p son S ies st esovonsz Y Me HENHOLSEN 0 91 x 5 PHA jm jue T 2 zsxcos AAS MAS 0 pea 1 1 osi seo 0199 894 osi EM 100 02 GND TOR Treo Em TT 182 51 gr i00 0av xor 44056 ARI xor 3 5 198 gz roc B mon so LTT 4 1 SvAs 2 SSA ey SSA SUA nas 2001 n yp TO 817z 11971172 E 19 am 9 5 Lis ux p 2052277075 vou rai T oza 8 T pe tori 0 6 9 51 T 069 LET n fati OL iz v ra 5 i T
11. INTERRUPTS 2 7 0 ZWAIT gt 2180 ZD 7 0 HOST PROCESSOR SRAM CONTROL MEMORY Z CTRL BOARD 2180 CONTROL SRAN HOST INTERFACE FPGA PROGRAM RESETS STANDBY BUTTON MEMORY EPROM ENCODER INTERFACE MEMORY CPLD FLASH ROM HOST PROCESSOR BLOCK BOARD 2180 schematic 2180 is responsible for all systems control in the unit It runs off the 29 491 2 crystal oscillator It is reset by the main PWR RST signal ZCLK is a buffered synchronous clock output that is used to synchronize signals in the Memory CPLD and the 1 FPGA One half of a VHCT244 is used to buffer ZA 3 0 to the DAR FPGA because of the length of signal trace Memory CPLD schematic page1 The Memory CPLD is programmed at the factory like an EPROM It can be programmed before or after it is soldered to the PC board It provides the following functionality Host data address and control interface provides all memory space address decoding plus a small section of I O space that is occupied by the Memory CPLD internal control and status registers SRAM read write signals and bank address bit Flash ROM and EPROM control signals and bank address bits RA 22 15 The FPGA programming bits Reset lines under host control to the Video Board Analog Board FPGA and Front Panel Board The Standby LED The St
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14. SHARC SHARC DSP CLOCKS amp AUDIO bdo spiel DATA C D SHARC SHARC DSP C D CLOCKS amp AUDIO nee gt I O OAS C D TO DSPD SDO gt 1 OCTALIN 4 STEREO OUT MAIN_DAC 0 5 _SDI gt ER MAIN AUDIO PATH AUDIO FPGA BLOCK Main Audio Clock Path schematic pages 4 16 17 18 There are three possible sources of master clock for the Main Audio Path The 22 5792MHz crystal oscillator that provides either a 44 1kHz or 88 2kHz sample rate the 24 576 oscillator that provides either a 48kHz or 96kHz sample rate or the master clock output of the main digital receiver In practice the unit runs off the crystal at 96 2 when the input is analog When the input is digital the master clock output of the digital receiver is used This master clock is de jittered by the Phase Lock Loop that is controlled by the DAR FPGA using signals derived from MAIN DRCVR MCKO Depending on the input selected the appropriate master clock is routed from the DAR FPGA to the Audio FPGA Here it drives a clock tree that divides down the master clock which is 256 times the sample rate 256FS to create the other clock rates required The SHARC DSPs receive a word clock or framing signal FS and a bit clock of 256FS e The Digital Receiver uses a word clock FS and bit clo
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20. 5 aaost 69 AST 57 566 54 e 1662 orra 1598 2 SEE SUME 11075871 i jt Ed 1076271 1073277 5 E d posene A Eus 4 k 8660 7 M E oo ozttoo BM 907575 0078275 6 ssaa 5276275 0072276 9 4 00 6 8000 ama ast ast eos rem wast ans 910 amavan NOISNHANOO SNOISIARE T 4 v 9 L 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 78 Lexicon 86821 00 T e v 9 9 8 11 69981 00 2 8 ass 00 2 5 2 0 t
21. e v 9 L 8 a s 65 6996 00 2 6 av cans 8 mi E P iP 90 E wenn saco azis 00 2 5 44 amomo 100 00 2 8 O I SINY WHHDS aun 06410 1 Nd v Bota aast ast za 1 U 52 4 6n 1 Wore WVAW u n suzao 400 5 Y inoomg 68 81 ase oA inooms 49 801 LIU ing IE aes 1 Rem mer umo 478 69 E ws mods pm Y 5 ID OA 11008 aast myhy ESI A org oteeso Jer p AST 99TA 62 5 8 e019 52 4 50 180 0 6 WAT T susto saso D 1 TUI as en aste vast HAST 104100 ast 4 8 Qu za sH 490 9 700 81 e F m atoe Y sut aast 1 asa i anoa 4 occu s T AST 4 4 asooez aaoozz Tezo 15
22. 10 52 9 00 180109 na aut 1 16891 0808 335 gt 9 ASSY SNOISIA3H 2 v 9 L 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 162 Lexicon xl SALON 8 163 30 2 Zi wes wA aanss TWS 108 00 065 1 080 wo Em E TE cu D BEER 09 405 8 2 uo xo 09 405 SISSVHO ASSV 37 21 06591 3me ui 0002 avoy 1 145 A18W3ssv 40 OL SISSVHO NL 318W3SSV nc ZL W X04 1 IHS 335 72 151 1494 IHS 335 1 0 405 8cL OW MHOM33 Q8 581 2 1 300301 5914 82 AWO 09 445 8 1 130 Sf 08 NIVW WOLLOS SISSVHO SNIN3dO NYHL NAVI 0334 581 9 sold 2 CHA 310N S8Y NI 01 8 30001 5214 SISSvHO 30 ex 107472 2 owo una x x SNOISIAH MC 12 MC 12 Balanced Service Manual Your Notes 8 164
23. MC 12 MC 12 Balanced Service Manual Your Notes 8 86 Lexicon 8 87 T e v 9 L 8 oz 5 699 00 2 5 anssi 8 7 P E e szis 00 2 5 5 Sindino saIS ens 007275 E O I S INV HiHOS S P 14 180 67 lt UIS sta 4 lt sezao m unowa 404 110 8 xot H 47 81 100 LHOIN eza m w Wei EM stes 980 T rr 488 801 ezo oeta E 498 00 dnd os omg ast octo OA AORTA ans xor 4 4 Tp 978 1 aaost 22 sta un 4 T is au HONE wa oor i T 1 ino mar
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29. 1 8 2131 Q8 140 Too TX of 25 02 sn 44 R46 CP3B R2 242 R1 142 22 Oos 8 139 MC 12 MC 12 Balanced Service Manual Your Notes 8 140 Lexicon 130 1 133 5 1 I IN3NOdWO2 2 104 Q8 Od Y N 31 25 9085 Quim V BB s 021 9 EL EL EL EL En E sr 9r gr B 2
30. 8 149 MC 12 MC 12 Balanced Service Manual Your Notes 8 150 Lexicon 140 1 133 5 V N 31 25 2 IN3NOdNOO awl 8 21 48 8 151 9 FC HH AA vin mI 12 ain MC 12 MC 12 Balanced Service Manual Your Notes 8 152 Lexicon 1401 133H Y N 37725 2 1 04 8 210N 48 AGGNVIS LNANOdNOD E X 9 185 ANDR VN 110 lt 8 153 MC 12 MC 12 Balanced Service Manual Your Notes 8 154 Lexicon 1 40 1 133 5 Y N 31 25 1 LNANOdWOD 4 213 04 AYOWANW VER e 8 155 8 ou 12 91 So mE 25 Qe LYZ 107 201 158 107 25 AQU ASSCOLTE LUN ozvy en m 0000 590099 eyo X L o INN lt lt lt M SE MC 12 MC 12 Balanced Service Manual Your Notes 8 156
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32. vos 222100 amv oo sozToo 30787711 90712711 DOE 00717 E xoa 2575275 597576 9079275 0072276 x d uN coss 55 NOLIATHOSEG SNOTSTARE T 4 v 9 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 116 Lexicon 8 117 T c S 9 8 2 ee Lz ot ex 8 Een zm 8 090 66 42 01 ex 5 ligo 66 12 01 cis 8 GNI MS T on Sui
33. _ n Y OXOW NIVW ed 501418 NIVW AINIS EEA NINH SOLES ASH NIV 153 HAONI NIVW IT SENIOd 188 22 BH sL en xec y ume vx zia senva iL 1 958 z T 1 Tout Wet 28 1691 93 7 ws gs 2 gi TO LZZTOO zat 7 e SHION 855 17 V vODOHPL vODOHPL 66776781 767 1T sup wo ie E 00 26000 Gates Tm 907575 007273 aee were xu y sm vos x 4 8 21 6628 0071 00 61 s 00 78 m EAE EE BOT RT Haw coss 20 sauvaa m 5 S 9 L 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 44 Lexicon 60 5 1002 21 2
34. SX Bang more 5 Savaa LSOH Deng sxaor 99 T 08008 Dc sy waT oa Sor 02 Mit Teor E ie sas E 2 TEIL waisines 1808 evasa THO SALIM LSOH vole ss NIST 4 he savaa asa Steuer Sr uis asd 5 oro ae 190 02 Tor Erin Sor AS EISSA 8 tre vasa quie omen mra o vasa 3 SX ESE sxsarel SV 10 41 AXES was evasa Sue woe _avasa ev ww SVdSd a wT we 15 s sin 52 abet evasa SPP ur ee ar ava i2 Era 5213 sc 009 DUI iE m 0 Era 10 ERES homi cmm 224 S SRI 30 2 98 SYST
35. PROGRAM 3 ee DAR FPGA DAR Ni BERGE PROGRAM FPGA gt FPGA PROGRAM ANLG FPGA ANALOG PROGRAM PINS PROGRAM FPGA MEMORY CPLD FPGA FPGA PROGRAMMING FPGA schematic page 2 The FPGA has only a four bit wide data path for the host interface It provides the following functions Handles the entire space memory map for the system Generates the chip selects for all peripheral devices that the host communicates with over the data bus Automatically generates wait states to the Host for devices that require longer access times Outputs the bits that are used to program the other FPGAs in the system Provides the host side of the Host DSP communication interface MC 12 MC 12 Balanced Service Manual 2180 HOST INTERFACE CHIP SELECTS HOST WAIT STATES CONTROL STATUS CHIP SELECTS AUDIO FPGA PROGRAM DAR FPGA PROGRAM ANLG FPGA PROGRAM DSP CONTROL INTERFACE FPGA Audio FPGA schematic page 4 The Audio FPGA is the central audio routing block for the system It performs the following functions e Generates word and bit clocks for each zone from the master clocks and distributes them to all audio devices and interfaces on the Main Board Routes all 125 audio data the system Packs and unpacks 25 audio into octal streams for the SHARC DSPs Provides interrupts to the SHARC and Crysta
36. BIRT m MT 38878 1 0 ve vi SN IY 1S4 aosi SA 19 91 SN 12088 ee ON Vt 9 090 WOO S5 TSE Ea pd we ow 9579064 202 29008859 982701 207911 tan 4 T T T E 589 J zssatao SINALNO MODTA 5 107677 mx ex Tore 170171 E TO LZZTOO DOTEL ET 0076 TET ex ex 75712727 5576717 gu E 00 426000 907279 007279 9971 8 9976176 is 00 000 aia 270 SNOISTARE MC 12 MC 12 Balanced Service Manual Your Notes 8 50 Lexicon 8 51 z S 9 L 8 5 9 rms 66 82 2 SX 3 3 66 12 72 wo SA EE 659 1 090 a 3H OROD saco 66 9t L ammo 2 51404 06054 WHMOd
37. IS 650 735 450 21 66 4 2802 zeaz zeaz 2 7_ 002802 sa 59 ea cv za c 1 amp X v LN 61 La t1 La c oa z IW as EET S2 014 280 cag tur so tua Sv 54 35 ta 19 Ta e sv 0 L d cad UV 2802 4 u whe 9 91 20 9 760 0 Ux v lt TIS TET i PEN TN 2887 180 91 um NN ag or 098 91 TY 5 TE mw se z v ea z va 1i UV TT TV vuv TW ead TW Ei ZH 510 Sw En SY ZH SV zaq 6 VVELOHATL 10 51 Do er v zaa
38. COAX x6 COAX 1 6 DRCVR NRZI MAIN DRCVR MAIN_DRCVR_SDO gt LN OPTO DAR RECORD AUDIO x6 OPTO 1 6 FPGA I REC DRCVR NRZI DRCVR I REC DRCVR 500 0 FPGA V AES ZONE XLR XLR I ZONE DRCVR NRZI DRCVR I ZONE DRCVR SDO DIGITAL AUDIO INPUT PATH 6 14 Lexicon Main Audio Data Path schematic pages 4 5 6 11 and 17 The Main Audio Data Path is as follows Output of the Main Digital Receiver and the Main ADC to the Audio FPGA Output of the Audio FPGA to the Crystal 49326 Decoder 4 2 channel outputs from the Crystal 49326 Decoder back to the Audio FPGA The 4 2 channel streams are packed into a single octal data stream in the Audio FPGA The output of the octal packer is sent to SHARC A The octal output of SHARC B is sent back to the Audio FPGA The octal output of the Audio FPGA is sent to SHARC C Two octal outputs of SHARC D are sent back to the Audio FPGA The two octal outputs of SHARC D not all slots are used are unpacked into 6 2 channel PCM streams in the Audio FPGA 10 These 6 2 channel streams are sent to the Analog board as MAIN DAC 0 5 SDI MAIN SDO CRYSTAL CRYSTAL DECOER 549326 r DECODER 01 49326 AUDIO CLOCKS amp DATA DECODER MAIN SDO DECODER 5 0 3 4 STEREO IN TO 1 OCTAL OUT
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40. 6306 4 i Sasa TORING e s 40 194 6 84 21 var ONAS v 6400 j it 4 T 9985 or ER RE ES 1 Cu t 6 3O S a a6 Y 06 6406 1 o i oe i Me OILS Ls xoor UII ROSE SINANI SLISOdWOD p 51551 050 E TOW 47 1 4 Tug n d x 4 T DER 4 1 2 M ggg 82 6 sci T z ove lo 67 9 vms o 1 9 s rms y ems aue s eof ete Y rov c ca 1 so ea t s aast 2 rms 8876 mast 6ta WM LAN STZA vus 84 6 50 11 ser ye see vad LG L9TO NO GASO SWOLVNDISGG i 139HS SALONGA Us
41. REC DXMTR RECORD MCKO FROM ANALOG REC ADC SDO RECORD BOARD DIGITAL REC DXMTR FSI RECORD XMITTER REC DXMTR SCKI M REC DXMTR MCKL DIGITAL CLOCKS DXMTR SDI XMITTER amp DATA RECORD DRCVR TO CLOCK amp DRCVR DIGITAL DATA m RCVR RECORD REC ANLG FSI 9 ANALOG REC ANLG gt ANALOG CLOCKS amp REC DAC SDI DATA RECORD AUDIO CLOCKS amp DATA PATH AUDIOS Zone 2 Audio Clock and Data Paths schematic pages 4 and 16 18 The Zone Audio Data Path is as follows 1 Output of the Zone Digital Receiver and the Zone ADC to the Audio FPGA 2 A2 channel stream is sent to the Analog board as ZONE DAC SDI This stream is either the output of the Zone ADC the Zone Digital Receiver or a 2 channel down mix of the Main Audio content There are three possible sources of master clock for the Zone Audio Path The 22 5792 2 crystal oscillator that provides either a 44 1kHz or 88 2kHz sample rate the 24 576MHz oscillator that provides either a 48kHz or 96kHz sample rate or the master clock output of the Zone digital receiver In practice the unit runs off the crystal at 96kHz when the input is analog When the input is digital the master clock output of the digital receiver is used Depending on the input selected the appropriate master clock is routed from the DAR FPGA to the Audio FPG
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46. R AUX DATA IR AUX IR IR ACK LED gt IR LED gt RECEIVER 4 IR DATA lt ____ 0 1 pem ENCODER 01 E ENCODER FRONT PANEL SWITCH LED BOARD CONNECTOR PNE FRONT PANEL IR ENCODER I R ENCODER 8 OSD BOARD ANALOG BOARD schematic page 12 The analog board has the following interface e FPGA programming bits Host I O data bus Host I O address bus Host I O control RD WR and CS Reset 4 MHz clock used on the analog board to derive serial control clocks Main audio clocks and data Record audio clocks and data Zone 2 audio clocks and data 6 8 FPGA PROGRAM HOST IO DATA BUFFER DBA DATA HOST ADDRESS DBA ADDR BUFFER 4O RD WR ANALOG CHIP SELECT 4 MHZ SERIAL CONTROL CLK MAIN AUDIO CLOCKS MAIN DAC DATA ZONE AUDIO CLOCKS ZONE DAC DATA RECORD AUDIO CLOCKS RECORD DAC DATA RESET I MAIN ADC DATA ADC DATA I RECORD gt ANALOG BOARD ANALOG BOARD INTERFACE CONNECTOR OPTION BOARDS schematic pages 13 15 The option board connectors have the follo
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90. 00702701 00702707 a ex 0072 01 o0 t1 0T 10 6 6000 wad 9070779 00701 a 00 02000 20 SNOISTARE 8 123 MC 12 MC 12 Balanced Service Manual Your Notes 8 124 Lexicon 8 125 8 S 9 1 d amp 0 62 6 9X 0 6 Mo 090 a um PP ewe 00 8276 44 amomo roe 5 00 61 6 me Ast SZI OW OH W IX WSHOS sz Lv 1 AT m atoe aun 30
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92. Analog FPGA Record Clock and Data Inputs Record Outputs REC AD A D Master clock 12825 96k REC AD 5 1 A D Serial data clock 64FS REC AD LRCK Word clock FS REC DAC MCLK D A Master clock 256FS REC 5 D A Serial data clock 64FS 6 27 MC 12 MC 12 Balanced Service Manual REC DAC LRCK D A Word clock FS REC DAC DATA D A 15 data Analog FPGA Record Clock and Data Outputs Record Inputs ZON2 ANLG MCK Master clock input 256FS ZON2 ANLG FS Word clock input 64 5 ZON2 ANLG SDI Zone 2 DAC l S data Analog FPGA Zone 2 Clock and Data Inputs Analog FPGA Zone 2 Clock and Data Outputs CONTROL REGISTERS AND MAIN BOARD CONNECTOR schematic sheet 18 Seven discrete 74HC273 control registers are located on the board The Z180 writes to them via the 8 bit data bus D 7 0 The decoding for the chip selects resides the Analog FPGA Control Register O provides the following e Mute relay control for the Main RCA outputs MAINOUTS MUTE e Mute relay control for the Main XLR outputs EXPOUTS_MUTE e Mute relay control for the Record fixed and variable RCA outputs RECOUT e Mute relay control for the Zone fixed and variable RCA 8 XLR outputs ZON2OUT MUTE Control Register 1 provides the following e Analog source selection for the Main audio path MAIN ANLG SEL 2 0 MAIN ANLG e Main A D calibration and 96kHz sample rate enable MAIN AD
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97. 2530 SNOISIGN MC 12 MC 12 Balanced Service Manual Your Notes 8 168 Lexicon 2 5 9 8 8 169 NO OL SINNOW 318VO 40 Nid 310N 6991 0899 a wee p moss azis vo ot z M w 07 905 8 21 2wW 272 dd OMG ASSY 1 30 13345 z i TWIS LON 00 4 P SEV NI 9 v 3NDYOL 5 1 66891 0ZXZ bios 9ma z18vo 5014 01 8670 ayov 35506 SEINN Hd HNd WWOXEW DIOS DXOS 1607 NAVO 9 9 581 9 9 3NDYOL 5014 v 198 0 0998 5014 2 96 01 0 9 NZ Hd HNd 1 96 2 MYOS 28 Hd HNd AWSX W MYOS 09 405 9869 2208 8 6901 6208 S 8 21 2 O66vi zzof NOWNOD 669 2208 ernie LON 5300 AINO 3ON3H343M ONILSM YIANNN L 86091 6020 583100 S310N 11 5 IHL 3015170 JAYI AvidS d 31008 5 9 29 434 6809 0898 3 OELXT Dios omd 0017 NAYO 434 2809 0898 OLXZ Dios 9ma 0017 NEVI 587 9 9 ANDYOL 5014 8 86801 0998 28 Hd HNd 09691 2028 09
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100. ren 0078676 92 00 42 000 waa aire oan NI NOLIATHOSEG SNOTSTARE MC 12 MC 12 Balanced Service Manual Your Notes 8 8 Lexicon 8 9 13 T e v 9 L 8 5 err 44 anser m seseer 233 wmm 66 92 01 8X ampaw aego 0140 SWE ex pem NIVA HiHOS OLIO rud H TLA xwa vast gt Eu y aas 5 u SNOLIOVdVO 9 se T 29 x ELTRIOL NI WOIDSNNOO 0140 TIWISNI SELON SINANI act M PERO tom act oce bat a TORIO T 2 wee 98 1 M uer 4 42 act oce 98 1 a UNDO ave 90 1 Str 1 ave oce 1 CADO 22 pea acc 1 90 1 zoomt pe om sur sel rl Svo occ E WLTEWT wat a ete F 19787 0722
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102. 66 80 2 cancer mex zH 659 T 090 8 1 4 ammon aaoo 66 92 2 av amomp HY 2 mun OLIO 525 ES Inest a e 19 5 a aC 98 01 9 6 10 Ting 1515 awas oasa 2 TIS SONIS 00451 58 a nus Wi Sumus 1 32 arw casa c BSNS EST So 10 0 a SS SIT uu TEES OD BITE narrow VNB EST evasa aW ue s EH 5 trs g5 tas or MOLOSNNOO LE mui Siam or 88145 w TOUR 2 pre Es ere 2 an e sums LE tH Lid eer Hol d oL WE ore Tu 544 OL OL 6M WHANA hud omv ev ora EM anoo aw ss nm iu ae em OF ex oe Ear WINE
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104. GHONVHD 8 9 s ARS 07273 57279 E El 8 mn oo rtsooo 1 xiv uncus S gt j en SNOTSTASE To te a T 4 v 9 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 28 Lexicon 8 29 B 2 E 9 L 8 ee semis sees se sc L ass US 2 5 ue 659 090 saco 66 97 L ammo 6 6 91 E E 66 92 1 5450 py 9 4 E v 188 00 ar 05 P 28 SOL 519 Si
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108. z T aaost 1 ji NI m p NO HLIM SINSNOdMOD L s 640 670 SYOINNOISHA 1841 9 bend oad TNOLOSS NSGHON LAHS SALONGA 5 Y mme 2 guo e amoa sisswio eoru v pet 180 2 A dn RM SHOLIOVdVO SSIMNSHLO SSTINN SHOLSISUN HSINNSHIO SSWIND 1 Ind 0 8 MOT T sHV SHOLSISSH GHLWOIGNI SSIMNSHLO T ue i XIA DIN aan STH SHION 5 5 uj ega sto Es Y ib z OIW vm 020 aaost I 0 vast z 3 T sLoceon aaost Lo 7 veo A 20751 NI il ur z ZU Teo STO Mt tsaz Z NI tsaa aane 58 1 fn vast est z ac wr oo teet00 waa PN 2271711 0073777 Y NI DIN gt nm T c E w T z 0070779 0070177 34 ae
109. 12 MC 12 Balanced Music and Cinema Processors Service Manual lexicon MC 12 MC 12 Balanced Service Manual Precautions Save these instructions for later use Follow all instructions and warnings marked on the unit Always use with the correct line voltage Refer to the manufacturer s operating instructions for power requirements Be advised that different operating voltages may require the use of a different line cord and or attachment plug Do not install the unit in an unventilated rack or directly above heat producing equipment such as power amplifiers Observe the maximum ambient operating temperature listed in the product specification Slots and openings on the case are provided for ventilation to ensure reliable operation and prevent it from overheating these openings must not be blocked or covered Never push objects of any kind through any of the ventilation slots Never spill a liquid of any kind on the unit This product is equipped with a 3 wire grounding type plug This is a safety feature and should not be defeated Never attach audio power amplifier outputs directly to any of the unit s connectors To prevent shock or fire hazard do not expose the unit to rain or moisture or operate it where it will be exposed to water Do not attempt to operate the unit if it has been dropped damaged exposed to liquids or if it exhibits a distinct change in performance indicating the need for service This unit s
110. 2 een 2 x ue 69 TOROS 5 en Quen snb denas 3s OLE ns ota Sg 91 19 91 gear Y wast ans aste ane e 9 90 167878 a WE xoa ms EISE TES SUIT WU zh 80186000 xem c 007273 007275 00 11500 xoa m 2 5 L 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 48 Lexicon 8 49 T 2 v S 9 L 4067 ussHS 6 6569 66 82 1 aansst 3 D 659 1 090 5 aaoo azis 66 9t L ammo WI S SS 66 92 14 HMA TOW da NIVW WSHOS zz PR urs xt ES PE uua 2 E WIRKT pna wr os a DU 28021 SERE oss 28 21 Pe Par 4 EE BE SEO PERE ino Xvoo ogg 47 911
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112. 9 71 91 4 ar 95 ios i 9 51 12771 Tas WD ENT 105 Wud ONE DS IXOS XNGz eg s tq s cd oY 184 5 5 WEGOOHG toas j Ti za 88 8 51 4 SS LEE 55 mos 2005 zoas 886080 44 5 3 468 51 e a 49 5 10 51 EI EORR ume NOSE 95 98TH 38 ru 29 149 h up Emm mI fugiet oi t Sos LPN SS VERDE ES DOR NIV EAE 35 Son aurum SE rA 922024 x 55 5 IV NIV E xam 1995 SS EHE 55 wow 23 46 61 3s Lea 15 138 ta sore 2574 oas Dawe XA arg wor Dasa zor aoasa 238 DEF 88 11758 7 0 21 GOD 0381
113. ASSV swwoudav Ze Qr Xx TL STONY 7 0 S8vi S3ONVN3T0L MOO 068 1 200 33S SALON 10 8 ay 91 v HM 00 60 010 1 81 10 99 10409 NNOO 10 91 SHOQN3A MOTIV Hinv o b a 3 3AVN 3114 0002 QvOv SNOISIASY S3HONI NI SNOISNAWIG 031312395 3SIMH3HlO 5531 0 3AVS JHL 10 0 JHL ONISNOH Q3MOTIV SMOQN3A M3HIO SLYYd 5 4 OL 33434 9686681 424 9 LEGZTL LZS 5 1 ALON A n N 00 S STOF 9 621 lt 2 lt 2 SLOYLNOO 64621 2250 42 9 5 3O193NNOO aa 8881 0198 Nv4 8 175 MC 12 MC 12 Balanced Service Manual Your Notes 8 176 Lexicon V 30 1335 1 1 xwos 0 01 6 aanssi Y S 21 25 00 Nouvoridav 70 66891 080 ws mol ON owO 10 976 lt 21 20 ASSY FORE SNOISNGNIG
114. After extended diagnostics are entered the front panel encoder Mode Up and Mode Down buttons are used to navigate through the diagnostics The front panel encoder is rotated to display the desired tests The Mode Down button is pressed to move down through the menu selections and to execute the desired diagnostic test The Mode Up is used to back up through menu selections similar to an escape button on a computer keyboard Types of Tests The Extended diagnostic tests fall into two categories The first category is for tests required to functionally verify an MC 12 MC 12 Balanced These will be referred to as manufacturing diagnostic tests The second category is for troubleshooting defective units These tests are only utilized if there is a failure The troubleshooting tests can be used to help isolate the source of failures These tests are referred to as troubleshooting diagnostics Three groups of tests are executed for every MC 12 MC 12 Balanced These are the Pre Burn In Tests Burn In Loop and the Manufacturing Suite The Pre Burn In Burn In and Manufacturing suite comprise the automated sets of tests used to verify proper operation of the unit Each of the tests in these suites are run in order unless there is a failure The failing test will loop to allow the electrical signals to be active for troubleshooting The user can optionally continue the suite The Repair suite allows a technician to run particular tests for troubleshooting
115. Ami Y SNOTSTARE AST MC 12 MC 12 Balanced Service Manual Your Notes 8 68 Lexicon 8 69 T v S L 8 u 5 95 699 00 2 8 ossi x 3 Een 14 9972 5 080 NS saco azis 00 2 5 44 amwmo 4160 80 M STEANI 100 8 ZHNOZ 00 2 5 O I 8 5 5 ER 2522 er ES eso anst ast xor va 4 Pr suu 4 p i 81240 5 5 lir 62 21 Y say ELAR OK 68 81 ase PRF 64 81 LIUM 75575 409 001 hep se ay AL mer 409 00 198 11 Rr E ws er srTH g DA 110807 aat 1004807
116. Error Log An error log or ring buffer containing a log of the last 20 13h failures is available If the error quantity exceeds 20 additional error messages are stored at the first location in the buffer FIFO The error log is stored in the non volatile section of SRAM Every failure stored in the error log has 6 parts ZNN E aYYYYYY wZZZZZZ rQQQQQQ NN Error Log Number The error log location number in hexadecimal It goes from 00 to 13 Turning the ENCODER knob clockwise allows one to scroll through all 20 error log locations E Failure Number 5 5 MC 12 MC 12 Balanced Service Manual The E stands for error amp the 2 digit number indicates which test failed tXX Error Code from the following list NO ERROR 0 ADDR FAILURE 1 DATA FAILURE 2 TIMEOUT FAILURE 3 COUNTER FAILURE 4 NON VOL DATA FAILURE 5 OPCODE FAILURE 6 FPGA ID NO MATCH 7 DAR FPGA ID NO MATCH 8 AUDIO FPGA ID NO MATCH 9 ANALOG FPGA ID NO MATCH OxA VFD TIME OUT OxB VFD RAM ERROR OxC SRAM PREBURNIN FAILURE 0x13 SRAM BURN FAILURE 0x14 EPROM CHKSUM FROM FLASH 0x15 SRAM FAILURE 0x16 FIFO ERROR OVERRUN 0x17 549326 BOOT START MESSAGE 0x100 549326 NO BOOT SUCCESS MESSAGE 0x101 549326 INIT ERROR 0x102
117. Servicing Do not attempt any service beyond that described in the operating instructions Refer all other service needs to qualified service personnel Damage Requiring Service The unit should be serviced by qualified service personnel when the power supply cord or the plug has been damaged objects have fallen or liquid has been spilled into the unit the unit has been exposed to rain the unit does not appear to operate normally or exhibits a marked change in performance the unit has been dropped or the enclosure damaged MC 12 MC 12 Balanced Service Manual SAFETY SUMMARY The following general safety precautions must be observed during all phases of operation service and repair of this instrument Failure to comply with these precautions or with specific warnings elsewhere in these instructions violates safety standards of design manufacture and intended use of the instrument Lexicon assumes no liability for the customer s failure to comply with these requirements GROUND THE INSTRUMENT To minimize shock hazard the instrument chassis and cabinet must be connected to an electrical ground The instrument is equipped with a three conductor AC power cable The power cable must either be plugged into an approved three contact electrical outlet or used with a three contact to two contact adapter with the grounding wire green firmly connected to an electrical ground safety ground at the power outlet The power jack and mating plug
118. Ventilation Make sure that the location or position of the unit does not interfere with its proper ventilation For example the unit should not be situated on a bed sofa rug or similar surface that may block the ventilation openings or placed in a cabinet which impedes the flow of air through the ventilation openings Wall or Ceiling Mounting Do not mount the unit to a wall or ceiling except as recommended by the manufacturer Power Sources Connect the unit only to a power supply of the type described in the operating instructions or as marked on the unit Grounding or Polarization Take precautions not to defeat the grounding or polarization of the unit s power cord Not applicable in Canada Lexicon Power Cord Protection Route power supply cords so that they are not likely to be walked on or pinched by items placed on or against them paying particular attention to cords at plugs convenience receptacles and the point at which they exit from the unit Nonuse Periods Unplug the power cord of the unit from the outlet when the unit is to be left unused for a long period of time Water and Moisture Do not use the unit near water for example near a sink in a wet basement near a swimming pool near an open window etc Object and Liquid Entry Do not allow objects to fall or liquids to be spilled into the enclosure through openings Cleaning The unit should be cleaned only as recommended by the manufacturer
119. 1 2 5 connects the output BNC jacks either to the selected component source or to the OSD Relays are actuated through their driver transistors when the associated PSELn bit is asserted high Note component video overlays are not implemented in current operating system software Component OSD luminance Y is taken from the normal analog luminance output of the OSD chip Color difference signals Pr Pb are derived from logic level signals from the RGB port of the chip U19 buffers the logic levels and provides inverted versions of R and B A resistor array forms a weighted sum of the RGB levels along with appropriate DC offset and scaling to implement the standard color difference matrix Y 587G 299R 114B Pr 713 R Y Pb 564 B Y U11 serves as buffer filter output driver for the Pr and Pb and drives the outputs through series terminating resistors R101 R105 The signals generated by the MC 12 OSD are compatible only with the 480i component format When incompatible formats are in use the component OSD is inapplicable and is not accessed by the operating system software ON SCREEN DISPLAY SIGNALS Video board schematic sheet 5 OSD chip U34 produces a character based video display that can be overlaid on program video or that can occupy a full screen based on an independent internal video generator OSD modes and parameters are controlled by an extensive set of internal registers accessed via serial interface The cha
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123. Crystal 43296 Boot Serial Protocol Interface This test verifies that the Crystal 43296 can communicate with the Host processor If a failure occurs the test will attempt to write an entry into the error log write the test number and the error number to the VFD and LED matrix Crystal 8420 Boot Memory Test This test verifies that the Crystal 8420 can communicate with the Host processor If a failure occurs the test will attempt to write an entry into the error log write the test number and the error number to the VFD and LED matrix SHARC SDRAM Test This test verifies that the SDRAM for each SHARC that has this test enabled on the Main Board is operational and can be written to and read from The SDRAM test is run on Pair 0 Processor and on Pair 1 Processor C If a failure occurs the test will attempt to write an entry into the error log write the test number the error number to the and LED matrix The test writes the test patterns of 0x55555555 OXAAAAAAAA and 0x00000000 to each location and reads them back Once each location is verified a counting test is applied to verify the address buss SHARC SRAM Test This test verifies that the SRAM for each SHARC that has this test enabled on the Main Board is operational and can be written to and read from The SRAM tests is run on Pair 0 Processor B and on Pair 1 Processor D If a failure occurs the test will attempt to write an entry into the error log write the test
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129. User Interface The user interface consists of a set of menus The top menu is the DIAGS MENU and is shown in the top line of the VFD display To view the available menu items turn the encoder knob in either direction and the menu choices will appear in the second row When the desired menu item is shown press the Mode Down button This selects the menu item If the item is another menu the menu s title now appears in the top line of the VFD and its menu items are in the second row If a test is selected the test name will appear in the top line and the results or information to run the test will be on the second row Once a test is finished or to get out of a menu press the Mode Up button 5 10 Lexicon The group tests are those diagnostics where if a test passes the diagnostics automatically execute the next test Group tests are the Power On Diagnostics the Manufacturing Suite the Pre Burn In test and the Burn In Loop If one of the group tests is selected the next test is automatically run if the current test passes Upon successful completion of the group tests the VFD will either display Pass or Fail come out of the test group to the menu or continuously loop as in the case of the Burn In Loop test If a test fails the VFD and front panel LEDs will attempt to indicate the failed test The test will attempt to loop to keep the signal lines active for debugging purposes If an individual test is selected it will continuously
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133. Slowly increase the volume on the amplifier to a comfortable listening level from the speakers Verify that you hear clean clear audio coming from the speakers Pause the DVD and power down the amplifier 0 In order to test the remaining Digital inputs both RCA and Optical you must move the Digital Input cable to the next Digital input RCA or Optical then highlight the input being tested in the Audio Tests Menu and select it by pressing the Right Menu button 11 Repeat steps 6 9 until all the remaining Digital Inputs have been tested 0 0 Digital Input to Digital Outputs Test This test will verify the path of the S PDIF 1 Digital input to the Digital S PDIF outputs RCA and Optical of the MC 12 MC 12 Balanced 1 Connect the digital output source DVD player to the 1 Coax Digital input on the rear panel of the MC 12 MC 12 Balanced 2 Connect the Coax S PDIF output on the back of the MC 12 MC 12 Balanced to the digital input of the DAT machine 3 Connect Left Right analog outputs of the DAT to the Analog Left and Right inputs of the amplifier and its outputs to a pair of speakers 4 If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter 5 In the Diagnostic Menu select Audio I O Tests 6 Highlight S PDIF Input Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see digital audio
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140. 12 dBV 4 Vrms signal level 8 Using the output level from Step 4 above set for a OdB reference to check Frequency Response for the MC 12 MC 12 Balanced 9 Turn the filter on the Analyzer off 10 Sweep the oscillator frequency from 10Hz to 20kHz 11 Verify the signal level is within 0 1 0 25dBV 0 754 40Hz of the reference level over the entire Sweep 12 Set the scale on the Distortion Analyzer to measure 100dBr signal level with the filter on 13 Turn off the oscillator to the MC 12 MC 12 Balanced and verify a noise level measurement lt 108dBr 14 Swap cables from the Left 1 input to the Right 1 input and the Left Fix RCA output to the Right Fix RCA output 15 Repeat Steps 1 11 above 16 Test the Zone 2 RCA Var outputs and the XLR Zone 2 outputs using the above test 4 12 Lexicon AUDIO INPUTS RCA 1 LEFT AND RIGHT TO RECORD LEFT AND RIGHT RCA FIX OUTPUTS TESTS Setup 1 Connect an audio cable between the output of the Low Distortion Oscillator and the MC 12 s Left RCA 1 audio input 2 Connect an audio cable between the Record Left Fix RCA output of the MC 12 MC 12 Balanced and the input of the Distortion Analyzer 3 Place the MC 12 MC 12 Balanced into Extended Diagnostics as described at the beginning of this chapter 4 Inthe Diagnostic Menu select Audio Tests 5 Highlight Audio Input 1 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now
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143. In this test we will be verifying the path of the 1 Left and Right RCA paired input to all Analog Outputs both RCA and XLR of the MC 12 MC 12 Balanced 1 Connect the oscillator output to the Left and Right audio inputs marked 81 on the rear panel of the MC 12 MC 12 Balanced 2 Connect the RCA Left and Right Front outputs of the MC 12 MC 12 Balanced to the amplifier Left and Right inputs and the outputs of the amplifier to a pair of speakers 4 2 Lexicon 3 If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter In the Diagnostic Menu select Audio Tests Highlight Audio Input 1 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set for audio coming into the Left and Right 1 RCA input to the Front Left and Right RCA output and all the remaining RCA and XLR paired Left and Right audio output connections Slowly increase the volume on the amplifier to a comfortable listening level from the speakers Sweep the oscillator from 20Hz to 20kHz Verify that you hear clean clear audio coming from the speakers 8 Power down the amplifier and move the cables from the Front Left and Right outputs to the Center Left and Right outputs 9 Power the amplifier and repeat the oscillator sweep as described in Step 7 10 Repeat steps 8 and 9 for the remaining paired RCA outputs up to the Left and Right Aux The Zone 2
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147. Video Board To access the video control registers sheet 8 VIDEO is asserted and 3 bytes of data are sent while VIDEO REG remains low VREG DATA is clocked into the shift stages of U3 4 5 by the rising edge of VREG SCLK When VIDEO REG returns high logic within the FPGA generates a special strobe VREG RCLK to transfer data from the internal stages to the output latches of the chips The FPGA synchronizes VREG RCLK with VSYNC so that latching occurs during vertical blanking In the absence of sync the strobe will occur by default after a several tens of milliseconds using the 15kHz clock as a timebase If VIDEO returns high after only one byte of serial data the byte gets latched into register implemented within the FPGA and no external strobe gets generated The FPGA recognizes one register bit as a command to enter a special mode for initializing the character font SRAM U31 32 33 In this mode the host keeps VIDEO asserted while it sends the font pattern bytes to fill the SRAMs Logic within the FPGA converts the received serial bytes to parallel drives the A 18 0 and D 7 0 buses and asserts WR generating write cycles to transfer data to the SRAMs It takes over over a second to complete the transfer and during this time the OSD A and D buses are tri stated with OSD TSC asserted low Once loaded the OSD chip accesses the SRAMs and fetches bytes of pattern data for each character for a total of 3x24
148. XLR board schematic sheets 1 2 Specific references are to the left front channel other main channels are similar is the unbalanced audio driven by volume control chip U37 on the Analog I O board fed through a series 100 ohm resistor and the ribbon cable connecting to the XLR Board at J15 4 FRONTRTN connects through the cable to the signal ground near the driving point Op amp U21 and associated circuitry amplify the difference between LFRONT FRONTRTN with a gain of 3 The combination of R62 and the 100 ohm resistor at the driven end matches the value of R60 preserving differential symmetry and giving high common mode rejection FRONTRTN is a ground sense line dedicated to the front channel pair The differential stage with remote ground sensing rejects common mode ground differences that arise between boards due to ir drops in the common ground connections U14 is a balanced audio line driver with nominal open circuit gain of 6 7dB and low output impedance capable of driving 600 ohm loads It also has high output common mode rejection so its differential output 6 29 MC 12 MC 12 Balanced Service Manual tends to be independent of any imbalance in output loading Its outputs are AC coupled through non polar electrolytic capacitors C109 C110 With a 600 ohm load the AC coupling gives a lower 3dB frequency of around 10Hz Relay RY14 mutes the left front output through its normally closed contacts in un powered and u
149. amp which acts as a current to voltage I V converter Similarly OUTL and OUTR fed to the other summing node The non inverting inputs are biased at about 2 7V by the FILTR pin of the AD1853 The converter produces a differential voltage from the combined D A current outputs Each current output pin sinks a bias of 1mA and delivers full scale signal current of 0 75mA around that bias point 0 25 to 1 75 mA The output voltage at the converter is determined by its feedback resistor 6 49k For example the full scale AC signal voltage developed due to OUTL would be 0 75mA 6 49k 4 9V it becomes 9 8V when the equal contribution of OUTR is added A separate DC feedback scheme is used to eliminate DC bias from the outputs of the I V converters The feedback loop is formed by 2N3904 and 2N3906 transistors and their associated passive components The 2N3906 supplies bias currents into the summing nodes via two resistors while the 2N3904 senses the sum of the converters outputs The objective of this circuit is to maximize the voltage range available for the audio signal thus improving the signal to noise ratio By eliminating DC bias in the output of the converters their full scale AC signal voltage is 9 8V The current outputs from the DACs have substantial components at frequencies well above the audio band and the combination of series ferrite beads across the line capacitor and feedback c
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151. number and the error number to the VFD and LED matrix 5 9 MC 12 MC 12 Balanced Service Manual The test writes the test patterns of 0x55555555 OXAAAAAAAA and 0x00000000 to each location and reads them back Once each location is verified a counting test is applied to verify the address buss Power on Diagnostics Completed After the power on diagnostics are completed the VFD will display the appropriate power up message MANUFACTURER MODEL VX XX c 2001 OPTIONS At this point the operating system takes over the functioning of the MC 12 MC 12 Balanced EXTENDED DIAGNOSTICS TESTS Entering Extended Diagnostic Tests The extended diagnostic tests are accessible by pressing and holding the RECORD LD and ZONE 210 front panel buttons when powering on a MC 12 MC 12 Balanced The audio outputs analog and digital are muted After entering the diagnostics and the VFD displays LEXICON the front panel buttons can be released After the model banner is briefly displayed on the VFD the display will indicate DIAGS MENU FUNCTIONAL TESTS The extended diagnostics can also be entered via the serial debug port by first entering the debug program Typing debug when connected to the serial port accesses the debug program the debug program is case sensitive In addition the extended diagnostics can be entered by sending ed for extended diagnostics to the unit via the serial debug port during the first 10 seconds after powering on the unit
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156. 12 MC 12 Balanced main power switch on the back of the MC 12 MC 12 Balanced Press and hold down 2 buttons on the front panel the Zone 2 LD button and the Record LD button While holding down those buttons turn on the Main power switch on the back of the unit Once the unit shows activity on the front panel release the buttons When the front panel reads DIAGS MENU FUNCTIONAL TESTS turn the volume knob on the front panel so that it reads DIAGNOSTICS MENU REPAIR TESTS Press the Down Mode button once The display reads REPAIR TESTS Z180 EPROM CHECKSUM Turn the Volume knob until the display reads REPAIR TESTS CLEAR NON VOL SRAM Press the Down Mode button once The display reads REPAIR TESTS Confirm Press MUTE Press the Mute button on the front panel once The display will quickly read REPAIR TESTS Initializing RAM then read REPAIR TESTS Test completed 10 Press the Up Mode button once The display will read REPAIR TESTS CLEAR NON VOL SRAM 11 Turn the Volume knob until the display reads REPAIR TESTS NORMAL OPERATION 12 Press the Down Mode button once The display will flash DIAG Menu Please Wait It will then go through a normal power up diagnostic test and drop into normal operation 5 20 Lexicon Chapter 6 Theory of Operation Main Board 2180 HOST PROCESSOR 29 491 MHZ CRYSTAL RS 232 Rev RS 232 XMT
157. 37 38 C41 42 45 46 49 50 C53 54 57 58 61 62 C65 66 69 70 328 332 C335 338 339 341 343 C345 348 349 360 361 C372 373 384 385 396 C397 408 409 420 421 C435 436 447 448 459 C460 471 472 483 484 245 10587 CAPSM CER 18PF 50V COG 10 26 00 C73 94 97 98 149 150 245 12485 CAPSM CER 1UF 25V Z5U 20 262 00 BC1 27 BC29A B BC29 BC31A B BC31 BC38 42 BC43 47A B BC43 47 BC48 55 58 62 BC63 65 BC68 74 BC75 76 85 86 BC87 91 7 9 MC 12 MC 12 Balanced Service Manual PART NO 270 00779 270 06671 270 09799 270 11545 300 01030 300 10563 300 11599 300 11599 300 14286 310 10510 310 10565 310 10566 330 10522 330 10536 340 00742 340 10550 340 10552 340 11597 340 12367 340 12936 346 10549 346 14451 346 14583 350 13855 355 13829 7 10 DESCRIPTION FERRITE BEAD FERRITE CHOKE 2 5 TURN FERRITESM CHIP 600 OHM 1206 FERRITESM CHIP 600 OHM 0805 134004 AND 4005 DIODESM DUAL SERIES GP SOT23 DIODESM GP 1N4002 MELF DIODESM GP 1N4002 MELF DIODESM SCHOTTKY 1A SMB TRANSISTORSM 2N3904 SOT23 TRANSISTORSM 2N3906 SOT23 TRANSISTORSM 2N4401 SOT23 ICSM DIGITAL 74HC04 SOIC ICSM DIGITAL 74HC273 SOIC IC LINEAR 7805 LM 340 T 5 ICSM LIN CS3310 VOL CTL SOIC ICSM LIN MC33078 DU OPAMP SOIC ICSM LIN TLO72 DUAL OPAMP SOIC ICSM LIN OP275 DU OP AMP SOIC ICSM LIN OPA2134 DU OP 5 8 ICSM SS SWITCH DG408 SOIC ICSM SS SW DG411QUAD 1P1T SOIC ICSM SS SW ADG451QUAD 1P1T SOI ICS
158. 405 16091 20 8 8 21 2 ANOS 581 9 300501 66 01 0998 NZ Hd HNd AWZIXCW MYDS 90 1 Z0 ASSY 031 5 96991 1028 140 OLN 581 9 3NDYOL 5014 2 86901 0990 Z8 HNd AW9XCW MYOS 9261 669 X 3046 09 405 xovig 8 6 1 lt 8 21 060 1 0654 X 002 581 4 5 1 1 25 N d 314405 3HSVM 2 INN ASSY 27 5014 2 55951 066 i 9091 6208 p d 5014 i 95961 066 NOLINE 06961 1028 M3A00 10 02 8 0 92 4 00 80c010f 10 2 Sg NI 01 8 1 9 0 62 6 ord E ga T E NZ Hd HNd AWOLXPW MYOS SNOISIA3N woo 2 9 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 170 Lexicon QG3131dWOO 30 4 13 401 35010 NMOHS SV 53 1835 NI 30 14 09 405 86 1 2204 8 21 24 66091 2200 5 08 303543405 LON AINO 04 NMOHS Livd SALON 09 90 0 OVE Nv310
159. 43 front panel switches are working Each button on the front panel is pressed and the VFD will indicate which front panel button has been pressed Example Switch Test MODE DN in the second line on the VFD If the button has an LED associated with it the LED will illuminate When all switches have been tested the bottom half of the display will indicate completion LED Test The LED test illuminates each LED by the tester turning the ENCODER knob clockwise or counter clockwise As the ENCODER knob is turned each individual LED is illuminated Encoder The Encoder Test verifies the operation of the Encoder including direction and the 24 positions It is designed so if there was a bad position on the Encoder the display will never indicate a Passed message This is achieved by having the accumulator value reset to 0 if a switch position is bad or if the Encoder was turned in the opposite direction during the test Therefore the accumulator never sees the expected value of 24 so the program isn t able to perform the next task i e instruct the user to perform the counter clockwise test or display Passed When the Encoder is being tested the bottom right half of the display will indicate the Encoder direction and position value The test requires the clockwise direction to be tested first When the ENCODER is being turned clockwise the display will read EXTENDED DIAGNOSTICS Encoder Test CW 05 In this example the Encoder was t
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162. 6 Press the Menu button on the remote The Main Menu should appear on the screen 7 With the Down Menu button on the remote scroll down to SETUP then select by pressing the Right Menu button 8 The SETUP Menu will appear and the INPUTS at the top will be highlighted At this point press the Right Menu button again 9 The INPUT SETUP Menu will appear At the top will be DVD1 To keep things simple use this DVD1 Input to test all the video input and outputs of the MC 12 MC 12 Balanced 10 Press the Right Menu button The MC 12 MC 12 Balanced will now be set to the DVD1 INPUT SETUP Menu 11 Using Down button scroll down to the COMPONENT IN and press the Right Menu button 12 In the DVD1 COMPONENT Menu select any of the 4 COMPONENT Video Inputs of the MC 12 MC 12 Balanced to be tested 13 At this time the MC 12 MC 12 Balanced is already set to COMPONENT 1 Video input to the COMPONENT Video output of the MC 12 MC 12 Balanced 14 Press the OSD button on the remote This will turn off the on screen video information from the MC 12 MC 12 Balanced and allow you to view the video for the DVD The video path is now set for testing Test 1 Load a disc into the DVD and press play 2 Verify a clean undistorted picture appears on the screen 3 Pause the tape 4 Testthe remaining COMPONENT Video inputs of the MC 12 MC 12 Balanced switch the COMPONENT Video input cable to 2 3 and 4 and repeat steps 1 3 above 5 Pause the player aft
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164. 88 2kHz sample rate the 24 576MHz oscillator that provides either a 48kHz or 96kHz sample rate or the master clock output of the Record digital receiver In practice the unit runs off the crystal at 96kHz when the input is analog When the input is digital the master clock output of the digital receiver is used Depending on the input selected the appropriate master clock is routed from the DAR FPGA to the Audio FPGA Here it drives a clock tree that divides down the master clock which is 256 times the sample rate 256FS to create the other clock rates required e Digital Receiver uses word clock FS and bit clock 6425 The Analog Board receives a 256FS Master Clock and a word clock FS These are used on the analog board to derive the audio clock signals required by the devices on that board Record Digital Transmitter requires an input master clock at 256FS a bit clock at 6425 and FS word clock A separate output master clock is required by the sample rate converter section of the transmitter which uses it to drive the output bitstream when the output sample rate is different from the input sample rate 6 16 Lexicon 22 5792 MHZ 4488 gt 24 576 MHZ 4896 gt RECORD DRCVR DRCVR DAR FPGA
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167. AUDIO INPUTS COAX OPTICAL AES EBU THE LEFT AND RIGHT FRONT RCA OUTPUTS TESTS Having tested all Analog to Analog specifications in the above tests it is now only necessary to prove that all the Digital inputs pass specifications This test will verify the specifications of all Digital Inputs to the Front Left and Right RCA outputs Setup 1 Connect the digital output source to the 1 Coax digital input on the rear panel of the MC 12 MC 12 Balanced 2 Connect the RCA Left Front output of the MC 12 MC 12 Balanced to the amplifier Left inputs and the output of the amplifier to a pair of speakers 3 Place the MC 12 MC 12 Balanced into Extended Diagnostics as described at the beginning of this chapter In the Diagnostic Menu select Audio Tests Highlight S PDIF Input CX1 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see digital audio from the S PDIF 81 digital input to the Front Left and Right RCA output and all the remaining RCA and XLR paired Left and Right audio output connections 4 13 MC 12 MC 12 Balanced Service Manual Tests Apply a 1kHz signal 0 00dBFS to the input of the MC 12 MC 12 Balanced Set the scale on the Distortion Analyzer to measure 12dBV 4 Vrms signal level Turn all the filters off on the Analyzer Verify that the output level from the MC 12 MC 12 Balanced is 12dBV 4 Vrms 4 025 to 3 5904 Adjust the scale on the Distorti
168. CONTROL SELECTS FPGA FRONT PANEL CONTROL STATUS ANALOG CHIP gt SELECTS AUDIO FPGA PROGRAM D BOARD 0 DAR PROGRAM D BOARD ANLG FPGA PROGRAM D BOARD 2 DSP CONTROL INTERFACE os CONTROL FPGA REGISTERS STATUS BLOCK REGISTERS RS 232 Serial Interface schematic pages 1 and 20 The 29 491MHz crystal oscillator is divided down to provide the 19 2K Serial Baud Rate of the MC 12 The 1 RX1 ports on the 2180 are connected to theMax202E Transceiver that drives the two female DE9 connectors RS 232 1 and 2 FPGAS Lexicon Host Programming of FPGAs schematic pages 1 and 2 The FPGAs are programmed by the Host processor as part of the boot process when the unit is powered on from the rear panel The FPGA is programmed by the host through the Memory CPLD The two remaining FPGAs I O and Audio are programmed by the host through the I O FPGA It is important to understand that until the FPGAs have been programmed most of the unit including the front panel and on screen display are in reset There are LEDs that light to indicate when the programming for each FPGA is complete 2180 ADDRESS gt Z180 DATA gt I 2180 4 HOST INTERFACE AUDIO
169. E ZG NC a IX NC NC Y V NC ua um IX ws oe oe ane ost Ld ost TIG sta 61 eza ose ose ose sea ION heat ON um TX NC wan AO NC Wan Qo NC NC us VON pee oe E zd ost zea ose ose ose vea PR Ee REC ama oet oer sza ose 6 ose eea N Rean haat N V NC wan XX ON us XX NC sas ON Gan ON VON Gus 7 oe oe one 2575727 907572 ans ex 5872 27 06075727 45 0926000 20 18000 00701 9 00701 9 a 0078279 557 27 lt 00 425000 ssa T HI WSXosHo walivad 8 121 MC 12 MC 12 Balanced Service Manual Your Notes 8 122 Lexicon LT ST 1002 08 1 2 v S 9 L T TE 669ET 66 42 01 aansst 667270
170. FPGA Rec DVD 1 and Rec DVD 2 and Record LD 8 Audio FPGA Z2LD 9 Analog FPGA Z2 LD and Rec LD 10 Crystal 49326 Boot Test Z2 LD and Rec DVD 2 11 Crystal 8420 Version Id Test Z2 LD and DVD 2 and Rec LD 12 SHARC Pair 0 51 GPIO Z2 LD and Rec DVD 1 13 SHARC Pair 0 PS2 GPIO Z2 LD and Rec DVD 1 and Rec LD 14 SHARC Pair 1 51 GPIO Z2 LD and Rec DVD 1 and Rec DVD2 5 3 MC 12 MC 12 Balanced Service Manual 15 SHARC Pair 1 52 GPIO Z2 LD and Rec DVD1 and Rec DVD2 and LD 16 SHARC Pair 0 PS1 SDRAM Z2 DVD1 Test 17 SHARC Pair 0 PS2 SDRAM Z2 DVD2 and Rec LD Test 18 SHARC Pair 1 PS1 SDRAM Z2 DVD2 and Rec DVD2 Test 19 SHARC Pair 1 PS2 SDRAM Z2 DVD2 and Rec DVD2 and Rec LD Test 20 SHARC Pair 0 PS1 SRAM Test Z2 DVD2 and Rec DVD1 21 SHARC Pair 0 PS2 SRAM Test Z2 DVD2 and Rec DVD1 and Rec LD 22 SHARC Pair 1 PS1 SRAM Test Z2 DVD2 and Rec DVD1and Rec DVD2 23 SHARC Pair 1 PS2 SRAM Test Z2 DVD2 and Rec DVD1 and Rec DVD2 and Rec LD 24 SHARC Pair 0 Boot Z2 DVD2 and 2210 25 SHARC Pair 1 Boot Z2 DVD2 and Z2 LD and Rec LD 26 SHARC Pair 2 Boot Z2 DVD2 and Z2 LD and Rec DVD2 27 SHARC Pair 3 Boot Z2 DVD2 and Z2 LD and Rec DVD2 and Rec LD 28 EPROM Chksum Via Flash Z2 DVD2 and Z2 LD and Rec DVD1 29 FLASH Chksum Via Flash Z2 DVD2
171. HNd AW9XEW MYOS 86701 09 IE 48 OL 434 1 9 OLXZ bios 9nd 0017 NAVO 568 1 080 21 09405 9 821 5 OL SWHO 48 OL 031 5 438 1 05 9 4 90 NAYI 089 LL 09405 801 SvHO ML OL 184 821 028 Q8 OL 08 9TNV 338 1 1 DOEXZ LIOS OMd 0017 NAVI 02621 089 01 SVH OL 1333 0 SVHO OL dd 61 Hd HNd AWOLXPW MYOS 96v01 0v9 69 SISSVHO OL 1505 AWOLXvIN MYOS 9961 099 760 AGL AS 405 2651 0547 789 1445 Sd OL MS 19 1 OL Q8 WIN Z 01 1545 Sd 6 Hd AW9XEW MYOS 19 09 4 1404416 Sd 13 ISNA 138 1 86 91 091 799 1446 Sd OL 414406 2 76 HMH 1 26 9 MYOS 22961 099 42 WOLLOG SISSVHO 53 510 3 1 8100 138V1 88891 091 759 2 NIVW 01 Q8 0140 MSS SISSVHO N S 138 1 88660 09 9 1 INd OL 08 Hd HNd 1 0 MYOS 4620 0998 7 lt 9 Sz 1404915 Sd 1 108WAS QNnONO 138v1 9 980 0 79 SISSVH OL 08 WW9 AWrLXEW 4245 6LLvL SC9 1 04406 Sd OL 3 3 13 5 9 25881 021 719 48 OL 6 4 W AWeEXEW 4245 1896 669 09405 821 5 2128 1004 1004 28961 021 09 22 IHS SINV M al X 915 195 WVO4 67 71 054 0 66 AINO
172. ID Audio FPGA Verify ID Analog FPGA Verify ID Crystal 49326 Boot Crystal 4820 Verify ID There is only one menu item in this menu and selecting it will start the sweep through the whole suite of loop tests As long as there are no errors the test will continue to run If there is a failure the entire bottom row of 9 LEDs on the front panel will light These are the TAPE TUNER and AUX LEDs for the Main Zone 2 and Record sections Depending upon the failure the failing test will cycle and the error code will be displayed on the second line of the VFD For example if the analog FPGA verify fails the VFD will show ANLG FPGA TEST Fail E 0A If the user wants to continue press the Mode Up switch Upon completion of all of the tests the second row of the VFD will briefly indicate Pass or Errors Loop SRAM test SRAM Test reads a bit pattern from a known location by the VOL RAM SETUP Test Audio Tests The Audio tests contain the following tests Audio Input 1 Test Audio Input 2 Test Audio Input 3 Test Audio Input 4 Test Audio Input 5 Test Audio Input 6 Test Audio Input 7 Test Audio Input 8 Test S PDIF Input CX1 Test S PDIF Input CX2 Test 5 16 Lexicon S PDIF Input Test S PDIF Input Test S PDIF Input CX5 Test S PDIF Input CX6 Test S PDIF Input OP1 Test S PDIF Input OP2 Test S PDIF Input OP3 Test S PDIF Input OP4 Test S PDIF Input OP5 Test S PDIF Input OP6 Test AES EBU
173. INOZ SINY OL 996 INOZ NIVO LNO 3NOZ DINY OL X96 INI 2 662 110 HVA 3NOZ 9 INV OL X96 INI INOZ 31nW INO OL 396 INI DINV 862 00096 X095 015 RIDENS 00601 4 woa ean oc 18 SHAD 0006 7012 00 00 0 mw oz 16 0 336 00096 Teu sip unis mio MuR UE 30085 015 anzewov ____50000 607910 960 00098 woos lt o1 gt oor euon szorszo 0000 080840 ____ o 002 swn ooz Sewuv xwooss or woa fean oc 0 1 6 swin oor px pmi geli cett E S er eee ee ae 77 lt woo 0008 wod 110 Oi 396 INI DINY SLOW AVI3H LNO HVA OL 596 INI 23H ZEZ wose vei sia eas
174. MC 12 MC 12 Balanced Service Manual Your Notes 8 84 Lexicon 8 85 n T e v 9 L 8 V 00 2 8 3X 8 In xanod eq 3 EWN 00 2 5 zm UM I E N NA saco 00 2 5 44 ammo SIROTA Sinaino ens waiNsO oo z s E O I 1 60 51 82 51 Ex as 80 61 ASI sta g 43 3 lt orra Y Iaoa ns 42 6 aast aste EL pa gh y sem 464 00 ovx R a oo ut e ir eue staa m 5 ib Lp 2 E Ss go 408 00 S Jr rre C EN PS xor A unus 98 21 dd 8849 seus mace meh
175. OL IN 3NOZ ONV Ino 140 OSH OIG INI INOZ INO 140 OL INI INOZ ino 140 Old INI 3NOZ INV 100 140 O3H 910 OL 3NOZ O INV 1nO 140 910 OL INI INOZ SNY NIVO INO 140 Old OL 3NOZ 100 140 934 Id OL INI SINY 88 LNO 140 SIG OL INI ANOZ DINV Tae sam wer 2 2 RT po peque eee Eee eee up oovor 5380 ean oz 296 0002 el 2 Samy 0005 205 wej wei eae sumo arce Suuogs pnm 0006 84 05 em osos mei ain 00098 suswoov susoo EILEEN erp ware ean 6 uec 25072 ern wr wen prse een oc
176. POWER IEC 6A 2M SWISS QTY__EFFECTIVEmINACTIVE 1 00 1 00 1 00 1 00 1 00 1 00 1 00 MC 12 MC 12 Balanced MOUNTING OPTION PART NO 630 08670 640 0867 1 640 14680 701 13635 DESCRIPTION WSHR FIN 10 NYL BLK SCRW 10 32X3 4 FH PH BLK SCRW M4X14MM FH SCKT SS BRACKET MTG RACK 3U MC12 QTY__EFFECTIVEsINACTIVE 4 00 4 00 4 00 2 00 Lexicon REFERENCE IR ENC BD DISPLAY TO FP IR ENC BD SPT BRKT TO FP OPT BD BRKT 2 SHIELD TO FP 10 SWILED BD TO FP 8 STANDBY BD TO FP 2 DSPLY TO SW LED BD STANDBY TO MAIN BD REFERENCE VIDEO BD TO BRKT VIDEO BD TO BRKT BNC TO VIDEO BRKT BNC TO VIDEO BRKT REFERENCE INNER BOX OUTER BOX REFERENCE N AMER REFERENCE 7 15 MC 12 MC 12 Balanced Service Manual MC 12 MC 12 Balanced SPARE ASSEMBLIES Available by special order PART NO 021 14570 021 14571 021 14572 021 14573 021 14574 021 14575 021 14576 021 14577 7 16 DESCRIPTION PL MAIN BD ASSY MC12 B TESTED PL OPTO MIC ASSY MC12 B TESTED PL VIDEO ASSY MC12 B TESTED PL ANLG ASSY MC12 B TESTED PL SW LED ASSY MC12 B TESTED ASSY MC12 B TESTED PL MEM BD ASSY MC12 B TESTED PL XLR BD ASSY MC12B TESTED Lexicon Chapter 8 Schematics and Drawings Schematics 060 13609 SCHEM VIDEO RCA BD 060 13619 SCHEM MAIN OPTO MIC BD 060 13629 SCHEM STANDBY BD 060 13659 5 BD 060 13669 SCHEM ANLG BD 060 13679 SCHEM VIDEO BD 060 13689 SCHEM SW LED BD 060 13699
177. RST MAIN AD 96K Control Register 2 provides the following e Analog source selection for the Record audio path REC ANLG SEL 2 0 ANLG Record A D calibration and 96kHz sample rate enable AD RST AD 96K EN Control Register 3 provides the following e Analog source selection for the Zone 2 audio path ZON2 SEL 2 0 ZON2 ANLG Zone 2 A D calibration and 96kHz sample rate enable ZON2 AD RST ZON2 AD 96K EN Control Register 4 provides the following e Independent Zero crossing enable for each Main output level control FRONT VC ZCEN etc e Zero crossing enable for the Record output level control RECOUT ZCEN e crossing enable for the Zone 2 output level control ZON2OUT VC ZCEN 6 28 Lexicon Control Register 5 provides the following Record DAC reset control DAC RST Record output selection DSP or analog direct path REC DACOUT SEL REC DIRECT SEL Mute for Record output level control RECOUT VC MUTE Zone 2 DAC reset control ZON2 DAC RST Zone 2 output selection DSP or analog direct path ZON2 DACOUT SEL ZON2 DIRECT SEL Mute for Zone 2 output level control 200 VC MUTE Control Register 6 provides the following Main DACs reset control MAIN DAC RST Main outputs selection DSP or analog direct path MAIN DACOUT SEL MAIN DIRECT SEL Mute for Main output level controls MAINOUT VC Front Main DACs reset co
178. RST This prevents the LEDs from lighting when the unit is first powered up until the host is initialized SWRD When this signal is high the MUX generates the enable for reading the Switch Buffer When it is low it generates write strobes to the LED Registers and the Switch Column register In order to read the switches the host must first select a column e Front Panel data bi directional e Front Panel address used by the MUX Signals used by the VF Display are as follows VFD EN chip select to the display e Data byte wide e Address two address bits Address determines whether an access is a read or a write Signals used by the IR Encoder Board are as follows IR auxiliary data from the rear panel connector This is optically coupled with the incoming IR signal at the IR receiver The IR acknowledge LED bit This comes from the PIC and is used to indicate that the unit is detecting an infrared signal System On and Overload LED bits e Encoder 0 1 these are the output of the Front Panel Encoder knob They are read and interpreted on the Main Board 6 6 VED ENABLE VFD m IO DATA BUFFER FRONI N DA
179. Record outputs Two separate analog output pairs are provided one with a fixed output level and the other with a variable output level for use as a 3 Zone output Two S PDIF output ports are also available one RCA coax and one Toslink optical The Zone 2 Audio Path is similar to the Record Audio Path but does not have the S PDIF outputs A third stereo A D converter and input level control have been designed in to permit selection of a 5 1 channel analog audio source for the Main Audio Path Note this A D section is not used for Zone 2 functionality and is not shown in the diagram Error Not a valid link ANALOG AUDIO INPUTS schematic sheets 1 amp 2 Sheets 1 and 2 are identical The Left input jacks and associated circuitry are on sheet 1 while sheet 2 includes the Right input jacks and circuitry Each input pair is buffered by a dual TL072 op amp followed by a resistive divider that reduces the signal by 6 dB Each buffer connects to three DG408 8x1 CMOS Switches There are separate switches for the Main Record and Zone 2 analog source selection with independent switches for left and right channels for a total of six DG408s The outputs of the Main source selectors feed the Main Input Level control on sheet 3 and two dual op amps on sheets 1 and 2 These op amps are used for the direct analog path to the Front L R outputs The first op amp is a unity gain voltage follower The second amplifier inverts the signal and has 1 9 dB of
180. SCHEM IR ENC BD 060 14469 SCHEM XLR BD 060 14479 SCHEM MEMORY BD 060 14849 SCHEM VCO BD 060 15009 SCHEM PS FILTER BD Drawings 080 14529 080 14530 080 14531 080 14533 080 14681 080 14834 080 14853 080 14895 MAIN BD COMPONENT LAYOUT OPTO MIX BD COMPONENT LAYOUT VIDEO BD COMPONENT LAYOUT VIDEO RCA BD COMPONENT LAYOUT ANALOG BD COMPONENT LAYOUT SW LED BD COMPONENT LAYOUT IR ENC BD COMPONENT LAYOUT STANDBY BD COMPONENT LAYOUT MEMORY BD COMPONENT LAYOUT XLR BD MC 12 BALANCED COMPONENT LAYOUT ASSY DWG SHIPMENT ASSY DWG CHASSIS ASSY DWG MECH VIDEO ASSY DWG MECH FP ASSY DWG ACCESS KIT ASSY DWG MECH VCO ASSY DWG FAN ASSY DWG SHIPMENT 8 1 MC 12 MC 12 Balanced Service Manual Your Notes Lexicon 8 3 p gt 5 9 L 8 5 9 sams oit e TEES 8 Se US vv x 121 090 p szis 007177 N _ amomp 5 mwoo avoa waaans vow 66 66 1 osara Wagos wu v GREY 2 EA M mil se t L 2L EU t5 1855 51850 rn 5 Ans vos tax am SUED 2 E E sest
181. SNOTSTARE 8 T 4 v S 9 L MC 12 MC 12 Balanced Service Manual Your Notes 8 64 Lexicon 8 65 T T e v S 9 L 8 oz ws esser 00 2 s mi sa I 20 x vas essex oso saco 00 2 5 X Tap 5 qucoss 00 2 5 puaa ora tsa 8 O T Uu il sin vec 4 BLOEEON duro ES teer su E D sen Pura Lezo M M Um gr si TOT lt esi ponte S ae wv TS i mec s
182. T RY9 20 RY10 ST 1 817 Du Ee Em ST TFBS Gs T air gir gir vir err er nr 6r er or sr m m Ir MC 12 MC 12 Balanced Service Manual Your Notes 8 146 Lexicon 2101 133HS V N 31 25 Z 1 LNINOdWOD Ax 8 2 Q8 03 1 5 8 147 lt 1 ery
183. THIN 1 1 10W 316 OHM RESSM THIN 1 1 10W 590 OHM RESSM THIN 1 1 10W 3 01K OHM RESSM THIN 1 1 10W 1 00K OHM RESSM THIN 1 1 10W 5 62K OHM RESSM THIN 1 1 10W 2 49K OHM RESSM THIN 1 1 10W 6 49K OHM RES WW 1 5W 10 OHM FP CAPSM ELEC 10UF 25V NONPOL 20 CAP ELEC 100UF 25V RAD LOW ESR CAPSM ELEC 47UF 6V NONPOL 20 CAPSM ELEC 2 2UF 35V 2096 CAPSM ELEC 47UF 16V 20 CAP ELEC 47UF 25V RAD NPOL 6D CAPSM TANT 10UF 10V 20 CAPSM TANT 4 7UF 6 3V 20 QTY__EFFECTIVEmINACTIVE REFERENCE 14 00 8 00 48 00 24 00 24 00 6 00 16 00 24 00 1 00 20 00 4 00 22 00 12 00 6 00 20 00 26 00 79 00 R507 510 517 520 527 R530 537 540 R228 229 286 287 295 R296 298 299 307 308 R310 311 319 320 R171 174 268 271 322 R325 331 334 R45 48 53 56 61 64 R69 72 77 80 85 88 R93 96 101 104 169 R172 266 269 272 275 R340 343 354 357 368 R371 382 385 396 399 R123 124 127 128 131 R132 135 136 139 140 R143 144 147 148 R153 154 170 173 R267 270 323 324 R332 333 R273 276 281 284 341 R344 349 352 355 358 R362 367 369 372 376 R381 383 386 390 395 R397 400 404 409 R289 292 301 304 R313 316 R230 231 290 293 302 R305 314 317 327 330 R336 339 R426 429 436 439 446 R449 456 459 466 469 R476 479 486 489 496 R499 506 509 516 519 R526 529 536 539 R255 C43 44 47 48 51 52 55 56 59 60 63 64 67 68 71 72 494 497 329 330 333 336 95 96 99 100 151 152 183 186 189 192 195 198 241 244 251
184. The MC 12 MC 12 Balanced is now set for audio coming into the Left and Right 2 RCA input to the ZONE 2 Left and Right RCA outputs 6 Slowly increase the volume on the amplifier to a comfortable listening level from the speakers 7 Sweep the oscillator from 20Hz to 20kHz Verify that you hear clean clear audio coming from the speakers 8 In order to test the remaining Analog inputs to the Zone 2 Fix output you must power down the amplifier and move the input cables to the next paired audio inputs Next highlight the input being tested in the Audio Tests Menu and select it by pressing the Right Menu button 9 Repeat steps 5 to 7 until all the Audio Inputs have been tested Analog Input to Record Output Test This test will verify the path of the 1 Left and Right RCA paired input to the Record Fix and Var outputs 1 Connect the oscillator output to the Left and Right audio inputs marked 1 on the rear panel of the MC 12 MC 12 Balanced 2 Connect the RCA Left and Right Record Fix outputs of the MC 12 MC 12 Balanced to the amplifier Left and Right inputs and the outputs of the amplifier to a pair of speakers 3 If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter 4 Inthe Diagnostic Menu select Audio Tests 5 Highlight Audio Input 1 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set for audio coming in
185. X 10 14 76701 79 166 SWOS 303543405 SISSVHO day AWZXVW LAN 26 01 6 0 796 10 5300 ONY AINO 09445 821 SISSVHO ni OL NNOO XIX 82 Hd e exvf MYOS 92 91 199 746 04 SI L Nd OL NNOO 2 IYL HNd NNS X MYOS 9841 89 98 Nd OL NNOO 0140 9 VON HNd e CXvf MYOS 99711 19 756 S310N SISSVHO OL Nd 9 Hd HNd ext MNOS 68601 199 AINO 21910 WOLLOG SISSVHO OL SS300V Z Hd HNd e iXvil MYOS 0L10 199 1845 Sd OL v Hd HNd AWOZXCW MYOS 95621 09 7 09405 821 2 SISSVHO OL 08 YIX 09445 INd OL 318VO 2 NZ Hd HNd AWvXS ZW MYOS 11890 099 708 1 SISSWHO 01 08 AINO 09405 08 OL INd 1 49 OS NIQ 9SH 318 0 089 6 OL 13 4 NOILdO AINO 09406 Sn NIV 333 Spo 002 1504 NNOO 2668 014 BL SISSWHO 01 1845 Sd ag 91 5 01061 10 774 SISSVHO 01 13 4 1 0 4 08 OL MHS NINY da AWS XEW LAN 16901 699 9L 4 5155 2 OL 08 OL MHS Hd HNd AWZLXEW MYOS 66701 09 94 09 OL 08 90 NV OL MHS 91 6 1294 245 061 059 vL 6 1 4 OL 06 90 9 TNd 01 ASSY 16 Hd
186. XOLG L E KINO INZHiOTRASG w zi Loma sovra Ho vir 021 84450 RR AS taa 10 2 TUB sta EUER tta a on Ey ue og ee 7584 91 X El lt evasa 44 4 10 91 Er RIP Eum E 25 GI E 5 E Trout was 19 4 015214 Tena Zana pe _ 9 oas wra VE 48 005 Eu 18 01 ox 8 130 ETEEN tavasa 9194 ox E EIL gr vasa 990 0 105 81 a r 8 188 10 5 va vl 8 vov 10 2 va vi EE DOS ox 2 9 muse maa visa 999 0 2 108 va vl UV evasa Sel THOS 12 9 8011 vaye 0 4 10 9 49 i ve e ca L ta 5 Lo V nEEN EC ssotzasav 18581
187. abun orvasev 954 83 7158 998 71 ny P IETS OORT pod 55 1S0H Ta SH ison ca 59 nmas 214084 d sna En 90 Lands a m iru a x E so 01615 rra pe ID OE ua wigs xx E 78 5 evasa WS gor e _ TE SINIOd 1581 107678 ES 0 5 sf mom oar 39751771 076171 ance M MM M TOT WEST zx nl pa 00 Lt6000 907578 wes 999 18 9 00 9 557179 wer oo rtsooo 1 Haw coss oo NOLIATHOSEG am SNOTSTARE MC 12 MC 12 Balanced Service Manual Your Notes 8 24 Lexicon 8 25 v c 9 8 ix esott __ muss E 6S9ET
188. and Record outs will be tested later 11 To test the XLR paired outputs power down the amplifier and remove the RCA output cables from the MC 12 MC 12 Balanced to the amplifier 12 Connect a pair of XLR cables Connect the Front Left and Right balanced outputs of the MC 12 MC 12 Balanced to the XLR balanced input of the amplifier 13 Repeat step 7 14 Test the remaining XLR Left and Right balanced outputs and Center L R to AUX L R by powering down the amp and repeating step 9 Remaining Analog Inputs to Analog Output Test This test will verify the path of the remaining analog Left and Right inputs 2 to 8 to the Main Front Left and Right analog outputs pass signal 1 Connect the oscillator output to the Left and Right audio inputs marked 82 on the rear panel of the MC 12 MC 12 Balanced 2 Connect the RCA Left and Right Front outputs of the MC 12 MC 12 Balanced to the amplifier Left and Right inputs and the outputs of the amplifier to a pair of speakers 3 If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter In the Diagnostic Menu select Audio I O Tests Highlight Audio Input 2 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set for audio coming in to the Left and Right 2 RCA input and out to the Front Left and Right RCA output Slowly increase the volume on the amplifier to a comfor
189. aste uara ry vw 460 0 SNOTSTARE aas T 4 t v 5 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 128 Lexicon 8 129 2 T e v 9 L 8 S oo ez e p E mex 00 62 6 a 090 saco 00 87 6 ammo 6114110 00 61 6 8 E 06470 woe m wi e v 3 t n E E nza A uxor 5 dace ast Laaost ol s ate 4 T ur 5 T z w T 5ue ta i 5 JA 100 IHIN oe E ur pM um 5 EET SC
190. connector on the analog board The main video 5 volt rail 1 a filtered version of system 5VD which also supplies relay coils through FB2 The negative rail is 5VV derived from the analog board 5VA The sync stripper U1 is specially powered from a well regulated rail 5VAS derived from the Analog Board 5VA 6 35 Chapter 7 Parts List MC 12 MC 12 Balanced MAIN BOARD Lexicon PART NO DESCRIPTION QTY EFFECTIVEmINACTIVE REFERENCE 202 09794 55 0 0805 11 00 R81 84 90 93 109 R157 282 202 09795 RESSM RO 5 1 10W 2 2K OHM 8 00 R1 16 18 20 22 24 R26 246 202 09871 RESSM RO 5 1 10W 1K OHM 7 00 R2 24 1 242 247 263 R283 287 202 09873 RESSM RO 5 1 10W 10K OHM 34 00 R28 29 56 111 137 R138 140 141 144 151 R175 232 244 248 255 R267 274 278 279 286 R296 297 202 09874 RESSM RO 5 1 10W 2 2M OHM 2 00 R119 121 202 09894 RESSM RO 5 1 10W 1M OHM 1 00 R152 202 09897 RESSM RO 5 1 10W 470 OHM 4 00 R31 76 80 280 202 10557 RESSM RO 5 1 10W 4 7K OHM 17 00 R3 6 65 133 135 136 R139 142 143 195 238 R243 249 256 257 202 10558 RESSM RO 5 1 10W 47K OHM 9 00 R15 17 19 21 23 25 R117 118 245 202 10559 RESSM RO 5 1 10W 100 OHM 3 00 R128 295 298 202 10571 RESSM RO 5 1 10W 100K OHM 1 00 R251 202 10836 RESSM RO 5 1 4W 1K OHM 6 00 R32 33 38 39 43 44 202 10890 RESSM RO 5 1 10W 220 OHM 24 00 R112 115 129 132 R252 254 284 285 R288 294 300 303 202 10944 55 5 1 10 33 OHM 1 00 R134 202 1094
191. considered functional due to it not being tested During these tests Trap Op Code EPROM FLASH Checksum Z80 SRAM programming of FPGAs and VFD RAM the unit will attempt to use the STANDBY LED to indicate if a failure occurs As Soon as these are completed the VFD will display DIAGNOSTIC TESTS 5 7 MC 12 MC 12 Balanced Service Manual The dots increment in number from both sides simultaneously as the rest of the power on diagnostic tests are completed This informs the user that the unit is still functioning The audio outputs digital and analog will be muted during this sequence The following is a list of test explanations The front panel display is shown only for the first test that can use the VFD Trap Opcode The Trap Opcode error occurs if during the initial boot sequence an undefined Opcode is fetched The INT TRAP Control register can be used to determine the starting address of the undefined instruction If the trap error occurs an attempt will be made to blink the STANDBY LED using a rate of a single blink per several seconds and the test will attempt to enter a loop to exercise signal lines to aid in debugging EPROM Checksum Test The EPROM Checksum test verifies the EPROM has the correct program by adding up all the values in the EPROM The test also verifies the 4 separate banks and the bank switching of the MC 12 MC 12 Balanced First the data in each of the 4 banks of the EPROM is added up The checksum of each ba
192. cs 222 vss ru b E miM 5 EL s iod BM wel 5 dug 3 lt 5 E 5 __ 23 8 BO g B em u34 24 71 emai Ons hugs 222 Fer 3 e use ES 7 bed 05 28 Lor TATED ios STATED WA ust BIBER DON M 22 vo ga Em 226 vie 082 ES vn an 226 Lexicon 8 137 MC 12 MC 12 Balanced Service Manual Your Notes 8 138 Lexicon 30 1 13385 Y N 31 25
193. different outlet so that the computer and receiver are on different branch circuits If necessary the user should consult the dealer or an experienced radio television technician for additional suggestions The user may find the following booklet prepared by the Federal Communications Commission helpful How to identify and Resolve Radio TV Interference Problems This booklet is available from the U S Government Printing Office Washington DC 20402 Stock No 004 000 00345 4 Le pr sent appareil num rique n met pas de bruits radio lectriques d passant les limites applicables aux appareils num riques de la class B prescrites dans le R glement sur le brouillage radio lectrique dict par le minist re des Communications du Canada Copyright 2002 Lexicon Inc Rights Reserved Lexicon Inc e 3 Oak Park e Bedford MA 01730 1441 e Tel 781 280 0300 e Customer Service Fax 781 280 0499 Lexicon Part 070 14828 Rev 0 Printed in the United States of America Safety Suggestions Read Instructions Read all safety and operating instructions before operating the unit Retain Instructions Keep the safety and operating instructions for future reference Heed Warnings Adhere to all warnings on the unit and in the operating instructions Follow Instructions Follow operating and use instructions Heat Keep the unit away from heat sources such as radiators heat registers stoves etc including amplifiers which produce heat
194. down the amplifier 13 Remove the RCA output cables from the Zone 2 Var Left and Right outs of the MC 12 MC 12 Balanced to the amplifier 14 With a pair of XLR cables connect the Left and Right Zone 2 Fix balanced outputs of the MC 12 MC 12 Balanced to the XLR balanced input of the amplifier 15 Power on the amplifier press play on the DVD player and repeat Step 7 9 Remaining Digital Inputs to Zone 2 Output Test This test will verify the path of all the remaining Digital Coax and Optical Digital inputs to the Zone 2 Fix Front Left and Right analog output 4 6 Lexicon Note In order to test the Optical 6 which is an Optical Mini Jack style connector you will need Optical to OMJ adapter in order to make the proper connection 1 2 ou o Connect the digital output source DVD player to the 2 Coax Digital input on the rear panel of the MC 12 MC 12 Balanced Connect the RCA Left and Right Zone 2 Fix outputs of the MC 12 MC 12 Balanced to the amplifier Left and Right inputs and the outputs of the amplifier to a pair of speakers If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter In the Diagnostic Menu select Audio Tests Highlight S PDIF Input CX2 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see digital audio from the S PDIF 2 digital input to the Fix L
195. em 76 63920009 5 0099 SNUNAG LNO xv NIV 910 26 lt gt coo wf ew 848800 648 001 OHL LNO OL NIVW DIG 161 ewa gt Fw wu wu 76 64800009 84800009 NIV 110 NIVW INV OL EN EADEM SEES REESE a 100 NIVW DINV Ol NIVW 910 0008 z or 094 mu eef 848 0009 s38p0009 100 NIVW SINY NI EXVOO NIV ig 00089 lt 500 209 ef Zee LNO NIVW SINY OL 87 wooss or 166 5480004 54680009 NIYO 100 NIVW NV OL SIG 181 vt ctc uere sees ROSE 100 NIVW NI NIVW 910 00088 021 412809 00084 wu ew vu 266 54880009 5 8 0009 SNENAG 1nO
196. failure the offending test will cycle and the error code will be displayed on the 25 line For example if the analog FPGA verify fails the VFD will show ANLG FPGA TEST Fail E 0A If the operator wants to continue he can hit the Mode Up button Some tests require the operator to help with the test This may be just to hit the Mode Up button or it may require the operator to turn the encoder to iterate through the test Upon completion of all of the tests the 274 row of the VFD shows Pass or Errors LOOP Tests Entering LOOP Tests The Loop burn in suite is available from the top level DIAGS MENU when the LOOP TESTS item is selected When the operator selects that menu item the VFD will display LOOP TESTS NON VOL RAM SETUP 5 15 MC 12 MC 12 Balanced Service Manual The NON VOL RAM setup initializes the non volatile section of the SRAM with a byte that is verified by the loop tests As the unit is in burn in this byte is continuously verified ensuring that the register section of the SRAM continues to hold data Rotating the encoder knob will display the following on the VFD START ALL TESTS When the Start All Tests menu option is selected the Loop tests are run continuously These are the tests available in the Loop Test Suite List of LOOP Tests 2180 EPROM checksum 2180 FLASH checksum 2180 Burn In SRAM FPGA Verify ID SHARC Internal GPIO x4 SHARC SRAM x4 SHARC SDRAM x4 SHARC Boot x2 DAR FPGA Verify
197. for the Front outputs MAIN DACOUT selects the respective DAC outputs for all of the other Main outputs Center Mono Sub L R Sub L R Side L R Rear whereas MAIN DIRECT SEL selects the 5 1 analog inputs directly MAIN OUTPUTS schematic sheets 14 16 Sheets 14 15 and 16 are identical with each sheet including four of the twelve Main output circuits One of the circuits is described below The output from the analog switch goes to a CS3310 output level control This level control operates from 5V rails with gain range from 31 5 to 95 5 dB 0 5 dB steps Each CS3310 controls a signal pair The outputs from the level control feed a dual op amp Each op amp is configured as an inverting amplifier with 10 4 dB of gain The output signals pass through DC blocking caps and relays before going to the RCA connectors The relays mute the Main outputs during a power cycle and whenever the unit is in Standby or Off Three separate 2N4401 transistors are used to drive four relays each to minimize the stress on the transistor The CS3310 outputs also to 34 pin connector on sheet 19 This connector is used for routing the audio to the XLR board in MC 12 Balanced models ANALOG FPGA schematic sheet 17 A Xilinx 144 pin FPGA is the brains behind the analog board Its purpose in life includes e 3 internal clock trees for the Main Record Zone 2 A D and D A converters Provides independent outputs for A D and D A co
198. from the S PDIF digital 81 input to both the RCA and Optical S PDIF digital output connections 7 Press play on the DVD player 8 Slowly increase the volume on the amplifier to a comfortable listening level from the speakers 9 Verify that you hear clean clear audio coming from the speakers 10 Power down the amplifier and MC 12 MC 12 Balanced move the digital cable from the S PDIF digital output to the Optical S PDIF digital output 11 Power on the amplifier and repeat Steps 7 9 Remaining Digital Inputs to Digital Output Test This test will verify the path of all remaining Digital Coax and Optical Digital inputs to the S PDIF RCA digital output 1 Connect the digital output source DVD player to the 82 Coax Digital input on the rear panel of the MC 12 MC 12 Balanced 2 Connect the Coax S PDIF output on the back of the MC 12 MC 12 Balanced to the digital input of the DAT machine 3 Connect the Left Right analog outputs of the DAT to the Analog Left and Right inputs of the amplifier and its outputs to a pair of speakers 4 If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter 5 In the Diagnostic Menu select Audio I O Tests 6 Highlight S PDIF Input Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see digital audio from the S PDIF digital 42 input to the S PDIF RCA digital output 7 Pres
199. gain At the bottom right hand corner of each sheet are two op amps These amplifiers are used when routing a 5 1 analog source One routes the Center and Subwoofer signals from Input 7 while the other routes the Surround L R signals from Input 8 Each inverting amplifier reduces the signal level by 4 4 dB MIC INPUTS AND MAIN A D CONVERTER schematic sheet 3 Up to four microphone inputs are provided on the MC 12 rear panel for future calibration features A 10 pin connector provides the interface to a separate small board that holds the 1 8 microphone connectors and preamplifiers This board is described later in this chapter A DG411 analog switch can select either Mic inputs 1 amp 2 when SELO is high or Mic inputs 3 amp 4 when SEL is high to be passed to the Main Input level control and A D converter When a Mic input is selected the Analog inputs are disabled by bringing MAIN ANLG EN low on sheets 1 and 2 The Main Input level control is the CS3310 which has a range from 31 5 to 95 5 dB 0 5 dB steps The 53310 operates 5 volt rails and cannot handle signal levels greater than 7 5 Vpp Two dual op amps provide the left and right differential audio signals to the A D converter The op amp circuits bias the signals at 2 5 V and attenuate it by 7 dB This means a 2 Vrms signal at the output of the level control will be equivalent to 0 dBFS after the A D conversion 6 23 MC 12 MC 12 Balanced Service Manua
200. inputs to the Main Front Left and Right analog output Note In order to test the Optical 46 which is an OMJ Optical Mini Jack style connector you will need an Optical to OMJ adapter in order to make the proper connection 1 Connect the digital output source DVD player to the 2 Coax digital input on the rear panel of the MC 12 MC 12 Balanced 2 Connect the RCA Left and Right Front outputs of the MC 12 MC 12 Balanced to the amplifier Left and Right inputs and the outputs of the amplifier to a pair of speakers 3 If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter 4 Inthe Diagnostic Menu select Audio Tests 5 Highlight S PDIF Input CX2 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see digital audio coming in to the S PDIF 2 digital input to the Front Left and Right RCA output 6 Press play on the DVD player 7 Slowly increase the volume on the amplifier to a comfortable listening level from the speakers 8 Verify that you hear clean clear audio coming from the speakers 9 Pause the DVD and power down the amplifier 10 In order to test the remaining Digital inputs both RCA and Optical you must move the Digital Input cable to the next Digital input RCA or Optical then highlight the input being tested in the Audio I O Tests Menu and select it by pressing the Right Menu button 11 Repe
201. is operating if the front panel Standby button is pressed the unit goes into a low power standby mode Pressing any front panel button or any remote key will bring the MC 12 MC 12 Balanced out of low power standby mode No diagnostics are run when the unit is brought out of standby DIAGNOSTICS REPORTING All diagnostic functionality is reported to the VFD Vacuum Fluorescent Display and to the front panel LEDs They report on what test is being executed and if the test passed or failed The LEDs are utilized to report diagnostic status in the event that the VFD is not functioning Diagnostic status and data is also available on an external PC or a terminal via the serial debug port located at the D9 connector labeled RS232 2 on the rear panel of the MC 12 MC 12 Balanced The D9 connector labeled RS232 1 is used for updating the flash memory In the event a diagnostic failure occurs additional failure information such as data sent data received address location etc is listed in the error log The error log can be viewed either via the VFD or it can be sent to the serial debug port VFD Vacuum Fluorescent Display The VFD is the primary source of information during diagnostics The exact display information will depend on the test or tests being executed When an individual diagnostic test is executed the VFD will display the name of that test Groups of tests such as during power on diagnostics or the burn in loop have a generic me
202. on sheet 6 MAIN D A CONVERTERS schematic sheets 8 13 There are 12 outputs for the Main Audio Path The D A circuitry is shown for two outputs on each sheet The circuitry is identical for all twelve outputs The AD1853 is a stereo multi bit delta sigma 24 bit D A converter that operates at sample rates up to 192 kHz Each D A IC is configured in mono mode This means there are two D A converters being used to provide each of the MC 12 s twelve outputs By doing so this topology insures the best performance in terms of high level THD and dynamic range The Analog FPGA sheet 17 is the source for the clocks and data for the D A converters The data is manipulated in the FPGA to create an inverted copy of the DAC s left channel data for its right channel necessary to operate the DACs in mono mode The MCLK SCLK and LRCK clocks are distributed from the Analog FPGA sheet 17 The MCLK is at 256x the sample rate FS and is inverted and distributed independently for each DAC pair The SCLK 64xFS and 1xFS are distributed to three sets of four DACs via separate source resistors All of the D A converters operate in 25 mode The AD1853 DACs are configured through their serial ports pins 3 4 5 FRONT DAC 5 puts the Front L R pair of DACs into reset while all other DACs share the same reset line MAIN DAC RST The AD1853 has current outputs The combined currents OUTL and OUTR fed to one summing node of a dual
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204. press the Right Menu button 12 Select any of the 5 Composite or 8 S Video Inputs of the MC 12 MC 12 Balanced from the DVD1 Video In Menu 4 14 Lexicon 13 Scroll to the COMPOSITE 1 Video input and press the Right Menu button This will assign the Composite Video input 1 Jack to all composite Video output jacks both in Main and Record of the MC 12 MC 12 Balanced 14 Press the OSD button on the remote This will turn off the on screen video information from the MC 12 MC 12 Balanced and allow you to view the video for the DVD The video path is now set for testing Test 1 Load a disc into the DVD player and press play 2 Verify a clean undistorted picture appears on the screen 3 Pause the DVD 4 Testthe remaining Composite outputs by switching the Composite output cable to Main2 and Record 1 2 and repeating steps 1 3 above 5 Pause the player 6 Totest the remaining Composite video inputs of the MC 12 MC 12 Balanced leave the Composite Video output on Record 2 output 7 Switch from the Composite 1 input to the Composite 2 input 8 Select the Composite 2 to 5 in the DVD1 VIDEO IN Menu as stated in the Setup section above then repeat steps 1 to 3 above S VIDEO INPUTS TO S VIDEO MAIN AND RECORD OUTPUTS TESTS This test will set up a simple pass through of Video information in order to verify the S Video switching properties of the MC 12 MC 12 Balanced Setup Connect the S Video output from the DVD to th
205. run and report if it passes every time it successfully completes the test If the test fails it will attempt to loop to keep the signal lines active for debugging purposes In addition test progress and failure information is available via the serial debug port Specific failure information will depend on the test being executed Pressing and holding the Mode Up button returns the user to the top level diagnostic menu EXTENDED DIAGNOSTICS SUITE The Repair Diagnostic Suite allows one to run every diagnostic test on the unit The Functional Suite uses the same tests as the Repair Diagnostic Suite but automates how the tests are run The following tests are available in the Functional Repair Diagnostics Extended Diagnostics Test List 2180 EPROM checksum 2180 FLASH checksum 2180 SRAM FPGA Verify RS232 Wrap Test SHARC Tests SHARC 4 PAIR 0 PROC A PAIR 0 PROC B PAIR 1 PROC A PAIR 2 PROC B SHARC SRAM x4 PAIR 2 PROC B SHARC SDRAM x4 PAIR 0 PROC A PAIR 0 PROC B PAIR 1 PROC A PAIR 2 PROC B SHARC WCLK x4 SEL 44 WORD CLK SEL 48 WORD CLK SEL 88 WORD CLK SEL 96 WORD CLK SEL 44 48 PLL WCLK SEL 88 96 PLL WCLK SEL DRCVR WCLK PAIR 0 PROC A PAIR 0 PROC B PAIR 1 PROC A PAIR 2 PROC B 5 11 MC 12 MC 12 Balanced Service Manual SHARC Boot x2 PAIR 0 PAIR 1 DAR FPGA Verify Audio FPGA Verify 549326 Boot Test CS4820 ID Test Analog FPGA Verify IR Remote VFD Memory Test VFD CHAR Test VFD BLOCK Test OSD CHAR
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207. that each LED turns on and off when depressed and that the display acknowledges its function 9 Press all the buttons on the remote and verify that the display is responding to all the remote commands POWER SUPPLY TEST The main power supply in the MC 12 MC 12 Balanced has an operational range of 100 240 VAC 50 60Hz 90Watts The following test is for North American line voltage of 120VAC Set the variable AC supply to 0 volts Verify that the MC 12 MC 12 Balanced is powered off at its rear panel power switch Connect the power cord between the supply and the MC 12 MC 12 Balanced Turn on the MC 12 MC 12 Balanced using the rear panel power switch Slowly bring up the voltage to 120VAC The current draw will bounce up and down a bit and should not exceed 1 5amps Once you have achieved 120VAC the current draw on the Variac should not exceed 0 6amps If the MC 12 MC 12 Balanced draws an excessive current turn the MC 12 MC 12 Balanced off and check the power supply rails for shorts to ground with the DMM meter 7 Using the DMM measure all the power supply rails as stated by the test points below being sure to use the MC 12 MC 12 Balanced chassis as ground 8 Verify that all voltages are within the tolerance range shown oo0RON 2 Main Board Supply Rail Tolerance Location facing front panel 5VD 4 94 5 26 Lower left hand corner connector J31 Red wires to ground Battery 22 5 Right side to the Left of U69 Mea
208. to achieve lock based on R122 R123 When the phase comparator detects that the duty cycle is 1 64 the loop is considered to be in lock and special gating logic within 019 disables the PUMP DOWN pulse so only LOCK DOWNY remains active This greatly reduces the gain of the loop based on R124 The reduced loop gain in lock means that the VCO frequency remains relatively insensitive to phase fluctuations jitter of the reference yet when out of lock it can slew rapidly to track abrupt reference frequency changes as when switching to a different sample rate When the PLL circuitry is not operating closed loop U45 1 drops to around 13V and VCOV eventually rises to around 13V Under these circumstances the VCO oscillates at a poorly controlled high frequency of 30MHz or higher Analog BOARD OVERVIEW The MC 12 Analog Board encompasses all of the analog audio inputs and outputs level controls and A D and D A converters This board is separate from and is located immediately above the MC 12 Main Board All the Digital Audio I O connectors transmitters and receivers are found on the Main board The MC 12 can be described as a complex audio switch matrix There are three separate signal paths Main Record and Zone 2 Each of the 8 analog stereo inputs or 13 digital inputs can be routed to any or all of the three paths The Main path digitizes the analog signal if selected and passes it to the DSP Please refer to the
209. to the Left and Right 1 RCA input to the Record Fix Left and Right outputs 6 Slowly increase the volume on the amplifier to a comfortable listening level from the speakers 7 Sweep the oscillator from 20Hz to 20kHz Verify that you hear clean clear audio coming from the speakers 8 Power down the amplifier and move the cables from the Record Fix Left and Right outputs to the Record Var Left and Right outputs 9 Power the amplifier and repeat the oscillator sweep as described in Step 7 4 4 Lexicon Remaining Analog Inputs to the Record Fix Output Test This test will verify the path of the remaining analog Left and Right inputs 2 to 8 to the Fix Record Left and Right analog outputs pass signal 1 Connect the oscillator output to the Left and Right audio inputs marked 2 on the rear panel of the MC 12 MC 12 Balanced 2 Connect the RCA Left and Right Record Fix outputs of the MC 12 MC 12 Balanced to the amplifier Left and Right inputs and the outputs of the amplifier to a pair of speakers 3 If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter In the Diagnostic Menu select Audio Tests Highlight Audio Input 2 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see audio coming in to the Left and Right 2 RCA input to the Record Fix Left and Right outputs Slowly increase the volum
210. train of active low pulses occurs on PLL PUMP DOWN PLL Error Amplifier Filter main board schematic sheet 18 The non inverting input of op amp 045 is biased at 2 5V by a voltage divider from the regulated 5VA The pump pulses from U19 are buffered by U33 and connect to schottky diodes D12 D13 When no pulses are asserted the diodes are reverse biased and no current is injected into the summing node of U45 When the VCO frequency is too low D12 will be forward biased by UP pulses asserted low by U33 The resulting current through R122 gets integrated by feedback capacitors C172 and C171 to produce progressively higher voltage at VCOV which raises the VCO frequency Conversely DOWN pulses asserted high produce progressively lower voltage lowering the VCO frequency R125 damps the transient response of the loop The integrator is the dominant element of the loop filter The tendency of the closed loop is to adjust VCOV to synchronize the VCO frequency with the reference PLL Behavior in Lock main board schematic sheet 18 In lock both of the pump pulses are inactive and other circuitry determines the behavior of the loop The loop enters a special state that produces high purity oscillation In lock LOCK DOWNY delivers a train low going pulses at 44 1 or 48kHz whose average duty cycle is designed to be about 1 128 independent of frequency Instability or jitter in the reference will appear as variations in pulse width but t
211. video information from the MC 12 MC 12 Balanced and allow you to view the video for the DVD The video path is now set for testing OU ROMA 1 Load a disc into the DVD player and press play 2 Verify a clean undistorted picture appears on the screen 3 Pause the player 4 Testthe remaining S Video outputs by switching the S Video output cable to Main2 and Record 1 2 and repeating steps 1 3 above Pause the DVD player e 4 15 MC 12 MC 12 Balanced Service Manual To test the remaining S Video inputs of the MC 12 MC 12 Balanced leave the S Video output on Record 2 output Switch from the S Video 1 input to the S Video 2 input You must select the S Video 2 8 in the DVD1 VIDEO IN Menu as stated in the Setup section above then repeat steps 1 3 above COMPONENT INPUTS TO COMPONENT OUTPUT TESTS This test will set up a simple pass through of Video information in order to verify the Component video switching properties of the MC 12 MC 12 Balanced Setup 1 Connect 3 wire Component Video output from the DVD to the MC 12 s Component Video 1 input 2 Connect the 3 wire Component BNC video outputs of the MC 12 MC 12 Balanced to the Monitor s BNC Component Video Inputs 3 Turn on the DVD Monitor and MC 12 MC 12 Balanced 4 The Monitor should have a blue screen display 5 Onthe MC 12 MC 12 Balanced remote press the DVD 1 button to select this as the Input for testing the video paths
212. wast wer 00 P d 00 Ei MOTA RENE 9 710 9 snivis 557275 007275 W ST LN vt s la rx pu 00 15000 0 11 1a 8 ama DET WU SNOISIASH 0 IONLNOO T 4 9 4 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 18 Lexicon 8 5 wer same presser Dena us E Y 8 5 9 eene e ve L saco 66 92 72 5 66 92 04 NIVH WEHOS pas
213. when an analog 5 1 channel source needs to be processed RECORD AND ZONE 2 D A CONVERTERS schematic sheets 5 amp 6 Sheets 5 and 6 are identical with one minor difference on the Zone 2 output at the lower right hand corner The Record path is on sheet 5 and Zone 2 path on sheet 6 The 4395 24 bit delta sigma stereo D A converter operates up to 192 kHz Each DAC is configured through its serial control port pins 8 10 11 with a separate Reset pin The output of the DAC passes through a 3 order low pass filter with its 3 dB frequency at 100 kHz The filter topology is a compromise between the flat passband Butterworth filter and the Bessel filter with its superb transient response The filter is pretty much flat out to 20 kHz It has an overall gain of 1 4 dB when measured at the test points This means a 0 dBFS signal at the D A converter will be 2 Vrms going into the analog switches DG411 analog switches select either the output of the respective DAC or the analog input source directly for the Record or Zone 2 outputs The selected signal goes off to sheet 7 to the fixed level outputs and to the on page CS3310 output level control Both Record and Zone 2 have two sets of analog outputs One set is labeled Fixed and has a maximum output level of 4 Vrms that cannot be varied The other set is labeled Variable and has an associated level control to vary the output level The Fixed outputs provide a unity gain path through the MC
214. will discharge C243 sufficiently When CHARGE drops below about the emitter of becomes reverse biased which asserts T RUN low When both encoder phases return high C243 is allowed to charge through R263 delaying the rise of CHARGE If either encoder phase returns low before CHARGE reaches around 4V another TRIGGER event is initiated and the sequence restarts When CHARGE finally is allowed to reach the emitter of becomes forward biased and T RUN returns high ending the detection sequence At that point logic within U79 updates the internal 2 bit position reguster Each complete T RUN cycle corresponds to a single transition between detents and direction is determined by whether ENCODER A or ENCODER B was the first phase asserted at the start of the cycle The timing circuit acts as a retriggerable one shot multivibrator whose interval begins when both encoder phases have returned high The time is chosen to be longer than the duration of expected sliding contact dropouts If both encoder phases are at a high level that state could either represent a brief dropout or it could represent a legitimate detent state Discriminating between the two is based on time The time must not be too long however because legitimate transitions occur close together when the encoder is rotated rapidly The time chosen for the MC 12 encoder is around 1msec and represents a good compromise between rejecting noise and accepting legitimate
215. 0 0078276 498 5072576 Blk W 00 t28000 wad WISE AN SNOTSTARE T v 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 70 Lexicon 8 71 17 e v 4 9 L 8 ot ix esset 00 2 5 00 qunser 3 24 essex oso g amman saco 00 2 5 X Tap SINALNO ZANOZ 00 2 5 HMN TIOW GH O T S INV W3HOS 06410 xwa LOO LX 9 E ET 440 5 12479 etta ozta oot 100 100 XuorRoz xg 48 9 ore aste ast suzo v sagpo 1 4 oot w 28 4 9 1 81404100 S IHVINVA CHNOZ ZHNOZ NIST
216. 0 07 905 8 21 0 IN3WdIHS ASSY 3 1 625 Fu 0 405 66691 0618 334 5214 3000 Yva YVAN 0 NI 138 1 1 0 405 303 XO8 ONiddIHS NO 138 1 01 0 0235 30 14 6 ONY 54 13 35010 ONiddIHS OINI XOG YANNI 405 6214 3000 39 4 MNYIB NI 138 1 14 07 305 304 30 45 01 138 1 01 54 13 35079 0 53234 30 401 NO 55300 1 Or dOS ONV BZL ON X04 Q3lvWOdH3d 3AON3N LINN 30 53015 NO 1435 WvO3 401 30 14 9 IN3SNI WOLLOB NI UNN 136 ISN LINN 30 3015 NO 5 ONY 0703 OVE NI NO INJA 0 14 AINO 09 405 303 9 JHL 30 NI v OL 53934 2 AT8W3SSV 1835 NOLLO8 0 405 z86vi zzof 82 2 8891 2208 zi oW lt 0 1 2204 10N 00 AINO 3ON3H3434 NMOHS SH3BADN Dd S310N 1 35V8 LYISNI 5034 9 6 0 405 8 6 1 09 0 5014 2 g zi oW 90961 09
217. 0 110 00 1 00 1 00 4 00 1 00 1 00 4 00 2 00 2 00 1 00 1 00 3 00 20 00 1 00 3 00 1 00 1 00 3 00 2 00 R170 171 183 186 195 R196 R180 188 R167 168 182 184 185 R190 193 194 199 200 R137 R106 108 111 113 201 R203 204 R133 134 R107 109 110 112 202 R65 R140 R100 104 181 189 R141 R138 C115 116 120 C25 C40 51 59 163 167 C31 104 117 119 142 C150 160 C88 97 114 C90 C72 C139 C32 33 102 C28 36 C26 94 C29 C30 C64 69 146 C35 C155 C140 C1 24 27 34 37 39 C41 50 60 63 66 67 C70 71 73 87 89 92 C93 95 96 98 101 103 C105 113 121 138 141 C143 144 149 151 C152 156 159 161 C148 C153 C65 68 145 147 C154 C91 FB1 4 L17 18 D1 7 D5 D6 D2 4 Q4 20 22 24 Q21 Q1 3 U19 U2 U3 5 U13 20 7 5 MC 12 MC 12 Balanced Service Manual PART NO 340 11495 340 13856 340 14791 345 10503 346 10507 346 10508 350 13921 350 14248 350 14785 365 13288 390 10516 390 13857 390 13858 410 13859 510 13128 510 13891 510 14079 520 00941 620 14766 680 14855 DESCRIPTION ICSM LIN LT1229 VID OPAMP SOIC ICSM LIN EL4421C VIDAMP W MUX ICSM LIN EL4422C VIDAMP W MUX ICSM INTER NJM2229 SYNSEP SOIC ISCM SS SWITCH 74HC4051 SOIC ICSM SS SWITCH 74HC4053 SOIC ICSM FPGA XCS05 3 10X10 PLCC ICSM SRAM 128KX8 70NS SOIC IC SPROM MC 12 VIDEO V1 00 ICSM UPROC MB90092 0SDC PQFP RESONATOR CER 503KHZ CRYSTAL OSCSM 14 31818MHZ TRI CRYSTAL OSCSM 17 73448MHZ TRI RELAY 5
218. 0 11 AOT 2 0 sauvaa re seta i MNT 07443 1 orav Wir 48 7 Y Wis 69 21 ane ee ance 8 19 MC 12 MC 12 Balanced Service Manual Your Notes 8 20 Lexicon i T e v 2 L 8 a 5 sc esset 66 8 20 8X 8 66 42 4 5 0 659 T 090 66 92 2 amomp 5 514 62 2 2 CIOW Q8 NIVW WSHOS GOW NOY NI SI dIHO NAHM ATIVNNHIXS LON NId SU 06110 AHL SI NON IV Lote W GENNER WI LOON 1008010 lt 10084 HLIM SHESIN 1859 NHHM O T
219. 0 754 40Hz of the reference level over the entire Sweep 12 Set the scale on the Distortion Analyzer to measure 100dBr signal level with the filter on 13 Turn off the oscillator to the MC 12 MC 12 Balanced and verify a noise level measurement lt 108dBr 14 Swap cables from the Left 1 RCA input to the Right 1 RCA input and the Left Front RCA output to the Right Front RCA output 15 Repeat Steps 1 to 13 above 16 To test the remaining Left and Right RCA XLR outputs for required specifications you will need to repeat the above tests using the same RCA 1 Left and Right inputs to the remaining RCA and XLR Left and Right outputs 17 Repeat steps 1 16 again until all the analog outputs are tested ALL REMAINING AUDIO RCA INPUTS LEFT AND RIGHT TO FRONT LEFT AND RIGHT RCA OUTPUT TESTS Setup 1 2 3 4 5 Connect an audio cable between the output of the Low Distortion Oscillator and the MC 12 s Left RCA 82 audio input Connect an audio cable between the Center RCA output of the MC 12 MC 12 Balanced and the input of the Distortion Analyzer Place the MC 12 MC 12 Balanced into Extended Diagnostics as described at the beginning of this chapter In the Diagnostic Menu select Audio I O Tests Highlight Audio Input 2 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see audio coming in to the Left and Right 2 RCA input to the Front Left and Right RCA output and all th
220. 022 pel p e pet 008 110 HVA 3NOZ 01 x96 NI 02 3NOZ Old CEN 00011 2 3 eu 166 5480009 53800 09 LNO 3NOZ 396 NI IXVOO 3NOZ 511 612 eu eu eu XVIX 100 3NOZ Ol NI IXVOO 3NOZ 812 Wig 0006 0009 00096 2 01 gt 007051 00086 teuexi lt 412809 2000 020 500 soo soos 8488001 __5 8 100 3NOZ OL i66 1xvoo INOZ gt 207920 oror eooo ap ww wu _____ xowwozoi 548001 s4800 LNO HVA HIX INOZ SINV OI IXVOO SNOZ 910 912 00096 __ _____ lt 01 6023 me sunt vu 5 5 76 5480004 8 0007 NIVO LNO INOZ OI 396 1XVCO 3NOZ 910 912 E po er vp E spo pcp m L 110 HVA YIX DINV OL 96 NI IXVOO 3NOZ 91A epu 921nos 18013 paun 7 1891 oipny 39012 puo nea
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223. 1 5 3 1 00 422 TO VIDEO BD MC 12 MC 12 Balanced ANALOG 1 BOARD PART NO 202 09794 202 09872 202 09873 202 09899 202 10426 202 10557 7 6 DESCRIPTION 55 0 0805 RESSM RO 5 1 10W 33 OHM RESSM RO 5 1 10W 10K OHM RESSM RO 5 1 10W 47 OHM RESSM RO 5 1 10W 15K OHM RESSM RO 5 1 10W 4 7K OHM QTY EFFECTIVEmINACTIVE 32 00 21 00 20 00 3 00 4 00 8 00 REFERENCE R157 159 163 164 179 R180 191 192 198 199 R205 206 212 213 219 220 226 227 236 237 R243 244 250 251 326 R335 411 415 419 572 R574 575 R546 558 562 565 567 R569 571 R3 4 7 8 11 12 15 16 R19 20 23 24 27 28 R31 32 35 36 39 40 R412 416 420 R542 545 R559 561 566 568 R573 576 577 PART NO 202 10558 202 10559 202 10569 202 10571 202 10585 202 10586 202 10598 202 10890 202 10948 202 11041 203 10583 203 11743 203 11980 203 12371 203 12372 DESCRIPTION RESSM RO 5 1 10W 47K OHM RESSM RO 5 1 10W 100 OHM RESSM RO 5 1 10W 10 OHM RESSM RO 5 1 10W 100K OHM RESSM RO 5 1 4W 51 OHM RESSM RO 5 1 4W 100 OHM RESSM RO 5 1 10W 330 OHM RESSM RO 5 1 10W 220 OHM RESSM RO 5 1 10W 390 OHM RESSM RO 5 1 10W 680 OHM RESSM RO 1 1 10W 10 0K OHM RESSM RO 1 1 10W 100K OHM RESSM THIN 1 1 10W 10 0K OHM RESSM THIN 1 1 10W 2 74K OHM RESSM THIN 1 1 10W 4 99K OHM Lexicon QTY EFFECTIVEmINACTIVE REFERENCE 23 00 14 00 11 00 16 00 12 00 36 00 1 00 1 00
224. 1 R64 66 67 69 72 74 R75 77 80 82 83 85 240 13642 CAP ELEC 47UF 25V RAD NPOL 6D 28 00 C43 44 49 50 53 54 C59 60 63 64 69 70 C73 74 79 80 83 84 C89 90 93 94 99 100 C103 104 109 110 240 13803 CAP ELEC 560UF 35V RAD LOW ESR 2 00 C156 157 241 14676 CAPSM TANT 1UF 25V 20 28 00 C45 46 51 52 55 56 7 12 C61 62 65 66 71 72 C75 76 81 82 85 86 Lexicon PART NO DESCRIPTION QTY EFFECTIVEmINACTIVE REFERENCE C91 92 95 96 101 102 C105 106 111 112 245 10562 CAPSM CER 150PF 50V COG 10 28 00 C1 3 4 6 7 9 10 12 C13 15 16 18 19 21 C22 24 25 27 28 30 C31 33 34 36 37 39 C40 42 245 10587 CAPSM CER 18PF 50V COG 10 24 00 C119 120 123 126 C129 132 135 136 C138 139 142 145 C148 151 154 155 245 10588 CAPSM CER 33PF 50V COG 10 4 00 C113 114 117 118 245 12485 CAPSM CER 1UF 25V Z5U 20 14 00 C115 116 121 122 C127 128 133 134 C140 141 146 147 C152 153 270 00779 FERRITE BEAD 28 00 FB1 28 270 06671 FERRITE CHOKE 2 5 TURN 2 00 FB29 30 300 11599 DIODESM GP 1N4002 MELF 2 00 D1 2 310 10566 TRANSISTORSM 2N4401 SOT23 2 00 Q1 2 340 10552 ICSM LIN MC33078 DU OPAMP SOIC 7 00 U15 21 340 13911 ICSM LIN DRV134 BAL LINE DRVR 14 00 U1 14 410 11639 RELAY 2P2T DIP 5V HI SENS 14 00 RY1 14 510 10881 CONN XLR 3MC PCRA PLASTIC 14 00 J1 14 510 14890 CONN POST 100 HDR 2X17MCG LK 1 00 J15 620 12428 LUG 4 INT STAR XLR GND 14 00 J1 14 MC 12 MC 12 Balanced CHASSIS ASSEMBLY Note items are on MC12 only items are on MC12B only PART NO DESCR
225. 1 00 2 00 6 00 36 00 36 00 36 00 68 00 03 28 01 m R149 150 155 156 167 R168 184 185 232 233 R256 265 413 417 421 R175 176 186 187 193 R194 200 201 207 208 R214 215 221 222 R166 182 190 197 R204 211 218 225 R238 245 252 R43 44 51 52 59 60 R67 68 75 76 83 84 R91 92 99 100 R288 291 294 297 300 R303 306 309 312 315 R318 321 R1 2 5 6 9 10 13 14 R17 18 21 22 25 26 R29 30 33 34 37 38 R41 42 49 50 57 58 R65 66 73 74 81 82 R89 90 97 98 R579 R578 R183 R165 181 R239 240 246 247 R253 254 R422 424 432 434 R442 444 452 454 R462 464 472 474 R482 484 492 494 R502 504 512 514 R522 524 532 534 R121 122 125 126 129 R130 133 134 137 138 R141 142 425 428 435 R438 445 448 455 458 R465 468 475 478 485 R488 495 498 505 508 R515 518 525 528 535 R538 274 277 282 283 342 R345 350 351 356 359 R364 365 370 373 378 R379 384 387 392 393 R398 401 406 407 431 R441 451 461 471 481 R491 501 511 521 R531 541 R105 120 145 146 R151 152 278 280 285 R346 348 353 360 361 R363 366 374 375 377 R380 388 389 391 394 R402 403 405 408 427 R430 437 440 447 450 R457 460 467 470 477 R480 487 490 497 500 7 7 MC 12 MC 12 Balanced Service Manual PART NO 203 12719 203 12969 203 12970 203 13132 203 13134 203 13537 203 13638 203 14296 204 14794 240 09367 240 09786 240 11111 240 12330 240 13217 240 13642 241 09798 241 11799 7 8 DESCRIPTION RESSM THIN 196 1 10W 2 00K OHM RESSM
226. 1 Oe coge 581 osa 1355 015451 108 0 19 6 vo V 10 6 19 71 Sm cour 7 Tu asa 9 8 Emi ur 58 52 1581 27 11 52 150 02454 w e 0 61 ca 59 78 En TET DR e teo T1 19 6 ie Eu 44 Bati 5612 1315 5s 490 0 Lv BT 80 tt to 6 MX 0 71 10 6 5644 Tk SINIOd 1981 onre 38 S 08 swe zs 6 res 107678 En 2 weet rar oar avis a 45 LR TO LZZTOO waa HOIH wer ance BOOHADL 877761 TOT SESE E o0 Lz6000 m 067275 507275 UI E xov 94 01 18 6 vo v 557179 wet oo rtsooo 1 25 5 MC 12 MC 12 Balanced Service Manual Your Notes 8 30 Lexicon 8 31
227. 10 14079 510 14796 510 14833 510 14835 520 04999 635 14671 640 01701 701 09640 704 06165 704 14452 DESCRIPTION ICSM SRAM 32KX8 70NS SOIC 20UA ICSM SDRAM 512KX32X4 3 3V TSOP ICSM FPGA XCS20XL 4 20X20 PQFP IC ROM 27C020 MC12 MAIN V1 00 ICSM UPROC ADSP21065 60MHZ PQF ICSM UPROC Z88180 33MHZ PQFP ICSM UPROC CS49326 DD DTS PLCC ICSM UPROC PIC16C54 MC12 V1 00 RESONATOR CER 4 00MHZ 5 5MM CRYSTAL OSCSM 29 491MHZ TRI CRYSTAL OSCSM 30 0MHZ TRI 3 3V CRYSTAL OSCSM 22 5792MHZ TRI3V CRYSTAL OSCSM 24 576MHZ TRI 3V LEDSM INNER LENS RED LEDSM INNER LENS YEL LEDSM INNER LENS GRN BATTERY LITH 3V 160MAH HORIZ XFORMER PULSE AES 1 1 2X 4SP CONN JUMPER 1X025 2FCG CONN EURO C ROW A C FEM CONN EURO C 48P ABC RECP VERT CONN POST 100X025 HDR 3MC CONN DSUB 9FC PCRA 4 40THD INS CONN POST 100X025 HDR 6MCG CONN POST 156X045 HDR 2MCG LOK CONN POST 079 HDR AMC PHONE JACK 3 5MM PCRA 3C STER CONN POST 100X025 HDR 2MC POL CONN POST 100 HDR 2X30MCG LK CONN POST 100 HDR 2X7MCG LP CONN RCA PCRA 1FCGX2V BLK GND CONN RCA PCRA 1FCG BLK GND CONN OPTO PCRA TORX173 6MBPS CONN HDR 200 6MC PCRA CONN POST 100 HDR 2X13MCG POL CONN POST 156X045 HDR 4MC LOK CONN XLR 3FC PCRA LATCH METSHL CONN OPTO PCRA XMTR 13 2MBPS CONN OPTO PCRA RCVR OMJ 8MBPS IC SCKT 32 PIN MACH TIN SPCR PCB 4 40X5 8 219RD STEEL SCRW 4 40X1 4 PNH PH ZN BRACKET KEYSTONE 621 4 40X2 HEATSINK TO220 75X 5X 5 TAB HEATSINK TO220 MTTAB NUT 1 45H Lexicon Q
228. 100 23H OL 396 INI 23H 3391 581 V V su ww ww _________ 26 8 84860011 wu ev su 76 539000 Lux mi moz V E 58 1981 _ einseow ra 1891941 Des e loe qv pejoejes Ose SIoUUEUS JGUOIIMS aan LNO SINY OL 396 NI 40 NIVW 910 LNO NIVW SINY 396 NI 1140 NIVW DIG 454 100 NIVW 01 96 1140 DIG 1591 4 22 Lexicon Chapter 5 Troubleshooting Check the Lexicon web site for the latest software and information http www lexicon com The Lexicon Support Knowledgebase http www lexicon com kbase index asp V1 00 Release Notes The following are additions and modifications to the MC 12 MC 12 Balanced User Guide Rev 1 based on Software Version 1 0 note page numbers refer to the User Guide not this Service Manual 1 2 10 11 12 13 The Mute LED lights whenever mute is activated either manually or automatically by the unit For example the unit will briefly activate mute when changing input types or listening modes Page 2 3 When using an analog input source the ZONE 2 AUDIO OUTPUTS and RECORD AUDIO OUTPUTS are approximately 2dB higher than the MAIN AUDIO OUTPUTS labeled FRONT L R When using a digital input sourc
229. 110111 a nan ss eee 8 888 pepe tay meses p amp sr Em 5855 NUI E E m 12014 SUJAOO v SUHAOO H GHL LNO 140 289 DIG OL INI ANOZ NIVO 388 LAO 140 OL 3NOZ 388 LNO 140 HID OL LNF INOZ 96 LNO 1dO SIG 8 2 ONY WIVIX 96 110 140 93H OL SNOZ 9NV x96 INO 140 SIG OL 3NOZ 396 170 190 OIG Ol 100 140 SNHNAG 96 110 140 OIG OL ZN 3NOZ X96 LNO 140 BIG OL ANOZ OHL 396 140 9d SNOZ 96 140 934 DIG OL ZNi 3NOZ 396 LNO 140 DIG OL ANI 3NOZ 9 INV ONHNAG 496 LNO 140 O3H Ol INOZ O INV M96 110 190 DIG Ol INOZ DIY 6 140 BIG Ol 3NOZ 596 LNO 140 910 OL 9 INV 396 100 1dO 23H SIG INOZ SNUNAG 3196 100 140 Ol SNI 3NOZ WIVIX 96 INO 1dO INOZ SINY GHI 96 100 120 Ol SNI SNOZ NV
230. 12 for Record and Zone 2 analog inputs After the signal passes through the CS3310 it is boosted by 6 dB by a non inverting op amp and then goes off to sheet 7 The one schematic difference is the muting relay for the variable output is shown on sheet 6 for Zone 2 the respective relay for the Record variable output is shown on sheet 7 RECORD AND ZONE 2 OUTPUTS schematic sheet 7 The Record outputs are located in the upper half of sheet 7 Zone 2 outputs in the lower half The Record variable level outputs from sheet 5 come in on the left hand side of the schematic and pass through a muting relay before going to the output jacks The fixed level outputs come into non inverting stages with 6 dB of gain to insure unity gain for analog input sources These signals also pass through a 6 24 Lexicon muting relay on the way to the output jacks The relays for both the fixed and variable level outputs operate in parallel and are controlled by the signal The Zone 2 variable level outputs from sheet 6 come in on the left hand side of the schematic and go directly to the output jacks As in the Record path the fixed level outputs come into non inverting stages with 6 dB of gain to insure unity gain for analog input sources These signals pass through a muting relay on the way to the output jacks The relays for both the fixed and variable level outputs operate in parallel and are controlled by the ZON2OUT signal
231. 14080 520 00941 640 01701 641 13116 680 12320 701 14088 704 14452 Lexicon DESCRIPTION QTY EFFECTIVEmINACTIVE REFERENCE ICSM DAC AD1853 24BIT SSOP 12 00 U78 84 96 100 ICSM DAC AK4395 24BIT VSOP 2 00 U56 57 RELAY 2P2T DIP 5V HI SENS 10 00 RY1 10 LEDSM INNER LENS RED 1 00 03 28 01 m D23 LEDSM INNER LENS GRN 1 00 D22 CONN POST 100X025 HDR 2MCG 1 00 W1 CONN RCA PCRA 1FCGX2V WH RED G18 00 J1 18 CONN POST 100 HDR 2XSMCG LP 1 00 J30 CONN POST 100 HDR 2X17MCG LP 1 00 J33 CONN POST 156X045 HDR AMC LOK 1 00 J25 CONN POST 156X045 HDR 6MC LOK 1 00 J26 IC SCKT 8 PIN LO PRO 1 00 U102 SCRW 4 40X1 4 PNH PH ZN 1 00 077 H S SCRW TAP AB 4X3 8 FH PH BZ 18 00 J1 18 RCAS TO BRKT CABLE 100 PLUG SCKT 2X30C 1 5 1 00 J32 ANLG TO MN BD BRACKET ANALOG BD MC12 1 00 HEATSINK TO220 MTTAB NUT 1 45H 1 00 077 MC 12 MC 12 Balanced SWITCH LED BOARD PART NO 202 09795 202 10597 202 10599 202 10945 202 10948 240 09786 245 12485 300 10509 310 10510 330 10372 330 10537 330 14244 430 13639 430 13888 430 14527 453 13899 510 13145 680 14083 DESCRIPTION QTY EFFECTIVEmINACTIVE REFERENCE RESSM RO 5 1 10W 2 2K OHM 8 00 R39 46 RESSM RO 5 1 10W 180 OHM 15 00 R1 12 47 49 RESSM RO 5 1 10W 3K OHM 2 00 R37 38 RESSM RO 5 1 10W 1 5K OHM 13 00 R13 24 50 RESSM RO 5 1 10W 390 OHM 12 00 R25 36 CAP ELEC 100UF 25V RAD LOW ESR 1 00 C10 CAPSM CER 1UF 25V Z5U 2096 9 00 C1 9 DIODESM 1N914 SOT23 6 00 D37 38 43 46 TRANSISTORSM 2N3904 SOT23 1 00 Q1 ICSM DIGI
232. 20 1 veo vsn 2 x EUM T bee 25589018850 woz rv z Sagpo Um Lo n whee M 2 GEZI vast 4 mus 26 1 5260 aec 4 3 5 tH ast vase 6TED IZED 40 ortu Y LOdNI NIV 3 w anst wast NELNSANOO NIYW i etzo son ast noe Tas om 49 90 4 A n or adus fa de 2 Y ten 8 ast anst AST emi 514 1 9 ast Ga ooa 6 Li 4 wr om 2 aan WSI 3 rb f 2 Juno 4 sh T GE7i 1575271 Y ten air aste aw anst AST a WE 1072 1 078761 4 4 N MOLOSNNOO INANI Ed xoa aaa Er e 0076278 0078275 ex son 5576276 4572276 1 uos NOLIATHOSEG am
233. 2120 SISSVHO WMV HS X 002 1004 15951 16 ic 09405 9 821 1 1INOMJ 13 vSbvl Z0L 9G AINO 0 405 821 SVHO NL 8 6 61960 06 90 0 AINO 2128 SISSVHO 55300 I3NVd 0 LG 1845 Sd 01 AIS 314434 2 TAN 318V2 AL 88 00 066 61 TNVd 1 0190 I3Nvd 16091 20 96 Nd OL NNOO 0 19057 8050 NNOO 1621 1209 81 09405 I3NVd 0 8 12 T3Nvd 96091 201 66 AINO 8219 ZLOW 1 049 4000 NNOO 24861 06 91 AWO OrddS 9 821 1 SISSVHO 14991 001 5 231 dwNS OS OW NNOO 29811 06 751 l Sd 1804405 9801 004 SS 33208 5 06851 76 43 09 68071 00 7S SISSWHO 98091 00 LS 19257 NNOOG 311007 12960 021 71 w gasn 0 AINO 09405 921 1 ASSY MIX ld 8071 5560 OL 09405 ASSY 08 ld 186 1 lt 00 l 8 ZVON ASSY 08 AMOW3N Id 8 1 00 6 8 ASSY Q8 0 1 INY ld 99071 50 Z ASSY Q8 51 0140 ld 2909 620 9 L 09445 ASSY 08 Id 88691 620 00 2010108 023 8 ZVOW ASSY 08 ld 18 91 620 6 QE ETE 249 TES one ao ASSY d 0589 2040 ooa z ASSY ld 5811 60 Z ax 09405 dd ASSY
234. 22 068 190 90 OT 2 orea oo E 460 40 tryed Vast sm sur cr ota AST 1 SLED guo arm zr MIME ie Wane ove awe 4190 40 una 75155 DWG AEH wombs 271 1 4 SVO serewao ur Xoo t TERT ASTE aT aT 57 bar 36696 ELED zw tserav 42 5 amp amp 62 2 P ser 757627 1073277 1 3l 1 Wr xoa x 00795761 DOE gx Hn OE oo ozttoo Y MAS yoor ur vt 6 6 esaa 0576275 0072276 0 EIN vase am NOISHSANOO V G SNOISIAmE T 4 v 9 4 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 82 Lexicon 8 83
235. 254 261 264 271 274 281 284 C347 359 371 383 395 C407 419 434 446 458 C470 482 C157 158 167 168 C177 178 C3 4 7 8 11 12 15 16 C19 20 23 24 27 28 C31 32 35 36 39 40 C101 104 107 110 113 C116 119 122 125 128 C131 134 137 140 143 C146 153 156 159 163 C166 169 173 176 C179 431 C106 112 117 123 129 C135 141 147 161 171 C181 221 224 225 228 Lexicon PART NO DESCRIPTION QTY EFFECTIVEmINACTIVE REFERENCE C233 236 237 240 292 C295 299 302 304 307 C311 314 316 319 323 326 350 352 355 357 362 364 367 369 374 376 379 381 386 388 391 393 398 400 403 405 410 412 415 417 422 424 427 429 437 439 442 444 449 451 C454 456 461 463 466 C468 473 475 478 480 C485 487 490 492 244 10423 CAP MYL 22UF 50V RAD 5 6 BOX 8 00 C327 331 334 337 340 C342 344 346 244 10592 CAP MYL 2200PF 100V RAD 5 26 00 C184 185 190 191 196 C197 217 218 229 230 C242 243 252 253 262 C263 272 273 282 283 C291 297 303 309 C315 321 245 09291 CAPSM CER 470PF 50V COG 5 32 00 C187 188 193 194 199 C200 202 203 219 220 C231 232 245 246 249 C250 255 256 259 260 C265 266 269 270 275 C276 279 280 285 286 C289 290 245 10416 CAPSM CER 1000PF 50V COG 5 12 00 C201 204 247 248 C257 258 267 268 C277 278 287 288 245 10544 CAPSM CER 220PF 50V COG 5 12 00 C351 363 375 387 C399 411 423 438 C450 462 474 486 245 10561 CAPSM CER 100PF 50V COG 5 12 00 C205 216 245 10562 CAPSM CER 150PF 50V COG 10 68 00 C1 2 5 6 9 10 13 14 C17 18 21 22 25 26 C29 30 33 34
236. 396 1dO OL ANOZ 9 INV 36 100 140 Id OI INOZ 96 INO 1407038 010 OL 3NOZ 96 140 SIG OL INOZ 1nO 140 039 OI 2 ONV NIVO 3196 INO 1dO OIC OL 3NOZ 1 SNHNAG X96 INO 140 OIG OL 3NOZ X IV1X 396 110 140 OG OL 8402 ONY 596 LNO 140 BIG 01 3NOZ DINY gt Lot qo asnos equ puo 3196 170 140 988 SI OL 3NOZ 396 INO 140 DIG Ol INOZ i591 51851 0 9 4 18 Lexicon 4 19 LL LLL LL ria ou iuo uim A ___ 00088 ewa 002 swaf aun 46 23o 230 100 6TNV 196 NI BENE ERN POE a FECI MIN tact LNO UWA Ol x96 NI 1 23H Id Ba oorr wez or oooi 00808 wu 188 6380009 64600009 ONHNAC HVA NI IXVOO oo
237. 4 SY pe eu Iso s 8 2788 01 55 waa Ei Zar z Taz St ET ie ba 2 T oaz am Wz 5 za Ed aol anoz E 22114 s n 188 ogo omo xn 4 zw nd 506 lzy 9 os or E T aE 51 User e on a 55 EE T 107576 ay E zar IW eu mee pre Me saxon zeza wer pu ooie rer 927671 gu EA 00 126000 1 sues weis US A La s taf Lo et ae B5 oo tts000 quom Taw 071102 gt o sama SNOISIARE 8 15 MC 12 MC 12 Balanced Service Manual Your Notes 8 16 Lexicon 8 17 LO ST 02 21 2
238. 40 E 796 100 140 OL ONT NIVW SINY 96 100 180 or SNI NIVW 1 M96 LNO 140 O3 396 100 140 DIG OL SN NIVO 296 LNO 140 288 Ol SNI 100 140 DIC OL NIVW OSTNY 396 LNO 140 OL PNI NIVW WIVLX 96 LNO 140 038 OIG OI NIYIN SINY INO 140 OSH OI OL 3196 LNO 140 OSH SIT OL NINIVW E INV 396 LNO 140 23H OIG OL NIVW O INV SNBNAG 396 110 140 OL ENI NIVW XTV1X x96 100 140 SIG OL NIVW 96 110 140 9Id OL NIVW 9 INV 396 110 140 DIG OL NIVW 396 ANO 140 23H 210 OL NIVW DINV ONHNAG 96 LNO 140 SAH DI OL ZNI NIVW SINY WWLX 396 LNO 140 DIG OL ZNI NIVW OSTNY GHL 96 LNO 140 DIG OL ZNE X96 LNO 140 Old Ol NIVW X96 LNO 140 288 910 OL NIVW 96 LNO 140 INI NIVW 1 1 396 LNO 140 DIG Ol iN NIVW OSTNY OHL 98 LNO 140 910 OL NIVW 9 INV pL pee Ee e Lew pou uw pen pepe uve 5 96 1nO 140 088 OL ENT NIV 9 INV 796 110 140 OI INI NIVW SINY SNHNAG ING 140 Sid
239. 41 av oo SNOISIARE aas z T v 5 9 L 8 8 21 MC 12 MC 12 Balanced Service Manual Your Notes 8 22 Lexicon 8 23 5 2 E 9 L 8 g ez seesser 66 8 2 amp auss 8 8 EK pu 6 0071 253 rrr ausa 499 2 719 91 5 i 8 41 T saco 66 97 L ammo ses n _ eo e NESE Es Tino OLIO m x war 1881 WIS v te ers ke evasa SHI EVIST FD avasa E d lt was PENSION X ev mors SINE Y ance aac ce fo tela avasa 8450 Nra OL ane 1SN18 OL gar
240. 534 340 09244 340 10567 340 11597 340 13137 340 13883 340 14535 345 12038 345 13138 345 13139 345 13140 350 12456 350 13676 350 13854 7 2 DESCRIPTION QTY EFFECTIVEmINACTIVE REFERENCE CAPSM ELEC 1UF 50V 20 5 5MMH 2 00 C171 243 CAPSM ELEC 2 2UF 35V 2096 2 00 C185 241 CAPSM ELEC 22UF 16V 20 3 00 C45 47 49 CAPSM ELEC 47UF 16V 20 3 00 C170 172 181 CAP ELEC 560UF 35V RAD LOW ESR 1 00 06 11 01m C267 CAPSM TANT 10UF 10V 20 3 00 C123 163 256 CAPSM TANT 4 7UF 6 3V 20 7 00 C43 75 90 179 184 C187 189 CAP MYL 22UF 50V RAD 5 BOX 2 00 C252 253 CAP MYL O68UF 63V RAD 5 BOX 3 00 C41 73 88 CAPSM CER 027UF 50V X7R 10 48 00 C92 115 125 148 CAPSM CER 470PF 50V COG 5 2 00 C183 240 CAPSM CER 01UF 50V Z5U 20 9 00 C13 16 17 20 21 C24 27 261 262 CAPSM CER 150PF 50V COG 10 9 00 C3 9 251 254 CAPSM CER 33PF 50V COG 10 11 00 C2 14 15 18 19 22 23 C25 26 191 192 CAPSM CER 01UF 50V COG 5 1 00 C182 CAPSM CER 47UF 50V Z5U 20 3 00 C46 48 50 CAPSM CER 1UF 25V Z5U 2096 152 00 C1 10 12 28 40 42 44 C51 72 74 76 87 89 C91 116 122 124 C149 154 157 162 C164 169 173 178 180 C186 188 190 193 239 C242 244 250 255 C258 260 263 FERRITESM CHIP 600 OHM 0805 15 00 FB1 13 15 16 INDUCTORSM 24UH 20 2 74A 1 00 06 11 01 L1 DIODESM 1N914 SOT23 5 00 D15 16 27 31 42 DIODESM DUAL SERIES GP SOT23 8 00 D1 8 DIODESM SCHOTTKY LOW VF SOT23 5 00 D11 14 26 DIODESM GP 1N4002 MELF 5 00 D9 10 21 28 29 TRANSISTORSM 2N3904 SOT23 2 00 Q2 3 TRANSISTORSM 2N3906 SO
241. 549326 ISC WR TIMEOUT 0x103 549326 ISC TIMEOUT 0x104 549326 INTREQ TIMEOUT 0x105 549326 AUTO BOOT FAILURE 0x106 58420 INIT ERROR 0x200 58420 WR TIMEOUT 0x201 58420 RD TIMEOUT 0x202 58420 WRONG VERSION 0x203 58420 WRONG 1 0x204 SHARC BAD OPCODE 0x300 SHARC TX TIMEOUT 0x301 5 TIMEOUT 0 302 5 GPIO FAILURE 0x302 5 SDRAM FAILURE 0x304 5 SRAM FAILURE 0x305 aYYYYYY Failing address location The address in hexadecimal where the failure occurred wZZZZZZ Value Written The target value in hexadecimal that was written to the address where the failure occurred Value Read The actual value in hexadecimal that was read from the address where the failure occurred The error log is available as a menu item in the extended diagnostics under Repair Tests In addition the error log can be viewed on an external PC or terminal via the D9 connector labeled RS232 2 on the rear panel of the MC 12 MC 12 Balanced The error log is sent to RS232 2 when the VIEW ERRORLOG selection is made 5 6 Lexicon DIAGNOSTICS CONTROL INTERFACE Various combinations of button pushes are used to control diagnostic activity During power on diagnostics the following options are available Entering Diagnostics RECORD LD amp ZONE 2 LD Pressing and holding the RECORD LD and ZONE 2 LD front panel buttons when powering on a MC 12 MC 12 Balanced will put the
242. 550 Lew oar LED SY oras 49 9 SED ocv Dow TED a v avi a v w v 197217 10767 Ser mx ex ua EE 22100 WOG 5 076176 00761781 GAs 55 ed 00 6000 waa 59 00 Se 00 000 5 SNOISTARE 8 37 MC 12 MC 12 Balanced Service Manual Your Notes 8 38 Lexicon 8 39 60 ST 1002 21 2 T 2 EZ Wr 659 66 82 14 659 090 a azis 66 12 41 66 92 14 ammo T NOIIdO NIVH 66 92 1 amat OELTO vo uoorxe 10 7 17 mx 19767 ex To7et7e 5 02 100 00781727 00761761 55 TT 0078717
243. 6 55 5 1 10 3 3 OHM 1 00 R299 202 10949 55 5 1 10 1 2 OHM 3 00 122 123 125 202 11071 RESSM RO 5 1 4W 75 OHM 7 00 R7 12 36 202 11496 55 0 1206 31 00 R48 49 54 55 59 61 77 78 89 98 176 R207 208 212 218 229 R233 237 239 240 R258 262 264 266 202 12365 RESSM RO 5 1 4W 110 OHM 1 00 R27 202 14792 RESSM RO 5 1 10W 56 OHM 110 00 R13 14 30 50 51 57 R58 60 62 64 66 75 R79 85 88 94 97 R101 107 110 116 R153 156 158 174 R177 194 R196 206 209 211 R213 217 219 228 230 231 275 277 203 10424 RESSM RO 1 1 10W 4 99K OHM 2 00 R126 127 203 10896 RESSM RO 1 1 10W 1 00K OHM 4 00 R37 42 47 250 203 11733 RESSM RO 1 1 10W 3 57K OHM 3 00 R34 40 45 203 11741 RESSM RO 1 1 10W 18 2K OHM 1 00 R120 203 12167 RESSM RO 1 1 10W 374 OHM 1 00 R53 203 12363 RESSM RO 1 1 10W 90 9 OHM 1 00 R52 203 12722 RESSM THIN 1 1 10W 49 9K OHM 1 00 R124 203 13131 RESSM RO 1 1 10W 8 45K OHM 3 00 R35 41 46 240 09786 CAP ELEC 100UF 25V RAD LOW ESR 2 00 C257 264 7 1 MC 12 MC 12 Balanced Service Manual PART NO 240 10758 240 12330 240 13216 240 13217 240 13803 241 09798 241 11799 244 10423 244 11589 245 09105 245 09291 245 09876 245 10562 245 10588 245 11595 245 11645 245 12485 270 11545 270 13802 300 10509 300 10563 300 10564 300 11599 310 10510 310 10565 310 10566 330 09241 330 09889 330 10523 330 12452 330 13865 330 13866 330 13868 330 13876 330 13882 330 14247 330 14
244. 628 dVOON3 WWOS 5960 0514 zix9 ova in 8 177 Lexicon Inc 3 Oak Park Bedford MA 01730 1441 Tel 781 280 0300 Customer Service Fax 781 280 0499 Email Lexicon Part No 070 14828 Rev 0 Printed in U S A
245. 7 OWNY 5 NIVO 100 140 588 INE NIA BN Ed epu 100 140 034 DIG OL INT SINY 5 acsor sae weu I unen ENUNAG 140 O36 OI OL oes tei we x 120 358 OIG OI WI NVA ON Tomy oes even cesrese Ssse iun Gex9ise suman ino 140 558 BI OL EN NW E T mun 7 106 14953888 oct ee qn 2020 1276 3 22202000 93H OI WW RV DTW sug n 00096 mue 84 05 0 gt 07081 y EIE EE ONHNAG 2196 LNO 140 O3H DIG OL ZN sumooy XIVIXOB6 11071407034 SIG OL NIV ONY 5 we o scm 02 09 36 11 02 88800 844007 96 110 140 OL ZN NIVA 2H boag
246. 702 14094 702 14097 702 14454 702 14495 720 13632 720 14749 740 09538 740 14888 MC 12 MC 12 Balanced POWER SUPPLY ASSEMBLY DESCRIPTION QTY EFFECTIVEmINACTIVE PART NO 454 13850 490 11462 530 02488 640 10467 640 12534 640 13622 643 10492 644 01740 644 10494 680 11461 680 14536 680 14537 680 14538 700 14086 720 14852 740 08556 740 14798 750 14532 DESCRIPTION QTY EFFECTIVEaINACTIVE REFERENCE 5 8 2 6 00 R PANEL TO CHASSIS SCRW TAP 44X3 8 PNH PH BZ TRI 5 00 OPTO CONN TO R PNL 1 RCA CONN TO R PNL 4 SCRW TAP M2 5X8MM PNH PH BZ TR 2 00 XLR CONN TO R PNL SCRW TAP 4X3 8 FH PH ZN TRI 28 00 XLR BD TO 1U CHASSIS NUT M3X 5MM KEP ZN 2 00 ANLG SHLD TO ANLG BD CABLE 10 SCKTX2 180 2X17C 6 1 00 XLR BD J15 TO ANLG BD J33 CABLE HSG HSG 4C 4 1 00 ANLG BD J25 TO VIDEO BD J22 CHASSIS 3U MC12 1 00 COVER 3U MC12 1 00 CHASSIS 1U MC12B 1 00 SHIELD ANLG BD MC 12 MC 12 Balanced1 00 PANEL REAR MC12 1 00 PANEL OPTION BLANK MC12 1 00 REAR PANEL PANEL FRONT 1U MC12B 1 00 PANEL ACCESS MC12 1 00 CHASSIS BOTTOM PAD FOOT 1 438DIA 4 00 MC12 3U CHAS BTM MC12B 1U CHAS BTM TAPE FOAM SGL STK 1 4THX1 W 3 00 LABEL S N CHASSIS PRINTED 1 00 REAR PANEL LABEL DOLBY THX EX DTS ES WARN 1 00 SW ROCKER 2P1T 5A 80A 250 TV5 1 00 CONN AC 3MC SNAP 04TH IEC 10A 1 00 TIE CABLE NYL 14 X5 5 8 2 00 SCRW M3X6MM FH PH BZ 2 00 SCRW M3X20MM PNH PH BZ 4 00 SCRW 6 32X1 4 HWH SL ZN 2 00 NUT M4X 7MM K
247. 75K OHM RESSM RO 1 1 10W 301 OHM RESSM RO 1 1 10W 1 37K OHM RESSM RO 1 1 10W 2 15K OHM RESSM RO 1 1 10W 30 1K OHM RESSM RO 1 1 10W 29 4K OHM RESSM RO 1 1 10W 976 OHM RESSM RO 1 1 10W 61 9K OHM RESSM RO 1 1 10W 11 8K OHM CAP ELEC 100UF 25V RAD LOW ESR CAPSM ELEC 1UF 50V 20 5 5MMH CAPSM ELEC 47UF 6V NONPOL 20 CAPSM ELEC 10UF 16V 20 CAPSM ELEC 47UF 16V 20 CAPSM CER 470PF 50V COG 5 CAPSM CER 01UF 50V Z5U 20 CAPSM CER 10PF 50V COG 10 CAPSM CER 1000PF 50V COG 5 CAPSM CER 220PF 50V COG 5 CAPSM CER 100PF 50V COG 5 6 CAPSM CER 068UF 50V X7R 2096 CAPSM CER 3300PF 50V X7R 1096 CAPSM CER 47PF 50V COG 5 CAPSM CER 330PF 50V COG 5 CAPSM CER 33PF 50V COG 5 CAPSM CER 15PF 50V COG 10 CAPSM CER 1UF 25V Z5U 2096 CAPSM CER 68PF 50V COG 5 CAPSM CER 6 8PF 50V COG 5 CAPSM CER 12PF 50V COG 5 CAPSM CER 82PF 50V COG 5 180 50 590 FERRITE BEAD INDUCTORSM 10UH 10 DIODESM 1N914 SOT23 DIODESM DUAL SERIES GP SOT23 DIODESM SCHOTTKY LOW VF SOT23 DIODESM GP 1N4002 MELF TRANSISTORSM 2N3904 SOT23 TRANSISTORSM 2N3906 SOT23 TRANSISTORSM 2N4401 SOT23 ICSM DIGITAL 74AC04 SOIC ICSM DIGITAL 74HC02 SOIC ICSM DIGITAL 74HC595 SOIC ICSM LIN LF353 DUAL OPAMP SOIC Lexicon QTY EFFECTIVEmINACTIVE REFERENCE 2 00 10 00 1 00 5 00 2 00 2 00 5 00 1 00 1 00 4 00 1 00 1 00 3 00 1 00 15 00 8 00 3 00 1 00 1 00 1 00 3 00 2 00 2 00 1 00 1 00 3 00 1 00 1 00 1 0
248. 78 GAS wast AST 27 27 90729787 00 2271711 0073777 A i vaste VASI NOG 00 00100 waa aise 2270178 0070177 ax 0078278 00702 7E 00 Lze000 waa SINIOd LSHL SOVITOA SVIS GERD 55 NOLIATHOSEG am SNOTSTARE T 4 v 9 L 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 10 Lexicon 8 11 o 66 12 01 ex H E 5 66 Lz 01 HME 8 629 1 090 270 Lam saco 66 42 70 Sf ammo 3 56705001 me suu O LTO VW Xvo uoo 0005 te 191 2 2000 T srsswo uen 4 SELON
249. 79 v 7 Ast 9777 vir 908 1 m 1 c uy WURDE 9 hs E T Uo M dmi 00 LO OIO 100 1481 Laaosr 191 ord 5 A 8LOEEOW T TAJT ve wisi yoo cuan Gm m 3 SINAINO NIYW VM 44 6 eo ib NOLIATHOSEG nas ae SNOTSTARE S 9 1 MC 12 MC 12 Balanced Service Manual Your Notes 8 126 Lexicon 8 127 T e v S 9 8 2 ce cover oo ez 6 SX canssr 3 00 60 6 wo 25 15 saco 00 8 6 ammo A 51041100
250. 8 ast o as WS i 5 E 25 10 195 5 Y A aste 4 EH is sn 4 E Darm i E Y i n 2 Do s 82 9 NI a AST FS Load AST SUA E 1 L 4 vou zT sorsa senya T seyor oor 984 Aste aste M 1 5 5 GNOOWN ow lt a A nA SUXAP Z SdHP0 A at ze 4 dd va c ev c lt a EI IVH Toye gx av WE waa auram ies oora 1 1072 7 90 7 7 065 El A 25 o oertoo curam 4 in 00 62 6 0078276 Mn asit s avs 3076276 0072276 PEN 944 W 00 t 8000 109195 24005 NIVW Ao Ast SINANI SOTWNY a m EST T e 9 MC 12 MC 12 Balanced Service Manual Your Notes 8 62 Lexicon 8 63
251. 8 38v 01 INIA D AINO 0 05 8 21 69291 0628 0 405 9v6vi oczf g zi oW 29491 05 6 820 0628 998 5014 2 1191 0620 10 02 8 0 2 4 oo iczoi0 09 405 8691 2208 S dOL LY3SNI 92 1 ww ova 00 005010 8 21 6509 2204 5 10 41 8 0 1 8 09 405 00 AMOSS30OV Wuw oo owo una 5 Tu SNOISIA3H 2 Y 4 MC 12 MC 12 Balanced Service Manual Your Notes 8 160 Lexicon 8 161 2 S 9 L 8 30 1 16 i i _ canssi TVOS LON 00 05691 080 D wu 20 NO 3859 SENI 9 581 9 1 ra 7 1 3 21 8 300401 0 405 8 21 9 09 405 70707 vov i bec anodo 5014 v SISSVHO OMG ASSV me 5214 T 16 06691 xou STIL 68 55380 581 2 300801 0002 ovo SENI 01 8 Sold 2 5 30 165 080 30 21 5
252. 8 89 5 Y 9 L 8 s mms 9 99 00 2 8 cass mim sua 0767 P esser oso 00 2 5 ammo 404100 00 2 5 E TIOW QH O I 8 5 82 61 a as AST 4 B ero JA lt lt T xoc vers dum su d af 7 2 100 oza w ERNE om Stt 28 NDZ 4188 80 5 ae 2 Oma os 4198 00 ast T xor 2 yp os anre 4098 00 ere 223 aov d re Y E ut THOT ET wou oot i T ino xov O w AM T Y se aste ___4 8 Te ar oot Ten Aste vase 180 67 IONINOO sa UID XE x E T 1 Da ast 2 T 5 moe 2 sLzao rd uerum 4 oor xor 20999 19780 100 LHOTY w vor w H
253. 80 has written the data to the Host to DSP Command Register DSP_ACKi gt DSP I DSP WAIT SHARC 5 DSP CMD RD AUDIO pos Ry FPGA FPGA CMDREGFULL ogy HOST DSP DATA pgp DATA LDSP COMMAND WR CMD REG 4 COMMAND RD DSP COMMAND WR Host Writes Data to a SHARC DSP schematic pages 2 4 6 11 This is how the host transmits data to the SHARCS during run time The Host writes a byte to the Host to DSP Command Register The write strobe COMMAND also interrupts the SHARC to let it know that a byte is waiting The SHARC then retrieves the byte by asserting DSP HOST CS and DSP_RD This also clears a status bit in the I O FPGA letting the host know that the command register is empty and can be written to again DSP COMMAND WR 7 7 SHARC CS AUDIO DSP TO DSP S FPGA CMDREGFULL OST 08 HOST DSP DSP COMMAND WR DSP DATA DATA CMD REG DSP COMMAND RD COMMAND WR HOST WRITES DATA TO SHARC SHARC DSP writes Data to the Host schematic pages 2 4 6 11 The SHARC write
254. A Here it drives a clock tree that divides down the master clock which is 256 times the sample rate 256FS to create the other clock rates required The Digital Receiver uses a word clock FS and bit clock 64FS The Analog Board receives a 256FS Master Clock and a word clock FS These are used on the analog board to derive the audio clock signals required by the devices on that board 6 17 MC 12 MC 12 Balanced Service Manual 22 5792 MHZ 4488 2 24 576 MHZ 4896 MCK gt ZONE 2 DRCVR DRCVR DAR FPGA ZONE DRCVR SDO ZONE MCKO FROM qu ANALOG ZONE SDO BOARD ZONE DRCVR TO ZONE DRCVR FSI CLOCK amp ZONE DRCVR 5 DIGITAL DATA RCVR ZONE ZONE ANLG FSl ANALOG ZONE ANLG ANALOG CLOCKS E ZONE DAC 501 0 DATA ZONE AUDIO 7 2 7 CLOCKS amp DATA PATH AUDIO FPGA ENCODER Encoder Processing main board schematic sheet 1 The two encoder signals ENCODER A ENCODER B connect to inputs on the mem cpld U79 When either one is asserted low the TRIGGER output is asserted which discharges the CHARGE voltage on C243 through D42 TRIGGER remains asserted until CHARGE is sensed to have reached the low logic threshold of the cpld input This guarantees that even brief signals from the encoder
255. ABLE 100 PLUG SCKT 2X7C 11 5 CABLE 079 SCKT SCKT 4C 4 CMP BRACKET SUPPORT COVER MC12 BRACKET OPT BD MC12 SHIELD 6 7X1 8X 4 H PANEL FRONT MC12 LENS 6 36X1 55 MC 12 1 00 4 00 1 00 2 00 22 00 LX L 23 MC 12 MC 12 Balanced VIDEO MECHANICAL ASSEMBLY PART NO 640 10498 641 13116 643 04942 644 04943 701 14087 DESCRIPTION SCRW M3X6MM PNH PH BZ SCRW TAP AB 4X3 8 FH PH BZ NUT 1 2 28 HEX SMALL BRASS NI WSHR INT STAR 1 2CLX5 8ODX 022 BRACKET VIDEO BD MC12 QTY EFFECTIVEmINACTIVE 6 00 18 00 6 00 6 00 1 00 MC 12 MC 12 Balanced PACKAGING MISCELLANOUS PART NO 070 14710 070 14773 460 08345 730 14767 730 14769 730 14770 730 14771 730 14772 750 14521 DESCRIPTION NOTES ERRATA MC12 B GUIDE USER MC12 B BAT ALK AA 21 3 4 19 12 BOX 22 1 2X19 3 4X13 1 4 BLANK INSERT CORR FOAM ACCESS MC12 B INSERT FOAM BASE 3 amp 4UX15 INSERT FOAM TOP 3 amp 4UX15 REMOTE CONTROL MC12 1 00 1 00 2 00 1 00 1 00 1 00 1 00 2 00 1 00 MC 12 MC 12 Balanced POWER CORD OPTIONS PART NO 680 09149 680 08830 680 10093 680 10096 680 10097 680 10094 680 10095 DESCRIPTION CORD POWER IEC 10A 2M NA SVT CORD POWER IEC 6A 2M EURO CORD POWER IEC 5A 2M UK CORD POWER IEC 6A 2M AUSTRALIA CORD POWER IEC 6A 2M JAPAN CORD POWER IEC 6A 2M ITALY CORD
256. DVD2 and Rec LD 76 SHARC Pair 6 PS2 SRAM Main LD and Z2 LD and Rec DVD1 77 SHARC Pair 7 PS1 SRAM Main LD and Z2 LD and Rec DVD1 and Rec LD 78 SHARC Pair 7 PS2 SRAM Main LD and Z2 LD and Rec DVD1 and Rec DVD2 79 SHARC Pair 4 Boot Main LD and Z2 LD and Rec DVD1 and Rec DVD2 and Rec LD 80 SHARC Pair 5 Boot Main LD and Z2 DVD1 81 SHARC Pair 6 Boot Main LD and Z2 DVD1 and Rec LD 82 SHARC Pair 7 Boot Main LD and Z2 DVD1 and Rec DVD2 83 SRAM Main LD and Z2 DVD2 and Rec DVD2 and Rec LD 84 Burn in Z180 SRAM Main LD and Z2 DVD2 and Rec DVD1 If a failure occurs the MUTE LED is illuminated to indicate the test failure and the LEDs indicating which test was running when the failure occurred will also continue to be illuminated The diagnostics will attempt to continuously execute the failed test a test loop to keep the signal lines active as an aid in debugging the failure Serial Debug Port The Serial Debug Port is available to provide diagnostic status to be viewed on an external PC from the D9 connector labeled RS232 2 Using a terminal or a PC running a terminal program connected to Remote 2 the progress of the diagnostics can be monitored and test failure information is reported Also the error log can be dumped to the serial debug port while in extended diagnostics The serial protocol is 19 200bps 8 N 1 8 data bits no parity and 1 stop bit
257. EP ZN 1 00 WSHR LOCK SPLIT 6 2 00 WSHR FL M4CLX90DX 8MM THK 1 00 WIRE 18G G Y 2 5 187QDC LUG 8 1 00 CABLE PWR 187 110QDC SLV 4 5 1 00 CABLE PWR HSG 110QDC 2C 5 1 00 CABLE HSG HSG 10C SLV 16 13 1 00 SUPPORT PS MC12 1 00 GASKET FAN 1 5D 1 7SQ BLK 1 00 LABEL GROUND SYMBOL 0 5 DIA 1 00 LABEL FUSE CAUTION F 1 4A 250V 1 00 PWR SUP 5V 15V 90W 1 00 MC 12 MC 12 Balanced FAN ASSEMBLY CHASSIS BOTTOM REFERENCE FERRITE SLEEVE TO PS SUPPORT PWR SW TO PS SPT FAN TO PS SPT PS TO PS SPT CHASSIS GND PS TO PS SPT CHASSIS GND AC CONN TO CHAS GND AC CONN TO PWR SW PWR SW TO PWR SUP PWR SUP TO MAIN J31 AND ANLG J26 BDS FAN TO PS SPT PS SUPPORT PS SUPPORT PART NO DESCRIPTION QTY EFFECTIVEmINACTIVE REFERENCE 410 14851 FAN 40X40X10MM 12VDC 3 43CFM 1 00 525 12536 CONN CONT CRIMP 22 26AWG AMP 2 00 527 12537 CONN HSG CRIMP 100X2 POL LK 1 00 MC 12 MC 12 Balanced FRONT PANEL MECHANICAL ASSEMBLY PART NO 430 13143 550 13633 550 13634 550 14090 7 14 DESCRIPTION QTY EFFECTIVEmINACTIVE REFERENCE DISPLAY VF 20X2 CHAR 5X8DOT 1 00 BUTTON 276X 572 BLK 2 00 BUTTON 276X 572 BLK W LTPIPE 41 00 KNOB 2 00X 95H 6MM ALUM PEWTER 1 00 ENCODER PART NO 635 14526 640 01841 640 10495 640 10496 640 10498 680 14693 680 14854 701 13630 701 14496 701 14858 702 14091 703 14098 DESCRIPTION SPCR M3CLX6MM 6MMRD SCRW 2 56X1 4 PNH PH ZN SCRW M3X12MM PNH PH ZN SCRW 4X10MM PNH PH ZN SCRW M3X6MM PNH PH BZ C
258. EX or 5 1 THX and dts ES THX listening modes This parameter only has an effect when the LFE parameter on the CUSTOM SETUP menu is set to ON page 3 23 Pages 5 10 and 5 14 19 The 5 1 MONO 5 1 MONO LOGIC and 5 1 MONO SURR listening modes are designed for playback of Dolby Digital mono sources Mono material can be found on both Dolby Digital 1 0 and 2 0 input types These modes are also available but not recommended for 5 1 Dolby Digital sources The unit will automatically select 5 1 MONO LOGIC when a 1 0 Dolby Digital input type is present Pages 5 12 to 5 13 20 It is possible to scroll through STATUS menu parameters with the MENU arrows for front panel display viewing STATUS menu parameters are not adjustable Page 5 18 21 Toggling the setting of the SURROUND EX parameter produces low level clicks in the front speakers Pressing the THX button on the remote control when the SHIFT command bank is active will still toggle the SURROUND EX parameter setting when the MODES parameter on the LOCK OPTIONS menu is set to LOCKED page 3 36 Pressing the 7 5 button on the remote control will not toggle the SURROUND EX parameter setting when either the REAR L R or SIDE L R parameters are set to NONE The REAR L R and SIDE L R parameters are located on the CUSTOM SETUP and THX SETUP menus pages 3 21 and 3 24 Page 5 24 22 The THD Noise specification for the Main Zone Zone 2 and the Record Zone is Below 008 at 1kHz maximum output lev
259. Ed EJ oe 1 A 27 zt ae Te 02 Sano t 1 II 55 T Ll Anse TI 949 0 ozara a ans secu SIISOdWOD Sr HOLINOW g i 25 47 1 5 Ta am wou eT THON GIA Y 5 TIS GIAR 8 w ye C 1 o T Y 0155 GIAN 27 T ES 07 preter ro eeet00 wow 4 0572701 6078276 pa SINANI ALISOAWOD 0072701 5978 76 oo NOLIATHOSEG SNOTSTARE T 4 v 9 4 8 MC 12 MC 12 Balanced Service Manual Your Notes Lexicon 0 9 e v S 9 L 8 zaoz 8 22 609 00 LT T Ganssi m
260. IG OL X96 NI 130 DIG 140 DIG 01 X96 NI DIG inO 140 O3H 910 OL 896 NI 1140 DIG 1nO 140 O3H DIG OL 396 NI 1140 034 DIG 110 140 23H DIG OL 396 NI 40 910 SUIEN 1521 159 SAP ueAUp Sinduj sere 701087 eie JeuoiMs xp eee puppe epe spem os Em pen R INO NIVA SINY OI 396 122 BNS LNO NIVW OL 396 0 72 LNO NIV DINV A96 8NI S INV 692 LNO NIVW SINY OL NIVA 9 NV 892 Ino NIVW SINY OI 396 BNI NIVW 292 1 NIVW DINY OL 396 NIVW OSTNY 992 NIVW SINY OI 396 8NI NIV Wod Tequn XnWutava LNO NIV OL 96 ZNI NIVW 1 S92 LNO NIVW SINY OL 396 ZNI NIVW SINY 792 MIViX LNO YIG NIVW OL 96 ZNI NIVW 9 INV 692 1nO HIG NIWA OSTNY OL 5I96 ANI NIVIN 292 Tod aun 0384 LNO NIVW ONY OL 396 LNE NIV O NV 192 NIVO LNO NIVW OL M96 ZNI RM lt a wai mmn os an sues ALNO DINV OL 396 ZNI NIV LNO NIYA OTNY Ol 596 NI
261. IPTION QTY EFFECTIVEmINACTIVE REFERENCE 120 09621 ADHESIVE THRD LOCK LOCTITE 242 0 00 DSUB JSCKT 490 13872 CONN PLUG 200 6FC RA 12 30G 1 00 REAR PANEL 527 12974 CONN DSUB JSCKT 4 40 187X 25 4 00 DCONN TO R PANEL 540 02472 PLUG HOLE 3 8 BLK 4 00 541 13631 FOOT 2 0X 5H ALUM BLK 4 00 CHASSIS 630 15011 SPCR 6CLX3 16 1 4RD NYL 2 00 ANLG SHLD TO ANLG BD 635 13637 SPCR M3X34MM M F 6MM HEX 3 00 ANLG BD TO MAIN BD 635 14779 SPCR M3X14MM 6MM HEX 1 00 MEM BD TO CHASSIS 640 02377 SCRW 4 40X1 4 PNH PH BLK 3 00 TO MAIN BD 2 MAIN BD TO R PNL 1 640 10467 SCRW M3X6MM FH PH BZ 3 00 PS SPT TO CHAS 2 MEM BD TO CHAS 1 640 10495 SCRW M3X12MM PNH PH ZN 2 00 ANLG SHLD TO ANLG BD 640 10496 SCRW AX10MM PNH PH ZN 2 00 F PANEL TO CHAS 640 10496 SCRW AX10MM PNH PH ZN 4 00 FEET TO CHAS 640 10496 SCRW 4X10MM PNH PH ZN 7 00 12B FP TO 1U CHAS 3 1U CHAS TO 3U CHAS 4 640 10498 SCRW M3X6MM PNH PH BZ 29 00 PS SPT TO CHAS 3 MAIN BD TO 7 F PANEL TO CHAS 3 OPT PNL TO REAR 2 ANLG BD TO R PNL 5 ANLG ASSY TO MNBD 3 VIDEO BDS TO R PNL 5 MEM BD TO CHAS 1 640 10498 SCRW M3X6MM PNH PH BZ 2 00 XLR BD TO 1U CHASSIS 640 13645 SCRW M4X10MM FH SCKT BZ 12 00 COVER TO CHASSIS 641 01703 SCRW TAP AB 4X1 4 PNH PH ZN 2 00 ACCESS PANEL TO CHAS 7 13 MC 12 MC 12 Balanced Service Manual PART NO 641 10989 641 11466 641 14672 641 14776 643 10491 680 14494 680 14539 700 14084 700 14085 700 14677 701 15010
262. IW NIVA en 18 617 9 55 ONON 55 854 85 um so rr ao 0140 aa EX SEE sordo 1 910140 SEO LACE P 58125 DEN TD acz XLV 04 10 wu senva irmCunoud moz 5 o TEV toret z 24 IR TZEN HADET NIV 38 2 or Exe n gt E Sxvoo 1 9 XVOD BE E en ans 10 9 BE ENO o lt T ST isa anaona m zo Two ee gr ee THEO awit E ru 222 quss ont eure 50 0 d D EE Cu Ri j mor snt 5 oae ENOZ 184 WADWI uNOZ 22156 7464 VAN 58 EUH S vow o LO L1 ig v1 La ct La et La v ea e 1a z 30472185 HW A Lid Am cu MN 8 OXOW EE TOPA OXW LA LT x 60
263. Input Test These tests put the unit into a state to pass audio through the path that is contained in the test name for troubleshooting For instance the Audio Input 1 Test will pass analog audio from analog input 1 to all the outputs Video I O Tests The Video I O tests contain the following tests INIT INT SYNC INIT EXT SYNC Select PAL Select SECAM Load Font Color Bars Show CHARS The video I O tests initialize the video circuitry to put the unit into a known state for troubleshooting The menu items select a few of the basic setups that can be used for troubleshooting These selections will instruct the On Screen Display OSD IC in the unit to output a video signal that can be used to verify the video circuit from the OSD to the monitor outputs of the unit Service Notes This section will address some of the descriptions and issues that involve the unit in order to repair and or replace boards or components in the MC 12 MC 12 Balanced Please refer to the Assembly Drawings found in Chapter 8 and additional drawings figures that have been included in this section Please refer to the Safety Suggestions and Summary Descriptions at the beginning of this manual REMOVING THE TOP COVER 1 Remove the 12 screws that hold the top cover of the unit as shown in Figure 1 below 2 Reverse the above procedure when reinstalling the cover 5 17 MC 12 MC 12 Balanced Service Manual Rear Panel Figure 1 REMOVING THE VIDE
264. L m erat E sun 4 2 18 80 i T E SS on 4 98 40 HI X ot ast PRETO nashe aa 8 40 1 n xor 1 EIN IBN va et 22 anov xmv lt a 00 00 d EI Y oor T EG _ 100 vsu O w sezao nes 1691 Y Aste 8 757627 9 aw 1079277 sere a Ed uoa astama oT eat Toer IOMINOD THANT 00 02 100 xoa waa 8104100 ami 2976276 0078276 0075278 0072275 227 00 2 000 astama 20 asuvaa NOLIATWOSEG m SNOTSTARE T 4 v 9 L 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 90 Lexicon 86821 1002 16 1
265. Lexicon 8 165 2 Y Y 9 8 f roue ANON 1105 LON 00 ag OL Gg 1 Ov OSH OSH NAYO 6 089 05 15 1 905571080 LS 435 assy 508 91 OL 405 L 61 94 AIS 201 9SH 9SH NYO 8 5 1 089 1 09 45 8 71 0 WARN 8 2 E 405 OL MS 20 000 OLL 9SH IAYO 581 089 SISSVHD OMG ASSY MS OL NNOD Ov S Y AIS 900 OLL L8V NEYO 9 6 1 080 Lv 09405 821 08 XX OL 1 1 9 OBL ZXLIOS 0017 318 2 6 71 089 Ov avoy SNNN Q8 OL OIN OldO 338 TAYO 01191 089 y 48 91 OL OIW OldO 4334 71 51 6 5 9 001 NAYO 18071 089 0 405 8691 2208 Q8 OL ABONVIS 438 1105 1305 640 318 2 8 089 Cy 21 4 14091 25008 QNO SISSVHD OL OV 9f 911 500 A D 98 19911 089 Zr 24 24 9 091 220 uv ASSY AlddNS 4 ZZ0vl Zzof 1446 Sd OL 414405 2 90 145 YHSM 09 10 999 Ov NOWNOD ASSY SISSVHO O90v1 ZzOf SISSVHO 1 MHL WS X GO 6
266. M FPGA XCS10 3 14X14 TQFP ICSM ADC AKM5383 24B 96KHZ SOP QTY__EFFECTIVEmINACTIVE REFERENCE 20 00 4 00 29 00 24 00 1 00 16 00 5 00 6 00 2 00 13 00 12 00 3 00 2 00 7 00 1 00 11 00 19 00 9 00 8 00 12 00 6 00 8 00 8 00 1 00 3 00 06 01 01 08 29 01 m 06 01 01 06 01 01 08 29 01 BC92 BC93A B BC93 BC94 BC95A H BC101 102 C102 103 105 108 109 C111 114 115 118 120 C121 124 126 127 130 C132 133 136 138 139 C142 144 145 148 154 C155 160 162 164 165 C170 172 174 175 180 182 222 223 226 227 234 235 238 239 293 294 296 298 300 301 C305 306 308 310 312 C313 317 318 320 322 C324 325 353 354 356 358 365 366 368 370 377 378 380 382 389 390 392 394 401 402 404 406 413 414 416 C418 425 426 428 430 C432 433 440 441 443 C445 452 453 455 457 C464 465 467 469 476 C477 479 481 488 489 C491 493 FB1 20 FB26 29 FB21 25 30 33 36 39 FB42 45 48 51 58 FB61 64 67 70 73 77 FB31 32 34 35 37 38 FB40 41 43 44 46 47 FB49 50 59 60 62 63 FB65 66 68 69 71 72 D26 D1 16 D17 21 D17 21 26 D24 25 Q4 6 8 10 12 14 16 Q18 20 22 24 26 28 Q5 7 9 11 13 15 17 Q19 21 23 25 27 Q1 3 U65 94 U63 75 76 85 86 U92 101 077 028 30 32 37 39 41 010 12 19 20 38 42 048 55 58 62 01 8 21 09 11 13 18 U68 74 87 91 U22 27 U29 31 43 47 93 U29 31 43 47 93 U95 U64 66 67 PART NO 355 13987 355 14761 410 11639 430 10419 430 10421 510 03961 510 13149 510 13877 510 13941 510 14079 510
267. Main Audio Path 2 Channel Input block diagram below The DSP can create as many as 12 different output signals from the 2 channel input Individual stereo D A converter ICs operate in mono mode to convert each of the 12 signals from the DSP to analog The signals pass through level controls and output drivers to their respective RCA connectors A direct analog path is also provided which passes a 2 channel analog input signal directly to the Left and Right Front outputs via the level controls bypassing the DSP and converters Error Not a valid link The MC 12 Balanced version offers additional Balanced Main and Zone 2 analog outputs using XLR connectors In this version an internal 34 pin ribbon cable routes the post level control signals from the Analog Board to the XLR Board The XLR Board incorporates active balanced output drivers for each of the 14 outputs In addition a 5 1 channel source can be selected for the Main audio path There are four possible methods of getting a 5 1 source into the box Please refer to the Main Audio Path 5 1 Channel Input block diagram below 1 S PDIF signal may be encoded in Dolby Digital or DTS format and passed through a decoder that outputs the 5 1 channels These channels are then passed along to the DSP 2 Three separate analog input pairs can be routed directly to the outputs bypassing the DSP and converters This mode is available for DVD Audio and multi channel SACD players with 5 1 analog o
268. NIVA OSTNY CHL INO NIVW SINY OL 396 INI NIVA DAYS LNO NIVW SINY OL X96 LNI NIVA NIVO LNO NIVW OTNV OL 596 INI NIVW 1 SINY OL 396 INI NIVW ILAW LNO NIVW Ol 3 96 INI NIVW 9 INV YSZ 13431110 INO NIVW OI 396 INi NIVW O INV 682 xii inse ep sine 7271 771 suuni teasee c ccu 121 1 01120110 BNS LNO NIVW O1NY OL 395 NIVIN O1NV 262 LNO O INV OL 5 96 NIVW OTNY 162 LNO OL 598 LNI NIVW 092 ALAW T3A311nO LNO 3NOZ OL 6 INI 3NOZ Pre Oss INO NIVW SINY 01 3195 INI NIVW DINV LNO NIV SINY 366 INI NIV INO OL 96 INI NIVW ONY AVISU 1o SNOZ Ol 3196 INI INOZ ONV 292 INO XH HNOZ SINY OL X96 INI 3NOZ BINA 1nO HWA 3NOZ OL 3596 INI 3NOZ O INV 992 XnBlava 1no INOZ NV OL 396 INL INOZ NV GYZ HNS LNO 3NOZ OTNY OL 396 INI 3NOZ Ere 1 INOZ OL 5196 INOZ LNO
269. NIVW Ol 2 00 00088 reuex3 lt 20007 00 2002 eu 1088 5460074 54880011 OHL 100 OL NI 2 00 NIV 00088 reweng lt 0 gt 200 azeor Zu ee d sum wu eu em f 76 58 000 y ANO x EEUU TERNOS 100 Ol NI zXVOO 0006 wuexi aizo wu wu wu 76 480009 64800001 SNHNAG LNO OL 5I96 1XVOO 5006 2 02 euw 0008 000 wu wu 100 OL 5 98 NI 1XVOO NIVW 910 681 00098 2009012 2000 0600000 820 600 2005 sof 2 848800 548 011 LNO OL 396 NI IXVOO NIVIN 910 0006 85 015 euw 520 520 oror ww 580001 848 011 LNO NIV OL 296 NI IXVOO 90 96 20009 lt 01 gt vw 288 Sa8pooo S3ePooo 110 NIVW 9 NV OL 96 NI IXVOO NIVW 910
270. NIVW OTNV OI XP NI 1145 NIV OIG 661 001 xoose orf aramon eee sua we ew _______ 266 94900004 39 000 NIVE 1nO OLI Ni Li30 BiG 861 XANTIGW NIVW SINY OI 9XYOO NIV SIG 161 XAWHIGVY LNO NIVW SINY Ol NISXYOO NIVW Dia moz b 1521 ajdwes Bojsuy 4 21 MC 12 MC 12 Balanced Service Manual sse eu Jee ese Ee zem ES wv 00666 sse em ww 300 ssa sarr e 2 Samos 7 2 EIE 330 Lew Due 580722 sip wir pun 00096 00096 6660 wu wm esi ues uer ua wg ya uei sinseay wog 396 110 140 OIG OL 1150 O3H BIG NIVO 596 110 140 93H Old OL NI 1150 238 DIG 296 110 140 23H DIG OL Wer 1140 288 GHL LNO 140 96 1140 23H DIG NIVO LNO 140 D
271. Nd NWO ptent SET 100624 7 xcvi SOLID 1 8 14584 12 80 LEC GNO TAR GRO OE GN en NNOO 5 TANYA dO 1591 TWKNHINI SYH O I ZLS6OX BION 6268 5 WaNOd Y 30 0E 11 3 585 orav om 2 4051 4 e tt 3o er cast 1585 GEI SWsAIOSW t tt 40 LT Bui WADE OIGDW DIG NI 8553 ipio ons 15 sacos 449 12 H E bor n 25 En 50 12 uus T m 99 16 19 1 HOIDENNOO 0 NOILAO 40 Foer T 8 ass 4 XOISENNCO Y OTIS REGNIS 150 t tt 40 tr T seems 55 E eee go 1 ao eum TN 254 oru 2400 21 Q9 WW ot px RII 15 SId toV dO S I so 91 10 v sv c so 7 iss
272. O AND ANALOG BOARDS 1 First rotate the MC 12 MC 12 Balanced so the rear panel is facing you 2 Disconnect the following cables using Figure 2 as a guide 2 A The ribbon cable connecting the Main Board to the Video Board Disconnect the cable from its location J26 on the Main Board by gently rocking the cable from side to side and pulling it away from the board 2 B The ribbon cable connecting the opto mic board to the analog board Disconnect the cable from its location J30 on the analog board The opto mic board is located between the Main Board and the analog board directly behind the Microphone Inputs on the rear of the panel 2 C The ribbon cable connecting the analog board to the Main Board Disconnect the cable from its location J29 on the Main Board by releasing the locking tabs on the sides of the connector then pulling the cable away from the board 2 D The power supply cable from its location J26 on the analog board The power supply cable may require more force to remove than the other cables 2 E The power cable connecting the analog board to the Video Board Disconnect the cable from its location J25 on the analog board 5 18 Lexicon 3 Screws Figure 2 Refer to 080 14530 ASSY DWG CHASSIS in chapter 8 and remove the five rear panel screws that are connected to the Video Board Carefully pull the board inward then up and out of the MC 12 MC 12 Balanced Store it in a stati
273. OHM 3 00 R60 68 70 202 10944 RESSM RO 5 1 10W 33K OHM 5 00 R95 212 215 202 10945 RESSM RO 5 1 10W 1 5K OHM 1 00 R62 202 10947 RESSM RO 5 1 10W 680K OHM 1 00 R59 202 10948 RESSM RO 5 1 10W 390 OHM 1 00 R63 202 11042 RESSM RO 5 1 10W 6 8K OHM 4 00 R160 161 163 166 202 12369 RESSM RO 5 1 10W 36K OHM 4 00 R124 129 149 156 202 13579 RESSM RO 5 1 10W 22 OHM 17 00 R6 9 13 16 20 23 27 R30 34 37 41 44 48 R51 55 58 78 203 10560 RESSM RO 1 1 10W 75 0 OHM 32 00 R3 4 10 11 17 18 24 R25 31 32 38 39 45 R46 52 53 79 101 R105 115 117 121 148 R159 162 164 165 172 R174 191 197 205 203 10583 RESSM RO 1 1 10W 10 0K OHM 4 00 R132 135 136 139 203 10837 RESSM RO 1 1 10W 475 OHM 7 00 R71 116 119 144 155 R169 192 203 10840 RESSM RO 1 1 10W 750 OHM 16 00 R102 103 123 125 128 R130 150 153 154 157 PART NO 203 10895 203 11080 203 11082 203 11723 203 11726 203 11730 203 12198 203 12298 203 12838 203 12897 203 14789 203 14790 240 09786 240 10758 240 11111 240 11827 240 13217 245 09291 245 09876 245 09895 245 10416 245 10544 245 10561 245 10972 245 10975 245 10976 245 10977 245 11625 245 12070 245 12485 245 12524 245 14762 245 14763 245 14764 245 14765 270 00779 270 11289 300 10509 300 10563 300 10564 300 11599 310 10510 310 10565 310 10566 330 09797 330 10505 330 10506 340 10502 DESCRIPTION RESSM RO 1 1 10W 681 OHM RESSM RO 1 1 10W 1 15K OHM RESSM RO 1 1 10W 15 0K OHM RESSM RO 1 1 10W 4
274. On Screen Display Consists of the chip select serial clock and data The FPGA converts the host parallel data to a serial data stream Host Serial Control Interface to the Record Digital Transmitter Consists of the chip select serial clock and data The FPGA converts the host parallel data to a serial data stream It also converts the serial output of the Crystal chip to parallel for the host to read The 1MHz clock signal used by the 16C54 PIC IR Receiver MC 12 MC 12 Balanced Service Manual HOST INTERFACE amp NRZ AUDIO DATA S PDIF RECORD INPUTS DRCVR AUDIO DATA ZONE XTAL OSC DRCVR AUDIO CONTROL MASTER amp NRZ CLOCKS AUDIO DATA MAIN MASTER CLOCK I O RECORD MASTER CLOCK I O ZONE MASTER CLOCK PLL amp CONTROL CRYSTAL DECODER CS49326 SERIAL CONTROL INTERFACE VIDEO BOARD 8 OSD SERIAL CONTROL INTERFACE RECORD DIGITAL XMTR SERIAL CONTROL INTERFACE SPARES DAR FPGA BLOCK HOST INTERFACE TO OTHER BOARDS Switch LED IR Encoder and VFD schematic page 21 The interface to the all of the front panel boards with the exception of the standby board is a single ribbon connector All signals are connected to the Switch LED Board It then passes signals as required to the IR Encoder Board and the VF Display The Signals used by the Switch LED Board are as follows e FP
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276. Park Bedford MA 01730 1441 Telephone 781 280 0300 Fax 781 280 0499 email ATTN Customer Service Returning Units to Lexicon for Service Before returning a unit for warranty or non warranty service consult with Lexicon Customer Service to determine the extent of the problem and to obtain Return Authorization No equipment will be accepted without Return Authorization from Lexicon If Lexicon recommends that an MC 12 MC 12 Balanced should be returned for repair and you choose to return the unit to Lexicon for service Lexicon assumes no responsibility for the unit in shipment from the customer to the factory whether the unit is in or out of warranty All shipments must be well packed using the original packing materials if possible properly insured and consigned prepaid to a reliable shipping agent When returning a unit for service please include the following information Your Name Company Name Street Address City State Zip Code Country Telephone number including area code and country code where applicable Serial Number of the unit Description of the problem Preferred method of return shipment Return Authorization on both the inside and outside of the package Please enclose a brief note describing any conversations with Lexicon personnel indicate the name of the person at Lexicon and give the name and daytime telephone number of the person directly responsible for maintaining the unit Do not include a
277. R1 245 12485 CAPSM CER 1UF 25V Z5U 20 3 00 C5 C1 2 IF U1 C3 4 IF U2 POP 350 14466 ICSM FLASH 16M MC12 V1 01 1 00 U1 TSOP PKG OR PART NO DESCRIPTION QTY _EFFECTIVEmINACTIVE REFERENCE U2 SOIC PKG 350 14786 27 020 12 1 00 1 00 U3 500 13644 CONN EURO C 48P ABC PLUG RA 1 00 J1 520 04999 IC SCKT 32 PIN MACH TIN 1 00 U3 MC 12 MC 12 Balanced VCO ASSEMBLY PART NO DESCRIPTION EFFECTIVEmINACTIVE REFERENCE 202 09899 RESSM RO 5 1 10W 47 OHM 1 00 R1 245 09895 CAPSM CER 10PF 50V COG 1096 1 00 C3 245 12485 CAPSM CER 1UF 25V Z5U 20 4 00 C1 2 4 5 270 11545 FERRITESM CHIP 600 0805 1 00 1 270 14359 COILSM VAR 1UH 596 5 6X6 2X6MM 1 00 L1 300 13881 DIODESM VARACTOR BB132 1 00 D1 340 14528 ICSM LIN MC100EL1648 VCO SOIC 1 00 U1 510 14836 CONN POST 100X025 HDR 5MC RA 1 00 J1 700 14838 HOUSING VCO MC12 1 00 700 14839 COVER VCO MC12 1 00 MC12 Balanced ONLY MC 12B XLR BOARD PART NO DESCRIPTION QTY REFERENCE 202 10943 RESSM RO 5 1 10W 22K OHM 28 00 R3 30 202 10948 RESSM RO 5 1 10W 390 OHM 2 00 R1 2 203 12720 RESSM THIN 1 1 10W 2 94K OHM 14 00 R33 38 41 46 49 54 R57 62 65 70 73 78 R81 86 203 13132 RESSM THIN 1 1 10W 3 01K OHM 14 00 R31 36 39 44 47 52 R55 60 63 68 71 76 R79 84 203 14874 RESSM THIN 195 1 10 6 04 OHM 4 00 R32 34 35 37 203 14891 RESSM THIN 196 1 10W 9 09K OHM 24 00 R40 42 43 45 48 50 R51 53 56 58 59 6
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279. S2 GPIO Z2 DVD1 and Z2 DVD2 and Rec DVD1 and Rec DVD2 55 SHARC Pair 2 PS1 SDRAM Z2 DVD1 and Z2 DVD2 and Rec DVD1 and Rec DVD1 and Rec LD 56 SHARC Pair 2 PS2 SDRAM Z2 DVD1 and Z2 DVD2 and Z2 LD 57 SHARC Pair 3 PS1 SDRAM Z2 DVD1 and Z2 DVD2 and Z2 LD and Rec LD 58 SHARC Pair 3 PS2 SDRAM Z2 DVD1 and Z2 DVD2 and Z2 LD and DVD2 59 SHARC Pair 4 PS1 SDRAM Z2 DVD1 and Z2 DVD2 and Z2 LD and Rec DVD2 and Rec LD 60 SHARC Pair 4 PS2 SDRAM Z2 DVD1 and Z2 DVD2 and Z2 LD and Rec DVD1 Lexicon 61 SHARC Pair 5 PS1 SDRAM Z2 DVD1 and Z2 DVD1 and Z2 LD and Rec DVD1 and Rec LD 62 SHARC Pair 5 PS2 SDRAM Z2 DVD1 and Z2 DVD2 and Z2 LD and Rec DVD1 and Rec DVD2 63 SHARC Pair 6 PS1 SDRAM Z2 DVD1 and Z2 DVD2 and Z2 LD and Rec DVD1 and Rec DVD2 and Rec LD 64 SHARC Pair 6 52 SDRAM Main LD 65 SHARC Pair 7 PS1 SDRAM Main LD and Rec LD 66 SHARC Pair 7 PS2 SDRAM Main LD and Rec DVD2 67 SHARC Pair 2 PS1 SRAM Main LD and Rec DVD2 and Rec LD 68 SHARC Pair 2 PS2 SRAM Main LD and Rec DVD1 69 SHARC Pair 3 PS1 SRAM Main LD and Rec DVD1 and Rec LD 70 SHARC Pair 3 PS2 SRAM Main LD and Rec DVD1 and Rec DVD2 71 SHARC Pair 4 PS1 SRAM Main LD and Rec DVD1 and Rec DVD2 and Rec LD 72 SHARC Pair 4 PS2 SRAM Main LD and Z2 LD 73 SHARC Pair 5 PS1 SRAM Main LD and Z2 LD and Rec LD 74 SHARC Pair 5 PS2 SRAM Main LD and Z2 LD and Rec DVD2 75 SHARC Pair 6 PS1 SRAM Main LD and Z2 LD and Rec
280. SM ELEC 22UF 16V 20 1 00 245 10562 CAPSM CER 150PF 50V COG 10 8 00 245 10976 CAPSM CER 47PF 50V COG 5 12 00 245 12485 CAPSM CER 1UF 25V Z5U 20 13 00 270 11545 FERRITESM CHIP 600 OHM 0805 8 00 300 11599 DIODESM GP 1N4002 MELF 2 00 340 10552 ICSM LIN MC33078 DU OPAMP SOIC 4 00 340 11559 ICSM LIN LM317M ADJ REG DPAK 1 00 510 10595 PHONE JACK 3 5MM PCRA 3C STER 4 00 510 13840 CONN OPTO PCRA TORX173 6MBPS 3 00 680 14081 CABLE 100 PLUG SCKT 2X5C 12 L 1 00 680 14170 CABLE RIB 24 26AWG 6CX 1 3 L 1 00 MC 12 MC 12 Balanced VIDEO BOARD QTY __EFFECTIVEmINACTIVE REFERENCE R34 37 R46 R9 19 29 41 R10 20 30 43 C3 10 12 20 22 C30 32 40 42 C46 C13 14 23 24 33 C34 43 44 C5 6 9 15 16 19 25 C26 29 35 36 39 C1 2 4 7 8 17 18 C27 28 37 38 45 47 FB1 8 01 2 U1 4 U5 J2 5 CP1 2 3A OPTO J6 TO ANLG BD OPTO J1 TO MAIN BD PART NO DESCRIPTION QTY EFFECTIVEmINACTIVE REFERENCE 202 09871 RESSM RO 5 1 10W 1K OHM 23 00 R7 8 14 15 21 22 28 R29 35 36 42 43 49 R50 56 57 69 73 75 77 92 143 202 09873 55 5 1 10 10 OHM 10 00 1 2 61 64 67 72 93 94 176 179 202 09874 RESSM RO 5 1 10W 2 2M OHM 1 00 R142 202 10426 RESSM RO 5 1 10W 15K OHM 15 00 R80 82 84 96 98 114 R118 120 147 173 175 R198 206 202 10571 RESSM RO 5 1 10W 100K OHM 17 00 R5 12 19 26 33 40 47 R54 66 126 127 131 R146 151 152 158 187 202 10573 RESSM RO 5 1 10W 470K OHM 16 00 76 85 91 99 122 145 R207 211 202 10943 55 5 1 10 22
281. T23 3 00 Q1 4 6 TRANSISTORSM 2N4401 SOT23 1 00 Q5 ICSM DIGITAL 74HCT574 SOIC 2 00 U42 48 ICSM DIGITAL 74ACT04 SOIC 1 00 U33 ICSM DIGITAL 74HCU04 SOIC 5 00 U2 4 44 52 ICSM DIGITAL 74VHCT244 SOIC 9 00 U55 62 64 68 70 72 U86 ICSM DIGITAL 74VHC04 SOIC 2 00 U26 49 ICSM DIGITAL 74VHC244 SOIC 1 00 051 ICSM DIGITAL 74VHC574 SOIC 4 00 U41 47 56 57 ICSM DIGITAL 74VHC273 SOIC 4 00 U40 46 53 83 ICSM DIGITAL 74LCX14 SOIC 1 00 038 ICSM DIGITAL 74VHCT245 SOIC 7 00 U59 61 69 73 75 ICSM DIGITAL 74VHCT541 SOIC 5 00 U9 21 28 54 84 ICSM LINEAR 78LS05 5V REG SOIC 1 00 ICSM LIN MC34164 5V MON SOIC 1 00 ICSM LIN TLO72 DUAL OPAMP SOIC 1 00 IC LINEAR LM2941CT ADJ TO 220 3 00 ICSM LIN LM2937 2 5V REG TO263 1 00 IC LIN 1585A 3 3V REG TO220 1 00 ICSM INTER 75ALS180 DR RC SOIC 1 00 ICSM INTER CS8414 RCVR SOIC 3 00 ICSM INTER CS8420 ASRC SOIC 1 00 ICSM INTER RS232 XCVR 5V SOIC 1 00 ICSM SRAM 128KX8 12NS 3 3V SOJ 8 00 ICSM CPLD MC12 MEM V1 00 1 00 ICSM FPGA XCSO5XL 4 10X10 VQFP 2 00 U32 U77 U45 U10 12 U43 U82 05 08 20 27 017 01 U13 16 22 25 079 019 67 PART NO 350 13863 350 13879 350 14540 350 14784 365 13860 365 13861 365 13862 365 14683 390 13864 390 13885 390 13886 390 14543 390 14544 430 10419 430 10420 430 10421 460 04598 470 12913 490 02356 500 03620 500 13643 510 02899 510 03550 510 03922 510 03989 510 10546 510 10595 510 10745 510 12999 510 13145 510 13148 510 13538 510 13840 510 13873 510 13887 5
282. TA N FRONT ADDR ADDR 0 1 HOST ADDRESS BUFFER PANEL ADDR 0 1 BUT MUX DISPLAY SWITCH READ LED WRITE RESET LED REG LED S IR AUX DATA ____8 AUX gt IR IR ACK LED IR ACK LED RECEIVER 4 IR DATA IR DATA ENCODER 0 1 225 ENCODER 0 1 ENCODER FRONT PANEL SWITCH LED BOARD CONNECTOR Se FRONT PANEL IR ENCODER I R ENCODER amp OSD BOARD Lexicon 6 7 MC 12 MC 12 Balanced Service Manual VIDEO BOARD amp OSD schematic page 21 The control interface to the Video Board consists of e Serial control data e serial control bit clock OSD chip select enables the serial control port of the On Screen Display chip Video Register select enables the serial to parallel registers that generate the control bits used on the Video Board e video reset line ENABLE VFD ENABLE FRONT IO DATA BUFFER DATA t DATA VFD DATA V FRONT N ADDR I ADDR 0 1 HOST ADDRESS BUFFER PANEL ADDR J 0 1 BUT L N mux TON DISPLAY SWITCH READ LED WRITE RESET LED s E LED S
283. TAL 74HC574 SOIC 7 00 U1 7 ICSM DIGITAL 74HC541 SOIC 1 00 U8 ICSM DIGITAL 74VHCT138 SOIC 1 00 09 LEDSM BLU 30MCB AX ZBEND 2 5MM 12 00 D25 36 LEDSM RED 60MCD AX ZBEND 2 5MM 15 00 D1 12 39 41 LEDSM SYEL 250MCD AX ZBEND 2 5 13 00 D13 24 42 SWSM PBM 1P1T 6 2MMSQ 200GF 42 00 SW1 42 CONN POST 100 HDR 2X7MCG LP 2 00 J1 2 CABLE 100 PLUG SCKT 2X13C 2 L 1 00 SW LED TO MAIN BD MC 12 MC 12 Balanced IR ENCODER BOARD PART NO DESCRIPTION QTY EFFECTIVEmINACTIVE REFERENCE 202 00528 RES CF 5 1 4W 820 OHM 1 00 R1 202 00530 RES CF 5 1 4W 1 2K OHM 1 00 R2 202 00531 RES CF 5 1 4W 1 5K OHM 1 00 R3 245 03609 CAP CER 1UF 50V Z5U AX 80 20 2 00 C1 2 345 14780 IC INTER GP1U28 38KHZ IR DET 1 00 U1B 430 10594 LED T1 3 4 IR 1 00 D1 430 14487 LED T1 BLU 430NM 1 00 SYSTEM ON D4 430 14787 LED T1 RED 700NM 1 00 OVERLOAD D2 430 14788 LED T1 YEL 585NM 1 00 IR ACK D3 452 13640 SW RTY ENC 24POS INC B 25L 1 00 SW1 630 14778 SPCR LED T1 375 H 3 00 D2 4 680 14082 CABLE 100 PLUG SCKT 2X7C 3 L 1 00 IR ENC BD 41 TO SW LED BD 7 11 MC 12 MC 12 Balanced Service Manual MC 12 MC 12 Balanced STANDBY BOARD PART NO DESCRIPTION QTY _EFFECTIVEmINACTIVE REFERENCE 430 13888 LEDSM RED 60MCD AX ZBEND 2 5MM 1 00 D1 453 13899 SWSM PBM 1P1T 6 2MMSQ 200GF 1 00 SW1 510 10546 CONN POST 079 HDR 4MC 1 00 J1 MC 12 MC 12 Balanced MEMORY BOARD PART NO DESCRIPTION QTY EFFECTIVEmlNACTIVE REFERENCE 202 09873 RESSM RO 5 1 10W 10K OHM 1 00
284. TY EFFECTIVEmINACTIVE REFERENCE 1 00 2 00 1 00 1 00 4 00 1 00 1 00 1 00 1 00 1 00 1 00 1 00 1 00 6 00 6 00 11 00 1 00 1 00 6 00 3 00 1 00 6 00 2 00 1 00 1 00 1 00 1 00 1 00 1 00 1 00 3 00 1 00 2 00 1 00 1 00 1 00 1 00 1 00 1 00 1 00 2 00 2 00 1 00 3 00 1 00 MC 12 MC 12 Balanced OPTO MIC BOARD PART NO 202 09795 202 09871 202 09899 202 10598 202 11073 203 11077 203 11980 DESCRIPTION RESSM RO 5 1 10W 2 2K OHM RESSM RO 5 1 10W 1K OHM RESSM RO 5 1 10W 47 OHM RESSM RO 5 1 10W 330 OHM RESSM RO 5 1 4W 270 OHM RESSM RO 1 1 10W 237 OHM RESSM THIN 196 1 10W 10 0K OHM QTY 8 00 1 00 3 00 4 00 4 00 1 00 16 00 EFFECTIVEmINACTIVE U76 U31 36 U66 U58 U29 30 34 35 U80 U50 085 Y1 U81 U39 U6 07 018 20 23 25 43 45 030 33 35 37 39 41 017 19 22 24 32 34 D36 38 40 44 46 BAT1 TX1 W1 6 PINS 182 J23 25 J39 W1 6 J3 4 J36 J32 J33 J1 J30 J29 J26 J6 8 J2 CP3 4 J5 J35 J31 J9 CP1 CP2 U58 OPTO MIC LUG1 DSUB CONN GND U82 REG TO H S LUG1 DSUB CONN GND U10 12 U82 REFERENCE R11 12 21 22 31 32 R38 39 R44 R1 3 R13 23 33 40 R8 18 28 42 R45 4 7 14 17 24 27 7 3 MC 12 MC 12 Balanced Service Manual PART NO DESCRIPTION 203 12481 RESSM RO 1 1 10W 1 5K OHM 1 00 203 12719 RESSM THIN 1 1 10W 2 00K OHM 4 00 203 12723 RESSM THIN 1 1 10W 102 OHM 4 00 240 11827 CAPSM ELEC 10UF 16V 20 13 00 240 13216 CAP
285. Test SWITCH Test LED Test ENCODER Test VIEW ERRORLOG Clear NON VOL SRAM Set Triggers Expand Output MUTE Show Serial NUM PIC SN Validity Flash Burn Test Normal Operation The diagnostic tests that are the same as in the power on tests are not described here RS232 Wrap Test This test verifies the RS232 ports are working by comparing the transmitted signal at pin 2 of J5 to the received signal at pin 3s of J5 If the signals are the same the test passed In order to test this circuit 2 RS232 Wraparound plugs are needed and must be installed at the female D9 connectors J3 amp 4 on the rear panel of the MC 12 MC 12 Balanced labeled RS232 Once these plugs are installed the test can be executed When the test is selected the display will read EXTENDED DIAGNOSTICS RS232 Test All buttons except for the Mode Down will be inactive The ENCODER is active to select another test Pressing the Mode Down button will execute the test and the display will read the following if both ports pass SERIAL PORT A PASSED SERIAL PORT B PASSED If Serial Port A Failed the display will read SERIAL PORT A Failed SERIAL PORT B PASSED If Serial Port B Failed the display will read SERIAL PORT A PASSED SERIAL PORT B Failed 5 12 Lexicon If both Serial Ports Failed the display will read SERIAL PORT A Failed SERIAL PORT B Failed To troubleshoot this type of failure use the front panel Mode Down button Each time
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289. and Right RCA outputs Press play on the DVD player Slowly increase the volume on the amplifier to a comfortable listening level from the speakers Verify that you hear clean clear audio coming from the speakers Pause the DVD and power down the amplifier 10 Move the cables from the Record Fix Left and Right outputs to the Record Var Left and Right outputs 11 Power on the amplifier and press play on the DVD player and repeat Steps 6 9 Remaining Digital Inputs to Record Output Test This test will verify the path of all of the remaining Digital Coax and Optical Digital inputs to the Record Fix Front Left and Right analog outputs in the test to follow 1 2 Connect the digital output source DVD player to the 2 Coax Digital input on the rear panel of the MC 12 MC 12 Balanced Connect the RCA Left and Right Record Fix outputs of the MC 12 MC 12 Balanced to the amplifier Left and Right inputs and the outputs of the amplifier to a pair of speakers If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter In the Diagnostic Menu select Audio I O Tests 4 7 MC 12 MC 12 Balanced Service Manual 5 Highlight S PDIF Input CX2 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see digital audio from the S PDIF 2 digital input to the Record Fix Left and Right RCA outputs Press play on the DVD player
290. and Z2 LD and Rec DVD1 and Rec LD 30 RS232 Wrap Test Z2 DVD2 and Z2 LD and Rec DVD1 and Rec DVD2 31 ID Remote Test Z2 DVD2 and Z2 LD and Rec DVD1 and Rec DVD2 and Rec LD 32 VFD Char Test Z2 DVD1 33 VFD Block Test Z2 DVD1 and Rec LD 34 OSD Char Test Z2 DVD1and Rec DVD2 35 Switch Test Z2 DVD1 and Rec DVD2 and Rec LD 36 LED Test Z2 DVD1 and Rec DVD1 37 View ERRORLOG Z2 DVD1 and Rec DVD1 and Rec LD 38 Clear NON VOL SRAM Z2 DVD1 and Rec DVD1 and Rec DVD2 39 Normal Operation Z2 DVD1 and Rec DVD1 and Rec DVD2 and Rec LD 40 Manufacturing Tests Start 22 DVD1 and 2210 41 Pre Burn Tests Start Z2 DVD1 and Z2 LD and Rec LD 42 Burn In Tests Start Z2 DVD1 and Z2 LD and Rec DVD2 43 SHARC Pair 2 1 Z2 DVD1 and Z2 LD and Rec DVD2 and Rec LD 44 SHARC Pair 2 PS2 GPIO Z2 DVD1 and Z2 LD and Rec DVD1 45 SHARC Pair 3 PS1 GPIO Z2 DVD1 and Z2 LD and Rec DVD1 and Rec LD 46 SHARC Pair 3 PS2 GPIO Z2 DVD1 and Z2 LD and Rec DVD1 and Rec DVD2 47 SHARC Pair 4 PS1 Z2 DVD1 and Z2 LD and Rec DVD1 and Rec DVD2 and Rec LD 48 SHARC Pair 4 PS2 GPIO Z2 DVD1 and Z2 DVD2 49 SHARC Pair 5 PS1 GPIO Z2 DVD1 and Z2 DVD2 and Rec LD 50 SHARC Pair 5 PS2 GPIO Z2 DVD1 and Z2 DVD2 and Rec DVD2 51 SHARC Pair 6 PS1 GPIO Z2 DVD1 and Z2 DVD2 and Rec DVD2 and Rec LD 52 SHARC Pair 6 PS2GPIO Z2 DVD1 and Z2 DVD2 and Rec DVD1 53 SHARC Pair 7 PS1 GPIO Z2 DVD1 and Z2 DVD2 and Rec DVD1 and Rec LD 54 SHARC Pair 7 P
291. and the monitor will have a distorted fractured looking screen This will happen on the monitor every time Diagnostics are loaded 5 To clear this display press the Down Menu button or turn the Volume knob on the remote until you see VIDEO I O TESTS displayed on their front panel 6 Press the Right Menu Button or the Mode button on the front panel to enter the top of the VIDEO TESTS Menu 7 Press the Down button or Modes Down button on the front panel several times until you see LOAD FONT displayed on the front panel 8 Press Right Menu button or Modes Down button on the front panel to load the Fonts The Monitor will turn to a blue screen and the front panel will read VIDEO I O TESTS completed 9 Press the Left Menu button or the Mode Up button on the front panel to bring a clear legible menu to the monitor screen The monitor will display the VIDEO TESTS menu with LOAD FONT highlighted with a black bar 10 Press the Left Menu button or Mode Up button on the front panel to bring you to the main DIAGS MENU The MC 12 MC 12 Balanced is now set up for monitor display for easier navigation through the Diagnostic menus Note The tests to follow assume you have entered the Diagnostics Menu as described above Each test will not repeat this setup procedure It will make reference to it in order to set the stage for proper testing of the MC 12 MC 12 Balanced AUDIO TESTS Analog Input To ALL Analog Outputs Test
292. andby Button The Front Panel Encoder interface MC 12 MC 12 Balanced Service Manual Host Processor Memory schematic page 2 and Memory Board There are three devices located in the Z180 s memory space the SRAM which is on the Main Board and the FLASH ROM and EPROM which are located on the Memory Board The 32kx8 70ns SRAM is powered by the battery backup BAT VCC so that user and factory default settings are preserved when the unit is powered down The Z180 boots from the 256kx8 70ns EPROM at power up Once the EPROM SRAM and FLASH diagnostics have passed the 2180 sets a bit in the Memory CPLD that allows the 2180 to run out of the FLASH ROM The 2Mx8 FLASH ROM is programmable from the RS 232 serial port Host Processor schematic page 2 and 3 All peripheral devices and boards live in the 2180 address space address decoding is handled by the FPGA Because of the size of the Main Board the 2180 data bus is buffered through two 74VHCT245s creating the IODX and IODY data buses All data and address buses going to other boards are also buffered 2180 ADDRES 2180 DATA 10 PAA 10 X DATA BUFFER 10 10 Y DATA BUFFER AUDIO FPGA 2180 HOST INTERFACE CHIP DAR 2180
293. aps in the converters are important for reducing this high frequency content 6 25 MC 12 MC 12 Balanced Service Manual The DAC s converters are followed by a 3 order low pass filter The filter topology is a compromise between the flat passband Butterworth filter and the Bessel filter with its superb transient response with the 3 dB point at 90 kHz and the passband flat to 20 kHz The filter attenuates the 17Vpp differential signal to 6 8Vpp 2 4Vrms and converts it to single ended for the level controls Note these values assume 0 dBFS digital input signal to the DAC In all of the output channels except for Aux DG411 analog switches are used to select either the DAC output or analog input for the respective output These direct analog signal paths have been designed in to support two modes 1 2 channel analog direct or bypass mode Any analog input can be routed directly to the L R Front outputs 2 5 1 analog direct or bypass mode When this mode is enabled specific analog input signals are routed to specific analog outputs according to the table below Analog Input Analog Output s 6 left channel Left Front 6 right channel Right Front Two different pairs of control bits are used to select the DSP DAC signals or analog input signals for the Main outputs FRONT DACOUT SEL selects the Front DAC outputs for the Left and Right Front outputs when low FRONT DIRECT SEL selects the analog input
294. at forms part of an overall Phase Locked Loop PLL for generating master clocks for digital audio in the MC 12 system The board is housed in a shielded enclosure and mounts to the Main Board through a 5 pin in line header J1 which carries control voltage input oscillator output and 5 volt power and ground The VCO assembly is soldered to the MC 12 Main Board schematic 060 13659 which incorporates the phase detector and error amplifier to form the complete PLL VCO Circuit VCO board schematic sheet 1 U1 oscillates at a frequency determined by L1 and the capacitance of varactor diode 01 11 permeable core inductor having high Q necessary for oscillator purity The tuning slug is factory set for a nominal 1uH inductance and the operating range of the circuit is wide enough that no adjustment is necessary positive voltage on VCO V of about 2VDC produces oscillation at about 17MHz and 13VDC produces about 33MHz A larger positive voltage increases the reverse bias of D1 lowering its capacitance and raising the resonant LC frequency The cathode of D1 is effectively grounded for AC through bypass capacitor C5 Series bead FB1 helps isolate the control point from spurious external influences If VCO V is much below 2V D1 will become forward biased oscillation will stop and there will be no output The oscillator output is about 700mV p p biased at around 3 5VDC coupled through series resistor R1 to help isolate the oscilla
295. at steps 6 8 until all the remaining Digital Inputs have been tested Digital Input to Zone 2 Output Test This test will verify the path of the 1 Coax Digital input to the Zone 2 Fix and Var Left and Right outputs 1 Connect the digital output source DVD player to the 1 Coax digital input on the rear panel of the MC 12 MC 12 Balanced 2 Connect the RCA Left and Right Zone 2 Fix outputs of the MC 12 MC 12 Balanced to the amplifier Left and Right inputs and the outputs of the amplifier to a pair of speakers 3 If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter 4 Inthe Diagnostic Menu select Audio Tests 5 Highlight S PDIF Input CX1 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see digital audio from the S PDIF 1 digital input to the Front Left and Right RCA output and all the remaining RCA and XLR paired Left and Right audio output connections 6 Press play on the DVD player 7 Slowly increase the volume on the amplifier to a comfortable listening level from the speakers 8 Verify that you hear clean clear audio coming from the speakers 9 Pause the DVD and power down the amplifier 10 Move the cables from the Zone 2 Fix Left and Right outputs to the Zone 2 Var Left and Right outputs 11 Power on the amplifier press play on the DVD player and repeat step 7 8 12 Pause the DVD and power
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297. c free area Next remove the five rear panel screws that are connected to the analog board Next remove the three internal screws connecting the analog board to the chassis These screws are black DO NOT REMOVE THE SILVER SCREWS As done with the Video Board carefully pull the analog board inward then up and out of the MC 12 MC 12 Balanced Store it in a static free area REMOVING THE MEMORY BOARD 1 2 3 With the MC 12 MC 12 Balanced front panel facing you locate the memory board mounted to the inside chassis on the Right front side of the MC 12 MC 12 Balanced Remove the screw at the top of the board that holds it to the chassis Carefully pull the board up and out of its connector J39 Store it in a static free area REMOVING THE POWER SUPPLY BOARD 1 2 3 With the MC 12 MC 12 Balanced front panel facing you locate the power supply module mounted to the inside chassis on the left hand side of the MC 12 MC 12 Balanced At the back left corner locate the wires that are attached to the rear power switch and remove them from the switch Hold the supply with one hand and remove the 2 nut screws that hold the supply to the inside chassis Rotate the far end of the supply up out of the chassis and then disconnect the 2 secondary wire connections from the other side of the power supply Store it in a static free area 5 19 MC 12 MC 12 Balanced Service Manual REMOVING THE FRONT PANEL 1 Just behind the front pan
298. ccessories such as manuals audio cables footswitches etc with the unit unless specifically requested to do so by Lexicon Customer Service personnel 2 1 Lexicon Chapter 3 Specifications Audio Inputs and Outputs Audio Inputs 8 stereo pairs RCA or 5 stereo pairs and one 5 1 channel analog input Digital Audio Inputs 6 coaxial 6 optical 5 TosLink 1 optical mini jack 1 AES EBU coaxial and optical inputs conform to IEC 958 S PDIF standards Sample Rates 44 1 48 88 2 96kHz Accepts 16 24 bits PCM audio Dolby Digital dts and dts ES discrete data formats Main Audio Outputs 12 unbalanced RCA and 12 balanced XLR MC 12 Balanced only for Front L R Center LFE Subwoofer L R Side L R Rear L R Auxiliary L R Zone 2 Audio Outputs 2 stereo pairs one fixed and one variable output level 2 balanced XLR for L R variable output MC 12 Balanced only Record Audio Outputs 2 stereo pairs RCA one fixed and one variable output level 1 coaxial RCA and 1 optical TosLink S PDIF output in parallel Performance Main Zone Analog to Digital Conversion 24 bit 96 dual bit AX architecture Digital to Analog Conversion 24 bit 44 1 to 192kHz multi bit AX architecture operating in dual mono mode Frequency Response 10Hz to 20kHz 0 1dB 0 25dB 0 75dB at 40 kHz reference 1kHz THD Noise Below 0 003 at 1kHz maximum output level Dynamic Range 108dB minimum 11188 typical 22kHz band
299. ck 64FS 6 15 MC 12 MC 12 Balanced Service Manual The Analog Board and Option Boards receive a 256FS Master Clock and a word clock FS These used on each individual board to derive the audio clock signals required by that particular board PLL MCKO 22 5792 MHZ 1 4488 MCK PLL 24 576 MHZ 4896 mck gt MAIN DRCVR DRCVR gt DAR FPGA MAIN MCKO DSP FSI 5 DSP SCKI gt DSP_IRQ gt _ main_DRcvR_FSI gt DRCVR MAIN DRCVR SCKl MAIN MAIN ANLG FSI ANALOG MAIN MCKI DAUGHTER BOARDS DBx SCKI 0 1 2 MAIN AUDIO CLOCKS AUDIO FPGA Record Audio Clock and Data Paths schematic pages 4 and 16 19 The Record Audio Data Path is as follows 1 Output of the Record Digital Receiver and the Record ADC to the Audio FPGA 2 A2 channel stream is sent to the Analog board as REC DAC SDI and to the Record Digital Transmitter as DXMTR SDI This stream is either the output of the Record ADC the Record Digital Receiver or a 2 channel down mix of the Main Audio content There are three possible sources of master clock for the Record Audio Path The 22 5792 2 crystal oscillator that provides either a 44 1kHz or
300. coder status data output to the host DECODER SCLK serial data bit clock DECODER serial port chip select DEC ABOOT IRQ Crystal Decoder interrupt to the host The Main zone input analog or digital is always routed through the Crystal decoder The serial audio interface consists of DECODER_SDI 2 channel PCM audio stream from either the Main Digital Receiver or the Main Analog ADC DECODER_SDO 3 0 four 2 channel PCM audio streams going to the Audio FPGA DECODER FSI word clock audio framing signal 1 x sample rate DECODER_SCKI audio bit clock 64 x sample rate 6 10 HOST SERIAL CONTROL CLOCKS V ONTROL DATA e SERIAL AUDIO DATA amp CLOCKS IN p CRYSTAL 49326 EPROM DATA T ADDRESS N N DATA LATCHES ADDRESSES 7 EPROM 4x2 CHANNEL PCM AUDIO DATA OUT CRYSTAL DSP BLOCK Lexicon MC 12 MC 12 Balanced Service Manual SHARC DSPs schematic pages 6 11 The principle DSP in the system consists of two pairs of Analog Devices 21065 SHARC DSP engines Each pair shares four 128kx8 12ns SRAMs one 2 32 SDRAM The SHARCs communicate with this external memory and each other over a 32 bit wide data bus All necessary chip selects are generated by the SHARCs including the clocking required for the Synchronous DRAM The SHARCs master clock is provided by a 30 MHz cr
301. ctly on the boards which attach to the rear panel of the MC 12 Separate cables supply power and control signals to the video assembly Control from the Main Board is implemented via a serial interface COMPOSITE VIDEO INPUTS Video RCA board schematic sheet 1 Specific references are to input 1 other inputs are similar Standard video levels applied to RCA jack J18 develop 1Vp p across 75 ohm termination resistor R17 Emitter follower Q7 is located close to the connector and buffers the input with a gain slightly less than unity Transistor bias is supplied through R16 only when the channel is selected by control lines MVID SEL or RVID SEL which operate CMOS switches U1 and U2 DC power from the 5V rail is applied to the emitter resistor through the on resistance of the Switch which is only a few tens of ohms Buffers without bias are effectively disabled so an on board video transmission path is subject to crosstalk from at most one other simultaneously active hostile composite video input Buffered video is fed to pin 27 of ribbon cable J22 through low value series resistor R15 which reduces high frequency peaking in the transmission path to the Video Board COMPOSITE VIDEO OUTPUTS Video RCA board schematic sheet 1 Composite video outputs originating on the Video Board are fed through individual pins of J22 to the corresponding output RCA jacks The on board traces are controlled impedance and form part of a 75 ohm wideband transmissio
302. d DVD player with RCA Analog Left and Right and Digital Coax and Optical Audio Outputs e 1 MC 12 AC power cord variable AC power supply 2 amp minimum Digital Multimeter DMM 3 5 digit 0 596 or better accuracy 1 1 MC 12 MC 12 Balanced Service Manual 1 Low Distortion Analog oscillator with single ended or balanced output 100 ohms output impedance 00596 THD 1 Analog Distortion Analyzer and Level Meter with single ended or balanced input switchable 30Hz high pass filter or audio bandpass 20 20 2 filter 1 100 MHz Oscilloscope 1 Digital Distortion Analyzer amp Digital Function Generator e g Stanford Research Systems Model DS360 or Audio Precision System 1 with DSP Option System 2 Lexicon Chapter 2 General Information Periodic Maintenance Under normal conditions the MC 12 MC 12 Balanced requires minimal maintenance Use a soft lint free cloth slightly dampened with warm water and mild detergent to clean the exterior surfaces of the connector box Do not use alcohol benzene or acetone based cleaners or any strong commercial cleaners DO NOT use abrasive materials such as steel wool or metal polish If the unit is exposed to a dusty environment a vacuum or ow pressure blower may be used to remove dust from the unit s exterior Ordering Parts When ordering parts identify each part by type price and Lexicon Part Number Replacement parts can be ordered from LEXICON INC 3 Oak
303. d Outputs Video Inputs 5 composite RCA 8 S video and 4 component video 3 RCA 1 BNC Video Outputs 4 composite RCA 2 monitor and 2 record 4 S video 2 monitor and 2 record and 1 component BNC Performance Composite amp S video NTSC M PAL and SECAM compatible Switching Active Output Level 1 0V peak to peak Impedance 750 Input Return Loss gt 40dB Differential Gain 0 596 Differential Phase 0 57 Bandwidth gt 25MHz K Factor 0 396 3 1 MC 12 MC 12 Balanced Service Manual Gain 0 15dB Signal Noise Ratio gt 70dB Frequency Response 10Hz to 10MHz 0 1 0 3dB Performance Component Video Other 3 channel Y Pr Pb format independent Switching Passive Impedance 750 Bandwidth gt 300MHz Insertion Loss Microphone Inputs 4 3 5mm miniature phone jacks Input sensitivity 10mVrms 400mV maximum input level Input Impedance 20 accepts balanced or unbalanced input signals Trigger Outputs 1 power on off trigger 2 programmable triggers 12 VDC 0 5 amps each detachable screw terminals RS 232 Serial Input Output 2 9 pin D sub connectors for system control and software upgrades Power Requirements 90 250 VAC 50 60Hz 90W universal line input detachable power cord Dimensions MC 12 17 3 w x 5 2 h x 14 85 d 440 x 132 x 377mm MC 12 Balanced 17 3 w x 6 63 h x 14 85 d 440 x 169 x 377mm Weight MC 12 36lbs 16 4kg MC 12 Balanced 45lbs 20 5
304. driven by 039 Luma and chroma from the input amplifiers are summed by R199 and R200 scaled by 1 2 The result is amplified by U39 which has a gain of slightly more than two With composite input there is no chroma and the result is simply the composite video With S video input the result is the composite version of the S video the sum of Y C As with the S video monitor 1 path the internal U39 multiplexer selects whether the OSD is in the path or whether the input is fed straight through controlled by MTHRU Output impedance is structured as with the Monitor 1 luma output Monitor 2 composite video CVID MON2 is driven by 938 and is always taken directly from the input amplifiers bypassing the OSD Summing gain and output are as described for Monitor 1 Standard 1Vp p video input levels produce 1Vp p output on the composite and luminance channels when terminated in 75 ohms or 2Vp p open circuit The composite monitor outputs are fed to RCA jacks on the Video RCA Board via ribbon cable J25 RECORD COMPOSITE S VIDEO Video board schematic sheet 3 Record video circuitry is structured similarly to monitor video but without OSD capability Refer to the previous section for additional description Multiplexers U16 U24 and U17 are addressed by the SELn bits to select an independent record source but otherwise operate like their counterparts in the monitor path There is no DC restorer in the record path so back porch DC level
305. e the ZONE 2 AUDIO OUTPUTS and RECORD AUDIO OUTPUTS are approximately 8dB higher than the MAIN AUDIO OUTPUTS labeled FRONT L R This is to accommodate THX level requirements Page 2 5 When the 2 CH parameter on the INPUT SETUP menu is set to USE LAST pressing the 2CH button on the remote control selects the 2 CHANNEL listening mode However pressing the 2CH button again does not select the previous listening mode To deselect the 2 CHANNEL listening mode press another mode family selection button or reselect the input Pages 2 14 and 3 10 Zone 2 and the Record Zone will provide a downmix a 2 channel version of multi channel digital audio only when using the same input that is selected in the Main Zone Page 2 16 Audio will mute for up to 2 seconds when The same input is selected in the Main Zone that is already selected in Zone 2 or the Record Zone Likewise when the input is deselected in the Main Zone The same input is selected in Zone 2 or the Record Zone that is already selected in the Main Zone Likewise when the input is deselected in Zone 2 or the Record Zone Page 2 16 When a connector is selected for both the DIGITAL IN and ANALOG IN parameters all INPUT SELECT parameters will automatically be set to AUTO The DIGITAL IN and ANALOG IN parameters are located on the INPUT SETUP menu The INPUT SELECT parameters are located on the MAIN ADV ZONE 2 ADV and RECORD ADV menus Pages 3 5 3 6 3 13 3 15 and 3 16 The level meters
306. e MC 12 MC 12 Balanced 2 Connect the RCA Left and Right Record Fix outputs of the MC 12 MC 12 Balanced to the amplifier Left and Right inputs and the outputs of the amplifier to a pair of speakers 3 If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter In the Diagnostic Menu select Audio 1 Tests Highlight AES Input Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see digital audio from the AES digital 1 input to both the RCA and Fix and Var outputs Press play on the DVD player Slowly increase the volume on the amplifier to a comfortable listening level from the speakers Verify that you hear clean clear audio coming from the speakers Pause the DVD and power down the amplifier 10 Move the cables from the Record Fix Left and Right outputs to the Record Var Left and Right outputs 11 Power on the amplifier press play on the DVD player and repeat Steps 7 9 oras OOND AES EBU Digital Input to Digital Outputs Test This test will verify the path of the AES EBU Digital input to the Digital S PDIF outputs RCA and Optical of the MC 12 MC 12 Balanced 1 Connect the digital output source to the AES EBU digital input on the rear panel of the MC 12 MC 12 Balanced 2 Connect the Coax S PDIF output on the back of the MC 12 MC 12 Balanced to the digital input of the DAT machine 3 Connect the L
307. e MC 12 s 1 S Video input Connect the S Video 1 Main output of the MC 12 MC 12 Balanced to the Monitors S Video Input Turn on the DVD Monitor and MC 12 MC 12 Balanced The Monitor should have a blue screen display On the MC 12 MC 12 Balanced remote press the DVD 1 button to select this as our Input for testing the video paths Press the Menu button on the remote The Main Menu should appear on the screen With the Down Menu button on the remote scroll down to SETUP then select by pressing the Right Menu button 8 The SETUP Menu will appear and the INPUTS at the top will be highlighted At this point press the Right Menu button again 9 The INPUT SETUP Menu will appear At the top will be DVD1 To keep things simple use this DVD1 Input to test all the video input and outputs of the MC 12 MC 12 Balanced 10 Press the Right Menu button The MC 12 MC 12 Balanced will now be set to the DVD1 INPUT SETUP Menu 11 Using Down button scroll down to the VIDEO IN S VIDEO 1 and press the Right Menu button 12 In the DVD1 VIDEO IN Menu select any of the 8 S Video Inputs of the MC 12 MC 12 Balanced to be tested by scrolling down to it and selecting the video path to be tested by pressing the Right Menu button 13 At this time the MC 12 MC 12 Balanced is already set to S Video 1 input to all the S video outputs Main 1 2 and Record 1 2 of the MC 12 MC 12 Balanced 14 Press the OSD button on the remote This will turn off the on screen
308. e filter This circuit discriminates a low or high DC voltage on the selected chroma input and forms a 0 or 5V level accordingly Sensing threshold is around 3V For both composite video and S video there are two monitor outputs available The On Screen Display OSD feature is available on the MONITOR 1 outputs but is absent from the MONITOR 2 outputs Monitor 1 S video at J4 is driven by gain of one amplifiers 915 and U22 chroma Internal multiplexers in these amplifiers determine whether the video is taken from the OSD path MTHRU hi straight through from the input amplifiers MTHRU low Amplifier outputs are fed through 75 ohm series resistors R121 R148 forming a matched transmission line driver system R120 and R147 compensate for slight impedance errors due to the resistance of the on board connecting traces The chroma output is AC coupled by C76 with a DC level introduced through R2 When 1 is asserted low switch U21 permits the Monitor 1 chroma output to follow the DC sensing circuit Monitor 2 S video at J3 is driven by gain of one amplifiers in U14 which are always driven from the input amplifiers R119 and R116 are required by the current amplifier topology of U14 Output impedance and coupling is structured as with Monitor 1 When MORPHEN low the chroma DC level of the selected input is sensed and replicated on the Monitor 2 chroma output through R1 Monitor 1 composite video CVID 1 is
309. e on the amplifier to a comfortable listening level from the speakers Sweep the oscillator from 20Hz to 20kHz Verify that you hear clean clear audio coming from the speakers 8 In order to test the remaining Analog inputs to the Record Fix output you must power down the amplifier move the input cables to the next paired audio inputs Next highlight the input being tested in the Audio Tests Menu and select it by pressing the Right Menu button 9 Repeat steps 5 to 7 until all the Audio Inputs have been tested ov Digital Input to Analog Outputs Test This test will verify the path of the 1 Coax digital input to all of the Main analog outputs both RCA and XLR of the MC 12 MC 12 Balanced Note This test requires the use of a DVD player as a source Therefore the tests to follow will be run at the 44 1kHz sample rate To properly test the full sample range of the MC 12 MC 12 Balanced you will need to repeat all of the Digital tests with 48 88 2 and 96kHz sample rate sources 1 Connect digital output source DVD Player to the 1 Coax digital input on the rear panel of the MC 12 MC 12 Balanced 2 Connect the RCA Left and Right Front outputs of the MC 12 MC 12 Balanced to the amplifier Left and Right inputs and the outputs of the amplifier to a pair of speakers 3 If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter In the Diagn
310. e remaining RCA and XLR paired Left and Right audio output connections Test Apply a 1kHz signal 12dBV 4 Vrms to the input of the MC 12 MC 12 Balanced Set the scale on the Distortion Analyzer to measure 12dBV 4 Vrms signal level Turn all the filters off on the Analyzer Verify that the output level from the MC 12 MC 12 Balanced is 12dBV 4 Vrms 3 71 to 3 45dBV Adjust the scale on the Distortion Analyzer to measure 0 005 THD N and turn on the 2 low pass or audio bandpass filter 4 11 MC 12 MC 12 Balanced Service Manual 17 Verify that the THD N measured is less than 0 003 Set the scale on the Distortion Analyzer to measure 12 dBV 4 Vrms signal level Using the output level from Step 4 above set for a OdB reference to check Frequency Response for the MC 12 MC 12 Balanced Turn the filter on the Analyzer off Sweep the oscillator frequency from 10Hz to 20kHz Verify the signal level is within 0 1 0 25dBV 0 754 40Hz of the of reference level over the entire sweep Set the scale on the Distortion Analyzer to measure 100dBr signal level with the filter on Turn off the oscillator to the MC 12 MC 12 Balanced and verify a noise level measurement lt 108dBr Swap cables from the Left 2 RCA input to the Right 2 RCA input and the Left Front RCA output to the Right Front RCA output Repeat Steps 1 13 above To test all the remaining Left and Right RCA inputs for r
311. eft Right analog outputs of the DAT to the Analog Left and Right inputs of the amplifier and its outputs to a pair of speakers If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter 4 Inthe Diagnostic Menu select Audio Tests 5 Highlight AES Input Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see digital audio from the AES digital 1 input to both the RCA and Fix and Var digital outputs 6 Press play on the DVD player 7 Slowly increase the volume on the amplifier to a comfortable listening level from the speakers 8 Verify that you hear clean clear audio coming from the speakers 9 Power down the amplifier and MC 12 MC 12 Balanced and move the digital cable from the S PDIF digital output to the Optical S PDIF digital output 10 Power on the amplifier and repeat Steps 6 to 8 Audio Performance Verification Performing these tests assures that the audio signal paths in the MC 12 MC 12 Balanced are functional and that the MC 12 MC 12 Balanced meets published specifications These tests will verify the performance of the A D and D A circuitry gain frequency response THD N and S N ratio AUDIO INPUTS RCA 1 LEFT AND RIGHT TO ALL LEFT AND RIGHT RCA XLR OUTPUTS TESTS This test will verify the specs of the main analog output channels for both RCA and XLRs Setup 1 Connect an audio cable betwe
312. eft and Right RCA output Press play on the DVD player Slowly increase the volume on the amplifier to a comfortable listening level from the speakers Verify that you hear clean clear audio coming from the speakers Pause the DVD and power down the amplifier In order to test the remaining Digital inputs both RCA and Optical you must move the Digital Input cable to the next Digital input RCA or Optical then highlight the input being tested in the Audio Tests Menu and select it by pressing the Right Menu button 11 Repeat steps 6 9 until all the remaining Digital Inputs have been tested Digital Input to Record Output Test This test will verify the path of the 1 Coax Digital input to the Record Fix and Var Left and Right outputs 1 2 E Connect digital output source DVD player to the 1 Coax Digital input on the rear panel of the MC 12 MC 12 Balanced Connect the RCA Left and Right Record Fix outputs of the MC 12 MC 12 Balanced to the amplifier Left and Right inputs and the outputs of the amplifier to a pair of speakers If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter In the Diagnostic Menu select Audio I O Tests Highlight S PDIF Input CX1 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see digital audio from the S PDIF 81 digital input to the Record Fix Left
313. el Page A 2 23 The MC 12 MC 12 MC 12 Balanced Balanced does not support MPEG input types 24 Some DVD players will produce audio artifacts when switching audio formats Diagnostics INTRODUCTION This section contains a complete description of the diagnostic tests for the MC 12 MC 12 Balanced The diagnostics in the MC 12 MC 12 Balanced are used to verify functionality of the unit and to aid in troubleshooting defective units DIAGNOSTICS CATEGORIES There are 2 types of diagnostics in the MC 12 MC 12 Balanced power on and extended The extended diagnostics contain the tests that are used by Lexicon manufacturing personnel to verify functionality and by repair personnel to aid in troubleshooting The entire set of power on diagnostics is executed every time a unit is powered on using the rear panel power switch The power on diagnostic tests can be run individually in the extended diagnostics The extended diagnostics also contain additional tests used to verify all the front panel controls infrared communications audio and video performance etc The troubleshooting or repair diagnostics are utilized to troubleshoot MC 12 MC 12 Balanced if any test fails Lexicon POWER ON MODES There are two power on modes available via the rear panel power switch or by bringing the MC 12 MC 12 Balanced out of standby mode The power on diagnostics are executed every time the rear panel power Switch is switched on When an MC 12 MC 12 Balanced
314. el you will need to locate 2 ribbon cables J35 and J33 Carefully remove them from the connectors on the Main Board 2 Remove the 2 screws from the inside top left and right corners of the front panel 3 Atthis time tip the MC 12 MC 12 Balanced carefully on its side and locate and remove the 3 remaining Screws on the bottom that hold the front panel 4 Remove the front panel and store it in a static free area CHANGING TRIGGER VOLTAGE FROM 12 VOLTS TO 5 VOLTS 1 With the Video and Analog boards removed as described above and the MC 12 MC 12 Balanced front panel facing you locate the 6 jumpers to the trigger circuit in the upper rear left hand corner of the Main board 2 Allthe jumpers W 1 6 are jumpered on pins 1 and 2 for 12 volt trigger output To make them all 5 volt trigger out all the jumpers must be moved to pins 2 and 3 REMOVING THE MAIN BOARD Removal of the Main Board can only be done after removal of the Video and Analog boards 1 Locate and remove the 7 screws and 3 standoffs holding the Main Board to the chassis 2 Using the same diagram locate and remove the 8 screws 5 dress nuts 4 nut screws and the trigger connector 3 Carefully remove the Main Board from the chassis and store it in a static free area INITIALIZATION HARD RESET PROCEDURE This is the initialization procedure for the MC 12 MC 12 Balanced CAUTION This procedure will clear all custom settings in the MC 12 MC 12 Balanced 1 Power down the MC
315. emote the display will read IR REMOTE Remote Test When a button is held down on the remote the display will read IR REMOTE Remote Test OCIR IR is displayed to indicate the remote is currently transmitting a signal VFD Character Test The combination of the Character Test and the Block Test verifies that all display segments are functioning The Character Test places the same character on all segments The ENCODER knob is then used to change the character The test has sufficient variation of characters to verify complete functionality of the display All characters present in the VFD can be observed When the test is selected the display will read 5 13 MC 12 MC 12 Balanced Service Manual The operator will use the ENCODER knob to view other characters To exit the test press the Mode Up button VFD Block Test The Block Test illuminates all pixels on a single segment of the VFD The ENCODER knob is then used to move the block to each segment Pressing the EFFECT DOWN button will execute the test and the display will read M The operator will use the ENCODER knob to view the block and to move the block through all VFD locations At the end of the line the block will wrap to the next line In the case of second line the block will return to the starting point on the first line Switch Test This test will verify all
316. en the output of the Low Distortion Oscillator and the MC 12 s Left RCA 1 audio input 4 10 Lexicon 2 Connect an audio cable between the Left Front RCA output of the MC 12 MC 12 Balanced and the input of the Distortion Analyzer 3 Place the MC 12 MC 12 Balanced into Extended Diagnostics as described at the beginning of this chapter 4 Inthe Diagnostic Menu select Audio Tests 5 Highlight Audio Input 1 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see audio coming in to the Left 1 RCA input to the Front Left RCA output Test 1 Apply a 1kHz signal 12dBV 4 Vrms to the input of the MC 12 MC 12 Balanced 2 Setthe scale on the Distortion Analyzer to measure 12dBV 44 Vrms signal level 3 Turn all the filters off on the Analyzer 4 Verify that the output level from the MC 12 MC 12 Balanced is 12dBV 4 Vrms 3 71 to 3 45dBV 5 Adjust the scale on the Distortion Analyzer to measure 0 005 THD N and turn on the 30kHz low pass or audio bandpass filter 6 Verify that the THD N measured is less than 0 003 7 Set the scale on the Distortion Analyzer to measure 12dBV 4 Vrms signal level 8 Using the output level from Step 4 above set for a OdB reference to check Frequency Response for the MC 12 MC 12 Balanced 9 Turn the filter on the Analyzer off 10 Sweep the oscillator frequency from 10Hz to 20kHz 11 Verify the signal level is within 0 1 0 25dBV
317. equired specifications you will need to repeat Step 5 in the Setup section and engage the next Audio Input Test in the diagnostic menu Repeat steps 1 14 AUDIO INPUTS RCA 1 LEFT AND RIGHT TO ZONE 2 LEFT AND RIGHT RCA FIX OUTPUTS AND ZONE 2 XLR OUTPUTS TESTS Setup 1 Connect an audio cable between the output of the Low Distortion Oscillator and the MC 12 s Left RCA 1 audio input 2 Connect an audio cable between the Zone 2 Left Fix RCA output of the MC 12 MC 12 Balanced and the input of the Distortion Analyzer 3 Place the MC 12 MC 12 Balanced into Extended Diagnostics as described at the beginning of this chapter 4 Inthe Diagnostic Menu select Audio Tests 5 Highlight Audio Input 1 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see audio coming in to the Left 1 RCA input to the Zone 2 Left Fix RCA output Tests 1 Apply a 1kHz signal 12dBV 4 Vrms to the input of the MC 12 MC 12 Balanced 2 Setthe scale on the Distortion Analyzer to measure 12dBV 4 Vrms signal level 3 Turn all the filters off on the Analyzer 4 Verify that the output level from the MC 12 MC 12 Balanced is 12dBV 4 Vrms 3 71 to 3 45dBV 5 Adjust the scale on the Distortion Analyzer to measure 0 005 THD N and turn on the 2 low pass or audio bandpass filter 6 Verify that the THD N measured is less than 0 003 7 Setthe scale on the Distortion Analyzer to measure
318. er testing Component Video 3 6 Remove the 3 wire RCA Component Video cable that connects the video output from the DVD player to the back of the MC 12 MC 12 Balanced 7 Using the 3 wire BNC Video cable connect the Component Video output of the DVD player to the MC 12 MC 12 Balanced Component 84 video input 8 Press play on the DVD player 9 Verify a clean undistorted picture appears on the screen 4 16 Lexicon LEXICON AUDIO PRECISION ATE SUMMARY This c Icon ided as a reference and supplement test settings and parameters used by Lex ision Prec hart represents a summary of Aud IS IS prov testing of all MC 12 MC 12 Balanced products Th production in this manual Ion IN to bench test settings found in the proof of performance sect wen x ERUNT 366 InO 140 098 OL WENO man or 3s WBE 110 10 938 OL 3807 Sov rue 84 05 5 2 OHLSSIno 190 INOZ ONY 57 or 1 men c 170 145 SI OL 3NOZ ONY DE RE LER GU
319. eri 16 evar 1 saa d ER 00 0 aste aste Xi gt 5 asian NOII4TNOSE NOISWHANOD V G LNOYd 1481 T 4 v 9 L 8 8 73 MC 12 MC 12 Balanced Service Manual Your Notes 8 74 Lexicon 8 75 n T e v 9 L 8 oz ao 115 00 2 8 ass 3 EWN 0 2 5 zm ast P 1 47 e saco azis 00 2 8 4 ammo gt SOYA 415 NHLNSO 00 2 8 mm a O T S INV WSHOS E p e nns 2 7188 mnt M T Y NI sns mw m 14
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322. hat closes the feedback loop around the input video amplifier during back porch time This acts to maintain the back porch level at OV D5 limits the negative going output of U20 in order to minimize the undesirable effects of unusual sync patterns inherent in the macrovision video copy protection scheme Additional logic within U1 detects the presence of a valid video input SYNC DETECT is fed to the Main Board for use in OSD management With video input absent OUT free runs at around 15kHz and is used as a general purpose clock to govern some default timing of state machines within the FPGA VIDEO CONTROL REGISTERS Video board schematic sheet 8 U3 4 and 5 are 8 bit shift registers which are cascaded to receive a 24 bit word Each chip contains internal shift stages plus a set of output latches The shift clock and data are arbitrated by the FPGA as described earlier Data that has been accumulated in the shift stages gets transferred simultaneously to all 24 output latches when the FPGA strobes the VREG RCLK All control bits are initialized to O at power up VIDEO RST is asserted to clear the internal shift stages When reset is removed the FPGA generates special VREG CLK to transfer the internal zeros to the output latches This occurs after a default interval based on the 15kHz clock POWER AND CONTROL INTERFACE Video board schematic sheet 9 J24 is the control and status interface to the host J22 supplies power from a
323. he instantaneous variation gets averaged by the action of the loop filter The result is a steady control voltage that produces a high stability VCO oscillation based on the average frequency of the reference The pulse duty cycle is adjusted automatically by an additional branch in the feedback loop When a pulse forward biases D11 current flows through R120 and gets integrated by C167 R119 supplies a constant current of opposite polarity which also gets integrated The two integrals oppose each other and when the net current into the summing node is 0 the voltage at U45 1 remains effectively constant DC If the duty cycle of the pulse is too small the voltage is driven progressively lower and vice versa The resulting voltage is applied to R121 which sinks current from the summing node of the loop integrator which tends to raise VCOV This tendency gets counteracted by current pulses through D14 and R124 When the integral of these two currents balance VCOV remains constant so OSC is a constant frequency and the loop is locked D16 prevents VCOV from going much below 2V to ensure that the VCO is never driven into a non oscillating state D15 prevents the duty cycle integrator from being driven to the wrong polarity when the loop is out of lock 6 21 MC 12 MC 12 Balanced Service Manual The gain of the loop is such that the PUMP UP and PLL PUMP DOWN pulses will cause VCO frequency to change quickly when the loop is trying
324. hould only be opened by qualified service personnel Removing covers will expose you to hazardous voltages A This triangle which appears on your component alerts you to the presence of uninsulated dangerous voltage inside the enclosure voltage that may be sufficient to constitute a risk of shock CAUTION RISK OF ELECTRIC SHOCK NOT OPEN A This triangle which appears on your component alerts you to important operating and maintenance Instructions in this accompanying literature Notice This equipment generates and uses radio frequency energy and if not installed and used properly that is in strict accordance with the manufacturer s instructions may cause interference to radio and television reception It has been type tested and found to comply with the limits for a Class B computing device in accordance with the specifications of Part 15 of FCC Rules which are designated to provide reasonable protection against such interference in a residential installation However there is no guarantee that interference will not occur in a particular installation If this equipment does cause interference to radio or television reception which can be determined by turning the equipment OFF and ON the user is encouraged to try to correct the interference by one or more of the following measures Reorient the receiving antenna Relocate the computer with respect to the receiver Move the computer away from the receiver Plug the computer into a
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326. ier to a comfortable listening level from the speakers 7 Sweep the oscillator from 20Hz to 20kHz Verify that you hear clean clear audio coming from the speakers 8 Power down the amplifier and move the cables from the Zone 2 Fix Left and Right outputs to the Zone 2 Var Left and Right outputs 9 Power on the amplifier and repeat the oscillator sweep as described in Step 7 10 Remove the RCA output cables from the Zone 2 Var Left and Right outputs of the MC 12 MC 12 Balanced to the amplifier 11 Connect a pair of XLR cables to the Left and Right Zone 2 Fix balanced outputs of the MC 12 MC 12 Balanced to the XLR balanced input of the amplifier 12 Repeat steps 7 to 9 All Remaining Analog Inputs to the ZONE 2 Fix Output Test This test will verify the path of the remaining analog Left and Right inputs 2 to 8 to the Fix Zone 2 Left and Right analog outputs pass signal 1 Connect the oscillator output to the Left and Right audio inputs marked 82 on the rear panel of the MC 12 MC 12 Balanced 2 Connect the RCA Left and Right Zone 2 Fix outputs of the MC 12 MC 12 Balanced to the amplifier Left and Right inputs and the outputs of the amplifier to a pair of speakers 3 If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter 4 Inthe Diagnostic Menu select Audio Tests 5 Highlight Audio Input 2 Test then press the Right menu button to engage the test
327. kg Rack Mounting Optional brackets are available for mounting either unit in a standard 19 equipment rack Environment Operating Temp 0 to 35 C 32 to 95 F Storage Temp 30 to 75 C 22 to 167 F Relative Humidity 9596 maximum without condensation Remote Control Hand held battery powered infrared remote control unit Batteries Two AA Lexicon Chapter 4 Performance Verification This section describes a quick verification of the operation of the MC 12 MC 12 Balanced and the integrity of its analog and digital audio signal paths Tests are included for the MC 12 Balanced version and can be omitted when testing an MC 12 MC 12 Balanced Functional Tests The following tests cover basic functions making sure the MC 12 MC 12 Balanced responds to button commands from the remote as well as from its front panel INITIAL INSPECTION 1 Inspect the MC 12 MC 12 Balanced for obvious signs of physical damage 2 Verify that all switches operate smoothly 3 Remove the MC 12 MC 12 Balanced top cover 4 Verify that all socketed ICs are correctly seated 5 Verify that all ribbon cables are correctly installed and are secure 6 Check for burnt or obviously damaged components 7 Using the main power switch on the back of the MC 12 MC 12 Balanced verify that it runs through its Diagnostics Test and settles into the last state it was powered down in 8 Check each of the front panel s switches for smooth mechanical operation
328. l The AK5383 stereo A D converter incorporates a dual bit delta sigma architecture It outputs 24 bits at a 96kHz sample rate under normal operation The serial audio data from the A D converter goes directly to the Main board The A D also provides a signal to mute the Main analog inputs MAININ VC when it is going through calibration during power up or sample rate changes Control signals are used for reset MAIN AD RST to place the converter in 88 2k or 96k sample rate mode MAIN AD 96K EN The Analog FPGA sheet 17 provides three clocks MAIN AD MCLK which is 256xFS for 44 1k and 48k sample rates 128xFS for 88 2k and 96k sample rates MAIN AD SCLK which is 64xFS and MAIN AD which is 1xFS where FS sample rate RECORD AND ZONE 2 A D CONVERTERS schematic sheet 4 The Record and Zone 2 Input level controls and A D converter circuits are identical to what is used by the Main inputs which are described in the Main A D Converter section The selected analog source gets routed to the 53310 level control Dual op amps condition the signal for the A D converters with 2 5 V of bias and 7 dB of attenuation Again 2 Vrms signal at the output of the level control will be equivalent to 0 dBFS after the A D conversion Note that the Zone 2 Input level control and A D converter are not required for the Zone 2 path because there is no associated digital output The Zone 2 A D converter and level control is only used
329. l DSPs and the 2180 Host processor Provides the DSP side of the Host DSP communication interface Lexicon DSP HOST INTERRUPTS INTERFACE HOST INTERRUPTS SHARC DSP A B CLOCKS amp AUDIO DATA SHARC DSP C D CLOCKS amp AUDIO DATA HOST DSP INTERFACE MAIN AUDIO CLOCKS amp DATA RECORD AUDIO CLOCKS amp DATA ZONE 2 AUDIO CLOCKS amp DATA CRYSTAL DECODER 549326 AUDIO CLOCKS amp DATA OPTION BOARD AUDIO I O AUDIO CLOCKS amp SPARES SPARES AUDIO FPGA BLOCK DAR FPGA schematic page 16 This FPGA provides the following functionality Allows the host to select which digital audio connector is connected to the Main Record and Zone 2 Digital Receivers Allows the host to choose between the crystal oscillators for analog audio the master clock output of the Digital Receivers or the output of the Phase Lock Loop as the master clock source for each zone Digital control signals for the Phase Lock Loop Control bits and sample rate detection clocks to the Main Record and Zone 2 Digital Receivers Host Serial Control Interface to the Crystal 49326 DSP Audio Decoder Consists of the chip select serial clock and data The FPGA converts the host parallel data to a serial data stream It also converts the serial output of the Crystal chip to parallel for the host to read Host Serial Control Interface to the Video Board and
330. lity Amplifier with RCA and XLR input connectors 1 Pair high quality Speakers with RCA and XLR input connectors 1 High quality Video Monitor with RCA S Video and Component RCA and BNC input connections 1 CD disc for test audio source 1 DVD movie disc for test video source Cables dependent on your signal source e Audio Input Cables with shield an RCA connector one end and an appropriate connector on the opposite end for connection to the Low Distortion Oscillator e Audio Output Cable with shield and an RCA connector end an appropriate connector on the opposite end for connection to the Distortion Analyzer e Audio Output Cable balanced with shield an XLR female plug on one end and appropriate connector on the opposite end for connection to the Distortion Analyzer 4 Audio Cables shielded with RCA connectors on both ends 2 Audio Cables shielded with an XLR male and female connector on either end 1 Digital Audio Cable with RCA connectors on both ends 1 Digital Audio Cable with Optical connectors on both ends 1 AES EBU Digital cable 1 Digital Audio Cable with Standard Optical connector on one end and an OMJ Optical Mini Jack connector on the other 2 Video Cables with RCA connectors on both ends 2 Video Cables with S Video connectors on both ends 1 Video Cable with 3 wire Component RCA connectors on both ends 2 Video Cables with 3 wire Component BNC connectors on both ends 1 High en
331. mmended Pages 3 18 to 3 23 and 3 26 to 3 27 The INTERNAL NOISE TEST calibration noise will pass briefly through the SUB R output when 13 1 The SUB L R parameter on the CUSTOM SETUP or THX SETUP menus is set to MONO Pages 3 22 and 3 24 5 1 MC 12 MC 12 Balanced Service Manual 13 2 During the INTERNAL NOISE TEST the SUB RIGHT parameter on the SPEAKER LEVELS ADJUST menu is manually selected Page 3 26 14 During the INTERNAL NOISE TEST it is possible to manually select a speaker just as the unit is about to automatically scroll to the next speaker This may cause the unit to send the noise signal to both outputs If this occurs reselect the desired speaker Page 3 26 15 Selecting EXTERNAL NOISE TEST on the LEVELS CALIBRATION menu will mute audio when the unit is configured for analog bypass To restore audio exit the SPEAKER LEVELS ADJUST menu To deactivate analog bypass set the ANALOG BYPASS parameter on the MAIN ADV menu to OFF page 3 13 Pages 3 26 and 3 27 16 When the SETUP parameter is set to LOCKED the STATUS parameter on the ON SCREEN DISPLAY and FRONT PANEL DISPLAY menus can still be set using the FP BLUE and OSD buttons on the remote control The SETUP parameter is located on the LOCKED OPTIONS menu Page 3 36 17 The MONO listening mode includes a SUB L R parameter Page 5 7 18 When a THX speaker configuration is selected the LFE parameter will appear on the OUTPUT LEVELS menu for the 5 1 THX SURROUND
332. n controlled situations Q2 energizes the relay un mutes when EXPOUTS is set high by software XLR Board has an overall inverting characteristic When LFRONT is negative going pin 2 of J14 is positive going This matches the inversion occurring in the final unbalanced output stage on the Analog I O Board so the RCA and XLR outputs are in phase The overall gain is such that the open circuit level at each balanced main output is approximately twice that of its unbalanced counterpart ZONE 2 VARIABLE CHANNELS XLR board schematic sheet 3 The description of the main channels applies to the zone 2 channels with the following exceptions The differential stage U15 has a gain of 2 The final unbalanced output stage on the analog i o board is non inverting so the zone 2 RCA and XLR outputs will be seen to be out of phase The overall gain is such that the open circuit level at each balanced zone 2 output is approximately 2 16 times that of its unbalanced counterpart The driver transistor for the zone 2 mute relays RY1 RY2 OPTO MIC INPUT BOARD This is a small helper board which has low level microphone preamplifiers and optical inputs The outputs from the microphone preamps are sent to the Analog Board via a ribbon cable and eventually to the A Ds on that board The optical inputs are sent via another ribbon cable to the Main Board Microphone Preamplifiers The circuitry here supplies power 9 volts to an exte
333. n diagnostic tests are completed This keeps the user informed as to the functioning of a MC 12 MC 12 Balanced If a failure occurs the test will attempt to write an entry into the error log and enter a loop to exercise signal lines to aid in debugging The error log is stored in the non volatile section of the SRAM so that it is not destroyed during the power on diagnostics A single error log entry is made each time the MC 12 MC 12 Balanced is powered up a diagnostic test is executed and a failure encountered IO FPGA The FPGA test loads and verifies the programming of the part If a failure occurs the test will attempt to write an entry into the error log write the test number and the error number to the VFD and LED matrix Digital Audio Receiver DAR FPGA The DAR test loads and verifies the programming of the part If a failure occurs the test will attempt to write an entry into the error log write the test number and the error number to the VFD and LED matrix Audio FPGA The Audio FPGA test loads and verifies the programming of the part If a failure occurs the test will attempt to write an entry into the error log write the test number and the error number to the VFD and LED matrix Analog FPGA The Analog FPGA test loads and verifies the programming of the part If a failure occurs the test will attempt write an entry into the error log write the test number and the error number to the VFD and LED matrix
334. n system and output level is 1Vp p when terminated in 75 ohms 2Vp p open circuit S VIDEO INPUTS Video board schematic sheet 1 Specific references are to input 1 other inputs are similar S video luminance inputs pin 4 of the mini DIN jacks are terminated and buffered the same as composite inputs AC coupling is applied after buffering C59 couples S video input 1 C167 couples composite input 1 Chrominance input 1 pin 3 of mini DIN jack J18 is first ac coupled by C22 and then buffered by emitter follower Q20 The DC level at the chroma input is direct coupled to subsequent sense circuitry through R54 Bias to the luma chroma emitter follower pairs is controlled by UG UT MONITOR COMPOSITE S VIDEO Video board schematic sheet 2 Composite and S video luminance connect to multiplexers U9 U25 and S video chrominance connects to 010 The monitor channel multiplexers are addressed by the MVID SELn bits When MCVID EN is asserted low U25 is enabled and the multiplexer selects one composite source The opposite sense enables U9 and U10 for selecting one S video source Q24 is a simple inverter The composite luminance MY signal from U9 U25 is amplified by non inverting stage U23 R156 makes the gain be slightly greater than the desired factor of two in order to make up for slight losses in other stages The signal from U23 1 is fed through R155 to the sync stripper and DC restorer sheet 7 The DC correction signal BPCOR return
335. ng devices Remove and insert boards with care When removing boards handle only by non conductive surfaces and never touch open edge connectors except at a static free workstation Minimize handling of ICs Handle each IC by its body Do not slide ICs or boards over any surface Insert ICs with the proper orientation and watch for bent pins on ICs Use static shielding containers for handling and transport To make a plastic laminated workbench anti static wash with a solution of Lux liquid detergent and allow drying without rinsing Lexicon Table of Contents MC 12 MC 12 Balanced Service Manual Lexicon Lexicon Chapter 1 Reference Documents Required Equipment Reference Documents MC 12 MC 12 Balanced User Guide Lexicon P N 070 14773 latest revision Required Equipment TOOLS The following is a minimum suggested technician s tool kit required for performing disassembly assembly and repairs Clean antistatic well lit work area with grounding wrist strap 1 1 Phillips tip screwdriver Magnetic tip preferred 1 14mm socket nut driver 1 Allen hex head wrench 2 5 mm 1 3 16 hollow nutdriver Solder 63 37 Tin Lead Alloy composition low residue no clean solder Magnification glasses and lamps SMT Soldering Desoldering bench top repair station TEST EQUIPMENT The following is a minimum suggested equipment list required to perform the proof of performance tests 1 High qua
336. nk is reported to the Serial Debug Port This performs an addition of the entire EPROM The test verifies that the calculated checksum matches the checksum value stored in the EPROM If an error occurs an attempt will be made to blink the STANDBY LED using a rate of a two blinks per several seconds and the test will attempt to enter a loop to exercise signal lines to aid in debugging 2180 SRAM The SRAM test will perform non destructive testing on the SRAM The non destructive test first saves the data in the location being tested Then that location is tested by writing and reading patterns 0x00 OxFF 0x55 OxAA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 and 0x80 The original data is then returned to the SRAM and the next location tested Once each location in the SRAM is verified a counting memory check is done throughout the SRAM to test buss integrity First each byte in a special 32 byte section is written with a count Then starting from the beginning of the block and incrementing through it the count is verified to be correct If so this area will be used to store the contents of the rest of SRAM as it under goes the count check in 32 byte blocks If an error occurs an attempt will be made to blink the STANDBY LED using a rate of a three blinks per several seconds and the test will attempt to enter a loop to exercise signal lines to aid in debugging Flash Checksum Test The Flash checksum test verifies the data in the flash memory Fo
337. nostic Test RECORD GAME amp ZONE 2 GAME Assuming the 2180 CPU and support circuitry is working pressing and holding the RECORD GAME and ZONE 2 GAME front panel buttons after a failure occurs will cause the MC 12 MC 12 Balanced to attempt to execute the next power on diagnostic step If a failure occurs the MC 12 MC 12 Balanced attempts to enter a test loop to keep the signal lines active as an aid in debugging the failure At the end of each successive loop the diagnostics will check to see if the RECORD GAME and ZONE 2 GAME buttons are being held Depending on the length of the test the amount of time required to press and hold the buttons will vary POWER ON DIAGNOSTICS As described earlier there are two power on modes in the MC 12 MC 12 Balanced Power on via the rear panel power switch and coming out of standby mode Power on diagnostics are executed every time the rear panel power switch is switched on Diagnostics are not run when the unit is brought out of Standby Power on diagnostics take approximately 40 seconds to complete The power on diagnostics are intended to verify basic hardware functionality of an MC 12 MC 12 Balanced Additional diagnostic tests are available for manufacturing and customer service to completely test the hardware and for debugging failures Initially an attempt is made to illuminate the VFD and front panel LEDs for approximately five seconds However during the first 6 tests processes the VFD will not be
338. not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter 4 n Diagnostic Menu select Audio Tests 5 Highlight AES Input Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see digital audio from the AES digital 1 input to both the RCA and XLR 6 Press play on the DVD player 7 Slowly increase the volume on the amplifier to a comfortable listening level from the speakers 8 Verify that you hear clean clear audio coming from the speakers 9 Pause the DVD and power down the amplifier 10 Move the cables from the Zone 2 Fix Left and Right outputs to the Zone 2 Var Left and Right outputs 11 Power on the amplifier press play on the DVD player and repeat Steps 7 8 12 Pause the DVD and power down the amplifier 13 Remove the RCA output cables from the Zone 2 Var Left and Right outputs of the MC 12 MC 12 Balanced to the amplifier 14 With a pair of XLR cables connect the Left and Right Zone 2 Fix balanced outputs of the MC 12 MC 12 Balanced to the XLR balanced input of the amplifier 15 Power on the amplifier press play on the DVD player and repeat Step 7 to 9 4 9 MC 12 MC 12 Balanced Service Manual AES EBU Digital Input to Record Output Test This test will verify path of the AES EBU digital input to the Record Fix and Var outputs 1 Connect the digital output source to the AES EBU digital input on the rear panel of th
339. ntrol FRONT DAC RST Front Main output selection DSP or analog direct path FRONT DACOUT SEL FRONT DIRECT SEL Mute for Front Main output level control FRONT VC MUTE Also shown on sheet 18 is a 60 pin dual row ribbon connector the interface to the Main board XLR BOARD CONNECTOR POWER SUPPLY CONNECTIONS AND REGULATORS schematic sheet 19 A 26 pin dual row ribbon connector routes the audio signals to the XLR board for MC 12 Balanced models There are two separate feeds from the 90W switching power supply to the Main and Analog boards The Video board gets its power from the analog board The Analog board has a 6 pin connector that accepts 215 volts 25 volts and two ground connections to the supply A 4 pin connector supplies the Video Board with 5VD 5 and 5VA A 7805 voltage regulator creates the 5VA supply from the 15V rail Heat is dissipated by a heatsink and 10 5W power resistor 5 is an alternative clean 5 volt supply used by the A D and D A converters and other sensitive circuitry XLR BOARD OVERVIEW The MC 12 Balanced XLR output board schematic 060 14469 provides balanced versions of the 12 main audio outputs and the two variable Zone 2 audio outputs Input signals and power are connected through a 34 pin ribbon cable to the Analog board The XLR board is housed in its own chassis which attaches to the basic MC 12 chassis to form the complete MC 12 Balanced MAIN CHANNELS
340. nverter clocks Realigns and buffers the audio data for all D A converters Serial state machine that allows the 2180 to control the DACs and level controls serially Provides the chip selects for 7 control registers 6 26 Lexicon The Z180 on the Main board communicates to the FPGA via an 8 bit data DBA D 7 0 and 5 bit address A 4 0 bus Appropriate Read RD Write WRJ and Chip select 5 signals active during communication The Main clock tree comes into the FPGA with a Master clock MAIN ANLG and word clock MAIN ANLG FS Data for the Main DACs MAIN DAC SD 5 0 comes into the FPGA in 25 format relative to the word clock input The FPGA reclocks the data internally and reformats it to support the mono mode operation of the Main DACs Each DAC receives its own data serially from the FPGA Separate clocks are provided for the Main A D converter and Main D A converters The following tables provide a description of the Main clock and data Main Inputs Description MAIN DAC 803 Side L R DAC 15 data Analog FPGA Main Clock and Data Inputs Analog FPGA Main A D amp D A Clock Outputs Likewise the Record and Zone 2 converters have independent clock trees so they can each run at different sample rates than the Main channels The data for the D A converters is reclocked inside the FPGA The following tables provide a description of the Record and Zone clock and data 1
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344. of the power cable meet International Electrotechnical Commission IEC safety standards DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE Do not operate the instrument in the presence of flammable gases or fumes Operation of any electrical instrument in such an environment constitutes a definite safety hazard KEEP AWAY FROM LIVE CIRCUITS Operating personnel must not remove instrument covers Component replacement and internal adjustments must be made by qualified maintenance personnel Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them DO NOT SERVICE OR ADJUST ALONE Do not attempt internal service or adjustment unless another person capable of rendering first aid and resuscitation is present DO NOT SUBSTITUTE PARTS OR MODIFY INSTRUMENT Because of the danger of introducing additional hazards do not install substitute parts or perform any unauthorized modification to the instrument DANGEROUS PROCEDURE WARNINGS Warnings such as the example below precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed Dangerous voltages capable of causing death are present in this instrument Use extreme caution when handling testing and adjusting CAUTION Notch ICs inserted backwards will be dest
345. on Analyzer to measure 0 005 THD N and turn on the 2 low pass or audio bandpass filter Verify that the THD N measured is less than 0 003 Set the scale on the Distortion Analyzer to measure 12 dBV 4 Vrms signal level Using the output level from Step 4 above set for a OdB reference to check Frequency Response for the MC 12 MC 12 Balanced 9 Turn the filter on the Analyzer off 10 Sweep the oscillator frequency from 10hz to 20kHz 11 Verify the signal level is within 40 1 0 254 0 754 40Hz of the reference level over the entire Sweep 12 Set the scale on the Distortion Analyzer to measure 100dBr signal level with the filter on 13 Turn off the oscillator to the MC 12 MC 12 Balanced and verify a noise level measurement lt 108dBr 14 Swap cables from the Coax 81 Digital input to the Coax 2 Digital input 15 To test all the remaining Left and Right RCA inputs for required specifications you will need to repeat Step 5 in the Setup section and engage the next Audio Input Test in the diagnostic menu 16 Repeat steps 1 13 Video Input Output Tests These tests will verify that all 17 video inputs and 9 outputs pass video There are 3 different types of video to be tested in the MC 12 MC 12 Balanced Composite 5 Input and 4 Outputs S Video 8 Inputs and 4 Outputs Component 4 Inputs and 1 Output The following tests will verify that the MC 12 MC 12 Balanced is passing clea
346. on the ANLG IN LVL menu indicate signal levels for the selected input whether the input signal is analog or digital For example if the input signal is digital only the level meters will indicate the digital input signal levels Page 3 6 The factory default setting of the COMPONENT OSD parameter is OFF When set to ON the component on screen display appears on a full blue screen background This includes the two line status The COMPONENT OSD parameter is located on the MAIN ADV menu Page 3 14 The ANLG IN LVL parameter on the RECORD ADV menu only affects the digital RECORD AUDIO OUTPUT labeled S PDIF This is used to prevent the internal analog to digital converter from overloading This can be adjusted while listening to an input source Page 3 17 Changing the setting of the DIG OUT RATE parameter will cause the digital RECORD AUDIO OUTPUT labeled S PDIF to mute momentarily even if the DIGITAL BYPASS parameter is set to ON The DIG OUT RATE and DIGITAL BYPASS parameters are located on the RECORD ADV menu Page 3 17 When the REAR L R parameter is set to NONE the unit redirects rear channel signals to the SIDE L R outputs This item refers to the REAR L R parameter on the CUSTOM SETUP menu Page 3 21 Speaker parameters that are set to NONE or OFF on the CUSTOM SETUP menu cannot be adjusted during the INTERNAL NOISE TEST These speakers can be adjusted during the EXTERNAL NOISE TEST or on the SPEAKER DISTANCES menu but this is not reco
347. ord E 9 20 43 mi f _ E 0781271 1181271 2081271 102745 7181271 181271 9381571 P 85 71 80 9n vn en 20 In Qus CON3 04 12 92 1621 72 t5 5 15 5 828 zT 9H 12 2 6n 5 2 bed Led 65 N etg Ezy ery 8 L BUR 20 LE me 278 38 M 2 2 2 EJ n OE 529 525 9 SH TE E E i gt Em E s MC 12 MC 12 Balanced Service Manual Your Notes 8 148 Lexicon 10 2 133 5 V N 31 25 2 InOAV LNINOdWOD a3 0 210N 48 Q031 MS 0021 9 3015 WOLLOd OO vMS 8 5 2119 0115 2 5 gems bems EMS LMS LIMS 286 L2MS 5 ZMS OMS 9204 ems IMS SMS 6MS erms
348. ostic Menu select Audio Tests Highlight S PDIF Input CX1 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see digital audio from the S PDIF 81 digital input to the Front Left and Right RCA output and all the remaining RCA and XLR paired Left and Right audio output connections Press play on the DVD player Slowly increase the volume on the amplifier to a comfortable listening level from the speakers Verify that you hear clean clear audio coming from the speakers Pause the DVD and power down the amplifier 10 Move the cables from the Front Left and Right outputs to the Center Left and Right outputs 11 Power on the amplifier press play on the DVD player and repeat Steps 7 8 12 Repeat steps 7 10 for the remaining paired RCA outputs up to the Left and Right Aux The Zone 2 and Record outs will be tested later Remove the RCA output cables from the MC 12 MC 12 Balanced to the amplifier 13 With a pair of XLR cables connect the Left and Right balanced outputs of the MC 12 MC 12 Balanced to the XLR balanced input of the amplifier 14 Repeat steps 7 10 for the remaining paired XLR balanced outputs up to the Left and Right Aux As in the RCA test above the Zone 2 XLR will be tested later oue 4 5 MC 12 MC 12 Balanced Service Manual Remaining Digital Inputs to Analog Output Test This test will verify the path of all the remaining Coax and Optical Digital
349. pae 81551 B Y en yn E 8 141 MC 12 MC 12 Balanced Service Manual Your Notes 8 142 Lexicon 8 143 T30 113385 Y N 31 25 2 1 LNINOdWOD Qd 28 0301 vo 1 3 YE SE SEE eau Eng 9 a 220 221 MC 12 MC 12 Balanced Service Manual Your Notes 8 144 Lexicon 8 145 1101 133 5 W N 3158 6 1 LNINOdNOD 8 212WN 44 901VNV UO XA
350. r clean video to it source It is not necessary to enter the Extended Diagnostics as we did in the Audio tests to perform the Video tests COMPOSITE INPUTS TO COMPOSITE MAIN AND RECORD OUTPUTS TESTS This test will set up a simple pass through of Video information in order to verify the Composite video switching properties of the MC 12 MC 12 Balanced Setup 1 Connect the Composite video output from the DVD to the MC 12 s 1 Composite video input 2 Connect the Composite video 1 Main output of the MC 12 MC 12 Balanced to the Monitor s Composite video Input 3 Turn on the DVD Monitor and MC 12 MC 12 Balanced 4 The Monitor should have a blue screen display 5 MC 12 MC 12 Balanced remote press the DVD 1 button to select this as the Input for testing the video paths 6 Press the Menu button on the remote The Main Menu should appear on the screen 7 With the Down Menu button on the remote scroll down to SETUP then select by pressing the Right Menu button 8 The SETUP Menu will appear and the INPUTS at the top will be highlighted At this point press the Right Menu button again 9 The INPUT SETUP Menu will appear At the top will be DVD1 To keep things simple use this DVD1 Input to test all the video inputs and outputs of the MC 12 MC 12 Balanced 10 Press the Right Menu button The MC 12 MC 12 Balanced will now be set to the DVD1 INPUT SETUP Menu 11 Using Down button scroll down to the VIDEO IN S VIDEO 1 and
351. r Notes 8 60 Lexicon 8 61 T 2 9 00 2 8 TS e men 00 2 5 20 090 xc wann 00 2 5 WE Sima inant 1 097075 nre Intl T d ERST E I E O LTO VW SuiA z S4gpo wo E m 1 done z seor ONG 8 T T 33 es Y aste i 4 1 iS 4 EH 954 085 2 mu 4 212 se or Pg oor vos YS cue i 0 87 054 aste aste at ry xoot aaost 065 Ir 094 0527 H 4 98 B 3 5 E xis Y aste aste SU3A0 z S4HpO AST m 1 L 084 2 9 4 oso zn 08 m z se or S93
352. r all banks the checksum test adds up all the data in each bank except for the bank and stored checksum locations stored in the last 3 locations of each bank The added value is then verified against stored values If an error occurs an attempt will be made to blink the STANDBY LED using a rate of a four blinks per several seconds and the test will attempt to enter a loop to exercise signal lines to aid in debugging Display for the Remaining Tests If the following tests fail the VFD display and LED matrix will display the test and error fault if one occurs as previously discussed The VFD will display the test number and the error code In the event that the VFD is not operable the same information will be written to the LED matrix The test number will be read out as in the top row The error number can be read out in the second row Most Significant Byte and third row Least Significant Byte VFD Test The VFD performs a busy test and a memory test The busy test sends information to the VFD and verifies that the VFD asserts then de asserts its busy status The VFD memory test consists of writing 55h and AAh to the character generator memory and display memory space of the VFD and reading them back After the MC 12 MC 12 Balanced has passed the VFD Test for the rest of the power on diagnostics the VFD displays 5 8 Lexicon DIAGNOSTIC TESTS The dots increment in number from both sides simultaneously as the rest of the power o
353. racter strings to be displayed are loaded serially into the screen memory within the chip The bitmapped patterns that define the shapes of individual characters are stored in external font memory interfaced through the A 18 0 and D 7 0 buses see below Character dot clock is fixed at about 15 MHz based on the external LC circuit formed by L18 C140 C139 A crystal clock is supplied by oscillator U35 PAL or U36 NTSC The active oscillator is determined by a high level on either NTSC_EN or PAL_EN enabling the respective oscillator In overlay mode composite or S video luminance from the input amplifier is applied to YIN and similarly S video chrominance if applicable is applied to CIN The video applied to YIN is shifted to have a back porch DC level of about 1 57VDC by U13 and associated circuitry C97 C75 passively couple the ac content of the luminance signal with the op amp providing the DC response The chroma channel is biased to the same 1 57V level by R201 R202 The OSD video is related to program video by the separate H and V syncs GMHSYN VSYNC derived by the sync stripper sheet 7 The full screen mode is independent of video and sync inputs Raster generation is based on the appropriate crystal clock 6 33 MC 12 MC 12 Balanced Service Manual The OSD luminance output is DC shifted back to OV back porch level by U13 and associated circuitry C141 C142 passively couple the AC content with the op amp providing the DC re
354. reads on every active horizontal scan line SYNC STRIPPER DC RESTORER Video board schematic sheet 7 Video from input amplifier 023 is fed through R155 to the series LC chroma trap formed by 117 and associated capacitors With EN asserted 012 connects directly to C91 disconnecting C90 making the LC trap frequency about 3 6MHz With the switches in the other position the effective capacitance is the series combination of C90 and C91 and the resulting lower capacitance raises the trap frequency to about 4 4MHz suitable for PAL Trapping the chroma enhances the accuracy of back porch DC restoring U20 buffers the chroma trap output and drives sync stripper U1 and the DC restorer formed by switch 012 and op 020 6 34 Lexicon Sync stripper U1 accepts analog video and extracts vertical and horizontal sync producing logic level VSYNC OUT and AFC OUT pulses respectively A phase locked loop based on ceramic resonator Y 1 provides robust horizontal sync extraction even from noisy video sources Pull down resistors on the outputs improve the pulse waveshapes Sections of U2 buffer and shape the pulses from U1 AFC OUT is stretched by R69 C1 before buffering in order to meet the minimum width necessary for the OSD chip Sections of U2 and the network formed by R71 R72 D1 and C36 form pulses that are aligned with video back porch These pulses switch U12 which in combination with integrator U20 forms a sample and hold circuit t
355. rnal microphone capsule and performs balanced to unbalanced conversion and amplification The input op amp is protected from the common mode phantom power by input capacitors and an inductor capacitor RFI filter network The op amp has unity gain to a differential signal from the microphone while rejecting common mode noise The output of the op amp is amplified by nineteen by the next op amp A 270 ohm resistor isolates the output from reactive loads Microphone Phantom Power Supply Power is pulled from the 415 supply and regulated down to 9 volts by a voltage regulator Diode D1 prevents back biasing the regulator when 15 is removed An RC filter is created by 330 ohms and 10uF The 2 2K resistors provide current limiting and define the input impedance that the microphone sees at the input of the amplifier Optical Inputs This part of the board serves as a riser board for three optical S PDIF inputs Power is supplied by the Main Board via a separate cable Video BOARD OVERVIEW The MC 12 video section consists of two major functional blocks video switcher and on screen display generator OSD 6 30 Lexicon The video assembly consists of two boards the Video RCA Board schematic 060 13609 and the Video Board schematic 060 13679 The two boards are interconnected with a flexible 32 pin ribbon connector with most of the active circuitry contained on the Video Board Video input and output connectors are mounted dire
356. royed Incorrect insertion of ICs is also likely to cause damage to the board Pin SAFETY SYMBOLS General definitions of safety symbols used on equipment or in manuals gt Instruction manual symbol the product will be marked with this symbol when it is necessary for the user to refer to the instruction manual in order to protect against damage to the instrument gt Indicates dangerous voltage Terminals fed from the interior by voltage exceeding 1000 volts must be so marked The WARNING sign denotes a hazard It calls attention to procedure practice condition or the like which if not correctly performed or adhered to could result in injury or death to personnel CAUTION The CAUTION sign denotes a hazard It calls attention to an operating procedure practice condition or the like which if not correctly performed or adhered to could result in damage to or destruction of part or all of the product NOTE The NOTE sign denotes important information It calls attention to procedure practice condition or the like which is essential to highlight Electrostatic Discharge ESD Precautions The following practices minimize possible damage to ICs resulting from electrostatic discharge or improper insertion Keep parts in original containers until ready for use Avoid having plastic vinyl or styrofoam in the work area Wear an anti static wrist strap Discharge personal static before handli
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358. s w A etaa m aaer 0 82 61 v 5 TONINOO Zo xn wn zta AST 2 3 T 5 moe oeta er 5 44 00 4 oco bells cm neum Ae 100 808 m w 880 ans 49 810 staa j 7 ze vere D cu ewe UN per a noun 69 0 x ast Recto e OA ANNA xor 1 409 410 TE vr unoowr 62 01 Va i ino ens 12481 w cere 016680 staa ae aste aaet otza L8 107327 d aw 1079277 oot sajet 1072 1 5 67671 TIONINOO CHANT 2 E 00 01100 84104100 NIVM ans 2576276 0078576 a 0276275 0972276 227 08000 woa astama 55 NOLIATHOSEG am SNOTSTARE T 4 v 9 L 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 88 Lexicon
359. s 8 132 Lexicon 8 133 T 2 5 2 cancer 3 3 8 o 6989 090 270 0072711 amomo 00788701 06410 VW Nd uoo 80 SWOINNDISSG 1641 S annos wawoa sisswuo T SOTWNY Y 45 SHOLSISSH GHINOIGNI SSIMNSHLO Z 9 to MOT T SSIMNSHIO SSSIND T OA sazon t 550 wna Y 1 204 c z zerea se t se T 4 2 iji w ES HIN EN 55 NOLIATHOSEG SNOTSTARE T 4 MC 12 MC 12 Balanced Service Manual Your Notes 8 134 Lexicon 8 135 5
360. s through R158 to close the DC feedback loop and maintain the video back porch near OVDC The signal OSD is distributed to output amplifiers 015 014 039 038 and also feeds the on screen display sheet 5 Chroma selected by U10 MC is ac coupled by C102 and amplified by U23 also with gain slightly greater than two With a composite source selected U10 is disabled no signal is selected and the chroma channel is turned off D6 is used to enhance chroma on off switching With U10 disabled D6 is forward biased by R152 shunting the un driven node with a low impedance to ground When U10 is enabled the DC level at 6 31 MC 12 MC 12 Balanced Service Manual U10 3 is negative due to the operating point of the selected emitter follower D6 is reverse biased and is effectively an open circuit The signal OSD C is distributed to output amplifiers 022 014 039 038 and also feeds the on screen display sheet 5 The DC level on the chroma channel of the selected source is fed to the base of Q22 through multiplexer U8 and the associated 100k series resistor R95 raises the threshold for sensing a high level The DC amplifier formed by 022 and 021 is disabled when MORPHEW is high When enabled a high DC level on the chroma input will drive base current into Q22 Q22 saturates and turns on Q21 which applies a high DC level to the filter formed by R92 and C49 With low DC level input both transistors remain off and no DC is fed to th
361. s a byte into the DSP to Host Status Register by asserting DSP HOST CS and DSP This sets a bit in the I O FPGA that lets the host know that that register is full and waiting to be 6 13 MC 12 MC 12 Balanced Service Manual read When the host reads the byte the STATUS FULL line to the SHARC is cleared so the SHARC knows that the register is empty and can be written to again AUDIO DSP STATUS WR 3 DSP STATUS FULL L DSP STATUS FULL DSP HOST CS n g FPGA DSP_WR gt yo STATUS REG TO SHARC FPGA FULL HOST DSP S 8 STATUS DSP HOST DATA DSP DATA STATUS REG le DSP STATUS RD DSP STATUS WR HOST DSP COMUNICATIONS SHARC DSP WRITES DATA TO HOST BLOCK AUDIO ROUTING Digital Audio Input Path schematic pages 4 16 and17 Digital Audio can be either PCM 2 channel data or one of the compressed data formats It enters the unit on one of the digital input connectors that are connected to the DAR FPGA The FPGA functions as a mux and routes the output NRZ Non Return to Zero data of the connector selected by the user to the three Digital Receivers Main Record and Zone These receivers lock to the incoming signal and extract a 2 channel PCM audio signal that is sent to the Audio FPGA N
362. s play on the DVD player 8 Slowly increase the volume on the amplifier to a comfortable listening level from the speakers 9 Verify that you hear clean clear audio coming from the speakers 10 In order to test the remaining Digital inputs both RCA and Optical to the digital S PDIF output you must power down the amplifier and move the Digital Input cable to the next Digital input RCA or 4 8 Lexicon Optical Next highlight the input being tested in the Audio Tests Menu and select it by pressing the Right Menu button 11 Repeat steps 7 9 until all the remaining Digital Inputs have been tested AES EBU Digital Input to all Analog Outputs Test This test will verify the path of the AES EBU digital Input to all of the Main analog outputs both RCA and XLR of the MC 12 MC 12 Balanced 1 Connect the digital output source DVD player to the AES EBU digital input on the rear panel of the MC 12 MC 12 Balanced 2 Connect the RCA Left and Right Front outputs of the MC 12 MC 12 Balanced to the amplifier Left and Right inputs and the outputs of the amplifier to a pair of speakers 3 If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter 4 Inthe Diagnostic Menu select Audio Tests 5 Highlight AES Input Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set to see digital audio from the AES digital 1 inpu
363. set to see audio coming in to the Left 1 RCA input to the Record Left Fix RCA output Tests Apply a 1kHz signal 12dBV 4 Vrms to the input of the MC 12 MC 12 Balanced Set the scale on the Distortion Analyzer to measure 12dBV 4 Vrms signal level Turn all the filters off on the Analyzer Verify that the output level from the MC 12 MC 12 Balanced is 12dBV 4 Vrms 43 71 to 3 45dBV Adjust the scale on the Distortion Analyzer to measure 0 005 THD N and turn on the 30kHz low pass or audio bandpass filter Verify that the THD N measured is less than 0 003 Set the scale on the Distortion Analyzer to measure 12 dBV 4 Vrms signal level Using the output level from Step 4 above set for a OdB reference to check Frequency Response for the MC 12 MC 12 Balanced 9 Turn the filter on the Analyzer off 10 Sweep the oscillator frequency from 10Hz to 20kHz 11 Verify the signal level is within 40 1 0 254 0 754 40Hz of the reference level over the entire sweep 12 Set the scale on the Distortion Analyzer to measure 100dBr signal level with the filter on 13 Turn off the oscillator to the MC 12 MC 12 Balanced and verify a noise level measurement lt 108dBr 14 Swap cables from the Left 1 input to the Right 1 input and the Left Record Fix output to the Right Record Fix output 15 Repeat Steps 1 13 above 16 Repeat the test above for the Left and Right Record Var outputs OU RONA ALL DIGITAL
364. sponse Chroma is simply ac coupled by C149 C150 The shifted OSD video is buffered and filtered by U37 to produce OSD SY OUT and OSD SC OUT OSD PY OUT is buffered separately by U38 to drive the component OSD luminance output Switch U21 permits the S video luminance to be turned off when MSVID OFF is asserted high OSD OUT is formed as half the sum of the buffer outputs These OSD output signals feed the output amplifiers as described earlier In order to produce usable overlays in the SECAM system the OSD switching action is bypassed at high frequency through U21 and R144 preserving an attenuated version of the FM color carriers SUPPORT LOGIC FPGA Video board schematic sheet 6 When power is applied the video FPGA receives its configuration program from SROM U29 Once configured the FPGA interfaces the Main Board serial control port to the Video Board There are 3 possible destinations for control data on the Video Board OSD control registers and character font SRAM Data are conveyed in multiple 8 bit packets on VIDEO DATA accompanied by VIDEO SCLK operating at 1 MHz Data and clock connect directly to the OSD chip U34 and when chip select OSD is asserted from the Main Board the FPGA asserts OSD 5 to implement the interface to the chip Each logical transfer to the OSD chip consists of a pair of single byte transfers VIDEO REG acts as a multi purpose chip select that supports data transfer to other subsystems of the
365. ssage on the top line of the VFD For example DIAGNOSTIC TESTS is on the VFD while the power on diagnostics is being run Failure messages are displayed by an E followed by a number that indicates which test failed Front Panel LEDs The top row of the front panel LEDs are also used to display diagnostic status The LEDs are used in binary format with the Record LD LED as the LSB and the Main DVD 1 LED as the MSB Running test number 1 would illuminate the Record LD LED only with all the others off Running test number 2 would illuminate the Record DVD 2 LED only with all others off Running test number 3 would illuminate the Record LD and the Record DVD 2 LEDs together with all others off etc The table below lists the tests run and what front panel LEDs are used to indicate them Not all of the tests listed are performed during power on Those tests that are run during power on are listed in the In Use column with Those marked with a are not The table shows all of the tests available not just power on tests Test Test Name In Front Panel LEDs On Num Use 1 Trap Opcode Blink Standby LED 1 time interval 2 EPROM Chksum Via EPROM Blink Standby LED 2 times interval 3 2180 SRAM Blink Standby LED 3 times interval 4 Flash Checksum Via EPROM Blink Standby LED 4 times interval 5 VFD Memory Rec DVD 1 and Record LD 6 10 FPGA Rec DVD 1 and Record DVD 2 7 Digital Audio Receiver
366. sure the top of the battery to ground Note If battery is in need of replacement CAUTION CAUTION Danger of explosion if battery is incorrectly replaced Replace only with the same or equivalent type 4 1 MC 12 MC 12 Balanced Service Manual Analog Board Supply Rail Tolerance Location facing front panel 5VDC 4 75 5 25VDC Lower left hand corner connector J26 Red wire to ground 5VDC 4 75 5 25 J26 Grey wire to ground 15V 15 00 16 95 J26 Yellow wire to ground 15V 14 25 15 75 J26 Blue wire to ground Video Board Supply Rail Tolerance Location facing front panel 5VA 4 75 5 26 Lower left hand corner connector J22 Red wire to ground 5 4 75 5 26 J22 Grey wire to ground SETUP In order to properly test the MC 12 MC 12 Balanced as described in this document follow this setup procedure before hand It will make it much easier to follow along and perform each of the tests to follow 1 Connect a small color monitor to the Composite output This will allow you to fully view the diagnostic menus of the MC 12 MC 12 Balanced 2 Press and hold down the Zone 2 LD and the Record LD buttons on the front panel while powering up the MC 12 MC 12 Balanced with the Main Power Switch on the back of the unit 3 Once the display reads Lexicon release the buttons on the front panel 4 The Display on the front panel will read DIAGS MENU FUNCTIONAL TESTS
367. szasu 00 62 6 0078276 SWNOLIOVdVO SSVdAH EA n W 00 tZ8000 a ES m mE T t v 5 9 L 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 98 Lexicon 8 99 7 y 5 9 L 8 omes e E 8 Se US XH I s 90 15 0076177 440 ammo P 83 2 OSGIA S SINANI 66 1 21 T j T 598 1 se Y 1 58104100 YOLINOW M gg T E 7 7 RLISOdWOD 1 1991 5 59 9 as v LOZA 190 0 555 DEE 1006 PEZO 7 8 80 678021 15153555 DXINDCIMUNOD
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369. t to both the RCA and XLR 6 Press play on the DVD player 7 Slowly increase the volume on the amplifier to a comfortable listening level from the speakers 8 Verify that you hear clean clear audio coming from the speakers 9 Pause the DVD and power down the amplifier 10 Move the cables from the Front Left and Right outputs to the Center Left and Right outputs 11 Power on the amplifier press play on the DVD player and repeat Step 7 12 Repeat steps 7 9 for the remaining paired RCA outputs up to the Left and Right Aux The Zone 2 Record outs will be tested later 13 Remove the RCA output cables from the MC 12 MC 12 Balanced to the amplifier 14 With a pair of XLR cables connect the Left and Right balanced outputs of the MC 12 MC 12 Balanced to the XLR balanced input of the amplifier 15 Repeat steps 7 9 for the remaining paired XLR balanced outputs up to the Left and Right Aux As in the RCA test above the Zone 2 XLR will be tested later AES EBU Digital Input to Zone 2 Output Test This test will verify the path of the AES EBU digital input to the Zone 2 Fix and Var RCA and XLR outputs 1 Connect the digital output source DVD player to the AES EBU digital input on the rear panel of the MC 12 MC 12 Balanced 2 Connect the RCA Left and Right Zone 2 Fix outputs of the MC 12 MC 12 Balanced to the amplifier Left and Right inputs and the outputs of the amplifier to a pair of speakers 3 If the MC 12 MC 12 Balanced is
370. table listening level from the speakers Sweep the oscillator from 20Hz to 20kHz Verify that you hear clean clear audio coming from the speakers 8 In order to test the remaining Analog inputs you must power down the amplifier and move the input cables to the next paired audio inputs 9 Repeat steps 4 8 5 above highlighting the next input to be tested in the Audio I O Tests Menu and select it by pressing the Right Menu button 10 Repeat steps 5 to 7 until all the Audio Inputs have been tested Analog Input to Zone 2 Output Test This test will verify the path of the 1 Left and Right RCA paired input to the Zone 2 Fix Var outputs 1 Connect the oscillator output to the Left and Right audio inputs marked 81 on the rear panel of the MC 12 MC 12 Balanced 2 Connect the RCA Left and Right Zone 2 Fix outputs of the MC 12 MC 12 Balanced to the amplifier Left and Right inputs and the outputs of the amplifier to a pair of speakers 3 If the MC 12 MC 12 Balanced is not in Extended Diagnostics follow the setup procedure as described at the beginning of this chapter 4 Inthe Diagnostic Menu select Audio Tests 4 3 MC 12 MC 12 Balanced Service Manual 5 Highlight Audio Input 1 Test then press the Right menu button to engage the test The MC 12 MC 12 Balanced is now set for audio coming in to the Left and Right 1 RCA input to the ZONE 2 Left and Right RCA outputs 6 Slowly increase the volume on the amplif
371. the button is pressed a message is sent out the RS232 port at pin2 of J4 Therefore this will activate the COMO TXO signal coming from the Z180 pin 48 In the situation where the test passes the COMO RX signal is present at 2180 pin 49 as long as the wraparound plug is connected Another way to test this circuit is to verify the IR Receiver green LED lights briefly when the button is pressed This approach can be helpful when troubleshooting intermittent failures Note Ifthe unit is attached to a debugging PC then serial port A will fail however if the PC s terminal software is showing results and the user is able to type in commands or run debug scripts then the port is working IR Remote This test verifies the functionality of the IR Remote by pressing on the remote and verifying that the VFD displays which IR remote button was pressed The VFD displays in hexadecimal the code received when a remote key is pressed The hex display on the VFD remains unchanged until another remote key is pressed While the remote key is being pressed the IR acknowledge LED will flash and the VFD displays the message IR without the quotes next to the hex value When you have successfully exited the test the VFD will display an arrow on the left side pointing to the word REMOTE When the test is selected the display will read IR REMOTE Remote Test All buttons except for Mode Down will be inactive When a button is hit pressed release on the r
372. tor from load influences External signal conditioning is necessary to convert the output OSC to a logic level that is compatible with downstream logic devices The VCO module is intended to be operated at 22 579 2 or 24 576 2 with control voltage in the 5 to 6 Volt range 6 20 Lexicon VCO Signal Conditioning main board schematic sheet 18 The 700 mVpp OSC output of the VCO is ac coupled and amplified to a 5V logic level by U44 which is self biased near the middle of its inverting characteristic The VCO module and associated sensitive circuitry is supplied from a dedicated 5V regulator U32 PLL OVERVIEW The purpose of the PLL is to develop a pure stable clock that matches the average properties of a potentially jittery unstable reference The elements of a PLL are frequency phase detector error amplifier filter and controllable oscillator PLL Phase Detector main board schematic sheet 16 PLL MCKO from the VCO is fed to the DAR FPGA U19 for use as a 512FS master clock at 44 48kHz and a 256FS master clock at 88 96kHz Within the FPGA the VCO frequency is divided by 512 to 44 or 48kHz and the result is frequency phase compared with a corresponding frequency derived from a selected reference e g quartz crystal digital audio receiver When the frequency of the VCO is too low relative to the reference a train of active high pulses occurs on PLL PUMP UP When the VCO frequency is too high relative to the reference a
373. transitions The following figures illustrate the operation of the circuit 6 18 E gt y eres vittime N PRE i 5 Ch2 5 00 V 10 008 1 60 5 00V 4 5 00 V 5 Dec 2001 12 19 60 16 56 27 Figure 1 Normal Encoder Lexicon ENCODER A ENCODER B CHARGE T RUN Figure 1 illustrates the operation of a new well behaved encoder T RUN can be seen to end at the delayed trailing edge of CHARGE which begins rising when ENCODER B returns high With opposite direction of rotatation B would precede A NJ REACH THRESHOLD b FRE 3 ONLY ONE DETENT 1 DETECTED gt 4 x 3 00V Ch2 5 00V 4 00 5 500 5 00 S Dec 2001 19 60 16 53 38 Figure 2 Noisy Encoder Detail ENCODER A ENCODER B CHARGE T 6 19 MC 12 MC 12 Balanced Service Manual 3 50 600 2 20ms 2 40ms ENCODER ENCODER B y INE c FAILURE Pn DROPOUT TOO LONG 1 T RUN 5 00 V ch4 5 00 5 Dec 2001 11119 60 17 03 12 Figure 3 Defective Encoder Figure 3 illustrates defective encoder operation Dropout time exceeds 2msec the manufacturer s spec and two RUN cycles are seen during a single detent transition VCO BOARD OVERVIEW The MC 12 VCO board schematic 060 14849 is an isolated Voltage Controlled Oscillator module th
374. ue 107577 fa a AG 2 5 zaz rua BP voc WE Eloy Er zu 7 7 087882 35 EI ans 00 426000 GHONWHD ON uos 007275 007275 Sica 0071 3 0076175 Ki p 00 115000 uos ans 20 UD La e sa 7 Y SNOISIASN 0 4 2 uae T 4 t v 5 9 L 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 14 Lexicon LO ST 1002 21 2 T e v S 9 L 8 ez so amms
375. unit into the extended diagnostics The extended diagnostics can also be entered via the serial debug port by first entering the debug program Typing debug when connected to the serial port accesses the debug program The debug program is case sensitive In addition the extended diagnostics can be entered by sending ed for extended diagnostics to the unit via the serial debug port during the first 10 seconds after powering on the unit Skip Power on Diagnostics ZONE 2 AUX amp RECORD AUX Skip the power up diagnostics and go right to the operating system Immediately after sufficient testing is performed to verify the system can boot the Z180 CPU Z80 SRAM loaded VFD etc after each subsequent test the diagnostics check to see if the ZONE 2 AUX and RECORD AUX front panel buttons are being pressed together If they are the unit will attempt to skip the rest of the power up diagnostic tests and jump to the operating system Branch to Extended Diagnostics RECORD OFF amp ZONE 2 OFF Pressing and holding the RECORD OFF and ZONE 2 OFF front panel buttons after a failure occurs will cause the unit to attempt to jump to the extended diagnostics After a failure occurs the unit will attempt to display on the VFD and the front panel LEDs the failed test number and loop on the failing test If the 2180 CPU and support circuitry is not working the unit will not attempt to read any front panel switches Go to the Next Diag
376. urned 5 positions clockwise After the ENCODER is turned 1 revolution clockwise covering all 24 positions the display will read EXTENDED DIAGNOSTICS Encoder Test CCW 24 The bottom half of the display CCW 24 indicates the counter clockwise test is ready to be executed After the ENCODER is turned 1 revolution counter clockwise covering all positions the display will then read 5 14 Lexicon ENCODER TEST Encoder test passed View Error Log This is not a test but it enables an operator to view the contents of the error log Turning the encoder allows the operator to view the log contents Clear Non Volatile RAM This is not a test but allows the operator to clear out the error log contents and other areas of RAM that are not cleared on a power up When the user selects this menu item the display will show CLEAR NON VOL SRAM Confirm Press MUTE When the MUTE key is pressed the second line will display Initializing RAM then it will display Test Pass Functional Suite The Functional Suite is available from the top level DIAGS MENU when the FUNCTIONAL TESTS item is selected When the operator selects that menu item the VFD will display FUNCTIONAL TESTS START ALL TESTS There is only one menu item in this menu and selecting it will start the sweep through the whole repair Suite As long as there are no errors the test will continue until the tests requiring an operator response are encountered If there is a
377. utputs In this case Input 6 would pass to the Left and Right Front outputs Input 7 would pass to the Center and Mono Subwoofer as well as the Left and Right Subwoofer outputs Input 8 would pass to the Left and Right Side and Rear outputs In this case Record and Zone 2 functionality is not restricted 3 Three separate analog input pairs can be routed to the DSP by using the Record and Zone 2 input muxes and A D converters While this is engaged the Record and Zone 2 paths cannot source analog inputs This allows 5 1 analog inputs to be processed by the MC 12 6 22 Lexicon 4 Three separate digital audio inputs with the same sample rate can be routed to the DSP by using the Record and Zone 2 input muxes and S PDIF receivers While this is engaged the Record and Zone 2 paths cannot source digital audio inputs Error Not a valid link Any of the 8 analog or 13 digital audio inputs can be selected as the source for the Record Audio Path Please refer to the Record amp Zone 2 Audio Paths block diagram below analog source can be passed directly to the analog outputs or be digitized and come out as an S PDIF data stream Likewise a digital Source can be sample rate converted or passed directly to the digital outputs and be routed to a D A converter for the analog outputs In addition a 5 1 Dolby Digital or DTS encoded 5 1 digital source may also be selected and passed through a decoder which will output a 2 channel downmix for the
378. varies with average picure level due to input ac coupling The two sets of record outputs are driven by common output amplifiers through separate series terminating resistor paths The multiplexer internal to U27 allows the record S video luminance to be shut off when a composite source is in use The record monitor outputs are fed to RCA jacks on the Video RCA board via ribbon cable J25 COMPONENT VIDEO SWITCHER Video RCA board schematic sheet 2 Video board schematic sheet 3 6 32 Lexicon Component video switching is performed by high bandwidth relays to maximize signal fidelity and format compatibility There is no active circuitry in the component video path Three sets of component input RCA jacks component inputs 1 2 3 are mounted on the video RCA board and feed a 3 wide two tier tree of DPDT relays The tree selects one of the input sets to be transmitted to the Main Board via 75 ohm coaxial jumpers J19 20 21 One transistor driver is associated with each set of 3 relays Relays are actuated when the associated PSELn bit is asserted high switching from the normally closed to the normally open circuits One set of component input BNC jacks component input 4 is mounted on the Video Board A set of 3 relays RY3 4 7 forms another tier of the relay tree and selects either input 4 or the set fed from the RCA board via J19 20 21 RY6 permits the selected luminance to be routed through the OSD via buffer Q4 The final tier of the tree
379. vase ans 178 5 NOISHSANOO 1 LHOIN E 4 NI 480 0 pen F om aval Y at aste xut wa TUDINSS EO 1 aes M 5 VIVI NIV ymo sevo T Lew 7 aaosr 9808 ro 090000 1 1 ien ip p Yous onaar amA voza zen T Nt bs 05 amahy 18 lt a a s 4 1n00Wd u T E 1820 96cu ARE le 1 gr uoo 4000 60 Y T aaoze n FF SS Erbe 000 wei sea ast oor uma ama z suav ass o avie E 40 0 sezo 8669 NIP ur xean Xoo t 9 0584 Y ASTE tar 6799 xen e TEPO xev 9 Love did 854 5 z 62 2 11675871 i 1 if m E i 1 57627 07927 2 seio octo P xoa E M ne oem D Hn 22 E R ic aasam Y Mo WAS oot 007676 0079276 v
380. w Nt gnd snl snl snl snl snl enl enl eal seal sal ee Geo p sep om I I E 00 109010 COS XP0 9 OL 22 5 ae 3 5 LE SE PE ZEN OHONO 8 89 1 E 5 j 80 0 4 EH 9 4 sore 1907 sop sop 1907 sop uz A o0 LTPOTO EG a TUE put ou WIR Dr 22 757474 107977 NY SNOLIOVdVO SSVdAH Haw coss 55 NOLIATHOSEG SNOTSTARE MC 12 MC 12 Balanced Service Manual Your Notes 8 130 Lexicon 8 131
381. width Signal to Noise Ratio 108dB minimum 111dB typical 22kHz bandwidth Input Sensitivity 200mVrms 2Vrms for maximum output level at 048 input gain Input Impedance 100 in parallel with 150pF Output Level 150mVrms typical GVrms maximum RCA outputs 300mVrms typ 12Vrms maximum XLR outputs MC 12 Balanced only maximum value with full scale input signal and volume at 1248 Output Impedance 1000 in parallel with 150pF RCA outputs 500 in parallel with 150pF XLR outputs MC 12 Balanced only Performance Zone 2 and Record Zone Analog to Digital Conversion 24 bit 44 1 to 96kHz dual bit AX architecture Record Zone only Digital to Analog Conversion 24 bit 44 1 to 192kHz multi bit AX architecture Frequency Response 10Hz to 20kHz 0 1dB 0 25dB 0 75dB at 40kHz reference 1kHz THD Noise Below 0 005 at 1kHz maximum output level Dynamic Range 105dB minimum 108dB typical 22kHz bandwidth Signal to Noise Ratio 1054 minimum 10888 typical 22kHz bandwidth Input Sensitivity 200mVrms AVrms for maximum output level Input Impedance 100 in parallel with 150pF Output Level 200mVrms typical 4Vrms maximum RCA outputs 400mVrms typical 8Vrms maximum XLR outputs Zone 2 only MC 12 Balanced only maximum value with full scale input signal and volume at 048 Output Impedance 1000 in parallel with 150pF RCA outputs 500 in parallel with 150pF XLR outputs Zone 2 only MC 12 Balanced only Video Inputs an
382. wing interface e Host I O data bus Host I O address bus Reset Main audio clocks spare lines to from FPGAs Host I O control RD WR and CS 4 2 clock used on the analog board to derive serial control clocks 3 audio input lines may be 2 channel or octal 3 audio output lines may be 2 channel or octal Lexicon MC 12 MC 12 Balanced Service Manual HOST IO DATA BUFFER DBADATA HOST ADDRESS DBA ADDR BUFFER IO RD RD IO WR WR OPTION BOARD CHIP SELECT 4 MHZ SERIAL CONTROL CLK AUDIO CLOCKS AUDIO DATA IN 3 AUDIO DAUNOUT y RESET SPARE LINES 2 OPTION BOARD INTERFACE OPTION BOARD CONNECTOR DSP Crystal 49326 DSP Audio Decoder schematic page 5 The Crystal DSP is responsible for detecting and decoding all compressed audio data formats Dolby Digital and DTS It is a 2 5 Volt part Its master clock DEC 24MHZ is derived from the audio crystal oscillator To boot the chip the Host processor sets the DEC ABOOT IRQ pin low and sets the DECODER pin high The chip then boots from the external EPROM During run time the host communicates with the Crystal Decoder through a serial control interface that consists of DECODER DATA host serial control data generated the DAR FPGA DECODER DATA OUT Crystal De
383. ystal oscillator that is distributed through a 74LCX14 inverter used as a buffer 30 MHZ 6 12 n A N SHARC SHARC ADDRESS amp DATA SHARC B DSP SF DSP DSP AAA HOST SRAM SDRAM HOST COMMAND STATUS DATA REGISTER REGISTER V L L A N SHARC SHARC ADDRESS amp DATA SHARC D DSP SHARC V C D DSP BLOCK LZ DSP DSP AAA HOST SRAM SDRAM HOST DATA COMMAND XA STATUS DATA REGISTER REGISTER Lexicon Host Communication with the SHARC DSPs schematic pages 2 4 6 11 The lowest byte of the external data bus is also connected to the Host to DSP Command Register a VHC574 and the DSP to Host Status Register an HCT574 There are three modes of communication between the Host and the DSPs The first occurs at boot time When it comes out of reset the or C SHARC asserts DSP 5 and RD These are combined by the Audio FPGA to create This signal goes to the I O FPGA where it is used to generate the WAIT signal DSP WAIT is then returned to the Audio FPGA where it is re clocked by the DSP_30MHZ to synchronize it to the SHARCs It is then sent to the SHARC as DSP ACK where it keeps the SHARC in wait state until the 21
384. zo Torong x667v 266 2 ast xot eu 100 LHOIN 100 LHOIW 220548 wane 42 81 Y s v E 4 4 51 y aast sto ast p 1076271 a 223 1976271 1079277 0 TEAST 15 za s SINAINO TEAST HIGVINVA 0079781 gx Toes 95762 1 00 081100 waa aste 9076276 0078276 av 5975275 6572275 astama uaaa ami SNOISIASH T 4 9 4 8 MC 12 MC 12 Balanced Service Manual Your Notes 8 72 Lexicon 86821 00 v 5 9 L 8 8 Iams 85 699 00 2 8 cans pup 00 2 5

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