BCT-1510 BCT-1520 BCT-1530
Contents
1. 1 2 3 4 TS5 BCT 1510 BCT 1520 3180 POWER ASSY BXF1139 2108 3106 100K b Ska 549 va m 0109 8 we 8 ve 3181 oy x lt oy x lt 100K REK1102 Et14 F115 F116 F117 770109 e e L25AH 250M 1110 5170 0102 F101 SDDF A CT283D3 L 4 5110 3 5 102 ocx WANS 6115 228 9 65 18 F103 e ala 105 1 2 HCS0528 e 104 5 6 UF1922P4 S1NB80 106 118 119 e e os EA 5 1 N F107 130 gt gt 108 eris 557 3 ar 6123 D LI 7125 E BAS216 STP3NB60FP 20107 2 2 3124 3123 47R 1K 20125 5 sage HEATSINK 3 BAV21 5 4 2 2 OSS 809 955 5 DSN 5 E e 4 2 2 5 2146 4 m 330p 2 918 Aye amp TR 2576 m e m Y 142 7163 7140 7 79 1 9 857 BC847B 1088 3163 ET an 6150 3147 7161 8 8 1 it BC847B MES 22K 10 2K2 21 1008 oTa tis N Nw tlc rex lt ot Uo oto AT ATS 552 5551729 3148 2 2 N z eL TCDT1103G Fuse 0109 REK1102 Only this part is supplied as a serv2. VCR SCART TV SCART 17 mile Q4008 Q4007 Q4015 4 222223 2407 Hh 0 0p Been pees 94 04011 04004 04003 04002 04001 1003 01009 1C4001 Q2011 2003 103005 02003 02005 8001 2001 IC3 Q2004 Q2002 Q2011 1 2002 5 PIN JACK o C5 e mm 3 3 N 2211 SHO LU TI N D 1 Sit 141 ju CN8503 Q4009 Q4010 1C4003 1 4002 1C3002 IC3003 1C3007 108001 103001 103006 6 7 m 8 TS5 BCT 1510 BCT 1520 BCT 1530 SIDE A D SUB 25PIN MODULAR D SUB 9PIN IEEE 1284 JACK 232 1 9 A 5 CN6001 13 ERI 105007 4 Wr 7 60 Sm 26002 16007 21 2 CE0 2 976013 06003 B i e e 1 8 umy ejui ST MORE 10 vy 1354 0 2 8001 0209
3. 8 gt D LDOM 7 0946 80 088 3 6 SD UDOM SD CLK 02001 2802411 0 18 CA VCC 8 5 5 02982 2802411 08 18 as gt BANK 8 8 o 008 Q1 lt 5_ gt SD_XRAS SDRAM AC 11 2TMHz 21 2 E amp amp 018 1 164 102003 TALVUS4PW TBB 06 gt 7 7 680 d 17164 lt CAN5 SUBCPU gt D2N TLB XRESET OMEGA gt DTL1038 A T 1 2884 102083 T4LVUG4PV 02004 Of 2078 28 4 77 CLOCKIN pe ADG AD PWM 3 3 gt 8 102803 T4LVU84PV TBB 82038 1 164 res AD3 YCS PURESEIT 8 INKOUT L INKIN 102881 4 alt 8 353 52836 2 E E 1249 MODEM O 6 gt lt CANS MODEM gt 1 DIR 4 2280 a 0288
4. TS5 1510 BCT 1520 K ST20 CPU 1T 2 Kbytes instruction cache and 2 Kbytes data cache 7 4 Kbytes SRAM 2850 audio decoder I F Ny decoder Q 2 PAL NTSC SECAM encoder TE Teletext interface 1530 41 TS5 1510 BCT 1520 BCT 1530 Function 1 5 Signal names are prefixed by not if they are active low otherwise they are active high Pin Number Function VDD 13 Power supply GND 16 Ground 1 3 3 Power supply for clamp diodes VDDAO 1 2 Analog power supply for PAL NTSC SECAM encoder VSSAO0 1 2 Analog ground for PAL NTSC SECAM encoder RTCVDD 1 Real time clock supply VDD VPLL 1 Analog power supply for video PLL VSS VPLL 1 Analog ground for video PLL 1 The VClamp pins are a power supply bus used to diode clamp the voltage on 5V tolerant digital input or output pins to The voltage on the digital signal pin is then clamped to within Vimax 5 5V if the applied voltage is increased above 5V If the device is to be interfaced to 3 3V logic signals only then the VClamp pins can be connected to the 5115512 3 3 VDD power supply However if any pin is to be interfaced to a 5V logic signal t
5. 2 a 8 5 3 21121121 123 4 4 5 ti S 515 d 5 S 8 8 5 E 5 lt _ gt RESET _ Low LNB OFF CExt ernal LNB_POWO ds LNB ON Internal Low LNB VC13V LNB POW High LNB HC18V n OFF_D 3 3V d 100 x esoosioy eav Bay igsasnap 019 5 24 o 9 22 3 95 J EF 95 AWH 582 48 8100 100 sav 014 3294 998014 ines 55 8
6. LNB POWERCRF IN Regulator RB501V 40 TRB 101801 NJM317DL1 TLB n 21906 AW DTC124EUA TLI 01011 rtr 01091 8381 188 XLNB POWOCXLNB OFF ON uL t B avori CANS SUBCPU 2SA15T6A COR TLB 01002 81887 Di LNB Through 28160 40 LNB 13 18 ov Ico La 5 5 DTCT24EUA TLB e 01807 1004 afe JES 515 2 01085 DTCI24EUA TLB CANS SUBCPUS n Lue 9 TIT gt 3 E 8 TS5 BCT 1510 BCT 1520 BCT 1530 DMUXCPU INT mm gt INT CHDEC I2C DA 126 SCL 5 1965 4 n OFF_D 3 3V 2 2 5 5 5 QS SIS 51 lays 7 zi lt HZ CANS DMUXCPU gt 18 11 Epa FA EA EA n 5 888588 288888 88584 AS 828 52858 PDOSYNC PDOVAL 1004 TS5 BCT 1510 BCT 1520 TDA8083H BCT 1530 TDA8083H E Domodulator and Decoder R1028 Dummy RAB4C828J T 002 sa 5
7. 6005 73K324BL IH MAIN 55 6 7 3NOL E uo1vinaowsa ae anya 100910 SSvd lt gt HOSS32OHd OS Lig avno gt 68 GIN AH 20 10 LWXL HOlVIndOW H3dvHS 3sind mvo gt O HOLWINGOW EE HOLVH3N39 3NOL ONITIVO H3MSNV INLA 5 5 5 5 m 40 04 9333308 5 snd du 118 8 53 TS5 1510 BCT 1520 BCT 1530 Function 1 3 POWER NAME PIN TYPE DESCRIPTION GND 1 System ground VDD 16 Power supply input 5 V 10 73K324BL Bypass with 0 1 and 22 uF capacitors to GND VREF 31 An internally generated reference voltage Bypass with 0 1 uF capacitor to ground ISET 28 Chip current reference Sets bias current for op amps The chip cu
8. 11 0 821 90 2 5 8 T 8 9 9 9 Q i Pi H 5 5 M3HLON M3HLON W3H10N 3 5 BL 1 v SEOIXIP 15 2 sva ESYA 15085821 JXOVIONFSZIOVIVOPBZI 1 2 9 g E x 8 90 5 5 5 1 8 8 2 o a 21 eia W3WLON W3WLON 10 27 TUNFEZT 1 5 38 lt 59 502 GIMOQYW3M ZVIVOH3H 12A GVLVGW3H SIVIVOH3H 02A 91019 34 040104 199785582 En 9 0 9 9 e Z Z amp 555 55 10 821 10821 193135 7 5 a peer SEDEM ep Mine p q301nvx EJ g 3513 3 8 S 5 IINIX 3 UId 3 8300 6300 OLAOOYHJH 2400 LVLYOH3MH F1 VLYOH3H 81 1 L2VLYOH3H PZVLYOH2H L2VLVOW3H GEVLYOW3M 609074 OLNI NT as V UU 9 e e ison 58 8589 pe THR LAQOVW3N 1 S AGOVHAW 8 SVLVOHSH 2 S VLYOW3M GLYLVOH3H
9. SZVlvOH3W SZVLYOM3H it VLVOH3H 126014 EINI 8 8 9 6 9 9 9 9 9 9 e 310959 t 2 5 88 0301 e 8 d 3 8 8 5 5 gt E a 5 LO xx ro HA EN 5 Eq N ym qum qum 5 7 Us m r gt 5 55 s p z 555 en Lt 4 12 d 488 7 gt 5 5 ET 5 5 5 gt 1 E 44 444444444444 444448 Dm ES 52 15 lt x J 99998 2 gt ooo 1 T ape CO 82 249 gis 2 Bis FE 584 lt E rm OOOO 3 Lmmm LO lt lt m m 7 8 TS5 1510 BCT 1520 BCT 1530 Boot Boot Boot 8 16bitROM 4 JOFF_D 3 3V 7 Speed 4 Speed Speed E 8 1 1 49 875 Be 8 5 12862 CAN5 MEMORY PP 1206 A SDRAM D B 15 icd Y nu re 3 1860 11 THS_In TCK_In 5 1 TDI 100 Men req z Men red 2132 not TRST_In IXRESET_OMEGA 5 IOFF D 3 3V n TESTPORT 8 9 788 TBB
10. 1510 BCT 1520 BCT 1530 T 04881 UNZ12N TLB UMZI2N TLB 1 A 5V ASV 4 cus 9 TV QUT ols 4 Sp FAST SW QUT 9 5 WR OUT 04813 ASV POZ12B TRB enl 6 QUT SLOW SW OUT 8 Su oy B 7 7 MES 4 TV Lch amp bs Lch OUT R4074 TV IN 28 Rch OUT 04885 a 8 UMZ12N TLB 1 160 04884 BKNIBIS tA wate CN4002 2 m TV Rch OUT Rae 688 17164 04882 DTCI23TKA TLB 2 8 Lch our 82888 d R VCR CVBS Y OUT 04811 7 JA 5V lo 04901 PDZ12B TRB OUT DTCI23TKA TLB 5 fl 5 04914 TIT L n 04812 P UMZI2N TLB PDZ12B TRB lo VCR SLOW SW 1 VCR Lch IN VCR Lch QUT OUT NCR Reh IN VCR Reh QUT 04018 688 UMZI2N TLB 04089 t4 UMZI2N TLB 7 7 04884 DTCI23TKA TLB ver Leh our _ 4952 688 17154 04003 DTC123TKA TLB RCA our 04036 10 58 4010 DTC123TKA TLB R4008 1 164 1699 84811 17164 1600p 1088p Analog A
11. 1B 1 7 717 MAIN ASSY TS5 BWE1103 1510 BWE1115 BCT 1520 BWE1115 BCT 1530 BWE1110 CHDEC BLOCK B1E1103 DMXCPU BLOCK B2E1103 MEMORY BLOCK 1103 ANALOG AV BLOCK 4 1103 IO BLOCK 5 1103 MODEM BLOCK B6E1103 SUBPOWER BLOCK B7E1103 CN2003 CNT802 96045 12 FFC CABLE BDD1022 J2 96045 12 E 5 CARD ASSY m 288 8 85 1080 22 25238282 0 8 8 00 1 OQ OG O 6 6G O00 2000009200 CN8502 S x CN8501 1141 1142 E Ege CA CARD SLOT BANK CARD SLOT 8 1 m 2 3 96048 21 CN8901 52044 2145 PERSO VALIDER 58003 S8006 LEFT UP 8002 S8001 RIGHT 8004 D8001 BEL1037 OQ O O O 58005 DOWN TSEGME 5 6 7 8 m TS5 BCT 1510 BCT 1520 Note When ordering service parts be sure to refer to EXPLODED VIEWS and PARTS LIST or PCB PARTS LIST 9 MODULAR JACK x AC230V 9 CN5004 CN6001 fv 4 s BKP1122 BKP1137 0102 x 2 31211 PES NN A 102 Bess T2 5A 250V LIVE BKP1098 CN4501 NEUTRAL 1110 PULSE T6001 TRANSFORMER 1
12. Function 5 5 The teletext clock and data inputs are shared PIO pins as shown in Table 15 High speed data port pins have a dual function and can be used either to interface to an external IEEE 1394 link layer controller or provide an IEEE 1284 parallel port interface Pin In Out Function 1284Data0 7 AVData0 7 in out IEEE 1284 port data or AV data 1284notSelectIn in IEEE 1284 port control signals or AV signals 1284notlnit AVPacketTag3 in 1284notFault AVPacketTag2 out 1284notAutoFd AVPacketTag1 in 1284Select AVPacketTagO out 1284PError AVByteClkValid out in out 1284Busy AVPacketClk out in out 1284notAck AVByteClk out 1284notStrobe AVPacketError in Table 13 High speed data port pins Pin In Out Function TDI in Test data input TDO out Test data output TMS in Test mode select TCK in Test clock notTRST in Test logic reset PIO pins and alternative functions Table 14 TAP pins To improve flexibility and to allow the STi5512 to fit into different set top box application architectures the input and output signals from some of the peripherals are not directly connected to the pins of the device Instead they are assigned to the alternative function inputs and outputs of a PIO port bit This scheme allows these pins to be configured as general purpose PIO if the associated peripheral input or output is not required in that particular app
13. 9008S 50085 lt 7008 21 f 20085 1427 gt 20085 EE 10085 S3HOLIMS 0031 20031 21037 21037 0031 00011 gt gt gt 2 1 610198 8 gt 50085 E E ge 2 baam 82 1 V 1019SV 19085 81111 01037 21037 11131 57037 2011 ASSY LNOHJ lt m 24 TS5 1510 BCT 1520 BCT 1530 3 10 CARD ASSY 00cN9 2 140 8 0 9 E 39 9 13538 4 29726 VO OYI ANVA 2 AT ANVE k 13534 873 299A 3NV8 8 0S8NJ 3421 9096 1 1801 3 40884 nr 1 081 1 4308 8 108813 Zk 1058 9 4 1 1879 18082 lo 6660 9 4 19 11439 20S8NJ ASSY E
14. LEAKAGE CURRENT CHECK Measure leakage current to a known earth ground water 2 PRODUCT SAF ETY NOTICE pipe conduit etc by connecting a leakage current tester such as Simpson Model 229 2 or equivalent between the earth ground and all exposed metal parts of the appliance input output terminals screwheads metal overlays control shaft etc Plug the AC line cord of the appliance directly into a 120V AC 60Hz outlet and turn the AC power switch on Any current measured must not exceed 0 5 Many electrical and mechanical parts in the appliance have special safety related characteristics These are often not evident from visual inspection nor the protection afforded by them necessarily can be obtained by using replacement components rated for voltage wattage etc Replacement parts which have these special safety characteristics are identified in this Service Manual Electrical components having such features are identified by marking with a on the schematics and on the parts list Reading should in this Service Manual The use of a substitute replacement component which does not have the same safety characteristics as the PIONEER recommended replacement one shown in the parts list in Test all this Service Manual may create shock fire or other hazards exposed metal Product Safety is continuously under review and new surfaces instructions are issued from time to time For the latest information always consult th
15. Output ALE signal to AFE Goes active high to latch an address into the AFE VCC2 Power Auxiliary power supply pin 7 gt 00 Multiplex Address Data bus connections to AFE Power Main power supply pin 58 TS5 1510 1520 PE5181A MAIN ASSY 7 7 1 7001 Sub CPU ePin Function Pin Name LED10 Active Pin Function Front LED seg BCT 1530 LED11 Front LED seg LED12 Front LED seg LED13 Front LED seg LED14 Front LED seg LED15 Front LED seg LED16 Front LED seg LED17 Front LED seg IRQ_TEIDEN Power failure interruption L output only at power failure IRQ_KEY Remote controller key interruption 2 SDA 2 SDA Output 120 SCL 01010 120 SCL Input x x x x x SUB MUTE Power off Mute TEST For production line RC MM RC MM Selection Disabel L Enable pioneer philips Remote control code selection Philips Pioneer XHALT Power failure process completion flag L Complete H Normaly x For AGC Reading 02 MENU Front key input 01 OK Front key input KEYOO Front key input REM Remote control input AC CLK Power failuer detection clock Both edge detectin LNB POWO LN
16. VA6002 2322 59 51516 COILS AND FILTERS 6003 BTF1087 L1001 L4001 BTH1065 T6001 BTX1035 L2005 BTX1036 L2002 L2004 DTL1038 CAPACITORS A C6016 470pF AC250V BCG1026 C7001 0 047F 5 5V BCH1072 4022 4023 5 101 50 4028 4029 CCSRCH181J50 7002 7003 CCSRCH220J50 2005 2008 2013 02014 2018 CCSRCH221J50 1010 1011 2010 2011 2019 5 330 50 6006 6007 CCSRCH390J50 1009 4031 6011 6013 100 50 7004 7019 101 10 C5001 CEAK101M25 C7018 CEAK221M10 C4053 CEAK221M25 1008 1012 470 16 7014 471 10 4036 4037 100 50 C4051 CEAT100M50 C4010 CEAT470M16 C7021 CEAT470M50 C4062 CEAT4R7M50 4039 4040 4042 4043 CKSQYB684K10 C4060 C4061 CKSQYB684K10 2034 2058 4001 4008 CKSRYB102K50 4016 4017 6002 CKSRYB102K50 1002 1006 1007 1013 1014 CKSRYB103K50 TS5 BCT 1510 BCT 1520 No Description BCT 1530 Part No 1016 2031 2033 2035 2037 CKSRYB103K50 2060 4011 4024 4025 1019 1024 1026 4038 4041 4044 4049 1032 6008 1001 6012 2059 2061 7007 7008 7016 7017 1017 1018 1020 1023 1027 1031 2003 2015 2032 2038 2050 3001 3005 C3007 C3009 C4018 C4021 C4030 C4050 C4052 C4056 C4059 5031 5035 6001 6003 6005 7005 7006 7009 7011 7013 7015 7020 7022 2063 2065 1004 1005
17. 18W typ Dimensions 380 W X 253 D X 71 Net Weight mese 2 3kg TS5 BCT 1510 BCT 1520 BCT 1530 61
18. 4 XWE DIGCBANK1 1XWE LDQM SDRAMCBANKO 4 XWECBANK2 3 1 XBEO 1 2 EA TS5 BCT 1510 BCT 1520 BCT 1530 3 5 MAIN ASSY 4 7 55 1 103 1510 BWE1115 14 7 main assy 47 1520 1115 ANALOG AV BLOCK 1530 BWE1110 MUTE n MUTE 54 CANS SUBCPU SUB MUTEL 50 1 168 POWER MUTE DTATASEUA TLB 04815 lt CANS_DMUXCPU gt Video 8 5 27 04044 2 1 04945 E 8 1718 04846 5 T _ 4048 0 1715 o CVBS 9 1716 vB 04049 C4047 0 1715 8 1716 200 R4025 17164 288 17164 R4021 200 17168 84026 4020 104881 CXA2161R AV Switch 02 2 yr n 41718 R4933 lt CAN5 DMUXCPU gt Lch Audio 8 4 gt 8 68718 YB 5 4003 E NJM4558MD TLB 84841 1 16 lt CANS SUBCPU gt page OFF D 5V HW 180p 17164 5 04661 vis 8 68718 T 104883 SASS NUM4558MD TLB yi 1 24063 R4035 i 7 8 TS5
19. 7 33 a a 4 E gt 5810 8 Andras 5 4 eo D lem 334 E CV1VONISI 1 1 151 OVIVGNISL 1144 551 us IJA 7 4 4 281 mE Ever V VIVENISL uo PA LLI LLI 4554 Y vivos TI 2 xvn 1 1004 3IABNISI NISL 40000 1913 9 4 181 SVLVQNISL AN ONASHIS1L ONASHION 8 9 5 wow gus e 0193135 0 1 60 236014 158109 158190 W3HLON 43348 UU x 280 1123135 Eo o NDOQ241 pe 9 a 101 009 x ANOS 8104105 00 5 sil 159009 zu b 99 D Su gt 5 6 E 18811098 W3HLON 20Nd io 0158 18171 a 259 G E xus 110821 m 882 ii 5 _W3HLON HYMOSION T 2 E xm E 952 WVIVORBZI idRY TUA E 3 9 1 E 8 a 50 8 W3HLON H3MION H3HION 8 ISYA 85 0059 esva S
20. BHA1147 Not used BXD1010 BRC1026 Not used Not used Not used Not used BDH1027 Not used BRM1034 BDH1014 Not used BCT 1510 INYXK SP BHD1375 Not used Not used BHA1146 BHA1147 Not used BXD1016 Not used BRC1004 Not used Not used Not used BDH1018 Not used BRM1035 BDH1015 BKP1124 BCT 1520 INYXK IT BHD1480 Not used Not used BHA1146 BHA1147 Not used BXD1018 Not used Not used BRC1027 Not used Not used BDH1018 Not used BRM1036 BDH1016 Not used BCT 1530 NYWXKPL BHD1442 Not used Not used BHA1146 BHA1147 Not used BXD1037 Not used Not used Not used BRC1011 BRC1012 BDH1018 Not used Not used BDH1015 BKP1130 TS5 1510 BCT 1520 BCT 1530 1 EXTERIOR SECTION PARTS LIST Mark No Description Part No 1 MAIN ASSY FRANCE See Contrast Table 2 2 FRONT ASSY BWE1102 3 CARD ASSY BWE1080 4 55 1139 5 Fuse 0109 T2 5AH250V 1102 6 Front Panel Assy See Contrast Table 2 7 Plastic Base BMA1002 8 Chassis BNA1151 9 PCB Support AEC1215 10 21 FFC J1 BDD1042 11 12P FFC J2 BDD1022 12 Rear Panel Assy See Contrast Table 2 NSP 13 Name Label See Contrast Table 2 14 Washer Faced Nut BBN1005 15 Joint BMR1133 16 Hexagon Headed screw BBA1059 17 Barrier BEC1231 18 Bonnet Case See Contrast Table 2 19 Screw BBZ30P080FZK 20 Heat Sink BNH1049 21 Serial No Label See Contrast Table 2 2 CONTRAST TABLE TS5 NYXK
21. Internal pull up Country Selection bit 1 Internal pull up Country Selection bit 2 Internal pull up Country Selection bit 3 Internal pull up Reset signal to the AMC2442A Controller Active High TXD Input DTE Transmit Data Pin All data communication from the DTE connects via this pin RXD Output DTE Receive Data Pin All data communication to the DTE connects via this pin RXC Input Receiver Clock Input from AFE Used in PSK QAM and synchronous data mode TXC Input Transmitter Clock Input from AFE Used in PSK QAM and synchronous data mode Output DTE Clear To Send output signal Used for hardware flow control Output Write signal to AFE Goes active low whenever the SMC wishes to write to the AFE RD Output Read signal to AFE Goes active low whenever the SMC wishes to read from the AFE Output Buffered Clock output signal Also used as a crystal drive signal when required Speaker Enable drive DO NOT CONNECT DO NOT CONNECT DAA Line Seize relay control Used if DPCO relay is used to share the telephone with a standard telephone instrument DAA Bell Shunt control Used during LD dialling to provide a low impedance loop SENSE Input Line In Use detection input CHECK Output Line In Use circuit drive pin HOOK Output DAA Hook switch control Delayed from Seize to allow for a low cost opto coupler
22. Moduration Method 5 Symbol Rate 22 27 27 5Mbaud Inner Code Rate 1 2 2 8 3 4 5 6 Error Correction ViterbitReed solomon Frequency Range 950 to 2150MHz Input Level 65 to 25dBm Input Level sssrinin 056 8 04 Spurious Signal and Local Oscillator Level max LNB Power Supply Ver 12 5V to 14V Hor 17V to 19V VIDEO N 55 min Responce Flatness 2 2 5dB at 4 7MHz Differential 10 Differential Phase 5deg max Chroma Delay 40 Non Linearity 2 5 AUDIO S N 72dB min Responce flatness 0 5 at 20 to 20kHz Channel Separation 50dB min DATA COMMUNICATION Serial Interface 2 5 232 Parallel Interface 1284 MOJEM Em V23 IG Card 150 7816 GENERAL Power Requirement AC230V 50Hz Power Consumption
23. Pin In Out Function LPClockin in Low power input clock LPClockOsc in out Low power clock oscillator AUX_CLK_OUT out Auxiliary clock for general use Table 8 Low power controller and real time clock pins 1 The low power clock pins are not 5V tolerant Pin In Out Function PIOO 0 7 in out Parallel input output pin or alternative function see Table 15 PIO1 0 7 in out Parallel input output pin or alternative function see Table 15 PIO2 0 7 in out Parallel input output pin or alternative function see Table 15 PIOS 0 7 in out Parallel input output pin or alternative function see Table 15 4 0 7 in out Parallel input output pin or alternative function see Table 15 Table 9 PIO pins Pin In Out Function Serial data input channel LinkOut out Serial data output channel Table 10 OS Link pins Pin In Out Function TSInByteCIk in Link IC byte clock TSInByteClkValid in Link IC byte clock valid edge TSInData0 7 in Link IC data TSInError in Link IC packet error TSInPacketClk in Link IC packet strobe Table 11 Transport stream input pins Pin In Out Function TtxtEvennotOdd in Teletext even not odd vertical sync signal TtxtHsync in The HSYNC signal input when the teletext interface is operating in the input mode Table 12 Teletext interface 45 TS5 1510 BCT 1520 BCT 1530
24. yourselfer Qualified technicians have the necessary test equipment and tools and have been trained to properly and safely repair complex products such as those covered by this manual Improperly performed repairs can adversely affect the safety and reliability of the product and may void the warranty If you are not qualified to perform the repair of this product properly and safely you should not risk trying to do so and refer the repair to a qualified service technician WARNING This product contains lead in solder and certain electrical parts contain chemicals which are known to the state of California to cause cancer birth defects or other reproductive harm Health amp Safety Code Section 25249 6 Proposition 65 NOTICE FOR CANADIAN MODEL ONLY Fuse symbols fast operating fuse and or slow operating fuse on PCB indicate that replacement parts must be of identical designation REMARQUE POUR MODELE CANADIEN SEULEMENT Les symboles de fusible fusible de type rapide et ou fusible de type lent sur indiquent que les pi ces de remplacement doivent avoir la m me d signation FOR USA MODEL ONLY 1 SAFETY PRECAUTIONS ANY MEASUREMENTS NOT WITHIN THE LIMITS OUTLINED ABOVE ARE INDICATIVE OF A POTENTIAL SHOCK HAZARD AND MUST BE CORRECTED BEFORE RETURNING THE APPLIANCE TO THE CUSTOMER The following check should be performed for the continued protection of the customer and service technician
25. 07440 350 _ _ Sag sd 2 j 7 Ta e ep 000 w e 5 9 Z ej alge 3 18407440 ut 0591 1998 0691 1998 0191 1989 lt 928213331 1241 6 0025254 uy 2018 Ole assy 6 TS5 1510 1520 1530 1 2 m 3 TS5 BCT 1510 BCT 1520 BCT 1530 3 7 MAIN ASSY 6 7 16 7 main assy 6 7 MODEM BLOCK OFF D 5V n TS5 1 103 1510 BWE1115 E BCT 1520 BWE1115 35 1530 BWE1110 E lt gt MODEM 0 6 n OFF D45V RESET DTA124EUA TLB 6 01 5022 060 47k 1 168 1006 55 AMC2442ACV 0 87 BCT 1510 BCT 1520 BCT 1530 AMC2442ACV 0 84 CANS SUBCPU abdis X6001 RESET CHDEC DTC144TUA TLB BSS1099 A T Sia 8 8 88 8 8 97 8 8 Sie 1035 881 aT 88 5 m 2 6 7 5 6 7 m 8 155 BCT 1510 1520 1530 gt A 5 13 32481
26. 1 105005 lt 13 8 14 t OFF D 5V 265 1 164 SECONDARY a ere oro PRIMARY 2 C6811 IE 19750 6085 1001 06002 9 01760 E 1ZB60 4072 TLB Modular Jack F6003 F 06001 A gs 87 OO m z 1762 gt A 5 4 m i x 8 AW 28 ales Bm 5 2 5289 E 872 1087 4 4 4 2 VAG002 1 2322 594 51516 PKX1001 A T 1 1 1 1 1 1 1 1 1 1 T 1 8816 418 1826 ES 1 um TS5 BCT 1510 BCT 1520 BCT 1530 3 8 MAIN ASSY 7 7 CN7001 1128 6020 2 3 4 07084 SM 5V 7 7 man assy 7 7 i e SUBPOWER BLOCK TS5 BWE11 03 155355 1510 BWE1115 alaa zl BCT 1520 BWE1115 E BCT 1530 BWE1110 EE EEPROM s Sexe Test Program D Hi Xi OFF_D 3 3V 4 lm gt TFGE2OI TES or psv rana 284081 8 2 we T A z MUTE 45V Nar TO Power Assu Sis 4 XLNB POV8 lt H in CANS
27. 1520 1530 2 3 1 um TS5 BCT 1510 BCT 1520 BWE1103 BWE1115 BWE1115 BWE1110 23906 M 1 168 K3026 Flash Memory 8M Boot Data LDQM_SDRAM BANKO 4 XWE BANK2 3 23007 17160 CK3903 XCS BANK3 OFF_D 3 3V n XCS BANK2 163006 TCTSZ126FU TLB R3025 1 Flash Memory 16M OFF 0 3 3V OFF_0 3 3V R3028 AW 10K 1 164 Application a gt H n m lt OF F_D 3 3V 83043 K3p45 ng vss 163005 HYB39S16 160CT 8 TBB CAN5 DMUXCPU SDRAM_D O 15 In lt CANS_DMUXCPU gt SDRAM A 0 11 SD UDOM SD_CLK SD_XRAS SD XCAS SD_XWE SD_LDOM 0 3 SDRAM 16M 3903 103803 NT56V1616A0T 8 TBB OFF D 3 3V 7 8 TS5 1510 BCT 1520 BCT 1530 lt CANS_DMUXCPU gt 1 21 UDOM_SDRAM BANKO XE CLK SORAMCBANKO n 1 XCAS1 27 XCS L SDRAMCBANKO SCANS OMUXCPUS XSDRAMCSO XRAS_SDRAM BANKO XRASO XCAS SDRAMCBANKO 1 0 XWE SDRAMCBANKO
28. 2 digital l input bit 2 ADC bypass 2 I3 digital l input bit ADC bypass 3 Vssp1 digital ground 1 core and input periphery 4 TPLL test normally connected to ground 5 Vssp2 digital ground 2 core and input periphery 6 l4 digital l input bit 4 ADC bypass 7 15 digital l input bit 5 ADC bypass 8 16 digital l input bit 6 ADC bypass MSB 9 QO digital Q input bit 0 ADC bypass LSB 10 digital supply voltage1 core and input periphery 11 Q1 digital Q input bit 1 ADC bypass 12 Q2 digital Q input bit 2 ADC bypass 13 Q3 digital Q input bit 3 ADC bypass 14 Q4 digital Q input bit 4 ADC bypass 15 Vssp3 digital ground 3 core and input periphery 16 Q5 digital Q input bit 5 ADC bypass 17 Q6 digital Q input bit 6 ADC bypass MSB 18 Vssp4 digital ground 4 output periphery 19 Vppp2 digital supply voltage 2 core and input periphery 20 PRESET set device into default mode 21 quasi bidirectional I O port bit 3 22 P2 quasi bidirectional I O port bit 2 23 P1 quasi bidirectional I O port bit 1 24 PO quasi bidirectional I O port bit 0 25 Vppp3 digital supply voltage 3 output periphery 26 P5 quasi bidirectional I O port bit 5 27 P4 quasi bidirectional I O port bit 4 28 PDOCLK output clock for transport stream bytes 29 PDOO parallel data output bit 0 Serial data output 30 PDO1 parallel data output bit 1 31 PDO2 paral
29. Description Part No 55 SEMICONDUCTORS D8001 BEL1037 SWITCHES AND RELAYS 58001 58006 507013 RESISTORS R8001 27 0 1 4 BCN1056 OTHERS 8001 1026 CN8001 21P FFC Connector 9607S 21F CARD ASSY CAPACITORS C8501 C8504 CKCYF103Z50 RESISTORS R8502 1000 1 4 BCN1057 OTHERS CN8503 12 Connector 9604S 12F CN8502 8Pin CARD Connector BKP1141 7 CN8501 16Pin CARD Connector BKP1142 POWER ASSY This ASSY has no service part as a assy part Only the fuse 0109 REK 1102 is the service part as a set part Refer to page 7 6 ADJUSTMENT There is no information to be shown in this chapter 36 1530 The information shown in the list is basic information and may not corre TS5 BCT 1510 BCT 1520 GENERAL INFORMATION 7 1 e List of IC TDA8083H 7 spond exactly to that shown in the schematic diagrams 73K324BL IH CS4335 KS CXA2161R STI5512MWD 5181 TDA8083H MAIN 55 1 7 2442 0 87 1 1004 Demodulator and Decoder eBlock Diagram l3S3Hd gt THLOSIG 18 8 ANOL 19534 NO H3MOd 4001 3SYHd 4340044 L1 IOH LNOO OLG 5 IVHu3N39 Y uudoadd 100
30. ep 3 3V SB340 202 olr gt e t e o 5 24V 19V E F233 8 8Va 5 6V 28V Coton oLa 8 545 548 0207 _ 2227170 NCE CDT1103G F223 2275 3275 r n1 33 10 245 7275 2246 43117 2 2 2 27 5 6 r3 7 r3 8 1 m TS5 BCT 1510 BCT 1520 BCT 1530 4 PCB CONNECTION DIAGRAM 4 1 FRONT ASSY NOTE FOR PCB DIAGRAMS 1 Part numbers in PCB diagrams match those in the schematic diagrams 2 A comparison between the main parts of PCB and schematic diagrams is shown below Symbol n PCB ELT n Schematic Transistor with resistor Field effect transistor 3 terminal regulator 3 The parts mounted on this PCB include all necessary parts for Several destinations For further information for respective destinations be sure to check with the schematic diagram 4 View point of PCB diagrams Connector Capacitor P C Board Chip Part SIDE 3 FRONT ASSY SIDE A 7002 BNP1353 B 1530 4 2 CARD ASSY CARD ASSY SE 1 R aE U 5 UO U SS SES EY 2003 3 4 H TS5 BCT 1510 BCT 1520 1 um TS5 BCT 1510 BCT 1520 BCT 1530 4 3 MAIN ASSY MAIN assy TUNER MODULE I Q1001 Q1011 Q1008 1004 01006 01003 01004 01007 01002 1C1001 1 m 2
31. 0 Pin Pin m Symbol Voltage Equivalent Circuit Description Num V VCC 50 VIN 1 6 7 VIN_2 2 4 i 190 RGB signal inputs 6 VIN 4 80 24 VOC RGB signal input 51 VIN 3 130 OR 2 35 CVBS signal input 24 RGB signal inputs 52 VIN 5 20k 5 VIN7 150 OF 3 0 Chrominance signal inputs VCC 53 VIN 6 30 20 hromi VIN 13 150 Chrominance signal inputs 54 VIN 8 55 VIN 9 4 VIN 10 2 35 CVBS Luminance signal inputs 3 VIN 11 56 VIN 12 47 VOUT 1 s 46 2 48 45 VOUT 3 0 4 32 RGB CVBS signal outputs 43 VOUT 4 277 39 VOUT 6 VCC 41 VOUT 5 0 4 12k 41 Chrominance signal output 49 55 1510 1520 1530 Function 2 3 50 Symbol Voltage Equivalent Circuit Description Num V VCC Typically 38 VOUT 7 0 4 88 RF modulator signal output 12k Minimum load 20k resistive VCC VCC 40 8k eo Internal reference bias for video circuits 49 VID_BIAS 0 9 150 A capacitor is connected from this pin to 18 3k GND Typically 100nF VCC 2k 37 TRAP 2 3 200 Connects trap circuit for subcarrier VCC Sync detect circuit time constant 2 SYNC ID 2 5 150 resistor and capacitor connection pin 22 LIN 1 23 RIN 1 6 0 19 LIN 2 Single 20 RIN 2 Audio signal inputs 16 LIN 3 17 RIN 3 29 LIN 4 0 0 42 RIN 4 Dual 2
32. 035 PRIMARY 513 5 CONVERTER HOUSING Assy TRANSFORMER GND 5170 GND 5 5 A 7180 GND 3 3 3 3V 3 3 5VReturn 5V 5 5 GND amp 5 55 8 5v 1139 1 19 e 12 e ev 9 3555885588 28 0209 FFC CABLE BDD1042 J1 FRONT ASSY BWE1102 RIGHT D8001 M8001 58004 BEL1037 BXX1026 88 88 jo TSEGMENT LED IR SENSOR 1 2 3 4 55 1510 1520 1530 M1001 1135 3 2 MAIN ASSY 1 7 4 E De wr __ DBS Front End 9 E a 5 DTC124EUA TLB R1 R2 22kohn SENE Tat TT equator az iF 18 355 TRB 7 5 ID m Bis D 6V 001 CAN5 SUBCPU XSTBY gi pie LOW Standby BL E 8 m SET ees R1016 1 7 assy 1 7 CHDEC BLOCK M NM TS5 BWE1103 ETE BCT 1510 BWE1115 TN BCT 1520 BWE1115 BCT 1530 BWE1110 T AGC E 5502 TERE 11 IVDDD1 il gr
33. 06007 06006 6002 6003 06002 6001 06005 6006 7002 07010 6004 6001 1 6007 105006 106005 96003 1 7001 1 7003 07001 97003 07002 07005 07004 97013 07016 07014 07011 07012 1 m 2 E 3 E 4 55 1510 1520 1530 FY MAIN assy 0 5 22 7 7 8 TS5 BCT 1510 1520 BCT 1530 BNP1354 D TS5 1510 BCT 1520 BCT 1530 5 PCB PARTS LIST NOTES 9 Parts marked by NSP are generally unavailable because they are not in our Master Spare Parts List 9 The mark found on some component parts indicates the importance of the safety factor of the part Therefore when replacing be sure to use parts of identical designatio
34. 2017 RESISTORS R5020 R5021 6800 1 2W R6017 820 1 2W R6018 470 1 2W 2146 7001 7013 R2022 R2054 R7015 R7016 R7002 R2001 R2017 1011 1013 1033 R2024 R2025 R7024 R7025 R7029 R7042 R2018 R7026 R7027 R1010 1012 R4020 R4022 R4025 R4026 R2079 R2081 R1005 R1006 Other Resistors OTHERS M1001 CN2003 12 FFC Connector CN7002 21P FFC Connector DBS Front End JA4001 2P Pin Jack CN4002 SCART Connector CN7001 19 Plug CN5004 DSUB Connector CN5005 DSUB 25P Connector CN6001 4 Modular Jack Ground Plate X1001 2002 X7002 32 768kHz X7001 X6001 KN6003 KN6006 Jumper Terminal CKSRYB103K50 CKSRYB104K16 CKSRYB104K16 CKSRYB153K50 CKSRYB273K16 CKSRYB332K50 CKSRYB333K25 CKSRYB471K50 CKSRYB473K16 CKSRYF104Z16 CKSRYF104Z16 CKSRYF104Z16 CKSRYF104Z16 CKSRYF104Z16 CKSRYF104Z16 CKSRYF104Z16 CKSRYF104Z16 CKSRYF224Z16 CKSRYF474Z16 BCN1046 1060 1063 RAB4C102J RAB4C103J 181 RAB4C333J RD1 2VM3R3J 851 105331 RS1 10S3601F 851 105471 RS1 10S681J RS1 10S750J RS1 10S821J RS1 16S1200F RS1 16S1202F RS1 16S2000F RS1 16S9101F RS1 281R8J RS1 16S J BXF1135 96045 12 96045 21 1017 1019 1120 1122 1123 1137 1081 551056 551061 551091 551097 551099 1001 35 TS5 1510 1520 1530
35. 4 01 86 0OQdse ve Le 06 62 ONASOQd 08 gv 8c 4 VITERBI DECODER REED SOLOMON DECODER DEINTERLEAVER gt ENERGY DISPERSAL REMOVAL A A gt WOLV LOY ASVHd 4001 24 AH3AOO3H 95199 9 509 1004 eenbs uomnejodieju NOLLVZINOHHONAS SJojoejeq 901 pue 080 4 95V 2019 HOLY LOY 3SVHd 11791 vk 90 9100 95v 3Suvoo L 2L LL 6 1004 ejenbs uonejodieju 808VQ L 1531 NVOS 29 69 59 V1Vd HOLIMS YANNL 221 1898 04 YZ 0 2 v9 8 4 9 c 100166 5 7 SIL MOL OGL v Od 01 Sd 1195 lvds 10S Yds 910101 TS5 1510 BCT 1520 BCT 1530 ePin Function 1 3 PIN SYMBOL y o DESCRIPTION 1
36. 5 5 215 RTS 2 135 82136 UPATEN TLB 88 95 95 65 00 5 8 8 8 4 CIS 3 9 9 2 8 RESET 8 0 65 65 2 ale CA ON Bie gle Sit po 26 DRIN a 5 Ke 92 8 LIRO Teiden PRANK ON 44 2 4 5 E I2C SDA 10 0 3 8 o oi 6 77 8 4 OFF DS CLAMP t CAN NCC 5 Kl verivi 1 kc L ene Stez M SERS SERS amp 140 12 e 5 5 NC 4 4 Lo BANK RESET 5 S 6 6 5 a4 220p 119 es 228 d 5 5 65 5 12 BANK 8 5 p 9 BANK CLK LO 7 7 8 CA_VCC 5 1 OFF D43 3V amp Pd 5 BANK VCC e ace 2 8 87 D CANS ANALOG AV wl Vo Video 0 5 lt OFF_0 3 3V nu CA CLK 012003 7 7 140 15 77164 8218 S CADET 1 lt CANS_ANALOG_AV gt 82146 Audio 8 4 ny RAB4C82J T R g 083 3 n 8115512 on each VCLAMP 8115512 Capasitor on each VDD 27 1530 3 4 MAIN ASSY 3 7 13 7 main assy 3 7 e MEMORY BLOCK XRD XBEO 27 XCSROM 052 14 95 1510
37. 5 LTV 6 0 VGC 26 RTV Single 27 20 28 ROUTI Audio signal outputs 30 1 0 0 31 Dual 32 MONO VCC VCC Capacitor 0 40 connected to GND Single Internal reference 18 AUD BIAS 8 190 bias for audio Typically 222 4 circuits Connected directly 0 0 to GND Dual TS5 1510 BCT 1520 Function 3 3 Symbol Voltage Equivalent Circuit Description Num VCC 10 FBLK INI 0 150 Fast blanking signal inputs 12 FBLK 2 VCC 9 TV FBLK Fast blanking signal output 13 FNC VCR SCART function pin 8 input output to 120k VER VCC 11 rie SCART function pin 8 output to TV LOGIC E Open collector logic outputs 5 Typically connect to 5V through 10k istor 36 INTRUPT 35 SCL bus clock line 34 SDA bus data line 14 45V DIG Digital supply 44 35V VOUT 5 0 Video output supply 48 45V VID Video supply 15 12V DIG 12 0 Digital supply 21 5 GNDA 5 0 0 0 Audio supply ground 24 5V 12V_VCCA 5 0 12 0 Audio supply 8 GND_DIG 0 0 Digital ground 40 GND_VID 0 0 Video ground 51 TS5 1510 BCT 1520 BCT 1530 CS4335 KS MAIN ASSY 4 7 1C4002 52 e BLOCK DIAGRAM DEM SCLK AGND VA LRCK gt De emphasis Volta
38. B external internal L external LNB POW1 LNB 18V 13V 18V L 13V REM Remote control input KEY Front key input x XSTBY Stand by signal H output at full power KEY 4 Front key input KEY gt Front key input XRESET OMEGA STi5512 Reset RESET CHDEC Link IC Reset x x x x x x Front LED dig Front LED dig Front LED dig 10 Front LED dig 59 TS5 1510 BCT 1520 BCT 1530 8 PANEL FACILITIES AND SPECIFICATIONS 8 1 PANEL FACILITIES Several functions keys Display of program number or time when 1 Movementon the 1 Selectionof gt Volume terminal is in standby gt display Program state Reader for a bank debit Validation of settings Power switch Reader for a subscriber Access to PERSO contract card screen PERITEL TV terminal PERITEL TV Application technology such as playback and Connection of power recording video and TV cord Cord provided to Telephone line games other than TV Input terminal for satellite terminal connection jack programs antenna Series and parallel Audio output terminal for PERITEL Parabola antenna output option computer connecting a stereo video terminal terminal for an analog connection terminal system satellite broadcast receiver 60 8 2 SPECIFICATIONS
39. CHDEC LNB_POWG lt 4 ni LNB_POW 2 17 lt CANS_DMUXCPU gt AC CLK AC CLK lt CANS_DMUXCPU gt XSTBY 5 Biz I 1 7 8128 eres 5 Sis 5 ETE 01894 7821 188718 41758 lt gt 22 17V t 1 07014 UMGIN TLB T 31 DTC124EUA TLI 07012 lt CAN5_CHDEC gt D 6V CAN5 CHDEC A 28V nu DTC124EUA TLB 07016 DTAT24EUA TLB 07010 P XSTBY n DTA124EUA TLB R1 R2z22kohn DTC124EUA TLB R1 R2z22kohn DTB113ZK TLB R1z 1kohn R2z 10kohn BTH1065 A T Lz2 2uH 77 5 6 7 8 TS5 1510 BCT 1520 BCT 1530 The power supply is shown with the marked box lt CANS_DMUXCPU gt 112 801 1 12 50 omm gt IRQ_Teiden 220 1 164 87015 RABACI81J T LED17 LED16 LED15 LED14 LED13 LED12 LED11 1 10 R7016 RAB4C181J T PE5181A 101601 Sub CPU n BBP 17 ANIT 3 151 1051 1 2 1158 1059 4 gt _ lt CAN
40. FR TS5 NYXK FR1 TS5 NYXK FR2 TS5 NYXK FR3 BCT 1510 NYXK SP BCT 1520 NYXK IT and BCT 1530 NYWXKPL are constructed the same except for the following Symbol and Description MAIN ASSY Front Panel Assy Rear Panel Assy Name Label Bonnet Case Serial No Label Part No TS5 INYXK FR2 NYXK FR3 TS5 INYXK FR TS5 NYXK FR1 BWE1103 BWX1144 BWX1168 BAL1414 BNE1120 BCT 1510 INYXK SP BCT 1520 INYXK IT BCT 1530 NYWXKPL BWE1110 BWX1146 1171 11403 1120 BWE1103 BWX1144 BWX1168 BAL1400 BNE1120 BWE1103 BWX1144 BWX1168 BAL1415 BNE1120 BWE1103 BWX1144 BWX1168 BAL1416 BNE1120 BWE1115 BWX1145 BWX1169 BAL1401 BNE1120 BWE1115 BWX1191 BWX1170 BAL1402 BNE1122 BAX1145 BAX1145 BAX1145 BAX1145 BAX1181 BAX1189 BAX1250 1 2 3 4 55 1510 1520 1530 3 1 OVERALL WIRING DIAGRAM UNER VCR SCARI RCA D SUB 25PIN D SUB SPIN MODULE SCART PIN JACK IEEE 1284 RS232C 38344282 2222282222228 See 20 18 16 14 108 6 4 2 CNA4001 1 JA4001 15 16 17 18 19 20 22 23 24 251 5005 6 7 CN5004 21 19 17 1513 8 7 5 1 1019 BKB1017 2 3 4 5 6 8 10 11 12 13BKP1123 2 4 6 BKP1122 IN BA 9 m lm 2 m BEERSESSEEZEE 1001 1135 4001 2 21 19 17 15 13 11 8 7 5 1 1019
41. OUT7 CVBS RF MOD FNC TV T V INTERRUPT MICRO LOGIC 47 AL 7 ALY o CN LIO ONOHd T OL ONOW lt 5 N om ME a e O gt 2 lt 8 20 HOLIMS Vd 8 ONON Din Ded ououd ssed g pue 99 01 9 E A L ssed g HOA ZHOLIMS suuAzz W ssed g ououg ssed g SLAW 8 AWNIOA AL LHOLIMS ann seg euo g ez 4 e 8 9 91 8 9 6 9 09 aperoeis 22 8p9 e 9 K Zt e ae oz 9pe 0 e9 ouo 09 5 yo uo ON ZN ON ZN L NH 1 V 1H3AO AL 1 d V TH3AO AL 48 Function 1 3 TS5 BCT 1510 BCT 1520 BCT 153
42. Pioneer Service Manual es ARP3079 CANAL PLUS TUNER 155 1510 1520 1530 THIS MANUAL IS APPLICABLE THE FOLLOWING MODEL S AND 5 Model BCT 1510 1520 1530 AC230V NYXK FR1 AC230V NYXK FR2 AC230V NYXK FR3 AC230V NYXK SP Q AC230V NYXK IT Q AC230V NYWXKPL AC230V Power Requirement Remarks CONTENTS 1 SAFETY INFORMATION 2 6 ADJUSTMENT NASA 36 2 EXPLODED VIEWS AND PARTS LIST 4 7 GENERAL INFORMATION 37 3 SCHEMATIC DIAGRAM 8 7 1 37 4 PCB CONNECTION DIAGRAM 28 8 PANEL FACILITIES AND SPECIFICATIONS gt gt 60 5 PCB PARTS LIST OR NN 34 PIONEER CORPORATION 4 1 Meguro 1 chome Meguro ku Tokyo 153 8654 Japan PIONEER ELECTRONICS SERVICE INC P O Box 1760 Long Beach CA 90801 1760 U S A PIONEER EUROPE NV Haven 1087 Keetberglaan 1 9120 Melsele Belgium PIONEER ELECTRONICS ASIACENTRE PTE LTD 253 Alexandra Road 04 01 Singapore 159936 PIONEER CORPORATION 2000 22 SEPT 2000 Printed in Japan TS5 1510 BCT 1520 BCT 1530 1 SAFETY INFORMATION This service manual is intended for qualified service technicians it is not meant for the casual do it
43. S_CHDEC gt m PIS TIBS To8 PXRESET OMEGA lt CANS_DMUXCPU gt ERP 14 ANI4 P12 ANIZ 12003 P03 INTP3 ADTRG g 3 LED14 2 002 amp 4 4 LED13 043 3V LED S 6 1 000 828 9 1 012 10 LED10 TI LEDIS rie LED 13 KEY RIGHT 4 KEY DOWN LEDO 15 KEY UP 16 KEY LEFT TIKEY OK 18 KEY MENU 13 REN 20 010 21 D45V 4 5 LEDO1 R7095 208 OF DTB1 e 07084 mm 8 1 062 591091 9 5 4 4 DTB113ZK TLB 07885 LED03 2 4V Vthresh 27813 401029 KEY RIGHT d KEY_DOWN KEY_UP KEY_LEFT KEY_OK KEY MENU REM A y R7001 RAB4C102J T R7002 RAB4C333J T TIT TS5 1510 BCT 1520 BCT 1530 3 9 FRONT ASSY 0009 Robe 22 gt LL 100 ee gt gt gt Z W W WU WU W NZ SZ 01 1 1 1 1 SNO D 00 69 SENE 5 00 09 CO Qu LO TM gt Ur gt gt gt LU Lg C C Lu Q 11 1 1 1 1 1 1 9981 208 18884 Sble bbOes 1008
44. UReset in Soft reset for analyzing from OS Link ErrorOut TrigOut in out out Error indicator Signal to trigger external debug circuitry e g LSA Table 5 System services pins 1 This pin is tri stated during reset and then sampled at the end of the reset to determine whether the OS Link is active and to determine the function of the shared CPUAnalyse and the ErrorOut TrigOut as described in the System Serv ices chapter If the ErrorOut pin is sampled high i e at VDD then the DCU signals TrigIn and TrigOut are selected and a low value indicates OS Link signals i e CPUAnalyse ErrorOut are to be used External 10KQ pull up or pull down resis tors should be fitted to the ErrorOut according to the functionality desired 43 TS5 1510 BCT 1520 BCT 1530 Function 3 5 Pin In Out Function 2 23 Address bus MemData0 31 in out Data bus MemData0 is the least significant bit LSB and MemData31 is the most significant bit MSB MemRdnotWr out ReadnotWrite strobe MemReq in Direct memory access request MemGrant out Direct memory access granted MemWait i n Memory cycle extender notMemCAS0 2 out CAS strobes for SDRAM DRAM in Banks 0 and 1 notMemCAS1 out CAS strobe for DRAM or SDRAM clock notMemCAS3 out CAS strobe for DRAM or sub bank chip select for bank 3 notMe
45. VID 12V DIG SDA VCR VCR 10 12 18 49 24 21 34 35 13 TS5 1510 BCT 1520 apo gt FBLK SW ov gt gt DC Restore Output DC Restore disable DC Restore Tip I itput DC Restore Pen DC Restore C Bias 9 Output disable DC Restore C I C re 25 Gain Control Tip e 1 2 388 Output Tp 2 disable E MIX SW Output Sync amp i direction Detect Control Output disable Bias Mute VIDEO SWITCH2 VCR XS MIX SW 0 6 12 0 6 12V Monitor Taterrupt Control 3 3V or 5V Fast Mode LOGIC Compatible Note All video outputs contain 75Q drivers except Vout7 47 46 45 44 41 39 37 38 36 33 1530 Typical Connection VOUTI T V BLUE VOUT2 T V GREEN VOUT3 T VRED C VOUT4 T VCVBS Y 4 VOUTS VCR CHROMA VCR VOUT6 VCRCVBS Y TRAP V
46. ator 59 digital supply voltage 8 core and input periphery 60 Vpppo digital supply voltage 9 core and input periphery 61 TEST test pin normally connected to ground 62 TRST BST optional asynchronous reset normally connected to ground 63 BST dedicated test clock normally connected to ground 64 SCLT serial clock of 2 loop through 65 SDAT serial data of 2 loop through 66 Vppp10 digital supply voltage 10 core and input periphery 67 Vssp11 digital ground 11 output periphery 68 Vssp12 digital ground 12 core and input periphery 69 TMS BST input control signal normally connected to ground 70 TDO BST serial test data out 71 TDI BST serial test data normally connected to ground 72 Vppptt1 digital supply voltage 11 core and input periphery 73 Vssp13 digital ground 13 core and input periphery 74 VssD AD digital ground A D converter 75 VDDD AD digital supply A D converter 76 Vret B bottom reference voltage for ADC 77 analog ground 1 78 QA analog input 79 Vret Q decoupling path 39 TS5 1510 1520 1530 ePin Function 3 3 PIN SYMBOL yo DESCRIPTION 80 analog input 1 81 VssA2 analog ground 2 82 Vret l O AGC decoupling Ipath 83 VDDA analog supply voltage 84 VDDXTAL supply voltage for crysta
47. cker See Contrast Table 2 NSP 14 Modem Approval Sheet See Contrast Table 2 15 Power Cord 2m Black BDG1035 16 Modem Cable 10m White Contrast Table 2 NSP 17 Modem Adapter See Contrast Table 2 NSP 18 Catalogue Bag BHG1047 2 CONTRAST TABLE TS5 NYXK FR TS5 NYXK FR1 TS5 NYXK FR2 TS5 NYXK FR3 BCT 1510 NYXK SP BCT 1520 NYXK IT and BCT 1530 NYWXKPL are constructed the same except for the following Symbol and Description Packing Case Pulp Mold Pad F Pulp Mold Pad R Side Pad L Side Pad R Sub Packing Case Remote Control Unit Instruction Manual French Instruction Manual Spanish Instruction Manual Italian Instruction Manual Polish Instruction Manual 2 Polish Scart Cable Sticker Modem Approval Sheet Modem Cable Modem Adapter TS5 BCT 1510 BCT 1520 Part No BCT 1530 TS5 INYXK FR TS5 NYXK FR1 BHD1369 Not used Not used BHA1146 BHA1147 BHD1489 BHX1028 BHX1029 Not used Not used BHB1036 BXD1010 BRC1030 Not used Not used Not used BXD1010 BRC1021 Not used Not used Not used Not used BDH1027 Not used BRM1034 Not used Not used BDH1018 BAX1271 BRM1034 BDH1014 Not used BDH1014 Not used TS5 INYXK FR2 BHD1369 Not used Not used BHA1146 BHA1147 Not used BXD1010 BRC1022 Not used Not used Not used Not used BDH1027 Not used BRM1034 BDH1014 Not used TS5 BHD1369 Not used Not used BHA1146
48. de crystal Load capacitors should be connected from XTL1 and XTL2 to ground XTL2 can also be driven from an external clock OFF HOOK RELAY DRIVER This signal is an open drain output capable of sinking 40 mA and is used for controlling a relay The output is the complement of the OH register bit in the ID Register TS5 1510 BCT 1520 BCT 1530 lll AMC2442ACVF 0 87 MAIN ASSY 6 7 IC6006 Modem Controller ePinouts Blockdiagram Pinouts 51 7 04 gt 92 8 05 53 9 AD6 RESET 10 AD7 TXD 11 2 13 14 TXC 15 HOOK 16 CHECK 17 SENCE Ex 11 9 96 9 ra BLOCK DIAGRAM CLKo CLKi Check CTS Oscillator Interpreter RTS Drivers DTR RXD TXD AFE Drivers Autobaud Country Detection Specific Routines 2442 y 8 9 50 CS1 CS2 CS3 57 TS5 1510 BCT 1520 BCT 1530 Function Pin Name TYPE Description Output DTE Data Carrier Detect output signal Indicates modem has detected carrier RING Input Ring detector input This pin assumes that a half wave opto coupler is used in the telephone line DAA circuit in the frequency detection algorithm RTS Input DTE Ready To Send input signal Used for hardware flow control DTR Input DTE Data Terminal input signal Used to enable modem device 0 Country Selection bit 0
49. ding to the model types as the following tabel Symbol and Description TS5 INYXK FR1 NYXK FR2 NYXK FR3 NYXK SP 3002 16M FLASH Memory BGC1059 A AV BGC1060 A AV BGC1061 A AV BGC1062 A AV BGC1063 A AV BGC1064 A AV BGC1065 A AV Description Part No Mark No Description Part No 4003 NJM4558MD 103003 NT56V1616A0T 8 MAIN ASSY 105007 PACS1284 04Q 1C7001 PE5181A 6005 73K324BL IH 2003 74LVUO4PW 2002 SN74ACTOSPWR 6006 2442 0 87 102001 5115512 IC1003 055 103001 BGC1058 A AV 7002 24 16 103002 103002 Contrast table 103006 TC7SZ126FU IC4002 CS4335 KS 4001 2161 1004 TDA8083H 5006 HIN211CB 6004 TL431CLP 103005 9516160 10 1 6001 TLP127 1001 NJM317DL1 A 1C6007 TLP181 GR 34 Mark Description Part No 01002 02003 07001 25 1576 02001 02002 2502411 01008 02011 06004 07013 25 4081 06002 2501760 Q6001 Q7010 DTA124EUA Q4015 DTA143EUA Q7002 Q7005 DTB113ZK 04001 04002 04009 04010 DTC123TKA Q1001 Q1003 Q1007 Q7012 Q7016 DTC124EUA Q6005 DTC144TUA Q7011 TPC8201 Q1011 TPC8301 Q2005 UMA10N Q2004 UMD2N Q7014 UMG1N D1002 D5004 D7003 155355 07004 DAP202U D2001 HVU356 D4011 D4013 D4014 PDZ12B D2007 D7005 PDZ4 7B D2005 PDZ5 6B D2004 PDZ8 2B D6003 PTZ43A D1004 RB160L 40 D1001 D2002 D2003 RB501V 40 06004 RD4 3MW D6001 512860 4072 04003 04010 04012 UMZ12N
50. e current PIONEER Service Manual subscription to or additional copies of PIONEER Also test with plug reversed Service Manual may be obtained at a nominal charge from Using AC adapter E PIONEER plug as required Leakage Test 55 1510 1520 1530 TS5 1510 BCT 1520 BCT 1530 2 EXPLODED VIEWS AND PARTS LIST NOTES 9 Parts marked by NSP are generally unavailable because they are not in our Master Spare Parts List The A mark found on some component parts indicates the importance of the safety factor of the part Therefore when replacing be sure to use parts of identical designation Screws adjacent to mark on the product are used for disassembly 2 1 PACKING 12 TS5 NYXK FR only Except TS5 NYXK FR 16 Except BCT 1520 15 20 14 1530 gt 10 11 BCT 1530 only 17 for BCT 1510 5 17 for 1530 a 1 PACKING PARTS LIST Mark No Description Part No 1 Packing Case See Contrast Table 2 2 Pulp Mold Pad F See Contrast Table 2 3 Pulp Mold Pad R See Contrast Table 2 4 Side PadL See Contrast Table 2 5 Side See Contrast Table 2 6 Sub Packing Case See Contrast Table 2 7 Remote Control Unit See Contrast Table 2 8 Sheet AHG1153 9 Battery RO3 2P VEM1018 10 Instruction Manual See Contrast Table 2 11 Instruction Manual 2 See Contrast Table 2 12 Scart Cable 1m Black See Contrast Table 2 NSP 13 Sti
51. eo DAC voltage and current reference pins 2 The YCO pin is tri stated during reset and then sampled at the end of the reset to determine whether the EMI pins are in STi5510 or 5115512 mode If the YCO pin is sampled high i e at VDD then the STi5510 mode is selected for the EMI pins and a low value selects 5115512 mode In 5715512 mode the address shift for bank is dependent on the boot bank width and the strobe pins are tri stated when the EMI bus is granted to an external DMA device External 10KQ pull up or pull down resistors should be fitted to the YCO according to the functionality desired If this pin is left not connected the pin will be pulled high by an internal pull up and will default the EMI pins to STi5510 mode Pin In Out Function SCLK A C STB out Serial clock or AC 3 data strobe PCM DATA A DATA out data out or AC 3 data out PCMCLK in out clock LRCLK A WORD CLK out Left right clock or AC 3 word clock REQ i n AC 3 data request PTS STB in AC 3 audio PTS strobe Table 3 AC 3 MPEG1 audio output interface pins Pin In Out Function InterruptO 1 in Interrupt Table 4 External interrupt pins Pin In Out Function System input clock PLL TimesOneMode SpeedSelect0 1 in PLL speed selector notRST in System reset CPUAnalyse TrigIn in Error analysis External trigger input to DCU CP
52. f no carrier is detected TRANSMIT CLOCK This signal is used in synchronous transmission to latch serial input data on the TXD pin Data must be provided so that valid data is available on the rising edge of the TXCLK The transmit clock is derived from different sources depending upon the synchronization mode selection In internal mode the clock is generated internally In external mode TXCLK is phase locked to the EXCLK pin In slave mode TXCLK is phase locked to the RXCLK pin TXCLK is always active TXD ANALOG INTERFACE AND OSCILLATOR DESCRIPTION 24 TRANSMIT DATA INPUT Serial data for transmission is applied on this pin In synchronous modes the data must be valid on the rising edge of the TXCLK clock In asynchronous modes 1200 600 bps or 300 1200 baud no clocking is necessary DPSK data must be 1200 600 bps 1 2 5 or 2 396 2 5 in extended over speed mode Received modulated analog signal input from the telephone line interface 1 TXA2 18 17 differential Transmit Analog These pins provide the analog output signals to be transmitted to the telephone line The drivers will differentially drive the impedance of the line transformer and the line matching resistor An external hybrid can also be built using TXA1 as a single ended transmit signal xTL1 XTL2 56 3 4 27 These pins are for the internal crystal oscillator requiring a 11 0592 MHz parallel mo
53. ge Reference SDATA 4 Analog Interpolator M ator Low Pass AOUTL Filter AX g Interpolator Modulator i AOUTR e PIN DESCRIPTIONS SERIAL DATA INPUT DE EMPHASIS SCLK LEFT RIGHT CLOCK MASTER CLOCK ANALOG LEFT CHANNEL OUTPUT ANALOG ANALOG GROUND ANALOG RIGHT CHANNEL OUTPUT Power Supply Connections VA Analog Power PIN 7 Analog supply Nominally 5V AGND Analog Ground PIN 6 Analog ground reference Analog Outputs AOUTL Analog Left Cannel Output PIN 8 Analog output for the left channel Typically 3 5V Vpp for a full scale input signal AOUTR Analog Right Cannel Output PIN 5 Analog output for the right channel Typically 3 5V Vpp for a full scale input signal Digital Inputs MCLK Master Clock Input PIN 4 The frequency must be 256x 384x or 512x the input sample rate in Base Rate Mode BRM and either 128x or 192x the input sample rate in High Rate mode HRM LRCK Left Right Clock PIN 3 This input determine which channel is currently being input on the Audio Serial Data Input pin SDATA SDATA Audio Serial Data Input PIN 1 Two s complement MSB first serial data is input on this pin The data is clocked into the 54335 via internal or external SCLK and the channel is determined by LRCK DEM SCLK De emphasis External serial clock input PIN 2 A dual purpose input used for de emphasis filter control or external serial clock input 1530 TS5 1510 BCT 1520
54. gnal on this pin will put the chip into an inactive state All Control Register bits CRO CR1 tone will be reset The output of the CLK pin will be set to the crystal frequency An internal pull down resistor permits power on reset using a capacitor to VDD 4 TS5 1510 BCT 1520 BCT 1530 Function 2 3 PARALLEL MICROPROCESSOR INTERFACE continued NAME PIN TYPE DESCRIPTION WR WRITE A low on this informs the 73K324BL that data is available ADO AD7 for writing into an internal register Data is latched on the rising edge of WR No data is written unless both WR and the latched CS are low SERIAL MICROPROCESSOR CONTROL INTERFACE MODE NAME TYPE DESCRIPTION ADO AD2 5 7 REGISTER ADDRESS SELECTION These lines carry register addresses and should be valid during any read or write operation SERIAL CONTROL DATA Data for a read write operation is clocked in or out on the falling edge of the EXCLK pin The direction of data flow is controlled by the RD pin RD low outputs data RD high inputs data READ A low on this input informs the 73K324BL that data or status information is being read by the processor The falling edge of the RD signal will initiate a read from the addressed register The RD signal must continue for eight falling edges of EXCLK in order to read all eight bits of the referenced register Read data is provided LSB first Data will not be output unless the RD
55. hen the VClamp pins must be connected to the 5V power supply the 5V logic device power supply Note in this case the 5V power supply must be capable of sinking the clamp current of transient signals above 5V In the latter case it is important to ensure the correct power supply ramp sequence The VClamp power supply must be ap plied before or at the same time as the VDD 3 3V power supply This is to ensure that during power supply power up and power down VClamp gt VDD 0 5V Table 1 Power supply pins Pin In Out Function R our out Red output our out Green output B OUT out Blue output C our out Chroma output our out Composite video output Y OUT out Luma output REF DAC in DAC current reference DAC in DAC current reference V REF DAC RGB in DAC voltage reference V REF DAC YCC in DAC voltage reference OSD ENABLE in out OSD enable notHSYNC in out Horizontal sync ODD OR EVEN in out Vertical sync 0 72 output Digital YUV output CFC input DENC color burst phase and frequency control This pin can be used in non scart based Genlock applications If itis not used this pin must ground 42 Table 2 Video output interface pins 5 1510 1520 1530 Function 2 5 1 digital encoder video outputs are analogue signals and not tolerant The same applies to the vid
56. ice part k 4 NOTE FOR FUSE REPLACEMENT 2170 CAUTION FOR CONTINUED PROTECTION AGAINST RISK OF FIRE REPLACE ONLY WITH SAME TYPE AND RATINGS ONLY 2 2n2 26 1 2 3 4 a 5 6 7 8 55 1510 1520 220 e p gt 5 Return 7180 4 8 245 TCDT1103G m F221 925 NCS 5170 F234 CT283D3 7 6220 3221 F201 F202 e 24 19 BYD33J 680R 255 atta 82x79 827 N YZ m 7204 6252 636 5208 9208 205 206 3 CI e 18 23V BYW95C 20 m as 9251 HO 12V 6250 Bx 899 95 2 NCA un T 33 A Jm 3206 F244 e 10K 6202 5200 209 210 0209 TWG VS Me ep 5V e F231 230 27 200 220 etia 8 2 E 3 3V gt 8Va 4 Mad 6210 5210 213 F214 T 4 e BYV27 200 1 3u3 5 45V Return a a A 5V 4 AE e 6225 5220 F217 F218 r T 100 Re 5V BYD33D 4 7 u 4 gt QN N 7 ATE srs X S AC CLK 1 F241 F242 6230 5230 F226 F227 12V gt M a
57. l oscillator 85 XTALI crystal oscillator input 86 XTALO crystal oscillator output 87 VSSXTAL ground for crystal oscillator 88 Vppp12 digital supply voltage 12 core and input periphery 89 Vppp13 digital supply voltage 13 core and input periphery 90 Vssp14 digital ground 14 core and input periphery 91 DiSCTRL 22 kHz 44kHz output for dish control applications 92 Vssp15 digital ground 15 output periphery 93 Vssp16 digital ground 16 core and input periphery 94 VAGC O Tuner AGC output 95 n c 96 Vppp14 digital supply voltage 14 output periphery 97 15 digital supply voltage 15 core and input periphery 98 OUTSD Sigma Delta Output 99 10 digital l input bit O ADC bypass LSB 100 digital l input bit 1 ADC bypass Note 1 Pins 10 to 16 QO to 06 SCL SDA INT SCLT SDAT and OUTSD are 5V tolerant 2 The structure of I O s and the maximum output drive are specified in Section 12 40 ll STI5512MWD MAIN ASSY 2 7 1C2001 Programmable Transport IC eBlock Diagram K Block move DMA Programmable transport interface IEEE 1394 link layer interface IEEE 1284 interface Interrupt controller lt gt 10S ink 2 UARTS 2 126 x 3 PWM Diagnostic controller and system A services 4 lt 2 SmartCard lt _ interfaces ASC
58. lel data output bit 2 32 Vssp5 digital ground 5 output periphery 33 parallel data output bit 3 34 4 parallel data output bit 4 35 PDO5 parallel data output bit 5 36 Vsspe digital ground 6 core and input periphery 37 Vssp7 digital ground 7 core and input periphery 38 PDO6 parallel data output bit 6 38 Function 2 3 TS5 BCT 1510 BCT 1520 BCT 1530 PIN SYMBOL yo DESCRIPTION 39 POR Power on Reset 40 Vppp4 digital supply voltage 4 output periphery 41 Vppps digital supply voltage 5 core and input periphery 42 digital ground 8 core and input periphery 43 Vpppe digital supply voltage 6 core and input periphery 44 Vppp7 digital supply voltage 7 output periphery 45 PDO7 parallel data output bit 7 46 n c not connected 47 digital ground 9 core and input periphery 48 PDOERR transport error indicator 49 PDOVAL data valid indicator 50 PDOSYNC transport packet synchronization signal 51 Vssp10 digital ground 10 output periphery 52 SCL serial clock of 12 53 SDA serial data of I2C bus 54 INT interrupt output active LOW 55 hardware address 56 RSLOCK Reed Solomon lock indicator 57 VLOCK Viterbi lock indicator 58 DLOCK Demodulator lock indic
59. lication Table 17 shows the assignment of the alternative functions to the PIO bits Parentheses in the table indicate suggested or possible pin usages as a PIO not an alternative function connection Port Alternative function of PIO pins bit PIO port 0 PIO port 1 PIO port 2 PIO port 3 PIO port 4 0 ASCOTxD or 55 0 MTSR ASC2TxD or 5501 MTSR ASC3TxD SciDataOut ScODataOut 1 ASCOTRxD or 55 0 5 ASC2RxD SSC1 MRST ASC3RxD Sc1Dataln ScODataln 2 Sc1ClkGenExtClk 55 0 SCIk ScOCIkGenExtClk SSC1 TtxtClockIn 3 Sc1CIk ScOCIk CapturelnO 1284PeriphLogicH ASC3 CTS 4 Sc1RST PWMOut1 ScORST Captureln1 1284HostLogicH ASC3 RTS 5 Sc1CmdVcc ASC1TxD ScOCmdVcc Captureln2 Interrupt2 6 Sc1CmdVpp ASC1RxD ScOCmdVpp Sc2Dir CompareOut2 Interrupt3 Sc1 Dir 7 Sc1Detect PWMOut2 ScODetect 1284InnotOut TtxtData 46 Table 15 Alternative function of PIO pins CXA2161R MAIN ASSY 4 7 IC4001 AV Switch e Block Diagram 1 2 Video and Digital section Typical Connection DIG FBLK VCR FBLK IN2 DIG BLUE VCR BLUE VIN2 DIG GREEN CVBS VCR GREEN VINA DIG RED CHROMA VIN5 DIG CHROMA VING VCR RED CHROMA VIN7 AUX CHROMA VINI3 DIG CVBS LUMA DIG CVBS LUMA VIN9 VCR CVBS LUMA TV CVBS AUX Y CVBS 2 SYNC 0 AUD BIAS VID BIAS 5V 12V_VCCA 5V_GNDA 5V_DIG GND_DIG 5V_VOUT 5
60. mRASO out RAS strobe for SDRAM DRAM in Bank 0 chip select for RAS strobe for lowest DRAM sub bank 0 notMemRAS1 out RAS strobe for highest DRAM sub bank in or SDRAM Chip select signal for highest sub bank of notMemRAS2 out RAS strobe for SDRAM DRAM in bank 1 chip select for Bank1 or RAS strobe for lowest DRAM sub bank in Bank1 notMemRAS3 out RAS strobe for highest DRAM sub bank in Bank1 or SDRAM Chip select signal for Bank1 5 Chip select 6 for ROM in bank3 notSDRAMCSO out SDRAM Chip select signal for or lowest sub bank of notMemOE out Output enable strobe banks 0 3 notMemBE0 3 out Byte enable strobes banks 0 3 notMemCS2 out Chip select strobe for memory in bank 2 BootSource0 1 in Boot from ROM or from link ProcClockOut out Processor clock Table 6 STi5512 External memory interface pins Pin In Out Function ADO 12 out SDRAM address bus 000 15 in out SDRAM data bus lower byte notSDCSO out SDRAM chip select for first SDRAM notSDCS1 AD13 out SDRAM chip select for second SDRAM or AD13 notSDCAS out SDRAM CAS notSDRAS out SDRAM RAS notSDWE out SDRAM write enable MEMCLKIN in SDRAM memory clock input MEMCLKOUT out SDRAM memory clock output DQML out DQ mask enable lower DQMU out DQ mask enable upper 44 Table 7 Shared SDRAM interface pins Function 4 5 TS5 BCT 1510 BCT 1520 BCT 1530
61. n 9 When ordering resistors first convert resistance values into code form as shown in the following examples Ex 1 When there are 2 effective digits any digit apart from 0 such as 560 ohm 47k ohm tolerance is shown by 5 and 10 560 Q gt 56 10 gt 561 1 4 51161117 47k gt 47x10 gt RDIAPU 411711317 059 RIO d RU RN2H R 5 0 10 M UE Ex 2 When there are 3 effective digits such as high precision metal film resistors 5 6280 gt 5623010 5 6 2 1 F B CONTRAST ASSEMBLIES Part No Symbol and Description TS5 BCT 1510 BCT 1520 BCT 1530 Remarks NYXK FR NYXK FR1 NYXK FR2 NYXK SP NYWXKPL NYXK FR2 MAIN ASSY BWE1103 BWE1115 BWE1115 BWE1110 FRONT ASSY BWE1102 BWE1102 BWE1102 BWE1102 CARD ASSY BWE1080 BWE1080 BWE1080 BWE1080 POWER ASSY BXF1139 BXF1139 BXF1139 BXF1139 55 1 103 BWE1115 and BWE1110 are constructed the same except for the following Part No Symbol and Description Remarks BWE1103 BWE1115 BWE1110 1004 TDA8083H TDA8083H TDA8083H E 2001 STI5512AWE STIB5512AWE 5115512 6006 AMC2442ACV 0 87 AMC2442ACV 0 84 AMC2442ACV 0 84 MAIN ASSY 1 3002 CONTRAST TABLE IC3002 16M FLASH Memory is different accor
62. rrent is set by connecting this pin to VDD through a 2 resistor ISET should be bypassed to GND with 0 1 uF capacitor PARALLEL MICROPROCESSOR CONTROL INTERFACE MODE ALE 13 ADDRESS LATCH ENABLE The falling edge of ALE latches the address on ADO AD2 and the chip select 86 ADO AD7 5 12 ADDRESS DATA BUS These bi directional tri state multiplexed lines carry information to and from the internal registers CS 23 CHIP SELECT A low on this during the falling edge of ALE allows a read cycle or a write cycle to occur ADO AD7 will not be driven and no registers will be written if CS latched is not active The state of CS is latched on the falling edge of ALE CLK 2 O OUTPUT CLOCK This pin is selectable under processor control to be either the crystal frequency for use as a processor clock or 16 times the data rate for use as a baud rate clock in DPSK modes only The pin defaults to the crystal frequency on reset 20 INTERRUPT This open drain output signal is used to inform the processor that a detect flag has occurred The processor must then read the Detect Register to determine which detect triggered the interrupt INT will stay low until the processor reads the detect register or does a full reset 15 READ A low requests read of the 73K324BL internal registers Data can not be output unless both RD and the latched CS are active or low RESET 30 RESET active high si
63. signal is active WRITE A low on this input informs the 73K324BL that data or status information has been shifted in through the DATA pin and is available for writing to an internal register The normal procedure for a write is to shift in data LSB first on the DATA pin for eight consecutive falling edges of EXCLK and then to pulse WR low Data is written on the rising edge of WR DATA AD7 NOTE The serial control mode is provided by tying ALE high and CS low In this configuration AD7 becomes DATA and ADO AD1 and AD2 become the register address 55 TS5 1510 1520 1530 Function 3 3 DTE USER NAME EXCLK PIN 22 TYPE DESCRIPTION EXTERNAL CLOCK This signal is used in synchronous transmission when the external timing option has been selected the external timing mode the rising edge of EXCLK is used to strobe synchronous DPSK transmit data applied to on the TXD pin Also used for serial control interface RXCLK RXD TXCLK 26 21 RECEIVE CLOCK The falling edge of this clock output is coincident with the transitions in the serial received data output The rising edge of RXCLK can be used to latch the valid output data RXCLK will be valid as long as a carrier is present RECEIVED DATA OUTPUT Serial receive data is available on this pin The data is always valid on the rising edge of RXCLK when in synchronous mode RXD will output constant marks i
64. udio Out C4037 RCA Lch OUT P 84654 1 8 66718 Ww t O L 6 686 17164 6 8 1817 DTCI23TKA TLB 04683 UNZ12N TLB JA4001 04841 TV CVBS 9 1716 cen M REN 8 68718CYB 64042 TV Lch IN 8 68718 VCR SLOW SW IN Se SIE SSR SSR 04938 VCR CVBS IN 8 1716 YB C4040 VCR Rch IN 8 68716 53939 VCR Lch IN 17 5 21 11971419414 98413331 leues 2 11 oie BCT 1530 3 6 MAIN ASSY 5 7 TS5 BCT 1510 BCT 1520 090 900991 881 82112 JOA 95655 54 52 88 18853 9 amp 5 5 e 3808 Sq 5 5 a 193135 S 5 5 0815 0815 380415 E 280 193798 josoinv LINI ol 881 050 82150 4 188891 1 0401 Tinvax 81 98551 amp JAS
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