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No. 2D730-I 33E”J SERVICE MANUAL FOR DIAGNOSTIC ULTRASOUND SYSTEM

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1. 3 26 dud UND OLD EE 3 29 3 3 1 PHASE DETECTOR suture RS De 3 31 3 3 2 s 3 33 3 3 3 FFT CONT AUDIO 3 35 jo dh CEM Una Sots et ete 3 38 8 5 1 ADC LB core es eee eee eee 3 40 30 9 PL 3 42 Bub 3 43 3 5 COLOR DSC Unit 3 45 2 5 1 DSC CEM N60 ete 3 45 8 5 2 RGB CONVERTER 3 47 326 3 50 3 7 Color Enhancement 3 52 2D730 133E 3 1 T amp R Unit 1 Outline The T amp R unit consists of the components below o Transmission circuit system which emits ultrasound from the probe The transmission circuit system has a 48 channel pulser for normal tomographic images B M mode PW Doppler FFT and color Doppler Reception circuit system which processes the signals received the probe The reception circuit system includes a reception circuit Echo Filter Log Amp wave detection etc for B M mode and a phase detection circuit for 2 Flow of signals in t
2. PHOTO PRINTER VD HD CSYNC i i 2 HD CSYNC COLOR 92 9 DSC VD HD CSYNC AUX REAR RGB MATI IMAGER CSYNC x pd EXT 1 PRINTER 1 1 4 EXT2 MO 1 i VD HD CSYNC SYNC VD HD CSYNC INT VD HD CSYNC SEP CSYNC EXT lt Het sence ECSYNC Remarks Mounted on the EXT CNN PWB Note The PAL version does not support the VHS input signal Figure 3 2 5 Block diagram for ENC DEC YI 6 0 2D730 133E F 3 2 6 MECHA CONT 1 Functions 2 The following operations are performed during annular array sector scanning a In B mode the scanning speed is controlled b In M mode the piezoelectric element is fixed at the desired angle c In B mode the data indicating the raster address and the transmission focal point are generated In addition the fundamental signals RATE and OF are generated d The zero point of the transducer is adjusted Description of operation This PWB controls the motor of the annular array sector transducer using CPU 780 motor rotation speed is obtained by measuring the pulse period of the output of the encoder attached to the motor In B mode scanning to make the raster density more uniform feedb
3. 3 45 3 5 1 DSC DSC 3 45 3 5 2 RGB CONVERTER 3 47 3 6 ECG NF 3 50 3 7 Color Enhancement 3 52 SOFTWARE 4 1 4 1 Overview 4 1 4 1 1 Interfacing with the hardware 4 1 4 1 2 Organization of software 4 4 4 2 Error Codes and Messages 4 7 POWER SUPPLY UNIT 5 1 OVERALL BLOCK DIAGRAM 6 1 ADJUSTMENTS 7 1 PATCH MENU OPERATION 8 1 8 1 Applicable Equipment 8 1 8 2 Starting 8 3 Memory Dump 8 2 8 4 Coordinate Check X Y 8 3 8 5 Image Cont External Value Set 8 3 8 6 Address Data Value Save 8 5 2D730 133E J OVERVIEW The SS
4. 2D730 133E H System noise elimination circuit The circuit is the same as the radio frequency elimination circuit It mainly eliminates CK noise of the DSC unit LOG AMP circuit logarithmic amplifier This circuit uses a LOG IC consisting of 4 logarithmic compressors in series Each compressor is a 30 dB logarithmic compressor and the series of 4 compressors provide a 120 dB logarithmic compressor Detection 0 V limiter circuit Both peak detection is performed in the detection circuit which consists of transistors The STC signal is added before wave detection for abdominal examination processing but the addition voltage is fixed to 0 V for cardiac examination processing Circuit for envelope detection LPF This is a L C LPF which eliminates carrier components from the echo signal and detects the envelope Edge enhancement circuit E E The degree of edge enhancement is switched by the setting of E E in B mode of abdominal examination processing The echo signal always passes this circuit to perform a certain degree of edge enhancement in M mode However the echo signal passes through this circuit without functioning in B mode for cardiovascular examination processing Dynamic range circuit This circuit consists of two inversion amplifiers and adds the STC signal to the first amplifier for cardiovascular examination processing It sets the dynamic range by switching the succeeding input resistor using an
5. gt 5 DVAF SW control circuit gt ee ee s s s s s s s PCRLCK70 PCRDB70 to 00 6 ADIUSTO STRCWON 1 lt lt am mm me am amn um ae am am am qm am ma anm ae am am am aa am an an mm am an aa a a am i D a A D o e a A a a M e A a m M e A S a ia a n aee ana UA 3 r n ow s eee s UB 3 ane nab s 4a eee UC 3 2MW30 14774 2MW30 14780 2MW30 14779 _ Echo filter circuit TPR6 STC control circuit ADDER OUT ka Ro 1 2 DVAF SW By pass a a lt am amn an a SO SS _ I Logarithmic Amplifier 2MW30 14776 Envelope detection circuit TPR12 TPR10 g Edge I s S dr ii cee S eh L lt lt lt v s s lt lt s Dynamic range circuit TPR17 TPR18 5 gt 0V imir UC 29 Selector VIDEO Echo enhancement circuit Q n l Data latch control logic circuit TPD11 DFCKRCV10 TPD12 I DFC
6. SHIFT GAIN OFFSET PSTCOL cp WC 12 n WC 12 0 CE 5 0 VR2 PECHOO2 TET 2 De s ED TRIG2 CHOO PSTC03 VR3 CC uc 11 TRIG3 4 PSTCO4 VR4 WC 10 TRIG4 eS 1 4 UC 6 4 VR47 TRIGA7 PECHO48 ER VRA8 UB 11 SE owe GE ewe P od 8 TRIG 1 to 8 TRIG 9 to 16 8 TRIG 17 to 24 8 TRIG 25 to 32 8 TRIG 33 to 40 8 TRIG 41 to 48 Figures in circle indicate the page number of the circuit Block diagram for the PULSER 2 6 1111 3 1 3 R DELAY 2D730 133E 1 Function a CG After providing delay time to echo signals PECHO 1 to 48 which are the outputs from the preamplifier inside the pulser PWB according to the appropriate focus pattern addition is performed to obtain the RDLECHO addition output signal Performs switching between ON and OFF of the preamplifier output signal given by the receiving element to permit reception aperture control Using two PWBs 48 element DVAF operation is performed 1 1 to 48 ch Focus 1 3 5 Odd numbered stage R2 1 to 48 ch Focus 2 4 6 Even numbered stage These PWBs perform the above functions They can be roughly divided into the following blocks o Input buffer and short delay block o Multiplexer block o Long delay block 1 Inp
7. INTERRUPT alll LOCAL t a LOCAL CPU 65000 116544 ADR DEC 134 321 Figure 3 2 3 Block diagram for PC DSC ace tT OeLde 35 2 4 2D730 133E 1 Function a Records and plays back BDF images loop frame advance b ECG synchronized recording records the images from R DELAY until freeze c Frame correlation of the B BDF images d Displays the interpolation image of CFM smoothing 2 Main specifications a Record playback mode differs from the EX Recording Loop ECG synchronization Playback Loop Slow playback is possible Frame advance The pseudo bi plane playback function LOOP HIGH FRAME function four frame edit function and the recording and playback functions of M MDF are not available b Memory capacity same as the EX B 32 Mbit maximum 127 frames differs depending on the number of rasters BDF 32 Mbit maximum 63 frames differs depending on the number of rasters c Frame correlation differs from the EX 12 types each for B BDF specified by the IP d Circuit method differs from the EX Control by the local CPU 280 Implementation of the frame correlation processing circuit into an ASIC One PWB for black white and color 2D730 133E 3 Functions by circuit block a d e f g h i FC 1 FC 2 Performs frame c
8. x SCF GAIN POWER AMP ESL B NK TL FWD AUDIO i 1 REV VOLUME P26 27 280 IBDT110 to 000 FROM E L SPEAKER FFT I O AUDIOCOS 222 PUR AUDIOSIN 1 ieee x DRAWING No 2MW30 10338 to 10367 Figure 3 3 4 Block diagram for FFT CONT AUDIO 3 4 2D730 133E Unit 1 Function and operation The CFM unit is a multi channel frequency analyzer for acquiring a two dimensional blood flow image In detail a number of points are assumed in the depth direction from the body surface and the Doppler frequency shift at each point is obtained To do this the orthogonal wave detection outputs of the phase detector are digitized ADC and a multi channel High Pass Filter is used to eliminate the motionless portion of the digitized signal at each depth point FIL To obtain the frequency of movement of this moving portion self correlation of movement over time at each depth is obtained CORR and the frequency of movement is obtained using the coefficient of this self correlation CAL At the same time the power of movement over time at each depth is obtained CORR CAL and the degree of dispersion of movement is obtained using the power and the coefficient of the self correlation CAL As the results of these arithmetic operations there are thr
9. ECG IN AUX IN SENSI VR POS VR 2 L Figure 3 6 1 MEMORY 9 512 512 11 DMARK MEMORY 512X512 x2 Block diagram for ECG NF a IM FRAME MARK GEN 2 9 DETECT E LAY COUNTER ECG DOT MIX lt um me mm mod P v SIGNAL 1 0 ee ee ee I c m sane RSYNCO ECG10 ECG20 10 icct oczac 2D730 133E D 3 7 Color Enhancement Function 1 Function The color enhancement function consists of 3 PWBs the following functions a IMAGE MEMORY 1 Persistence function Normal V ANGIO lt 2 gt ANGIO DR lt 3 gt ANGIO DISPLAY TYPE b ADC LB CAL new functions are controlled by the DSC DSC lt 1 gt V FILTER control of low velocity blanking lt 2 gt P FILTER control of high power blanking lt 3 gt Control of the dynamic range of the power value coupled with ANGIO DR COLOR RESOLUTION PC DSC CFM DSC lt 1 gt 3D PERSPECTIVE lt 2 gt COLOR CAPTURE lt 3 gt COLOR RESOLUTION lt 4 gt ANGIO DISPLAY LEVEL each of which has tSt 55 340 Color Enhancement Block Diagram Cable ADC LB CAL PC DSC
10. RGB Color PULSER h PC DSC B W 22 PROBE 48 c monitor lt DVAF RECEIVER VIDEO VIDEO observation lt 48 ch PHASE monitor DETECTOR ENC DEC VCR Front panel 2 RGB CONV External RGB RGB output PC DSC COLOR Rear panel FFT External video output Speaker i Color EXT photography unit FIL CORR CNN or Color printer ADC LB CAL MTI CONT RPG TRCONT CPU B W photography Front panel 1 unit MECHA CONT ECG NONFADE DC IN B W printer Magneto optical Operating disk unit etc panel POWER UNIT 111 No 2D730 133E ADJUSTMENTS Adjusting the anti RFI anti radio frequency interference circuit 1 Principle This circuit comprises of 2 series of notch filters which include parallel connected Ls and Cs changing the values of Ls and the elimination frequency fr can be set Attenuation with fr is 50 dB Eo 50 Gs Figure 7 1 The noise elimination frequency fr can be set by changing the combinations of the 3 Ls and 2 Cs and by changing the value of Cs using the trimmer capacitor For the combinations of the Ls and Cs specifying the adjustment range for fr refer to table 7 1 The settings indicated with No 1 in the table are used at the time of shipment from the factory L T M O IIF nF No 2D730 133E 2 Counterm
11. The functions above are performed for 48 channels per PWB 2 Figure 3 1 3 shows block diagram 3 5 M 1 48 HVSWD HVSWCK HVSWLE HVSWCL WA S PW I CUE 2 indicates the page of the circuit diagram Figure 3 1 2 PROBE Granddaughter board SW PROBE CNN oom oup me mom ode a momo 48 PROBE Granddaughter board Block diagram for the PROBE SELECTOR IT CNN detection LJ A POUTINHI MHVDCMDI WA 12 WA 4 HOLOSTSS 20 8 ON dixHttI Ot4G7 Block diagram for the PULSER VH VN CH1 T2943 BUFFER PRE ULPF 2 TRANS POUT 01 AMP 12dB 30 to DS0026 4 18dB BUFFER qe INH 5 SAME ABOVE T INH VH VN CH3 PULPF 6 pouT 03 SAME ABOVE PULPF 7 pour 04 INH VH VN we lt wee CH47 48 PULPF 98 POUT47 C SAME ABOVE 2 INH 1 5 V 9 TP4 55 55 WB 31 WG 31 TIMING yo H GENERATOR 2 1 WA 25 MTCKO J 9 CLK 11 to Figure 3 1 3 3 1TC160G33AF1125 Wc 19 LATCH TRDB000 100 Li 9 PECHOO1 WC 18 LESS TS
12. but it is also possible using the Data Set in the patch menu a RIP Test Pattern Address 200016 Data 008F b LIP Test Pattern Address 200016 Data 00A7 or 00B7 C DSC Test Pattern not existing in the Test Pro Address 200016 Data 00AE or 2 Differences from the EX DSC a Speed up of Frame Memory writing b CFM Smooth is possible in Dual display by constructing Frame Memory corresponding directly to TV1 TV2 c Lateral Filter processing is possible with 4Line FM IN SC 3 45 99 6 1 FFT ECHO DIGITALI MTIQ iFFTD HOST c Leu CPU ACCESS 1 9 123 26 27 IMAGE HEHORY FM CN SC RIP FILTER 4 z MBIT come TN MUX 13 14 8 8 19 LOCAL CPU i t a 31 321 Figure 3 5 1 Block diagram for PC DSC CFM DSC 19 VIDEO 24 TO 5C AREEN lt gt ipai ON OxS3ttli 0 4C No 2D730 133E 3 5 2 RGB CONVERTER 1 Function a b f Synthesizes black white echo data with color blood flow data for display Converts blood flow data to an RGB color image Synthesizes ECG waveform signals from NONFADE w
13. As shown in the block diagram the long DL consists of the seven 300 ns delay lines A buffer is installed between these delay lines to compensate the frequency and delay characteristics DVAF SW block Echo to which delay is added by the long DL block passes through HPF and is sent to DVAF SW The DVAF SW block utilizes FET SW and provides differential output to enable dynamic delay control in which noise is suppressed addition to this the output is sent to the DVAF RECEIVER PWB through a separate line in order to provide a wide dynamic range when the DVAF is OFF Control block Control block consists of two blocks write control and read control blocks through FIFO 3 2D730 133E 1 Write control block The figure below shows the timing for input data and clocks The input data is the delay data quantized at 4 ns The bit allocation is shown in the figure below The input data is latched and then sent to the sing around ROM The sing around ROM is so programmed that the tap most suitable for the input data may be selected The ROM is not interchangeable with the other RDL PWB Thereafter the data is accumulated in FIFO RDLDB Positive logic on bus 11110 1 amount pS 1008000088 108880000080 saa 5 RDLDBO 0 Disables reception D aua TL Level 1 Enables reception 1 H level e 2 Read control block Accumulated data are read from the FIFO
14. CFM DSC RGB CNV P and V FILTER P DR Control Capture 3D FMA e Angio display level Color reso lution e Input buffer e Lateral filter Blank processing section Color bar e P FILTER e V FILTER P Dynamic Range e Angio DR e Angio istence nee 1 V Old persistence type persistence Image Memory IMAGE MEMORY IM ON 4 51 05245 2D730 133E SOFTWARE 4 1 Overview Interfacing with the hardware 1 Noise elimination The system is designed so that the CPU bus is made available only when the CPU accesses a terminal to prevent image data from being affected by noise 12 MHz on the bus Figure 4 1 2 shows the CPU bus gating arrangement Figure 4 1 1 shows how the CPU bus gate allows the CPU to access a terminal The system in the same manner as for the EX series opens the gate allows the CPU to access several I O units then closes the gate for more efficient processing The gate is opened The CPU accesses the terminals The gate is closed Figure 4 1 1 CPU bus gate operation 2 Logical system configuration Figure 4 1 3 shows the logical configuration i e the software and hardware control paths of the system As seen from this figure the software controls almost all of the units boards The system has about 500 hardware ports For efficiency software controls the minimum number of h
15. TRC section PDE control Gase taste sock geri x generation ion generation lt 17 gt IOSEL O olro o RCMPXCKO MSEL60 COMSELO f H BRISELO Each types Each type T amp RSELO e CK755 efcomro 1 e Each type of timing CU COMMAND Each type K H DVAFLD 1 21 seccion of control Storage of each lt 2 gt lt 3 gt lt 4 gt lt 5 gt j type of setting Ed condition such as echo filter etc DVA 1 CRAMWEO CRAMOEO lt 9 gt RCPSDB 1 amies timing S j HYSW CONT Each type of TRC section setting high voltage endurance switch etc Each type of Control si nal setting lt 10 E DVA CONT TRC section TRC section delay data transmission p aperture 18 19 data generation TRC section transmission reception delay data generation RESETO Each type of clock TCK GEN To each section TRC section 10 Each type transmission of setting basic clock generation A lt 11 gt V x 2 HOTINTI INTERRUPT CONT TRC section PBEN 1 HVDNCMD1 e ANN interruption r4 VINT 7 signal S generation 6 m of timing POWER UNIT CONT TRC section power supply unit control signal generation 2 3 gt Each type of setting Figures in lt gt indicate the number of the page of the circuit diagram PBCH
16. the following functions are provided to control each PWB in the T R unit a Generates and transfers transmission reception DELAY data b Generates and transfers transmission reception aperture data c Generates and transfers the control signals of the high voltage endurance switch and the reception echo signal processing circuits the GAIN control circuit of PREAMP ECHO FILTER circuit DYNAMIC RANGE ECHO ENHANCE circuit etc d Generates the control signal for progressive dynamic focus e Generates the transmission basic clock signal f Generates the control data in the high voltage circuit in the power supply unit 2 Figure 3 2 2 shows a block diagram Connection destination HOST CPU 06 6 RPG OSC RPG section 1 Basic clock generation lt 14 gt RPG section CK151 RPG section Raster address generation RPG section TRC section CPU 1 0 SCAN CONT TRC section Storage of each type of setting condition such Data RPG RASTER CONT 1 lt 15 gt T RATEL TRSTA O TRC section conversion lt 7 gt MSRFTGOO 1 TRRSTA 1 ROL1 as preamplifier gain DR EE etc Probe ID detection ED j CAB 1 _ 1 PDF CONTROL 0 sekring BASIC GEN TRC section c4
17. Controls the RS 232C interface IC b PANEL I O section The following information is transmitted and received between the host CPU and the panel o ON OFF information of the SW and LED o Information concerning the amount of shift of the trackball and rotary encoder o SCAN IC control information c TV SYNC GEN section Generates the read clock in the TV horizontal direction and generates the TV signal in synchronization with the graphic signal of the host CPU 2D730 133E STC waveform generating section Performs A D conversion of the voltage value of each STC slide control on the panel performs horizontal interpolation generates data for STC waveforms adds the preset STC value gain gain correction value transferred from the host CPU to the data and performs D A conversion to generate the STC waveform ROM 4 5 MB 16 MPU 68000 gt SRAM 256 KB EEPROM Power monitor TV SYNC HCCONT GA i E Uma SIGNAL No 2D730 133E 5 232 2D730 133E 3 2 2 RPG TRCONT 1 Function This PWB consists of the RPG section and the T R CONT section In the RPG section the functions to generate the following signals to be the basics of the system are provided a Basic clock signals b Basic rate of ultrasound RATE OF and sample enable signals c Raster address signals of ultrasound In the T R CONT section
18. ISR has the OF task FI ISR has the FI task RTC ISR has the RTC task ECG ISR has the ECG task and black white DSC hole pixel calculation completion ISR and color DSC hole pixel calculation completion ISR have the DSC task and DSC error ISR has the ERROR task Exception processing is provided as processing when a software malfunction occurs Common functions and Common functions for measurements are provided as common functions shared with software Common table and T amp R delay data table are provided to support additional probes by simply making a minor change of the table Separate tables are provided for measurement related data auto annotation and body mark data on which demands specific to the user are made so that service personnel can make additions or modifications 2D730 133E 05 E PATIENT 75 Initialize Distance CONDITION PRESET MONEX i measurement ellipse MEE Area trace i i i 1 Area Probe ISR ira Histogram anaman amema t VCR TALLY SW bf i 5 processing Image CONT Marker x rectangular t 1 n nn v asuremen t Velocity j CONT trace x x x Fixed
19. Sample processing f LIP processing while reading Frame Memory FM OUT GA g Post processing while reading Frame Memory Gamma RAM h Outputs the B W Composite Video signal DAC ENC DEC PWB i Outputs the B W Digital image signal RGB CONV PWB j Generates the Test signal Operation is performed using the Test Pro However the Data Set by the following patch menu can be also used a DSC Test Pattern Address 200006 Data 00AE or OOAC b LIP Test Pattern Address 200006 Data 00B4 or 00A4 2 Differences from the EX DSC a Smooth Filter processing Digital Filter b Speeds up Frame Memory writing Constructs Frame Memory directly corresponding to TV1 2 4 FFT Data is input in digital form E JHAOE Y un xd DS 1 N V 6 N ECHO r P M 2 VEATICAL 19 114 v10 0 SMOOTH SC RIP ICFHJ LATERAL FILTER DIGITAL MT1 utfT FFT ECHO DIGITAL VERTICAL SHODIH FFT 18 10 eos 18 MUX Hf Fila La 19 2 COAT CPU CON T MUASEL WE O FM CQM F EUN EPA O 1 0 lt m OGT UP NATE HOST ENAGE cout 19 25 26 27 gt LOC AL
20. according to the read clock The data written in the previous DVAF data transfer period is read from the FIFO at one time 2D730 133E THIS PAGE IS LEFT BLANK INTENTIONALLY 3 10A 2D730 133E AVZ039 01 x 24 30 21299 6 1 098 7dB iff UC 30 va 30 4 gt 8 ch 8 7 x x x x 9 16 16 16 en 9 M 15nsx2tap 30nx2tap 3 9 6 lm 1201 9 B SDL SMC 2401 nti 300 V I EI F 10 2 47 Ie 111 UA 2 Tt e T Buffer Small DL 15 1 60 5 315 L SDL aa di li dw 48 x 16 matrix SW EPROM 25 2 5 N REG sing around RDLDB T1 B WA 26 t 1 O 270 TT ap 521 1924 RDLECHO 1 B4 Pp MM 2B RDLECHO C Even numbered TP3 WA 3 channels m LL RDLECHO 2 Odd numbered WA 4 channels 1648 DVAF SW 1 RWRCK WA 19 164 RDLECHO 6 DVAF Write CONT OFFO HC40105 Large DL RRDCK x9 HC174x6 WA 17 Figure 3 1 4 Read CONT 300 ns x 7 tap 2 1ps Block diagram for the R DELAY 2D730 133E 3 1 4 DVAF RECEIVER 1 Outline 2 This PWB comprises three types of circuits the DVAF SW circuit the RECEIVER circuit and the PRE STC CONT circuit The circuits are implemented on a single Kl size PWB using surface mounting technolo
21. added through the DELAY LINE on the R DELAY PWB so that the wavefronts of echo signals from the 48 channels can be matched for deflecting and focusing the reception beam Because focusing during signal reception is performed dynamically two systems of R DELAY PWB output signals are selected using the DVAF SW so that DELAY LINE tap setting noise is not mixed in data which sets the delay time through the DELAY LINE on the R DELAY PWB is generated in the same manner as for transmission data and transferred to on the R DELAY PWB data is transferred during each DVAF interval via the two bus systems RDLDB Then the DVAF output signal from the DVAF RECEIVER PWB is transferred to the RECEIVER circuit for B M display and to the PHASE DETECTOR PWB for FFT CFM display The signal which has been transferred to the RECEIVER circuit has its central frequency changed via the band pass filter with respect to time depth in the ECHO FILTER circuit the resolution and S N ratio is improved wave detection and gain adjustment are performed in the DETECTOR via the LOG AMP and the signal is output to the D amp D unit Gain adjustment is performed by the STC signal generated from the CPU PWB in the D amp D unit The signal transferred to the PHASE DETECTOR PWB is amplified in the AGC PRE AMP via the SELECTOR and phase detection is performed through multiplication by the Doppler Reference signal in the MIXER circuit The output signals are d
22. analog switch Echo enhancement circuit AGC For observing the heart etc this circuit feeds back intense echo signals near the wall with a certain time constant This switches the degree of enhancement by the setting of E E in M mode and B mode for cardiovascular examination processing Control circuit This circuit latches the data bus PCRDB 8 bits during the rate blanking period and sets data and control for each circuit 2D730 133E H c 12 STC control circuit This circuit receives the STC signal and switches the point at which the STC signal is added by the setting of abdominal or cardiovascular examination processing Gain conversion of STC voltage is 0 5 V 10 dB 3 Differences from the EX series The DVAF SW circuit is based on the structure of the SSH 140A The adjustment circuit is changed The RECEIVER circuit is implemented on the RECEIVER PWB common to the EX series using surface mounting technology for the LOG AMP only however the LOG AMP on the circuit of the SSA 220A is used and the number of adjustment VRs is reduced The PRE STC CONT circuit is based on the saw tooth wave generation circuit of the OFFSET DELAY of the SSH 140A however three types of depth to sensitivity curves by which the close range sensitivity is made lower than 140A are added 61 6 2MW30 14772 RDL1 ECHO DVAF SW WA WA 3 RDL2 t 2 c2 Q 9 N 5
23. devices 1 Function to switch the input of the video signal VIDEO SELECTOR Selects the input signal using the data set to the I O PORT according to the panel SW menu operation Outputs the color DSC output as the RGB signal in the color system in INT mode At this time the black white DSC output is output as the black white video signal for which positive and negative have been selected Selects positive and negative to output the black white DSC output as the black white video signal for the black white system in INT mode The VCR playback signal for which the input has been selected between the SVHS and VHS using the toggle SW on the VCR panel is input The PAL version does not support the VHS input signal The EXT RGB signal is the input signal for which EXT1 printer or EXT2 MO etc has been switched on the EXT CNN PWB 2 Function to separate select the synchronization signal according to the selection of the input signal SYNC SEP SYNC SEL Selects and outputs the synchronization signal of the system when the DSC output is selected If the VCR or external device C VIDEO output is selected it separates CSYNC HD VD from the video signal before output If the EXT RGB signal is selected it separates CSYNC HD VD from the EXT CSYNC before output 3 Encoder RGB S VIDEO S VIDEO Y C C VIDEO O Converts the RGB component signal to separate video Y C Con
24. frequency 50 Hz or 60 Hz Functional description The AC input is connected to the power unit by a cord and goes via circuit breakers and a line filter to terminals 1 and 2 of the terminal board connected to a switch Terminals 3 and 4 of the terminal board are connected to the isolation transformer via a filter The AC output is output from the secondary of the isolation transformer to AUX OUT POLOJN PO11JN PO12JN 107 is used for the color observation monitor is connected to AC OUTLET on front panel 2 and PO12JN is connected to OUTLET on front panel 1 Another AC output is output from transformer to the DC power supply Eleven regulated voltages of 5 V 5 V 5 2 V 15 V 15 V 12 V 10 V VL VH VP and VN are output from the stable DC power supply and direct current and voltage are supplied to each unit through the output filter Abnormality detection The following abnormality detection functions are provided in the power supply unit for direct stable power supply outputs When one of the direct outputs is abnormal all outputs of the direct stable power supply are shut down a Overcurrent detection b Overvoltage detection When the FAN is stopped abnormal temperature rise is detected and all outputs of the direct stable power supply are shut down 2D730 133E THIS PAGE IS LEFT BLANK INTENTIONALLY No 2D730 133E F 6 OVERALL BLOCK DIAGRAM 48
25. granddaughter board for the annular array sector transducer can be selected as an option for switching of three transducers Selects the transducer corresponding to the specified raster for each rate Switches between two transducers for the PWB supporting two transducers three transducers for systems incorporating an option Provides probes incorporating an impedance converter with direct bias voltage Turns OFF the high voltage relay when high voltage leaks to the ultrasonic signal line or when a probe ID is not identified correctly At this time the system stops and ERROR is displayed on the monitor If a resonance transducer is connected by mistake the high voltage relay is turned OFF and system operation is terminated Connects motor control signals from the MECHA CONT PWB to the annular array sector transducer 2 Figure 3 1 2 shows a block diagram 3 1 2 PULSER 1 Outline a b PULSER This circuit electrically drives the transducer inside the probe and outputs high voltage pulses set by VH according to the TRIG signal described below PRE AMP Preamplifies the echo signal from the transducer with a gain corresponding to the external control voltage PSTC 6 to 30 dB 18 dB when CH is OFF with variable aperture used T DELAY CONTROL Outputs the TRIG signal to excite the PULSER by providing the pulse width the number of burst waves and the delay time set by MICKO and TRDB
26. not receive it 5201 No FI interrupt from the PANEL I F section on the CPU PWB in calculation of TR delay time 5202 The local CPU of the ECG NONFADE board generated an interrupt but the host CPU did not receive it 5204 The host CPU failed to access the C RAM in the monochrome DSC 5205 The host CPU failed to access the C RAM in the color DSC 5206 Undefined probe ID detected by the host CPU 5208 The local CPU of the COLOR DSC generated an interrupt but the host CPU did not receive it 5209 The host CPU failed to access the C RAM in the FFT CONT AUDIO board 5215 host CPU received interrupt from the RPG section RPG TRCONT board after sending OF RESET information to the RPG section 5218 host CPU received OF interrupt from the RPG section before sending TR OFF information to the T R CONT section on the RPG TRCONT PWB in freeze on mode 5219 The host CPU received no OF interrupt from the RPG section on the RPG TRCONT PWB before erasing frame memory 5221 signal is not generated within 3 seconds after MECHA OF signal is switched to RPG OF signal 5222 Control of the MECHA CONT PWB is not set to OFF within one second after the host CPU outputs OFF to the MECHA CONT control 1 0 Endless loop 5223 host CPU received OF interrupt from the RPG section on the RPG TRCONT PWB when it expected the interrupt 5224 The host CPU received no OF interrupt or ECG OF interrupt during ECG S
27. the existing three PWBs FFT PWB AUDIO amp LM PWB and FFT CONT PWB are integrated into a single PWB by implementing the FFT arithmetic operation section in an ASIC and using surface mounting technology for components 3 29 No 2D730 133E THIS PAGE IS LEFT BLANK INTENTIONALLY 3 29 FFT I O PWB FFT CONT AUDIO PWB f JEN RANGE GATE FFT PHASE DETECTOR HPF GAIN FFT DSP ASIC gt PWB SIN lt j j f SPECTRUM s 1 RINGE 105 CONT ADC y rmo to Cos nu AUDIO J Buffer 280 280 SEQUENCE 1 0 TIETO amp i CLOCK AUDIO Buffer tame a Sa et 0 see Ne oe ete ae d to PHASE DETECTOR x AUDIO BLOCK PWB J uM i DIRECTION GAIN SEPARATOR POWER 1 CPU PWB HOST Cre I O BUS 68000 CPU BUS PHASE DETECTOR Figure 3 3 1 Block diagram for the FFT unit No 2D730 133E to B amp W DSC 70 PWB FWD AUDIO REV AUDIO TMI REV VOLUME SPEAKER AR 111 2D730 133E 3 3 1 PHASE DETECTOR 1 Outline 2 This PWB inputs the received ECHO which has been added using the DVAF SW on the DVAF RECEIVER PWB performs quadrature wave detection and outputs the output to the CFM UNIT FFT UNIT Functi
28. 1 PWHVD 1 RESENALO HVMSELO CWHVD 1 VO BUF lt 16 gt Figure 3 2 2 Block diagram for RPG TRCONT TRC I O BUF lt 1 gt CK20M1 CK10M1 ADCCK1 REFCK1 0 5 0 RATE1 BOVCK1 BRASTCK1 SAENO FFTCMDO DFINTO Connection 0 ECGFRO RFFRO desti SCN20 BWRENo NEWRATEO TIMECK1 Unit TRAST O DRAST O Each PWB MSRFTGO MRYRSTO REFCLR1 DVAFONI1 TRATEL T R lt o T EFCK1 MIDSEL 1 SECTORO SHRTINTVO HPRFENO STRCWONL DFCK1 PRLCK70 Connection desti nation T R Unit PRDB O Each PWB TRDB O TLCK70 RDLOB 1 RWRCK 0 RRDCK O PWRCLR1 MTCK10 MPBEN O MHVDNCMD1 PBCHANG1 MPOINH1 VLCMD 1 VHCMD 1 E RESOENO MECHSELO Connection destination Power supply unit dJccr oczde 2D730 133E G 3 2 3 DSC B amp W DSC 1 Function This DSC is a single PWB into which the upgraded versions of the DSC I O and DSC FM functions of the EX series are implemented a Digitizes the analog echo signal output from the RECEIVER PWB at 15 MHz ADC b Vertical Smooth Filter processing Digital Filter c Input output of data to from the IMAGE MEMORY PWB d Lateral Filter processing FM IN SC e Constructs B W images by Frame Memory B mode Performs Frame Correction processing if there is not the IMAGE MEMORY PWB M mode MAX
29. 3E 1 Outline 2 This PWB performs extraction filtering gain setting and A D conversion of signals in accordance with the range gate position in PW mode Function The functions and the outline of the operation of this PWB are described below Abbreviations enclosed in parentheses indicate the name of the block which contains the function a b f Detecting the Doppler signal in a certain region using the range gate in PW mode 5 This integrates the Doppler output signal of the PHASE DETECTOR PWB based on the control signal RGATE10 S HP10 RESETP10 output from the FFT CONT AUDIO PWB at the range gate timing and samples and holds the signal Removing clutters HPF Receives the data for cut off frequency and for the number of orders via the 780 I O port and eliminates clutter Eliminating noise in the non required region PW LPF Receives the data for cut off frequency changes depending on the PRF and mode via the Z80 I O port and eliminates clutter Amplifying the Doppler signal FFT GAIN Changes the degree of amplification in 2 dB steps within the range from 4 to 30 dB according to the Doppler gain knob on the panel Performing analog to digital conversion of the Doppler signal FFT ADC This consists of the S H BUFFER and ADC and performs A D conversion of the Doppler signal based on the timing signals ADCCONVO ADCLCKO output from the FFT CONT AUDIO PWB O
30. 4 Observation monitor Speaker Sub panel Main panel VCR connector Footswitch connector Transducer holder connector 9941 signal Cu connector Fuse ufi ote Printer camera connector Transducer Note Figure 2 1 Reference UZMK 340A not applicable to TAMS Fuse for monitor Note mama C e T VT w CUP ue DD ER ee l K F EY CR RE Ne DRE uM ee CS s r re ES ee Geren camaman mamam one GU Ga sees Caw amana amana md External output connector interface CPU reset switch Breaker Grounding terminal T of the rating indication for fuses indicates that the is time lag fuse 1184 JO 7 7 0 lt 02 No 2D730 133E I 2 2 Observation Monitor 1 To check the interior of the observation monitor remove the four retaining screws A which fix the monitor rear cover for the color 15 inch monitor or the two retaining screws A and two retaining screws B which fix the monitor rear cover for the color 10 inch and black white 12 inch monitors and remove the monitor rear cover by s
31. A 340A diagnostic ultrasound system is an entry level version of the 55 140 SSA 340A supports FFT Doppler and color blood flow modes The SSA 340A consists basically of the following units 1 T amp R unit 2 D amp D unit Table 1 lists the printed wiring boards in these units Table 1 PWBs in the SSA 340A PROBE SELECTOR PBCNN Granddaughter board for electronic scan transducer PBCNNSMA Granddaughter board for annular array sector transducer not applicable to TAMS PULSER R DELAY DVAF RECEIVER PHASE DETECTOR T amp R MOTHER Motherboard CPU RPG TRCONT ECG NONFADE PC DSC IMAGE MEMORY CFM DSC RGB CONV DEC NTSC or PAL MTI CONT FIL CORR ADC LB CAL FET IJO FFT CONT AUDIO MECHA CONT not applicable to TAMS D amp D MOTHER Motherboard Other 1 EXT CNN Interface PWB for the use of external recording devices T amp R D amp D 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 5 e 2D730 133E 2 DISASSEMBLY AND REASSEMBLY Page 2 1 Name of Each Part 29 2 2 Observation Monitor 2 3 2 3 Removing the Main Panel Cover and Main Panel 2 6 2 2 4 Checking and Removing the Power Supply 2 9 2 5 Service Work for PWBs 2 12 2 6 Layout of the Racks 2 1
32. FF of plane data COLOR BAR GEN Generates the color bar from the synchronization signal of the TV according to the color mode Zero shift of the color bar Generates the timing signal for displaying the color bar CPU IF I O port of the host CPU COLOR MUX Synthesizes each data of B W CFM color bar and plane pixel by pixel Adjusts the color balance CLUT Converts image data to RGB data Transfers color data from EPROM to CLUT when the color mode is changed DAC Generates the analog RGB signal Switches NTSC PAL of the RGB signal 2D730 133E THIS PAGE IS LEFT BLANK INTENTIONALLY 3 48A RGB CNV No 2D730 133E VPTOUT uq COLOR MUX 8 5 MUX GAIN PROM B W B W PROCESS 8 pes gt 8 from FB COLOR BWTH 8 COLOR RGBBUS BALANCE SYNTH COLOR PROCESS orou 8 12 12 AMO MUX it ZERO 8 RGBBUS 3 b NE VPTOUT to n 8 8 RGBBUS from PTDB 8 pe gt VPTIN 8 from FB PLANE ENC PLANE 8 A B A A SHIFT VPTIN from FB 4 VP quM gt PRIO RITY ON OFF 6 ENCO DER PLENO x 8 H en CBH 5 pua y 27 COLOR 8 E START 24 TRAD 20 FI TIMING i CFMON1 GEN gt DECO 1 3 DER CBSEL DBSEL A 12 Figure 3 5 2 Block diagram for RGB CONVERTER 3 49 2D730 133E 3 6 This PWB has the functions below for amplifyi
33. KRCV20 mm i 4 Qe Resistor Control Logic Circuit pu 2MW30 14777 lt gt lt lt 9 Q 2 30 14778 PSTCI 5 gt m generation LA gt circuit UA 28 i PSTC4 I Ca ue lt lt lt lt lt lt s J Figure 3 1 5 Block diagram for DVAF RECEIVER wlll i I lt 0 lt 42 3111 No 2D730 133E 3 2 D amp D Unit 2224 CPU 1 Outline a Function This PWB consists of the following four different blocks and functions a Host CPU section which controls each unit using a 68000 microcomputer which has a wide address space and low power consumption b PANEL I O section which controls the interface with the panel c TV SYNC GEN section which generates the TV sync signal d STC waveform generating section b Description of operation a Host CPU section Performs the following control using the control program stored in EPROM and preserves preset data in EEPROM o Performs arithmetic operations and processing in SRAM as work area and controls each unit o Controls the graphic LSI 1 072020 to display marks etc on the monitor o Receives interrupts from each unit and processes the interrupts o Controls the timer IC o
34. Output buffer Color DSC output RGB Black white DSC output POSI NEGA VCR output SVHS VHS Note External RGB External C VIDEO For color observation monitor For EXT devices MO PRINTER camera etc For AUX multi imager etc S VIDEO S VHS C VIDEO VCR VBS B W OBS Black white observation monitor B W VIDEO B W MO B W camera printer etc SEL VIDEO Switches black white and color using the toggle SW Note The PAL version does not support the VHS input signal 3 27 86 6 5 MONITOR B W 5 C NCVIDEO B 1 2 1 3 idi EU BA VIDEO q BUE EXT1 CLOR PHOTO PRINTER 1 6 2 SEL 2 4 1 3 ba BUF EXT B W BA PHOTO PRINTER a ins VID REAR EXT2 MO CVIDEOIN 4 2 t i R VBS VHS VCR 4 1 Crores eo e a Je n e e e WCR Y C S VHS EXT Y C gt w bg VCR EXT NBS dT Note h Sees cM RGB x TEST MONITOR BGB COLOR OBS MONITOR VD HD CSINC 958
35. RR CORRELATOR section The CORR inputs the output of FIL section and performs a Self correlation arithmetic operation and power calculation b Detection of the MAX bit and bit shift c CFM AVERAGE and other processing ACREAC ACIMAC ACPWR PB to 13 14 to 20 BITSHIFT to gt ADC LB CAL PWB from MTI CONT Each type of control signal Figure 3 4 3 Block diagram for FIL CORR DRAWING No 2MW30 10174 to 10194 3 42 IEEE 3 4 3 CONT 2D730 133E 1 Outline 2 On this PWB the 280 receives data from the HOST CPU 68000 via the communication RAM For some signals the results of arithmetic operations performed on the signals in the 280 are output from the port other signals without any processing are output from the port Function The MTI CONT is roughly divided into the following functions a b c d e f 6 h 1 CPU PWB I F function Function to generate the write clock of the ADC LB the write enable range the reading clock of the CAL output buffer and the read enable range Function to generate the signals for the internal write enable WE system and output enable OE system and the internal rate Function to generate the data output timing command and to output the data for the number of combination focus steps according to the timing Function to generate the CAL output buffer write timing and CORR MAX bit det
36. TOSHIBA 2D730 133E J SERVICE MANUAL FOR DIAGNOSTIC ULTRASOUND SYSTEM ECC CEE MODEL SSA 340A 2D730 133E J TOSHIBA CORPORATION TOSHIBA CORPORATION 1994 ALL RIGHTS RESERVED 2D730 133E F No part of this manual may be copied reprinted whole in part without written permission The contents of this manual are subject to change without prior notice and without our legal obligation No 2D730 133E J REVISION RECORD Jap z AUTHOR CHANGED No PRODUCT N pate Nakajima pate Nakajima i 11 96 Support switching of three transducers F 01 97 Support the annular array transducer Mr Okumoto E 117797 02 98 1 1 3 13 to 15 98 99 ee ee 2D730 133E F CONTENTS Page OVERVIEW DISASSEMBLY AND REASSEMBLY 2 1 Name of Each Part 227 2 2 Observation Monitor lt 2 3 2 3 Removing the Main Panel Cover and Main Panel 2 6 2 4 Checking and Removing the Power Supply 2 9 2 5 Service Work for PWBs 2 12 2 6 Layout of the Rack
37. VAF SW circuit and PRE STC CONT circuit onto which components are mounted using surface mounting technology but also on the RECEIVER PWB common to the EX series onto which components are mounted using surface mounting technology with partial circuit change 3 3 2D730 133E J THIS PAGE IS LEFT BLANK INTENTIONALLY No 2D730 133E F PROBE SELECTOR PULSER pws R DELAY PWB DVAF RECEIVER PWB PREAMP 48 48 48 MM PULSER 48 CH 48 k T DELAY CONT 48 DELAY ipvar LINE SWT 48 CH 5 5 From CPU PWB f VIDEO TO ld mu DSC PWB PHASE DETECTOR PWB 8 PDDATA 71 to 01 LCKO From FFT CONT AUDIO PWB PRDB 70 to 00 TLCK 70 PRLCK 70 olo AIN olo Y lt O IO 216 100 00 TRDB D CKRPG In the case of the optional unit UIPS 343A The block diagrarn in the case that the optional unit UIAA 340A is installed is shown on the left RPG TRCONT PWB ENC 1 to 3 From z Q 2 0 90 FFT 2 2 2 R I CFM I O PWB gt ADC LB CAL PWB Figure 3 1 1 T amp R unit 2D730 133E F 3 1 1 PROBE SELECTOR 1 Outline a The standard configuration includes the daughter board and two d e f granddaughter boards for electronic scan transducers The granddaughter board for the electronic scan transducer or the
38. Velocity Vel OF ISR character 504 Color velocity measurement FL ISR ID Arbitrary MEE cu ne RTC ISR RTC x character x Black white DSC pixel I hole calculation DSC Body mark completion ISR x Heart volume trace MANUAL i Calculator function Color DSC pixel hole caleulation completion Preset ISR menu Register DSC error ISR x ERROR functi comen i shared tabl 22 4 processing function function ance TAREE data table data table RS232C Common function Auto annota Body mark BREAK for measurements i tion data table data table RS232C measurement data setting 52326 data output 72771 Test Figure 4 1 4 Task relationships 2D730 133E F 4 2 Error Codes and Messages The host CPU detects errors and outputs error codes and messages If an error code appears on the monitor find it in the following list 1 Error codes Error code Description 5200 The local CPU of the monochrome DSC generated an interrupt but the host CPU did
39. YNC from the RPG section on the RPG TRCONT PWB when the freeze switch was pressed during recording in B LOOP image memory mode 5225 The host CPU received no OF interrupt from the RPG section on the RPG TRCONT while re recording images in image memory TE 2D730 133E F Error code Description 5226 The host CPU received no OF interrupt from the RPG section on the RPG TRCONT when the image memory is to be erased 5450 The host CPU failed to access the C RAM on the ECG NONFADE board 2 Error messages Error message Description EEPROM CHECK ERROR Writing in EEPROM for check does not end within 2 5 seconds EEPROM INIT ERROR EEPROM is not ready to be written at power on EEPROM WRITE ERROR Writing in EEPROM does not end within 2 5 seconds after write operation completed TR ERROR The high voltage falls below a preset limit due to a fault in the TR circuitry MECHA PROBE ERROR There is an abnormality in the annular array sector transducer connections from the MECHA CONT PWB to the annular array sector transducer or the MECHA CONT PWB No 2D730 133E J POWER SUPPLY UNIT This unit supplies power to the main unit and external devices There are two types of power units for 100 VAC and for 200 VAC 1 2 3 Ratings of line voltage o 100 VAC unit Input voltage 100 VAC 104 to 127 VAC 102 o 200 VAC unit Input voltage 220 VAC 10 to 240 VAC 102 Input power
40. ack control is performed so that the motor rotation speed is faster at the scanning center and slower at the edges The base voltage at which the amount of feedback is reduced is determined beforehand and the feedback voltage is calculated from the difference between the motor rotation speed and desired speed This voltage is added to the base voltage and supplied to the motor The motor rotation angle is obtained based on C phase and B phase pulses of the encoder From these signals the raster address corresponding to the scanning angle the transmission focal point data and the fundamental signals RATE and OF are generated In M mode the piezoelectric element is fixed at the angle corresponding to the M address by obtaining the rotation angle from the A B and C phases 3 28A 88076 1111 ROTARY ENCODER MECHA oc E BEADR 1 SPEED ADR COUNTER SADR I 7 FILTER 7 BUFFER SPEED COUNTER SELECTOR U 7 SAMP EVEN SPEED 22 COUNTER 1 780 1 f f f f U zx 4 To ay 180 CP oF Mm VINT650 CLOCK GEN Figure 3 2 6 NECHA CONT PWB block diagram Oscillator DRIVER gt MSBCKENO MSRP MSFA 0 MSRAST 0 MOTOR e 1111 No 2D730 133E 252 Unit 1 Fun
41. ack shield 2 6 Layout of the Racks 1 The T amp R rack is located The PWB must be pulled 2 The D amp D rack is located The PWB must be pulled Right side view of the system No 2D730 133E at the upper part of the system out toward the rear of the system at the lower part of the system out toward the right of the system Rear view of the system Figure 2 13 2 14 PWB layout in the T amp R rack PROBE SEL Reserved PULSER R DELAY R DELAY DVAF RECEIVER PHASE DET Figure 2 14 No 2D730 133E 111 PWB layout the D amp D rack CPU RPG TRCONT ECG NONFADE B amp W DSC IMAGE MEMORY COLOR DSC MECHA CONT RGB CNV Figure 2 15 No 2D730 133E F FFT CONT AUDIO FFT 1 O ADC LB CAL FIL CORR MTI CONT ENC DEC 2D730 133E D 3 OPERATION OF EACH PWB Page 2 TER Uni sates ase Se eed ee ese eee eee 3 2 3 1 1 PROBE SELECTOR 3 5 deica E 3 5 3 8 374 RECEIVER S39 3 2 PED 2 E 3 16 3 2 CPU E a 3 16 3 2 2 RPG TRCONT M 3 19 2 2 4 PO DSC CREW DSC 3 21 a MEMORY EI eee 32235 3 2 5 ENC DEC
42. ardware ports each time Hardware outputs are used for presetting the probes scanning normal processing gain processing independent I O processing and other special processes 2D730 133E CPU PWB Gate T US Internal bus External bus Terminal board 1 0 port communi cation RAM Figure 4 1 2 Operation of the CPU bus gate 2D730 133E unit Color signal generator PHASE DETECTOR relat ed PWB Image memory Color monitor Black white Or observa tion FFT related PWB FFT CONT AUDIO Optical disk Image Hardware 1 CONT control processing processing Electrodes e etc Auto E processing NONFADE processing No Int SW Character L temps RF ol d penc processing Ss a display signal 1 ty Control signal Each type processing Men of cpu for hardware ment CONT ment 5 4 processing ing Control information HOST CPU from software ftware SO ET LLL PM d sss r External computer Figure 4 1 3 System configuration
43. ch items 1 to 4 4 Quit with the SERVICE menu by pressing PATCH Data set in the PATCH menu cannot cleared with a CONDITION PRESET operation Data set in the PATCH menu can be cleared by NEW PATIENT operation i 8 3 Memory R W amp Dump No 2D730 133E 1 When 1 is entered in the PATCH menu the following menu is displayed I O READ I O WRITE HEX DUMP LISTOUT HEX amp ASCIT 2 To select a desired item from this menu enter the number or R for item 1 or W for item 2 on the full keyboard 3 Functions of the other keys with this menu a S key When this key is pressed this menu ends 8 2 2 is redisplayed b 2 key When this key is pressed the address is lt key When this key is pressed the address is d T key When this key is pressed the address is key When this key is pressed the address is and the PATCH menu see increased by two decreased by two increased by 256 decreased by 256 i 2D730 133E 8 4 Coordinate Check X Y 1 Data to be entered in this menu a X X coordinate b Y Y coordinate c X DOT Number of dots in the X direction d Y DOT Number of dots in the Y direction Data items a b c and d change in that order each time the CR key is pressed 2 Press the S key to terminate operations for this menu and to redisplay th
44. ction 2 This unit has the following four functions a Extraction of Doppler signal PW b Frequency analysis by the FFT c Output of Doppler sounds which are forward backward separated d Control of PHASE DETECTOR as well as the unit itself The FFT unit consists of the following two boards FFT 0 FFT CONT AUDIO Operations The FFT unit receives the phase detected sine and cosine signals from the PHASE DETECTOR board The Doppler signals of the target test part in accordance with the range gate are sampled and held the low frequency component is cut off by the Doppler filters and frequency is analyzed with the FFTs The signals undergo FFT conversion through butterfly arithmetic operation in the FFT section undergo square addition to obtain the power spectrum perform LOG conversion and the spectrum output is obtained For separation of Doppler signal directions the FFT unit shifts the outputs of the Doppler filters so that they are 90 out of phase with each other performs analog operation on the output for direction separation amplifies the result with the audio amplifier then outputs it to the loudspeakers 3 Differences between the FFT unit of the 55 340 and the FFT unit of the EX series equipment a In the FFT I O PWB the existing PWBs including the grand daughter PWB are implemented in a single PWB using surface mounting technology for components b For the FFT CONT AUDIO PWB
45. e PATCH menu see 8 2 2 8 5 Image Cont External Value Set 1 When 3 is entered in the PATCH menu the follow menu is displayed ADDRESS T 2 4 Oy 6 7 8 9 e 2D730 133E 2 Functions of the other keys this menu a ENTER key Press this key b DEL key Press this key c SPACE key Press this key d T key Press this key key Press this key 3 PATCH MENU display 2 4 Data output timing after entering an address and data to delete all addresses and data to delete one address and data value to move the cursor up from 10 to 1 to move the cursor down from 1 to 10 by KEY IN S Return to the status in 8 2 IMAGE CONT EXTERNAL VALUE SET is selected in the PATCH menu Data is output before hardware controlling 1 0 processing is performed PM3 is displayed during execution of the program 5 Turn off the PATCH menu The PATCH program starts Note To terminate processing call up the PATCH menu again 2D730 133E 8 6 Address amp Data Value Save 1 When 4 is entered in the PATCH menu the following menu is displayed ADDRESS 2 Functions of the other keys in this menu a ENTER key Press this key after entering an address and data b DEL key Press this key to delete all addresses and data c SPACE key Press this key to delete one address and data value d T key Pr
46. easures against RFI a Checking for RFI Hold the probe and check whether or not noise which is apparently caused by external radio frequency is displayed on the CRT when the gain is turned up When noise is observed follow the steps below b Investigating radio frequency interference Investigate radio frequency interference using a field strength meter radio etc If investigation shows any transmitter station near the site the interfering radio frequency can be guessed c Adjusting the notch filters a Pull out the DVAF RECEIVER PWB using the extension PWB b Set SW1 1 and SW1 4 to OFF c Refer to table 7 1 to select the combination of the SWs so that the interfering radio frequency is placed at the center of the frequency range for noise elimination d Turn the power ON and turn up the gain until RFI noise can be observed easily Use an insulated screwdriver to adjust and VCR2 so that the RF noise is minimized e Observe an abdominal image and check that there is no abnormality such as significant decrease in S N When the filter is adjusted to 1 5 MHz to 2 5 MHz the signal level is decreased This is not a malfunction If interfering radio frequency is more than 2 MHz the notch filter will cause the signal level to be decreased tremendously For this reason it is recommended that another type of countermeasure line filter for example be taken No 2D730 133E Table 7 1 No Range for re
47. ection timing Port output function Function to control the relative cut off value Sets the ID that indicates the revision of the unit and PWB Self diagnoses function 3 43 3 va ae C3 HOST 280 I F RAM P3 P1 Working RAM P2 LB CAL ADC LB CAL PWB section P2 LATCH to CFM each PWB PORT section P5 from RPG TRCONT PWB to CFM each PWB to CFM DSC PWB CFM TIMING GEN P6 to P14 Figure 3 4 4 Block diagram for MTI CONT DRAWING No 2MW30 10196 to 10209 alll mi 0 No 2D730 133E G 3 5 COLOR DSC Unit 3 5 1 PC DSC CFM DSC 1 Function This DSC is a single PWB into which an upgraded version of functions of the CFM I O CFM FM and CFM CONT of the EX series are integrated a The digital signal output from the MTI Unit is input b Inputs outputs data to from the IMAGE MEMORY PWB c Interpolates Color Data in the axial R direction FM IN SC d Lateral Filter processing FM IN SC It is possible to switch between 2Line and 4Line e Constructs CFM images by Frame Memory f LIP processing during Frame Memory reading FM OUT GA g CFM Smooth processing during Frame Memory reading FM OUT GA h Outputs the CFM Digital image signal RGB CONV PWB i Generates the Test signal Note This is operated using the Test Pro
48. ee data V mean frequency or mean velocity dispersion and P power These data are written into color display frame memory and read out at the timing of the TV system CFM DSC and these data V o and P are converted to the R G and B video signals RGB CONV Differences from the EX series a For the ADC LB CAL PWB the existing MTI ADC PWB and LB CAL PWB are implemented in a single PWB using surface mounting technology for components PHASE DETECTOR PWB RPG TRCONT CPU PWB HOST CPU Timing signals c ND s m m s s s cmt Wave detection MTI CONT PWB No 2D730 133E CFM unit ADC LB CAL PWB outputs ADC section L J LB section ix ru ae CAL section ae eed GF ae Se eee W s ee d tf as m q Q w MD CFM DSC unit Figure 3 amp 1 Block diagram for the CFM unit No 2D730 133E 3 4 1 ADC LB CAL 1 Outline This PWB is provided with functions in which the MTI ADC section LINE BUFFER section and CALCULATOR section are combined The functions of each section are described below 2 Function ADC MTI ADC section The function of the MTI ADC is performed in the section which converts the analog signal of the p
49. eft side shield plate 4 Remove retaining screw F to remove the power shield plate 5 After steps 1 to 4 above have been completed the connector section of the power supply will be visible to permit checking Cable hanger knob Left side shield plate Retaining screw Retaining screw ae W 7 Rubber rectangular Connector section of the power supply Power shield Left side cover plate Retaining Napa ysi screw C etaining Brace left screw D Figure 2 8 2 9 Retaining screw K 2D730 133E F 6 To remove the power supply do steps 1 to 4 and remove rubber caps rectangular and round retaining screws G I and J to remove the right side cover 7 Remove retaining screw K to remove the brace right 8 Remove retaining screw L Rubber cap round 5 p m o J Brace right Retaining screw G Rubber cap Retaining round screw Rubber cap rectangular 5 Retaining screw I Right side cover Retaining screw L Figure 2 9 2D730 133E ay M 9 Retaining screw M IT D Pull out Power supply unit Figure 2 10 9 Remove retaining screw M and pull the power supply unit out while sliding it to the left 10 At this time take care with caster direction 2 N
50. erting the Doppler signal to audio signal for outputting AUDIO o Constructs LPF using SCF Switched Capacitor Filter The cut off frequency changes in conjunction with the display of the Doppler spectrum o Switches the gain in 3 dB steps within the range from 15 dB to 30 dB in conjunction with the BASE SHIFT o Shifts the phase between the SIN and COS channels by 90 using the all pass filter and detects forward and backward flow components through addition and subtraction o Switches the audio output internal output VCR input 2D730 133E CONT BLOCK _ _ E Poy 19 FFT BLOCK l P1 SPECTRUM to HOST 780 280 CPU PWB 68000 5 2 4 COMMUN 18 18 18 20 3 280 External ROM P13 16 5 Clocks gig FET _ CONT BLOCK _ e m S g PWB Enable signals 5 3 ES a P13 RANGE GATE Sal PWB GENERATOR amp fx H E 912 EE Co puero 1 0 PHASE Phase Det REF CK DETECTOR CONT GENERATOR PWB a s P13 P14 AUDIO BLOCK al wae DIRECTION SCF GAIN SEPARATOR NN POWER I P23 P24
51. ess this key to move the cursor up from 10 to 1 e key Press this key to move the cursor down from 1 to 10 3 Display the PATCH MENU by KEY IN S Return to the status in 8 2 2 Note The set data is saved in EEPROM and preserved even after the power is turned OFF until the EEPROM is initialized by using DIP SW3 No 2D730 133E 4 Data output timing o ADDRESS amp DATA VALUE SAVE is selected in the PATCH menu Data is output after hardware controlling I O processing is performed PM4 is displayed during execution of the program 5 Turn off the PATCH menu The PATCH program starts Note To terminate processing call up the PATCH menu again TOSHIBA TOSHIBA CORPORATION 1385 SHIMOISHIGAMI OTAWARA SHI TOCHIGI KEN 324 8550 JAPAN
52. gy Functions a The DVAF SW circuit performs DVAF switching of echo signals b c transferred from the R DELAY PWB The DVAF switching function is performed with a preceding SW on the R DELAY PWB and a succeeding SW and a control circuit on the DVAF RECEIVER The control circuit controls the succeeding and preceding SWs The PRE STC CONT circuit generates the gain control signal of PRE STC to control the gain of the PRE AMP incorporated in the PULSER PWB in synchronization with the RATE This signal has four types of curve to prevent saturation at close range The RECEIVER circuit receives the output signal from the DVAF circuit and outputs the ultrasound VIDEO signal Each circuit block is described along the flow of the signal c 1 HPF Improves the lateral resolution by eliminating low frequencies to improve the image quality when a high frequency probe is used c 2 Circuit for eliminating radio frequencies This circuit consists of two passive band L C parallel elimination filters and eliminates noise from a radio station etc For the adjustment procedures refer to 7 ADJUSTMENTS c 3 Echo filter circuit This circuit consists of six BPFs in series in which HPF and LPF use variable capacitance diodes and of HPF fixed by L and C This can be changed from 2 MHz to 12 MHz continuously by controlling the voltage c 4 c 5 6 7 8 9 10 11
53. hase detector to a digital signal The signal is processed as a digital signal after ADC LB LINE BUFFER section a Temporarily stores into memory the data in synchronization with the sampling clock of the MTI ADC DFADCCK1 sent from the MTI ADC and reads the data sequentially at a fixed cycle 0 6 psec By doing this it has a time buffer function so that the sampling clock can be speeded up regardless of the processing speed of the arithmetic operation function b It contains RAM for self diagnosis and visual check CAL CALCULATOR section a The CAL inputs self correlation coefficients RE C 1 and Im 1 which have undergone arithmetic operations in the CORR section of FIL CORR PWB and C 0 corresponding to the power and performs the following arithmetic operations using the ROM table As the results of these arithmetic operations it outputs mean blood flow velocity v dispersion information 2 3 2 and mean power P b It has the following preprocessing functions o A function to perform zero level shift of mean blood flow velocity v in 1 8 fr steps within a range from 1 2 fr to 1 2 fr o An auto color rejection function This can suppress the occurrence of color noise c The Z80 on the MTI CONT can read the contents of the output buffer RAM of the CAL Using this it is possible to perform self diagnosis 3 40 from PHASE DETECTOR PWB REALIN IMAGIN Each type of control s
54. he T amp R unit a b Transmission circuit system Transmission delay data which has undergone arithmetic operations in the CPU is transferred to BRI RAM on the RPG TRCONT PWB Delay data which has been transferred undergoes arithmetic operations for raster interpolation in the arithmetic operation section Then 48 channels of data are transferred to the PULSER via the data bus during the rate blanking period The T DELAY gate array IC on the PULSER PWB uses the 48 channels of data to count the number of TCK waves 10 MHz 12 MHz and 15 MHz burst waves generated in the RPG TRCONT and outputs the trigger signal for transmission after the period of time specified by the delay data elapses The high voltage DC is converted to high voltage pulses on the PULSER using the signal to drive the transducers in the probe from the free edge coaxial flat cable via the high voltage switch HVSW on the PROBE SELECTOR PWB Reception circuit system The echo signal received from the transducers is amplified by the PRE AMP on the PULSER PWB via the high voltage switch on the PROBE SELECTOR PWB In order to avoid saturation in the succeeding circuits due to close intense signals the gain is controlled in the PRE AMP with respect to time depth The gain control signal PRE STC signal is generated in the PRE STC CONT circuit on the DVAF RECEIVER PWB 2D730 133E F The output signals from the PRE AMP are delayed and
55. ignal Clock signal from MTI CONT PWB from FIL CORR PWB ACREAL ACPWR ACIMAG 1 5 ADC section P1 c M ee eS Reference Voltage TIL t Trans BUFFER AMP Reference Voltage o ECL lators Each type of control signal clock signal CAL section lt 10 to 14 gt LB section alll LINE BUFFER lt P4 to 9 gt CL 771 Arithmetic operation ROM table Blank processing section Output buffer section Q 0 ee we s s cre s Figure 3 4 2 Block diagram for ADC LB CAL D RAWING No 2MW30 10159 to 10172 1111 IMD to FIL CORR PWB to CFM DSC PWB ON 3 4 2 FIL CORR from ADC LB CAL Outline 2 Function 1 FIL FILTER section No 2D730 133E This PWB has the function in which FILTER processing and CORRELATOR processing are combined The FIL is a digital filter HPF which performs filtering of LB data outputs and inputs at the same position same pixel in the rate direction to eliminate low frequency clutter components The cut off frequency of the filter is selected by external control CO
56. ith planes such as character and measurement of the CPU for display Generates a color bar Color reverse function Generates the RGB signal 2 Main specifications a b 6 Word length differs from the EX series V 6 bits 5 bits 6 bits gt RGB 8 x 3 24 bits Color mode different from the EX series 32 types color reverse color contrast four types in each mode Zero shift same as the EX 9 steps Synthesizing black white and color different from the EX The black white gain must be and the color rejection value can be set from the CPU Synthesizing planes differs from the EX Character White Marker Green Measurement Cyan ECG waveform Green Frame mark Dark green Menu Gray Color bar same as the EX 32 x 256 pixels Circuit method differs from the EX Method in which data is transferred from EPROM with a low speed and large capacity to the color palette high speed SRAM when the mode is changed to the other color mode 2D730 133E 3 Functions by circuit block a b 5 g h B W PROCESS Gain adjustment of B W image Compares B W image data with rejection value for color balance ad justment COLOR PROCESS Color rejection Compares color image data with the rejection value for color balance adjustment PLANE ENCODER Priority encode for eight types of plane ON O
57. ivided to feed two destinations One is the ATT circuit for FFT and the other is the ATT circuit for CFM Amplitude adjustment is performed in both ATT circuits The signal for FFT is transferred to the FFT unit and the one for CFM to the CFM unit For detailed explanation of the PHASE DETECTOR PWB refer to 3 3 FFT Unit Differences from the EX series a series The basic technologies of each PWB in this unit are the same as those of the EX series integrate the same functions into a single compact PWB the density of components mounted on the PWB surface is increased using surface mounting technology for components except for the R DELAY PWB The PROBE SELECTOR PWB is newly designed based on that of the SSA 240A to support switching of three transducers with a granddaughter board incorporating the HVSW and transducer connector section This PWB cannot be interchanged with the old PWB supporting switching of two transducers For transducer C optional an electronic scan transducer or an annular array sector transducer can be connected by replacing two kinds of granddaughter board The PULSER PWB is based on that of the SSA 240A with partial change in circuit and newly designed pattern to upgrade the manufacturing characteristics The R DELAY PWB is based on that of the SSA 270A with the connectors changed to DIN connectors The DVAF RECEIVER PWB is based not only on the OFFSET DELAY PWB of the SSH 140A with partial change in the D
58. liding it backward rear cover Retaining screw A Retaining screw B for color 10 inch and B W 12 inch monitors Figure 2 2 2 3 No 2D730 133E I 2 To remove the monitor together with the front cover remove one looseness prevention setscrew using a bladed screwdriver or hexagonal wrench and lift up the monitor together with the fork support At this time the cables connected to the rear of the monitor must have been removed Color monitor Five RGB signals power cable Black white monitor BNC cable for VIDEO signals power connector GND terminal Lift up Monitor Front cover Fork support BNC cable for R G B VD and HD signals UE Looseness Power CNN prevention setscrew Figure 2 3 il Front cover No 2D730 133E I Plate A Retaining screw C Retaining screw D Plate B Brightness VR Brightness VR Contrast VR erem Knob Contrast VR screw F Retaining Plate B Retaining screw E screw E Retaining screw F 15 inch color monitor Other monitors Figure 2 4 3 To remove the front cover remove retaining screw C or D When retaining screw C is removed the front cover can be removed together with plate A At this time be careful not to disconnect the brightness and contrast VRs 4 Remove retaining screw
59. movable SW1 SW2 SW3 frequencies MHz 1 3 E tO 0 48 to 0 54 D 0900 0 95 to to to to to to Los EO to 16 C 5 t oy PF N tj Qn t2 t Note The combinations of SW2 and SW3 setting which are not listed can also be used 2D730 133E 8 PATCH MENU OPERATION 8 1 Applicable Equipment SSA 340A 8 2 Starting Important notice This starting procedure is for authorized personnel only for software protection This procedure must not be disclosed to the user 1 LSETTING menu SERVICE lt On the full keyboard Also start with the SERVICE menu by pressing PATCH 2 The PATCH MENU is displayed PATCH MENU HIT 1 4 MEMORY R W amp DUMP To write data e g a test pattern to a desired memory port COORDINATE CHECK Y To display a point at a desired set of coordinates in graphic memory for coordinate checking IMAGE CONT EXTERNAL VALUE SET Turns off control from the IMAGE CONT and uses fixed values ADDRESS DATA VALUE SAVE write data to up to 20 ports 3 To select a patch item from the PATCH menu press the number key on the full keyboard See 8 3 to 8 6 for descriptions of pat
60. ng and scroll displaying the ECG signal 1 2 3 4 5 6 7 ECG isolation amplifier Isolates the ECG electrode connected to the patient using lead IT and amplifies the ECG signal DC amplifier input Amplifies the output signal of the electrocardiograph etc by DC coupling Switching the input Normally the isolation amplifier output is selected for R wave detection and display The DC amplifier output becomes effective when the DC input connector is connected Detecting R waves and generating the ECG Delay signal Detects the R wave timing by the comparator after absolute value amplifier amplitude level correction When ECG SYNC mode is set using the panel SW menu operation it generates the timing signal delayed from the detected R wave by the DELAY value in units of 10 msec CH1 is supported and CH2 is mounted for extension Scroll displaying the ECG signal 2 planes Provided with two planes of frame memory and corresponds to the image display mode B single B dual M etc Displaying the ECG SYNC time phase In ECG SYNC mode the B mode display frame is indicated with a low gradation ECG waveform on B display or with a vertical line on M display Displaying the ECG waveform corresponding to image memory playback and displaying the frame mark Indicates the time phase of the display B frame with an arrow mark t on the ECG waveform TS E FOSI VR SENSI VR
61. o 2D730 133E F 5 Service Work for PWBs 1 T amp R rack e Shield plate for the T amp R rack 9 Retaining screw C Fan plate Rear cover Rubber Retaining f screw Retaining screw B Plate A Retaining 227 screw D Cable hanger knob PROBE SEL PWB Retaining screw A Rubber cap Figure 2 11 a Remove two cable hanger knobs two rubber caps and two retaining screws A to remove the rear cover from the main unit b Remove 4 retaining screws to remove the fan plate from the main unit At this time be sure to disconnect the power CNN of the fan c Remove 11 retaining screws C to remove the T amp R rack shield plate from the rack d To perform service work on the PROBE SEL PWB remove retaining screw D to remove plate A which connects the PROBE SEL PWB and the PULSER PWB in the T amp R rack e Remove the rubber caps and eight retaining screws E on the side of the system 2 12 Retaining screw No 2D730 133E C 2 D amp D rack Retaining screw A Rubber cap side cover L Retaining Retaining screw C screw B Figure 2 12 a Remove the five rubber caps and retaining screws A seven in total to remove the right side cover from the main unit b Remove 6 retaining screws B to remove the shield plate c Remove 8 retaining screws C to remove the D amp D r
62. on The PHASE DETECTOR has the following functions roughly divided as follows a b f g Performs amplitude limiting of the input ECHO signal INPUT LIMITER Eliminates noise in the non required bandwidth BPF Performs quadrature wave detection Eliminates higher harmonics generated by wave detection LPF Performs gain setting according to the echo level of the PW PW ECHO LEVEL Performs gain setting according to the echo level of PW and the color gain knob on the panel CFM ECHO LEVEL CFM ECHO LEVEL is affected by the PW ECHO LEVEL Generates the test signal TEST from DVAF RECEIVER PWB Core from FFT CONT AUDIO PWB SS WX signal INPUT Quadrature LIMITER wave J P Es detection P1 P2 P2 TEST P6 Control signal Signal 5 E Figure 3 3 2 Block diagram for PHASE DETECTOR DRAWING No cll CFM ECHO LEVEL PW ECHO LEVEL 2MW30 10132 to 10137 awe q m s ole 90 to the CFM unit ADC LB CAL PWB to the FFT unit FFT I O PWB 3 3 2 FFI I O No 2D730 13
63. orrelation B W MEMORY 512 k x 8 bits x 8 blocks B mode image memory 32 Mbit COLOR MEMORY 512 k x 16 bits x 4 blocks BDF mode image memory 32 Mbit DATA SELECTOR Selects data corresponding to the specified frame NO from the memory block SAMPLING CONT Controls the starting point for data fetch with respect to the RATE signal Composes image using the combination focus MEMORY CYCLE GEN Generates the timing signals such as RAS CAS of memory DRAM ADDRESS GEN Generates the address data of memory DRAM HOST CPU IF 1 0 port of the host CPU MAIN CONT Receives commands and data from the host CPU and controls recording playback and frame correlation in the 280 gt 5 0775 BDSC CDSG CPU RPG TR NONFADE DSCBFRZO IMAGE MEMORY B W MEMORY ECGFRO COLOR MEMORY ADCCK1 NEWRATEO unr CYCLE ar DFAOO to 20 2 SAMPLING CONT IMPIXCKO IMLPSFRO IMBUSYO IMRONO IOSEL80 RESETO EIORDLO EIOWRLO 10 to 70 EDOO to 150 MAIN CONT 1 Figure 3 2 4 Block diagram for IMAGE MEMORY ana 2 DATA SELECTOR ADDRESS GEN 1 1 DRATE1 DOFO BSAENO FTEET OELAT 2D730 133E B 3 2 5 ENC DEC This PWB has the following functions to output each type of video signal to the observation monitor and peripheral video
64. processing include NEW PATIENT CONDITION PRESET image CONT measurement CONT fixed character ID arbitrary character timer adjustment body mark preset menu register processing patch function 5232 BREAK RS232C measurement data setting RS232C data output and test tasks When a measurement related SW is input measurement CONT is activated from SW processing detailed analysis of the SW code is performed and subordinate tasks are activated The subordinate tasks include distance measurement area trace area ellipse area rectangular histogram velocity trace velocity histogram color velocity measurement profile heart volume trace MANUAL calculator function and report Application measurement functions are provided in the measurement CONT to permit various types of application measurements Application measurements provide LV measurements MV measurements AoV measurements fetal measurements Doppler measurements and user defined measurements that support the user s requirements in as flexible a manner as possible 2D7 30 133E When image related SW is input the image CONT is activated from SW processing For time consuming marker display this system handles marker as a task to abort processing The image CONT contains each type of function image CONT main image memory main hardware control and auto data display OF
65. s 2 14 OPERATION OP BACH 3 1 3 1 T amp R Unit 3 2 2 311 PROBE SELECTOR nO a 3 5 3 5 3 1 3 R DELAY 3 8 3 3 4 JDVAEIBREGEIVER iE 3 12 3 2 D amp D Unit 3 16 3 2 1 CPU 3 16 2 20 0 3 19 22028 PG DSC 3 21 454 IMAGE MEMORY 3 23 3 2 5 ENC DEC 3 26 3 205 MECHASCONT Gee 3 28 3 3 FFT Unit 3 29 3 3 1 PHASE DETECTOR 3 31 243202 ete seas 3 33 3 5 9 AUDIO 3 35 3 38 3 40 No 2D730 133E D CONTENTS continued Page 3 4 2 FIL CORR 3 42 3 4 3 MTI CONT 3 43 3 5 COLOR DSC Unit
66. the control signals from the CPU PWB RPG TRCONT PWB and controls the interior of the unit and the PHASE DETECTOR PWB It also undertakes FFT arithmetic operation of the Doppler spectrum and audio outputs Function The functions and the outline of the operation of this PWB are described below Abbreviations in parentheses are the name of the block which contains the function a Generating the control signal and timing signal of the FFT unit CONT o It has a CPU 780 for controlling the FFT unit and also has a CRAM as the interface with the CPU PWB The Z80 sets the 1 0 PORT for controlling each PWB and BLOCK in accordance with the content of the CRAM o Sets the RANGE GATE and performs operation control of ADC on the FFT I O PWB o Transmits and receives each type of clock and enable signals and generates the timing signals required for each PWB and clock o Sets the ID which indicates the revision of the unit and PWB b Performing FFT analysis of the Doppler signal and converting it to the power spectrum signal FFT o Provided with the ASIC FFTDSP and performs FFT analysis o Provided with information such as a window function post filter coefficient BASE SHIFT and LOG in external ROM and performs FFT analysis in FFTDSP while controlling this information o Provided with the OUTPUT BUFFER in the FFTDSP and performs control according to each type of condition mode 1111 No 2D730 133E c Conv
67. to remove the brightness and contrast VRs together with plate B from the front cover 5 To remove the brightness and contrast VRs from plate B remove the knobs and retaining screw F 2 5 2D730 133E 2 3 Removing the Main Panel Cover and Main Panel retaining screw A on the bottom of the main panel By 1 Remove w the handle is also removing retaining screw A the cover belo removed Cover below the handle Retaining screw A Figure 2 5 2 Remove the knob and the concentric VRS of the sub panel by loosening the headless screws 2D730 133E 3 Remove the main panel cover by lifting it upward Concentric VRs 3 VRs Headless screw Knob 1 knob e Headless screw Figure 2 6 1111 No 2D730 133E 4 Remove retaining screw B at the upper part of the sub panel to remove the main panel At this time be careful not to subject the connected cable to J excessive strain Remove each cable as required Figure 2 7 No 2D730 133E C 2 4 Checking and Removing the Power Supply 1 To check the power supply remove the rubber caps rectangular and round retaining screws A B and C and cable hanger knob to remove the left side cover 2 Remove retaining screw to remove the left brace 3 Remove retaining screw to remove the l
68. ut buffer short o DVAF SW block delay block o Control block 2 Multiplexer block 3 Long dela 4 3 e DVAF SW block 5 Control block 2D730 133E 2 Operations a Input buffer and short delay TD62505P 2039 01 PECHO 1 to 48 has a DC bias of about 6 V It is supplied to the array transistor TD62505P OL through W near the PWB plug The output from the array transistor is supplied to the short delay SMC SDL SMC and then passes through a delay circuit 0 to 315 ns 15 ns steps SDL SMC 2039 01 has 15 ns and 300 ns 30 60 120 180 240 300 ns delay lines and selects one of them to perform a variable delay function b Multiplexer PM30 21299 The signal sent from SDL SMC is fed to MPX SMC PM30 21299 MPX SMC is provided with a matrix type switch and connects the 1 to 48 ch signal to one of the 16 taps Thus each MPX SMC can select among 8 channels x 16 taps Out of 16 taps 8 taps of output are used However the output from MPX SMC is a current output Thus it cannot be checked using the voltage probe Long delay block DL10 to 16 The signal 51 to 58 sent from the multiplexer corresponds to the tap input for the long DL It is fed to the emitter of the base grounding circuit for through 8 collector is fed to the long DL having taps with 300 ns steps resulting in a selectable delay of 300 ns x 7 taps 2100 ns
69. utputting the audio Doppler signal AUDIO BUFFER This consists of a 14 dB non inversion amplifier and the output is sent to the FFT CONT AUDIO PWB and used as the audio Doppler signal 2D730 133E THIS PAGE IS LEFT BLANK INTENTIONALLY 3 33A No 2D730 133E Signal bus Control from the exterior Control trom the 280 S H P5 19 HPF P6 19 7 19 AUDIO Buffer P17 19 FFT GAIN 16 19 17 19 FROM Two Two Two Two FFT CONT 0 FFT order gt order order gt order 2 AUDIO PWB PHASE HPF HPF HPF HPF s s 2 5 T a D a 5 e d am z PWB m TO EPO POEs o gt FFT CONT tt 5 z o tt P12 19 13 19 14 19 ADC P17 19 18 19 4 5128 O 5 e FFT P16 19 17 19 5 8 19 9 19 Two Two TWO Two FROM 90 FFT order order gt order AUDIO PHASE HPF HPF HPF HPF Buffer DETECTOR 5 17 19 AUDIO PWB s SIN TO 5 FFT CONT 5 5 AUDIO PWB B 828 E4 n al i 22 s es el 1 EGER 25 D 0 10140 to 2 30 10158 Figure 3 3 3 Block diagram for FFT I O DRAWING No 2MW30 101540 to 20020 29250 111 2D730 133E 3 3 3 1 2 Outline This PWB receives
70. verts separate video Y C to a composite video signal Y brightness signal synchronization signal C chroma color difference signal 4 Decoder C VIDEO S VIDEO S VIDEO RGB o Separates the composite video signal into separate video Y C PAL version does not support this function Converts separate video Y C into the RGB component signal 2D730 133E B 5 Outputting the video signal o Three types of RGB output color monitor EXT RGB separated into EXT1 2 at EXT CNN AUX RGB o Separate video Y C o Composite video signal for the VCR o Two types of black white video black white monitor B W VIDEO separated into 1 EXT2 at EXT CNN SEL VIDEO switches the black white signal and color signal with the toggle SW on the rear panel in INT mode a ear i ae MEE 3868 Switches the input video signal Menu selection Toggle SW selection Separation selection of the synchronization signal When the input is S VIDEO C VIDEO the C SYNC HD VD signals are separated Video signal conversion Encoder RGB S VIDEO S VIDEO C VIDEO Decoder C VIDEO S VIDEO S VIDEO RGB Note
71. viewed from software 2D730 133E 4 1 2 Organization of software 1 Relationships between tasks Figure 4 1 4 shows the relationships between tasks Processing is always performed via interrupts Therefore the ISR interrupt service routine is provided at the beginning of the flow of processing to branch processing to each task The term task refers to a related series of work procedures An OS operating system is used to control all software This system uses MONEX Monitor for EX as the operating system ISR includes SW probe VCR TALLY OF FI hlack white DSC hole pixel calculation completion color DSC hole pixel calculation completion and DSC error ISRs Initialization is performed at power ON and when the RESET SW is pressed SW processing is activated via panel processing from SW ISR when the SW on the panel or the pop up menu is pressed from probe ISR when a probe is connected disconnected or from VCR TALLY ISR when the status of the VCR is changed SW processing calls subordinate tasks using SW code and other information The image CONT is used for analysis of image data and the measurement CONT is used for analysis of measurement data in detail In other cases as well processes up to the broad classification of the SW code are performed by SW processing and detailed analysis of the SW code is performed by subordinate tasks Subordinate tasks of SW

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