SERVICE MANUAL
Contents
1. Ref No Part No Description Value F601 604 539006999944 EMI NFM60 SMD NFM60R J603 4428592510 WAFER BOX 1419 104 WAFER 10P J602 4428592520 WAFER BOX 1419 204 WAFER 20P J101 84410510626 CON FFC FPC 26 ZIP ANGLE WAFER 26P 601 4428590807 PIN HEADER 2X7PIN 27 pin header X602 3938000860 CRYSTAL 24 576MHz ATS 49U 24 576MHz X601 3938000830 CRYSTAL 33MHz ATS 49U 33MHz C528 C534 ie 534121000422 CAP RC 10UF 16V C689 0522 0555 4409210149 T CAP RG 100UF 25V 105 100 25 C537 834114700232 CAP SC 47UF 6 3V SAMWHA 47163 C680 682 34104700642 SC 47UF 25V SAMWHA 47125 C501 502 C508 509 a C515 516 523 3409247041 CAP AF RSG 47UF 25V 5 P 47125 Shot C554 10607 521229069401 IC DS2401P TSOC DALLAS 082401 quu g IC602 521235328101 SST28VFO40A 200 4C NH FALSH ROM PES re 1 604 821210009801 IC ALG265QL 4009 ROUTER TQFP100 QL4009 EE 24 10608 921102030402 IC NJM78LOSUA TE1 JRC 78105 o 451 10603 S21243862501 IC K4S64323C TCIL70 SRAM EO IC606 521285055402 IC TPS3801 SOT 323 TIA TPS3801 otm o 1 E 601 521213009601 IC ADSP21065LKS 264 66MH ADI adsp 21065 T 10614 521286282701 IC AKM4524 24BIT 96kHz CODEC AKM4524 1 6091 611 613 521101083204 IC NJM 5532 DMP 8 JRC 5532DD St2. 105 C W Lead Temperature Soldering 10 260 C SOIC Package Power 450mW Thermal Impedance 75 CAN Lead Temperature Soldering Vapor Phase 60 sec 215 C niemals T 220 C SSOP Package Power 450mW Thermal Impedance 115 C W Lead Temperature Soldering Vapor Phase 60 sec 215 C 15 566 5 5 ERES 220 C Figure 1 Load Circuit for Digital Output Timing Specifications m ORDERING GUIDE Linearity Error LSB Package Description Package Option AD7819YN Plastic DIP N 16 AD7819YR Small Outline IC R 16A AD7819YRU Thin Shark Small RU 16 Outline TSSOP Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability m PIN FUNCTION DESCRIPTION Reference Input 1 2V to Vo Vin Analog Input OV to GND Analog and
3. 762 2255 IN OR 0 30 or 00 co 53 54 ASS Y DRAWING AC INPUT 3 482 24 bit 1 80 bit DSP E E inter Yl GEQ 1231 D STEREO 31 BAND GRAPHIC EQUALIZER with HC LC amp LIMITER 2 8 o 2 2 5 m HIGHCUT Q REDUCTION 25 32 40 50 100 125 160 200 250 315 400 500 630 800 125K 16K 2K 25K 315 SK 16K 20K SEN 55 m A LOWCUT LIMITER z m o v 6 10 3 3 3 3 Description POWER SWITCH KNOB CONTROL PUSH KNOB PC GREEN LED LTL YELLOW LED LTL RED LED LTL KNOB SLIDE FRONT PANEL OP COVER MAIN CHASSIS AC INLET XLR JACK M JACK PHONE SWITCH SLIDE XLR JACK F 56 Part No 4648097810 048543991912 8543982210 2300032100 2300030100 2300031100 048545993011 046123694823 046121674711 046121674712 046121674713 046121674714 046121674715 444899741 440819461 443809731 46259955
4. 48 5 30100007231 RES TF 0 1 10W 2012 0 prm R614 R628 630 530100007121 RES TF 0 1 16W 1608 0 8503 504 R523 524 530321505121 RES 1 5K 1 16W 1608 15K 1 E OIM 8658 680 681 530101017231 RES TF 100 1 10W 2012 100 omm s R525 528 59511005121 RES MF 100K 1 16W 1608 100K 1 8548 550 R615 R617 619 R625 627 R652 R671 673 530101037121 RES TF 10K t 16W 1608 10K eei EUR R607 609 R536 R565 303320110120 RES MF 18 7K 1608 18 7K 1 R670 520101007121 RES TF 10 1 16W 1608 10 8507 5612 R515 520 MEE 2 c 8532 533 R539 540 530399305121 RES MF 3 3K 1 16 1608 3 3K 1 R561 562 R568 569 8543 544 R557 558 530396345120 RES 6 34K 1608 6 34K 1 Iz cwm 85 R551 554 R650 651 654 657 Re10 613 Re1e 930103907121 RES TF 39 1716W 1608 39 Pss R620 623 R601 606 gt FEES R513 514 R529 Bog R563 Rs72 930104707121 RES MF 47 1 16W 1608 47 e R547 530104797121 RES TF 4 7 1 16W 1608 47 fo EE 530 531 534 535 566 567 530318255120 RES MF 8 25K 1608 8 25K 196 A R537 R564 530321025120 RES MF 10 2K 1608 10 2K1 omm R541 545 R556 530318255120 RES MF 768 1608 768 1 ea LESS 2 R560
5. 100n 8 207 21 20 4 gt 206 IC116P 717100 1107 e T106 o o gt IC115P e 205 n 1 t 0210 C105P P C 104P 100n 100 T104 7912 17 10191 if gt 1105 975 9 cL T102 8 9 9 ano 975 279 10115 74LVC138 10116 74LVC138 T101 4 L e WACQ31 MOT13A WACO31 geld WWca31 13A31 1 im Vid _ M01134 M 13431 10 3 A31 LNdN EN MOTI3A WW Q31 13431 1 LNdN ELIT e mue 13411 6012 2 1 13A31 1 im C N3349 Wwe 038 WM Q31 2 1713 31 1naNi aio T 110 cau MEOS 1 T uononpey AMOR Le on dn 1 AM gt i 671 uononpay ug Amt aas Meat nnea31 HO 312 9 T 5 N3349 now 2190 T 103 N3389 WAcQ
6. 16 Lead Small Outline Integrated Circuit SOIC JEDEC MS 013 0 300 Wide Package Number M16B 74LV164 8 bit SERIAL IN PARALLEL OUT SHIFT REGISTER FEATURES Wide operating voltage 1 0 to 5 5V Optimized for Low Voltage applications 1 0 to 3 6V Accepts TTL input levels between Vcc 2 7V and Vcc 3 6V Typical output ground bounce lt 0 8V Vcc 3 3V 25 Typical output undershoot gt 2V 9 Vccz3 3V Tam 25 C Gated serial data inputs Asynchronous master reset Output capability standard lec category MSI m DESCRIPTION The 74LV164 is low voltage Si gate CMOS device and is pin and function compatible with the 74HC HCT 164 The 74LV164 is an 8 bit edge triggered shift register with serial data entry and an output from each of the eight stages Data is entered serially through one of two inputs Ds or Ds either input be used as active HIGH enable for data entry through the other input Both inputs must be connected together or an unused input must be tied HIGH Data shifts one place to the right on each LOW to HIGH transition of the clock CP input and enters into Qo which is the logical AND of the two data inputs Dsa Ds that existed one set up time prior to the rising clock edge A LOW on the master reset MR input overrides all other inputs and clears the register asynchronously forcing all outputs LOW QUICK REFERENCE DA
7. GEQ 1231D 1HU Rack 482 W x44 H x 280 D mm GEQ 2231D 2HU Rack 482 W x88 H x 280 D mm Due to continuous improvements specifications and design are subject to change without prior notice 22 ELECTRICAL PARTS LIST Ref No Part No Description Value Ref No Part No Description Value AC INPUT B D 4003482620 C427 3509101130 T CE SL 100PF 50V J 100p 433 436 3689103219 CAP X7R 10N 10 LS5 08 10n C402 403 3549222091 CAP DE7100F 222 2 2n 250 C428 C432 3689102219 CAP X7R 1N 10 LS5 08 in C404 405 3549472092 CAP DE7100F472MVAI KC 4 7n 250 310 317 3509331130 CAP CE SL 330PF 50V J 330P TR301 2658399940 COMON MODE CHOKE COILMEQ 2000 CN401 402 4428595005 LW5267 LWB0640 2 5MM 05P WAFER P1P3P14P27 _ 4465998210 TERMINAL 250 PCB TERMINAL CN305 CN403 CN405 4428595002 LW5267 LWB0640 2 5MM 02P WAFER 2P 4458999110 FUSE CLIP 520 FUSE CLIP CN301 304 CN406 4428595003 LW5267 LWB0640 2 5MM 07P WAFER 3P CN404 4428595007 CON WAFER A2505WV2 07P WAFER 7P FRONT B D GEQ 2231D 4003482400 F402 3008609980 EMI FILTER 2200PF 22 IC115 116 521225165401 IC 138 SOP16 PHI TALCX138 0301 30 0401 402 2058100996 DIODE RECTIFIER LT1N4006 4007 1 4006 6110 140 6142 197 0405 0406 202 207 209 211 535101045039 100 10 63V 2012 100n 0407 2058304100 DIODE IN4148M 1N 4148
8. X X7 10114 74HC4051 VCC GND XO VSS X1 INH X2 X3 A X4 X5 X6 P62 Gain 1 P63 Gain B X P64 Low Cut 1 X7 Low Cut R P69 LIMIT R 19 1K e AW R203 1K R204 wr e 1000 R205 R208 P67 High_Cut_R VR166 10KB 1K 210 P32 25Hz_R P33 32Hz_R P34 40Hz_R P35 50Hz_R P36 63Hz_R P37 80Hz_R P38100Hz_R P39125Hz_R wie 12 100n pu R135 R136 wie AMY 0133 100n 1K R140 100n A 1 2 cio 21521 SVR103 10KB 100n 2 10KB 310KB 2 SVR104 10KB SVR105 30KB E SVR106 310KB SVR107 3 10KB SVR108 310KB P40160Hz P41200Hz P42250Hz R 43315 2 P44400Hz_R P45500Hz_R P46 630Hz_R 1K R142 3 P47 800Hz_R R143 1K 137 100n 9 R144 K 138 100n IM K W 1K AW 1K AW 1K AW R145 R147 R148 R149 1 1 2 C120 10KB 2 1 1 2 54 1 1 1 1K AN R150 100n 09 310 310KB SVRI3 310KB e SVR112 310KB SVR114 3 10KB 310KB 5 2 2 lt 5
9. 405 ol 429 1 100 R406 R407 3 IN 2 our 390 1x 3 48 1 47K 1 x Io F402 8 CAUTION Resistors R401 and R402 only for LM 317 T For LT1584 CT3 3 only a wire or 0 ohm in pos R402 is required R401 is obsolete R408 1405 LM311N C428 100 ix R415 AW 470 1 FOR TQ2 12V CN406 FROM CN501 KRC103M KRC103M CFLAG6 42 DGND CFLAG4 NC SHT D 1 4 FRAME96 C IRQ2 880 C601 22 1 24 SH R602 39 SH RX1B IRQ1 A 6015 SH TX1A 0 qp cesa 222 ADSP21065 SH TXIB GND VCC GND vcc C_ IRQO 8603 39 GND SH RX2A GND vcc mou GND 22P SH TX2A GND R607 39 GND VCDSP 4 AN SH TX2B GND 125 CLK48 GND R608 GND 1 FRAME48 GND GND VCC GND 125 96 GND lt FREE lt 0 2401 10K ABCFLAG1 FRAME96 CSO DTA FLAGO 97 FLAG1 98 FLAG2I99 FALG4I38 65137 FALG6 36 FLAG7IS4 FLAGBBO FALGS 9 FALG10 8 FLAG11 V6 CADR 00 23 311 1 601 ADSP 21065 Share C_SDCLKO CFLAG3 R C SDCL
10. 101 102 835102204321 CAP CL 22PF 50V J 1608 22 403 404 2058100890 DIODE RECTIFIER IN5401 1N5401 F101 539006999944 EMI 60 5 0 NFM6OR C426 3409210033 T CAP E SE 10UF 16V 4 5 10 16 C201 C208 534121000422 CAP RC 10UF 16V 10u C430 431 3409210059 RG 10UF 50V 105C 10 50 1 106 114 521225160201 IC 74HC4051 SOIC 051 414 415 C424 3408210233 RSD 1000UF 16V SNAP 10 1000 16 101 105 120 521224147701 IC 74LV164 SOT108 1 74LVC164 410 411 3419533265 HC 3300UF 35V 3300 85 D101 003D142 522400502001 DIODE BAW56 50123 56 C422 3419568238 CAP AF HM 6800UF 16V25PLUG 6800 6 D6 D8 13 D104 111 FB301 308 2648609900 FERITE BEAD H5B FERRITE D12012 D128 p40 2309770100 LED BL S4548 TBS22A 1 8MM LED1 8MM D116 117 0132 133 2300031100 LED LTL 1CHY LITEON LED3MM YELLOW FS402 403 5508212233 FUSE NB 20MM 1A 250V U C 1AT 014 0113 D123 124 FS404 4458999110 FUSE CLIP 590 FUSE CLIP 0114 D129 131 2300032100 LED LTL 1CHG LITEON LED3MM GREEN JX302 JX304 4408194510 XLR JACK F E303A0070N XLR JACK F D115 D141 JX301 JX303 4408194610 XLR JACK M E403A0090N XLR JACK M 0126 127 D118 119 2300030000 LED LTL 1CHEE LITEON LEDOMM RED JK301 304 4408194210 XLR JACK M E503A0130N JACK PHONE 0112 0125 10405 2168640979 IC LM311N 018 FSC LM311N R102 R133 30101017121 RES 100 1 16W 1608 100 1 402 2168640987 IC 7915 SAMSUNG 7915 104 119 9211 2021 1404 2118089
11. 5 00384 00383 5014 plastic small outline package 14 leads body width 3 9 mm AD7819 2 7V to 5 5V 200 kSPS 8 bit SAMPLING ADC m FEATURES 8 Bit ADC with 4 5 us Conversion Time On Chip Track and Hold Operating Supply Range 2 7V to 5 5V Specifications at 2 7V 3 6V and 5V x 1096 8 Bit Parallel Interface 8 Bit Read Power Performance Normal Operation 10 5mW Vo 3V Automatic Power Down 57 75uW 1kSPS Voo 3V Analog Input Range OV to Vre Reference Input Range 1 2V to Voo FUNCTIONAL BLOCK DIAGRAM AGND VREF CONTROL LOGIC BUSY CS RD CONVST m GENERAL DESCRIPTION m DIMENSIONS inch dimensions are derived from the original mm dimensions The AD7819 is a high speed microprocessor compatible 8 bit analog to digital converter with a maximum throughput of 200kSPS The converter operates off a single 2 7V to 5 5V supply and contains a 4 5 5 successive approximation A D converter track hold circuitry on chip clock oscillator and 8 bit wide parallel interface The parallel interface is designed to allow easy interfacing to microprocessors and DSPs Using only address decoding logic the AD7819 is easily mapped into the microprocessor address space When used in its power down mode the AD7819 automatically powers down at the end of a conversion and powers up at the start of a new conversion This feature significantly reduces the powe
12. CHASSIS MAIN 612167 CHASSIS FRONT 612228 PANEL FRONT 860296 1 PARTS NAME PARTS NUMBER Q TY REMARK 00 O O O O O O 1 O1 O IN gt 2 51 52 5 4 6 810934 0065 EW PM2x6Y 801912 0061 EW BM 5 20 800913 0203 SCREW PM 4X8N 809599 4710 2BTC 3X8B 810923 0083 EW 800913 0063 3 2 2 3 EW_ 3BTC3x6B 810933 0063 EW PM2x3Y 8019 0031 EW FM2x8B 802912 0083 EW FM3x8B 8029 0083 PART NUMBER 07 REMARK 462898 0110 T INSULATION 670599 3110 056335999520 400348 2610 400348 1200 PUT PCB 400348 2620 R 400348 2600 400348 2700 PCB 400348 2500 D DOMES CORES 430899 73 TRANS 282805 800 444899 73 L KNOB 854399 191 SWITCH 464809 781 ACK F 440819 45 SWITCH 462599 55 650595 971 443809 421 440819 46 ED LIMITER 2DOT 854598 55 P COVER 612569 482 ED LIMITER 854599 369 OLDER BRACKET 650595 33 KNOB SLIDE 854599 30 KNOB PUSH 854398 221 CHASSIS MAIN 612167 46 CHASSIS FRONT 612228 98 PANEL FRONT 860296 461 PARTS NAME PARTS NUMBER REMARK
13. P10 200Hz L 250Hz L P12 315Hz L P13 400Hz P14 500Hz P15 630Hz_L C166 R173 Aw e P8 125Hz L 100n Ke wie P9 R174 R175 1K C169 R176 R177 C172 R179 C173 R180 IES C167 016 100 1K AW 100n ES 1 A e 2 A e P A e 1 2 1 2 1 2 1 2 1 2 1 2 E x E 10KB VRM2 SVRI43 SVRI44 310KB 310KB SVR145 SVRI46 3 10KB E SVR148 30KB SVR149 310KB P16 800Hz L P17 1KHz 1 P18 1 25KHz_L P19 1 6KHz_L P202KHz L 21 P21 2 5KHz L P22 3 15 2 P23 4KHz_L 1K R181 Aw e R182 1K AW R183 R184 1K W 100 178 1K AW R185 1K W 1K R187 R188 VR150 10KB 2 1 2 2 2 2 1 2 SVR151 310KB 310KB e lt SVR152 SVRI5 3 10KB 5 PSVR154 3 10KB e SVR155 310KB e SVRI5 5 10KB e 10KB e 6 5 157 P25 6 3KHz L P26 8KHz P28 12 5KHz L 20Hz 182 100 R189 P we 24 5KHz js 100 i n R190 C184 Ee 100n I E 1K AW R191 1K e P27 10KHz L 1K 92 R1 R193 R194 LP wie 29 16KHz_L 1K P e 30 20KHz L C18
14. TSSO IN OUT Y6 OUT IN Y7 Y5 INH Vee GND IN OUT IN OUT Top View m TRUTH TABLES ON Channel Irr 0 gt eee Mm ee eee TLELI pF LOGIC DIAGRAMS CHANNEL IN OUT BINARY TO LOGIC 10F8 OUT IN LEVEL CONVERSION DECODER WITH INHIBIT m PHYSICAL DIMENSIONS inches millimeters unless otherwise noted 0 386 0 394 9 804 10 00 0 228 0 244 5191 6198 LEAD NO 1 IDENT 0150 0457 3 810 3 988 0 010 0 020 0 053 0 069 0254 0508 45 1 346 1 753 0 004 0 010 8 0 102 0 254 0 016 0 050 0 014 0 020 406 1 270 0 356 0 508 0 008 0 010 0 406 1 270 0 203 0 254 TYP ALL LEADS 0 004 TYP ALL LEADS 0408 10 102 10 203 MIGA REV Hj ALL LEAD TIPS 16 Lead Small Outline Integrated Circuit SOIC JEDEC MS 012 0 150 Narrow Package Number M16A 0 3977 0 4133 10 10 10 50 LEAD NO 1 IDENTIFICATION 0 2914 0 2992 0 3940 0 4190 10 00 10 65 0 0158 0 0200 0 350 0 508 0 010 0 029 0 009 1 0 0125 9 0 0926 0 1043 459 X 700255075 ALL LEADS 1 foe SEATING 1 0 004 PLANE L m 2 1 035 ALL LEAD TIPS ALL LEADS 0 0160 0 0500 40 137 ALL LEADS M16B REV 0 0040 0 0118 0 1 0 3
15. X2 A X4 X5 X6 B C X X7 IC106 74HC40 51 vcc GND VSS Xi INH X2 X3 QB QC QD B QE 10 A X4 x5 X6 B C X X7 1C107 74HC4051 GND X0 VSS X1 INH X2 BYPASS 1 101 74LV164 KEY OUT J KEY 33 25 LED OUT 23 21 19 17 LED KEY OUT KEY 15 7113 10101 10u 1000 5 VCDSP 10110 74LVC138 A X4 x5 X6 B C X X7 IC108 74HC4051 VCC GND VSS Xi PO 20Hz P3 40Hz 1K e AW 1K 119 100n R123 C122 1008 R126 C126 1 3 2 2 1 2 1 1 3 sos shs 3 2 2 lt sve 5 3 3 a o 28 lt ME P10 200Hz 250Hz 9 RI33 1K AW R134 1K AWW C131 00 8135 AW 12 315Hz C132 R136 1K P am 13 400Hz 0133 ux x P14 500Hz C134 1005 RISB ik P15 630Hz 1 ks 2 2 1 2 2 x 2 2 3 e lt ISVRI09f SVR 110 TOK SVR
16. 5W FN 390 1 J101 544410510626 CON 26 ZIP ANGLE WAFER 26P R402 3004240953 RES CF 240 1 5W FN 240 1 C157 C162 534121000632 CAP RC 10UF 25V 10 R413 3003470953 RES CF 4 7K 1 5WFN 47K 1 1 105 109 521225160201 IC 74HC4051 SOIC 74HC4051 R407 3002470953 RES CF 47K 1 5W 47K 1 01 103 521224147701 IC 741 164 SOT108 74LV164 R415 3004470953 RES 470 1 5W FN 470 1 D117 118 522400502001 DIODE 56 SOT 23 BAWS6 R405 3009564973 RES CF 560K 1 5W 560K 01 30100 102 520510482001 LED BL S4548 TBS22A 1 8MM RLY301 302 5528007800 RELAY AZB50 12 DC12V RELAY DC12V 003 104 110 112 2300032100 LED LTL 1CHG LITEON LED3MM GREEN SW301 302 4625995510 SW SLIDE SSAF122NB011 9MM SW SLIDE BHN D109 D105 107 S401 4648099310 POWER SWITCH H8500VB POWER SW D115 116 2300030000 LED LTL 1CHEE LITEON IC406 2128612400 IC TLA31CLP TO92 TIA 1431 0113 114 2300031100 LED LTL 1CHY LITEON LEDSMILVELLON 0401 402 2008405980 T KRA103M AT KRC103M R118 R155 530101017121 RES TF 100 1 16W 1608 100 R101 116 530101517121 RES TF 150 1 16W 1608 150 SHT B D 4003482700 R100 R123 154 10605 521281169601 IC AD7819 8 SAMPLING ADC AD7819 R157 160 59010102121 OW TUR 26620 62 522300502001 DIODE 545 SOT 23 BATS4S 101 103 4628980110 PUSH SWITCH PUSH SW 529 530 535 536 0101 520510482001 TR MMBT4124 507 23 mmBT4124 C538 542 C545 549 SVR101 132 3238010324 VR 852011106 1
17. Processor Execution Performs Transfers Between Internal RAM and Host Internal RAM and Serial Ports Internal RAM and Master or Slave SHARC Internal RAM and External Memory or I O Devices External Memory and External Devices Host Processor Interface Efficient Interface to 8 16 and 32 Bit Microprocessors Host Can Directly Read Write ADSP 21065L IOP Registers Multiprocessing Distributed On Chip Bus Arbitration for Glueless Parallel Bus Connect Between Two ADSP 21065Ls Plus Host 132 Mbytes s Transfer Rate Over Parallel Bus Serial Ports Independent Transmit and Receive Functions Programmable 3 Bit to 32 Bit Serial Word Width 25 Support Allowing Eight Transmit and Eight Receive Channels Glueless Interface to Industry Standard Codecs Multichannel Mode with y Law A Law Hardware Companding Multichannel Signaling Protocol m BLOCK DIAGRAM CORE PROCESSOR DUAL PORTED SRAM INSTRUCTION TWO INDEPENDENT CACHE DUAL PORTED BLOCKS 32 48BIT PROCESSOR PORT VO PORT 1 ADDR DATA DATA DATA EXTERNAL DAG1 DAG2 PROGRAM PORT 8x4x24 SEQUENCER 2 5 2 E SDRAM 24 PM ADDRESS BUS ifi t 4 48 2 X ADDR Bus A 32 DM ADDRESS BUS MULTIPROCESSOR INTERFACE 48 PM DATA BUS RM N pata BUS 40 DM DATA BUS T PORT da JTAG TEST
18. Support for Eight Simultaneous Receive and Transmit Channels m KEY FEATURES 66 MIPS 198 MFLOPS Peak 132 MFLOPS Sustained Performance User Configurable 544 Kbits On Chip SRAM Memory Two External Port DMA Channels and Eight Serial Port DMA Channels SDRAM Controller for Glueless Interface to Low Cost External Memory 966 MHz 64M Words External Address Range 12 Programmable I O Pins and Two Timers with Event Capture Options Code Compatible with ADSP 2106x Family 208 Lead MQFP or 196 Ball Mini BGA Package 3 3 Volt Operation Flexible Data Formats and 40 Bit Extended Precision 32 Bit Single Precision and 40 Bit Extended Precision IEEE Floating Point Data Formats 32 Bit Fixed Point Data Format Integer and Fractional with Dual 80 Bit Accumulators Parallel Computations Single Cycle Multiply and ALU Operations in Parallel with Dual Memory Read Writes and Instruction Fetch Multiply with Add and Subtract for Accelerated FFT Butterfly Computation 1024 Point Complex FFT Benchmark 0 274 ms 18 221 Cycles 544 Kbits Configurable On Chip SRAM Dual Ported for Independent Access by Core Processor and DMA Configurable in Combinations of 16 32 48 Bit Data and Program Words in Block 0 and Block 1 DMA Controller Ten DMA Channels Two Dedicated to the External Port and Eight Dedicated to the Serial Ports Background DMA Transfers at up to 66 MHz in Parallel with Full Speed
19. amp EMULATION gt o gt BLOCK 0 BLOCK 1 DMA REGISTERS CONTROLLER MEMORY MAPPED 2 Rx 2Tx CONTROL SPORT 2 STATUS FS amp 2 Rx 2Tx SPORT 1 25 VO PROCESSOR 14 m DESCRIPTIONS ADSP 21065L pin definitions are listed below Inputs identified as synchronous S must meet timing requirements with respect to CLKIN or with respect to TCK for TMS TDI Inputs identified as asynchronous A can be asserted asynchronously to CLKIN or to TCK for TRST Unused inputs should be tied or pulled to VDD or GND except for ADDRes o DATAsi 0 FLAG11 0 SW and inputs that have internal pull up or pull down resistors CPA ACK DTxX DRxX TCLKx RCLKx TMS and pins be left floating These pins have a logic level hold circuit that prevents the input from floating internally I Input S Synchronous P Power Supply O D Open Drain O Output A Asynchronous G Ground A D Active Drive T Three state when SBTS is asserted or when the ADSP 2106x is a bus slave External Bus Address The ADSP 21065L outputs addresses for external memory and peripherals on these pins In a multiprocessor system the bus master outputs addresses for read writes of the IOP registers of the other ADSP 21065L The ADSP 21065L inputs addresses when a host processor or multiprocessing bus master is reading or writing its IOP registers DATAs1 0 Externa
20. on the chain The 14 pin 2 row pin strip header is keyed at the Pin 3 location you must remove Pin 3 from the header The pins must be 0 025 inch square and at least 0 20 inch in length Pin spacing should be 0 1x0 1 inches Pin strip headers are available from vendors such as 3M McKenzie and Samtec GND EMU KEY NO PIN CLKIN OPTIONAL BTMS TMS BTCK TCK RESET BTDI GND TOP VIEW Figure 3 Target Board Connector for ADSP 2106x EZ ICE JTAG Header m 208 LEAD MQFP PIN CONFIGURATION m 208 LEAD MQFP PIN Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name VDD DATA28 ADDR17 DATA3 DATA29 ADDR16 DATA4 GND ADDR15 DATA5 VDD VDD 208 LEAD MQFP PIN GND VDD ADDR14 DATA6 DATA30 ADDR13 DATA7 DATA31 ADDR12 DATA8 FLAG7 VDD VOD ven VDD GND GND onp GND FLAG6 ADDR11 ges VDD FLAGS ADDR10 Tenn TCLKO TMS DATA9 FLAG4 ADDR9 GND DATA10 GND GND m TDO DTOB DATA11 VDD VDD pud GND VDD ADDR8 n WR DATA12 NC ADDR7 para GND RD DATA13 ID1 ADDR6 VDD FLAG6 GND NC IDO GND DTIA GND DT1B FLAG7 VDD NC EMU GND PWM_EVENT1 DATA31 GND DATA30 GND DATA14 TDO ADDR5 EVENTO ADSP 21065L end TOP VIEW VDD REDY VDD TRST ADDR4 Not to Seale VDD DATA29 DT1A SW GND TDI ADDR3 CLKIN Au DT1B CPA DATA15 TMS VDD Mes vue PWM EVENT1 VDD DATA16 GND VDD SNO nar
21. 0KB SVR 10KB C606 630 C650 651 535101045029 X7R 100N 10 63V 2012 100n SVR133 135 3208010324 VR RKO9K11330CC9 10KB VR 10KB 0655 659 C670 677 J01 544410510626 CON FFC FPC 26 ZIP ANGLE CON 26P C683 684 4355735900 FLAT CABLE 1 0 80MM 26P ASSY C654 535101025039 CAP NPO 1N 10 63V 2012 1N C505 C507 C510 C512 535101014331 100PF J 08052012 100 NPO DIP S W B D 4003481200 C531 532 535201005020 NPO 10 10 63V SMD 10p NPO DS701 4698099610 SW DIP 4 WAY JEC DIP SW C601 603 535102204339 CAP CL 22PF 50V J 2012 22 4355738616 CON ASS Y 360MM ASSY C604 525102704321 27PF 50V J0603 1608 27P POWER IN OUT B D 4003482600 4 1 935203314030 NPO 330P 5 50V 2012 330P IC401 2168640988 IC 7815 SAMSUNG 7815 C524 C527 C550 535203324030 NPO 3 3N 5 50V 2012 4308991810 AC CORD DOM 12A INLET AC INPUT C553 C506 C511 BD401 2058100976 DIODE BRIDGE KBP202G KBP203G 2 0518 521 C556 559 535103304321 CAP CL 33PF J 1608 301 303 C307 309 3609104120 MA 0 1UF 100V J C605 412 413 416 417 3689104219 CAP X7R 100 10 63V LS5 08 100n CN501CN503 506 4428595003 LW5267 LWBO640 2 5MM 03P WAFER 3P C423 C425 C420 CN502 4428505007 LW5267 LWBO640 2 5MM 07P CON 7P 23 AND BOTTOM VIEW OF BOARD
22. 1 44381937 e PERE m lt N LIFT 2 818 WE LIFT GND 482 O inter Yl GEG 2231 D DUAL 31 BAND GRAPHIC EQUALIZER with HC LC amp LIMITER ourcue 20KO REDUCTION e N A 4 cur E v M so oem 25K 25K EXXPEJ 42 y 57 53K 20K SENS No Description Part No POWER SWITCH 4648097810 048543991912 8543982210 2300032100 2300030100 2300031100 048545993011 048602964611 046123694823 046121674611 046121674612 10 MAIN CHASSIS 046121674613 046121674614 046121674615 4448997410 4408194610 4438097310 4625995510 XLR JACK F 4438193710 o 20 N o ES 5 58
23. 10 defines the operation for the SDRAM to perform SUGGESTED COMPONENTS FOR 30 MHz OPERATION ECLIPTEK EC2SM 33 30 000M SURFACE MOUNT PACKAGE ECLIPTEK EC 33 30 000M THRU HOLE PACKAGE C1 33pF C2 27pF NOTE C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1 CONTACT CRYSTAL MANUFACTURER FOR DETAILS Figure 1 30 MHz Operation Fundamental Mode Crystal SUGGESTED COMPONENTS FOR 30 MHz OPERATION ECLIPTEK EC2SM T 30 000M SURFACE MOUNT PACKAGE ECLIPTEK ECT 30 000M THRU HOLE PACKAGE C1 18pF C2 27pF C3 75pF L1 3300nH Rs SEE NOTE NOTE C1 C2 C3 Rs AND Li ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1 CONTACT MANUFACTURER FOR DETAILS Figure 2 30 MHz Operation 3rd Overtone Crystal SDRAM Write Enable In conjunction with CAS RAS MSx SDCLKx and sometimes SDA10 defines the operation for the SDRAM to perform O T SDRAM Data Mask In write mode DQM has a latency of zero and is used to block write operations 5 SDRAM 2x Clock Output In systems with multiple SDRAM devices connected in parallel supports the corresponding increased clock load requirements eliminating need of off chip clock buffers Either SDCLK or both SDCLKx pins can be three stated m TARGET BOARD CONNECTOR FOR EZ ICE PROBE The ADSP 2106x EZ ICE emulator uses the IEEE 1149 1 JTAG test access port of the ADSP 2106x to monitor and control the target board processor during emulation The EZ ICE probe requires the ADSP 2106x
24. 115 SVR116 3 10KB 3 2 SVR167 1 10KB 2 lt SVR168 1 10KB 2 4 SVR169 310KB P48 1KHz_R E ad N a P501 6KHz_R P51 2KHz_R P52 2 5KHz_R P53 3 15 2 P544KHz P555KHz 1K C144 111 4 R151 0122 100n P566 3KHz R SVR123 310KB SVR126 P61 20KHz_R 100n 100n 100n 100n R198 1 mo P578KHz C154 8199 1K ant 58 10KHz_R C155 R200 1K ww P5912 5KHz_R C156 R201 e P60 16KHz_R C157 H R202 VR127 SVR128 10KB 1 2 2 1 2 1K e AW ES 310KB 310KB e lt SVR131 SVR132 310KB e C124 100n C125 100n lt 70 C126 100n PO 20Hz_L P1 25Hz_L P2 32Hz_L 40 2 1 P4 50Hz cil P5 63Hz L P6 80Hz P7 100Hz_L 100n 1K R165 C159 e R166 R167 1K C161 e 100n e 100n e A e 100n 1K AW R170 C164 R171 C165 R172 1 1 2 2 2 1 2 9 1 2 9 1 2 lt SVR136 SVR135 310KB SVR137 310KB SVR138 3 10KB e SVR139 310KB e SVR140 3 10 e 310KB e 160Hz L
25. 30 114100 SSVdA8 1193 3304 114405 LHI 39V3431NI 931 9 H LIMS 39V3343LNI 3313A0ILN310d gt X lt lt os amp WIT 10197H 9IH 103 401 I ONYE 32018 1620 0193 300 33 5 5 13 1N9 H9IH 1n3 An01 LAdNI 32 GEQ 1231D FRONTB D VCDSP Q101 mmBT4124 SCHEMATIC DIAGRAM Range switch default 6dB When press Range switch D3MM GREEN Reduction 6 LED1 8MM LED1 8MM ED1 8MM 74LV164 QE 10 06 12 TIN LED_OUT LED_CLK B_LCLK QF 1 9 CLR QH LED3MM RED Reduction 3 RED 0106 LED3MM 36 LEVEL 12 LEVEL 24 Reduction 1 NPUT LEVEL 12 NPUT LEVEL 0 104 INPUT LEVEL 150 GREEN LED3MM AW 7 150 LED3MM RED 109 150 RED R mte D110 15 LED3MM_GREEN LED3MM GREEN 8113 4 d 013 150 LED3MM_YELLOW R 0114 150 LED3MM_YELLOW 114 NPUT 3 10103 74LV164 4 0 5 ol CLR QH 0115 RED LED3MM Q102 mmBT4124 74LVC164 R120 75 We RED 5 LED3MM 6 4 150 10105 74HC40 51 GND vss X1 INH
26. 31 1n9 ubi c 90 T 9 Had giyo M ubiH 912 T SSVdAB8 i 2517 20121 SSVdA8 vOlol T kuo 037 7014 T mmBT4124 1298 051 ve mmBT4124 4 mmBT4124 Range switch default 6dB When press Range switch zi GEQ 2231D FRONT B D 1 2 36 35 GEQ 2231D FRONT B D 2 2 106 74HC4051 vcc GND VSS X1 INH x2 X3 A X4 x5 X6 B C X 07 74HC4051 X7 x1 X2 X3 X4 x5 X6 X1 X2 X3 X4 x5 X6 X7 74HC4051 IC109 GND VSS X1 INH X2 X3 A X4 x5 X6 B C X X7 37 C127 100n 74HC4051 VCC GND XO VSS X1 X2 INH X3 A X4 x5 B X6 X7 X 1 111 74HC4051 LIS GND XO VSS X1 X2 INH X3 A X4 x5 B X6 X7 X 2 74 4051 VCC GND XO VSS XI x2 INH X3 A X4 B x5 X6 X7 X 10113 74HC4051 GND XO VSS X1 INH 2 X3 A X4 x5 X6 B
27. 330P T NPO Vv AM R545 AW 768 1 R546 1 C553 330P NPO IC613B 2 0552 3 3 70551 3 30 0550 L 1 8557 6 54K 1 AINL AINR VCOM C529 1100 26 29 28 Qu AOUTR AKM AK4524 24Bit 96KHz Codec 100n X7R 11 LRCK 17 8554 39 FRAME96 8553 39 125 CLK96 BICK HS AW R552 SH_RX2A SDTIP ______5 TX2A 20 R549 M S 1 WW 9 5 C530 100N X7R X602 0 124 576MHz 50 10K EXPLODED CIEW OF CABINET amp CHASSIS MACHANICAL PARTS LIST PM2x6Y BM 3X20B CREW PM 4X8N 2872 3X8B BM3x6N 3BTC3x6B PM2x3Y FM2x8B EW FM3x8B PART NAME REMARK SW PUSH 462898 0110 HEET INSULATION 670599 3120 OOT 673599 1210 T PCB 400348 2610 S W PCB 400348 1200 PUT PCB 400348 2620 ER PCB 400348 2600 HT PCB 400348 2700 T PCB 400348 2500 DOME3 CORES 430899 731 R TRANS 282805 LET 444899 ROL KNOB 854399 19 R SWITCH 464809 ACK F 440819 DE SWITCH 462599 JACK 650595 ONE JACK 443809 R JACK M 440819 D LIMITER 2DOT 854598 P COVER 612369 D LIMITER 854599 HOLDER BRACKET 650595 KNOB SLIDE 854599 KNOB PUSH 854398
28. 47 ea 8542 R546 R555 Eres dd R559 530332110120 RES MF F1608 11K 1 go ea 8505 506 R521 522 5 nes D601 2308660126 LED TLM 2100 RED SOT 23 SMD 2100 2 omm a T601 602 4628988710 SW TACT THHV501BAA SW LL n E ERIT 544410013632 SOCKET IC PLCC 32 SMD SOCKET Bend 4408194800 CON JUMP CON K CN508 4428595005 LW5267 LWB0640 2 5MM 05P WAFER 5P e 5 ier p D faite NOEL 1 5 o I pee Eus B m ness Es pire YE EE omm fio 24 25 4003482400 FRONT B D GEQ 2231D 26 3 5 2 i0 G0 OC G DO Q0 G0 o 09 910 OTE Ge IO GO 00 00 60 00 CO 00 00 GO OG 00 CO OCC G b SI mE EN 73 0 4005482700 iL TOP 6 ER
29. 8 R195 C189 1 R19 AM 100n 6 VR158 10KB 1 2 1 2 1 2 2 1 2 1 2 E 1 2 E SVR159 310KB lt SVRI60 310KB SVR161 310KB 8162 10KB SVR163 3 10KB SVR164 SVR165 310KB 38 IN OUT B D CN301 TO CN503 INL GND Gl 14 SW301 A 0 00 GND LIFT IN T CN302 FROM CN505 OUTL 2 CND Bl OUTPUT SW302 A ooo GND LIFT OUT CN303 TO CN504 INR D 6l DS701 SW301 B SW 4WAY 8P GND LIFT IN nu FB307 CN304 FROM CN506 OUTR 2257 2 GND Bl jJ JUMPER m default JP302 JP304 2 3 connected closed CN305 FROM CN403 JP301 JP303 1 2 connected open nus CATHODE TL431 39 40 POWER D SERVICE INFORMATION TRESISTANCE VALUES ARE INDICATED IN OHMS UNLESS OTHERWISE SPECIFIED 1 000 1 000 000 2 VALUES ARE SHOWN IN MICROFARADS UNLESS OTHERWISE NOTED P MICRO MICROF ARADS VOLTAGES ARE REFERED TO GROUND UNDER THE FOLLOWING CONDITIONS DC NO SIGNAL EXCEPT WHERE INDICATED AC RMS 4 PRECAUTION A ALL COMPONENTS MARKED MUST BE REPLACED ONLY WITH ORIGINAL SPECIFIED BY THE M
30. 926 IC LM 350T LM350T nog 228 30101517121 RES TF 150 1 16W 1608 150 n R101 R103 407 4235007210 GND TERMINAL POWER GND TERMINAL 135 158 R165 210 30101027121 RES TF 1K 1 16W 1608 1K P32 P36 P38 39 R230 R243 P4142 7101 108 4628980110 PUSH SWITCH PUSH SW P401 404 4465998210 TERMINAL 250 PCB TAB TERMINAL TAB Q101 103 520510482001 TR MMBT4124 SOT 23 mmBT4124 SVR101 116 JP301 304 4428590423 PIN HEADER 2 152 54 pinheader 3p SVR119 132 3038010324 VR RS20111D6 10KB ALP SVR 10KB PTI PT SVR134 167 R408 3004100953 RES CF 100 1 5W FN SMA 4000 100 1 SVR168 173 3208010324 VR RKO9K11330CC9 10KB ALP VR 10KB R403 R418 3001100953 RES CF 100K 1 5W 400K 1 544410510626 FFC FPC 26 ZIP ANGLE CON 26P R417 R425 3005100953 RES CF 10 1 5WFN 101 4355735800 FLAT CABLE 1 0 140MM 26 ASSY R420 3002150953 RES CF 15K 1 5W 15K 1 R423 3003220953 RES CF 22K 1 5WFN 22K FRONT B D GEQ 1231D 400382500 8409 3003274953 RES CF 2 7K 1 5W F N 27K 1 1 110 521225165401 IC 74LCX 138 SOP16 FSC 7ALCX138 410 411 R416 R419 3002220953 RES CF 22K 1 5W F N 22K 1 C108 112 C117 156 R421 158461 C163 535101045039 CAP 100N 10 63V 2012 1001 R404 3003330953 RES CF 3 3K 1 5W F N 3 3K 1 C100 101 535102204321 CAP CL 22PF 50V J 1608 22 R406 3003348953 RES CF 348K 1 5WFNSMA 4000 348K 1 F101 539006999944 EMI NEM60 SMD R401 3004390953 RES CF 390 1
31. ADSP 21065L bus master Chip Select Asserted by host processor to select the ADSP 21065L Host Bus Acknowledge The ADSP 21065L deasserts REDY to add wait states to an asynchronous access of its internal memory or IOP registers by a host Open drain output O D by default can be programmed in ADREDY bit of SYSCON register to be active drive A D REDY will only be output if the CS and HBR inputs are asserted DMA Request 1 DMA Channel 9 DMA Request 2 DMA Channel 8 DMA Grant 1 DMA Channel 9 DMA Grant 2 DMA Channel 8 Multiprocessing Bus Requests Used by multiprocessing ADSP 21065L s to arbitrate for bus mastership An ADSP 21065L drives its own BRx line corresponding to the value of its 102 inputs only and monitors all others In a uniprocessor system tie both BRx pins to VDD Multiprocessing ID Determines which multiprocessor bus request BR BRz2 is used by ADSP 21065L ID 01 corresponds to 10 10 corresponds to ID 00 in single processor systems These lines a System configuration selection which should be hard wired or changed only at reset Core Priority Access Asserting its CPA pin allows the core processor of an ADSP 21065L bus slave to interrupt background DMA transfers and gain m CLOCK SIGNALS Test Mode Select JTAG Used to control the test state machine TMS has a 20kQ internal pull up resistor The ADSP 21065L can use an external clock or a crystal See CLKIN pin descriptio
32. ANUFACTURER INTER M CORPORATION AND INSTALLED AS THE ORIGINAL SPACERS AND POSITIONED AWAY FORM ADJACENT COMPONENTS WHERE APPLICABLE SOLDERING MUST BE DONE IN A PROFESSIONAL MANNER USING SOLDER WHITE RESINE CORE ONLY C ALL COVERS SHIELD AND INSULATING SPACERS MUST BE REPLACED BEFORE RETURING APPLIANCE TO CUSTOMER D A DAMAGE POWER SUPPLY CORD MUST BE REPLACED BEFORE RETURING TO CUSTOMER E DIELECTRIC TEST CONSISTING 120V AC 80HZ IS TO BE APPLIED BETWEEN BOTH BALDES OF THE POWER SUPPLY CIRD ATTACHMENT PLUG THE EXPOSE CONDUCTIVE SURFACE OF THE APPLIANCE FOR A PERIOD OF NOT LESS THAN ONE SECOND BEFORE RETURING APPLIANCE TO CUSTOMER 433 80401 10n AC INPUT FS401 FS402 FS403 FS404 EUROPE 230Vac 50Hz T125mA 250V FIA 250V F1A 250V 124 250 UL CSA 120Vac 60Hz 250 250 F1A 250V F1A 250V T2A 250V 41 FS404 T2A 250V A C401 4 7n 250 401 POWER SW FS401 0 125A 250V AC INPUT NET2FILTER C402 2 2n 250 1221 4 0403 T2 2n 250 404 47 250 405 4 7n 250 57 1 0402 4006 2 5 10402 7915 CN405 FOR POWER LED 1N5401 404 LM350T gt e D403 1N5401 D404
33. Digital Ground CONVST Convert Start A low to high transition on this pin initiates a 1 5 pulse on an internally generated CONVST signal A high to low transition on this line initiates the conversion process if the internal CONVST signal is low Depending on the signal on this pin at the end of a conversion the AD7819 automatically powers down Chip Select This is a logic input CS is used in conjunction with RD to enable outputs Read Pin This is a logic input When CS is low and RD goes low the DB7 DBO leave their high impedance state and data is driven onto the data bus ADC Busy Signal This is a logic output This signal goes logic high during the conversion process DBO DB7 Data Bit 0 to 7 These outputs are three state TTL compatible Positive power supply voltage 2 7V to 5 5V m PIN CONFIGURATION DIP SOIC P TOP VIEW 5 Not to Scale m CAUTION ESD electrostatic discharge sensitive device Electrostatic charge as high as 4000V WARNING readily accumulate on the human body and test equipment and can discharge lt without detection Although the AD7819 features proprietary ESD protection circuitry m permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precaution are recommended to avoid performance degradation or loss of functionality SENSITIVE DEVICE AK4524 24 bit 96kHz AUDIO CODEC m BLOCK DIAGRAM GENERAL DESCRIPTION T
34. II M SVRIIS OK lt SVRI14 10K SVR115 SVR116 INH X2 X3 5 G1 YO 1 T2 Y4 YS Y6 Y7 A X4 x5 X6 B X X7 09 74HC4 051 GND VSS X1 INH X2 X3 A X4 X5 5 38 20157 C15 14 9 vec 7 e VCC 159 SP 1 0160 440 S Ct61 106 IC120P 100n 7 GND Slo z 5 I 2721 X X6 X7 C154 id ES C155 100 ee R158 P52 Low Cut R159 i Ww e 223 High Cut 2 1 ri OK ISVR132 SVR133 REM IRIS 3 1 P22 3 15KHz P23 4KHz 1K Mme R146 P30 20KHz 1K e P24 5KHz 1K e P27 10KHz R147 W C146 tog R148 4 US e P25 6 3KHz C147 oon R149 Mw e P26 8KHz C148 igo R150 C149 R151 LS e P28 12 5KHz C150 ipo R152 1K e P29 16 2 0151 ign 1 C152 2 1 2 2 1 1K R153 2 AW 100n 3 125 SVR126 SvR127 3 4 3 E 4 E 3 SVR130 3 SVR131 1 2 10K 34 3
35. K C643C642 C641 C640 10 10 10 10 PWMO 24 DMAR1 2 BMSTR C606 C607 C608 C609 C610 C611 C612 C613 C614 100n 100n 100n 100n 100n 100n 100n 100n 100n e e bi ee pue D601 TLM2100 26 38 39 53 R616 MARI FPGA_CLK C615 C616 C617 C618 C619 C620 C621 C622 C623 VCDSP 100n 100n 100n 100n 100n 100n 100n 100n 100n C624 C625 C626 C627 C628 C629 C630 o t 100n 100n 100n 100n 100n 100 100 e e e 7 e e 43 44 CLK CLK48 SHT B D 2 4 00 311 SDCLK1i FPGA C MS3 125 CLK96 VCDSP R661 10K CDATAOO R662 Aw 10K TMS TRSTB eek 035 SH RX28 125 2 382 034 5 1 96748 83 052 855 125 TX1 R65 FRAME96 48 84 CCIO 9 1051 C604 CADRI00 23 C PIN31 030 CADR18 M 029 ALG0266R 0A20430 GND C_WR 25 RX2_ 89 028 25 RX1 30 IO ROUTER 027 ABCFLAG GND 5 _ 92 026 AD BUSY 95 025 CADR18 CRD 94 024 5 95 023 ADR19 2 96 022 FLASH 1021 SH TXIB TDI VCDSP N k
36. OR 14724 25 9 p ON p UU NO a aaa aaa y pL D penr ieee eet ny E 9 9 9 9 C 9 9 9 308 RS ciem X 2 gt C TEES 0000 4 27 4003481200 SW B D DIP IN 4003482600 LEM 8701 DiP701 B702 oo Se 030100 4 3 2 0621 701 28 29 BLOCK DIAGRAM WIRING DIAGRAM OV 029209600 0 8 1094 e gt gt m 5 d e 20 32V3831NI 031 9 HJLIMS 119 103 01 SSVdAB SSVdAB 1143 329V3331NI YILANOILNILOd EBEN EBEN X 0078 1601 0193 1 4 44 eee 103 AND 1n3 119 01 030 00 89600 8 21 039 0082896009 4 8 LNO3J v 9 801019 918 04649484 61816 st 21601 22457 0092872007 0042872007 0 8 514405 nana 0 8 JYVHS SOSNO vOSNO 0 8 5 dig olgzevcooy 048 LNO NI 31
37. SERVICE MANUAL STEREO DUAL 31 BAND GRAPHIC GEQ 1231D 2231D inter I inter MADE IN KOREA 2003 2 9017100300 MICOM DATA MM74HC4051 8 CHANNEL ANALOG MULTIPLEXER m GENERAL DESCRIPTION The MM74HC4051 MM74HC4052 and MM74HC4053 Multiplexers are digitally controlled analog switches implemented in advanced silicon gate CMOS technology These switches have low on resistance and low off leakages They are bidirectional switches thus any analog input may be used as an output vice versa Also These switches contain linearization circuity which lowers the on resistance and increases switch linearity These devices allow control of up to 6V peak analog signals with digital control signals of 0 to 6V Three supply pins are provided for Vcc ground and Vee This enables the connection of 0 5V logic signals when 5V and an analog input range of x 5V when Ve 5V All three devices also have an inhibit control which when HIGH will disable all switches to their off state All analog inputs and outputs and digital inputs are protected from electrostatic damage by diodes to Vcc and ground This device connects together the outputs of 8 switches thus achieving an 8 channel multiplexer The binary code placed on the A B and C select lines determines which one of the eight switches is on and connects one of the eight inputs to the common output m FEATURES Wide analog input voltage range 6V e Low o
38. TA GND OV Tam 25 C tet lt 2 5ns Symbol Propagation delay CP to Qn MR to Qu 15 3 3 ten fmax Maximum clock frequency Ci Input capacitance Power dissipation capacitance per gate 3 3 Notes 1 and 2 NOTES 1 Ce is used to determine the dynamic power dissipation Po in yW Po CPD x gt fo where fi input frequency in MHz C output load capacitance in pF fo output frequency in MHz Vcc supply voltage in V gt fo sum of the outputs 2 The condition is GND to m ORDERING INFORMATION 14 Pin Plastic DIL 40 C to 125 C 74LV164N 74LV164N SOT27 1 40 C to 125 C 74LV164D 74LV164D SOT108 1 40 C to 125 C 74LV164DB 74LV164DB SOT337 1 40 C to 125 C 74LV164PW 74LV164PW DH SOT402 1 14 Pin Plastic SO 14 Pin Plastic SSOP Type 14 Pin Plastic TSSOP Type m PIN CONFIGURATION m PIN DESCRIPTION 1 2 Ds SV00381 Date inputs 3 4 5 6 Qo to Q7 Outputs 10 11 12 13 GND Ground ov CP Clock input LOW to HIGH edge trig gered MR Master reset input active LOW FUNCTIONAL DIAGRAM 9 P 95 9 Positive supply voltage m LOGIC SYMBOL IEEE IEC SV00382 8 BIT SERIAL IN PARALLEL OUT SHIFT REGISTER
39. asynchronous access of its internal memory or IOP registers by a host Open drain output O D by default can be programmed in ADREDY bit of SYSCON register to be active drive A D REDY will only be output if the CS and HBR inputs are asserted DMA Request 1 DMA Channel 9 DMA Request 2 DMA Channel 8 DMA Grant 1 DMA Channel 9 DMA Grant 2 DMA Channel 8 Multiprocessing Bus Requests Used by multiprocessing ADSP 21065L s to arbitrate for bus mastership An ADSP 21065L drives its own BRx line corresponding to the value of its 102 inputs only and monitors all others In a uniprocessor system tie both BRx pins to VDD Multiprocessing ID Determines which multiprocessor bus request BR1 BRo is used by ADSP 21065L ID 01 corresponds to 10 10 corresponds to ID 00 in single processor systems These lines are a System configuration selection which should be hard wired or changed only at reset Core Priority Access Asserting its CPA pin allows the core processor of an ADSP 21065L bus slave to interrupt background DMA transfers and gain 16 IRQ2 0 FLAGi1 0 CS REDY O D access The ADSP 21065L deasserts ACK as an output to add wait states to a synchronous access of its IOP registers In a multiprocessor system a slave ADSP 21065L deasserts the bus master s ACK input to add wait state s to an access of its IOP registers The bus master has a keeper latch on its ACK pin that maintains the input at the l
40. el N IC SDRAM64M SRAM SDA10 CADR12 311 e SH TX2B C658 659 SDCLKO ATA CDATAL00 311 A SDCKE 4 CONVST C RD AD BUSY AD7819 8bit AD Converter _ 670 671 672 C673 ioon ioon 100 100 ABCFLAG1 lt TPS3801 MRESETPS3801 5 05 052401 07 052401 GND 602 T MODE C676 C677 d 45 46 SHT B D 3 4 FRAME96 Q K 14 47 LED OUT LED CLK KEY CLK KEY OUT K N F602 NFM60R AN 15V F603 NFM60R R68 c682 2 100 47u 2 C681 470 254 48 10 25 10 25 100 25 SHT B D 4 4 CN503 FROM CN3O INL CN504 ROM CN3OS INR CN505 TO CN302 OUTL CN506 TO CN304 OUTR 609 0505 nsu 6909 a 3 3K IC611 A 10 2K1x 18 7K 1x 49 47 C524 330P NPO 620 545 50725 621 545 50723 615 613 C525 3 3n NPO C526 3 3n NP 0 R544 6 34 1 00 1 527 7
41. es VDD DATA24 GND VDD DATA17 TCK ADDR2 SDCLKO GND PWM EVENTO GND VDD BSEL 1 DATA23 DATA22 BR1 ACK DATA18 BMS ADDRO DATA21 BR2 MSO DATA19 GND GND VDD MS1 DATA20 GND FLAGO 19 CLKIN GND GND VDD FLAG1 DATA XTAL GND NC RESET FLAG2 DATAS VDD MS2 DATA21 VDD VDD GND MS3 DATA22 GND FLAG3 SDCLK1 FLAG11 DATA23 ADDR23 NC GND VDD GND ADDR22 NC VDD FLAG10 VDD ADDR21 SDCLKO FLAG9 DATA24 VDD FLAG8 DATA25 ADDR20 DMAR2 GND DATA26 ADDR19 HBR DATAO VDD ADDR18 GND DATA1 GND GND RAS DATA2 DATA27 GND NC NO CONNECT 20 21 SPECIFICATIONS m ELECTRICAL ANALOG INPUT XLR amp 1 4 TRS Electronically Balanced RF Filtered and fully unbalanced compatible luieze uo gt Maximal Input Level 20dBu ANALOG OUTPUT XLR amp 1 4 TRS Electronically Balanced RF Filtered and fully unbalanced compatible Maximum Output Level gt 6000 DIP Switch Selectable Output Attenuator Steps GRAPHIC EQUALIZER 31 Band 1 3 Octave Interpolating Constant Q Filter Bank Selectable Boost Cut Range z12dB 6dB and 0 to 12dB 0 to 6dB in Cut Only m
42. evel to which it was last driven Suspend Bus Three State External devices can assert SBTS to place the external bus address data selects and strobes but not SDRAM control pins in a high impedance state for the following cycle If the ADSP 21065L attempts to access external memory while SBTS is asserted the processor will halt and the memory access will not finish until SBTS is deasserted SBTS should only be used to recover from host processor ADSP 21065L deadlock Interrupt Request Lines May be either edge triggered or level sensitive Flag Pins Each is configured via control bits as either an input or an output As an input it can be tested as a condition As an output it can be used to signal external peripherals Host Bus Request Must be asserted by a host processor to request control of the ADSP 21065L s external bus When HBR is asserted in a multiprocessing system the ADSP 21065L that is bus master will relinquish the bus and assert HBG To relinquish the bus the ADSP 21065L places the address data select and strobe lines in a high impedance state It does however continue to drive the SDRAM control pins HBR has priority over all ADSP 21065L bus requests 2 1 in a multiprocessor system Host Bus Grant Acknowledges an HBR bus request indicating that the host processor may take control of the external bus HBG is asserted by the ADSP 21065L until HBR is released In a multiprocessor system HBG is output by the
43. he AK4524 is a high performance 24bit CODEC for the 96kHz recording system The ADC has an Enhanced Dual Bit architecture with wide dynamic range The DAC uses the new developed Advanced Multi Bit architecture and achieves low outband noise and high jitter tolerance by use of SCF switched capacitor filter techniques The AK4524 has an input PGA and is well suited MD DVTR system and musical instruments m FEATURES AINR WW 4 24bit 2ch ADC Audio 64x Oversampling VCOM 4 Controller Single End inputs AOUTL lt S N D 90dB AOUTL 4 Dynamic Range S N 100dB Digital HPF for offset cancellation Input PGA with 8dB gain 4 0 588 step VREF VA Control Register I F ock Gen amp Divi Input DATT with 72dB att format MSB justified or Lui WI 24bit 2ch DAC CS CCLK CDTI CIF xn 128 x Oversampling 24bit 8 times Digital Filter Ripple 0 005dB Attenuation 75dB SCF Differential Outputs S N D 94dB Dynamic Range S N 110dB De emphasis for 32kHz 44 1kHz 48kHz sampling m ORDERING GUIDE Output DATT with 724 att AK452AVF 7 40 79 28 VSOP 0 65mm pitch format MSB justified LSB justified or 25 A Ed High Jitter Tolerance 3 w
44. ire Serial Interface for Volume Control m PIN LAYOUT Master Clock X tal Oscillating Circuit 25615 38415 76815 102415 Master Mode Slave Mode AGND operation Internal pull down TEST 4524 Power Supply Pin for I F Small 28pin VSOP package 10 11 m PACKAGZ 28pin VSOP Unit mm 9 8 0 2 1 25 0 2 polla 0 675 28 err O ae 0 22 0 1 Detail A IH Seating Plane Note Dimension does not include moid flash PACKAGE amp LEAD FRAME MATERIAI Package molding compound Epoxy Lead frame material Cu Lead frame surface treatment Solder plate 12 ADSP 21065L DSP MICROCOMPUTER m SUMMARY High Performance Signal Computer for Communications Audio Automotive Instrumentation and Industrial Applications Super Harvard Architecture Computer SHARC Four Independent Buses for Dual Data Instruction and I O Fetch on a Single Cycle 32 Bit Fixed Point Arithmetic 32 Bit and 40 Bit Floating Point Arithmetic 544 Kbits On Chip SRAM Memory and Integrated I O Peripheral FS
45. l Bus Data The ADSP 21065L inputs and outputs data and instructions on these pins The external data bus transfers 32 bit single precision floating point data and 32 bit fixed point data over bits 31 0 16 bit short word data is transferred over bits 15 0 of the bus Pull up resistors on unused DATA pins are not necessary Memory Select Lines These lines are asserted as chip selects for the corresponding banks of external memory Internal ADDRes 24 are decoded into MS3 0 The MSs lines are decoded memory address lines that change at the same time as the other address lines When no external memory access is occurring the lines are inactive they are active however when a conditional memory access instruction is executed whether or not the condition is true Additionally MS3 o line which is mapped to SDRAM may be asserted even when no SDRAM access is active Ina multiprocessor system the MS3 o lines are output by the bus master Memory Read Strobe This pin is asserted when the ADSP 21065L reads from external memory devices or from the IOP register of another ADSP __ 21065L External devices including another ADSP 21065L must assert RD to read from the ADSP 21065L s IOP registers a multiprocessor system RD is output by the bus master and is input by another ADSP 21065L Memory Write Strobe This pin is asserted when the ADSP 21065L writes to external memory devices or to the IOP register of another ADSP 21065L Exte
46. n resistance 50 typ Vcc Vee 4 5V 30 typ Vcc Vee 9V Logic level translation to enable 5V logic with x 5V analog signals e Low quiescent current 800A maximum 74 Matched Switch characteristic m ORDERING CODE Order Number Package Number Package Description MM74HC4051M M16A 16 Lead Small Outline Integrated Circuit SOIC MS 012 0 150 Narrow MM74HC4051WM M16B 16 Lead Small Outline Integrated Circuit SOIC JEDEC MS 013 0 300 Wide MM74HC4051SJ M16D 16 Lead Small Outline Package SOP ELAJ TYPE Il 5 3mm Wide MM74HC4051MTC MTC16 16 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 4 4mm Wide MM74HC4051N N16E 16 Lead Plastic Dual In Line Package PDIP MS 0010 300 Wide Devices also available in Tape and Reel Specify by appending the suffix letter X to the ordering code CONTENTS Micom Data E 4 14 207 01 07 1270 Mm IRE 1 21 Specifications 22 Electrical Parts List sn gn 1283 24 Top and PG Board AMISSIS Wiring Diagram rw us 7 30 Block Diagram Sh Ee do du qo 3132 Schematic Diagram 33 50 Exploded View of Cabinet Chassis Mechanical Parts List 51 54 5 Drawing 55 58 m CONNECTION DIAGRAMS Pin Assignments for DIP SOIC SOP
47. n You can configure the ADSP 21065L to use its internal clock generator by connecting the necessary components to CLKIN and XTAL You can use either a crystal operating in the fundamental mode or a crystal operating at an overtone Figure shows the component connections used for a crystal operating in fundamental mode and Figure 2 shows the component connections used for a crystal operating at an overtone Test Data Input JTAG Provides serial data for the boundary scan logic TDI has a 20kQ internal pull up resistor Test Data Output JTAG Serial scan output of the boundary scan path Test Reset JTAG Resets the test state machine TRST must be asserted pulsed low after power up or held low for proper operation of the ADSP 21065L TRST has a 20kQ internal pull up resistor Emulation Status Must be connected to the ADSP 21065L EZ ICE target board connector only CLKIN XTAL Bus Master Output In a multiprocessor system indicates whether the ADSP 21065L is current bus master of the shared external bus The ADSP 21065L drives BMSTR high only while it is the bus master In a single processor system 10 00 the processor drives this pin high SDRAM Column Access Strobe Provides the column address In conjunction with RAS MSx SDWE SDCLKx and sometimes SDA10 defines the operation for the SDRAM to perform SDRAM Row Access Strobe Provides the row address In conjunction with CAS SDWE SDCLKx and sometimes SDA
48. ode Gain 0 to 18dB 6 LED Input Level Meter 40dBu 24dBu 15dBu 8dBu 3dBu Peak gt 18dBu CUT FILTERS Low Cut Frequency 12 5Hz 200Hz Low Cut M 18dB octave Butterworth High Cut Frequency 3 3kHz 29 5kHz High Cut Slope 18dB octave Butterworth PEAK LIMITER eee Maximizer with Soft Clip Threshold ge 0 to 19dBu 3 LED Gain Reduction Output Clip Indicator Limiter Link GEQ 2231D only Channel Link GEQ 2231D only SYSTEM PERFORMANCE Frequency Response 0 59 10 2 31 5 2 Dynamic RINGE gt 954 TADEN oet ek re 0 003 m GENERAL iue gel eL AC 100V 120V 230V 240V 50 60Hz Power evel Due tas rua LU DE ET DA VAR ege 10W Weight GEQ 1231D 3 5kg GEQ 2231D 5 0kg e Dimensions
49. r consumption of the part at lower throughput rates The AD7819 can also operate in a high speed mode where the part is not powered down between conversions In this mode of operation the part is capable of providing 200 kSPS throughput Outline References European ghp Version Jedec Eiaj Projection 55 Date The part is available in a small 16 lead 0 3 wide plastic dual in line package DIP in a 6 lead 0 15 SOT108 1 076 65 MS 012AB pepe wide narrow body small outline IC SOIC and in a 16 lead narrow body thin shrink small outline package 95 01 28 TSSOP NOTE Plastic or metal protrusions of 0 15 mm maximum per side are not included m ABSOLUTE MAXIMUM RATINGS Von t A Ea EEE 0 3V to 7V Digital Input Voltage to DGND CS E EES 0 3V 0 3V Digital Output Voltage to DGND BUSY A DBO DBT pon outer teins 0 3V 0 3V AGND 0 3V 0 3V Analog Input 0 3V 0 3V Storage Temperature 65 C to 150 C JUNCTION 150 C Plastic DIP Package Power Dissipation 450mW Thermal
50. rnal devices must assert WR to write to the ADSP 21065L s IOP registers In a multiprocessor system WR is output by the bus master and is input by the other ADSP 21065L Synchronous Write Select This signal interfaces the ADSP 21065L to synchronous memory devices including another ADSP 21065L The ADSP 21065L asserts SW to provide an early indication of an impending write cycle which can be aborted if WR is not later asserted e g ina conditional write instruction In a multiprocessor system SW is output by the bus master and is input by the other ADSP 21065L to determine if the multiprocessor access is a read or write SW is asserted at the same time as the address output Memory Acknowledge External devices can deassert ACK to add wait states to an external memory access ACK is used by I O devices memory controllers or other peripherals to hold off completion of an external memory IRQ2 0 FLAG11 0 CS REDY O D access The ADSP 21065L deasserts ACK as an output to add wait states to a synchronous access of its IOP registers In a multiprocessor system a slave ADSP 21065L deasserts the bus master s ACK input to add wait state s to an access of its IOP registers The bus master has a keeper latch on its ACK pin that maintains the input at the level to which it was last driven Suspend Bus Three State External devices can assert SBTS to place the external bus address data selects and strobes but not SDRAM con
51. s CLKIN TMS TCK TRST TDI TDO EMU and GND signals be made accessible on the target System via a 14 pin connector a 2 row x 7 pin strip header such as that shown in Figure 3 The EZ ICE probe plugs directly onto this connector for chip on board emulation You must add this connector to your target board design if you intend to use the ADSP 2106x EZ ICE SDCKE SDA10 XTAL EVENT o SDRAM Clock Enable Enables and disables the CLK signal For details see the data sheet supplied with your SDRAM device SDRAM A10 Pin Enables applications to refresh an SDRAM in parallel with a host access Crystal Oscillator Terminal Used in conjunction with CLKIN to enable the ADSP 21065L s internal clock generator or to disable it to use an external clock source See CLKIN PWM Output Event Capture In PWMOUT mode is an output pin and functions as a timer counter In WIDTH mode is an input pin and functions as a pulse counter event capture Power Supply nominally 3 3V dc 33 pins Power Supply Return 37 pins Do Not Connect Reserved pins that must be left open and unconnected 7 18 The total trace length between the EZ ICE connector and the furthest device sharing the EZ ICE JTAG pins should be limited to 15 inches maximum for guaranteed operation This restriction on length must include EZ ICE JTAG signals which are routed to one or more 2106x devices or to a combination of 2106xs and other JTAG devices
52. trol pins in a high impedance state for the following cycle If the ADSP 21065L attempts to access external memory while SBTS is asserted the processor will halt and the memory access will not finish until SBTS is deasserted SBTS should only be used to recover from host processor ADSP 21065L deadlock Interrupt Request Lines May be either edge triggered or level sensitive Flag Pins Each is configured via control bits as either an input or an output As an input it can be tested as a condition As an output it can be used to signal external peripherals Host Bus Request Must be asserted by a host processor to request control of the ADSP 21065L s external bus When HBR is asserted in a multiprocessing system the ADSP 21065L that is bus master will relinquish the bus and assert HBG To relinquish the bus the ADSP 21065L places the address data select and strobe lines in a high impedance state It does however continue to drive the SDRAM control pins HBR has priority over all ADSP 21065L bus requests 2 1 in multiprocessor system Host Bus Grant Acknowledges an HBR bus request indicating that the host processor may take control of the external bus HBG is asserted by the ADSP 21065L until HBR is released In a multiprocessor system HBG is output by the ADSP 21065L bus master Chip Select Asserted by host processor to select the ADSP 21065L Host Bus Acknowledge The ADSP 21065L deasserts REDY to add wait states to an
Download Pdf Manuals
Related Search