SH-2A, SH-2 E200F エミュレータ ご使用上の注意事項
Contents
1. 1 15 5 NE 1 16 12. 10 11 12 sl3 14 15 HW 1 11 1 Radix H 0x 16 10 16
3. 200F Go STEP 1 2 3 1STEP
4. 3 1 14 1 1 15 1 C 1 15 2
5. 14 E200F SuperH RISC engine C C H H8S H8 300 Series C CCr High performance Embedded Workshop 39
6. Event Condition 6 6 2 1 4 TRAPA 1 Event Condition 6 2 1 5 6 2 2 AUD 6 2 2 1 Software trace Softwar e trace 24
7. 1 13 2 High performance Embedded Workshop
8. 2 2 1 3 To Event Condition 5 To Event Condition 5 Event Condition 6 2 2 1 4 TRAPA
9. ON ROM RAM 11 5 11 5 1 EA Exception interrupt counts TRAPA 11 6 MCU 11 7 SH7216 Select Emulator mode
10. address size 1 2 4 data 5 hdi progress hdi progress text percentage 36 6 TCL hdi doevents hdi doevents 7 Radix radix radix base 8 hdi msgbox text hdi msgbox text opti
11. C Sx CSx Pu11 Up CS Pull Up gt hn E200F H UDI CS 28 E200F SH7083 SH7084 SH7085 SH7086 SH7146 SH7149 SH7124
12. CPU_Reset Reset_Go WS 2 es Ni
13. H UDI SH 2A SH 2 E200F SH7147 1 5 HUDI 9 1 9 2 9 2 1 Onchip 1 CH1 2 2 DTC Event Condition Event Condition 9 3 9 3 1 SH7136 SH7137 SH7142 SH7147
14. 1 Event Condition 4 3 4 3 1 1 6 ROE0200F1ETU00 2 ROBE0200FIMSRO0 ROEB0200F1MSRO1 3 4 4 4 4 1 EA Exception interrupt counts TRAPA
15. 6 2 6 2 1 6 2 1 1 1 BUS To 1 BUS Onchip To 6 2 1 2 To To 6 2 1 3 To Event Condition 5 To Event Condition 5
16. 1 8 9 FILE_SAVEP ELF DWARF2 1 8 10 In Place UNICODE In Place TT 1 8 11 1 8 12 ROM RAM ROM RAM RAR SR ROM RAM
17. Break Emulation mode Configuration General Emulation mode No break 1 7 1 8 1 8 1 E200F
18. 5 3 5 3 1 1 ROE0200F1ETU00 50MHz 30MHz 8 30MHz 6 2 ROE0200F1MSRO0 ROE0200F1MSRO1 50MHz 30MHz 3 30MHz 2 5 4 SH7286 SH7285 SH7243 E200F
19. Eyent Condition 6 4 2 1 4 TRAPA 1 Event Condition 4 2 1 5 4 2 2 AUD 4 2 2 1 Software trace Software trace 4 2 2 2 TRAPA
20. 1 3 1 3 1 CD R SH 2A SH 2 E200F Manuals Japanese jSH 2AE200Fuh pdf SH 2A SH 2 SH7206 Manuals JapaneseYSH 2AYjSH 2AE200F7206ph pdf E200F SH7203 SH7263 YManuals Japanese SH 2AYjSH 2AF200F7263pa pdf SH7211 Manuals YJapanese SH 2AYjSH 2AE200F7211pd pdf SH72546RFCC SH72543R Manuals Japanese YSH 2AYjSH 2AF200F7254pa pdf SH72544R SH72531 SH72531FCC SH7286 SH7285 SH7243 YManuals Japanese YSH 2AYjSH 2AF200F7285pc pdf SH7214 SH7216 Manuals Japanese YSH 2AYjSH 2AF200F7216pa pdf SH2A_custom_SoC Manuals Japanese SH 2A jSH 2AB200FCUSTOMSOCpb pdf SH7083 SH7084 Manuals YJapanese SH7080 jSH7080F200F7080ph pdf SH7085 SH7086 SH7146 SH7149 SH7124 SH7125 iY
21. EA Exception interrupt counts TRAPA 4 E200F SH7211 4 1 4 2 4 1 1 SW S W gt ul 1H S W ul gt SH2A_SBSTK H 4 S W 4 1 R15
22. 8 SH7125 8 1 E200F No 1 2 AUD 3 4 Event Condition CH1 2
23. AUD BUS Onchip 1 5 4 AUD Event BUS Event AUD Eyent BUS Eyent 1 5 5 Onchip 1 0nchip 2 Onchip 1 2 Combination action Sequential or PtoP
24. Event Condition 11 3 11 3 1 1 ROE0200F1ETU00 50MHz 30MHz 8 30MHz 6 2 ROE0200F1MSRO00 ROE0200F1MSRO1 50MHz 30MHz 3 30MHz 2 33 11 4 SH7214 SH7216 E200F
25. On Chip Event Prefetch address break before executing S W 2 1 2 Onchip DIVU DIVS DIVU DIVS DIVU DIVAS 2 2 2 2 1 2 2 1 1 BUS To I BUS Onchip To 2 2 1 2 To To
26. ROM RAM ROM RAM SH7083 256KB 16KB 512KB 32KB 256KB 512KB 32KB 512KB 32KB 512KB SH7084 256KB 16KB 512KB 32KB 256KB 512KB 32KB 512KB 32KB 512KB SH7085 256KB 16KB 512KB 32KB 256KB 512KB 32KB 512KB 32KB 512KB SH7147 R5F71474BJ80FPV 256KB 16KB 256KB 16KB R5F71474BD80FPV 256KB 16KB 256KB 16KB R5F71474AK64FPV 256KB 12KB 256KB 16KB R5F71474BJ80FPV 256KB 16KB 256KB 16KB R5F71475BJ80FPV 384KB 16KB 384KB 16KB R5F71475AK64FPV 384KB 16KB 384KB 16KB R5F71476BJ80FPV 512KB 16KB 512KB 16KB R5F71476BD80FPV 512KB 16KB 512KB 16KB R5F71476AK64FPV 512KB 16KB 512KB 16KB SH7142 R5F71424BJ80FPV 256KB 16KB 256KB 16KB R5F71424AK64FPV 256KB 12KB 256KB 16KB R5F71426BJ80FPV 512KB 16KB 512KB 16KB R5F71426BD80FPV 512KB 16KB 512KB 16KB R5F71426AK64FPV 512KB 16KB 512KB 16KB SH7136 R5F71364AN8OFPV 256KB 16KB 256KB 16KB R5F71364AD8OFPV 256KB 16KB 256KB 16KB 1 9 ROM RAM
27. 1 1 8 5 1 8 6 Binary TIntelHex
28. 0927 Select Emulator mode R5F72167ADF 0927 R5F72167ADF_Option R5F72167ADB 0927 R5F72167ADB_Option 11 8 Writing Flash Memory Configration l gt General Flash memory synchronization Flash memory to PC PC to flash memory Flash memory to PC Disable PC to flash memory Eeprom memory synchronization Eeprom memory to PC Disable 34 High performance Embedded Workshop 12 High performance
29. 1 17 1 1 17 2 1 17 3 At target connection a OPEN_WORKSPACE b CHANGE_PROJECT c CHANGE_CONFIGURATION 2 Before download of modules a b c g h G STEP STEP STEP OPEN_ CHANGE_PROJECT CHANGE_CONFIGURATION GO GO_RESET
30. E200F SH7206 2 1 2 1 1 SW S W 15 1 H S W SH2A_SBSTK 4 R15 S W RO0 gt SH2A_SBSTK enable ul
31. 3 6 4 1 EA Exception interrupt counts TRAPA RAM RAM Flash memory synchronization Disable SW JTAG SH72544R SH72543R SH72531FCC SH72531 JTAG TCK
32. 21 5 E200F SH7286 SH7285 SH7243 5 1 5 2 5 1 1 S W S W S W SH2A_SBSTK ul 4 R15 ul S W RO0
33. 1 Event Condition 2 2 1 5 2 2 2 AUD Dr Dol TRAPA 1 Event Condition 2 3
34. DIVU DIVAS S To I BUS Onchip T gt 20 To EE To E 4 2 1 3 To Byvent Condition 5 To Event Condition 5 F
35. F enable 4 1 2 Onchip DIVU DIVS DIVU DIVS 4 2 1 4 2 1 1 1 BU 4 2 1 2 To E SH2A_SBSTK E RO0 On Chip Event Prefetch address break before executing S W
36. ROM RAM ROM RAM SH7137 R5F71374AN80FPV 256KB 16KB 256KB 16KB R5F71374AD80FPV 256KB 16KB 256KB 16KB SH72543R R5F72543RKBGV 2 0MB 128KB 3 75MB 256KB SH72544R R5F72544RKBGV 2 5MB 128KB 3 75MB 256KB SH72531 R5F72531KFPV 1 25MB 64KB 1 25MB 64KB SH72531FCC R5E72531KFPV 1 25MB 64KB 1 25MB 64KB SH72546RFCC R5E72546RBGV 3 75MB 256KB 3 75 MB 256KB SI 1 9 1 Run Run 1 9 2 0 seconds 1 9 3 1 1 E2
37. 11 2 1 4 TRAPA 1 Event Condition 11 2 1 5 11 2 2 AUD 11 2 2 1 Software trace Software trace 11 2 2 2 TRAPA 1
38. S W SH2A_SBSTK F 4 R15 S W RO0 gt SH2A_SBSTK enable On Chip Event Prefetch address break before executing S W
39. TRAPA 1 Event Condition 5 2 1 5 5 2 2 AUD 5 2 2 1 Software trace Software trace 5 2 2 2 TRAPA 1 Event Condition
40. 1 8 2 3 1 8 3 1 8 4 1 I0
41. BYTE abs S mot abs 1 27 Help AERO SR NN PST AC BT SH72531 1 SH72531FCC i OG AC IfF Te BT I
42. HH N N 4 E N 4 512kbyteX8 Main 1 512kbyteX8 2 Option_1 0ption_2 Main Option_1 0ption_2 Option_1 Main Option_2 Option 2 Main Option_1 1 26 abs abs
43. ON ROM RAMW 5 5 5 5 1 EA Exception interrupt counts TRAPA 23 E200F 6 1 6 1 1 Onchip SH72546RFCC SH72544R SH72543R SH72531 SH72531FCC DIVU DIVS DIVU DIVS DIVU DIVAS
44. 1 DTC 31 9 4 9 4 1 1 ROE0200F1ETU00 8 2 3 ROE0200F1MSRO0 ROE0200F1MSRO1 10 SH7080 SH7146 SH7147 11 CSx
45. Event Condition 3 2 1 5 3 2 2 AUD 3 2 2 1 TRAPA 1 Event Condition 922 2 1 SH7263 DMAC AUD Non realtime trace 2 SH7263 SDRAM AUD
46. Non realtime trace 3 3 7 3 3 1 1 ROE0200F1ETU00 66 67MHz 45MHz 8 45MHz 6 2 ROE0200F1MSRO00 ROE0200F1MSRO1 66 67MHz 45MHz 3 45MHz 2 3 4 SH7200 3 5 3 5 1
47. ul ul 3 1 2 Onchip DIVU DIVS DIVU DIVS DIVU DIVAS 3 2 3 2 1 3 2 1 1 1 BUS To 1I BUS Onchip To 3 2 1 2 _ To To 3 12 8
48. 2 3 1 1 ROE0200F1ETU00 66 67MHz 56MHz 8 56MHz 6 2 ROE0200FIMSRO00 ROEO0200F1MSRO1 66 67MHz 50MHz 3 50MHz 2 2 4 2 4 1 EA Exception interrupt counts TRAPA 3 E200F SH72630 SH72632 SH72631 SH72633 SH7203 3 1 3 1 1 S W S W
49. 7 Radix 8 hdi msgbox text 9 hdi assemble al getbrkcause Ne 12 hdi status 1 hdi cmd High performance Embedded Workshop E hdi expr d 16 3 hdi memread
50. To 1 11 2 1 2 To To 32 11 2 1 3 To Event Condition 5 To Event Condition 5 Event Condition 6
51. BUS 5 10 1 5 7 BUS BUS BUS BUS BUS 1 5 8 1 2 SW S W 1
52. 1 9 5 HUDI H UDI E200F 1 9 6 UBC OUBC 1 9 7 SLEEP E200F Stop HUDI 1 9 8
53. hdi memread space address count size TCL space NR address count size 1 2 4 4 hdi memwrite hdi memwrite space address size data TCL SDace
54. SH71240A SH71240 30 SH71240A SH71241A SH71250A SH71251A A No Select Emulator mode 1 SH71240A SH71242 SH71243 2 SH71241A SH71242 SH71243 3 SH71250A SH71252 SH71253 4 SH71251A SH71252 SH71253 8 7 Writing Flash Memory SH71240 SH71241 SH71242 SH71243 SH71250 SH71251 SH71252 SH71253 Writing Flash Memory Flash Sum 128KB E200F SH7136 SH7137 SH7142 SH7147 E200F FE200F SH7142 SH7147
55. 5 Configuration Step option Flash memory Disable synchronizatio n 6 8 2 8 2 1 0nchip 1 CH1 2 2 DMA DTC Event Condition Event Condition 29 8 3 8 3 1 SH7083 SH7084 SH7085 SH7086 1
56. Ch1 2 3 Ch 2 to Ch 1 PA Ch1 to Ch 2 PA 3 1 5 6 BUS BUS 5 10 E200F 5 BUS
57. S Record 1 8 7 FILE LOAD FILE LOAD YV FILE_VERIFY FILE LOAD FILE LOAD R A 1 8 8 MEMORY EDIT ASCII
58. 19 ENTRY PC PC 1 20 21 SYSROF rr SYSROF ELF DWARF2 1 22
59. ROE0200F1ETU00 8 2 ROE0200F1MSR00 ROE0200F1MSR01 3 8 5 1T 0 R5F70834A R5F70835A R5F70844A R5F70845A R5F70854A R5F70855A R5E70835R R5E70845R R5E70855R SH71240 SH71241 SH71242 SH71243 SH71250 SH71251 SH71252 SH71253 F L PFDRL 15 8 R5F71464R R5F71494R R5F71491R R5E71464R R5E71494R R5E71491R F L PFDRL 7 5 3 1 8 6 SH7124 SH7125 A SH71240A SH71241A SH71250A SH71251A Select Emulator mode A
60. gt SH2A_SBSTK enable Prefetch address break before executing S W 0n Chip Event 5 1 2 Onchip DIVU DIVS DIVU DIVS DIVU DIVAS 5 2 1 5 2 1 1 1 BUS To 1 BUS Onchip To 5 2 1 2 To
61. 1 28 1H MCU MCU 2 1 29 1 29 1 ON 1 E200F ON 2 High peformance Embedded Workshop FPGA Connecting Function Select FPGA Functian select Functian setting Main board mode setting HOISIHDBTd TTP SETHT to board Moiesetine Downloading E20O0
62. SH7136 SH7137 SH7142 SH7147 Manuals Japanese SH7080 jSH7080E200F7147pe pdf 1 4 1 5 1 5 1 Onchip 1 BREAKPOINT S W 2 1 5 2 BreakConditionSet BreakConditionSet Onchip Event 1 5 3
63. 2 DMA DTC SH7146 SH7149 1 2 DMA DTC SH7124 SH7125 1 8 4 8 4 1 1
64. IT 3 H E200F SH7214 SH7216 11 1 Onchip DIVU DIVS 11 2 11 2 1 11 2 1 1 1 BU E DIVU DIVS S To 1 BUS Onchip
65. GO_T WORKSPACE LL 0UT OVER 1 17 4 1 18 1 18 1 1 C 3 8 4 Labels
66. 1 15 3 1 15 4 static auto E H E 16 17
67. E Open Open 1 23 24 r 1 25 B 1 25 1 Nest lt 1 25 2 Ll
68. 6 3 6 4 6 5 6 6 6 7 6 2 2 2 TRAPA 1 Event Condition 6 2 2 3 AUD OFF WDT Eva Board User Signals User Reset enable E200F 6 3 1 ROE0200F1MSR00 ROE0200F1MSRO1
69. Step C Step Out for while 1 1 9 9 Select Emulation User system Mode User system Mode User System pin MDS2 0 is NC User system Clock Mode User system Clock Mode User System pin CLK_ MD2 0 is NcC
70. To Event Condition 5 To BEyent Condition 5 Event Condition 6 18 3 2 1 4 TRAPA 1
71. SH72546RFCC JTAG TCK EXTAL 25 6 8 SH72531 SH72531FCC 6 1 6 1 AUD SH72531FCC CS EC 6 9 SH72546 26 27 7 SH7206 SH7211 1 2 CS H CS
72. 6 1 6 1 Timestamp Difference Timestamp Difference Timestamp Difference 1 6 2 Interna1 AUD 1 Type BRANCH 2 AUD Type BRANCH DESTINATION DESTINATION 3 AUD DESTINATION 1 6 3 Interna1 AUD Interna1 AUD Type FETCH 1 6 4
73. 00F E200F Eyent Condition 1 9 4 High performance Embedded Workshop 0 E200F RUN LED RUN LED
74. 2166ADFP R5F72167ADFP R5F72165ADBR R5F72166ADBR R5F72167ADBR SH 2 SH7080Series E200F SYSTEM CPU SH 2 R5E70835R R5E70845R R5E70855R R5E70865R R5F70834A R5F70835A R5F70844A R5F70845A R5F70854A R5F70855A R5F70865A SH7125Series E200F SYSTEM CPU SH 2 SH71240 SH71241 SH71242 SH71243 SH71250 SH71251 SH71252 SH71253 SH7146Series E200F SYSTEM CPU SH 2 R5E71464R R5E71494R R5E71491R R5F71464R R5F71494R R5F71491R SH7147Series E200F SYSTEM CPU SH 2 R5F71474 R5F71475 R5F71476 R5F71424 R5F71426 SH7137Series E200F SYSTEM CPU SH 2 SH7136 SH7137 1 2 CD R CD ROM CD ROM HewInstMan exe D HewInstMan exe OK Windows R
75. Embedded Workshop TCL TCL High performance Embedded Workshop hdi cmd command command TCL 2 2 hdi expr hdi expr expression 35 High performance Embedded Workshop High performance Embedded Workshop TCL EE 3 1 hdi cmd 2 hdi expr 3 hdi memread 4 hdi memwrite 5 hdi progress ee A ER 4
76. F Program Downloading FPGA data filename aud7080 mot GT EE HE Downloading FPGA data filename evcont7085 mot ra ace 3 ON 4 E200F 1 29 2 OFF 1 High peformance Embedded Workshop 2 OFF 3 E200F OFF 1 30 E200F 1 2 200F ON E200F Onchip Event AUD Eyent Action gnable output trigger AUD 3
77. Rev 16 SH 2A SH 2 E200F a SH 2A SH 2 E200F 1 SH 2A SH 2 E200F 1 1 le 4 SH 2A SH 2A E200F SYSTEM SH7206 SH 2A FLASH E200F SYSTEM SH7211 SH7286 SH7285 SH7243 SH2A FPU E200F SYSTEM SH2A SH72630 SH72632 SH72631 SH72633 SH7203 SH72546R E200F SYSTEM SH2A FPU SH72546RFCC SH72543R SH72544R SH72531 SH72531FCC SH2A_custom_SoC E200F SYSTEM SH2A_custom_SoC_1 SH 2A SH2A FPU SH2A_custom_SoC_2 SH7214 E200F SYSTEM SH2A R5F72145BDFA R5F72146BDFA D R5F72147BDFA R5F72145BD R5F72146BDFP R5F72147BD R5F72145BDBR R5F72146BDBR R5F72147BDBR R5F72145AD R5F72146ADFA R5F72147AD R5F72145ADFP R5F72146AD R5F72147ADFP R5F72145ADBR R5F72146ADBR R5F72147ADBR SH7216 E200F SYSTEM SH2A FPU R5F72165BDFA R5F72166BDFA R5F72167BDFA R5F72165BDFP R5F72166BDFP R5F72167BDFP R5F72165BDBR R5F72166BDBR R5F72167BDBR R5F72165ADFA R5F72166ADFA R5F72167ADFA R5F72165ADFP R5F7
78. To 1 02 To Event Condition 5 To Event Condition 5 Event Condition 6 22 5 2 1 4
79. indows 9 hdi assemble hdi assemble address instruction CPU 10 hdi getbrkcause hdi getbrkcause 11 hdi islinkup hdi islinkup 12 hdi status hdi status linenumber 38 status 13 13 1
80. ons text 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 OK Yes No Cance1 Yes No Retry Cancel 0x0010 0x0020 0x0030 0x0040 OK Cancel Abort Retry Ignore 3 1 OLE 0 OK 1 NN OO OO wo O OK Cancel Abort Retry 1gnore Yes No 37 options w
Download Pdf Manuals
Related Search