ハード ウェア記述言語
Contents
1. VHDL Verilog HDL SFL VHDL VHDL VHDL 2 2 1 VHDL VHDL VHSIC Hardware Description Language 1981 VHSIC Very High Speed In tegrated Circuit VHSIC HDL 1986 ASIC VHDL IEEE std 1076 1987 IEEE std 1164 1992 VHDL2. 3 RTL CPU RTL Register Transfer Level RTL 4 RTL 5
3. MOS IC CPU MOS IC 5 IC FPGA FPGA IC
4. 124 124 M BS RTL ui H 7 A NM Sail LAP ht 2 VHDL 3 ALU 3 1 ALU 3 1 X 8 M 8 Control 4 Vol 49 No 1 1998 a xk X 2 Z 8 Flag 4 e 2 e Flag 4
5. ALU RTL HDL Hardware Description Language CAD C A HDL
6. Vol 49 No 1 1998 amp o x m ox 8 X a c VHDL module ARCHITECTURE ENTITY 1 c VHDL LIBRARY WORK IEEE USE IEEE STD_LOGIC_1164 ALL Full Adder ENTITY full_add IS PORT x IN STD LOGIC y IN STD LOGIC c IN STD LOGIC sum OUT STD LOGIC carry OUT STD LOGIC
7. c 126 126 LED LED ZD FPGA KITE FPGA XACT Step FPGA c 4 4 VHDL XACT Step 1 4
8. 1 0 X Y Control ESPERE Z Flag 3 ALU 3 2 ALU 100 16 Control K 1 Wa wu w boss 1 miasan wilzcxty MUL 0x3 A iN smesan we pex v Ze XEEN y kR h LM ES MCON EE ABRI RLS oxb z x amp Biit v F8 7 2 F LAN E EnS NM Oxc ZA XEETIE v ERT h Lc till Z Xxt B5kit v Z x 1 ot lt Z x 1 ALU 4 4 1 ALU C FPGA ALU VHDL 1
9. HDL VHDL VHDL VHDL C
10. 4 2 1 ns 1 ns 10E 9 sec 1 2 1 ns 470 JOE6 ALU MPU ALU FPGA XC4010 400 155 38 KITE 5 VHDL CAD Lc Xf FPGA KITE
11. 2 HDL HDL 3 ALU 4 2 F HDL Hardware Description Language c 122 122
12. VHDL CPU CPU IC VHDL 2 1 CPU 2 CPU
13. 32 PC AT 64MB OS Windows Ver3 1 KITE XILINX FPGA XC4010 2 VHDL ViewSynthesis Ver5 0 2x FPGA XACT STEP Ver5 2 1 4 2 KITE FPGA PC LED 1 CPU XILINX FPGA XC4010 10K 400 225 RAM 2RAM 128K 3 ROM 64K 4 JCONFIG ROM 64K KTITE 1 KITE 2 5 8
14. 6 1 O 16 16 LED 60 7 FPGA PC 125 125 8 LED 28 LED 26 CPU I O HI CONFIG ROM FPGA KITE 1 KITE 2 ALU 4 3 VHDL KITE 1
15. c VHDL Verilog HDL 2 IEEE HDL 01998 The Faculty of Engineering Yamaguchi University Digital design CAD HDL VHDL FPGA KITE board LS1 FPGA Field Programmable Gate Array
16. o ALU VHDL FPGA X CAD Vol 49 No 1 1998 dB Gd x m RF OX c c ns 117 FF FF 3 i HMA C 3999999 115 18 1 1 55 2 CONTROL E 4 ALU 1 Z Navabi VHDL BP 1994 2 EONI VHDL CQ 1997 3
17. VHDL 1 VHDL Cc RTL Register Transfer Level 2 VHDL VHDL
18. VHDL VHDL 3 ALU VHDL BR 4 VHDL 2 VHDL ViewSynthesis VHDL FPGA XACT Step FPGA FPGA 4 K KITE I O sede dapi ud au ci ALU I O I O
19. END full add ARCHITECTURE behave OF full add IS BEGIN sum lt x XOR y XOR C carry lt x AND y OR x AND c OR y AND c 3 END behave 1 VHDL 3 VHDL VHDL e VHDL e C e ALU 123 123 2 2 VHDL
20. 121 121 ALU gt gt 3 2 3 CAD VHDL ALU FPGA Key Words 1
21. KITE KITE PLUS 1995 4 VHDL ALU KITE 9 1998 2 H 1998 5 15 ALU 127 127 ALU DESIGN USING A HARDWARE DESCRIPTION LANGUAGE VHDL AND IMPLEMENTATION ON AN FPGA BOARD Yuji KAWASHIM A Takahiro WATANABE Yoshihiro TANADA and Kazuo MORIKAWA As the integration and the design complexity of digital systems are increasing a sophisticated design style like a hierarchical design and many efficient CAD tools are widely used Especially design using hardware description language HDL and a logic synthesis is most interesting We try to design a small sized digital system ALU by VHDL and a synthesis tool and implement it using an FPGA board
Download Pdf Manuals
Related Search