59JTagStick 取扱説明書
Contents
1. 8 1 lt O 39kk HE GE XE XE ZE XZ BE NU SRE XK CUBOS u 59 l o d B ad 104 9 s mmu COREIA A SS a ee oo M O E 8 1 uSDCONF1A03 Bottom View HHPH D lD p D li O 8 12. microSD CONEFIGTXT AREA 3 0 E 0 F 16 16 AREA 3 0 SW 16 FPGA 3 data3 rbf SW 3 data3 rbf microSD 50MHz HighSpeed FPGA TCK CONFIGLTXT 0MHz 2SMHz 12 5MHz 6 25MHz 3 57MHz 2 778MHz 1 923MHz 1MHz
3. JTAG VCCIO VCCIO 1 2V 3 6V microSD 2GB FAT16 Card microSD Windows Explorer Drag amp Copy Jag microSD CONFIGITXT FPGA CONFIGTXT
4. 3 LED 6 o 5 28b db 5 28D 58D 5 111 101 001 000 01 6 02 2 0 5 0 5 1 0 2 3 16 50 _ 5 O SVF Ver1 905 SVF Interpreter 3 24 1677 711 CONFIG TXT P CE 0 3 P CE 1 3 P CE 0 1 XMODE
5. CONEIGTXTY microSD O0 CONFIGTXT CONFIGTXT CONFIGTXT PO Po 0 19 50 o y 6 2 Commands gt bp mo O axs En 2277 7 5 e roca PR xexkxwx E nmm D2 a XRST TCK le a maze fes Jon Ver V1 905 CA Jon SVF Frequency S CE Joi SVF_mterpreter
6. O S9kky 1 3mm O O 82 8 1 83 45 50 E 8 2 El 8 3 84 I DILY
7. 8 FAT16 TAB TAB 8 FPGA CS Multi FPGA bitfilel rbf bitfile2 rbf bitfile3 rbf bitfile4 rbf 1 ec Hz gt fm x V1 902 KU in line in line I 26 50 mA DHO HF bitfile name E dE ES T ES A 0 F 16180 16 AREA SW
8. Pin NE Signal name Dir Descriptions No Pullup Li xem CE K 2 VCCIO gt VCCIO O TE ev a SW elo E quo PIT SERRAS 8 TO 1 330 JTAG TDOESAR DONE 9 TK JTAG TCK CCLK 10 TS O 4K JTAG TMS PROGB SW MSB ur mno O am AMZ CINTO 5 wur Ux ra o motores 09 se CE PI O 16 o High Z Hj zm Pullup D2 17 o High Z Pullup D3 fse CE 9 wfo EN G 20 O High Z Pullup D5 Cn xem O AZAR Do x amp Rm 0O RAZA 0 GVF 24 o HighZ Pullup XCS1 X 4 4 uSDCONF1A03JTag 12 50 In 0 D XAREA 3 0 XMODE DONE nCONFIGnSTATUS Pullup 4 5 XAREA CONFIGITXT microSD
9. 0 9 30h 39h A F 41h 46h af 61h 66h gt ALTERA rbf XILINX bin bit 8 FAT16 TAB TAB 8 Multi FPGA 0 bitfilel rbf bitfile2 rbf binfile3 rbf binfile4 rbf 1 V1 902 KU in line DaisyChain in line V1 904 E
10. 85 Amazon PRO Amazon PRO 309018 0000 4905533 132782 8 4 46 50 9 UOL ww 5 7 Adapter H91HHHHHUHHHHHHUHHHHI Q Q9 59J TagStick ALTERA HI U LU LI LU XILINX L1 LL U L HHHHHHHHHHHHHHHHL Gbyte microsSDCard L Hu L1 HL ODO DO LL DD LE HL UO D OD COD SDCard LL readme Hi OO BU OOO DO DO OOO D 7E B 7 HE UI U 7 E 0 Datasheet 1 CONFIG TXT O O O O ALTERA Xilinx S
11. 60MHz FPGA TCK gt 50MHz 0 50MHz 1 25MHz 12 5MHz 6 25MHz 57IMHz 2 778MHz 1 923MHz IMHz A OQ ta A Q N gt 60MHz 0 60MHz 1 30MHz 2 15MHz 3 7 MHz 4 SMHz 5 3MHz 6 2MHz 7 1MHz SVF FREQENCY TCK 21 50 5 mA d HP SS 0 1 JTAG JTAG LSB 0 TDI MSB LSB 0 MSB 1 LSB e P SB 0 1 JTAG AP SW 0 1 JTAG g HP PR XXxx xxxx h P PO FPGA
12. CONFIGTXT CONFIGTXT 8 microSD rename 0 5 0 5 1 CONFIGTXT 8 microSD 8 rename microSD SVF GVF SVF Interpreter 3 24 3 3 CONFIG TXT THP C9 1 microSD R 5 1 LED 15 50 mA 5 2
13. SOMHz SD SD 17msec 000C 0000 15 7msec SD m P PW xx JTAGOIRLYASDADES 16 0OA 10bit JTAG V1 8xx Virtex7V2000T 7VX1140T 7VH580T 7VH870T rcAwike AA Mem Aldo UG me rn pre wr TUER HHHHHHHH wes OD L LT CI CI ci Lers 0AQ0b To So li o lerf lm To So CI BE 23 50 a w A 9 n P C0 1 2 3 4 5 6 7 8 9 0 1 DO 0 9 HP HP HP HP HP
14. Data Bus AII 1 TCK 16 8 0000 0000 FFFF FFFF 16 0000 0000 0000 0000 FPGA 0000 0000 Altera RBF 32 FF XILINX bin 32 DO FF XXXX XXXX FPGA Initialazation TCK FPGA
15. 0 M o 1 E 2 Filel file2 F uSDCONF1A03JTag 59JTagStick 20 50 mA 6 3 Commands a o s slash CR Verilog A X Maker 7 4 2 PO FPGA c 4S 0 1 2 3 4 5 6 78 9 A B C D JED 30MHz 60MHz 50MHz
16. LED 16 1 0 4bit Hex BRO Abit Abit 4bit 2 Abit 8 3 CA 0 1 1 SVF FREQUENCY S TCK 0 CE 0 1 SVF P CE 0 ERR3bit ERRLINENO24bit
17. XMODEpin SW O ON 3bit LINENO24bit 1 OFF 3bit LINENO V1 904 XMODE XMODE XMODE XMODE 3 100 IDCODE IDCODE IDCODE om meme IDCODE 010 INIT INIT 1 011 DONE DONE 1 001 TDO TDO 111 SVF ERR3bit LINENO24bit 503msec 168msec 1 68sec a e ep 670msec
18. Ver1 905 LED 0 5 0 5 3 6 111 110 6 1 101 100 5 1 011 4 1 010 3 1 001 2 1 000 1 1 6 5 02 6 5
19. AREA 3 0 0 F 16 16 XAREA 3 0 AREA 3 0 CONFIGTXT 16 16 4 2 XAREA 3 0 SW l dlls mm H ar w EAN L m juro L v fuso o w w 24 L H r E A 0 9 L L H 76e L L ESA H H H j zUZT8 C Z H bol T le T ul FIZIO T DT L 9 o ow ja 4 2 XAREA 3 0 L L 13 50 O 46 XMODEH Ver1 905 KY SVF Interpreter LED 5 3 SVF XMODEpin SW O ON 3bit LINENo 24bit
20. 5 2 LED LED 0 1 16 2 4 1310 1h 3 1h Oh 503msec 4 di 4 d3 4 d1 4d0 Version 1 310 5 2 LED 18 50 O 6 CONFIGTXT 6 1 CONFIG TXT EI amp microSD FPGA
21. Data Bus AII 1 TCK 16 8 0000 0000 FFFF FFFF 16 0000 0000 FFFF FFFF TCK COBRA HR 0000 1000 DCLK DONE 22 50 mA 1 FP PM xxxx XXXX JTAG k FP D1 xxxx xxxx JTAG 1 P D2 XXXX XXXX XRST High TCK 16 8 0000 0000 FFFF FFFF 16 x 20nsec
22. PR 0000 0000 PO 0000 4000 4096CLK HP HP HP HP HP HP D1 0000 2000 nSTATUS DCLK 164usec D2 000C 0000 XRST nCONFIG 15 7msec C0 0 C1 0 Pump ON C2 C3 0 Bus Multi FPGA mode C9 0 SS 1 LSB SB 0 Swap FEL SW 0 Swap 0 50MHz Slave PR 0000 0100 256CLK HA PO 0010 0000 1048576CLK D1 0000 0010 INITB CCLK 320nsec D2 000C 0000 XRST PROGB 15 7msec C0 1 C1 0 Pump ON C2 C3 0 Bus 9 EI Multi FPGA mode C9 0 39 50 Sd 69 RBFHHHHHHHH Quartus II Tl PullDown H EH UD D l File gt Converter Program Files DU OOOO NOW Window 00000 rbf Save Conversion Setup t programming file ills TI X 2 3 Options Configuration device Dit Passive Seria File name G work a toiawase 2013 20130522 XXXX AES 201306 12JushinData FPX 004 sd test rbf a Advanced Remote Local update difference file NONE rDZMREDT PIINATI E Fast Passive Paralel x32 Create CvP files Generate s
23. SPI Master Slave JTag JTag o ROM e uSDCONF lt gt AE T 220 0004 1 11 1 7 FreeCall 0800 7775559 9 00 18 00 045 590 6227 Fax 050 3156 1404 Email info01 59kk jp URL https www 59kk p 50 50
24. HP HP HP HP C0 01 JTAG C1 0 1 nCONFIG Pump ON JTAG JTAG C2 0 1 JTAG JTAG hi Cla C3 0 1 JTAG TAG C4 0 1 JTAG TAG C5 0 1 JTAG C6 0 1 JTAG C7 0 1 JTAG C8 0 1 Reserved 24 50 HP HP P mA C9 0 1 V1 905 ON
25. 1 OFF 3bit 5 LED 9JTagStick LBD 27 1 LED 14 50 5 LED LED LED rh 167msec 167msec SVF GVF _ G i 3 Ga microSD JTAG LED 1 3 lll 6 1 110 6 1 101 5 1 emo 100 1 011 4 1 010 3 1 001 2 1 000 1 1 microSD CONEFIGITXT
26. P CE 1 BRR3bit XMODE XMODE ON ERR3bit ERRLINENO24bit XMODE OFF ERR3bit XMODE uSDCONF1A03JTAG XMODE 59JTagStick XMODE XMODE 25 50 o ZR 0 F JTAG p bitfile name a b Line Processor Line Processor rbf
27. 1 fpgal bin p pw 06 fpga2 bin p pw 10 fpga3 bin HHHHHHHHHHHHHHHHH 0 fpga1 bin EM A tp d2 0000 0020 fpga2 rbf GEM X fpga3 bin 29 50 o Da 6 4 3 FPGA FPGADODODDO B B D EL B E U D U UI bypass t 000 8000000000000 pypass tsfHHHHHHHHHHHHHHHHHHHHHHHHHHHHLH HHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHH mieroSDCardHHHHHHHHHHHHHHOHHHLH HHHHHHHHHHHHHHHHH Ifpga2 bypass HHHHHHHHHHHHHHHHHHHHHHHH 000 0 fpgal bin bypass2 txt fpga3 bin fpgan bin HHHHHHHHHHHHHHHHHHHHHHL uSDCONF1A03JTag 30 50 6 4 4 In Direct 0000000 vi905 DD D D BH OD HL OL BL OL D DT SPIO BEIHHHHHHHHHHHHHHHHHHHHH badge T 000 800000 UDDDBDID brdgeX bivrbPT D DD DDDD BD SPIO BPI0000 ROM HHHUHHHHHHHHHHUHHH 00060 O bridgel bin fpgal bin bypass txt bypass txt bypass txt 000000001006 bridgel bn 1000 FPGAT TT LU LU 2 HH fpgal bin HHHHHH1HHH FPGA NO bridget HHHHHHHHHHHHHH SPI ND BPI U fpgal bin T 000000000 SPI BPI LI D D D E DE HE UU DU D D bin rbf mes kx D D D UU 0 U l HHHUHHHHHHUHHUHHHHHHHUHHHLH bridgeX bimrbfHHHHUHHHHHHHHHHHHHHHHHHHHHHLH 31 50 mA 65 SVFII ULULELULULU 6 5 1 SVF I LULUL U D 59JTagStick uSDCONF1A03JTag O HVer1 904 SVFHHHHHHHHHHHHH HHHHHHHL SVF Sernal Vector Format DJTAG O TCK TMS TDL TDO O HIHHHHHEPeGAHHHHHHHHHHH
28. mA 59JTagStick 59JTagStick 8 Rev1 05 2015 04 17 ROMVerJ1 906 Rev1 04 2015 04 12 ROMVerJ1 905 Rev1 03 2015 03 02 ROMVer J1 904b Rev1 02 2015 01 22 ROMVer J1 904 Rev1 01 2014 12 12 ROMVer J1 902 Rev1 00 2014 12 02 ROMVer J1 902 1 50 _ 5 Dn al 30141271 DE 2014 12 12 6 5 5 DaisyChain in line 20522 XE d _ LLL 2015 3 2 X RE 1 03 JTAG 6 5 SVF 6 6 reformSVF 6 10 CONFIGTXT 2015 4 12 8 3 4 6 XODE 5 1 LED SVF interpreter 5 2 5 3 SVF 5 4 6 3 Commands c S 6 3 Commands n AD P C9 6 3 Commands n P CA 6 3 Commands n D P CE 6 reformSVF exe EINEN ES 1 1 59JTagStick TCK j j I 2 50 L 1 2 7 5 l de u oa 5 5 ss 1 I E q A 8 8 A IO E 2 8 8 9 9 42 5 IA
29. JTAG Hi Z XRSTLSD_DETX Hi Z 3 JTAGEN SD DATO Low SDCard Adapter SD_DATO Low Pulldown SDCard JTAG JTAGEN Hi Z EL 4 7K Q Pullup High TDI TCK JTAG TDO SD DATI XP2 CPLD JTAGEN Hi Z JTAG XRST SDCard SDCard JTAG SD_DAT1 TDO JTAGEN Low 44 50 mA 8 8 1 8 2 uSDCONF1A03JTag
30. S0MHz 60MHz TCK D2 1 8 3 EFAT 22 FAT 512 5 50 AAA O FPGA o9JTagStick 8 uSDCONF1A03JTag 8 Vcc ref 1 1 59JTagStick microSD 2 on SUR fanout 2 buffer DmicrosD gt FPGA microSD gt FPGA XMODE d CE a H 5 sw E 1 2 uSDCONF1A03JTAG 6 50 s M 9 2 59JtagStick uSDCONFIA03JTAG 2 1 59
31. input 6 VCC3V3 P 4 7K JTAGEN T 3 TMS Lvcos A N TDI A A Lvcos TCK LVC126 DS 7 2 1 SDCard 1 HL D D D D LUI D D O 7 2 SDCard SD XRST SD DETX assign SD PWRX XRST SD DETX SD DETX SDCONF TRANS SDCard 1 SD_DETX 1 b1 SD DETX 1 b0 7FFFh x 20nsec 655usec SDCard SDCard SDCard SDCONF3 ERROR ERROR AT HIBERLT BF XRST ERROR D IO Tri State SD_DAT O0 3 SD CMD SDCard UT XRSTISD_ DETX Hi Z SD CLK
32. 0000000000000000000000 000000000000000000000000000 SDR I 39 50 o Qa 6 5 4 SVEGVFT II D UD DD D IIHHHHHHHSVEGVEFHHHHHHHHHHHHHHHHH OOOO SVEHHHHHHHHHHesDRHHHHHH 266HHHHHHHHHHHHLH HHHHHHHHHHHHH SVEGVEHHHHHHrpfH b bitrt HH OU D D UO UL D DUE UO D U 7E 706 D E FF D I U L HHHHHHHHHHHHHHHL HHHHHHHHHHHHHHH SVE GVEOHHHHHHHHHHHHHHHH 000000000000 SVE GVEOHHHHHHHHHHHIHHHHHHHHHHHHH 000 HO filel svf 1 erase gvf pre only gvf HL E E HL E E E D FPGA FPGA2 FPGA3 FPGAn 34 50 O 6 6 reformSVF exe reformSVFexe reformSVF I O 0O reformSVF how2use rev1 pdt HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHL UDO DODOLDUL SV D UJ l reformsSVEFHHHHHHHHHHHHHHHHHL HHHHHHHHHHHH DragHHHHHHHH 35 50 9 6 7 D1 D2 PO I EHIHWu uu 6 7 1 I XRST D10000 L FPP uSDCONF1A03 D2 ALTERA tCFG nCONFIG low pluse width 2usec uSDCONF1A03 SDCard config txt 17msec Low JTag uSDCONF1A03JT
33. 0010 0000 320nS def 15 7mS def def Artix 7 105 gt 5ms 150ns lt Spartan 6 5 lt lt 4ms 6 5 2 XILINX D1 D2 PO 1 J Kintex 10S lt Sms 150ns 0000 0010 000C 0000 0010 0000 lt 50ms 320nS def 15 7mS def def 37150 68 HHHHUHHHH HHHHHL CONFIGTXT 1 Maker Maker ss Code Name P SS 0 MSB P SB 1 Swap P SW 0 Swap FS 0 50MHz Passive HP PR 0000 0100 HP PO 0001 0000 65536CLK HA HP PM 0000 1000 4096CLK HA HP DI 0000 0010 nSIATUS DCLK 320nsec HP D2 000 0000 XRST nCONFIG 15 7msec HP C0 1 P C1 0 Pump ON P C2 C3 0 Bus Multi FPGA mode 4P C9 0 38 50 mA 2 ALTERA Maker Maker Code Name l 3 XILINX Maker Maker Code Name HP HP HP HS HP HP MSB Swap Swap 0 50MHz Passive
34. AG E H B B U D XILINX H D 00000000 GVE 1MPACT SVF I reformS VF GVFOLUUUUDULUU S DD UI p pw 0000000000 L GVFHHHHHH DO RAMHHHHHHSETH BPIHHHHHHHHHHHL C erase gVf x ED 000000000000 SvrGvPp 00000000 D erase gvf prg_only gvf x E fileE bit F fileF bit iMPACT SVF ODO E DL reformSVF LU J x B prg_spi gvf end Woseooooeooooooo 6 10 2 CONFIGTXT 42 50 43 50 DCard 1 U D D UE D LI UL SDCard Socket VDD PROTECT SD DETX COMGND SD_DAT1 SD_DATO SD_CLK SD_CMD CD DAT3 SD_DAT2 Vss Vss R f SDCLK EN lt SDCLK SDCMD C SDCMD O JTAGEN EN VCC3V3 TPS2550DRV XP2 5 4 VCCSD GUT n XEN SD PWRX 130R ER EE VCCFLSH 1 8V GND B an PROTECT BE MK SD DETX Di 6 V47K SD DAT input 7 V47K SD DATO input 5 V47K SD CLK 2 V47K SD_CMD x 1 V47K CD DAT3 input gt gt SDCMDI 9 WVA7K SD DAT
35. DCard Ll 1 L 192HHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHH 50mm x 85mm x 20mm UT 47 1 50 m X O 10 HH DOLO VCCIOI E LB D EE UT D uSDCONFI1AO3JTag O O O0 LL DL D D VCCIO 1 E CEU D D DE EL UU D miereSD D BD D D DD DU IlHHHHHHHHHHHH HH 13100 59J1agStcklHHHHHHHHHHVCCIOI2 56VHHHHHHHHHHHHHHHHH mnnnnn veo umm nmm Im ssmsw uwewomssw one O 13 1 48 50 O 11 D SD 2G 2G FAT16 SD SD SD LED FAT32 2G SDHC 2G microSD FAT32 FAT16 Microsoft W
36. DOADA COCO u aaa 10 SS hpa VS DS O NS A nen 11 44 WSDEONFIAUI ITIEE IR PK M 12 D OEEP C dp 0 13 Eo 14 SO 14 SSP 15 A o e e o O A 16 D o ONE F aro m 17 54 E A A 18 EC ON T E r E AE E E E E EE S E 19 Gl ON 19 O Oad Pi u pra ua nanan reerae 20 6 CU Te 21 6 4 1 DaisyUhainl mline HB LT zes ss een neu 28 DAL Jaco mur u ee ee 28 Do ei HE d A a dup du eun 29 ot CAM O aan 30 6435 A ee 31 Do PVE ce een 32 role DS PE AAA oc 32 Do gt ITP HPP n MO m P taa crepas 32 od Oh ipi pp ph PD aii x OEE 39 OP E SE 34 65 Sorma Pee A uuu uuu n nunanmanta asas sasana 35 3 50 67 D1D2PODODO DD arena nennen nnne 36 SEE DU 36 6 8 DDJDDDDDDD An 38 69 RBFOIQOODADO ee 40 6 10 CONHTG TXT eee 41 CoOL ER Cc A 41 6 10 2 XILINX DO oo 42 7 DCard B D HI ELO UI D 43 EN 43 12 SDCadi 0000 DD ersen ANEAN TANE i 44 8 erre rrenan 45 8 1 es 45 2 TITTEN E e O EER EEE 45 cd E A een 47 10 VCCIOHHHHHHHH ee 48 l kk 49 12 kk 50 4 50 1 1 mA 59JTagStick 1 L uSDCONF1A03JTag JTAG VCCIO
37. HHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHL Programmer iMFACTHHHH JTAGeHHHHHHHHH TPGAHHHHHHHHH HIHHHsSVEFHHHHHHJTAGHHHHHHHHHHHHHHHHHHHHHHHHH uut tli uU HHHHHHHHHH SVEHHHHHHHHHHmnieroSDCardHHHHHH SVET LU HIHHHHHHH JTAGHHHHHH FPGA UL U HH B ODO HE B DL D D UO HE U HE DU LU 0000 ROMHHHHHHHHHHHHHHHHHHHHHHHHHHHHH 6 5 2 MEM 1000 RUNTEST run count TCK gt FFFFFFFF SCKHHHHHTCKHHHHHHHHHH min time SEC gt 85E00 SE 85 J 86E00 SEC 1 BU D HL HL BU D D D 1E00 SEC T ET D DT U D UI L length TDI tdi TDO tdo MASK mask SMASK smask Length 256 256000000000 reformSVF SIR length TDI tdi TDO tdo MASK mask SMASK smask um Length 256 256HHHHHHHHH reformsvF p DO ImnHTDR DDDDDDD S s Taa BEE ldTRST Joon 8 o o 32 50 65 3 GVFHHHHHHHHHHHL SVEHHHHHHHHHHHHHHHHHHsDRHHHHHHHHHHUHHUHHLH HsDRHHHHHHHHHHHHHHHHHHUHUHHHHHHHHHH HEXHHHH HHHHHHHUHHHHHHHHHHHHUHHHHHHUHHHHHHHHUHHHHL HHHHHHHHHHHHHHHHHTDIH First 1NHHHHHHHHHHHHHHLH HHHHHHHHHHLast1N7EirstOUTHHHHHH HHHHHHHSVEHHHUHUHHHHHHHHHHHHHHHHHHHHHHHHHHH U reformSVEFHHHHHHHsSDRHHHHHHUHHHHHHHHHHHHHHHHHH HHHHHHHHHHHH HHHLIGVEHHHUHHHHHHHHHHHHHHHHHH SDR 111836736 TDI 00000000000 ffffffffF00000000 SMASK ffffffffFfffff fffffffff TDI SDRS 256 TDI 0000ea10000000000000000000000000000000000000000fffffffff00000000 T TDI SDRS 256 TDI 000000000000000000000000000000000000000000
38. JTagStick 1 27mm 1 26mm Sm E 2 2 uSDCONF1A03JTAG 7 50 3 3 14 DIU U supply Voltage VCC3V 0 2V to Input or I O Tristage Voltage Applied 0 2V to Storage Temperature Ambient 65 C to 32 D BI Ult supply Voltage VCC3V 1 2V to Ambient Temperature 0 C to 3 9 DI LU U 59 3 75V 3 75V 150 C 3 6V 70 C mage ve ma vecina Wm sb AK vooo Juma REO Mari emo o 3 3 200mA ROM 8 50 mu 5 Dn 4 Pin 41 HHHHL 59JTagStick 1 3 5 7 9 11 13 _ 4 1 59JTagStick E 9 50 5x 4 2 ALIERAHHHHHHH BOLD E E S b 1L O LI LJ Lie 2 O O LJ Lio CO I 9 mm OD j X 42ALTERA 10750 5x 4 3 XILINXIJ HD ELO BD UO D BE D 7E DI a SSTATUSQNITB I 1357913 enbo lm 00000 4 3 XILINX 11 50 mA 4 4 uSDCONFIAO03 usSDCONF1A03JTag DO Hi D B DO DH DO HH E BD H E DH B DD B EE 7 UE OE DI Front side 8 000000000000 i e 3 vf o Lad us 1 27mm
39. O 9 0 0 0 0 0 0 0 0 0 0 0 o el a a e e 0 0 0 0 0 0 0 1 0 7 S 2 N IDCODE 4 hO 4h0 4h0 4 h0 4 hB 4 h8 24h0000B8 184 IDCODE 17 50 o O LT OOOO O 0 168msec 670msec O V1 905 CONFIG TXT T 4P C9 1 LED 5 1 amp 16 4 4 LED 0 1 168msec 670msec 0 503msec 3 670msec 1 16 1 68sec
40. U SVF GVF Se 27 1 50 6 4 DaisyChain in line L LH L U O0 V1 902 in line FPGA FPGA 6 4 1 DaisyChain L L J DaisyChain D H DO O O AUTERA FPP PSIXILINX SelectMap SlaveSerial HHHHHHHHHHHL 0 fpgal rbf fpga2 rbf fpga3 rbf fpgan rbf HALTERA 1 fpgal bin fpga2 bin fpga3 bin fpgan bin XILINX HHHHHHHHHHHHHHHHL JUDO mnDirectHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHIH HHHHEPGAHHHHHHHHHHHHHLH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHUHHHHHHHHH 28 50 mA 6 4 2 In line 0000000 IIHHHHHHH TPGAHHHHHHHHH FPGAHHHHHHHHHHHHH FPGA HHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHOV1 902 HHHHHHHHHLH JTAG FPPPS SelectMAPSlaveSemal U FPGAHHHHHHHHHHHHHHHHHHHHHHHHHHHHI HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHL 9HHHHHHHHHHHHHHHHHHHHHHHHH inline J0000000000Y0 000000000000000000000000 HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHLH 0000 HHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHH 000000000000 0042000000000 0 fpgal bin M A fpea2 rbf GEM X5 fpga3 bin
41. ag nCONEFIG PROGB nSTATUS INITB D2 RST TCK D1 ALTERA tST2CK nSTATUS hgih to first rising edge of DCLK JTAG DI 0000 0200 10uSec gt config xt D1 0000 2000 164usec PO ALTERA USRCLK 6 1 FPGA FPGA FPGA Read Data from SDCard JTAG STATE Read binarydata Read rest of till buffer is full binarydata Read i pr Paramet
42. d test periph rbf and sd test core rbf EN 1bit Passive Serial N SOF Data Add File HHHHHHHrbfHHHHHHH HHHHHHHHHHHHHHHH8SHHHHHHHHHHHHHHH SDCardHHHHHHL uut HHHHHHHHHHHHHHHHHHrpfHHHHHHHHHHHHHH 1 bit Passive Serial U E U U Look in G work a_toiawase 2013 201305 AES 20130612JushinData Fpx 004 gt O O O E IE File Ider 2013 06 13 17 09 54 File Ider 2013 06 15 5 23 46 27 2MB sofFile 2012 08 02 11 28 00 BSfELTUAL Kev _fpga sof File name GOKU fpga sof Files of type SRAM Object Files sof y Cancel Z o HHHHHHHHHHOpenHHHHHHHH I Generate HHHHHUHHrbflHHHHHHHHHHH I HUHUHHHrbfH SDCardHHHHHHHHHHHHHHHHHL 40 50 mA 6 10 CONFIG TXT O O O microSD root CONFIGTXT 6 10 1 HHHHHHL fp pr 0001 0000 ror Ayam ae y FeAHHHHHHHHHHHHHCLKRH Hp pw 0A ALTERA B0 file0 rbf RSTDODO TCKHHHHHHHHHHHHH 1 file1 rbf ODDO CLKIJDU D D D m SPIHHHHHHHHHHHHHHHHHHH x 2 file2 rbf H3 file3 rbf 4 file4 rbf file5 rbf adi 10 0 Bypass Ho files rbf Bypass txt Obyte x 6 bypass txt f
43. ers N Delay 2 r D2 000C 0000 15 7ms Hi Z Test Logic Reset Shift DR IDLE i i i 1 1 ERRO rono 7 Hi Z ea3HHHHHHHHLH 36 50 _ G Qa Cyclone III lt 800uS gt 800uS 2uS 3 185 0000 0200 000C 0000 0000 1000 Cyclone IV lt 230uS 230uS 2uS 3 192 0000 0200 000C 0000 0000 1000 m quem me em pm Cyclone V 1 506uS gt 1 506uS 2uS 17 408 0000 0200 000C 0000 0000 5000 I Stratix III lt 100uS gt 100uS 2uS 4 436 0000 0200 000C 0000 0000 1200 mpm mepmm Stratix IV lt 500uS gt 500uS 2uS 8 932 0000 0200 000C 0000 0000 2400 mm que e a Stratix V lt 1 506uS 2 1 506uS 2uS 17 408 0000 0200 000C 0000 0000 5000 m qt m Arria GX lt 100uS gt 100uS 2uS 299 0000 0200 000C 0000 0000 0200 mm qempmpm Arria II gt 500uS 500uS 2uS 8 932 0000 0200 000C 0000 0000 2400 m qo fe Pe Arria V 1 506uS 2 1 506uS 2uS 17 408 0000 0200 000C 0000 0000 5000 6 5 1 ALTRA D1 D2 P0 D 0000 0010 000C 0000 0010 0000 0000 0010 000C 0000 0010 0000 320nS def 15 7mS def def 0000 0010 000C 0000 0010 0000 320nS def 15 7mS def def FPGA Series HICCK CLKUSR Virtex 5 105 lt 3ms 400ns gt 50ms Virtex 6 155 lt Sms 400ns lt 55ms Virtex 7 10S lt Sms 150ns gt 50ms PL 0000 0010 000C 0000 0010 0000 320nS def 15 7mS def def 0000 0010 000C 0000
44. ile6 rbf 1 file T file7 rbf 8 file8 rbf 49 file9 rbf A fileA gvf HB prg spigvf x C erase gvf x ED ugagagaudauauud SVE GVEHHHHHHHHH x D erase gvf prg only gvf x M A Maker 1 FPGA TCK Fmax 8 2 0 50MHz 1 25MHz 2 12 5MHz 3 6 25MHz 4 5 6 7 i Lu ULL p ss 1 JTAG LSB First Data D D B B U U l HHUHUUHUIHIUIHUIHUIHUHUHHHH JTAG E HU B B D ALTERA OA 10biO D J Doo o Co COCO COCO CO EB E E ELE TL TT T VH programmer SVFT lH reformSVF GVFO000000000 S 0 0000 p pwz 0000000000 L GVF EH H DJ JU programmer SVE J reformSVF JUL SPI BPIHHHHHH E fileE rbf F fileF rbf Ilend m et El 6 10 1 CONFIG TXT 77 JU 41 50 6 10 2 XILINX O U M X Maker x FPGA TCK Fmax S 2 0 50MHz 1 25MHz 2 12 5MHz 3 6 25M Hz A 5 6 T x JTAG LSB First 0000000 x p ss 1 Data O0 HU B LU U D fp pr 0000 0100 131 0 72clk Data 0 0 D 0 D gt 1 U D E FPGAHHHHHHHHHHHHH KO p pw 06 KINTEX 06 0 file0 bit RSTDODO TOK 1 filel bin N HHUHHHHHU CLRHHHUH 2 file2 bit ET PTT 43 file3 bit HHHHHHHHHHHHHHHIHHHHHHH 4 file4 bit files bit 1000 Bypass 5 file5 bit REO an 6 bypass txt file6 bit file 7 file7 bit 8 file8 bit 9 file9 bit A fileA gvf JT
45. indows FAT D 8 FAT16 8 microSD rename 8 8 7 CONEFIGTXT microSD Windows Linux Unix microSD Linux Unix Windows Wo 4 Vir
46. tex 7 7V2000T7VX1140T 7VHS80T7VH870T FPGA BPI SPIROM O SVF 49 50 12 S9kk 128 HS Key Encryption msd Adapter JTag Key bit S9kk Key Tag gt FAT32 SDHC microSD
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