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MVME2500 Installation and Use - Artesyn Embedded Technologies

1. 1 5 1 5v PGOOD BSCRST_N MUX reset is deasserted 3 3VFROM 5 0V B JTAG MUX A JTAG MUX is running at this time CPLD C CPLD is running at this time RESET The reset pin of each IC will be deasserted depending on their time requirement after power up PR V1POS EN 1 05 Supply is enable by CPLD PUR VIPOS PWRGD 1 05 Power is Good 2 PUR V1P2 EN 1 2v Supply is enable by CPLD PR VIP2 PWRGD 1 2v Power is Good PR VAPB EN 8V Supply is enable CPLD PWR_V1P8_PWRGD 1 8 Power is Good PWR_Y3P3_EN 33v Supply is Enable by CPLD if 1 05V 1 2V and 1 8V are GOOD PAR V3P3 PWRGD i 33V Power is Good PWR_V2P5_EN 2 5V Supply is EnableD when 3 3 is GOOD PR V2P5 PARGD H 2 5 Power is Good 3 PR VAP2 SW EN 11 2V SW Supply is enable by CPLD 2 5V is GOOD 3 2 SW PARGD i 1 2 SW POWER IS GOOD PYWR_V1P5_S3_EN asserted if 3 3 Power is GOOD PR VIPS S5 EN asserted if 3 3 Power is GOOD PAAR VIPS PARGD 4 LSV Power is Good 140 500ms 4 1 8V supply turn ON time POWER SEQUENCE DIAGRAM ms 3 3 supply turn ONtime DOT NUES u 35ms 1 24 Switch supply turn ON time 6306822HA cpm a 14045 1 5V switch supply turn ON time B Ic ms D Im E ms 1 05 supply turn ON time 1 2V supply turn ON time G Sms
2. 10 after 1 5 GOOD and stable clock 3 USB CONT RST 30000000000 atter 33v GOOD QUART RESET 30000000000 Toms after 33V 500 TSH48 PLL RSTI N PURST_N CPU_HRESET_L 189999999007 iat least 100us a CPU TRST L iat least 100us RESET SEQUENCE SE x PAGE OF 87 A e D MVME2500 Installation and Use 6806800L01L Functional Description 4 18 Thermal Management The MVME2500 utilizes two on board temperature sensors one for the board and the other for the CPU temperature sensor The board temperature sensor is located near the dual RJ45 connector near the front panel The CPU temperature sensor is located near the P2020 CPU The MVME2500 thermal management support will interrupt the process only to show the current board and CPU temperature This interrupt is routed directly to one of the processor s IRQ4 The table below shows the low and high threshold temperature in order for the interrupt to be asserted Table 4 2 Thermal Interrupt Threshold Board CPU Temperature Temperature Limit Limit Board Variant Board Temperature Limit Low High Low Standard Variant 0 to 55 C Extended Temperature 55 C to 71 C Variant 4 19 Real Time Clock Battery A back up battery based on the CR2325 specification is provided It helps support t
3. MVME2500 Installation and Use 6806800L01L 147 Related Documentation B 2 Manufacturers Documents For additional information refer to the following table for manufacturers data sheets or user manuals As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table B 2 Manufacturers Publications Company Freescale Document Freescale Semiconductor QorlQ P2020 Integrated Processor Reference Manual Rev 0 Tundra Semiconductor Corporation Tsi148 PCI X to VME Bus Bridge User Manual March 2009 Related Specifications For additional information refer to the following table for related specifications As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table B 3 Related Specifications Organization American National Standards Institute ANSI VITA Standards Organization Document ANSI VITA 1 0 1994 R2002 VME64 Standard ANSI VITA 1 1 1997 R2003 VME64x Extensions ANSI VITA 1 5 2003 VME 2eSST ANSI VITA 35 2000 Pin Assignments for PMC P4 Connector ANSI VITA 39 2003 PCI X for PMC and Processor VITA Standards Organization 148 High Speed Switched Interconnect Protocols on PMC VITA 42 0
4. em PRI Sigua ERR A SE Ro ala 118 5 6 3 Compare High and Low Word 119 5 6 4 Counter High and Low Word lt 120 6 MVME2500 Installation and Use 68068001011 Contents 6 Beetsystem n nenn 121 6 11 CLE 121 6 2 Accessing U BOOb 121 6 3 BOOtODptlOs a ea KE eb 122 6 3 1 Booting froma Network hen 122 6 3 2 Booting from an Optional SATA 123 6 3 3 Booting froma USB Drive km bed 123 6 3 4 Booting from SD Card 6 ee hh 124 6 3 5 Booting VxWorks Through the Network 2 cece eee cece eee eee 124 6 4 Using the Persistent Memory Feature eee 125 6 5 MVME2500 Specific U Boot Commands 126 6 6 Updating USBOOt nu nahe er Oen E esee 128 7 Programming Model or u a ann 131 PME UJUI I O 131 1 2 Reset Configuration nen cada 131 7 3 Interrupt Controller i e eer ee REPRE ee eee DEF Eae ge 135 7 4 2CBus Device Addressing 0 cece cece ence nee nee eee e e en 136 7 5 Ethernet PHY Address 22 ine ae a 136 7 6 Other Software Consideratio
5. 110 Table 5 15 PLD Test Register 1 u ee EX eee 112 Table 5 16 PLD Test Register 2 asian 112 Table 5 17 PLD GPIO2 Interrupt Register eee tk inini 113 Table 5 18 PLD Shutdown and Reset Control and Reset Reason Register 114 Table 5 19 PLD Watchdog Timer Refresh Register 115 Table 5 20 PLD Watchdog Control Register lesse me 116 Table 5 21 PLD Watchdog Timer Count Register 116 Table 5 22 Prescaler Register renn titi ee REI E 117 Table 5 23 Control Registers oic RR PER be e Aer aue bte ripa 3 118 Table 5 24 Compare High Word Registers 119 Table 5 25 Compare Low Word lt lt 119 Table 5 26 Counter High Word Registers m 120 Table 5 27 Counter Low Word lt 8 120 Table 6 1 MVME2500 Specific U Boot Commands 126 Table 7 1 POR Configuration Settings Ih 131 Table 7 2 MVME2500 InterruptList eee cece eee eee nee nee eee eens 135 Table 7 3 I2C Bus Device Addressing I 136 Table 7 4 PHY Types and Management Bus Addre
6. page 91 USB Interface The P20x0 implements a USB 2 0 compliant serial interface engine For more information see USB on page 90 DUART The chipset provides two universal asynchronous receiver transmitter UART each of which acts independently of the other Each UART is clocked by the CCB clock and is compatible with PC16522D As a full duplex interface it provides a 16 byte FIFO for both transmitter and receiver mode MVME2500 Installation and Use 6806800L01L Functional Description 4 2 9 4 2 10 4 2 11 MU 4 2 12 DMA Controller The DMA controller transfers blocks of data between the various interfaces and functional blocks of P20x0 that are independent of the e500 cores The P20x0 DMA controller has three high speed DMA channels all of which capable of complex data movement and advanced transaction chaining Enhanced Three Speed Ethernet Controller eTSEC The eTSEC controller of the device communicates to the 10 Mbps 100 Mbps and 1 Gbps Ethernet IEE 802 3 networks as well as to devices with generic 8 to 16 bit FIFO ports The MVME2500 uses the eTSEC using the RGMII interface General Purpose 1 GPIO The P20x0 has a total of sixteen I O ports Four of these ports are used alternately as external input interrupt All sixteen ports have open drain capabilities The P20x0 processor provides a Serial Rapid 1 0 interface However this interface is not utilized by the MVME2500 Security Engin
7. 1 GA2 0 GA2 1 7 Wi GA1 0 1 1 8 0 GAO 1 Table 3 19 Geographical Address Switch Position Function Default VME SCON Auto Auto SCON VME SCON SEL2 Non SCON GAP 1 GAP4 GAP3 GAP2 1 The VME SCON MAN switch is OFF to select Auto SCON mode The switch is to select manual SCON mode which works in conjunction with the VME SCON SEL switch 2 The VME SCON SEL switch is OFF to select non SCON mode The switch is ON to select always SCON mode This switch is only effective when the VME SCON MAN switch is MVME2500 Installation and Use 6806800L01L Controls LEDs and Connectors 3 5 2 SMT Configuration Switch 52 This eight position SMT configuration switch controls the flash bank write protect selects the flash boot image and controls the safe start ENV settings The default setting on all switch positions is OFF and is indicated by brackets in Table 3 20 Figure 3 6 Configuration Switch Position Normal ENV Boot Block A Flash WP N PMC XMC SEL PMC 133 Master WP Disabled GBE MUX SEL Reserved Table 3 20 Geographical Address Switch Settings DEFAULT Signal Name Description Notes OFF Normal Env NORMAL_ENV Safe Start ON Use normal ENV OFF Use safe ENV MVME2500 Installation and Use 68068001011 73 Controls LEDs and Connectors Table 3 20 Geographical Address Switch Settings continued sw2 DEFAULT OFF
8. 6 Install the board into the appropriate card slot Make sure that the board is well seated into the backplane connectors Do not damage or bend connector pins 7 Replace the chassis or system cover 8 Reconnect the system to the power source and then turn on the system When removing the PMC XMC hold it by its long side and exert minimal force when pulling it from the baseboard to prevent pin damage Installing and Removing the Board This section describes the recommended procedure for installing the board in a chassis Read all warnings and instructions before installing the board The MVME2500 does not support hot swap Power off the slot or system and make sure that the serial ports and switches are properly configured NOTICE Damage of Circuits Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life Before touching the board or electronic components make sure that you are working in an ESD safe environment Product Damage e Only use injector handles for board insertion to avoid damage to the front panel and or PCB Deformation of the front panel can cause an electrical short or other board malfunction MVME2500 Installation and Use 6806800L01L Hardware Preparation and Installation Installation Procedure 1 Ss gr 8 Attach an ESD strap to your wrist Attach the other end of the strap to an electrical ground Make sure that it is securely fa
9. 82 4 2 14 P20x0 Hardware Configuration Pins 0 eee cee eee eee 82 4 3 SystemMemoLy es vances set yay 82 dere M 82 4 41 Clock ror E eee rh RC EI Rex VERE EE ERE 82 4 4 2 Internal Timer cece cece ccc cence teen heme eh ehh nn 83 4 4 3 Watchdog eh em ees 83 444 FPGATickTimer ssleesessseee III 83 4 5 Ethernet Interfaces eee nee een hm heh 83 4 6 SPLBusInterface ei ea lehren 84 4 6 1 SPIFlash Memory nee een e eee n ee rne 84 4 6 2 SPI Flash Programming III he 84 4 6 3 Firmware cence nen nennen nmn nn 85 AGA Crisis RECOV N cassis Seu Good a eee Re Oe dee 87 4 7 Front UART Control nee 87 4 8 Rear UART Control en iad en 88 49 PME XMGESites nennen he ea 88 491 PMCAdd on hehe hh eth 89 4 9 2 XMGCAdd onCatd sense ee na 89 4 10 SATA Interface SERRA ne een 90 4 14 MESUppOFLEs ecceses3 AA Ade E PEERS are ba Saree eee PPP PU CES 90 4 11 1 Tsi148 Controller 1 eese ee ee ERR eres 90 4 12 EET 90 4 13 12C Devices CLOTS ee PAPO ese ees Rete 91 4 14 Reset Control FPGA cece ccc cee ence nent e nents
10. About thisiManial an un 13 Safety Notes perti up PUE PPPePSRRDPeSeROS QE 19 Sicherliershirlelsb uso dur e TERN ARE EE DU ERE QI 23 1 Introduction ess sro ht n E EU PLE YE 29 1 1 QVGeIVIeW ee VY GP ERG e ERA M Y uev 29 1 2 Standard nen Re here vue xr eec A eR ace eh 31 1 3 Mechanical se cee a LETTERE ees 33 1 4 Ordering Information nennen ee sek ee 33 1 5 Productlldentification a ee a nah 35 2 Hardware Preparation and Installation 55 85 37 NE Jue ted 37 2 2 Unpacking and Inspecting the Board 38 2 3 Requirements ge ee 39 2 3 1 Environmental 5 0 cece eee cence eee ence me ene 39 2 3 2 POWerREQUITEMENTS va Wi E x ea MOA Seas 40 2 3 3 Equipment RequireMe nts ccc042 5556 ee 42 2 4 Configuring the Board ene ees e 42 2 5 Installing Accessoire asec dee 43 2 5 1 RearTransition Module 43 2 5 2 5 ur ese PEE 45 2 6 Installing and Removing the Board e 46
11. SD Connector 2 eaten ia pee ee kn 69 3 4 2 7 XMCConnector X 2 0 0 0 c cece cece 69 3 4 2 8 Miscellaneous P2020 Debug Connectors 70 ee aad ea ea 71 3 5 1 Geographical Address Switch 51 71 3 5 2 SMT Configuration Switch S2 0 ccc cece eee 73 4 Functional Description 77 4 1 Block Diagram en 77 78 4 2 1 6500 Processor Core cere ee ne 78 4 2 2 Integrated Memory eee eee 79 4 2 3 PCI Express Interface cece cece cece cence hmmm 79 4 2 4 Local Bus Controller cece cece cece cence 80 4 2 5 Secure Digital Hub Controller 80 4 2 6 2C Interface kr ee 80 4 2 7 USBintertace a nel 80 4 2 8 DUART ea a eae ete 80 4 2 9 DMAController eoi RR erre teed ee era cotter 81 4 2 10 Enhanced Three Speed Ethernet Controller 81 4 2 11 General Purpose I O GPIO 00 cece cece eee een Imre 81 4 MVME2500 Installation and Use 6806800L01L Contents 4 2 12 Security Engine SEC 3 1 nE eel emn 81 4 2 13 Common On Chip Processor eee e cece cece ee ee eee eee ee
12. The VME P2 connector is a 160 pin DIN Row B of the P2 connector provides power to the MVME2500 board and to the upper eight VMEbus address lines and additional 16 VMEbus data lines The Z A C and D pin assignments for the P2 connector are same for both the MVME2500 and the MVME7216E MVME721E and are as follows Table 3 7 VMEbus P2 Connector PMCIO 2 5V PMCIO 1 Serial 1 RX 2 PMCIO 4 GND PMCIO 3 3 PMCIO 6 RETRY PMCIO5 Serial 1 TX 4 PMCIO 8 ADDRESS 24 PMCIO7 8 9 PMCIO10 ADDRESS25 PMCIO9 _1 Serial 1 CTS PMCIO12 ADDRESS26 PMCIO 11 o oO PMCIO 14 ADDRESS 27 PMCIO 13 B Serial 1 RTS PMCIO 16 ADDRESS28 PMCIO 15 GND PMCIO 18 ADDRESS 29 PMCIO 17 Serial 2 RX 10 PMC IO 20 ADDRESS 30 PMCIO 19 11 PMCIO22 ADDRESS 31 21 3 Serial 2 TX PMC IO 26 PMC IO 25 12 DATA Serial 2 CTS 14 PMC IO 28 DATA 16 PMC IO 27 12C CLK GND 15 PMC IO 30 DATA 17 PMC IO 29 GE3_LINK_LED Serial 2 RTS PMC IO 32 DATA 18 PMC IO 31 GE3_ACT_LED GND PMCIO34 DATA19 PMCIO33 GE4_LINK_LED Serial3 RX MVME2500 Installation and Use 6806800L01L Controls LEDs and Connectors Table 3 7 VMEbus P2 Connector continued Pin RowA Row B Row C Row D Row Z PMC 10 36 DATA 20 PMCIO35 GE4_A_LED PMCIO38 DATA21 PMCIO 37 Serial 3 TX PMCIO40 DATA22 PMCIO39 3 PMCIO 42 DATA 23 IO 41 Serial 3 CTS PMCIO 44 GND PMCIO 43 GND PMC IO 46 DATA 24 P
13. this port will automatically read as low due to AND connection between the two ports 111 Memory Maps and Registers 5 5 12 5 5 13 112 PLD Test Register 1 The MVME2500 PLD provides an 8 bit general purpose read write register which is used by the software for PLD testing or general status bit storage Table 5 15 PLD Test Register 1 REG PLD Test Register 1 OXFFDF0080 Field TEST REC OPER R W RESET 00 Field Description TEST_REG1 General purpose 8 bit R W field PLD Test Register 2 The MVME2500 PLD provides an 8 bit general purpose read write register which is used by the software for PLD testing or general status bit storage Table 5 16 PLD Test Register 2 p I 5 pp Field Description TEST_REG2 General purpose 8 bit R W field MVME2500 Installation and Use 6806800L01L Memory Maps and Registers 5 5 14 PLD GPIO2 Interrupt Register The Abort switch Tick Timer 0 1 and 2 interrupts are ORed together The MVME2500 provides an interrupt register that the system software reads to determine which device the interrupt originated from GPIO2 will be driven low if any of the interrupts asserts Table 5 17 PLD GPIO2 Interrupt Register PLD Write Protect I2C OxFFDF0095 RSVD RSVD RSVD RSVD PME TICKO INT TICK1 INT TICK2 INT OPER ee i Field Description NMI Abort switch interrupt if pressed less than three seconds 1 I
14. 2 7 Completing the Installation 0 cece cece cee seem 48 3 Controls LEDs and Connectors ne ak 49 3 1 Board Layout nn hen 49 3 2 50 EMEN CAES prd 51 3 3 LEDS dieser UE Er 2a A RM E er r IR PU EV 51 3 3 1 FrontPanelLEDs cierre tr the kim en n a De RR on omo UR nee 51 MVME2500 Installation and Use 68068001011 3 Contents 3 3 2 On board LEDS nn aa ERR weeded ba 53 3 4 5 53 3 4 1 ed eve de babes 54 3 4 1 1 RJ45 with Integrated Magnetics 1 2 54 3 4 1 2 Front Panel Serial Port J4 55 3 4 1 3 USB Connector 5 00 ccc ce ccc cece erent een nenn 56 3 4 1 4 VMEBus P1 Connector eee eee 56 3 4 1 5 VMEBus P2 Connector ee ERR ER 58 3 4 2 On board Connectors cece cee eee ehe mere 59 3 4 2 1 Flash Program 7 59 3 4 2 2 SATA Connector 3 eee 60 3 4 2 3 PMCCOhRTnecEOIS cocco RR rr ea 61 3 4 2 4 JTAG Connector P6 cece cece eee eee e 66 3 4 2 5 COPConnector P50 ccc cece iti eee NE ep 68 3 4 2 6
15. SMT Surface Mounted Technology UART Universal Asynchronous Receiver Transmitter VITA VMEbus International Trade Association VME Versa Module Eurocard XMC PCI Express Mezzanine Card Conventions The following table describes the conventions used throughout this manual Notation Description 0x00000000 Typical notation for hexadecimal numbers digits are 0 through F for example used for addresses and offsets 0b0000 Same for binary numbers digits are 0 and 1 bold Used to emphasize a word Screen Used for on screen output and code related elements or commands in body text Courier Bold Used to characterize user input and to separate it from system output Reference Used for references and for table and figure descriptions File gt Exit Notation for selecting a submenu lt text gt Notation for variables and keys text Notation for software buttons to click on the screen and parameter description Repeated item for example node 1 node 2 node 12 Omission of information from example command that is not necessary at the time being MVME2500 Installation and Use 68068001011 15 About this Manual 16 Notation A QOCCIOODXOOOCOCOOO COODOCOCOOCOOOO0O000O00000000000 0 XOOOOOOOOOOOD0OOQOO ODODOODOOOOO OO OR IR Description Ranges for example 0 4 means one of the integers 0 1
16. The JTAG Connector can be used in conjunction with the JTAG board and ASSET hardware Table 3 14 JTAG Connector P6 Pin Signal Description Pin Signal Description 66 MVME2500 Installation and Use 68068001011 Controls LEDs and Connectors Table 3 14 JTAG Connector P6 continued Pin Signal Description Pin Signal Description 9 SPI MISO GND 11 SPI VCC SCAN 1 TCK 13 SCAN 1 TDI GND 15 SCAN 1 TRST SCAN 1 TDO 21 SCAN 2 TMS 23 NC SCAN 2 TDO 25 SCAN 2 TCK 3 3V FROM 5V 27 GND 28 SCAN 2 TDI m p 33 SCAN 3 TDO SCAN 3 TCK 2 35 2 5V SCAN 3 TCK 3 37 SCAN 3 TDI GND 39 SCAN 3 TRST SCAN 3 TCK3 45 SCAN 4 TCK 2 3 3V 47 GND SCAN 4 TDI 49 SCAN 4 TCK 3 SCAN 4 TRST 51 SCAN 5 TMS SCAN 5 MVME2500 Installation and Use 6806800L01L 67 Controls LEDs and Connectors 3 4 2 5 68 Table 3 14 JTAG Connector P6 continued Pin Signal Description Pin Signal Description mem COP Connector P50 The COP header is used for the CPU debug The pin assignment is dictated by Freescale and is compatible with the processor s debugging tool Table 3 15 COP Header P50 Pin Signal Description JTAG TDI COP QACK JTAG TDO COP TRST COP RUNSTOP Pulled UP COP VDD SENSE JTAG TCK COP CHECK STOP IN JTAG TMS P2020 SW RESET COP PRESENT 13 COP HARD RESET KEYING
17. 14 COP CHECK STOP OUT MVME2500 Installation and Use 6806800L01L Controls LEDs and Connectors 3 4 2 6 SD Connector 2 Table 3 16 SD Connector 2 Pin Signal Description DATA 3 COMMAND GND VCC 3 3V WRITE PROTECT 11 CARD DETECT 12 GND 3 4 2 7 Connector 2 The MVME2500 has one XMC connector XJ2 that supports XMC cards with J15 connector It can also support cards with 16 connector without encountering any mechanical interference Table 3 17 Connector 2 Pinout Pin RowA Row B Row C Row D Row Row F RX1 RX1 3 3V GND GND HRESET NC NC 3 3V 4 GND GND JTAG TCK GND GND MRSTO PULLED UP MVME2500 Installation and Use 68068001011 69 Controls LEDs and Connectors Table 3 17 Connector 2 Pinout continued Row D Row Row F NC NC 3 3V GND GND 12V NC 3 3V JTAG TMS GND GND 12V NC 3 3V GND GND BIST TX1 TX1 3 3V PULLED UP GND GND PRESENT 3 3V GND GND I2C DATA NC NC 3 3V MVMRO GND GND I2C CLOCK PULLED DOWN NC NC NC NC NC GND GND NC NC NC ROOTO NC PULLED UP 3 4 2 8 Miscellaneous P2020 Debug Connectors Table 3 18 P20x0 Debug Header Signal Description Pee 70 MVME2500 Installation and Use 68068001011 Controls LEDs and Connectors 3 5 3 5 1 Table 3 18 P
18. 2 Reset Configuration The MVME2500 supports the power on reset POR pin sampling method for processor reset configuration Each option and the corresponding default setting are described in the following table Table 7 1 POR Configuration Settings CONFIG CCB Config CONFIG PINS LA 29 31 CONFIG SELECTION 41 CCB CLOCK 400 MHz REMARKS DDR PLL Config TSEC_1588_CLK_O UT TSEC_1588_PULSE_ OUT1 TSEC_1588_PULSE_ OUT2 8 1 DDR PLL 800 MHz DDR rate is twice the value of the DDR controller frequency which is then divided by two through the software Core 0 PLL LBCTL LALE LGPL2 LOE LFRE 3 1 CORE CLOCK PLL 1200 MHz 2 1 CORE CLOCK PLL 800 MHz For 1200 MHz board configuration For 800 MHz board configuration Core 1 PLL 5 CPU Boot Config LWEO UART_SOUT1 LA27 LA16 3 1 CORE CLOCK PLL 1200 MHz For 1200 MHz board configuration 2 1 CORECLOCK PLL 800 MHz e500 core O is allowed to boot without waiting for configuration by an external master while e500 core 1 is prevented from booting until configured by an external master or the other core For 800 MHz board configuration MVME2500 Installation and Use 68068001011 131 Programming Model Table 7 1 POR Configuration Settings continued CONFIG Boot Sequence Memory Debug Config DDR Debug Config CONFIG PINS LGPL3 LFWP LGPL5 DMA2_DACKO DMA2_DDONEO
19. 2 3 and 4 used in registers Logical OR Indicates a hazardous situation which if not avoided could result in death or serious injury A JOO 9 6 6 2 OOOO 2 8 2 9 2 8 9 2 8 6 9 2 2 5 2 2 6 8 2 2 8 3 2 0 6 97 Indicates a hazardous situation which if not avoided may result in minor or moderate injury XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX i 30000000000000000000000000000000000000000000000000 30O000000000000000000000000000000000000000000000000 Indicates a property damage message No danger encountered Pay attention to important information MVME2500 Installation and Use 68068001011 About this Manual Summary of Changes This manual has been revised and replaces all prior editions 6806800L01B October 2010 This version includes updates and revisions for the EA release of the MVME2500 Table 1 3 Added mechanical data Table 4 3 Removed the following commands brd_reset irqinfo mac Added soft_reset Table 4 1 Removed L2 SRAM L1 for stack and Boot Page entries Changed all instances of via to through Implem
20. B crisis image Power on the board Press h key on the keyboard to go to the U Boot prompt Type moninit fru to copy the crisis image to SPI Device A Once the U Boot prompt is visible power off the board Set the 52 2 back to OFF to point to the SPI Device A on aM PF WN Power on the board to boot from the newly recovered image on the SPI Device A The board will automatically switch over if one of the devices is corrupted Front UART Control The MVME2500 utilizes one of the two UART functions provided in the male micro mini DB 9 front panel A male to male micro mini DB 9 to DB9 adapter cable is available under Artesyn Part Number SERIAL MINI D 30 W2400E01A and is approximately 12 inches in length MVME2500 Installation and Use 68068001011 87 Functional Description 4 8 4 9 88 Only 115200 bps and 9600 bps are supported The default baud rate on the front panel serial is 9600 kbps Rear UART Control The MVME2500 utilizes the Exar ST16C554 quad UART QUART to provide four additional ports to the RTM These devices feature 16 bytes of transmit and receive first in first out FIFO with selectable receive FIFO trigger levels and data rates of up to 1 5 Mbps Each UART has a set of registers that provide the user with operating status and control The QUART are 8 bit devices connected to the processor through the local bus controller using LBC chipset CS1 CS2 CS3 and CS4 These four serial interfaces are
21. Flash Block A Signal Name BOOT_BLOCK_A Description Boot Block B Select ON Flash Block B OFF Flash Block A Notes The MVME2500 supports dual boot User can select either Flash Aor Flash B to boot the board If the selected flash is corrupted the board will automatically switch over to the next flash If both flash banks are corrupted the board should be sent for repair OFF WP Disabled FLASH_WP_N SPI Flash Write Protect ON WP Enabled OFF WP Disabled Hardware via 52 3 write protects the flash To disable the write protect 52 3 should be OFF You need to set the U Boot configuration to successfully write on the flash For details see Programming Model 4 OFF PMC PMC_XMC_SEL XMC or PMC selection Will select if XMC card or switch PMC card is used ON XMC OFF PMC 5 OFF 133 MHz PMC_133 PCI frequency selection This option can only be used ON 100 MHz if the PMC supports PCI X interface The board will OFF 133 Mhz automatically detect the frequency of operation of the PMC and will execute accordingly If the PMC supports PCI X speed this switch can be configured to run either 100 MHz or 133 MHz frequency 74 MVME2500 Installation and Use 68068001011 Controls LEDs and Connectors Table 3 20 Geographical Address Switch Settings continued sw2 DEFAULT OFF WP Enabled Signal Name MASTER_WP_DISA BLED Description Write Protect Disable switch ON WP
22. IO interfaces default PCI E 1 x1 2 5 Gbps SerDes lane 0 PCI E 2 x1 2 5 Gbps SerDes lane 2 PCI E 3 x2 2 5 Gbps SerDes lane 2 3 DDR31 5 V CKE low at reset default Disable PLL lock time out counter The power on reset sequence waits indefinitely for the SerDes PLL to lock default SYSCLOCK is above 66 MHz SDHC Card Detect Polarity TSEC2_TXD_5 Not Inverted RAPID System Size 134 Default RapidlO is not used MVME2500 Installation and Use 68068001011 7 3 Interrupt Controller Programming Model The MVME2500 uses the MPC8548E integrated programmable interrupt controller PIC to manage locally generated interrupts Currently defined external interrupting devices and interrupt assignments along with corresponding edge levels and polarities are shown in the following table Table 7 2 MVME2500 Interrupt List Interrupt Usage Interrupt Line Schematic Interface to CPU QUART IRQ1 Description Reserved for VME interrupt RTB Quart Interrupt QUART IRQ2 RTB Quart Interrupt QUART IRQ3 RTB Quart Interrupt Temperature Interrupt Ethernet 1 Management I2C Two on board Thermal Sensors one is for CPU temp and the other is for board temp Ethernet interrupt is handled by PHY Connected for flexibility Ethernet 3 Management I2C IRQ7 Management I2C IRQS GPIO1 RTC Real Time an Ethernet interrupt is handled
23. MVME2500 and is attached using an external cable It is used to update the boot loader in the field Using this method programming is done through the JTAG interface or by using the dedicated SPI Flash programming header on the JTAG board MVME2500 Installation and Use 68068001011 Functional Description Factory Pre Programming the SPI Flash usually takes a while Ideally the SPI Flash should be pre programmed in the factory before shipment ICT Programming This programming is done on exposed test points using a bed of nails tester 1y Theboard power should be switched on before programming The switch 52 8 should also be NN powered on to successfully detect the SPI Flash chip 4 6 3 Firmware Redundancy The MVME2500 uses two physically separate boot devices to provide boot firmware redundancy Although the P20x0 provides four SPI Bus chip selects the P20x0 is only capable of booting from the SPI Device controlled by Chip Select 0 External SPI multiplexing logic is implemented on the MVME2500 to accommodate this chipset limitation MVME2500 Installation and Use 6806800L01L 85 Functional Description 86 The MVME2500 FPGA controls the chip select to SPI devices A and B The FPGA chip select control is based on the Switch Bank 52 2 Figure 4 2 Device Multiplexing Logic Switch 2 2 OFF SELA P20x0 SPI_SELO SPI SEL1 SPI BUS At power up the selection of the SPI boot device is strictly based upon
24. Preparation and Installation __ 2 1 Overview This chapter provides unpacking instructions hardware preparation installation procedures of the board Installation instructions for the optional PMC XMC modules and transitions modules are also included A fully implemented MVME2500 consists of the base board and the following modules PCI Mezzanine Card PMC or PCI E Mezzanine Card XMC for added versatility Rear transition module SATA kit The following are the steps to be performed before using the board Be sure to read the entire chapter including all caution and warning notes before you begin 1 2 Bow Unpack the hardware Refer to Unpacking and Inspecting the Board on page 38 Configure the hardware by setting jumpers on the board and the RTM Refer to Configuring the Board on page 42 Install the rear transition module in the chassis Refer to Rear Transition Module on page 43 Install PMC module if required Refer to PMC XMC Support page 45 Install XMC span module if required Refer to Support on page 45 Install the board in the chassis Refer to Installing and Removing the Board on page 46 Attach cables and apply power Refer to Completing the Installation on page 48 MVME2500 Installation and Use 68068001011 37 Hardware Preparation and Installation 2 2 38 Unpacking and Inspecting the Board Read all notices and cautions prior to unpacking the produc
25. Produkt zerst ren kann e Kennzeichnen Sie deshalb TPE Anschl sse in der N he Ihres Arbeitsplatzes deutlich als Netzwerkanschl sse e Stellen Sie sicher dass die L nge eines mit Ihrem Produkt verbundenen TPE Kabels 100 m nicht berschreitet e Das Produkt darf ber die TPE Stecker nur mit einem Sicherheits Kleinspannungs Stromkreis SELV verbunden werden Bei Fragen wenden Sie sich an Ihren Systemverwalter Besch digung des Blades Ein unsachgem er Einbau der Batterie kann gef hrliche Explosionen und Besch digungen des Blades zur Folge haben Verwenden Sie deshalb nur den Batterietyp der auch bereits eingesetzt wurde und befolgen Sie die Installationsanleitung Datenverlust Wenn Sie die Batterie austauschen k nnen die Zeiteinstellungen verloren gehen Eine Backupversorgung verhindert den Datenverlust w hrend des Austauschs Wenn Sie die Batterie schnell austauschen bleiben die Zeiteinstellungen m glicherweise erhalten MVME2500 Installation and Use 68068001011 Sicherheitshinweise Datenverlust Wenn die Batterie wenig oder unzureichend mit Spannung versorgt wird wird der RTC initialisiert Tauschen Sie die Batterie aus bevor sieben Jahre tats chlicher Nutzung vergangen sind Sch den an der Platine oder dem Batteriehalter Wenn Sie die Batterie mit einem Schraubendreher entfernen k nnen die Platine oder der Batteriehalter besch digt werden Um Sch den zu vermeiden sollten Sie keinen Schraubend
26. by PHY Connected for flexibility Ethernet interrupt is handled by PHY Connected for flexibility IRQ9 GPIO2 FPGA Interrupt NMI and 3 Tick Timer Interrupts IRQ10 FPGA Interrupt IRQ11 GPIO4 QUART IRQO MVME2500 Installation and Use 68068001011 Power Interruption RTB Quart Interrupt 135 Programming Model 7 4 12C Bus Device Addressing The following table contains the I2C devices used for the MVME2500 and its assigned device address Table 7 3 I2C Bus Device Addressing SPD 256x8 ADT 7461 Temperature Sensor N A DS 1375 real time clock N A VPD 8192x8 1 0x55 RTM EEPROM 8192X8 1 2 0x56 XMC EEPROM N A 3 1 Thisis a dual address serial EEPROM 2 TheRTM Bus address can be manually changed through the S1 Switch on RTM The default switch configuration will set the address to 0x55 Make sure that the address is unique to the RTM Bus address when setting the switch 3 The address of the EEPROM is configured through Geographic Address resistor on board 7 5 Ethernet PHY Address The assigned Ethernet PHY on the management bus is shown in the following table Table 7 4 PHY Types and Management Bus Address PHY MIIM Ethernet Port Function Location PHY Types Address TSEC1 Gigabit Ethernet port routed to front panel BCM54616 136 MVME2500 Installation and Use 6806800L01L Programming Model 7 6 7 6 1 7 6 2 Ta
27. disabled OFF WP enabled Notes For I2C write protect only Switching will disable the write protect OFF Front OFF CPU Reset Deasserted GBE_MUX_SEL CPU Reset MVME2500 Installation and Use 6806800L01L User Defined switch that will select if the GBE PHY will function on the front panel or on the backplane ON RTM Genet OFF Front Panel Two GbE ports cannot be used at the same time The front panel GENET 2 and RTM GENET 2 shares same controller and PHY When the S2 7 can be set to select the Ethernet will be routed either to the front panel or to the RTM Should be OFF for normal operation 75 Controls LEDs and Connectors eee 76 MVME2500 Installation and Use 68068001011 Chapter 4 Functional Description EN 4 1 Block Diagram The MVME2500 block diagram is illustrated in Figure 4 1 All variants provide front panel access to one serial port via a micro mini DB 9 connector two 10 100 1000 Ethernet port one is configurable to be routed to the front panel or to the rear panel through ganged RJ45 connector and one Type A USB port It includes board fail LED indicator user defined LED indicator and an ABORT RESET switch Figure 4 1 Block Diagram GbE 5 cst XMCIPMC 1 RJ45 m 8 000 TE 10 00 1000 Base T gl 1 GhE t lt 168 268 b 4 i DDR3 SDRAM EEPROM LILILILI RS 232 BCN5482 XCVR PHY UART SA
28. ehh 91 4 15 Power Management b RP EGG Y ERE WV bbb sade an 91 4 15 1 On board Voltage Supply Requirement e eee e eee eee 92 4 15 2 Power Up Sequencing Requirements eee cece e ee eee eene 92 4 16 Clock Sbr ctle eee anes 94 417 m Ses Ue eae ne 94 4 17 1 RES CESCQUENCE Eda EEA LEN EE pee E X ELSES Re eae 95 4 18 Thermal Management messe 97 4 19 Real Time Clock Battery cc cece ccc III Hem 97 4 20 Debugging Support ccc ec cee TE EE E 97 4 20 1 POST Code Indicator 98 MVME2500 Installation and Use 6806800L01L 5 Contents 4 20 2 JTAG Chain and Board cece ete ee nee II nee 98 4 20 3 Custom Debugging he 99 4 21 Rear Transition Module sen 99 5 Memory Maps and Registers 101 51 OVEIVIEW e 8 ee ERE le 101 5 2 Memory uns etes ble ea teer ege ea METRE e E et 101 5 3 Flash Map nenne ee EAR penes 102 5 4 Linux Devices Memory eee nee eee hh 102 5 5 Programmable Logic Device PLD Registers 104 5 3 1 PLDiRevision Register russ en ee kobe wie mn do 104 5 5 2 gt PEDYearRegister u ne MiG E UD 104 5 5 3 PLD Month cec
29. local Artesyn sales representative for the availability of alternative officially approved battery models Data Loss Exchanging the battery can result in loss of time settings Backup power prevents the loss of data during exchange Quickly replacing the battery may save time settings Data Loss If the battery has low or insufficient power the RTC is initialized Exchange the battery before seven years of actual battery use have elapsed PCB and Battery Holder Damage Removing the battery with a screw driver may damage the PCB or the battery holder To prevent damage do not use a screw driver to remove the battery from its holder MVME2500 Installation and Use 6806800L01L Sicherheitshinweise EN Dieses Kapitel enth lt Hinweise die potentiell gef hrlichen Prozeduren innerhalb dieses Handbuchs vorrangestellt sind Beachten Sie unbedingt in allen Phasen des Betriebs der Wartung und der Reparatur des Systems die Anweisungen die diesen Hinweisen enthalten sind Sie sollten au erdem alle anderen Vorsichtsma nahmen treffen die f r den Betrieb des Produktes innerhalb Ihrer Betriebsumgebung notwendig sind Wenn Sie diese Vorsichtsma nahmen oder Sicherheitshinweise die an anderer Stelle diese Handbuchs enthalten sind nicht beachten kann das Verletzungen oder Sch den am Produkt zur Folge haben Artesyn Embedded Technologies ist darauf bedacht alle notwendigen Informationen zum Einbau und zum Umgang mit dem Produkt in diesem Handb
30. routed to P2 I O for RTM accessibility There are a total of five serial ports available on the MVME2500 Sites The MVME2500 hosts only one PMC XMC site and accepts either a PMC or an XMC add on card Only an XMC or a PMC may be populated at any given time as both occupy the same physical space on the PCB Combination PMC XM cards are not supported by the MVME2500 The site provides a rear PMC I O The PMC site is fully compliant with the following 1 VITA 39 PCI X for PMC VITA 35 2000 for PMC P4 to VME P2 Connection PCI Rev 2 2 for PCI Local Bus Specification PCI X PT 2 0 for PCI X Protocol Addendum to the PCI Local Bus Specs IEEE Standard P1386 2001 for Standard for Common Mezzanine Card Family IEEE Standard P1386 1 2001 for Standard Physical and Environmental Layer for Mezzanine Card VITA 42 for XMC 8 VITA 42 3 PCle for XMC Ur A Wi T MVME2500 Installation and Use 6806800L01L Functional Description 4 9 1 4 9 2 PMC XMC sites are keyed for 3 3V PMC signaling The PMC and the add on cards must have a hole in the 3 3 V PMC keying position in order to be populated on the MVME2500 The XMC specification accommodates this since it is expected that carrier cards will host both XMC and PMC capable add on cards The MVME2500 have a keying pin at the 3 3V location at the PMC site The MVME2500 boards are not 5 volt IO compatible The MVME2500 also has 5 volt keying pin loca
31. the Switch Bank 52 2 setting Depending on the S2 2 setting SPI_SELO is routed to one of two SPI devices The selected SPI device must contain a boot image Once the boot image is copied into memory and executed the FPGA will wait and once the P20x0 will write on one bit of the FPGA watchdog register the FPGA will then pass through the SPI chip select from the P20x0 to SPI device chip selects The software can now perform read write processes on any SPI device including copying from one SPI device to another With this flexible approach to firmware redundancy one should always be ableto recoverfrom a corrupt active firmware image as long as a healthy firmware image is maintained in single bootable SPI Device MVME2500 Installation and Use 68068001011 Functional Description 4 6 4 4 7 The MVME2500 supports automatic switch over If booting one device is not successful the watchdog will trigger the board reset and it will automatically boot on the other device Crisis Recovery The MVME2500 provides an independent boot firmware recovery mechanism for the operating system The firmware recovery can be performed without leaving the firmware environment During crisis recovery the healthy boot image contained in SPI Device B is copied to SPI Device A replacing the corrupt boot image contained in SPI Device A Crisis recovery is performed as follows 1 Power off the board Set Switch S2 2 to ON to point to SPI Device
32. the result of eval expression SPI flash sub system Print local hushshell variables sleep Delay execution for some time soft_reset Soft reset the board source Run script from memory test Minimal test like bin sh Boot image through network using TFTP protocol Initialize and configure Tundra Tsi148 usb USB sub system usbboot Boot from USB device version Print monitor version Updating U Boot To update the U Boot place the image in the RAM address 0x1000000 in this example before copying it to the SPI flash The following procedure will replace the image in SPI bank 0 1 Disable SPI write protect in FPGA register Chapter 5 PLD Write Protect and 12 Debug Register 2 Ensure FLASH_WP_N in SMT Configuration Switch S2 is in the OFF position MVME2500 Installation and Use 68068001011 Boot System eee 3 Select SPI flash 0 sf probe 0 4 Erase 0x90000 bytes starting at SPI address 0 sf erase 0 0x90000 5 Write 0x90000 bytes from RAM address 0x1000000 starting at SPI address 0 sf write 0x1000000 0 0x90000 To replace the image in SPI bank 1 replace step 2 with Select SPI flash 1 sf probe 1 MVME2500 Installation and Use 68068001011 129 Boot System _ _ _ 130 MVME2500 Installation and Use 68068001011 Programming Model __ 7 1 Overview Chapter 7 This chapter includes additional programming information for the MVME2500 7
33. 00 Installation and Use 68068001011 117 Memory Maps and Registers 5 6 2 Control Registers Table 5 23 Control Registers Tick Timer 0 Control Register OxFFC80202 Tick Timer 1 Control Register OxFFC80302 REG Tick Timer 2 Control Register OxFFC80402 15 R W 0x0000 Field Description ENC Enable counter When the bit is set the counter increments When the bit is cleared the counter does not increment COC Clear Counter on Compare When the bit is set the counter is reset to 0 when it compares with the compare register When the bit is cleared the counter is not reset COVF Clear Overflow Bits The overflow counter is cleared when 1 is written to this bit OVF Overflow Bits are the output of the overflow counter It increments each time the tick timer sends an interrupt to the local bus interrupter The overflow counter is cleared by writing a 1 to the COVF bit ENINT Enable Interrupt When the bit is set the interrupt is enabled When the bit is cleared the interrupt is not enabled CINT Clear Interrupt INTS Interrupt Status RSVD Reserved for future implementation 118 MVME2500 Installation and Use 6806800L01L Memory Maps and Registers 5 6 3 Compare High and Low Word Registers The tick timer counter is compared to the Compare Register When the values are equal the tick timer interrupt is asserted and the overflow counter increments If the clear on compare mode is enable the count
34. 021CC MVME2500ET 0161 MVME2500ET 0163 MVME2500ET 0171 MVME2500ET 0173 has been designed and manufactured to the following specifications EN55022 2006 Class A EN55024 A1 2001 A2 2003 1998 2011 65 EU RoHS Directive As manufacturer we hereby declare that the product named above has been designed to comply with the rele vant sections of the above referenced specifications This product complies with the essential health and safety requirements of the above specified directives We have an internal production control system that ensures compliance between the manufactured products and the technical documentation 2 08 Tom Tuttle Manager Product Testing Services Date MM DD YYYY RTESYN SU 5 386 03 11 2014 32 MVME2500 Installation and Use 68068001011 Introduction 1 3 Mechanical Data The following table provides the dimensions and the weight of the board Table 1 2 Mechanical Data Feature Height Value 233 44 mm 9 2 inches Depth 160 0 mm 6 3 inches Front Panel Height Max Component Height Weight 261 8 mm 10 3 inches 14 8 mm 0 58 inches 400 grams standard variant 700 grams ET variants 1 4 Ordering Information As of the printing date of this manual this guide supports the models listed below Table 1 3 Available Board Variants Order Number MVME2500 0163 Processor QorlQ P2010 Ejector single c
35. 1L Memory Maps and Registers 5 5 3 5 5 4 PLD Month Register The MVME2500 PLD provides an 8 bit register which contains the build month of the timers registers PLD Table 5 6 PLD Month Register REG PLD Year Register OxFFDFO005 PLD Day Register MVME2500 PLD provides an 8 bit register which contains the build day of the timers registers PLD Table 5 7 PLD Day Register REG PLD Revision Register OXFFDF0006 PLD Sequence Register The MVME2500 PLD provides an 8 bit register which contains the sequence of the PLD which is in synchrony with the PCB version Table 5 8 PLD Sequence Register PLD Revision Register OxFFDF0007 pr ow quecqes qe am Ou MVME2500 Installation and Use 68068001011 105 Memory Maps and Registers Table 5 8 PLD Sequence Register REG PLD Revision Register OxFFDF0007 5 5 6 PLD Power Good Monitor Register The MVME2500 PLD provides an 8 bit register which indicates the instantaneous status of the supply s power good signals Table 5 9 PLD Power Good Monitor Register Field Description PWR_V1PO5_PWRGD 1 05V Core supply power good indicator PWR_V1P2_PWRGD 1 2V Supply power good indicator PWR_V1P8_PWRGD 1 8V Supply power good indicator 106 MVME2500 Installation and Use 6806800L01L Memory Maps and Registers 5 5 7 PWR_V3P3_PWRGD 3 3V Supply power good indicator PWR_V2P5_PWRGD 2 5V Supply powe
36. 2 V 12 V are defined by the base XMC standard MVME2500 Installation and Use 68068001011 89 Functional Description 4 10 4 11 4 11 1 4 12 90 SATA Interface The MVME2500 supports an optional 2 5 SATA HDD The connector interface is compatible with the SATAMNKIT which contains the following one SSD HDD one SATA board screws and a mounting guide The SATA connector can support a horizontal mounted SSD HDD The MVME2500 uses Marvell s 88SE6121B2 NAA2C000 SATA controller and supports up to 1 5 Gbps SATA Gen 1 For status indicators it has an on board green LED D12 and D13 for SATA link and SATA activity status respectively VME Support The MVME2500 can operate in either System Controller SCON mode or non SCON mode as determined by the switch setting of 51 1 and 51 2 The 20 0 x1 link is used for the VME backplane connectivity through the Tsi384 PCI E PCI X and 751148 PCI X VMEBus bridges See VMEBus 1 Connector on page 56 and VMEBus 2 Connector on page 58 for more information Tsi148 VME Controller The VMEbus interface for the MVME2500 is provided by the Tsi148 VMEbus controller The Tsi148 provides the required VME VME extensions and 2eSST functions SN74VMEH22501 transceivers are used to buffer the VME signals between the Tsi148 and the VME backplane Refer to the Tsi148 user s manual for additional details and or programming information USB The MVME2500 processor implements a d
37. 2005 General Purpose I O Standard VITA 42 10 XMC PCI Express Protocol Layer Standard VITA 42 3 2006 MVME2500 Installation and Use 68068001011 Related Documentation Table B 3 Related Specifications continued Organization IEEE Peripheral Component Interconnect Special Interest Group PCI SIG Serial ATA International Organization SATA IO Document IEEE 802 3 LAN MAN CSMA CD Access Method IEEE 802 3 2005 IEEE Standard for a Common Mezzanine Card CMC Family IEEE Std 1386 2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC IEEE Std 1386 1 2001 IEEE Standard Test Access Port and Boundary Scan Architecture IEEE Std 1149 1 2001 Low Pin Count Interface Specification LPC Revision 1 1 PCI Express Base Specification Revision 2 0 PCI Local Bus Specification PCI Rev 3 0 PCI X Electrical and Mechanical Addendum to the PCI Local Bus Specification PCI X EM Revision 2 0a PCI X Protocol Addendum to the PCI Local Bus Specification PCI X PT Revision 2 0a Serial ATA SATA Specification Revision 2 6 Serial ATA Extensions to Serial 1 0 Revision 1 0 Trusted Computing Group TCG USB Implementers Forum USB IF TPM Specification 1 2 Level 2 Revision 103 Version 1 2 Universal Serial Bus Specification USB Revision 2 0 MVME2500 Installation and Use 68068001011 149 Related Documentation EN 85 n
38. 20x0 Debug Header continued Pin Signal Description 3 MSRCDI1 4 MDVAL 5 MSRCDI2 TRIG_OUT MSRCDI3 TRIG_IN MSRCID4 Switches These switches control the configuration of the MVME2500 NOTICE Board Malfunction Switches marked as reserved might carry production related functions and can cause the board to malfunction if their settings are changed Do not change settings of switches marked as reserved The setting of switches which are not marked as reserved has to be checked and changed before board installation Geographical Address Switch 51 The Tsi148 VMEbus Status Register provides the VMEbus geographical address of the MVM2500 The switch reflects the inverted states of the geographical address signals Applications not using the five row backplane can use the geographical address switch to assign a geographical address based on the following diagram MVME2500 Installation and Use 68068001011 71 Controls LEDs and Connectors 72 Note that this switch is wired in parallel with the geographical address pins on the 5 row connector These switches must be in the OFF position when installed in a 5 row chassis in order to get the correct address from the P1 connector This switch also includes the SCON control switches Figure 3 5 Geographical Address Switch i 1 ON oom Table dis table 2 See Table See Table 3 GAP 0 GAP 1 4 GA4 0 GA4 amp 1 5 GA3 0
39. 3 Boot System 6 3 4 Booting from an SD Card 1 Make sure thatthe kernel dtb and ramdisk are saved in the SD card with FAT partition 2 Configure the U Boot environment variable setenv File_ulmage lt kernel_image gt setenv File_dtb lt kernel dtb gt setenv File_ramdisk lt ramdisk gt saveenv 3 Initialize SD card mmcinfo 4 Load the files from the SD card to the memory option mmc interface 0 1 device 0 partition 1 fatload mmc 0 1 1000000 File_ulmage fatload mmc 0 1 2000000 File_ramdisk fatload mmc 0 1 c00000 File_dtb 5 Boot the Linux in memory bootm 1000000 2000000 c00000 6 3 5 Booting VxWorks Through the Network In this mode the U Boot downloads and boots VxWorks from an external TFTP server 1 Make sure that the VxWorks image is accessible by the board from the TFTP server 2 Configure U Boot environment variables setenv ipaddr lt IP address of MVME2500 gt setenv serverip lt IP address of TFTP server gt setenv gatewayip lt gateway IP gt setenv netmask lt netmask gt setenv vxboot tftpboot vxbootfile amp amp setenv bootargs Svxbootargs amp amp bootvx setenv vxbootfile lt VxWorks_image gt setenv vxbootargs motetsec 0 0 IP address of TFTP server gt VxWorks h lt IP address of TFTP server gt e lt IP address of MVME2500 gt ffffff00 b lt unused IP u vxworks pw vxworks f 0x80 saveenv 124 MVME2500 Installation and Use 6806800L01L Boot System 6 4 3 TF
40. 546165 FP_PHY_25MHZ_CLK 25Mhz 546165 SW_25MHZ_CLK 25Mhz ICS83905AGILF XMC CLK_XMC1 100MHz ICS9FG108 QorlQ P20x0 SD REF CLK 100MHz ICS9FG109 TSI384 CLK_PCIECI 100MHz ICS9FG110 TSI384 CLK PCIEC3 100MHz 88SE6121 CLK_88SE6121_PCIE_100MH 100MHz ICS9FG112 7 CLK_CPLD 1 8432MHz Oscillator USB CLK_USB_1_24MHZ 24MHz Oscillator QorlQ P20x0 CPU_RTC 1MHz FPGA CLK_PMC1 33 66 100 133M hz 751148 PCI 133Mhz ICS8405071 RTC CLK_32K 32 768KHz DS32KHz FPGA CPU_LCKO 25MHz QorlQ P20x0 QUART CLK_QUART 1 8432MHz FPGA ICS83905 CLK 25MHZ ICS9FG108 7 7 1 System Clock The system and DDR clock is driven by 1 58405071 device The following table defines the clock frequency Table 7 7 System Clock SYSCLK CORE CCB Clock Platform DDR3 LBC 140 MVME2500 Installation and Use 6806800L01L Programming Model 7 7 2 Real Time Clock Input The RTC clock input is driven by a 1 MHz clock generated by the FPGA This provides a fixed clock reference for the QorlQ P20x0 PIC timers which the software can use as a known time reference 7 7 3 Local Bus Controller Clock Divisor Thelocal bus controller LBC clock output is connected to the FPGA for LBC bus transaction It is also the source of 1 MHz CPU RTC and FPGA tick timers MVME2500 Installation and Use 68068001011 141 Programming Model m 142 MVME2500 Installation and Use 68068001011 Replacing the Battery E eS M A 1 Replacing the Battery The figure below sho
41. 6 MVME2500 Installation and Use 68068001011 Memory Maps and Registers Field Description Count Count These bits define the watchdog timer count value When the watchdog counter is enabled it will count up from zero reset value with a 1 ms resolution until it reaches the COUNT value set by this register Watchdog will generate a soft reset signal if it bites Setting this register to OXEA60 or 60 000 counts will provide a watchdog timeout of 60 seconds 5 6 External Timer Registers The MVME2500 provides a set of tick timer registers to access the three external timers implemented in the timers registers PLD These registers are 32 bit and are word writable The following sections describe the timer prescaler and control registers 5 6 1 Prescaler Register The prescaler adjust value is determined by this formula Prescaler Adjust 256 CLKIN CLKOUT CLKIN is the input clock source in MHz and CLKOUT is the desired output clock reference in MHz Table 5 22 Prescaler Register Prescaler T OxFFC80100 15 13 12 10 Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Prescaler Register 8 bits OPER RESET 0x00e7 The prescaler provides the clock required by each of the three times The tick timers require 1 MHz clock input The input clock to the prescaler is 25 MHz The default value is set for 0x00E7 which gives 1 MHz reference clock for a 25 MHz input clock source MVME25
42. Board products are tested in a representative system to show compliance with the above mentioned requirements A proper installation in a compliant system will maintain the required performance Use only shielded cables when connecting peripherals to assure that appropriate radio frequency emissions compliance is maintained Operation Product Damage High humidity and condensation on the board surface causes short circuits Do not operate the board outside the specified environmental limits Make sure the board is completely dry and there is no moisture on any surface before applying power Damage of Circuits Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life Before touching the board or electronic components make sure that you are working in an ESD safe environment Board Malfunction Switches marked as reserved might carry production related functions and can cause the board to malfunction if their setting is changed Do not change settings of switches marked as reserved The setting of switches which are not marked as reserved has to be checked and changed before board installation Installation Data Loss Powering down or removing a board before the operating system or other software running on the board has been properly shut down may cause corruption of data or file systems 20 MVME2500 Installation and Use 68068001011 Safety Notes Make sure all software is
43. C I O that goes to the RTM PMC The tables below show the pinout detail of J11 J12 J13 J14 See Figure 3 1 for the location of the PMC connectors Table 3 10 PMC J11 Connector Signal Description JTAG TCK FRAME 12V GND GND IRDY DEVSEL INTC 5V PRESENT SIGNAL PCIXCAP 5V LOCK NC NC PAR MVME2500 Installation and Use 6806800L01L 61 Controls LEDs and Connectors Table 3 10 11 Connector continued Pin Signal Description Pin Signal Description 15 GND 47 AD 12 48 AD 11 49 AD9 50 5V 51 GND 52 CBEO 53 AD6 54 AD5 55 AD 4 56 GND 57 3 3V 58 AD3 59 AD2 60 AD 1 61 ADO 30 5V 62 5V mos Table 3 11 PMC 12 Connector Signal Description GND TRST IDSELB JTAG TMS TRDY 62 MVME2500 Installation and Use 68068001011 Controls LEDs and Connectors Table 3 11 PMC 12 Connector continued Pin Signal Description Signal Description 3 3V GND STOP PERR GND 3 3V SERR BUSMODE2 Pulled CBE1 UP 3 3V GND PCI RESET AD 14 BUSMODE3 PULLED AD 13 DWN M66EN BUSMODE4 PULLED AD 10 DWN AD 8 GND 3 3V AD 7 REQB 3 3V GNTB NC GND NC EREADY GND RSTOUT MVME2500 Installation and Use 68068001011 63 Controls LEDs and Connectors Table 3 11 PMC 12 Connector continued Table 3 12 PMC J13 C
44. CONFIG SELECTION CFG_BOOT_SEQ 1 0 BOOT SEQUENCE DISABLED Debug information from the DDR SDRAM controller is driven on the MSPCID and MDVAL signs default Debug information is not driven on ECC pins ECC function in their normal mode default REMARKS ELBCECC Enable Config Platform Speed MSRCIDO Default operation eLBC ECC checking is disabled PLAT SPEED 1 CCB CLOCK gt 333 MHz CORE 0 Speed CFG COREO SPEED 1 C ORE FREQ gt 1000 MHz For 1200 MHz board configuration CORE 1 Speed CFG COREO SPEED 0 C ORE FREQ 1000 MHz CFG_CORE1_SPEED 1 C ORE FREQ gt 1000 MHz For 800 MHz board configuration For 1200 MHz board configuration CFG_CORE1_SPEED 0 C ORE FREQ lt 1000 MHz For 800 MHz board configuration DDR Controller Speed Engineering use LA 22 20 UART SOUT O TRIG OUT MSRCID 1 MSRCID 4 DMA1_DDONE_B 0 111111 11 CFG_DDR_SPEED 1 DDR FREQ gt 500 MHz Default for future use 17 SerDes Ref TSEC_1588_ALARM 1 SerDes expects a 100 Clock Config _OUT1 MHz reference clock frequency default 132 MVME2500 Installation and Use 6806800L01L Programming Model Table 7 1 POR Configuration Settings continued CONFIG ETSEC2 SGMII Mode CONFIG PINS CONFIG SELECTION eTSEC2 Ethernet interface operates in standard parallel interface mode and uses the TSEC_2 pins default REMARKS E
45. D SPEED USER 1 FAIL GENET 1 GENET 2 MVME2500 Installation and Use 68068001011 51 Controls LEDs and Connectors Table 3 1 Front Panel LEDs Label Function User Defined Location Front panel Color Off Yellow Red Description By default User Software Controllable Refer to the User LED Register User Software Controllable Refer to the User LED Register Board Fail Front panel Off Normal operation after successful firmware boot One or more on board power rails has failed and the board has to shutdown to protect the hardware Normal during power up during hardware reset such as a front panel reset May be asserted by the BDFAIL bit in the 751148 VSTAT register GENET1 TSEC1 Front panel No link SPEED Link Speed Integrated 1 0 1 OOBASE T operation 1000 BASE T operation GENET1 TSEC1 Front panel Off No activity ACT Activity Integrated Blinking Green Activity proportional to bandwidth RJ45 LED utilization GENET2 TSEC2 Front panel Off No link SPEED Link Speed Integrated Amber 10 100BASE T operation RJ45 LED s Green 1000BASE T operation GENET2 TSEC2 Front panel Off No activity ACT Activity Integrated Blinking Green Activity proportional to bandwidth RJ45 LED utilization 52 MVME2500 Installation and Use 68068001011 Controls LEDs and Connectors 3 3 2 On board LEDs The on board LEDs are listed below To v
46. D3 5A Port TRD2 6A Port ATRD2 7A Port ATRD1 8A Port ATRD1 9A Port A TRDO 10A Port A TRDO D1A Port A Green LED1 Anode Yellow LED1 Cathode D2A Port A Yellow LED1 Anode Green LED1 Cathode D3A Port A Green LED2 Anode Yellow LED2 Cathode D4A Port A Yellow LED2 Anode Green LED2 Cathode 1B GND 2B NC 3B Port B TRD3 4B Port BTRD3 5B Port B TRD2 54 MVME2500 Installation and Use 68068001011 Controls LEDs and Connectors Table 3 3 Front Panel Tri Speed Ethernet Connector J1 continued Pin Name Signal Description 6B Port B TRD2 7B Port B TRD1 8B Port B TRD1 9B Port B TRDO 10B Port B TRDO D1B Port B Green LED1Anode Yellow LED1 Cathode D2B Port B Yellow LED1 Anode Green LED1 Cathode D3B Port B Green LED2Anode Yellow LED2 Cathode D4B Port B Yellow LED2 Anode Green LED2 Cathode 3 4 1 2 Front Panel Serial Port There is one front access asynchronous serial port interface that is routed to the micro mini DB 9 front panel connector A male to male micro mini DB9 adapter cable is available under Artesyn part number SERIAL MINI D 30 W2400E01A and ACC CABLE SER DTE 6E 9 pin micro DSUB to 9 pin DSUB cross connected serial console cable The pin assignments for these connectors are as follows Table 3 4 Front Panel Serial Port 4 Signal Description MVME2500 Installation and Use 68068001011 55 Controls LEDs and Conne
47. ET 0171 Cooling Method Operating Temperature Storage Forced Air 7 CFM 0 C to 55 C 40 C to 85 C Forced Air 7 CFM 40 C to 71 C 50 C to 100 C Vibration Sine 10min axis 2G 5 to 2000 Hz 15 to 2000 Hz Vibration Random 1hr axis Shock 20g 11 mS to 95 RH non condensing Humidity 1 ft3 min 0 01g2 Hz 15 to 2000 Hz MVME2500 Installation and Use 6806800L01L 0 04g2 Hz 15 to 2000 Hz 8 GRMS 30g 11 mS to 100 RH non condensing 2 Flat 15 1000Hz 6db octave 1000Hz 2000Hz MIL STD 810F Figure 514 5C 17 39 Hardware Preparation and Installation NOTICE Product Damage High humidity and condensation on the board surface causes short circuits Do not operate the board outside the specified environmental limits Make sure the board is completely dry and there is no moisture on any surface before applying power 2 3 2 Power Requirements The board uses 5 0 V from the VMEbus backplane On board power supply generates required voltages for various ICs The MVME2500 connects the 12 V and 12 V supplies from the backplane to the PMC sites while the 3 3 V power supplied to the PMC sites comes from the 5 0 V backplane power A maximum of 10 A of 3 3 V power is available to the PMC sites however the 90 W 5 0 V limit must be observed as well as any cooling limitations 40 MVME2500 Installation and Use 6806800L01L Hardware Preparation and
48. Gbit device forms 2 GB and 1 GB memory capacity A total of 16 devices for 2 GB and eight devices are used to form 16 GB MVME2500 supports ENP1 and ENP2 operating environment The ENP1 environment uses Samsung for all variants including the commercial grade devices while the ENP2 variants use Micron Timers There are various timer functions implemented on the MVME2500 platform Real Time Clock This operates on 3 3 V supply monitoring and battery control function MAX6364PUT29 a 32 768 KHz clock generator DS32KHZS and an RTC with alarm DS1375T MVME2500 Installation and Use 6806800L01L 4 4 2 4 4 3 4 4 4 4 5 Functional Description See Real Time Clock Battery on page 97 for more information on the real time clock back up battery Internal Timer The processor s internal timer is composed of eight global timers divided into two groups of four timers each Each timer has four individual configuration registers and they cannot be cascaded together Watchdog Timer The on board FPGA provides programmable 16 bit watchdog timers It has a 1 ms resolution and generates a board reset when the counter expires Interrupt is generated to the processor when this occurs Default value is 60 seconds FPGA Tick Timer The MVME2500 supports three independent 32 bit timers that are implemented on the FPGA to provide fully programmable registers for the timers Ethernet Interfaces The MVME2500 has three eTSEC controlle
49. Ho I PAGE 83 OF 87 MVME2500 Installation and Use 68068001011 93 Functional Description 4 16 Clock Structure A total of three IDT chips a discrete oscillator and crystal supports all the clock requirements of MVME2500 Figure 4 4 Clock Distribution Diagram 25 MHz LVCMOS ICS9FG108 S GBE PHY ICS83905 PCIE SATA BR GBE SWITCH BP GBE PHY 25 MHz LVCMOS 125 MHz LVCMOS 100 MHz LVCMOS ICS840S071 100 MHz LVCMOS 133 MHz 151384 Bridge 51148 Bridge 1 8432 MHz OSG 18 FPGA 8 MHz 4 17 Reset Structure The MVME2500 reset will initiate after the power up sequence if the 1 5 V power supply is GOOD When the board is at ready state the reset logic will monitor the reset sources and implement the necessary reset function 94 MVME2500 Installation and Use 68068001011 Functional Description 4 17 1 Reset Sequence The timing of the reset sequence supports each chip reset requirements with respect to the power supply Allthe resets are controlled by the FPGA with a power supply of 3 3 V from 5 V All the resets are asserted until 1 5 V power is Good Initially peripherals resets are released to corresponding sequence then later the CPU reset is released Once the CPU reset is released the CPU starts boot up sequence Below is the SW event sequence from the release of CPU reset to boot up 1 Copying of U boot from SPI to CPU cache Ini
50. Installation The following table provides an estimate of the typical and maximum power required Table 2 2 Power Requirements Typical Maximum Measured Board Variant Calculated Operating MVME2500 0163 14 8 W MVME2500 0161 14 8 W MVME2500 0173 16 6 W MVME2500 0171 23 5W 16 6 W MVME2500ET 0173 23 5W 16 6 W MVME2500ET 0171 23 5W 16 6 W y The power is measured when the board is in standby Linux prompt mode Power will NN significantly increase when adding hard drives or card The following table shows the power available when the MVME2500 is installed in either a three row or five row chassis and when PMCs are present Chassis Type Available Power Three Row 70 W maximum Power With PMCs below 70 W below 90 W Five Row 90 W maximum M 1 Keep below power limit Cooling limitations must be considered MVME2500 Installation and Use 68068001011 41 Hardware Preparation and Installation 2 3 3 Equipment Requirements The following are recommended to complete a MVME2500 system VMEbus system enclosure System console terminal Operating system and or application software Transition module and connecting cables 2 4 Configuring the Board The board provides software control over most options Settings can be modified to fit the user s specifications To configure set the bits in the control register after installing the board
51. MC IO 45 Serial 3 RTS PMC IO 48 DATA 25 PMC IO 47 GND 25 pmcioso DATA26 PMCIO 49 Serial 4 RX 26 52 DATA27 51 GE4_1 PMCIO 54 DATA 28 PMC IO 53 Serial 4 TX PMC IO 56 DATA 29 PMC IO 55 GND PMC IO 58 DATA 30 PMC IO 57 Serial 4 CTS PMC IO 60 DATA 31 PMC IO 59 GND 31 pMcio62 GND PMCIO 61 GND Serial4RTS 3 4 2 On board Connectors 3 4 2 1 Flash Program Connector 7 The Flash Program Connector is depopulated in the production version of the MVME2500 However each pin is exposed for the 60 pin header connector for the JTAG boundary scan Table 3 8 Flash Programming Header P7 Signal Description 2 Chip Select 1 3 Chip Select 0 MVME2500 Installation and Use 68068001011 59 Controls LEDs and Connectors Table 3 8 Flash Programming Header P7 continued Pin Signal Description Programmer s VCC 5 Master In Slave OUT MISO HOLD 0 Keying CLOCK Master OUT Slave IN MOSI 3 4 2 2 SATA Connector The on board customized SATA connector is compatible with the SATA kit namely VME 64GBSSDKIT and IVME7210 MNTKIT Table 3 9 Custom SATA Connector J3 60 MVME2500 Installation and Use 6806800L01L Controls LEDs and Connectors Table 3 9 Custom SATA Connector 3 continued 3 4 2 3 PMC Connectors The MVME2500 supports only one PMC site It utilizes J14 to support PM
52. MVME2500 Installation and Use P N 6806800L01L April 2015 EIE SS Ss SS SSS ee Copyright 2015 Artesyn Embedded Technologies Inc All rights reserved Trademarks Artesyn Embedded Technologies Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc 2015 Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries Java and all other Java based marks are trademarks or registered trademarks of Oracle America Inc in the U S and other countries Microsoft Windows and Windows Me are registered trademarks of Microsoft Corporation and Windows XP is a trademark of Microsoft Corporation PICMG CompactPCI AdvancedTCA and the PICMG CompactPCI and AdvancedTCA logos are registered trademarks of the PCI Industrial Computer Manufacturers Group UNIX is a registered trademark of The Open Group in the United States and other countries Notice While reasonable efforts have been made to assure the accuracy of this document Artesyn assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Artesyn reserves the right to revise this document and to make changes from time to time in the content hereof without obli
53. Maps and Registers CPU_RESET CPU_HRESET_REQ_L Reset Reason 1 Reset is due to CPU_HRESET_REQ_L signal 0 None WD_TIMEOUT Watchdog Timeout Reset Reason 1 Reset is due to watchdog timing out 0 None LRSTO TSI LRSTO Reset Reason 1 Reset is due to LRSTO signal 0 None Sft RST Soft Reset Reset Reason 1 Reset is due to Soft RST register being set or the front panel switch being pressed more than three 0 None 5 5 16 PLD Watchdog Timer Refresh Register The MVME2500 provides a watchdog timer refresh register Table 5 19 PLD Watchdog Timer Refresh Register REG PLD Watch Dog Timer Load OXFFC80600 Field Description Refresh Counter Refresh When the pattern 0x00DB is written the watchdog counter will be reset to zero MVME2500 Installation and Use 68068001011 115 Memory Maps and Registers 5 5 17 PLD Watchdog Control Register The MVME2500 provides a watchdog control register Table 5 20 PLD Watchdog Control Register REG PLD Watch Dog Timer Load OxFFC80604 ee Tu m To 8 5 T T 5 1 7 T IW R OPER R RESET 0000 Field Description EN Enable If cleared the watchdog timer is disabled If set the watchdog timer is enabled 5 5 18 PLD Watchdog Timer Count Register The MVME2500 provides a watchdog timer count register Table 5 21 PLD Watchdog Timer Count Register PLD Watchdog Timer Count Oxffc80606 15 0 Count R W OxEA60 60secs 11
54. PU Debug P4 Battery Flash A U30 15148 m U58001 m E PMC Connectors U35 d SDRAM Chips IH i 1 2V_SW Supply MVME2500 Installation and Use 68068001011 49 Controls LEDs and Connectors 3 2 FrontPanel The following components are found on the MVME2500 front panel Figure 3 2 Front Panel LEDs Connectors and Switches Front USER 1 Serial Port Reset Switch FAIL USB rer SPEED GENET 1 iE ACT 2 SPEED f 50 MVME2500 Installation and Use 68068001011 Controls LEDs and Connectors 3 2 1 Reset Switch The MVME2500 has a single push button switch that has both abort and reset functions Pressing the switch for less than three seconds generates an abort interrupt to the P20x0 QorlQ PIC Holding it down for more than three seconds will generate a hard reset The VME SYSRESET is generated if the MVME2500 is the VMEbus system controller 3 3 LEDs The MVME2500 utilizes light emitting diodes LEDs to provide a visible status indicator on the front panel These LEDs show power failures power up status Ethernet link speed Ethernet activity SATA link and activity and PCI E valid lane status There are also a few user configurable LEDs Each LED description is necessary for troubleshooting and debugging 3 3 1 Front Panel LEDs The front panel LEDs are listed below Figure3 3 Front Panel LEDs SPEE
55. Richtlinien betrieben wird Verwenden Sie nur abgeschirmte Kabel zum Anschluss von Zusatzmodulen So ist sichergestellt dass sich die Aussendung von Hochfrequenzstrahlung im Rahmen der erlaubten Grenzwerte bewegt Warnung Dies ist eine Einrichtung der Klasse A Diese Einrichtung kann im Wohnbereich Funkst rungen verursachen In diesem Fall kann vom Betreiber verlangt werden angemessene Ma nahmen durchzuf hren 1 Besch digung des Produktes Hohe Luftfeuchtigkeit und Kondensat auf der Oberfl che des Produktes k nnen zu Kurzschl ssen f hren Betreiben Sie das Produkt nur innerhalb der angegebenen Grenzwerte f r die relative Luftfeuchtigkeit und Temperatur Stellen Sie vor dem Einschalten des Stroms sicher dass sich auf dem Produkt kein Kondensat befindet MVME2500 Installation and Use 68068001011 Sicherheitshinweise Besch digung von Schaltkreisen Elektrostatische Entladung und unsachgem er Ein und Ausbau des Produktes kann Schaltkreise besch digen oder ihre Lebensdauer verk rzen Bevor Sie das Produkt oder elektronische Komponenten ber hren vergewissern Sie sich da Sie in einem ESD gesch tzten Bereich arbeiten Fehlfunktion des Produktes Schalter die mit Reserved gekennzeichnet sind k nnen mit produktionsrelevanten Funktionen belegt sein Das Andern dieser Schalter kann im normalen Betrieb St rungen ausl sen Verstellen Sie nur solche Schalter die nicht mit Reserved gekennzeichnet sind Pr fen u
56. TA S SATA DOR Controller Connector STSEG 1 USB ee Controller 2c 808 Optional SATA Drive Kit Freescale QorlQ SDH P2020 SPI 16MB Flash E Connector Local Bus PMC1 Connectors LEDS RST PCI Xto Mc 110 VME Bridge eR Vetus MVME2500 Installation and Use 68068001011 77 Functional Description 4 2 4 2 1 78 Chipset The MVME2500 utilizes the QorlQ P20x0 integrated processor It offers an excellent combination of protocol and interface support which includes the following components e The QorlQ P20x0 integrated processor or e500v2 processor core P2020 and a single e500v2 processor core P2010 PCI Express interface Local Bus Controller Secure Digital Host Controller e 2Cinterface e USB interface DUART DMAcontroller Enhanced three speed Ethernet controller General Purpose I O GPIO Integrated Security Engine Common On chip Processor P20x0 Strapping pins e500 Processor Core The QorlQ integrated processors offer dual high performance e500v2 core P2020 anda single e500v2 core P2010 operates from 800 MHz up to 1 2 GHz core frequency The e500 processor core is a low power implementation of the family of reduced instruction set computing RISC embedded processor that implement the Book E definition of the PowerPC arc
57. TP the files from the server to local memory then boot run vxboot Using the Persistent Memory Feature The persistent memory means that the RAM s memory is not deleted during a reset Power cycling or by temporarily removing the power and then powering up the blade again will delete the memory content Persistent memory feature is enabled by default This feature can be useful in many situations including Analyzing kernel logs after a Linux kernel panic Defining a particular memory region for the persistent storage of application specific data Analyzing Kernel Log Files after a Kernel Panic When a board that is running the Linux OS indicates a kernel panic issue a reset through the faceplate button for example to analyze the cause then subsequently analyze kernel log files The persistent memory feature keeps the log files available in the memory To analyze the kernel log files 1 Issue a reset 2 Connect to U Boot For more information see Accessing U Boot on page 121 3 Enter the following command to obtain memory addresses of the kernel log files locate_kernel_log 1 The memory addresses of any found kernel log files will be displayed 4 Enter the following command to display the kernel logfile at any of these memory addresses printf lt memory address gt The persistent memory is useful in application specific data storage The standard U Boot variable pram can be used to reserve a memory region at t
58. TR Extended hold time on read accesses 0 The memory controller generates normal timing No additional cycles are inserted EAD External address latch delay 0 No additional bus clock cycles LALE asserted for one bus clock cycle only Clock Distribution The clock function generates and distributes all of the clocks required for system operation The ICS9FG108 is used to generate all the required PCI E clocks The 25 MHz clocks for the Ethernet PHY and SATA bridge are supplied by ICS83905 device Most of the QorlQ P2020 clocks are generated by ICS8405S071 device Additional clocks required by individual devices are generated near the devices using individual oscillators The following table lists the clocks required on the MVME2500 along with the frequency and source Table 7 6 Clock Distribution Device QorlQ P20x0 Clock Signal Frequency Clock Tree Source VIO CPU_SYSCLK 100MHz 1 58405071 QorlQ P20x0 CPU_DDR_CLK 100MHz 1 58405071 QorlQ P20x0 CLK_PCI_BR3 133Mhz 1 58405071 QorlQ P20x0 1 58405071 885 6121 MVME2500 In EC_GTX_CLK125 125Mhz 1 58405071 CLK_25MHZ_ICS840S07 ICS83905AGILF CLK_88SE6121_25MHZ ICS83905AGILF stallation and Use 68068001011 139 Programming Model Table 7 6 Clock Distribution continued Device Clock Signal Frequency Clock Tree Source VIO ICS9FG108 CLK_25MHZ_ICS9FG108 25Mhz 546165 BP_PHY_25MHZ_CLK 25Mhz
59. TSEC3 SGMMI Mode TSEC_1588_ALARM _OUT2 eTSEC3 Ethernet interface operates in standard parallel interface mode and uses the TSEC_3 pins default ETSEC1 and ETSEC2 Width eTSEC1 and eTSEC2 Ethernet interfaces operate in reduced pin mode either RTBI RGMI RMII 8 bit FIFO mode ETSEC1 Protocol TSEC1_TXDO TSEC1_TXD7 The eTSEC2 controller operates using the protocol or if configured in reduced mode if its not configured to operate in SGMII mode ETSEC2 Protocol 23 ETSEC3 Protocol TSEC2 TXDO TSEC2 TXD7 UART_RTSO UART_RTS1 10 The eTSEC2 controller operates using the protocol if configured in reduced mode if its not configured to operate in SGMII mode The eTSEC3 controller operates using the RGMII protocolif not configured to operate in SGMII mode MVME2500 Installation and Use 68068001011 133 Programming Model Table 7 1 POR Configuration Settings continued CONFIG BOOT ROM Location Host Agent Config Port Select DDR SDRAM TYPE SerDes PLL Time Out Enable System Speed CONFIG PINS TSEC1_TXD 6 4 TSEC1_TX_ER LWE1 LBS1 LA 18 19 TSEC1_TXDJ 3 1 TSEC2_TX_ER TSEC2_TXD1 TRIG_OUT LA 28 CONFIG SELECTION On chip boot ROM SPI configuration x 0 SDHC x 1 REMARKS The processor acts as the host root complex for all PCI E Serial Rapid
60. Write Protect and I2C Debug Register The MVME2500 PLD provides an 8 bit register which is used to indicate the status of I2C and SPI write protect manual switches and is used to control the SPI write enable The I2C debug ports are also provided in this register which is used in controlling the bus status Table 5 14 PLD Write Protect and I2C Debug Register PREG Write Protect I2C OxFFDF0054 6 3 2 1 0 Field RSVD MASTER FLASH_ I2C_DEB SERIAL_ RSVD I2C_1_ 12C_1_C _WP_DI WP_N UG EN FLASH_ D SABLED WP FE 222080 22281 RESET 110 MVME2500 Installation and Use 6806800L01L Memory Maps and Registers Field Description MASTER_WP_DISABLED FLASH_WP_N I2C DEBUG EN SERIAL FLASH WP I2C 1 D I2C_1_C 5 MVME2500 Installation and Use 68068001011 12 devices manual switch write protect status 1 Write protect enabled 0 Write protect disabled SPI devices manual switch write protect status 1 Write protect disabled 0 Write protect enabled I2C debug ports I2C 1 D and I2C_1_C enable 1 Drive Enabled 0 Drive Disabled SPI devices write protect register 1 Write protect enabled 0 Write protect disabled I2C debug port Data 12C_DEBUG_EN 0 Tri Stated I2C DEBUG EN 1 1 Driven High 0 Driven Low 12C debug port Clock 12C_DEBUG_EN 0 HiZ Tri Stated I2C_DEBUG_EN 1 1 Driven High 0 Driven Low When SERIAL FLASH WP is set to Low
61. ader information for application image imxtract Extract a part of a multi image interrupts Enable or disable interrupts itest Return true false on integer compare loadb Load binary file over serial line kermit mode Load S Record file over serial line Load binary file over serial line ymodem mode loop Infinite loop on address range md Memory display memmap Displays memory map mii MIl utility commands Memory modify auto incrementing address mmc MMC sub system mmcinfo Display MMC info moninit Reset nvram serial and write monitor to SPI flash mtest Simple RAM read write test mw Memory write fill Boot image through network using NFS protocol Memory modify constant address pci List and access PCI Configuration Space pci info Show information about devices on PCI bus ping Send ICMP ECHO REQUEST to network host printenv Print environment variables Boot image through network using RARP TFTP protocol Perform RESET of the CPU MVME2500 Installation and Use 68068001011 127 Boot System 6 6 128 Table 6 1 MVME2500 Specific U Boot Commands continued Command Description Run commands in an environment variable Save environment variables to persistent storage Run a delimited terminated list of commands scsi SCSI sub system scsiboot Boot from SCSI device setenv Set environment variables setexpr Set environment variable as
62. and Use 68068001011 11 List of Figures eee 12 MVME2500 Installation and Use 6806800L01L About this Manual EN Overview of Contents This manual is intended for users who install and configure MVME2500 product It is assumed that the user is familiar with the standard cabling procedures configuration of operating systems U Boot system and MVME Chassis The purpose of this manual is to describe MVME2500 product and the services it provides This manual includes description of MVME2500 product hardware firmware and also information about operating system This manual is divided into the following chapters and appendices About this Manual lists all conventions and abbreviations used in this manual and outlines the revision history Safety Notes summarizes the safety instructions in the manual Sicherheitshinweise is a German translation of the Safety Notes chapter Introduction gives an overview of the features of the product standard compliances mechanical data and ordering information Hardware Preparation and Installation outlines the installation requirements hardware accessories switch settings and installation procedures Controls LEDs and Connectors describes external interfaces of the board This includes connectors and LEDs Functional Description includes a block diagram and functional description of major components of the product Memory Maps and Registers contains information on system r
63. ble 7 4 PHY Types and Management Bus Address continued PHY MIIM Ethernet Port Function Location PHY Types Address Gigabit Ethernet port routed to front or back panel BCM54616 7 set by GBE_MUX_SEL in 52 TSEC3 Gigabit Ethernet port routed to back panel BCM54616 3 Other Software Considerations This section provides programming information in relation to various board components MRAM The MVME2500 provides 512 K bytes of fast non volatile storage in the form of Magnetoresistive Random Access Memory MRAM The MRAM is directly accessible by software using processor load and store instructions similar to the DRAM The difference is that the MRAM retains its contents even if the board is power cycled The MRAM is accessed through the LBC Real Time Clock The MVME2500 provides a battery back up DS1375 Real Time Clock RTC chip The RTC chip provides time keeping and alarm interrupts It is an I2C device and is accessed through the I2C bus address at 0x68 Ifthe RTC is stopped or started by default the following commands are necessary to start RTC in u boot dat get set reset date amp time Usage date MMDDhhmm CC YY ss date reset without arguments print date amp time with numeric argument set the system date amp time with reset argument reset the MVME2500 Installation and Use 68068001011 137 Programming Model 7 6 3 7 6 4 138 Quad UART Th
64. completely shut down before removing power from the board or removing the board from the chassis Product Damage Only use injector handles for board insertion to avoid damage to the front panel and or PCB Deformation of the front panel can cause an electrical short or other board malfunction Product Damage Inserting or removing modules with power applied may result in damage to module components Before installing or removing additional devices or modules read the documentation that came with the product Cabling and Connectors Product Damage RJ 45 connectors on modules are either twisted pair Ethernet TPE or E1 T1 1 network interfaces Connecting E1 T1 1 line to an Ethernet connector may damage your system e Make sure that TPE connectors near your working area are clearly marked as network connectors e Verify that the length of an electric cable connected to a TPE bushing does not exceed 100 meters e Make sure the TPE bushing of the system is connected only to safety extra low voltage circuits SELV circuits If in doubt ask your system administrator MVME2500 Installation and Use 68068001011 21 Safety Notes Battery 22 Board System Damage Incorrect exchange of lithium batteries can result in a hazardous explosion When exchanging the on board lithium battery make sure that the new and the old battery are exactly the same battery models If the respective battery model is not available contact your
65. ctors 3 4 1 3 3 4 1 4 56 USB Connector J5 The MVME2500 uses upright USB receptacle mounted in the front panel Table 3 5 USB Connector 5 Signal Description Mounting Ground Mounting Ground MTG Mounting Ground MTG Mounting Ground VMEBus P1 Connector The VME P1 connector is 160 pin DIN The P1 connector provides power and VME signals for 24 bit address and 16 bit data The pin assignments for the P1 connector are as follows Table 3 6 VMEbus P1 Connector 2 BCLR DATA 9 3 ACFAIL DATA 10 4 BGINO DATA 11 5 BGOUTO DATA 12 Towns was omen wc fan 7 Tonne Teo ow qw ne 8 DATA 7 BGIN2 DATA 15 NC 9 GND BGOUT2 GND GAP NC MVME2500 Installation and Use 68068001011 Controls LEDs and Connectors Table 3 6 VMEbus P1 Connector continued Pin RowA Row B Row C Row D Row Z SYSCLK BGIN3 SYSFAIL SYSRESET 3 3V not used LWORD GA2 5 3 3V not used 3 3V not used GA4 3 3V not used ADD 27 NC IACK 3 3V not used IACKIN NC IACKOUT 3 3V not used 3 3V not used NC 3 3V not used ADD 35 NC 3 3V not used NC 3 3V not used MVME2500 Installation and Use 68068001011 57 Controls LEDs and Connectors 3 4 1 5 58 Table 3 6 VMEbus P1 Connector continued br qe ae qo 1 VMEBus P2 Connector
66. d automatic DRAM data initialization Write leveling for DDR3 memories and supports up to eight posted refreshes PCI Express Interface The PCI Express interface is compatible with the PCI Express Base Specification Rev 1 0a The PCI Express controller connects the internal platform to a 2 5 GHz serial interface The P20x0 has options for up to three PCI E interfaces with up to x4 link width The PCI E controller is configured to operate as either PCI E root complex RC or as an endpoint EP device MVME2500 Installation and Use 68068001011 79 Functional Description 4 2 4 4 2 5 4 2 6 4 2 7 4 2 8 80 Local Bus Controller LBC The main component of the enhanced LBC is the memory controller that provides a 16 bit interface to various types of memory devices and peripherals The memory controller is responsible for controlling eight memory banks shared by the following a general purpose chip select machine a flash controller machine FCM and user programmable machines UPMs Secure Digital Hub Controller SDHC The SDHC eSDHC provides an interface between the host system and the memory cards such as the MMCand the SD It is compatible with the SD Host Controller Standard Specification Ver 2 0 and supports the following SD miniSD SD Combo MMC and RS MMC I2C Interface The MVME2500 uses only one of the two independent I C buses on the processor For more information see I2C Devices
67. duction Boot Flash Memory 16 MB SPI flash Support crisis recovery Boot Firmware U Boot based firmware image in 16 MB SPI Flash This flash is split into two 8 MB chips Operating Systems Based from BSP provided by Freescale which is based from standard Linux version 2 6 32 rc3 Development tool is Itib 9 1 1 Linux Target Image Builder from Freescale VxWorks MVME721X Transition Module 1 0 Two GbE interfaces Four RS 232 serial ports 12 PMCI O e Software U Boot firmware e OnePMC XMC site SATA port for optional on board hard drive e Extended temperature and rugged variants e Thefrontpanell O configuration consists of two RJ45 10 100 1000BASE T Ethernet ports a USB 2 0 port a Micro DB9 RS 232 serial console port anda reset abort switch It also has an LED to signal board failure and another LED that can be configured in the LED register e Therearl O includes support for VMEbus Legacy VME VME 64 VME64x and 2eSST rear PMC XMC I O RTM I O through VME P2 two 10 100 1000BASE T Ethernet four UART and RTM I2C Presence Power 2Cdevices Real Time Clock Board Temperature Sensor 30 MVME2500 Installation and Use 68068001011 Introduction 8KBVPD EEPROM Two 64 User EEPROM VMEbus Interface Controller Tsi148 PCI X to VMEbus bridge with support for VME64 and 2eSST protocols Watchdog timers and registers 1 2 Standard Compliances The product i
68. e SEC 3 1 Theintegrated security engine ofthe P20x0 is designed to off load intensive security functions like key generation and exchange authentication and bulk encryption from the processor core It includes eight different execution units where data flows in and out of an EU MVME2500 Installation and Use 68068001011 81 Functional Description 4 2 13 4 2 14 4 3 4 4 4 4 1 82 Common On Chip Processor COP The COP is the debug interface of the QorlQ 20 0 processor It allows a remote computer system to access and control the internal operation of the processor The COP interface connects primarily through the JTAG and has additional status monitoring signals The COP has additional features like breakpoints watch points register and memory examination modification and other standard debugging features P20x0 Hardware Configuration Pins Aseries of strapping pins are required to initialize the P20x0 These pins are samples during the assertion of HRESET and return to their assigned function after HRESET is deasserted System Memory The processors integrated memory controller supports both DDR2 and DDR3 memory devices It has one channel and can be configured up to four memory banks with x8 x16 and x32 devices Using 4 GB devices allows support of up to 16 GB of memory The MVME2500 has total of eight board variants half of which has soldered 2 GB memory while the remaining half has 16 GB memory The x8 or 1
69. e MVME2500 console RS232 port is driven by the UART built into the P20x0 QorlQ chip Additionally the MVME2500 has a Quad UART chip which provides four 16550 compatible UART These additional UARTS are internally accessed through the LBC bus The Quad UART chip clock input which is internally divided to generate the baud rate is 1 8432 MHz The four physically connect to RS232 DB9 serial ports through the RTM LBC Timing Parameters The following table defines the timing parameters for the devices on the local bus Table 7 5 LBC Timing Parameters 0011 0011 0011 0011 0011 0011 0011 0 0 0 0 0 Field Description BCTLD CSNT ACS Buffer control disable 0 LBCTL is asserted upon access to the current memory bank Chip Select negation time 1 1 and LWE are negated one quarter of the bus clock cycle earlier Address to chip select setup 10 LCSn is outputted one quarter bus clock cycle after the address lines MVME2500 Installation and Use 68068001011 Programming Model 7 7 5 Extra Address to chip select setup 0 Address to chip select setup is determined by ORx ACS SCY Cycle length in bus clocks 0011 Three bus clock cycle wait state SETA External address termination 0 Access is terminated internally the memory controller unless the external device asserts LGTA earlier to terminate the access TRLX Timing Relaxed 0 Normal timing is generated by the GPCM EH
70. e cece eee ence EEEN EEEE ENC ENTNER 105 5 5 4 PLD Day Register china He lb 105 5 5 PLD Sequenice Register abbot add I I a 105 5 5 6 PLD Power Good Monitor lt 106 5 5 7 PLD LED 107 5 5 8 PLD PCI PMC XMC 5 108 5 5 9 PLD U Boot and TSI Monitor 109 5 5 10 PLD Boot Bank Register cece eee eee eh re 109 5 5 11 PLD Write Protect and I2C Debug Register 110 5 5 12 PED Test Register ee bias Saad eee th eae anaes 112 5 9 13 PED Test Register 2 IEEE mi 112 5 5 14 PLD GPIO2 Interrupt een een 113 5 5 15 PLD Shutdown and Reset Control and Reset Reason Register 114 5 5 16 PLD Watchdog Timer Refresh lt 2 115 5 5 17 PLD Watchdog Control Register eee nee een 116 5 5 18 PLD Watchdog Timer Count lt 116 5 6 External Timer Registers cece cece eee ene ee hen 117 5 6 1 PrescalerRegistar 117 5 6 2 Control Registers ose
71. ect peripherals and apply power to the board NOTICE Product Damage 45 connectors modules are either twisted pair Ethernet or E1 T1 J1 network interfaces Connecting an E1 T1 1 line to an Ethernet connector may damage your system Make sure that TPE connectors near your working area are clearly marked as network connectors Verify that the length of an electric cable connected to a TPE bushing does not exceed 100 meters Make sure the TPE bushing of the system is connected only to safety extra low voltage circuits SELV circuits If in doubt ask your system administrator The console settings for the MVME2500 are e Eightbits per character e One stop bit per character e Parity disabled no parity e Baud rate of 9600 baud Verify that hardware is installed and the power peripheral cables connected are appropriate for your system configuration Replace the chassis or system cover reconnect the chassis to power source and turn the equipment power on MVME2500 Installation and Use 68068001011 Chapter 3 Controls LEDs and Connectors 3 1 Board Layout The following figure shows the components and the connectors on the MVME2500 board Figure 3 1 Component Layout 51 Switch 1 8V Supply T51384 Onboard LEDs 2 Switch 055001 036 33 ND35 037 09 012 60 Header rmm 415V He a Omni E Supply C
72. ented editorial changes 6806800L01C May 2011 Updated Chapter 3 Controls LEDs and Connectors by adding the following Chapter 3 Board Layout Chapter 3 Front Panel Connectors Chapter 3 On board Connectors Added Chapter 4 Functional Description Applied editorial edits 6806800L01D May 2011 Edited Memory Maps and Registers Edited Programming Model Edited Figure Component Layout Edited Figure On board LEDs Added Front Panel Serial Port J4 6806800L01E July 2011 Updated Table Available Board Variants Updated Appendix B Related Documentation MVME2500 Installation and Use 68068001011 17 About this Manual 18 Part Number 6806800L01F Publication Date August 2011 Description Changed title of Section 3 4 1 to Front Panel Connectors Edited Front Panel Serial Port J4 Updated Figure Component Layout to include proper label for XMC connectors Updated Safety Notes and Sicherheitshinweise 6806800L01G January 2013 Updated Standard Compliances on page 21 6806800L01H 6806800101 January 2014 February 2014 Added Flash Memory and updated SPI Flash Memory Re branded to Artesyn template Added Declaration of Conformity 6806800L01K 68068001011 2015 April 2015 Added Figure Power Up Sequence on page 93 and Figure Reset Sequence on page 96 Updated Boot Options on page 122 Real Time Clock o
73. er Requirements 41 Table 3 1 FrontPanel LEDS 4 2 ener ae ba s 52 Table 3 2 On board EEDS Status ER 53 Table 3 3 Front Panel Tri Speed Ethernet Connector J1 54 Table 3 4 Front Panel Serial Porta ter eere eee eee RAT REI arn 55 Table 3 5 USB Connector 5 teer E E RI 56 Table 3 6 VMEbus P1 Connector anne a 56 Table 3 7 VMEbus P2 Gonnect r asien exei beue Reese 58 Table 3 8 Flash Programming Header P7 59 Table 3 9 Custom SATA Connector J3 E 60 Table 3 10 Connector 61 Table 3 11 PMC T12 Connector u ee ea ne 62 Table 3 12 13 Connector eco rem t ee ash ana 64 Table 3 13 14 Connector ee een 65 Table 3 14 JTAG Connector 6 e hm em emere 66 Table 3 15 COP Header P50 ea en en 68 Table 3 16 SDiConnector 2 lan 69 Table 3 17 Connector 2 Pinout cece cece II e meme 69 Table 3 18 P20x0 Debug Header 70 Table 3 19 Geographical Address Switch cece cece e een 72 Table 3 20 Geographical Address Switch Settings eee eee nee eee 73 Table 4 1 Voltage Supp
74. er is also cleared For periodic interrupts this equation should be used to calculate the compare value for a specific period T Compare register value T us When programming the tick timer for periodic interrupt the counter should be cleared to zero by software and then enabled If the counter does not initially start at zero the time to the first interrupt may be longer or shorter than expected Note that the rollover time for the counter is 71 6 minutes Since the processoris 16 bits and the tick timer is 32 bits the compare register was split in half Accessing the whole register will require two transactions Table 5 24 Compare High Word Registers Tick Timer 0 Compare Value High Word OxFFC80204 Tick Timer 1 Compare Value High Word OxFFC80304 REG Tick Timer 2 Compare Value High Word OxFFC80404 es BER A EUN EEE Field TickTimer Compare Value High Word 16 bits OPER R W RESET 0x0000 Table 5 25 Compare Low Word Registers Tick Timer 0 Compare Value Low Word OxFFC80206 Tick Timer 1 Compare Value Low Word OxFFC80306 REG Tick Timer 2 Compare Value Low Word OxFFC80406 TickTimer Compare Value Low Word 16 bits R W RESET 0x0000 MVME2500 Installation and Use 68068001011 119 Memory Maps and Registers 5 6 4 Counter High and Low Word Registers When enabled the tick timer counter register increments every microsecond Software may read or
75. esources including system control and status registers and external timers Boot System describes the boot loader software Programming Model contains additional programming information for the board Replacing the Battery contains the procedures for replacing the battery Related Documentation provides a listing of related product documentation manufacturer s documents and industry standard specifications MVME2500 Installation and Use 68068001011 13 About this Manual Abbreviations This document uses the following abbreviations Common On Chip Processor Complex Programmable Logic Device Double Data Rate 3 Dual UART Error Checking Correction EEPROM Erasable Programmable Read Only Memory Federal Communications Commission Field Programmable Gate Array General Purpose Input Output Institute of Electrical and Electronics Engineers Hard Disk Drive Local Bus Controller Multi Chip Package Magneto resistive Random Access Memory Peripheral Component Interconnect PCI Express Peripheral Component Interconnect extended PCI Mezzanine Card Input Output Module Programmable Logic Device PCI Mezzanine Card IEEE P1386 1 Processor PCI Mezzanine Card Real Time Clock Rear Transition Module SATA Serial AT Attachment SDHC Secure Digital Host Controller 14 MVME2500 Installation and Use 68068001011 About this Manual Term Definition
76. fe09000 OxffeO9fff PCIE1CCSR DMA2 CCSR GPIO CCSR L2 Cache CCSR Oxffe0a000 OxffeOafff Oxffe0c100 Oxffe0c303 OxffeOfcOO OxffeOfcff Oxffe20000 Oxffe20fff DMA1 CCSR Oxffe21100 Oxffe21303 USB CCSR Oxffe22000 Oxffe22fff ETSECI CCSR ETSEC2 CCSR ETSEC3 CCSR SDHCI CCSR Oxffe24000 Oxffe24fff Oxffe25000 Oxffe25fff Oxffe26000 Oxffe26fff Oxffe2e000 Oxffe2efff 4KB Crypto CCSR Oxffe30000 Oxffe3ffff 64 KB msi CCSR Oxffe41600 Oxffe4167f 128B mpic CCSR Global Utilities CCSR L2 Cache Mem MVME2500 Installation and Use 68068001011 Oxffe40000 Oxffe7ffff Oxffee0000 OxffeeOfff Oxf0f80000 OxfOffffff 256 KB 4 512 103 Memory Maps and Registers 5 9 5 5 1 5 5 2 104 Programmable Logic Device PLD Registers PLD Revision Register The MVME2500 provides a PLD revision register that is read by the system software to determine the current version of the timers registers PLD Table 5 4 PLD Revision Register PLD Revision Register OXFFDF0000 7 PLD Rev R Field Description PLD_REV 8 bit field containing the current timer register PLD revision The revision number starts at 01 PLD Year Register The MVME2500 PLD provides an 8 bit register which contains the build year of the timers registers PLD Table 5 5 PLD Year Register PLD Year Register OXFFDF0004 MVME2500 Installation and Use 6806800L0
77. gation of Artesyn to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to an Artesyn website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Artesyn It is possible that this publication may contain reference to or information about Artesyn products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Artesyn intends to announce such Artesyn products programming or services in your country Limited and Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Artesyn Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Contact Address Artesyn Embedded Technologies Artesyn Embedded Technologies Marketing Communications Lilienthalstr 17 19 2900 S Diablo Way Suite 190 85579 Neubiberg Munich Tempe Arizona 85282 Germany Contents
78. he RTC hold up requirements that maintain the correct date and time It provides backup power for the on board RTC when primary power is unavailable 4 20 Debugging Support The following information shows the details of Artesyn debugging support as applied to the MVME2500 MVME2500 Installation and Use 68068001011 97 Functional Description 4 20 1 4 20 2 98 POST Code Indicator The following table shows the LED status of the POST Codes For the location of the POST Code LEDs see On board LEDs on page 53 Logic 1 LED is ON Logic 0 LED is OFF Table 4 3 POST Code Indicator on the LED Sequence D33 D34 D35 Description 1 0 0 0 U boot has been copied from SPI flash to CPU cache 2 0 1 0 Serial console has been initialized some text is visible on the terminal 3 0 1 1 DDR has been initialized using SPD parameters Execution is still in the cache 4 1 0 0 Execution has been relocated to RAM 5 1 0 1 PCI has been initialized 6 1 1 0 POST routines are finished 7 1 1 1 Additional SW routines are finished 8 0 0 0 U boot prompt is visible on the terminal can start loading OS image from USB Ethernet SATA SSD SD JTAG Chain and Board The MVME2500 is designed to work with separate JTAG board rather than with an on board JTAG multiplexer The chip can support up to a 6 scan port and the board s boundary scan requires the following to function ASSET hardware JTAG board a
79. he end of the physical memory to prevent it from being overwritten U Boot reports less memory to the Linux kernel through the mem parameter indicating that the operating system should not use it either For more information see the U Boot documentation MVME2500 Installation and Use 68068001011 125 Boot System 6 5 2500 Specific U Boot Commands Table 6 1 MVME2500 Specific U Boot Commands base Print or set address offset bdinfo Print board info structure boot Boot default i e run bootcmd Boot default i e run bootcmd Boot from an ELF image in memory bootm Boot application image from memory bootp Boot image through network using BOOTP TFTP protocol bootvx Boot VxWorks from an ELF image Memory compare Print console devices and information Multiprocessor CPU boot manipulation and release Checksum calculation Get set reset date amp time Runs POST diags Echo args to console ext2load Load binary file from a Ext2 file system ext2ls List files in a directory default fatinfo Print information about file system fatload Load binary file from a DOS file system List files in a directory default m Flattened device tree utility commands Start application at address addr 126 MVME2500 Installation and Use 68068001011 Boot System Table 6 1 MVME2500 Specific U Boot Commands continued Command Description Print online help Print he
80. hexXt cELUUIUGucc uUPeirco o BM 150 MVME2500 Installation and Use 68068001011 A mS YN Eu E EMBEDDED TECHNOLOGIES Artesyn Embedded Technologies Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners 2015 Artesyn Embedded Technologies Inc
81. hitecture The e500 is a 32 bit implementation of the Book E architecture using the lower words of 64 bit general purpose registers GPRs while E500v2 uses 36 bit physical addressing MVME2500 Installation and Use 6806800L01L Functional Description 4 2 2 4 2 3 Integrated Memory Controller A fully programmable DDR SDRAM controller supports most JEDEC standard DDR2 and DDR3 memories available Unbuffered registered DIMMs are also supported A built in error checking and correction ECC ensures very low bit error rates for reliable high frequency operation Though ECC is not implemented on MVME2500 the board includes a place holder for additional chips for ECC whenever it is needed in the future The memory controller supports the following 16GBofmemory Asynchronous clocking from platform clock with programmable settings that meets all the SDRAM timing parameters Upto four physical banks each bank can be independently addressed to 64 Mb to 4 Gb memory devices depending on the internal device configuration with x8 x16 x32 data ports Chip set interleaving and partial array self refresh Data mask signal and read modify write for sub double word writes when ECC is enabled e Double bit error detection and single bit error correction ECC 8 bit check work across 64 bit data Address parity for registered DIMMs Automatic DRAM initialization sequence or software controlled initialization sequence an
82. iew its location on the board see Figure 3 1 on page 49 Figure 3 4 On board LEDs D33 D34 D35 D36 D37 D38 09 Table 3 2 On board LEDs Status Power Fail Red This indicator is illuminated when one or more of the on board voltage rails fails D33 User Defined Amber Controlled by the FPGA Used for boot up sequence indicator User Defined Amber Controlled by the FPGA Used for boot up sequence indicator User Defined Amber Controlled by the FPGA Used for boot up sequence indicator D36 Early Power Fail Amber This indicator is lit when the early 3 3V power supply fails D37 User Defined Amber Controlled by the FPGA User Defined Amber Controlled by the FPGA 3 4 Connectors This section describes the pin assignments and signals for the connectors on the MVME2500 MVME2500 Installation and Use 68068001011 53 Controls LEDs and Connectors 3 4 1 Front Panel Connectors The following connectors are found on the outside of the MVME2500 board These connectors are divided between the front panel connectors and the backplane connectors The front panel connectors include the J1 and the J5 connectors The backplane connectors include the P1 and the P2 connectors 3 4 1 1 RJ45 with Integrated Magnetics J1 The MVME2500 uses an X2 RJ45 Table 3 3 Front Panel Tri Speed Ethernet Connector J1 Pin Name Signal Description 1A GND 2A NC 3A Port A TRD3 4A Port A TR
83. in a system Make sure that all user defined switches are properly set before installing a PMC XMC module For more information see Switches on page 71 42 MVME2500 Installation and Use 68068001011 Hardware Preparation and Installation 2 5 Installing Accessories 2 5 1 Rear Transition Module The MVME2500 does not support hot swap Remove power to the rear slot or system before installing the module A PCMI O Module PIM needs to be manually configured and installed before placing the transition module NOTICE Damage of Circuits Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life Before touching the board or electronic components make sure that you are working in an ESD safe environment Product Damage e Only use injector handles for board insertion to avoid damage to the front panel and or PCB Deformation of the front panel can cause an electrical short or other board malfunction Board Malfunction Switches marked as reserved might carry production related functions and can cause the board to malfunction if their setting is changed Do not change settings of switches marked as reserved The setting of switches which are not marked as reserved has to be checked and changed before board installation Installation Procedure 1 Turn OFF all equipment and disconnect the power cable from the AC power source 2 Remove the chassis cover 3 Rem
84. lacement Procedure To replace the battery proceed as follows 1 Remove the old battery 2 Install the new battery with the plus sign facing up 3 Dispose of the old battery according to your country s legislation and in an environmentally safe way MVME2500 Installation and Use 68068001011 145 Replacing the Battery _ s 146 MVME2500 Installation and Use 68068001011 Related Documentation Appendix 1 Artesyn Embedded Technologies Embedded Computing Documentation The publications listed below are referenced in this manual You can obtain electronic copies of Artesyn Embedded Technologies Embedded Computing publications by contacting your local Artesyn sales office For released products you can also visit our Web site for the latest copies of our product documentation 1 Goto www artesyn com computing support product technical documentation php 2 Under FILTER OPTIONS click the Document types drop down list box to select the type of document you are looking for 3 Inthe Search text box type the product name and click GO Table B 1 Artesyn Embedded Technologies Embedded Computing Publications Document Title Publication Number MVME2500 Release Notes 6806800L02 MVME2500 Quick Start Guide 6806800L03 MVME2500 Safety Notes 6806800L13 MVME721X RTM Installation and Use 6806800M42 MVME721X RTM Quick Start Guide 6806800M53 MVME721X RTM Safety Notes 6806800M54
85. list and must not be used as replacement for qualified personnel Keep away from live circuits inside the equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not install substitute parts or perform any unauthorized modification of the equipment or the warranty may be voided Contact your local Artesyn representative for service and repair to make sure that all safety features are maintained EMC Results pending testing This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications MVME2500 Installation and Use 68068001011 19 Safety Notes Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense Changes or modifications not expressly approved by Artesyn could void the user s authority to operate the equipment
86. ly Requirement 92 Table 4 2 Thermal Interrupt Threshold eee ene een nent been eee eeae 97 Table 4 3 POST Code Indicator on the LED eee een een een 98 Table 4 4 Transition Module Features 99 Table 5 1 Physical Address Map 0 eee e eee e cece cere 101 Table 5 2 Flash Memory 102 Table 5 3 Linux Devices Memory ssssese II 102 Table 5 4 PLB Revision Register rendre ae mean 104 Table 5 5 PLD dde belie aad aan 104 Table 5 6 PLD M nth Register un nee a has 105 MVME2500 Installation and Use 68068001011 9 List of Tables Table 5 7 PLD Register u a esse ae eee du Rc RR 105 Table 5 8 PLD Sequence Register 2 rrr mans ae 105 Table 5 9 PLD Power Good Monitor 106 Table 5 10 PLD LED Control Register cence eect EEEREN EEDE ENE 107 Table 5 11 PLD PCI PMC XMC Monitor 108 Table 5 12 PLD U Boot and TSI Monitor Register 109 Table 5 13 PLD Boot Bank Register 109 Table 5 14 PLD Write Protect and I2C Debug Register
87. n page 137 and Crisis Recovery on page 87 Replaced MVME7216 and its variants with MVME721X MVME2500 Installation and Use 68068001011 Safety Notes EN This section provides warnings that precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed during all phases of operation service and repair of this equipment You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment Artesyn Embedded Technologies intends to provide all necessary information to install and handle the product in this manual Because of the complexity of this product and its various uses we do not guarantee that the given information is complete If you need additional information ask your Artesyn representative This product is a Safety Extra Low Voltage SELV device designed to meet the EN60950 1 requirements for Information Technology Equipment The use of the product in any other application may require safety evaluation specific to that application Only personnel trained by Artesyn or persons qualified in electronics or electrical engineering are authorized to install remove or maintain the product The information given in this manual is meantto complete the knowledge of a specia
88. nd JTAG cable The MVME2500 provides 60 pin header that can connect to the JTAG board using a custom cable The JTAG board provides three different connectors for the ASSET hardware flash programming and the MVME2500 JTAG connector The board is equipped with TTL buffers to help improve the signal quality as it traverses over the wires MVME2500 Installation and Use 68068001011 Functional Description 4 20 3 Custom Debugging Custom debugging makes use of the common on chip processor Refer to Common On Chip Processor COP on page 82 for details 4 21 RearTransition Module RTM The MVME2500 is compatible with the MVME721x RTM The MVME721X RTM is for I O routing through the rear of a compact VMEbus chassis It connects directly to the VME backplane in chassis with an 80 mm deep rear transition area The MVME721X RTM is designed for use with the MVME7100 MVME2500 iVME7210 and MVME 4100 It has the following features Table 4 4 Transition Module Features One five row P2 backplane connector for serial and Ethernet I O passed from the SBC Four RJ 45 connectors for rear panel I O four asynchronous serial channels Two RJ 45 connectors with integrated LEDs for rear panel I O two 10 100 1000 Ethernet channels One PIM site with rear panel I O For more information refer to the MVME721x RTM Installation and Use See Appendix Related Documentation on page 147 for details on how to obtain and dow
89. nd ggf andern Sie die Einstellungen der nicht mit Reserved gekennzeichneten Schalter bevor Sie das Produkt installieren Installation Datenverlust Das Herunterfahren oder die Deinstallation eines Boards bevor das Betriebssystem oder andere auf dem Board laufende Software ordnungsmemass beendet wurde kann zu partiellem Datenverlust sowie zu Sch den am Filesystem f hren Stellen Sie sicher dass s mtliche Software auf dem Board ordnungsgemass beendet wurde bevor Sie das Board herunterfahren oder das Board aus dem Chassis entfernen Besch digung des Produktes Fehlerhafte Installation des Produktes kann zu einer Besch digung des Produktes f hren Verwenden Sie die Handles um das Produkt zu installieren deinstallieren Auf diese Weise vermeiden Sie dass das faceplate oder die Platine deformiert oder zerstort wird Besch digung des Produktes und von Zusatzmodulen Fehlerhafte Installation von Zusatzmodulen kann zur Besch digung des Produktes und der Zusatzmodule f hren Lesen Sie daher vor der Installation von Zusatzmodulen die zugeh rige Dokumentation MVME2500 Installation and Use 68068001011 25 Sicherheitshinweise Kabel und Stecker Batterie 26 Besch digung des Produktes Bei den RJ 45 Steckern die sich an dem Produkt befinden handelt es sich entweder um Twisted Pair Ethernet TPE oder um E1 T1 1 Stecker Beachten Sie dass ein versehentliches Anschlie en einer E1 T1 1 Leitung an einen TPE Stecker das
90. ndige Gesch ftsstelle von Artesyn So stellen Sie sicher dass alle sicherheitsrelevanten Aspekte beachtet werden MVME2500 Installation and Use 68068001011 23 Sicherheitshinweise EMV Betrieb 24 Das Produkt wurde in einem Artesyn Standardsystem getestet Es erf llt die f r digitale Ger te der Klasse A g ltigen Grenzwerte in einem solchen System gem den FCC Richtlinien Abschnitt 15 bzw EN 55022 Klasse A Diese Grenzwerte sollen einen angemessenen Schutz vor St rstrahlung beim Betrieb des Produktes in Gewerbe sowie Industriegebieten gew hrleisten Das Produkt arbeitet im Hochfrequenzbereich und erzeugt St rstrahlung Bei unsachgem em Einbau und anderem als in diesem Handbuch beschriebenen Betrieb k nnen St rungen im Hochfrequenzbereich auftreten Wird das Produkt in einem Wohngebiet betrieben so kann dies mit grosser Wahrscheinlichkeit zu starken St rungen f hren welche dann auf Kosten des Produktanwenders beseitigt werden m ssen nderungen oder Modifikationen am Produkt welche ohne ausdr ckliche Genehmigung von Artesyn durchgef hrt werden k nnen dazu f hren dass der Anwender die Genehmigung zum Betrieb des Produktes verliert Boardprodukte werden in einem repr sentativen System getestet um zu zeigen dass das Board den oben aufgef hrten EMV Richtlinien entspricht Eine ordnungsgem sse Installation in einem System welches die EMV Richtlinien erf llt stellt sicher dass das Produkt gem ss den EMV
91. nload the document MVME2500 Installation and Use 68068001011 99 Functional Description _ 5 8 0_0 0 _ _ u 100 MVME2500 Installation and Use 68068001011 Chapter 5 Memory Maps and Registers 5 1 Overview System resources including system control and status registers external timers and the QUART are mapped into 16 MB address range accessible from the MVME2500 local bus through the P20x0 QorlQ LBC 5 2 Memory Map The following table shows the physical address map of the MVME2500 Table 5 1 Physical Address Map Device Name Start Address 0 0000 0000 End Address Ox7fff ffff Size 2 PCIE 3 Mem 0x8000_0000 OxOfff_ffff 512 MB PCIE 2 Mem 0xa000 0000 Oxbfff_ffff 512 MB PCIE 1 Mem 0xc000_0000 Oxdfff_ffff 512 MB PCIE 3 IO 0 0_0000 Oxffco_ffff PCIE 210 Oxffc1_0000 Oxffc1_ffff PCIE 110 Oxffc2_0000 Oxffc2_ffff UARTO Oxffc4_0000 OxffcA_ffff UART1 Oxffc5_0000 Oxffc5 ffff 64 KB UART2 Oxffc6 0000 Oxffc6_ffff 64 KB Oxffc7_0000 Oxffc7_ffff Oxffc8_0000 Oxffc8_ffff Oxffdf_0000 Oxffdf_Offf Oxffe0_0000 Oxffef_ffff MRAM Oxfff0_0000 Oxfff7_ffff 512 KB MVME2500 Installation and Use 68068001011 101 Memory Maps and Registers 5 3 5 4 102 Flash Memory Map The table below lists the memory range designated to U boot and ENV variables Table 5 2 Flash Memory Map U bo
92. ns e enn 137 Lol UU 137 7 6 2 RealTimeClock nose ee ee RR UB es 137 7 6 3 Quad VART 138 7 6 4 LBCTiming Parameters hh 138 7 7 Clock Distribution a et e 139 7 4 1 System Clock ne ne ee 140 7 7 2 RealTimeClockInput secessit 141 7 7 3 Local Bus Controller Clock Divisor l esses 141 A Replacing the Battery eue oe a 143 Replacing the Battery cece cece cee een nee ehh 143 MVME2500 Installation and Use 6806800L01L 7 Contents B Related Documentation 147 B 1 Artesyn Embedded Technologies Embedded Computing Documentation 147 B 2 Manufacturers Documents cence nen ee nee m sen 148 Related ccc cece cece ene nen nee n eee emen 148 8 MVME2500 Installation and Use 6806800L01L List of Tables EN Table 1 1 Board Standard Compliances 31 Table 1 2 Mechanical rre eere ERU rx e ORO RR RE EE PU EE RR ERR 33 Table 1 3 Available Board Variants eer ne 33 Table 1 4 Available Board Accessories _ 34 Table 2 1 Environmental Requirements 0 ec cece eee 39 Table 2 2 Pow
93. nterrupt enabled 0 No Interrupt TICKO_INT Tick Timer 0 interrupt 1 Interrupt enabled 0 No Interrupt TICK1_INT Tick Timer 1 interrupt 1 Interrupt enabled 0 No Interrupt TICK2_INT Tick Timer 2 interrupt 1 Interrupt enabled 0 No Interrupt MVME2500 Installation and Use 68068001011 113 Memory Maps and Registers 5 5 15 PLD Shutdown and Reset Control and Reset Reason Register The MVME2500 provides an 8 bit register to execute the shutdown and reset commands The board s reset reason is also included in this register Table 5 18 PLD Shutdown and Reset Control and Reset Reason Register REG PLD Shutdown and Reset Reason OxFFDFOOFF Field AUTO_SH RSVD Soft_RST Clear_Cause CPU_RESET WD_TIME LRSTO Sft_RST DN_MASK OUT R OPER R W W W W RESET 0 0 0 0 X X X X Note Changing a Reserved Register setting may cause damage to the board or malfunction Reserved register settings should not be changed Field Description AUTO SHDN MASK Automatic Shutdown Mask 1 Auto Shutdown Mask Enable 0 Auto Shutdown Mask Disable Note Automatic shutdown is generated after 1 second whenever a power good signal de asserts RSVD Reserved Note This bit is reserved and cannot be used Soft RST Board Soft Reset self clearing 1 Execute soft reset 0 No reset Clear Cause Clear Reset Reason self clearing 1 Clear Reason 0 None 114 MVME2500 Installation and Use 68068001011 Memory
94. on 2 5 2 PMC XMC Support Installation Procedure Read all notices and follow these steps to install a PMC on the baseboard Damage of Circuits Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life Before touching the board or electronic components make sure that you are working in an ESD safe environment Product Damage Inserting or removing modules with power applied may result in damage to module components e Before installing or removing additional devices or modules read the documentation that came with the product 1 Attach an ESD strap to your wrist Attach the other end of the strap to the chassis as a ground Make sure that it is securely fastened throughout the procedure 2 Remove the PMC XMC filler plate from the front panel cut out 3 Slide the front bezel of the PMC XMC into the front panel cut out from backside The front bezel of the PMC XMC module will be placed with the board when the connectors on the module align with the connectors on the board 4 Align the mating connectors properly and apply minimal pressure to the PMC XMC until it is seated to the board 5 Insert the four PMC XMC mounting screws through the mounting holes on the bottom side of the board and then thread the four mount points on the Fasten the screws MVME2500 Installation and Use 68068001011 45 Hardware Preparation and Installation 2 6 46
95. onnector Pin Signal Description Pin Signal Description KR WwW U1 64 2500 Installation and Use 68068001011 Controls LEDs and Connectors Table 3 12 PMC J13 Connector continued Signal Description Signal Description AD 50 GND 31 AD 49 63 GND 32 GND 64 NC Table 3 13 PMC J14 Connector Signal Description PMCIO 1 PMCIO 2 PMCIO3 Signal Description PMCIO 33 PMCIO 34 PMCIO 35 PMCIO 4 PMCIO 36 PMCIO 5 PMCIO 37 PMCIO 6 PMCIO 7 PMCIO 8 PMCIO 9 PMCIO 38 PMCIO 39 PMCIO 40 PMCIO 41 LENIN 3 4 5 6 B 10 PMCIO 10 PMCIO 42 11 PMCIO 11 PMCIO 43 12 PMCIO 12 MVME2500 Installation and Use 68068001011 PMCIO 44 65 Controls LEDs and Connectors Table 3 13 PMC 14 Connector continued Signal Description Pin Signal Description Pin 16 PMCIO 16 48 PMC 48 17 PMCIO 17 49 PMC IO 49 18 PMCIO 18 50 PMC IO 50 PMCIO 19 5 PMCIO 51 1 PMCIO 20 52 PMCIO 52 PMCIO 21 53 PMCIO 53 4 PMCIO 22 5 PMCIO 54 PMCIO 23 55 PMCIO 55 PMC IO 24 56 PMC IO 56 PMC IO 25 5 PMC IO 57 19 22 23 24 25 27 28 29 30 31 7 58 PMCIO 27 59 PMCIO 59 0 PMCIO 28 6 PMCIO 60 PMCIO 29 61 PMCIO 61 PMCIO 30 62 PMCIO 62 PMCIO 31 63 PMCIO 63 PMCIO 32 64 PMCIO 64 3 4 2 4 JTAG Connector
96. ore 800 MHz IEEE MVME2500 0161 800 MHz SCANBE MVME2500 0173 MVME2500 0171 MVME2500ET 0173 MVME2500ET 0171 QorlQ P2010 single core QorlQ P2020 QorlQ P2020 dual core QorlQ P2020 dual core QorlQ P2020 dual core 1 2 GHz IEEE SCANBE IEEE ENP2 SCANBE ENP2 dual core 1 GHz 2 MVME2500 Installation and Use 68068001011 33 Introduction As of the printing date of this manual the following board accessories are available Table 1 4 Available Board Accessories VME HDMNTKIT Used on ENP1 board VME HDMNTKIT2 Used on ENP2 board VME 64GBSSDKIT VME 64 GB SSD and mounting kit MVME7216E 101 VME RTM IEEE handle MVME7216E 102 VME RTM SCANBE Handle MVME721ET 101 VME RTM Extended Temperature IEEE handle MVME721ET 102 VME RTM Extended Temperature SCANBE Handle SERIAL MINI D 30 Female to male micro mini DB 9 to DB9 adapter cable W2400E01A ACC CABLE SER DTE 9 pin micro DSUB to 9 pin DSUB cross connected serial 6E console cable 34 MVME2500 Installation and Use 68068001011 eee tee MVME2500 Installation and Use 6806800L01L Introduction Product Identification The following figure shows the location of the serial number label Figure 1 2 Serial Number Location Serial number Tr 35 Introduction eee 36 MVME2500 Installation and Use 68068001011 Chapter 2 Hardware
97. ot 0x00000000 0x0008ffff Reserved 0x00090000 0x0009ffff ENV Variables 0x00100000 0x001 1ffff Available Flash 0x00120000 0x007fffff Linux Devices Memory Map The table below lists the memory ranges designated to different devices in Linux Table 5 3 Linux Devices Memory Map Device Memory Range Memory Area Size Ram Mem 0x00000000 Ox7fffffff PCIE3 Mem 0x80000000 Ox9fffffff PCIE2 Mem 0xa0000000 Oxbfffffff PCIE1 Mem 0xc0000000 Oxdfffffff MRAM Oxfff00000 Oxfff7ffff 512 KB PCIE3 IO Oxffc00000 OxffcOfff 64 KB PCIE2 IO Oxffc10000 Oxffc1ffff 64 KB PCIE1 IO Oxffc20000 Oxffc2ffff 64 KB QUARTO Oxffc40000 OxffcAffff QUART1 Oxffc50000 Oxffc5ffff QUART2 Oxffc60000 Oxffc6ffff 64 KB QUART3 Oxffc70000 Oxffc7ffff 64 Timer Oxffc80000 Oxffc8ffff 64 KB MVME2500 Installation and Use 68068001011 Memory Maps and Registers Table 5 3 Linux Devices Memory Map continued Device Memory Range Memory Area Size FPGA Oxffdf0000 OxffdfOfff ecm local access window CCSR Oxffe00000 OxffeOOffff 4KB ecm Error Correction Module CCSR Oxffe01000 Oxffe01 fff 4 Memory Controller CCSR Oxffe02000 OxffeO2fff I2C1 CCSR Oxffe03000 Oxffe030ff 12C2 CCSR Oxffe03100 Oxffe031 ff UARTO CCSR UART1CCSR ELBC CCSR SPI CCSR Oxffe04500 Oxffe045ff Oxffe04600 Oxffe046ff Oxffe05000 OxffeO5fff Oxffe07000 OxffeO7fff PCIE3 CCSR Oxffe08000 Oxffedsfff PCIE2 CCSR Oxf
98. ove the filler panel s from the appropriate card slot s at the rear of the chassis if the chassis has a rear card cage MVME2500 Installation and Use 68068001011 43 Hardware Preparation and Installation 44 Install the top and bottom edge of the transition module into the rear guides of the chassis Ensure that the levers of the two injector ejectors are in the outward position Slide the transition module into the chassis until resistance is felt Move the injector ejector levers in an inward direction A Verify that the transition module is properly seated and secure it to the chassis using two screws adjacent to the injector ejector levers 9 Connect the cables to the transition module To remove the transition module from the chassis reverse the procedure and press the red locking tabs IEEE handles only to extract the board Removal Procedure 1 Turn off the power 2 Disconnect all the cables 3 Press the red locking tabs IEEE handles only to eject the board 4 Loosen and remove the screws adjacent to the injector ejector levers that securing the module to the chassis Move the injector ejector levers in outward direction 6 Slide the module from the chassis and make sure that no damage is caused to the pins 7 Remove the transition module from the chassis and insert the filler panels MVME2500 Installation and Use 6806800L01L Hardware Preparation and Installati
99. pability Indicator 1 PCI X capable 0 PCI capable MVME2500 Installation and Use 6806800L01L Memory Maps and Registers 5 9 9 PLD U Boot and TSI Monitor Register The MVME2500 PLD provides an 8 bit register which indicates the status of the U Boot s normal environment switch and TSI interface signals Table 5 12 PLD U Boot and TSI Monitor Register EG it R 7 p p p p p T PLD PCI_PMC_XMC_MNTR OXFFDFOOTF 5 5 10 MVME2500 Field Description BDFAIL_N TSI148 BDFAIL_N Pin out 1 TSI Fail 0 TSI Fail NORMAL_ENV Normal Environment Switch Indicator 1 Use safe ENV 0 Use normal ENV SCON System Controller Indicator 1 System Controller 0 Non system Controller PLD Boot Bank Register The MVME2500 PLD provides an 8 bit register which is used to declare successful U Boot loading indicating the SPI boot bank priority and actual SPI bank it booted from Table 5 13 PLD Boot Bank Register REG PLD Boot Bank OXFFDF0050 Installation and Use 6806800L01L 109 Memory Maps and Registers Table 5 13 PLD Boot Bank Register REG PLD Boot Bank OXFFDF0050 SPI_GOODReg BOOT_B BOOT_S write OxA4 into this reg to indicate successful loading of the U Boot R W R R FD Field Description BOOT_BLOCK_A Boot Block Manual Selector Switch 1 SPIO 0 SPI BOOT SPI Actual Boot Bank 1 SP1 0 SPIO 5 5 11 PLD
100. r each have a FIFO of 32 Bytes The P20x0 supports up to four chip selects and RapidS full clock cycle operation It can operate both full duplex and half duplex It works with a range of 4 bit to 16 bit data characters and is a single master environment The MVME2500 is configured such that the eSPI can operate up to 200 MHz clock rate and can support booting process The firmware boot flash resides in the P20x0 eSPI bus interface SPI Flash Memory The MVME2500 has two 8 MB on board serial flash Both contain the ENV variables and the U Boot firmware image which is about 513 KB in size Both SPI flash contain the same programming for firmware redundancy and crisis recovery The SPI flash is programmed through the JTAG interface or through an on board SPI flash programming header For information on U boot and ENV Variables location see Flash Memory Map Table 5 2 on page 102 SPI Flash Programming The MVME2500 has three headers a 10 pin header for SPI Flash programming an 80 pin header for the TAG connectivity and a 20 pin TAG header for ASSET hardware connectivity The following options are used to program the on board flash Using on board SPI header The MVME2500 uses the 10 pin header with a dual SPI Flash in circuit programming configuration The pin connection is compatible with DediProg SPI Universal Pin Header Using 60 pin external JTAG header An external JTAG board with a multiplexer is compatible with the
101. r good indicator PWR VIP2 SW PWRG 1 2V SW Supply power good indicator D PWR 5 PWRGD 1 5V Supply power good indicator 1 Supply Good and Stable 0 Otherwise PLD LED Control Register The MVME2500 PLD provides an 8 bit register which controls the eight LEDs Table 5 10 PLD LED Control Register REG PLD LED CTRL OXFFDFOO1C i 7 6 5 4 3 2 1 0 Bit Field D2 Yellow OPER 1 LED on 0 LED off For more information on LEDs refer to Table Front Panel LEDs on page 52 and Table On board LEDs Status on page 53 MVME2500 Installation and Use 68068001011 107 Memory Maps and Registers 5 5 8 108 PLD PCI PMC XMC Monitor Register The MVME2500 PLD provides an 8 bit register which indicates the status of the PCI PMC XMC interface signals Table 5 11 PLD PCI PMC XMC Monitor Register REG PLD PCI_PMC_XMC_MNTR OxFFDF001D ee ee Field RSVD RSVD RSVD PMC_X PMCI_E PMC1P_ 1 MC SEL READY N N IXCAP OPER R RESET 0 Field Description PMC_XMC_SEL XMC or PMC Selection Switch 1 PMC 0 XMC PMC1_EREADY Indicates that the PrPMC module is installed in PMC site 1 PrPMC is ready for enumeration or no PrPMC is installed 0 PrPMC is not ready for enumeration PMC1P_N PMC Presence Indicator 1 PMCis not present 0 PMC is present XMCP1_N XMC Presence Indicator 1 not present 0 is present PCI1_PCIXCAP PCI Ca
102. re to use the access parameters that are specified in U Boot By default the access parameters are as follows Baud rate 9600 PC ANSI 8 data bits No parity 1 stop bit These serial access parameters are the default values These values can be changed within the U Boot For details refer to the U Boot documentation 3 Boot the MVME2500 4 When prompted press the lt h gt key MVME2500 Installation and Use 68068001011 121 Boot System U Boot aborts the boot sequence and enters into a command line interface mode Enterthe command setenv bootdelay 1 saveenv to disable the U Boot auto boot WM feature and let the U Boot directly enter the command line interface after the next reboot power up 6 3 Boot Options 6 3 1 Booting from a Network In this mode U Boot downloads and boots the Linux kernel from an external TFTP server and mounts a root file system located on a network server 1 Make sure thatthe kernel dtb and ramdisk are accessible to the board from the TFTP server 2 Configure U Boot environment variables setenv ipaddr lt IP address of MVME2500 gt setenv serverip lt IP address of TFTP server gt setenv gatewayip lt gateway IP gt setenv netmask lt netmask gt setenv bootargs root dev ram rw console ttyS0 9600n8 ramdisk_size 700000 cache sram size 0x10000 saveenv 3 Transfer the files through the TFTP from the server to the local memory tftp 1000000 lt kernel_image gt
103. reher zum Ausbau der Batterie verwenden Umweltschutz Entsorgen Sie alte Batterien und oder Blades Systemkomponenten RTMs stets gem der in Ihrem Land g ltigen Gesetzgebung wenn m glich immer umweltfreundlich MVME2500 Installation and Use 68068001011 27 Sicherheitshinweise eee 28 MVME2500 Installation and Use 68068001011 Chapter 1 Introduction 1 1 Overview The MVME2500 is a VME form factor single board computer based on the Freescale QorlQ P2010 single core or P2020 dual core processors A e500 v2 core QorlQ processor uses 45 nanometer technology which delivers an excellent performance to power ratio The MVME2500 is ideal for automation medical and military applications such as railway control semiconductor processing test and measurement image processing and radar sonar The main features of the MVME2502 board are as follows Freescale QorlQ P2010 single core or P2020 dual core 800 MHz Freescale P2010 single core processor 1 2 GHz Freescale P2020 dual core processor 512 L2 shared cache Integrated on chip controllers for DDR2 3 SPI flash 12 security acceleration Express USB2 0 DUART 10 100 1000 Ethernet SDHC Eight 32 bit timers 1 2 GBDDR3 800 soldered down Single channel 800MB s User Flash NVRAM Memory 512 MRAM NVRAM SDHC socket MVME2500 Installation and Use 68068001011 29 Intro
104. rs Each one supports and SGMII interface to the external PHY All controllers can only be utilized when using the interface Using the allows only up to two usable controllers MVME2500 provides two 10 100 1000 Ethernet interfaces on the front panel and another two are routed to the RTM through the backplane connector Due to controller limitations one controller is designed to be routed to the front panel or to the RTM This setting is possible by using a third party gigabit Ethernet LAN switch with a single enable switch such as PERICOM s P13L301D The routing direction can be configured through the on board dip switch Each Ethernet controller has a single dedicated Broadcom 546165 with integrated MAC and PHY The registers of the PHY can be accessed through the processor s two wire Ethernet management interface The front panel RJ45 connector has integrated speed and activity status indicator LEDs Isolation transformers are provided on board for each port MVME2500 Installation and Use 68068001011 83 Functional Description 4 6 4 6 1 4 6 2 84 SPI Bus Interface The enhanced serial peripheral interface eSPI allows the device to exchange data with peripheral devices such as EEPROMs RTC Flash and the like The eSPI is a full duplex synchronous character oriented channel that supports a simple interface such as receive transmit clock and chip selects The eSPI receiver and transmitte
105. s designed to meet the following standards Table 1 1 Board Standard Compliances Standard Description EN 60950 1 A11 2009 Safety Requirements legal IEC 60950 1 2005 2nd Edition CAN CSA C22 2 No 60950 1 FCC Part 15 Subpart B Class A non EMC requirements legal on system level residential predefined Artesyn Embedded Technologies ICES 003 Class A non residential system EMC Directive 89 336 EEC EN55022 Class B EN55024 AS NZS CISPR 22 Class A EN300386 ETSI EN 300 019 series Environmental Requirements Directive 2011 65 EU Directive on the restriction of the use of certain hazardous substances in electrical and electronic equipment RoHS MVME2500 Installation and Use 68068001011 31 Introduction Figure 1 1 1 MVME2500 Declaration of Conformity EC Declaration of Conformity According to EN 17050 1 2004 Manufacturer s Name Artesyn Embedded Technologies Manufacturer s Address Zhongshan General Carton Box Factory Co Ltd No 62 Qi Guan Road West Shiqi District 528400 Zhongshan City Guangdong PRC Declares that the following product in accordance with the requirements of 2004 108 EC 2006 95 EC 2011 65 EU and their amending directives MVME2500 Series Single Board Computers Model Name Number MVME2500 01080101E MVME2500 01080101S MVME2500 0161 MVME2500 0163 MVME2500 0171 MVME2500 0173 MVME2500 02100202E MVME2500 02100202S MVME2500 02120201E MVME2500 02120201S MVME2500
106. sable each supply To restart the system the chassis power switch must be power cycled MVME2500 Installation and Use 68068001011 91 Functional Description 4 15 1 4 15 2 92 On board Voltage Supply Requirement The on board power supply is considered to be out of regulation if the output voltage level is below the minimum required power or goes beyond the maximum Table 4 1 Voltage Supply Requirement Voltage Rail Requirement Voltage Rail Minimum Maximum 1 8V 1 5V 1 2V 1 2 V_SW Power Up Sequencing Requirements The power up sequence describes the voltage rail power up timing which is designed to support all the chip supply voltage sequencing requirement The backplane contains three power supplies 12 V 12 V and 5 V The 12 V is assigned to PMC XMC sites only while the 5 V and below are assigned to different voltage levels to support all the voltage requirements on the board Each voltage rail is controlled by FPGA and sequenced to provide correct voltage sequencing requirements When the 1 5 V is Good it means that all the DCDC power is Good MVME2500 Installation and Use 6806800L01L Functional Description The figure below describes the detailed power up sequence of the board from 5V main source from backplane up to the 1 5 V Power Good Figure 4 3 Power Up Sequence 12 Backplane 12V Backplane 5V Backplane
107. ss 136 Table 7 5 LBC Timing Parameters tess bao Ebr PERRA RE dee 138 Table 7 6 Clock Distribution rer ep E YO rx RECENTE ei De an Rer 139 Table 7 7 System m 140 Table B 1 Artesyn Embedded Technologies Embedded Computing Publications 147 Table B 2 Manufacturers Publications e tence m 148 Table B 3 Related Specifications u ee eines 148 10 MVME2500 Installation and Use 68068001011 List of Figures EN Figure 1 1 MVME2500 Declaration of Conformity 32 Figure 1 2 Serial Number Location m 35 Figure 3 1 COMPONENELAYOUE sa innen 49 Figure 3 2 Front Panel LEDs Connectors and Switches 50 Figure 3 3 Front Panel LEDs ne ae a an 51 Figure 3 4 On board LEDS i355 sa ee been 53 Figure 3 5 Geographical Address Switch 0 cee cece eee eee eee eee eee 72 Figure 3 6 SMT Configuration Switch Position eect ene nee 73 Figure 4 1 Block Diagram ur a 77 Figure 4 2 SPI Device Multiplexing Logic 2222220 een eee eee ence 86 Figure 4 3 Power Up Seguente a bahia REI RR CH NERO PET EE 93 Figure 4 4 Clock Distribution Diagram 94 Figure 4 5 Reset Sequence Hessen ee 96 Figure A 1 BatteryLocation da tie en 143 MVME2500 Installation
108. stened throughout the procedure Remove VME filler panels from the VME enclosures as appropriate Install the top and bottom edge of the board into the guides of the chassis Ensure that the levers of the two injector ejectors are in the outward position Slide the board into the chassis until resistance is felt Simultaneously move the injector ejector levers in an inward direction Verify that the board is properly seated and secure it to the chassis using the two screws located adjacent to the injector ejector levers Connect the appropriate cables to the board Removal Procedure 1 2 3 4 yi Turn off the power Disconnect all the cables Press the red locking tabs IEEE handles only to extract the board Loosen and remove the screws located adjacent to the injector ejector levers that securing board to the chassis Move the injector ejector levers in outward direction Hold top and bottom edges of the board and exert minimal force when pulling the board from the chassis to prevent pin damage Carefully remove the board from the chassis and store the board in anti static envelope MVME2500 Installation and Use 6806800L01L 47 Hardware Preparation and Installation 2 7 48 Completing the Installation The board is designed to operate as an application specific computer blade or an intelligent I O board carrier It can be used in any slot VME chassis Once the board is installed you are ready to conn
109. t Damage of Circuits Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life Before touching the board or electronic components make sure that you are working in an ESD safe environment Shipment Inspection To inspect the shipment perform the following steps 1 Verify that you have received all items of your shipment MVME2500 board Quick Start Guide e Safety Notes Summary Any optional items ordered 2 Check for damage and report any damage or differences to customer service 3 Remove the desiccant bag shipped together with the board and dispose of it according to your country s legislation The product is thoroughly inspected before shipment If any damage occurred during transportation or any items are missing contact customer service immediately MVME2500 Installation and Use 6806800L01L Hardware Preparation and Installation 2 3 2 3 1 MU Requirements Make sure that the board meets the following requirements when operated in your particular system configuration Environmental Requirements Operating temperatures refer to the temperature of the air circulating around the board and notto the component temperature Table 2 1 Environmental Requirements Characteristics Applicable Variants Commercial Versions MVME2500 0163 MVME2500 0161 MVME2500 0173 MVME2500 0171 Extended Temperature Versions MVME2500ET 0173 MVME2500
110. tftp 2000000 lt ramdisk gt tftp C00000 kernel dtb gt 4 Bootthe Linux from the memory bootm 1000000 2000000 c00000 122 MVME2500 Installation and Use 6806800L01L Boot System 6 3 2 6 3 3 Booting from an Optional SATA Drive 1 Make surethatthe kernel dtb ramdisk saved in the SATA drive with ext2 partition Configure U Boot environment variable setenv File_ulmage lt kernel_image gt setenv File_dtb lt kernel dtb gt setenv File_ramdisk lt ramdisk gt saveenv Copy the files from the SATA drive to the memory option scsi interface 0 1 device 0 partition 1 ext2load scsi 0 1 1000000 File_ulmage ext2load scsi 0 1 2000000 File_ramdisk ext2load scsi 0 1 c00000 SFile_dtb Boot the Linux in memory bootm 1000000 2000000 c00000 Booting from a USB Drive 1 Make sure thatthe kernel dtb and ramdisk are saved in the USB drive with FAT partition Configure the U Boot environment variable setenv File ulImage kernel image setenv File dtb kernel dtb gt setenv File ramdisk lt ramdisk gt saveenv Initialize USB drive usb start Load the files from the USB drive to the memory option usb interface 0 1 device 0 partition 1 fatload usb 0 1 1000000 File_ulmage fatload usb 0 1 2000000 File_ramdisk fatload usb 0 1 c00000 File_dtb Bootthe Linux in memory bootm 1000000 2000000 c00000 MVME2500 Installation and Use 68068001011 12
111. tialization of Serial Console Initialization of DDR using SPD parameters in cache Execution relocation to RAM Initialization of PCI POST routine Additional SW routines pm de s U boot terminal visibility ready to load OS image MVME2500 Installation and Use 68068001011 95 Functional Description 96 The figure below describes the reset sequence from the 5 V Power Good to the release of the CPU reset Figure 4 5 Reset Sequence c D 3 3VFROM 5 0V CPLD CPLD is running at this time PAR V3P3 PWRGD 3 3v Power is Good PAR VIP2 SW PWRGD Sw Power is Good PWR VIP5 S3 EN Ff 3 Asserted if 3 3V Power is GOOD PWR VIPS S5 EN i if 3 3V Power is GOOD PAR VIPS PARGD HSV Power is Good 2 FP_PHY_RST_N after 12V Sw oon and stable clock BP_PHY_RST_N Oms after 12V_SW and stable clock SW_RST_N afteri2V SW sooo and stable clock PCIE PERST BR1 N 100ms after 3 3V GOOD and stable clock i PCIE PERST BR3 N 3OOO0000000 100ms after 3 3 goon and stable clock PCIE PERST SATA j 10ms after 1 5 GOOD and stable clock RESET N
112. tion at the PMC site used to mount the SATA adapter card The MVME2500 utilizes the P20x0 x2 link PCI Express interface It is designed such that the same PCI E interface is used for either PMC through Pericom s PI2PCIE2412 It is PCI E Gen2 compliant with four differential channel input and 2 1 MUX switch with single enable The enable pin is controlled by FPGA through on board switch The on board switch 52 4 determines the direction of the PCI E MUX switch The default setting OFF routes the differential lines to the PMC Otherwise it is routed to the XMC connector PMC Add on Card The MVME2500 PMC interface utilizes IDT s TSI384 as the PCie PCI X bridge It can support up to 8 5 Gbps 64 bits x 133 MHz The on board switch 52 5 configures the TSI384 to run on either 100 MHz or 133 MHz with 133 MHz as default The MVME2500 supports multi function PMCs and processor PMCs PrPMCs The PMC site has two IDSELs two REQ GNT pairs and EREADY to support PrPMC as defined by VITA39 XMC Add on Card The x2 links the PCI E Gen 1 and is directly routed to the P15 XM connector through Pericom MUX Switch The on board switch 52 4 should be set to The add on cards are required to operate at 5V or 12V from carrier to XMC The MVME2500 provides 5V to the XMC VPWR Variable Power pins The MVME2500 does not provide 12V to the XMC VPWR pins Voltage tolerances for VPWR and all carrier supplied voltage 3 3 V 1
113. ual role DR USB 2 0 compliant serial interface engine DC power to the front panel USB port is supplied using a USB power switch which provides soft start current limiting over current detection and power enable for port 1 MVME2500 Installation and Use 6806800L01L Functional Description 4 13 4 14 4 15 12 Devices The MVME2500 utilizes one of the two I2C ports provided by the board s processor The I C bus is a two wire serial data SDA and serial clock SCL synchronous multi master bi directional serial bus that allows data exchange between this device and other devices such as VPD SPD EEPROM RTC temperature sensor RTM XMC and IDT clocking The RTM I2C address can be configured by the user and should not contain duplicate addresses to avoid conflict For more information see 2 Bus Device Addressing on page 136 Reset Control FPGA The FPGA provides the following functions Power control and fault detection e Reset sequence and reset management e Status and control registers e Miscellaneous control logic e Watchdog timer e 32 bit Tick Timer Clock generator Switch decoder and LED controller Power Management The MVME2500 backplane is utilized to derive 3 3V 2 5V 1 8V 1 5V 1 2V 1 05V voltage rail Each voltage rail is controlled by the FPGA through an enable pin of the regulator while the output is monitored through power good signal If a voltage rail fails the FPGA will di
114. uch bereit zu stellen Da es sich jedoch um ein komplexes Produkt mit vielfaltigen Einsatzm glichkeiten handelt k nnen wir die Vollst ndigkeit der im Handbuch enthaltenen Informationen nicht garantieren Falls Sie weitere Informationen ben tigen sollten wenden Sie sich bitte an die f r Sie zustandige Gesch ftsstelle von Artesyn Das Produkt wurde entwickelt um die Sicherheitsanforderungen f r SELV Ger te nach der Norm EN 60950 1 f r informationstechnische Einrichtungen zu erf llen Die Verwendung des Produkts in einer anderen Anwendung erfordert eine Sicherheits berpr fung f r diese spezifische Anwendung Einbau Wartung und Betrieb d rfen nur von durch Artesyn ausgebildetem oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgef hrt werden Die in diesem Handbuch enthaltenen Informationen dienen ausschlie lich dazu das Wissen von Fachpersonal zu erg nzen k nnen dieses jedoch nicht ersetzen Halten Sie sich von stromf hrenden Leitungen innerhalb des Produktes fern Entfernen Sie auf keinen Fall Abdeckungen am Produkt Nur werksseitig zugelassenes Wartungspersonal oder anderweitig qualifiziertes Wartungspersonal darf Abdeckungen entfernen um Komponenten zu ersetzen oder andere Anpassungen vorzunehmen Installieren Sie keine Ersatzteile oder f hren Sie keine unerlaubten Ver nderungen am Produkt durch sonst verfallt die Garantie Wenden Sie sich f r Wartung oder Reparatur bitte an die f r Sie zust
115. write the counter at any time Table 5 26 Counter High Word Registers Tick Timer 0 Counter Value High Word OxFFC80208 Tick Timer 1 Counter Value High Word OxFFC80308 REG Tick Timer 2 Counter Value High Word OxFFC80408 Ce a EEE I Field TickTimer Counter Value High Word 16 bits OPER R W RESET 0x0000 Table 5 27 Counter Low Word Registers Tick Timer 0 Counter Value Low Word OxFFC8020A Tick Timer 1 Counter Value Low Word OxFFC8030A REG Tick Timer 2 Counter Value Low Word OxFFC8040A TickTimer Counter Value Low Word 16 bits R W 0x0000 120 MVME2500 Installation and Use 6806800L01L Chapter 6 Boot System eee 6 1 6 2 Overview The MVME2500 uses Das U Boot a boot loader software based on the GNU Public License It boots the blade and is the first software to be executed after the system is powered on Its main functions are Initialize the hardware Pass boot parameters to the Linux kernel Start the Linux kernel Update Linux kernel and U Boot images This section describes U Boot features and procedures that are specific to the MVME2500 For general information on U Boot see http www denx de wiki U Boot WebHome Accessing U Boot 1 Connect the board to a computer with a serial interface connector and terminal emulation software running on it The serial connector of the board is found on the faceplate 2 Configure the terminal softwa
116. ws the location of the board battery Figure 1 Battery Location MVME2500 Installation and Use 6806800L01L 143 Replacing the Battery The battery provides seven years of data retention summing up all periods of actual data use Artesyn therefore assumes that there is usually no need to replace the battery except for example in case of long term spare part handling Board System Damage Incorrect replacement of lithium batteries can result in a hazardous explosion When replacing the on board lithium battery make sure that the new and the old battery are exactly the same battery models ifthe respective battery model is not available contact your local Artesyn sales representative for the availability of alternative officially approved battery models Data Loss Replacing the battery can result in loss of time settings Backup power prevents the loss of data during replacement Quickly replacing the battery may save time settings Data Loss ifthe battery has low or insufficient power the RTC is initialized Replace the battery before seven years of actual battery use have elapsed PCB and Battery Holder Damage Removing the battery with a screw driver may damage the PCB or the battery holder To prevent damage do not use a screw driver to remove the battery from its holder 144 MVME2500 Installation and Use 6806800L01L Replacing the Battery eee LE S s est Rep

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