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1. EQU SFFFFCA 1 HBAR EQU SFFFFC5 1 HRX EQU SFFFFC6 HTX EQU SFFFFC7 HCR bits definition 1 HRIE EQU 0 1 HTIE EQU 1 1 EQU 2 1 HF2 EQU 3 EQU 4 HSR bits definition 1 EQU 0 1 HIDE EQU 1 HCP EQU 2 1 EQU 3 EQU 4 HPCR bits definition I HGEN EQU 0 HABEN EQU 51 HA9EN EQU 52 I HCSEN 53 HRE EQU 4 I EQU 5 EQU 6 1 HOD EQU 8 I HDSP EQU 59 HASP EQU SA 1 HMUX EQU SB 1 HD HS EQU 5 HCSP EQU SD 1 HRP EQU SE 1 HAP EQU SF ost ost ost ost ost ost ost ost ost ost ost ost ost ost ost ost ost ost ost ost ost ost ost ost ost Host Polarity Control Register Host Base Address Register Host Receive Register Host Transmit Register Receive interrupts Enable Transmit Interrupt Enable Command Interrupt Enable Flag 2 Flag 3 Receive Data Full Receive Data Empty Command Pending Flag 0 Flag 1 Port GPIO Enable Address 8 Enable Address 9 Enable Chip Select Enable Request Enable Acknowledge Enable Enable Request Open Drain mode Data Strobe Polarity Address Strobe Polarity lultiplexed bus select Double Single Strobe select Chip Select Polarity Request Polarity
2. DAM5 EQU 9 DMA Address Mode 5 1 D3D EQU 10 DMA Three Dimensional Mode 1 DRS EQU SF800 DMA Request Source Mask DRSO DRS4 1 DCON EQU 16 DMA Continuous Mode DPR EQU 60000 DMA Channel Priority 1 DPRO EQU 17 DMA Channel Priority Level low 1 DPR1 EQU 18 DMA Channel Priority Level high 1 DTI EQU 380000 DMA Transfer Mode Mask DIM2 DTMO 1 DTMO EQU 19 DMA Transfer Mode 0 1 DTM1 EQU 20 DMA Transfer Mode 1 DIM2 EQU 21 DMA Transfer Mode 2 1 DIE EQU 22 DMA Interrupt Enable bit DE EQU 23 DMA Channel Enable bit DMA Status Register 1 DTD EQU 5 Channel Transfer Done Status MASK 1 DTDO EQU 0 DMA Channel Transfer Done Status 0 1 DTD1 EQU 1 DMA Channel Transfer Done Status 1 1 DID2 EQU 2 DMA Channel Transfer Done Status 2 1 DID3 EQU 3 DMA Channel Transfer Done Status 3 1 DIDA EQU 4 DMA Channel Transfer Done Status 4 1 DTD5S EQU 5 DMA Channel Transfer Done Status 5 1 DACT EQU 8 DMA Active State 1 DCH EQU 5 00 DMA Active Channel Mask DCHODCH2 1 DCHO EQU 9 DMA Active Channel 0 1 DCH1 EQU 10 DMA Active Channel 1 1 DCH2 EQU 11 DMA Active Channel 2 B 8 PHASE LOCKED LOOP PLL EQUATES gt EQUATES for Phase Locked Loop PLL Register Addresses Of PLL M PCTL EQU SFFFFFD PLL Control Register PLL Control Register EQU SFFF Multiplication Factor Bits Mask
3. MD MC MB MA 1000 then the Boot ROM is bypassed and tHe DSP56303 will start fetching structions beginning with the 8000 assuming that A an external memory using 31 wait states wD ses will be performed selected default area MOTOROLA DSP56303UM AD A 1 Bootstrap Programs A 2 DSP56303UM AD MOTOROLA Bootstrap Programs BOOTSTRAP CODE FOR DSP56303 Copyright 1995 Motorola Inc Revised June 29 1995 This is the Bootstrap program contained in the ROM This program can load any program RAM segment from an external EPROM from the Host Interface or from the SCI serial interface Bootstrap through the Host Interface External EPROM or SCI DSP56303 192 word Boot P p p p On EE EE EEE ES EEE ET POP EEE ROF POOP Y Y EEE LEE SE ST ESE POPOP OP OROE OFE FOP LEE EES MD MC MB MA 1000 then the Boot ROM is bypassed and the DSP56303 will start fetching instructions beginning with the address 8000 assuming that is used The accesses will be performed using 31 wait states with no address attributes selected default area an external memory of SRAM typ LEVEE EEE EE EE FE EE EEE P OP EI EE OP EEE OE FE POP EEE address MC MB MA 001 then it load
4. 2 18 Enhanced Synchronous Serial Interface 0 5510 2 25 Enhanced Synchronous Serial Interface 1 ESSI1 2 29 Serial Communication Interface 5 2 33 Triple Timer 5 10 2 34 OnCE JTAG 2 35 Memory Space Configuration Bit Settings for the DSP56303 3 5 DSP56303UM AD xxiii Table 3 2 Table 3 3 Table 3 4 Table 3 5 Table 3 6 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 6 1 Table 6 2 Table 6 3 Table 6 4 Table 6 5 Table 6 6 Table 6 7 Table 6 8 Table 6 9 Table 6 10 Table 6 11 Table 6 12 xxiv RAM Configuration Bit Settings for the DSP56303 3 5 Memory Space Configurations for the DSP56303 3 7 RAM Configurations for the 05 56303 3 8 Memory Locations for Program RAM and Instruction Cache 3 8 Memory Locations for Data 3 9 DSP56303 Operating Modes 4 4 Interrupt 5 5 4 10 Interrupt Priority Level 4 12 Interrupt Source Priorities within 4 14 Request 5 4 16 Signal Pin Definitions for Various Operational 5 6 6 HIO8 Data Strobe Signal 6 6 08
5. 8 23 Port Control Register and Port Direction Register Bits Functionality Basti ee ERE mM RU A ET 8 28 Prescaler Source 9 8 Timer Control 9 10 Inverter INV Bit 9 11 EXGBILDOUIUOTTC n uu back OER CREDE RU ESPERE 10 6 GO Bit 10 6 R W Bit Definition _ 10 6 OnCE Register Select Encoding 10 6 Core Status Bits Description 10 9 Memory Breakpoint 0 and 1 Select Table 10 12 Breakpoint 0 Read Write Select Table 10 13 Breakpoint 0 Condition Select Table 10 13 DSP56303UM AD XXV Table 10 9 Table 10 10 Table 10 11 Table 10 12 Table 10 13 Table 10 14 Table 11 1 Table 11 2 Table D 1 Table D 2 Table D 3 xxvi Breakpoint 1 Read Write Select Table 10 13 Breakpoint 1 Condition Select 10 14 Breakpoint 0 and 1 Event Select Table 10 14 TMS Sequencing for DEBUG_REQUEST 10 29 TMS Sequencing for ENABLE ONCE 10 30 TMS Sequencing for Reading Pipeline Registers 10 31 JEACIBSUDGCIOFDS A oi uta Cas eo na ur gare es 11 8 DSP56303 Boundary Scan Register BSR Bit Definitions
6. 6 28 6 6 5 Receive Byte Registers RXH RXM RXL 6 28 6 6 6 Transmit Byte Registers TXH TXM TXL 6 29 6 6 7 Host Side Registers After Reset 6 29 6 6 8 General Purpose 6 30 6 7 SERVICING THE HOST INTERFACE 6 31 6 7 1 08 Host Processor Data Transfer 6 31 6 7 2 FOUN CP a ah weaves a Po ero eed 6 31 6 7 3 Servicing 1 6 33 6 8 08 PROGRAMMING MODEL QUICK REFERENCE 6 34 SECTION 7 ENHANCED SYNCHRONOUS SERIAL INTERFACE ESSI esu uve xe a wee w ups 7 1 7 1 INTRODUCTIONS 55555 atc ec e EY UR Een 7 3 7 2 ENHANCEMENTS 55 7 3 7 3 ESSI DATA AND CONTROL PINS 7 4 7 3 1 Serial Transmit Data Pin 5 0 7 4 7 3 2 Serial Receive Data Pin 5 0 7 4 7 3 3 Serial Clock SGK u ul okt o RE ESSE EA TEES 7 5 7 3 4 Serial Control Pin 5 0 7 6 7 3 5 Serial Control Pin 501 7 7 7 3 6 Serial Control Pin 6 2 7 8 7 4 ESSI PROGRAMMING MODEL 7 8 7 4 1 ESSI Control Register CRA 7 10 7 4 1 1 CRA Prescale Modulus Select PM 7 0 Bits 7 0 7 10 7 4 1 2 CRA Reserved Bits 8 10 7 11 7 4 1 3 CRA Pres
7. S I sju urtuo d L S0TH T 9 lqe L 6 38 SECTION 7 ENHANCED SYNCHRONOUS SERIAL INTERFACE ESSI MOTOROLA DSP56303UM AD 7 1 Enhanced Synchronous Serial Interface ESSI 7 1 7 3 7 4 7 5 7 6 7 2 INTRODUCTION aus en et LR RH te ea 7 3 ESSI DATA AND CONTROL 7 4 ESSI PROGRAMMING MODEL 7 8 OPERATING MODES ete wd ex e er RICE 7 36 GPIO PINS AND REGISTERS 7 44 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI Introduction 7 1 INTRODUCTION The Enhanced Synchronous Serial Interface ESSI provides a full duplex serial port for serial communication with a variety of serial devices including one or more industry standard codecs other DSPs microprocessors and peripherals that implement the Motorola Serial Peripheral Interface SPI The ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator There are two independent and identical Enhanced Synchronous Serial Interfaces in the DSP56303 ESSIO and ESSI1 For the sake of simplicity a single generic ESSI is described The ESSI block diagram is shown in Figure 7 1 This interface is synchronous because all serial transfers are synchronized to
8. num cell port func safe ccell dis rslt 0 BC_1 MODA input amp 1 BC 1 MODB input 5 12 BC_1 MODC input X amp 3 BC 1 MODD input 5 4 BC_6 D 23 bidir X 13 Z amp 5 BC 6 D 22 bidir X 13 2 amp 6 BC 6 D 21 bidir X 13 2 amp BC_6 D 20 bidir X 13 2 amp 8 BC_6 D 19 bidir X 13 2 amp BC_6 D 18 bidir X 13 2 amp TEO BC_6 D 17 bidir X 13 2 amp 11 BC_6 D 16 bidir X 13 2 amp 2 BC 6 D 15 bidir X 13 Z 2 amp BC T control 1 amp 14 BC_6 D 14 bidir X 13 Zu 5 BC 6 D 13 bidir X 13 2 amp 16 BC_6 D 12 bidir X 26 7 2 amp 6 DSP56303UM AD MOTOROLA 7 18 19 num 20 21 22 23 24 25 26 27 28 29 30 tai 152 33 34 35 36 37 38 39 Bam am 0 amp Q NN n O Cn 51 152 153 54 55 56 od 158 159 num 60 61 62 63 64 65 66 40404 N d ao 2 4 PrP gt Ww 2 wa 9 H n A 8 A 7 A 6 ccel DSP56303 BSDL Listing 1 2 amp 1 2 amp Ly 2
9. 1soH r a MS I MH Sow d L yasay penunuo BOTH 1 9 214 6 35 DSP56303UM AD MOTOROLA Host Interface HI08 08 Programming Model Quick Reference 0000 2q OldD 0q 9ra 0 91 s rx eyeq 1 dsa 0 2 ws RP uU SI f 4 G J sc e Q III r vr OT JeisiBou 5 0 62 Waru SSE EEE eee eee JeisiBou 08 SseJppy eseg 150 eva Olvad 0 2 gt _ lt 0 150H r 0 0 1s0H 03H Buipued 1504 Bulpued 010 0 Buipued 1509 ou 0 1S0H dwa jou si ejeq eu 0 L L si geq eu 15 L IIN S L 0 0 0 peal ou 0 150 0 YSH 0 N3H MOVH L uelod 0 4 pesoubl 5141 50 dVH SL 0 N3H uiu OHHH OHLH O3HH
10. MODB IROB Input Input Input Input Mode Select A External Interrupt Request A is an active low Schmitt trigger input internally synchronized to CLKOUT selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing MODA MODB MODC and MODD select one of sixteen initial chip operating modes latched into the OMR when the RESET signal is deasserted If IRQA is asserted synchronous to CLKOUT multiple processors can be re synchronized using the WAIT instruction and asserting to exit the Wait state If the processor is in Stop standby state and is asserted the processor will exit the Stop state can tolerate 5 V Mode Select B External Interrupt Request B MODB IROB is an active low Schmitt trigger input internally synchronized to CLKOUT MODB IRQB selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing MODA MODB MODC and MODD select one of sixteen initial chip operating modes latched into OMR when the RESET signal is deasserted If IROB is asserted synchronous to CLKOUT multiple processors can be re synchronized using the WAIT instruction
11. 9 25 mode 9 watchdog pulse 9 25 mode 10 measurement toggle 9 26 modes 11 15 reserved 9 27 Timer module 1 17 2 34 architecture 9 3 programming model 9 5 timer block diagram 9 4 Timer Overflow Flag bit TOF 9 14 Timer Overflow Interrupt Enable bit 9 9 Timer Prescaler Count Register TPCR 9 8 Timer Prescaler Load Register TPLR 9 7 Timer Reload Mode bit TRM 9 13 Timers 2 3 TLIE bit 7 26 TLR register 9 15 TME bit 10 8 TMIE bit 8 12 TMS pin 11 5 TMS signal 2 36 TO bit 10 9 TOF bit 9 14 TOIE bit 9 9 TPCR register 9 8 bits 0 20 Prescaler Counter Value bits 20 9 9 bit 21 23 reserved bits 9 9 reserved bits bits 21 23 9 9 TPLR register 9 7 bits 0 20 Prescaler Load Value bits PLO PL20 9 7 bits 21 22 Prescaler Source bits PLO PL20 9 7 bit 23 reserved bit 9 8 reserved bit bit 23 9 8 Trace buffer 10 21 Trace mode l 13 enabling 10 18 in OnCE module 10 15 Trace Mode Enable bit TME 10 8 Trace Occurrence bit TO 10 9 transfer acknowledge signal 2 11 Transmit 0 Enable bit 7 24 Transmit 1 Enable bit TE1 7 23 Transmit 2 Enable bit TE2 7 22 Transmit Byte Registers TXL 6 29 Transmit Clock Source bit TCM 8 18 Transmit Data Register Empty bit TDE 7 29 Transmit Data Register Empty bit TDRE 8 13 Transmit Data Register Empty bit TXDE 6 26 Transmit Data signal TXD 8 4 Transmit Exception Interrupt Enable bit TEIE 7 27 Transmit Frame S
12. 11 7 JTAG ID Register u de ete ect org 11 9 Bypass Register wate we Ou auqa iu 11 12 Status Register 5 D 15 Operating Mode Register D 16 Interrupt Priority Register Core D 17 Interrupt Priority Register Peripherals IPR P D 18 Phase Lock Loop Control Register PCTL D 19 Host Receive and Host Transmit Data Registers D 20 Host Control and Host Status Registers D 21 Host Base Address and Host Port Control Registers D 22 Interrupt Control and Interrupt Status Registers D 23 Interrupt Vector and Command Vector Registers D 24 Host Receive and Host Transmit Data Registers D 25 ESSI Control Register A D 26 ESSI Control Register D 27 ESSI Status Register 55 5 D 28 ESSR Transmit and Receive Slot Mask Registers TSM RSM D 29 SCI Control Register D 30 SCI Status and Clock Control Registers SSR SCCR D 31 SCI Receive and Transmit Data Registers SRX TRX D 32 Timer Prescaler Load Count Register TPLR TPCR D 33 DSP56303UM AD xxi Figure D 20 Figure D 21 Figure D 22 Figure D 23 Figure D 24 Figure D 25 xxii Timer Control Statu
13. used as input When Timer 2 functions in Watchdog Timer or Pulse Modulation mode TIO2 is used as output The default mode after reset is GPIO input This can be changed to output or configured as a Timer Input Output through the Timer 2 Control Status Register TCSR2 This input is 5 V tolerant Note The Wait processing state does not affect the signal s state 213 OnCE JTAG INTERFACE Table 2 16 OnCE JTAG Interface Signal 5 During Signal Description Name Reset TCK Input Input Test Clock TCK is a test clock input signal used to synchronize the JTAG test logic This input is 5 V tolerant TDI Input Input Test Data Input TDI is a test data serial input signal used for test instructions and data TDI is sampled on the rising edge of TCK and has an internal pull up resistor This input is 5 V tolerant MOTOROLA DSP56303UM AD 2 35 Signal Connection Descriptions OnCE JTAG Interface Table 2 16 OnCE JTAG Interface Continued Signal State 5 During Signal Description Name Reset TDO Output Tri stated Test Data Output TDO is a test data serial output signal used for test instructions and data TDO is tri statable and is actively driven in the shift IR and shift DR controller states TDO changes on the falling edge of TCK TMS Input Input Test Mode Select TMS is an input signal used to sequence the test controller s state ma
14. TAGOW SNIWINVHDOHd 89 DSP56303UM AD 6 34 Host Interface HI08 08 Programming Model Quick Reference 0 eieq eiqnog L pe1oui si 4q 5141 2 0 enq 150 0 eyep sseippe sng JI pasou s 19 Sty L sseJppe ejejedes 0 XNWH LL 0 N3H uejoq eqoas pe1oui si 4q 5141 0 SseJppy 1soH dSVH 01 0 pe1oui si 4q 5141 HMH QHH SQH 0 150 6 0 N3H OHHH OHLH OdHH L s 5141 OHHH OH LH O3HH 0 1soH 8 ISOH 01849 HOd 0 jqeu4 150 9 OHHH OHHH MOVH OH LH O3HH MOVH OHHH MOVH 07 0 S 10 SIU L 0189 OHHHPOVH 0 N3HH J 0 OHLH O3HH Old9 OHHH MOVH 0 S 10 SIUL OUCH L OYCH lqeu3 JI s 19 Sty L 0 Bp lwouyov N3VH S DH1H OHHH MOVH OH LH O3HH O3HH OHLH O3HH 0189 OYYH MOVH OH LH O3HH Old9 OHLH O3HH 0 lqeua 0
15. In this mode the timer generates an internal interrupt when a counter value is reached if the timer compare interrupt is enabled Set the TE bit to clear the counter and enable the timer Load the value the timer is to count into the TCPR The counter is loaded with the TLR value when the first timer clock signal is received The timer clock can be taken from either the DSP56303 clock divided by two CLK 2 or from the prescaler clock output Each subsequent clock signal increments the counter When the counter equals the TCPR value the TCF bit in TCSR is set and a compare interrupt is generated if the TCIE bit is set If the TRM bit in the TCSR is set the counter is reloaded with the TLR value at the next timer clock and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each timer clock signal This process is repeated until the timer is disabled i e TE is cleared If the counter overflows the TOF bit is set and if TOIE is set an overflow interrupt is generated MOTOROLA DSP56303UM AD 9 17 Triple Timer Module Timer Modes of Operation The counter contents can be read at any time by reading the TCR 9 4 1 2 Timer Pulse Mode 1 Bit Settings Mode Characteristics TC3 TC2 TCO TIO Clock KIND NAME 0 0 0 1 Output Internal 1 Timer Pulse In this mode the timer generates an external pulse on its TIO pin when the timer count
16. Bit Mnemonic Bit Number HW SW IR ST Reset Reset Reset Reset TRNE 0 1 1 1 1 TCM 15 0 0 RCM 14 0 0 SCCR SCP 13 0 0 COD 12 0 0 CD 11 0 11 0 0 0 SRX SRX 23 0 23 16 15 8 7 0 STX STX 23 0 23 0 SRSH SRS 8 0 8 0 STSH STS 8 0 8 0 Note SRSH SCI Receive Shift Register STSH SCI Transmit Shift Register Note HW Hardware reset is caused by asserting the external RESET pin Note SW Software reset is caused by executing the RESET instruction Note IR Individual reset is caused by clearing PCRE bits 0 2 configured for GPIO Note ST Stop reset is caused by executing the STOP instruction Note 1 The bit is set during this reset Note 0 bit is cleared during this reset Note The bit is not changed during this reset 8 4 2 SCI Initialization The correct way to initialize the SCT is as follows 1 Hardware or software reset 2 Program SCI control registers 3 Configure at least one SCI pin as not GPIO 8 24 DSP56303UM AD MOTOROLA Serial Communication Interface SCI Operating Modes If interrupts are to be used the pins must be selected and interrupts must be enabled and unmasked before the SCI can operate The order does not matter any one of these three requirements for interrupts can be used to enable the SCI Synchronous applications usually require exact frequencies which require that the
17. ESSI Transmit Transmit High Byte Transmit Middle Byte Transmit Low Byte Shift Register 7 0 7 07 0 LSB MSB 8 bit Data lt 0 0 0 Least Significant Zero Fill LSB MSE 12 bit Data LSB 16 bit Data LSB 24 bit Data b Transmit Registers NOTES Data is transmitted MSB first if SHFD 0 4 bit fractional format ALC 0 32 bit mode i t shown it mode is not s AROGHG Figure 7 16 ESSI Data Path Programming Model SHFD 0 MOTOROLA DSP56303UM AD 7 31 Enhanced Synchronous Serial Interface ESSI ESSI Programming Model 23 16 15 87 0 3 ESSI Receive Data Register Receive High Byte Receive Middle Byte Receive Low Byte Read Only 0 23 16 15 07 0 SRD Receive High Byte Receive Middle Byte Receive Low Byte ESSI Receive y gt VU Shift Register 7 0 7 07 0 MSB LSB 8 bit Data 0 0 0 Least Significant Zero Fill MSB LSB 12 bit Data LSB 16 bit Data LSB 24 bit Data 3 5 Receive Registers Data is received MSB first if SHFD 0 24 bit fractional format ALC 0 32 bit mode is not shown 23 16 15 87 0 ESSI Transmit Data Transmit High Byte Transmit Middle Byte Transmit Low Byte Register Write Only ESSI Transmit Shift Register 24 Bit MSB LSB 8 bit Data 0 0 0 WL1 WLO LSB Least Significant 12 bit Data Zero Fill LSB 16 bit Data LSB 24 bit Data NOTES b Transmit Registers Data is receive
18. 7 20 CRB MOD Bit Operation 7 21 Normal Mode External Frame Sync 8 Bit 1 Word in Frame 7 22 Network Mode External Frame Sync 8 Bit 2 Words in Frame 7 23 ESSI Data Path Programming Model SHFD 0 7 31 ESSI Data Path Programming Model 1 7 32 Port Control Register PCR PCRC X FFFFBF PCRDX FFFFAF 7 44 Port Direction Register PRR PRRC X FFFFBE PRRD X FFFFAE 7 45 Port Data Register PDR X FFFFBD PDRD X FFFFAD 7 46 SCI Control Register SCR 8 5 SCI Status Register SSR 8 5 SCI Clock Control Register SCCR 8 5 SCI Data Word Formats 8 6 16X Seral Glock es ese Ose 8 16 DSP56303UM AD xix Figure 8 6 Figure 8 7 Figure 8 8 Figure 8 9 Figure 8 10 Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Figure 9 5 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 Figure 10 5 Figure 10 6 Figure 10 7 Figure 10 8 Figure 10 9 Figure 10 10 Figure 11 1 Figure 11 2 XX SCI Baud Rate Generator 8 18 SCI Programming Model Data 8 19 Port Control Register 8 27 Port E Direction Register PRRE 8 28 Port E D
19. 5 Input Output Data 65 BC_1 HAD6 Control 66 BC_6 HAD6 Input Output Data 67 BC_1 HAD7 Control 68 BC 6 HAD7 Input Output Data 69 BC 1 HAS A0 m Control 70 BC 6 5 0 Input Output Data 71 BC_1 HA8 A1 Control 72 BC 6 HA8 A1 Input Output Data 73 BC_1 HA9 A2 Control 74 _6 HA9 A2 Input Output Data 75 BC_1 HCS A10 Control 76 BC_6 HCS A10 Input Output Data 77 BC_1 TIOO Control 78 BC_6 TIOO Input Output Data 79 BC_1 TIO1 Control 80 BC 6 Input Output Data 81 BC_1 TIO2 Control 82 BC_6 TIO2 Input Output Data 83 BC_1 Control 84 BC 6 HREQ TRO Input Output Data 85 BC 1 Control 86 BC 6 HACK RRO Input Output Data 87 BC 1 HRW RD Control DSP56303UM AD MOTOROLA JTAG Port DSP56303 Boundary Scan Register Table 11 2 DSP56303 Boundary Scan Register BSR Bit Definitions Continued Bit Cell Type Pin Name Pin Type BSR Cell Type 88 BC_6 HRW RD Input Output Data 89 BC_1 HDS WR Control 90 BC_6 HDS WR Input Output Data 91 BC_1 SCKO Control 92 _6 SCKO Input Output Data 93 BC_1 SCK1 Control 94 _6 SCK1 Input Output Data 95 BC_1 GPIO2 Control 96 BC 6 GPIO2 Input Output Data 97 BC 1 GPIO1 Control 98 BC 6 GPIO1 Input Output Data 99 BC_1 GPIOO Control 100 BC 6 GPIOO Input Output Data 101 BC_1 5 00 Control 102 BC_6 5 00 Input Output Dat
20. TSMB Two receive slot mask registers RSMB One special purpose time slot register TSR The following paragraphs give detailed descriptions and operations of each of the bits in the ESSI registers The GPIO functionality of the ESSI is described in Section 7 6 of this manual 11 10 9 8 7 6 5 4 3 2 1 0 PSR PW PMe PM5 PM PM PMO 23 22 21 20 19 18 17 16 15 14 13 12 5501 2 wit wo c pc4 pcs pco 0857 Figure 7 2 ESSI Control Register A CRA ESSIO X FFFFB5 ESSI1 X FFFFA5 11 10 9 8 7 6 5 4 3 2 1 0 CKP FSP FSR FSL1 FSLO SHFD SCKD SCD2 SCD1 SCDO 1 OFO 23 22 21 20 19 18 17 16 15 14 13 12 REIE TEIE RLIE TLIE RIE TIE RE 1 2 MOD SYN AA0858 Figure 7 3 ESSI Control Register CRB ESSIO X FFFFB6 55 X FFFFA6 11 10 9 8 7 6 5 4 3 2 1 0 RDF TDE 5 TFS IF1 IFO 23 22 21 20 19 18 17 16 15 14 13 12 PE 0859 Figure 7 4 ESSI Status Register 5515 25510 X FFFFB7 ESSI1 X FFFFA7 11 10 9 8 7 6 5 4 3 2 1 0 759 8 757 tse 755 184 rss 182 750 23 22 21 20 19 18 17 16 15 14 13 12 515 TS14 513 TS12 0860 Figure 7 5 ESSI Transmit Slot Mask Register E
21. Test Access Port TAP and On Chip Emulation OnCE module Memory In addition the DSP56303 provides a set of on chip peripherals described in Section 1 8 1 6 1 Data ALU The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core The components of the Data ALU are as follows Fully pipelined 24 x 24 bit parallel Multiplier Accumulator MAC Bit Field Unit comprising 56 bit parallel barrel shifter fast shift and normalization bit stream generation and parsing Conditional ALU instructions 24 bit or 16 bit arithmetic support under software control Four 24 bit input general purpose registers X1 X0 Y1 and YO e Six Data ALU registers A2 A1 0 B2 B1 and that are concatenated into two general purpose 56 bit accumulators A and B accumulator shifters e Two data bus shifter limiter circuits 1 6 1 1 Data ALU Registers The Data ALU registers can be read or written over the X Data Bus XDB and the Y Data Bus YDB as 16 or 32 bit operands The source operands for the Data ALU which can be 16 32 or 40 bits always originate from Data ALU registers The results of all Data ALU operations are stored in an accumulator 1 8 DSP56303UM AD MOTOROLA DSP56303 Overview DSP56300 Core Functional Blocks All the Data ALU operations are performed in two clock cycles in pipeline fashion so that a new instruction can be initiated in every clock yielding an
22. 5 5 4 5 2 4 Port E Pins and Registers 5 4 5 2 5 Triple Timer 5 4 SECTION 6 HOST INTERFACE HI08 6 1 6 1 INTRODUCTION 25 2 tono E e ERREUR 6 3 6 2 HOS FEATURES sh oss oo eae ut 6 3 6 2 1 Host to DSP Core 6 3 6 2 2 HIO8 to Host Processor Interface 6 4 6 3 HIOS HOST PORT SIGNALS 6 6 6 4 08 BLOCK DIAGRAM 6 7 6 5 08 SIDE PROGRAMMER S MODEL 6 8 6 5 1 Host Receive Data Register HRX 6 9 6 5 2 Host Transmit Data Register HTX 6 9 6 5 3 Host Control Register 6 9 6 5 3 1 HCR Host Receive Interrupt Enable HRIE Bit O 6 10 6 5 3 2 HCR Host Transmit Interrupt Enable HTIE Bit 1 6 10 6 5 3 3 HCR Host Command Interrupt Enable Bit 2 6 10 6 5 3 4 HCR Host Flags 2 3 HF 3 2 Bits 3 4 6 10 6 5 3 5 HCR Reserved Bits 5 15 6 10 6 5 4 Host Status Register 6 11 6 5 4 1 Host Receive Data Full HRDF 6 11 6 5 4 2 Host Transmit Data Empty HTDE Bit 1 6 11 6 5 4 3 Host Command Pending HCP Bit 2 6 11 6 5 4 4 HSR Host Flags 0 1 HF 1 0 Bits 3 4 6 11 6 5 4 5 Reserved Bits 5
23. MOTOROLA DSP56303UM AD Motorola s High Performance DSP Technology SEP This document and other documents can be viewed on the World Wide Web at http www motorola dsp com This manual is one of a set of three documents You need the following manuals to have complete product information Family Manual User s Manual and Technical Data is a trademark of Motorola Inc MOTOROLA INC 1996 Order this document by DSP56303UM AD Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its product or products for the use intended Motorola and 4 are registered trademarks of Motorola Inc Motorola Inc is an Equal Employment Opportunity Affirmative Action Employer TABLE OF CONTENTS SECTION 1 DSP56303 OVERVIEW 1 1 1 1 INTRODUCTION 224i rtr prr deter EUER DER 1 3 1 2 MANUAL ORGANIZA
24. Ne s UC Oe FX FU FU DU DU FU _ 0 to 7 poe eee eee eee P E p p P D g E E Fee GER QE cu Ne x sx Ct _vector 0 to 23 _vector 0 to 17 ct ss d vector 0 to 3 CT VF owT CT h ct c ct rh x s Ct ct cF ct MOTOROLA DSP56303UM AD C 3 DSP56303 8501 Listing C 4 TDO out bit TDI in bit bit linkage linkage linkage kage kage kage kage kage kage kage kage kage kage ND Linkage HACK inow HDS inow HRW inow CVCC linkage CGND linkage HCS inow HA9 inou HA8 inou HAS inou it vector 0 it vector 0 it vector 0 0 0 it vector it vector _ Vector _ Vector O 8 5 LJ C OQ EN D amp _ Vector 5 j Gt ete eh sek ete aa SE nk ct ct ct it vector 0 it vector 0 LU LU it poe eee eee eee eee ct ct ct cf use S
25. The INV bit does not affect the polarity of the prescaler source when the TIO is used as input to the prescaler 9 3 4 6 Timer Reload Mode TRM Bit 9 The Timer Reload Mode TRM bit controls the counter preload operation In Timer 0 3 and Watchdog 9 10 modes the counter is preloaded with the TLR value after the TE bit is set and the first internal or external clock signal is received If the TRM bit is set the counter is reloaded each time after it reaches the value contained by the TCR In PWM mode 7 the counter is reloaded each time counter overflow occurs In Measurement 4 5 modes if the and the TE bits are set the counter is preloaded with the TLR value on each appropriate edge of the input signal If the TRM bit is cleared the counter operates as free running counter and is incremented on each incoming event The TRM bit is cleared by a hardware RESET signal or a software RESET instruction 9 3 4 7 Direction DIR Bit 11 The Direction DIR bit determines the behavior of the TIO pin when it is used as a GPIO pin When the DIR bit is set the TIO pin is an output when the DIR bit is cleared the TIO pin is an input The TIO pin can be used as a GPIO pin only when the TC 3 0 bits are all cleared If any of the TC 3 0 bits are set then the GPIO function is disabled and the DIR bit has no effect The DIR bit is cleared by a hardware RESET signal or a software RESET instruction 9 3 4 8 Data Input DI Bit 12
26. the reset operating state written as Reset and the reset function written as reset 14 DSP56303 FEATURES The DSP56303 is a member of the DSP56300 family of programmable CMOS DSPs The DSP56303 uses the DSP56300 core a high performance single clock cycle per instruction engine providing up to twice the performance of Motorola s popular DSP56000 core family while retaining code compatibility The DSP56300 core family offers a new level of performance in speed and power provided by its rich instruction set and low power dissipation enabling a new generation of wireless telecommunications and multimedia products The DSP56300 core is composed of the Data Arithmetic Logic Unit Data ALU Address Generation Unit AGU Program Controller PC Instruction Cache Controller Bus Interface Unit Direct Memory Access DMA controller On Chip Emulation OnCE module and a Phase Lock Loop PLL based clock oscillator Significant architectural enhancements to the DSP56300 core family include a barrel shifter 24 bit addressing an instruction cache and DMA The DSP56300 core family members contain the DSP56300 core and additional modules The modules are chosen from a library of standard pre designed elements such as memories and peripherals New modules may be added to the library to meet customer specifications A standard interface between the DSP56300 core and 1 6 DSP56303UM AD MOTOROLA DSP56303 Overview DSP56303 Core Descrip
27. 1 16 1 10 4 Serial Communications Interface 5 1 16 1 10 5 Timer Module SORE SSE 1 17 MOTOROLA DSP56303UM AD i SECTION 2 SIGNAL CONNECTION DESCRIPTIONS 2 1 2 1 SIGNAL GROUPINGS 2 3 2 2 POWER Seca Sb TV D 2 5 2 3 GROUND tore xc ak A 2 6 2 4 Sth oe oe Mt artes Geers 2 7 2 5 PHASE LOCK LOOP PLL 2 7 2 6 EXTERNAL MEMORY EXPANSION PORT PORT A 2 8 2 6 1 External Address 2 9 2 6 2 External Data BUS 2 9 2 6 3 External Bus Control 2 10 2 7 INTERRUPT AND MODE CONTROL 2 14 2 8 HOST INTERFACE HI08 2 16 2 8 1 Host Port Usage Considerations 2 17 2 8 2 Host Port Configuration 2 17 2 9 ENHANCED SYNCHRONOUS SERIAL INTERFACE 0 a oN eaten equ o tues tiq au A 2 24 2 10 ENHANCED SYNCHRONOUS SERIAL INTERFACE 1 551 Dh OR 2 29 2 11 SERIAL COMMUNICATION INTERFACE SCl 2 32 2 12 HMERS ea ie Ge ae dE a 2 34 2 13 ONCE JTAG INTERFACE 2 35 SECTION MEMORY CONFIGURATION 3 1 3 1 MEMORY SPACES EXE e Ye ne ets 3 3 3 1 1 Progr
28. 11 M_DE EQU 7000 Division Factor Bits Mask DFO DF2 M XTLR EQU 15 XTAL Range select bit M XTLD EQU 16 XTAL Disable Bit B 12 DSP56303UM AD MOTOROLA Equates M_PSTP EQU 17 STOP Processing State Bit M PEN EQU 18 PLL Enable Bit M_PCOD EQU 19 PLL Clock Output Disable Bit M PD EQU F00000 PreDivider Factor Bits Mask PDO PD3 EQUATES for BIU Register Addresses Of BIU 1 BCR EQU SFFFFFB Bus Control Register 1 DCR EQU SFFFFFA DRAM Control Register AARO EQU SFFFFF9 Address Attribute Register 0 AAR1 EQU SFFFFF8 Address Attribute Register 1 AAR2 EQU SFFFFF7 Address Attribute Register 2 AAR3 EQU SFFFFF6 Address Attribute Register 3 IDR EQU SFFFFF5 ID Register Bus Control Register I BAOW EQU Area 0 Wait Control Mask BAOWO BAOWA 1 EQU 5 Area 1 Wait Control Mask BA1WO BA14 BA2W EQU 51 00 Area 2 Wait Control Mask BA2WO BA2W2 BA3W EQU 5 000 Area 3 Wait Control Mask BFW EQU 1F0000 Default Area Wait Control Mask BDFWO BDFW4 1 BBS EQU 21 Bus State BLH EQU 22 Bus Lock Hold 1 EQU 23 Bus Request Hold DRAM Control Register 1 EQU 3 In Page Wait States Bits Mask BCWO BCW1
29. BRW EQU SC Out Of Page Wait States Bits Mask BRWO BRWI 1 BPS EQU 300 DRAM Page Size Bits Mask 50 51 BPLE EQU 14 1 BME EQU 12 Mastership Enable 1 BRE EQU 13 Refresh Enable I BSTR EQU 14 Software Triggered Refresh BRF EQU S7F8000 Refresh Rate Bits Mask BRFO BRF7 1 EQU 23 Refresh prescaler Address Attribute Registers M_BAT EQU 3 External Access Type and Pin Definition Bits MOTOROLA DSP56303UM AD B 13 Equates I BAAP EQU 2 BPEN EQU 3 I EQU 4 i BYEN EQU 5 1 BAI EQU 6 1 BPAC EQU E 1 BNC EQU SFOO BAC EQU SEFF000 control and status bits in EQU c00000 CA EQU 0 V EQU 1 12 EQU 2 4 EQU 3 10 EQU 4 H EQU 5 ITL EQU 6 19 EQU 7 H IO EQU 8 1 1 EQU 9 150 EQU 10 181 EQU 11 SC EQU 13 LD EQU 14 ir EQU 15 FV EQU 16 SA EQU 17 19 DS EQU 20 RI EQU 21 CPO EQU 22 CP1 EQU 23 control and status bits in 1 CDP EQU 300 EQUO 1 EQU1 MC EQU2 1 MD EQU3 EBD EQU 4 SD EQU 6 1 MS EQU 7 1 CDPO EQU 8 1 CDP1 EQU 9 1 BEN EQU 10 TAS EQU 14 1 BRT EQU 12 ATE EQU 15 IXYS EQU 16 B 14 Scaling Sixteen Bit Compatibility Double Precision DO L
30. 2048 x 24 bit enabled disabled 3072 x 24 bit 1024 x 24 bit 2048 x24 bit 2048 x 24 bit disabled enabled 2048 x 24 bit 0 3072 x 24 bit 3072 x 24 bit enabled enabled 1024x 24 bit 1024 x 24 bit 3072x24 bit 3072 x 24 bit There is an on chip 192 x 24 bit bootstrap ROM 1 12 DSP56303UM AD MOTOROLA DSP56303 Overview Internal Buses 1 6 7 Off Chip Memory Expansion Memory can be expanded off chip to Data memory expansion to two 16 M x 24 bit word memory spaces in 24 bit Address mode 64 K in 16 bit Address mode Program memory expansion to one 16 M x 24 bit word memory space in 24 bit Address mode 64 K in 16 bit Address mode Further features of off chip memory include e External memory expansion port e Simultaneous glueless interface to Static Random Access Memory SRAM and Dynamic Random Access Memory DRAM 1 7 INTERNAL BUSES To provide data exchange between these blocks the following buses are implemented Peripheral I O Expansion Bus PIO_EB to peripherals Program Memory Expansion Bus PM EB to Program ROM XMemory Expansion Bus XM EB to X Memory Y Memory Expansion YM_EB to Y Memory Global Data Bus GDB between Program Control Unit and other core structures e Program Data PDB for carrying program data throughout the core XMemory Data Bus XDB for carrying X data throughout the core Y Memory Data Bus YDB for carrying Y data throughout the c
31. 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Si 82 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 num 101 102 103 104 105 106 107 108 109 110 IEL 112 113 114 115 116 117 C 8 BC 1 BC BC 1 BC 1 BC 1 BC 1 BC 6 BC_6 BG al BC_6 12 11 6 BCl BC_6 BC 6 BC BC 6 BC 1 BC 6 BC T1 BC 6 BC 1 BC 6 BC 1 BC 6 BC 1 BC 6 BC 1 BC 6 1 11 BC_6 BC 1 BC 6 EC 1 BC_6 UJ Q a UJ UJ UJ e Oo np No UJ UJ UJ UJ UJ UJ UU UJ e e e e e e e e UJ a BC 1 1 control 1 amp input X amp output3 X 65 output3 X 66 output3 X 67 input 6 control 1 amp bidir X 13 control 1 amp bidir X 75 control 1 amp bidir X TH control func safe ccel bidir X 79 control 1 bidir X 81 control 1 amp bidir X 83 control 1 amp bidir X 85 control 1 amp bidir X 87 control 1 amp bidir X 89 control 1 amp bidir X 91 control 1 amp bidir X 93 control 1 amp bidir X 95 control 1 amp bidir X 97 control 1 amp func safe ccel bidir X 99 control 1 amp bidir X 101
32. Ayrejod 0 s 19 Sty L OHHH OHLH O3HH 0 senbey 1soH 0 L Aelod SS 0 JI s 19 Stu L S H 0 1 ejeg diu 150 dS OH L HOdH LH MS S I Sow d L S0TH T 9 lqe L DSP56303UM AD 6 36 Host Interface HI08 08 Programming Model Quick Reference O3YY 0 Aq pue 01 syed L ezienu LINI 4 ueipu3 Dig L Big 150 0 ueipu3 0 ISOH S 0 150 L3H v 0 0 1soH 04H OHLH OHLH O3HH L MOVH 1senbeu 0 JHH OHLH O3HH 0 1S0H 2 OH LH L lqeu3 0 1dnu lu OH LH 0 1senbeg L pejqeue 1dnu lu OHHH L lqeu3 0 1dnu lu OHHH 0 0 1915 LSOH indino 0000 0 0 91 LH MS uorpung S I sju urtuo d L
33. DMA5 FFDB Source Address Register DSR5 FFDA FFFFDA Destination Address Register DDR5 FFD9 FFFFD9 DMA Counter 5 FFD8 FFFFD8 Control Register DCR5 MOTOROLA DSP56303UM AD D 5 PROGRAMMING REFERENCE Table D 1 Internal I O Memory Map Continued Peripheral de 52 Register FFD7 FFFFD7 Reserved FFD6 FFFFD6 Reserved FFD5 FFFFD5 Reserved FFD4 FFFFD4 Reserved FFD3 FFFFD3 Reserved FFD2 FFFFD2 Reserved FFD1 FFFFD1 Reserved FFDO FFFFDO Reserved FFCF FFFFCF Reserved FFCE FFFFCE Reserved FFCD FFFFCD Reserved FFCC FFFFCC Reserved FFCB FFFFCB Reserved FFCA FFFFCA Reserved PORT B FFC9 FFFFC9 Host Port GPIO Data Register HDR FFC8 FFFFC8 Host Port GPIO Direction Register HDDR 08 7 FFFFC7 Host Transmit Register HTX FFC6 FFFFC6 Host Receive Register HRX 5 FFFFC5 Host Base Address Register HBAR FFC4 FFFFC4 Host Polarity Control Register HPCR FFC3 FFFFC3 Host Status Register HSR FFC2 FFFFC2 Host Control Register HCR FFC1 Reserved FFCO FFFFCO Reserved D 6 DSP56303UM AD MOTOROLA PROGRAMMING REFERENCE Table D 1 Internal I O Memory Map Continued Peripheral 2 1 Register Name PORT C FFBF FFFFBF Port C Control
34. ESSIO There are two synchronous serial interfaces ESSIO and ESSI1 that provide a full duplex serial port for serial communication with a variety of serial devices including one or more industry standard codecs other DSPs microprocessors and peripherals which implement the Motorola Serial Peripheral Interface SPI 2 24 DSP56303UM AD MOTOROLA Signal Connection Descriptions Enhanced Synchronous Serial Interface 0 ESSIO Table 2 12 Enhanced Synchronous Serial Interface 0 5510 Signal Name Type State During Reset Stop Signal Description 5 00 Input or Output Input Discon nected Internally Serial Control 0 The function of SC00 is determined by the selection of either Synchronous or Asynchronous mode For Asynchronous mode this signal will be used for the receive clock I O Schmitt trigger input For Synchronous mode this signal is used either for Transmitter 1 output or for Serial I O Flag 0 Port C 0 The default configuration following reset is GPIO input When configured as PCO signal direction is controlled through the Port C Direction Register PRRC The signal can be configured as ESSI signal SC00 through Port C Control Register PCRC This input is 5 V tolerant 5 01 1 Input Output Input or Output Input Discon nected Internally Serial Control 1 The function of this signal is determined by
35. GPIO HTRQ HRRQ Active Low 1 HIO8 Enable HTRQ HRRQ Active High Host Acknowledge Priority 0 HACK Active Low 1 HACK Active High 14 1 10 9 15 3 12 817 6 5 413 2 1 0 Host Port Control HRP HCSP HDDS HASP HDSP HROD HREN HGEN Register HPCR 0 X FFFFC4 Reset 0 Reserved Program as 0 Figure D 8 Host Base Address and Host Port Control Registers D 22 DSP56303UM AD MOTOROLA PROGRAMMING REFERENCE Application Date Programmer Sheet 4 of 6 HO ST Processor Side Receive Request Enable DMA Off 0 Interrupts Disabled 1 Interrupts Enabled DMA On 0 Host gt DSP 1 DSP Host Transmit Request Enable DMA Off 0 Interrupts Disabled 1 Interrupts Enabled DMA On 0 DSP Host 1 Host DSP HREQ HTRQ HACK HRRQ Host Flags Write Only Host Little Endian Initialize Write Only 0 1 Initialize DMA INIT HLEND HFO HDRQ TREQ RREQ Interrupt Control Register ICR 0 X Reset 0 Receive Data Register Full 0 Wait 1 Read Transmit Data Register Empty 0 Wait 1 Write Transmitter Ready 0 Datain HI 1 Data Not in HI Host Flags Read Only DMA Status 0 DMA Disabled 1 Enabled Host Request 0 HREQ Deasserted 1 HREQ Asserted DMA Interrupt Status Register ISR 0
36. HROD 6 14 bit 9 Host Data Strobe Polarity bit HDSP 6 15 bit 10 Host Address Strobe Polarity bit HASP 6 15 bit 11 Host Multiplexed Bus bit HMUX 6 15 bit 12 Host Dual Data Strobe bit HDDS 6 15 bit 13 Host Chip Select Polarity bit HCSP 6 16 bit 14 Host Request Polarity bit HRP 6 16 DSP56303UM AD l 5 bit 15 Host Acknowledge Polarity bit HAP 6 16 reserved bit bit 7 6 14 HRD HRD 2 20 HRDF bit 6 11 HREN bit 6 14 bit 6 27 HRIE bit 6 10 HROD bit 6 14 HRP bit 6 16 2 24 HRW 2 20 register 6 9 HSR register 6 11 bit 0 Hlost Receive Data Full bit 6 11 bit 1 Host Transmit Data Empty bit HTDE 6 11 bit 2 Host Command Pending bit 6 11 bits 3 4 Host Flag 0 and 1 bits HF1 6 11 reserved bits bits 5 15 6 12 HTDE bit 6 11 HTIE bit 6 10 HTRO HTRO 2 23 HTX register 6 9 0 bits 6 25 HWR HWR signal 2 21 ICR register 6 22 bit 0 Receive Request Enable bit 6 23 bit 1 Transmit Request Enable bit 6 23 bit 2 Double Host Request bit HDRQ 6 23 bit 3 Host Flag 0 bit 6 24 bit 4 Host Flag 1 bit HF1 6 24 bit 5 Host Little Endian bit HLEND 6 24 bit 6 reserved bit 6 24 bit 7 Initialize bit INIT 6 24 reserved bit bit 6 6 24 IDCODE instruction 11 9 IDLE bit 8 14 Idle Line Flag bit IDLE 8 14 Idle Line Interrupt Enable bit ILIE 8 11 IFO bit 7 28 l 6 DSP56303UM AD I
37. The Data Input DI bit reflects the value of the TIO pin If the INV bit is set the value of the TIO pin is inverted before it is written to the DI bit If the INV bit is cleared the value of the TIO pin is written directly to the DI bit DI is cleared by a hardware RESET signal or a software RESET instruction MOTOROLA DSP56303UM AD 9 13 Triple Timer Module Triple Timer Module Programming Model 9 3 4 9 Data Output DO Bit 13 The Data Output DO bit is the source of the TIO value when it is a data output pin The TIO pin is data output when the GPIO mode is enabled and DIR is set A value written to the DO bit is written to the TIO pin If the INV bit is set the value of the DO bit is inverted when written to the TIO pin When the INV bit is cleared the value of the DO bit is written directly to the TIO pin When GPIO mode is disabled writing the DO bit has no effect The DO bit is cleared by a hardware RESET signal or a software RESET instruction 9 3 4 10 Prescaler Clock Enable PCE Bit 15 The Prescaler Clock Enable PCE bit is used to select the prescaler clock as the timer source clock When the PCE bit is cleared the timer uses either an internal CLK 2 signal or an external TIO signal as its source clock When the PCE bit is set the prescaler output is used as the timer source clock for the counter regardless of the timer operating mode To ensure proper operation the PCE bit should be changed only when the time i
38. Transmit Data pin 1 Note TD2 Transmit Data pin 2 TOD Transmitter 0 drive enable if SSC1 1 amp SCD1 1 Note RD Receive Data Note F0 Hag0 Note F1 HaglifSSC1 0 Note U Unused may be used as GPIO pin Note X Indeterminate MOTOROLA DSP56303UM AD 7 25 Enhanced Synchronous Serial Interface ESSI ESSI Programming Model 7 4 2 17 CRB ESSI Receive Enable RE Bit 17 When the RE bit is set the receive portion of the ESSI is enabled When this bit is cleared the receiver is disabled by inhibiting data transfer into RX If data is being received while this bit is cleared the remainder of the word is shifted in and transferred to the ESSI Receive Data Register RE must be set in both the Normal and On demand modes for the ESSI to receive data In Network mode clearing RE and setting it again disables the receiver after reception of the current data word The receiver remains disabled until the beginning of the next data frame RE is cleared by either a hardware reset signal or a software reset instruction Note The setting of the RE bit does not affect the generation of a frame sync 7 4 2 18 CRB ESSI Transmit Interrupt Enable TIE Bit 18 Setting the TIE bit enables a DSP transmit interrupt which is generated when both the TIE and the TDE bits in the ESSI Status Register are set When TIE is cleared the transmit interrupt is disabled The use of the transmit interrupt is described in Sect
39. and Table 2 13 Serial Communication Interface SCD Port E 3 Table 2 14 Timer 3 Table 2 15 OnCE JTAG Port 6 Table 2 16 1 PortA signals define the external memory interface port including the external address bus data bus and control signals 2 Port B signals are the HI08 port signals multiplexed with the GPIO signals 3 PortC and D signals are the two ESSI port signals multiplexed with the GPIO signals 4 PortE signals are the SCI port signals multiplexed with the GPIO signals MOTOROLA DSP56303UWAD 2 3 Signal Connection Descriptions Signal Groupings Figure 2 1 is a diagram of DSP56303 signals by functional group DSP56303 Power Inputs VccP PLL Vcco 4 Internal Logic Address Bus Vcco Data Bus Vccc 2 Bus Control VccH HI08 ESSI SCI Timer Grounds GNDp PLL GNDp GNDg Internal Logic Address Bus GNDp 5 Data GNDc Bus Control GNDy 5 HI08 GNDs ESSI SCI Timer EXTAL XTAL Clock CLKOUT PCAP PLL PINIT NMI Port A 0 17 18 External Address Bus 00 023 24 External Data Bus 0 4 RASO RAS3 External RD Bus WR Control TA BR BG BB CAS BCLK BCLK Note 1 Interrupt Mode Control Host Interface HIO8 Port Enhanced Synchronous Serial Interface Port 0 ESSIO Enhanced Synchronous Serial Interface Port 1 ESSI Serial Communications Interface SCI Port Timers OnCE JTAG Port MODA IRQA MOD
40. or in Asynchronous mode SYN 0 SCD0 controls the direction of the SCO I O pin When SCD0 is set SCO is an output when SCDO is cleared SCO is an input When is set the value of SCDO is ignored and the SCO pin is always an output Bit SCDO is cleared by a hardware reset signal or by a software reset instruction 7 4 2 3 CRB Serial Control Direction 1 SCD1 Bit 3 In Synchronous mode SYN 1 when transmitter 2 is disabled TE2 0 or in Asynchronous mode SYN 0 SCD1 controls the direction of the SC1 I O pin When SCD1 is set SC1 is an output when SCD1 is cleared SC1 is an input When TE2 is set the value of SCD1 is ignored and the SC1 pin is always an output Bit SCD1 is cleared by a hardware reset signal or by a software reset instruction 7 4 2 4 CRB Serial Control Direction 2 SCD2 Bit 4 SCD2 controls the direction of the SC2 I O pin When SCD2 is set SC2 is an output when SCD2 is cleared SC2 is an input SCD2 is cleared by a hardware reset signal or by a software reset instruction 7 4 2 5 CRB Clock Source Direction SCKD Bit 5 SCKD selects the source of the clock signal used to clock the Transmit Shift Register in Asynchronous mode If SCKD is set and the ESSI is in Synchronous mode the internal clock is the source of the clock signal used for all the Transmit Shift Registers and the Receive Shift Register If SCKD is set and the ESSI is in Asynchronous mode the internal clock source becomes the bit c
41. the PE bit is always cleared since there is no parity bit in these modes If the byte received causes both parity and overrun errors the SCI receiver recognizes only the overrun error 8 14 DSP56303UM AD MOTOROLA Serial Communication Interface SCI SCI Programming Model 8 3 2 7 SSR Framing Error Flag FE Bit 6 The FE bit is set in the Asynchronous modes when no stop bit is detected in the data string received FE and RDRE are set simultaneously when the received word is transferred to the SRX However the FE flag inhibits further transfer of data into the SRX until it is cleared FE is cleared when the SCI Status Register is read followed by reading the SRX The hardware software SCI individual and stop reset also clear FE In the 8 bit Synchronous mode FE is always cleared If the byte received causes both framing and overrun errors the SCI receiver recognizes only the overrun error 8 3 2 8 SSR Received Bit 8 R8 Address Bit 7 In the 11 bit Asynchronous Multidrop mode the R8 bit is used to indicate whether the received byte is an address data R8 is set for addresses and is cleared for data 15 not affected by reading SRX or SCI Status Register The hardware software SCI individual and stop resets clear R8 8 3 3 SCI Clock Control Register SCCR The SCCR is a 24 bit read write register that controls the selection of the clock modes and baud rates for the transmit and receive sections of the SCI interface T
42. 1 where SCP 200r 1 CD 000 to FFF TO SCLK 0693 Figure 8 6 SCI Baud Rate Generator 8 3 3 5 SCCR Transmit Clock Source Bit TCM Bit 15 TCM selects whether an internal or external clock is used for the transmitter If TCM is cleared the internal clock is used If TCM is set the external clock from the SCLK pin is used Hardware and software reset clear TCM 8 3 4 SCI Data Registers The SCI data registers are divided into two groups receive and transmit see Figure 8 7 There are two receive registers a Receive Data Register SRX and a serial to parallel Receive Shift Register There are also two transmit registers a Transmit Data Register called either STX or STXA and a parallel to serial Transmit Shift Register 8 18 DSP56303UM AD MOTOROLA Serial Communication Interface SCI SCI Programming Model SCI Receive Data Register High Read Only SCI Receive Data Register Middle Read Only SCI Receive Data Register Low Read Only SCI Receive Data Shift Register Note 1 SRX is the same register decoded at three different addresses a Receive Data Register SCI Transmit Data Register High Write Only SCI Transmit Data Register Middle Write Only SCI Transmit Data Register Low Write Only SCI Transmit Data Shift Register i TXD gt 23 16 15 a lt SCI Transmit Data Address Register Write Only Note 1 Bytes are masked on the fly 2 STX is the same register
43. 1 Host chip select input enabled HA9EN 0 address 9 enable bit has no meaning in non multiplexed bus HA8EN 0 address 8 enable bit has no meaning in non multiplexed bus HGE 0 Host GPIO pins are disabled HIO8CONT bset HEN x M_HPCR Enable the HI08 to operate as host interface set HEN 1 jclr HSR wait for the program length to be written movep x M HRX a0 HRDF x M_HSR wait for the program starting address to be written movep x M HRX rO move r0 r1 do a0 HIO8LOOP set a loop with the downloaded length 4 counts HIO8LL jset HRDF x M_HSR HIO8NW If new word was loaded then jump to read that word jclr THEO x M HSR HIO8LL If HF0 0 then continue with the downloading enddo Must terminate the do loop bra HI08LOOP HIOS8NW movep HRX p r0 Move the new word into its destination location in the program RAM 8 bra lt FINISH EPRSCILD jclr 1 EPROMLD MC MB MA 001 go load from EPROM This is the routine that loads from the SCI MC MB MA 010 external SCI clock SCILD A 8 DSP56303UM AD MOTOROLA movep 0302 X M_SCR movep C000 X M_SCCR movep 7 X M_PCRE do 6 100 6 jclr 2 558 movep X M SRXL A2 1 X M_SSR movep A2 X M_STXL 8 __ 10096 move al r0 move 1 1 do a0 LOOP7 do 3 LOOP8 2 X M_SSR movep X M SRXL A2
44. 8 3 1 3 8 3 1 4 8 3 1 5 8 3 1 6 8 3 1 7 8 3 1 8 8 3 1 9 8 3 1 10 8 3 1 11 8 3 1 12 8 3 1 13 8 3 1 14 8 3 1 15 8 3 2 8 3 2 1 8 3 2 2 8 3 2 3 8 3 2 4 8 3 2 5 8 3 2 6 8 3 2 7 8 3 2 8 8 3 3 8 3 3 1 8 3 3 2 INTRODUCTION 8 3 SGIHIO PINS Ati 8 3 Receive Data RXD uuu u un 8 4 Transmit Data 8 4 SCI Serial Clock 5 8 4 SCI PROGRAMMING 8 4 SCI Control Register 5 8 8 SCR Word Select WDS 0 2 Bits 0 2 8 8 SCR SCI Shift Direction SSFTD Bit3 8 9 SCR Send Break SBK Bit4 8 9 SCR Wakeup Mode Select WAKE Bit5 8 9 SCR Receiver Wakeup Enable RWU Bit6 8 10 SCR Wired OR Mode Select WOMS Bit7 8 10 SCR Receiver Enable RE Bit8 8 10 SCR Transmitter Enable TE Bit9 8 11 SCR Idle Line Interrupt Enable ILIE Bit10 8 11 SCR SCI Receive Interrupt Enable RIE Bit11 8 12 SCR SCI Transmit Interrupt Enable TIE Bit12 8 12 SCR Timer Interrupt Enable TMIE Bit13 8 12 SCR Timer Interrupt Rate STIR Bit14 8 12 SCR SCI Clock Polarity SCKP Bit15 8 12 SCR SCI Receive with Exception Interrupt Enable HBIBYBICIO ott n eee oq d bod me eae uut aes 8 13 SCI Statu
45. 81 6 02 le Ee a 982 7 01 1 44 00 0 ZINd L 8 0 JO JO Jeynq 1o9ejes sessed JO 0 1 Jo JOAUP se suonoun jeues se 19S 0 Hq ye 19 91 O XL SB LOS 1091096 q 19 91 0 J043u02 26 01 1 41 00 7080 51 10 1 00 0 9 HSd DIA suq pz 1521 z 0000005 19598 S S1IJ Ul 44445 LISSA 616 vc 151 u 26 cgJ44 01553 ve v 91 1553 21 8 jo jequnN L1A 101 u09 gt 1553 MOTOROLA Figure D 12 ESSI Control Register A CRA DSP56303UM AD D 26 PROGRAMMING REFERENCE Date Application Programmer Sheet 2 of 4 eee ee ee 9844449 01553 IonuoS NAS 231 38 SIL aria 3188 1553 1998 RER 0184 1164 0 2 7 9 9 718 6 OL EF VE 919 ZL 8 6L Oc 1
46. Acknowledge Polarity SERIAL COMMUNICATIONS INTERFACE SCI EQUATES EQUATES for Serial Communications Interface SCI gt Register Addresses M STXH EQU B 4 SFFFF97 SCI Transmit Data Register high DSP56303UM AD MOTOROLA Equates 1 STXM SFFFF96 SCI Transmit Data Register middle STXL EQU SFFFF95 SCI Transmit Data Register low SRXH EQU SFFFF9A SCI Receive Data Register high SRXM SFFFF99 SCI Receive Data Register middle SRXL EQU SFFFF 98 SCI Receive Data Register low STXA EQU SFFFF94 SCI Transmit Address Register SCR EQU SFFFF9C SCI Control Register SSR EQU SFFFF93 SCI Status Register 1 SCCR EQU SFFFF 9B SCI Clock Control Register SCI Control Register Bit Flags 1 WDS EQU 57 Word Select Mask WDSO WDS3 1 WDSO EQU 0 Word Select 0 1 WDS1 EQU i Word Select 1 1 WDS2 EQU 2 Word Select 2 1 SSFTD EQU 3 SCI Shift Direction 1 SBK EQU 4 Send Break WAKE EQU 5 Wakeup Mode Select RWU EQU 6 Receiver Wakeup Enable WOMS EQU 7 Wired OR Mode Select SCRE EQU 8 SCI Receiver Enable SCTE EQU 9 SCI Transmitter Enable ILIE EQU 10 Idle Line Inte
47. External External External Internal Program RAM 0800 0800 AR Internal Y data RAM Internal X data RAM 2K 2K 0000 0000 0000 Bit Settings Memory Configuration Program X Data Y Data Addressable See Mee er RAM RAM RAM Cache Memory Size 1 0 0 AK 2K 2K None 64K 000 FFF 000 7FF 000 7FF 0558 Figure 3 5 16 bit Space with Default 1 0 0 3 14 DSP56303UM AD MOTOROLA Memory Configuration Memory Maps Program X Data Y Data FFFF SFFFF Internal I O External I O FF80 External External External 1000 0C00 0800 0800 Internal Internal Internal Program RAM X data RAM Y data RAM 3K 2K 2K 0000 0000 0000 Bit Settings Memory Configuration Program X Data Y Data Addressable Cache Memory Size 1 0 1 3K 2K 2K 1K 64K 000 BFF 000 7FF 000 7FF 00 AA0562 Figure 3 6 16 bit Space with Instruction Cache Enabled 1 0 1 MOTOROLA DSP56303UM AD 3 15 Memory Configuration Memory Maps Program X Data FFFF SFFFF SFFFF External 0 FF80 FF80 External External External 0C00 0C00 0800 Internal Internal Internal X data RAM Y data RAM Program RAM 3K 3K 2K 0000 0000 0000 Bit Settings Memory Configuration Program X Data Y Data Addressable 96s Caches Memory Size 1 1 0 2K 3K 3K None 64K
48. Hlost Receive Interrupt Enable bit HRIE 6 10 bit 1 Host Transmit Interrupt Enable bit HTIE 6 10 bit 2 Host Command Interrupt Enable bit HCIE 6 10 bits 3 4 Host Flag 2 and 3 bits HF2 HF3 6 10 reserved bits bits 5 15 6 10 HCS signal 2 22 HCSEN bit 6 14 HCSP bit 6 16 l 4 DSP56303UM AD register 6 17 HDDS bit 6 15 HDR register 6 17 HDRQ bit 6 23 HDS signal 2 21 HDSP bit 6 15 HEN bit 6 14 bit 6 24 HF1 bits 6 11 HF1 bit 6 24 bit 6 27 HF2 HF3 bits 6 10 bit 6 27 HGEN bit 6 13 1108 1 15 2 3 2 16 2 18 2 19 2 22 6 3 GPIO 5 3 data transfer 6 31 DSP core interrupts 6 19 DSP side control registers 6 8 DSP side data registers 6 8 DSP side registers after reset 6 18 DSP to host data word 6 4 handshaking protocols 6 5 interrupts 6 5 mapping 6 4 transfer modes 6 5 external host programmer s model 6 20 GPIO 6 30 108 to DSP core interface 6 3 108 to host processor interface 6 4 Host Base Address Register HBAR 6 12 Host Control Register HCR 6 9 6 10 Host Data Direction Register HDDR 6 17 Host Data Register HDR 6 17 Host Port Control Register HPCR 6 13 Host Receive Data Register HRX 6 9 host side Command Vector Register CVR 6 25 Interface Control Register ICR 6 22 Interface Status Register ISR 6 26 Interface Vector Register IVR 6 28 Receive Byte Registers RXH RXM RXL 6 28 Transmit Byte Registers TXM TXL 6 29 host side registers a
49. Mode 1 External timer pulse generated by the internal clock Toggle Mode 2 Output timing signal toggled by the internal clock Event Counter Mode 3 Internal timer interrupt generated by an external clock Measurement Input Width Mode 4 Input pulse width measurement Input Pulse Mode 5 Input signal period measurement Capture Mode 6 Capture external signal PWM Mode 7 Pulse Width Modulation Watchdog Pulse Mode 9 Output pulse internal clock Toggle Mode 10 Output toggle internal clock These modes are described in detail below Timer modes are selected by setting the TC 3 0 bits in the TCSR Table 9 2 shows how the different timer modes are selected by setting the bits in the TCSR The table also shows the TIO pin direction and the clock source for each timer mode Table 9 2 on page 9 10 summarizes these modes and the following paragraphs describe these modes in detail 9 16 DSP56303UM AD MOTOROLA Triple Timer Module Timer Modes of Operation Note To ensure proper operation the TC 3 0 bits should be changed only when the timer is disabled when the TE bit in the TCSR is cleared 9 4 1 Timer Modes The following Timer modes are provided e Timer GPIO e Timer Pulse Timer Toggle e Event Counter 9 4 1 1 Timer GPIO Mode 0 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO TIO Clock KIND NAME 0 0 0 0 GPIO Internal 0 Timer GPIO
50. Mode 10 9 26 9 4 5 Reserved Mod s LESS DRE PER 9 27 9 4 6 Special Cases ee e 9 27 9 4 6 1 Timer Behavior during 9 27 9 4 6 2 Timer Behavior during Stop 9 27 9 4 7 DMA Trigger 9 27 MOTOROLA DSP56303UM AD xi SECTION 10 1 10 2 10 3 10 4 10 4 1 10 4 1 1 10 4 1 2 10 4 1 3 10 4 1 4 10 4 2 10 4 3 10 4 3 1 10 4 3 2 10 4 3 3 10 4 3 4 10 4 3 5 10 4 3 6 10 4 3 7 10 4 3 8 10 5 10 5 1 10 5 2 10 5 3 10 5 4 10 5 5 10 5 6 10 5 6 1 10 5 6 2 10 5 6 3 10 5 6 4 10 5 6 5 xii 10 ON CHIP EMULATION MODULE 10 1 INTRODUCTION 10 3 ONCE MODULE PINS 10 3 DEBUG EVENT DE ead ein Ze ttes 10 4 ONCE CONTROLLER 10 4 OnCE Command Register 10 5 Register Select RS4 RS0 Bits 0 4 10 5 Exit Command EX Bit5 10 5 GO Command GO 6 10 6 Read Write Command RW Bit7 10 6 OnCE Decoder ODEC 10 8 OnCE Status and Control Register OSCR 10 8 Trace Mode Enable TME BitO 10 8 Interrupt Mode Enable Bit 1 10 8 Software Debug Occurrence SWO Bit 2 10 8 Memory Breakpoint Occurrence MBO
51. PL 0 20 Timer Prescaler Load Register Reserved Program as 0 TPLR FFFF83 Read Write Reset 000000 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Current Value of Prescaler Counter 0 20 Timer Prescaler Count Register Reserved Program as 0 TPCR FFFF82 Read Only Reset 000000 Figure D 19 Timer Prescaler Load Count Register TPLR TPCR MOTOROLA DSP56303UM AD D 33 PROGRAMMING REFERENCE Application Date Programmer Sheet 2 of 3 Inverter Bit 8 0 0 to 1 transitions on TIO input increment the counter or high pulse width measured or high pulse output on TIO 1 1 to 0 transitions on TIO input increment the counter or low pulse width measured or low pulse output on TIO Timer Reload Mode Bit 9 Timer Control Bits 4 7 TCO TC3 0 Timer operates as a free TC 3 0 TIO Clock Mode running counter 0000 GPIO Internal Timer 1 Timer is reloaded when 0001 Output Internal Timer Pulse selected condition occurs 0010 Output Internal Timer Toggle 0011 Input External Event Counter Direction Bit 11 0100 Input Internal Input Width 0 TIO pin is input 0101 Input Internal Input Period 1 TIO pin is output 0110 Input Internal Capture 0111 Output Internal Pulse Width Modulation 1000 X Reserved ee 1001 Output Internal Watchdog Pulse Zero read on in L un 09 Output Internal wee Toggle 1100
52. PROGRAMMING REFERENCE Application Date Programmer Sheet 4 of 4 GPIO Port E SCI Port E Control PCRE H X S FFFOP ReadWrite Reset PCn 1 Port Pin configured as PCn 0 gt Port Pin configured as GPIO ReadWrite Reset PDCn 1 gt Port Pin is Output PDCn 0 gt Port Pin is Input 3 5 4 Port E Direction Register H X SFFFFSE ReadWre Reset 6 5 4 0 X FFFF9D 01010 port pin n is GPIO input then PDn reflects the value on port pin n if port pin n is GPIO output then value written to PDn is reflected on port pin n Reserved Program as 0 Figure D 25 Port E Registers PCRE PRRE PDRE MOTOROLA DSP56303UM AD D 39 PROGRAMMING REFERENCE D 40 DSP56303UM AD MOTOROLA INDEX Numerics 5 V tolerance 2 3 A 0 17 signals 2 9 0 signals 2 10 adder modulo 1 9 offset 1 9 reverse carry 1 9 address attribute signals 2 10 address bus 2 3 signals 2 9 Address Generation Unit 1 9 addressing modes 1 10 AGU 1 9 ALC bit 7 13 Alignment Control bit ALC 7 13 applications 1 7 Asynchronous Synchronous bit SYN 7 18 BA3 BA10 bits 6 12 barrel shifter 1 8 Base Address bits BA3 BA10 6 12 BB signal 2 13 BCLK signal 2 13 BCLK signal 2 13 BG signal 2 12 bootstrap 4 4 bootstrap from byte wide external memory 4 6 bootstrap program options invoking 4 5 bootstrap ROM 3 7 bootstr
53. Repeat steps 7 and 8 for the entire FIFO 12 times Note The user must read the entire FIFO since each read increments the FIFO pointer thus pointing to the next FIFO location At the end of this procedure the FIFO pointer points back to the beginning of the FIFO The information that has been read by the external command controller now contains the address of the newly fetched instruction the address of the instruction currently on the PDB the address of the instruction currently on the instruction latch as well as the addresses of the last twelve instructions that have been executed and are change of flow A user program can now reconstruct the flow of a full trace based on this information and on the original source code of the currently running program 10 12 5 Displaying a Specified Register The DSP56300 must be in Debug mode and all actions described in Saving Pipeline Information on page 10 25 have been executed The sequence of actions is 1 Select shift DR Shift in the Write PDB with GO no EX Pass through update DR 2 Select shift DR Shift in the 24 bit opcode MOVE reg X 0GDB Pass through update DR to actually write OPDBR and thus begin executing the MOVE instruction 3 Wait for DSP to reenter Debug mode wait for DE or poll core status 4 Select shift DR and shift in READ GDB REGISTER Pass through update DR this selects OGDBR as the data register for read 5 Select shift DR Shift out
54. SSISR1 FFA6 FFFFA6 ESSI 1 Control Register B CRB1 FFA5 FFFFA5 ESSI 1 Control Register A CRA1 FFA4 FFFFA4 ESSI 1 Transmit Slot Mask Register A TSMA1 FFA3 FFFFA3 ESSI 1 Transmit Slot Mask Register B TSMB1 FFA2 FFFFA2 ESSI 1 Receive Slot Mask Register A RSMA1 FFA1 FFFFA1 ESSI 1 Receive Slot Mask Register RSMB1 0 FFFFAO Reserved PORT FF9F FFFF9F Port E Control Register PCRE FF9E FFFF9E Port E Direction Register PRRE FF9D FFFF9D Port E GPIO Data Register PDRE D 8 DSP56303UM AD MOTOROLA PROGRAMMING REFERENCE Table D 1 Internal I O Memory Map Continued Peripheral 2 1 us Register Name SCI FF9C FFFF9C SCI Control Register SCR FF9B FFFF9B SCI Clock Control Register SCCR FF9A FFFF9A SCI Receive Data Register High SRXH FF99 FFFF99 SCI Receive Data Register Middle SRXM FF98 FFFF98 SCI Recieve Data Register Low SRXL FF97 FFFF97 SCI Transmit Data Register High STXH FF96 FFFF96 SCI Transmit Data Register Middle STXM FF95 FFFF95 SCI Transmit Data Register Low STXL FF94 FFFF94 SCI Transmit Address Register STXA FF93 FFFF93 SCI Status Register SSR FF92 FFFF92 Reserved FF91 FFFF91 Reserved FF90 FFFF90 Reserved MOTOROLA DSP56303UM AD D 9 PROGRAMMING REFERENCE Table D 1 Internal I O Memory Map Continued Peripheral
55. Sereni hace sone dote chee desit inte 11 5 TAP GONTROLLER ee Cen oak 11 6 DSP56300 RESTRICTIONS 11 12 DSP56303UM AD MOTOROLA JTAG Port Introduction 11 1 INTRODUCTION The DSP56300 core provides a dedicated user accessible Test Access Port TAP that is fully compatible with the IEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture Problems associated with testing high density circuit boards have led to development of this proposed standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group JTAG The DSP56300 core implementation supports circuit board test strategies based on this standard The test logic includes a TAP that consists of five dedicated signal pins a 16 state controller and three test data registers A Boundary Scan Register BSR links all device signal pins into a single shift register The test logic implemented utilizing static logic design is independent of the device system logic The DSP56300 core implementation provides the following capabilities Perform boundary scan operations to test circuit board electrical continuity EXTEST Bypass the DSP56300 core for a given circuit board test by effectively reducing the BSR to a single cell BYPASS Sample the DSP56300 core based device system pins during operation and transparently shift out the result in the BSR Preload values to o
56. The TXDE bit indicates that the Transmit Byte Registers TXH TXM TXL are empty and can be written by the host processor TXDE is set when the contents of the Transmit Byte Registers are transferred to the HRX register TXDE is cleared when the transmit TXL or TXH according to HLEND bit register is written by the host processor TXDE can be set by the host processor using the initialize function TXDE may be used to assert the external HTRQ pin if the TREQ bit is set Regardless of whether the TXDE interrupt is enabled TXDE indicates whether the TX registers are full and data can be latched in so that polling techniques may be used by the host processor 6 26 DSP56303UM AD MOTOROLA Host Interface 108 HI08 External Host Programmer s Model 6 6 3 3 ISR Transmitter Ready TRDY Bit 2 The TRDY status bit indicates that TXH TXM TXL and the HRX registers are empty TRDY TXDE and HRDF If TRDY is set the data that the host processor writes to TXH TXM TXL is immediately transferred to the DSP side of the HI08 This feature has many applications For example if the host processor issues a host command which causes the DSP56303 to read the HRX the host processor can be guaranteed that the data it just transferred to 108 is that being received by the DSP56303 6 6 3 4 ISR Host Flag 2 HF2 Bit 3 The HF2 bit in the ISR indicates the state of Host Flag 2 in the HCR on the DSP side can be changed only by the DSP56303 see
57. The idle interrupt is not asserted again until at least one character has been received The results are as follows 1 The IDLE bit shows the real status of the receive line at all times 2 idle interrupt is generated once for each idle state no matter how long the idle state lasts MOTOROLA DSP56303UM AD 8 11 Serial Communication Interface SCI SCI Programming Model 8 3 1 10 SCR SCI Receive Interrupt Enable RIE Bit 11 The RIE bit is set to enable the SCI Receive Data interrupt If RIE is cleared the Receive Data interrupt is disabled and then the RDRF bit in the SCI Status Register must be polled to determine if the Receive Data Register is full If both RIE and RDRF are set the SCI requests an SCI Receive Data interrupt from the interrupt controller Receive interrupts with exception have higher priority than normal Receive Data interrupts Therefore if an exception occurs i e if PE FE or OR are set and REIE is set the SCI requests an SCI Receive Data with Exception interrupt from the interrupt controller RIE is cleared by hardware and software reset 8 3 1 11 SCR SCI Transmit Interrupt Enable TIE Bit 12 The TIE bit is set to enable the SCI Transmit Data interrupt If TIE is cleared Transmit Data interrupts are disabled and the Transmit Data Register Empty TDRE bit in the SCI status register must be polled to determine if the Transmit Data Register is empty If both TIE and TDRE are set the SCI requests
58. jclr 1 X M_SSR movep a2 X M_STXL 8 _LOOP8 movem 1 0 _LOOP7 bra lt FINISH Bootstrap Programs Configure SCI Control Reg Configure SCI Clock Control Reg Configure SCLK TXD and RXD get 3 bytes for number of program words and 3 bytes for the starting address Wait for RDRF to go high Put 8 bits in 22 Wait for TDRE to go high cho the received byt starting address for load save starting address Receive program words Wait for RDRF to go high Put 8 bits in 22 Wait for TDRE to go high cho the received byt Store 24 bit result in P mem Boot from SCI done This is the routine that loads from external EPROM MC MB MA 001 EPROMLD move 2 movep AARV X M_AAR1 do 6 _LOOP9 movem p 2 2 8 _ LOOPY move 1 0 move 1 1 do a0 _LOOP10 do 3 100 11 movem p 2 2 8 _LOOP11 movem al p r0 _LOOP10 MOTOROLA r2 address of external EPROM aarl configured for SRAM types of access read number of words and starting address Get the 8 LSB from ext P mem Shift 8 bit data into Al starting address for load save it in rl a0 holds the number of words read program words Each instruction has 3 bytes Get the 8 LSB from ext P mem Shift 8 bit data into Al Go get another byte Store 24 bit result in mem and go get ano
59. the bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set The contents of the counter are loaded into the TCR The TCR then contains the value of the time that elapsed between the two signal transitions on the TIO pin After the second signal transition if the TRM bit is set the TE bit is set to clear the counter and enable the timer The counter is loaded with the TLR value on the first timer clock signal Each subsequent clock signal increments the counter After the second signal transition if the TRM bit is set the TE bit is set to clear if the TRM bit is cleared the counter continues to be incremented on each timer clock This process is repeated until the timer is disabled i e TE is cleared 9 22 DSP56303UM AD MOTOROLA Triple Timer Module Timer Modes of Operation If the counter overflows the TOF bit is set and if TOIE is set an overflow interrupt is generated The counter contents can be read at any time by reading the TCR 9 4 2 4 Measurement Capture Mode 6 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Kind TIO Clock 0 1 1 0 6 Capture Measurement Input Internal In this mode the timer counts the number of clocks that elapse between starting the timer and receiving an external signal Set the TE bit to clear the counter and enable the timer The value the timer is to count is loaded into the TLR When the
60. the Receive Data Register is full and no receive error conditions exist Reading RX clears the pending interrupt This error free interrupt can use a fast interrupt service routine for minimum overhead ESSI Receive Last Slot Interrupt Occurs when the ESSI is in Network mode and the last slot of the frame has ended This interrupt is generated regardless of the Receive Mask Register setting The receive last slot interrupt may be used to signal that the Receive Mask Slot Register can be reset the DMA channels may be reconfigured and data memory pointers may be reassigned Using the receive last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame will be serviced with the new setting without synchronization problems The maximum time it takes to service a receive last slot interrupt should not exceed N 1 ESSI bits service time where N is the number of bits the ESSI can transmit per time slot ESSI Transmit Data with Exception Status Occurs when the transmit exception interrupt is enabled at least one Transmit Data Register of the enabled transmitters is empty and a transmitter underrun error has occurred This exception sets the TUE bit The TUE bit is cleared by first reading the SSISR and then writing to all the Transmit Data Registers of the enabled transmitters or by writing to the TSR to clear the pending interrupt ESSI Transmit Last Slot Interrupt Occurs when the ESS
61. the bus BR is typically sent to an external bus arbitrator that controls the priority parking and tenure of each master on the same external bus BR is only affected by DSP requests for the external bus never for the internal bus During hardware reset BR is deasserted and the arbitration is reset to the bus slave state Input Ignored Input Bus Grant BG is an active low input BG must be asserted deasserted synchronous to CLKOUT for proper operation BG is asserted by an external bus arbitration circuit when the DSP56303 becomes the next bus master When BG is asserted the DSP56303 must wait until BB is deasserted before taking bus mastership When BG is deasserted bus mastership is typically given up at the end of the current bus cycle This may occur in the middle of an instruction that requires more than one external bus cycle for execution 2 12 DSP56303UM AD MOTOROLA Signal Connection Descriptions External Memory Expansion Port Port A Table 2 8 External Bus Control Signals Continued State During Type Reset Signal Description Stop or Wait Signal Name BB Input Input Bus Busy BB is a bidirectional active low Output input output and must be asserted and deasserted synchronous to CLKOUT BB indicates that the bus is active Only after BB is deasserted can the pending bus master become the bus master and then assert the signal again The bus master may keep B
62. 0 peiqeua 0705 0705 01559 SOA So ON 1441 1SOH 141195 SOA So ON peiqeua O1LS 141 HSS3 Figure D 4 Interrupt Priority Register Peripherals IPR P dOsss00dd MOTOROLA DSP56303UM AD D 18 PROGRAMMING REFERENCE Sheet 5 of 5 G4j4444 X 110d 195 Law zan ean saw fora LIN zaa 1 Nad 19409 11 6 S 9 718 COE EE LT Grey RUM p p es p s Z 2222 16 ae e 1 0 E 101264 UOISIAIG 24d sug 101284 UOISIAIG e 1 0 i4 um o o 3336 3436 200 100 000 JIN 101024 uoneordnini 03JNW LLIN LLIN OJIN 401984 lt 5 ZHMO0 gt 0 471X Iels 1O uy 1V1X3 5 101 1080 ejqeua 0 8 q11X lqesiq 1V1X lt Add 1019224 Odd dd 00 101983 UOISIAIPA1d ejeis ul 31949 9608
63. 0 dod lqesiq 1ndino x2015 peiqeu3 peigeu3 p lqesiq peiaesia 1250 Td N3d dlSd dOLS Nad 4158 Figure D 5 Phase Lock Loop Control Register PCTL D 19 DSP56303UM AD MOTOROLA PROGRAMMING REFERENCE Application Date Programmer Sheet 1 of 6 Host Receive Data usually Read by program eee ee Ee ee ee 23 22 21 20 19 18 17 16115 14 13 1211110 9 817 6 5 413 2 1 0 Receive High Byte Receive Low Byte Host Receive Data Register HRX X FFEC6 Read Only Reset empty Host Transmit Data usually Loaded by program SSS aoe SSS 23 22 21 20119 18 17 16115 14 13 1211110 9 87 6 5 413 2 1 0 E E ERE 3 Host Transmit Data Register HTX X FFEC7 Write Only Reset empty Figure D 6 Host Receive and Host Transmit Data Registers D 20 DSP56303UM AD MOTOROLA PROGRAMMING REFERENCE Application Date Programmer Sheet 2 of 6 Host Receive Interrupt Enable 0 Disable 1 Enable if HRDF 1 Host Transmit Interrupt Enable 0 Disable 1 Enable if HTDE 1 Host Command Interrupt Enable 0 Disable 1 Enable if HCP 1 Host Control Register HCR X FFFFC2 Read Write Reset 0 DSP Side Host Receive Data Full 0 1 2 Read Host Transmit Data Empty 0 1 Write
64. 0 in the ICR on the host side These two flags are not designated for a specific purpose but are general purpose flags They can be used individually or as encoded pairs in a simple host to DSP communication protocol implemented in both the DSP and the host processor software 6 5 4 5 HSR Reserved Bits 5 15 These bits are reserved They are read as 0 and should be written with 0 6 5 5 Host Base Address Register HBAR The HBAR is used in multiplexed bus modes This register selects the base address where the host side registers are mapped into the bus address space The address from the host bus is compared with the base address as programmed in the base address register If the addresses match an internal chip select is generated if a match is found The use of this register by the chip select logic is described in Figure 6 5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BA10 9 7 BAS 4 0665 Figure 6 4 Host Base Address Register HBAR X FFFFC5 6 5 5 1 HBAR Base Address BA 10 3 Bits 0 7 These bits reflect the base address where the host side registers are mapped into the bus address space 6 5 5 2 HBAR Reserved Bits 8 15 These bits are reserved They are read as 0 and should be written with 0 6 12 DSP56303UM AD MOTOROLA Host Interface HI08 HI08 DSP Side Programmer s Model HAD 0 7 HAS HA 8 1
65. 000 7FF 000 BFF 000 BFF 0560 Figure 3 7 16 bit Space with Switched Program RAM 1 1 0 3 16 DSP56303UM AD MOTOROLA Memory Configuration Memory Maps Program X Data Y Data FFFF SFFFF Internal I O External I O FF80 SFF80 External External External 0800 0C00 0C00 1K Internal Internal 0400 X data RAM Y data RAM Internal 3K 3K Program 0000 RAM 1 K 0000 0000 Bit Settings Memory Configuration Program X Data Y Data Addressable en Cache aVemory Size 1 1 1K 3K 3K 1K 64K 000 3FF 000 BFF 000 BFF 5400 7 0564 Figure 3 8 16 bit Space Switched Program Instruction Cache Enabled 1 1 1 DSP56303UM AD 3 17 Memory Configuration Internal Memory 3 5 INTERNAL I O MEMORY The DSP56303 internal X I O space the top 128 locations of the X data memory space is listed in Appendix D Table D 2 3 18 DSP56303UM AD MOTOROLA MOTOROLA SECTION 4 CORE CONFIGURATION DSP56303UM AD 4 1 Core Configuration 4 2 INTRODUCTION 55 up tr eee tr the RO 4 3 OPERATING 4 3 BOOTSTRAP 4 4 INTERRUPT SOURCES AND PRIORITIES 4 9 REQUEST SOURCES 4 16 OPERATING MODE REGISTER OMR 4
66. 1 Exit1 DR Idle f 1 Update DR Execute Read PIL The PIL value is loaded in the shifter g 1 Select DR Scan Idle 0 Capture DR Idle i 0 Shift DR Idle The 24 bits of the PIL are shifted out 24 steps i 0 Shift DR Idle MOTOROLA DSP56303UM AD 10 31 On Chip Emulation Module Examples of JTAG and OnCE interaction Table 10 14 TMS Sequencing for Reading Pipeline Registers Continued Step TMS JTAG Port OnCE Module Note j 1 Exitl DR Idle k 1 Update DR Idle 1 1 Select DR Scan Idle m 0 Capture DR Idle n 0 Shift DR Idle The eight bits of the OnCE command Read PDB A 10001010 are shifted in n 0 Shift DR Idle 1 Exit1 DR Idle 1 Update DR Execute Read PDB PDB value is loaded in shifter q 1 Select DR Scan Idle r 0 Capture DR Idle 5 0 Shift DR Idle The 24 bits of the PDB are shifted out 24 steps 5 0 Shift DR Idle t 1 Exitl DR Idle u 1 Update DR Idle 0 Run Test Idle Idle This step can be repeated enabling an external T command controller to n 0 Rune Test idle Idle analyze the information During step v the external command controller stores the pipeline information and afterwards it can proceed with the debug activities as requested by the user Es 10 32 DSP56303UM AD MOTOROLA MOTOROLA SECTION 11 JTAG PORT DSP56303UM AD JTAG Port INTRODUCTIONS u oe ees 11 3 JTAG PINS
67. 1 IBLO EQU 3 Mode Interrupt Priority Level low 1 1 EQU 4 IRQB Mode Interrupt Priority Level high IBI2 EQU 5 Mode Trigger Mode ICL EQU 51 0 1 ICLO EQU 6 IRQC Mode Interrupt Priority Level low 1 1 EQU 7 IRQC Mode Interrupt Priority Level high ICL2 EQU 8 IRQC Mode Trigger Mode IDL EQU 5 00 Mode Mask 1 IDLO EQU 9 IRQD Mode Interrupt Priority Level Low 1 1011 EQU 0 IRQD Mode Interrupt Priority Level high IDI2 EQU 11 IRQD Mode Trigger Mode 1 DOL EQU 3000 DMAO Interrupt priority Level Mask 1 DOLO EQU 12 DMAO Interrupt Priority Level low 1 DOL1 EQU 13 DMAO Interrupt Priority Level high 1 DIL EQU 5 000 1 Interrupt Priority Level Mask 1 D1LO EQU 14 1 Interrupt Priority Level low 1 111 EQU 15 Interrupt Priority Level high 1221 530000 DMA2 Interrupt priority Level Mask 1 2210 EQU 16 DMA2 Interrupt Priority Level low 1 211 EQU 17 DMA2 Interrupt Priority Level high 1 D3L EQU 5 0000 DMA3 Interrupt Priority Level Mask 1 D3LO EQU 18 DMA3 Interrupt Priority Level low 1 0311 EQU 19 DMA3 Interrupt Priority Level high 1 EQU 300000 DMA4 Interrupt priority Level Mask 1 D4L0 EQU 20 DMA4 Interrupt Priority Level low 19411 EQU 21 DMA4 Interrupt Priority Level high DSL EQU 5 00000 DMA5 Interrupt priority Level Mask 1 D5LO EQU 22 DMA5 Interrupt Priority Level OW
68. 10 6 bit 7 Read Write Command bit R W 10 6 ODEC 10 8 OFO OF1 bits 7 15 offset adder 1 9 OGDBR register 10 20 OMACO comparator 10 11 comparator 10 11 OMAL register 10 11 OMBC counter 10 14 OMLRO register 10 11 OMLRI register 10 11 OMR register 1 11 OnCE 14 1 7 commands 10 23 controller 10 4 trace logic 10 15 OnCE Breakpoint Control Register OBCR 10 12 OnCE Command Register OCR 10 5 OnCE Decoder ODEC 10 8 OnCE GDB Register OGDBR 10 20 DSP56303UM AD I 7 OnCE Memory Address Comparator 0 10 11 OnCE Memory Address Comparator 1 10 11 Memory Address Latch register OMAL 10 11 OnCE Memory Breakpoint Counter OMBC 10 14 OnCE Memory Limit Register 0 OMLRO 10 11 OnCE Memory Limit Register 1 OMLR1 10 11 OnCE module 1 12 10 3 checking for Debug mode 10 24 displaying a specified register 10 26 displaying X data memory 10 26 interaction with JTAG port 10 29 polling the JTAG Instruction Shift register 10 24 reading the Trace buffer 10 25 returning to Normal mode 10 28 saving pipeline information 10 25 OnCE PAB Register for Decode Register OPABDR 10 20 OnCE PAB Register for Execute OPABEX 10 21 OnCE PAB Register for Fetch Register OPABFR 10 20 OnCE PIL Register OPILR 10 19 OnCE Program Data Bus Register OPDBR 10 19 OnCE Status and Control Register OSCR 10 8 OnCE Trace Counter OTC 10 16 OnCE JTAG debug event signal DE 2 37 test clock signal TCK 2 35
69. 15 6 12 6 5 5 Host Base Address Register HBAR 6 12 6 5 5 1 HBAR Base Address BA 10 3 Bits 0 7 6 12 6 5 5 2 HBAR Reserved Bits 8 15 6 12 6 5 6 Host Port Control Register HPCR 6 13 6 5 6 1 HPCR Host GPIO Port Enable HGEN Bit 0 6 13 iv DSP56303UM AD MOTOROLA 6 5 6 2 6 5 6 3 6 5 6 4 6 5 6 5 6 5 6 6 6 5 6 7 6 5 6 8 6 5 6 9 6 5 6 10 6 5 6 11 6 5 6 12 6 5 6 13 6 5 6 14 6 5 6 15 6 5 6 16 6 5 7 6 5 8 6 5 9 6 5 10 6 6 6 6 1 6 6 1 1 6 6 1 2 6 6 1 3 6 6 1 4 6 6 1 5 6 6 1 6 6 6 1 7 6 6 1 8 6 6 2 6 6 2 1 6 6 2 2 6 6 3 6 6 3 1 6 6 3 2 6 6 3 3 HPCR Host Address Line 8 Enable HA8EN Bit 1 6 13 HPCR Host Address Line 9 Enable HA9EN Bit 2 6 13 HPCR Host Chip Select Enable HCSEN Bit 3 6 14 HPCR Host Request Enable HREN Bit 4 6 14 HPCR Host Acknowledge Enable HAEN Bit5 6 14 HPCR Host Enable HEN Bit6 6 14 HPCR Reserved 7 6 14 HPCR Host Request Open Drain HROD Bit 8 6 14 HPCR Host Data Strobe Polarity HDSP Bit 9 6 15 HPCR Host Address Strobe Polarity HASP Bit 10 6 15 HPCR Host Multiplexed Bus HMUX Bit11 6 15 HPCR Host Dual Data Strobe HDDS Bit12 6 15 HPCR Host Chip Select Polarity HCSP Bit13 6 16 HPCR Host Request Polarity HRP Bit14 6 16 HPCR Host Acknowledge Polarity HAP Bit15 6 1
70. 17 PLL CONTROL REGISTER 4 18 AA CONTROL REGISTERS AAR1 AAR4 4 18 JTAG BOUNDARY SCAN REGISTER 4 19 DSP56303UM AD MOTOROLA Core Configuration Introduction 41 INTRODUCTION This chapter contains DSP56300 core configuration details specific to the DSP56303 These configuration details include Operating modes Bootstrap program Interrupt sources and priorities DMA request sources Operating Mode Register PLL control register AA control registers JTAG Boundary Scan Register For more information on specific registers or modules in the DSP56300 core refer to the DSP56300 Family Manual DSP56300FM AD 42 OPERATING MODES The DSP56303 begins operations by leaving Reset and going into one of eight operating modes As the DSP56303 exits the Reset state it loads the values of MODA MODB and MODD into bits MA MB MC and MD of the Operating Mode Register OMR These bit settings determine the chip s operating mode which determines what bootstrap program option the chip uses to start up The MA MD bits of the OMR can also be set directly by software Jumping directly to the bootstrap program entry point 0000 after setting the OMR bits causes the DSP56303 to execute the specified bootstrap program option except modes 0 and 8 Table 4 1 shows the DPS56303 bootstrap operation modes the corresponding settings of the external op
71. 3 Servicing Interrupts If either the HRRQ pin or both are connected to the host processor s interrupt input the HI08 can request service from the host processor by asserting one of these pins The and or the pin 55 asserted when TXDE is set and or RXDF is set and the corresponding enable bit TREQ or RREQ respectively is set This is depicted in Figure 6 16 is normally connected to the maskable interrupt input of the host processor The host processor acknowledges host interrupts by executing an interrupt service routine The two Least Significant Bits RXDF and TXDE of the ISR register may be tested by the host processor to determine the interrupt source see Figure 6 16 The host processor interrupt service routine must read or write the appropriate 108 data register to clear the interrupt HREQ HTRQ and or 15 deasserted under the following conditions The enabled request is cleared or masked or The DSP is reset If the host processor is a member of the MC68000 family there is no need for the additional step when the host processor reads the ISR to determine how to respond to an interrupt generated by the DSP56303 Instead the DSP56303 automatically sources the contents of the IVR on the data bus when the host processor acknowledges the interrupt by asserting HACK The contents of the IVR are placed on the host data bus while HREQ TRQ or HRRQ and HACK are sim
72. 6 5 3 4 HCR Host Flags 2 3 HF 3 2 Bits 3 4 on page 6 10 6 6 3 5 ISR Host Flag 3 HF3 Bit 4 The bit in the ISR indicates the state of Host Flag 3 in the HCR on the DSP side HF3 can be changed only by the DSP56303 see 6 5 3 4 HCR Host Flags 2 3 HF 3 2 Bits 3 4 on page 6 10 6 6 3 6 ISR Reserved Bits 5 6 These bits are reserved They are read as 0 and should be written with 0 6 6 3 7 ISR Host Request HREQ Bit 7 The HREQ bit indicates the status of the external transmit and receive request output pins HTRO and HRRO if HDRO is set If HDRO is cleared it indicates the status of the external Host Request output pin MOTOROLA DSP56303UM AD 6 27 Host Interface HI08 HI08 External Host Programmer s Model Table 6 11 HREO and HDRO Settings HDRQ HREQ Effect 0 0 HREQ is cleared no host processor interrupts are requested 0 1 is set an interrupt is requested 1 0 and are cleared no host processor interrupts requested 1 1 are set an interrupt is requested The HREQ bit may be set from either or both of two conditions either the Receive Byte Registers are full or the Transmit Byte Registers are empty These conditions are indicated by the ISR RXDF and TXDE status bits respectively If the interrupt source has been enabled by the associated request enable bit in the ICR HREQ is set if one or more of the t
73. 76 77 78 79 82 83 84 85 88 89 92 93 94 97 98 99 108 109 110 113 114 115 116 117 132 133 5 DSP56303 8501 Listing 5 11 144 attribute 5 TDI signal is true attribute SCAN OUT of DO signal is true attribute SCAN MODE of TMS signal is true attribute SCAN RESET of signal is true attribute SCAN CLOCK of TCK signal is 20 0e6 BOTH attribute INSTRUCTION LENGTH of DSP56303 entity is 4 attribute INSTRUCTION OPCODE of DSP56303 entity is EXTEST 0000 amp SAMPLE 0001 amp IDCODE 0010 amp CLAMP 0101 amp HIGHZ 0100 amp ENABLE ONCE 0110 amp DEBUG REQUEST 0111 amp BYPASS 1111 attribute INSTRUCTION CAPTURE of DSP56303 entity is 0001 attribute IDCODE REGISTER of DSP56303 entity is 0001 amp version 000110 amp manufacturer s use 0000000011 amp sequence number 00000001110 amp manufacturer identity IUS 1149 1 requirement attribute REGISTER ACCESS of DSP56303 entity is ONCE 8 ENABLE ONCE DEBUG REQUEST attribute BOUNDARY LENGTH of DSP56303 entity is 144 attribute BOUNDARY REGISTER of DSP56303 entity is
74. CRB ESSI Transmit 1 Enable TE1 Bit 15 CRB ESSI Transmit 0 Enable Bit 16 CRB ESSI Receive Enable RE Bit 17 CRB ESSI Transmit Interrupt Enable TIE Bit 18 CRB ESSI Receive Interrupt Enable RIE Bit 19 CRB ESSI Transmit Last Slot Interrupt Enable TLIE Bit 20 CRB ESSI Receive Last Slot Interrupt Enable RLIE Bit 21 CRB ESSI Transmit Exception Interrupt Enable TEIE Bit 22 CRB ESSI Receive Exception Interrupt Enable seer ch teat eee ee ee eee ee ESSI Status Register 55 58 SSISR Serial Input Flag 0 IFO Bit 0 DSP56303UM AD 7 27 7 27 7 27 7 28 vii 7 4 3 2 SSISR Serial Input Flag 1 IF1 Bit 1 7 28 7 4 3 3 SSISR Transmit Frame Sync Flag TFS Bit 2 7 28 7 4 3 4 SSISR Receive Frame Sync Flag RFS Bit3 7 28 7 4 3 5 SSISR Transmitter Underrun Error Flag TUE Bit 4 7 29 7 4 3 6 SSISR Receiver Overrun Error Flag ROE Bit 5 7 29 7 4 3 7 SSISR ESSI Transmit Data Register Empty IDE eerie ie EM TORRE 7 29 7 4 3 8 SSISR ESSI Receive Data Register Full RDF Bit 7 7 30 7 4 4 ESSI Receive Shift Register 7 33 7 4 5 ESSI Receive Data Register 7 33 7 4 6 ESSI Transmit Shift 7 33 7 4 7 ESSI Transmit Data Registers 7 34 7 4 8 ESSI Time Slot Register TSR 7 34 7 4 9 Transmit
75. Clock 0 1 0 0 4 Input Width Measurement Input Internal In this mode the timer counts the number of clocks that occur between opposite edges of an input signal Set the TE bit to clear the counter and enable the timer Load the timer s count value into the TLR After the first appropriate transition as determined by the INV bit occurs on the TIO input pin the counter is loaded with the TLR value on the first timer clock signal received either from the DSP56303 clock divided by two CLK 2 or from the prescaler clock input Each subsequent clock signal increments the counter If the INV bit is set the timer starts on the first high to low 1 to 0 signal transition on the TIO pin If the INV bit is cleared the timer starts on the first low to high 0 to 1 transition on the TIO pin When the first transition opposite in polarity to the INV bit setting occurs on the TIO pin the counter stops The TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set The value of the counter which measures the width of the TIO pulse is loaded into the TCR The TCR can be read to determine the external signal pulse width If the TRM bit is set the counter is loaded with the TLR value on the first timer clock received following the next valid transition occurring on the TIO input pin and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each
76. Control Register 6 26 Interrupt Vector Register 6 28 08 Host Request 6 33 ESSI Block uu prede arse Sr do 7 5 ESSI Control Register A CRA ESSIO X FFFFB5 ESSI1 5 7 9 ESSI Control Register B CRB ESSIO X FFFFB6 ESSIT 6 7 9 ESSI Status Register SSISR ESSIO X FFFFB7 ESSI1 7 7 9 ESSI Transmit Slot Mask Register A TSMA ESSIO X FFFFB4 ESSI1 4 7 9 ESSI Transmit Slot Mask Register B TSMB ESSIO X FFFFB3 ESSI1 7 10 DSP56303UM AD MOTOROLA Figure 7 7 Figure 7 8 Figure 7 9 Figure 7 10 Figure 7 11 Figure 7 12 Figure 7 13 Figure 7 14 Figure 7 15 Figure 7 16 Figure 7 17 Figure 7 18 Figure 7 19 Figure 7 20 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 MOTOROLA ESSI Receive Slot Mask Register A RSMA ESSIO X SFFFFB2 ESSI1 X FFFFA2 7 10 ESSI Receive Slot Mask Register B RSMB ESSIOOCSFFFEBI ESSH X FFFFA1 7 10 ESSI Clock Generator Functional Block Diagram 7 12 ESSI Frame Sync Generator Functional Block Diagram 7 13 CRB FSLO and FSL1 Bit Operation FSR 0 7 19 CRB SYN Bit
77. Control Register PCRE This input is 5 V tolerant TXD Output Input Discon Serial Transmit Data This signal transmits nected data from SCI Transmit Data Register Internally 1 Input Port E 1 The default configuration Or following reset is GPIO input PE1 When Output configured as PE1 signal direction is controlled through the SCI PRRE The signal can be configured as an SCI signal TXD through the SCI PCRE This input is 5 V tolerant SCLK Input Input Discon Serial Clock This is the bidirectional Output nected Schmitt trigger input signal providing the Internally input or output clock used by the transmitter and or the receiver PE2 Input Port E 2 The default configuration Or following reset is GPIO input PE2 When Output configured as PE2 signal direction is controlled through the SCI PRRE The signal can be configured as an SCI signal SCLK through the SCI PCRE This input is 5 V tolerant Note The Wait processing state does not affect the signal s state MOTOROLA DSP56303UM AD 2 33 Signal Connection Descriptions Timers 2 12 TIMERS Three identical and independent timers are implemented in the DSP56303 Each timer can use internal or external clocking and can interrupt the DSP56303 after a specified number of events clocks or can signal an external device after counting a specific number of internal events Table 2 15 Triple Timer Signals Signal Name Type State During R
78. DSP56303UM AD 7 7 Enhanced Synchronous Serial Interface ESSI ESSI Programming Model Table 7 1 ESSI Clock Sources ses Temas Source Out Source Asynchronous 0 0 0 EXT SCO EXT SCK 0 0 1 INT SCO EXT SCK 0 1 0 EXT SCO INT SCK 0 1 1 INT SCO INT SCK Synchronous 1 0 0 1 EXT SCK EXT SCK 1 1 0 1 INT SCK INT SCK 7 3 6 Serial Control Pin SC2 5510 5 02 5511 5 02 This is used for frame sync I O 5 2 is the frame sync for both the transmitter and receiver in Synchronous mode and for the transmitter only in Asynchronous mode The direction of this pin is determined by the SCD2 bit in the CRB When configured as an output this pin outputs the internally generated frame sync signal When configured as an input this pin receives an external frame sync signal for the transmitter in Asynchronous mode and for the receiver when in Synchronous mode SC2 may be programmed as a GPIO pin P2 when the ESSI SC2 function is not being used 74 ESSI PROGRAMMING MODEL The ESSI is composed of Two control registers CRA CRB One status register SSISR 7 8 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI ESSI Programming Model Three transmit data registers TX1 TX2 One receive data register RX Two transmit slot mask registers
79. Data Full RXDF ISR Bit 0 on the host side bits are cleared This transfer operation sets the RXDF and HTDE bits The DSP56303 may set the bit to cause a host transmit data interrupt when is set To prevent the previous data from being overwritten data should not be written to the HTX until the HTDE bit is set Note When writing data to a peripheral device there is a two cycle pipeline delay until any status bits affected by this operation are updated If the user reads any of those status bits within the next two cycles the bit will not reflect its current status See the DSP56300 Family Manual appendix B Polling a peripheral device for write for further details 6 5 3 Host Control Register HCR The HCR is a 16 bit read write control register used by the DSP core to control the 108 operating mode The HCR bits are described in the following paragraphs Initialization values for HCR bits are described in 6 5 9 DSP Side Registers After Reset on page 6 18 Reserved bits are read as 0 and should be written with 0 for future compatibility MOTOROLA DSP56303UM AD 6 9 Host Interface HI08 HI08 DSP Side Programmer s Model 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HF2 HCIE HTIE HRIE Reserved bit read as 0 should be written with 0 for future compatibility 0658 Figure 6 2 Host Control Register X FFFFC2 6 5 3 1
80. Description section Section 2 of this manual describes the special uses of these pins in detail There are five groups of these pins They can be controlled separately or as groups The groups are Port B sixteen GPIO pins shared with HI08 pins Port C six GPIO pins shared with the ESSIO pins Port D six GPIO pins shared with ESSI1 pins Port E three GPIO pins shared with the SCI pins Timers three GPIO pins shared with the Triple Timer pins 5 2 1 Port B Pins and Registers Each of the sixteen Port pins not used as a HI08 pin can be configured as a GPIO pin The GPIO functionality of Port B is controlled by three registers Host Control Register HCR Host Port GPIO Data Register HDR and Host Port GPIO Direction Register HDDR These registers are described in Section 6 of this document 5 2 2 Port C Pins and Registers Each of the six Port C pins not used as an ESSIO pin can be configured as a GPIO pin The GPIO functionality of Port C is controlled by three registers Port C Control Register PCRC Port C Direction Register PRRC and Port C Data Register PDRC These registers are described in Section 7 of this document MOTOROLA DSP56303UM AD 5 3 General Purpose I O Programming Model 5 2 3 Port D Pins and Registers Each of the six Port D pins not used as a ESSI1 pin can be configured as a GPIO pin The GPIO functionality of Port D is controlled by three registers Port D Contro
81. HDS Schmitt trigger input The polarity of the data strobe is programmable but is configured as active low HDS following reset Input Host Write Data When 108 is programmed to interface a double data strobe host bus and the HI function is selected this signal is the Host Write Data Strobe HWR Schmitt trigger input The polarity of the data strobe is programmable but is configured as active low HWR following reset Input or Port B 12 When 08 is configured as GPIO Output through the HPCR this signal is individually programmed as an input or output through the HDDR This input is 5 V tolerant This pin is electrically disconnected internally during Stop mode MOTOROLA DSP56303UM AD 2 21 Signal Connection Descriptions Host Interface HI08 Table 2 11 Host Interface Continued State Signal During ENS NE Type Reset or Signal Description Stop HCS Input Discon Host Chip Select When HI08 is programmed to nected interface a non multiplexed host bus and the HI Internally function is selected this signal is the Host Chip Select HCS input The polarity of the chip select is programmable but is configured active low HCS after reset HA10 Input Host Address 10 When 108 is programmed to interface a multiplexed host bus and the HI function is selected this signal is line 10 of the Host Address HA10 input bus PB13 Input or Port B 13 When the 08 is con
82. HFO HF1 6 11 Host Flag 0 bit 6 24 Host Flag 1 bit 6 24 Host Flag 2 and 3 bits HF2 HF3 6 10 Host Flag 2 bit HF2 6 27 Host Flag 3 bit HF3 6 27 Host GPIO Port Enable bit HGEN 6 13 Host Interface 1 15 2 3 2 16 2 18 2 19 2 22 6 3 MOTOROLA Host Little Endian bit HLEND 6 24 Host Multiplexed Bus bit HMUX 6 15 host port configuration 2 17 usage considerations 2 16 Host Port Control Register HPCR 6 13 host read data signal HRD HRD signal 2 20 host read write signal HRW 2 20 Host Receive Data Full bit HRDF 6 11 Host Receive Data Register HRX 6 9 Host Receive Interrupt Enable bit HRIE 6 10 Host Request Double 2 4 Single 2 4 Host Request Enable bit HREN 6 14 Host Request Open Drain bit HROD 6 14 Host Request Polarity bit HRP 6 16 host request signal HREQ HREQ 2 23 Host Status Register HSR 6 11 Host Transmit Data Empty bit HTDE 6 11 Host Transmit Data Register HTX 6 9 Host Transmit Interrupt Enable bit HTIE 6 10 Host Vector bits HV0 HV6 6 25 host write data signal HWR HWR 2 21 HPCR register 6 13 bit 0 Host GPIO Port Enable bit HGEN 6 13 bit 1 Host Address Line 8 bit HA8EN 6 13 bit 2 Host Address Line 9 bit HA9EN 6 13 bit 3 Host Chip Select Enable bit HCSEN 6 14 bit 4 Host Request Enable bit HREN 6 14 bit 5 Host Acknowledge Enable bit HAEN 6 14 bit 6 Host Enable bit HEN 6 14 bit 7 reserved bit 6 14 bit 8 Host Request Open Drain bit
83. Host Command Pending 0 1 Ready Host Flags Read Only Host Staus Register HSR X FFFFC3 Read Only Reset 2 Reserved Program as 0 Figure D 7 Host Control and Host Status Registers MOTOROLA DSP56303UM AD D 21 PROGRAMMING REFERENCE Application Date Programmer Sheet 3 of 6 15 8 7 6 5 4 3 2 1 0 BA10 BAY BA8 BA7 BA6 5 4 SEPT X FFFFC5 Reset 80 Host Request Open Drain Host GPIO Port Enable HDRQ HROD HREN HEW 0 GPIO Pins Disable 1 GPIO Pin Enable 0 0 1 0 1 1 Host Address Line 8 Enable 1 0 1 0 HA8 GPIO 1 HA8 HA8 1 1 1 Host Address Line 9 Enable Host Data Strobe Polarity HA9 GPIO 1 HA9 0 Strobe Active Low 1 Strobe Active High O HAS GPIO Host Address Strobe Polarity Host Chip Select Enable 0 Strobe Active Low 1 Strobe Active High 0 HCS HAIO GPIO 1 HCS HA10 if HMUX 0 Host Multiplexed Bus 1 HCS HA10 HC10 if HMUX 1 0 Nonmultiplexed 1 Multiplexed Host Dual Data Strobe Host Request Enable 0 Singles Stroke 1 Dual Stoke 0 HREQ HACK GPIO 1 gt HREQ HREQ if 0 Host Chip Select Polarity 0 HCS Active Low Host Acknowledge Enable HTRQ amp HRRQ Enable 0 2 HACK GPIO 1 HCS Active High If HDRQ amp HREN 1 HACK HACK Host Request Priority Host Enable HREQ Active Low 0 08 Disable HREQ Active High Pins
84. I O 5 Internal FFFOOO FFFOOO Reserved Internal Internal Reserved Reserved FFFOCO BOSE ROM r FF0000 FF0000 FF0000 External 001000 External External Internal 000800 000800 Program RAM Internal Internal 4K X data RAM 2K Y data RAM 2K 000000 000000 000000 Bit Settings Memory Configuration Program X Data Y Data Addressable sea GE RAM RAM RAM Cache Memory Size 0 0 0 4K 2K 2K None 16M 000 FFF 000 7FF 000 7FF 0557 Figure 3 1 Default Settings 0 0 0 3 10 DSP56303UM AD MOTOROLA Memory Configuration FFFFFF Program X Data FFFFFF FFFFFF Y Data Memory Maps Internal I O External I O RE Internal FFFOOO Reserved Internal Internal Reserved Reserved FFFOCO ont ROM FF0000 FF0000 FF0000 External 001000 External External 000C00 Internal 000800 000800 Internal Internal k X data RAM Y data RAM 2K 2K 000000 000000 000000 Bit Settings Memory Configuration Program X Data Y Data Addressable Se ae GE RAM RAM RAM Cache Memory Size 0 0 1 3K 2K 2K 1K 16M 000 BFF 000 7FF 000 7FF C00 0561 Figure 3 2 Instruction Cache Enabled 0 0 1 MOTOROLA DSP56303UM AD 3 11 Memory Configuration Memory Maps Program X Data Y Data SREEREE SFFFFFF Internal I O SFFFFFF External oe Internal FFFOOO 000 Reserve
85. I O Pin Port E Control Register PCRE X FFFF9F Read Write Reset 000000 Reserved Program as 0 Port E Control Register PCRE Transmitter Enable 0 Transmitter Disable 1 Transmitter Enable Idle Line Interrupt Enable 0 Idle Line Interrupt Disabled 1 Idle Line Interrupt Enabled Receive Interrupt Enable 0 Receive Interrupt Disabled 1 Idle Line Interrupt Enabled Transmit Interrupt Enable 0 Transmit Interrupts Disabled 1 Transmit Interrupts Enabled Timer Interrupt Enable 0 Timer Interrupts Disabled 1 Timer Interrupts Enabled SCI Timer Interrupt Rate 0 32 1 1 SCI Clock Polarity 0 Clock Polarity is Positive 1 Clock Polarity is Negative SCI Receive Exception Inerrupt 0 Receive Interrupt Disable 1 Receive Interrupt Enable Word Select Bits 0 0 0 8 bit Synchronous Data Shift Register Mode 001 Reserved 10 bit Asynchronous 1 Start 8 Data 1 Stop Reserved 11 bit Asynchronous 1 Start 8 Data Even Parity 1 Stop 11 bit Asynchronous 1 Start 8 Data Odd Parity 1 Stop 11 bit Multidrop 1 Start 8 Data Data Type 1 Stop Reserved SCI Shift Direction 0 LSB First 1 MSB First Receiver Wakeup Enable 0 receiver has awakened 1 Wakeup function enabled Wired Or Mode Select 1 Multidrop 0 Point to Point Send Break 0 Send break then revert 1 Continually send breaks Receiver Enable Wakeup Mode Select 0 Receiver Disabled 0 idle Line Wakeup 1
86. INPUT OUTPUT GPIO Describes the DSP56303 General Purpose Input Output GPIO capability and the programming model for the GPIO pins operation registers and control SECTION 6 HOST INTERFACE HI08 Describes 8 bit Host Interface HI08 including a quick reference to the HI08 programming model SECTION 7 ENHANCED SYNCHRONOUS SERIAL INTERFACE ESSI Describes the 24 bit Enhanced Synchronous Serial Interface ESSI which provides two identical full duplex UART style serial ports for communications with devices such as codecs DSPs microprocessors and peripherals implementing the Motorola Serial Peripheral Interface SPI SECTION 8 SERIAL COMMUNICATIONS INTERFACE SCI Describes the 24 bit Serial Communications Interface SCI a full duplex serial port for serial communication to DSPs microcontrollers or other peripherals such as modems or other RS 232 devices SECTION 9 TIMER MODULE Describes the three identical internal timers event counter devices SECTION 10 ON CHIP EMULATION MODULE Describes the On Chip Emulation OnCE module which is accessed through the JTAG port SECTION 11 JTAG PORT Describes the specifics of the JTAG port on the DSP56303 APPENDIX A BOOTSTRAP PROGRAM Lists the bootstrap code used for the DSP56303 APPENDIX B EQUATES Lists the equates I O SCI ESSI Exception Processing Timer DMA PLL BIU and Interrupts for the DSP56303
87. Interface 108 is a byte wide full duplex double buffered parallel port that can be connected directly to the data bus of a host processor The HI08 supports a variety of buses and provides glueless connection with a number of industry standard microcomputers microprocessors and DSPs The host bus can operate asynchronously to the DSP core clock so the 108 registers are divided into two banks The host register bank is accessible to the external host and the DSP register bank is accessible to the DSP core The 08 supports two classes of interfaces Host Processor Microcontroller MCU connection interface General Purpose I O GPIO port Pins not used as 108 port pins can be configured as General Purpose I O GPIO pins up to a total of 16 6 2 8 FEATURES This section lists the features of the host to DSP and DSP to host interfaces Further details are in Section 6 5 and Section 6 6 6 2 1 Host to DSP Core Interface Mapping Registers are directly mapped into eight internal X data memory locations Data word DSP56303 24 bit native data words are supported as are 8 bit and 16 bit words e Transfer modes DSP to host Host to DSP Host command MOTOROLA DSP56303UM AD 6 3 Host Interface HI08 08 Features 6 2 2 6 4 Handshaking protocols Software polled Interrupt driven Core DMA accesses Instructions Memory mapped registers allow the standard MOVE instr
88. PRRE register 8 28 PSR bit 7 11 R R W bit 10 6 R8 bit 8 15 RASO RASS signals 2 10 RCM bit 8 17 RD signal 2 10 RDF bit 7 30 bit 8 14 RE bit 7 26 8 10 read enable signal RD 2 10 Read Write Command bit R W 10 6 Receive Byte Registers RXH RXM RXL 6 28 Receive Clock Mode Source bit RCM 8 17 Receive Data Register RX 7 33 Receive Data Register Full bit RDF 7 30 Receive Data Register Full bit 8 14 Receive Data Register Full bit RXDF 6 26 Receive Data signal RXD 8 4 Receive Exception Interrupt Enable bit REIE 7 27 Receive Frame Sync Flag bit RFS 7 28 receive host request signal HRRO HRRO 2 24 Receive Interrupt Enable bit RIE 7 26 8 12 Receive Last Slot Interrupt Enable bit RLIE 7 27 Receive Request Enable bit RREQ 6 23 Receive Shift Register 7 33 Receive Slot Mask Registers RSMA RSMB 7 35 Received Bit 8 Address bit R8 8 15 Receiver Enable bit RE 8 10 Receiver Overrun Error Flag bit ROE 7 29 Receiver Wakeup Enable bit SBK 8 10 Register Select bits 50 54 10 5 1 10 DSP56303UM AD REIE bit 7 27 8 13 reserved bits in CRA register 7 11 7 13 7 14 in HBAR register bits 5 15 6 12 in HCR register bits 5 15 6 10 in HPC register bit 7 6 14 in HSR register bits 5 15 6 12 in ICR register bit 6 6 24 in ISR register bit 5 6 27 bit 6 6 27 in OBCR register bits 12 15 10 15 in OSCR register bit 5 bits 8 23 10 9 in TCSR register bits 3 10 14 16 19 22 23
89. RXH is located at address 5 RXM at 6 and RXL at 7 When data is written to the Receive Byte Register at host address 7 the Receive Data Register Full RXDF bit is set The host processor may program the RREO bit to assert the external HREO pin when RXDF is set This indicates that the 108 has a full word either 8 16 or 24 bits for the host processor The host processor may program the RREO bit to assert the external HREO pin when RXDF is set Asserting the pin informs the host processor that the receive byte registers have data to be read When the host reads the Receive Byte Register at host address 7 the RXDF bit is cleared 6 6 6 Transmit Byte Registers TXH TXM TXL The Transmit Byte Registers are viewed as three 8 bit write only registers by the host processor These registers are the Transmit High register the Transmit Middle register and the Transmit Low register TXL These registers send data to the high middle and low bytes respectively of the HRX register and are selected by the external host address inputs HA 2 0 during a host processor write operation If the HLEND bit in the ICR is set the TXH register is located at address 7 the register at 6 and the TXL register at 5 If the HLEND bit in the ICR is cleared the TXH register is located at address 5 the TXM register at 6 and the TXL register at 7 Data may be written into the Transmit Byte Registers when the Transm
90. Receiver Enabled 1 Address Bit Wakeup 16 15 14 13 12 11 10 9 8 Address X FFFF9C Read Write SCKP STIR TMIE TIE RIE TE WAKE SBK SSFTD WDS2 WDS1 L SCI Control Register zi Reserved Program as 0 SCI Control Register SCR Figure D 16 SCI Control Register SCR D 30 DSP56303UM AD MOTOROLA Application Overrun Error Flag 0 No error 1 Overrun detected Parity Error Flag 0 No error 1 Incorrect Parity detected Framing Error Flag 0 No error 1 No Stop Bit detected Received Bit 8 Data 1 Address PROGRAMMING REFERENCE Date Programmer Sheet 2 of 3 Idle Line Flag 0 Idle not detected 1 Idle State Receive Data Register Full 0 Receive Data Register Full 1 Receive Data Register Empty Transmitter Data Register Empty 0 Transmitter Data Register full 1 Transmitter Data Register empt Transmitter Empty 0 Transmitter full 1 Transmitter empty SCI Status Register SSR Address X FFFF93 Read Only Reset 000003 Reserved Program as 0 SCI Status Register SSR Clock Divider Bits CD11 0 CD11 CDO Rate 000 1 5001 2 002 3 Clock Divider Bits CD11 0 TX Clock Clock SCLK Pin Internal Internal Output Internal External Input External Internal Input External External Input Mode Synchronous Asynchronous Asynchronous only Asyn
91. Register PCRC FFBE FFFFBE Port C Direction Register PRRC FFBD FFFFBD Port C GPIO Data Register PDRC ESSI 0 FFBC FFFFBC ESSI 0 Transmit Data Register 0 FFBB FFFFBB ESSI 0 Transmit Data Register 1 TX01 FFBA FFFFBA ESSI 0 Transmit Data Register 2 TX02 FFB9 FFFFB9 ESSI 0 Time Slot Register TSRO FFB8 FFFFB8 ESSI 0 Receive Data Register FFB7 FFFFB7 ESSI 0 Status Register SSISRO 6 6 ESSI 0 Control Register 5 5 ESSI 0 Control Register FFB4 FFFFB4 ESSI 0 Transmit Slot Mask Register FFB3 FFFFB3 ESSI 0 Transmit Slot Mask Register 5 FFB2 FFFFB2 ESSI 0 Receive Slot Mask Register RSMAO FFB1 FFFFB1 ESSI 0 Receive Slot Mask Register RSMBO FFBO FFFFBO Reserved PORT D FFAF FFFFAF Port D Control Register PCRD FFAE FFFFAE Port D Direction Register PRRD FFAD FFFFAD Port C GPIO Data Register PDRD MOTOROLA DSP56303UM AD D 7 PROGRAMMING REFERENCE Table D 1 Internal I O Memory Map Continued Peripheral 4 Fon Register Name ESSI 1 FFAC FFFFAC ESSI 1 Transmit Data Register 0 TX10 FFAB FFFFAB ESSI 1 Transmit Data Register 1 TX11 FFAA FFFFAA ESSI 1 Transmit Data Register 2 TX12 FFA9 FFFFA9 ESSI 1 Time Slot Register TSR1 FFA8 FFFFA8 ESSI 1 Receive Data Register RX1 FFA7 FFFFA7 ESSI 1 Status Register
92. S24 TIMER 0 compare I TIMOOF EQU I 526 TIMER 0 overflow I I 528 TIMER 1 compare I TIMIOF EQU I 52 TIMER 1 overflow I TIM2C EQU I VEC S2C TIMER 2 compare I TIM2OF EQU I 52 TIMER 2 overflow ESSI Interrupts I SIORD EQU I VEC S30 ESSIO Receive Data I SIORDE EQU I_VEC S32 ESSIO Receive Data With Exception Status I SIORLS EQU I 534 ESSIO Receive last slot I SIOTD EQU I 536 ESSIO Transmit data I SIOTDE EQU I 538 ESSIO Transmit Data With Exception Status I SIOTLS EQU I 53 ESSIO Transmit last slot I SIIRD EQU 540 25511 Receive Data I SIIRDE I 542 25511 Receive Data With Exception Status I SIIRLS I 544 ESSI1 Receive last slot I 5 EQU I 546 25511 Transmit data I SIITDE EQU 48 5511 Transmit Data With Exception Status I SIITLS I VEC S 4A 5511 Transmit last slot SCI Interrupts I EQU I SCIRDE EQU I_SCITD EQU I 550 I VEC 52 I 554 I SCIIL EQU I 556 I SCITM I 558 SCI SCI SCI SCI SCI Receive Data Receive Data With Exception Status Transmit Data Idle Line Timer HOST Interrupts __HRDE EQU I_VEC 60 Host Receive Data Full I EQU I 562
93. SCR 8 8 SCI exceptions Receive Data 8 26 SCI pins RXD TXD SCLK 8 3 MOTOROLA SCI Receive Register SRX 8 19 SCI Receive with Exception Interrupt bit REIE 8 13 SCI Serial Clock signal SCLK 8 4 SCI Shift Direction bit SSFTD 8 9 SCI Status Register SSR 8 13 SCI Transmit Register STX STX register 8 20 SCK signal 7 5 5 2 27 SCK1 signal 2 31 SCKD bit 7 16 SCKP bit 8 12 SCLK signal 2 33 8 4 SCP bit 8 17 SCR register 8 8 bits 0 2 Word Select bits WDS0 WDS2 8 8 bit 3 SCI Shift Direction bit SSFTD 8 9 bit 4 Send Break bit SBK 8 9 bit 5 Wakeup Mode Select bit WAKE 8 9 bit 6 Receiver Wakeup Enable bit RWU 8 10 bit 7 Wired OR Mode Select bit WOMS 8 10 bit 8 Receiver Enable bit RE 8 10 bit 9 Transmitter Enable bit TE 8 11 bit 10 Idle Line Interrupt Enable bit 8 11 bit 11 Receive Interrupt Enable bit RIE 8 12 bit 12 Transmit Interrupt Enable bit TIE 8 12 bit 13 Timer Interrupt Enable bit TMIE 8 12 bit 14 Timer Interrupt Rate bit STIR 8 12 bit 15 SCI Clock Polarity bit 5 8 12 bit 16 SCI Receive with Exception Interrupt Enable bit REIE 8 13 Select SC1 as Transmitter 0 Drive Enable bit SSC1 7 14 Send Break bit SBK 8 9 Serial Clock signal SCK 7 5 serial clock signal 5 2 27 serial clock signal SCK1 2 31 serial clock signal SCLK 2 33 Serial Communication Interface SCI 2 33 Serial Communications Interface SCI 1 16 2 3 8 3 Se
94. The SCI consists of separate transmit and receive sections that can operate asynchronously with respect to each other A programmable baud rate generator provides the transmit and receive clocks An enable vector and an interrupt vector have been included so that the baud rate generator can function as a general purpose timer when it is not being used by the SCI or when the interrupt timing is the same as that used by the SCI 8 2 SCII O PINS Each of the three SCI pins RXD TXD and SCLK can be configured as either a General Purpose I O GPIO pin or as a specific SCI pin Each pin is independent of the others For example if only the TXD pin is needed the RXD and SCLK pins can be programmed for GPIO However at least one of the three pins must be selected as an SCI pin to release the SCI from reset SCI interrupts can be enabled by programming the SCI control registers before any of the SCI pins are programmed as SCI functions In this case only one transmit interrupt can be generated because the Transmit Data Register is empty The timer and timer interrupt operate when one or more of the SCI pins is programmed as an SCI pin MOTOROLA DSP56303UM AD 8 3 Serial Communication Interface SCI SCI Programming Model 8 2 1 Receive Data RXD This input pin receives byte oriented serial data and transfers the data to the SCI Receive Shift Register Asynchronous input data is sampled on the positive edge of the receive clock 1 x SCLK
95. This input is 5 V tolerant This pin is electrically disconnected internally during Stop mode MOTOROLA DSP56303UM AD 2 23 Signal Connection Descriptions Enhanced Synchronous Serial Interface 0 ESSIO Table 2 11 Host Interface Continued State Signal During ENS NE Type Reset or Signal Description Stop HACK Input Discon Host Acknowledge When HI08 is programmed HACK nected to interface a single host request host bus and the Internally HI function is selected this signal is the Host Acknowledge HACK Schmitt trigger input The polarity of the host acknowledge is programmable but is configured as active low HACK after reset HRRQ Output Receive Host Request When 108 15 HRRQ programmed to interface a double host request host bus and the HI function is selected this signal is the Receive Host Request HRRQ output The polarity of the host request is programmable but is configured as active low HRRQ after reset The host request may be programmed as a driven or open drain output PB15 Input or Port B 15 When the 08 is configured as GPIO Output through the HPCR this signal is individually programmed as an input or output through the HDDR This input is 5 V tolerant This pin is electrically disconnected internally during Stop mode Note 1 The Wait processing state does not affect the signal s state 29 ENHANCED SYNCHRONOUS SERIAL INTERFACE 0
96. Z amp 2 amp Z amp Z amp 2 amp r Z amp 1 2 amp 1 dis rslt Z amp C 9 DSP56303 8501 Listing C 10 DSP56303UM AD MOTOROLA APPENDIX D PROGRAMMING REFERENCE MOTOROLA DSP56303UM AD D 1 PROGRAMMING REFERENCE D 1 INTRODUCTION soot Em D 2 INTERNAL I O MEMORY D 3 INTERRUPT ADDRESSES AND SOURCES D 4 INTERRUPT PRIORITIES D 5 PROGRAMMING REFERENCE CENTRAL PROCESSOR eee ene a E Rn HOST INTERFACE HI08 ENHANCED SYNCHRONOUS SERIAL INTERFACE iz GN OD pastu nina is wana a mansa eran SERIAL COMMUNICATIONS INTERFACE TINIE S GENERAL PURPOSE D 2 DSP56303UM AD MOTOROLA PERIPHERAL ADDRESSES PROGRAMMING REFERENCE D 1 INTRODUCTION This section has been compiled as a reference for programmers It contains a table showing the addresses of all the DSP s memory mapped peripherals an exception priority table and programming sheets for the major programmable registers on the DSP The programming sheets are grouped in the following order central processor Phase Lock Loop PLL Host Interface H108 Enhanced Synchronous Serial Interface ESSI Serial Communication Interface SCI Timer and GPIO Each sheet provides ro
97. a 24 bit word specifying the address to start loading the program words and then 3 bytes forming 24 bit words for each program word to be loaded The program words will be stored in contiguous PRAM memory locations starting at the specified starting address After reading the program words program execution starts from the same address where loading started The Host Interface bootstrap load program may be stopped by setting the Host Flag 0 his will start execution of the loaded program from the specified starting address BOOT equ 5000000 this is the location in P memory on the external memory bus where the external byte wide EPROM would be located AARV equ D00409 AAR1 selects the EPROM as mapped as P from 5000000 to SDFFFFF active low SSR EQU SFFFF 93 SCI Status Register STXL EQU SFFFF95 SCI Transmit Data Register low SRXL EQU SFFFF98 SCI Receive Data Register low 1 SCCR EQU SFFFF 9B SCI Clock Control Register I SCR EQU SFFFF9C SCI Control Register PCRE EQU Port Control register EQU SFFFFF8 Address Attribute Register 1 HPCR EQU SFFFFCA Host Polarity Control Register HSR EQUSFFFFC3 Host Status Register
98. and asserting IROB to exit the Wait state MODB IROB can tolerate 5 V MOTOROLA DSP56303UM AD 2 15 Signal Connection Descriptions Host Interface HI08 Table 2 9 Interrupt and Mode Control Continued Signal Name Type State During Reset Signal Description MODC IROC Input Input Mode Select C External Interrupt Request C MODC IRQC is an active low Schmitt trigger input internally synchronized to CLKOUT MODC IRQC selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing MODA MODB MODC and MODD select one of sixteen initial chip operating modes latched into OMR when the RESET signal is deasserted If is asserted synchronous to CLKOUT multiple processors can be re synchronized using the WAIT instruction and asserting to exit the Wait state MODC IRQC can tolerate 5 V MODD IROD Input Input Mode Select D External Interrupt Request D MODD IROD is active low Schmitt trigger input internally synchronized to CLKOUT MODD IROD selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing MODA MODB MODC and MODD select one of sixteen initial chip operating modes lat
99. as 0 Should be Written with 0 for Future Compatibility 0695 Figure 8 8 Port E Control Register Note Hardware and software reset clear all PCR bits MOTOROLA DSP56303UM AD 8 27 Serial Communication Interface SCI GPIO Pins and Registers 8 5 2 Port E Direction Register PRRE The read write 24 bit PRRE controls the direction of SCI GPIO pins When port pin i is configured as GPIO PDCTi controls the port pin direction When PDCTi is set the GPIO port is configured as output When PDCTi is cleared the GPIO port pin i is configured as input 7 6 5 4 3 2 1 0 2 Direction Control Bits 1 Output 0 Input E Reserved Bit Read as 0 Should be Written with O for Future Compatibility AA0696 Figure 8 9 Port E Direction Register PRRE Note Hardware and software reset clear all PRR bits The following table describe the port pin configurations Table 8 4 Port Control Register and Port Direction Register Bits Functionality PDCIi Port Pin i Function 1 10 0 SCI 0 0 GPIO input 0 1 GPIO output 8 5 3 Port E Data Register PDRE The read write 24 bit PDRE is used to read or write data to or from SCI GPIO pins Bits PD 2 0 are used to read or write data from or to the corresponding port pins if they are configured as GPIO If a port pin i is configured as a GPIO input 8 28 DSP56303UM AD MOTOROLA Serial Communication Interfac
100. by the TA input or by the Bus Control Register BCR whichever is longer The BCR can be used to set the minimum number of wait states in external bus cycles In order to use the TA functionality the BCR must be programmed to at least one wait state A zero wait state access can not be extended by TA deassertion otherwise improper operation may result TA can operate synchronously or asynchronously depending on the setting of the TAS bit in the Operating Mode Register TA functionality may not be used while performing DRAM type accesses otherwise improper operation may result MOTOROLA DSP56303UM AD 2 11 Signal Connection Descriptions External Memory Expansion Port Port A Table 2 8 External Bus Control Signals Continued Signal Name Type State During Reset Stop or Wait Signal Description Output Output driven high deasserted Bus Request BR is an active low output never tri stated BR is asserted when the DSP requests bus mastership BR is deasserted when the DSP no longer needs the bus BR may be asserted or deasserted independent of whether the DSP56303 is a bus master or a bus slave Bus parking allows BR to be deasserted even though the DSP56303 is the bus master see the description of bus parking in the BB signal description The Bus Request Hole BRH bit in the BCR allows BR to be asserted under software control even though the DSP does not need
101. by writing to all the data registers of the enabled transmitters clears both TUE and the pending interrupt TEIE is cleared by either a hardware reset signal or a software reset instruction 7 4 2 23 CRB ESSI Receive Exception Interrupt Enable REIE Bit 23 When the REIE bit is set the DSP is interrupted when both RDF and ROE in the ESSI Status Register are set When REIE is cleared this interrupt is disabled The use of the receive interrupt is described in Section 7 5 3 Reading the Status Register followed by reading the Receive Data Register clears both ROE and the pending interrupt REIE is cleared by either a hardware reset signal or a software reset instruction 7 4 3 ESSI Status Register SSISR The SSISR see Figure 7 4 on page 7 9 is a 24 bit read only Status Register used by the DSP to read the status and serial input flags of the ESSI The meaning of the SSISR bits is described in the following paragraphs MOTOROLA DSP56303UM AD 7 27 Enhanced Synchronous Serial Interface ESSI ESSI Programming Model 7 4 3 1 SSISR Serial Input Flag 0 IFO Bit 0 The IFO bit is enabled only when SCO is an input flag and the Synchronous mode is selected 1 when SCO is programmed as ESSI in the Port Control Register PCR the SYN bit is set and TE1 and SCD0 bits are cleared The ESSI latches data present on the SCO pin during reception of the first received bit after the frame sync is detected The IFO bit is updated with this
102. can also examine these bits and determine the cause why the chip has not entered the Debug mode after debug event assertion DE or as a result of the execution of the JTAG Debug Request instruction core waiting for the bus STOP or WAIT instruction etc These bits are also reflected in the JTAG instruction shift register which allows the polling of the core status information at the JTAG level This is useful when the DSP56300 core executes the STOP instruction and therefore there are no clocks to allow the reading of OSCR See Table 10 5 for the definition of the OS0 OSI bits Table 10 5 Core Status Bits Description OS1 050 Description 0 0 DSP56300 core is executing instructions 0 1 DSP56300 core is in Wait or Stop 1 0 DSP56300 is waiting for bus 1 1 DSP56300 core is in Debug mode 10 4 3 8 Reserved Bits 8 23 Bits 8 23 are reserved for future use They are read as 0 and should be written with 0 for future compatibility MOTOROLA DSP56303UM AD 10 9 On Chip Emulation Module OnCE Memory Breakpoint Logic 10 5 OnCE MEMORY BREAKPOINT LOGIC Memory breakpoints can be set on program memory or data memory locations In addition the breakpoint does not have to be in a specific memory address but within an approximate address range of where the program may be executing This significantly increases the programmer s ability to monitor what the program is doing in real time The breakpoint logic
103. change thus minimizing system cost for applications that use the smaller address space See the DSP56300 Family Manual Section 6 4 for further information 3 1 1 Program Memory Space Program memory space consists of Internal program memory Program 4 K by default Bootstrap Program ROM 192 x 24 bit Optionally off chip memory expansion as much as 16 M in 24 bit mode and 64 K in 16 bit mode Optionally Instruction Cache 1 K formed from Program RAM Program memory space at locations FF00CO to FFFFFF is reserved and should not be accessed 3 1 2 Data Memory Spaces Data memory space is divided into X data memory and Y data memory to match the natural partitioning of DSP algorithms The data memory partitioning allows the MOTOROLA DSP56303UM AD 3 3 Memory Configuration Memory Spaces DSP56303 to feed two operands to the Data ALU simultaneously enabling it to perform a multiply accumulate operation in one clock cycle X and Y data memory are identical in structure and functionality except for the upper 128 words of each space The upper 128 words of X data memory are reserved for internal I O It is suggested that the programmer reserve the upper 128 words of Y data memory for external I O for further information see Section 3 1 2 1 and Section 3 1 2 2 X and Y data memory space each consist of Internal data memory X data RAM and Y data RAM the default size of each is 2 K but t
104. crystal frequency be chosen carefully An alternative to selecting the system clock to accommodate the SCI requirements is to provide an external clock to the SCI 8 4 3 SCI Initialization Example One way to initialize the SCI is described below as an example 1 2 5 The SCI should be in its individual reset state 0 Configure the control registers SCR SCCR according to the operating mode but do not enable neither transmitter TE 0 nor receiver RE 0 It is possible to set the interrupts enable bits that would be in use during the operation no interrupt occurs Enable the SCI by setting the PCR bits according to which pins will be in use during operation If transmit interrupt is not used write data to the transmitter If transmitter interrupt enable is set an interrupt is issued and the interrupt handler should write data into the transmitter SCI transmit request is serviced by DMA channel if it is programmed to service the SCI transmitter Enable transmitters TE 1 and receiver RE 1 according to usage Operation starts as follows For an internally generated clock the SCLK pin starts operation immediately after the SCI is enabled Step 3 above for Asynchronous modes In Synchronous mode the SCLK pin is active only while transmitting gated clock Data is received only when the receiver is enabled RE 1 and after the occurrence of the SCI receive sequence on the RXD pin as
105. data The CRA control bits are described in the following paragraphs see Figure 7 2 7 4 1 1 CRA Prescale Modulus Select PM 7 0 Bits 7 0 The PM 7 0 bits specify the divide ratio of the prescale divider in the ESSI clock generator A divide ratio from 1 to 256 PM 0 to FF may be selected The bit clock output is available at the transmit clock pin SCK and or the receive clock SCO pin of the DSP The bit clock output is also available internally for use as the bit clock to shift the Transmit and Receive Shift Registers The ESSI clock generator functional 7 10 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI ESSI Programming Model diagram is shown in Figure 7 9 is the DSP56303 core clock frequency the same frequency as the CLKOUT pin when that pin is enabled Careful choice of the crystal oscillator frequency and the prescaler modulus will allow the industry standard codec master clock frequencies of 2 048 MHz 1 544 MHz and 1 536 MHz to be generated Both the hardware reset signal and the software reset instruction clear PM 7 0 7 4 1 2 CRA Reserved Bits 8 10 These bits are reserved They are read as 0 and should be written with 0 7 4 1 3 CRA Prescaler Range PSR Bit 11 The PSR controls a fixed divide by eight prescaler in series with the variable prescaler This bit is used to extend the range of the prescaler for those cases where a slower bit clock is desired When PSR is set the fixed
106. data read can be performed by the host processor 2 If TXDE is set the Transmit Data Register is empty A data write can be performed by the host processor 3 If TRDY is set the Transmit Data Register is empty This implies that the Receive Data Register on the DSP side is also empty Data written by the host processor to the 108 is transferred directly to the DSP side 4 If HF2 and 0 depending on how the host flags have been used this may indicate that an application specific state within the DSP56303 has been reached Intervention by the host processor may be required 5 If HREQ is set the pin has been asserted and the DSP56303 is requesting the attention of the host processor One of the previous four conditions exists After the appropriate data transfer has been made the corresponding status bit is updated to reflect the transfer If the host processor has issued a command to the DSP56303 by writing to the CVR and setting the HC bit it can read the HC bit in the CVR to determine whether the command has been accepted by the interrupt controller in the DSP core When the command has been accepted for execution the HC bit is cleared by the interrupt controller in the DSP core 6 32 DSP56303UM AD MOTOROLA Host Interface HI08 Servicing the Host Interface Status 7 puer Host Request Asserted 0 E v Enable AA0672 Figure 6 16 HI08 Host Request Structure 6 7
107. decoded at four different addresses b Transmit Data Register 0694 Figure 8 7 SCI Programming Model Data Registers 8 3 4 1 SCI Receive Registers SRX Data bits received on the RXD pin are shifted into the SCI Receive Shift Register When a complete word has been received the data portion of the word is transferred to the byte wide SRX This process converts the serial data to parallel data and provides double buffering Double buffering provides flexibility to the programmer and increased throughput since the programmer can save and process the previous word while the current word is being received The SRX can be read at three locations as SRXL SRXM and SRXH When SRXL is read the contents of the SRX are placed in the lower byte of the data bus and the remaining bits on the data bus are read as Os Similarly when SRXM is read the contents of SRX are placed in the middle byte of the bus and when SRXH is read the contents of SRX are placed in the high byte with the remaining bits are read as Os Mapping SRX as described allows three bytes to be efficiently packed into one 24 bit word by ORing three data bytes read from the three addresses MOTOROLA DSP56303UM AD 8 19 Serial Communication Interface SCI SCI Programming Model The length and format of the serial word are defined by the WDS0 WDS1 WDS2 control bits in the SCR The clock source is defined by the Receive Clock Mode RCM select bit in the SCR In
108. described in the IEEE 1149 1 document the JTAG port requires a minimum of four pins to support TDI TDO TCK and TMS signals The DSP56300 family also provides the optional TRST pin On the DSP56303 the Debug Event DE signal is provided for use by the OnCE module and is described in Section 10 On Chip Emulation Module The pin functions are described in the following paragraphs 11 2 1 Test Clock TCK The Test Clock Input TCK pin is used to synchronize the test logic 11 2 2 Test Mode Select TMS The Test Mode Select Input TMS pin is used to sequence the test controller s state machine The TMS is sampled on the rising edge of TCK and it has an internal pullup resistor 11 2 3 Test Data Input TDI Serial test instruction and data are received through the Test Data Input TDI pin TDI is sampled on the rising edge of TCK and it has an internal pullup resistor 11 2 4 Test Data Output The Test Data Output pin is the serial output for test instructions and data TDO is tri stateable and is actively driven in the Shift IR and Shift DR controller states TDO changes on the falling edge of TCK 11 2 5 Test Reset TRST The Test Reset Input TRST pin is used to asynchronously initialize the test controller The TRST pin has an internal pullup resistor MOTOROLA DSP56303UM AD 11 5 JTAG Port TAP Controller 11 3 TAP CONTROLLER The TAP controller is responsible for interpreting the sequence o
109. first timer clock signal is received the counter is loaded with the TLR value The timer clock signal can be taken from either the DSP56303 clock divided by two CLK 2 or from the prescaler clock output Each subsequent clock signal increments the counter At the first appropriate transition of the external clock detected on the TIO pin the TCF bit in the TCSR is set and if the TCIE bit is set a compare interrupt is generated The counter halts The contents of the counter are loaded into the TCR The value of the TCR represents the delay between the setting of the TE bit and the detection of the first clock edge signal on the TIO pin The value of the INV bit determines whether a high to low 1 to 0 or low to high 0 to 1 transition of the external clock signals the end of the timing period If the INV bit is set a high to low transition signals the end of the timing period If INV is cleared a low to high transition signals the end of the timing period If the counter overflows the TOF bit is set and if TOIE is set an overflow interrupt is generated The counter contents can be read at any time by reading the TCR MOTOROLA DSP56303UM AD 9 23 Triple Timer Module Timer Modes of Operation 9 4 3 Pulse Width Modulation PWM Mode 7 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Kind TIO Clock 0 1 1 1 7 Pulse Width PWM Output Internal Modulation In this
110. frame sync word length 7 42 GPIO functionality 7 44 initialization 7 36 interrupts 7 37 Network mode 7 40 Normal mode 7 40 operating mode 7 36 operating modes 7 40 Port Control Register PCR 7 44 Port Data Register PDR 7 45 Port Direction Register PRR 7 45 programming model 7 8 synchronous operating mode 7 41 ESSI Control Register A CRA 7 10 ESSI Mode Select bit MOD 7 20 ESSI Receive Data Register RX 7 33 ESSI Receive Enable bit RE 7 26 ESSI Receive Exception Interrupt Enable bit REIE 7 27 ESSI Receive Interrupt Enable bit RIE 7 26 ESSI Receive Last Slot Interrupt Enable bit RLIE 7 27 ESSI Receive Shift Register 7 33 ESSI Receive Slot Mask Registers RSMA RSMB 7 35 ESSI Status Register SSISR 7 27 ESSI Time Slot Register TSR 7 34 ESSI Transmit 0 Enable bit 7 24 ESSI Transmit 1 Enable bit TE1 7 23 ESSI Transmit 2 Enable bit TE2 7 22 ESSI Transmit Data registers TX2 TX1 7 34 ESSI Transmit Exception Interrupt Enable bit TEIE 7 27 ESSI Transmit Interrupt Enable bit TIE 7 26 ESSI Transmit Last Slot Interrupt Enable bit TLIE 7 26 ESSI Transmit Shift Registers 7 33 MOTOROLA ESSI Transmit Slot Mask Registers TSMA TSMB 7 34 ESSIO 2 25 ESSIO GPIO 5 3 ESSI1 2 29 ESSI1 GPIO 5 4 EX bit 10 5 Exit Command bit EX 10 5 expanded mode 4 6 EXTAL 2 7 EXTAL signal 2 7 external address bus 2 8 external bus control 2 8 2 11 2 12 external clock crystal input 2 7 exte
111. if SCKP is cleared RXD can be configured as a GPIO pin PEO when the SCI RXD function is not being used 8 2 2 Transmit Data TXD This output pin transmits serial data from the SCI Transmit Shift Register Data changes on the negative edge of the asynchronous transmit clock SCLK if SCKP is cleared This output is stable on the positive edge of the transmit clock TXD can be programmed as a GPIO pin PE1 when the SCI TXD function is not being used 8 2 3 SCI Serial Clock SCLK This bidirectional pin provides an input or output clock from which the transmit and or receive baud rate is derived in the Asynchronous mode and from which data is transferred in the Synchronous mode SCLK can be programmed as a GPIO pin PE2 when the SCI SCLK function is not being used This pin can be programmed as PE2 when data is being transmitted on TXD since the clock does not need to be transmitted in the Asynchronous mode Because SCLK is independent of SCI data I O there is no connection between programming 2 pin as SCLK and data coming out the TXD pin 83 SCI PROGRAMMING MODEL The SCI programming model can be viewed as three types of registers e Control SCI Control Register SCR in Figure 8 1 SCI Clock Control Register SCCR in Figure 8 3 e Status SCI Status Register SSR in Figure 8 2 e Data transfer 8 4 DSP56303UM AD MOTOROLA Serial Communication Interface SCI SCI Programming Model SCI Receive Data Regi
112. indeterminate after reset 6 5 10 Host Interface DSP Core Interrupts The 108 may request interrupt service from either the DSP56303 or the host processor The DSP56303 interrupts are internal and do not require the use of an external interrupt pin When the appropriate interrupt enable bit in the HCR is set an interrupt condition caused by the host processor sets the appropriate bit in the HSR generating an interrupt request to the DSP56303 The DSP56303 acknowledges interrupts caused by the host processor by jumping to the appropriate interrupt service routine The three possible interrupts are 1 host command 2 transmit data register empty and 3 receive data register full Although there is a set of vectors reserved for host command use the host command can access any interrupt vector in the interrupt vector table The DSP interrupt MOTOROLA DSP56303UM AD 6 19 Host Interface HI08 HI08 External Host Programmer s Model service routine must read or write the appropriate 108 register e g clearing HRDF or HTDE to clear the interrupt In the case of host command interrupts the interrupt acknowledge from the DSP56303 program controller clears the pending interrupt condition DSP Core Interrupts Receive Data Full Transmit Data Empty Host Command Status 0667 Figure 6 11 5 Operation 6 6 1 08 HOST PROGRAMMER S MODEL The 108 has been designed to provide a simp
113. interrupt equate file is included c Load the exception vector table entry two word fast interrupt or jump branch to subroutine long interrupt _6 10 Configure interrupt trigger Preload transmit data a Enable and prioritize overall peripheral interrupt functionality 5011 0 b Enable peripheral and associated pins 5 0 Write data to all enabled transmit registers TX00 d Enable peripheral interrupt generating function CRB TEO e Enable specific peripheral interrupt CRBO TIE f Unmask interrupts at global level SR 11 0 1 The code to the left of the steps above gives an example configuring an ESSIO transmit interrupt using transmitter 0 2 The order of the steps is optional except that the interrupt trigger configuration must not be completed until the ISR configuration has been completed Since 2d may cause an immediate transmit without generating an interrupt the transmit data preload in 2c should be MOTOROLA DSP56303UM AD 7 39 Enhanced Synchronous Serial Interface ESSI Operating Modes performed before 2d to ensure valid data is sent in the first transmission 3 After the first transmit subsequent transmit values are typically loaded into TXnn by the ISR one value per register per interrupt Therefore if N items are to be sent from a particular TXnn the ISR will need to load the transmit register N 1 times 4 Steps d and
114. links all device signal pins into a single shift register The test logic implemented utilizing static logic design is independent of the device system logic More information on the JTAG port is provided in Section 11 JTAG Port The On Chip Emulation OnCE module provides a means of interacting with the DSP56300 core and its peripherals non intrusively so that a user can examine registers memory or on chip peripherals This facilitates hardware and software development on the DSP56300 core processor OnCE module functions are provided through the JTAG TAP pins More information on the OnCE module is provided in Section 10 On Chip Emulation Module 1 6 6 On Chip Memory The memory space of the DSP56300 core is partitioned into program memory space X data memory space and Y data memory space The data memory space is divided into X data memory and to Y data memory in order to work with the two Address ALUs and to feed two operands simultaneously to the Data ALU Memory space includes internal RAM and ROM and can be expanded off chip under software control More information on the internal memory is provided in Section 3 Memory Configuration Program RAM Instruction Cache X data RAM and Y data RAM size are programmable Table 1 2 Chip Memory Instruction Switch Program Instruction XData RAM Y Data RAM Cache Mode RAM Size Cache Size Size Size disabled disabled 4096 x 24 bit 0 2048 x 24 bit
115. may be set or cleared by the DSP core The values of HF 3 2 are reflected in the Interface Status Register ISR that is if they are modified by the DSP software the host processor can read the modified values by reading the ISR 6 10 DSP56303UM AD MOTOROLA Host Interface HI08 HI08 DSP Side Programmer s Model These two flags are not designated for a specific purpose but are general purpose flags They can be used individually or as encoded pairs in a simple DSP to host communication protocol implemented in both the DSP and the host processor software 6 5 3 5 HCR Reserved Bits 5 15 These bits are reserved They are read as 0 and should be written with 0 6 5 4 Host Status Register HSR The HSR is a 16 bit read only status register used by the DSP to read the status and flags of the HI08 It cannot be directly accessed by the host processor Reserved bits are read as 0 and should be written with 0 The initialization values for the HSR bits are described in 6 5 9 DSP Side Registers After Reset on page 6 18 The HSR bits are described in the following paragraphs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HCP HTDE HRDF Reserved bit read as 0 should be written with 0 for future compatibility 0659 Figure 6 3 Host Status Register HSR X FFFFC3 6 5 4 1 HSR Host Receive Data Full HRDF Bit 0 The HRDF bit indicates that th
116. mode the timer generates periodic pulses of a preset width Set the TE bit to clear the counter and enable the timer The value the timer is to count is loaded into the TPCR When first timer clock is received from either the DSP56303 internal clock divided by two CLK 2 or the prescaler clock output the counter is loaded with the TLR value Each subsequent timer clock increments the counter When the counter equals the value in the TCPR the TIO output pin is toggled and the TCF bit in the TCSR is set The contents of the counter are placed into the TCR If the TCIE bit is set a compare interrupt is generated The counter continues to be incremented on each timer clock If counter overflow has occurred the TIO output pin is toggled the TOF bit in TCSR is set and an overflow interrupt is generated if the TOIE bit is set If the TRM bit is set the counter is loaded with the TLR value on the next timer clock and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each timer clock This process is repeated until the timer is disabled by clearing the TE bit TIO signal polarity is determined by the value of the INV bit When the counter is started by setting the TE bit the TIO pin assumes the value of the INV bit On each subsequent toggling of the TIO pin the polarity of the TIO pin is reversed For example if the INV bit is set the TIO pin generates the following signal 1010 If the INV bit is cl
117. number is divided into two parts Core Number bits 21 17 and Chip Derivative Number bits 16 12 Motorola Semiconductor IsraeL MSIL Design Center Number is 000110 and DSP56300 core number is 00001 Once the IDCODE instruction is decoded it selects the ID register which is a 32 bit data register Since the Bypass register loads a logic 0 at the start of a scan cycle whereas the ID register loads a logic 1 into its Least Significant Bit examination of the first bit of data shifted out of a component during a test data scan sequence immediate following exit from Test Logic Reset controller state shows whether such a register is included in the design When the IDCODE instruction is selected the operation of the test logic has no effect on the operation of the on chip system logic as required by the IEEE 1149 1 standard 11 3 2 4 CLAMP B 3 0 0011 The CLAMP instruction is not included in the IEEE 1149 1 standard It is provided as a public instruction that selects the 1 bit Bypass register as the serial path between TDI and TDO while allowing signals driven from the component pins to be determined from the BSR During testing of ICs on PCB it may be necessary to place static guarding values on signals that control operation of logic not involved in the test The EXTEST instruction could be used for this purpose but since it selects the Boundary Scan Register the required guarding signals would be loaded as part of the complete serial data
118. of the following protocols Polling e Interrupts The host processor writes to the appropriate 108 register to reset the control bits an configure the HI08 for proper operation 6 7 1 08 Host Processor Data Transfer To the host processor the 108 looks like a contiguous block of Static RAM To transfer data between itself and HI08 the host processor performs the following steps 1 asserts HIO8 address to select the register to be read or written 2 selects the direction of the data transfer If it is writing the host processor sources the data on the bus 3 strobes the data transfer 6 7 2 Polling In the Polling mode of operation the pin is not connected to the host processor and HACK must be deasserted to insure IVR data is not being driven on H 7 0 when other registers are being polled If the HACK function is not needed the HACK pin can be configured as a GPIO pin see 6 5 6 Host Port Control Register HPCR on page 6 13 MOTOROLA DSP56303UM AD 6 31 Host Interface HI08 Servicing the Host Interface The host processor first performs a data read transfer to read the ISR see Figure 6 16 This allows the host processor to assess the status of the HI08 and perform the appropriate actions Generally after the appropriate data transfer has been made the corresponding status bit is updated to reflect the transfer 1 If RXDF is set the Receive Data Register is full and a
119. prescaler is bypassed When PSR is cleared the fixed divide by eight prescaler is operational see Figure 7 9 Note this definition is reversed from that of the 560xx SSI The maximum allowed internally generated bit clock frequency is the internal DSP56308 clock frequency divided by 4 the minimum possible internally generated bit clock frequency is the DSP56303 internal clock frequency divided by 4096 Both the hardware reset signal and the software reset instruction clear PSR MOTOROLA DSP56303UM AD 7 11 Enhanced Synchronous Serial Interface ESSI ESSI Programming Model Note The combination PSR 1 and PM 7 0 00 dividing by 2 may cause synchronization problems and should not be used TX 1 or FlagO Out In CRB TE1 CRB OFO SSISR IFO Sync Mode Sync Mode CRA WL2 0 Sync TX 1 or RX clk CRB SCDO Sync TX RX clk Async TX clk CRB SCKD I Note 1 is the DSP56300 Core internal CRA PSR CRA PM7 0 queer 2 ESSI internal clock range min 4096 0 Fosc 4 FconE Opposite 3 pin name is ESSI 0 or 1 from SSI AA0679 Figure 7 9 ESSI Clock Generator Functional Block Diagram 7 4 1 4 CRA Frame Rate Divider Control DC 4 0 Bits 16 12 The values of the DC 4 0 bits control the divide ratio for the programmable frame rate dividers used to generate the frame clocks In Network mode this ratio may
120. reaches a pre set value Set the TE bit to clear the counter and enable the timer The value to which the timer is to count is loaded into the TCPR The counter is loaded with the TLR value when the first timer clock signal is received The TIO pin is loaded with the value of the INV bit The timer clock signal can be taken from either the DSP56303 clock divided by two CLK 2 or from the prescaler clock output Each subsequent clock signal increments the counter When the counter matches the TCPR value the TCF bit in TCSR is set and a compare interrupt is generated if the TCIE bit is set The polarity of the TIO pin is inverted for one timer clock period If the TRM bit is set the counter is loaded with the TLR value on the next timer clock and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each timer clock This process is repeated until the TE bit is cleared disabling the timer The counter contents can be read at any time by reading TCR The value of the TLR sets the delay between starting the timer and the generation of the output pulse To generate successive output pulses with a delay of X clocks between signals the TLR value should be set to X 2 and the TRM bit should be set This process is repeated until the timer is disabled i e TE is cleared If the counter overflows the TOF bit is set and if TOIE is set an overflow interrupt is generated The counter contents can be re
121. selecting different length data words The ESSI data registers are 24 bits long The ESSI transmits 32 bit words either by duplicating the last bit 8 times when WL 2 0 100 or by duplicating the first bit 8 times when WL 2 0 101 The WL 2 0 bits are cleared by a hardware reset signal or by a software reset instruction Table 7 2 ESSI Word Length Selection WL2 WL1 WLO Number of Bits Word 0 0 0 8 0 0 1 12 0 1 0 16 0 1 1 24 1 0 0 32 valid data in the first 24 bits 1 0 1 32 valid data in the last 24 bits 1 1 0 Reserved 1 1 1 Reserved 7 4 1 8 CRA Select SC1 as Transmitter 0 Drive Enable SSC1 Bit 22 The SSC1 bit controls the functionality of the SC1 pin If SSC1 is set the ESSI is configured in Synchronous mode the CRB synchronous asynchronous bit SYN is set and transmitter 2 is disabled Transmit Enable TE2 0 then the SC1 pin acts as the driver enable of transmitter 0 while the SC1 pin is configured as output SCD1 1 This enables the use of an external buffer for the transmitter 0 output If SSC1 is cleared the ESSI is configured in Synchronous mode SYN 1 and transmitter 2 is disabled TE2 0 then the SC1 acts as the serial I O flag while the SC1 pin is configured as output SCD1 1 7 4 1 9 CRA Reserved Bit 23 This bit is reserved It is read as 0 and should be written with 0 7 14 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI
122. sequence when downloading the user program through an external port 1 Three bytes defining the number of 24 bit program words to be loaded 2 Three bytes defining the 24 bit start address to which the user program loads in the DSP56303 program memory 3 The user program three bytes for each 24 bit program word The three bytes for each data sequence must be loaded with the least significant byte first Once the bootstrap program completes loading the specified number of words it jumps to the specified starting address and executes the loaded program MOTOROLA DSP56303UM AD 4 5 Core Configuration Bootstrap Program 4 3 1 Mode 0 Expanded Mode Reset EN Mode MODD MODC MODB MODA Description Vector 0 0 0 0 0 C00000 Expanded mode The bootstrap ROM is bypassed and the DSP56303 starts fetching instructions beginning at address C00000 Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected 4 3 2 Mode 1 Bootstrap from Byte Wide External Memory Reset OR Mode MODD MODC MODB MODA Description Vector 1 1 0 0 1 0000 Bootstrap from byte wide memory at D00000 The bootstrap program loads instructions through Port A from external byte wide memory starting at 5000000 The SRAM memory access type is selected by the values in Address Attribute Register 1 AAR1 Thirty one 3
123. signal or a software reset instruction clears FSL 1 0 7 4 2 8 CRB Frame Sync Relative Timing FSR Bit 9 The FSR bit determines the relative timing of the receive and transmit frame sync signal in reference to the serial data lines for word length frame sync only When FSR is cleared the word length frame sync occurs together with the first bit of the data word of the first slot When FSR is set the word length frame sync occurs one serial clock cycle earlier i e simultaneously with the last bit of the previous data word MOTOROLA DSP56303UM AD 7 17 Enhanced Synchronous Serial Interface ESSI ESSI Programming Model Either a hardware reset signal or a software reset instruction clears FSR 7 4 2 9 CRB Frame Sync Polarity FSP Bit 10 The FSP bit determines the polarity of the receive and transmit frame sync signals When FSP is cleared the frame sync signal polarity is positive i e the frame start is indicated by the frame sync pin going high When FSP is set the frame sync signal polarity is negative i e the frame start is indicated by the frame sync pin going low Either a hardware reset signal or a software reset instruction clears FRB 7 4 2 10 CRB Clock Polarity CKP Bit 11 The CKP bit controls on which bit clock edge data and frame sync are clocked out and latched in If CKP is cleared the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge o
124. status bits are set to their Reset state However the contents of the SCR are not affected allowing the DSP program to reset the SCI separately from the other internal peripherals During individual reset internal DMA accesses to the data registers of the SCI are not valid and the data read will be unknown Stop processing state reset Executing the STOP instruction halts operation of the SCI until the DSP is restarted causing the SSR to be reset No other SCI registers are affected by the STOP instruction Table 8 3 illustrates how each type of reset affects each register in the SCI DSP56303UM AD MOTOROLA Serial Communication Interface SCI Operating Modes Table 8 3 SCI Registers after Reset Reset Type Bit Mnemonic Bit Number HW SW IR ST Reset Reset Reset Reset REIE 16 0 0 15 0 0 STIR 14 0 0 TMIE 13 0 0 TIE 12 0 0 RIE 11 0 0 ILIE 10 0 0 TE 9 0 0 SCR RE 0 0 WOMS 0 0 RWU 6 0 0 WAKE b 0 0 m SBK 4 0 0 SSFTD 3 0 0 WDS 2 0 2 0 0 0 R8 7 0 0 0 0 6 0 0 0 0 5 0 0 0 0 55 4 0 0 0 0 IDLE 3 0 0 0 0 RDRF 2 0 0 0 0 1 1 1 1 1 MOTOROLA DSP56303UM AD 8 23 Serial Communication Interface SCI Operating Modes Table 8 3 SCI Registers after Reset Continued Reset Type Register
125. stream shifted in both at the start of the test and each time a new test pattern is entered Since the CLAMP instruction allows guarding values to be applied using the Boundary Scan Register of the appropriate ICs while selecting their Bypass registers it allows much faster testing than does the EXTEST instruction Data in the boundary scan cell remains unchanged until a new instruction is shifted in or the JTAG state machine is set to its reset state The CLAMP instruction also asserts internal reset for the DSP56300 core system logic to force a predictable internal state while performing external boundary scan operations 11 3 2 5 HI Z B 3 0 0100 The HI Z instruction is not included in the IEEE 1149 1 standard It is provided as a manufacturer s optional public instruction to prevent having to backdrive the output pins during circuit board testing When HI Z is invoked all output drivers including the two state drivers are turned off i e high impedance The instruction selects the Bypass register The HI Z instruction also asserts internal reset for the 11 10 DSP56303UM AD MOTOROLA JTAG Port TAP Controller DSP56300 core system logic to force a predictable internal state while performing external boundary scan operations 11 3 2 6 ENABLE ONCE B 3 0 0110 The ENABLE ONCE instruction is not included in the IEEE 1149 1 standard It is provided as a public instruction to allow the user to perform system debug functions When t
126. test data input signal TDI 2 35 test data output signal TDO 2 36 test mode select signal TMS 2 36 port 2 3 On Chip Emulation OnCE module 1 12 On Chip Emulation module 10 3 on chip memory 1 12 program 3 6 X data RAM 3 6 Y data RAM 3 7 OPABDR register 10 20 OPABEX register 10 21 register 10 20 OPDBR register 10 19 Operating 4 3 operating mode 4 3 4 4 l 8 DSP56303UM AD bootstrap from byte wide external memory 4 6 bootstrap thorugh 108 68302 68360 4 9 bootstrap through ISA 4 7 bootstrap through 108 multiplexed 4 8 bootstrap through 108 non multiplexed 4 8 bootstrap through SCI 4 6 ESSI 7 36 7 40 expanded 4 6 expanded mode 4 9 Operating Mode Register OMR 1 11 operating modes 4 3 OPILR register 10 19 OR bit 8 14 050 051 bits 10 9 OSCR register 10 8 bit 0 Trace Mode Enable bit TME 10 8 bit 1 Interrupt Mode Enable bit IME 10 8 bit 2 Software Debug Occurrence bit SWO 10 8 bit 3 Memory Breakpoint Occurrence bit MBO 10 9 bit 4 Trace Occurrence bit TO 10 9 bit 5 reserved bit 10 9 bits 6 7 Status bits OS0 OS1 10 9 reserved bits bits 8 23 10 9 OTC counter 10 16 Overrun Error Flag bit OR 8 14 1 13 1 10 Parity Error bit PE 8 14 PBO PB7 signals 2 18 PB10 signal 2 19 PB11 signal 2 20 PB12 signal 2 21 PB13 signal 2 22 PB14 signal 2 23 PB15 signal 2 24 signal 2 18 PB9 signal 2 19 PC register
127. the Synchronous mode the start bit the eight data bits the address data indicator bit and or the parity bit and the stop bit are received in that order Data bits are sent LSB first if SSFTD is cleared and MSB first if SSFTD is set In Synchronous mode the synchronization is provided by gating the clock In either Synchronous or Asynchronous mode when a complete word has been clocked in the contents of the Shift Register can be transferred to the SRX and the flags FE PE and OR are changed appropriately Because the operation of the Receive Shift Register is transparent to the DSP the contents of this register are not directly accessible to the programmer 8 3 4 2 SCI Transmit Registers The Transmit Data Register is a one byte wide register mapped into four addresses as STXL STXM STXH and STXA In the Asynchronous mode when data is to be transmitted STXL STXM and STXH are used When STXL is written the low byte on the data bus is transferred to the STX When STXM is written the middle byte is transferred to the STX When STXH is written the high byte is transferred to the STX This structure makes it easy for the programmer to unpack the bytes in a 24 bit word for transmission TDXA should be written in the 11 bit Asynchronous Multidrop mode when the data is an address and it is desired that the ninth bit the address bit be set When STXA is written the data from the low byte on the data bus is stored in it The addre
128. the cache is enabled will cause conflicts To change the MS bit when CE is set 1 Clear CE 2 Change MS 3 Set CE 3 2 1 On Chip Program Memory Program RAM The on chip Program RAM consists of 24 bit wide high speed internal Static RAM occupying the lowest 4 K default 3 K 2 K or 1 K locations in the program memory space depending on the settings of the MS and CE bits The Program RAM default organization is sixteen banks of 256 24 bit words 4 K The upper eight banks can be configured as X data RAM and Y data RAM by setting the MS bit When the CE is set the upper 1 K of Program RAM is used as an internal Instruction Cache CAUTION While the contents of Program RAM are unaffected by toggling the MS bit the location of program data placed in the Program RAM Instruction Cache area changes after the MS bit is toggled since the cache always occupies the top most 1 K Program RAM addresses To preserve program data integrity do not set or clear the MS bit when the CE bit is set See Section 3 2 for the correct procedure 3 2 2 On Chip X Data Memory X Data RAM The on chip X data RAM consists of 24 bit wide high speed internal Static RAM occupying the lowest 2 K default or 3 K locations in the X memory space The size of the X data RAM depends on the setting of the MS bit default MS is cleared The X data RAM default organization is eight banks of 256 2 K 24 bit words Four banks of RAM can be switched from the Prog
129. the external command controller Upon exiting the Debug mode the counter is decremented after each execution of an instruction Interrupts are serviceable and all instructions executed including fast interrupt services and the execution of each repeated instruction cause the Trace Counter to be decremented Upon decrementing to 0 the DSP56300 core re enters the Debug mode the Trace Occurrence bit TO in the OSCR register is set the core Status bits OS 1 0 are set to 11 and the DE pin is asserted to indicate that the DSP56300 core has entered Debug mode and is requesting service The OnCE Trace Counter OTC is a 16 bit counter that can be read or written through the JTAG port If N instructions are to be executed before entering the Debug mode the Trace Counter should be loaded with N 1 The Trace Counter is cleared by hardware reset 10 7 METHODS OF ENTERING THE DEBUG MODE Entering the Debug mode is acknowledged by the chip by setting the Core Status bits OS1 and 050 and asserting the DE line This informs the external command controller that the chip has entered the Debug mode and is waiting for commands The DSP56300 core can disable the OnCE module if the ROM Security option is implemented If the ROM Security is implemented the OnCE module remains inactive until a write operation to the OGDBR is executed by the DSP56300 core 10 7 1 External Debug Request During RESET Assertion Holding the DE line asserted during the asser
130. the selection of either Synchronous or Asynchronous mode For Asynchronous mode this signal is the receiver frame sync I O For Synchronous mode this signal is used either for Transmitter 2 output or for Serial I O Flag 1 Port C 1 The default configuration following reset is GPIO input PC1 When configured as PC1 signal direction is controlled through PRRC The signal can be configured as ESSI signal 5 01 through PCRC This input is 5 V tolerant MOTOROLA DSP56303UM AD 2 25 Signal Connection Descriptions Enhanced Synchronous Serial Interface 0 ESSIO Table 2 12 Enhanced Synchronous Serial Interface 0 ESSIO Continued Signal Name Type State During Reset Stop Signal Description SC02 PC2 Input Output Input or Output Input Discon nected Internally Serial Control Signal 2 5 02 is used for frame sync I O SC02 is the frame sync for both the transmitter and receiver in Synchronous mode and for the transmitter only in Asynchronous mode When configured as an output this signal is the internally generated frame sync signal When configured as an input this signal receives an external frame sync signal for the transmitter and the receiver in synchronous operation Port C 2 The default configuration following reset is GPIO input PC2 When configured as PC2 signal direction is controlled through PRRCO The signal can be configured a
131. time slot If the TIE bit is set a DSP transmit data interrupt request is issued when TDE is set Hardware software ESSI individual and stop reset clear the TDE bit MOTOROLA DSP56303UM AD 7 29 Enhanced Synchronous Serial Interface ESSI ESSI Programming Model 7 4 3 8 SSISR ESSI Receive Data Register Full RDF Bit 7 The RDF bit is set when the contents of the Receive Shift Register are transferred to the Receive Data Register The RDF bit is cleared when the DSP reads the Receive Data Register If RIE is set a DSP receive data interrupt request is issued when RDF is set Hardware software ESSI individual and stop reset clear the RDF bit 7 30 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI ESSI Programming Model 23 16 15 87 0 ESSI Receive Data Register Receive High Byte Receive Middle Byte Receive Low Byte Read Only 7 0 7 07 0 7 0 Receive Low Byte i 7 0 16 Bit 23 16 15 8 Receive High Byte Receive Middle Byte i 7 0 7 Seria Receive Shift Register MSB LSB 8 bit Data 0 0 0 Least Significant Zero Fill LSB 12 bit Data LSB 16 bit Data LSB 24 bit Data Receive Reqist NOTES SU Receive Registers Data is received MSB first if SHFD 0 24 bit fractional format ALC 0 32 bit mode is not shown 23 16 15 87 0 ESSI Transmit Data Transmit High Byte Transmit Middle Byte Transmit Low Byte Register Write Only
132. time slots per frame If the TEIE bit is set a DSP transmit underrun error interrupt request is issued when the TUE bit is set Hardware software ESSI individual and stop reset clear TUE TUE can also be cleared by first reading the SSISR with the TUE bit set then writing to all the enabled Transmit Data Registers or to the TSR 7 4 3 6 SSISR Receiver Overrun Error Flag ROE Bit 5 The ROE bit is set when the Serial Receive Shift Register is filled and ready to transfer to the Receive Data Register RX but RX is already full i e the RDF bit is set If the bit is set a DSP receiver overrun error interrupt request issued when the ROE bit is set Hardware software ESSI individual and stop reset clear ROE ROE can also be cleared by reading the SSISR with the ROE bit set and then reading the RX 7 4 3 7 SSISR ESSI Transmit Data Register Empty TDE Bit 6 The TDE bit is set when the contents of the Transmit Data Register of every enabled transmitter are transferred to the Transmit Shift Register It is also set for TSR disabled time slot period in Network mode as if data were being transmitted after the TSR was written When set the TDE bit indicates that data should be written to all the TX registers of the enabled transmitters or to the TSR The TDE bit is cleared when the DSP56303 writes to all the Transmit Data Registers of the enabled transmitters or when the DSP writes to the TSR to disable transmission of the next
133. tri stated MOTOROLA DSP56303UM AD 2 13 Signal Connection Descriptions Interrupt and Mode Control 27 INTERRUPT AND MODE CONTROL The interrupt and mode control signals select the chip s operating mode as it comes out of hardware reset After RESET is deasserted these inputs are hardware interrupt request lines Table 2 9 Interrupt and Mode Control Signal Name Type State During Reset Signal Description RESET Input Input Reset RESET is an active low Schmitt trigger input Deassertion of RESET is internally synchronized to the clock out CLKOUT When asserted the chip is placed in the Reset state and the internal phase generator is reset The Schmitt trigger input allows a slowly rising input such as a capacitor charging to reset the chip reliably If RESET is deasserted synchronous to CLKOUT exact start up timing is guaranteed allowing multiple processors to start synchronously and operate together in lock step When the RESET signal is deasserted the initial chip operating mode is latched from the MODA MODB and MODD inputs The RESET signal must be asserted after power up RESET can tolerate 5 V 2 14 DSP56303UM AD MOTOROLA Signal Connection Descriptions Interrupt and Mode Control Table 2 9 Interrupt and Mode Control Continued Signal Name Type State During Reset Signal Description
134. which corresponds to an MF of one 4 7 2 PCTL XTAL Disable Bit XTLD Bit 16 The XTAL Disable bit XTLD controls the on chip crystal oscillator XTAL output The XTLD bit is cleared during DSP56303 hardware reset which means that the XTAL output pin is active permitting normal operation of the crystal oscillator 4 7 3 PCTL PreDivider Factor PDO PD3 Bits 20 23 The PreDivider Factor bits 0 define the predivision factor PDF that will be applied to the PLL input frequency The 0 bits are cleared during DSP56303 hardware reset which corresponds to a PDF of one 48 AA CONTROL REGISTERS AAR1 AARA The Address Attribute Register AAR is shown in Figure 4 5 There are four of these registers in the DSP56303 one for each AA pin 4 18 DSP56303UM AD MOTOROLA Core Configuration JTAG Boundary Scan Register BSR For a full description of the Address Attribute Registers see the DSP56300 Family Manual Address multiplexing is not supported by the DSP56303 Bit 6 BAM of the AARS is reserved and should have only 0 written to it 11 10 9 8 7 6 5 4 3 2 1 0 Ens suce BNCT NCO SVEN BXEN SPEN e BATO External Access Type AA pin polarity Program space Enable X data space Enable Y data space Enable Reserved Packing Enable Number of Address bit to compare 23 22 21 20 19 18 17 16 15 14 13 12 Address to Compar
135. 0 l S Chip select Base DSP Peripheral Address 8 Data Bus Register AA0666 Figure 6 5 Self Chip Select Logic 6 5 6 Host Port Control Register HPCR The is a 16 bit read write control register used by the DSP to control the HI08 operating mode Reserved bits are read as 0 and should be written with 0 for future compatibility The initialization values for the HPCR bits are described in Section 6 5 9 on page 6 18 The HPCR bits are described in the following paragraphs 15 14 13 12 1111019 8 7 6 5 4 3 2 1 0 HRP HCSP HDDS HMUX HASP HDSP HROD HEN HREN HCSEN HA9EN HABEN HGEN Reserved bit read as 0 should be written with 0 for future compatibility 0660 Figure 6 6 Host Port Control Register X FFFFC4 Note To assure proper operation of the DSP56303 the HPCR bits HAP HRP HCSP HDDS HMUX HASP HDSP HROD HAEN and HREN should be changed only if HEN is cleared Note To assure proper operation of the DSP56303 the HPCR bits HAP HRP HCSP HDDS HMUX HASP HDSP HROD HAEN HREN HCSEN HA9EN and HA8EN should not be set when is set or simultaneously with setting HEN 6 5 6 1 HPCR Host GPIO Port Enable HGEN Bit 0 If HGEN is set pins configured as GPIO are enabled If this bit is cleared pins configured as GPIO are disconnected outputs are high impedance inputs are electri
136. 0 ESSI Frame Sync Generator Functional Block Diagram 7 4 1 5 CRA Reserved Bit 17 This bit is reserved It is read as 0 and should be written with 0 7 4 1 6 CRA Alignment Control ALC Bit 18 The ESSI is designed for 24 bit fractional data Shorter data words are left aligned to the Most Significant Bit 5 Bit 23 For applications that use 16 bit fractional data shorter data words are left aligned to Bit 15 The ALC bit supports shorter data words If ALC is set received words are left aligned to Bit 15 in the Receive Shift Register Transmitted words must be left aligned to Bit 15 in the Transmit Shift Register If the ALC bit is cleared received words are left aligned to Bit 23 in the Receive Shift Register Transmitted words must be left aligned to Bit 23 in the Transmit Shift Register The ALC bit is cleared by either a hardware reset signal or a software reset instruction Note If the ALC bit is set only 8 12 or 16 bit words should be used The use of 24 or 32 bit words leads to unpredictable results MOTOROLA DSP56303UM AD 7 13 Enhanced Synchronous Serial Interface ESSI ESSI Programming Model 7 4 1 7 CRA Word Length Control WL 2 0 Bits 21 19 The WL 2 0 bits are used to select the length of data words being transferred via the ESSI Word lengths of 8 12 16 24 or 32 bits may be selected see Table 7 2 The ESSI data path programming model in Figure 7 16 and Figure 7 17 has additional information on
137. 1 FSLO 1 Serial Clock RX Frame SYNC TX Frame SYNC ____ Figure 7 11 CRB FSLO and FSL1 Bit Operation FSR 0 0681 DSP56303UM AD 7 19 Enhanced Synchronous Serial Interface ESSI ESSI Programming Model 7 4 2 12 CRB ESSI Mode Select MOD Bit 13 MOD selects the operational mode of the ESSI see Figure 7 13 on page 7 21 Figure 7 14 on page 7 22 and Figure 7 15 on page 7 23 When MOD is cleared the Normal mode is selected when MOD is set the Network mode is selected In the Normal mode the frame rate divider determines the word transfer rate one word is transferred per frame sync during the frame sync time slot In Network mode a word may be transferred every time slot For more details see Section 7 5 Either a hardware reset signal or a software reset instruction will clear MOD Asynchronous SYN 0 Transmitter External Transmit Frame SYNC Internal Frame SYNC External Receive Frame SYNC External Transmit Clock Internal Clock External Receive Clock Frame SYNC RECEIVER NOTE Transmitter and receiver may have different clocks and frame syncs SYNCHRONOUS SYN 1 Transmitter External Frame SYNC Internal Frame SYNC 4 Internal Clock Receiver NOTE Transmitter and receiver may have the same clock frame syncs 0682 Figure 7 12 CRB SYN Operation 7 20 DSP56303UM AD MOTOROL
138. 1 wait states are inserted between each memory access Address D00000 is reflected as address 00000 on Port A pins 7 4 3 3 Mode 2 Bootstrap Through SCI Reset ae Mode MODD MODC MODB MODA Description Vector 2 1 0 1 0 5 000 Bootstrap through SCI Instructions are loaded through the SCI The bootstrap program sets the SCI to operate in 10 bit Asynchronous mode with 1 start bit 8 data bits 1 stop bit and no parity Data is received in this order start bit 8 data bits Least Significant Bit first and one stop bit Data is aligned in the SCI Receive Data Register with the Least Significant Bit of the least significant byte of the received data appearing at bit 0 The DSP56303UM AD MOTOROLA Core Configuration Bootstrap Program user must provide an external clock source with a frequency at least 16 times the transmission data rate Each byte received by the SCI is echoed back through the SCI transmitter to the external transmitter 4 3 4 Mode 3 Reserved Mode MODD MODC MODB MODA 2 Description 3 1 0 1 1 Reserved This mode is reserved for future use 4 3 5 Mode 4 Bootstrap Through ISA DSP5630X Mode 8 Wide Bus Mode MODD MODB Reset Description Vector 4 1 1 0 0 5 000 108 Bootstrap in ISA DSP5630X In thi
139. 1 10 PCO signal 2 25 20 bits 9 9 1 signal 2 25 PC2 signal 2 26 MOTOROLA PC3 signal 2 27 PC4 signal 2 27 PC5 signal 2 28 PCAP signal 2 7 PCE bit 9 14 PCRC register 7 44 PCRD register 7 44 PCRE register 8 27 PCTL register bits 0 11 Multiplication Factor bits MFO MF11 4 18 bit 16 XTAL Disable bit XTLD 4 18 bits 20 23 PreDivider Factor bits PD0 PD3 4 18 PCU 1 10 PD bits 4 18 PDO signal 2 29 signal 2 29 PD2 signal 2 30 signal 2 31 signal 2 31 PD5 signal 2 32 PDB 1 13 PDC 1 10 PDRC register 7 45 PDRD register 7 45 PDRE register 8 28 PE bit 8 14 PEO signal 2 33 1 signal 2 33 PE2 signal 2 33 Peripheral I O Expansion Bus 1 13 PIC 1 10 PINIT NMI 2 8 PLL initial 2 8 PLO PL20 bits 9 7 PL21 PL22 bits 9 7 PLL 1 11 2 3 PLL capacitor signal 2 7 PLL initialize signal 2 8 PLL signals 2 7 7 bits 7 10 Port A 2 3 2 8 Port B 2 3 2 4 2 19 5 3 port B 10 signal PB10 2 19 port B 11 signal PB11 2 20 port B 12 signal PB12 2 21 port B 13 signal PB13 2 22 port B 14 signal PB14 2 23 port B 15 signal PB15 2 24 port B 8 signal PB8 2 18 MOTOROLA port B 9 signal PB9 2 19 port B signal PBO PB7 2 18 Port C 2 3 2 25 2 26 2 29 5 3 port C 0 signal 2 25 port C 1 signal PC1 2 25 port C 2 signal PC2 2 26 port C 3 signal PC3 2 27 port C 4 signal 2 27 port C 5 signal PC5 2 28 Port C Control Register PCRC 7 44 Port C Data Regist
140. 1 3 2 8 BYPASS 3 0 1111 11 11 11 4 DSP56300 RESTRICTIONS 11 12 11 5 DSP56303 BOUNDARY SCAN REGISTER 11 13 APPENDIX A BOOTSTRAP PROGRAMS A 1 APPENDIX 1 1 VO EQUATES ic eere ae 3 2 HOST INTERFACE 108 EQUATES B 3 B 3 SERIAL COMMUNICATIONS INTERFACE SCI EQUATES prem B 4 B 4 ENHANCED SYNCHRONOUS SERIAL INTERFACE ESSI EQUATES ch eux RE he a B 6 B 5 EXCEPTION PROCESSING 5 B 8 xiv DSP56303UM AD MOTOROLA 6 TIMER MODULE EQUATES B 9 B 7 DIRECT MEMORY ACCESS DMA EQUATES B 10 B 8 PHASE LOCKED LOOP PLL EQUATES B 12 B 9 BUS INTERFACE UNIT BIU EQUATES B 13 B 10 INTERRUPT EQUATES B 15 APPENDIX DSP56303 BSDL LISTING C 1 APPENDIX D PROGRAMMING REFERENCE D 1 D 1 INTRODUCTION ee D 3 D 1 1 Peripheral Addresses D 3 D 1 2 Interrupt Addresses D 3 D 1 3 Interrupt Priorities D 3 D 1 4 Programming Sheets D 3 D 2 INTERNAL I O MEMORY MAP D 4 D 3 INTERRUPT ADDRESSES AND SOURCES D 11 D 4 INTERR
141. 1 External Address Bus Table 2 6 External Address Bus Signals State Signal Burns 5 Reset Signal Description Name Stop or Wait 0 17 Output Tri stated Address Bus When the DSP is the bus master 0 17 are active high outputs that specify the address for external program and data memory accesses Otherwise the signals are tri stated To minimize power dissipation A0 A17 do not change state when external memory spaces are not being accessed 2 6 2 External Data Bus Table 2 7 External Data Bus Signals State Durin Signal Type Reset Signal Description Name Stop or Wait D0 D23 Input Tri stated Data Bus When the DSP is the bus master Output 00 023 are active high bidirectional input outputs that provide the bidirectional data bus for external program and data memory accesses Otherwise D0 D23 are tri stated MOTOROLA DSP56303UM AD 2 9 Signal Connection Descriptions External Memory Expansion Port Port A 2 6 3 External Bus Control Table 2 8 External Bus Control Signals State Sienal During 5 Reset Signal Description Name Stop or Wait AAO Output Tri stated Address Attribute or Row Address Strobe When defined as AA these signals can be used as chip RASO selects or additional address lines When defined as RAS3 RAS these signals can be used as RAS for Dynamic Random Access Memory DRAM interf
142. 10 15 ONCE TRACE LOGIC 10 15 METHODS OF ENTERING THE DEBUG MODE 10 16 External Debug Request During RESET Assertion 10 16 External Debug Request During Normal Activity 10 17 Executing the JTAG DEBUG REQUEST Instruction 10 17 External Debug Request During Stop 10 17 External Debug Request During Wait 10 17 Software Request During Normal Activity 10 18 Enabling Trace 10 18 Enabling Memory 5 10 18 PIPELINE INFORMATION AND OGDB REGISTER 10 18 OnCE PDB Register OPDBR 10 19 OnCE PIL Register OPILR 10 19 OnCE GDB Register OGDBR 10 20 TRACE BUFFER ataw ets set aqa 10 20 OnCE PAB Register for Fetch OPABFR 10 20 PAB Register for Decode OPABDR 10 20 OnCE PAB Register for Execute OPABEX 10 21 Trace Buffer ebd Pes a E E 10 21 SERIAL PROTOCOL DESCRIPTION 10 23 TARGET SITE DEBUG SYSTEM REQUIREMENTS 10 23 EXAMPLES OF USING THE ONCE 10 24 Checking Whether the Chip has Entered the Debug MOGG ote asas O et 10 24 Polling the JTAG instruction shift register 10 24 Saving Pipeline 10 25 Reading the Trace 10 25 Displaying a Speci
143. 1051 EQU 23 DMA5 Interrupt Priority Level high B 8 Interrupt Priority Register Peripheral IPRP DSP56303UM AD MOTOROLA Equates 1 HPL EQU 3 Host Interrupt Priority Level Mask I HPLO EQU 0 Host Interrupt Priority Level low 1 HPL1 EQU 1 Host Interrupt Priority Level high 1 SOL EQU 5 5510 Interrupt Priority Level Mask 1 SOLO EQU 2 5510 Interrupt Priority Level low 1 5011 EQU 3 SSIO Interrupt Priority Level high 1511 530 5511 Interrupt Priority Level Mask 15110 4 5511 Interrupt Priority Level low 1 5111 EQU 5 5511 Interrupt Priority Level high 1 SCL EQU SCO SCI Interrupt Priority Level Mask 1 SCLO EQU 6 SCI Interrupt Priority Level OW 15011 EQU 7 SCI Interrupt Priority Level high 1 TOL EQU 300 TIMER Interrupt Priority Level Mask 1 TOLO EQU 8 TIMER Interrupt Priority Level low 1 TOL1 EQU 9 TIMER Interrupt Priority Level high EQUATES for TIMER E Register Addresses Of TIMERO M TCSRO EQU S
144. 11 13 Internal O Memory D 4 Interrupt SOlIGOS ato be o ente e eee o D 11 Interrupt Source Priorities within D 13 DSP56303UM AD MOTOROLA MOTOROLA SECTION 1 DSP56303 OVERVIEW DSP56303UM AD DSP56303 Overview tk IE A LIE OMANDORWD 1 2 INTRODUCTIONS SEE Rue 1 3 MANUAL ORGANIZATION 1 3 MANUAL CONVENTIONS 1 5 05 56303 FEATURES 2m ace XP T RIEF eee 1 6 DSP56303 CORE DESCRIPTION 1 7 DSP56300 CORE FUNCTIONAL BLOCKS 1 8 INTERNAL BUSES cheat e ap 1 13 DSP56303 BLOCK DIAGRAM 1 14 DIRECT MEMORY ACCESS 1 15 DSP56303 ARCHITECTURE OVERVIEW 1 15 DSP56303UM AD MOTOROLA DSP56303 Overview Introduction 11 INTRODUCTION This manual describes the DSP56303 24 bit Digital Signal Processor DSP its memory operating modes and peripheral modules The DSP56303 is an implementation of the DSP56300 core with a unique configuration of on chip memory cache and peripherals This manual is intended to be used with the DSP56300 Family Manual DSP56300FM AD which describes the Central Processing Unit CPU core programming models and instruction set details DSP56303 Tech
145. 149 1 The HI Z public instruction provides the capability for disabling all device output drivers The ENABLE_ONCE public instruction enables the JTAG port to communicate with the OnCE circuitry The DEBUG_REQUEST public instruction enables the JTAG port to force the DSP56300 core into the Debug mode of operation The DSP56300 core includes a 4 bit instruction register without parity consisting of a shift register with four parallel outputs Data is transferred from the shift register to the parallel outputs during the Update IR controller state Figure 11 3 shows the JTAG Instruction Register JTAG Instruction Register IR 83 82 81 AA0746 Figure 11 3 JTAG Instruction Register The four bits are used to decode the eight unique instructions shown in Table 11 1 All other encodings are reserved for future enhancements and are decoded as BYPASS MOTOROLA DSP56303UM AD 11 7 JTAG Port TAP Controller Table 11 1 JTAG Instructions Instruction EXTEST SAMPLE PRELOAD IDCODE CLAMP HI Z RESERVED ENABLE ONCE DEBUG REQUEST RESERVED RESERVED RESERVED BYPASS The parallel output of the instruction register is reset to 0010 in the Test Logic Reset controller state which is equivalent to the IDCODE instruction During the Capture IR controller state the parallel inputs to the instruction shift register are loaded with 01 in the Least Significant Bits as req
146. 2 wD sss lh ue 320 2 0 e24nos 42015 513 857 L 1814 GSW 0 HUS ou S 4 XH XL 0 Su S 1 XL ou S 4 XH MIO uld 205 LOS 00S xaos andino 0 sig uonoeuig 0409 XOS lt XJO 1006 NAS 1ndino XL 0000008 19594 9 44439 LISSA aiqesiq 0 ejqeu3 e qeu a1qesiq 0 uondoeox3 0 lqeug 1016 1527 aiqeu ejqeu3 3 7 0 1016 1527 5 0 aiq eug 1dnui lul 0 aiqe e qeu 0 e qeu3 ELEM 0 jqeuz 0 0 L NAS qes q 0 Ajuo L NAS 5 0 SnouoJuSu S 19919 snouoiyoursy 0 j
147. 2 Select shift DR Shift out the 24 bit OPDB register Pass through update DR 3 Select shift DR Shift in the Read PIL Pass through update DR 4 Select shift DR Shift out the 24 bit OPILR register Pass through update DR Note that there is no need to verify acknowledge between steps 1 and 2 as well as 3 and 4 because completion is guaranteed by design 10 12 4 Reading the Trace Buffer An optional step during debugging activity is reading the information associated with the Trace buffer in order to enable an external program to reconstruct the full trace of the executed program Following is the description of the read Trace buffer procedure assume that all actions described in Saving Pipeline Information have been executed Select shift DR Shift in the Read PABFR Pass through update DR Select shift DR Shift out the 16 bit OPABFR register Pass through update DR Select shift DR Shift in the Read PABDR Pass through update DR Select shift DR Shift out the 16 bit OPABDR register Pass through update DR Select shift DR Shift in the Read PABEX Pass through update DR 6 Select shift DR Shift out the 16 bit OPABEX register Pass through update DR pss pa er dm gi MOTOROLA DSP56303UM AD 10 25 On Chip Emulation Module Examples of Using the OnCE 7 Select shift DR Shift in the Read FIFO Pass through update DR 8 Select shift DR Shift out the 17 bit FIFO register Pass through update DR 9
148. 2 Read Write Tm us Reserved Program as 0 Figure D 9 Interrupt Control and Interrupt Status Registers MOTOROLA DSP56303UM AD D 23 PROGRAMMING REFERENCE Application Date Programmer Sheet 5 of 6 iv7 ive 5 Interrupt Vector Register ae RENE Contains the interruptvectoror number Host Vector Contains Host Command Interrupt Address 2 Host Command Handshakes Executing Host Command Interrupt 7T 6 5 4143 2 1 0 5 HC4 HC3 2 Command Vector Register CVR aa Contains the host command interrupt addressr Figure D 10 Interrupt Vector and Command Vector Registers D 24 DSP56303UM AD MOTOROLA PROGRAMMING REFERENCE Application Date Programmer Sheet 6 of 6 Processor Side Host Receive Data usually Read by program 017 Receive Low Byte Receive Middle Byte Receive High Byte Not Used Receive Byte Registers 7 6 5 4 Read Only Reset 00 Receive Byte Registers Host Transmit Data usually loaded by program 017 Transmit Low Byte Transmit Middle Byte Transmit High Byte Transmit Byte Registers 7 6 5 4 Write Only Reset 00 Figure D 11 Host Receive and Host Transmit Data Registers MOTOROLA DSP56303UM AD D 25 Sheet 1 of 4 Programmer Date PROGRAMMING REFERENCE Application 0 se S 9 7 OL IL dl L VE SL 9L 2
149. 2 Reserved D 12 DSP56303UM AD MOTOROLA PROGRAMMING REFERENCE 0 4 INTERRUPT PRIORITIES Table D 3 Interrupt Source Priorities within an IPL Priority Interrupt Source Level 3 Nonmaskable Highest Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Lowest Non Maskable Interrupt Levels 0 1 2 Maskable Highest IRQA External Interrupt IROB External Interrupt IRQC External Interrupt IROD External Interrupt DMA Channel 0 Interrupt MA Channel 1 Interrupt MA Channel 2 Interrupt MA Channel 4 Interrupt D D DMA Channel 3 Interrupt D D MA Channel 5 Interrupt Host Command Interrupt Host Transmit Data Empty Host Receive Data Full ESSIO RX Data with Exception Interrupt MOTOROLA DSP56303UM AD D 13 PROGRAMMING REFERENCE Table D 3 Interrupt Source Priorities within an IPL Continued Priority Interrupt Source ESSIO RX Data Interrupt ESSIO Receive Last Slot Interrupt ESSIO TX Data With Exception Interrupt ESSIO Transmit Last Slot Interrupt ESSIO TX Data Interrupt ESSI1 RX Data With Exception Interrupt 55 RX Data Interrupt ESSI1 Receive Last Slot Interrupt 55 TX Data With Exception Interrupt ESSI1 Transmit Last Slot Interrupt ESSI1 TX Data Interrupt SCI Receive Data With Exception Interrupt SCI Receive Data S
150. 3UM AD 9 7 Triple Timer Module Triple Timer Module Programming Model If the prescaler source clock is external the prescaler counter is incremented by signal transitions on the TIO pin The external clock is internally synchronized to the internal clock The external clock frequency must be lower than the DSP56303 internal operating frequency divided by 4 CLK 4 The PS 1 0 bits are cleared by a hardware RESET signal or a software RESET instruction Note To ensure proper operation change the PS 1 0 bits only when the prescaler counter is disabled Disable the prescalar counter by clearing the TE bit in the TCSR of each of three timers Table 9 1 Prescaler Source Selection PS1 PSO PRESCALER CLOCK SOURCE 0 0 Internal CLK 2 0 1 TIOO 1 0 1 1 1 2 9 3 2 3 TPLR Reserved Bit 23 This reserved bit is read as 0 and should be written with 0 for future compatibility 9 3 3 Timer Prescaler Count Register TPCR The Timer Prescaler Count Register is a 24 bit read only register that reflects the current value in the prescaler counter The register bits are described below see Figure 9 5 23 22 21 20 19 18 17 16 15 14 13 12 PC20 19 PC18 17 PC16 15 14 13 PC12 11 10 9 8 7 6 5 4 3 2 1 0 11 PCIO 9 pcs pce pcs 2 reserved read as 0 should be
151. 5 If the transmit data register empty interrupt has been enabled the DSP is interrupted whenever a Transmit Data Register becomes empty Note When writing data to a peripheral device there is a two cycle pipeline delay until any status bits affected by this operation are updated If the user reads any of those status bits within the next two cycles the bit will not reflect its current status See the DSP56300 Family Manual appendix B Polling a peripheral device for write for further details 7 4 8 ESSI Time Slot Register TSR TSR is effectively a write only null data register that is used to prevent data transmission in the current transmit time slot For the purposes of timing TSR is a write only register that behaves like an alternative Transmit Data Register except that rather than transmitting data the transmit data pins of all the enabled transmitters are in the high impedance state for the current time slot 7 4 9 Transmit Slot Mask Registers TSMB The Transmit Slot Mask Registers are two 16 bit read write registers When the TSMA or TSMB is read to the internal data bus the register contents occupy the two low order bytes of the data bus and the high order byte is zero filled In Network mode these registers are used by the transmitter s to determine what action to take in the current transmission slot Depending on the setting of the bits the transmitter s either tri state the transmitter s data pin s or
152. 6 Host Data Direction Register HDDR 6 17 Host Data Register 6 17 DSP Side Registers After Reset 6 18 Host Interface DSP Core Interrupts 6 19 HIO8 EXTERNAL HOST PROGRAMMER S MODEL 6 20 Interface Control Register ICR 6 22 ICR Receive Request Enable RREQ Bit 0 6 23 ICR Transmit Request Enable TREQ Bit1 6 23 ICR Double Host Request Bit 2 6 23 ICR Host Flag 0 HFO Bit 3 6 24 ICR Host Flag 1 Bit4 6 24 ICR Host Little Endian HLEND Bit5 6 24 ICR Reserved Bit 6 6 24 ICR Initialize Bit INIT Bit7 6 24 Command Vector Register 6 25 CVR Host Vector HV 0 6 Bits 0 6 6 25 CVR Host Command Bit HC Bit 7 6 25 Interface Status Register ISR 6 26 ISR Receive Data Register Full RXDF BitO 6 26 ISR Transmit Data Register Empty TXDE Bit 1 6 26 ISR Transmitter Ready TRDY Bit2 6 27 MOTOROLA DSP56303UM AD 6 6 3 4 ISR Host Flag 2 2 6 27 6 6 3 5 ISR Host Flag 3 Bit4 6 27 6 6 3 6 ISR Reserved 55 6 6 27 6 6 3 7 ISR Host Request HREQ Bit 7 6 27 6 6 4 Interrupt Vector Register
153. 7 28 1 12 DSP56303UM AD bit 4 Transmitter Underrun Error Flag bit TUE 7 29 bit 5 Receiver Overrun Error Flag bit ROE 7 29 bit 6 Transmit Data Register Empty bit TDE 7 29 bit 7 Receive Data Register Full bit RDF 7 30 SSR register 8 13 bit 1 Transmitter Empty bit TRNE 8 13 bit 2 Receive Data Register Full bit 8 14 bit 2 Transmit Data Register Empty bit TDRE 8 13 bit 3 Idle Line Flag bit IDLE 8 14 bit 4 Overrun Error Flag bit OR 8 14 bit 5 Parity Error bit PE 8 14 bit 6 Framing Error Flag bit FE 8 15 bit 7 Received Bit 8 Address bit R8 8 15 Stack Counter register SC 1 11 Stack Pointer SP 1 11 standby mode Stop 1 7 Wait 1 7 Status Register SR 1 10 STD signal 7 4 STDO 2 28 STD1 2 32 STIR bit 8 12 stop standby mode 1 7 STX register read as STXL STXM STXH and STXA 8 20 SWO bit 10 8 SYN bit 7 18 System Stack SS 1 11 SZ register 1 11 T TA signal 2 11 TAP 1 11 TAP controller 11 6 TCO TC3 bits 9 10 TCF bit 9 14 TCIE bit 9 9 TCK pin 11 5 TCK signal 2 35 MOTOROLA TCM bit 8 18 TCPR register 9 15 TCR register 9 16 TCSR register 9 9 bit 0 Timer Enable bit TE 9 9 bit 1 Timer Overflow Interrupt Enable bit TOIE 9 9 bit 2 Timer Compare Interrupt Enable bit TCIE 9 9 bits 4 7 Timer Control bits TC0 TC3 9 10 bit 8 Inverter bit INV 9 11 bit 9 Timer Reload Mode bit TRM 9 13 bit 11 Direction bit DIR 9 13 bit 12 Data Input b
154. 9 15 in TPCR 9 9 in TPLR 9 8 RESET 2 14 reset signal 2 14 reverse carry adder 1 9 RFS bit 7 28 RIE bit 7 26 8 12 RLIE bit 7 27 ROE bit 7 29 ROM bootstrap 3 7 row address strobe signals RASO RAS3 2 10 RREQ bit 6 23 RSO RS4 bits 10 5 RSMA RSMB registers 7 35 RWO00 RWO I bits 10 12 RW10 RW11 bits 10 13 RWU bit 8 10 RX register 7 33 RXD 2 33 RXD signal 8 4 RXDF bit 6 26 RXH RXM RXL registers 6 28 S SAMPLE PRELOAD instruction 11 9 MOTOROLA SBK bit 8 9 SC register 1 11 SCO signal 7 6 7 8 SC00 signal 2 25 SC01 signal 2 25 SC02 signal 2 26 signal 7 7 SC10 2 29 SC11 2 29 5 12 2 30 SCCR register 8 15 bits 0 11 Clock Divider bits CD0 CD11 8 16 bit 12 Clock Out Divider bit COD 8 16 bit 13 SCI Clock Prescaler bit SCP 8 17 bit 14 Receive Clock Mode Source bit RCM 8 17 bit 15 Transmit Clock Source bit TCM 8 18 5 0 bit 7 16 SCD1 bit 7 16 SCD2 bit 7 16 SCI 1 16 2 33 exceptions 8 26 Idle Line 8 27 Receive Data 8 26 Receive Data with Exception Status 8 26 Timer 8 27 Transmit Data 8 26 GPIO functionality 8 27 initialization 8 24 example 8 25 operating mode Asynchronous 8 21 Synchronous 8 21 operating modes Asynchronous 8 21 programming model 8 4 reset 8 22 state after reset 8 23 transmission priority preamble break and data 8 26 SCI GPIO 5 4 SCI Clock Control Register 5 8 15 SCI Clock Polarity bit 5 8 12 SCI Clock Prescaler bit SCP 8 17 SCI Control Register
155. A Enhanced Synchronous Serial Interface ESSI ESSI Programming Model 890VV uoneredo COW T Z peuejsue eq e pue 1015 1900 3 LON 195 4 pue isenbeu JO 1dnueju i i i 195 4 pue isenbeu 10 sidnueju ONAS WEIJ 880 155 L GOW 9PON 00 5 ouAS aad eouo si ejep pue sidnueju 3 LON 195 4 pue isenbeu 10 1dnueju Jes 4 pue 10 0 GOIN Y geq euas ONAS 4 ees MOTOROLA DSP56303UM AD 7 21 Enhanced Synchronous Serial Interface ESSI ESSI Programming Model Frame SYNC 5569 FSLO 0 FSL1 0 Frame SYNC FSLO 0 FSL1 1 Slot 0 Wait Slot 0 0684 Figure 7 14 Normal Mode External Frame Sync 8 Bit 1 Word in Frame 7 4 2 13 Enabling and Disabling Data Transmission from ESSI The ESSI has three Transmit Enable bits TE 2 0 one for each data transmitter The process of transmitting data from TX1 and TX2 is the same can also operate in Asynchronous mode The normal transmit enable sequence is to write data to one or
156. APPENDIX C BSDL LISTING Provides the BSDL listing for the DSP56303 APPENDIX D PROGRAMMING REFERENCE Lists peripheral addresses interrupt addresses and interrupt priorities for the DSP56303 and contains programming sheets listing the contents of the major DSP56303 registers for programmer s reference 1 4 DSP56303UM AD MOTOROLA 1 3 DSP56303 Overview Manual Conventions MANUAL CONVENTIONS The following conventions are used in this manual Bits within registers are always listed from Most Significant Bit MSB to Least Significant Bit LSB Bits within a register are indicated AA n m n gt m when more than one bit is involved in a description For purposes of description the bits are presented as if they are contiguous within a register However this is not always the case Refer to the programming model diagrams or to the programmer s sheets to see the exact location of bits within a register When a bit is described as set its value is 1 When a bit is described as cleared its value is 0 The word assert means that a high true active high signal is pulled high to or that a low true active low signal is pulled low to ground The word deassert means that a high true signal is pulled low to ground or that a low true signal is pulled high to Vcc See Table 1 1 Table 1 1 High True Low True Signal Conventions Signal Symbol Logic State Signal State Voltage PIN True A
157. Address When HI08 is programmed to HAD7 Output interface a multiplexed host bus and the HI function is selected these signals are lines 0 7 of the Address Data bidirectional multiplexed tri state bus Input or PBO PB7 Output Port B 0 7 When the 108 is configured as GPIO through the HPCR these signals are individually programmed as inputs or outputs through the 108 Data Direction Register ADDR This input is 5 V tolerant This pin is electrically disconnected internally during Stop mode Input Discon Host Address Input 0 When the 08 is nected programmed to interface a non multiplexed host Internally bus and the HI function is selected this signal is line 0 of the Host Address input bus HAS HAS Input Host Address Strobe When HI08 is programmed to interface a multiplexed host bus and the HI function is selected this signal is the Host Address Strobe HAS Schmitt trigger input The polarity of the address strobe is programmable but is configured active low HAS following reset PB8 Input or Port B 8 When 08 is configured as GPIO Output through the HPCR this signal is individually programmed as an input or output through the HDDR This input is 5 V tolerant This pin is electrically disconnected internally during Stop mode 2 18 DSP56303UM AD MOTOROLA Signal Connection Descriptions Host Interface HI08 Table 2 11 Host Interface Continued Signal Name Ty
158. B asserted after ceasing bus activity regardless of whether BR is asserted or deasserted This is called bus parking and allows the current bus master to reuse the bus without re arbitration until another device requires the bus The deassertion of BB is done by an active pull up method i e BB is driven high and then released and held high by an external pull up resistor BB requires an external pull up resistor CAS Output Tri stated Column Address Strobe When the DSP is the bus master CAS is an active low output used by DRAM to strobe the column address Otherwise if the Bus Mastership Enable BME bit in the DRAM Control Register is cleared the signal is tri stated BCLK Output Tri stated Bus Clock When the DSP is the bus master BCLK is an active high output used by Synchronous Static Random Access Memory SSRAM to sample address data and control signals BCLK is active either during SSRAM accesses or as a sampling signal when the program Address Tracing mode is enabled by setting the ATE bit in the OMR When BCLK is active and synchronized to CLKOUT by the internal PLL BCLK precedes CLKOUT by one fourth of a clock cycle The BCLK rising edge may be used to sample the internal Program Memory access on the 0 23 address lines BCLK Output Tri stated Bus Clock Not When the DSP is the bus master is an active low output and 15 the inverse of the BCLK signal Otherwise the signal is
159. B IRQB MODC IRQC MODD IRQD RESET Non Multiplexed Multiplexed Port B Bus Bus GPIO H0 H7 HADO HAD7 PBO PB7 HAS HAS PB8 HA1 HA8 PB9 HA2 HA9 PB10 HCS HCS HA10 PB13 Single DS Double DS HRW HRD HRD PB11 HDS HDS HWR HWR PB12 Single HR Double HR HREQ HREQ HTRQ HTRQ 14 HACK HACK HRRQ HRRQ PB15 Port C GPIO SC00 SC02 PCO PC2 SCKO PC3 SRDO PC4 STDO PC5 Port D GPIO SC10 SC12 PDO PD2 SCK1 PD3 SRD1 PD4 STD1 PD5 Port E GPIO RXD PEO TXD PE1 SCLK PE2 Timer GPIO TIOO TIOO TIO1 TIO1 TIO2 TIO2 TCK TDI TDO TMS TRST DE The 108 port supports a non multiplexed or a multiplexed bus single or double Data Strobe DS and single or double Host Request HR configurations Since each these modes is configured independently any combination of these modes is possible These 108 signals can also be configured alternately as GPIO signals 0 15 Signals with dual designations e g HAS HAS have configurable polarity 2 The ESSIO ESSI1 and SCI signals are multiplexed with the Port C GPIO signals PCO PC5 Port D GPIO signals PDO PD5 and Port E GPIO signals 0 2 respectively 3 0 2 can be configured as GPIO signals AA0601 Figure 2 1 Signals Identified by Functional Group 2 4 DSP56303UM AD MOTOROLA Signal Connection Descriptions Power 2 2 POWER Table 2 2 Power Inputs Power Name Description PLL Power V cp is an isolated power dedicated for Phase Lock Loop
160. BE PRRD X FFFFAE Note Either a hardware reset signal or a software reset instruction clear all PRR bits The following table describes the port pin configurations Table 7 5 Port Control Register and Port Direction Register Bits Functionality Port Pin i Function 1 X ESSI 0 0 GPIO input 0 1 GPIO output Note X The pin setting is irrelevant to Port Pin i function T 6 3 Port Data Register PDR The read write 24 bit PDR is used to read or write data to and from the ESSI GPIO pins The PD 5 0 bits are used to read or write data from and to the corresponding port pins if they are configured as GPIO pins If a port pin i is configured as a GPIO MOTOROLA DSP56303UM AD 7 45 Enhanced Synchronous Serial Interface ESSI GPIO Pins and Registers input then the corresponding bit reflects the value present on this pin If a port pin i is configured as a GPIO output then the value written into the corresponding PD i bit is reflected on the this pin 7 6 5 4 3 2 1 0 _ Pos PD4 Pos Pp2 ppt Po STDn SRDn SCKn SCKn2 SCKn1 SCKnO PDRD ESSIO ESSI1 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 Reserved Bit Read As Zero Should Be Written With Zero For Future Compatibility 0690 Figure 7 20 Port Data Register PDRC X FFFFBD PDRD X FFFFAD Note Either a hardware reset signal or a software reset instruction clear all P
161. Bit 3 10 9 Trace Occurrence TO Bit4 10 9 Reserved OCSR Bit5 10 9 Core Status 050 OS1 Bits 6 7 10 9 Reserved Bits 8 23 10 9 ONCE MEMORY BREAKPOINT LOGIC 10 10 OnCE Memory Address Latch OMAL 10 11 OnCE Memory Limit Register 0 OMLRO 10 11 OnCE Memory Address Comparator 0 OMACO 10 11 OnCE Memory Limit Register 1 OMLR1 10 11 OnCE Memory Address Comparator 1 OMAC1 10 11 Breakpoint Control Register OBCR 10 12 Memory Breakpoint Select 50 51 Bits 0 1 10 12 Breakpoint 0 Read Write Select RWOO RW01 Bits 2 3 10 12 Breakpoint 0 Condition Code Select CC00 CCO01 Bits 4 10 13 Breakpoint 1 Read Write Select RW10 RW11 Bits 6 7 10 13 Breakpoint 1 Condition Code Select 10 11 Bits 8 59 10 14 DSP56303UM AD MOTOROLA 10 5 6 6 10 5 6 7 10 5 6 8 10 6 10 7 10 7 1 10 7 2 10 7 3 10 7 4 10 7 5 10 7 6 10 7 7 10 7 8 10 8 10 8 1 10 8 2 10 8 3 10 9 10 9 1 10 9 2 10 9 3 10 9 4 10 10 10 11 10 12 10 12 1 10 12 2 10 12 3 10 12 4 10 12 5 10 12 6 10 12 7 Breakpoint 0 and 1 Event Select BTO BT1 10 11 10 14 OnCE Memory Breakpoint Counter OMBC 10 14 Reserved Bits 12 15
162. CI Transmit Data SCI Idle Line SCI Timer TIMERO Overflow Interrupt TIMERO Compare Interrupt Overflow Interrupt TIMERI Compare Interrupt TIMER2 Overflow Interrupt Lowest TIMER2 Compare Interrupt D 14 DSP56303UM AD MOTOROLA Application Central Processor Unnormalized U Acc 47 xnor Acc 46 Extension Limit FFT Scaling 5 Acc 46 Acc 45 Interrupt Mask Scaling Mode 1 0 Exceptions Masked Scaling Mode 00 No scaling IPLO Scale down IPL 0 1 Scale up IPL 0 1 2 Reserved Reserved Sixteen Bit Compatibilitity Double Precision Multiply Mode Loop Flag DO Forever Flag Sixteenth Bit Arithmetic Reserved Instruction Cache Enable Arithmetic Saturation Rounding Mode Core Priority Core Priority 0 lowest 1 2 3 highest CM PROGRAMMING REFERENCE Date Programmer Sheet 1 of 5 Carry Overflow Zero Negative aie OT 23 22 21 20 19 18 17 16 15 14 13 12111109 8 7 6 5 413 2 1 0 FAEERE ole ore Welt Extended Mode Register MR Status Register SR Read Write Reset C00300 Mode Register MR ee Condition Code Register CCR Reserved Program as 0 Figure D 1 Status Register SR MOTOROLA DSP56303UM AD D 15 PROGRAMMING REFERENCE Application Date Programmer Sheet 2 of 5 Central P
163. CRE 8 27 8 5 2 Port E Direction Register PRRE 8 28 8 5 8 Port E Data Register 8 28 SECTION 9 TRIPLE TIMER MODULE 9 1 9 1 INTRODUCTION uman hot God iude nre vs 9 3 9 2 TRIPLE TIMER MODULE ARCHITECTURE 9 3 9 2 1 Triple Timer Module Block Diagram 9 3 9 2 2 Timer Block 9 4 9 3 TRIPLE TIMER MODULE PROGRAMMING MODEL 9 5 9 3 1 Prescaler 225 3 cette tue IEEE E 9 7 9 3 2 Timer Prescaler Load Register TPLR 9 7 9 3 2 1 TPLR Prescaler Preload Value PL 20 0 Bits 20 0 9 7 9 3 2 2 TPLR Prescaler Source PS 1 0 Bits 22 21 9 7 9 3 2 3 TPLR Reserved 123 9 8 9 3 3 Timer Prescaler Count Register TPCR 9 8 9 3 3 1 TPCR Prescaler Counter Value PC 20 0 Bits 20 0 9 9 9 3 3 2 TPCR Reserved Bits 23 21 9 9 9 3 4 Timer Control Status Register 9 9 9 3 4 1 Timer Enable 9 9 9 3 4 2 Timer Overflow Interrupt Enable TOIE Bit 1 9 9 9 3 4 3 Timer Compare Interrupt Enable TCIE Bit2 9 9 9 3 4 4 Timer Control TC 3 0 Bits 4 7 9 10 x DSP56303UM AD MOTOROLA 9 3 4 5 Inverter INV BI8 9 11 9 3 4 6 Timer Reload Mode TRM Bit9 9 13 9 3 4 7 D
164. C_2 Al4 Output 2 Data 32 BC_2 A13 Output 2 Data 33 BC 2 A12 Output 2 Data 34 BC 2 A11 Output 2 Data 35 BC 2 A10 Output 2 Data 36 BC 2 A9 Output 2 Data 37 BC 2 AB Output 2 Data 38 BC 2 A7 Output 2 Data 39 BC 2 A6 Output 2 Data DSP56303UM AD MOTOROLA JTAG Port DSP56303 Boundary Scan Register Table 11 2 DSP56303 Boundary Scan Register BSR Bit Definitions Continued Bit Cell Type Pin Name Pin Type BSR Cell Type 40 BC_2 A5 Output 2 Data 41 BC_2 A4 Output 2 Data 42 BC_2 A3 Output 2 Data 43 BC_2 A2 Output 2 Data 44 BC_2 Al Output 2 Data 45 BC_2 AO Output 2 Data 46 BC_2 MCS Output Data 47 BC 2 RD Output Data 48 BC 2 WR Output Data 49 BC 2 AT Output Data 50 2 CLKOUT Output Data 51 BC_1 EXTAL Input Data 52 _1 RESET Input Data 53 BC_1 HADO Control 54 _6 Input Output Data 55 BC_1 Control 56 BC_6 HAD1 Input Output Data 57 BC_1 HAD2 Control 58 BC 6 HAD2 Input Output Data 59 BC 1 HAD3 Control 60 BC 6 HADS3 Input Output Data 61 BC 1 HAD4 Control 62 BC 6 HAD4 Input Output Data 63 BC 1 HAD5 Control MOTOROLA DSP56303UM AD 11 15 JTAG Port DSP56303 Boundary Scan Register Table 11 2 DSP56303 Boundary Scan Register BSR Bit Definitions Continued 11 16 Bit Cell Type Pin Name Pin Type BSR Cell Type 64 _6
165. DR bits Esa 7 46 DSP56303UM AD MOTOROLA SECTION 8 SERIAL COMMUNICATION INTERFACE 5 MOTOROLA DSP56303UM AD 8 1 Serial Communication Interface SCI 8 1 8 2 8 3 8 4 8 5 8 2 INTRODUCTION SCIVO PINS 2 a ls kas SCI PROGRAMMING MODEL OPERATING MODES GPIO PINS AND REGISTERS DSP56303UM AD MOTOROLA Serial Communication Interface SCI Introduction 8 1 INTRODUCTION The DSP56303 s Serial Communications Interface SCI provides a full duplex port for serial communication to other DSPs microprocessors or peripherals such as modems The SCI interfaces without additional logic to peripherals that use TTL level signals With a small amount of additional logic the SCI can connect to peripheral interfaces that have non TTL level signals such as the RS232C RS422 etc This interface uses three dedicated pins Transmit Data TXD Receive Data RXD and SCI Serial Clock SCLK It supports industry standard asynchronous bit rates and protocols as well as high speed synchronous data transmission up to 8 25 Mbps for a 66 MHz clock The asynchronous protocols supported by the SCI include a Multidrop mode for master slave operation with Wakeup On Idle Line and Wakeup On Address Bit capability This mode allows the DSP56303 to share a single serial line efficiently with other peripherals
166. DSP 0 HROD 0H spare future compatibility HEN HEN should be cleared HAEN 0 Hos HREN 1 Hos HCSEN HA9EN HA8EN z no HGEN 0 Hos bra HIO8CONT HC11HOSTLD movep 50000001000011000 x M HPCR Configure the following conditions HAP 0 Negative host acknowledge A 6 DSP56303UM AD MOTOROLA HA8EN 0 address 8 enable bit has meaning in non multiplexed bus HGE 0 Host GPIO pins are disabled bra lt HIO8CONT I8051HOSTLD movep 50001110000011110 HPCR Configure the following conditions HAP 0 Negative host acknowledge HRP 0 Negative host request HCSP 0 Negative chip select input HD HS 1 Dual strobes bus RD and WR strobes HMUX 1 Multiplexed bus HASP 1 Positive address strobe polarity HDSP 0 Negative data strobes polarity HROD 0 Host request is active when enabled Spare 0 This bit should be set to 0 for future H compatibility HEN 0 When the HPCR register is modified HEN 7 should be cleared HAEN 0 Host acknowledge is disabled HRE 1 Host requests are enabled HCSEN 1 Host chip select input enabled HA9EN 1 Enable address 9 input HA8EN 1 Enable address 8 input HGE 0 Host GPIO pins are disabled bra lt HIO8CONT MC68302HOSTLD movep 0000000000111000 x M HPCR Configure the following conditions HAP 0 Negative host acknowledge HRP 0 Negative host request HCSP 0 Nega
167. EQU 22 Timer Control Bits TCO EQU 4 Timer Control 0 EQU 5 Timer Control 1 1 TC2 EQU 6 Timer Control 2 1 TC3 EQU 7 Timer Control 3 B 7 DIRECT MEMORY ACCESS DMA EQUATES gt EQUATES for Direct Memory Access DMA z Register Addresses Of DMA M DSTR EQU SFFFFF4 DMA Status Register M_DORO EQU SFFFFF3 DMA Offset Register 0 M DOR1 EQU SFFFFF2 DMA Offset Register 1 M DOR2 EQU SFFFFF1 DMA Offset Register 2 M DOR3 EQU SFFFFFO DMA Offset Register 3 Register Addresses Of DMAO M_DSRO EQU DMAO Source Address Register M DDRO EQU SFFFFEE DMAO Destination Address Register M EQU SFFFFED DMAO Counter M DCRO EQU SFFFFEC DMAO Control Register B 10 DSP56303UM AD MOTOROLA M DSR1 M DDR1 M DCO1 M DCR1 M DSR2 M DDR2 M DCO2 M DCR2 M DSR3 M DDR3 M DCO3 M DCR3 M_DSR4 M_DDR4 DCO4 M DCR4 M DSR5 M_DDR5 M DCO5 M DCR5 1 DSS 1 DSSO 1 DSS1 1 DDS 1 DDSO 1 DDS1 DAI DAI DAI DAM DAI DAI SO Equates Register Addresses Of DMA1 EQU SFFFFEB 1 Source Address Register EQU SFFFFEA Destination Address Register EQU SFFFFE9 DMA1 Counter EQU SFFFFE8 DMAIL Control Register Register Ad
168. ESSI Programming Model 7 4 2 ESSI Control Register B CRB The is one of two 24 bit read write control registers used to direct the operation of the ESSI see Figure 7 3 on page 7 9 CRB controls the ESSI multifunction pins SC 2 0 which can be used as clock inputs or outputs frame synchronization pins transmit data pins or serial I O flag pins The serial output flag control bits and the direction control bits for the serial control pins are in the ESSI CRB Interrupt enable bits for the receiver and the transmitter are also in the CRB The bit setting of the CRB also determines how many transmitters are enabled 0 1 2 or 3 transmitters can be enabled The CRB settings also determine the ESSI operating mode Either a hardware reset signal or a software reset instruction clear all the bits in the CRB The relationship between the ESSI pins SC 2 0 SCK and the CRB bits is summarized in Table 7 4 on page 7 24 The ESSI bits are described in the following paragraphs 7 4 2 1 CRB Serial Output Flags OF1 Bits 0 1 The ESSI has two serial output flag bits OF1 and The normal sequence for setting output flags when transmitting data by transmitter 0 through the STD pin only is 1 Wait for TDE empty to be set 2 Write the flags 3 Write the transmit data to the TX register Bits OF0 and OF1 are double buffered so that the flag states appear on the pins when the TX data is transferred t
169. ESSI individual or stop reset Note In Normal mode TFS is always read as 1 when transmitting data because there is only one time slot per frame the frame sync time slot 7 4 3 4 SSISR Receive Frame Sync Flag RFS Bit 3 When set the RFS bit indicates that a receive frame sync occurred during the reception of a word in the serial Receive Data Register This means that the data 7 28 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI ESSI Programming Model word is from the first time slot in the frame When the RFS bit is cleared and a word is received it indicates only in the Network mode that the frame sync did not occur during reception of that word RFS is valid only if the receiver is enabled i e the RE bit is set RFS is cleared by hardware software ESSI individual or stop reset Note In Normal mode RFS is always read as 1 when reading data because there is only one time slot per frame the frame sync time slot 7 4 3 5 SSISR Transmitter Underrun Error Flag TUE Bit 4 The TUE bit is set when at least one of the enabled Serial Transmit Shift Registers is empty no new data to be transmitted and a transmit time slot occurs When a transmit underrun error occurs the previous data which is still present in the TX registers that were not written will be retransmitted In the Normal mode there is only one transmit time slot per frame In the Network mode there can be up to thirty two transmit
170. F1 bit 7 28 ILIE bit 8 11 IME bit 10 8 INIT bit 6 24 Initialize bit INIT 6 24 instruction cache 3 3 location 3 8 instruction set 1 7 Interface Control Register ICR 6 22 Interface Status Register ISR 6 26 Interface Vector Register IVR 6 28 internal buses 1 13 interrupt 1 10 ESSI 7 37 6 19 priority levels 4 12 servicing 108 6 33 sources 4 9 interrupt and mode control 2 3 2 14 2 15 interrupt control 2 14 2 15 Interrupt Mode Enable bit IME 10 8 Interrupt Priority Register P IPR P 4 13 INV bit 9 11 Inverter bit INV 9 11 IPR P 4 13 ISR Host Request bit HREQ 6 27 ISR register 6 26 bit 0 Receive Data Register Full bit RXDF 6 26 bit 1 Transmit Data Register Empty bit 6 26 bit 2 Transmitter Ready bit TRDY 6 27 bit 3 Host Flag 2 bit HF2 6 27 bit 4 Host Flag 3 bit HF3 6 27 bit 5 reserved bit 6 27 bit 6 reserved bit 6 27 bit 7 ISR Host Request bit HREQ 6 27 reserved bits bits 5 6 6 27 IVR register 6 28 J Joint Test Action Group JTAG 11 3 JTAG 1 7 1 11 2 35 JTAG instructions BYPASS instruction 11 11 CLAMP instruction 11 10 DEBUG_REQUEST instruction 11 11 ENABLE_ONCE instruction 11 11 MOTOROLA EXTEST instruction 11 8 HI Z instruction 11 10 IDCODE instruction 11 9 SAMPLE PRELOAD instruction 11 9 JTAG OnCE Interface signals Debug Event signal DE signal 10 4 L LA register 1 10 LC register 1 11 logic 1 7 Loop Address register LA 1 10 Lo
171. FFFF8E TIMERO Control Status Register M TLRO EQU SFFFF8E TIMERO Load Reg M TCPRO SFFFF8D TIMERO Compare Register M TCRO EQU SFFFF8C TIMERO Count Register Register Addresses TIMER1 M TCSR1 EQU SFFFF8B Control Status Register SFFFF8A Load Reg M SFFFF89 Compare Register M_TCR1 EQU SFFFF88 TIMER1 Count Register Register Addresses TIMER2 M_TCSR2 EQU SFFFF87 TIMER2 Control Status Register M TLR2 EQU SFFFF86 TIMER2 Load Reg M TCPR2 EQU SFFFF85 TIMER2 Compare Register M TCR2 EQU SFFFF84 TIMER2 Count Register M TPLR EQU SFFFF83 TIMER Prescaler Load Register M TPCR EQU SFFFF82 TIMER Prescaler Count Register Timer Control Status Register Bit Flags MOTOROLA DSP56303UM AD B 9 Equates 1 EQU 0 Timer Enable 1 TOIE EQU ak Timer Overflow Interrupt Enable 1 TCIE 2 Timer Compare Interrupt Enable 1 TC EQU SFO Timer Control Mask TC 3 0 1 INV EQU 8 Inverter Bit 1 TRI EQU 9 Timer Restart Mode DIR EQU 11 Direction Bit DI EQU 12 Data Input 1 DO EQU 13 Data Output PCE EQU 15 Prescaled Clock Enable EQU 20 Timer Overflow Flag 21 Timer Compare Flag 4 Timer Register Bit Flags 1 5 EQU 5600000 Prescaler Source Mask 1 PSO EQU 21 1 PS1
172. HCR Host Receive Interrupt Enable HRIE Bit 0 When set the HRIE bit generates a host receive data interrupt request if the Host Receive Data Full HRDF bit in the Host Status Register HSR Bit 0 is set The HRDF bit is set when data is written to the HRX If HRIE is cleared HRDF interrupts are disabled 6 5 3 2 HCR Host Transmit Interrupt Enable HTIE Bit 1 When set the HTIE bit generates a host transmit data interrupt request if the Host Transmit Data Empty HTDE bit in the HSR is set The HTDE bit is set when data is read from the HTX If HTIE is cleared HTDE interrupts are disabled 6 5 3 3 HCR Host Command Interrupt Enable HCIE Bit 2 When set the HCIE bit generates a host command interrupt request if the Host Command Pending status bit in the HSR is set If HCIE is cleared HCP interrupts are disabled The interrupt address is determined by the host Command Vector Register CVR Note If more than one interrupt request source is asserted and enabled e g HRDF is set HCP is set HRIE is set and HCIE is set the 108 generates interrupt requests according to priorities shown in Table 6 4 Table 6 4 Host Command Interrupt Priority List Priority Interrupt Source Highest Host Command HCP 1 Transmit Data HTDE 1 Lowest Receive Data HRDF 1 6 5 3 4 HCR Host Flags 2 3 HF 3 2 Bits 3 4 HF 3 2 bits are used as a general purpose flags for DSP to host communication HF 3 2
173. HRX EQUSFFFFC6 Host Receive Register HRDE EQUSO Host Receive Data Full 20053 Host Flag 0 20056 Host Enable ORG PL Sf 0000 PL 0000 bootstrap code starts at Sff0000 START clr a 0a clear a and load with constant 0a0000 jclr 2 omr EPRSCILD 0 go load from EPROM SCI jclr 1 omr OMR1ISO MC MB MA 10x go to look for ISA HC11 options jclr 0 omr I8051HOSTLD If MC MB MA 110 go load from 8051 Host jmp MC68302HOSTLD MC MB MA 111 go load from MC68302 Host 1 150 jset 0 omr HC11HOSTLD MC MB MA 101 go load from 11 Host If MC MB MA 100 go load from ISA HOST This is the routine which loads a program through the HI08 host port MOTOROLA DSP56303UM AD A 5 Bootstrap Programs The program is downloaded from the host MCU with the following scenario 1 3 2 8 593 5 5 byt Define the program length byt Define the address to which to start loading the program to n bytes while n is any integer number The program words will be stored in contiguous PRAM memory locations starting at t he specified starting address After reading the program words program execution starts from the same address wher The When e loading started host MCU may terminate the loading process by setting the HF1 0 and HF0 1 the downloading is terminated th
174. Host Request Signal Pins 6 6 Host Command Interrupt Priority 81 6 10 HDR and HDDR Functionality 6 18 DSP Side Registers after Reset 6 19 Host Side Register 6 22 TREQ and RREQ modes 0 6 23 TREQ RREQ modes 1 6 23 INIT Command 6 24 HREQ and HDRQ Settings 6 28 Host Side Registers After Reset 6 30 DSP56303UM AD MOTOROLA Table 6 13 Table 7 1 Table 7 2 Table 7 3 Table 7 4 Table 7 5 Table 8 1 Table 8 2 Table 8 3 Table 8 4 Table 9 1 Table 9 2 Table 9 3 Table 10 1 Table 10 2 Table 10 3 Table 10 4 Table 10 5 Table 10 6 Table 10 7 Table 10 8 MOTOROLA 08 Programming 6 34 ESSI Clock Sources 7 8 ESSI Word Length Selection 7 14 FSL1 and FSL0 Encoding 7 17 Mode and Pin Definition Table 7 24 Port Control Register and Port Direction Register Bits Functionality EUR 7 45 Word a iud 8 8 TCM and RCM Bit Configuration 8 17 SCI Registers after
175. Host Transmit Data Empty I HC EQU I 564 Default Host Command INTERRUPT ENDING ADDRESS I INTEND EQU B 16 I last address of interrupt vector space DSP56303UM AD MOTOROLA APPENDIX DSP56303 BSDL LISTING MO TOR OE 15 D T JTAG 5 06 m ARE BSDL File Gefierated Mon Apr 8 10 13 47 1996 Revisa n History tity DSP56303 is generic PHYSICAL PIN MAP string TQFP144 port DE inout bit SC02 inout lole SCO1 inout Toss SC00 inout oiio STDO inout inout DSP56303UM AD C 1 DSP56303 8501 Listing C 2 DSP56303UM AD MOTOROLA DSP56303 BSDL Listing MOTOROLA S 9D JTAG SOFTWARI BSDL File Generated Mon Apr 8 10 13 47 1996 LH Revision History entity DSP56303 is generic PHYSICAL PIN MAP string TQFP144 port DE inou SC02 inou SCO1 inou SC00 inou STD0 inou SCK0 inou SRD0 inou SRD1 inou SCK1 inou STD1 inou SC10 inou SC11 inou SC12 inou TXD inou SCLK inou RXD inou TIO0 inou 1 inow TIO2 inou HAD inou EQ inou DD in bi MODC in bi DB in bi inout out EXTAL in XTAL linkage D ou WR ou AA ou BR_ bu BG_ in BB_ inout PCAP Linkage RESET_ in bi PINIT in bi TA_ in bi CAS_ out bi BCLK out bi BCLK out bi LKOUT buffer bi TRST in bi Ne Ne Ne Ne Ne Ne 9 S
176. I is in Network mode at the start of the last slot of the frame This exception occurs regardless of the Transmit Mask Register setting The transmit last slot interrupt may be used to signal that the Transmit Mask Slot Register can be reset the DMA channels can be reconfigured and data memory pointers can be reassigned Using the transmit last slot interrupt DSP56303UM AD MOTOROLA Note Enhanced Synchronous Serial Interface ESSI Operating Modes guarantees that the previous frame was serviced with the previous setting and the new frame will be serviced with the new setting without synchronization problems The maximum transmit last slot interrupt service time should not exceed N 1 ESSI bits service time where N is the number of bits in a slot ESSI Transmit Data Occurs when the transmit interrupt is enabled at least one of the enabled Transmit Data Registers is empty and no transmitter error conditions exist Writing to all the enabled TX registers or to the TSR clears this interrupt This error free interrupt may use a fast interrupt service routine for minimum overhead if no more than two transmitters are used To configure an ESSI exception perform the following steps 1 2 Notes Configure Interrupt Service Routine ISR a Load Vector Base Address Register VBA b23 8 b Define I_VEC to be equal to the VBA value if that is nonzero If it is defined I must be defined for the assembler before the
177. I08 External Host Programmer s Model Table 6 7 Host Side Register Host Little Endian Big Endian Address HLEND 0 HLEND 1 0 ICR ICR Interface Control 1 CVR CVR Command Vector 2 ISR ISR Interface Status 3 IVR IVR Interrupt Vector 4 00000000 00000000 Unused 5 RXH TXH RXL TXL Receive Transmit 6 RXM TXM RXM TXM Bytes 7 RXL TXL RXH TXH Host Data Bus Host Data Bus HO H7 HO H7 6 6 1 Interface Control Register ICR The ICR is an 8 bit read write control register used by the host processor to control 08 interrupts and flags The ICR cannot be accessed by the DSP core The ICR is a read write register which allows the use of bit manipulation instructions on control register bits The control bits are described in the following paragraphs 6 22 7 6 5 4 3 2 1 0 INIT HLEND TREQ RREQ Reserved bit Read as 0 Should be written with 0 for future compatibility 0668 Figure 6 12 Interface Control Register DSP56303UM AD MOTOROLA Host Interface HI08 HI08 External Host Programmer s Model 6 6 1 1 ICR Receive Request Enable RREQ Bit 0 The RREQ bit is used to control the HREQ pin for host receive data transfers RREQ is used to enable host requests via the Host Request HREQ or HRRQ pin when the Receive Data Register Full RXDF status bit in the ISR is set If RREQ is clear
178. IE EQU 23 SSI Receive Error Interrupt Enable SSI Status Register Bit Flags EQU 3 Serial Input Flag Mask IFO EQU 0 Serial Input Flag 0 1 1 Serial Input Flag 1 1 TES EQU 2 Transmit Frame Sync Flag RFS EQU 3 Receive Frame Sync Flag 1 TUE EQU 4 Transmitter Underrun Error FLag 1 5 Receiver Overrun Error Flag 1 TDF EQU 6 Transmit Data Register Empty 1 RDF EQU 7 Receive Data Register Full SSI Transmit Slot Mask Register M SSTSA SFFFF SSI Transmit Slot Bits Mask 50 515 H SSI Transmit Slot Mask Register B M SSTSB EQU SFFFF SSI Transmit Slot Bits Mask B TS16 TS31 SSI Receive Slot Mask Register A M SSRSA SFFFF SSI Receive Slot Bits Mask A RSO RS15 SSI Receive Slot Mask Register B M 55858 EQU SFFFF SSI Receive Slot Bits Mask B RS16 RS31 MOTOROLA DSP56303UM AD B 7 Equates 5 EXCEPTION PROCESSING EQUATES EQUATES for Exception Processing gt Register Addresses M IPRC EQU SFFFFFE Interrupt Priority Register Core M IPRP EQU SFFFFFE Interrupt Priority Register Peripheral Interrupt Priority Register Core IPRC IAL EQU 7 IRQA Mode Mask IALO EQU 0 Mode Interrupt Priority Level low 1 1 Mode Interrupt Priority Level high IAL2 EQU 2 Mode Trigger Mode IBL EQU 38 IROB Mode Mask
179. If HREN is set and 108 is in the Single Host Request mode is cleared in the host Interface Control Register ICR is configured as the Host Request HREQ output If HREN is cleared HREO HTRO and HACK HRRO are configured as GPIO pins according to the value of the HDDR and HDR If HREN is set in the Double Host Request mode HDRO is set in the ICR HREO HTRO is configured as the Host Transmit Request HTRQ output and HACK HRRQ as the Host Receive Request output If HREN is cleared HREO HTRO and HACK HRRO are configured as GPIO pins according to the value of the HDDR and HDR 6 5 6 6 HPCR Host Acknowledge Enable HAEN Bit 5 The HAEN bit controls the HACK pin In the Single Host Request mode HDRO is cleared in the ICR if HAEN and HREN are both set is configured as the Host Acknowledge HACK input If HAEN or HREN is cleared is configured as a GPIO pin according to the value of the HDDR and HDR In the double host request mode is set in ICR is ignored 6 14 DSP56303UM AD MOTOROLA Host Interface 108 HI08 DSP Side Programmer s Model 6 5 6 7 HPCR Host Enable HEN Bit 6 If HEN is set 108 operates as the Host Interface If HEN is cleared HI08 is not active and all the HI08 pins are configured as GPIO pins according to the value of the HDDR and HDR 6 5 6 8 HPCR Reserved Bit 7 This bit is reserved It is r
180. KKK KK KKK lt lt lt lt lt lt KKK EQUATES for 56303 I O registers ports Last update June 11 1995 KKK KKK KKK KKK KKK KK KKK KK KKK KK KKK KK KK KKK KKK KKK KKK KK KKK lt lt lt lt lt lt lt lt lt lt lt lt KKK KKK KKK KKK KK page 132 55 0 0 0 opt mex ioequ ident 1 0 EQUATES for I O Port Programming Register Addresses 1 HDR EQU SFFFFC9 Host port GPIO data Register 1 HDR EQU SFFFFC8 Host port GPIO direction Register EQU SFFFFBE Port C Control Register EQU SFFFFBE Port C Direction Register I PDRC EQU SFFFFBD Port C GPIO Data Register I PCRD EQU SFFFFAF Port D Control register PRRD EQU SFFFFAE Port D Direction Data Register PDRD EQU SFFFFAD Port D GPIO Data Register PCRE EQU SFFFF 9F Port E Control register SFFFF9E Port E Direction Register 1 PDRE EQU SFFFF9D Port E Data Register 1 OGDB EQU SFFFFFC OnCE GDB Register B 2 HOST INTERFACE HI08 EQUATES EQUATES for Host Interface Register Addresses M_HCR EQU SFFFFC2 Host Control Register M_HSR EQU SFFFFC3 Host Status Register MOTOROLA DSP56303UM AD B 3 Equates
181. L If more than one interrupt request is pending when an instruction is executed the interrupt source with the highest IPL is serviced first When several interrupt requests having the same IPL are pending another fixed priority structure within that IPL determines which interrupt source is serviced first This fixed priority list of interrupt sources within an IPL is shown in Table 4 4 Table 4 4 Interrupt Source Priorities within an IPL Priority Interrupt Source Level 3 Nonmaskable Highest Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Lowest Non Maskable Interrupt Levels 0 1 2 Maskable Highest IRQA External Interrupt IROB External Interrupt External Interrupt IRQD External Interrupt DMA Channel 0 Interrupt MA Channel 1 Interrupt MA Channel 2 Interrupt MA Channel 4 Interrupt D D DMA Channel 3 Interrupt D D MA Channel 5 Interrupt 4 14 DSP56303UM AD MOTOROLA Core Configuration Interrupt Sources and Priorities Table 4 4 Interrupt Source Priorities within an IPL Continued Priority Interrupt Source Host Command Interrupt Host Transmit Data Empty Host Receive Data Full ESSIO RX Data with Exception Interrupt ESSIO RX Data Interrupt ESSIO Receive Last Slot Interrupt ESSIO TX Data With Exception Interrupt ESSIO Transmit Last Slot Inter
182. Load Register TPLR is a 24 bit read write register that controls the prescaler divide factor i e the number that the prescaler counter will load and begin counting from and the source for the prescaler input clock The control bits are described below see Figure 9 4 23 22 21 20 19 18 17 16 15 14 13 12 PS1 PSO PL20 PL19 PL18 PL17 PL16 PL15 PL14 PL13 PL12 11 10 9 8 7 6 5 4 3 2 1 0 PL11 PL10 PL9 PL8 PL7 PL6 PL5 PL4 PL3 PL2 PRI PLO reserved read as 0 should be written with 0 for future compatibility Figure 9 4 Timer Prescaler Load Register TPLR 9 3 2 1 TPLR Prescaler Preload Value PL 20 0 Bits 20 0 These 21 bits contain the prescaler preload value This value is loaded into the prescaler counter when the counter value reaches 0 or the counter switches state from disabled to enabled If PL 20 0 N then the prescaler counts N 1 source clock cycles before generating a prescaler clock pulse Therefore the prescaler divide factor preload value 1 The PL 20 0 bits are cleared by a hardware RESET signal or a software RESET instruction 9 3 2 2 TPLR Prescaler Source PS 1 0 Bits 22 21 The two Prescaler Source PS bits control the source of the prescaler clock Table 9 1 summarizes PS bit functionality The prescaler s use of a TIO pin is not affected by the TCSR settings of the timer corresponding to the TIO pin being used MOTOROLA DSP5630
183. MA triggers generated by the timer To ensure that all DMA triggers are serviced the user must provide for the preceding DMA trigger to be serviced before the next trigger is received by the DMA channel ESP MOTOROLA DSP56303UM AD 9 27 Triple Timer Module Timer Modes of Operation 9 28 DSP56303UM AD MOTOROLA SECTION 10 ON CHIP EMULATION MODULE MOTOROLA DSP56303UM AD On Chip Emulation Module 10 1 10 2 10 4 10 5 10 6 10 7 10 8 10 9 10 10 10 11 10 12 10 13 10 2 INTRODUCTION on cue vut ee em tex 10 3 ONCE MODULE PINS 10 3 ONCE CONTROLLER 10 4 ONCE MEMORY BREAKPOINT LOGIC 10 10 ONGE TRACE LOGIC ec we we Eee 10 15 METHODS OF ENTERING THE DEBUG MODE 10 16 PIPELINE INFORMATION AND OGDB REGISTER 10 18 TRACE BUFFER vas 10 20 SERIAL PROTOCOL DESCRIPTION 10 23 TARGET SITE DEBUG SYSTEM REQUIREMENTS 10 23 EXAMPLES OF USING THE 10 24 EXAMPLES OF JTAG AND ONCE INTERACTION 10 29 DSP56303UM AD MOTOROLA On Chip Emulation Module Introduction 10 1 INTRODUCTION The DSP56300 core On Chip Emulation OnCE module provides a means of interacting with the DSP56300 core and its peripherals non intrusively so that a user can examine registers memory or on chip peripherals thus facilitating hardware and software development on the DSP56300 core pr
184. Memory Configurations 3 3 2 RAM Configurations The RAM configurations for the DSP56303 are listed in Table 3 4 Table 3 4 RAM Configurations for the DSP56303 Bit Settings Memory Sizes in K MS CE 2 0 0 4 2 2 0 0 1 3 2 2 1 1 0 2 3 3 0 1 1 1 3 3 1 The actual memory locations for Program RAM and the Instruction Cache in the Program memory space are determined by the MS and CE bits and their addresses are given in Table 3 5 Table 3 5 Memory Locations for Program RAM and Instruction Cache Program MS CE RAM Cache N Location Location 0 0 5000 0 1 000 BFF C00 FFF 1 0 000 7FF N A 1 1 000 3FF 400 7FF DSP56303UM AD MOTOROLA Memory Configuration Memory Maps The actual memory locations for both X and Y data RAM in their own memory space are determined by the MS bit and their addresses are listed in Table 3 6 Table 3 6 Memory Locations for Data RAM MS Data RAM Location 0 000 7FF 1 000 BFF 3 4 MEMORY MAPS The following figures describe each of the memory space and RAM configurations defined by the settings of the SC MS and CE bits The figures show the configuration and the table describes the bit settings memory sizes and memory locations MOTOROLA DSP56303UM AD 3 9 Memory Configuration Memory Maps Default Program X Data Y Data SERPERE Internal I O External
185. OIE bit is used to enable the timer overflow interrupts Setting TOIE enables overflow interrupt generation The timer counter can hold a maximum value of FFFFFF When the counter value is at the maximum value and a new event causes the counter to be incremented to 000000 the timer generates an overflow interrupt Clearing the TOIE bit disables overflow interrupt generation The TOIE bit is cleared by a hardware RESET signal or a software RESET instruction 9 3 4 3 Timer Compare Interrupt Enable TCIE Bit 2 The Timer Compare Interrupt Enable TCIE bit is used to enable or disable the timer compare interrupts Setting TCIE enables the compare interrupts In the Timer PWM or Watchdog modes a compare interrupt is generated after the counter value matches the value of the TCPR The counter will start counting up from the number MOTOROLA DSP56303UM AD 9 9 Triple Timer Module Triple Timer Module Programming Model loaded from the TLR and if the TCPR value is an interrupt occurs after N M 1 events where M is the value of TLR Clearing the TCIE bit disables the compare interrupts The TCIE bit is cleared by a hardware RESET signal or a software RESET instruction 9 3 4 4 Timer Control TC 3 0 Bits 4 7 The four Timer Control TC bits control the source of the timer clock the behavior of the TIO pin and the Timer mode of operation Table 9 2 summarizes the TC bit functionality A detailed description of the timer ope
186. PLL use The voltage should be well regulated and the input should be provided with an extremely low impedance path to the Vcc power rail should be bypassed to GNDp a 0 47 uF capacitor located as close as possible to the chip package There is one input Vcco 4 Quiet Power V cq is an isolated power for the internal processing logic This input must be tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors There are four inputs 4 Address Bus Power V ca is an isolated power for sections of the address bus I O drivers This input must be tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors There are four Vcc inputs Vccp 4 Data Bus Power V cp is an isolated power for sections of the data bus I O drivers This input must be tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors There are four Vccp inputs 2 Bus Control Power Vccc is an isolated power for the bus control I O drivers This input must be tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors There are two inputs Host Power V is an isolated power for 108 I O drivers This input must be tied externally to all other chip power inputs The user mu
187. PTIONS MEMORY CONFIGURATION CORE CONFIGURATION GENERAL PURPOSE I O HOST INTERFACE 108 ENHANCED SYNCHRONOUS SERIAL INTERFACE SERIAL COMMUNICATION INTERFACE SCI TIMER MODULE ON CHIP EMULATION MODULE JTAG PORT BOOTSTRAP PROGRAM EQUATES BSDL LISTING PROGRAMMING REFERENCE INDEX DSP56303 OVERVIEW SIGNAL CONNECTION DESCRIPTIONS MEMORY CONFIGURATION CORE CONFIGURATION GENERAL PURPOSE I O HOST INTERFACE 108 ENHANCED SYNCHRONOUS SERIAL INTERFACE SERIAL COMMUNICATION INTERFACE SCI TIMER MODULE ON CHIP EMULATION MODULE JTAG PORT BOOTSTRAP PROGRAM EQUATES BSDL LISTING PROGRAMMING REFERENCE INDEX
188. R EQU SFFFFB9 SSIO Time Slot Register 1 EQU SFFFFB8 5510 Receive Data Register SSISRO EQU SFFFFB7 SSIO Status Register I EQU SFFFFB6 SSIO Control Register B I EQU SFFFFB5 SSIO Control Register A I EQU SFFFFB4 SSIO Transmit Slot Mask Register A 1 TSMBO EQU SFFFFB3 SSIO Transmit Slot Mask Register B I RSMAO EQU SFFFFB2 5510 Receive Slot Mask Register A 1 RSMBO EQU SFFFFBl SSIO Receive Slot Mask Register B Register Addresses Of 5511 1 TX10 EQU 5511 Transmit Data Register 0 1 TX11 EQU SFFFFAB 5511 Transmit Data Register 1 TX12 EQU SFFFFAA 5511 Transmit Data Register 2 1 TSR1 EQU SFFFFA9 5511 Time Slot Register 1 RX1 EQU SFFFFA8 5511 Receive Data Register 1 SSISRI EQU SFFFFA7 5511 Status Register I CRB1 EQU SFFFFA6 5511 Control Register B I EQU 5 5511 Control Register I EQU SFFFFA4 5511 Transmit Slot Mask Register A TSMB1 EQU SFFFFA3 5511 Transmit Slot Mask Register B 1 RSMA1 EQU SFFFFA2 5511 Receive Slot Mask Register A RSMB1 EQU SFFFFAL 5511 Receive Slot Mask Register B SSI Control Register Bit Flags M_PM EQU SFF Prescale Modulus Select Mask 7 M_PSR EQU 11 Prescaler Range M DC EQU 51 000 Frame Rate Divider Control Mask DCO DC7 M_ALC EQU 18 Alignment Control ALC M WL EQU S380000 Word Length Control Mask WL0 WL7 M 5501 EQU 22 Select 5 as TR 0 drive en
189. ROLA PROGRAMMING REFERENCE Date Application Programmer Sheet 3 of 5 4444 X 0 O11 1191 SOA SOA SOA ON 0 0 ben 19407 0100 m S 9 L 8 6 OL IL cL EL VE SE 96 ZL SL 6 06 Lo Ee c Uc occu S EU Ma e Mi i 2 Hdl o1sa fauoud 1idnu lul SoA SOA SOA ON 0 1949 018l SOA SOA SOA 0 804 0 0 19497 SOA SOA SOA ON 19497 01 HIVI peiqeua3 dOsss00dd Figure D 3 Interrupt Priority Register Core IPR C D 17 DSP56303UM AD MOTOROLA PROGRAMMING REFERENCE Date Application Programmer Sheet 4 of 5 r S 9 40 vL 914 A PE9H 4444 X 0105 0115 rus 0105 ros 010 1101 00 0 L EL 1 1 rere ee iaa 9 ZL 8 6L Oc 12 22 66 0 se SOA SOA SOA ON 0 S9A 9A ON
190. Reserved Data Output Bit 13 1101 Reserved 0 Zero written to TIO pin 1110 Reserved 1 One written to TIO pin 1111 Reserved Timer Enable Bit 0 Prescaled Clock Enable Bit 15 0 Timer Disabled 0 Clock source is CLK 2 or TIO 1 Timer Enabled 1 Clock source is prescaler output Timer Overflow Interrupt Enable Bit 1 5 0 Overflow Interrupts Disabled Timer Compare Flag Bit 21 1 Overflow Interrupts Enabled 0 1 has been written to TCSR TCF or timer compare interrupt serviced Timer Compare Interrupt Enable Bit 2 1 Timer Compare has occurred 0 Compare Interrupts Disabled 1 Compare Interrupts Enabled Timer Overflow Flag Bit 20 0 1 has been written to TCSR TOF or timer Overflow interrupt serviced 1 Counter wraparound has occurred 23 22 21 20119 18 17 16115 14 13 1211110 9 8 7 6 5 413 2 1 k k k PCE TRM inv o 10 1 1 lol Timer Control Status Register Reserved Program as 0 TCSRO FFFF8F Read Write TCSR1 FFFF8B Read Write TCSR2 FFFF87 Read Write Reset 000000 Figure D 20 Timer Control Status Register TCSR D 34 DSP56303UM AD MOTOROLA PROGRAMMING REFERENCE Application Date Programmer Sheet 3 of 3 Timers 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 Timer Reload Value Time
191. SI PCn 0 5 Port Pin configured as GPIO ReadWrite Reset Pl PDOCn 1 gt Port Pin is Output PDOCn 0 gt Port Pin is Input 5 4 Port Direction Register H Ppos X EFFFBL ReadWrite Reset 5 4 0 Port C GPIO Data Register H Pps PDs PD2 TUTTE sir port pin n is GPIO input then PDn reflects the value on port pin n if port pin n is GPIO output then value written to PDn is reflected on port pin n Reserved Program as 0 Figure D 23 Port C Registers PCRC PRRC MOTOROLA DSP56303UWAD D 37 PROGRAMMING REFERENCE Application Date Programmer Sheet 3 of 4 G Port ESSI1 D 38 Port D Control Register H PCRD H X EFFFAP ReadWrite B 1 Port Pin configured as ESSI PCn 0 Port Pin configured as GPIO ReadWrite Reset iej PDCn 1 gt Port Pin is Output PDCn 0 Port Pin is Input 5 4 Port D Direction Register H Pbos PDC4 X EFFFAE ReadWrite Reset 5 4 0 Port D GPIO Data Register H Pps TUTTE FEAL port pin n is GPIO input then PDn reflects the value on port pin n if port pin n is GPIO output then value written to PDn is reflected on port pin n Reserved Program as 0 Figure D 24 Port D Registers PCRD PRRD PDRD DSP56303UM AD MOTOROLA
192. SI is in Network mode When TLIE is set the DSP is interrupted at the 7 26 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI ESSI Programming Model start of the last slot in a frame regardless of the Transmit Mask Register setting When TLIE is cleared the transmit last slot interrupt is disabled The use of the transmit last slot interrupt is described in Section 7 5 3 TLIE is cleared by either a hardware reset signal or a software reset instruction TLIE is disabled when the ESSI is in On demand mode DC 0 7 4 2 21 CRB ESSI Receive Last Slot Interrupt Enable RLIE Bit 21 Setting the RLIE bit enables an interrupt after the last slot of a frame ends when the ESSI is in Network mode When RLIE is set the DSP is interrupted after the last slot in a frame ends regardless of the Receive Mask Register setting When RLIE is cleared the receive last slot interrupt is disabled The use of the receive last slot interrupt is described in Section 7 5 3 RLIE is cleared by either a hardware reset signal or a software reset instruction RLIE is disabled when the ESSI is in On demand mode DC 0 7 4 2 22 CRB ESSI Transmit Exception Interrupt Enable TEIE Bit 22 When the TEIE bit is set the DSP is interrupted when both TDE and TUE in the ESSI Status Register are set When is cleared this interrupt is disabled The use of the transmit interrupt is described in Section 7 5 3 Reading the Status Register followed
193. SPs with multiple words per frame Network mode has as sub mode called On demand mode Setting the MOD bit in the for Network mode and setting the frame rate divider to 0 DC 00000 selects the On demand mode This sub mode does not generate a periodic frame sync A frame sync pulse is generated only when data is available to transmit The frame sync signal indicates the first time slot in the frame The On demand mode requires that 7 40 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI Operating Modes the transmit frame sync be internal output and the receive frame sync be external input For simplex operation the Synchronous mode could be used however for full duplex operation the Asynchronous mode must be used Data transmission that is data driven is enabled by writing data into each TX Although the ESSI is double buffered only one word can be written to each TX even if the Transmit Shift Register is empty The receive and transmit interrupts function normally using TDE and RDF however transmit underruns are impossible for On demand transmission and are disabled This mode is useful for interfacing to codecs requiring a continuous clock 7 5 4 2 Synchronous Asynchronous Operating Modes The transmit and receive sections of the ESSI interface may be synchronous or asynchronous The transmitter and receiver use common clock and synchronization signals in the Synchronous mode they use separate c
194. SSIO X FFFFB4 ESSI1 X FFFFA4 MOTOROLA DSP56303UM AD 7 9 Enhanced Synchronous Serial Interface ESSI ESSI Programming Model 11 10 9 8 7 6 5 4 3 2 1 0 TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 7519 7518 TS17 7516 23 22 21 20 19 18 17 16 15 14 13 12 531 1530 7529 528 0861 Figure 7 6 ESSI Transmit Slot Mask Register TSMB ESSIO X FFFFB3 55 X FFFFA3 11 10 9 8 7 6 5 4 3 2 1 0 Ret RS10 59 Rs8 57 Rse 55 Rs4 RS2 RSO 23 22 21 20 19 18 17 16 15 14 13 12 515 T rsi 0862 Figure 7 7 ESSI Receive Slot Mask Register ESSIO X FFFFB2 55 X FFFFA2 11 10 9 8 7 6 5 4 3 2 1 0 RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 8519 RS18 8517 RS16 23 22 21 20 19 18 17 16 15 14 13 12 Rss RS30 8529 8528 Reserved bit read as zero should be written with zero for future compatibility AA0863 Figure 7 8 ESSI Receive Slot Mask Register B RSMB ESSIO X FFFFB1 ESSI1 X FFFFA1 7 4 1 ESSI Control Register A CRA The ESSI Control Register A CRA is one of two 24 bit read write control registers used to direct the operation of the ESSI The CRA controls the ESSI clock generator bit and frame sync rates word length and number of words per frame for the serial
195. Slot Mask Registers TSMB 7 34 7 4 10 Receive Slot Mask Registers RSMA RSMB 7 35 7 5 OPERATING 7 36 7 5 1 ESSI Aller Reset uw 7 36 7 5 2 ESSI Initialization 7 36 7 5 3 ESSI EXCSDIIODS 7 37 7 5 4 Operating Modes Normal Network and On Demand 7 40 7 5 4 1 Normal Network On Demand Mode Selection 7 40 7 5 4 2 Synchronous Asynchronous Operating Modes 7 41 7 5 4 3 Frame Sync Selection 7 41 7 5 4 3 1 Controlling the Frame Sync Signal Format 7 41 7 5 4 3 2 Controlling the Frame Sync Length for Multiple DOVICOS np ert HN atv oh ues 7 42 7 5 4 3 3 Controlling the Word Length Frame Sync Relative to the Data Word Timing 7 42 7 5 4 3 4 Controlling the Frame Sync Polarity 7 42 7 5 4 4 Selecting the Byte Format LSB MSB for the 7 43 7 5 5 Flajs COG Ga uk ote a ua 7 43 7 6 GPIO PINS AND REGISTERS 7 44 7 6 1 Port Control Register PCR 7 44 7 6 2 Port Direction Register 7 45 7 6 3 Port Data Register PDR 7 45 viii DSP56303UM AD MOTOROLA SECTION 8 SERIAL COMMUNICATION INTERFACE SCI 8 1 8 1 8 2 8 2 1 8 2 2 8 2 3 8 3 8 3 1 8 3 1 1 8 3 1 2
196. TD 1149 1 1994 11 attribute PIN MAP of DSP56303 entity is PHYSICAL PIN MAP constant 144 PIN MAP STRING 5801 1 5101 2 75 5 02 3 5 01 4 DE oy PINIT 6 amp SRDO 7 SVCC 8 25 amp 9 26 5 STDO 10 5 10 TT us 5 00 I2 4 l3 4 TXD 14 6 SCLK 15 6 SCK1 16 amp SCKO Liy ux QVCC 18 56 91 126 amp 19 54 90 127 RESERVED 49 20 DSP56303UM AD to to S WWW CO MOTOROLA HDS HRW HACK HREQ TIO2 TIOTI TIOO JGND1 AGND 118 121 MOTORO D amp DVCC DGND IODC TRST_ LA 71 72 73 74 75 100 103 104 134 135 136 137 138 139 140 141 142 143 m m VI m m m m m m m m m m m lt 65 66 amp amp amp amp amp amp amp amp 41 40 37 36 35 34 51 50 amp 80 86 95 6 81 101 102 105 106 107 87 96 122 123 124 125 128 131 111 119 129 112 120 130 amp m m m m m m DSP56303UM AD amp DSP56303 BSDL Listing
197. TE Address Tracing Enable MS Memory Switch Mode WRP Extended Stack Wrap BRT Bus Release Timing SD Stop Delay EOV Extended Stack Overflow Flag TAS TA Synchronize Select EBD External Bus Disable EUN Extended Stack Underflow Flag BE Burst Mode Enable MD Operating Mode D XYS Stack Extension Space Select CDP1 Core DMA Priority 1 Mode C CDP0 Core DMA Priority 0 MB Operating Mode B MA Operating Mode A Reserved bit Read as zero should be written with zero for future compatibility AA0851 Figure 4 3 DSP56303 Operating Mode Register OMR MOTOROLA DSP56303UM AD 4 17 Core Configuration PLL Control Register 47 PLL CONTROL REGISTER The PLL control register PCTL is an X I O mapped 24 bit read write register used to direct the operation of the on chip PLL The PCTL control bits are shown in Figure 4 4 Refer to the DSP56300 Family Manual for a full description of the PCTL 11 10 9 8 7 6 5 4 3 2 1 0 MF11 MF10 MF9 MF8 MF7 MF6 5 4 2 1 23 22 21 20 19 18 17 16 15 14 13 12 PD3 PD2 PD1 PDO COD PEN PSTP XTLD XTLR DF2 DF1 DFO AA0852 Figure 4 4 PLL Control Register PCTL 4 7 1 PCTL PLL Multiplication Factor Bits 0 11 The Multiplication Factor bits MF 11 0 define the Multiplication Factor MF that is applied to the PLL input frequency The MF bits are cleared during DSP56303 hardware reset
198. TION 1 3 1 3 MANUAL 5 1 5 1 4 DSP56303 FEATURES wu Pott 1 6 1 5 DSP56303 CORE 1 7 1 5 1 General Fealures 1 7 1 5 2 Hardware Debugging 1 7 1 5 3 Reduced Power 1 7 1 6 DSP56300 CORE FUNCTIONAL BLOCKS 1 8 1 6 1 Data Ab ue intei 1 8 1 6 1 1 Data ALU Registers 1 8 1 6 1 2 Multiplier Accumulator 1 9 1 6 2 Address Generation Unit AGU 1 9 1 6 3 Program Control Unit PCU 1 10 1 6 4 PLL and Glock Oscillator 1 11 1 6 5 JTAG Test Access Port and On Chip Emulation OnCE Modules ee aaa ee ak Ae saq Q 1 11 1 6 6 On Chip 1 12 1 6 7 Off Chip Memory Expansion 1 12 1 7 INTERNAL BUSES 1 13 1 8 DSP56303 BLOCK 1 14 1 9 DIRECT MEMORY ACCESS 1 14 1 10 DSP56303 ARCHITECTURE OVERVIEW 1 15 1 10 1 GPIO Functionalily 1 15 1 10 2 Host Interface 08 1 15 1 10 3 Enhanced Synchronous Serial Interface ESSI
199. UPT 5 D 13 D 5 PROGRAMMING REFERENCE CENTRAL PROCESSOR D 15 eM clin cranes S sa D 19 HOST INTERFACE HIl08 D 20 ENHANCED SYNCHRONOUS SERIAL INTERFACE ESSI Sarrera eee D 26 SERIAL COMMUNICATIONS INTERFACE D 30 TIMERS uns Lee ase hoes D 33 GENERAL PURPOSE D 36 MOTOROLA DSP56303UM AD XV Figure 1 1 Figure 2 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 6 1 Figure 6 2 Figure 6 3 MOTOROLA LIST OF FIGURES DSP56303 Block Diagram 1 14 Signals Identified by Functional Group 2 4 Default Settings 0 0 0 3 10 Instruction Cache Enabled 0 0 1 3 11 Switched Program RAM 0 1 0 3 12 Switched Program RAM and Instruction Cache Enabled 0 1 1 edd 3 13 16 bit Space with Default RAM 1 0 0 3 14 16 bit Space with Instruction Cache Enabled 1 0 1 3 15 16 bit Space with Switched Program RAM 1 1 0 3 16 16 bit Space Switched Program RAM Instruction Cache Enabled 1 1 1 3 17 Interrupt Priori
200. a 103 BC_1 SC10 Control 104 BC 6 SC10 Input Output Data 105 BC 1 STDO Control 106 BC 6 STDO Input Output Data 107 BC 1 SRDO Control 108 BC 6 SRDO Input Output Data 109 BC 1 PINIT Control 110 BC 6 PINIT Input Output Data 111 BC 1 DE Control MOTOROLA DSP56303UM AD 11 17 JTAG Port DSP56303 Boundary Scan Register Table 11 2 DSP56303 Boundary Scan Register BSR Bit Definitions Continued 11 18 Bit Cell Type Pin Name Pin Type BSR Cell Type 112 _6 Input Output Data 113 BC_1 5 01 Control 114 BC_6 5 01 Input Output Data 115 BC_1 5 02 Control 116 BC_6 5 02 Input Output Data 117 BC_1 STD1 Control 118 BC 6 STD1 Input Output Data 119 BC_1 SRD1 Control 120 BC 6 SRD1 Input Output Data 121 BC_1 5 11 Control 122 BC_6 5 11 Input Output Data 123 BC_1 SC12 Control es DSP56303UM AD MOTOROLA APPENDIX BOOTSTRAP PROGRAMS BOOTSTRAP CODE FOR DSP56303 Copyright 1995 Motorola Inc Revised June 29 1 Bootstrap thx6 ugh the Host Interface External EPROM or SI This program contained in the DSP56303 192 word Boot gt This program can load any program RAM segment from an externa EBROM from the Host Interface or from the SCI serial interface f
201. a clock Note This should not be confused with what is known as the Asynchronous channels mode of the ESSI in which separate clocks are used for the receiver and transmitter In this mode the ESSI is still a synchronous device because all transfers are synchronized to these clocks Additional synchronization signals are used to delineate the word frames The Normal mode of operation is used to transfer data at a periodic rate one word per period The Network mode is similar in that it is also intended for periodic transfers however it supports up to 32 words time slots per period The Network mode can be used to build Time Division Multiplexed TDM networks In contrast the On Demand mode is intended for non periodic transfers of data This mode can be used to transfer data serially at high speed when the data become available This mode offers a subset of the SPI protocol Since each ESSI unit can be configured with one receiver and three transmitters the two units can be used together for surround sound applications which need two digital input channels and six digital output channels 7 2 ENHANCEMENTS TO THE ESSI The Synchronous Serial Interface SSI used in the DSP56000 family has been enhanced in the following ways to make the Enhanced Synchronous Serial Interface ESSI e Network Enhancements Time Slot Mask Registers receive and transmit added MOTOROLA DSP56303UM AD 7 3 Enhanced Synchronous Serial Interfac
202. able 55 1 z SSI Control Register B Bit Flags M OF EQU 3 Serial Output Flag Mask M_OFO EQU 0 Serial Output Flag 0 M OF1 EQU 1 Serial Output Flag 1 M_SCD EQU 1C Serial Control Direction Mask B 6 DSP56303UM AD MOTOROLA Equates 1 SCDO EQU 2 Serial Control 0 Direction 1 SCD1 EQU 3 Serial Control 1 Direction SCD2 EQU 4 Serial Control 2 Direction 1 5 EQU 5 Clock Source Direction EQU 6 Shift Direction 1 FSL EQU 180 Frame Sync Length Mask FSLO FSL1 FSLO EQU 7 Frame Sync Length 0 1 FSL1 EQU 8 Frame Sync Length 1 1 FSR EQU 9 Frame Sync Relative Timing FSP EQU 10 Frame Sync Polarity EQU 11 Clock Polarity SYN EQU 12 Sync Async Control 1 MOD EQU 13 SSI Mode Select 1 55 EQU 1C000 SSI Transmit enable Mask SSTE2 EQU 14 SSI Transmit 42 Enable 1 SS EQU 15 SSI Transmit 41 Enable SSTEO EQU 16 SSI Transmit 40 Enable SSR EQU 1 SSI Receive Enable SSTI EQU 18 SSI Transmit Interrupt Enable SSRI EQU 19 SSI Receive Interrupt Enable STLI EQU 20 SSI Transmit Last Slot Interrupt Enable SRLI EQU 21 SSI Receive Last Slot Interrupt Enable STEIE EQU 22 SSI Transmit Error Interrupt Enable SRE
203. able 6 3 HI08 Host Request Signal Pins br Vector required No vector required GPIO mode HREO HREQ HREQ HTRO HTRO PB14 HTRQ HACK HACK HACK 15 HRRQ 6 6 DSP56303UM AD MOTOROLA Host Interface HI08 08 Block Diagram 6 4 HI08 BLOCK DIAGRAM Figure 6 1 shows the 108 registers The top row of registers HCR HSR HDDR HDR HBAR HPCR HTX HRX can be accessed by the DSP core The bottom row of registers ISR ICR CVR IVR RXH RXM RXL and TXH TXM TXL can be accessed by the host processor HCR Host Control Register HSR Host Status Register HPCR Host Port Control Register HBAR Host Base Address register HTX Host Transmit register HRX Host Receive register HDDR Host Data Direction Register HDR Host Data Register Core DMA Data Bus DSP Peripheral Data Bus H 24 24 1 P SS a 3 1 1 1 p 1 Address 1 24 24 Comparator 1 I I 3 Mara 1 Li om g u pw pw I 8 HOST Bus ICR Interface Control Register CVR Command Vector Register ISR Interface Status Register IVR Interrupt Vector Register RXH Receive Register High RXM Receive Register Middle RXL Receive Register Low TXH Transmit Register High TXM Transmit Register Middle TXL Transmit Register High AA0657 Figure 6 1 HI08 Block Diagram MOTOROLA DSP56303UWAD 6 7 Host Interface HI08 HI08 DSP S
204. ace These signals are tri statable outputs with programmable polarity RD Output Tri stated Read Enable When the DSP is the bus master RD is an active low output that is asserted to read external memory on the data bus D0 D23 Otherwise RD is tri stated WR Output Tri stated Write Enable When the DSP is the bus master WR is an active low output that is asserted to write external memory on data bus 00 023 Otherwise the signals are tri stated 2 10 DSP56303UM AD MOTOROLA Signal Connection Descriptions External Memory Expansion Port Port A Table 2 8 External Bus Control Signals Continued Signal Name State During Type Reset Signal Description Stop or Wait Input Ignored Transfer Acknowledge If the DSP56303 is the bus Input master and there is no external bus activity or the DSP56303 is not the bus master the TA input is ignored The TA input is a Data Transfer Acknowledge DTACK function that can extend an external bus cycle indefinitely Any number of wait states 1 2 infinity may be added to the wait states inserted by the BCR by keeping deasserted In typical operation TA is deasserted at the start of a bus cycle is asserted to enable completion of the bus cycle and is deasserted before the next bus cycle The current bus cycle completes one clock period after T is asserted synchronous to CLKOUT The number of wait states is determined
205. ad it shows the current setting After a hardware or software reset instruction the TSM register is reset to which enables all thirty two slots for data transmission 7 4 10 Receive Slot Mask Registers RSMA RSMB The Receive Slot Mask Registers are two 16 bit read write registers In Network mode these registers are used by the receiver s to determine what action to take in the current time slot Depending on the setting of the bits the receiver s either tri state the receiver s data pin s or receive a data word and generate a receiver full condition RSMA and RSMB see Figure 7 16 and Figure 7 17 can be seen as one 32 bit register RSM Bit n in RSM RSn is an enable disable control bit for time slot number N When is cleared all the data pins of the enabled receivers tri stated during time slot number N Data is transferred from the Receive Data Register s to the Receive Shift Register s and the RDF and ROE flags are not set During a disabled slot no receiver full interrupt is generated The DSP is interrupted only for enabled slots When RSn is set the receive sequence proceeds normally Data is received during slot number N and the RDF flag is set Using the RSM slot mask does not conflict with using the RSR Even if a slot is enabled in RSM the user may chose to write to RSR instead of writing to the Receive Data Registers RXx This causes all the transmit data pins of the enabled rec
206. ad at any time by reading the TCR 9 18 DSP56303UM AD MOTOROLA Triple Timer Module Timer Modes of Operation 9 4 1 3 Timer Toggle Mode 2 Bit Settings Mode Characteristics TC3 2 TCO Clock KIND NAME 0 0 1 0 Output Internal 0 Timer Toggle In this mode the timer periodically toggles the polarity of the TIO pin Set the TE bit in the TCR to clear the counter and enable the timer The value the timer is to count is loaded into the TPCR The counter is loaded with the TLR value when the first timer clock signal is received The TIO pin is loaded with the value of the INV bit The timer clock signal can be taken from either the DSP56303 clock divided by two CLK 2 or from the prescaler clock output Each subsequent clock signal increments the counter When the counter value matches the value in the TCPR the polarity of the TIO output pin is inverted The TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set If the TRM bit is set the counter is loaded with the value of the TLR when the next timer clock is received and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each timer clock This process is repeated until the TE bit is cleared disabling the timer The counter contents can be read at any time by reading the TCR The TLR value in the TCPR sets the delay between starting the time
207. am Memory 3 3 3 1 2 Data Memory 5 3 3 3 1 2 1 X Data Memory 3 4 3 1 2 2 Y Data Memory 3 4 3 1 3 Memory Space Configuration 3 5 3 2 RAM 3 5 3 2 1 On Chip Program Memory Program RAM 3 6 3 2 2 On Chip X Data Memory X Data RAM 3 6 3 2 3 On Chip Y Data Memory Y Data RAM 3 7 3 2 4 Bootstrap 3 7 3 3 MEMORY 5 3 7 3 3 1 Memory Space Configurations 3 7 ii DSP56303UM AD MOTOROLA 3 3 2 RAM Configurations 3 8 3 4 MEMORY 3 9 3 5 INTERNAL I O MEMORY 3 18 SECTION 4 CONFIGURATION 4 1 4 1 INTRODUCTION tetera corde 4 3 4 2 OPERATING MODES 22 E RS 4 3 4 3 BOOTSTRAP PROGRAM 4 4 4 3 1 Mode 0 Expanded 4 6 4 3 2 Mode 1 Bootstrap from Byte Wide External Memory 4 6 4 3 3 Mode 2 Bootstrap Through 501 4 6 4 3 4 Mode 3 Reserved e dome ae ea t 4 7 4 3 5 Mode 4 Bootstrap Through 108 in ISA DSP5630X Mode S Bi
208. amp l dis rslt 1 Z amp Ly Z amp 1 Z amp Ly Z amp Ly Z amp Ly 2 amp dy Z 5 dy Z amp Ly Z amp Ly Z amp Ly Z amp Ly 2 amp Ly 2 amp Ly 2 amp Ly 2 amp Ly Z amp 1 2 5 l 2 amp 1 dis rslt 1 2 5 Ly amp 1 2 amp 1 2 5 1 LZ gh amp 1 Z fh amp 1 Z amp 1 2 5 1 Z amp 1 Z amp 1 Z amp 1 2 amp 1 2 amp 1 2 amp ccell dis rslt bidir X 26 bidir X 26 bidir X 26 func safe bidir X 26 bidir X 26 bidir X 26 bidir X 26 bidir X 26 bidir X 26 control 1 amp bidir X 26 bidir X 26 bidir X 26 output3 X 33 output3 X 33 output3 X 33 control 1 amp output3 X 33 output3 X 39 output3 X 33 output3 X 39 output3 X 33 output3 X 33 func safe output3 X 43 output3 X 43 output3 X 43 control 1 amp output3 X 43 output3 X 43 output3 X 43 output3 X 43 output3 X 43 output3 X 43 input amp output3 X 55 output3 X 56 output3 X 64 output3 X 64 control 1 amp control 1 amp control 1 amp bidir X 51 output2 X amp func safe input X amp output3 X 64 output3 X 64 output2 X amp control 1 amp control 1 amp control 1 amp DSP56303UM AD 2 amp 2 amp C 7 DSP56303 8501 Listing
209. an SCI Transmit Data interrupt from the interrupt controller TIE is cleared by hardware and software reset 8 3 1 12 SCR Timer Interrupt Enable TMIE Bit 13 The TMIE bit is set to enable the SCI timer interrupt If TMIE is set timer interrupt requests are sent to the interrupt controller at the rate set by the SCI clock register The timer interrupt is automatically cleared by the timer interrupt acknowledge from the interrupt controller This feature allows DSP programmers to use the SCI baud rate generator as a simple periodic interrupt generator if the SCI is not in use if external clocks are used for the SCI or if periodic interrupts are needed at the SCI baud rate The SCI internal clock is divided by 16 to match the 1 X SCI baud rate for timer interrupt generation This timer does not require that any SCI pins be configured for SCI use to operate TMIE is cleared by hardware and software reset 8 3 1 13 SCR Timer Interrupt Rate STIR Bit 14 The STIR bit controls a divide by 32 in the SCI Timer interrupt generator When STIR is cleared the divide by 32 is inserted in the chain When STIR is set the divide by 32 is bypassed thereby increasing timer resolution by a factor of thirty two This bit is cleared by hardware and software reset To ensure proper operation of the timer STIR must not be changed during timer operation i e if TMIE 1 8 3 1 14 SCR SCI Clock Polarity SCKP Bit 15 The SCKP bit controls the clock polarity sou
210. and Vector Register CVR 6 25 Core Status bits OS0 OS1 10 9 CRA register 7 10 bits 0 7 Prescale Modulus Select bits PMO PM7 7 10 bits 8 10 reserved bits 7 11 bit 11 Prescaler Range bit PSR 7 11 bits 12 16 Frame Rate Divider Control bits 4 0 0 7 12 bit 17 reserved bit 7 13 bit 18 Alignment Control bit ALC 7 13 bits 19 21 Word Length Control bits WLO WL1 7 14 bit 22 Select SC1 as Transmitter 0 Drive Enable bit SSC1 7 14 bit 23 reserved bit 7 14 reserved bits bit 17 7 13 reserved bits bit 23 7 14 reserved bits bits 8 10 7 11 CRB register bits 0 1 Serial Output Flag bits OFO OF1 7 15 bit 2 Serial Control 0 Direction bit 5 00 7 16 bit 3 Serial Control 1 Direction bit SCD1 7 16 bit 4 Serial Control 2 Direction bit SCD2 7 16 bit 5 Clock Source Direction bit SCKD 7 16 bit 6 Shift Direction bit SHFD 7 17 bits 7 8 Frame Sync Length bits FSL1 FSLO 7 17 bit 9 Frame Sync Relative Timing bit FSR 7 17 bit 10 Frame Sync Polarity bit FSP 7 18 bit 11 Clock Polarity bit CKP 7 18 bit 12 Asynchronous Synchronous bit SYN 7 18 bit 13 ESSI Mode Select bit MOD 7 20 bit 14 ESSI Transmit 2 Enable bit TE2 7 22 bit 15 ESSI Transmit 1 Enable bit TE1 7 23 bit 16 ESSI Transmit 0 Enable bit TEO 7 24 bit 17 ESSI Receive Enable bit RE 7 26 bit 18 ESSI Transmit Interrupt Enable bit TIE 7 26 1 2 DSP56303UM AD bit 19 ESSI Receive Interrupt Enable b
211. ap through 68302 68360 4 9 bootstrap through ISA 4 7 bootstrap through 108 Multiplexed 4 8 bootstrap through 108 non multiplexed 4 8 bootstrap through SCI 4 6 Boundary Scan Register BSR 11 7 BR signal 2 12 break 8 9 Breakpoint 0 and 1 Event bits BTO BT1 10 14 Breakpoint 0 Read Write Select bits 00 01 10 12 Breakpoint 1 Condition Code Select bits CC10 CC11 10 14 Breakpoint 1 Read Write Select bits RW10 RW11 10 13 BSR register 11 7 0 1 bits 10 14 bus address 2 4 data 2 4 external address 2 8 external data 2 8 multiplexed 2 4 non multiplexed 2 4 bus busy signal BB 2 13 bus clock not signal BCLK 2 13 bus clock signal BCLK 2 13 bus control 2 3 bus grant signal BG 2 12 bus parking 2 13 bus request signal BR 2 12 buses internal 1 13 BYPASS instruction 11 11 CAS signal 2 13 CC00 CCO1 bits 10 13 CC10 CC11 bits 10 14 0 1 bits 8 16 Central Processing Unit CPU 1 3 CKP bit 7 18 CLAMP instruction 11 10 CLKGEN 1 11 CLKOUT signal 2 8 clock 1 7 2 3 Clock Divider bits CD0 CD11 8 16 Clock Generator CLKGEN 1 11 Clock Out Divider bit COD 8 16 clock output signal CLKOUT 2 8 Clock Polarity bit CKP 7 18 clock signals 2 7 Clock Source Direction bit SCKD 7 16 CMOS 1 7 Breakpoint 0 Condition Code Select bits COD bit 8 16 00 01 10 13 code MOTOROLA DSP56303UM AD l 1 compatible 1 7 column address strobe signal CAS 2 13 Comm
212. ata Register 8 29 Triple Timer Module Block 9 4 Timer Module Block 9 5 Timer Module Programmer s 9 6 Timer Prescaler Load Register TPLR 9 7 Timer Prescaler Count Register 9 8 OnCE Module Block Diagram 10 3 OnCE Module Multiprocessor Configuration 10 4 OnCE Controller Block 10 5 OnCE Command Register 10 5 OnCE Status and Control Register OSCR 10 8 OnCE Memory Breakpoint Logic 0 10 10 Breakpoint Control Register OBCR 10 12 OnCE Trace Logic Block Diagram 10 15 OnCE Pipeline Information and GDB Registers 10 19 OnCE Trace 10 22 TAP BOCK Diagram u os oa rers are e Ege Gis Bake uns 11 4 TAP Controller State Machine 11 6 DSP56303UM AD MOTOROLA Figure 11 3 Figure 11 4 Figure 11 5 Figure D 1 Figure D 2 Figure D 3 Figure D 4 Figure D 5 Figure D 6 Figure D 7 Figure D 8 Figure D 9 Figure D 10 Figure D 11 Figure D 12 Figure D 13 Figure D 14 Figure D 15 Figure D 16 Figure D 17 Figure D 18 Figure D 19 MOTOROLA JTAG Instruction
213. be interpreted as the number of words per frame minus one In Normal mode this ratio determines the word transfer rate The divide ratio may range from 1 to 32 DC 00000 to 11111 for Normal mode and 2 to 32 DC 00001 to 11111 for Network mode A divide ratio of one DC 00000 in Network mode is a special case known as On demand mode In Normal mode a divide ratio of one DC 00000 provides continuous periodic data word transfers A bit length frame sync must be used in this case and is selected by setting the FSL 1 0 bits in the CRA to 01 Both the hardware reset signal and the software reset instruction clear DC 4 0 The ESSI frame sync generator functional diagram is shown in Figure 7 10 7 12 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI ESSI Programming Model CRB FSL1 CRB FSR RX Word Clock CRA DC4 0 Internal Rx Frame Sync CRB SCD1 CRB SCD1 1 CRB SYN 0 Receive Receive Frame Sync Syne Control Logic 9 SCD1 0 TX 2 SYN 1 Flag1 or drive enb These signals are Async identical in sync mode ES CRB FSL1 0 Bici C DX Out or drive CRA SSC1 CRB FSR Sync Mode CRB TE2 CRB OF1 Y Sync Mode TX Word CRB SCD2 Clock CRA DC4 0 Sync Internal TX Frame Sync to 32 Sync TX RX ES Async TX FS Transmit Control Logic Frame Sync 0680 Figure 7 1
214. between breakpoint 0 and 1 If the condition defined by BTO BT1 is met then the Breakpoint Counter OMBC is decremented See Table 10 11 for the definition of the BTO BT1 bits Table 10 11 Breakpoint 0 and 1 Event Select Table BT1 BTO Description 0 0 Breakpoint 0 and Breakpoint 1 0 1 Breakpoint 0 or Breakpoint 1 1 0 Breakpoint 1 after Breakpoint 0 1 1 Breakpoint 0 after Breakpoint 1 10 5 6 7 OnCE Memory Breakpoint Counter OMBC The OnCE Memory Breakpoint Counter OMBC is a 16 bit counter that is loaded with a value equal to the number of times minus one that a memory access event should occur before a memory breakpoint is declared The memory access event is specified by the OBCR and by the memory limit registers On each occurrence of the memory access event the breakpoint counter is decremented When the counter reaches 0 and a new occurrence takes place the chip enters the Debug mode The OMBC can be read or written through the JTAG port Every time that the limit register is changed or a different breakpoint event is selected in the OBCR the breakpoint counter must be written afterwards This ensures that the OnCE 10 14 DSP56303UM AD MOTOROLA On Chip Emulation Module OnCE Trace Logic breakpoint logic is reset and that no previous events can affect the new breakpoint event selected The breakpoint counter is cleared by hardware reset 10 5 6 8 Reserved Bits 12 15 Bits 12 15 are reserved for future u
215. bility mode by setting the Sixteen bit Compatibility SC bit in the Status Register SR Table 3 1 Memory Space Configuration Bit Settings for the DSP56303 Bit Cleared 0 Abbicvis on Bit Name Bit Location Effect Default Set 1 Effect SC Sixteen bit SR 13 16 M word 64 K word Compatibility address space address space 24 bit address 16 bit address Memory maps for the different configurations are shown in Figure 3 1 to Figure 3 8 3 2 RAM CONFIGURATION The DSP56303 contains 8 K of RAM divided by default into e Program RAM 4 K Xdata RAM 2 K Y data RAM 2 K RAM configuration depends on two bits the Cache Enable CE of the SR and the Memory Select MS of the Operating Mode Register OMR Table 3 2 RAM Configuration Bit Settings for the DSP56303 Bit 2 Bit Cleared 0 Effect Abbreviation Bat Name Location Default Set 1 Effect CE Cache SR 19 Cache Disabled Cache Enabled Enable 1K MS Memory OMR 7 Program RAM4K Program 2 Switch X data RAM 2 X data RAM data RAM 2 K Y data RAM 3 K Memory maps for the different configurations are shown in Figure 3 1 to Figure 3 8 MOTOROLA DSP56303UM AD Memory Configuration RAM Configuration Note The MS bit may not be changed when CE is set The Instruction Cache occupies the top 1 K of what would otherwise be Program RAM and to switch memory into or out of Program RAM when
216. bit Transmit Shift Registers contain the data being transmitted see Figure 7 16 and Figure 7 17 Data is shifted out to the Serial Transmit Data pins by the selected internal external bit clock when the associated frame sync I O is asserted The word length control bits in the CRA determine the number of bits that must be shifted out before the shift registers are considered empty and may be written to again Depending on the setting of the CRA the number of bits to be shifted out can be 8 12 16 24 or 32 bits The data transmitted is aligned according to the value of the ALC bit When the ALC bit is cleared the MSB is Bit 23 and the least significant byte is unused When ALC is set the MSB is Bit 15 and the most significant byte is unused Unused bits are read as Os Data is shifted out of these registers MSB first if the SHFD bit is cleared and LSB first if the SHFD bit is set MOTOROLA DSP56303UM AD 7 33 Enhanced Synchronous Serial Interface ESSI ESSI Programming Model 7 4 7 ESSI Transmit Data Registers ESSIO TX20 TX10 TX00 ESSI1 TX21 TX11 01 TX2 TX1 and are 24 bit write only registers Data to be transmitted is written into these registers and automatically transferred to the Transmit Shift Registers see Figure 7 16 and Figure 7 17 The data transmitted 8 12 16 or 24 bits is aligned according to the value of the ALC bit When the ALC bit is cleared the MSB is Bit 23 When ALC is set the MSB is Bit 1
217. bit represents the status of the receive line The transition of IDLE from 0 to 1 can cause an IDLE interrupt ILIE IDLE is cleared by the hardware software SCI individual and stop processing state resets 8 3 2 5 SSR Overrun Error Flag OR Bit 4 The OR flag bit is set when a byte is ready to be transferred from the Receive Shift Register to the Receive Data Register SRX that is already full RDRF 1 The Receive Shift Register data is not transferred to the SRX The OR flag indicates that character s in the received data stream may have been lost The only valid data is located in the SRX OR is cleared when the SCI Status Register is read followed by a read of SRX The OR bit clears the FE and PE bits that is overrun error has higher priority than FE or PE OR is cleared by the hardware software SCI individual and stop resets 8 3 2 6 SSR Parity Error PE Bit 5 In the 11 bit Asynchronous modes the PE bit is set when an incorrect parity bit has been detected in the received character It is set simultaneously with RDRF for the byte which contains the parity error that is when the received word is transferred to the SRX If PE is set further data transfer into the SRX is not inhibited PE is cleared when the SCI Status Register is read followed by a read of SRX PE is also cleared by the hardware software SCI individual or stop reset In the 10 bit Asynchronous mode the 11 bit Multidrop mode and the 8 bit Synchronous mode
218. caler Range PSR Bit11 7 11 7 4 1 4 CRA Frame Rate Divider Control DC 4 0 Bits 16 12 7 12 7 4 1 5 CRA Reserved 17 7 13 7 4 1 6 CRA Alignment Control ALC 18 7 13 7 4 1 7 CRA Word Length Control WL 2 0 Bits 21 19 7 14 vi DSP56303UM AD MOTOROLA 7 4 1 8 7 4 1 9 7 4 2 7 4 2 1 7 4 2 1 1 7 4 2 1 2 7 4 2 2 7 4 2 3 7 4 2 4 7 4 2 5 7 4 2 6 7 4 2 7 7 4 2 8 7 4 2 9 7 4 2 10 7 4 2 11 7 4 2 12 7 4 2 13 7 4 2 14 7 4 2 15 7 4 2 16 7 4 2 17 7 4 2 18 7 4 2 19 7 4 2 20 7 4 2 21 7 4 2 22 7 4 2 23 7 4 3 7 4 3 1 MOTOROLA CRA Select SC1 as Transmitter 0 Drive Enable 5501 Bit 22 CRA Reserved Bit 23 ESSI Control Register B CRB CRB Serial Output Flags OF1 Bits 0 1 CRB Serial Output 0 OFO Bit 0 CRB Serial Output Flag 1 OF1 Bit 1 CRB Serial Control Direction 0 SCDO Bit 2 CRB Serial Control Direction 1 SCD1 Bit CRB Serial Control Direction 2 SCD2 Bit 4 CRB Clock Source Direction SCKD Bit 5 CRB Shift Direction SHFD Bit 6 CRB Frame Sync Length FSL 1 0 Bits 7 and 8 CRB Frame Sync Relative Timing FSR Bit 9 CRB Frame Sync Polarity FSP Bit 10 CRB Clock Polarity Bit 11 CRB Synchronous Asynchronous SYN Bit 12 CRB ESSI Mode Select MOD Bit 13 Enabling and Disabling Data Transmission from the ESSI CRB ESSI Transmit 2 Enable TE2 Bit14
219. cally disconnected Pins configured as 108 are not affected by the value of HGEN MOTOROLA DSP56303UM AD 6 13 Host Interface HI08 HI08 DSP Side Programmer s Model 6 5 6 2 HPCR Host Address Line 8 Enable HA8EN Bit 1 If HA8EN is set and HI08 is used in Multiplexed Bus mode then HA8 A1 is used as Host Address line 8 HA8 If this bit is cleared and 108 is used in Multiplexed Bus mode then HA8 HAL is used as a GPIO pin according to the value of the HDDR and HDR Note HASEN is ignored when 108 is not in the Multiplexed Bus mode HMUX is cleared 6 5 6 3 HPCR Host Address Line 9 Enable HA9EN Bit 2 If HA9EN is set and the 108 is used in Multiplexed Bus mode then HA9 HA2 is used as Host Address line 9 HA9 If this bit is cleared and the 108 is used in Multiplexed Bus mode then HA9 HA2 is configured as a GPIO pin according to the value of the HDDR and HDR Note is ignored when the 108 is not in the Multiplexed Bus mode HMUX is cleared 6 5 6 4 HPCR Host Chip Select Enable HCSEN Bit 3 If the HCSEN bit is set then HCS HA10 is used as Host Chip Select HCS in the Non multiplexed Bus mode HMUX is cleared and as Host Address line 10 HA10 in the Multiplexed Bus mode HMUX is set If this bit is cleared then HCS HA10 is configured as a GPIO pin according to the value of the HDDR and HDR 6 5 6 5 HPCR Host Request Enable HREN Bit 4 The HREN bit controls the host request pins
220. ccesses that are byte wide rap code expects to read 3 bytes forming a 24 bit word specifying the number of program words 3 bytes forming a 24 bit word specifying the address to start loading the program words and then 3 bytes forming 24 bit words The program words wil for each program word to be loaded ll be stored in contiguous PRAM memory locations starting at the specified starting address After reading the program words program execution starts from the same address where loading started The Host Inter Host Flag 0 the specified starti face bootstrap load program may be stopped by setting the his will start execution of the loaded program from ng address The base address of the HI08 in multiplexed mode is 0x80 and is not modified by the bootstrap code All the address lines are enabled and should be connected accordingly EFI EEE EL EEL OE EET PES LEE EE EEE ELE PA gg EL EEE LE EE EES LEE EEE If MC MB MA 111 then it loads the program RAM from the Host A 4 DSP56303UM AD MOTOROLA Interface programmed to operate in the MC68302 bus mode in single strobe pin configuration Bootstrap Programs The HOST MC68302 bootstrap code expects accesses that are byte wide The HOST MC68302 bootstrap code expects to read 3 bytes forming a 24 bit word specifying the number of program words 3 bytes forming
221. ce Buffer and Increment Pointer 10011 Reserved Address 101xx Reserved Address 11xx0 Reserved Address 11x0x Reserved Address 110xx Reserved Address 11111 No Register Selected MOTOROLA DSP56303UM AD 10 7 On Chip Emulation Module OnCE Controller 10 4 2 OnCE Decoder ODEC The OnCE Decoder ODEC supervises the entire OnCE module activity It receives as input the 8 bit command from the OCR a signal from JTAG Controller indicating that 8 24 bits have been received and update of the selected data register must be performed and a signal indicating that the core was halted The ODEC generates all the strobes required for reading and writing the selected OnCE registers 10 4 8 Status and Control Register OSCR The OnCE Status and Control Register OSCR is a 24 bit register used to enable the Trace mode of operation and to indicate the cause of entering the Debug mode The control bits are read write while the status bits are read only The OSCR bits are cleared on hardware reset The OSCR is shown in Figure 10 5 OnCE Status and Control Register Read Write Indicates reserved bits written as 0 for future compatibility 0705 Figure 10 5 Status and Control Register OSCR 10 4 3 1 Trace Mode Enable TME Bit 0 The Trace Mode Enable TME control bit when set enables the Trace mode of operation 10 4 3 2 Interrupt Mode Enable IME Bit 1 The Interrupt Mode Enable IME control bit when set caus
222. ch performs clock input division frequency multiplication and skew elimination and the Clock Generator CLKGEN which performs low power division and clock pulse generation Allows change of low power Divide Factor DF without loss of lock Output clock with skew elimination The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock input a feature that offers two immediate benefits lower frequency clock input reduces the overall electromagnetic interference generated by a system The ability to oscillate at different frequencies reduces costs by eliminating need to add additional oscillators to a system 1 6 5 JTAG Test Access Port and On Chip Emulation OnCE Module The DSP56300 core provides a dedicated user accessible Test Access Port that is fully compatible with the IEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture Problems associated with testing high density circuit boards have led to development of this standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group JTAG The DSP56300 core implementation supports circuit board test strategies based on this standard MOTOROLA DSP56303UM AD 1 11 DSP56303 Overview DSP56300 Core Functional Blocks The test logic includes a TAP consisting of four dedicated signal pins a 16 state controller and three test data registers A boundary scan register
223. ched into OMR when the RESET signal is deasserted If IRQD is asserted synchronous to CLKOUT multiple processors can be re synchronized using the WAIT instruction and asserting to exit the Wait state MODD IROD can tolerate 5 V 2 8 HOST INTERFACE 108 The 108 provides a fast parallel 8 bit port which may be connected directly to host bus 2 16 DSP56303UM AD MOTOROLA Signal Connection Descriptions Host Interface HI08 The 108 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers microprocessors DSPs and DMA hardware 2 8 1 Host Port Usage Considerations Careful synchronization is required when reading multiple bit registers that are written by another asynchronous system This is a common problem when two asynchronous systems are connected as they are in the Host port The considerations for proper operation are discussed in the following table Table 2 10 Host Port Usage Considerations Action Description Asynchronous read of When reading the receive byte registers Receive register High receive byte registers RXH Receive register Middle RXM or Receive register Low RXL the host interface programmer should use interrupts or poll the Receive Register Data Full RXDF flag which indicates that data is available This assures that the data in the receive byte registers will be valid Asynchronous wri
224. chine TMS is sampled on the rising edge of TCK and has an internal pull up resistor This input is 5 V tolerant TRST Input Input Test Reset TRST is an active low Schmitt trigger input signal used to asynchronously initialize the test controller TRST has an internal pull up resistor TRST must be asserted after power up This input is 5 V tolerant 2 36 DSP56303UM AD MOTOROLA Signal Connection Descriptions OnCE JTAG Interface Table 2 16 OnCE JTAG Interface Continued Signal Name State During Reset Signal Description DE Input Output Input Debug Event DE is an open drain bidirectional active low signal providing as an input a means of entering the Debug mode of operation from an external command controller and as an output a means of acknowledging that the chip has entered the Debug mode This signal when asserted as an input causes the DSP56300 core to finish the current instruction being executed save the instruction pipeline information enter the Debug mode and wait for commands to be entered from the debug serial input line This signal is asserted as an output for three clock cycles when the chip enters the Debug mode as a result of a debug request or as a result of meeting a breakpoint condition The DE has an internal pull up resistor This is not a standard part of the JTAG Test Access Port TAP Controller The signal connects dire
225. chronous only Synchronous Asynchronous Receiver Clock Mode Source nternal clock for Receiver 1 External clock from SCLK Transmitter Clock Mode Source Internal clock for Transmitter 1 External clock from SCLK Clock Out Divider 0 Divide clock by 16 before feed to SCLK 1 Feed clock to directly to SCLK SCI Clock Prescaler 0221 12 8 15 14 13 12 11 10 9 7 Reserved Program as 0 SCI Clock Control Register SCCR Figure D 17 SCIStatus and Clock Control Registers SSR SCCR MOTOROLA DSP56303UM AD D 31 PROGRAMMING REFERENCE Application Date Programmer Sheet 3 of 3 SCI Transmit Data Registers X FFFF97 Address X FFFF95 X SFFFF97 y c EEEgo Write Reset xxxxxx X SFFFF95 Note STX is same register decoded at four different addresses SCI Receive Data Registers X FFFF9A Address X FFFF98 X FFFF9A X FFFF99 Read Reset X FFFF98 Note STX is same register decoded at three different addresses SCI Receive Data Registers Figure D 18 SCI Receive and Transmit Data Registers SRX TRX D 32 DSP56303UM AD MOTOROLA PROGRAMMING REFERENCE Application Date Programmer Sheet 1 of 3 Timers PS 1 0 Prescaler Clock Source 00 Internal CLK 2 01 TIOO 10 TIO1 11 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 51 Pso 0 Prescaler Preload Value
226. cond function of the SAMPLE PRELOAD instruction is to initialize the BSR output cells prior to selection of EXTEST This initialization ensures that known data appears on the outputs when entering the EXTEST instruction 11 3 2 3 IDCODE B 3 0 0010 The IDCODE instruction selects the ID register This instruction is provided as a public instruction to allow the manufacturer part number and version of a component to be determined through the TAP Figure 11 4 shows the ID register configuration 281 27 22 21 17 16 12 11 Version Manufacturer Customer Part Number Identity Design Core Chip Center Number Derivative Number Number 0000 000110 00000 00011 00000001110 1 AA0718 Figure 11 4 JTAG ID Register One application of the ID register is to distinguish the manufacturer s of components on a board when multiple sourcing is used As more components emerge which conform to the IEEE 1149 1 standard it is desirable to allow for a MOTOROLA DSP56303UM AD 11 9 JTAG Port TAP Controller system diagnostic controller unit to blindly interrogate a board design in order to determine the type of each component in each location This information is also available for factory process monitoring and for failure mode analysis of assembled boards Motorola s Manufacturer Identity is 00000001110 The Customer Part Number consists of two parts Motorola Design Center Number bits 27 22 and a sequence number bits 21 12 The sequence
227. control 1 amp bidir X 103 control 1 amp bidir X 105 control 1 amp bidir X 107 control 1 amp bidir X 109 control 1 amp bidir X 111 control 1 amp bidir X 113 control 1 amp bidir X 115 control 1 amp DSP56303UM AD 1 dis rslt ty 1 dis rslt ty 2 amp 2 amp MOTOROLA 118 119 num end DSP56303 MOTOROLA 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 T3 138 139 140 141 142 143 BC 6 BC 1 cell BC 6 BC 1 UJ Q gt u w O F F O P NUN NM M ORD RS Ww uu ie ee ees H g 11 BC 1 BC 6 BC 1 BC 6 bidir X 117 control 1 amp func safe ccel bidir 119 control 1 amp bidir X 121 control 1 amp bidir X 123 control 1 amp bidir X 125 control 1 amp bidir X 124 input amp control 1 amp bidir X 130 control 1 amp bidir X 1325 control 1 amp bidir X 134 control 1 amp bidir X 136 control 1 amp bidir X 138 func safe ccel control 1 amp bidir X 140 control 1 amp bidir X 142 DSP56303UM AD DSP56303 BSDL Listing 1 2 amp 1 dis rslt 1 2 amp Z amp Z amp
228. ctly to the OnCE module to initiate Debug mode directly or to provide a direct external indication that the chip has entered the Debug mode All other interfacing with the OnCE module must occur through the JTAG port This input is 5 V tolerant MOTOROLA DSP56303UM AD 2 37 Signal Connection Descriptions OnCE JTAG Interface 2 38 DSP56303UM AD MOTOROLA SECTION 3 MEMORY CONFIGURATION MOTOROLA DSP56303UM AD Memory Configuration 3 1 3 2 3 3 3 4 3 5 3 2 MEMORY SPACES cess cee eee 3 3 RAM CONFIGURATION 3 5 MEMORY 5 3 7 MEMORY MAPS 233 x u d exte dues 3 9 INTERNAL MEMORY MAP DSP56303UM AD MOTOROLA Memory Configuration Memory Spaces 31 MEMORY SPACES The DSP56303 provides three independent memory spaces Program Xdata Y data Each memory space uses 24 bit addressing by default allowing access to 16 M of memory The program and data word length is 24 bits The DSP56303 provides a Sixteen bit Compatibility mode that effectively uses 16 bit addressing for each memory space allowing access to 64 K each of memory This mode puts Os in the most significant byte of the usual 24 bit program and data word and ignores the zeroed byte thus effectively using 16 bit program and data words The Sixteen bit Compatibility mode allows the DSP56303 to use 56000 object code without
229. d Internal Internal Reserved Reserved FFFOCO ROM ootstrap FF0000 FF0000 FF0000 External External 000C00 000C00 000800 Internal Program RAM 2K 000000 000000 Internal X data RAM 3K Internal Y data RAM 3K 000000 Bit Settings Memory Configuration Program X Data Y Data Addressable Cache Memory Size 0 1 0 2K 3K 3K None 16M 000 800 000 BFF 000 BFF AA0559 Figure 3 3 Switched Program RAM 0 1 0 3 12 DSP56303UM AD MOTOROLA Program Memory Configuration Memory Maps X Data Y Data eC BEERS Internal I O SFFFFFF External I O FFFF80 FFFF80 Internal 000 FFFOOO Reserved Internal Internal Reserved Reserved Bootstrap ROM FF0000 FF0000 FF0000 External External External 000800 000C00 000C00 000400 LR Internal Internal Internal X data RAM Y data RAM Program 3K 3K 0000001 8000000 5000000 Bit Settings Memory Configuration Program X Data Y Data Addressable zie RAM RAM Cache Memory Size 0 1 1 1K 3K 3K 1K 16M 000 3FF 5000 000 BFF 400 7FF Figure 3 4 Switched Program RAM and Instruction Cache Enabled 0 1 1 MOTOROLA DSP56303UM AD AA0563 3 13 Memory Configuration Memory Maps Program X Data Y Data FFFF SFFFF internal 1 0 External I O FF80
230. d MD in the OMR The contents of the MA MB MC and MD bits determine which bootstrap mode the DSP56303 enters DSP56303UM AD MOTOROLA Core Configuration Bootstrap Program 1 If MA MB MC and MD are all cleared Bootstrap mode 0 the program bypasses the bootstrap ROM and the DSP56303 starts loading instructions from external program memory location C00000 2 If MA MB and MC are cleared and MD is set Bootstrap mode 8 the program bypasses the bootstrap ROM and the DSP56303 starts loading in instruction values from external program memory location 008000 3 Otherwise Bootstrap modes 1 7 DSP56303 jumps to the bootstrap program entry point at 0000 If the bootstrap program is loading via the Host Interface HI08 setting the bit in the HSR causes the DSP56303 to stop loading and begin execution of the loaded program at the specified start address See Table 4 1 on page 4 4 for a tabular description of the mode bit settings for the operating modes The bootstrap program options except modes 0 and 8 can be invoked at any time by setting the MA MB MC and MD bits in the OMR and jumping to the bootstrap program entry point 0000 The mode selection bits in the OMR can be set directly by software Bootstrap modes 0 and 8 are the normal functioning modes for the DSP56303 Bootstrap modes 1 7 are the bootstrap modes proper In bootstrap modes 1 7 the bootstrap program expects the following data
231. d MSB first if SHFD 0 4 bit fractional format ALC 0 32 bit mode is not shown 0687 Figure 7 17 ESSI Data Path Programming Model SHFD 1 7 32 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI ESSI Programming Model 7 4 4 ESSI Receive Shift Register The 24 bit Receive Shift Register see Figure 7 16 and Figure 7 17 receives the incoming data from the Serial Receive Data pin Data is shifted in by the selected internal external bit clock when the associated frame sync I O is asserted It is assumed that data is received Most Significant Bit MSB first if SHFD is cleared and Least Significant Bit LSB first if SHFD is set Data is transferred to the ESSI Receive Data Register after 8 12 16 24 or 32 serial clock cycles are counted depending on the word length control bits in the CRA 7 4 5 ESSI Receive Data Register RX The Receive Data Register RX is a 24 bit read only register that accepts data from the Receive Shift Register as it becomes full see Figure 7 16 and Figure 7 17 The data read is aligned according to the value of the ALC bit When the ALC bit is cleared the MSB is Bit 23 and the least significant byte is unused When the ALC bit is set the MSB is Bit 15 and the most significant byte is unused Unused bits are read as Os If the associated interrupt is enabled the DSP is interrupted whenever the RX register becomes full 7 4 6 ESSI Transmit Shift Registers The three 24
232. d software reset 8 16 DSP56303UM AD MOTOROLA Serial Communication Interface SCI SCI Programming Model 8 3 3 3 SCCR SCI Clock Prescaler SCP Bit 13 The SCP bit selects a divide by 1 SCP is cleared or divide by 8 SCP is set prescaler for the clock divider The output of the prescaler is further divided by 2 to form the SCI clock Hardware and software reset clear SCP 8 3 3 4 SCCR Receive Clock Mode Source Bit RCM Bit 14 RCM selects whether an internal or external clock is used for the receiver If RCM is cleared the internal clock is used If RCM is set the external clock from the SCLK pin is used Hardware and software reset clear RCM Table 8 2 TCM and RCM Bit Configuration RCM TX Clock RX Clock SCLK Pin Mode 0 0 Internal Internal Output Synchronous Asynchronous 0 1 Internal External Input Asynchronous Only 1 0 External Internal Input Asynchronous Only 1 1 1 External Input Synchronous Asynchronous MOTOROLA DSP56303UM AD 8 17 Serial Communication Interface SCI SCI Programming Model Divide 12 bit Counter Prescaler Divide By 2 Divide by By 2 1078 CD11 CDO SOP Internal Clock Divide SCI Core Logic By 16 Uses Divide by 16 for Asynchronous Uses Divide by 2 for Timer Synchronous Interrupt STMINT If Asynchronous Divide by 1 or 16 If Synchronous Divide By 2 BPS ae SCKP 0 w 64 x 7 x SCP 1 x CD 1 SCKP SCKP
233. d until the timer is disabled by clearing the TE bit The counter contents can be read at any time by reading the TCR register Note In this mode internal logic preserves the TIO value and direction for an additional 2 5 internal clock cycles after the DSP56303 hardware reset signal is asserted This ensures that a valid reset signal is generated when the TIO pin is used to reset the DSP56303 9 4 5 Reserved Modes Modes 8 11 12 13 14 and 15 are reserved 9 4 6 Special Cases The following special cases apply during Wait and Stop state 9 4 6 1 Timer Behavior during Wait Timer clocks are active during the execution of the WAIT instruction and timer activity is undisturbed If a timer interrupt is generated the DSP56303 leaves the Wait state and services the interrupt 9 4 6 2 Timer Behavior during Stop During the execution of the STOP instruction the timer clocks are disabled timer activity is stopped and the TIO pins are disconnected Any external changes that happen to the TIO pins are ignored when the DSP56303 is the Stop state To ensure correct operation the timers should be disabled before the DSP56303 is placed into the Stop state 9 4 7 DMA Trigger Each timer can also be used to trigger DMA transfers For this to occur a DMA channel must be programmed to be triggered by a timer event The timer issues a DMA trigger on every event in all modes of operation The DMA channel does not have the capability to save multiple D
234. data when the data in the Receive Shift Register is transferred into the Receive Data Register If it is not enabled the IFO bit is cleared Hardware software ESSI individual and stop reset clear the IFO bit 7 4 3 2 SSISR Serial Input Flag 1 IF1 Bit 1 The IF1bit is enabled only when SC1 is an input flag and the Synchronous mode is selected i e when SC1 is programmed as ESSI in the Port Control Register PCR the SYN bit is set and TE2 and SCD1 bits are cleared The ESSI latches data present on the SC1 pin during reception of the first received bit after the frame sync is detected The IF1 bit is updated with this data when the data in the Receive Shift Register is transferred into the Receive Data Register If it is not enabled the IF1 bit is cleared Hardware software ESSI individual and stop reset clear the IF1 bit 7 4 3 3 SSISR Transmit Frame Sync Flag TFS Bit 2 When set TFS indicates that a transmit frame sync occurred in the current time slot TFS is set at the start of the first time slot in the frame and cleared during all other time slots If the transmitter is enabled data written to a Transmit Data Register during the time slot when TFS is set will be transmitted in Network mode during the second time slot in the frame TFS is useful in Network mode to identify the start of a frame TFS is valid only if at least one transmitter is enabled TEO TE1 or TE2 are set TFS is cleared by hardware software
235. ddress Arithmetic Logic Unit Address ALU Each Address ALU has four sets of register triplets and each register triplet is composed of an address register an offset register and a modifier register The two Address ALUs are identical Each contains a 16 bit full adder called an offset adder A second full adder called a modulo adder adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register A third full adder called a reverse carry adder is also provided The offset adder and the reverse carry adder are in parallel and share common inputs The only difference between them is that the carry propagates in opposite directions Test logic determines which of the three summed results of the full adders is output MOTOROLA DSP56303UM AD 1 9 DSP56303 Overview DSP56300 Core Functional Blocks Each Address ALU can update one address register from its respective address register file during one instruction cycle The contents of the associated modifier register specifies the type of arithmetic to be used in the address register update calculation The modifier value is decoded in the Address ALU 1 6 3 Program Control Unit PCU The Program Control Unit PCU performs instruction prefetch instruction decoding hardware DO loop control and exception processing The PCU implements a seven stage pipeline and controls the different processing states of the DSP56300 core The PCU consi
236. ddress Bit capability It allows the DSP56303 to share a single serial line efficiently with other peripherals These modes are selected using the WD 0 2 bits in the SCR The Synchronous data mode is essentially a high speed shift register used for I O expansion and stream mode channel interfaces Data synchronization is accomplished by the use of a gated transmit and receive clock that is compatible with the Intel 8051 serial interface mode 0 The Asynchronous modes are compatible with most UART type serial devices Standard RS232C communication links are supported by these modes MOTOROLA DSP56303UM AD 8 21 Serial Communication Interface SCI Operating Modes The Multidrop Asynchronous modes are compatible with the MC68681 DUART the M68HC11 SCI interface and the Intel 8051 serial interface 8 4 1 SCI After Reset There are four different methods of resetting the SCI 1 2 8 22 Hardware reset Software reset Both hardware and software resets clear the Port Control Register bits which configure all I O as GPIO input The SCI remains in the Reset state as long as all SCI pins are programmed as GPIO CC2 and CCO all are cleared the SCI becomes active only when at least one of the SCI I O pins is not programmed as GPIO Individual reset During program execution the CC2 CC1 and bits can be cleared individual reset which causes the SCI to stop serial activity and enter the Reset state All SCI
237. de MOTOROLA DSP56303UM AD 2 19 Signal Connection Descriptions Host Interface HI08 Table 2 11 Host Interface Continued State Signal During ENS NE Type Reset or Signal Description Stop HRW Input Discon Host Read Write When HI08 is programmed to nected interface a single data strobe host bus and the HI Internally function is selected this signal is the Host Read Write HRW input HRD HRD Input Host Read Data When 108 is programmed to interface a double data strobe host bus and the HI function is selected this signal is the Host Read Data strobe HRD Schmitt trigger input The polarity of the data strobe is programmable but is configured as active low HRD after reset PB11 Input or Port B 11 When the 108 is configured as GPIO Output through the HPCR this signal is individually programmed as an input or output through the HDDR This input is 5 V tolerant This pin is electrically disconnected internally during Stop mode 2 20 DSP56303UM AD MOTOROLA Signal Connection Descriptions Host Interface HI08 Table 2 11 Host Interface Continued Signal Name State Durin Type Reset T e Signal Description Stop HDS HDS HWR HWR PB12 Input Discon Host Data Strobe When 108 is programmed to nected interface a single data strobe host bus and the HI Internally function is selected this signal is the Host Data Strobe
238. de 5 Register Name TRIPLE Timer 0 Control Status Register 5 FF8E FFFF8E Timer 0 Load Register TLRO FF8D FFFF8D Timer 0 Compare Register TCPRO FF8C FFFF8C Timer 0 Count Register TCRO FF8B FFFF8B Timer 1 Control Status Register TCSR1 FF8A Timer 1 Load Register TLR1 FF89 FFFF89 Timer 1 Compare Register TCPR1 FF88 FFFF88 Timer 1 Count Register TCR1 FF87 FFFF87 Timer 2 Control Status Register TCSR2 FF86 FFFF86 Timer 2 Load Register TLR2 FF85 FFFF85 Timer 2 Compare Register TCPR2 FF84 FFFF84 Timer 2 Count Register TCR2 FF83 FFFF83 Timer Prescaler Load Register TPLR FF82 FFFF82 Timer Prescaler Count Register TPCR FF81 FFFF81 Reserved FF80 FFFF80 Reserved D 10 DSP56303UM AD MOTOROLA PROGRAMMING REFERENCE 0 3 INTERRUPT ADDRESSES AND SOURCES Table D 2 Interrupt Sources Interrupt puny Starting monty Interrupt Source Address reve Range VBA 00 3 Hardware RESET VBA 02 3 Stack Error VBA 04 3 Illegal Instruction VBA 06 3 Debug Request Interrupt VBA 08 3 Trap VBA 0A 3 Non Maskable Interrupt NMI VBA 0C 3 Reserved VBA 0E 3 Reserved VBA 10 0 2 IRQA VBA 12 0 2 IROB VBA 14 0 2 IROC VBA 16 0 2 IROD VBA 18 0 2 DMA Channel 0 VBA 1A 0 2 DMA Channel 1 VBA 1C 0 2 DMA Channel 2 VBA 1E 0 2 DMA Channe
239. depends on the state of TREQ and RREO in the H108 The INIT command which is local to 08 is designed to conveniently configure the 108 into the desired data transfer mode The effect of the INIT command is described in Table 6 10 When the host sets the INIT bit the HI08 hardware executes the INIT command The interface hardware clears the INIT bit after the command has been executed Table 6 10 INIT Command Effects Transfer Direction TREO RREQ After INIT Execution Initialized 0 0 INIT 0 None 0 1 INIT 0 RXDF 0 HTDE 1 DSP to Host 6 24 DSP56303UM AD MOTOROLA Host Interface HI08 HI08 External Host Programmer s Model Table 6 10 INIT Command Effects Transfer Direction TREO RREQ After INIT Execution Initialized 1 0 INIT 0 TXDE 1 HRDF 0 Host to DSP 1 1 INIT 0 RXDF 0 HTDE 1 TXDE 1 Host to from DSP HRDF 0 6 6 2 Command Vector Register CVR The is used by the host processor to cause the DSP56303 to execute an interrupt The host command feature is independent of any of the data transfer mechanisms in the 08 It can be used to cause any of the 128 possible interrupt routines in the DSP core to be executed 7 6 5 4 3 2 1 0 Hve Hvo 0669 Figure 6 13 Command Vector Register 6 6 2 1 CVR Host Vector HV 0 6 Bits 0 6 The seven HV b
240. des connection with a number of industry standard DSPs microcomputers and microprocessors without requiring any additional logic DSP core views the 08 as a memory mapped peripheral occupying eight 24 bit words in data memory space The DSP can use the HI08 as a memory mapped peripheral using either standard polled or interrupt programming techniques Separate transmit and receive data registers are double buffered to allow the DSP and host processor to efficiently transfer data at high speed Memory mapping allows DSP core communication with HI08 registers to be accomplished using standard instructions and addressing modes 1 10 3 Enhanced Synchronous Serial Interface ESSI The DSP56308 provides two independent and identical Enhanced Synchronous Serial Interfaces ESSI Each ESSI provides a full duplex serial port for communication with a variety of serial devices including one or more industry standard codecs other DSPs microprocessors and peripherals that implement the Motorola SPI The ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator The capabilities of the ESSI include Independent asynchronous or shared synchronous transmit and receive sections with separate or shared internal external clocks and frame syncs Normal mode operation using frame sync Network mode operation with as many as 32 time slots Programmable word length 8 12 or 16 bits Progra
241. described by the operating mode i e idle line sequence MOTOROLA DSP56303UM AD 8 25 Serial Communication Interface SCI Operating Modes Data is transmitted only after the transmitter is enabled TE 1 and after transmitting the initialization sequence depending on the operating mode 8 4 4 Preamble Break and Data Transmission Priority Two or three transmission commands may be set simultaneously 1 A preamble TE is set 2 A break SBK is set or is cleared 3 There is data for transmission TDRE is cleared After the current character transmission if two or more of these commands are set the transmitter executes them in the following order 1 Preamble 2 Break 3 Data 8 4 5 SCI Exceptions The SCI can cause five different exceptions in the DSP These exceptions are as follows ordered from the highest to the lowest priority 1 SCIReceive Data with Exception Status is caused by Receive Data Register full with a receiver error parity framing or overrun error Clearing the pending interrupt is done by reading the SCI status register followed by a read of SRX A long interrupt service routine should be used to handle the error condition This interrupt is enabled by SCR Bit 16 RETE 2 SCI Receive Data is caused by Receive Data Register full Reading SRX clears the pending interrupt This error free interrupt can use a fast interrupt service routine for minimum overhead This interrupt is enabled b
242. described in Figure 10 6 contains a latch for the addresses which are registers that store the upper and lower address limit address comparators and a breakpoint counter TCK TDO TDI Memory Bus Select Memory Address Latch Address Comparator 0 TDI TCK Breakpoint Control Memory Breakpoint Selection Breakpoint Occurred Count 0 ISBKPT AA0706 Figure 10 6 OnCE Memory Breakpoint Logic 0 Address comparators are useful in determining where a program may be getting lost or when data is being written where it should not be written They are also useful in halting a program at a specific point to examine change registers or memory Using address comparators to set breakpoints enables the user to set breakpoints in RAM or 10 10 DSP56303UM AD MOTOROLA On Chip Emulation Module OnCE Memory Breakpoint Logic ROM and while in any operating mode Memory accesses are monitored according to the contents of the OBCR as specified in OnCE Breakpoint Control Register OBCR on page 10 12 10 5 1 OnCE Memory Address Latch OMAL The OnCE Memory Address Latch OMAL is a 16 bit register that latches the PAB or YAB on every instruction cycle according to 51 50 bits in OBCR 10 5 2 OnCE Memory Limit Register 0 OMLRO The OnCE Memory Limit Register 0 OMLRO is a 16 bit register that stores memory breakpoint limit OMLRO can be read or written through t
243. ding circular buffering End of block transfer interrupts Triggering from interrupt lines and all peripherals 1 10 DSP56303 ARCHITECTURE OVERVIEW The DSP56303 is designed to perform a wide variety of fixed point digital signal processing functions In addition to the core features previously discussed the DSP56303 provides the following peripherals As many as thirty four user configurable GPIO pins 8 bit parallel Host Interface HI08 to external hosts Dual Enhanced Synchronous Serial Interface ESSI Serial Communications interface SCI Triple timer module Memory Switch mode Four external interrupt mode control lines 1 10 1 GPIO Functionality The General Purpose I O GPIO port consists of as many as thirty four programmable pins all of which are also used by the peripherals 108 ESSI SCI and Timer There are no dedicated GPIO pins The pins are configured GPIO after reset The GPIO functionality for each peripheral is controlled by three memory mapped registers per peripheral The techniques for register programming for all GPIO functionality is very similar between these interfaces MOTOROLA DSP56303UM AD 1 15 DSP56303 Overview DSP56303 Architecture Overview 1 10 2 Host Interface 108 The Host Interface 108 is a byte wide full duplex double buffered parallel port that can be connected directly to the data bus of a host processor The HI08 supports a variety of buses and provi
244. dresses Of DMA2 EQU SFFFFE7 DMA2 Source Address Register EQU SFFFFE6 DMA2 Destination Address Register EQU SFFFFE5 DMA2 Counter EQU SFFFFEA DMA2 Control Register Register Addresses Of DMA4 EQU SFFFFE3 DMA3 Source Address Register EQU SFFFFE2 DMA3 Destination Address Register EQU SFFFFEl DMA3 Counter EQU SFFFFEO DMA3 Control Register Register Addresses Of DMA4 EQU SFFFFDE DMA4 Source Address Register EQU SFFFFDE DMA4 Destination Address Register EQU SFFFFDD DMA4 Counter EQU SFFFFDC DMA4 Control Register Register Addr sses Of DMA5 EQU EQU EQU EQU SFFE SFFE SFFE SFFE A FD9 FD8 DMA Control Register EQU EQU EQU EQU EQU Cu lt C lt MOTOROLA 53 Q e DMA5 DMA5 DMA5 DMA5 Source Address Register Destination Address Register Counter Control Register Source Space Mask DSSO Dss1 A Source Memory space 0 A Source Memory space 1 A Destination Space Mask DDS DDS1 Destination Memory Space 0 Destination Memory Space 1 Address Mode Mask 5 Address Mode Address Mode Address Mode Address Mode Address Mode UUU UUUaAu o g g g g DSP56303UM AD B 11 Equates
245. dure is depicted in Table 10 12 Table 10 12 TMS Sequencing for DEBUG_REQUEST Step TMS JTAG Port OnCE Module Note a 0 Run Test Idle Idle b 1 Select DR Scan Idle 1 Select IR Scan Idle d 0 Capture IR Idle The status is sampled in the shifter e 0 Shift IR Idle The four bits of the JTAG DEBUG_REQUEST 0111 are A shifted in while status is elo Shift IR Idle DSP56303UM AD 10 29 On Chip Emulation Module Examples of JTAG and OnCE interaction Table 10 12 TMS Sequencing for DEBUG_REQUEST Continued Step TMS JTAG Port OnCE Module Note f 1 Exit1 IR Idle 1 Update IR Idle The debug request is generated 1 Select DR Scan Idle i 1 Select IR Scan Idle j 0 Capture IR Idle The status is sampled in the shifter k 0 Shift IR Idle The four bits of the JTAG DEBUG_REQUEST 0111 are VVRRTUE VER E ER ae EE TE EU shifted in while status is k 0 Shift IR Idle Safe pul 1 1 Exit1 IR Idle 1 Update IR Idle n 0 Run Test Idle Idle This step is repeated enabling an external command controller to ee ee ere eee poll the status n 0 Run Test Idle Idle In step n the external command controller verifies that the OS 1 0 bits have the value 11 indicating that the chip has entered the Debug mode If the chip has not yet entered the Debug mode the external c
246. e Reserved Bit Figure 4 5 Address Attribute Registers AARO AAR3 X FFFFF9 FFFFF6 4 9 BOUNDARY SCAN REGISTER BSR The Boundary Scan Register BSR in the DSP56303 JTAG implementation contains bits for all device signal and clock pins and associated control signals All DSP56303 bidirectional pins have a corresponding register bit in the boundary scan register for pin data and are controlled by an associated control bit in the boundary scan register The BSR is listed in Section 11 The JTAG code listing is in Appendix C Es MOTOROLA DSP56303UM AD 4 19 Core Configuration JTAG Boundary Scan Register BSR 4 20 DSP56303UM AD MOTOROLA MOTOROLA SECTION 5 GENERAL PURPOSE I O DSP56303UM AD 5 1 General Purpose I O 5 1 5 2 5 2 INTRODUCTION nurul sh EE 5 3 PROGRAMMING MODEL 5 3 DSP56303UM AD MOTOROLA General Purpose I O Introduction 51 INTRODUCTION The DSP56303 provides thirty four bidirectional signal pins that can be configured as General Purpose Input Output GPIO pins or as peripheral dedicated signal pins No dedicated GPIO pins are provided All of these pins are GPIO by default after reset The control register settings of the DSP56303 s peripherals determine whether these pins are used as GPIO or as peripheral dedicated signal pins This section describes how pins may be used as GPIO 5 2 PROGRAMMING MODEL The Signals
247. e 10 9 2 PAB Register for Decode OPABDR The OnCE Register for Decode Register OPABDR is a 16 bit register that stores the address of the instruction currently on the PDB This is the instruction whose fetch was completed before the chip has entered the Debug mode The OPABDR can only be read through the JTAG port This register is not affected by the operations performed during the Debug mode 10 20 DSP56303UM AD MOTOROLA On Chip Emulation Module Trace Buffer 10 9 3 PAB Register for Execute OPABEX The OnCE PAB Register for Execute OPABEX is a 16 bit register that stores the address of the instruction currently in the Instruction Latch This is the instruction that would have been decoded and executed if the chip would not have entered the Debug mode The OPABEX register can only be read through the JTAG port This register is not affected by the operations performed during the Debug mode 10 9 4 Trace Buffer The Trace buffer stores the addresses of the last twelve change of flow instructions that were executed as well as the address of the last executed instruction The Trace buffer is implemented as a circular buffer containing twelve 17 bit registers and one 4 bit counter All the registers have the same address but any read access to the Trace buffer address causes the counter to increment thus pointing to the next Trace buffer register The registers are serially available to the external command controll
248. e Trace Buffer 10 8 3 GDB Register OGDBR The OnCE GDB Register OGDBR is a 16 bit latch that can only be read through the JT AG port The OGDBR is not actually required for restoring the pipeline status but is required as a means of passing information between the chip and the external command controller The OGDBR is mapped on the X internal I O space at address FFFC Whenever the external command controller needs the contents of a register or memory location it forces the chip to execute an instruction that brings that information to the OGDBR Then the contents of the OGDBR are delivered serially to the external command controller by the command READ GDB REGISTER 10 9 TRACE BUFFER To ease debugging activity and keep track of program flow the DSP56300 core provides a number of on chip dedicated resources There are three read only PAB registers that give pipeline information when the Debug mode is entered and a Trace buffer that stores the address of the last instruction that was executed as well as the addresses of the last twelve change of flow instructions 10 9 1 OnCE PAB Register for Fetch OPABFR The OnCE PAB Register for Fetch Register OPABFR is a 16 bit register that stores the address of the last instruction whose fetch was started before the Debug mode was entered The can only be read through the JTAG port This register is not affected by the operations performed during the Debug mod
249. e if SCKP 0 or on the negative edge if SCKP 1 of the 1 X serial clock 7 For the Asynchronous mode the output clock is continuous 8 For the Synchronous mode a 1 X clock is used for the output or input baud rate The maximum 1 X clock is the crystal frequency divided by 8 9 For the Synchronous mode the clock is gated 10 For the Synchronous mode the transmitter and receiver are synchronous with each other Select 8 or 9 bit Words Idle Line 0 1 2 3 4 5 6 7 8 RX TX Data SSFTD 0 Start Stop Start x1 Clock x16 Clock SCKP 0 0692 Figure 8 5 16 x Serial Clock 8 3 3 1 SCCR Clock Divider CD 11 0 Bits 11 0 The CD 11 0 bits specify the divide ratio of the prescale divider in the SCI clock generator A divide ratio from 1 to 4096 CD 11 0 000 to FFF can be selected Hardware and software reset clear CD11 CD0 8 3 3 2 SCCR Clock Out Divider COD Bit 12 The clock output divider is controlled by COD and the SCI mode If the SCI mode is synchronous the output divider is fixed at divide by 2 If the SCI mode is asynchronous either If COD is cleared and SCLK is an output 1 and RCM are both cleared the SCI clock is divided by 16 before being output to the SCLK pin Thus the SCLK output is a 1 X clock e If COD is set and SCLK is an output the SCI clock is fed directly out to the SCLK pin Thus the SCLK output is a 16 X baud clock The COD bit is cleared by hardware an
250. e ESSI ESSI Data and Control Pins End of frame interrupt added Drive Enable pin added to be used with transmitter 0 Audio Enhancements Three transmitters per ESSI for six channel surround sound General Enhancements Cantrigger DMA interrupts receive or transmit Separate exception enable bits Other Changes One divide by 2 removed from the internal clock source chain CRA PSR bit definition is reversed Gated Clock mode not available 7 3 ESSIDATA AND CONTROL PINS Three to six pins are required for ESSI operation depending on the operating mode selected The Serial Transmit Data STD pin and Serial Control SCO and SC1 pins are fully synchronized to the clock if they are programmed as transmit data pins 7 3 1 Serial Transmit Data Pin STD The STD pin is used for transmitting data from the Serial Transmit Shift Register STD is an output when data is being transmitted from Shift Register With an internally generated bit clock the STD pin becomes a high impedance output pin for a full clock period after the last data bit has been transmitted If sequential data words are being transmitted the STD pin does not assume a high impedance state The STD pin may be programmed as a General Purpose Input Output GPIO pin P5 when the ESSI STD function is not being used 7 3 2 Serial Receive Data Pin SRD The SRD pin receives serial data and transfers the data to the ESSI Receive Sh
251. e SCI GPIO Pins and Registers then the corresponding 1 bit reflects the value of this pin If a port pin i is configured as a GPIO output then the value of the corresponding 1 bit is reflected on this pin 7 6 5 4 3 2 1 0 P01 epo 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 eer Reserved Bit Read as 0 Should be Written with 0 for Future Compatibility 0697 Figure 8 10 Port Data Register PDRE Note Hardware and software reset clear all PDRE bits MOTOROLA DSP56303UM AD 8 29 Serial Communication Interface SCI GPIO Pins and Registers 8 30 DSP56303UM AD MOTOROLA MOTOROLA SECTION 9 TRIPLE TIMER MODULE DSP56303UWAD 9 1 Triple Timer Module 9 1 9 2 9 3 9 4 9 2 INTRODUCTION eee eRe 9 3 TRIPLE TIMER MODULE ARCHITECTURE 9 3 TRIPLE TIMER MODULE PROGRAMMING MODEL 9 5 TIMER MODES OF 9 16 DSP56303UM AD MOTOROLA Triple Timer Module Introduction 9 1 INTRODUCTION This section describes the internal triple timer module in the DSP56303 Each timer has a single pin that can be used as a GPIO pin or as a timer pin These three timers can be used to generate timed pulses or as pulse width modulators They can also be used as an event counter to capture an event or to measure the width or period o
252. e 7 4 Mode and Pin Definition Table Control Bits ESSI PINS SYN TE1 2 RE SCO SC1 SC2 SCK STD SRD 0 0 X X 0 U U U U U U 0 0 X X 1 RXC FSR U U U RD 0 1 X X 0 U U FST TXC TDO U 0 1 X X 1 RXC FSR FST TXC TDO RD 1 0 0 0 0 U U U U U U 1 0 0 0 1 F0 U F1 TOD U FS XC U RD 1 0 0 1 0 F0 U TD2 FS XC U U 7 24 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI ESSI Programming Model Table 7 4 Mode and Pin Definition Table Continued Control Bits ESSI PINS SYN TE1 TE2 RE SCO 5 1 SC2 SCK STD SRD 1 0 0 1 1 FO U TD2 FS XC U RD 1 0 1 0 0 TD1 F1 TOD U FS XC U U 1 0 1 0 1 TD1 F1 TOD U FS XC U RD 1 0 1 1 0 101 102 FS XC U U 1 0 1 1 1 TD1 TD2 FS XC U RD 1 1 0 0 0 FO U F1 TOD U FS XC TDO U 1 1 0 0 1 FO U F1 TOD U FS XC TDO RD 1 1 0 1 0 FO U TD2 FS XC TDO U 1 1 0 1 1 FO U TD2 FS XC TDO RD 1 1 1 0 0 TD1 F1 TOD U FS XC TDO U 1 1 1 0 1 TD1 F1 TOD U FS XC TDO RD 1 1 1 1 0 101 102 FS XC TDO U 1 1 1 1 1 101 102 FS XC TDO RD TXC Transmitter Clock Note RXC Receiver Clock Note XC Transmitter Receiver Clock Synchronous Operation Note FST Transmitter Frame Sync Note FSR Receiver Frame Sync Note FS Transmitter Frame Sync Synchronous Operation Note TDO gt Transmit Data 0 Note TD1
253. e HFObit is used as a general purpose flag for host to DSP communication may be set or cleared by the host processor and cannot be changed by the DSP56303 is reflected in the HSR on the DSP side of the 108 6 6 1 5 ICR Host Flag 1 HF1 Bit 4 The HF1 bit is used as a general purpose flag for host to DSP communication HF1 may be set or cleared by the host processor and cannot be changed by the DSP56303 1 is reflected in the HSR on the DSP side of the 108 6 6 1 6 ICR Host Little Endian HLEND Bit 5 If the HLEND bit is cleared the 108 can be accessed by the host in big endian byte order If set the 108 can be accessed by the host in little endian byte order If the HLEND bit is cleared the RXH TXH register is located at address 5 the RXM TXM register at 6 and the RXL TXL register at 7 If the HLEND bit is set the RXH TXH register is located at address 7 the RXM TXM register at 6 and the RXL TXL register at 5 6 6 1 7 ICR Reserved Bit Bit 6 This bit is reserved It is read as 0 and should be written with 0 6 6 1 8 ICR Initialize Bit INIT Bit 7 The INIT bit is used by the host processor to force initialization of the HI08 hardware During initialization HI08 transmit and receive control bits are configured Using the INIT bit to initialize the HI08 hardware may or may not be necessary depending on the software design of the interface The type of initialization done when the INIT bit is set
254. e Host Receive Data Register HRX contains data from the host processor HRDF is set when data is transferred from the TXH TXM TXL registers to the HRX register If HRDF is set the 108 generates receive data full DMA request HRDF is cleared when is read by the DSP core can also be cleared by the host processor using the initialize function 6 5 4 2 HSR Host Transmit Data Empty HTDE Bit 1 The HTDE bit indicates that the Host Transmit Data Register HTX is empty and can be written by the DSP core HTDE is set when the HTX register is transferred to the RXH RXM RXL registers HTDE can also be set by the host processor using the initialize function If HTDE is set the HI08 generates a transmit data full request HTDE is cleared when HTX is written by the DSP core 6 5 4 3 HSR Host Command Pending HCP Bit 2 The HCP bit indicates that the host has set the HC bit and that a host command interrupt is pending The HCP bit reflects the status of the HC bit in the CVR HC and MOTOROLA DSP56303UM AD 6 11 Host Interface HI08 HI08 DSP Side Programmer s Model HCP are cleared by the 08 hardware when the interrupt request is serviced by the DSP core If the host clears HC HCP is also cleared 6 5 4 4 HSR Host Flags 0 1 HF 1 0 Bits 3 4 1 0 bits are used as general purpose flags for host to DSP communication HF 1 0 may be set or cleared by the host These bits reflect the status of host flags HF 1
255. e masma msn 2 7 PHASE LOCK LOOP 2 7 EXTERNAL MEMORY EXPANSION PORT PORT A 2 8 INTERRUPT AND MODE 2 14 HOST INTERFACE HI08 2 16 ENHANCED SYNCHRONOUS SERIAL INTERFACE 0 ESSIO DAS 2 24 ENHANCED SYNCHRONOUS SERIAL INTERFACE 1 2 29 SERIAL COMMUNICATION INTERFACE SCI 2 32 TIMERS hott oa m E EE 2 34 ONCE JTAG 2 35 DSP56303UM AD MOTOROLA 2 1 SIGNAL GROUPINGS Signal Connection Descriptions Signal Groupings The input and output signals of the DSP56303 are organized into functional groups as shown in Table 2 1 and as illustrated in Figure 2 1 The DSP56303 is operated from 3 V supply however some of the inputs can tolerate 5 V A special notice for this feature is added to the signal descriptions of those inputs Table 2 1 DSP56303 Functional Signal Groupings Functional Grou Number of Detailed P Signals Description Power Vcc 18 Table 2 2 Ground GND 19 Table 2 3 Clock 2 Table 2 4 PLL 3 Table 2 5 Address Bus 18 Table 2 6 1 Data Bus 24 Table 2 7 Bus Control 13 Table 2 8 Interrupt and Mode Control 5 Table 2 9 Host Interface 108 Port B2 16 Table 2 11 Enhanced Synchronous Serial Interface Ports C and 12 Table 2 12 ESSI p
256. e may be performed using a single instruction 5 If an interrupt trigger event occurs at a time when not all interrupt trigger configuration steps have been performed the event will be ignored forever the event will not be queued in this case 6 If interrupts derived from the core or other peripherals need to be enabled at the same time as ESSI interrupts step f should be done last 7 5 4 Operating Modes Normal Network and On Demand The ESSI has three basic operating modes and several data operation formats These modes can be programmed using the ESSI Control Registers The data operation formats available to the ESSI are selected by setting or clearing control bits in the CRA and CRB These control bits WL 2 1 MOD SYN FSL 1 0 FSR FSP and SHFD 7 5 4 1 Normal Network On Demand Mode Selection Selecting between the Normal mode and Network mode is accomplished by clearing or setting the MOD bit in the CRB In Normal mode the ESSI sends or receives one data word per frame per enabled receiver or transmitter In Network mode two to thirty two time slots per frame may be selected During each frame zero to thirty two data words may be received or transmitted from each enabled receiver or transmitter In either case the transfers are periodic The Normal mode is typically used to transfer data to or from a single device Network mode is typically used in Time Division Multiplexed TDM networks of codecs or D
257. e program will start execution of t ne loaded program from the specified starting address Ihe through the HI08 port 8 boot ROM program enables the following busses to download programs Dual strobes non multiplexed bus with negative strobe strobe non multiplexed bus with positive strobe strobe pulses strobe non multiplexed bus with negative strobe 1 ISA pulses dual positive request 2 11 Singl pulse single negative request 4 18051 Dual strobes multiplexed bus with negativ dual negative request 5 MC68302 Singl pulse single negative request owing conditions ive host acknowledge itive host request Negative chip select input strobes bus RD and WR strobes Non multiplexed bus address strobe polarity has no g in non multiplexed bus tive data strobes polarity ost request is active when enabled 0 This bit should be set to 0 for 0 When the HPCR register is modified t acknowledge is disabled nabled t requests ar 1 Host chip select input enabled 0 address 9 enable bit has no meaning in n multiplexed bus 0 address 8 enable bit has no meaning in n multiplexed bus t GPIO pins are disabled ISAHOSTLD movep 0101000000011000 _ Configure the foll HAP 0 Negat HRP 1 Pos HCSP 0 HD HS 1 Dual HMUX 0 HASP 0 meanin H
258. e set in the HSR The host can write to the HC and HV bits in the same write cycle 6 6 3 Interface Status Register ISR The Interface Status Register ISR is an 8 bit read only status register used by the host processor to interrogate the status and flags of the 108 The host processor can write to this address without affecting the internal state of the HI08 The ISR cannot be accessed by the DSP core The ISR bits are described in the following paragraphs 7 6 5 4 3 2 1 0 HREQ HF2 TRDY TXDE RXDF Reserved bit Read as 0 Should be written with 0 for future compatibility AA0670 Figure 6 14 Interface Control Register 6 6 3 1 ISR Receive Data Register Full RXDF Bit 0 The RXDF bit indicates that the Receive Byte Registers RXH RXM RXL contain data from the DSP56303 and may be read by the host processor RXDF is set when the is transferred to the Receive Byte Registers RXDF is cleared when the receive data RXL or RXH according to HLEND bit register is read by the host processor can be cleared by the host processor using the initialize function RXDF may be used to assert the external HREQ pin if the RREQ bit is set Regardless of whether the RXDF interrupt is enabled RXDF indicates whether the RX registers are full and data can be latched out so that polling techniques may be used by the host processor 6 6 3 2 ISR Transmit Data Register Empty TXDE Bit 1
259. ead as 0 and should be written as 0 6 5 6 9 HPCR Host Request Open Drain HROD Bit 8 The HROD bit controls the output drive of the host request pins In the Single Host Request mode HDRQ is cleared in ICR if HROD is cleared and host requests are enabled HREN is set and HEN is set in the Host Port Control Register HPCR the pin is always driven by the 108 If HROD is set and host requests are enabled the pin is an open drain output In the Double Host Request mode HDRQ is set in the ICR if HROD is cleared and host requests are enabled HREN is set and HEN is set in the the HTRO and HRRO pins are always driven If HROD is set and host requests are enabled the HTRO and HRRO pins are open drain outputs 6 5 6 10 HPCR Host Data Strobe Polarity HDSP Bit 9 If HDSP is cleared the data strobe pins are configured as active low inputs and data is transferred when the data strobe is low If HDSP is set the data strobe pins are configured as active high inputs and data is transferred when the data strobe is high The data strobe pins are either HDS by itself or both HRD and HWR together 6 5 6 11 HPCR Host Address Strobe Polarity HASP Bit 10 If HASP is cleared the Host Address Strobe HAS pin is an active low input and the address on the host address data bus is sampled when the HAS pin is low If HASP is set HAS is an active high address strobe input and the address on the host address or data bus is
260. eared the TIO pin generates the following signal 0101 The counter contents can be read at any time by reading the TCR The value of the TLR determines the output period TLR 1 The timer counter increments the initial TLR value and toggles the TIO pin when the counter value exceeds FFFFFF 9 24 DSP56303UM AD MOTOROLA Triple Timer Module Timer Modes of Operation The duty cycle of the TIO signal is determined by the value in the TCPR When the value in the TLR is incremented to a value equal to the value in the TCPR the TIO pin is toggled The duty cycle is equal to TCPR divided by SFFFFFF TLR 1 For a 50 duty cycle the value of TCPR is equal to TLR 1 2 Note The value in TCPR must be greater than the value in TLR 9 4 4 Watchdog Modes The following Watchdog Timer modes are provided Watchdog Pulse Watchdog Toggle 9 4 4 1 Watchdog Pulse Mode 9 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Kind TIO Clock 1 0 0 1 9 Pulse Watchdog Output Internal In this mode the timer generates an external signal at a preset rate The signal period is equal to the period of one timer clock Set the TE bit to clear the counter and enable the timer The value the timer is to count is loaded into the TCPR The counter is loaded with the TLR value on the first timer clock received from eith
261. ed RXDF interrupts are disabled If and RXDF are set the Host Request pin HREQ or HRRQ is asserted 6 6 1 2 ICR Transmit Request Enable TREQ Bit 1 TREQ is used to enable host requests via the Host Request HREQ or HTRQ pin when the Transmit Data Register Empty TXDE status bit in the ISR is set If TREQ is cleared TXDE interrupts are disabled If TREQ and TXDE are set the Host Request pin is asserted Table 6 8 and Table 6 9 summarize the effect of RREQ and TREQ on the HREQ and pins Table 6 8 TREQ and RREQ modes HDRQ 0 TREQ Pin 0 0 No Interrupts Polling 0 1 RXDF Request Interrupt 1 0 TXDE Request Interrupt 1 1 RXDF and TXDE Request Interrupts Table 6 9 TREQ and RREQ modes HDRQ 1 TREQ RREQ HTRQ Pin Pin 0 0 No Interrupts Polling No Interrupts Polling 0 1 No Interrupts Polling RXDF Request Interrupt 1 0 TXDE Request Interrupt No Interrupts Polling 1 1 TXDE Request Interrupt RXDF Request Interrupt 6 6 1 3 ICR Double Host Request HDRQ Bit 2 If cleared the HDRQ bit configures HREQ HTRO and as HREQ and HACK respectively If HDRQ is set HACK HRRO configured as and HRRQ respectively MOTOROLA DSP56303UM AD 6 23 Host Interface HI08 HI08 External Host Programmer s Model 6 6 1 4 ICR Host Flag 0 HFO Bit 3 Th
262. effective execution rate of one instruction per clock cycle The destination of every arithmetic operation can be used as a source operand for the immediate following operation without penalty 1 6 1 2 Multiplier Accumulator MAC The Multiplier Accumulator MAC unit comprises the main arithmetic processing unit of the DSP56300 core and performs all of the calculations on data operands In the case of arithmetic instructions the unit accepts as many as three input operands and outputs one 56 bit result of the following form Extension Most Significant Product Least Significant Product EXT MSP LSP The multiplier executes 24 bit x 24 bit parallel fractional multiplies between two s complement signed unsigned or mixed operands The 48 bit product is right justified and added to the 56 bit contents of either the A or B accumulator A 56 bit result can be stored as a 24 bit operand The LSP can either be truncated or rounded into the MSP Rounding is performed if specified 1 6 2 Address Generation Unit AGU The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers used to generate the addresses It implements four types of arithmetic linear modulo multiple wrap around modulo and reverse carry The AGU operates in parallel with other chip resources to minimize address generation overhead The AGU is divided into two halves each with its own A
263. egister HDDR Host GPIO Data Register HDR Both hardware and software reset disable the HI08 After reset the HI08 signal pins are configured to GPIO and disconnected from the DSP56303 core i e the pins are left floating 6 8 DSP56303UM AD MOTOROLA Host Interface HI08 HI08 DSP Side Programmer s Model 6 5 1 Host Receive Data Register HRX The HRX register is used for host to DSP data transfers The DSP56303 views it as a 24 bit read only register Its address is X FFFFC6 It is loaded with 24 bit data from the transmit data registers TXH TXM TXL on the host side when both the Transmit Data Register Empty TXDE ISR Bit 1 on the host side and Host Receive Data Full HRDF HSR Bit 0 on the DSP side bits are cleared The transfer operation sets both the TXDE and HRDF bits When the HRDF bit is set the HRX register contains valid data The DSP56303 may set the HRIE bit HCR Bit 0 to cause a host receive data interrupt when HRDF is set When the DSP56303 reads the HRX register the HRDF bit is cleared 6 5 2 Host Transmit Data Register HTX The HTX register is used for DSP to host data transfers The DSP56303 views it as a 24 bit write only register Its address is X SFFFFC7 Writing to the HTX register clears the Host Transfer Data Empty bit HTDE HSR Bit 1 on the DSP side The contents of the HTX register are transferred as 24 bit data to the Receive Byte Registers RXH RXM RXL when both the HTDE and Receive
264. egister Register Name Data HW SW IR ST Reset Reset Reset Reset ICR All Bits 0 0 0 0 0 0 HV 0 6 2A 2A ISR HREQ 0 0 1 if TREQ is set 1 if TREQ is set 0 otherwise 0 otherwise HF3 HF2 0 0 TRDY 1 1 1 1 TXDE 1 1 1 1 RXDF 0 0 0 0 IVR IV 0 7 0F 0F RX RXH RXM RXL empty empty empty empty TX TXH TXM TXL empty empty empty empty 6 6 8 General Purpose I O When configured as General Purpose I O GPIO the 08 is viewed by the DSP56303 as memory mapped registers see Section 6 5 that control up to sixteen I O pins Software and hardware resets clear all DSP side control registers and configure HI08 as GPIO with all sixteen pins disconnected External circuitry connected to HI08 may need external pull up pull down resistors until the pins 6 30 DSP56303UM AD MOTOROLA Host Interface HI08 Servicing the Host Interface are configured for operation The registers cleared are the HPCR HDDR and HDR Selection between GPIO and HI08 is made by clearing HPCR bits 6 through 1 for GPIO or setting these bits for HI08 functionality If the 108 is in GPIO mode the HDDR configures each corresponding pin in the HDR as an input pin if the HDDR bit is cleared or as an output pin if the HDDR bit is set see 6 5 7 Host Data Direction Register HDDR on page 6 17 and 6 5 8 Host Data Register HDR on page 6 17 6 7 SERVICING THE HOST INTERFACE The HI08 can be serviced by using one
265. eivers to MOTOROLA DSP56303UM AD 7 35 Enhanced Synchronous Serial Interface ESSI Operating Modes be tri stated during the next slot Setting the bits in the RSM affects the next frame transmission The frame currently being transmitted is not affected by the new RSM setting If the RSM is read it shows the current setting When the RSMA or RSMB register are read by the internal data bus the register contents occupy the two low order bytes of the data bus and the high order byte is zero filled After a hardware reset or a software reset instruction the RSM register is reset to FFFFFFFF This enables all thirty two time slots for data transmission 7 5 OPERATING MODES The ESSI operating modes are selected by the ESSI Control Registers CRA and CRB The operating modes are described in the following paragraphs 7 5 1 ESSI After Reset A hardware reset signal or software reset instruction clears the Port Control Register and the Port Direction Control Register This configures all the ESSI signal pins as GPIO The ESSI is in the reset state while all ESSI pins are programmed as GPIO and is active only if at least one of the ESSI I O pins is programmed as an ESSI pin 7 5 2 ESSI Initialization To initialize the ESSI do the following Send a reset hardware software ESSI individual or STOP instruction reset Program the ESSI control and time slot registers Write data to all the enabled transmitters Configure at least
266. er OCR The OnCE Command Register OCR is an 8 bit shift register that receives its serial data from the TDI pin It holds the 8 bit commands to be used as input for the OnCE Decoder The OCR is shown in Figure 10 4 OCR 7 6 5 ae OnCE Command Reset 00 Write Only AA0106 Figure 10 4 OnCE Command Register 10 4 1 1 Register Select RS4 RSO Bits 0 4 The Register Select bits define which register is source destination for the read write operation See Table 10 4 for the OnCE register select encoding 10 4 1 2 Exit Command EX Bit 5 If the EX bit is set leave Debug mode and resume normal operation The EXIT command is executed only if the GO command is issued and the operation is write MOTOROLA DSP56303UM AD 10 5 On Chip Emulation Module OnCE Controller to OPDBR or read write to No Register Selected Otherwise the EX bit is ignored Table 10 1 shows the definition of the EX bit Table 10 1 EX Bit Definition EX Action 0 Remain in Debug mode 1 Leave Debug mode 10 4 1 3 GO Command GO Bit 6 If the GO bit is set execute the instruction that resides in the PIL register To execute the instruction the core leaves the Debug mode The core returns to the Debug mode immediately after executing the instruction if the EX bit is cleared The core goes on to normal operation if the EX bit is set The GO command is executed only if the operation is write to OPDBR or read write to No Regi
267. er PDRC 7 45 Port C Direction Register PRRC 7 45 Port D 2 3 2 29 5 4 port D 0 signal PDO 2 29 port D 1 signal PD1 2 29 port D 2 signal PD2 2 30 port D 3 signal PD3 2 31 port D 4 signal 2 31 port D 5 signal PD5 2 32 Port D Control Register PCRD 7 44 Port D Data Register PDRD 7 45 Port D Direction Register PRRD 7 45 Port E 2 3 2 33 5 4 port E 0 signal PEO 2 33 port E 1 signal PE1 2 33 port E 2 signal PE2 2 33 Port E Control Register PCRE 8 27 Port E Data Register PDRE 8 28 Port E Direction Register PRRE 8 28 power 2 3 2 5 ground 2 6 low 1 7 management 1 7 standby modes 1 7 power input address bus 2 5 bus control 2 5 data bus 2 5 ESSI 2 5 host interface 2 5 PLL 2 5 quiet 2 5 SCI 2 5 timer 2 5 PreDivider Factor bits PD 4 18 Prescale Modulus Select bits PM0 PM7 7 10 Prescaler Clock Enable bit PCE 9 14 Prescaler Counter 9 7 Prescaler Counter Value bits 20 9 9 Prescaler Load Value bits PLO PL20 9 7 Prescaler Range bit PSR 7 11 DSP56303UM AD 9 Prescaler Source bits PL21 PL22 9 7 Program Address Bus PAB 1 13 Program Address Generator PAG 1 10 Program Control Unit PCU 1 10 Program Counter register PC 1 10 Program Data Bus PDB 1 13 Program Decode Controller PDC 1 10 Program Interrupt Controller PIC 1 10 Program Memory Expansion Bus 1 13 program RAM 3 6 Programming Sheets See Appendix B PRRC register 7 45 PRRD register 7 45
268. er through their common Trace buffer address Figure 10 10 on page 10 22 shows the block diagram of the Trace buffer The Trace buffer is not affected by the operations performed during the Debug mode except for the Trace buffer pointer increment when reading the Trace buffer When entering the Debug mode the Trace buffer counter is pointing to the Trace buffer register containing the address of the last executed instructions The first Trace buffer read obtains the oldest address and the following Trace buffer reads get the other addresses from the oldest to the newest in order of execution Notes 1 To ensure Trace buffer coherence a complete set of twelve reads of the Trace buffer must be performed This is necessary due to the fact that each read increments the Trace buffer pointer thus pointing to the next location After twelve reads the pointer indicates the same location as before starting the read procedure 2 Onany change of flow instruction the Trace buffer stores both the address of the change of flow instruction as well as the address of the target of the change of flow instruction In the case of conditional change of flows the address of the change of flow instruction is always stored regardless of the fact that the change of flow is true or false but if the conditional change of flow is false 1 not taken the address of the target is not stored In order to facilitate the program trace reconstruction every Trace buf
269. er the DSP56303 internal clock divided by two CLK 2 or the prescaler clock output Each subsequent timer clock increments the counter When the counter matches the value of the TCPR the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is also set If the TRM bit is set the counter is loaded with the TLR value on the next timer clock and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each subsequent timer clock This process is repeated until the timer is disabled i e TE is cleared MOTOROLA DSP56303UM AD 9 25 Triple Timer Module Timer Modes of Operation If the counter overflows the TOF bit is set and if TOIE is set an overflow interrupt is generated At the same time a pulse is output on the TIO pin with a pulse width equal to the timer clock period The pulse polarity is determined by the value of the INV bit If the INV bit is set the pulse polarity is high logical 1 If the INV bit is cleared the pulse polarity is low logical 0 The counter contents can be read at any time by reading the TCR The counter is reloaded whenever the TLR is written with a new value while the TE bit is set Note In this mode internal logic preserves the TIO value and direction for an additional 2 5 internal clock cycles after the DSP56303 hardware reset signal is asserted This ensures that a valid RESET signal is generated when the TIO pin is used to reset
270. erational mode signal lines the mode bits in the OMR and the reset vector address to which the DSP56303 jumps once it leaves the Reset state MOTOROLA DSP56303UM AD 4 3 Core Configuration Bootstrap Program Table 4 1 DSP56303 Operating Modes Mode MODD Beset Description Vector 0 0 0 0 0 C00000 Expanded mode 1 1 0 0 1 5 000 Bootstrap from byte wide memory at D00000 2 1 0 1 0 5 000 Bootstrap through SCI 3 1 0 1 1 4 1 1 0 0 5 000 108 Bootstrap in ISA DSP5630X 5 1 1 0 1 0000 108 Bootstrap in non multiplexed 6 1 1 1 0 0000 108 Bootstrap in 8051 multiplexed bus 7 1 1 1 1 0000 108 Bootstrap in 68302 bus 8 1 0 0 0 008000 Expanded mode Note 1 Address C00000 is reflected as address 00000 on Port A pins 0 17 4 3 BOOTSTRAP PROGRAM The bootstrap program is factory programmed in an internal 192 word by 24 bit bootstrap ROM located in Program memory space at locations FF0000 FFOOBF The bootstrap program can load any Program RAM segment from an external byte wide EPROM the SCI or the host port The bootstrap program code is listed in Appendix A On exiting the Reset state the DSP56303 1 Samples the MODA MODB MODC and MODD signal lines 2 Loads their values into bits MA MB MC an
271. es the chip to execute a vectored interrupt to the address VBA 06 instead of entering the Debug mode 10 4 3 3 Software Debug Occurrence SWO Bit 2 The Software Debug Occurrence SWO bit is a read only status bit that is set when the Debug mode of operation is entered because of the execution of the DEBUG or DEBUGcc instruction with condition true This bit is cleared when leaving the Debug mode 10 8 DSP56303UM AD MOTOROLA On Chip Emulation Module OnCE Controller 10 4 3 4 Memory Breakpoint Occurrence MBO Bit 3 The Memory Breakpoint Occurrence MBO bit is a read only status bit that is set when the Debug mode of operation is entered because a memory breakpoint has been encountered This bit is cleared when leaving the Debug mode 10 4 3 5 Trace Occurrence TO Bit 4 The Trace Occurrence TO bit is a read only status bit that is set when the Debug mode of operation is entered when the Trace Counter is zero while Trace mode is enabled This bit is cleared when leaving the Debug mode 10 4 3 6 Reserved OCSR Bit 5 Bit 5 is reserved for future use It is read as 0 and should be written with 0 for future compatibility 10 4 3 7 Core Status 050 OS1 Bits 6 7 The Core Status 050 OS1 bits are read only status bits that provide core status information By examining the status bits the user can determine whether the chip has entered the Debug mode Examining SWO MBO and TO identifies the cause of entering the Debug mode The user
272. eset Reset Stop Signal Description TIOO 1 Input or Output Input or Output Input Input Discon nected Internally Discon nected Internally Timer 0 Schmitt Trigger Input Output When Timer 0 functions as an external event counter or in Measurement mode TIOO is used as input When Timer 0 functions in Watchdog Timer or Pulse Modulation mode TIOO is used as output The default mode after reset is GPIO input This can be changed to output or configured as a Timer Input Output through the Timer 0 Control Status Register TCSRO This input is 5 V tolerant Timer 1 Schmitt Trigger Input Output When Timer 1 functions as an external event counter or in Measurement mode is used as input When Timer 1 functions in Watchdog Timer or Pulse Modulation mode TIO1 is used as output The default mode after reset is GPIO input This can be changed to output or configured as a Timer Input Output through the Timer 1 Control Status Register TCSR1 This input is 5 V tolerant 2 34 DSP56303UM AD MOTOROLA Signal Connection Descriptions OnCE JTAG Interface Table 2 15 Triple Timer Signals Continued State During Reset Signal Description Reset Stop TIO2 Input Input Discon Timer 2 Schmitt Trigger Input Output or nected When Timer 2 functions as an external event Output Internally counter or in Measurement mode TIO2 is
273. f a signal 9 2 TRIPLE TIMER MODULE ARCHITECTURE The timer module is composed of a common 21 bit prescaler and three independent and identical general purpose 24 bit timer event counters each having its own register set Each timer can use internal or external clocking and can interrupt the DSP56308 after a specified number of events clocks or can signal an external device after counting internal events Each timer can also be used to trigger DMA transfers after a specified number of events clocks has occurred Each timer connects to the external world through one bidirectional signal pin designated TIOO TIO2 for Timers 0 2 respectively When the TIO pin is configured as input the timer functions as an external event counter or measures external pulse width signal period When the TIO pin is used as output the timer functions as a timer a watchdog timer or a pulse width modulator When the TIO pin is not used by the timer it can be used as a GPIO pin also called TIOO TIO2 9 2 1 Triple Timer Module Block Diagram Figure 9 1 shows a block diagram of the triple timer module This module includes a 24 bit Timer Prescaler Load Register TPLR 24 bit Timer Prescaler Count Register TPCR a 21 bit prescaler clock counter and three timers Each of the three timers may use the prescaler clock as its clock source MOTOROLA DSP56303UM AD 9 3 Triple Timer Module Triple Timer Module Architecture GDB 24 24 TPCR 24 T
274. f logical values on the TMS signal It is a synchronous state machine that controls the operation of the JTAG logic The state machine is shown in Figure 11 2 The TAP controller responds to changes at the TMS and TCK signals Transitions from one state to another occur on the rising edge of TCK The value shown adjacent to each state transition represents the value of the TMS signal sampled on the rising edge of TCK signal For a description of the TAP controller states please refer to the IEEE 1149 1 document A Test Logic Reset C Run Test idle Select IR Scan N Select DR Scan 0 Capture IR gt 0 0 Exit1 IR 0 1 0 Exit2 DR Exit2 IR 1 1 Update DR Update IR o 1 0 0114 Figure 11 2 Controller State Machine 11 6 DSP56303UM AD MOTOROLA JTAG Port TAP Controller 11 31 Boundary Scan Register The Boundary Scan Register BSR in the DSP56303 JTAG implementation contains bits for all device signal and clock pins and associated control signals All DSP56303 bidirectional pins have a single register bit in the BSR for pin data and are controlled by an associated control bit in the BSR The DSP56303 BSR bit definitions are described in Table 11 2 on page 11 13 11 3 2 Instruction Register The DSP56303 JTAG implementation includes the three mandatory public instructions EXTEST SAMPLE PRELOAD and BYPASS and also supports the optional CLAMP instruction defined by IEEE 1
275. f the receive bit clock If CKP is set the data and the frame sync are clocked out on the falling edge of the transmit bit clock and latched in on the rising edge of the receive bit clock Either a hardware reset signal or a software reset instruction will clear CKP 7 4 2 11 CRB Synchronous Asynchronous SYN Bit 12 SYN controls whether the receive and transmit functions of the ESSI occur synchronously or asynchronously with respect to each other see Figure 7 12 on page 7 20 When SYN is cleared the ESSI is in Asynchronous mode and separate clock and frame sync signals are used for the transmit and receive sections When SYN is set the ESSI is in Synchronous mode and the transmit and receive sections use common clock and frame sync signals Only in the Synchronous mode can more than one transmitter can be enabled Either a hardware reset signal or a software reset instruction clears SYN 7 18 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI ESSI Programming Model Word Length FSL1 0 FSLO 0 Serial Clock RX TX Frame SYNC RX TX Serial Data NOTE Frame sync occurs while data is valid One Bit Length FSL1 1 FSLO 0 Serial Clock RX TX Frame SYNC NOTE Frame sync occurs for one bit time preceding the data Mixed Frame Length FSL1 0 FSLO 1 Serial Clock RX Frame Sync TX Frame SYNC TX Serial Data Mixed Frame Length FSL1
276. f the twenty four bits are currently defined Each bit is described in the following paragraphs 8 3 1 1 SCR Word Select WDS 0 2 Bits 0 2 The word select WDS 0 2 bits select the format of transmitted and received data Format modes are listed in Table 8 1 and described in Figure 8 4 Table 8 1 Word Formats WDS2 WDS1 WDSO Mode Word Formats 0 0 0 0 8 Bit Synchronous Data shift register mode 0 0 1 1 0 1 0 2 10 Asynchronous 1 start 8 data 1 stop 0 1 1 3 Reserved 1 0 0 4 11 Bit Asynchronous 1 start 8 data 1 even parity 1 stop 1 0 1 5 11 Bit Asynchronous 1 start 8 data 1 odd parity 1 stop 1 1 0 6 11 Bit Multidrop Asynchronous 1 start 8 data 1 data type 1 stop 1 1 1 7 Reserved The Asynchronous modes are compatible with most UART type serial devices and support standard RS232C communication links The Multidrop Asynchronous mode is compatible with the MC68681 DUART the M68HC11 SCI interface and the Intel 8051 serial interface The Synchronous data mode is essentially a high speed shift register used for I O expansion and stream mode channel interfaces Data synchronization is accomplished by the use of a gated transmit and receive clock that is compatible with the Intel 8051 serial interface mode 0 When odd parity is selected the transmitter counts the number of 1s in the data word If the total is not an odd number the parity bit is set thus
277. face 1 ESSI1 Table 2 13 Enhanced Synchronous Serial Interface 1 ESSI1 Continued State During Type Signal Description Reset Stop Signal Name 5612 Input Input Discon Serial Control Signal 2 SC12 is used for Output nected frame sync I O SC12 is the frame sync for Internally both the transmitter and receiver in Synchronous mode and for the transmitter only in Asynchronous mode When configured as an output this signal is the internally generated frame sync signal When configured as an input this signal receives an external frame sync signal for the transmitter and the receiver in Synchronous operation PD2 Input Port D 2 The default configuration Or following reset is GPIO input PD2 When Output configured as PD2 signal direction is controlled through PRRD The signal can be configured as an ESSI signal SC12 through PCRD This input is 5 V tolerant 2 30 DSP56303UM AD MOTOROLA Signal Connection Descriptions Enhanced Synchronous Serial Interface 1 ESSI1 Table 2 13 Enhanced Synchronous Serial Interface 1 ESSI1 Continued Signal Name Type State During Reset Stop Signal Description PD3 Input Output Input or Output Input Discon nected Internally Serial Clock SCK1 is a bidirectional Schmitt trigger input signal providing the serial bit rate clock for the ESSI interface The SCKI is a clock input or out
278. fer location has an additional invalid bit the 25th bit If a conditional change of flow instruction has a condition false the invalid bit is set thus marking this instruction as MOTOROLA DSP56303UM AD 10 21 On Chip Emulation Module Trace Buffer not taken Therefore it is imperative to read seventeen bits of data when reading the twelve Trace buffer registers Since data is read LSB first the invalid bit is the first bit to be read PAB Fetch Address OPABFR Decode Address OPABDR Execute Address OPABEX Trace Buffer Register 0 Circular Trace Buffer Register 1 Buffer mai e Pointer Trace Buffer Register 2 Trace Buffer Register 11 ce P TCK TDO 0710 TDI gt Trace Buffer Shift Register Figure 10 10 OnCE Trace Buffer 10 22 DSP56303UM AD MOTOROLA On Chip Emulation Module Serial Protocol Description 10 10 SERIAL PROTOCOL DESCRIPTION To permit an efficient means of communication between the external command controller and the DSP56300 core chip the following protocol is adopted Before starting any debugging activity the external command controller has to wait for an acknowledge on the DE line indicating that the chip has entered the Debug mode optionally the external command controller can poll the OS1 and 50 bits in the JT AG instruction shift register The external command controller communicates with the chip by sending 8 bit co
279. fied Register 10 26 Displaying X Memory Area Starting at Address xxxx 10 26 Returning from Debug Mode to Normal Mode to Current Program 10 28 MOTOROLA DSP56303UM AD xiii 10 128 Returning Debug Mode to Normal Mode toa New 10 28 10 13 EXAMPLES OF JTAG AND ONCE INTERACTION 10 29 SECTION 11 JTAG PORT 11 1 11 1 INTRODUCTION 11 3 11 2 JTAGPINS CE Lcd o x win or det u a dat bri et as 11 5 11 2 1 Test Clock TOK ue creek eee edhe 11 5 11 2 2 Test Mode Select 5 11 5 11 2 3 Test Data Input 11 5 11 2 4 Test Data Output TDO 11 5 11 2 5 test Reset TRST inns dato ie u pa w do e oues 11 5 11 3 TAP CONTROLLER em m ERES 11 6 11 3 1 Boundary Scan 11 7 11 3 2 Instruction 11 7 11 3 2 1 3 0 0000 11 8 11 3 2 2 SAMPLE PRELOAD B 3 0 0001 11 9 11 3 2 3 IDCODE B 3 0 0010 11 9 11 3 2 4 CLAMP B 3 0 0011 11 10 11 3 2 5 HI Z B 3 0 0100 11 10 11 3 2 6 ENABLE ONCE B 3 0 0110 11 11 11 3 2 7 DEBUG REQUEST B 3 0 0111 11 11 1
280. figured as GPIO Output through the HPCR this signal is individually programmed as an input or output through the HDDR This input is 5 V tolerant This pin is electrically disconnected internally during Stop mode 2 22 DSP56303UM AD MOTOROLA Signal Connection Descriptions Host Interface HI08 Table 2 11 Host Interface Continued Signal Name State Durin Type Reset T e Signal Description Stop HREQ HREQ HTRO HTRO PB14 Output Discon Host Request When 108 is programmed to nected interface a single host request host bus and the HI Internally function is selected this signal is the Host Request HREQ output The polarity of the host request is programmable but is configured as active low HREQ following reset The host request may be programmed as a driven or open drain output Output Transmit Host Request When 08 is programmed to interface a double host request host bus and the HI function is selected this signal is the Transmit Host Request HTRQ output The polarity of the host request is programmable but is configured as active low HTRQ following reset The host request may be programmed as a driven or open drain output Input or Output Port B 14 When HI08 is programmed to interface a multiplexed host bus and the signal is configured as GPIO through the HPCR this signal is individually programmed as an input or output through the HDDR
281. fter reset 6 29 Host Status Register HSR 6 11 host to DSP MOTOROLA data word 6 3 handshaking protocols 6 4 instructions 6 4 mapping 6 3 transfer modes 6 3 Host Transmit Data Register HTX 6 9 polling 6 31 registers 6 7 servicing interrupts 6 33 HI Z instruction 11 10 HLEND bit 6 24 HMUX bit 6 15 Host Acknowledge Enable bit HAEN 6 14 Host Acknowledge Polarity bit 6 16 host acknowledge signal HACK HACK 2 24 host address 10 signal HA10 2 22 host address 8 signal 8 2 19 host address 9 signal 9 2 19 host address input 0 signal 2 18 host address input 1 signal HA1 2 19 host address input 2 signal HA2 2 19 Host Address Line 8 Enable bit HA8EN 6 13 Host Address Line 9 Enable bit 6 13 host address signal HADO HAD 7 2 18 Host Address Strobe Polarity bit HASP 6 15 host address strobe signal HAS HAS signal 2 18 Host Base Address Register HBAR 6 12 Host Chip Select Enable bit HCSEN 6 14 Host Chip Select Polarity bit HCSP 6 16 host chip select signal HCS 2 22 Host Command bit HC 6 25 Host Command Interrupt Enable bit HCIE 6 10 Host Command Pending bit HCP 6 11 Host Control Register HCR 6 9 6 10 Host Data Direction Register HDDR 6 17 Host Data Register HDR 6 17 host data signal 7 2 18 Host Data Strobe Polarity bit HDSP 6 15 host data strobe signal HDS HDS 2 21 Host Dual Data Strobe bit HDDS 6 15 Host Enable bit HEN 6 14 Host Flag 0 and 1 bits
282. g Trace Mode When the Trace mode mechanism is enabled and the Trace Counter is greater than zero the Trace Counter is decremented after each instruction execution Execution of an instruction when the value in the Trace Counter is 0 causes the chip to enter the Debug mode after completing the execution of the instruction Only instructions actually executed cause the Trace Counter to decrement An aborted instruction does not decrement the Trace Counter and does not cause the chip to enter the Debug mode 10 7 8 Enabling Memory Breakpoints When the memory breakpoint mechanism is enabled with a Breakpoint Counter value of 0 the chip enters the Debug mode after completing the execution of the instruction that caused the memory breakpoint to occur In case of breakpoints on executed Program memory fetches the breakpoint is acknowledged immediately after the execution of the fetched instruction In case of breakpoints on accesses to X Y or Program memory spaces by MOVE instructions the breakpoint is acknowledged after the completion of the instruction following the instruction that accessed the specified address 10 8 PIPELINE INFORMATION AND OGDB REGISTER To restore the pipeline and to resume normal chip activity upon returning from the Debug mode a number of on chip registers store the chip pipeline status Figure 10 9 shows the block diagram of the Pipeline Information Registers with the exception of the PAB registers which are shown in F
283. g edge directly on TIO pin the signal from of the signal from the TIO pin the TIO pin 3 Counter is Counter is incremented on incremented on the rising edge of the falling edge the signal from of the signal from the TIO pin the TIO pin 4 Width of the high Width of the low input pulse is input pulse is measured measured 5 Period is Period is measured between the between the rising edges of falling edges of the input signal the input signal 6 Event is captured Event is captured on the rising edge on the falling of the signal from edge of the signal the TIO pin from the TIO pin 7 Pulse generated Pulse generated by by the timer has the timer has positive polarity negative polarity 9 Pulse generated Pulse generated by by the timer has the timer has positive polarity negative polarity 10 xz Pulse generated Pulse generated by by the timer has positive polarity the timer has negative polarity The INV bit is cleared by a hardware RESET signal or a software RESET instruction 9 12 DSP56303UM AD MOTOROLA Triple Timer Module Triple Timer Module Programming Model Note The INV bit affects both the timer and GPIO modes of operation To ensure correct operation this bit should be changed only when one or both of the following conditions is true The timer has been disabled by clearing the TE bit in the TCSR The timer is in GPIO mode
284. gnificant byte first ress and the followed by the mid and then by the most significant byte After receiving the program words program executio l 55 wher n starts in the same addr oading started The SCI is programmed to work in asynchronous mode with 8 data bits 1 stop bit and no parity The clock source is external and the clock frequency must be 16x the baud rate After each byte is received it is echoed back through the SCI transmitter DSP56303UM AD Bootstrap Programs If MC MB MA 100 then it loads the program RAM from the Host Interface programmed to operate in the ISA mode The HOST ISA bootstrap code expects to read a 24 bit word specifying the numbe to start loading the program words and then a 24 bit word for each program word to be loaded The program words will be stored in contiguous PRAM memo r of program words a 24 bit word specifying the address ry locations starting at the specified starting address After reading the program words program execution starts from the same address where loading started Ihe Host Interface bootstrap load program may be stopped by setting the Host Flag 0 This will start execution of the loaded program from the s
285. h frame sync is generated or expected with the last bit of the previous word FSR is ignored when a bit length frame sync is selected 7 5 4 3 4 Controlling the Frame Sync Polarity The FSP bit controls the polarity of the frame sync When the FSP bit is cleared the polarity of the frame sync is positive i e the frame sync signal is asserted high The ESSI synchronizes on the leading edge of the frame sync signal When the FSP bit is set the polarity of the frame sync is negative i e the frame sync is asserted low The ESSI synchronizes on the trailing edge of the frame sync signal The ESSI receiver looks for a receive frame sync edge leading edge if FSP is cleared trailing edge if FSP is set only when the previous frame is completed If the frame sync is asserted before the frame is completed or before the last bit of the frame is received in the case of a bit frame sync or a word length frame sync with FSR set the current frame sync is not recognized and the receiver is internally disabled until the next frame sync 7 42 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI Operating Modes Frames do not have to be adjacent that is a new frame sync does not have to follow immediately the previous frame Gaps of arbitrary periods can occur between frames All the enabled transmitters will be tri stated during these gaps 7 5 4 4 Selecting the Byte Format LSB MSB for the Transmitter Some dev
286. has been transferred from the STX to the Transmit Shift Register There is a 2 to 4 serial clock cycle delay between writing STX and loading the Transmit Shift Register in addition TDRE is set in the middle of transmitting the MOTOROLA DSP56303UM AD 8 13 Serial Communication Interface SCI SCI Programming Model second bit When using an external serial transmit clock if the clock stops the SCI transmitter stops TDRE is not set until the middle of the second bit transmitted after the external clock starts Gating the external clock off after the first bit has been transmitted delays TDRE indefinitely In the Asynchronous mode the TDRE flag is not set immediately after a word is transferred from the STX or STXA to the Transmit Shift Register nor when the word first begins to be shifted out is set 2 cycles of the 16 X clock after the start bit that 15 2 16 X clock cycles into the transmission time of the first data bit 8 3 2 3 SSR Receive Data Register Full RDRF Bit 2 The bit is set when a valid character is transferred to the SCI Receive Data Register from the SCI Receive Shift Register regardless of the error bits condition is cleared when the SCI Receive Data Register is read or by the hardware software SCI individual and stop resets 8 3 2 4 SSR Idle Line Flag IDLE Bit 3 IDLE is set when ten or eleven consecutive 1s are received IDLE is cleared by a start bit detection The IDLE status
287. he corresponding pin is configured as an input HDDR HDR Dxx DRxx GPIO non GPIO pin 0 Read only bit The value read is the Read only bit Does not contain significant data Read write bit The value written is the value read The corresponding pin is configured as an output and is driven with the data written to Dxx Read write bit The value written is the value read a defined by the selected configuration 6 5 9 DSP Side Registers After Reset Table 6 6 shows the results of the four reset types on the bits in each of the 108 registers accessible by the DSP56303 The Hardware reset HW is caused by the RESET signal The Software reset SW is caused by executing the RESET instruction The Individual Reset IR is caused by clearing the HEN bit HPCR Bit 6 The Stop reset ST is caused by executing the STOP instruction DSP56303UM AD MOTOROLA Host Interface HI08 HI08 DSP Side Programmer s Model Table 6 6 DSP Side Registers after Reset Reset Type Register Register Name Data HW SW IR ST Reset Reset Reset Reset HCR All bits 0 0 HPCR Allbits 0 0 HSR HF 1 0 0 0 HCP 0 0 0 0 HTDE 1 1 1 1 HRDF 0 0 0 0 HBAR BA 10 3 80 80 HDDR DR 15 0 0 0 HDR D 15 0 HRX HRX 23 0 empty empty empty empty HTX HTX 23 0 empty empty empty empty Note The bit value is
288. he ENABLE ONCE instruction is decoded the TDI and TDO pins are connected directly to the OnCE registers The particular OnCE register connected between TDI and TDO at a given time is selected by the OnCE controller depending on the OnCE instruction being currently executed All communication with the OnCE controller is done through the Select DR Scan path of the JTAG TAP Controller See Section 10 On Chip Emulation OnCE for more information 11 3 2 7 DEBUG REQUEST B 3 0 0111 The REQUEST instruction is not included in the IEEE 1149 1 standard It is provided as a public instruction to allow the user to generate a debug request signal to the DSP56300 core When the DEBUG REQUEST instruction is decoded the TDI and TDO pins are connected to the Instruction Registers Due to the fact that in the Capture IR state of the TAP the OnCE status bits are captured in the Instruction shift register the external JTAG controller must continue to shift in the DEBUG REQUEST instruction while polling the status bits that are shifted out until the Debug mode of operation is entered acknowledged by the combination 11 on 051 050 After the acknowledgment of the Debug mode is received the external JT AG controller must issue the ENABLE ONCE instruction to allow the user to perform system debug functions 11 3 2 8 BYPASS B 3 0 1111 The BYPASS instruction selects the single bit Bypass register as shown in Figure 11 5 This creates a shift regi
289. he JT AG port Before enabling breakpoints OMLRO must be loaded by the external command controller 10 5 3 OnCE Memory Address Comparator 0 OMACO The OnCE Memory Address Comparator 0 OMACO compares the current memory address stored in OMALO with the OMLRO contents 10 5 4 OnCE Memory Limit Register 1 OMLR1 The OnCE Memory Limit Register 1 OMLR1 is a 16 bit register that stores the memory breakpoint limit OMLR1 can be read or written through JTAG port Before enabling breakpoints OMLR1 must be loaded by the external command controller 10 5 5 OnCE Memory Address Comparator 1 OMAC1 The OnCE Memory Address Comparator 1 compares the current memory address stored in OMALO with the OMLRI contents MOTOROLA DSP56303UM AD 10 11 On Chip Emulation Module OnCE Memory Breakpoint Logic 10 5 6 OnCE Breakpoint Control Register The OnCE Breakpoint Control Register OBCR is a 16 bit register used to define the memory breakpoint events OBCR can be read or written through the JTAG port All the bits of the OBCR are cleared on hardware reset The OBCR is described in Figure 10 7 OnCE Breakpoint 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Control Register cc Rw Reset 0010 11 11 10 01 s1 SO Read Write Indicates reserved bits written as 0 for future compatibility 0707 Figu
290. he control bits are described in the following paragraphs The SCCR is cleared by hardware reset The basic features of the clock generator see Figure 8 5 and Figure 8 6 are 1 The SCI logic always uses a 16 X internal clock in the Asynchronous modes and always uses a 2 X internal clock in the Synchronous mode The maximum internal clock available to the SCI peripheral block is the oscillator frequency divided by 4 With a 66 MHz DSP56303 processor this gives a maximum data rate of 1031 25 Kbps for asynchronous data and 8 25 Mbps for synchronous data These maximum rates are the same for internally or externally supplied clocks 2 The 16 X clock is necessary for the Asynchronous modes to synchronize the SCI to the incoming data see Figure 8 5 3 For the Asynchronous modes the user must provide a 16 X clock if the user wishes to use an external baud rate generator i e SCLK input 4 For the Asynchronous modes the user can select either 1 X 16 X for the output clock when using internal TX and RX clocks TCM 0 RCM 0 5 When 5 is cleared the transmitted data on the TXD pin changes on the negative edge of the 1 X serial clock and is stable on the positive edge When SCKP is set the data changes on the positive edge and is stable on the negative edge MOTOROLA DSP56303UM AD 8 15 Serial Communication Interface SCI SCI Programming Model 6 The received data on the RXD pin is sampled on the positive edg
291. hey can be switched to 3 K each Optionally Off chip memory expansion up to 16 M in the 24 bit Address mode and 64 K in the 16 bit Address mode 3 1 2 1 X Data Memory Space The on chip peripheral registers and some of the DSP56303 core registers occupy the top 128 locations of X data memory FFFF80 FFFFFF in the 24 bit Address mode FF80 FFFF in the 16 bit Address mode This area is called X I O space and it can be accessed by MOVE and MOVEP instructions and by bit oriented instructions BCHG BCLR BSET BTST BRCLR BRSET BSCLR BSSET JCLR JSET JSCLR and JSSET For a listing of the contents of this area see the Programming Sheets in Appendix D The X memory space at locations FF0000 to FFEFFF is reserved and should not be accessed 3 1 2 2 Y Data Memory Space The off chip peripheral registers should be mapped into the top 128 locations of Y data memory FFFF80 FFFFFF in 24 bit Address mode or FF80 FFFF in the 16 bit Address mode to take advantage of the Move Peripheral Data MOVEP instruction and the bit oriented instructions BCHG BCLR BSET BTST BRCLR BRSET BSCLR BSSET JCLR JSET JSCLR and JSSET The Y memory space at locations FF0000 to FFEFFF is reserved and should not be accessed 3 4 DSP56303UM AD MOTOROLA Memory Configuration RAM Configuration 3 1 3 Memory Space Configuration Memory space addressing is 24 bit by default The DSP56303 switches to Sixteen bit Address Compati
292. ices such as codecs require MSB first data format Other devices such as those that use the AES EBU digital audio format require the LSB first To be compatible with all formats the shift registers in the ESSI are bidirectional The MSB LSB selection is made by programming the SHFD bit in the CRB If the SHFD bit is cleared data is shifted into the Receive Shift Register MSB first and shifted out of the Transmit Shift Register MSB first If the SHFD bit is set data is shifted into the Receive Shift Register LSB first and shifted out of the Transmit Shift Register LSB first 7 5 5 Flags Two ESSI pins SC 1 0 are available for use as serial I O flags Their operation is controlled by the SYN SCD 1 0 SSC1 and TE 2 1 bits in the CRB CRA The control bits OF 1 0 and status bits IF 1 0 are double buffered to from SC 1 0 Double buffering the flags keeps the flags in sync with TX and RX The SC 1 0 flags are available in the Synchronous mode only Each flag can be separately programmed Flag SCO is enabled when transmitter 1 is disabled TE1 0 The flag s direction is selected by the 5 0 bit When SCDO is set SCO is configured as output When SCDO is cleared SCO is configured as input Similarly the SC1 flag is enabled when transmitter 2 is disabled TE2 0 and the SC1 pin is not configured as transmitter drive enable Bit SSC1 0 SC1 s direction is selected by the SCD1 bit When SCD1 is set SC1 is an out
293. ide Programmer s Model 6 5 HI08 DSP SIDE PROGRAMMER S MODEL The DSP56303 core treats the 108 as a memory mapped peripheral occupying eight 24 bit words in X data memory space The DSP may use the 108 as a normal memory mapped peripheral employing either standard polled or interrupt driven programming techniques Separate transmit and receive data registers are double buffered to allow the DSP and host processor to transfer data efficiently at high speed Direct memory mapping allows the DSP56303 core to communicate with the 08 registers using standard instructions and addressing modes In addition the MOVEP instruction allows direct data transfers between DSP56303 internal memory and the 108 registers or vice versa There are two kinds of host processor registers data and control with eight registers in all eight registers can be accessed by the DSP core but not by the external host Data registers are 24 bit registers used for high speed data transfer to and from the DSP They are Host Data Receive Register HRX Host Data Transmit Register HTX The DSP side control registers are 16 bit registers used to control DSP functions The eight Most Significant Bits in the DSP side control registers are read by the DSP56303 as 0 These registers Host Control Register HCR Host Status Register HSR e Host Base Address Register HBAR Host Port Control Register HPCR Host GPIO Data Direction R
294. ift Register SRD may be programmed as a GPIO pin P4 when the ESSI SRD function is not being used 7 4 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI ESSI Data and Control Pins GDB DDB RX SHIFT REG SRD STD SCO 5 1 E Interrupts Clock Frame Sync Generators and Control Logic SC2 SCK AA0678 Figure 7 1 ESSI Block Diagram 7 3 3 Serial Clock SCK The SCK pin is a bidirectional pin providing the serial bit rate clock for the ESSI interface The SCK pin is a clock input or output used by all the enabled transmitters and receiver in Synchronous modes or by all the enabled transmitters in MOTOROLA DSP56303UM AD 7 5 Enhanced Synchronous Serial Interface ESSI ESSI Data and Control Pins Asynchronous modes see Table 7 1 on page 7 8 SCK may be programmed as a GPIO pin P3 when the ESSI SCK function is not being used Notes 1 Although an external serial clock can be independent of and asynchronous to the DSP system clock the external ESSI clock frequency must not exceed F 3 and each ESSI phase must exceed the minimum of 1 5 CLKOUT cycles 2 The internally sourced ESSI clock frequency must not exceed F 4 7 3 4 Serial Control Pin SCO 25510 SC00 ESSI SC10 The function of this pin is determined by selecting either Synchronous or Asynchronous mode see Table 7 4 on page 7 24 In Asynchronous mode this pin is used for the receive clock I O In Synchr
295. igure 10 10 on page 10 22 10 18 DSP56303UM AD MOTOROLA On Chip Emulation Module Pipeline Information and OGDB Register GDB Register OGDBR GDB PDB Register OPDBR 4 TDI PDB PIL Register OPILR TDO PIL AA0709 Figure 10 9 OnCE Pipeline Information and GDB Registers 10 81 OnCE PDB Register OPDBR The OnCE Program Data Bus Register OPDBR is a 24 bit latch that stores the value of the Program Data Bus generated by the last program memory access of the core before the Debug mode is entered The OPDBR register can be read or written through the JTAG port This register is affected by the operations performed during the Debug mode and must be restored by the external command controller when returning to Normal mode 10 8 2 PIL Register OPILR The OnCE PIL Register OPILR is a 24 bit latch that stores the value of the Instruction Latch before the Debug mode is entered OPILR can only be read through the JTAG port Note Since the Instruction Latch is affected by the operations performed during the Debug mode it must be restored by the external command controller when returning to Normal mode Since there is no direct write access to the Instruction Latch the task of restoring is accomplished by writing to OPDBR with no GO and In this case the data written on PDB is transferred into the Instruction Latch MOTOROLA DSP56303UM AD 10 19 On Chip Emulation Modul
296. imer Prescaler Timer Prescaler Load Register Count Register m Timer 0 21 bit Counter Timer 1 CLK 2 TIO2 AA0673 Figure 9 1 Triple Timer Module Block Diagram 9 2 2 Timer Block Diagram The timer block diagram see Figure 9 2 shows the structure of a timer module The timer programmer s model see Figure 9 3 shows the structure of the timer registers The three timers are identical in structure and function A generic timer is discussed in this section The timer includes a 24 bit counter a 24 bit read write Timer Control and Status Register TCSR a 24 bit read only Timer Count Register TCR a 24 bit write only Timer Load Register TLR a 24 bit read write Timer Compare Register TCPR and logic for clock selection and interrupt DMA trigger generation The Timer mode is controlled by the TC 3 0 bits of the Timer Control Status Register TCSR For a listing of the timer modes see Section 9 4 For a description of their operation see Section 9 4 1 9 4 DSP56303UM AD MOTOROLA Triple Timer Module Triple Timer Module Programming Model The DSP56303 views each timer as a memory mapped peripheral with four registers occupying four 24 bit words in the X data memory space Either standard polled or interrupt programming techniques can be used to service the timers The timer programming model is shown in Figure 9 3 GDB 24 Control Status Load Count Compare Register Register Register Regis
297. in to act as serial I O flag from the start of the frame in both Normal and Network mode The On demand mode transmit enable sequence can be the same as the Normal mode or the TE2 bit can be left enabled The TE2 bit is cleared by either a hardware reset signal or a software reset instruction Note The setting of the TE2 bit does not affect the generation of frame sync or output flags Frame SYNC 7 FSLO 0 FSL1 0 Frame SYNC FSLO 0 FSL1 1 _ XXX XXX SLOT 0 SLOT 1 SLOT 0 SLOT 1 0685 Figure 7 15 Network Mode External Frame Sync 8 Bit 2 Words Frame 7 4 2 15 CRB ESSI Transmit 1 Enable TE1 Bit 15 The 1 bit enables the transfer of data from 1 to Transmit Shift Register 1 TET is functional only when the ESSI is in Synchronous mode and is ignored when the ESSI is in Asynchronous mode When is set and a frame sync is detected the transmitter 1 is enabled for that frame When TE1 is cleared transmitter 1 is disabled after completing transmission of data currently in the ESSI Transmit Shift Register Any data present in TX1 is not transmitted If is cleared data can be written to TX1 the bit will be cleared but data will not be transferred to Transmit Shift Register 1 Keeping the 1 bit cleared until the start of the next frame causes the SCO pin to act as serial I O flag from the start of the frame in both Normal and Netw
298. increment the counter If the INV bit is set high to low transitions increment the counter If the INV bit is cleared low to high transitions increment the counter When the counter matches the value contained in the TCPR the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set If the TRM bit is set the counter is loaded with the value of the TLR when the next timer clock is received and the count is resumed If TRM bit is cleared the counter continues to be incremented on each timer clock This process is repeated until the timer is disabled i e TE is cleared If the counter overflows the TOF bit is set and if TOIE is set an overflow interrupt is generated The counter contents can be read at any time by reading the TCR 9 4 2 Signal Measurement Modes The following Signal Measurement modes are provided Measurement Input Width 9 20 DSP56303UM AD MOTOROLA Triple Timer Module Timer Modes of Operation Measurement Input Period Measurement Capture 9 4 2 1 Measurement Accuracy The external signal is synchronized with the internal clock used to increment the counter This synchronization process can cause the number of clocks measured for the selected signal value to vary from the actual signal value by plus or minus one counter clock cycle 9 4 2 2 Measurement Input Width Mode 4 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Kind TIO
299. inted to by the Vector Base Address VBA register in the Program Control Unit 4 4 1 Interrupt Sources Each interrupt is allocated two instructions in the table so there are 128 table entries for interrupt handling Table 4 2 shows the table entry address for each interrupt MOTOROLA DSP56303UM AD 4 9 Core Configuration Interrupt Sources and Priorities source The DSP56303 initialization program loads the table entry for each interrupt serviced with two interrupt servicing instructions In the DSP56303 only 46 of the 128 vector addresses are used for specific interrupt sources The remaining 82 are reserved If it is known that certain interrupts will not be used those interrupt vector locations may be used for program or data storage Table 4 2 Interrupt Sources rr Priority Address Level Interrupt Source Range VBA 00 3 Hardware RESET VBA 02 3 Stack Error VBA 04 3 Illegal Instruction VBA 06 3 Debug Request Interrupt VBA 08 3 Trap VBA 0A 3 Non Maskable Interrupt NMI VBA 0C 3 Reserved VBA 0E 3 Reserved VBA 10 0 2 IROA VBA 12 0 2 IROB VBA 14 0 2 16 0 2 TROD VBA 18 0 2 DMA Channel 0 VBA 1A 0 2 DMA Channel 1 VBA 1C 0 2 DMA Channel 2 VBA 1E 0 2 DMA Channel 3 VBA 20 0 2 DMA Channel 4 VBA 22 0 2 DMA Channel 5 VBA 24 0 2 TIMER 0 Compare VBA 26 0 2 TIMER 0 Overflow VBA 28 0 2 TIMER 1 C
300. ion message etc by forcing a frame error which is caused by a missing stop bit Hardware and software reset clear SBK 8 3 1 4 SCR Wakeup Mode Select WAKE Bit 5 When WAKE is cleared the Wakeup On Idle Line mode is selected In the Wakeup On Idle Line mode the SCI receiver is re enabled by an idle string of at least ten or eleven depending on WDS mode consecutive 1s The transmitter s software must provide this idle string between consecutive messages The idle string cannot occur within a valid message because each word frame contains a start bit that is 0 When WAKE is set the Wakeup On Address Bit mode is selected In the Wakeup On Address Bit mode the SCI receiver is re enabled when the last eighth or ninth data bit received in a character frame is 1 The ninth data bit is the address bit R8 in the 11 bit Multidrop mode the eighth data bit is the address bit in the 10 bit Asynchronous and 11 bit Asynchronous with parity modes Thus the received character is an address that has to be processed by all sleeping processors that is each processor has to compare the received character with its own address and decide whether to receive or ignore all following characters WAKE is cleared by hardware and software reset MOTOROLA DSP56303UM AD 8 9 Serial Communication Interface SCI SCI Programming Model 8 3 1 5 SCR Receiver Wakeup Enable RWU Bit 6 When RWU is set and the SCI is in an Asynchronous mode the wakeup funct
301. ion 7 5 3 Writing data to the data registers of the enabled transmitters or to the TSR clears TDE and also clears the interrupt Transmit interrupts with exception conditions have higher priority than normal transmit data interrupts If the Transmit Underrun Run TUE bit is set signaling that an exception has occurred and the TEIE bit is set the ESSI requests an SSI transmit data with exception interrupt from the interrupt controller TIE is cleared by either a hardware reset signal or a software reset instruction 7 4 2 19 CRB ESSI Receive Interrupt Enable RIE Bit 19 Setting the RIE enables a DSP receive data interrupt which is generated when both the RIE and Receive Data Register Full RDF bit in the SSISR are set When RIE is cleared this interrupt is disabled The use of the receive interrupt is described in Section 7 5 3 Reading the Receive Data Register clears RDF and the pending interrupt Receive interrupts with exception have higher priority than normal receive data interrupts If the Receiver Overrun Error ROE bit is set signaling that an exception has occurred and the REIE bit is set the ESSI requests an SSI receive data with exception interrupt from the interrupt controller RIE is cleared by either a hardware reset signal or a software reset instruction 7 4 2 20 CRB ESSI Transmit Last Slot Interrupt Enable TLIE Bit 20 Setting the TLIE bit enables an interrupt at the beginning of the last slot of a frame when the ES
302. ion is enabled is the SCI is asleep and can be awakened by the event defined by the WAKE bit In the Sleep state all interrupts and all receive flags except IDLE are disabled When the receiver wakes up RWU is cleared by the wakeup hardware The programmer can also clear the RWU bit to wake up the receiver RWU can be used by the programmer to ignore messages that are for other devices on a multidrop serial network Wakeup On Idle Line WAKE is cleared or Wakeup On Address Bit WAKE is set must be chosen 1 When WAKE is cleared and RWU is set the receiver does not respond to data on the data line until an idle line is detected 2 When WAKE is set and RWU is set the receiver does not respond to data on the data line until a data frame with Bit 9 set is detected When the receiver wakes up the RWU bit is cleared and the first frame of data is received If interrupts are enabled the CPU is interrupted and the interrupt routine reads the message header to determine if the message is intended for this DSP 1 If the message is for this DSP the message is received and RWU is set to wait for the next message 2 If the message is not for this DSP the DSP immediately sets RWU Setting RWU causes the DSP to ignore the remainder of the message and wait for the next message RWU is cleared by hardware and software reset RWU is ignored in the Synchronous mode 8 3 1 6 SCR Wired OR Mode Select WOMS Bit 7 When the WOMS bit i
303. ip Select Polarity HCSP Bit 13 If the HCSP bit is cleared the Host Chip Select HCS pin is configured as an active low input and HI08 is selected when the HCS pin is low If the HCSP pin is set HCS is configured as an active high input and 8 is selected when the HCS pin is high 6 5 6 15 HPCR Host Request Polarity HRP Bit 14 The HRP bit controls the polarity of the host request pins In the Single Host Request mode is cleared in ICR if HRP is cleared and host requests are enabled HREN is set and HEN is set the HREQ pin is an active low output If HRP is set and host requests are enabled the HREQ pin is an active high output 6 16 DSP56303UM AD MOTOROLA Host Interface HI08 HI08 DSP Side Programmer s Model In the Double Host Request mode is set in the ICR if HRP is cleared and host requests are enabled HREN is set and HEN is set the and HRRQ pins are active low outputs If HRP is set and host requests are enabled the and pins are active high outputs 6 5 6 16 HPCR Host Acknowledge Polarity HAP Bit 15 If the HAP bit is cleared the Host Acknowledge HACK pin is configured as an active low input The 108 drives the contents of the IVR onto the host bus when the HACK pin is low If the HAP bit is set the HACK pin is configured as an active high input HI08 outputs the contents of the when the HACK pin is high 6 5 7 Host Data Directi
304. irection DIR Bit 11 9 13 9 3 4 8 Data Input DI Bit 12 9 13 9 3 4 9 Data Output DO 13 9 14 9 3 4 10 Prescaler Clock Enable PCE Bit15 9 14 9 3 4 11 Timer Overflow Flag TOF Bit 20 9 14 9 3 4 12 Timer Compare 21 9 14 9 3 4 13 TCSR Reserved Bits 3 10 14 16 19 22 23 9 15 9 3 5 Timer Load Register TLR 9 15 9 3 6 Timer Compare Register TCPR 9 15 9 3 7 Timer Count Register TCR 9 16 9 4 TIMER MODES OF OPERATION 9 16 9 4 1 Timer 5 aa RS 9 17 9 4 1 1 Timer GPIO Mode 0 9 17 9 4 1 2 Timer Pulse Mode 1 9 18 9 4 1 3 Timer Toggle Mode 2 9 19 9 4 1 4 Timer Event Counter Mode 3 9 20 9 4 2 Signal Measurement Modes 9 20 9 4 2 1 Measurement Accuracy 9 21 9 4 2 2 Measurement Input Width Mode 4 9 21 9 4 2 3 Measurement Input Period Mode 5 9 22 9 4 2 4 Measurement Capture 9 23 9 4 3 Pulse Width Modulation PWM Mode 7 9 24 9 4 4 Watchdog 9 25 9 4 4 1 Watchdog Pulse Mode 9 9 25 9 4 4 2 Watchdog Toggle
305. ister PCR The read write 24 bit PCR controls the functionality of the ESSI GPIO pins Each of PC 5 0 bits controls the functionality of the corresponding port pin When PC i bit is set the corresponding port pin is configured as a ESSI pin When a bit is cleared the corresponding port pin is configured as a GPIO pin Either a hardware reset signal or a software reset instruction clear all PCR bits 7 6 5 4 3 2 1 0 Pos Pc4 Pco o GPio ESSI STDn SRDn SCKn SCKn2 SCKn1 5 55 0 PCRD ESSI 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 Reserved Bit Read As Zero Should Be Written With Zero For Future Compatibility 0688 Figure 7 18 Port Control Register PCR PCRC X FFFFBF PCRDX FFFFAF 7 44 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI GPIO Pins and Registers 7 6 2 Port Direction Register PRR The read write 24 bit PRR controls the data direction of the ESSI GPIO pins When is set the corresponding pin is an output pin When PRR i is cleared the corresponding pin is an input pin 7 6 5 4 3 2 1 0 Poco 0 1 ouput STDn SRDn SCKn SCKn2 SCKn1 SCKnO PRRC ESSIO PRRD ESSI 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 e Reserved Bit Read As Zero Should Be Written With Zero For Future Compatibility 0689 Figure 7 19 Port Direction Register PRR PRRC X FFFF
306. it RIE 7 26 bit 20 ESSI Transmit Last Slot Interrupt Enable bit TLIE 7 26 bit 21 ESSI Receive Last Slot Interrupt Enable bit RLIE 7 27 bit 22 ESSI Transmit Exception Interrupt Enable bit TEIE 7 27 bit 23 ESSI Receive Exception Interrupt Enable bit REIE 7 27 crystal input 2 7 register 6 25 bits 0 6 Host Vector bits HVO HV6 6 25 bit 7 Host Command bit HC 6 25 D D0 D23 2 9 data ALU 1 8 registers 1 8 data bus 2 3 signals 2 9 Data Input bit DI 9 13 Data Output bit DO 9 14 DC4 DC9 bits 7 12 DE signal 2 37 10 4 Debug Event signal DE signal 10 4 Debug mode in OnCE module 10 16 DEBUG REQUEST instruction 11 11 executing during Stop state 10 17 executing during Wait state 10 17 executing in OnCE module 10 17 DI bit 9 13 DIR bit 9 13 Direct Memory Access DMA 1 14 Direction bit DIR 9 13 Divide Factor DF 1 11 DMA 1 14 triggered by timer 9 27 DO bit 9 14 DO loop 1 10 Double Host Request bit HDRQ 6 23 DRAM 1 13 DSP56300 core 1 3 1 6 DSP56300 Family Manual 1 3 1 7 DSP56303 Functional Signal Groupings 2 3 signal groupings 2 3 DSP56303 Technical Data 1 3 MOTOROLA ENABLE_ONCE instruction 11 11 Enhanced Synchronous Serial Interface ESSI 1 16 2 3 2 26 2 29 Enhanced Synchronous Serial Interface 0 2 25 Enhanced Synchronous Serial Interface 1 2 29 ESSI after reset 7 36 asynchronous operating mode 7 41 frame sync length 7 42 frame sync polarity 7 42 frame sync selection 7 41
307. it DI 9 13 bit 13 Data Output bit DO 9 14 bit 15 Prescaler Clock Enable bit PCE 9 14 bit 20 Timer Overflow Flag bit TOF 9 14 bit 21 Timer Compare Flag bit TCF 9 14 reserved bits bits 3 10 14 16 19 22 23 9 15 TDE bit 7 29 TDI pin 11 5 TDI signal 2 35 TDO pin 11 5 TDO signal 2 36 TDRE bit 8 13 TE bit 8 11 9 9 TEO bit 7 24 bit 7 23 TE2 bit 7 22 TEIE bit 7 27 Test Access Port 1 11 11 3 Test Clock Input pin TCK 11 5 Test Data Input pin TDI 11 5 Test Data Output pin TDO 11 5 Test Mode Select Input pin TMS 11 5 Test Reset Input pin TRST 11 5 TFS bit 7 28 TIE bit 7 26 8 12 Time Slot Register TSR 7 34 timer special cases 9 27 Timer GPIO 5 4 timer 0 signal 100 2 34 timer 1 signal TIO1 2 34 timer 2 signal TIO2 2 35 Timer Compare Flag bit TCF 9 14 Timer Compare Interrupt Enable bit TCIE 9 9 Timer Compare Register TCPR 9 15 Timer Control bits 9 10 Timer Control Status Register TCSR 9 9 MOTOROLA DSP56303UM AD Timer Count Register TCR 9 16 Timer Enable bit TE 9 9 Timer Interrupt Enable bit TMIE 8 12 Timer Interrupt Rate bit STIR 8 12 Timer Load Register TLR 9 15 timer mode mode 0 GPIO 9 17 mode 1 timer pulse 9 18 mode 2 timer toggle 9 19 mode 3 timer event counter 9 20 mode 4 measurement input width 9 21 mode 5 measurement input period 9 22 mode 6 measurement capture 9 23 mode 7 pulse width modulation 9 24 mode 8
308. it Data Register Empty TXDE bit is set The host processor may program the TREO bit to assert the external HREO HTRO pin when TXDE is set This informs the host processor that the Transmit Byte Registers are empty Writing to the data register at host address 7 clears the TXDE bit The contents of the Transmit Byte Registers are transferred as 24 bit data to the HRX register when both the TXDE and the HRDF bit are cleared This transfer operation sets TXDE and HRDF Note When writing data to a peripheral device there is a two cycle pipeline delay until any status bits affected by this operation are updated If the user reads any of those status bits within the next two cycles the bit will not reflect its current status See the DSP56300 Family Manual appendix B Polling a peripheral device for write for further details MOTOROLA DSP56303UM AD 6 29 Host Interface HI08 HI08 External Host Programmer s Model 6 6 7 Host Side Registers After Reset Table 6 12 shows the result of the four kinds of reset on bits in each of the 108 registers seen by the host processor The hardware reset is caused by asserting the RESET pin The software reset is caused by executing the RESET instruction The individual reset is caused by clearing the HEN bit in the HPCR The stop reset is caused by executing the STOP instruction Table 6 12 Host Side Registers After Reset Reset Type R
309. its select the host command interrupt address to be used by the host command interrupt logic When the host command interrupt is recognized by the DSP interrupt control logic the address of the interrupt routine taken is 2 x HV The host can write HC and HV in the same write cycle The host processor can select any of the 128 possible interrupt routine starting addresses in the DSP by writing the interrupt routine address divided by 2 into the HV bits This means that the host processor can force any of the existing interrupt handlers 551 SCI IROA IRQB etc and can use any of the reserved or otherwise unused addresses provided they have been pre programmed in the DSP HV is set to 2A vector location 0054 by hardware software individual and stop resets 6 6 2 2 CVR Host Command Bit HC Bit 7 The HC bit is used by the host processor to handshake the execution of host command interrupts Normally the host processor sets HC to request a host command interrupt from the DSP56303 When the host command interrupt is acknowledged by the DSP56303 the HC bit is cleared by the 108 hardware The host processor can read the state of HC to determine when the host command has MOTOROLA DSP56303UM AD 6 25 Host Interface HI08 HI08 External Host Programmer s Model been accepted After setting HC the host must not write to the CVR again until HC is cleared by HI08 hardware Setting the HC bit causes Host Command Pending HCP to b
310. l Register PCRD Port D Direction Register PRRD and Port D Data Register PDRD These registers are described in Section 7 of this document 5 2 4 Port E Pins and Registers Each of the three Port E pins not used as a SCI pin can be configured as a GPIO pin The GPIO functionality of Port E is controlled by three registers Port E Control Register PCRE Port E Direction Register PRRE and Port E Data Register PDRE These registers are described in Section 8 of this document 5 2 5 Triple Timer Pins Each of the three Triple Timer Interface pins 0 2 not used as a timer pin can be configured as a GPIO pin Each pin is controlled by the appropriate Timer Control Status register TCSRO TCSR2 These registers are described in Section 9 of this document Es 5 4 DSP56303UM AD MOTOROLA MOTOROLA SECTION 6 HOST INTERFACE 108 DSP56303UM AD 6 1 Host Interface HI08 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 2 INTRODUCTION at oe Hee sey 6 3 HIOS FEATUBMES 4 t cd u tei 6 3 HI08 HOST PORT SIGNALS 6 6 8 BLOCK DIAGRAM 6 7 HI08 DSP SIDE PROGRAMMER S MODEL 6 8 HI08 EXTERNAL HOST PROGRAMMER S MODEL 6 20 SERVICING THE HOST INTERFACE 6 31 08 PROGRAMMING MODEL QUICK REFERENCE 6 34 DSP56303UM AD MOTOROLA Host Interface HI08 Introduction 6 1 INTRODUCTION The Host
311. l 3 VBA 20 0 2 DMA Channel 4 VBA 22 0 2 DMA Channel 5 VBA 24 0 2 TIMER 0 Compare VBA 26 0 2 TIMER 0 Overflow VBA 28 0 2 TIMER 1 Compare VBA 2A 0 2 TIMER 1 Overflow VBA 2C 0 2 TIMER 2 Compare 2 0 2 TIMER 2 Overflow VBA 30 0 2 ESSIO Receive Data VBA 32 0 2 ESSIO Receive Data With Exception Status VBA 34 0 2 ESSIO Receive Last Slot VBA 36 0 2 ESSIO Transmit Data MOTOROLA DSP56303UM AD D 11 PROGRAMMING REFERENCE Table D 2 Interrupt Sources Continued Interrupt Starting Interrupt Source Address Fever Range 38 0 2 ESSIO Transmit Data With Exception Status VBA 3A 0 2 ESSIO Transmit Last Slot VBA 3C 0 2 Reserved VBA 3E 0 2 Reserved VBA 40 0 2 55 Receive Data VBA 42 0 2 55 Receive Data With Exception Status VBA 44 0 2 ESSI1 Receive Last Slot VBA 46 0 2 ESSI1 Transmit Data 48 0 2 ESSI1 Transmit Data With Exception Status VBA 4A 0 2 ESSI1 Transmit Last Slot VBA 4C 0 2 Reserved VBA 4E 0 2 Reserved VBA 50 0 2 SCI Receive Data VBA 52 0 2 SCI Receive Data With Exception Status VBA 54 0 2 SCI Transmit Data VBA 56 0 2 SCI Idle Line VBA 58 0 2 SCI Timer VBA 5A 0 2 Reserved VBA 5C 0 2 Reserved VBA 5E 0 2 Reserved VBA 60 0 2 Host Receive Data Full VBA 62 0 2 Host Transmit Data Empty VBA 64 0 2 Host Command Default VBA 66 0 2 Reserved VBA FE 0
312. l Description SC10 PDO Input Or Output Input Discon nected Internally Serial Control 0 The function of SC10 is determined by the selection of either Synchronous or Asynchronous mode For Asynchronous mode this signal will be used for the receive clock I O Schmitt trigger input For Synchronous mode this signal is used either for Transmitter 1 output or for Serial I O Flag 0 Port D 0 The default configuration following reset is GPIO input PDO When configured as PDO signal direction is controlled through the Port D Direction Register PRRD The signal can be configured as an ESSI signal SC10 through the Port D Control Register PCRD This input is 5 V tolerant SC11 PD1 Input Output Input or Output Input Discon nected Internally Serial Control 1 The function of this signal is determined by the selection of either Synchronous or Asynchronous mode For Asynchronous mode this signal is the receiver frame sync I O For Synchronous mode this signal is used either for Transmitter 2 output or for Serial I O Flag 1 Port D 1 The default configuration following reset is GPIO input PD1 When configured as PD1 signal direction is controlled through PRRD The signal can be configured as an ESSI signal SC11 through PCRD This input is 5 V tolerant MOTOROLA DSP56303UM AD 2 29 Signal Connection Descriptions Enhanced Synchronous Serial Inter
313. le high speed interface to a host processor To the host bus the HI08 appears to be eight byte wide registers Separate transmit and receive data registers are double buffered to allow the DSP core and host processor to transfer data efficiently at high speed The host may access the 108 asynchronously by using polling techniques or interrupt based techniques The HI08 appears to the host processor as a memory mapped peripheral occupying eight bytes in the host processor address space see Table 6 7 The eight 108 registers include Acontrol register ICR Astatus register ISR e Three data registers RXH TXH RXM TXM and RXL TXL 6 20 DSP56303UM AD MOTOROLA Host Interface 108 HI08 External Host Programmer s Model Two vector registers IVR and CVR The CVR is a special command register that is used by the host processor to issue commands to the DSP56303 This register can be accessed only by the host processor Host processors may use standard host processor instructions e g byte move and addressing modes to communicate with the 108 registers 108 registers are aligned so that 8 bit host processors can use 8 16 24 bit load and store instructions for data transfers The and handshake flags are provided for polled or interrupt driven data transfers with the host processor Because of the speed of the DSP56303 interrupt response most host microprocessors can load o
314. lock and sync signals in the Asynchronous mode The SYN bit in CRB selects synchronous or asynchronous operation When the SYN bit is cleared the ESSI TX and RX clocks and frame sync sources are independent If the SYN bit is set the ESSI TX and RX clocks and frame sync are driven by the same source either external or internal Since the ESSI is designed to operate either synchronously or asynchronously separate receive and transmit interrupts are provided Transmitter 1 and transmitter 2 operate only in Synchronous mode Data clock and frame sync signals can be generated internally by the DSP or may be obtained from external sources If clocks are internally generated the ESSI clock generator derives bit clock and frame sync signals from the DSP internal system clock The ESSI clock generator consists of a selectable fixed prescaler with a programmable prescaler for bit rate clock generation and a programmable frame rate divider with a word length divider for frame rate sync signal generation 7 5 4 3 Frame Sync Selection The transmitter and receiver can operate independently The transmitter can have either a bit long or word long frame sync signal format and the receiver can have the same or another format The selection is made by programming FSL 1 0 FSR and FSP bits in the CRB 7 5 4 3 1 Controlling the Frame Sync Signal Format controls the frame sync signal format If the FSL1 bitis cleared the RX frame sync is asser
315. lock for the Transmit Shift Register and word length divider The internal clock is output on the SCK pin 7 16 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI ESSI Programming Model When SCKD is cleared the external clock source is selected The internal clock generator is disconnected from the SCK pin and an external clock source may drive this pin Either a hardware reset signal or a software reset instruction clears SCKD 7 4 2 6 CRB Shift Direction SHFD Bit 6 The setting of the SHFD bit determines the shift direction of the Transmit or Receive Shift Register If SHFD is set data is shifted out with the Least Significant Bit LSB first If SHFD is cleared data is shifted out MSB first see Figure 7 16 on page 7 31 and Figure 7 17 on page 7 32 Received data is shifted in LSB first when SHFD is set or MSB first when SHFD is cleared Either a hardware reset signal or a software reset instruction clears SHFD 7 4 2 7 CRB Frame Sync Length FSL 1 0 Bits 7 and 8 These bits select the length of frame sync to be generated or recognized see Figure 7 11 on page 7 19 Figure 7 14 on page 7 22 and Figure 7 15 on page 7 23 The meaning of the values of FSL 1 0 is described in Table 7 3 Table 7 3 FSL1 and FSLO Encoding Frame Sync Length FSL1 FSLO RX TX 0 0 word word 0 1 word bit 1 0 bit bit 1 1 bit word The word length is defined by WL 2 0 Either a hardware reset
316. lt lt lt lt lt lt lt lt KKK KKK x lt x KK KKK KKK KKK KK KKK KKK KK KKK KKK KK KK EQUAT ES for 56303 interrupts Last update June 11 1995 k x lt KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KK KKK KK KKK KKK KKK KK KKK page 132 55 0 0 0 opt mex intequ ident 1 0 if DEF I_VEC leave user definition as is else I EQU 50 endif Non Maskable interrupts I RESET EQU I 500 Hardware RESET I STACK EQU I 502 Stack Error I ILL I 504 Illegal Instruction I DBG I VEC 06 Debug Request I TRAP EQU I VEC 08 Trap I NMI EQU I VEC 0A Non Maskable Interrupt Interrupt Request Pins I IRQA EQU I 510 I IRQB EQU I 512 IROB I IRQC EQU I 514 I IRQD EQU I VEC4 16 DMA Interrupts I EQU I VEC S18 DMA Channel 0 I DMA1 EQU I_VEC S1A DMA Channel 1 IDMA2 EQU I VEC 1C DMA Channel 2 I DMA3 EQU I VEC SIE DMA Channel 3 MOTOROLA DSP56303UM AD B 15 Equates 4 EQU I 520 DMA Channel 4 I DMA5 EQU I 522 DMA Channel 5 Timer Interrupts I TIMOC EQU I_VEC
317. lue while the TE bit in the TCSR is set Inall modes if the TRM bit in the is cleared 0 the counter operates as a free running counter 9 3 6 Timer Compare Register TCPR The Timer Compare Register TCPR is a 24 bit read write register that contains the value to be compared to the counter value These two values are compared every timer clock after the TE bit in the TCSR is set When the values match the Timer Compare Flag TCF bit is set and an interrupt is generated if interrupts are enabled if the Timer Compare Interrupt Enable TCTE bit in the TCSR is set The TCPR is ignored in Measurement modes MOTOROLA DSP56303UM AD 9 15 Triple Timer Module Timer Modes of Operation 9 3 7 Timer Count Register TCR The Timer Count Register TCR is a 24 bit read only register In Timer and Watchdog modes the counter s contents can be read at any time by reading the TCR register In Measurement modes the TCR is loaded with the current value of the counter on the appropriate edge of the input signal and its value can be read to determine the width period or delay of the leading edge of the input signal When the timer is in Measurement modes the TIO pin is used for the input signal 9 4 TIMER MODES OF OPERATION Each timer has various operational modes that meet a variety of system requirements These modes are Timer GPIO Mode 0 Internal timer interrupt generated by the internal clock Pulse
318. ly the desired bit is cleared do not use the BSET 9 14 DSP56303UM AD MOTOROLA Triple Timer Module Triple Timer Module Programming Model command The proper way to clear these bits is to write using a MOVEP instruction a 1 to the flag to be cleared and a 0 to the other flag 9 3 4 13 TCSR Reserved Bits Bits 3 10 14 16 19 22 23 These reserved bits are read as 0 and should be written with 0 for future compatibility 9 3 5 Timer Load Register TLR The Timer Load Register TLR is a 24 bit write only register In all modes the counter is preloaded with the TLR value after the TE bit in the TCSR is set and a first event occurs e In Timer modes if the Timer Reload Mode TRM bit in the TCSR is set the counter is reloaded each time after it has reached the value contained by the Timer Compare Register and the new event occurs In Measurement modes if the TRM bit in the TCSR is set and the TE bit in the TCSR is set the counter is reloaded with the value in the TLR on each appropriate edge of the input signal In PWM modes if the TRM bit in the is set the counter is reloaded each time after it has overflowed and the new event occurs In Watchdog modes if the TRM bit in the TCSR is set the counter is reloaded each time after it has reached the value contained by the Timer Compare Register TCR and the new event occurs In this mode the counter is also reloaded whenever the TLR is written with a new va
319. m options for frame synchronization and clock generation One receiver and three transmitters per ESSI allows six channel home theater 1 16 DSP56303UM AD MOTOROLA DSP56303 Overview DSP56303 Architecture Overview 1 10 4 Serial Communications Interface SCI The DSP56303 s Serial Communications Interface SCI provides a full duplex port for serial communication to other DSPs microprocessors or peripherals such as modems The SCI interfaces without additional logic to peripherals that use TTL level signals With a small amount of additional logic the SCI can connect to peripheral interfaces that have non TTL level signals such as the RS 232C RS 422 etc This interface uses three dedicated pins Transmit Data TXD Receive Data RXD and SCI Serial Clock SCLK It supports industry standard asynchronous bit rates and protocols as well as high speed synchronous data transmission up to 8 25 Mbps for a 66 MHz clock The asynchronous protocols supported by the SCI include a Multidrop mode for master slave operation with Wakeup On Idle Line and Wakeup On Address Bit capability This mode allows the DSP56303 to share a single serial line efficiently with other peripherals The SCI consists of separate transmit and receive sections that can operate asynchronously with respect to each other A programmable baud rate generator provides the transmit and receive clocks An enable vector and an interrupt vector have been included so that
320. mand controller causes the DSP56300 core to finish the current instruction being executed save the instruction pipeline information enter the Debug mode and wait for commands to be entered from the TDI line If the DE pin is used to enter the Debug mode then it must be deasserted after the OnCE port responds with an acknowledge and before sending the first OnCE command The assertion of this pin by the DSP56300 core indicates that the DSP has entered the Debug mode and is waiting for commands to be entered from the TDI line The DE pin also facilitates multiple processor connections as shown in Figure 10 2 TDI AA0703 Figure 10 2 OnCE Module Multiprocessor Configuration In this way the user can stop all the devices in the system when one of the devices enters the Debug mode The user can also stop all the devices synchronously by asserting the DE line 10 4 OnCE CONTROLLER The OnCE controller contains the following blocks OnCE Command Register OCR OnCE Decoder and the status control register Figure 10 3 illustrates a block diagram of the OnCE controller 10 4 DSP56303UM AD MOTOROLA On Chip Emulation Module OnCE Controller TDI TCK OnCE Command Register t Update OnCE Decoder Status and Control E ie Register Register Read Register Write Mode Select AA0704 ISBKPT ISTRACE ISDR ISSWDBG TDO Figure 10 3 OnCE Controller Block Diagram 10 4 1 OnCE Command Regist
321. mitter Empty TRNE Bit 0 The TRNE flag bit is set when both the Transmit Shift Register and Transmit Data Register STX are empty to indicate that there is no data in the transmitter When TRNE is set data written to one of the three STX locations or to the Transmit Data Address Register STXA is transferred to the Transmit Shift Register and is the first data transmitted TRNE is cleared when TDRE is cleared by writing data into the STX or the STXA or when an idle preamble or break is transmitted This bit when set indicates that the transmitter is empty therefore the data written to STX or STXA is transmitted next That is there is no word in the Transmit Shift Register presently being transmitted This procedure is useful when initiating the transfer of a message i e a string of characters TRNE is set by the hardware software SCI individual and stop reset 8 3 2 2 SSR Transmit Data Register Empty TDRE Bit 1 The TDRE flag bit is set when the SCI Transmit Data Register is empty When TDRE is set new data can be written to one of the SCI Transmit Data Registers STX or the Transmit Data Address Register STXA TDRE is cleared when the SCI Transmit Data Register is written TDRE is set by the hardware software SCI individual and stop reset In the Synchronous mode when using the internal SCI clock there is a delay of up to 5 5 serial clock cycles between the time that STX is written until TDRE is set indicating the data
322. mmand controller to check whether the Debug mode has been entered either by sensing DE or by polling JTAG instruction shift register 10 12 2 Polling the JTAG instruction shift register In order to poll the core status bits in the JTAG Instruction Shift register the following sequence must be performed 1 Select shift IR Passing through capture IR loads the core status bits into the instruction shift register 2 Shiftin ENABLE ONCE While shifting in the new instruction the captured status information is shifted out Pass through update IR 3 Return to Run Test Idle 10 24 DSP56303UM AD MOTOROLA On Chip Emulation Module Examples of Using the OnCE The external command controller can analyze the information shifted out and detect whether the chip has entered the Debug mode 10 12 3 Saving Pipeline Information The debugging activity is accomplished by means of DSP56300 core instructions supplied from the external command controller Therefore the current state of the DSP56300 core pipeline must be saved prior to starting the debug activity and of course the state must be restored prior to returning to the Normal mode of operation Following is the description of the saving procedure assume that ENABLE_ONCE has been executed and Debug mode has been entered and verified as described in Checking Whether the Chip has Entered the Debug Mode on page 10 24 1 Select shift DR Shift in the Read PDB Pass through update DR
323. mmands that can be accompanied by 24 bits of data Both commands and data are sent or received LSB first After sending a command the external command controller should wait for the DSP56300 core chip to acknowledge execution of the command The external command controller can send a new command only after the chip has acknowledged execution of the previous command The OnCE commands are classified as follows Read commands when the chip delivers the required data Write commands when the chip receives data and writes the data in one of the OnCE registers Commands that do not have data transfers associated with them The commands are 8 bits long and have the format shown in Figure 10 4 on page 10 5 10 11 TARGET SITE DEBUG SYSTEM REQUIREMENTS A typical debug environment consists of a target system where the DSP56300 core based device resides in the user defined hardware The JTAG port interfaces to the external command controller over a 8 wire link consisting of the five JTAG port wires one OnCE module wire a ground and a reset wire The reset wire is optional and is only used to reset the DSP56300 core based device and its associated circuitry The external command controller acts as the medium between the DSP56300 core target system and a host computer The external command controller circuit acts as a JT AG port driver and host computer command interpreter The controller issues commands based on the host computer input
324. more Transmit Data Registers or the Time Slot Register TSR before setting the TE bit The normal transmit disable sequence is to clear the TE Transmit Interrupt Enable TIE and Transmit Exception Interrupt Enable TEIE bits after the Transmit Data Empty TDE bit is set In the Network mode clearing the appropriate TE bit and setting it again disables the corresponding transmitter 0 1 or 2 after transmission of the current data word The transmitter remains disabled until the beginning of the next frame During that time period the corresponding SC or STD in the case of pin remains in the high impedance state 7 4 2 14 CRB ESSI Transmit 2 Enable TE2 Bit 14 The TE2 bit enables the transfer of data from TX2 to Transmit Shift Register 2 TE2 is functional only when the ESSI is in Synchronous mode and is ignored when the ESSI is in Asynchronous mode When TE2 is set and a frame sync is detected the transmitter 2 is enabled for that frame When TE2 is cleared transmitter 2 is disabled after completing transmission of data currently in the ESSI Transmit Shift Register Any data present in TX2 is not transmitted If TE2 is cleared data can be written to TX2 the TDE bit will be cleared but data will not be transferred to Transmit Shift Register 2 7 22 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI ESSI Programming Model Keeping the TE2 bit cleared until the start of the next frame causes the SC1 p
325. nable normal instruction execution The sequence of actions is 1 Select shift DR Shift in the Write PDB with no GO no EX Pass through update DR 2 Select shift DR Shift in the 24 bits of saved PIL instruction latch value Pass through update DR to actually write the Instruction Latch 3 Select shift DR Shift in the Write PDB with GO and EX Pass through update DR 4 Select shift DR Shift in the 24 bits of saved PDB Pass through update DR to actually write the PDB At the same time the internally saved value of the PAB is driven back from the PABFR register onto the PAB the ODEC releases the chip from Debug mode and the normal flow of execution is continued 10 12 8 Returning from Debug Mode to Normal Mode to a New Program In this case the user has finished examining the current state of the machine changed some of the registers and wishes to start the execution of a new program the GOTO command Therefore the user must force a change of flow to the starting address of the new program xxxx The sequence of actions is 1 Select shift DR Shift in the Write PDB with no GO no EX Pass through update DR 1 Select shift DR Shift in the 24 bit 0AF080 which is the opcode of the JUMP instruction Pass through update DR to actually write the Instruction Latch 2 Select shift DR Shift in the Write PDB GO TO with GO and EX Pass through update DR 3 Select shift DR Shift in the 16 bit of xx
326. nal Description Reset Stop STD1 Input Input Discon Serial Transmit Data STD1 is used for Output nected transmitting data from the serial Transmit Internally Shift Register STD1 is an output when data is being transmitted Port D 5 The default configuration following reset is GPIO input PD5 When configured as PD5 signal direction is controlled through PRRD The signal can be configured as an ESSI signal STD1 through PCRD This input is 5 V tolerant Note 1 The Wait processing state does not affect the signal s state 2 11 SERIAL COMMUNICATION INTERFACE 5 The Serial Communication interface SCI provides a full duplex port for serial communication to other DSPs microprocessors or peripherals such as modems 2 32 DSP56303UM AD MOTOROLA Signal Connection Descriptions Serial Communication Interface SCI Table 2 14 Serial Communication Interface SCI State During Signal Signal Description Reset Stop RXD Input Input Discon Serial Receive Data This input receives nected byte oriented serial data and transfers it to the Internally SCI Receive Shift Register PEO Input Port E 0 The default configuration Or following reset is GPIO input When Output configured as PEO signal direction is controlled through the SCI Port E Direction Register PRRE The signal can be configured as an SCI signal RXD through the SCI Port E
327. ndition Select Table 01 00 Description 0 0 Breakpoint on not equal 0 1 Breakpoint on equal 1 0 Breakpoint on less than 1 1 Breakpoint on greater than 10 5 6 4 Breakpoint 1 Read Write Select RW10 RW11 Bits 6 7 The Breakpoint 1 Read Write Select RW10 RW11 bits control define memory breakpoint 1 to occur when a memory address accesses is performed for read write or both See Table 10 9 for the definition of the RW10 RW11 bits Table 10 9 Breakpoint 1 Read Write Select Table RW11 RW10 Description 0 0 Breakpoint disabled 0 1 Breakpoint on write access 1 0 Breakpoint on read access 1 1 Breakpoint read write access MOTOROLA DSP56303UM AD 10 13 On Chip Emulation Module OnCE Memory Breakpoint Logic 10 5 6 5 Breakpoint 1 Condition Code Select 10 11 Bits8 9 The Breakpoint 1 Condition Code Select bits CC10 CC11 define the condition of the comparison between the current memory address OMALO and the OnCE Memory Limit Register 1 OMLR1 See Table 10 10 for the definition of the CC10 CC11 bits Table 10 10 Breakpoint 1 Condition Select Table CC11 CC10 Description 0 0 Breakpoint on not equal 0 1 Breakpoint on equal 1 0 Breakpoint on less than 1 1 Breakpoint on greater than 10 5 6 6 Breakpoint 0 and 1 Event Select BT0 BT1 Bits10 11 Breakpoint 0 and 1 Event Select bits 0 1 define the sequence
328. nical Data DSP56303 D provides electrical specifications timing pinout and packaging descriptions of the DSP56303 These documents as well as Motorola s DSP development tools can be obtained through a local Motorola Semiconductor Sales Office or authorized distributor To receive the latest information on this DSP access the Motorola DSP home page at the address given on the back cover of this document 1 2 MANUAL ORGANIZATION This manual contains the following sections and appendices SECTION 1 DSP56303 OVERVIEW Provides a brief description of the DSP56303 including a features list and block diagram lists related documentation needed to use this chip and describes the organization of this manual SECTION 2 SECTION CONNECTION DESCRIPTIONS Describes the signals on the DSP56303 pins and how these signals are grouped into interfaces SECTION 3 MEMORY CONFIGURATION Describes the DSP56303 memory spaces RAM configuration memory configuration bit settings memory configurations and memory maps SECTION 4 CORE CONFIGURATION Describes the registers used to configure the DSP56300 core when programming the DSP56303 in particular the interrupt vector locations and the operation of the interrupt priority registers explains the operating modes and how they affect the processor s program and data memories MOTOROLA DSP56303UM AD 1 3 DSP56303 Overview Manual Organization SECTION 5 GENERAL PURPOSE
329. nsmit Slot Mask 0 IgnoreTime Slot 1 Active Time Slot Sheet 4 of 4 23 16 115 14 13 12 11 3 1 ESSI Transmit Slot Mask A X rsis rsi4 Tsis Tsi2 Tsii Tsio 59 TS8 TS7 TS6 55 154 52 51 TSO 25510 FFFFB4 Read Write Reset FFFF ESSI Transmit Slot Mask A Reserved Program as 0 SSI Transmit Slot Mask 0 IgnoreTime Slot 1 ActiveTime Slot 23 16 15 14 13 12 11 10 ESSI Transmit Slot Mask B TSMBx ESSIO FFFFB3 Read Write ESSI FFFFA3 Read Write E Reset FFFF ESSI Transmit Slot Mask B Reserved Program as 0 SSI Receive Slot Mask 0 IgnoreTime Slot 1 ActiveTime Slot 23 16 115 14 13 12 11 7 6 3 SSI Receive Slot Mask A X RS15 RS14 RS13 RS12 RS11 RS10 859 RS8 857 Rse 855 854 853 852 851 RSO ESSIO FFFFB2 Read Write Reset FFFF ESSI Receive Slot Mask A Reserved Program as 0 SSI Receive Slot Mask 0 Ignore Time Slot 1 Active Time Slot 23 16115 14 13 12 11 10 9 8 SSI Receive Slot Mask B 4 nss nsso Rs2e Rszs Rs27 Rs2e Rse5 8524 523 522 Rse1 8520 519 8518 8517 8516 meo ESSIO FFFFB1 Read Write Reset FFFF ESSI Receive Slot Mask B Reserved Program as 0 Figure D 15 ESSR Transmit and Receive Slot Mask Registers TSM RSM MOTOROLA DSP56303UM AD D 29 PROGRAMMING REFERENCE Application Date Programmer Sheet 1 of 3 Port E Pin Control 0 General Purpose
330. o be used 4 Write initial data to the transmitters which will be in use during operation This step is needed even if DMA is used to service the transmitters 5 Enable the transmitters and receiver to be used Now the ESSI can be serviced by polling interrupts or DMA Once the ESSI has been enabled Step 3 operation will start as follows For internally generated clock and frame sync these signals will start activity immediate after the ESSI is enabled Data will be received by the ESSI after the occurrence of a frame sync signal either internally or externally generated only when the Receive Enable RE bit is set Data will be transmitted after the occurrence of a frame sync signal either internally or externally generated only when the Transmitter Enable TE 2 0 bit is set MOTOROLA DSP56303UM AD 7 37 Enhanced Synchronous Serial Interface ESSI Operating Modes 7 5 3 ESSI Exceptions The ESSI can generate six different exceptions They are discussed in the following paragraphs ordered from the highest to the lowest exception priority 1 Note 7 38 ESSI Receive Data with Exception Status Occurs when the receive exception interrupt is enabled the Receive Data Register is full and a receiver overrun error has occurred This exception sets the ROE bit The ROE bit is cleared by first reading the SSISR and then reading RX ESSI Receive Data Occurs when the receive interrupt is enabled
331. o the Transmit Shift Register The flag bits values are synchronized with the data transfer Note The timing of the optional serial output pins SC 2 0 is controlled by the frame timing and is not affected by the settings of TE2 TE1 or the Receive Enable RE bit of the CRB 7 4 2 1 1 CRB Serial Output Flag 0 Bit 0 When the ESSI is in Synchronous mode and transmitter 1 is disabled TE1 0 the SCO pin is configured as ESSI flag 0 If the serial control direction bit SCDO is set the SCO pin is an output Data present in bit OFO is written to SCO at the beginning of the frame in Normal mode or at the beginning of the next time slot in Network mode MOTOROLA DSP56303UM AD 7 15 Enhanced Synchronous Serial Interface ESSI ESSI Programming Model Bit is cleared by a hardware reset signal or by a software reset instruction 7 4 2 1 2 CRB Serial Output Flag 1 OF1 Bit 1 When the ESSI is in Synchronous mode and transmitter 2 is disabled TE2 0 the pin is configured as ESSI flag 1 If the serial control direction bit SCD1 is set the 5 1 pin is an output Data present in bit OF1 is written to SC1 at the beginning of the frame in Normal mode or at the beginning of the next time slot in Network mode Bit OF1 is cleared by a hardware reset signal or by a software reset instruction 7 4 2 2 CRB Serial Control Direction 0 SCDO Bit 2 In Synchronous mode SYN 1 when transmitter 1 is disabled TE1 0
332. ocessor To achieve this special circuits and dedicated pins on the DSP56300 core are defined to avoid sacrificing any user accessible on chip resource The OnCE module resources can be accessed only after executing the JTAG instruction ENABLE ONCE these resources are accessible even when the chip is operating in Normal mode See Section 11 JTAG Port for a description of the JTAG functionality and its relation to the OnCE Figure 10 1 shows the block diagram of the OnCE module PDB PIL GDB Pipeline Controller TDO Breakpoint Logic AA0702 Figure 10 1 OnCE Module Block Diagram 10 2 OnCE MODULE PINS The OnCE module controller functionality is accessed through the JTAG port There are no dedicated OnCE module pins for clock data in data out The JT AG pins TCK TDI and TDO are used to shift in and out data and instructions See JTAG Pins on page 11 5 for the description of the JTAG pins To facilitate emulation specific functions one additional pin called DE is provided on the DSP56303 MOTOROLA DSP56303UM AD 10 3 On Chip Emulation Module Debug Event DE 10 3 DEBUG EVENT DE The bidirectional open drain Debug Event pin DE provides a fast means of entering the Debug mode of operation from an external command controller when input as well as a fast means of acknowledging the entering of the Debug mode of operation to an external command controller when output The assertion of this pin by a com
333. om to write in the value of each bit and the hexadecimal value for each register The programmer can photocopy these sheets and reuse them for each application development project For details on the instruction set of the DSP56300 family chips see the DSP56300 Family Manual D 1 1 Peripheral Addresses Table D 1 lists the memory addresses of all on chip peripherals D 1 2 Interrupt Addresses Table D 2 lists the interrupt starting addresses and sources D 1 3 Interrupt Priorities Table D 3 lists the priorities of specific interrupts within interrupt priority levels D 1 4 Programming Sheets The remaining figures describe the major programmable registers on the DSP56303 MOTOROLA DSP56303UM AD D 3 PROGRAMMING REFERENCE D 2 INTERNAL I O MEMORY MAP Table D 1 Internal I O Memory 16 Bit 24 Bit Peripheral Address Address Register Name IPR FFFF FFFFFF Interrupt Priority Register Core IPR C FFFE FFFFFE Interrupt Priority Register Peripheral IPR P PLL FFFD FFFFFD PLL Control Register PCTL OnCE FFFC FFFFFC OnCE GDB Register OGDB BIU FFFB Bus Control Register BCR FFFA FFFFFA DRAM Control Register DCR FFF9 FFFFF9 Address Attribute Register 0 AARO FFF8 FFFFF8 Address Attribute Register 1 AAR1 FFF7 7 Address Attribute Register 2 2 FFF6 FFFFF6 Address Attribute Register 3 FFF5 FFFFF5 ID Regi
334. ommand controller goes to step b step etc until the Debug mode is acknowledged Table 10 13 TMS Sequencing for ENABLE ONCE Step TMS JT AG Port OnCE Module Note a 1 Test Logic Reset Idle b 0 Run Test Idle Idle 1 Select DR Scan Idle d 1 Select IR Scan Idle e 0 Capture IR Idle The core status bits are captured 10 30 DSP56303UM AD MOTOROLA On Chip Emulation Module Examples of JTAG and OnCE interaction Table 10 13 TMS Sequencing for ENABLE ONCE Step TMS JT AG Port OnCE Module Note f 0 Shift IR Idle The four bits of the JTAG ENABLE_ONCE instruction 0 Shift IR Idle 0110 are shifted into the JTAG 0 Shift IR Idle instruction register while status is shifted out i 0 Shift IR Idle j 1 Exit1 IR Idle k 1 Update IR Idle The OnCE module is enabled 1 0 Run Test Idle Idle This step can be repeated enabling an external command controller to ee E adie Ce T eos poll the status 1 0 Run Test Idle Idle Table 10 14 TMS Sequencing for Reading Pipeline Registers Step TMS JTAG Port OnCE Module Note a 0 Run Test Idle Idle b 1 Select DR Scan Idle 0 Capture DR Idle d 0 Shift DR Idle The eight bits of the OnCE command Read PIL 10001011 are shifted in d 0 Shift DR Idle e
335. ompare VBA 2A 0 2 TIMER 1 Overflow VBA 2C 0 2 TIMER 2 Compare VBA 2E 0 2 TIMER 2 Overflow 4 10 DSP56303UM AD MOTOROLA Core Configuration Interrupt Sources and Priorities Table 4 2 Interrupt Sources Continued Interrupt Starting pu I Address eve nterrupt Source Range VBA 30 0 2 ESSIO Receive Data VBA 32 0 2 ESSIO Receive Data With Exception Status VBA 34 0 2 ESSIO Receive Last Slot VBA 36 0 2 ESSIO Transmit Data VBA 38 0 2 ESSIO Transmit Data With Exception Status VBA 3A 0 2 ESSIO Transmit Last Slot VBA 3C 0 2 Reserved VBA 3E 0 2 Reserved VBA 40 0 2 ESSI1 Receive Data VBA 42 0 2 ESSI1 Receive Data With Exception Status VBA 44 0 2 ESSI1 Receive Last Slot VBA 46 0 2 ESSI1 Transmit Data VBA 48 0 2 ESSI1 Transmit Data With Exception Status VBA 4A 0 2 ESSI1 Transmit Last Slot VBA 4C 0 2 Reserved VBA 4E 0 2 Reserved VBA 50 0 2 SCI Receive Data VBA 52 0 2 SCI Receive Data With Exception Status VBA 54 0 2 SCI Transmit Data VBA 56 0 2 SCI Idle Line VBA 58 0 2 SCI Timer VBA 5A 0 2 Reserved VBA 5C 0 2 Reserved VBA 5E 0 2 Reserved VBA 60 0 2 Host Receive Data Full VBA 62 0 2 Host Transmit Data Empty VBA 64 0 2 Host Command Default VBA 66 0 2 Reserved VBA FE 0 2 Reserved MOTOROLA DSP56303UM AD 4 11 Core Configuration Interrupt Sources and Priorities 4 4 2 Interrupt P
336. on Register HDDR The HDDR controls the direction of the data flow for each of the 108 pins configured as GPIO Even when 08 is used as the host interface its unused pins may be configured as GPIO pins For information on the HI08 GPIO configuration options see 6 6 8 General Purpose I O on page 6 30 If bit DRxx is set the corresponding 08 pin is configured as an output pin If bit is DRxx cleared the corresponding 08 pin is configured as an input pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DR15 DR14 DR13 DR12 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR3 DR1 DRO 0663 Figure 6 9 Host Data Direction Register HDDR X FFFFC8 6 5 8 Host Data Register HDR The register holds the data value of the corresponding bits of the 108 pins configured as GPIO pins The functionality of the bit Dxx depends on the corresponding HDDR bit DRxx The HDR cannot be accessed by the host processor 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 015 D14 013 D12 011 D10 D9 D8 D7 06 D5 D4 D3 D2 D1 DO 0664 Figure 6 10 Host Data Register HDR 9 MOTOROLA DSP56303UM AD 6 17 Host Interface HI08 HI08 DSP Side Programmer s Model Table 6 5 HDR Functionality binary value of the pin T
337. one from DMA channel 2 00111 Transfer Done from DMA channel 3 01000 Transfer Done from DMA channel 4 01001 Transfer Done from DMA channel 5 01010 ESSIO Receive Data RDFO 1 01011 ESSIO Transmit Data TDEO 1 01100 ESSI1 Receive Data RDF1 1 4 16 DSP56303UM AD MOTOROLA Core Configuration Operating Mode Register OMR Table 4 5 DMA Request Sources Continued DMA Request Source Bits Requesting Device DRS4 DRSO 01101 ESSI1 Transmit Data TDE1 1 01110 SCI Receive Data RDRF 1 01111 SCI Transmit Data TDRE 1 10000 0 1 10001 1 TCF1 1 10010 Timer2 TCF2 1 10011 Host Receive Data Full HRDF 1 10100 Host Transmit Data Empty HTDE 1 10101 11111 Reserved 4 6 OPERATING MODE REGISTER OMR The Operating Mode Register OMR is a 24 bit read write register divided into three byte sized units The first two bytes COM and EOM are used to control the chip s operating mode The third byte SCS is used to control and monitor the stack extension The OMR control bits are shown in Figure 4 3 Refer to the DSP56300 Family Manual for a complete description of the OMR SCS EOM COM 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BRT TAS CDP1 0 MS SD EBD MD MB MA SEN Stack Extension Enable A
338. one pin as ESSI pin QUE dec 29552 If an external frame sync will be used from the moment the ESSI is activated at least five 5 serial clocks are needed before the first external frame sync is supplied Otherwise improper operation may result 7 36 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI Operating Modes Clearing the PC 5 0 bits in the GPIO Port Control Register PCR during program execution causes the ESSI to stop serial activity and enter the individual reset state status bits of the interface are set to their reset state The contents of CRA and CRB are not affected The ESSI individual reset allows a program to reset each interface separately from the other internal peripherals During ESSI individual reset internal DMA accesses to the data registers of the ESSI are not valid and data read is undefined To ensure proper operation of the ESSI use an ESSI individual reset when changing the ESSI Control Registers except for bits TEIE REIE TLIE RLIE TIE RIE TE2 TE1 TEO and RE Here is an example of initializing the ESSI 1 Put the ESSI in its individual reset state by clearing the PCR bits 2 Configure the Control Registers CRA to set the operating mode Disable the transmitters and receiver by clearing the TE 2 0 and RE bits Set the interrupt enable bits for the operating mode chosen 3 Enable the ESSI by setting the PCR bits to activate the input output pins t
339. onous mode this pin is used as the transmitter data out pin for Transmit Shift Register 1 or for serial flag I O A typical application of serial flag I O would be multiple device selection for addressing in codec systems If SCO is configured as a serial flag pin its direction is determined by the Serial Control Direction 0 SCD0 bit in the ESSI Control Register B CRB When configured as an output its direction is determined by the value of the serial Output Flag 0 bit in the CRB If 5 0 is an output this pin can be configured as either serial output flag 0 or a Receive Shift Register clock output If SCO is an input this pin may be used either as serial input flag 0 or as a Receive Shift Register clock input If SCO is used as serial input flag 0 it controls the state of serial Input Flag 0 IFO bit in the ESSI Status Register SSISR When SCO is configured as a transmit data pin it is always an output pin regardless of the SCDO bit value SCO is fully synchronized with the other transmit data pins STD and SC1 SCO may be programmed as a GPIO pin when the ESSI SCO function is not being used Note The ESSI can operate with more than one active transmitter only in Synchronous mode 7 6 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI ESSI Data and Control Pins 7 3 5 Serial Control Pin SC1 5510 5 01 ESSI1 SCI11 The function of this pin is determined by selecting either Synchr
340. onous or Asynchronous mode see Table 7 4 on page 7 24 In Asynchronous mode such as a single codec with asynchronous transmit and receive SC1 is the receiver frame sync I O In Synchronous mode SC1 is used for the transmitter data out pin of Transmit Shift Register TX2 for the drive enable transmitter 0 signal or for serial flag SC1 When used as 5 1 it operates like the previously described SCO SCO and SC1 are independent flags but may be used together for multiple serial device selection SCO and 5 1 can be used unencoded to select up to two codecs or may be decoded externally to select up to four codecs If SC1 is configured as a serial flag pin its direction is determined by the SCD1 bit in the CRB When configured as an output SC1 functionality is determined by control bit OF1 in the SSISR The SC1 pin can be used as a serial output flag the transmitter 0 drive enable signal or the receive frame sync signal output When configured as an input this pin can be used as to receive frame sync signals from an external source or it can be used as a serial input flag When SC1 is a serial input flag it controls status bit IF1 in the SSISR When this pin is configured as a transmit data pin it is always an output pin regardless of the SCD1 bit value As an output it is fully synchronized with the other ESSI transmit data pins STD and SCO SC1 may be programmed as a GPIO pin P1 when the ESSI SC1 function is not being used MOTOROLA
341. ontroller that the Debug mode of operation has been entered 10 7 4 External Debug Request During Stop Executing the JTAG instruction DEBUG REQUEST or asserting DE while the chip is in the Stop state i e has executed a STOP instruction causes the chip to exit the Stop state and enter the Debug mode After receiving the acknowledge the external command controller must negate DE before sending the first command Note In this case the chip completes the execution of the STOP instruction and halts after the next instruction enters the instruction latch 10 7 5 External Debug Request During Wait Executing the JTAG instruction REQUEST or asserting DE while the chip is in the Wait state i e has executed a WAIT instruction causes the chip to exit the Wait state and enter the Debug mode After receiving the acknowledge the external command controller must negate DE before sending the first command MOTOROLA DSP56303UM AD 10 17 On Chip Emulation Module Pipeline Information and OGDB Register Note In this case the chip completes the execution of the WAIT instruction and halts after the next instruction enters the instruction latch 10 7 6 Software Request During Normal Activity Upon executing the DSP56300 core instruction DEBUG or DEBUGcc when the specified condition is true the chip enters the Debug mode after the instruction following the DEBUG instruction has entered the instruction latch 10 7 7 Enablin
342. oop Flag DO Forever Flag Sixteen Bit Arithmetic Mask 1 0 Address Attribute Pin Polarity Program Space Enable X Data Space Enable Y Data Space Enable Address Muxing Packing Enable Number of Address Bits to Compare Mask Address to Compare Bits Mask 11 0 SR mask for CORE DMA priority bits in SR Carry Overflow Zero legative Unnormalized Extension Limit Scaling Bit Interrupt Mask Interrupt Mask Scaling Mode Bi lode Bi Bi Bi Cc Cr 1 lultiply Enable Instruction Cache Arithmetic Saturation Rounding Mode bit 0 of priority bits in SR bit 1 of priority bits in SR OMR mask for CORE DMA priority bits in OMR Operating Mode A Operating Mode B Operating Mode C Operating Mode D External Bus Disable bit in OMR Stop Delay Memory Switch bit in OMR bit 0 of priority bits in OMR bit 1 of priority bits in OMR Burst Enable Synchronize Select Bus Release Timing Address Tracing Enable bit in OMR Stack Extension space select bit in OMR DSP56303UM AD MOTOROLA M EUN EQU M EOV EQU M WRP EQU M SEN EQU 10 17 18 19 20 Equates Extended stack UNderflow flag in OMR Extended stack OVerflow flag in OMR Extended WRaP flag in OMR Stack Extension Enable bit in OMR INTERRUPT EQUATES INT ERRUPT EQUAT ES k x KKK KKK KK KKK lt
343. op Counter register LC 1 11 MAC 1 9 Manual Conventions 1 5 MBO bit 10 9 MBSO MBS1 bits 10 12 memory bootstrap ROM 3 7 enabling breakpoints 10 18 expansion 1 13 external expansion port 1 13 maps 3 9 off chip 1 13 on chip 1 12 program RAM 3 6 X data RAM 3 6 Y data RAM 3 7 Memory Breakpoint Occurrence bit MBO 10 9 Memory Breakpoint Select bits MBSO MBS1 10 12 memory configuration 3 7 memory spaces 3 7 RAM 3 8 MF bits 4 18 MIPS 1 7 MOD bit 7 20 2 15 MODB IRQB 2 15 MODC IRQC 2 16 MODD IRQD 2 16 mode control 2 14 2 15 Mode Select bit MOD 7 20 mode select A signal 2 15 mode select B signal 2 15 mode select C signal 2 16 mode select D signal 2 16 MOTOROLA modulo adder 1 9 multiplexed bus 2 4 Multiplication Factor bits MF 4 18 multiplier accumulator MAC 1 8 1 9 N non maskable interrupt 2 8 non multiplexed bus 2 4 O OBCR register 10 12 bits 0 1 Memory Breakpoint Select bits MBSO MBS1 10 12 bits 2 3 Breakpoint 0 Read Write Select bits RW00 RWO 10 12 bits 4 5 Breakpoint 0 Condition Code Select bits CC00 CCO01 10 13 bits 6 7 Breakpoint 1 Read Write Select bits RW10 RW11 10 13 bits 8 9 Breakpoint 1 Condition Code Select bits CC10 CC11 10 14 bits 10 11 Breakpoint 0 and 1 Event Select bits BTO BT1 10 14 reserved bits bits 12 15 10 15 OCR register bits 0 4 Register Select bits RS0 RS4 10 5 bit 5 Exit Command bit EX 10 5 bit 6 GO Command bit GO
344. ore e Program Address Bus PAB for carrying program memory addresses throughout the core XMemory Address for carrying X memory addresses throughout the core Y Memory Address Bus for carrying Y memory addresses throughout the core MOTOROLA DSP56303UM AD 1 13 DSP56303 Overview DSP56303 Block Diagram With the exception of the Program Data Bus PDB all internal buses on the DSP56300 family members are 16 bit buses The PDB is a 24 bit bus Figure 1 1 provides a block diagram of the DSP56303 1 8 DSP56303 BLOCK DIAGRAM Memory Expansion Area Host ESSI Interface Interface Peripheral Expansion Area External Address Generation Address ADDRESS Six Channel DMA Unit External Bus Interface Cache Control CONTROL o L I pas co ata Bus a suc Program Program ce Interrupt Decode Address 24 x 24 56 gt 56 bit MAC Controller Controller Generator Two 58 ot Acoumu atore MODD IRQA MODC IRQB MODB IRQC PINIT NMI MODA IRQD Figure 1 1 DSP56303 Block Diagram AA0456 Note See Section 1 6 6 On Chip Memories for details of memory size 4 DSp563O3UMAD MOTOROLA DSP56303 Overview Direct Memory Access DMA 1 9 DIRECT MEMORY ACCESS DMA The Direct Memory Access DMA block has the following features e Six DMA channels supporting internal and external accesses One two and three dimensional transfers inclu
345. ork mode The On demand mode transmit enable sequence can be the same as the Normal mode or the bit can be left enabled MOTOROLA DSP56303UM AD 7 23 Enhanced Synchronous Serial Interface ESSI ESSI Programming Model The 1 bit is cleared by either a hardware reset signal or a software reset instruction Note The setting of the bit does not affect the generation of frame sync or output flags 7 4 2 16 CRB ESSI Transmit 0 Enable TEO Bit 16 The TEO bit enables the transfer of data from TX1 to Transmit Shift Register 0 TEO is functional when the ESSI is in either Synchronous or Asynchronous mode When is set and a frame sync is detected the transmitter 0 is enabled for that frame When TEO is cleared transmitter 0 is disabled after completing transmission of data currently in the ESSI Transmit Shift Register The STD output is tri stated and any data present in will not be transmitted i e data be written to with cleared the TDE bit is cleared but data will not be transferred to the Transmit Shift Register 0 The TEO bit is cleared by either a hardware reset signal or a software reset instruction The On demand mode transmit enable sequence can be the same as the Normal mode or TEO can be left enabled Note Transmitter 0 is the only transmitter that can operate in Asynchronous mode SYN 0 does not affect the generation of frame sync or output flags Tabl
346. ou XY 9 XL uo uo uo ui uo 0 Su S 9 ejep Aelod 3201 0 151 1 15 UHA 0 Su S 1A Su S 4 Su S 4 Figure D 13 ESSI Control Register CRB D 27 DSP56303UM AD MOTOROLA PROGRAMMING REFERENCE Application Date Programmer Sheet 3 of 4 Serial Input Flag 0 If SCDO 0 SYN 1 amp TE1 0 latch SCO on FS Serial Input Flag 1 If SCD1 0 SYN 1 amp TE2 0 latch SCO on FS Transmit Frame Sync 0 Sync Inactive 1 Sync Active Receive Frame Sync 0 Wait 1 Frame Sync Occurred Transmitter Underrun Error Flag 0 1 Error Receiver Overrun Error Flag 0 OK 1 Error Transmit Data Register Empty 0 1 Write Receive Data Register Full 0 1 Read 23 RDF TOE ROE TUE RFS TES 1 1 0 SSI Status Register SSISRx 0 Loo ESSI1 FFFFA7 Read eed SSI Status Bits Reserved program as 0 Figure D 14 ESSI Status Register SSISR D 28 DSP56303UM AD MOTOROLA PROGRAMMING REFERENCE Application Date Programmer 5 5 SSI Tra
347. pe State During Reset or Stop Signal Description HA1 9 Input Input Input or Output Discon nected Internally Host Address Input 1 When the 108 is programmed to interface a non multiplexed host bus and the HI function is selected this signal is line 1 of the Host Address HA1 input bus Host Address 8 When 08 is programmed to interface a multiplexed host bus and the HI function is selected this signal is line 8 of the Host Address HA8 input bus Port B 9 When 08 is configured as GPIO through the HPCR this signal is individually programmed as an input or output through the HDDR This input is 5 V tolerant This pin is electrically disconnected internally during Stop mode HA2 HA9 PB10 Input Input Input or Output Discon nected Internally Host Address Input 2 When the 108 is programmed to interface a non multiplexed host bus and the HI function is selected this signal is line 2 of the Host Address HA2 input bus Host Address 9 When HI08 is programmed to interface a multiplexed host bus and the HI function is selected this signal is line 9 of the Host Address 9 input bus Port B 10 When HI08 is configured as GPIO through the HPCR this signal is individually programmed as an input or output through the HDDR This input is 5 V tolerant This pin is electrically disconnected internally during Stop mo
348. pecified starting address TL GF POP P POYOF SOP OP OP P T F Pf y 45 34 MC MB MA 101 then it loads the program RAM from the Host Interface programmed to operate in the 11 non multiplexed mode The HOST 11 bootstrap code expects to read a 24 bit word specifying the numbe to start loading the word to be loaded T contiguous PRAM memo r of program words a 24 bit word specifying the address program words and then a 24 bit word for each program he program words will be stored in ry locations starting at the specified starting address After reading the program words program execution starts from the same address where loading started Ihe Host Interface bootstrap load program may be stopped by setting the Host Flag 0 HF0 This will start execution of the loaded program from the specified starting address EES fE YY EME EEE P P MC MB MA 110 then it loads the program RAM from the Host Interface programmed to operate in the 8051 multiplexed bus mode in double strobe pin configuration he HOS he HOS 8051 bootst 8051 bootst rap code expects a
349. producing an odd number If the receiver counts an even number of 1s an error in transmission has occurred When even parity is selected an even number must result from the 8 8 DSP56303UM AD MOTOROLA Serial Communication Interface SCI SCI Programming Model calculation performed at both ends of the line or an error in transmission has occurred The word select bits are cleared by hardware and software reset 8 3 1 2 SCR SCI Shift Direction SSFTD Bit 3 The SSFTD bit determines the order in which the SCI Data Shift Registers shift data in or out MSB first when set LSB first when cleared The parity and data type bits do not change their position in the frame and remain adjacent to the stop bit SSFTD is cleared by hardware and software reset 8 3 1 3 SCR Send Break SBK Bit 4 A break is an all zero word frame a start bit 0 characters of all 05 including any parity and a stop bit 0 1 ten or eleven 05 depending on the mode selected If SBK is set and then cleared the transmitter completes transmission of the current frame sends ten or eleven 0s depending on WDS mode and reverts to idle or sending data If SBK remains set the transmitter continually sends whole frames of Os ten or eleven bits with no stop bit At the completion of the break code the transmitter sends at least one high set bit before transmitting any data to guarantee recognition of a valid start bit Break can be used to signal an unusual condit
350. put flag When SCD1 is cleared SC1 is an input flag When programmed as input flags the value of the SC 1 0 bits are latched at the same time as the first bit of the receive data word is sampled Once the input has been latched the signal on the input flag pin SCO and SC1 can change without affecting the input flag The value of SC 1 0 does not change until the first bit of the next data word is received When the received data word is latched by RX the latched values of SC 1 0 are latched by the SSISR IF 1 0 bits respectively and can be read by software MOTOROLA DSP56303UM AD 7 43 Enhanced Synchronous Serial Interface ESSI GPIO Pins and Registers When programed as output flags the value of the SC 1 0 bits is taken from the value of the OF 1 0 bits The value of the OF 1 0 bits is latched when the contents of TX are transferred to the Transmit Shift Register The value on SC 1 0 is stable from the time the first bit of the transmit data word is transmitted until the first bit of the next transmit data word is transmitted The OF 1 0 values can be set directly by software This allows the DSP56303 to control data transmission by indirectly controlling the value of the SC 1 0 flags 7 6 GPIO PINS AND REGISTERS The GPIO functionality of an ESSI port C D is controlled by three registers Port Control Register PCRC PCRD Port Direction Register PRRC PRRD and Port Data Register PDRC PDRD 7 6 1 Port Control Reg
351. put used by both the transmitter and receiver in Synchronous modes or by the transmitter in Asynchronous modes Although an external serial clock can be independent of and asynchronous to the DSP system clock it must exceed the minimum clock cycle time of 6T i e the system clock frequency must be at least three times the external ESSI clock frequency The ESSI needs at least three DSP phases inside each half of the serial clock Port D 3 The default configuration following reset is GPIO input PD3 When configured as PD3 signal direction is controlled through PRRD The signal can be configured as an ESSI signal SCK1 through PCRD This input is 5 V tolerant SRD1 PD4 Input Output Input or Output Input Discon nected Internally Serial Receive Data SRD1 receives serial data and transfers the data to the ESSI Receive Shift Register SRD1 is an input when data is being received Port D 4 The default configuration following reset is GPIO input When configured as PD4 signal direction is controlled through PRRD The signal can be configured as an ESSI signal SRD1 through PCRD This input is 5 V tolerant MOTOROLA DSP56303UM AD 2 31 Signal Connection Descriptions Serial Communication Interface SCI Table 2 13 Enhanced Synchronous Serial Interface 1 ESSI1 Continued State During PD5 Input Or Output Signal Name Type Sig
352. r Load Register TLRO FFFF8E Write Only TLR1 FFFF8A Write Only TLR2 FFFF86 Write Only Reset 000000 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Value Compared to Counter Value Timer Compare Register TCPRO FFFF8D Read Write TCPR1 FFFF89 Read Write TCPR2 FFFF85 Read Write Reset 000000 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Timer Count Value Timer Count Register TCRO FFFF8C Read Only TCR1 FFFF88 Read Only TCR2 FFFF84 Read Only Reset 000000 Figure D 21 Timer Load Compare Count Registers TLR TCPR TCR MOTOROLA DSP56303UM AD D 35 PROGRAMMING REFERENCE Application Date Programmer Sheet 1 of 4 G Port 108 Host Data 15 14 1 1 3 12 0 9 8 7 6 5 4 3 2 1 0 Direction Register DR15 DR14 DR13 DR12 DR10 DR8 DR7 DR5 DR3 DR2 DR1 HDDR X FFFFC8 Reset 0 DRx 1 is Output DRx 0 gt HIkx is Input Host Data 15 14 13 12111 10 9 8 7 6 5 4 3 2 1 0 s X FFFFC9 Write Reset Undefined DRx holds value of corresponding 108 GPIO pin Function depends on HDDR Figure D 22 Host Data Direction and Host Data Registers HDDR HDR D 36 DSP56303UM AD MOTOROLA PROGRAMMING REFERENCE Application Date Programmer Sheet 2 of 4 GPIO Port C 5510 Port C Control Register H PCRC H X SFFFFB ReadWre Reset 1 Port Pin configured as ES
353. r and toggling the TIO pin To generate output signals with a delay of X clock cycles between toggles the TLR value should be set to X 2 and the TRM bit should be set This process is repeated until the timer is disabled i e TE is cleared If the counter overflows the TOF bit is set and if TOIE is set an overflow interrupt is generated The counter contents can be read at any time by reading the TCR MOTOROLA DSP56303UM AD 9 19 Triple Timer Module Timer Modes of Operation 9 4 1 4 Timer Event Counter Mode 3 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO TIO Clock KIND NAME 0 0 1 1 Input External 3 Timer Event Counter In this mode the timer counts external events and issues an interrupt when a preset number of events is counted Set the TE bit to clear the counter and enable the timer The value the timer is to count is loaded into the TPCR The counter is loaded with the TLR value when the first timer clock signal is received The timer clock signal can be taken from either the TIO input pin or the prescaler clock output Each subsequent clock signal increments the counter If an external clock is used it must be internally synchronized to the internal clock and its frequency must be less than the DSP56303 internal operating frequency divided by 4 The value of the INV bit in the TCSR determines whether low to high 0 to 1 transitions or high to low 1 to 0 transitions
354. r store data at their maximum programmed I O instruction rate without testing the handshake flags for each transfer If full handshake is not needed the host processor can treat the DSP56303 as a fast device and data can be transferred between the host processor and the DSP56303 at the fastest host processor data rate One of the most innovative features of the Host Interface is the host command feature With this feature the host processor can issue vectored interrupt requests to the DSP56303 The host may select any of 128 DSP interrupt routines for execution by writing a vector address register in the HI08 This flexibility allows the host processor to execute up to 128 pre programmed functions inside the DSP56303 For example use of the DSP56303 host interrupts can allow the host processor to read or write DSP registers X Y or program memory locations force interrupt handlers e g SSI SCI IROA IROB interrupt routines and perform control and debugging operations Note Users should be aware that when the DSP enters the Stop mode the 108 pins are electrically disconnected internally thus disabling the HI08 until the core leaves Stop mode While the 108 configuration remains unchanged while in Stop mode the core cannot be restarted via the HI08 interface Do not issue a STOP command to the DSP via the HI08 unless some other mechanism for exiting Stop mode is provided MOTOROLA DSP56303UM AD 6 21 Host Interface HI08 H
355. ram RAM to the X data RAM by setting the MS bit for a total of 3 K 3 6 DSP56303UM AD MOTOROLA Memory Configuration Memory Configurations 3 2 3 On Chip Y Data Memory Y Data RAM The on chip Y data RAM consists of 24 bit wide high speed internal Static RAM occupying the lowest 2 K default or 3 K locations in the Y memory space The size of the Y data RAM is dependent on the setting of the MS bit default MS is cleared The Y data RAM default organization is eight banks of 256 2 K 24 bit words Four banks of RAM may be switched from the Program RAM to the Y data RAM by setting the MS bit for a total of 3 K 3 2 4 Bootstrap ROM The bootstrap code is accessed at addresses FF0000 to FFFOBF 192 words in program memory space The bootstrap ROM can not be accessed in 16 bit Address Compatibility mode See Appendix A for a complete listing of the bootstrap code 3 MEMORY CONFIGURATIONS Memory configuration determines the size and address range for addressable memory and the amount of memory allocated to Program RAM data RAM and the Instruction Cache 3 3 1 Memory Space Configurations The memory space configurations are listed in Table 3 3 Table 3 3 Memory Space Configurations for the DSP56303 SC Bit Addressable Number of Setting Memoty Size 5 Address Bits 0 16 M words 000000 24 SFFFFFF 1 64 K words 0000 FFFF 16 MOTOROLA DSP56303UM AD 3 7 Memory Configuration
356. rating modes is given in Section 9 4 Timer Modes of Operation on page 9 16 The TC bits are cleared by a hardware RESET signal or a software RESET instruction Note If the clock is external the counter is incremented by the transitions on the TIO pin The external clock is internally synchronized to the internal clock and its frequency should be lower than the internal operating frequency divided by 4 CLK 4 Note To ensure proper operation the TC 3 0 bits should be changed only when the timer is disabled when the TE bit in the TCSR has been cleared Table 9 2 Timer Control Bits Bit Settings Mode Characteristics Mode TC3 TC2 TC1 TCO Mode Function TIO Clock Number 0 0 0 0 0 Timer and GPIO GPIO Internal 0 0 0 1 1 Timer Pulse Output Internal 0 0 1 0 2 Timer Toggle Output Internal 0 0 1 1 3 Event Counter Input External 0 1 0 0 4 Input Width Input Internal Measurement 0 1 0 1 5 Input Period Input Internal Measurement 0 1 1 0 6 Capture Event Input Internal 9 10 DSP56303UM AD MOTOROLA Table 9 2 Timer Control Continued Triple Timer Module Triple Timer Module Programming Model 9 3 4 5 Inverter INV Bit 8 The Inverter INV bit affects the polarity definition of the incoming signal on the TIO pin when TIO is programmed as input and affects the polarity of the output pulse genera
357. rced or received on the clock pin SCLK eliminating the need for an external inverter When SCKP is cleared the clock polarity is positive when SCKP is set the clock polarity is negative In the Synchronous mode positive polarity means that the clock is normally positive and transitions negative during valid data Negative polarity means that the clock is normally negative and transitions positive during valid data In the Asynchronous 8 12 DSP56303UM AD MOTOROLA Serial Communication Interface SCI SCI Programming Model mode positive polarity means that the rising edge of the clock occurs in the center of the period that data is valid Negative polarity means that the falling edge of the clock occurs during the center of the period that data is valid SCKP is cleared on hardware and software reset 8 3 1 15 SCR SCI Receive with Exception Interrupt Enable REIE Bit 16 The REIE bit is set to enable the SCI Receive Data with Exception interrupt If is cleared the Receive Data with Exception interrupt is disabled If both REIE and are set and PE FE and OR are not all cleared the SCI requests SCI Receive Data with Exception interrupt from the interrupt controller REIE is cleared by hardware and software reset 8 3 2 SCI Status Register SSR The SSR is a 24 bit read only register used by the DSP to determine the status of the SCI The status bits are described in the following paragraphs 8 3 2 1 SSR Trans
358. re 10 7 Breakpoint Control Register OBCR 10 5 6 1 Memory Breakpoint Select MBSO MBS1 Bits 0 1 The Memory Breakpoint Select bits 50 51 enable memory breakpoints 0 and 1 allowing them to occur when a memory access is performed on X space See Table 10 6 for the definition of the MBS0 MBSI bits Table 10 6 Memory Breakpoint 0 and 1 Select Table MBS1 MBSO Description 0 0 Reserved 0 1 Breakpoint on P access 1 0 Breakpoint on X access 1 1 Breakpoint on Y access 10 5 6 2 Breakpoint 0 Read Write Select RW00 RWO 1 Bits 2 3 The Breakpoint 0 Read Write Select bits RW00 RW01 define the memory breakpoints 0 to occur when a memory address accesses is performed for read write or both See Table 10 7 for the definition of the RW00 RW01 bits 10 12 DSP56303UM AD MOTOROLA On Chip Emulation Module OnCE Memory Breakpoint Logic Table 10 7 Breakpoint 0 Read Write Select Table RW01 RW00 Description 0 0 Breakpoint disabled 0 1 Breakpoint on write access 1 0 Breakpoint on read access 1 1 Breakpoint on read or write access 10 5 6 3 Breakpoint 0 Condition Code Select CC00 CC01 Bits 4 5 The Breakpoint 0 Condition Code Select bits CC00 CC01 define the condition of the comparison between the current Memory Address OMALO and the Memory Limit Register 0 OMLRO See Table 10 8 for the definition of the CC00 CCO1 bits Table 10 8 Breakpoint 0 Co
359. reamble of ten or eleven consecutive 1s depending on WDS This procedure gives the programmer a convenient way to ensure that the line goes idle before starting a new message To force this separation of messages by the minimum idle line time the following sequence is recommended 1 Write the last byte of the first message to STX 2 Wait for TDRE to go high indicating the last byte has been transferred to the Transmit Shift Register 3 Clear TE and set TE This queues an idle line preamble to follow immediately the transmission of the last character of the message including the stop bit 4 Write the first byte of the second message to STX In this sequence if the first byte of the second message is not transferred to STX prior to the finish of the preamble transmission the transmit data line marks idle until STX is finally written 8 3 1 9 SCR Idle Line Interrupt Enable ILIE Bit 10 When ILIE is set the SCI interrupt occurs when IDLE SCI Status Register Bit 3 is set When ILIE is cleared the IDLE interrupt is disabled ILIE is cleared by hardware and software reset An internal flag the Shift Register Idle Interrupt SRIINT flag is the interrupt request to the interrupt controller SRIINT is not directly accessible to the user When a valid start bit has been received an idle interrupt is generated if both IDLE and ILIE are set The idle interrupt acknowledge from the interrupt controller clears this interrupt request
360. rial Control 0 Direction bit SCD0 7 16 serial control 0 signal SCO 7 6 7 8 serial control 0 signal 5 00 2 25 DSP56303UM AD l 11 serial control 0 signal SC10 2 29 Serial Control 1 Direction bit SCD1 7 16 serial control 1 signal 5 01 2 25 serial control 1 signal SC1 7 7 serial control 1 signal SC11 2 29 Serial Control 2 Direction bit SCD2 7 16 serial control 2 signal 5 02 2 26 serial control 2 signal SC12 2 30 Serial Input Flag 0 bit IFO 7 28 Serial Input Flag 1 bit IF1 7 28 Serial Output Flag bits OFO OF1 7 15 serial protocol in OnCE module 10 23 serial receive data signal RXD 2 33 Serial Receive Data signal SRD 7 4 serial receive data signal SRDO 2 27 serial receive data signal SRD1 2 31 Serial Transmit Data signal STD 7 4 serial transmit data signal 5100 2 28 serial transmit data signal STD1 2 32 serial transmit data signal 2 33 SHFD bit 7 17 Shift Direction bit SHFD 7 17 signal groupings 2 3 2 4 signals 2 3 Sixteen bit Compatibility 3 3 Size register 52 1 11 Software Debug Occurrence bit SWO 10 8 SP 1 11 SR register 1 10 SRAM interfacing 1 13 SRD signal 7 4 SRDO 2 27 SRD1 2 31 SRX read as SRXL SRXM SRXH 8 19 SRX register 8 19 SS 1 11 SSC1 bit 7 14 SSFTD bit 8 9 SSISR register 7 27 bit 0 Serial Input Flag 0 bit 7 28 bit 1 Serial Input Flag 1 bit IF1 7 28 bit 2 Transmit Frame Sync Flag bit TFS 7 28 bit 3 Receive Frame Sync Flag bit RFS
361. riority Levels The DSP56303 has a four level interrupt priority structure Each interrupt has two Interrupt Priority Level bits IPL 1 0 that determine its interrupt priority level Level 0 is the lowest priority level Level is the highest level priority and is non maskable Table 4 3 defines the IPL bits Table 4 3 Interrupt Priority Level Bits IPL bit its Interrupts Interrupts Interrupt Priority Enabled Masked Level There are two interrupt priority registers in the DSP56303 The IPR C is dedicated to DSP56300 core interrupt sources and IPR P is dedicated to DSP56303 peripheral 4 12 DSP56303UM AD MOTOROLA Core Configuration Interrupt Sources and Priorities interrupt sources IPR C is shown on Figure 4 1 on page 4 13and IPR P is shown in Figure 4 2 on page 4 13 11 10 5 9 8 7 6 5 4 3 2 1 0 21 2 0 19 18 17 1 23 22 6 15 14 13 12 DMAO IPL IPL DMA2 IPL DMAS IPL DMA4 IPL DMAS IPL Figure 4 1 Interrupt Priority Register C IPR C X FFFFFF 9 8 7 6 5 4 3 2 1 0 08 IPL ESSIO IPL ESSI1 IPL SCI IPL TRIPLE TIMER IPL reserved 23 22 21 20 19 18 17 16 15 14 13 12 reserved Figure 4 2 Interrupt Priority Register P IPR P X FFFFFE MOTOROLA DSP56303UM AD 4 13 Core Configuration Interrupt Sources and Priorities 4 4 3 Interrupt Source Priorities within an IP
362. rnal data bus 2 8 external interrupt request A signal 2 15 external interrupt request B signal 2 15 external interrupt request C signal 2 16 external interrupt request D signal 2 16 external memory expansion port 2 8 EXTEST instruction 11 8 F FE bit 8 15 Frame Rate Divider Control bits 4 7 12 Frame Sync Length bits FSL1 FSLO 7 17 Frame Sync Polarity bit FSP 7 18 Frame Sync Relative Timing bit FSR 7 17 frame sync selection ESSI 7 41 Framing Error Flag bit FE 8 15 frequency operation 1 7 FSL1 FSLO bits 7 17 FSP bit 7 18 FSR bit 7 17 G general purpose input output GPIO 2 34 Global Data Bus 1 13 GO Command bit GO 10 6 GPIO 1 15 2 4 2 34 on HI08 6 30 GPIO ESSIO Port C 5 3 GPIO 55 Port D 5 4 GPIO HI08 Port B 5 3 GPIO SCI Port E 5 4 GPIO Timer 5 4 GPIO functionality DSP56303UM AD l 3 on ESSI 7 44 ground 2 3 2 6 address bus 2 6 bus control 2 6 data bus 2 6 ESSI 2 6 host interface 2 6 PLL 2 6 quiet 2 6 SCI 2 6 timer 2 6 H 7 signals 2 18 HAO signal 2 18 HA1 signal 2 19 HA2 signal 2 19 signal 2 19 HA10 signal 2 22 HA signal 2 19 bit 6 13 bit 6 13 HADO0 HADY signals 2 18 HAEN bit 6 14 HAP bit 6 16 hardware stack 1 10 HAS HAS 2 18 HASP bit 6 15 HBAR register 6 12 bits 0 7 Base Address bits BA3 BA10 6 12 reserved bits bits 5 15 6 12 HC bit 6 25 HCIE bit 6 10 HCP bit 6 11 HCR register 6 9 6 10 bit 0
363. rocessor MOD D A Reset Vector Description 0000 C00000 mode X001 FF0000 Bootstrap from byte wide memory X010 FF0000 Bootstrap through SCI X011 Reserved X100 FF0000 Host Bootstrap PCI mode 32 bit wide X101 FF0000 Host Bootstrap 16 bit wide UB mode ISA X110 FF0000 Host Bootstrap 8 bit wide UB mode dbl strb X111 FF0000 Host Bootstrap 8 bit wide UB mode sgl strb 1000 008000 Expanded mode External Bus Disable Stop Delay Memory Switch Mode Core DMA Priority 1 0 Core DMA Priority Core vs DMA Priority DMA accesses gt Core DMA accesses Core DMA accesses lt Core Burst Mode Enable TA Synchronize Select Bus Release Timing Stack Extension Space Select Extended Stack Underflow Flag Extended Stack Overflow Flag Extended Stack Wrap Flag Stack Extension Enable oe 23 22 21 20 19 18 17 16115 14 13 12 1110 9 8 7 6 5 413 2 1 0 5 Je TAS BE cpPi cpPo 5 SD EBD MC M8 MA ooo ool 1 19 LI Se S System Stack Control Extended Chip Operating Chip Operating Mode Status Register SCS Mode Register COM Register COM Operating Mode Register OMR x Reserved Program as 0 Read Write 00030 Latched from levels on Mode pins Figure D 2 Operating Mode Register ERCR D 16 DSP56303UM AD MOTO
364. rrupt Enable SCRIE 11 SCI Receive Interrupt Enable SCTIE EQU 12 SCI Transmit Interrupt Enable 1 EQU 13 Timer Interrupt Enable TIR EQU 14 Timer Interrupt Rate SCKP EQU 15 SCI Clock Polarity 1 EQU 16 SCI Error Interrupt Enable REIE SCI Status Register Bit Flags 1 EQU 0 Transmitter Empty 1 EQU 1 Transmit Data Register Empty EQU 2 Receive Data Register Full IDLE EQU 3 Idle Line Flag LO EQU 4 Overrun Error Flag 1 PE EQU 5 Parity Error FE EQU 6 Framing Error Flag R8 EQU 7 Received Bit 8 R8 Address SCI Clock Control Register M CD EQU SFFF Clock Divider Mask CD0 CD11 M COD EQU 12 Clock Out Divider M SCP EQU 13 Clock Prescaler M RCM EQU 14 Receive Clock Mode Source Bit M TCM EQU 15 Transmit Clock Source Bit MOTOROLA DSP56303UM AD B 5 Equates B 4 ENHANCED SYNCHRONOUS SERIAL INTERFACE ESSI EQUATES EQUATES for Synchronous Serial Interface SST Register Addresses 5510 1 TXOO 5510 Transmit Data Register 0 1 1 EQU SFFFFBB SSIO Transmit Data Register 1 1 2 EQU SFFFFBA SSIO Transmit Data Register 2 1 TS
365. rupt ESSIO TX Data Interrupt ESSI1 RX Data With Exception Interrupt 55 RX Data Interrupt ESSI1 Receive Last Slot Interrupt 55 TX Data With Exception Interrupt ESSI1 Transmit Last Slot Interrupt ESSI1 TX Data Interrupt SCI Receive Data With Exception Interrupt SCI Receive Data SCI Transmit Data SCI Idle Line SCI Timer TIMERO Overflow Interrupt TIMERO Compare Interrupt TIMER1 Overflow Interrupt TIMER1 Compare Interrupt MOTOROLA DSP56303UM AD 4 15 Core Configuration DMA Request Sources Table 4 4 Interrupt Source Priorities within an IPL Continued Priority Interrupt Source TIMER2 Overflow Interrupt Lowest TIMER2 Compare Interrupt 4 5 DMA REQUEST SOURCES The DMA Request Source bits DRS 4 0 in the DMA Control Status registers encode the source of DMA requests used to trigger DMA transfers The DMA request sources may be internal peripherals or external devices requesting service through the IROA IROB or pins Table 4 5 describes the meanings of the DRS bits Table 4 5 DMA Request Sources EMA pits Requesting Device T 0 00000 External pin 00001 External IRQB pin 00010 External IRQC pin 00011 External IRQD pin 00100 Transfer Done from DMA channel 0 00101 Transfer Done from DMA channel 1 00110 Transfer D
366. s Register D 34 Timer Load Compare Count Registers TLR TCPR TCR 0 35 Host Data Direction and Host Data Registers HDDR HDR D 36 Port C Registers PCRC PRRC D 37 Port D Registers PCRD PDRD D 38 Port E Registers PCRE PRRE PDRE D 39 DSP56303UM AD MOTOROLA 1 1 1 2 Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 2 7 Table 2 8 Table 2 9 Table 2 10 Table 2 11 Table 2 12 Table 2 13 Table 2 14 Table 2 15 Table 2 16 Table 3 1 MOTOROLA LIST OF TABLES High True Low True Signal Conventions 1 5 On Chip 1 12 DSP56303 Functional Signal Groupings 2 3 bth eee bet ne eee NES 2 5 6 E BE Eoi aUe Desi dota ius 2 6 eoque Ru spo dear heehee Steed 2 7 Phase Lock Loop 50 5 2 7 External Address Bus 2 9 External Data Bus 5 2 9 External Bus Control 510 2 10 Interrupt and Mode 2 14 Host Port Usage 2 17 Host Interface
367. s Register SSR 8 13 SSH Transmitter Empty BitO 8 13 SSH Transmit Data Register Empty TDRE Bit 8 13 SSR Receive Data Register Full RDRF Bit2 8 14 SSR Line Flag IDLE Bit3 8 14 SSR Overrun Error OR Bit4 8 14 SSR Parity Error PE 5 8 14 SSR Framing Error Flag FE Bit6 8 15 SSR Received Bit 8 R8 Address Bit 7 8 15 SCI Clock Control Register SCCR 8 15 SCCR Clock Divider CD 11 0 Bits 11 0 8 16 SCCR Clock Out Divider COD Bit12 8 16 MOTOROLA DSP56303UM AD ix 8 3 3 3 SCCR SCI Clock Prescaler SCP Bit13 8 17 8 3 3 4 SCCR Receive Clock Mode Source Bit RCM Bit 14 8 17 8 3 3 5 SCCR Transmit Clock Source Bit TCM Bit15 8 18 8 3 4 SCI Data Registers 8 18 8 3 4 1 SCI Receive Registers SRX 8 19 8 3 4 2 SCI Transmit Registers 8 20 8 4 OPERATING MODES ll etr b 8 21 8 4 1 SGIAfter Reset uoc uate eis ed eS 8 22 8 4 2 SCI Initialization 8 24 8 4 3 SCI Initialization Example 8 25 8 4 4 Preamble Break and Data Transmission Priority 8 26 8 4 5 SGI EXCEPNONS as edad I or es CIE 8 26 8 5 GPIO PINS AND REGISTERS 8 27 8 5 1 Port E Control Register P
368. s a program RAM segment from consecutive byte wide P memory locations starting at P D00000 bits 7 0 31 wait states he EPROM bootstrap code expect S to read 3 bytes The memory is selected by the Address Attribute 1 and is accessed with specifying the number of program words 3 bytes specifying the address to start loading the program words and then 3 bytes for each program word to be loaded The number of words the starting address and the program words are read least significant byte first followed by the mid and then by the most significant byte The program words will be condensed into 24 bit words and stored in contiguous PRAM memory locations starting at the specified starting After reading the program words program execution starts from the same address where loading started TOE PEE ELE p OR UE OP OR TEE EL SEE ELE LE EELS EEO 48 If MC MB MA 010 then it loads the program RAM from the SCI interface The number of program words to be loaded and the starting address must be specified The SCI bootstrap code expects to receive 3 bytes specifying the number of program words 3 bytes specifying the address to start loading the program words and then 3 bytes for each program word to be loaded The number of words the starting add program words are received leas t si
369. s an ESSI signal SC02 through PCRC This input is 5 V tolerant 2 26 DSP56303UM AD MOTOROLA Signal Connection Descriptions Enhanced Synchronous Serial Interface 0 ESSIO Table 2 12 Enhanced Synchronous Serial Interface 0 ESSIO Continued Signal Name Type State During Reset Stop Signal Description SCKO PC3 Input Output Input or Output Input Discon nected Internally Serial Clock SCK0 is a bidirectional Schmitt trigger input signal providing the serial bit rate clock for the ESSI interface The 5 is a clock input or output used by both the transmitter and receiver in Synchronous modes or by the transmitter in Asynchronous modes Although an external serial clock can be independent of and asynchronous to the DSP system clock it must exceed the minimum clock cycle time of 6 T i e the system clock frequency must be at least three times the external ESSI clock frequency The ESSI needs at least three DSP phases inside each half of the serial clock Port C 3 The default configuration following reset is GPIO input PC3 When configured as PC3 signal direction is controlled through PRRC The signal can be configured as an ESSI signal SCKO through PCRC This input is 5 V tolerant SRDO PC4 Input Output Input or Output Input Discon nected Internally Serial Receive Data SRD O receives serial data and transfer
370. s connections 2 6 DSP56303UM AD MOTOROLA Signal Connection Descriptions Clock Table 2 3 Grounds Continued Ground Name Description Note These designations are package dependent Some packages connect all GND inputs except GNDp and GNDp to each other internally On those packages all ground connections except GNDp and GNDp are labeled GND The number of connections indicated in this table are minimum values the total GND connections are package dependent 2 4 CLOCK Table 2 4 Clock Signals Sienal State 5 During Signal Description Name Reset EXTAL Input External Clock Crystal Input EXTAL interfaces the internal crystal oscillator input to an external crystal or an external clock XTAL Output Chip driven Crystal Output XTAL connects the internal crystal oscillator output to an external crystal If an external clock is used leave XTAL unconnected 2 5 PHASE LOCK LOOP PLL Table 2 5 Phase Lock Loop Signals Signal 5 During Signal Description Name Reset PCAP Input Input PLL Capacitor PCAP is an input connecting an off chip capacitor to the PLL filter Connect one capacitor terminal to PCAP and the other terminal to Vccp If the PLL is not used PCAP may be tied to Vcc GND or left floating MOTOROLA DSP56303UM AD 2 7 Signal Connection Descriptions External Memory Expansion Port Por
371. s disabled when the TE bit is cleared Which source clock is used for the prescaler is determined by the PS 1 0 bits of the TPLR A timer can be clocked by a prescaler clock derived from the TIO of another timer 9 3 4 11 Timer Overflow Flag TOF Bit 20 The Timer Overflow Flag TOF bit is set to indicate that counter overflow has occurred This bit is cleared by writing a 1 to the TOF bit Writing a 0 to the TOF bit has no effect The bit is also cleared when the timer overflow interrupt is serviced The TOF bit is cleared by a hardware RESET signal a software RESET instruction the STOP instruction or by clearing the TE bit to disable the timer 9 3 4 12 Timer Compare Flag TCF Bit 21 The Timer Compare Flag TCF bit is set to indicate that the event count is complete In the Timer PWM and Watchdog modes the TCF bit is set when N M 1 events have been counted N is the value in the compare register and M is the TLR value In the Measurement modes the TCF bit is set when the measurement has been completed The bit is cleared by writing a 1 into the TCF bit Writing a 0 into the TCF bit has no effect The bit is also cleared when the timer compare interrupt is serviced The TCF bit is cleared by a hardware RESET signal a software RESET instruction the STOP instruction or by clearing the TE bit to disable the timer Note The TOF and TCF bits are cleared by writing a 1 to the specific bit In order to assure that on
372. s from a user interface program that communicates with the user MOTOROLA DSP56303UM AD 10 23 On Chip Emulation Module Examples of Using the OnCE 10 12 EXAMPLES OF USING THE OnCE Following are some examples of debugging procedures All these examples assume that the DSP is the only device in the JTAG chain If there is more than one device in the chain additional DSPs or other devices the other devices can be forced to execute the JTAG BYPASS instruction such as their effect in the serial stream will be one bit per additional device The events such as select DR select IR update DR and shift DR refer to bringing JTAG TAP in the corresponding state Please refer to Section 11 JTAG for a detailed description of the JTAG protocol 10 12 1 Checking Whether the Chip has Entered the Debug Mode There are two methods to verify that the chip has entered the Debug mode 1 Every time the chip enters the Debug mode a pulse is generated on the DE pin A pulse is also generated every time the chip acknowledges the execution of an instruction while in Debug mode An external command controller can connect the DE line to an interrupt pin in order to sense the acknowledge 2 Anexternal command controller can poll the JTAG instruction shift register for the status bits OS 1 0 When the chip is in Debug mode these bits are set to the value 11 Note In the following paragraphs the ACK notation denotes the operation performed by the co
373. s mode the 108 is configured to interface with an ISA bus or with the memory expansion port of a master DSP5630X processor If the host processor sets Host Flag 0 the 108 Interface Control Register HCR while writing the initialization program the bootstrap program stops loading instructions jumps to the starting address specified and executes the loaded program MOTOROLA DSP56303UM AD 4 7 Core Configuration Bootstrap Program 4 3 6 Mode 5 Bootstrap Through HI08 in HC11 Non Multiplexed Mode Reset Mode MODD MODB Description Vector 5 1 1 0 1 0000 108 Bootstrap in non multiplexed The bootstrap program sets the Host Interface to interface with the Motorola HC11 microcontroller If the host processor sets Host Flag 0 in the 108 Interface Control Register HCR while writing the initialization program the bootstrap program stops loading instructions jumps to the starting address specified and executes the loaded program 4 3 7 Mode 6 Bootstrap Through HI08 in 8051 Multiplexed Bus Mode Reset Aa Mode MODD MODC MODB MODA Description Vector 6 1 1 1 0 0000 108 Bootstrap in 8051 multiplexed bus The bootstrap program sets the Host Interface to interface with the Intel 8051 bus If the host processor sets Host Flag 0 HFO in the 108 Interface Control Regis
374. s set the SCI TXD driver is programmed to function as an open drain output and can be wired together with other TXD pins in an appropriate bus configuration such as a master slave multidrop configuration An external pullup resistor is required on the bus When the WOMS is cleared the TXD pin uses an active internal pullup WOMS is cleared by hardware and software reset 8 3 1 7 SCR Receiver Enable RE Bit 8 When RE is set the receiver is enabled When RE is cleared the receiver is disabled and data transfer from the Receive Shift Register to the Receive Data Register SRX is inhibited If RE is cleared while a character is being received the reception of the character is completed before the receiver is disabled RE does not inhibit RDRF or receive interrupts RE is cleared by hardware and software reset 8 10 DSP56303UM AD MOTOROLA Serial Communication Interface SCI SCI Programming Model 8 3 1 8 SCR Transmitter Enable TE Bit 9 When TE is set the transmitter is enabled When TE is cleared the transmitter completes transmission of data in the SCI Transmit Data Shift Register then the serial output is forced high i e idle Data present in the SCI Transmit Data Register STX is not transmitted STX may be written and TDRE cleared but the data is not transferred into the shift register TE does not inhibit TDRE or transmit interrupts TE is cleared by hardware and software reset Setting TE causes the transmitter to send a p
375. s the data to the ESSI Receive Shift Register SRDO is an input when data is being received Port C 4 The default configuration following reset is GPIO input PC4 When configured as signal direction is controlled through PRRC The signal can be configured as an ESSI signal SRDO through PCRC This input is 5 V tolerant MOTOROLA DSP56303UM AD 2 27 Signal Connection Descriptions Enhanced Synchronous Serial Interface 0 ESSIO Table 2 12 Enhanced Synchronous Serial Interface 0 ESSIO Continued State During Signal Name Type Signal Description Reset Stop STDO Input Input Discon Serial Transmit Data STD0 is used for Output nected transmitting data from the serial Transmit Internally Shift Register 5700 is an output when data is being transmitted 5 Input Port C 5 The default configuration or following reset is GPIO input PC5 When Output configured as PC5 signal direction is controlled through PRRC The signal can be configured as an ESSI signal STD0 through PCRC This input is 5 V tolerant Note 1 The Wait processing state does not affect the signal s state 2 28 DSP56303UM AD MOTOROLA Signal Connection Descriptions Enhanced Synchronous Serial Interface 1 ESSI1 2 10 ENHANCED SYNCHRONOUS SERIAL INTERFACE 1 ESSI1 Table 2 13 Enhanced Synchronous Serial Interface 1 ESSI1 Signal Name Type State During Reset Stop Signa
376. sampled when the HAS pin is high 6 5 6 12 HPCR Host Multiplexed Bus HMUX Bit 11 If HMUX is set the HI08 latches the lower portion of a multiplexed address data bus In this mode the internal address line values of the host registers are taken from the internal latch If HMUX is cleared it indicates that the HI08 is connected to a non multiplexed type of bus The values of the address lines are then taken from the HI08 input pins 6 5 6 13 HPCR Host Dual Data Strobe HDDS Bit 12 If the HDDS bit is cleared the 108 operates in the Single Strobe Bus mode In this mode the bus has a single data strobe signal for both reads and writes If set the 108 operates in the Dual Strobe Bus mode In this mode the bus has two separate MOTOROLA DSP56303UM AD 6 15 Host Interface HI08 HI08 DSP Side Programmer s Model data strobes one for data reads the other for data writes See Figure 6 7 and Figure 6 8 for more information on the two types of buses HDS In a single strobe bus a DS data strobe signal qualifies the access while a R W Read Write signal specifies the direction of the access 0661 Figure 6 7 Single Strobe Data Write Data In HWR Write Cycle Data X Read Dataout Data Out Read Cycle In dual strobe bus there are separate HRD and HWR signals that specify the access as being a read or write access respectively HRD 0662 Figure 6 8 Dual Strobe 6 5 6 14 HPCR Host Ch
377. se They are read as 0 and should be written with 0 for future compatibility 10 6 OnCE TRACE LOGIC Using the OnCE Trace Logic execution of instructions in single or multiple steps is possible The OnCE Trace Logic causes the chip to enter the Debug mode of operation after the execution of one or more instructions and wait for OnCE commands from the debug serial port The OnCE Trace Logic block diagram is shown in Figure 10 8 End of Instruction TDI TDO Trace Counter Count 0 ISTRACE AA0708 Figure 10 8 OnCE Trace Logic Block Diagram The Trace mode has a counter associated with it so that more than one instruction can be executed before returning back to the Debug mode of operation The objective of the counter is to allow the user to take multiple instruction steps real time before entering the Debug mode This feature helps the software developer debug sections of code that do not have a normal flow or are getting hung up in infinite loops The Trace Counter also enables the user to count the number of instructions executed in a code segment MOTOROLA DSP56303UM AD 10 15 On Chip Emulation Module Methods of Entering the Debug Mode To enable the Trace mode of operation the counter is loaded with a value the program counter is set to the start location of the instruction s to be executed real time the TME bit is set in the OSCR and the DSP56300 core exits the Debug mode by executing the appropriate command issued by
378. ss data bit is cleared in the 11 bit Asynchronous Multidrop mode when any of STXL STXM or STXH is written When either STX STXL STXM or STXH or STXA is written TDRE is cleared The transfer from either STX or STXA to the Transmit Shift Register occurs automatically but not immediately when the last bit from the previous word has been shifted out that is the Transmit Shift Register is empty Like the receiver the transmitter is double buffered However a 2 to 4 serial clock cycle delay occurs between when the data is transferred from either STX or STXA to the Transmit Shift Register and when the first bit appears on the TXD pin A serial clock cycle is the time required to transmit one data bit The Transmit Shift Register is not directly addressable and a dedicated flag for this register does not exist Because of this fact and the 2 to 4 cycle delay two bytes cannot be written consecutively to STX or STXA without polling as the second byte might overwrite the first byte The TDRE flag should always be polled prior to writing STX or STXA to prevent overruns unless transmit interrupts have been enabled Either STX or STXA is usually written as part of the interrupt service routine An interrupt is generated only if TDRE is set The Transmit Shift Register is indirectly visible via the TRNE bit in the SSR 8 20 DSP56303UM AD MOTOROLA Serial Communication Interface SCI Operating Modes In the Synchronous mode data is synchronized
379. sserted Ground2 PIN False Deasserted Veo PIN True Asserted False Deasserted Ground PIN is a generic term for any pin on the chip Ground is an acceptable low voltage level See the appropriate data sheet for the range of acceptable low voltage levels typically a TTL logic low 3 Vcc is an acceptable high voltage level See the appropriate data sheet for the range of acceptable high voltage levels typically a TTL logic high Uu Pins or signals that are asserted low made active when pulled to ground Intext have an overbar for example RESET is asserted low Incode examples have a tilde in front of their names In the example on the following page line 3 refers to the 550 pin shown as 550 Sets of pins are indicated by the first and last pins in the set for instance HA1 HAS MOTOROLA DSP56303UM AD 1 5 DSP56303 Overview DSP56303 Features e Code examples are displayed in a monospaced font as shown in Example 1 1 Example 1 1 Sample Code Listing BFSET 50007 X PCC Configure line 1 MISOO MOSIO SCKO for SPI master line 2 SSO as PC3 for GPIO line 3 Hex values are indicated with a dollar sign preceding the hex value as follows FFFFFF is the X memory address for the Core Interrupt Priority Register IPR C The word reset is used in four different contexts in this manual the reset pin written as RESET the reset instruction written as RESET
380. st provide adequate external decoupling capacitors There is one input Vecs 2 ESSI SCI and Timer Power V cz is an isolated power for the ESSI SCI and timer I O drivers This input must be tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors There are two Vccs inputs Note These designations are package dependent Some packages connect all Vcc inputs except to each other internally On those packages all power input except Vccp are labeled Vcc The number of connections indicated in this table are minimum values the total Vcc connections are package dependent MOTOROLA DSP56303UM AD 2 5 Signal Connection Descriptions Ground 2 3 GROUND Table 2 3 Grounds Ground Name Description GNDp PLL Ground GNDp is an isolated ground dedicated for PLL use The connection should be provided with an extremely low impedance path to ground Vccp should be bypassed to GNDp by a 0 47 capacitor located as close as possible to the chip package There is one GNDp connection GNDp PLL Ground 1 GND pj is a ground dedicated for PLL use The connection should be provided with an extremely low impedance path to ground There is one GNDp connection GNDg 4 Quiet Ground GNDo is an isolated ground for the internal processing logic This connection must be tied externally to all other chip ground connections The
381. ster IDR DMA FFF4 FFFFF4 DMA Status Register DSTR FFFFF3 DMA Offset Register 0 DORO FFF2 FFFFF2 DMA Offset Register 1 DOR1 FFF1 FFFFF1 DMA Offset Register 2 DOR2 FFFO FFFFFO DMA Offset Register 3 DOR3 DMAO FFEF FFFFEF Source Address Register DSRO FFEE FFFFEE Destination Address Register FFED FFFFED DMA Counter FFEC FFFFEC DMA Control Register D 4 DSP56303UM AD MOTOROLA PROGRAMMING REFERENCE Table D 1 Internal I O Memory Map Continued Peripheral 2 1 2 Register Name FFEB FFFFEB DMA Source Address Register DSR1 FFEA FFFFEA Destination Address Register DDR1 FFE9 9 DMA Counter DCO1 FFE8 FFFFE8 DMA Control Register DCR1 DMA2 FFE7 FFFFE7 DMA Source Address Register DSR2 FFE6 FFFFE6 Destination Address Register DDR2 FFE5 5 DMA Counter DCO2 FFE4 FFFFE4 Control Register DCR2 DMA3 FFE3 FFFFE3 DMA Source Address Register DSR3 FFE2 FFFFE2 Destination Address Register DDR3 FFE1 FFFFE1 DMA Counter DCO3 FFEO FFFFEO DMA Control Register DCR3 DMA4 FFDF FFFFDF DMA Source Address Register DSR4 FFDE FFFFDE DMA Destination Address Register DDR4 FFDD FFFFDD DMA Counter DCO4 FFDC FFFFDC DMA Control Register DCR4
382. ster Selected Otherwise the GO bit is ignored Table 10 2 shows the definition of the GO bit Table 10 2 GO Bit Definition GO Action 0 Inactive no action taken 1 Execute instruction in PIL 10 4 1 4 Read Write Command R W Bit 7 The R W bit specifies the direction of data transfer Table 10 3 R W Bit Definition R W Action 0 Write the data associated with the command into the register specified by RS4 RSO 1 Read the data contained in the register specified by 54 50 Table 10 4 OnCE Register Select Encoding RS 4 0 Register Selected 00000 OnCE Status and Control Register OSCR 10 6 DSP56303UM AD MOTOROLA On Chip Emulation Module OnCE Controller Table 10 4 OnCE Register Select Encoding Continued RS 4 0 Register Selected 00001 Memory Breakpoint Counter OMBC 00010 Breakpoint Control Register OBCR 00011 Reserved Address 00100 Reserved Address 00101 Memory Limit Register 0 OMLRO 00110 Memory Limit Register 1 OMLRI 00111 Reserved Address 01000 Reserved Address 01001 GDB Register OGDBR 01010 PDB Register OPDBR 01011 PIL Register OPILR 01100 PDB GO TO Register for GO TO command 01101 Trace Counter OTC 01110 Reserved Address 01111 PAB Register for Fetch OPABFR 10000 PAB Register for Decode OPABDR 10001 PAB Register for Execute OPABEX 10010 Tra
383. ster path from TDI to the Bypass register and finally to TDO circumventing the BSR This instruction is used to enhance test efficiency when a component other than the DSP56300 core based device becomes the device under test When the Bypass register is selected by the current instruction the shift register stage is set to a logic 0 on the rising edge of TCK in the Capture DR controller state Therefore the first bit shifted out after selecting the Bypass register is always a logic 0 MOTOROLA DSP56303UM AD 11 11 JTAG Port DSP56300 Restrictions Shift DR 0 To TDO From TDI CLOCKDR 0115 Figure 11 5 Bypass Register 11 4 DSP56300 RESTRICTIONS The control afforded by the output enable signals using the BSR and the EXTEST instruction requires a compatible circuit board test environment to avoid device destructive configurations The user must avoid situations in which the DSP56300 core output drivers are enabled into actively driven networks In addition the EXTEST instruction can be performed only after power up or regular hardware reset while EXTAL was provided Then during the execution of EXTEST EXTAL can remain inactive There are two constraints related to the JTAG interface First the TCK input does not include an internal pullup resistor and should not be left unconnected The second constraint is to ensure that the JTAG test logic is kept transparent to the system logic by forcing the TAP into the Test Logic Reset con
384. sters SRX inFigure 8 7 SCI Transmit Data Registers STX in Figure 8 7 SCI Transmit Data Address Register STXA in Figure 8 7 The SCI contains also the GPIO functionality described in Section 8 5 The following paragraphs describe each bit in the programming model 7 6 5 4 3 2 1 0 woms RWU WAKE SBK SSFTD WDS2 WDS1 WDSO 15 14 13 12 11 10 9 8 SCKP STIR TMIE TIE ILIE 23 22 21 20 19 18 17 16 REIE 0854 Figure 8 1 SCI Control Register SCR 7 6 5 4 3 2 1 0 R8 FE PE OR IDLE RDRF TDRE TRNE 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 EE es 0855 Figure 8 2 SCI Status Register SSR CD7 CD6 CD5 CD4 CD3 CD2 CD1 CDO 15 14 13 12 11 10 9 8 TCM RCM SCP COD CD11 CD10 CD9 CD8 23 22 21 20 19 18 17 16 Reserved bit read as 0 should be written with 0 for future compatibility 0856 Figure 8 3 SCI Clock Control Register SCCR MOTOROLA DSP56303UM AD 8 5 Serial Communication Interface SCI SCI Programming Model Mode 0 8 bit Synchronous Data Shift Register Mode WDS2 WDS1 WDSO TX SSFTD 0 One Byte From Shift Register Mode 2 10 bit Asynchronous 1 Start 8 Data 1 Stop WDS2 WDS1 WDSO lt Start Stop SSFTD 0 Bit Bit Mode 4 11 bit Asynchronous 1 Start 8 Data 1 Even Parit
385. sting of the contents of the Boundary Scan Register BSR for the DSP56303 Table 11 2 DSP56303 Boundary Scan Register BSR Bit Definitions Bit 4 Cell Type Pin Name Pin Type BSR Cell Type 0 BC 1 MODA Input Data 1 _1 MODB Input Data 2 _1 MODC Input Data 3 BC_1 MODD Input Data 4 BC_6 D23 Input Output Data 5 BC_6 D22 Input Output Data 6 BC_6 D21 Input Output Data 7 BC_6 D20 Input Output Data 8 BC_6 019 Input Output Data 9 BC_6 D18 Input Output Data 10 BC_6 D17 Input Output Data 11 BC_6 D16 Input Output Data 12 BC_6 015 Input Output Data 13 BC_1 D 23 12 Control 14 BC 6 D14 Input Output Data 15 _6 D13 Input Output Data MOTOROLA DSP56303UM AD 11 13 JTAG Port DSP56303 Boundary Scan Register Table 11 2 DSP56303 Boundary Scan Register BSR Bit Definitions Continued 11 14 Bit Cell Type Pin Name Pin Type BSR Cell Type 16 BC_6 012 Input Output Data 17 _6 D11 Input Output Data 18 _6 D10 Input Output Data 19 BC_6 D9 Input Output Data 20 BC_6 D8 Input Output Data 21 BC_6 D7 Input Output Data 22 BC_6 D6 Input Output Data 23 BC_6 D5 Input Output Data 24 _6 D4 Input Output Data 25 BC_6 D3 Input Output Data 26 BC_1 D 11 0 Control 27 BC 6 D2 Input Output Data 28 BC 6 1 Input Output Data 29 BC_6 DO Input Output Data 30 BC_2 15 Output 2 Data 31 B
386. sts of three hardware blocks Program Decode Controller PDC e Program Address Generator PAG Program Interrupt Controller PIC The PDC decodes the 24 bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control The PAG contains all the hardware needed for program address generation system stack and loop control The PIC arbitrates among all interrupt requests internal interrupts as well as the five external requests IROA IROB and NMI and generates the appropriate interrupt vector address PCU features include Position Independent Code PIC support e Addressing modes optimized for DSP applications including immediate offsets e On chip instruction cache controller On chip memory expandable hardware stack Nested hardware DO loops e Fast auto return interrupts The PCU implements its functions using the following registers e PC Program Counter register e SR Status Register LA Loop Address register 1 10 DSP56303UM AD MOTOROLA DSP56303 Overview DSP56300 Core Functional Blocks e LC Loop Counter register VBA Vector Base Address register SZ Size register e SP Stack Pointer OMR Operating Mode Register SC Stack Counter register The PCU also includes a hardware System Stack 55 1 6 4 PLL and Clock Oscillator The clock generator in the DSP56300 core is composed of two main blocks the PLL whi
387. t A Table 2 5 Phase Lock Loop Signals Continued Signal State 5 During Signal Description Name Reset CLKOUT Output Chip driven Clock Output CLKOUT provides an output clock synchronized to the internal core clock phase If the PLL is enabled and both the multiplication and division factors equal one then CLKOUT is also synchronized to EXTAL If the PLL is disabled the CLKOUT frequency is half the frequency of EXTAL PINIT Input Input PLL Initial Non Maskable Interrupt During NMI assertion of RESET the value of PINIT NMI is written into the PLL Enable PEN bit of the PLL control register determining whether the PLL is enabled or disabled After RESET deassertion and during normal instruction processing the PINIT NMI Schmitt trigger input is a negative edge triggered Non Maskable Interrupt NMI request internally synchronized to CLKOUT PINIT NMI can tolerate 5 V 2 6 EXTERNAL MEMORY EXPANSION PORT PORT A When the DSP56303 enters a low power standby mode Stop or Wait it releases bus mastership and tri states the relevant Port A signals A0 A17 00 023 AA0 RASO AA3 RAS3 RD WR BB CAS BCLK BCLK If the hardware refresh of external DRAM is enabled Port A pins exit Wait state to perform the refresh and then return to the Wait state 2 8 DSP56303UM AD MOTOROLA Signal Connection Descriptions External Memory Expansion Port Port A 2 6
388. t Wide BUS ke heh ERE ee eee eek 4 7 4 3 6 Mode 5 Bootstrap Through 08 in HC11 Non Multiplexed 1981612 Serv EET 4 8 4 3 7 Mode 6 Bootstrap Through in 8051 Multiplexed Bus Modei 2258 5 rr CLE 4 8 4 3 8 Mode 7 Bootstrap Through 08 68302 68360 Bus Mode Fees Se a Eta Ae ee 4 9 4 3 9 Mode 8 Expanded 4 9 4 4 INTERRUPT SOURCES AND PRIORITIES 4 9 4 4 1 Interrupt 5 4 9 4 4 2 Interrupt Priority 4 12 4 4 3 Interrupt Source Priorities within an IPL 4 14 4 5 REQUEST SOURCES 4 16 4 6 OPERATING MODE REGISTER 4 17 4 7 PLL CONTROL REGISTER 4 18 4 7 1 PCTL PLL Multiplication Factor Bits 0 11 4 18 4 7 2 PCTL XTAL Disable Bit XTLD Bit16 4 18 4 7 3 PCTL PreDivider Factor Bits PDO PD3 Bits 20 23 4 18 4 8 AA CONTROL REGISTERS AAR1 AAR4 4 18 4 9 JTAG BOUNDARY SCAN REGISTER BSR 4 19 MOTOROLA DSP56303UM AD iii SECTION 5 GENERAL PURPOSE 5 1 5 1 INTRODUCTION 5 3 5 2 PROGRAMMING MODEL 5 3 5 2 1 Port B Pins and Registers 5 3 5 2 2 Port C Pins and Registers 5 3 5 2 3 Port D Pins and
389. te to The host interface programmer should not write to the transmit transmit byte registers byte registers Transmit register High TXH Transmit register Middle TXM or Transmit register Low TXL unless the Transmit Register Data Empty TXDE bit is set indicating that the transmit byte registers are empty This guarantees that the transmit byte registers will transfer valid data to the Host Receive HRX register Asynchronous write to The host interface programmer should change the Host Vector host vector HV register only when the Host Command bit HC is clear This will guarantee that the DSP interrupt control logic will receive a stable vector 2 8 2 Host Port Configuration The functions of the signals associated with the HI08 vary according to the programmed configuration of the interface as determined by the HI08 Port Control Register HPCR Refer to Section 6 for detailed descriptions of this and the other configuration registers used with the 08 MOTOROLA DSP56303UM AD 2 17 Signal Connection Descriptions Host Interface HI08 Table 2 11 Host Interface State Signal During Reset or Signal Description Stop H0 H7 Input Discon Host Data When 108 is programmed to Output nected interface a non multiplexed host bus and the HI Internally function is selected these signals are lines 0 7 of the data bidirectional tri state bus HADO Input Host
390. ted during the entire data transfer period This frame sync length is compatible with Motorola codecs serial peripherals that conform to the Motorola SPI serial A D and D A converters shift registers and telecommunication Pulse Code Modulation PCM serial I O MOTOROLA DSP56303UM AD 7 41 Enhanced Synchronous Serial Interface ESSI Operating Modes If the FSL1 bit is set the RX frame sync pulses active for one bit clock immediately before the data transfer period This frame sync length is compatible with Intel and National components codecs and telecommunication PCM serial I O 7 5 4 3 2 Controlling the Frame Sync Length for Multiple Devices The ability to mix frame sync lengths is useful in configuring systems in which data is received from one type of device e g codec and transmitted to a different type of device FSLO controls whether RX and TX have the same frame sync length If the FSLO bit is cleared both RX and TX have the same frame sync length e If the FSLO bit is set RX and TX have different frame sync lengths FSLO is ignored when the SYN bit is set 7 5 4 3 3 Controlling the Word Length Frame Sync Relative to the Data Word Timing The FSR bit controls the relative timing of the word length frame sync relative to the data word timing When the FSR bit is cleared the word length frame sync is generated or expected with the first bit of the data word When the FSR bit is set the word lengt
391. ted on the TIO pin when TIO is programmed as output Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Mode Function TIO Clock Number 0 1 1 1 7 Pulse Width Modulation Output Internal PWM 1 0 0 0 8 1 0 0 1 9 Watchdog Pulse Output Internal 1 0 1 0 10 Watchdog Toggle Output Internal 1 0 1 1 11 Reserved 1 1 0 0 12 Reserved 1 1 0 1 13 Reserved 1 1 1 0 14 Reserved 1 1 1 1 15 me Note 1 The GPIO function is enabled only if all of the TC 3 0 bits are 0 Table 9 3 Inverter INV Bit Operation TIO Programmed as Input TIO Programmed as Output Mode INV 0 INV 1 INV 0 INV 1 0 GPIO signal on GPIO signal on Bit written to Bit written to GPIO the TIO pin read the TIO pin GPIO put on inverted and put directly inverted pin directly on TIO pin 1 Counter is Counter is E incremented on incremented on the rising edge of the falling edge the signal from of the signal from the TIO pin the TIO pin MOTOROLA DSP56303UM AD 9 11 Triple Timer Module Triple Timer Module Programming Model Table 9 3 Inverter INV Bit Operation Continued TIO Programmed as Input TIO Programmed as Output Mode INV 0 INV 1 INV 0 INV 1 2 Counter is Counter is TCRx output put TCRx output incremented on incremented on on TIO pin inverted and put the rising edge of the fallin
392. ter HCR while writing the initialization program the bootstrap program stops loading instructions jumps to the starting address specified and executes the loaded program 4 8 DSP56303UM AD MOTOROLA Core Configuration Interrupt Sources and Priorities 4 3 8 Mode 7 Bootstrap Through HI08 in 68302 68360 Bus Mode Mode MODD Beset Description Vector 7 1 1 1 1 0000 HI08 Bootstrap in 68302 bus The bootstrap program sets the Host Interface to interface with the Motorola 68302 or 68360 bus If the host processor sets Host Flag 0 in the HCR while writing the initialization program the bootstrap program stops loading instructions jumps to the starting address specified and executes the loaded program 4 3 9 Mode 8 Expanded Mode Mode MODD MODB MODA Reset Description Vector 8 1 0 0 0 008000 Expanded mode The bootstrap ROM is bypassed and the DSP56303 starts fetching instructions beginning at address 008000 Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected 44 INTERRUPT SOURCES AND PRIORITIES Interrupt handling by the DSP56303 like that of all DSP56300 family members has been optimized for DSP applications Refer to Section 7 of the DSP56300 Family Manual The interrupt table is located in the 256 locations of program memory po
393. ter 24 Timer interrupt Timer Control DMA request TIO CLK 2 prescaler CLK AA0676 Figure 9 2 Timer Module Block Diagram 9 3 TRIPLE TIMER MODULE PROGRAMMING MODEL The programming model for the triple timer module is shown in Figure 9 3 MOTOROLA DSP56303UM AD 9 5 Triple Timer Module Triple Timer Module Programming Model Register TPLR TPLR FFFF83 Register TPCR TPLR FFFF82 7 6 5 4 3 2 1 0 TCIE TOIE Timer Control Status Register TCSR 1 14 13 12 11 10 9 8 TCSRO FFFF8F 5 1 FFFF8B pin TRM TCSR2 FFFF87 23 22 21 20 19 18 17 16 23 0 Register TLR TLRO FFFF8E TLR1 FFFF8B TLR2 FFFF87 Register TCPR TCPRO FFFF8F TCPR1 FFFF86 TCPR2 FFFF87 Register TCR TCRO FFFF8C TCR1 FFFF88 TCR2 FFFF84 reserved read as 0 should be written with 0 for future compatibility Figure 9 3 Timer Module Programmer s Model 9 6 DSP56303UM AD MOTOROLA Triple Timer Module Triple Timer Module Programming Model 9 3 1 Prescaler Counter The prescaler counter is a 21 bit counter that is decremented on the rising edge of the prescaler input clock The counter is enabled when at least one of the three timers is enabled i e one or more of the Timer Enable TE bits are set and is using the prescaler output as its source 1 one or more of the PCE bits are set 9 3 2 Timer Prescaler Load Register TPLR The Timer Prescaler
394. the DSP56303 9 4 4 2 Watchdog Toggle Mode 10 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode NAME Kind TIO Clock 1 0 1 0 10 Toggle Watchdog Output Internal In this mode the timer toggles an external signal after preset period Set the TE bit to clear the counter and enable the timer The value the timer is to count is loaded into the TPCR The counter is loaded with the TLR value on the first timer clock received from either the DSP56303 internal clock divided by two CLK 2 or the prescaler clock output Each subsequent timer clock increments the counter The TIO pin is set to the value of the INV bit When the counter equals the value in the TCPR the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is also set If the TRM bit is set the counter is loaded with the TLR value on the next timer clock and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each subsequent timer clock When counter overflow has occurred the polarity of the TIO output pin is inverted the TOF bit in the TCSR is set and an overflow interrupt is generated if the TOIE bit is also set The TIO polarity is determined by the INV bit 9 26 DSP56303UM AD MOTOROLA Triple Timer Module Timer Modes of Operation The counter is reloaded whenever the TLR is written with a new value while the TE bit is set This process is repeate
395. the OGDBR contents Pass through update DR Wait for next command 10 12 6 Displaying X Memory Area Starting at Address xxxx The DSP56300 must be in Debug mode and all actions described in Saving Pipeline Information on page 10 25 have been executed Since RO is used as pointer for the memory RO is saved first The sequence of actions is 10 26 DSP56303UM AD MOTOROLA On Chip Emulation Module Examples of Using the OnCE 1 Select shift DR Shift in the Write PDB with GO no EX Pass through update DR 2 Select shift DR Shift in the 24 bit opcode MOVE X 0GDB Pass through update DR to actually write OPDBR and thus begin executing the MOVE instruction 3 Wait for DSP to reenter Debug mode wait for DE or poll core status 4 Select shift DR and shift in READ GDB REGISTER Pass through update DR this selects OGDBR as the data register for read 5 Select shift DR Shift out the OGDBR contents Pass through update DR is now saved 6 Select shift DR Shift in the Write PDB with no GO no EX Pass through update DR Z Select shift DR Shift in the 24 bit opcode MOVE xxxx RO Pass through update DR to actually write OPDBR 8 Select shift DR Shift in the Write PDB with GO no EX Pass through update DR 9 Select shift DR Shift in the second word of the 24 bit opcode MOVE xxxx RO the xxxx field Pass through update DR to actually write OPDBR and execute the ins
396. the baud rate generator can function as a general purpose timer when it is not being used by the SCI or when the interrupt timing is the same as that used by the SCI 1 10 5 Timer Module The triple timer module is composed of a common 21 bit prescaler and three independent and identical general purpose 24 bit timer event counters each one having its own memory mapped register set Each timer has a single pin that can be used as a GPIO pin or as a timer pin Each timer can use internal or external clocking and can interrupt the DSP after a specified number of events clocks or can signal an external device after counting internal events Each timer connects to the external world through one bidirectional pin When this pin is configured as an input the timer can function as an external event counter or measures external pulse width signal period When the pin is used as an output the timer can function as either a timer a watchdog or a Pulse Width Modulator PWM MOTOROLA DSP56303UM AD 1 17 DSP56303 Overview DSP56303 Architecture Overview 118 5 56 MOTOROLA SECTION 2 SIGNAL CONNECTION DESCRIPTIONS MOTOROLA DSP56303UM AD 2 1 Signal Connection Descriptions 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 2 SIGNAL GROUPINGS 2 3 e ped LL ELM EAA 2 5 GROUND a e 2 6 S e
397. ther 24 bit word Boot from EPROM done DSP56303UM AD A 9 Bootstrap Programs FINISH This is the exit handler that returns execution to normal expanded mode and jumps to the RESET vector andi 0 ccr Clear CCR as if RESET to 0 jmp r1 Then go to starting Prog addr End of bootstrap code Number of program words 91 A 10 DSP56303UM AD MOTOROLA APPENDIX EQUATES RA EMEA k RAE RRR KKK KKK KKK ckckckckckckckckckckckckckckckckckckck ck kckckckck ck ck kckckckckckckck kk EQUATES for 56303 I O registers and ports Last update June 11 1995 152 55 0 020 ioequ ident 1 0 MOTOROLA DSP56303UM AD B 1 Equates B 2 VO EQUATES es B 3 HOST INTERFACE HI08 EQUATES B 3 SERIAL COMMUNICATIONS INTERFACE SCI EQUATES S usutay yan a SOC eee eee S B 4 ENHANCED SYNCHRONOUS SERIAL INTERFACE ESSI IM M I IL ie ise B 6 EXCEPTION PROCESSING 5 B 8 TIMER MODULE EQUATES 9 DIRECT MEMORY ACCESS DMA EQUATES B 10 PHASE LOCKED LOOP PLL EQUATES B 12 BUS INTERFACE UNIT BIU EQUATES B 13 INTERRUPT EQUATES B 15 DSP56303UM AD MOTOROLA Equates I O EQUATES k k KKK KKK KK KKK KKK KK KK KKK KKK KKK KK KKK KKK
398. timer clock MOTOROLA DSP56303UM AD 9 21 Triple Timer Module Timer Modes of Operation This process is repeated until the timer is disabled i e TE is cleared If the counter overflows the TOF bit is set and if TOIE is set an overflow interrupt is generated The counter contents can be read at any time by reading the TCR 9 4 2 3 Measurement Input Period Mode 5 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Kind TIO Clock 0 1 0 1 5 Input Period Measurement Input Internal In this mode the timer counts the period between the reception of signal edges of the same polarity across the TIO pin Set the TE bit to clear the counter and enable the timer The value the timer is to count is loaded into the TLR The value of the INV bit determines whether the period is measured between consecutive low to high 0 to 1 transitions of TIO or between consecutive high to low 1 to 0 transitions of TIO If INV is set high to low signal transitions are selected If INV is cleared low to high signal transitions are selected After the first appropriate transition occurs on the TIO input pin the counter is loaded with the TLR value on the first timer clock signal received from either the DSP56303 clock divided by two CLK 2 or the prescaler clock output Each subsequent clock signal increments the counter On the next signal transition of the same polarity that occurs on TIO
399. tion the on chip memory and peripherals supports a wide variety of memory and peripheral configurations The DSP56303 may be used in telecommunications applications such as multi line voice data fax processing videoconferencing audio applications control and general digital signal processing 15 DSP56303 CORE DESCRIPTION Core features are described fully in the DSP56300 Family Manual Pinout memory and peripheral features are described in this manual 1 5 1 General Features 66 80 Million Instructions Per Second MIPS with a 66 80 MHz clock at 3 3 V Object code compatible with the DSP56000 core Highly parallel instruction set 1 5 2 Hardware Debugging Support On Chip Emulation OnCE module Joint Action Test Group JTAG Test Access Port TAP port e Address Tracing mode reflects internal accesses at the external port 1 5 3 Reduced Power Dissipation Very low power CMOS design Wait and Stop low power standby modes Fully static logic operation frequency down to 0 Hz DC Optimized power management circuitry instruction dependent peripheral dependent and mode dependent MOTOROLA DSP56303UM AD 1 7 DSP56303 Overview DSP56300 Core Functional Blocks 1 6 DSP56300 CORE FUNCTIONAL BLOCKS The DSP56300 core provides the following functional blocks Data Arithmetic Logic Unit Data ALU e Address Generation Unit AGU e Program Control Unit PCU e PLL and Clock Oscillator
400. tion of RESET causes the chip to enter the Debug mode After receiving the acknowledge the external command controller must negate the DE line before sending the first command Note In this case the chip does not execute any instruction before entering the Debug mode 10 16 DSP56303UM AD MOTOROLA On Chip Emulation Module Methods of Entering the Debug Mode 10 7 2 External Debug Request During Normal Activity Holding the DE line asserted during normal chip activity causes the chip to finish the execution of the current instruction and then enter the Debug mode After receiving the acknowledge the external command controller must negate the DE line before sending the first command This process is the same for any newly fetched instruction including instructions fetched by the interrupt processing or instructions that will be aborted by the interrupt processing Note In this case the chip completes the execution of the current instruction and stops after the newly fetched instruction enters the instruction latch 10 7 3 Executing the JTAG DEBUG REQUEST Instruction Executing the JTAG instruction DEBUG REQUEST asserts an internal debug request signal Consequently the chip finishes the execution of the current instruction and stops after the newly fetched instruction enters the instruction latch After entering the Debug mode the Core Status bits OS1 and OS0 are set and the DE line is asserted thus acknowledging the external command c
401. tive chip select input HD HS 0 Single strobe bus R W and DS strobes HMUX 0 Non multiplexed bus HASP 0 address strobe polarity has no meaning in MOTOROLA Bootstrap Programs HCSEN 1 Host chip select input enabled non multiplexed bus non multiplexed bus DSP56303UM AD HRP 0 Negative host request HCSP 0 Negative chip select input HD HS 0 Single strobe bus R W and DS strobes HMUX 0 Non multiplexed bus HASP 0 address strobe polarity has no meaning in non multiplexed bus HDSP 1 Negative data strobes polarity HROD 0 Host request is active when enabled 0 This bit should be set to 0 for future compatibility HEN 0 When the HPCR register is modified HEN should be cleared HAE 0 Host acknowledge is disabled HRE 1 Host requests are enabled 0 address 9 enable bit has no meaning in Bootstrap Programs HDSP 0 Negative data strobes polarity HROD 0 Host request is active when enabled 0 This bit should be set to 0 for future compatibility HEN 0 When the HPCR register is modified HEN should be E cleared HAEN 1 Host acknowledge is enabled HRE 1 Host requests ar nabled HCSEN
402. transmit a data word and generate a transmitter empty condition TSMA and TSMB see Figure 7 16 and Figure 7 17 can be seen as a single 32 bit register Bit n in TSn is an enable disable control bit for transmission in slot number N When TSn is cleared all the transmit data pins of the enabled 7 34 DSP56303UM AD MOTOROLA Enhanced Synchronous Serial Interface ESSI ESSI Programming Model transmitters are tri stated during transmit time slot number N The data is still transferred from the enabled Transmit Data Register s to the Transmit Shift Register However the TDE and the TUE flags are not set This means that during a disabled slot no transmitter empty interrupt is generated The DSP is interrupted only for enabled slots Data written to the Transmit Data Register when servicing the transmitter empty interrupt request is transmitted in the next enabled transmit time slot When TSn is set the transmit sequence proceeds normally Data is transferred from the TX register to the shift register during slot number N and the TDE flag is set Using the TSM slot mask does not conflict with using the TSR Even if a slot is enabled in the TSM the user may chose to write to the TSR to tri state the pins of the enabled transmitters during the next transmission slot Setting the bits in the TSM affects the next frame transmission The frame currently being transmitted is not affected by the new TSM setting If the TSM is re
403. troller state using either of two methods During power up TRST must be externally asserted to force the TAP controller into this state After power up is concluded TMS must be sampled as a logic 1 for five consecutive TCK rising edges If TMS either remains unconnected or is connected to Vcc then the TAP controller cannot leave the Test Logic Reset state regardless of the state of TCK The DSP56300 core features a low power Stop mode which is invoked using the STOP instruction The interaction of the JT AG interface with low power Stop mode is as follows 1 The TAP controller must be in the Test Logic Reset state to either enter or remain in the low power Stop mode Leaving the TAP controller Test Logic Reset state negates the ability to achieve low power but does not otherwise affect device functionality 2 The TCK input is not blocked in low power Stop mode To consume minimal power the TCK input should be externally connected to Vcc or GND 11 12 DSP56303UM AD MOTOROLA JTAG Port DSP56303 Boundary Scan Register 3 The TMS and TDI pins include on chip pullup resistors In low power Stop mode these two pins should remain either unconnected or connected to Vcc to achieve minimal power consumption Since during Stop mode all DSP56303 core clocks are disabled the JTAG interface provides the means of polling the device status sampled in the Capture IR state 11 5 DSP56303 BOUNDARY SCAN REGISTER Table 11 2 provides a li
404. truction is loaded with the base address of the memory block to be read 10 Wait for DSP to reenter Debug mode wait for DE or poll core status 11 Select shift DR Shift in the Write with GO Pass through update DR 12 Select shift DR Shift in the 24 bit opcode MOVE X OGDB Pass through update DR to actually write OPDBR and thus begin executing the MOVE instruction 13 Wait for DSP to reenter Debug mode wait for DE or poll core status 14 Select shift DR and shift in READ GDB REGISTER Pass through update DR this selects OGDBR as the data register for read 15 Select shift DR Shift out the OGDBR contents Pass through update DR The memory contents of address xxxx has been read 16 Select shift DR Shift in the NO SELECT with GO no EX Pass through update DR This re executes the same MOVE 0 instruction 17 Repeat from step 14 to complete the reading of the entire block When finished restore the original value of RO MOTOROLA DSP56303UM AD 10 27 On Chip Emulation Module Examples of Using the OnCE 10 12 7 Returning from Debug Mode to Normal Mode to Current Program In this case the user has finished examining the current state of the machine changed some of the registers and wishes to return and continue execution of its program from the point where it stopped Therefore the user must restore the pipeline of the machine end e
405. ts are compatible with most processors including the MC68000 8051 HC11 and Hitachi H8 Dedicated interrupts Separate interrupt lines for each interrupt source Special host commands force DSP core interrupts under host processor control These commands are useful for e Real time production diagnostics Creating a debugging window for program development e Host control protocols Interface capabilities Glueless interface no external logic required to Motorola HC11 e Hitachi H8 8051 family Thomson P6 family Minimal glue logic pullups pulldowns required to interface to ISA bus Motorola 68K family Intel X86 family MOTOROLA DSP56303UM AD 6 5 Host Interface HI08 Host Port Signals 6 3 HI08 HOST PORT SIGNALS The host port signals are described in Section 2 Each host port pin may be programmed as a host port pin or as a GPIO pin PBO PB15 see Table 6 1 through Table 6 3 below Table 6 1 HI08 Signal Pin Definitions for Various Operational Modes Multiplexed address data Non Multiplexed bus GPIO 8108 port pin bus mode mode mode HAD0 HAD7 HAD0 HAD7 H0 H7 PBO PB7 HAS HAO HAS HAS HAO PB8 HA8 HA1 HA8 HA1 PB9 HA9 HA2 HA9 HA2 PB10 HCS HA10 HA10 HCS HCS PB13 Table 6 2 HI08 Data Strobe Signal Pins Single strobe bus Dual strobe bus GPIO mode HRW HRD HRW HRD HRD PB11 HDS HWR HDS HDS HWR HWR PB12 T
406. ty Register IPR C X FFFFFF 4 13 Interrupt Priority Register P IPR P X FFFFFE 4 13 DSP56303 Operating Mode Register OMR 4 17 PLL Control Register PCTL 4 18 Address Attribute Registers AAR0 AAR3 9 nir 4 19 HIOS Block 6 7 Host Control Register HCR X FFFFC2 6 10 Host Status Register X FFFFC3 6 11 DSP56303UM AD xvii Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 6 8 Figure 6 9 Figure 6 10 Figure 6 11 Figure 6 12 Figure 6 13 Figure 6 14 Figure 6 15 Figure 6 16 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 xviii Host Base Address Register HBAR X SFFFFC5 6 12 Self Chip Select Logic 6 13 Host Port Control Register HPCR X FFFFC4 6 13 Single Stroba BUS i a ae Qs ka 6 16 Dual Strobe BUS HUS ere ais dte 6 16 Host Data Direction Register X SFFFFC8 6 17 Host Data Register HDR 9 6 17 HSR HCR Operation 6 20 Interface Control 4234 ve eaten leet ee te cis 6 22 Command Vector Register CVR 6 25 Interface
407. uction to be used to transfer data between the DSP56303 and external hosts Special instruction provides for I O service capability using fast interrupts Bit addressing instructions e g BCHG BCLR BSET BTST JCLR JSCLR JSET JSSET simplify I O service routines HI08 to Host Processor Interface Sixteen signal pins are provided to support non multiplexed or multiplexed buses H0 H7 HAD0 HAD host data bus 0 7 or host multiplexed address data bus HADO HAD7 HAS HAO address strobe HAS or host address line HAO HA8 HA1 host address line HA8 or host address line HA1 9 2 host address line HA9 or host address line HA2 HRW HRD read write select HRW or read strobe HRD HDS HWR data strobe HDS or write strobe HWR HCS HA10 host chip select HCS or host address line HA10 host request or host transmit request HTRQ HACK HRRQ host acknowledge HACK or host receive request HRRQ Mapping HI08 registers are mapped into eight consecutive locations in external bus address space 08 acts as a memory or I O mapped peripheral for microprocessors microcontrollers etc Data word 8 bit DSP56303UM AD MOTOROLA Host Interface HI08 08 Features e Transfer modes Mixed 8 bit 16 bit and 24 bit data transfers DSP to host Host to DSP Host command Handshaking protocols Software polled Interrupt driven Interrup
408. uired by the standard The two Most Significant Bits are loaded with the values of the core status bits 51 and 050 from the OnCE controller See Section 10 On Chip Emulation Module for a description of the status bits 11 3 2 1 EXTEST B 3 0 0000 The external test EXTEST instruction selects the BSR EXTEST also asserts internal reset for the DSP56300 core system logic to force a predictable internal state while performing external boundary scan operations By using the the BSR is capable of the following e Scanning user defined values into the output buffers 11 8 DSP56303UM AD MOTOROLA JTAG Port TAP Controller Capturing values presented to input pins Controlling the direction of bidirectional pins Controlling the output drive of tri stateable output pins For more details on the function and use of the EXTEST instruction please refer to the IEEE 1149 1 document 11 3 2 2 SAMPLE PRELOAD B 3 0 0001 The SAMPLE PRELOAD instruction provides two separate functions First it provides a means to obtain a snapshot of system data and control signals The snapshot occurs on the rising edge of TCK in the Capture DR controller state The data can be observed by shifting it transparently through the BSR Note Since there is no internal synchronization between the JTAG clock and the system clock CLK the user must provide some form of external synchronization to achieve meaningful results The se
409. ultaneously asserted The IVR data tells the MC680XX host processor which interrupt routine to execute to service the DSP56303 MOTOROLA DSP56303UM AD 6 33 Host Interface HI08 08 Programming Model Quick Reference 07 0 SOH OLW SOH lqeu3 se payee si 514 Old 0LV SOH 0 1 e eg diu 150 N3SOH 0 H 0 S SIU 0 XNWH FL 6VH L lqeu3 6 s yq 514 Old9 2V 6VH 0 sur ss ppy 1soH N36VH 07 H 0 S 4q 514 0 XNWH FL 8VH 8 se s 514 Old LV 8VH 0 10H N38VH suid Old L 0 p lo uuoosip Old5 alqeuz 0149 IS0H HOdH 0 150 3H 0 JOH L ejqeu3 1dnu lu 0 peigesip 1dnu lu 0 5 peiqeue OH LH lqeua 0 peigesip 0 5 p lqeu OHHH lqeua e 0 peigesip 1dnuu lu OHHH 0 1dnueju HdIs 45 LH MS uornoung A S I sju urtuo Sow d L yasay I PON 801 61 9 214 4
410. user must provide adequate external decoupling capacitors There four connections GND 4 Address Bus Ground GND is an isolated ground for sections of the address bus I O drivers This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors There are four GND connections GND 4 Data Ground GNDp is an isolated ground for sections of the data bus I O drivers This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors There are four GNDp connections GNDc 2 Bus Control Ground GNDc is an isolated ground for the bus control I O drivers This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors There two GNDy connections GND Host Ground GNDy is an isolated ground for the 108 I O drivers This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors There is one connection GNDs 2 ESSI SCI and Timer Ground GNDes is an isolated ground for the ESSI SCI and timer I O drivers This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors There two GND
411. utput pins prior to invoking the EXTEST instruction SAMPLE PRELOAD Disable the output drive to pins during circuit board testing HI Z Provide a means of accessing the On Chip Emulation OnCE controller and circuits to control a target system ENABLE_ONCE Provide a means of entering the Debug Mode of operation DEBUG REQUEST Query identification information manufacturer part number and version from an DSP56300 core based device IDCODE Force test data onto the outputs of an DSP56300 core based device while replacing its boundary scan register in the serial data path with a single bit register CLAMP This section which includes aspects of the JTAG implementation that are specific to the DSP56300 core is intended to be used with the supporting IEEE 1149 1 document The discussion includes those items required by the standard to be defined and in certain cases provides additional information specific to the DSP56300 core implementation For internal details and applications of the standard MOTOROLA DSP56303UM AD 11 3 JTAG Port Introduction refer to the IEEE 1149 1 document Figure 11 1 shows a block diagram of the TAP port i Boundary Scan Register a ID Register 2 eae OnCE Logic Decoder al a 4 Bit Instruction Register TRST AA0113 Figure 11 1 TAP Block Diagram 11 4 DSP56303UM AD MOTOROLA JTAG Port JTAG Pins 11 2 JTAG PINS As
412. with the transmit clock which can have either an internal or external source as defined by the TCM bit in the SCCR The length and format of the serial word is defined by the WDS0 WDS1 WDS2 control bits in the SCR In the Asynchronous modes the start bit the eight data bits with the LSB first if SSFTD 0 and the MSB first if SSFTD 1 the address data indicator bit or parity bit and the stop bit are transmitted in that order The data to be transmitted can be written to any one of the three STX addresses If SCKP is set and SSHTD is set the SCI Synchronous mode is equivalent to the SSI operation in the 8 bit Data On demand mode Note When writing data to a peripheral device there is a two cycle pipeline delay until any status bits affected by this operation are updated If the user reads any of those status bits within the next two cycles the bit will not reflect its current status See the DSP56300 Family Manual appendix B Polling a peripheral device for write for further details 8 4 OPERATING MODES The operating modes for the DSP56303 SCI are 8 bit Synchronous shift register mode e 10 bit Asynchronous 1 start 8 data 1 stop 11 bit Asynchronous 1 start 8 data 1 even parity 1 stop 11 bit Asynchronous 1 start 8 data 1 odd parity 1 stop 11 bit Multidrop Asynchronous 1 start 8 data 1 data type 1 stop This mode is used for master slave operation with Wakeup On Idle Line and Wakeup On A
413. wo enabled interrupt sources is set 6 6 4 Interrupt Vector Register IVR The IVR is an 8 bit read write register which typically contains the interrupt vector number used with MC68000 family processor vectored interrupts Only the host processor can read and write this register The contents of the IVR are placed on the host data bus H 7 0 when both the HREQ and HACK pins are asserted The contents of this register are initialized to 0F by a hardware or software reset This value corresponds to the uninitialized interrupt vector in the MC68000 family 7 6 5 4 3 2 1 0 7 IV6 5 iva IV2 0671 Figure 6 15 Interrupt Vector Register 6 6 5 Receive Byte Registers RXH RXM RXL The Receive Byte Registers are viewed by the host processor as three 8 bit read only registers These registers are the Receive High register RXH the Receive Middle register RXM and the Receive Low register RXL They receive data from the high middle and low bytes respectively of the HTX register and are selected by the external host address inputs HA 2 0 during a host processor read operation 6 28 DSP56303UM AD MOTOROLA Host Interface 108 HI08 External Host Programmer s Model The memory address of the Receive Byte Registers are set by the HLEND bit in the ICR If the HLEND bit is set the RXH is located at address 7 RXM at 6 and RXL at 5 If the HLEND bit is cleared the
414. written with 0 for future compatibility Figure 9 5 Timer Prescaler Count Register TPCR 9 8 DSP56303UM AD MOTOROLA Triple Timer Module Triple Timer Module Programming Model 9 3 3 1 TPCR Prescaler Counter Value PC 20 0 Bits 20 0 These 21 bits contain the current value of the prescaler counter 9 3 3 2 TPCR Reserved Bits 23 21 These reserved bits are read as 0 and should be written with 0 for future compatibility 9 3 4 Timer Control Status Register TCSR The Timer Control Status Register TCSR is a 24 bit read write register controlling the timer and reflecting its status The control and status bits are described below see Table 9 2 9 3 4 1 Timer Enable TE Bit 0 The Timer Enable TE bit is used to enable or disable the timer Setting TE enables the timer and clears the timer counter The counter starts counting according to the mode selected by the Timer Control TC 3 0 bit values Clearing the TE bit disables the timer The TE bit is cleared by a hardware RESET signal or a software RESET instruction Note When all the three timers are disabled and the signal pins are not in GPIO mode all three TIO pins are tri stated To prevent undesired spikes on the TIO pins when switching from tri state into active state these pins should be tied to the high or low signal state by the use of pull up or pull down resistors 9 3 4 2 Timer Overflow Interrupt Enable TOIE Bit 1 The Timer Overflow Interrupt Enable T
415. xx Pass through update DR to actually write the PDB At this time the ODEC releases the chip from Debug mode and the execution is started from the address xxxx 10 28 DSP56303UM AD MOTOROLA On Chip Emulation Module Examples of JTAG and OnCE interaction Note If the entering of the Debug mode happened during a DO LOOP REP instruction or other special cases such as interrupt processing STOP WAIT or conditional branching it is mandatory that the user first resets the DSP56300 and only afterwards proceeds with the execution of the new program 10 13 EXAMPLES OF JTAG AND OnCE INTERACTION This subsection lists the details of the JTAG port OnCE module interaction and TMS sequencing required in order to achieve the communication described in Examples of Using the OnCE on page 10 24 The external command controller can force the DSP56300 into Debug mode by executing the JTAG instruction DEBUG REQUEST In order to check that the DSP56300 has entered the Debug mode the external command controller must poll the status by reading the OS 1 0 bits in the JTAG instruction shift register The TMS sequencing is depicted in Table 10 12 The sequencing of enabling the OnCE module is described in Table 10 13 on page 10 30 After executing the JTAG instructions DEBUG_REQUEST and ENABLE_ONCE and after the core status was polled to verify that the chip is in Debug mode the pipeline saving procedure must take place The TMS sequencing for this proce
416. y 1 Stop WDS2 WDS1 WDSO TX Stop SSFTD 0 Bit Mode 5 Log gs 11 bit Asynchronous 1 Start 8 Data 1 Odd Parity 1 Stop WDS2 WDS1 WDSO TX Stop SSFTD 0 Bit Mode 6 PATARAS 11 bit Asynchronous Multidrop 1 Start 8 Data 1 Data Type 1 Stop WDS2 WDS1 WDSO TX Stop SSFTD 0 Bit Data Type c u L 1 Modes 1 3 and 7 are reserved ata Byte 2 D0 LSB D7 MSB 3 Data is transmitted and received LSB first if SSFTD 0 or MSB first if SSFTD 1 0691 Figure 8 4 SCI Data Word Formats 8 6 DSP56303UM AD MOTOROLA Serial Communication Interface SCI SCI Programming Model Mode 0 8 bit Synchronous Data Shift Register Mode WDS2 WDS1 WDSO IX D3 SSFTD 1 One Byte From Shift Register Stop Bit Stop Bit Mode 5 Stop Bit Mode 6 1 11 bit Asynchronous 1 Start 8 Data 1 Data Type 1 Stop WDS2 WDS1 WDSO TX Stop SSFTD 1 Bit Data Type 1 Address Byte jy 1 0 Data Byte ote Modes 1 3 and 7 are reserved 2 DO LSB D7 MSB 3 Data is transmitted and received LSB first if SSFTD 0 or MSB first if SSFTD 1 AA0691 cont Figure 8 4 SCI Data Word Formats MOTOROLA DSP56303UM AD 8 7 Serial Communication Interface SCI SCI Programming Model 8 3 1 SCI Control Register SCR The SCI Control Register SCR is a 24 bit read write register that controls the serial interface operation Seventeen o
417. y SCR Bit 11 RIE 3 SCI Transmit Data is caused by Transmit Data Register empty Writing STX clears the pending interrupt This error free interrupt can use a fast interrupt service routine for minimum overhead This interrupt is enabled by SCR Bit 12 TIE 8 26 DSP56303UM AD MOTOROLA Serial Communication Interface SCI GPIO Pins and Registers 4 SCI Idle Line is caused by the receive line entering the idle state ten or eleven bits of 1s This interrupt is latched and then automatically reset when the interrupt is accepted This interrupt is enabled by SCR Bit 10 ILIE 5 SCI Timer is caused by the baud rate counter reaching zero This interrupt is automatically reset when the interrupt is accepted This interrupt is enabled by SCR Bit 13 TMIE 85 GPIO PINS AND REGISTERS The GPIO functionality of port SCI is controlled by three registers Port E Control Register PCRE Port E Direction Register PRRE and Port E Data Register PDRE 8 5 1 Port E Control Register PCRE The read write 24 bit PCRE controls the functionality of SCI GPIO pins Each of PC 2 0 bits controls the functionality of the corresponding port pin When PC i bit is set the corresponding port pin is configured as a SCI pin When a bit is cleared the corresponding port pin is configured as GPIO pin 7 6 5 4 3 2 i 0 _ 2 1 Port Control Bits 1 SCI 0 GPIO i Reserved Bit Read
418. yasay p nunuo2O 90 T 9 lqe 1 6 37 DSP56303UM AD MOTOROLA Host Interface HI08 08 Programming Model Quick Reference J peuesse s 4 40 1 15 60 00089 1 1 OAI ZAI 0 Z A dwa 150 0 4 VW HXL JeisiBou ISOH 0 4 SI s nb 1 OH Buipu d soy 010 0 90IH 1509 ou 0 2H L J0129A BIA JOJOBA 190H OAH 9AH 0 9 DSP56303UM AD 010 0 s 0 1soH OaYH 2 0 10H 4H v 0 150 jou s 14 0 L si deep 9 O4IJ L 2 IInJ S 190H 0 L si lluusue11 SOH L Usu L JIN S ISOH L n4 010 0 si ISOH 0 0 LH MS
419. ync Flag bit TFS 7 28 transmit host request signal HTRO HTRO 2 23 Transmit Interrupt Enable bit TIE 7 26 8 12 Transmit Last Slot Interrupt Enable bit TLIE 7 26 Transmit Request Enable bit TREQ 6 23 Transmit Shift Registers 7 33 Transmit Slot Mask Registers TSMA TSMB 7 34 Transmitter Empty bit TRNE 8 13 Transmitter Enable bit TE 8 11 Transmitter Ready bit TRDY 6 27 Transmitter Underrun Error Flag bit TUE 7 29 TRDY bit 6 27 TREQ bit 6 23 triple timer module 1 17 TRM bit 9 13 TRNE bit 8 13 TRST pin 11 5 TSMA TSMB registers 7 34 TSR register 7 34 TUE bit 7 29 TX2 TX1 registers 7 34 TXD signal 2 33 8 4 TXDE bit 6 26 TXL registers 6 29 V VBA register 1 11 Vector Base Address register VBA 1 11 1 14 DSP56303UM AD W wait standby mode 1 7 WAKE bit 8 9 Wakeup Mode Select bit WAKE 8 9 WDS0 WDS2 bits 8 8 Wired OR Select bit WOMS 8 10 WLO WLI bits 7 14 WOMS bit 8 10 Word Length Control bits WLO WL1 7 14 Word Select bits WDS0 WDS2 8 8 WR signal 2 10 write enable signal 2 10 X X data RAM 3 6 X Memory Address Bus XAB 1 13 X Memory Data Bus XDB 1 13 X Memory Expansion Bus 1 13 1 13 XDB 1 13 XTAL 2 7 XTAL Disable bit XTLD 4 18 XTLD bit 4 18 Y Y data RAM 3 7 Y Memory Address Bus YAB 1 13 Y Memory Data Bus YDB 1 13 Y Memory Expansion Bus 1 13 1 13 YDB 1 13 MOTOROLA DSP56303 OVERVIEW SIGNAL CONNECTION DESCRI

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