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HCS12 V1.5 Core User Guide Version 1.2

1. Mnemonic Function Operation LSL Logic shift left memory LSLA Logic shift left A Tan oe LSLB Logic shift left B ere 0 LSLD Logic shift left D oS a a eer ee LSR Logic shift right memory LSRA Logic shift right A 0 gt e LSRB Logic shift right B DERRI 0 LSRD Logic shift right D a A mace B eS ASL Arithmetic shift left memory ASLA Arithmetic shift left A E Pa ASLB Arithmetic shift left B ASLD Arithmetic shift left D A EE EEEE Eg ASR Arithmetic shift right memory ASRA Arithmetic shift right A gt gt ASRB Arithmetic shift right B a yr 6 ROL Rotate left memory ROLA Rotate left A Lk tH ROLB Rotate left B c 7 0 ROR Rotate right memory RORA Rotate right A p gt _ gt RORB Rotate right B 0 7 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 4 3 13 Fuzzy Logic Instructions The instruction set supports efficient processing of fuzzy logic operations A summary of the fuzzy logic instructions is given in Table 4 15 Table 4 15 Fuzzy Logic Instructions Mnemonic Function Operation u grade My X 4 X Y 1 Y A unchanged If A lt P1 or A gt P2 then y 0 else u MIN A P1 x S1 P2
2. Source Form Operation Mode Coding Hex Access Detail SXHINZVC LBMI re 16 Long branch if minus 18 2Baqqrr PPP branch If N 1 then PC 4 rel gt PC PO no branch LBNE re 16 Long branch if not equal to 0 1826qqrr p branch If Z 0 then PC 4 rel gt PC no branch LBPL re 16 Long branch if plus 18 2Aqqrr PPP branch If N 0 then PC 4 rel gt PC no branch LBRA rel16 Long branch always 18 20 qqrr LBRN rel16 Long branch never 18 21 qqrr LBVC rel16 Long branch if V clear 1828 qqrr OPPP branch If V 0 then PC 4 rel gt PC OPO no branch LBVS rel16 Long branch if V set 1829qqrr OPPP branch If V 1 then PC 4 rel gt PC OPO no branch LDAA opr8i LoadA 8644 P LDAA opr8a M gt A 96 dd rPf LDAA opr16a orimm gt A B6hh11 rPO LDAA oprx0_xysppc A6 xb rPf LDAA oprx9 xysppc A6 xbff rPO LDAA oprx16 xysppc A6 xbee ff frPP LDAA D xysppc A6 xb flfrPf LDAA oprx16 xysppc A6 xbee ff fIPrP LDAB opr8i LoadB j P LDAB opr8a M B rPf LDAB opr16a or imm gt B rPO LDAB oprx0_xysppc rPf LDAB oprx9 xysppc rPO LDAB oprx16 xysppc frPP LDAB D xysppc flfrPf LDAB oprx16 xysppc fIPrP LDD opr16i Load D j PO LDD opr8a M M 1 A B RP LDD opr16a or imm gt A B RPO LDD oprx0_xysppc RP LDD oprx9 xysppc RPO LDD oprx16 xysppc fRPP LDD D xysppc fIfRPf LDD oprx16 xysppc fIPRPf LDS
3. Source Form Operation be c oana ex Access Detail SXHINZVC SBCB opr8i Subtract with carry from B Cc2 ii P SBCB opr8a B M C B D2 dd rPf SBCB opr16a or B imm C B F2hh11 rPO SBCB oprx0_xysppc E2 xb rPf SBCB oprx9 xysppc E2 xb ff rPO SBCB oprx16 xysppc E2xbee ff frPP SBCB D xysppc E2 xb flfrPf SBCB oprx16 xysppc E2 xbee ff fIPrPf SECSame as ORCC 01 Set C bit 1401 SEISame as ORCC 10 Set bit SEVSame as ORCC 02 Set V bit SEX abc dxyspSame as TFRri r2_ Sign extend 8 bit r1 to 16 bit r2 00 r1 r2 if bit 7 of r1 is O FF r1 r2 if bit 7 of r1 is 1 STAA opr8a Store accumulator A DIR 5A dd Pw JaJa o STAA opr16a A gt M EXT 7Ahh11 PwO STAA oprx0_xysppc IDX 6A xb Pw STAA oprx9 xysppc IDX1 6A xb ff PwO STAA oprx16 xysppc IDX2 6Axbeeff PwP STAA D xysppc D IDX 6Axb PIfw STAA oprx16 xysppc IDX2 6Axbee ff PIPw STAB opr8a Store accumulator B DIR 5Bdd Pw Ja a o STAB opr16a B M EXT 7Bhh11 PwO STAB oprx0_xysppc IDX 6B xb Pw STAB oprx9 xysppc IDX1 6B xb ff PwO STAB oprx16 xysppc IDX2 6Bxbeeff PwP STAB D xysppc D IDX 6Bxb PIfw STAB oprx16 xysppc IDX2 6Bxbee ff PIPw STD opr8a Store D DIR 5C dd PW Ja a o STD opr16a A B gt M M 1 EXT 7Chh11 PWO STD oprx0_xysppc IDX 6C xb PW STD oprx9 xysppc IDX1 6C xb ff PWO STD oprx16 xysppc IDX2 6C xbee ff PWP
4. OSSSSsf before interrupt VfPPP after interrupt Initialize B X and Y B number of elements X points at first element in S list The frr ff ff sequence is the loop for one iteration of SOP and SOW accu Calculate weighted average sum of products SOP and sum of weights SOW Special Y points at Additional cycles caused by an interrupt SSS is the exit sequence and UUUrr is the first elementin F list mulation The denotes a che OE TEESEELEJOR SSS UUUrro x x All S and F elements are 8 bit values ck for pending interrupt requests re entry sequence Intermediate values use six stack bytes wavr Resume executing interrupted WAV Special 3 UVUrr ffff frr _I 2I 2TA T EELLJOS SS UUUrr wavr is a pseudoinstruction that recovers intermediate results from the stack rather than initializing them to 0 The frr ffff sequence is the loop for one iteration of SOP and SOW recovery The denotes a check for pending interrupt requests These are additional cycles caused by an interrupt sss is the exit sequence and UUUrr is the eens sequence XGDXSame as EXGD X Exchange D with X D X For More Information On This Product Go to www freescale com Core User
5. Branch Complementary Branch Test R gt M or B gt A Z NOV 0 R gt M or B gt A 61220 Comment Mnemonic Opcode Mnemonic Opcode LBLE LBLS LBHI 18 22 Unsigned For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 LBLO ong branen Lower LBLO same as LBCS Operation IfC 1 then PC 0004 rel PC LBLO can be used to branch after subtracting or comparing unsigned values After CMPA CMPB CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the CPU register value is less than the value in M After CBA or SBA the branch occurs if the value in B is less than the value in A Rel is a 16 bit two s complement offset for branching forward or backward in memory Branching range is 8000 to 7FFF 32768 to 32767 from the address following the last byte of object code in the instruction CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex LBLO rel16 REL 18 25 qq rr OPPP branch OPO no branch Branch Complementary Branch Comment Mnemonic Opcode Mnemonic Opcode Test LBLO LBCS LBHS LBCC For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor
6. BEGIN LDY FTABLE_START 2 setup initial table pointer FIND_LOOP CMPA 2 Y find first Xn gt XL auto pre inc Y by 2 BLS FIND_LOOP loop if XL le Xn on fall thru XB 2 Y YB 1 Y XE 0 Y and YE 1 Y TER D X save XL in high half of X CLRA zero upper half of D LDAB 0 Y D 0 XE SUBB 2 Y D 0 XE XB EXG D X X XE XB D XL junk SUBA 2 Y A XL XB EXG A D D 0 XL XB uses trick of EXG FDIV X reg XL XB XE XB EXG D X move fractional result to A B EXG A B byte swap need result in B STA check for rounding BPL NO_ROUND INCB round B up by 1 NO_ROUND LDAA dis Y YE PSHA put on stack for TBL later LDAA 1 Y YB PSHA now YB 0 SP and YE 1 SP TBL 2 SP interpolate and deallocate stack temps Figure B 12 Endpoint Table Handling The basic idea is to find the segment of interest temporarily build a one segment table of the correct format on the stack then use TBL with stack relative indexed addressing to interpolate The most difficult part of the routine is calculating the proportional distance from the beginning of the segment to the lookup point versus the width of the segment XL XB XE XB With this type of table this calculation must For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 be done at run time In the previous type of table this proportional term is an inherent part the lo
7. For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 ET B L Extended Table Lookup and Interpolate ET B L Operation M M 1 B x M 2 M 3 M M 1 gt D Linearly interpolates and stores in D one of 256 values between a pair of data entries Y1 and Y2 in a lookup table Data entries represent y coordinates of line segment endpoints Table entries and the interpolated results are 16 bit values Y2 Before executing ETBL point an indexing register at the Y1 value closest to but less than or equal to the Y value to interpolate Point to Y1 using any indexed addressing mode except indirect 9 bit offset YE and 16 bit offset The next table entry after Y1 is Y2 Load B with a binary fraction radix point to the left of the MSB representing the Y1 o Xi XL xo TAUG XL X1 X2 X1 where X1 Yl and X2 Y2 XL is the x coordinate of the value to interpolate The 16 bit unrounded result YL is calculated using the expression YL Y1 B x Y2 Y1 where Y1 16 bit data entry pointed to by effective address Y2 16 bit data entry pointed to by the effective address plus two The 24 bit intermediate value B x Y2 Y1 has a radix point between bits 7 and 8 CCR Effects S XH I N ZV C LEERTE N Set if MSB of result is set cleared otherwise Z Set if result is 0000 clea
8. 0 00 eee 254 14 4 4 Standard BDM Firmware Commands 00000 eee eee eee eee 255 14 4 5 BDM Command Structure anaana 256 14 4 6 BDM Serial Interface ses cti eaea a a n aa aa 258 14 47 Instruction Tracing ees A ed aE rors mente ER aa O E a AAA 260 14 4 8 Instruction Tagging sei ereas toee Aa BORE 260 14 5 Modes of Operation 2er Des idad a ea da a O ed A A 261 AD Norma Operation IS hanes el ats 08 261 14 5 2 Special Operation co daa a da 262 14 5 3 Emulation MoneS gt srt e y E a AA 262 14 6 Low Power Options dal a De 262 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide S12CPU15UG V1 2 Aba AUMIMOdO ds aca AC oO OTR ke Be Cee wre be E Beet bs ae 262 146 2 Wait Moder 2 27 2 sce seis EN 262 146 3 A O O Be 262 14 7 Interrupt Operation AAA O Ba Oe eRe See Hes 262 14 8 Motorola Internal Information 0 0 ee 262 14 81 O 62202 nto te ete yx te Ee ROMER a Ls Sea hee ee ee es 263 14 8 2 BDM Instruction Register Hardware 000 c eee eee 264 14 8 3 BDM Instruction Register Firmware 000 0c eee eee eee 265 14 8 4 BDM Status Register a tye Mein ye att elt ead oe ed eee A oe Mile dd chi 266 148 5 AS O DO 267 14 8 6 BDM Address Register o oooocccococccconnnccn ee 268 14 8 7 Special Peripheral Mode ie vsuicc sh sads ease eevee e Gee reece es 268 14 8 8 Standard BDM Firmware Listing
9. CALL opr16a page CALL oprx0_xysppc page CALL oprx9 xysppc page CALL oprx16 xysppc page CALL D xysppc CALL oprx16 xysppc CLCSame as ANDCC FE Branch if V set if V 1 then PC 2 rel gt PC Call subroutine in expanded memory SP 2 gt SP RTNy RTN gt Mgp Mgp 4 SP 1 SP PPG gt Mgp pg PPAGE register subroutine address gt PC Compare A to B A B Clear C bit 4Ahh1llpg 4Bx 4Bx 4Bx 4Bx 4Bx O pg b ff pg bee ff pg b bee ff PPP branch P no branch gnSsPPP gnSsPPP gnSsPPP fgnSsPPP flignSsPPP flignSsPPP CLISame as ANDCC EF Clear bit CLR opr16a CLR oprx0_xysppc CLR oprx9 xysppc CLR oprx16 xysppc CLR D xysppc CLR oprx16 xysppc CLRA CLRB CLVSame as ANDCC FD CMPA opr8i CMPA opr8a CMPA opr16a CMPA oprx0_xysppc CMPA oprx9 xysppc CMPA oprx16 xysppc CMPA D xysppc CMPA oprx16 xysppc CMPB Hopr8i CMPB opr8a CMPB opr16a CMPB oprx0_xysppc CMPB oprx9 xysppc CMPB oprx16 xysppc CMPB D xysppc CMPB oprx16 xysppc Clear M 00 gt M Clear A 00 gt A Clear B 00 gt B Clear V Compare A A M or A imm Compare B B M or B imm IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 Clii D1 dd Flh El x El x El x Elx El x ALL bff bee ff bee ff rPf rPO rPf rPO frPP fIfrPf fIPrPf P TP E rro rPf rPO frPP fIfr
10. For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 B C L R Clear Bit s in M B C L R Operation CCR Effects Code and CPU Cycles M mask byte gt M Performs a logical AND of the value in M and the complement of a mask byte contained in the instruction Puts the result in M Bits in M that correspond to 1s in the mask byte are cleared No other bits in M change N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Address Machine Source Form Mode Code Hex CPU Cycles BCLR opr8a msk8 4D dd mm rPwO BCLR opr16a msk8 1D hh 11 mm rPwP BCLR oprx0_xysppc msk8 0D xb mm rPwO BCLR oprx9 xysppc msk8 OD xb ff mm rPwP BCLR oprx16 xysppc msk8 OD xb ee ff mm frPwPO NOTES 1 Indirect forms of indexed addressing cannot be used with this instruction For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc BCS baron BCS same as BLO Operation If C 1 then PC 0002 rel PC Tests the C bit and branches if C 1 Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction CCR Effects S XH IN ZV C Code and CPU Addres
11. Address Machine Source Form Mode Code Hex CPU Cycles BRSET opr8a msk8 rel8 DIR 4E dd mm rr rPPP BRSET opr16a msk8 rel8 EXT 1E hh 11 mm rr rfPPP BRSET oprx0_xysppc msk8 rel8 IDX OE xb mm rr rPPP BRSET oprx9 xysppc msk8 rel8 IDX1 OF xb ff mm rr rfPPP BRSET oprx16 xysppc msk8 rel8 IDX2 OF xb ee ff mm rr PrfPPP For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc BSET Operation CCR Effects Code and CPU Cycles BSET Set Bit s in M M mask byte M Performs a logical OR of the value in M and a mask byte contained in the instruction Puts the result in M Bits in M that correspond to 1s in the mask are set No other bits in M change N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Source Form ggg Goda Hon CPU Cycles BSET opr8a msk8 4C dd mm rPwO BSET opr16a msk8 1C hh 11 mm rPwP BSET oprx0_xysppc msk8 OC xb mm rPwO BSET oprx9 xysppc msk8 OC xb ff mm rPwP BSET oprx16 xysppc msk8 OC xb ee ff mm frPwPO For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 BSR Branch to Subroutine BSR Operation CCR Effects Code and CPU Cycles SP 0002 gt SP RTNg RTN gt Msp Msp 1 PC 0002 rel PC Sets up conditions to return to normal program flow then tra
12. ADDB opr8i ADDB opr8a ADDB opr16a ADDB oprx0_xysppc ADDB oprx9 xysppc ADDB oprx16 xysppc ADDB D xysppc ADDB oprx16 xysppc ADDD opr16i ADDD opr8a ADDD opr16a ADDD oprx0_xysppc ADDD oprx9 xysppc ADDD oprx16 xysppc ADDD D xysppc ADDD oprx16 xysppc NDA opr i NDA opr8a NDA opr16a NDA oprx0_xysppc NDA oprx9 xysppc NDA oprx16 xysppc NDA D xysppc NDA oprx16 xysppc Add to B B M B or B imm gt B Add to D A B M M 1 gt A B or A B imm A B AND with A A e M gt A or Ajeimm gt A P rPf rPO rPf rPO frPP fIfrPf fIPrPf PO RP RPO RP RPO fRPP fIfRP fIPRP P rPf rPO rPf rPO frPP fIfrPf fIPrPf NDB opr i NDB opr8a NDB opr16a NDB oprx0_xysppc NDB oprx9 xysppc NDB oprx16 xysppc NDB D xysppc NDB oprx16 xysppc ANDCC ttopr8i PDD PPP gt DP gt AND with B B e M gt B or B eimm gt B AND with CCR CCR eimm gt CCR P rPf rPO TP E TPO frPP fIfrPf fIPrPf P ASL opr16aSame as LSL ASL oprx0_xysp ASL oprx9 xysppc ASL oprx16 xysppc ASL D xysppc ASL oprx16 xysppc ASLASame as LSLA ASLBSame as LSLB ASLDSame as LSLD Arithmetic shift left M 4 0 C b7 bO Arithmetic shift left A Arithmetic shift left B Arithmetic shift left D My e
13. 000 ee 268 14 8 9 Secured Mode BDM Firmware Listing 0000 eee eee eee 275 Section 15 Secured Mode of Operation IS COVE is o Si 279 SN E AA II EN 279 15 41 22 BIOCK Diagrami s simenti ge it E e NA O 280 15 2 nterface Signals oin e css each a Ii ara o 280 15 37 REJSTES e tati Debheet Sue SOL ee a ee as 281 0 24 Operation ai A E a eM aden a eee 281 15 4 1 Normal Singl Chip Mode s coco cia poi did beets 281 15 4 2 Expanded Mode osea e dl e ae Sl O Delos dd a he ot hte 281 154 3 Unsecurng The NS A E Es 281 15 5 Motorola Internal Information oooocccocccccneeo eee 283 15 5 1 BDM Secured Mode Firmware 0 00 eee eee 283 Appendix A Instruction Set and Commands E A E E A Beet dope gee nq toes AS A ARA e 285 A 2 Glossary Notation ce ee eaea e A to 285 A 2 1 Condition Code State Notation nnna naaa aaeeea 285 A 2 2 Register and Memory Notation tania tas 286 A 2 3 Address Mode NOTO oi E SAA AAA waa O LAIA ACE 287 A 2 4 Operator Notatlon cba taa recados dad idad 287 A 2 5 Machine Gode Notation isa ts is a e eee 287 For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc A 2 6 SOuUrCe Form NEGATION siase DES Ok a AA a ati a ea te 288 A 2 7 CPU Cycles Nodo res were eS ee wie ed wears Bee ee ee wa 289 Pode E enee Boscia be A a Opp Sed kee Leena gd ance ee Behe 292 Appendix B Fuzzy Logic Support B l GON
14. For More Information On This Product Go to www freescale com Core User Guide siocpuimtaRscale Semiconductor Inc Table 5 7 Access Detail Notation Continued Read indirect PPAGE value An i cycle is used only in indexed indirect CALL instructions The 8 bit PPAGE value for the CALL destination is fetched from an indirect memory location An i cycle is stretched only when controlled by a chip select circuit that is programmed for slow memory Write PPAGE register An n cycle is used only in CALL and RTC instructions to write the destination value of the PPAGE register and is not visible on the external bus Since the PPAGE register is an internal 8 bit register an n cycle is never stretched Optional cycle An o cycle adjusts instruction alignment in the instruction queue An cycle can be a free cycle or a program word access cycle P When the first byte of an instruction with an odd number of bytes is misaligned the o cycle becomes a P cycle to maintain queue order If the first byte is aligned the o cycle is an cycle The 18 prebyte for a page two opcode is treated as a special one byte instruction If the prebyte is misaligned the o cycle at the beginning of the instruction becomes a P cycle to maintain queue order If the prebyte is aligned the O cycle is an cycle If the instruction has an odd number of bytes it has a second O cycle at the end If the first o cycle is a P cycle prebyte misa
15. 0000 0c 543 PUZZy LOGIC SUPON econ teen Se themed pee eso uns 543 Table Lookup and Interpolation o oooooccccccono coo 544 Extended Bit Manipulalonexs Dista 4 544 Push and Pull D and GRA vicc fees awe so ri Pansies ed 544 Compare ore cintas rias ot tA a eee orale aa ot 544 Support for Memory Expansion 0 000 cee eee 544 For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide List of Figures Figure 1 1 Figure 1 2 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 5 1 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 Figure 7 7 Figure 7 8 Figure 7 9 Figure 7 10 Figure 7 11 Figure 7 12 Figure 7 13 Figure 7 14 Figure 7 15 Figure 8 1 Figure 8 2 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 Gore Block Diagram in sa set A ed Sor EA 25 Programming Model asaan 2eee eats ee antag es 2e2e4 27 Programming Model 2000 cece eee eee 53 ACCUMUIALOR Asa wai dee eno 54 Accumulator IE MA TN 54 Index Register X AAA Asse eed See Pek 54 Index Register a ies cea Is 54 Stack POInten SP icctceeastotaretey coho ce sa Aaaa eae 55 Program Counter POL tt a 56 Condition Code Register CCR oooocococoooccococoo 56 Core Register Map Summary a nn nan
16. 1ddSHIFTER Get data to write exgd t2 User PC in Temp2 reg braINST_DONE Branch to loop top WRIT ie a 1ddSHIFTER Get data to write exgt3 d User D in Temp3 reg was exg d t2 tp 3 28 braINST_DONE Branch to loop top WRITI 5a x ldxSHIFTER Update X register braINST_DONE Branch to loop top nop Pad to make command take 7 bytes nop WRIT E K ldySHIFTER Update Y register braINST_DONE Branch to loop top nop Pad to make command take 7 bytes nop WRITE_SP ldsSHIFTER Update SP register braINST_DONE Branch to loop top No need to pad last command since we don t index past it COMP_GOTO asla 7x2 asla A reg_code 2 4 jmpa pc Calculated GOTO For More Information On This Product Go to www freescale com S12CPU15UG V1 2 Core User Guide hh hh Q N ec 20 Fh h Q DA Hh hh Q OY 20 Hh H Q 00 w Y b7 Hh Q y ce b7 do 20 d2 b7 d4 20 db f7 de 18 Fh H 10 N LE 20 Hh H O Y fe9 b7 feb 7c fee b7 FFO 20 Fh Fh Fh hh Fh Fh Mh H mh Fh Ss DO pp O 20 fff6 EEEO EL EFES E 21 T2 21 34 Oa 54 06 64 02 74 TE ff 27 EL b2 c3 ff c3 e9 89 a5 24 2 02 00 ff 62 01 10 4 02 si2cpui HABg 5Scale Semiconductor Inc
17. 227 Table 12 6 Mode Pin Setup and Hold Timing 227 Table 12 7 Peripheral Mode Pin Configuration 232 Table 13 1 Breakpoint Mask Bits for First Address 240 Table 13 2 Breakpoint Mask Bits for Second Address Dual Mode 241 Table 13 3 Breakpoint Mask Bits for Data Breakpoints Full Mode 241 Table 14 1 Hardware Commands 000 eee eee eee 255 Table 14 2 Firmware Commands 0000 cece eee eees 256 Table 14 3 Tag Pin Function 0 0 0 e cece eee eee 261 Table 14 4 TTAGO Decoding 00 0c eee eee 265 Table 14 5 RNEXT Decoding 00 00 eee eee 266 Table 15 1 Security Interface Signal Definitions 280 Table A 1 Condition Code State Notation 2 000 285 Table A 2 Register and Memory Notation 220005 286 Table A 3 Address Mode Notation 0000 ce eee eee 287 Table A 4 Operator Notations iras 287 Table A 5 Machine Code Notation 000 0c eee eee 288 Table A 6 Source Form Notation 0200 cee eee 289 Table A 7 CPU Cycle Notation 00 0 cece eee 290 Table C 1 Translated M68HC11 Mnemonics 531 Table C 2 Instructions with Smaller Object Code 532 Table C 3 Comparison of Math Instruction Speeds 539 Table C 4 New HCS12 Instructions 00 0000 eee eee eee 5
18. Figure 11 1 Module Mapping Control Block Diagram Figure 11 2 Module Mapping Control Register Summary Figure 11 3 INITRM Register n annaa ri ar Aa Figure 11 4 INITRG Register 2 0 00 e eee eee eee Figure 11 5 INITEE Register ox sureste eas Figure 11 6 Miscellaneous System Control Register MISC Figure 11 7 Reserved Test Register Zero MTSTO Figure 11 8 Reserved Test Register One MTST1 Figure 11 9 Memory Size Register Zer0 oooooooooooo Figure 11 10 Memory Size Register One 2 000 eee Figure 11 11 Program Page Index Register PPAGE Figure 11 13 Mapping Test Register Zero MTSTO Figure 11 14 Mapping Test Register One MTST1 Figure 12 1 MEBI Block DiagraM oooccccccoocooon oo Figure 12 2 MEBI Register Map Summary 00 085 Figure 12 3 Port A Data Register PORTA ocooooocoooo Figure 12 4 Data Direction Register A DDRA Figure 12 5 Port B Data Register PORTB ocooooooooo Figure 12 6 Data Direction Register B DDRB Figure 12 7 Port E Data Register PORTE ocooooooooo Figure 12 8 Data Direction Register E DDRE Figure 12 9 Port E Assignment Register PEAR Figure 12 10 MODE Register MODE 0 055 Figure 12 11 Pullup Con
19. 12CPU15UG V1 2 e point lt point2 e The sloping sides of the trapezoid meet at or above FF Each system input such as temperature has several labels such as cold cool normal warm and hot Each label of each system input must have a membership function to describe its meaning in an unambiguous numerical way Typically there are three to seven labels per system input but there is no practical restriction on this number as far as the fuzzification step is concerned B 5 2 Abnormal Membership Function Definitions In the HCS12 CPU it is possible and proper to define crisp membership functions A crisp membership function has one or both sides vertical infinite slope Since the slope value 00 is not used otherwise it is assigned to mean infinite slope to the MEM instruction Although a good fuzzy development tool does not allow the user to specify an improper membership function it is possible to have program errors or memory errors which result in erroneous abnormal membership functions Although these abnormal shapes do not correspond to any working systems understanding how the HCS12 CPU treats these cases can be helpful for debugging 4 GRAPHICAL REPRESENTATION FF E0 co DEGREE OF TRUTH 40 20 00 SLOPE_2 SLOPE_1 POINT_1 00 10 20 30 40 50 60 70 80 90 A0 BO CO Do EO FO FF POINT_2 lt INPUT RANGE z gt MEMORY REPRESENTATION ADD
20. 16 bit wide Read Data Bus input to the Core from the system peripherals via the I P Bus Interface block 7 2 1 3 16 bit Read Data Bus from on chip RAM ram_rdb_L12 15 0 16 bit wide Read Data Bus input to the Core from the on chip RAM memory block 7 2 1 4 16 bit Read Data Bus from on chip EEPROM ee_rdb_L12 15 0 16 bit wide Read Data Bus input to the Core from the on chip EEPROM memory block 7 2 1 5 16 bit Read Data Bus from on chip Flash EEPROM or ROM fee_rdb_L12 15 0 16 bit wide Read Data Bus input to the Core from the on chip Flash EEPROM or ROM memory block 7 2 1 6 Core 16 bit Write Data Bus core_wdb_t4 15 0 This 16 bit wide Core output provides the Core Write Data Bus to the system memory and peripheral blocks For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc 7 2 1 7 Core Read Write signal core_rw_t2 This single bit Core output indicates the direction of bus access read or write with write being active low by the Core 7 2 1 8 Core bus data size request indicator core_sz8_t2 This single bit Core output indicates the size of data 8 bit or 16 bit when high or low respectively being read written by a Core bus access 7 2 1 9 Core Expanded Mode indicator core_exp_t2 This single bit Core output indicates that the Core is in Expanded Mode i e the Core has been configured in one of the expanded modes via the MODE pins 7 2 1 10 Core
21. CCR imm gt CCR Performs a logical inclusive OR of the value in the CCR and an immediate value Puts the result in the CCR CCR bits that correspond to 1s in M are set No other CCR bits change NOTE The X bit cannot be set by any software instruction A condition code bit is set if the corresponding bit was 1 before the operation or if the corresponding bit in the instruction provided mask is 1 The X bit cannot be set by any software instruction Address Machine Source Form Mode Code Hex CPU Cycles ORCC opr8i IMM 14 ii P For More Information On This Product Go to www freescale com PSHA SP 0001 SP A gt Msp Operation CCR Effects Code and CPU Cycles Decrements SP by one and loads the value in A into the address to which SP points Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine Complementary pull instructions can be used to restore the saved Freescale Semiconductor WOE Guide Push A onto Stack CPU registers just before returning from the subroutine Source Form Address Machine Mode Code Hex CPU Cycles PSHA INH 36 Os For More Information On This Product Go to www freescale com 12CPU15UG V1 2 PSHA Core User Guide si2cpu A A8gscale Semiconductor Inc PSHB Push B onto Stack PSHB Operation CCR Effects Code and CPU Cycles SP 0
22. LS R D Logical Shift Right D LS R D Operation o gt b7 b6 bs b4 p3 b2 bt bo gt b7 b6 b5 b4 o8 be bt bo A B Shifts all bits of D one place to the right Loads D15 A7 with 0 Loads the C bit from DO BO CCR Effects S XH I N ZV C N Cleared Z Set if result is 0000 cleared otherwise V DO set if after the shift operation C is set cleared otherwise C DO set if the LSB of D was set before the shift cleared otherwise Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex LSRD INH 49 O For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc MAXA Maximum in A MAXA Operation CCR Effects Code and CPU Cycles MAX A M gt A Subtracts an unsigned 8 bit value in M from an unsigned 8 bit value in A to determine which is larger Puts the larger value in A If the values are equal the Z bit is set If the value in M is larger the C bit is set when the value in M replaces the value in A If the value in A is larger the C bit is cleared MAXA accesses memory with indexed addressing modes for flexibility in specifying operand addresses Autoincrement and autodecrement functions can facilitate finding the largest value in a list of values S X H I N Z V C a a a a N Set if MSB of result is set cleared otherwise Z Set if result is 00 clear
23. This 8 bit wide output from the Core provides the Port B data output to the system port pad logic for Port B 12 2 1 9 Port B output buffer enable from Core core_pbobe 7 0 This 8 bit wide output from the Core provides the bit by bit output buffer enable signal to the system port pad logic for Port B 12 2 1 10 Port B input buffer enable from Core core_pbibe_t2 This single bit output from the Core provides the input buffer enable signal to the system port pad logic for Port B 12 2 1 11 Port B pullup enable from Core core_pbpue_t2 When asserted logic 1 this single bit output from the Core indicates that the pullup devices within the system port pad logic for Port B should be enabled for all Port B pins 12 2 1 12 Port B drive strength enable from Core core_pbdse_t2 This single bit output from the Core indicates whether all Port B pins will operate with full or reduced drive strength For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 12 2 1 13 Port E Input Data to Core core_peind 7 0 This 8 bit wide input to the Core provides the Core with the input data from the system port pad logic for Port E When the system has an external IRQ pin implemented the input signal from the IRQ pin pad logic must be tied to Port E Input Data Bit 1 Likewise when the system has an external XIRQ pin implemented the input signal from the XIRQ pin pad logic must be t
24. ooooocccoooccco eee Multiply and Accumulate Instructon co 247 be AAA Table Interpolation Instructions s es 0600 cee Brea AMIS UGH ONS i yee sea oleae A Sieh Oh MA ON BNE Roe perso Jump and Subroutine Instructions 00 ccc eee Interrupt INSIMUICHONS irie te 81s toa Beh ate eee ete et eet ee a Index Manipulation Instructions xr AE A Mentone ee eis Stacking INSIMICHONG re enegie tomei Shed dn aewes ont a E ee Load Effective Address Instructions 0 0c eee eee eee Condition Code NStTUCHONS gt citer E aie ed eed a Mod ele Sng we es STOP and WAI INSUUCHONS ty fi scone Bye efi d ae Bod aS Sie o keane wa ene De OR Roe For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide S12CPU15UG V1 2 4 3 25 Background Mode and Null Operation Instructions o ooocoooooo o 91 44 High Level Language Support sei E watever ed oo Rae ee ee wets 92 4 4 1 AA A toni a6 Oe O II fe 8 Bk 92 4 4 2 Parameters and Variables esti y eater beats band aj eae sues 92 4 4 3 Increment and Decrement Operators 00 000 cee eee eee 94 4 4 4 Higher Math FUNCIONS eransten tinaa 4hute mane ass 94 4 4 5 Conditional lf COMMS HOTS rest ek TA MR aad ieee eR ar een SS E iA 94 4 4 6 Case and Switch Statements ecuacion 95 4 4 7 POSES sgt oie bee BR Ae i hoe hoe epee a Met de ole Siar te ed oe eo do AE AE Sad 95 4 4 8 A A O 95 4 4 9 Instruction Set Orthogonality ooooooo
25. siocpuimtaRscale Semiconductor Inc Read anytime Write anytime These bits determine which test register is selected on a read or write The hexadecimal value written here will be the same as the upper nibble of the lower byte of the vector selects That is an F written into ADR3 ADRO will select vectors FFFE FFFO while a 7 written to ADR3 ADRO will select vectors FF7E FF70 10 3 2 Interrupt Test Registers Address 0016 Bit 7 6 5 4 3 2 1 Bit 0 Read INTE INTC INTA INT8 INT6 INT4 INT2 INTO Write Reset 0 0 0 0 0 0 0 0 Figure 10 4 Interrupt TEST Registers ITEST Read Only in special modes Reads will return either the state of the interrupt inputs of the Interrupt sub block WRTINT 0 or the values written into the TEST registers WRTINT 1 Reads will always return zeroes in normal modes Write Only in special modes and with WRTINT 1 and CCR mask 1 INTE INTO Interrupt TEST bits These registers are used in special modes for testing the interrupt logic and priority independent of the system configuration Each bit is used to force a specific interrupt vector by writing it to a logic one state Bits are named with INTE through INTO to indicate vectors FFxE through FFx0 These bits can be written only in special modes and only with the WRTINT bit set logic one in the Interrupt Test Control Register ITCR In addition I interrupts must be masked using the I bit in the CCR In this
26. 1 Target clock cycles are cycles measured using the target system s serial clock rate See 14 4 6 and 14 3 1 for information on how serial clock rate is selected For More Information On This Product Go to www freescale com Core User Guide si2cPu Rf Scale Semiconductor Inc 14 4 6 BDM Serial Interface The BDM communicates with external devices serially via the BKGD pin During reset this pin is a mode select input which selects between normal and special modes of operation After reset this pin becomes the dedicated serial interface pin for the BDM The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see 14 3 1 This clock will be referred to as the target clock in the following explanation The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time This falling edge is sent for every bit whether data is transmitted or received Data is transferred most significant bit MSB first at 16 target clock cycles per bit The interface times out if 512 clock cycles occur between falling edges from the host The BKGD pin is a pseudo open drain pin and has an weak on chip active pull up that is enabled at all times It is assumed that there is an external pullup and that drivers connected to BKGD do not typically drive the high level Since R C rise time could be unacceptably long the target sys
27. Address Name Bit 7 6 5 4 3 2 1 Bit 0 goooo PORTA 9 Bitz 6 5 4 3 2 1 Bit O write 0001 Porta 4 pit7 6 5 4 3 2 1 Bit 0 write 0002 DDRA 4 Bitz 6 5 4 3 2 1 Bit O write 0003 DDRB 9 Bitz 6 5 4 3 2 1 Bit O write 0004 Reserved 24 0 0 9 y 0 E write EAS SANS PE PES 0005 Reserved read E 0 0 0 2 y 0 write Sa ares ar a A 0006 Reserved SA 9 E 0 g 0 0 g 9 write SS SSS a 0007 Reserved 24 0 0 9 9 0 y write Pa ees a eee 0008 Porte Bitz 6 5 4 3 2 1 BILD write 0009 DDRE 89 Bity 6 5 4 3 2 y write 000A PEAR a NOACCE PIPOE NECLK LSTRE RDWE 9 9 000B MODE oe MODC MODB MODA t IVIS 9 EMK EME 000C PUCR E PUPKE 0 0 PUPEE 0 0 PUPBE PUPAE 000D RDRIV des RDPK g 0 RDPE 0 g RDPB RDPA 000E EBIcTL O84 E 0 0 g ESTR write aS SSS E See 000F Reserved 24 0 L 0 a 9 0 y 0 write Penn ban AA gooie track 39 irae IRQEN 0 0 e g g E write SSS Lee PS SS ES 0032 Portk 4 opit7 6 5 4 3 2 1 Bit O write 0033 DDRK 4 gy 6 5 4 3 2 1 Bit O write Unimplemented X Indeterminate Figure 12 2 MEBI Register Map Summary For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc 12 3 1 Port A Data Register PORTA Address Base 0 BIT 7 6 5 4 3 2 1 BIT O Read Bit 7 6 5 4 3 2 1 Bit O Write Reset Single Chip PA7 PA6 PA5 PA4 PA3 PA2 PA1 PAO Exp Wide Emul Nar AB AB A
28. Bkov3 BKov2 BKovi BKOVO Write Re 0 0 0 0 0 0 0 0 set Reserved or unimplemented Figure 13 5 Breakpoint First Address Expansion Register BKPOX This register contains the data to be matched against expansion address lines for the first address breakpoint when a page is selected BKOVJ 5 0 Value of first breakpoint address to be matched in memory expansion space For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 13 3 4 Breakpoint First Address High Byte Register BKPOH Read anytime Write anytime Address 002B Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 Write ne 0 0 0 0 0 0 0 0 set Figure 13 6 Breakpoint First Address High Byte Register BKP0H This register is used to set the breakpoint when compared against the high byte of the address 13 3 5 Breakpoint First Address Low Byte Register BKPOL Read anytime Write anytime Address 002C Bit 7 6 5 4 3 2 1 Bit O Read Bit 7 6 5 4 3 2 1 Bit O Write Re 0 0 0 0 0 0 0 0 set Figure 13 7 Breakpoint First Address Low Byte Register BKPOL This register is used to set the breakpoint when compared against the low byte of the address 13 3 6 Breakpoint Second Address Expansion Register BKP1X Read anytime Write anytime For More Information On This Product Go to www freescale com Core User Guide si2cpu R
29. CCR Effects Code and CPU Cycles si2cpu A A8gscale Semiconductor Inc Increment Y N y Y 0001 gt Y Adds one to Y LEAY 1 Y can produce the same result but LEAY does not affect the Z bit Although the LEAY instruction is more flexible INY requires only one byte of object code S X H I N Z V C Z Set if result is 0000 cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 JMP Jump JMP Operation Subroutine address PC Jumps to the instruction stored at the effective address The effective address is obtained according to the rules for extended or indexed addressing CCR Effects S XH I N ZV C Code and CPU Source Form Se code HO CPU Cycles Cycles JMP opr16a EXT 06 hh 11 PPP JMP oprx0_xysppc IDX 05 xb PPP JMP oprx9 xysppc IDX1 05 xb ff PPP JMP oprx16 xysppc IDX2 05 xbee ff fPPP JMP D xysppc D IDX 05 xb fIfPPP JMP oprx16 xysppc IDX2 05 xbee ff IfPPP For More Information On This Product Go to www freescale com Core User Guide JSR Operation CCR Effects Code and CPU Cycles si2cpu A A8gscale Semiconductor Inc Jump to Subroutine J S R SP 0002 SP RTNg RTN gt Msp Msp 1 Subroutine address PC Sets up conditions to return to normal program flow t
30. Case and switch statements and computed GOTOs can use PC relative indexed indirect addressing to determine which path to take Depending upon the situation cases can use either the constant offset variation or the accumulator D offset variation of indexed indirect addressing 4 4 7 Pointers The HCS12 supports pointers with direct arithmetic operations on the 16 bit index registers LEAS LEAX and LEAY instructions and with indexed indirect addressing modes 4 4 8 Function Calls Bank switching is a common way of adapting a CPU with a 16 bit address bus to accommodate more than 64K bytes of program memory space One of the most significant drawbacks of this technique is the requirement of masking interrupts while the bank page value is being changed Another problem is that the physical location of the bank page register can change from one system to another or even due to a change to mapping controls by a user program In these situations an operating system program has to keep track of the physical location of the page register The HCS12 addresses both of these problems with the uninterruptible CALL and return from call RTC instructions The CALL instruction is similar to a JSR instruction except that the programmer supplies a destination page value as part of the instruction When CALL executes the old page value is saved on the stack and the new page value is written to the bank page register Since the CALL instruction is uninterrupt
31. Core User Guide s12cpu af Scale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Section 15 Secured Mode of Operation This section provides a brief description of the secured mode of operation of the Core Detailed information relating to integration issues is provided in the HCS12 V1 5 Core Integration Guide 15 1 Overview The implementation of the secured mode of operation for the Core provides for protecting the contents of internal on chip memory arrays While in secured mode the system can execute in single chip mode or from an external memory block but the contents of the internal memory will not be accessible and all normal BDM functions will be blocked from execution A mechanism is provided to release the system from the secured mode at which time normal operation will resume allowing the system to be reconfigured for unsecured mode 15 1 1 Features The secured mode of operation provides e Protection of internal on chip Flash EEPROM contents e Protection of internal on chip EEPROM contents e Operation in single chip mode while secured e Operation from external memory with internal Flash and EEPROM disabled while secured For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc 15 1 2 Block Diagram A block diagram of the Core security implementation is given
32. D M M 1 gt M M 1 Subtracts an unsigned 16 bit value in M M 1 from an unsigned 16 bit value in D to determine which is larger Puts the larger value in M M 1 If the values are equal the Z bit is set If the value in M M 1 is larger the C bit is set If the value in D is larger the C bit is cleared when the value in D replaces the value in M M 1 EMAXM accesses memory with indexed addressing modes for flexibility in specifying operand addresses Autoincrement and autodecrement functions can facilitate controlling the values in a list of values S X H I N Z V C 4 4 4 a4 N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V D15 e M15 e R15 D15 M15 e R15 set if the operation produces a two s complement overflow cleared otherwise C D15 e M15 M15 R15 R15 e D15 set if M M 1 is larger than D cleared otherwise Condition code bits reflect internal subtraction R D M M 1 Address Machine Source Form Mode Code Hex CPU Cycles EMAXM oprx0_xysppc IDX 18 1E xb ORPW EMAXM oprx9 xysppc IDX1 18 1E xb ff ORPWO EMAXM oprx16 xysppc IDX2 18 1E xb ee ff OfRPWP EMAXM D xysppc D IDX 18 1E xb OfTERPW EMAXM oprx16 xysppc IDX2 18 1E xb ee ff OfIPRPW For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 EMIND Extended Minimum in D EMIN
33. E A A A H B3 M3 M3 e R3 R3 e B3 set if there is a carry from bit 3 cleared otherwise N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V B7 e M7 e R7 B7 M7 e R7 set if the operation produces a two s complement overflow cleared otherwise C B7 M7 M7 e R7 R7 e B7 set if there is a carry from the MSB of the result cleared otherwise Code and CPU Source Form Araba a E CPU Cycles Cycles ADCB opr8i IMM C9 ii P ADCB opr8a DIR D9 dd rPf ADCB opr16a EXT F9hh 11 rPo ADCB oprx0_xysppc IDX E9 xb rPf ADCB oprx9 xysppc IDX1 E9 xb ff rPO ADCB oprx16 xysppc IDX2 E9 xb ee ff frPP ADCB D xysppc D IDX E9 xb fIfrPf ADCB oprx16 xysppc IDX2 E9 xb ee ff IPrbf For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 ADDA Addo ADDA Operation CCR Effects Code and CPU Cycles A M A or A imm gt A Adds either the value in M or an immediate value to the value in A and places the result in A This instruction affects the H bit so it is suitable for use in BCD arithmetic operations see DAA instruction for additional information A3 M3 M3 e R3 R3 e A3 set if there is a carry from bit 3 cleared otherwise Set if MSB of result is set cleared otherwise Set if result is 00 cleared otherwise A7e M7 R7 A7 e M7 e R7 se
34. FF A current crisp input value X points at 4 data bytes P1 P2 S1 S2 ofa trapezoidal membership function Y points at fuzzy input RAM location Special OrPw OrPwO OfrPwP OfIfrPw OfIPrPw MINA oprx0_xysppc MINA oprx9 xysppc MINA oprx16 xysppc MINA D xysppc MINA oprx16 xysppc MINM oprx0_xysppc MINM oprx9 xysppc MINM oprx16 xysppc MINM D xysppc MINM oprx16 xysppc Minimum in A put smaller of 2 unsigned 8 bit values in A MIN A M gt A N Z V C bits reflect result of internal compare A M Minimum in N put smaller of two unsigned 8 bit values in M MIN A M gt M N Z V C bits reflect result of internal compare A M For More Information On This Product Go to www freescale com OrPf OrPO OfrPP OfIfrPf OfIPrPf OrPw OrPwO OfrPwP OfIfrPw OfIPrPw Freescale Semiconductor ING cuide s12cPuU15UG V1 2 Address Machine Source Form Operation Mode Coding Hex Access Detail SXHINZVC MOVB opr8 opr16a Move byte IMM EXT 18 0B ii MOVB opr8i oprx0_xysppc Memory to memory 8 bit byte move IMM IDX 18 08 x MOVB opr16a opr16a M1 Mo EXT EXT 18 0Ch MOVB opr16a oprx0_xysppc First operand specifies byte to move EXT IDX 18 09 x MOVB oprx0_xysppc opr16a IDX EXT 18 0D x MOVB oprx0_xys
35. JaTa o TBL oprx0_xysppc Table lookup and interpolate 8 bit 18 3D xb ORff P M B x M 1 M A TBNE abdxysp rel9 Test and branch if not equal to 0 PPP branch If counter x0 then PC 2 rel gt PC PPO no branch TFR abcdxysp abcdxysp Transfer from register to register r1 r2r1 and r2 same size 00 r1 r2r1 8 bit r2 16 bit r1 gt r2r1 16 bit r2 8 bit TPASame as TFRCCR A Transfer CCR to A CCR gt A For More Information On This Product Go to www freescale com Core User Guide siocpuimtaRscale Semiconductor Inc Source Form Operation TRAP trapnum Trap unimplemented opcode SP 2 gt SP RTNy RTN_ gt Msp Mspy1 SP 2 gt 8P Yu YL Mgp Mgp41 SP 2 gt SP Xy X gt Msp Msp 1 SP 2 gt 8SP B A gt Mgp Mgp 4 SP 1 SP CCR Mgp 11 trap vector PC TST opr16a Test M M 0 TST oprx0_xysppc TST oprx9 xysppc TST oprx16 xysppc TST D xysppc TST oprx16 xysppc TSTA TSTB TSXSame as TFR SP X Test A A 0 Test B B 0 Transfer SP to X SP gt X TSYSame as TFR SP Y Transfer SP to Y SP gt Y TXSSame as TFR X SP Transfer X to SP X SP TYSSame as TFR Y SP Transfer Y to SP Y gt SP Wait for interrupt SP 2 gt SP RTNy RTN gt Mgp Mgp 4 SP 2 gt SP VYy Y gt Msp Msp 1 SP 2 gt SP Xy X_ gt Msgp Mgp 4 SP 2 gt SP B A gt Msp Msp 1 SP 1 SP CCR Mgp Addr
36. Performs logical inclusive OR of the value in A and either the value in M or an immediate value Puts the result in A S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Machine Source Form Code Hex CPU Cycles ORAA opr8i 8A ii ORAA opr8a 9A dd ORAA opr16a BA hh 11 ORAA oprx0_xysppc AA xb ORAA oprx9 xysppc AA xb ff ORAA oprx16 xysppc AA xb ee ff ORAA D xysppc AA xb ORAA oprx16 xysppc AA xb ee ff For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 ORAB OR Accumulator B ORAB Operation CCR Effects Code and CPU Cycles B 1 M gt B or B l imm gt B Performs logical inclusive OR of the value in B and either the value in M or an immediate value Puts the result in B S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Machine Coding Source Form Hex CPU Cycles ORAB opr8i CREL ORAB opr8a DA dd ORAB opr16a FA hh 11 ORAB oprx0_xysppc EA xb ORAB oprx9 xysppc EA xb ff ORAB oprx16 xysppc EA xb ee ff ORAB D xysppc EA xb ORAB oprx16 xysppc EA xb ee ff For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc ORCC OR COR ORCC Operation CCR Effects Code and CPU Cycles
37. X X gt M M 1 Stores the high byte of X in M and the low byte in M 1 CCR Effects S XH I N ZV C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V Cleared Code and CPU Source Form Code Hex CPU Cycles Cycles STX opr8a STX opr16a STX oprx0_xysppc STX oprx9 xysppc STX oprx16 xysppc STX D xysppc STX oprx16 xysppc For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPuU15UG V1 2 STY Store Y STY Operation Yy Y gt M M 1 Stores the high by of Y in M and the low byte in M 1 CCR Effects S XH I N ZV C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V Cleared Code and CPU Source Form Code Hex CPU Cycles Cycles STY opr8a STY opr16a STY oprx0_xysppc STY oprx9 xysppc STY oprx16 xysppc STY D xysppc STY oprx16 xysppc For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc SUBA Subtract from A SUBA Operation CCR Effects Code and CPU Cycles A M gt A or A imm gt A Subtracts either the value in M or an immediate value from the value in A Puts the result in A The C bit represents a borrow S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V A7e M7 e R7
38. X A MIN A IN2 MINA 1 X A MIN A IN3 MINA 1 X A MIN A IN4 so A holds smallest input MAXM rX OUT1 MAX A OUT1 and A is unchanged MAXM ay OUT1 MAX A OUT2 A still has min input Before this sequence is executed the fuzzy outputs must be cleared to zeros not shown M68HC11 MIN or MAX operations are performed by executing a compare followed by a conditional branch around a load or store operation These instructions can also be used to limit a data value prior to using it as an input to a table lookup or other routine Suppose a table is valid for input values between 20 and 7F An arbitrary input value can be tested against these limits and be replaced by the largest legal value if it is too big or the smallest legal value if too small using the following two HCS12 instructions HILIMIT FCB STE comparison value needs to be in mem LOWLIMIT FCB 20 so it can be referenced via indexed MINA HILIMIT PCR A MIN A 7F MAXA LOWLIMIT PCR A MAX A 20 A now within the legal range 20 to 7F The PCR notation is also new for the HCS12 This notation indicates the programmer wants an appropriate offset from the PC reference to the memory location HILIMIT or LOWLIMIT in this example and then to assemble this instruction into a PC relative indexed MIN or MAX instruction C 7 7 Fuzzy Logic Support The HCS12 includes four instructions MEM REV REVW and WAV specifically designed to suppor
39. gt B SP 0001 SP Loads B from the address to which SP points Then increments SP by one Pull instructions are commonly used at the end of a subroutine to restore the contents of CPU registers that were pushed onto the stack before subroutine execution S X H I N Z V C Address Machine Source Form Mode Code Hex CPU Cycles PULB INH 33 ufo For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 p U LC Pull CCR from Stack P U LC Operation CCR Effects Code and CPU Cycles Msp CCR SP 0001 SP Loads CCR from the address to which SP points Then increments SP by one Pull instructions are commonly used at the end of a subroutine to restore the contents of CPU registers that were pushed onto the stack before subroutine execution S X H I N Z V C a t a a a ala a Condition codes take on the value pulled from the stack except that the X mask bit cannot change from 0 to 1 Software can leave the X bit set leave it cleared or change it from 1 to 0 but it can only be set by a reset or by recognition of an XIRQ interrupt Address Machine For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc p U L D Pull D from Stack P U L D Operation CCR Effects Code and CPU Cycles Msp Msp 1 gt A B
40. peri_clk34 yy Figure 7 2 Basic 8 bit Peripheral Read Timing peri_clk24 TRIS TATU TA AA V VYA VY VAYA core_ab_t2 addr0X_addrt peri_rdb_L12 data0 K data1 K data2 data3 core_perisel_t2 E FNO O A O O core A So Awa S Aaa S Aa core_sz8_t2 16 BIT 16 BIT 16 BIT peri_clk34 o Figure 7 3 Basic 16 bit Peripheral Read Timing 7 3 1 2 Memory Reads The timing relationship for a basic 8 bit read of a on chip memory register or array byte by the Core is shown in below in Figure 7 4 and that of a basic 16 bit read in Figure 7 5 In the diagrams the MEM_rdb_L12 signal represents any of the on chip memory read data bus signals ram_rdb_L12 ee_rdb_L12 or fee_rdb_L12 and core_MSEL_ 12 represents any of the on chip memory register or array selects such as core_ramregsel_t2 or core_ramarraysel_t2 for the RAM and likewise for the EEPROM and Flash EEPROM For More Information On This Product Go to www freescale com Core User Guide si2cpu Rf Scale Semiconductor Inc peri_clk24 PTA TO TATI TA AS A AA core_ab_t2 addrO _addr1 MEM_rdb_L12 data0 X data1 X data2 data3 core_MSEL_t2 T R O OS A IS A core_rw_t2 a E AE TIAS a A e lt a core_sz8_t2 8 BIT 8B B8BT A peri_clk34 j j W Figure 7 4 Basic 8 bit Memory Read Timing peri_clk24 TOS TAUTA A V V V V VUV core_ab_t2 addrOX addrt MEM
41. 0 All Port B output pins have full drive enabled RDPA Reduced Drive of Ports A 1 All Port A output pins have reduced drive enabled 0 All Port A output pins have full drive enabled For More Information On This Product Go to www freescale com Core User Guide si2cru ERA Scale Semiconductor Inc 12 3 11 Extemal Bus Interface Control Register EBICTL Address Base E BIT 7 6 5 4 3 2 1 BITO Read 0 0 0 0 0 0 ESTR Write Reset 0 0 0 0 0 0 0 0 ii Reset 0 0 0 0 0 0 0 4 All other modes all Unimplemented Figure 12 13 External Bus Interface Control Register EBICTL Read anytime provided this register is in the map Write refer to individual bit descriptions below The EBICTL register is used to control miscellaneous functions i e stretching of external E clock This register is not in the on chip map in peripheral mode ESTR E clock Stretches This control bit determines whether the E clock behaves as a simple free running clock or as a bus control signal that is active only for external bus cycles Normal and Emulation write once Special write anytime 1 E stretches high during stretch cycles and low during non visible internal accesses 0 E never stretches always free running This bit has no effect in single chip modes 12 3 12 IRQ Control Register IRQCR Address Base 1E Bit 7 6 5 4 3 2 1 Bit O IRQE IRQEN Write Reset 0 1 0 0 0 0 0 0 Figure 12 14 IRQ Control Regi
42. 1 SP Decrement SP SP 1 SP IDX 1B 9F Pf A O O O O O O E DEX Decrement X X 1 X INH 09 O 11H N G DEY Decrement Y Y 1 Y INH 03 O Tal_ _ EDIV Extended divide unsigned 32by16 INH 11 ffffffffffo J TATATATA to 16 bit Y D X Y remainder gt D For More Information On This Product Go to www freescale com Core User Guide siocpuimtaRscale Semiconductor Inc Source Form EDIVS Operation Extended divide signed 32 by 16 to 16 bit Y D X gt Y remainder gt D Address Mode INH Machine Coding Hex Access Detail Offffffffffo0 SXHINZVC EMACS opr16a EMAXD oprx0_xysppc EMAXD oprx9 xysppc EMAXD oprx16 xysppc EMAXD D xysppc EMAXD oprx16 xysppc Extended multiply and accumulate signed Mx Myx 1 x My My 1 M M 3 M M 3 16 by 16 to 32 bit Extended maximum in D put larger of 2 unsigned 16 bit values in D MAX D M M 1 gt D N Z V C bits reflect result of internal compare D M M 1 Special IDX IDX1 IDX2 D IDX IDX2 D D x x ORROf f fRR WWP ORP ORPO OfRPP OfIfRP OfIPRP EMAXM oprx0_xysppc EMAXM oprx9 xysppc EMAXM oprx16 xysppc EMAXM D xysppc EMAXM oprx16 xysppc Extended maximum in M put larger of 2 unsigned 16 bit values in M MAX D M M 1 gt M M 1 N Z V C bits reflect result of internal compare D
43. 4 3 18 4 3 19 4 3 20 4 3 21 4 3 22 4 3 23 4 3 24 INSTRUCTION TYPOS Pas op aA aK cul oO OID e Gee te De tae tte NE e A Address WMOUGES erresetan na ees tiie Ses we cee eek Ge ae Ea ead ed act Effective Address oe line e bes Aarts Due dira aaa Sola da a eRe OO Inherent Addressing Mode vortic ca ad A oh o4 Immediate Addressing Mode oocoocccoccco eee Direct Addressing Mod s scort td is Extended Addressing Mode ia a A Relative Addressing Mod6 222 2 instcekcne AAA ee Indexed Addressing Modes ot ese eset ew ted ed listada Instructions Using Multiple Modes Ica od bs Wee wes Os es Instruction Descriptions se da O eee is o CA eae Dee A Lees Load and Store Instructions sassa lt ie Moe ees ree Transfer and Exchange Instructions naaa anaa eea Move INSTUCIONS Date ereti tee ee ke Pad das Ot AAA Add and Subtract Instructions A A Binary Coded Decimal Instructions 0 2 0c c eee eee Decrement and Increment Instructions 0 000 eee eee Compare and Test Instructions cuca Boolean Logic Instructions 0 00 ds ee Clear Complement and Negate Instructions ooooooooooooooo Multiply and Divide Instructions s s s anann 000 eee ee Bit Test and Bit Manipulation Instructions 0000 cee eee Shift and Rotate Instructions 2 ui IA EI a as ohn ree ae ge Fuzzy LOGIC INSIMICHONS 20 tera ed Oho eee ee bea eee e Maximum and Minimum Instructions
44. 6 n a ns 7 Address valid time to E rise PW_ Tap 12 10 ns 8 Muxed address hold time 2 1 ns 9 Address hold to data valid 3 2 ns o foros ET fs EC EF e resonar f fet fe fe es 15 Write data setup time PWey topw tosw 16 ns 17 Read write valid time to E rise PWe trwp tRwv 16 ns 20 Low strobe valid time to E rise PWe t sp tLsv 16 ns 21 Low strobe hold time tLsH 2 2 1 ns 22 Address access time t yo tan tpsr tacca 36 30 24 ns 23 E high access time PWgp tpsp tacce 14 12 10 ns 26 Chip select delay time tcsp 22 18 15 ns 27 Chip select access time tey tesp tosr taccs 26 22 17 ns 28 Chip select hold time tcsH 1 1 1 ns 29 Chip select negated time tcsn 12 10 8 ns For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPuU15UG V1 2 NOTES 1 Crystal input is required to be within 45 to 55 duty 2 Reduced drive must be off to meet these timings 3 Unequal loading of pins will affect relative timing numbers 4 Affected by clock stretch add N x teye where N 0 1 2 or 3 depending on the number of clock stretches 7 3 4 General Internal Read Visibility Timing Internal writes have the same timing as external writes Internal read visibility is shown in Figure 7 15 and Table 7 3 shows the associated timing numbers Muxed Addr Data data read Figure 7 15 General Internal Read Visibility Timing Table 7 3 Expansion Bus
45. 6 pa aay pagel TMP3 gt Y D gt Y X Y Y gt Y SP Y 7 sexA gt SP sexB SP sex CCR gt SP IMP3 gt SP DSP XSP Y SP SsP SP TMP2 and TMP3 registers are for factory use only Exchanges o RSA iig CERSA 0AN pa Pan oy ee BSR CORB rE aes RES ee aes Bescon conecor ocaso ees 4 00 B gt D aa TMP35D DesD XeD YeD SP amp D 5 per gara TMP35X DeX XOX Yoox SPSX 6 caer see ne oe TMP35Y DeY xo Y Yo Y SPY Se Se er moe For More Information On This Product Go to www freescale com Core User Guide 4 7 Loop Primitive Postbyte Ib Encoding siocpuimtaRscale Semiconductor Inc 00 A 10 A 20 A 30 A 40 A 50 A 60 A 70 A 80 A 90 A A0 A BO A DBEQ DBEQ DBNE DBNE TBEQ TBEQ TBNE TBNE IBEQ IBEQ IBNE IBNE Q Q Q Q Q 01 B 11 B 21 B 31 B 41 B 51 B 61 B 71 B 81 B 91 B At B Bt B DBEQ DBEQ DBNE DBNE TBEQ TBEQ TBNE TBNE IBEQ IBEQ IBNE IBNE 6 6 6 0 0 02 12 22 32 42 52 62 72 82 92 A2 B2 03 13 23 33 43 53 63 73 83 93 A3 B3 04 D 14 D 24 D 34 D 44 D 54 D 64 D 74 D 84 D 94 D A4 D B4 D DBEQ DBEQ DBNE DBNE TBEQ TBEQ TBNE TBNE IBEQ IBEQ IBNE IBNE E E E E E 05 X 15 X 25 X 35 X 45 X 55 X 65 X 75 X 85 X 95 X A5 X BS X DBEQ DBEQ DBNE DBNE TBEQ TBEQ TBNE TBNE IBEQ IBEQ IBNE IBNE E E E E E
46. ADDD D xysppc ADDD oprx16 xysppc NDA opr i NDA opr8a NDA opr16a NDA oprx0_xysppc NDA oprx9 xysppc NDA oprx16 xysppc NDA D xysppc NDA oprx16 xysppc Add to B B M B or B imm gt B Add to D A B M M 1 gt A B or A B imm A B AND with A A e M gt A or Ajeimm gt A P rPf rPO rPf rPO frPP fIfrPf fIPrPf PO RP RPO RP RPO fRPP fIfRP fIPRP P rPf rPO rPf rPO frPP fIfrPf fIPrPf NDB opr i NDB opr8a NDB opr16a NDB oprx0_xysppc NDB oprx9 xysppc NDB oprx16 xysppc NDB D xysppc NDB oprx16 xysppc ANDCC ttopr8i PDD PPP gt DP gt AND with B B e M gt B or B eimm gt B AND with CCR CCR eimm gt CCR P rPf rPO TP E TPO frPP fIfrPf fIPrPf P ASL opr16aSame as LSL ASL oprx0_xysp ASL oprx9 xysppc ASL oprx16 xysppc ASL D xysppc ASL oprx16 xysppc ASLASame as LSLA ASLBSame as LSLB ASLDSame as LSLD Arithmetic shift left M 4 0 C b7 bO Arithmetic shift left A Arithmetic shift left B Arithmetic shift left D My ee rE bare M0 C b7 A bO b7 B bO rPwO rPw rPwO frPwP fIfrPw fIPrPw For More Information On This Product Go
47. Address Base 33 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 Bit 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 12 17 Port K Data Direction Register DDRK Read anytime Write anytime For More Information On This Product Go to www freescale com Core User Guide si2cru ERA Scale Semiconductor Inc This register determines the primary direction for each port K pin configured as general purpose I O This register is not in the map in peripheral or expanded modes while the EMK control bit in MODE register is set DDRK 7 0 The Data Direction Port K 1 Associated pin is an output 0 Associated pin is a high impedance input CAUTION It is unwise to write PORTK and DDRK as a word access If you are changing Port K pins from inputs to outputs the data may have extra transitions during the write It is best to initialize PORTK before enabling as outputs CAUTION To ensure that you read the correct value from the PORTK pins always wait at least one cycle after writing to the DDRK register before reading from the PORTK register 12 4 Operation There are four main sub blocks within the MEBI external bus control external data bus interface control and registers 12 4 1 External Bus Control The external bus control generates the miscellaneous control functions pipe signals ECLK LSTRB and R W that will be sent external on Port E bits 6 2 It also generate
48. After CMPA CMPB CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the CPU register value is greater than the value in M After CBA or SBA the branch occurs if the value in B is greater than the value in A BHI is not for branching after instructions that do not affect the C bit such as increment decrement load store test clear or complement Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction Address Mode Machine Code Hex CPU Cycles Source Form BHI rela PPP branch P no branch Branch Complementary Branch Comment Mnemonic Opcode Test Mnemonic Opcode Test R gt M R lt M or or BHI 22 B gt A BLS 23 B lt A Unsigned C Z 0 C Z R gt M R lt M or or BGT 2E B gt A BLE 2F B lt A Signed Z N V 0 Z N V For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc B H S Branch if Higher or Same B H S same as BCC Operation CCR Effects Code and CPU Cycles If C 0 then PC 0002 rel PC BHS can be used to branch after subtracting or comparing unsigned values After CMPA CMPB CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the C
49. Any positive integer from 1 to 8 for pre post increment decrement Any integer from 16 to 15 Any integer from 256 to 255 Any integer from 32 768 to 65 535 Ene 8 bit value for PPAGE register pag Some assemblers require the symbol before this value rel8 Label of branch destination within 256 to 255 locations rel9 Label of branch destination within 512 to 511 locations Any label within the 64K byte memory space trapnum Any 8 bit integer from 30 to 39 or from 40 to FF xysp Register designator for X or Y or SP Register designator for X or Y or SP or PC For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc 5 4 3 Operation Notation Table 5 4 Operation Notation Add Subtract e AND OR Exclusive OR x Multiply Divide Concatenate Transfer lt Exchange 5 4 4 Address Mode Notation Table 5 5 Address Mode Notation INH Inherent no operands in instruction stream Immediate operand immediate value in instruction stream Direct operand is lower byte of address from 0000 to 00FF Operand is a 16 bit address Two s complement relative offset for branch instructions Indexed no extension bytes includes 5 bit constant offset from X Y SP or PC Pre post increment decrement by 1 8 Accumulator A B or D offset IDX1 9 bit signed offset from X Y SP or PC 1 extens
50. B D X Y or SP Branches to a relative destination if the counter register reaches zero Rel is a 9 bit two s complement offset for branching forward or backward in memory Branching range is 100 to OFF 256 to 255 from the address following the last byte of object code in the instruction Address Machine Source Form Mode Code Hex CPU Cycles 04 lb rr PPP branch IBEQ abdxysp rel9 REL PPO no branch Loop Primitive Postbyte 1b Coding forme postbyte Cage Register Offset IBEQ A rel9 1000 X000 04 80 rr A IBEQ B rel9 1000 X001 04 81 rr B IBEQ D rel9 1000 X100 04 84 rr D Positive IBEQ X rel9 1000 X101 04 85 rr x IBEQ Y rel9 1000 X110 04 86 rr Y IBEQ SP rel9 1000 X111 04 87 rr SP IBEQ A rel9 1001 X000 04 90 rr A IBEQ B rel9 1001 X001 04 91 rr B IBEQ D rel9 1001 X100 04 94 rr D esas IBEQ X rel9 1001 X101 04 95 rr x IBEQ Y rel9 1001 X110 04 96 rr Y IBEQ SP rel9 1001 X111 04 97 rr SP NOTES 1 Bits 7 6 5 select IBEQ or IBNE bit 4 is the offset sign bit bit 3 is not used bits 2 1 0 select the counter register For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc B N E Increment and Branch if Not Equal to Zero B N E Operation counter 1 counter If counter 0 then PC 0003 rel PC Adds one to the counter register A B D X Y or SP Branches to a relative destination if th
51. BRA rel8 Complementary Branch opcode Test mnemonic Opcode Test Comment Mnemonic For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide BRCLR If M mask byte 0 then PC 0002 rel PC Operation CCR Effects Code and CPU Cycles Performs a logical AND of the value in M and the mask value supplied with the instruction Branch if Bit s Clear Branches if all the Os in M correspond to 1s in the mask byte Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction S X H l N Z V C Address Machine Source Form Mode Code Hex CPU Cycles BRCLR opr8a msk8 rel8 DIR 4F dd mm rr rPPP BRCLR opr16a msk8 rel8 EXT 1F hh 11 mm rr rfPPP BRCLR oprx0_xysppc mskg8 rel8 IDX OF xb mm rr rPPP BRCLR oprx9 xysppc msk8 rel8 IDX1 OF xb ff mmrr rfPPP BRCLR oprx16 xysppc mskg8 rel8 IDX2 OF xb ee ff mm rr PrfPPP For More Information On This Product Go to www freescale com 12CPU15UG V1 2 BRCLR Core User Guide si2cpu RR Scale Semiconductor Inc BRN Branch Never BRN Operation PC 0002 PC Never branches BRN is effectively a 2 byte NOP that requires one cycle BRN is included in the instruction set to provide a complement to the BRA instru
52. Code and CPU Cycles Mx Mx D X My My y 1 M M 1 M 2 M 3 gt M 1 M 2 M 3 Multiplies two 16 bit values Adds the 32 bit product to the value in a 32 bit accumulator in memory EMACS is a signed integer operation All operands and results are located in memory X must point to the high byte of the first source operand and Y must point to the high byte of the second source operand An extended address supplied with the instruction must point to the most significant byte of the 32 bit result S X H I N Z V C 4 4 4 4 N Set if MSB of result R31 is set cleared otherwise Set if result is 00000000 cleared otherwise V M31 e 131 e R31 M31 e 131 e R31 set if result is greater than 7FFFFFFF overflow or less than 80000000 underflow indicates two s complement overflow C M15 e115 115 e R15 R15 e M15 set if there is a carry from bit 15 of the result R15 cleared otherwise indicates a carry from low word to high word of the result N Address Machine EMACS opr16a Special 18 12 hh 11 ORRO RREWWP NOTES 1 opr16a is an extended address specification Both X and Y point to source operands For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 EMAXD se cxendedmaximmno EMAXD Operation CCR Effects Code and CPU Cycles MAX D M M 1 gt D Subtracts an unsign
53. For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc TSY Transfer SP to Y TSY same as TFR SP Y Operation SP gt Y Transfers the value in SP to Y The value in SP does not change After a TSY instruction Y points at the last value that was stored on the stack TPY assembles as TFR SP Y CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex TSY INH B7 76 P For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPuU15UG V1 2 TXS Transfer X to SP TXS same as TFR X SP Operation X SP Transfers the value in X to SP The value in X does not change TXS assembles as TFR X SP CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex TXS INH B7 57 P For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc TYS Transfer Y to SP TYS same as TFR Y SP Operation Y gt SP Transfers the value in Y to SP The value in Y does not change TYS assembles as TFR Y SP CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex TYS INH B7 67 P For More Information On This Product Go to w
54. Freescale Semiconductor WOE Guide 12CPU15UG V1 2 7 A 0 7 B O 8 BITACCUMULATORS A AND B 15 D O 16 BIT DOUBLE ACCUMULATOR D A B 15 X 0 INDEX REGISTER X 15 Y 0 INDEX REGISTER Y 15 SP 0 STACK POINTER 15 PC 0 PROGRAM COUNTER SIX H IIN Z V C CONDITION CODE REGISTER CARRY OVERFLOW ZERO NEGATIVE IRQ INTERRUPT MASK DISABLE HALF CARRY FOR BCD ARITHMETIC XIRQ INTERRUPT MASK DISABLE STOP DISABLE IGNORE STOP INSTRUCTION Figure 1 2 Programming Model 1 6 Data Format Summary Following is a discussion of the data types used and their organization in memory for the Core 1 6 1 Data Types The CPU uses the following types of data Bits 5 bit signed integers 8 bit signed and unsigned integers 8 bit 2 digit binary coded decimal numbers 9 bit signed integers 16 bit signed and unsigned integers 16 bit effective addresses For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc e 32 bit signed and unsigned integers NOTE Negative integers are represented in two s complement form Five bit and 9 bit signed integers are used only as offsets for indexed addressing modes Sixteen bit effective addresses are formed during addressing mode computations Thirty two bit integer dividends are used by extended division instructions Extended multiply and ext
55. If Ry FE or FF then read byte Rx Y fuzzy in or out Fy else no bus access If Rx FE and V was 1 reset ACCA to FF If Rx FE toggle V bit 12CPU15UG V1 2 Yes Interrupt pending Ry FF other Read byte 0 X rule element Rx X X 1 point at next rule element Update Fy with value read in cycle 4 0 If Rx FE then A min A Fy else A A no change to A Ry FF end of rules Yes Read program word if 3A misaligned END No bus access Adjust PC to point at current REV instruction No bus access Adjust X X 1 Continue to interrupt stacking Update Fy with value read in cycle 4 0 If Ry FE or FF and ACCA gt Fy then write byte Rx Y else no bus access Figure B 9 REV Instruction Flow Diagram Rule evaluation begins at cycle 2 0 with a byte read of the first element in the rule list Usually this is the first antecedent of the first rule but the REV instruction can be interrupted so this could be a read of any byte in the rule list The X index register is incremented so it points to the next element in the rule list Cycle 3 0 satisfies the required delay between a read and when data is valid to the CPU Some internal For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc CPU housekeeping activity takes place during this cycle but there is no bus activity By cycle 4 0 the rule element that
56. M M 1 IDX IDX1 IDX2 D IDX IDX2 cc al ORPW ORPWO OfRPWP OfIfRPW OfIPRPW EMIND oprx0_xysppc EMIND oprx9 xysppc EMIND oprx16 xysppc EMIND D xysppc EMIND oprx16 xysppc EMINM oprx0_xysppc EMINM oprx9 xysppc EMINM oprx16 xysppc EMINM D xysppc EMINM oprx16 xysppc Extended minimum in D put smaller of 2 unsigned 16 bit values in D MIN D M M 1 gt D N Z V C bits reflect result of internal compare D M M 1 Extended minimum in M put smaller of 2 unsigned 16 bit values in M MIN D M M 1 M M 1 N Z V C bits reflect result of internal compare D M M 1 IDX IDX1 IDX2 D IDX IDX2 IDX IDX1 IDX2 D IDX IDX2 ORP ORPO OfRPP OfIfRP OfIPRP ORPW ORPWO OfRPWP OfIfRPW OfIPRPW EMUL Extended multiply unsigned D x Y Y D 16 by 16 to 32 bit INH ffO EMULS Extended multiply signed D x Y Y D 16 by 16 to 32 bit INH Of0 Of 0 if followed by page 2 instruction EORA opr8i EORA opr8a EORA opr16a EORA oprx0_xysppc EORA oprx9 xysppc EORA oprx16 xysppc EORA D xysppc EORA oprx16 xysppc EORB opr8i EORB opr8a EORB opr16a EORB oprx0_xysppc EORB oprx9 xysppc EORB oprx16 xysppc EORB D xysppc EORB oprx16 xysppc ETBL oprx0_xysppc Before executing ETBL initialize B wit indirect address
57. Mgp 1 gt Yui Yi SP 0004 SP Restores the values of CPU registers CCR B A X PC and Y from the stack The X bit may be cleared as a result of an RTI instruction but cannot be set if it was cleared prior to execution of the RTI instruction If another interrupt is pending when RTI finishes restoring registers from the stack the SP is adjusted to preserve stack content and the new vector is fetched S X H I N Z V C a t a a a ala a Condition codes take on the value pulled from the stack except that the X mask bit cannot change from 0 to 1 Software can leave the X bit set leave it cleared or change it from 1 to 0 but it can only be set by a reset or by recognition of an XIRQ interrupt Address Machine RTI INH uUUUUPPP OB or UUUUUfVE PPP NOTES 1 RTI takes 11 cycles if an interrupt is pending For More Information On This Product Go to www freescale com RTS Operation CCR Effects Code and CPU Cycles Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Return from Subroutine RTS Mgp Mgp 1 gt PCy PCy SP 0002 gt SP Restores the value of PC from the stack and increments SP by two Program execution continues at the address restored from the stack Address Machine Source Form Mode Code Hex CPU Cycles RTS INH 3D UfPPP For More Information On This Product Go to www freescale com Core User Guide SBA Operat
58. Read byte 1 X singleton S Interrupt pending es No No bus access TMP3 TMP3 F No bus access Start multiply PPROD x F No bus access Finish multiply TMP2 TMP2 PPROD No bus access TMP1 TMP1 carry from PPROD add B 0 Yes Adjust PC to point at next instruction Y D TMP1 TMP2 X TMP3 END Write word 2 SP stack TMP3 Write word 2 SP stack TMP2 Write word 2 SP stack TMP1 SP SP 2 Adjust PC to point at 3C wavr pseudoinstruction Continue to interrupt stacking Figure B 11 WAV and wavr Instruction Flow Diagram The resume sequence includes recovery of the temporary registers from the stack 1 1 through 5 0 and reads to get the operands for the current iteration The normal WAV flow is then rejoined at cycle 6 0 Upon normal completion of the instruction cycle 10 0 the PC is adjusted so it points to the next instruction The results transfer from the TMP registers into CPU registers in such a way that the EDIV For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 instruction can divide the sum of products by the sum of weights TMP1 TMP2 transfers into Y D and TMP3 transfers into X B 8 Custom Fuzzy Logic Programming The basic fuzzy logic inference techniques described above are suitable for a broad range of applications but some systems may require customiz
59. The Program Page Index Register allows for integrating up to 1M byte of Flash EEPROM or ROM into the system by using the six page index bits to page 16K byte blocks into the Program Page Window located from 8000 to BFFF as defined in Table 11 6 below CALL and RTC instructions have a special single wire mechanism to read and write this register without using the address bus NOTE Normal writes to this register take one cycle to go into effect Writes to this register using the special single wire mechanism of the CALL and RTC instructions will be complete before the end of the associated instruction PIX5 PIXO Program Page Index Bits 5 0 These six page index bits are used to select which of the 64 Flash EEPROM or ROM array pages is to be accessed in the Program Page Window as shown in Table 11 6 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Table 11 6 Program Page Index Register Bits Program Space Selected 16K page 0 16K page 1 16K page 2 16K page 3 16K page 60 16K page 61 1 1 1 1 1 0 16K page 62 1 1 1 1 1 1 16K page 63 11 4 Operation The MMC sub block performs four basic functions of the Core operation bus control address decoding and select signal generation memory expansion and security decoding for the system Each aspect is described in the subsections following 11 4 1 Bus Control The MM
60. The pins operate independently that is the state of one pin does not affect the function of the other The presence of logic level 0 on either pin at the fall of the external clock ECLK performs the indicated function High tagging is allowed in all modes Low tagging 1s allowed only when low strobe is enabled LSTRB is allowed only in wide expanded modes and emulation expanded narrow mode Table 14 3 Tag Pin Function TAGHI TAGLO Tag 1 1 No tag 1 0 Low byte 0 1 High byte 0 0 Both bytes 14 5 Modes of Operation BDM is available in all operating modes but must be enabled before firmware commands are executed Some system peripherals may have a control bit which allows suspending the peripheral function during background debug mode In special single chip mode background operation is enabled and active out of reset This allows programming a system with blank memory BDM is also active out of special peripheral mode reset and can be turned off by clearing the BDMACT bit in the BDM status BDMSTS register This allows testing of the BDM memory space as well as the user s memory space NOTE The BDM serial system should not be used in special peripheral mode since the CPU which in other modes interfaces with the BDM to relinquish control of the bus during a free cycle or a steal operation is not operating in this mode 14 5 1 Normal Operation BDM operates the same in all normal modes For More Inform
61. Transfer instructions copy the value in a CPU register into another CPU register The source value is not changed by the operation TFR is a universal transfer instruction but other mnemonics are accepted for compatibility with the M68HC12 The TAB and TBA instructions affect the N Z and V condition code bits in the same way as M68HC12 instructions The TFR instruction does not affect the condition code bits Exchange instructions exchange the values in pairs of CPU registers The sign extend instruction SEX is a special case of the universal transfer instruction It adds a sign extension to an 8 bit two s complement number so that the number can be used in 16 bit operations The 8 bit number is copied from accumulator A B or the condition code register to accumulator D the X index register the Y index register or the stack pointer All the bits in the upper byte of the 16 bit result are given the value of the MSB of the 8 bit number A summary of the transfer and exchange instructions is given in Table 4 4 Table 4 4 Transfer and Exchange Instructions Mnemonic Function operation TAB Transfer A to B A gt TAP Transfer A to CCR A CCR TBA Transfer B to A B gt TFR Transfer register A B CCR D X Y or SP gt A B CCR D X Y or SP TPA Transfer CCR to A CCR gt TSX Transfer SP to X SP gt TSY Transfer SP to Y SP gt TXS Transfer X to SP X SP TYS Transfer
62. and the end of the last rule is marked by the reserved 16 bit value FFFF Since FFFE and FFFF are the addresses of the reset vector there is never a fuzzy input or output at either of these locations B 6 2 1 Initialization Prior to Executing REVW Some CPU registers and memory locations need to be initialized before executing the REVW instruction X and Y index registers are index pointers to the rule list and the list of rule weights The A accumulator holds intermediate calculation results and needs to be initialized to FF The V bit is an instruction status indicator that shows whether antecedents or consequents are being processed Initially the V bit is cleared to indicate antecedent processing The C bit enables 1 or disables 0 rule weighting The fuzzy outputs in working RAM locations need to be cleared to 00 Improper initialization produces erroneous results Initialize the X index register with the address of the first element in the rule list in the knowledge base The REVW instruction automatically updates this pointer so that the instruction can resume correctly if it is interrupted After the REVW instruction finishes X points at the next address past the FFFF separator word that marks the end of the rule list Initialize the Y index register with the starting address of the list of rule weights Each rule weight is an 8 bit value The weighted result is the truncated upper eight bits of the 16 bit result which is derived
63. ff8f 83 00 80 subd 50080 point to next word f 92 2b 6 bmi FLOOP until we go under 8000 On each succesive Page we start at a different point such that if we only had one array we would check the A entire array ff94 c3 3f fe addd S3FFE point toward end of next page ff97 73 00 30 dec PPAGE change to next lower pag f 9a 2a ee bpl FLOOP until we go under 00 Completed FLASH verify if we make it her Verify the EEPROM is erased all ones Move EEPROM to 7800 This will be 7000 if the size is 4K This will be 6000 if the size is 8K ff9c 86 79 ldaa 8579 bit 0 is EEON ff9e 5a 12 staa INITEE A First determine the size of th EPROM ffa0 d6 lc ldab EMSIZO size is encoded in bits 5 amp 4 ffa2 c4 30 andb 30 Just the bits we need ffa4 27 15 beq ECLEAR no EEPROM we re done ffa6 86 78 ldaa 78 set up for 2K size ffa8 c0 10 SLOOP subb 10 2K if clear after lst subtract ffaa 27 03 beq EECHK 2nd sub is 4K 3rd is 8K ffac 48 lsla adjust for next size ffad 20 9 bra SLOOP A Finally the erase verify loop Every ninth word is verified Accumulator D has already been set to the array size note that X still 0 from earlier routines For More Information On This Product Go to www freescale com ffaf ffb1 f fb3 ffb4 ffb6 ffb9 ffbb ffbd ffc0 ffc2 Fh FH Ph Ph Ph Ph Ph Ph th bh Fh H
64. gt core_rdbl X 1lo 1 rdbh gt core_rdbl 1 X 1 1 1 rdbl gt core_rdbl rdbl gt core_rdbh X 1 j 0 l i rdbh gt core_rdbl For More Information On This Product Go to www freescale com Core User Guide siocpurmtarscale Semiconductor Inc Table 11 15 Read Data Bus Swapping 2 Q Win Plols Read Data Bus MODE 2 s E N a CYCLES Internal or External S E lt gt CPU Read Data Bus 3 1 extrdbh gt core_rdbh o 0 E 2 2 extrdbl gt core_rdbl 1 extrdbl gt core _rdbh X 0 i 2 2 extrdbh gt core_rdbl extrdbh gt core_rdbh 0 0 j extrdbl gt core_rdbl 0 X 1 0 1 extrdbh gt core_rdbl Emulation Oo X 1 1 1 extrdbl gt core_rdbl Expanded Narrow rdbh gt core_rdbh X Oe 1 rdbl gt core_rdbl 1 rdbl gt core_rdbh 5 E 2 2 rdbh gt core_rdbl 1 0 1 rdbh gt core_rdbl 1 X 1 1 1 rdbl gt core_rdbl rdbl gt core_rdbh 1 1 0 1 1 rdbh gt core_rdbl ext rdbh gt core_rdbh X A 0 0 f ext rdbl gt core_rdbl 1 ext rdbl gt core_rdbh X o 0 2 2 ext rdbh gt core_rdbl Expanded Wide 1 0 1 ext rdbh gt core_rdbl 1 1 1 ext rdbl gt core_rdbl 0 4 4 ext rdbl gt core_rdbh ext rdbh gt core_rdbl For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 Section 12 Multiplexed External Bus Interface MEBI This section describes the functionality
65. i OR CCR CCR imm gt CCR Push A SP 1 gt SP A gt Mgp Push B SP 1 gt SP B gt Mgp Push CCR SP 1 gt SP CCR Mgp Push D SP 2 gt 8P A B gt Mgp Mgp Push X SP 2 SP Xy X_ gt Msp Mgp 4 Push Y SP 2 gt SP Yu Y_ gt Msp Mgp 4 Pull A Msp gt A SP 1 gt SP Pull B Mgp B SP 1 gt SP Pull CCR Mgp CCR SP 1 gt SP PULD Pull D INH 3A U O SEE Msp Msp 1 gt A B SP 2 gt SP For More Information On This Product Go to www freescale com Core User Guide siocpuimtaRscale Semiconductor Inc Source Form Operation Pull X Mgp Mgp 4 gt X X_ SP 2 gt SP Pull Y Msp Mgp41 gt Y H YL SP 2 SP Address Mode INH Machine Coding Hex Access Detail UfO SXHINZVC Rule evaluation unweighted find smallest rule input store to rule outputs unless fuzzy output is larger Special Orf t tx O ELFOLEE The t tx loop is executed once for each element in the rule list The denotes a check These are additional cycles caused by an interrupt f is the exit sequence and Orft for pending interrup t requests is the re entry sequence REVW Rule evaluation weighted rule weights optiona
66. o Q Hh a o 84 ed 02 26 c3 2a 86 ce 6a 06 18 6 ca ce 86 aa 53 27 6a a7 a7 20 Clear ffdt f 6 fff6 fff8 fffa fffc fffe 00 00 00 00 ff ff EE ff ff 78 e6 Of 00 6 42 ff 00 GE 0b bf fe ff 80 00 03 00 fd 12 01 20 3f Of 01 00 out spac 00 00 00 00 24 c5 80 80 80 00 00 00 00 00 00 00 00 Freescale Semiconductor MS Guide 12CPU15UG V1 2 ECHK anda 578 index D X last word ELOOP ldy D X read word from EEPROM iny erased will become 0000 bne FAIL not blank gt done addd 0012 point to next word bpl ELOOP until we get to or under 4000 When we arrive here all is clear ECLEAR ldaa 42 bit 1 is UNSEC ldx BDMSTS staa 0 X use instr that ends with write cycle jmp BDMSTAR Failures arrive here forever 30 FAIL movb 53 PPAGE ldab SBFOF orab SEC ldx BDMSTS ldaa 580 oraa 0 x decb beq BDMLOCK staa Oo align 1 BDMLOCK nop bra BDMLOCK between here and the vectors 00 00 zmb VECTORS 00 00 00 00 00 VECTORS HERE org VECTORS fdb BDMSTAR 4 SWI fdb FAIL TRAP fdb STAR COP fdb STAR CLK Monitor fdb STAR RESET ARI RARA end KKK KK KKK KKK KK RR RAR RRA KK KKK KK KK KKK KK KK KKK For More Information On This Product Go to www freescale com
67. on chip Flash EEPROM memory block 7 2 1 23 Core Security Request secreq This single bit input indicates to the Core that the system memory is in a secured state and that the Core should operate in secured mode Please see Section 15 for functional details 7 2 1 24 56 bit Interrupt request signals from peripheral block to Core peri_ffxx_t3 This 56 bit wide input to the Core provides the Core with the Interrupt request signals from all the system interrupt sources via the I P Bus Interface For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc 7 2 1 25 System Real Time Interrupt request peri_rtifffOi_t3 This input signal indicates to the Core that the system is requesting the interrupt vector for a Real Time Interrupt RTI from the Core 7 2 1 26 Background Debug Mode active indicator core_bdmact_t4 This single bit output from the Core indicates that the Background Debug Mode BDM is active 7 2 2 External Bus Interface Signals These descriptions apply to the interface signals between the Core and the system External Bus Interface pad logic Please see Section 12 of this guide for further functional details of the External Bus Interface 7 2 2 1 Port A Input Data to Core core_paind 7 0 This 8 bit wide input to the Core provides the Core with the input data from the system port pad logic for Port A 7 2 2 2 Port A Output Data from Core core_pado 7
68. opr8a 16 bit immediate value 8 bit address value used with direct address mode opr16a 16 bit address value oprx0_xysp Indexed addressing postbyte code oprx3 xysp Predecrement X Y or SP by 1 8 oprx3 xysp Preincrement X Y or SP by 1 8 oprx3 xysp Postdecrement X Y or SP by 1 8 oprx3 xysp Postincrement X Y or SP by 1 8 oprx5 xysppc 5 bit constant offset from X Y SP or PC abd xysppc Accumulator A B or D offset from X Y SP or PC Any positive integer from 1 to 8 for pre post increment decrement Any integer from 16 to 15 Any integer from 256 to 255 Any integer from 32 768 to 65 535 8 bit value for PPAGE register Some assemblers require the symbol before this value Label of branch destination within 256 to 255 locations Label of branch destination within 512 to 511 locations rel16 Any label within the 64 Kbyte memory space trapnum Any 8 bit integer from 30 to 39 or from 40 to FF Register designator for X or Y or SP xysppc Register designator for X or Y or SP or PC For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 1 8 3 Operation Notation Table 1 5 Operation Notation Add Subtract e AND OR Exclusive OR x Multiply Divide Concatenate Transfer lt Exchange 1 8 4 Address Mode Notation Table 1
69. pins or alternatively as the address data and control signals for a multiplexed expansion bus Address and data are multiplexed on Ports A and B The control pin functions are dependent on the operating mode and the control registers PEAR and MODE The initial state of bits in the PEAR and MODE registers are also established during reset to configure various aspects of the expansion bus After the system is running application software can access the PEAR and MODE registers to modify the expansion bus configuration Some aspects of Port E are not mode dependent Bit 1 of Port E is a general purpose input or the IRQ interrupt input IRQ can be enabled by bits in the CPU condition code register but it is inhibited at reset so this pin is initially configured as a simple input with a pullup Bit 0 of Port E is a general purpose input or the XIRQ interrupt input XIRQ also can be enabled by bits in the CPU condition code register but it is inhibited at reset so this pin is initially configured as a simple input with a pullup The ESTR bit in the EBICTL register is set to one by reset in any user mode This assures that the reset vector can be fetched even if it is located in an external slow memory device The PE6 MODB IPIPE1 and PES MODA IPIPEO pins act as high impedance mode select inputs during reset The following subsections discuss the default bus setup and describe which aspects of the bus can be changed after reset on a per mode basis 12 4
70. state the interrupt input lines to the Interrupt sub block will be disconnected and interrupt requests will be generated only by this register These bits can also be read in special modes to view that an interrupt requested by a system block such as a peripheral block has reached the INT module There is a test register implemented for every 8 interrupts in the overall system All of the test registers share the same address and are individually selected using the value stored in the ADR3 ADRO bits of the Interrupt Test Control Register ITCR NOTE When ADR3 ADRO have the value of F only bits 2 0 in the ITEST register will be accessible That is vectors higher than F FF4 cannot be tested using the test registers and bits 7 3 will always read as a logic zero If ADR3 ADRO point to an unimplemented test register writes will have no effect and reads will always return a logic zero value For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 10 3 3 Highest Priority Interrupt Optional Address 001F Bit 7 6 5 4 3 2 1 Bit O Read 0 PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 Write Reset 1 1 1 1 0 0 1 0 Figure 10 5 Highest Priority Interrupt Register HPRIO Read anytime Write only if mask in CCR 1 PSEL7 PSEL1 Highest priority I interrupt select bits The state of these bits determines which I bit maskable interrupt will be promoted t
71. www freescale com 11 5 1 2 Mapping Test Register 1 MTST1 Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Address Base 17 Read MT17 MT16 MT15 MT14 MT13 MT12 MT11 MT10 Write PNORME FLAGSE BKGDPUE Reset 0 0 0 1 0 0 0 0 Unimplemented Figure 11 14 Mapping Test Register One MTST1 Read Anytime Write See individual bit descriptions MT17 Unimplemented reads back zero MT16 Mapping Test Register 1 Bit 6 PNORME Normally the system will enter peripheral mode and be in a special mode Setting this bit will put the system into normal peripheral mode This is so that testing of register normal mode read write conditions can be performed while in peripheral mode Normal Special amp Emulation Write never Peripheral Write anytime 1 The system operates in normal peripheral mode 0 The system operates in special peripheral mode MT15 Mapping Test Register 1 Bit 5 FLAGSE This bit is used to enable the select signal flag function of the MTST registers When asserted the MTST registers that have an associated block select signal flag bit will act as flag registers where an access to the block causes the flag bit to assert When unasserted the MTST registers will not act as flag bits Normal amp Emulation Write never Special Write anytime 1 The MTST registers act as flag bits for the block select signals 0 The MTST registers do not act as flag bits
72. 0 External Bus Interface Signals core_pado 7 0 core_paobe 7 0 core_paibe_t2 Port A input data 7 0 Port A data output 7 0 Oi Port A output buffer enable 7 0 core_papue_t2 core_padse_t2 core_pbind 7 0 Port A input buffer enable Port A pullup enable O Port A drive strength enable core_pbdo 7 0 core_pbobe 7 0 core_pbibe_t2 Port B input data 7 0 Port B data output 7 0 o Port B output buffer enable 7 0 core_pbpue_t2 core_pbdse_t2 core_peind 7 0 Port B input buffer enable Port B pullup enable O PortB drive strength enable Port E input data 7 0 NOTE PE1 is IRQ pin input PEO is XIRQ pin input core_pedo 7 0 Port E data output 7 0 core_peobe 7 0 core_peibe_t2 Port E output buffer enable 7 0 Port E input buffer enable core_pepue_t2 Port E pullup enable core_mdrste core_pedse_t2 Enable signal for EBI Mode pin pullups at the pad core_pkind 7 0 core_pkdo 7 0 core_pkobe 7 0 Port K output buffer enable 7 0 core_pkibe_t2 Port K input buffer enable core_pkpue_t2 core_pkdse_t2 Port K pullup enable Port K drive strength enable Port E drive strength enable Port K input data 7 0 Port K data output 7 0 O 12 2 1 MEBI Signal Descriptions These descriptions apply to the MEBI signals that pass through the Core boundary and interface with the system External Bus Interface port pad logic
73. 0 0 0 normal Exp Nar Reset 1 1 0 0 0 0 0 0 Peripheral Normal Reset 1 1 1 0 0 0 0 0 Exp Wide ae Unimplemented Figure 12 10 MODE Register MODE Read anytime provided this register is in the map Write each bit has specific write conditions Please refer to the descriptions of each bit on the following pages The MODE register is used to establish the operating mode and other miscellaneous functions i e internal visibility and emulation of Port E and K For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc In peripheral modes this register is not accessible but it is reset as shown to configure system features Changes to bits in the MODE register are delayed one cycle after the write This register 1s not in the on chip map in emulation and peripheral modes MODC MODB MODA Mode Select bits These bits indicate the current operating mode If MODA 1 then MODC MODB MODA are write never If MODC MODA 0 then MODC MODB MODA are write anytime except that you cannot change to or from peripheral mode If MODC 1 MODB 0 and MODA 0 then MODC is write never and MODB MODA are write once except that you cannot change to peripheral special test special single chip or emulation modes Table 12 2 MODC MODB MODA Write Capability MODC MODB MODA Mode MODx Write Capability 0 0 0 Special Single Chip MODC B A write anytime but not to 11
74. 1 not used Ore 1 O dl PE Xalo D A O ES xX UY Roderic GSP TTAG GO coding 0 0 No execution command 0 1 Go to user program ANO Trace on First BDM ROM vector Start of BDM map Instruction TTAG BKGND GO registers command register R2 R1 RO W B BD USR NEXT il 0 Next Word 2 X pre inc X by 2 and r w next word later r w next will work from ADDRESS reg value not X command 00 is null command GX user instruction and return to BDM For More Information On This Product Go to www freescale com ff01 ff02 ff04 ff06 20 20 ff24 hh Fh Fh Fh Fh Hh Hh Hh w od Hh hh w oO EBST ff39 ff3e FESE ff41 Le b7 b7 Ta b7 8e 24 e7 26 08 b7 le 87 20 79 ff 01 80 b4 20 ff 06 d3 ff 00 04 00 01 d3 ff 01 80 06 le ff 00 Freescale Semiconductor WOE Guide 12CPU15UG V1 2 1 1 Tag Go command reconfigure BKGD pin for tagging in STATUS rmb1 Status Control register x enBDM BDACTV TAG VALID TRACE Exit conditions vs value written to STATUS on exit BDM not allowed 00 Trace 1 88 Go 80 X Tag Go SAO SHIFTER rmb2 For serial data in out ADDRESS rmb2 Address for some commands ADDRESS will be read only on first parts but later it will be r w so r w next CCRSAVE CCRSAVE also u
75. 11 9 si2cpu A A8gscale Semiconductor Inc Jump and Subroutine Instructi0NS 87 Interrupt Instructions ceed oe a 87 Index Manipulation Instructi0NS ooooo 88 Stacking MSUUCIONS srta eet be otro bans Sheed 89 Load Effective Address Instructions 90 Condition Code Instructions cies i n as 90 STOP and WAI INStUCHONS w 26 ba oats Seared cea See ws 91 Background Mode and Null Operation Instructions 91 Instruction Set Summary 0000 eee eee eee 106 Register and Memory Notation 220 055 120 Source Form Notation 000 0c eee eee 121 Operation Notation ce cote oe oc 122 Address Mode Notation 2200 cee eee 122 Machine Code Notation 0000 eee ee eee 123 Access Detail NOUN iis a ieee Pe eae eee ane 123 Condition Code State Notation 220005 126 IPIPE 1 0 Decoding when E Clock is High 127 IPIPE 1 0 Decoding when E Clock is Low 128 Exception Vector Map and Priority 135 Reset SOUICES 4 cSt dG eae el een o eS wie 136 Interrupt SOUIGES s n s eee ae aint 137 Core Interface Signal Definitions 142 Multiplexed Expansion Bus Timing Preliminary Targets 160 Expansion Bus Timing Preliminary Targets 161 Access Type vs Bus Control PiNS 162 Core Clock and Reset Interface
76. 128 to 7F 127 relative to the byte following the relative offset byte E A or low byte of a 16 bit relative offset for long branches xb Indexed addressing postbyte 5 4 6 Access Detail Notation A single letter code in the Access Detail column of Table 5 1 represents a single CPU access cycle An upper case letter indicates a 16 bit access Table 5 7 Access Detail Notation Free cycle During an f cycle the CPU does not use the bus An cycle is always one cycle of the system bus clock An cycle can be used by a queue controller or the background debug system to perform a single cycle access without disturbing the CPU g Read PPAGE register A g cycle is used only in CALL instructions and is not visible on the external bus Since PPAGE is an internal 8 bit register a g cycle is never stretched I Read indirect pointer Indexed indirect instructions use the 16 bit indirect pointer from memory to address the instruction operand An I cycle is a 16 bit read that can be aligned or misaligned An I cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the corresponding data is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory An I cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access
77. 8 1 Special Single Chip Mode When the system is reset in this mode the background debug mode is enabled and active The system does not fetch the reset vector and execute application code as it would in other modes Instead the active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin When a serial command instructs the system to return to normal execution the system will be configured as described below unless the reset states of internal control registers have been changed through background commands after the system was reset There is no external expansion bus after reset in this mode Ports A and B are initially simple bidirectional I O pins that are configured as high impedance inputs with internal pullups enabled however writing to the mode select bits in the MODE register which is allowed in special modes can change this after reset All of the Port E pins except PE4 ECLK are initially configured as general purpose high impedance inputs with pullups enabled PE4 ECLK is configured as the E clock output in this mode The pins associated with Port E bits 6 5 3 and 2 cannot be configured for their alternate functions IPIPE1 IPIPEO LSTRB and R W respectively while the system is in single chip modes The associated control bits PIPOE LSTRE and RDWE are reset to zero Writing the opposite value into these bits in this mode does not change the operation o
78. AND of an immediate value and the value in the CCR Puts the result in the CCR If the I mask bit is cleared there is a one cycle delay before the system allows interrupt requests This prevents interrupts from occurring between instructions in the sequences CLI WAI and CLI SEI CLI is equivalent to ANDCC EF All CCR bits Clear if 0 before operation or if corresponding bit in mask is 0 Address Machine Source Form Mode Code Hex CPU Cycles ANDCC opr8i IMM 10 ii P For More Information On This Product Go to www freescale com ASL Operation CCR Effects Code and CPU Cycles Freescale Semiconductor ING cuide s12cPuU15UG V1 2 Arithmetic Shift Left M A S L same as LSL b7 b6 bs b4 b3 b2 bt bo e 0 M Shifts all bits of M one bit position to the left Bit O is loaded with a 0 The C bit is loaded from the most significant bit of M N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V NO C set if Nis set and C is cleared after the shift or Nis cleared and C is set after the shift cleared otherwise C M7 set if the MSB of M was set before the shift cleared otherwise Source Form ea Code Heo CPU Cycles ASL opr16a EXT 78 hh 11 rPwO ASL oprx0_xysppc IDX 68 xb rPw ASL oprx9 xysppc IDX1 68 xb ff rPwO ASL oprx16 xysppc IDX2 68 xb ee ff frPwP ASL D xysppc D IDX 68 xb fIfrPw ASL oprx16 xysp
79. Address Machine Source Form Mode Code Hex CPU Cycles ADDB opr8i IMM CB ii P ADDB opr8a DIR DB dd rPf ADDB opr16a EXT FB hh 11 rPO ADDB oprx0_xysppc IDX EB xb rPf ADDB oprx9 xysppc IDX1 EB xb ff rPO ADDB oprx16 xysppc IDX2 EB xb ee ff frPP ADDB D xysppc D IDX EB xb fIfrPf ADDB oprx16 xysppc IDX2 EB xb ee ff IPrbf For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 ADDD Add to ADDD Operation CCR Effects Code and CPU Cycles A B M M 1 gt A B or A B imm gt A B Adds either the value in M concatenated with the value in M 1 or an immediate value to the value in D Puts the result in D A is the high byte of D B is the low byte N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V Di5eM15e R15 D15 M15 e R15 set if the operation produces a two s complement overflow cleared otherwise C D15 e M15 M15 e R15 R15 e D15 set if there is a carry from the MSB of the result cleared otherwise Machine Source Form Code Hex CPU Cycles ADDD opr16i C3 jj kk ADDD opr8a D3 dd ADDD opr16a F3 hh 11 ADDD oprx0_xysppc E3 xb ADDD oprx9 xysppc E3 xb ff ADDD oprx16 xysppc E3 xb ee ff ADDD D xysppc E3 xb ADDD oprx16 xysppc E3 xb ee ff For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Sca
80. B gt X Adds the 8 bit unsigned value in B to the value in X considering the possible carry out of Add B to X same as LEAX B X the low byte of X and places the result in X The value in B does not change ABX assembles as LEAX B X The LEAX instruction allows A B D or a constant to be added to X S X H I N ZV C Address Machine Source Form Mode Code Hex CPU Cycles ABX IDX 1A E5 Pf For More Information On This Product Go to www freescale com 12CPU15UG V1 2 ABX Core User Guide si2cpu A A8gscale Semiconductor Inc A B Y aoe cen A B Y Operation CCR Effects Code and CPU Cycles Y B gt Y Adds the 8 bit unsigned value in B to the value in Y considering the possible carry out of the low byte of Y and places the result in Y The value in B does not change ABY assembles as LEAY B Y The LEAY instruction allows A B D or a constant to be added to Y S X H I N Z V C Address Machine Source Form Mode Code Hex CPU Cycles ABY IDX 19 ED Pf For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 ADCA Add with Carry to A ADCA Operation A M C gt A or A imm C gt A Adds either the value in M and the C bit or an immediate value and the C bit to the value in A Puts the result in A This instruction affects the H
81. Branch if greater than R gt M Z N V 0 BLE pane Branch if less than or equal R lt M Z N V 1 BLT Branch if less than R lt M N V 1 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 4 3 17 2 Long Branch Instructions When a specified condition is met a long branch instruction adds a signed 16 bit offset to the value in the program counter Program execution continues at the new address Long branches are used when large displacements between decision making steps are necessary The numeric range of long branch offset values is 8000 32 768 to 7FFF 32 767 from the address of the next memory location after the offset value This permits branching from any location in the standard 64K byte address map to any other location in the map A summary of the long branch instructions is given in Table 4 20 Table 4 20 Long Branch Instructions Mnemonic Class Function Condition Equation LBRA Long branch always 1 1 Unary LBRN Long branch never 1 0 LBCC Long branch if carry clear C 0 LBCS Long branch if carry set C 1 LBEQ Long branch if equal Z 1 LBMI Long branch if minus N 1 Simple LBNE Long branch if not equal Z 0 LBPL Long branch if plus N 0 LBVC Long branch if overflow clear V 0 LBVS Long branch if overflow set V 1 LBHI Long branch if higher R gt M C Z 0 LBHS Long br
82. C bit from the least significant bit of A CCR Effects S XH I N ZV C 0 A A A N Cleared Z Set if result is 00 cleared otherwise V NO C N C N C for N and C after the shift set if N is set and C is cleared or N is cleared and C is set cleared otherwise for values of N and C after the shift C AO set if the LSB of A was set before the shift cleared otherwise Code and CPU Source Form SS Code Hes CPU Cycles Cycles LSRA INH 44 O For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc LS R B Logical Shift Right B LS R B Operation CCR Effects Code and CPU Cycles o 67 b6 bs ba bg 62 bt v0 B Shifts all bits of B one place to the right Loads bit 7 with 0 Loads the C bit from the least significant bit of B S X H I N Z V C o 4 4 a4 N Cleared Z Set if result is 00 cleared otherwise V NO C N o C N o C for N and C after the shift set if N is set and C is cleared or N is cleared and C is set cleared otherwise for values of N and C after the shift C BO set if the LSB of B was set before the shift cleared otherwise Address Machine Mode Code Hex CPU Cycles Source Form LSRB INH 54 O For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2
83. CURRENT_INS Get first input value 04 1 LDAB 7 7 labels per input 05 5 GRAD_LOOP MEM Evaluate one MF 06 3 DBNE B GRAD_LOOP For 7 labels of 1 input 07 3 LDAA CURRENT_INS 1 Get second input value 08 1 LDAB 7 7 labels per input 09 5 GRAD_LOOP1MEM Evaluate one MF 10 3 DBNE B GRAD_LOOP1 For 7 labels of 1 input lial 1 LDAB Loop count 12 2 RULE_EVAL CLR 1 Y Clr a fuzzy out inc ptr 13 3 DBNE b RULE_EVAL Loop to clr all fuzzy outs 14 2 LDX RULE_START Point at first rule element LS 2 LDY FUZ_INS Point at fuzzy ins and outs 16 1 LDAA SFF Init A and clears V bit Ly 3n 4 REV Process rule list 18 2 DEFUZ LDY FUZ_OUT Point at fuzzy outputs 19 1 LDX SGLTN_POS Point at singleton positions 20 1 LDAB 7 7 fuzzy outs per COG output 21 8b 9 WAV Calculate sums for wtd av 22 11 EDIV Final divide for wtd av 23 1 TFR YD Move result to A B 24 3 STAB COG_OUT Store system output KkKKKK End Figure B 3 Fuzzy Inference Engine Line 11 sets the loop count to clear seven fuzzy outputs Lines 12 and 13 form a loop to clear all fuzzy outputs before rule evaluation starts Line 14 initializes the X index register to point at the first element in the rule list for the REV instruction For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc Line 15 initializes the Y index register to point at the fuzzy inputs and outputs in the system The rule lis
84. Cycles si2cpu A A8gscale Semiconductor Inc BGT Branch if Greater Than Zero If Z NO V 0 then PC 0002 rel gt PC BGT can be used to branch after comparing or subtracting signed two s complement values After CMPA CMPB CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the CPU register value is greater than the value in M After CBA or SBA the branch occurs if the value in B is greater than the value in A Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction S X H I N ZV C Address Machine Source Form Mode Code Hex CPU Cycles BGT rel8 REL ZE er PPP branch P no branch Branch Complementary Branch Comment Mnemonic Opcode Test Mnemonic Opcode Test R gt M R lt M or or BGT 2E B gt A BLE 2F B lt A Signed Z N V 0 Z N V R gt M R lt M or or BHI 22 B gt A BLS 23 B lt A Unsigned For More Information On This Product Go to www freescale com BHI Operation CCR Effects Code and CPU Cycles Freescale Semiconductor WOE Guide 12CPU15UG V1 2 BHI Branch if Higher If C I Z 0 then PC 0002 rel PC BHI can be used to branch after comparing or subtracting unsigned values
85. EXG B TMP2 EXG B D EXG B X EXG B Y EXG B SP 1001 X000 1001 X001 1001 X010 1001 X011 1001 X100 1001 X101 1001 X110 1001 X111 EXG CCR A EXG CCR B EXG CCR CCR EXG CCR TMP2 EXG CCR D EXG CCR X EXG CCR Y EXG CCR SP 1010 X000 1010 X001 1010 X010 1010 X011 1010 X100 1010 X101 1010 X110 1010 X111 EXG TMP3 A EXG TMP3 B 1011 X001 EXG TMP3 CCR 1011 X010 EXG TMP3 TMP2 1011 X011 EXG TMP3 D 1011 X100 EXG TMP3 X 1011 X101 EXG TMP3 Y 1011 X110 EXG TMP3 SP 1011 X111 1011 X000 Freescale Semiconductor WOE Guide Object B7 80 81 82 83 84 85 86 87 Exchange Register Contents continued Exchange Postbyte eb Coding Exchange 00 A gt TMP2 TMP2 gt A 00 A gt D 00 A gt X XL gt A 00 A gt Y Y gt A 00 A gt SP SP_ gt A BoA B amp B B amp CCR 00 B gt TMP2 TMP2 B 00 B D 00 B gt X X_B 00 B gt Y Y B 00 B gt SP SP_ B CCRaA CCReB CCReCCR 00 CCR TMP2 TMP2 gt CCR 00 CCR gt D 00 CCR gt X XL gt CCR 00 CCR gt Y Y gt CCR 00 CCR gt SP SP gt CCR TMP3 gt A 00 A gt TMP3 TMP3 8 FF B TMP3 TMP3 CCR FF CCR TMP3 TMP3 lt TMP2 TMP3 lt 3D TMP3eX TMP3eY TMP39SP Source Forn Postbyte EXG B A EXG B B EXG B CCR EXG D TMP2 EXG D D EXG D X EXG D Y EXG D SP 1100 X000 1100 X001 1100 X010 1100 X011 1100 X100 1100 X101 1100 X110 1100 X111 EXG X A EXG X B EXG X CCR EXG X TMP2 EXG X D EXG X X EXG X Y EXG X SP 1101 X000 1101 X001 1
86. Each read command corresponding to reg code 2 7 takes exactly 4 bytes For command 2 read next word the jump will GOTO 0 pc or the location immediately after the jump For command 7 read SP the jump will go to 5 4 pc Each command ends with a branch to the main command loop R_NXT_WRD ldd2 x pre inc X by 2 and read word braR_COMMON D gt SHIFTER and bra loop top READ_PC braREAD_PC1 This command needs 4 bytes nop Pad to make command take 4 bytes nop READ_D tirts a User D was in Temp3 braR_COMMON D gt SHIFTER and bra loop top READ_X EXEX A Requested data to D braR_COMMON D gt SHIFTER and bra loop top READ_Y tfry d Requested data to D braR_COMMON D gt SHIFTER and bra loop top READ_SP tfrsp d Requested data to D R_COMMON StdSHIFTER Requested data to SHIFTER WAIT tst INSTR Check for new command tp 3 30 lbeq INST_LOOP Need escape if old command aborted tp 3 30 brclrSTATUS 10 WAIT Wait for data ready tp 3 30 braINST_DONE1 Back to loop top READ_PC1 exgd t2 User PC to D junk to Temp2 std SHIFTER User PC to SHIFTER exg d t2 User PC to Temp2 junk to D bra WAIT D gt SHIFTER and bra loop top FIXSP leas 9 sp Restore sp braINST_DONE1 And try to resume PR eKE CAUTION 5 zmbBDMVEC All unused space must be set to 7 zero KKK KK All other normal vectors are blocked out when in BDM The bdmact signal goes into INT module and blocks all I and X interrupts EXIAECAUTION 6 5 OrgBDMVEC BDM ve
87. Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc L B CS Long Branch if C Set same as LBLO Operation If C 1 then PC 0004 rel PC Tests the C bit and branches if C 1 LBCS CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex Branch Complementary Branch Mnemonic Mnemonic Opcode LBCS LBLO LBCC LBHS LBCS rel16 18 25 qq rr OPPP branch OPO no branch Comment LBLT For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 LBEQ NS LBEQ Operation CCR Effects Code and CPU Cycles If Z 1 PC 0004 rel gt PC Tests the Z bit and branches if Z 1 Rel is a 16 bit two s complement offset for branching forward or backward in memory Branching range is 8000 to 7FFF 32768 to 32767 from the address following the last byte of object code in the instruction S X H I N Z V C Address Machine Source Form Mode Code Hex CPU Cycles LBEQ rel16 REL 18 27 qq rr OPPP no branch OPO no branch Branch Complementary Branch F Comment Mnemonic Opcode Test Mnemonic Opcode Test R M R M or or Signed LBEQ 1827 R zero LBNE 1826 R zzero unsigned or simple Z Z 0 For More Information On This Product Go to www freescale com Core Use
88. Guide si2cpu ERA Scale Semiconductor Inc with the internal value During CPU no access cycles when the BDM is not driving R W will remain high and address data and the LSTRB pins will remain at their previous state 12 4 10 Secure Mode When the system is operating in a secure mode internal visibility is not available i e IVIS 1 has no effect Also the IPIPE signals will not be visible regardless of operating mode IPIPE1 IPIPEO will display zeroes if they are enabled In addition the MOD bits in the MODE control register cannot be written 12 5 Low Power Options The MEBI does not contain any user controlled options for reducing power consumption The operation of the MEBI in low power modes is discussed in the following subsections 12 5 1 Run Mode The MEBI does not contain any options for reducing power in run mode however the external addresses are conditioned with expanded mode to reduce power in single chip modes 12 5 2 Wait Mode The MEBI does not contain any options for reducing power in wait mode 12 5 3 Stop Mode The MEBI will cease to function during execution of a CPU STOP instruction 12 6 Motorola Internal Information This subsection details information about the MEBI sub block that is for Motorola use only and should not be published in any form outside of Motorola 12 6 1 Peripheral Mode Operation The only way to enter peripheral mode is via reset with the pins configured as shown in Table 12
89. Information On This Product Go to www freescale com Core User Guide si2cpu Rf Scale Semiconductor Inc Figure 14 9 shows the host receiving a logic O from the target Since the host is asynchronous to the target there is up to a one clock cycle delay from the host generated falling edge on BKGD to the start of the bit time as perceived by the target The host initiates the bit time but the target finishes it Since the target wants the host to receive a logic 0 it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge The host samples the bit level about 10 target clock cycles after starting the bit time CLOCK TARGET SYS HOST DAVETO Sm atada HIGH IMPEDANCE ees eee BKGDPIN Y o oos A AS TARGET SYS DRIVE AND A A O VY IS Siren SPEEDUP PULSE _ PERCEIVED START OF BIT TIME BKGD PIN 10 CYCLES 10 CYCLES gt EARLIEST START OF HOST SAMPLES NEXT BIT BKGD PIN Figure 14 9 BDM Target to Host Serial Bit Timing Logic 0 14 4 7 Instruction Tracing When a TRACE command is issued to the BDM in active BDM the CPU exits the standard BDM firmware and executes a single instruction in the user code Once this has occurred the CPU is forced to return to the standard BDM firmware and the BDM is active and ready to receive a new command If the TRACE1 command is issued again the next user instruction will be exec
90. J Y J a J EST A O A A AA Figure 7 12 Basic 8 bit Core Register Write Timing peri_clk24 LTA TS TAT TAG V V A A AE NAAA core _ ab t2 X addri addr3 X core_wdb_t4 X data1 data3 core_RSEL_t2 E A o ES core w2 Y f f Y Y f core_sz8_t2 e O A Figure 7 13 Basic 16 bit Core Register Write Timing 7 3 3 Multiplexed External Bus Interface A timing diagram of the multiplexed external bus is shown in Major bus signals are included in the diagram While both a data write and data read cycle are shown only one would occur on a particular bus cycle Table 7 2 gives the preliminary timing characteristics for the signals illustrated in For More Information On This Product Go to www freescale com Addr read Addr write Freescale Semiconductor WOE Guide Data data Data data Figure 7 14 General External Bus Timing For More Information On This Product Go to www freescale com 12CPU15UG V1 2 Core User Guide siocpuimtaRscale Semiconductor Inc Table 7 2 Multiplexed Expansion Bus Timing Preliminary Targets 16 MHz 20 MHz 25 MHz Num Characteristic 3 Symbol Unit Min Max Min Max Min Max Frequency of operation E clock fo D C 16 0 D C 20 0 25 0 MHz 2 Pulse width E low 22 18 ns 3 Pulse width E high 22 18 ns 5 Address delay time 12 10 8 ns
91. LSLDSame as ASLD Logical shift left M Pa C b7 Logical shift left A Logical shift left B Logical shift left D LH Cc MH b7 A b0 rOPw rPw rPOw frPPw fIfrPw fIPrPw LSR opr16a LSR oprx0_xysppc LSR oprx9 xysppc LSR oprx16 xysppc LSR D xysppc LSR oprx16 xysppc LSRA LSRB Logical shift right M o gt H b7 bo C Logical shift right A Logical shift right B Logical shift right D o gt b7 A bO b7 B 74hh 11 64 xb 64xb ff 64xbee ff 64 xb 64xbee ff 44 54 rPwO rPw rPwO frPwP fIfrPw fIPrPw MAXA oprx0_xysppc MAXA oprx9 xysppc MAXA oprx16 xysppc MAXA D xysppc MAXA oprx16 xysppc Maximum in A put larger of 2 unsigned 8 bit values in A MAX A M gt A N Z V C bits reflect result of internal compare A M OrPf OrPO OfrPP OfIfrPf OfIPrPf MAXM oprx0_xysppc MAXM oprx9 xysppc MAXM oprx16 xysppc MAXM D xysppc MAXM oprx16 xysppc Maximum in M put larger of 2 unsigned 8 bit values in M MAX A M gt M N Z V C bits reflect result of internal compare A M Determine grade of membership u grade gt My X 4 gt X Y 1 gt Y If A lt P1 or A gt P2 then u 0 else u MIN A P1 xS1 P2 A xS2
92. Mode this register is used to compare against the low order data lines 13 4 Operation The Breakpoint sub block supports two modes of operation Dual Address Mode and Full Breakpoint Mode Within each of these modes forced or tagged breakpoint types can be used Forced breakpoints occur at the next instruction boundary if a match occurs and tagged breakpoints allow for breaking just before a specific instruction executes The action taken upon a successful match can be to either place the CPU in Background Debug Mode or to initiate a software interrupt 13 4 1 Modes of Operation The Breakpoint can operate in Dual Address Mode or Full Breakpoint Mode Each of these modes is discussed in the subsections below 13 4 1 1 Dual Address Mode When Dual Address Mode is enabled two address breakpoints can be set Each breakpoint can cause the system to enter Background Debug Mode or to initiate a software interrupt based upon the state of the BKBDM bit in the BKPCTO Register being logic one or logic zero respectively BDM requests have a higher priority than SWI requests No data breakpoints are allowed in this mode The BKTAG bit in the BKPCTO register selects whether the breakpoint mode is force or tag The BKxMBH L bits in the BKPCT1 register select whether or not the breakpoint is matched exactly or is a range breakpoint They also select whether the address is matched on the high byte low byte both bytes and or memory expansion The BKxRW a
93. More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc CPS Compare SP CPS Operation CCR Effects Code and CPU Cycles SP M M 1 or SP imm Compares the value in SP to either the value in M M 1 or an immediate value CCR bits reflect the result The values in SP and M M 1 do not change Z Set if MSB of result is set cleared otherwise Set if result is 0000 cleared otherwise V SP15 e M15 R15 SP15 e M15 e R15 set if the operation produces a two s complement overflow cleared otherwise C SP15 e M15 M15 R15 R15 e SP15 set if the absolute value of M M 1 is larger than the absolute value of SP cleared otherwise N Address Machine Source Form Mode Code Hex CPU Cycles CPS opr16i CPS opr8a CPS opr16a CPS oprx0_xysppc CPS oprx9 xysppc CPS oprx16 xysppc CPS D xysppc CPS oprx16 xysppc For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 CPX Compare x CPX Operation CCR Effects Code and CPU Cycles X M M 1 or X imm Compares the value in X to either the value in M M 1 or an immediate value CCR bits reflect the result The values in X and M M 1 do not change Z Set if MSB of result is set cleared otherwise Set if result is 0000 cleared otherwise V X15 e M15 e R15
94. N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V Cleared Machine Source Form Code Hex CPU Cycles LDX opr16i LDX opr8a LDX opr16a LDX oprx0_xysppc LDX oprx9 xysppc LDX oprx16 xysppc LDX D xysppc LDX oprx16 xysppc For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc LDY Operation CCR Effects Code and CPU Cycles Load Y LDY MM 1 gt Y or imm gt Y Loads the high byte of Y with the value in M and the low byte with the value in M 1 or loads Y with an immediate value S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V Cleared Machine Source Form Code Hex CPU Cycles LDY opr16i LDY opr8a LDY opr16a LDY oprx0_xysppc LDY oprx9 xysppc LDY oprx16 xysppc LDY D xysppc E E E E E E LDY oprx16 xysppc For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 L E AS Load Effective Address into SP L E AS Operation Effective address SP Loads the stack pointer with an effective address specified by the program The effective address can be any indexed addressing mode operand address except an indirect address Indexed addressing mode operand addresses are formed by adding an opt
95. Once in Normal and Emulation modes and anytime in Special modes For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 1 Disables direct access to the Flash EEPROM or ROM in the lower half of the memory map These physical locations of the Flash EEPROM or ROM can still be accessed through the Program Page window 0 The fixed page s of Flash EEPROM or ROM in the lower half of the memory map can be accessed ROMON Enable Flash EEPROM or ROM Write Once in Normal and Emulation modes and anytime in Special modes This bit is used to enable the Flash EEPROM or ROM memory in the memory map 1 Enables the Flash EEPROM or ROM in the memory map 0 Disables the Flash EEPROM or ROM from the memory map 11 3 5 Reserved Test Register Zero MTSTO Address Base 17 Read 0 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 11 7 Reserved Test Register Zero MTSTO Read Anytime Write No effect this register location is used for internal test purposes 11 3 6 Reserved Test Register One MTST1 Address Base 14 Read 0 0 0 0 0 0 0 0 Write Reset 0 0 0 1 0 0 0 0 Unimplemented Figure 11 8 Reserved Test Register One MTST1 Read Anytime Write No effect this register location is used for internal test purposes For More Information On This Product Go to ww
96. Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc 10 4 1 3 Interrupt Priority Decoder The priority decoder evaluates all interrupts pending and determines their validity and priority When the CPU requests an interrupt vector the decoder will provide the vector for the highest priority interrupt request Because the vector is not supplied until the CPU requests it it is possible that a higher priority interrupt request could override the original exception that caused the CPU to request the vector In this case the CPU will receive the highest priority vector and the system will process this exception instead of the original request NOTE Care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine otherwise the exception request may not get processed If for any reason the interrupt source is unknown e g an interrupt request becomes inactive after the interrupt has been recognized but prior to the vector request the vector address will default to that of the last valid interrupt that existed during the particular interrupt sequence If the CPU requests an interrupt vector when there has never been a pending interrupt request the INT will provide the Software Interrupt SWI vector address 10 4 2 Reset Exception Requests The INT supports three system reset exception request types normal system reset or power on res
97. RTN gt Msp Msp 1 SP 0002 SP Y YL gt Msp Mgp 1 SP 0002 SP Xpy X1 gt Msp Msp 1 SP 0002 gt SP B A Msp Msp 1 SP 0001 SP CCR gt Msp 1 I trap vector PC Traps unimplemented opcodes There are opcodes in all 256 positions in the page 1 opcode map but only 54 of the 256 positions on page two of the opcode map are used If the CPU attempts to execute one of the unimplemented opcodes on page two an opcode trap interrupt occurs Unimplemented opcode traps are essentially interrupts that share the FFF8 FFF9 interrupt vector TRAP uses the next address after the unimplemented opcode as a return address It stacks the return address CPU registers Y X B A and CCR decrementing the SP before each item is stacked The I bit is then set the PC is loaded with the trap vector and instruction execution resumes at that location This instruction is not maskable by the I bit S X H I N Z V C ee ee ne Aa l Set Address Machine NOTES 1 The value tn is an unimplemented page two opcode from 30 to 39 or 40 to FF For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc TST Test m TST Operation M 00 Subtracts 00 from the value in M The condition code bits reflect the result The value in M does not change The TST instruction provides limited information when testing unsigned value
98. Reserved Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved INITRM INITRG INITEE MISC Reserved ITCR read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write Bit 7 Bit 7 1 Bit 0 Bit 7 Bit 7 Bit 7 0 0 0 0 Bit 7 Bit 7 NOACCE MODC PUPKE RDPK EE11 EXSTR1 For More Information On This Product Go to www freescale com WRTINT ADR1 ADRO Core User Guide 0016 0017 0018 to 001B 001C 001D 001E 001F 0020 to 0027 0028 0029 002A 002B 002C 002D 002E 002F 0030 0031 0032 0033 0034 to 00FF 0100 to 010F ITEST Reserved Reserved MEMSIZO MEMSIZ1 IRQCR HPRIO Reserved BKPCTO BKPCT1 BKPOX BKPOH BKPOL BKP1X BKP1H BKP1L PPAGE Reserved PORTK DDRK Reserved Reserved si2cpu A A8gscale Semiconductor Inc read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write rea
99. SP 0002 gt SP Loads the high byte of D from the address to which SP points Loads the low byte of D from the address to which SP points plus one Then increments SP by two Pull instructions are commonly used at the end of a subroutine to restore the contents of CPU registers that were pushed onto the stack before subroutine execution Address Machine Source Form Mode Code Hex CPU Cycles PULD INH 3A UfO For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 p U LX Pull X from Stack P U LX Operation Msp Msp 1 gt XH XL SP 0002 gt SP Loads the high byte of X from the address to which SP points Loads the low byte of X from the address to which SP points plus one Then increments SP by two Pull instructions are commonly used at the end of a subroutine to restore the contents of CPU registers that were pushed onto the stack before subroutine execution CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex PULX INH 30 U O For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc p U LY Pull Y from Stack P U LY Operation CCR Effects Code and CPU Cycles Msp Mgp 1 gt Yu YL SP 0002 gt SP Loads the high byte of Y from the address to which SP points Loads the low
100. SS 152 7 2 8 Scan Control Interface SIGNAlS e5 voc ne aaceGs iia eee ORES 152 7 3 Interface Operation sise otk Aes A E 152 7 3 1 Read Operations x sissy on eid E E Sat eid eee Se ease 152 7 3 2 Write Operations 2 5 2 4 05 eee ab ae ag De een no OG hE boas Sage Maw oe PEt 155 7 3 3 Multiplexed External Bus Interface ooooooococcoconooon o 158 7 3 4 General Internal Read Visibility Timing 000 00 eee eee eee 161 7 3 5 Detecting Access Type from External Signals nannaa annaa aa 162 Section 8 Core Clock and Reset Connections 8 1 Glocking Overview sus E E A E E 163 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide S12CPU15UG V1 2 8 1 1 Basic Clock Relationships cao loth one is Re ok Bee ai ett Gee 2 164 8 1 2 Reset Relations is oan EA ie ees ee ok Be eS ee ae aes 165 8 1 3 Phase Locked Loop Interface 0 00 c eee eee 165 8 1 4 HCS12 CPU Wait and Stop Modes ices unos etd dans ia eit ot 166 8 2 Signal SUMMARY 0 o ate Secs o 166 8 3 Detailed Clock and Reset Signal Descriptions 0 00 2c eee eee 167 8 3 1 Clock and Reset Signals pi A Oe wee 167 8 3 2 Stop and Wait Mode Control Status Signals 000 cece eee 168 Section 9 Core Power Connections 9 1 Power Overview cto aparece Ene een atras 169 9 1 1 Power and Ground SuMMarye se fen Otek e eee She cee ea Ses 169 Section 10 Interrupt INT HOT SOVGIVIGW rd A Aro
101. Semiconductor Inc EMINM exendedminimminw EMINIM Operation CCR Effects Code and CPU Cycles MIN D M M 1 gt M M 1 Subtracts an unsigned 16 bit value in M M 1 from an unsigned 16 bit value in D to determine which is larger Puts the smaller value in M M 1 If the values are equal the Z bit is set If the value in M M 1 is larger the C bit is set when the value in D replaces the value in M M 1 If the value in D is larger the C bit is cleared EMINM accesses memory with indexed addressing modes for flexibility in specifying operand addresses Autoincrement and autodecrement functions can facilitate finding the smallest value in a list of values S X H I N Z V C 4 4 4 a4 N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V D15 e M15 e R15 D15 M15 e R15 set if the operation produces a two s complement overflow cleared otherwise C D15 e M15 M15 R15 R15 e D15 set if M M 1 is larger than D cleared otherwise Condition code bits reflect internal subtraction R D M M 1 Address Machine Source Form Mode Code Hex CPU Cycles EMINM oprx0_xysppc IDX 18 1F xb ORPW EMINM oprx9 xysppc IDX1 18 1F xb ff ORPWO EMINM oprx16 xysppc IDX2 18 1F xb ee ff OfRPWP EMINM D xysppc D IDX 18 1F xb OfTERPW EMINM oprx16 xysppc IDX2 18 1F xbee ff OfIPRPW For More Information On This Produc
102. Signals 166 Exception Vector Map and Priority 176 External Stretch Bit Definition 184 Allocated EEPROM Memory Space 4 186 Allocated RAM Memory Space 0 005 186 Allocated Flash EEPROM ROM Physical Memory Space 187 Allocated Off Chip Memory Options 188 Program Page Index Register Bits 189 Select Signal PHONY ties ag Mi ES E ae Steed as 190 Allocated Off Chip Memory Options 191 External Internal Page Window ACCess 191 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE tuide Table 11 100K Byte Physical Flash ROM Allocated 193 Table 11 1116K Byte Physical Flash ROM Allocated 193 Table 11 1248K Byte Physical Flash ROM Allocated 193 Table 11 1364K Byte Physical Flash ROM Allocated 194 Table 11 14Wide Bus Enable Signal Generation 198 Table 11 15Read Data Bus Swapping 0 2 2 ee eee 199 Table 12 1 MEBI Interface Signal Definitions 203 Table 12 2 MODC MODB MODA Write Capability 216 Table 12 3 Mode Select and State of Mode Bits 216 Table 12 4 External System Pins Associated With MEBI 225 Table 12 5 Access Type vs Bus Control PINS
103. The INT does not contain any user controlled options for reducing power consumption The operation of the INT in low power modes is discussed in the following subsections 10 6 1 Run Mode The INT does not contain any options for reducing power in run mode 10 6 2 Wait Mode Clocks to the INT can be shut off during system wait mode and the asynchronous interrupt path will be used to generate the wakeup signal upon recognition of a valid interrupt or any XIRQ request 10 6 3 Stop Mode Clocks to the INT can be shut off during system stop mode and the asynchronous interrupt path will be used to generate the wakeup signal upon recognition of a valid interrupt or any XIRQ request 10 7 Motorola Internal Information The INT does not contain any functionality that is considered to be for Motorola internal use only For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Section 11 Module Mapping Control MMC This section describes the functionality of the Module Mapping Control MMC sub block of the Core 11 1 Overview The Module Mapping Control MMC sub block of the Core performs all mapping and select operations for the on chip and external memory blocks The MMC also handles mapping functions for the system peripheral blocks and provides a glob
104. The numeric range of 9 bit offset values is 256 to 255 from the address of the next memory location after the offset value A summary of the loop primitive instructions is given in Table 4 22 Table 4 22 Loop Primitive Instructions Mnemonic Function Operation DBEQ Decrement counter counter 1 counter and branch if zero If counter 0 then branch else continue to next instruction DBNE Decrement counter counter 1 counter and branch if not zero f counter 0 then branch else continue to next instruction IBEQ Increment counter counter 1 counter and branch if zero If counter 0 then branch else continue to next instruction IBNE Increment counter counter 1 counter and branch if not zero f counter 0 then branch else continue to next instruction TBEQ lest counter If counter 0 then branch else continue to next instruction and branch if zero TBNE JES counter If counter 0 then branch else continue to next instruction and branch if not zero 4 3 18 Jump and Subroutine Instructions Jump instructions cause immediate changes in program sequence The JMP instruction loads the PC with an address in the 64K byte memory map and program execution continues at that address The address can be provided as an absolute 16 bit address or determined by various forms of indexed addressing Subroutine instructions transfer control to a code segment that performs a particular task A sho
105. The queue treats the 18 prebyte of an instruction on page two of the opcode map as a special For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 one byte one cycle instruction However interrupts are not recognized at the boundary between the prebyte and the rest of the instruction 5 5 6 SOD Start Odd Instruction 1 1 This state indicates that the instruction in the odd low half of the word in stage three of the instruction queue The queue treats the 18 prebyte of an instruction on page two of the opcode map as a special one byte one cycle instruction However interrupts are not recognized at the boundary between the prebyte and the rest of the instruction For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Section 6 Exception Processing Exceptions are events that require a change in the sequence of instruction execution This section describes the exceptions supported by the Core and their functionality 6 1 Exception Processing Overview The Core supports two basic types of exceptions those from resets and those from interrupt requests Regardless of the source the first cycle in exception processing is a vector fetch cycle The exception processing flow is show
106. There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory An I cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access Read indirect PPAGE value An i cycle is used only in indexed indirect CALL instructions The 8 bit PPAGE value for the CALL destination is fetched from an indirect memory location An i cycle is stretched only when controlled by a chip select circuit that is programmed for slow memory Write PPAGE register An n cycle is used only in CALL and RTC instructions to write the destination value of the PPAGE register and is not visible on the external bus Since the PPAGE register is an internal 8 bit register an n cycle is never stretched Optional cycle An o cycle adjusts instruction alignment in the instruction queue An o cycle can be a free cycle or a program word access cycle P When the first byte of an instruction with an odd number of bytes is misaligned the o cycle becomes a P cycle to maintain queue order If the first byte is aligned the o cycle is an cycle The 18 prebyte for a page two opcode is treated as a special one byte instruction If the prebyte is misaligned the o cycle at the beginning of the instruction becomes a P cycle to maintain queue order If the prebyte is aligned the O cycle is an cycle If the instruction has an odd number of bytes it has a seco
107. User Guide si2cpu RR Scale Semiconductor Inc SUBD Subtract from D SUBD Operation CCR Effects Code and CPU Cycles A B M M 1 A B or A B imm gt A B Subtracts either the value in M M 1 or an immediate value from the value in D Puts the result in D The C bit represents a borrow S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V D15 e M15 e R15 D15 e M15 e R15 set if a two s complement overflow resulted from the operation cleared otherwise C D15 e M15 M15 R15 R15 e D15 set if the value in M is larger than the value in D cleared otherwise Machine Source Form Code Hex CPU Cycles SUBD opr16i SUBD opr8a SUBD opr16a SUBD oprx0_xysppc SUBD oprx9 xyssp SUBD oprx16 xysppc SUBD D xysppc SUBD oprx16 xysppc A3 xb ee ff For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 SWI Software Interrupt SWI Operation SP 0002 gt SP RTNg RTNL gt Msp Msp 1 SP 0002 gt SP Y y Y gt Mgp Msgp 1 SP 0002 gt SP Xq Xz gt Msp Msp 1 SP 0002 SP B A gt Msp Msp 1 SP 0001 SP CCR Msp l I SWI vector PC Causes an interrupt without an external interrupt service request Uses the address of the next instruction after SWI as a return address Stacks the return add
108. X gt X Remainder D 16 by 16 bit Integer divide signed D X X Remainder D 16 by 16 bit 18 Offffffffffo OLTELFEEEELO INC opr16a INC oprx0_xysppc INC oprx9 xysppc INC oprx16 xysppc INC D xysppc INC oprx16 xysppc INCA INCB Increment M M 1 gt M Increment A A 1 gt A Increment B B 1 gt B 72hh11 62 xb 62 xb ff 62 xbee ff 62 xb 62 xbee ff 42 52 rPwO rPw rPwO frPwP fIfrPw fIPrPw O O INSSame as LEAS 1 SP Increment SP SP 1 SP 1B 81 Pf INX Increment X X 1 gt X 08 INY Increment Y Y 1 gt Y 02 JMP opr16a JMP oprx0_xysppc JMP oprx9 xysppc JMP oprx16 xysppc JMP D xysppc JMP oprx16 xysppc Jump Subroutine address gt PC 06hh11 05 xb 05xbff 05 xbeeff 05 xb 05 xbeeff U HH U0 0 g PPP JSR opr8a JSR opr16a JSR oprx0_xysppc JSR oprx9 xysppc JSR oprx16 xysppc JSR D xysppc JSR oprx16 xysppc Jump to subroutine SP 2 gt SP RTNy RTN gt Mgp Mgp 4 Subroutine address gt PC 17 dd 16hh11 15 xb 15xb ff l5xbee ff 15 xb 15xbee ff p p S S PS PPPS PPPS h UU WM hh th FO FO tU FU U O tU tU Fh Fh HH Fy Fh LBCC re 16Same as LBHS LBCS re 16Same as LBLO LBEQ rel16 Long branch if C clear if C 0 then PC 4 rel gt PC Long branch
109. X points at the next address past the FF separator character that marks the end of the rule list The Y index register is set to the base address for the fuzzy inputs and outputs in working RAM Each rule antecedent is an unsigned 8 bit offset from this base address to the referenced fuzzy input Each rule consequent is an unsigned 8 bit offset from this base address to the referenced fuzzy output The Y index register remains constant throughout execution of the REV instruction The 8 bit A accumulator is used to hold intermediate calculation results during execution of the REV instruction During antecedent processing A starts out at FF and is replaced by any smaller fuzzy input that is referenced by a rule antecedent MIN During consequent processing A holds the truth value for the rule This truth value is stored to any fuzzy output that is referenced by a rule consequent unless that fuzzy output is already larger MAX Before execution of REV begins A must be set to FF the largest 8 bit value because rule evaluation always starts with processing of the antecedents of the first rule For subsequent rules in the list A is automatically set to FF when the instruction detects the FE marker character between the last consequent of the previous rule and the first antecedent of a new rule The instruction LDAA FF clears the V bit at the same time it initializes A to FF This satisfies the REV setup requirement to clear the V bit as we
110. X15 e M15 e R15 set if the operation produces a two s complement overflow cleared otherwise C X15 e M15 M15 R15 R15 e X15 set if the absolute value of M M 1 is larger than the absolute value of X cleared otherwise N Address Machine Source Form Mode Code Hex CPU Cycles CPX opr16i CPX opr8a CPX opr16a CPX oprx0_xysppc CPX oprx9 xysppc CPX oprx16 xysppc CPX D xysppc CPX oprx16 xysppc E E E E E E E E 8 9 B Al A A A A For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc CPY Compare v CPY Operation CCR Effects Code and CPU Cycles Y M M 1 or Y imm Compares the value in Y to either the value in M M 1 or an immediate value CCR bits reflect the result The values in Y and M M 1 do not change Z Set if MSB of result is set cleared otherwise Set if result is 0000 cleared otherwise V Y15 e M15 e R15 Y15 M15 e R15 set if the operation produces a two s complement overflow cleared otherwise C Y15 e M15 M15 R15 R15 Y15 set if the absolute value of M M 1 is larger than the absolute value of Y cleared otherwise N Address Machine Source Form Mode Code Hex CPU Cycles CPY opr16i CPY opr8a CPY opr16a CPY oprx0_xysppc CPY oprx9 xysppc CPY oprx16 xysppc CPY D xysppc CPY oprx16 xysppc For More Informa
111. YL gt Mgp Mpp 1 Decrements SP by two and loads the high byte of Y into the address to which SP points Loads the low byte of Y into the address to which SP points plus one After PSHY executes SP points to the stacked value of the high byte of Y Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine Complementary pull instructions can restore the saved CPU registers just before returning from the subroutine CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex PSHY INH 35 OS For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 p U LA Pull A from Stack P U LA Operation CCR Effects Code and CPU Cycles Msp gt A SP 0001 SP Loads A from the address to which SP points Then increments SP by one Pull instructions are commonly used at the end of a subroutine to restore the contents of CPU registers that were pushed onto the stack before subroutine execution S X H I N ZV C Address Machine Source Form Mode Code Hex CPU Cycles PULA INH 32 ufo For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc p U L B Pull B from Stack P U L B Operation CCR Effects Code and CPU Cycles Msp
112. abcdxysp Transfer from register to register r1 r2r1 and r2 same size 00 r1 r2r1 8 bit r2 16 bit r1 gt r2r1 16 bit r2 8 bit TPASame as TFRCCR A Transfer CCR to A CCR gt A For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Source Form TRAP trapnum TST opr16a TST oprx0_xysppc TST oprx9 xysppc TST oprx16 xysppc TST D xysppc TST oprx16 xysppc TSTA TSTB TSXSame as TFR SP X TSYSame as TFR SP Y TXSSame as TFR X SP TYSSame as TFR Y SP Operation Trap unimplemented opcode SP 2 gt SP RTNy RTN_ gt Msp Mspy1 SP 2 gt 8P Yu YL Mgp Mgp41 SP 2 gt SP Xy X gt Msp Msp 1 SP 2 gt 8SP B A gt Mgp Mgp 4 SP 1 SP CCR Mgp 11 trap vector PC Test M M 0 Test A A 0 Test B B 0 Transfer SP to X SP X Transfer SP to Y SP Y Transfer X to SP X gt SP Transfer Y to SP Y gt SP Wait for interrupt SP 2 gt SP RTNy RTN gt Mgp Mgp 4 SP 2 gt SP VYy Y gt Msp Msp 1 SP 2 gt SP Xy X_ gt Msgp Mgp 4 SP 2 gt SP B A gt Msp Msp 1 SP 1 SP CCR Mgp Address Mode Machine Coding Hex 18tn tn 30 39 or tn 40 FF F7hh11 E7 xb E7 xb ff E7 xbee ff E7 xb E7 xbee ff 97 D7 Access Detail SXHINZVC OVSPSSPSsP rPO rPf rPO frPP fIfrPf fIPrPf
113. access any memory locations to complete the instruction NOP this instruction has no operands INX operand is a CPU register 4 2 3 Immediate Addressing Mode Operands for immediate mode instructions are included in the instruction and are fetched into the instruction queue one 16 bit word at a time during normal program fetch cycles Since program data is read into the instruction queue several cycles before it is needed when an immediate addressing mode operand is called for by an instruction it is already present in the instruction queue The pound symbol is used to indicate an immediate addressing mode operand One very common programming error is to accidentally omit the symbol This causes the assembler to misinterpret the following expression as an address rather than explicitly provided data For example LDAA 55 means to load the immediate value 55 into the A accumulator while LDAA 55 means to load the value from address 0055 into the A accumulator Without the symbol the instruction is erroneously interpreted as a direct addressing instruction LDAA 555 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 LDX 51234 LDY 567 The size of the immediate operand is implied by the instruction context In the third example the instruction implies a 16 bit immediate value but only an 8 bit value is supplied In this case the assembler generates t
114. address to which SP points plus one After PSHD executes SP points to the stacked value of A Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine Complementary pull instructions can restore the saved CPU registers just before returning from the subroutine S X H I N Z V C Address Machine Source Form Mode Code Hex CPU Cycles PSHD INH 3B OS For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 PS H X Push X onto Stack PS H X Operation SP 0002 SP Xp XL Msp Mgp 1 Decrements SP by two and loads the high byte of X into the address to which SP points Loads the low byte of X into the address to which SP points plus one After PSHX executes SP points to the stacked value of the high byte of X Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine Complementary pull instructions can restore the saved CPU registers just before returning from the subroutine CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex PSHX INH 34 OS For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc PS H Y Push Y onto Stack PS H Y Operation SP 0002 SP Yq
115. alle qaje HIE HI dW0 END END adNOD YANO VAD Yano Yano Woo WOO ENOD VWOO ANa NYa AIGA WAN e lilo Lele a LOJE L8 9 v e Ivje 16 lelp 14 9o e 9 s keje eje zik tig 10 e xaivz alz idj e wie xa alz idj e wije xajre ali Hito alt ale we wie HI dans dans dans dans vans vans vans vanS DAN SAN GOAN VOAN X1INd WHE OOGNY UND o04 9 r E OAJE 0a 09 08 9v e ovy e 06 08 p_ OZ 9 e 09 os Obvle oeje 0z O 00 dew apodo Sc p For More Information On This Product O MOTOROLA Go to www freescale com Core User Guide s12cpu IR afscale Semiconductor Inc saj q jo Jaquinn 1 HI lt apou sseippy eidads ys juesayu HI paxapu dI ANDA Juw 2NJe 91 Ty papuajxe X4 sejo o jo JaquINN g 00 e apodo xaH aJelpauu NI 141p q Suopenesqqe epow sseippy Zz Hiz Hie Alle Hlje He He Hez Hile Alle Hile Alle He Gye ase xaz al dVHL dvel dVel dvel dvel dVHL dvel dVul dvel dvel del dvel Tala 3181 ANINI val ot alot alot aalo 300 alot viol 6 0 glot zlot 49 01 3GO0L aplot aele dzl Liz 40 Z HZ HZ HZ Hie Hz Hz Hz Hz He He He He ale alse alz HI dVHL dvel dVel dvel dvel dVHL dvel dVel dvel dvel dvel dvel dOLS 1987 WXVWS avL OL 330 35 0 3q0l 300 aglo avlo gelor 3
116. and peri_clk4 the main peripheral clock peri_clk34 and the system clk23 peri_clk23 to the Core the Core uses peri_clk23 to generate the ECLK signal The method of clock generation i e crystal PLL etc is left up to the system integrator as long as the clocks provided meet the phase relationship shown in the figure For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 peri_clk24 TAT3 TATUTATSYT4 _ A A VS VS VS US peri_clk34 T374 T1T2 EFN peri_clk23 T2T3 T4T1 Y Pe ea a ee peri_clk2 TA TA EA A PA PA peri_clk4 T TA a a PA Figure 8 2 System Clock Timing Diagram The remaining clock input to the Core peri_phase_oscdX is the same frequency as the peri_clk34 as derived directly from the oscillator When using the PLL for the system clocks the BDM sub block must maintain a constant rate clock and cannot depend upon the use of the PLL generated clock Because of this this signal operates at the same frequency as peri_clk34 prior to engaging the PLL or as derived directly from the oscillator Once the PLL is engaged this clock must maintain the pre PLL frequency in order to keep the BDM synchronized 8 1 2 Reset Relationship The Core depends upon the use of two input signals reset_pin_ind and peri_reset_ta4 for controlling the reset conditions of all logic within the Core The active low r
117. are available CCR Effects S XH I N ZV C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Set if the operation produces a two s complement overflow if and only if B was 7F before the operation cleared otherwise Code and CPU Source Form S Code Hex CPU Cycles Cycles For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc N S Increment SP N S same as LEAS 1 SP Operation SP 0001 SP Adds one to SP INS assembles as LEAS 1 SP INS does not affect condition code bits as INX and INY instructions do CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex INS IDX 1B 81 Pf For More Information On This Product Go to www freescale com INX Operation CCR Effects Code and CPU Cycles Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Increment X N X X 0001 X Adds one to X LEAX 1 X can produce the same result but LEAX does not affect the Z bit Although the LEAX instruction is more flexible INX requires only one byte of object code S X H I N Z V C Z Set if result is 0000 cleared otherwise Address Machine CPU Cycles Source Form Mode Code Hex For More Information On This Product Go to www freescale com Core User Guide INY Operation
118. as an emulation chip select signal for the emulation of the internal memory expansion or as general purpose I O depending upon the state of the EMK bit in the MODE register While this bit is used as a chip select the external bit will return to its de asserted state vdd for approximately 1 4 cycle just after the negative edge of ECLK unless the external access is stretched and ECLK is free running ESTR bit in EBICTL 0 See the HCS12v1 5 MMC spec for additional details on when this signal will be active Bit 6 Port K bit 6 This bit is used as an external chip select signal for most external accesses that are not selected by ECS see the MMC spec for more details depending upon the state the of the EMK bit in the MODE register While this bit is used as a chip select the external pin will return to its de asserted state vdd for approximately 1 4 cycle just after the negative edge of ECLK unless the external access is stretched and ECLK is free running ESTR bit in EBICTL 0 Bit 5 Bit O Port K bits 5 0 These six bits are used to determine which Flash ROM or external memory array page is being accessed They can be viewed as expanded addresses XAB19 XAB14 of the 20 bit address used to access up tolM byte internal Flash ROM or external memory array Alternatively these bits can be used for general purpose I O depending upon the state of the EMK bit in the MODE register 12 3 15 Port K Data Direction Register DDRK
119. bai Gane mecha ered 171 O A E E E E 171 10 12 A teu dys Ges gine meee bead SL aba eee eee ees 172 1032 Interface SIGHS nr 2 cee Se orci ahr EN Ar od 172 103 REgISterS ere rarna e aitor ire 173 10 3 1 Interrupt Test Control Register nannaa aana 173 10 3 27 Interrupt Test Registers 232 5 ce ES A 174 10 3 3 Highest Priority Interrupt Optional nananana aaea 175 T04 Operation 2 sree tims seh ries wine Pte hake eM SE eS Ses e ENE ee eed 175 10 4 1 Interrupt Exception Requests nassa anena 175 10 4 2 Reset Exception Requests vr cirio bicis riada 176 10 4 3 Exception Priority rt a a hoe wei ei or a a a E ayes eae Lie 176 10 57 Modesof Operations se Labra tea Ai me ES E a 177 10 5 1 Normal Operation as a e 177 10 5 27 Special Operatii rss se A A det Se ae 177 10 5 3 Emulation Modes 4 210258 oe Ae cece A ada beret Bee ened eee 177 10 6 Low Power Options os uni aisladas re 177 106A RUMMOdG cacas a a o are Tae hate aes at ae EA AEE Ea AEA EEN 177 106 2 Wat Mode tari siz amp oe atada tae rta 177 106 3 la AAA A E NN 177 10 7 Motorola Internal IntORMAtON 1 20 00 toos a 177 Section 11 Module Mapping Control MMC For More Information On This Product Go to www freescale com Core User Guide si2cpu Rf Scale Semiconductor Inc ET SOWGIVIOW a bs A OR OTR e y a ra 179 PA A ED 179 11 1 2 Block DIO dci e e Bei a RA eto 180 11 2 nterface SIGN AIS 6516 unseen Sais Nee Yung beet ira 180 11 374 TRE
120. bit Data Register MEBI Port A 8 bit Data Direction Register MEBI MEBI Port B 8 bit Data Direction Register Port E 8 bit Data Register MEBI Port E 8 bit Data Direction Register 000C PUCR MEBI MEBI Port E Assignment Register configures functionality of Port E as general purpose I O and or alternate functions 000B MODE MEBI Used to establish mode of operation of the Core and configure other miscellaneous functions Pullup Control Register to configure state of pullups on Ports A B E and K For More Information On This Product Go to www freescale com Core User Guide Address 000D si2cpu A A8gscale Semiconductor Inc Table 3 1 Core Register Map Reference Name Sub block Description Reduced Drive Register to configure drive strength of pins RDRIV MEBI associated with Ports A B E and K EBICTL MEBI External Bus Interface Control Register to configure functionality of external E clock signal INITRM MMC Initialization of Internal RAM Position Register INITRG Initialization of Internal Registers Position Register ITEST Interrupt Test Register used in special modes of operation testing interrupt logic C INITEE C Initialization of Internal EEPROM Registers Position Register MISC C Miscellaneous Register to configure various system functions ITCR Interrupt Test Control Register used in special modes of operation for testing interrupt logic MEMSIZO MMC Memory Siz
121. bit constant offset indexed indirect addressing IDX2 7 6 5 4 3 2 1 0 Postbyte 1 1 1 rr Oo 1 1 two offset extension bytes X Y SP or PC is address of pointer to effective address Accumulator D offset indexed indirect addressing D IDX 7 6 5 4 3 2 1 0 Postbyte 1 1 1 om 1 1 1 X Y SP or PC D is address of pointer to effective address NOTES 1 rr selects X 00 Y 01 SP 10 or PC 11 2 aa selects A 00 B 01 or D 10 3 In autoincrement decrement indexed addressing PC is not a valid selection 4 p selects pre 0 or post 1 increment decrement 5 Increment values range from 0000 1 to 0111 8 Decrement values range from 1111 1 to 1000 8 6 s is the sign bit of the offset extension byte All indexed addressing modes use a 16 bit CPU register and additional information to create an indexed address In most cases the indexed address is the effective address of the instruction that is the address of the memory location that the instruction acts on In indexed indirect addressing the indexed address is the location of a value that points to the effective address For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 PC offsets are calculated from the location immediately following the current instruction 1000 18 09 C2 20 00 MOVB 2000 2 PC 1005 A7 NOP This example moves a byte o
122. comparison can be used for conditional branches The values in A and B do not change N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V A7 e B7 e R7 A7 e B7 e R7 set if the operation produces a two s complement overflow cleared otherwise C A7 B7 B7 e R7 R7 A7 set if there is a borrow from the MSB of the result cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles CBA INH 18 17 OO For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc C LC same nce FE C LC Operation CCR Effects Code and CPU Cycles 0 gt C bit Clears the C bit CLC assembles as ANDCC FE CLC can be used to initialize the C bit prior to a shift or rotate instruction affecting the C bit C Cleared Address Machine Source Form Mode Code Hex CPU Cycles CLC IMM 10 FE P For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 C LI same Prine EF C LI Operation 0 Ibit Clears the I bit CLI assembles as ANDCC EF Clearing the I bit enables interrupts There is a one cycle bus clock delay in the clearing mechanism If interrupts were previously disabled the next instruction after a CLI is always executed even if there was an interrupt pending prior to exec
123. core_ramhal_t2 This single bit Core output reflects the state of the RAMHAL bit in the INITRAM register within the Module Mapping Control MMC sub block of the Core Please see Section 11 of this guide for further functional details 7 2 1 17 On Chip EEPROM register select signal core_eeregsel_t2 This single bit Core output indicates that the Core is accessing an address within the on chip EEPROM register space of the system memory map 7 2 1 18 On Chip EEPROM array select signal core_eearraysel_t2 This single bit Core output indicates that the Core is accessing an address within the on chip EEPROM array space of the system memory map 7 2 1 19 On Chip Flash EEPROM register select signal core_feeregsel_t2 This single bit Core output indicates that the Core is accessing an address within the on chip Flash EEPROM register space of the system memory map 7 2 1 20 On Chip Flash EEPROM array select signal core_feearraysel_t2 This single bit Core output indicates that the Core is accessing an address within the on chip Flash EEPROM array space of the system memory map 7 2 1 21 On Chip EEPROM hold signal to Core ee_hold_t1 This single bit input to the Core is used to suspend operation of the CPU when needed for functions of the on chip EEPROM memory block 7 2 1 22 On Chip Flash EEPROM hold signal to Core fee_hold_t1 This single bit input to the Core is used to suspend operation of the CPU when needed for functions of the
124. cycles caused by an interrupt sss is the exit sequence and UUUrr is the eens sequence XGDXSame as EXGD X Exchange D with X D X For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide Y 1 8 1 Register and Memory Notation Aora An Table 1 3 Register and Memory Notation Accumulator A Bit n of accumulator A 12CPU15UG V1 2 Borb Bn Dord Accumulator B Bit n of accumulator B Accumulator D Dn X or x XH Bit n of accumulator D Index register X High byte of index register X XL Low byte of index register X Xn Yory Yu Bit n of index register X Index register Y High byte of index register Y YL Low byte of index register Y Yn SP or sp Bit n of index register Y Stack pointer SPn Bit n of stack pointer PC or pc PCy PCL Program counter High byte of program counter Low byte of program counter CCRorc Condition code register Address of 8 bit memory location Bit n of byte at memory location M Bit n of the result of an arithmetic or logical operation RTNy Bit n of the intermediate result of an arithmetic or logical operation High byte of return address RTN Low byte of return address 1 8 2 Source Form Contents of Notation The Source Form column of the summary in Table 1 2 gives essential information about ass
125. extra level of indirection compared to ordinary indexed addressing The two forms of indexed indirect addressing are 16 bit constant offset indexed indirect and accumulator D indexed indirect The indexing register can be X Y SP or PC as in other HCS12 indexed addressing modes PC relative indirect addressing is one of the more common uses of indexed indirect addressing The indirect variations of indexed addressing help to implement pointers Accumulator D indexed indirect addressing can implement a runtime computed GOTO function Indirect addressing is also useful in high level language compilers For instance PC relative indirect indexing can efficiently implement some C case statements C 6 Improved Performance HCS12 based systems provide a number of performance improvements over the M68HC11 These improvements include cycle count reduction faster math instruction execution and reduction of code size Each of these aspects is discussed in the subsections below C 6 1 Reduced Cycle Counts No M68HC11 instruction takes less than two cycles but the HCS12 has more than 50 opcodes that take only one cycle Some of the reduction comes from the instruction queue which assures that several program bytes are available at the start of each instruction Other cycle reductions occur because the HCS12 can fetch 16 bits of information at a time rather than eight bits at a time C 6 2 Fast Math The HCS12 has some of the fastest math ever designed in
126. for the block select signals MT14 Mapping Test Register 3 Bit 4 BKGDPUE This bit used to enable disable the pull up on the BKGD pin Normal amp Emulation Write never Special Write anytime 1 The pull up on the BKGD pin is enabled 0 The pull up on the BKGD pin is disabled MT 13 10 Mapping Test Register 1 Bits 3 0 For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc 11 5 2 MMC Bus Control This subsection discusses aspects of the bus control multiplexing performed by the MMC 11 5 2 1 Address Bus The MMC multiplexes the EBI Alternate Address Bus BDM Alternate Address Bus and the CPU Address Bus to form the main address bus for the Core The EBI Alternate Address Bus is the address bus source in peripheral mode The BDM Alternate Address Bus is the address bus source whenever the BDM 1s driving the bus The CPU Address Bus is the address bus source whenever the CPU has a valid address the BDM is not driving the bus and the system is not operating in peripheral mode 11 5 2 2 Write Data Bus The CPU Write Data bus EBI Alternate Write Data bus or BDM Alternate Write Data bus supply data to the master bus The CPU Write Data bus is the write data source unless the cycle is a BDM access or the system is operating in peripheral mode The BDM Alternate Write Data bus is the write data source only when the BDM is driving the bus The EBI Alternate Write Data b
127. from the Core provides the bit by bit output buffer enable signal to the system port pad logic for Port E 7 2 2 16 Port E input buffer enable from Core core_peibe _t2 This single bit output from the Core provides the input buffer enable signal to the system port pad logic for Port E For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc 7 2 2 17 Port E pullup enable from Core core_pepue_t2 This single bit output from the Core indicates that the pullup devices within the system port pad logic for Port E should be enabled for all Port E pins except the MODA PES and MODB PE6 pins 7 2 2 18 Port E MODE pin pullup enable from Core core_mdrste This single bit output from the Core indicates that the pullup devices within the system port pad logic for the MODA PE5 and MODB PE6 pins within Port E should be enabled 7 2 2 19 Port E drive strength enable from Core core_pedse_t2 This single bit output from the Core indicates whether all Port E pins will operate with full or reduced drive strength 7 2 2 20 Port K Input Data to Core core_pkind 7 0 This 8 bit wide input to the Core provides the Core with the input data from the system port pad logic for Port K 7 2 2 21 Port K Output Data from Core core_pkdo 7 0 This 8 bit wide output from the Core provides the Port K data output to the system port pad logic for Port K 7 2 2 22 Port K output buffer
128. fuzzification step begins the current value of the system input is in an accumulator one index register points to the first membership function definition in the knowledge base and a second index register points to the first fuzzy input in RAM As each fuzzy input is calculated by executing a MEM instruction the result is stored to the fuzzy input and both pointers are updated automatically to point to the locations associated with the next fuzzy input The MEM instruction takes care of everything except counting the number of labels per system input and loading the current value of any subsequent system inputs The end result of the fuzzification step is a table of fuzzy inputs representing current system conditions For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc MEMBERSHIP FUNCTIONS FOR TEMPERATURE FUZZY INPUTS FF C0 80 40 00 TEMPERATURE IS HOT 00 0 F 32 F 64 F 96 F 128 F FF C0 80 TEMPERATURE IS WARM 40 00 o F 32 F 64 F 96 F 128 F FF gt C0 80 TEMPERATURE IS COLD C0 00 0 F 32 F 64 F 96 F 128 F CURRENT TEMPERATURE IS 64 F Figure B 2 Fuzzification Using Membership Functions B 3 2 Rule Evaluation REV and REVW Rule evaluation is the central element of a fuzzy logic inference program This step processes a list of rules from the knowledge base using current fuzzy input
129. fuzzy logic programs B 2 Introduction There are four instructions that perform fuzzy logic tasks Several other instructions are also useful in fuzzy logic programs This section explains the basic fuzzy logic algorithm for which the four fuzzy logic instructions are intended Each fuzzy logic instruction is then explained in detail Finally other custom fuzzy logic algorithms are discussed with emphasis on other useful instructions The four fuzzy logic instructions are e MEM evaluates trapezoidal membership functions e REV and REVW perform unweighted or weighted MIN MAX rule evaluation e WAV performs weighted average defuzzification on singleton output membership functions Other instructions that are useful for custom fuzzy logic programs include MINA EMIND MAXM EMAXM TBL ETBL and EMACS For higher resolution fuzzy programs the extended math instructions are also useful Indexed addressing modes help simplify access to fuzzy logic data structures stored as lists or tabular data structures in memory B 3 Fuzzy Logic Basics This overview of basic fuzzy logic concepts is the background for a detailed explanation of the fuzzy logic instructions In general fuzzy logic provides for definitions of sets that have fuzzy boundaries rather than the crisp boundaries of Aristotelian logic The sets can overlap so that for a particular input value one or more sets may be true at the same time As the input varies out of the
130. generates the signals for the CPU for the tag high tag low force SWI and force BDM functions In addition it generates the register read and write signals and the comparator block enable signals NOTE There is a two cycle latency for address compares for forces a two cycle latency for write data compares and a three cycle latency for read data compares For More Information On This Product Go to www freescale com BKP Read Data Bus Write Data Bus Freescale Semiconductor ING cuide s12cPU15UG V1 2 Clocks and control signals BKP control signals CONTROL BLOCK Breakpoint Modes and generation of SWI force BDM amp tags EXPANSION F ADDRESS S 8 8 2 ADDRESS O EE r WRITE DATA m READ DATA FE IE ee REGISTER BLOCK BKPCTO BKPCT1 Ca COMPARE BLOCK expansion addresses Comparator EN expansion addresses P con read data low Figure 13 1 Breakpoint Block Diagram address low data high Data Address High Mux address high data low Data Address Low Mux address low read data high ro 208 For More Information On This Product Go to www freescale com Core User Guide 13 2 Interface Signals All interfacing with the Breakpoint sub block is done within the Core 13 3 Registers siocpurmtaRscale Semiconductor Inc A summary of the registers associated with the Breakpoint sub bloc
131. have no effect These registers are not in the on chip map in peripheral mode 12 3 14 Port K Data Register PORTK Address Base 32 Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Alpin Ecs XCS XAB19 XAB18 XAB17 XAB16 XABI5 XAB14 function as Unimplemented Figure 12 16 Port K Data Register PORTK Reset Read anytime Write anytime This port is associated with the internal memory expansion emulation pins When the port is not enabled to emulate the internal memory expansion the port pins are used as general purpose I O When Port K is operating as a general purpose I O port DDRK determines the primary direction for each Port K pin A 1 causes the associated port pin to be an output and a 0 causes the associated pin to be a For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 high impedance input The value ina DDR bit also affects the source of data for reads of the corresponding PORTK register If the DDR bit is zero input the buffered pin input is read If the DDR bit is one output the output of the port data register is read This register is not in the map in peripheral or expanded modes while the EMK control bit in MODE register is set When inputs these pins can be selected to be high impedance or pulled up based upon the state of the PUPKE bit in the PUCR register Bit 7 Port K bit 7 This bit is used
132. if Plus B D L If N 0 then PC 0002 rel gt PC Tests the N bit and branches if N 0 Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction S X H I N Z V C Address Machine Source Form Mode Code Hex Source Form BPL rela REL 2A rr PPP branch P no branch Branch Complementary Branch F Comment Mnemonic Opcode Test Mnemonic Opcode Test Positive Negative BPL 2A BMI 2B Simple For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc BRA Branch Always BRA Operation PC 0002 rel PC Branches unconditionally Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction Execution time is longer when a conditional branch is taken than when it is not taken because the instruction queue must be refilled before execution resumes at the new address Since the BRA branch condition is always satisfied the branch is always taken and the instruction queue must always be refilled CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex
133. in Figure 15 1 HCS12 V1 5 Core System Memories secreq y 5 Security Register M M C core_secure_t2 Module Flash Mapping EEPROM Control Bus Signals BDM BDM BDM Bus Signals BKGD Background Signal a M EEPROM Pin Debug Mode MEBI RAM Multiplexed External Bus Interface Figure 15 1 Security Implementation Block Diagram This figure includes one example system implementation of the Core security feature In this implementation the Flash EEPROM block contains a security register that is programmed to the proper secured un secured state which generates a security request to the Core See 15 4 for a complete description of the operation of the secured mode 15 2 Interface Signals The Core interface signals associated with the secured mode of operation are shown in Table 15 1 below The functional descriptions of the signals are provided below for completeness Table 15 1 Security Interface Signal Definitions Signal Name Type Functional Description core_secure_t2 Core secure mode signal secreq Security mode request from applicable memory 15 2 0 1 Core Secure Mode indicator core_secure_t2 This single bit Core output indicates that the Core is operating in secured mode For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 15 2 0 2 Core Security Request secreq This single bit input indicates
134. in the LDS instruction Since the stack builds downward M68HC11 programs reassembled for the HCS12 operate normally but the program stack is one physical address lower in memory In very uncommon situations such as test programs used to verify CPU operation a program could initialize the SP stack data and then read the stack via an extended mode read it is normally improper to read stack data from an absolute extended address To make an M68HC11 source program that contains such a sequence work on the HCS12 change either the initial LDS xxxx or the absolute extended address used to read the stack C 5 Improved Indexing The HCS12 has significantly improved indexed addressing capability yet retains compatibility with the M68HC11 The one cycle and one byte cost of doing Y related indexing in the M68HC11 has been eliminated In addition high level language requirements including stack relative indexing and the ability to perform pointer arithmetic directly in the index registers have been accommodated The M68HC11 has one variation of indexed addressing that works from X or Y as the reference pointer For X indexed addressing an 8 bit unsigned offset in the instruction is added to the index pointer to arrive For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc at the address of the operand for the instruction A load accumulator instruction assembles into two byte
135. instruction EMAXM 2 X process one rule consequent The M at the end of the mnemonic indicates that the result replaces the referenced memory operand Again indexed addressing is used These two instructions can form the working part of a 16 bit resolution fuzzy inference routine For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc There are many other methods of performing inference but the min max method is most widely used Since the HCS12 is a general purpose microcontroller the programmer has complete freedom to program any algorithm desired A custom algorithm would typically take more code space and execution time than a routine that used the built in REV or REVW instructions B 8 3 Defuzzification Variations There are two main areas where other HCS12 instructions can help with custom defuzzification routines The first case is working with operands with more than eight bits The second case involves using an entirely different approach than weighted average of singletons The primary part of the WAV instruction is a multiply and accumulate operation to get the numerator for the weighted average calculation When working with operands as large as 16 bits the EMACS instruction could at least automate the multiply and accumulate function The HCS12 CPU has extended math capabilities including 32 bit by 16 bit divide instructions and the EMACS instruction wh
136. is greater than FFFF cleared otherwise undefined after division by 0 C Set if divisor is 0000 cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles EDIV INH 11 ffffffffffo For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 E D VS Extended Divide Signed E D IVS Operation CCR Effects Code and CPU Cycles Y D X Y remainder gt D Divides a signed 32 bit dividend by a 16 bit signed divisor producing a signed 16 bit quotient and a signed 16 bit remainder All operands and results are located in CPU registers Division by zero has no effect except that the C bit is set and the states of the N Z and V bits are undefined S X H I N Z V C N Set if MSB of result is set cleared otherwise undefined after overflow or division by 0 Z Set if result is 0000 cleared otherwise undefined after overflow or division by 0 V Set if the result is greater than 7FFF or less than 8000 cleared otherwise undefined after division by 0 C Set if divisor is 0000 cleared otherwise indicates division by 0 Address Machine Source Form Mode Code Hex CPU Cycles EDIVS INH 18 14 OffffffffffO For More Information On This Product Go to www freescale com Core User Guide siocpuimtaRscale Semiconductor Inc E M ACS Extended Multiply and Accumulate E M ACS Signed Operation CCR Effects
137. is more than one flow path through the REV instruction cycle numbers have a decimal place This decimal place indicates which of several possible paths is being used The CPU normally moves forward by one digit at a time within the same flow The flow number is indicated after the decimal point in the cycle number There are two exceptions possible to this orderly sequence through an instruction The first is a branch back to an earlier cycle number to form a loop as in 6 0 to 4 0 The second type of sequence change is from one flow to a parallel flow within the same instruction such as 4 0 to 5 2 which occurs if the REV instruction senses an interrupt In this second type of sequence branch the whole number advances by one and the flow number the digit after the decimal point changes to a new value In cycle 1 0 the CPU does an optional program word access to replace the 18 prebyte of the REV instruction Notice that cycle 7 0 is also an O cycle One of these cycles is a program word fetch while the other is a free cycle in which the CPU does not access the bus Although the 18 page prebyte is part of the REV instruction the CPU treats it as a separate single cycle instruction For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide START Read program word if 18 misaligned Read byte 0 X rule element Rx X X 1 point at next rule element Update Ry with value read in cycle 2 or 5
138. l Exp Wide EE Unimplemented Figure 12 9 Port E Assignment Register PEAR Read anytime provided this register is in the map Write each bit has specific write conditions Please refer to the descriptions of each bit on the following pages Port E serves as general purpose I O or as system and bus control signals The PEAR register is used to choose between the general purpose I O function and the alternate control functions When an alternate control function is selected the associated DDRE bits are overridden The reset condition of this register depends on the mode of operation because bus control signals are needed immediately after reset in some modes In normal single chip mode no external bus control signals are needed so all of Port E is configured for general purpose I O In normal expanded modes only the E clock is configured for its alternate bus control function and the other bits of Port E are configured for general purpose I O As the reset vector is located in external memory the E clock is required for this access R W is only needed by the system when there are external writable resources If the normal expanded system needs any other bus control signals PEAR would need to be written before any access that needed the additional signals In special test and emulation modes IPIPE1 IPIPEO E LSTRB and R W are configured out of reset as bus control signals For More Information On This Product Go to www freescale c
139. mathematical calculations for fuzzy logic operations 4 2 Addressing Modes A summary of the addressing modes used by the Core is given in Table 4 1 below The operation of each of these modes is discussed in the subsections that follow Table 4 1 Addressing Mode Summary Addressing Mode Inherent Source Form INST no externally supplied operands Abbreviation Description Operands if any are in CPU registers Immediate INST opr8i or INST opr16i Operand is included in instruction stream 8 bit or 16 bit size implied by context Direct Extended INST opr8a INST opr16a Operand is the lower 8 bits of an address in the range 0000 00FF Operand is a 16 bit address Relative INST rel8 or INST rel16 Effective address is the value in PC plus an 8 bit or 16 bit relative offset value Indexed 5 bit offset Indexed predecrement Indexed preincrement INST oprx5 xysp INST oprx3 xys INST oprx3 xys Effective address is the value in X Y SP or PC plus a 5 bit signed constant offset Effective address is the value in X Y or SP autodecremented by 1 to 8 Effective address is the value in X Y or SP autoincremented by 1 to 8 Indexed postdecrement INST oprx3 xys Effective address is the value in X Y or SP The value is postdecremented by 1 to 8 For More Information On This Product Go to www freescale com Core User G
140. memory read data bus signals ram_rdb_L12 ee_rdb_L12 or fee_rdb_L12 and core_MSEL_t2 represents any of the on chip memory register or array selects such as core_ramregsel_t2 or core_ramarraysel_t2 for the RAM and likewise for the EEPROM and Flash EEPROM For More Information On This Product Go to www freescale com Freescale Semiconductor IQ guide s12cPU15UG V1 2 peri_clk24 PTA TS TATTA 7 UV V V VYA V AAN core_ab_t2 X addri addr3 X core_wdb_t4 X data data3 core_MSEL_t2 mE ES eee O SAD corea A A O OA RA o S core _sz8_t2 8 BIT 8BIT E peri_clk34 1 N E k rn A Figure 7 10 Basic 8 bit Memory Write Timing peri_clk24 ATTA I UV V VYA NE AVA core_ab_t2 X addr1 addr3 X core_wdb_t4 X_ datai data3 core_MSEL_t2 core_rw_t2 A AA SS SA ES Coes Sie core_sz8_t2 16 BIT 16 BIT peri_clk34 f Figure 7 11 Basic 16 bit Memory Write Timing 7 3 2 3 Internal Core Register Writes The timing for basic 8 bit and 16 bit writes of internal Core registers are shown in Figure 7 12 and Figure 7 13 respectively For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc peri_clk24 TAS TAT TA A A a A NP NS E AN core_ab_t2 X adadri addr3 X core_wdb_t4 X data1 data3 core RSEL_t4 core wt2
141. mode Branch if gt 0 signed if Z NOV 0 then PC 2 rel gt PC PP branch no branch PP branch P no branch PP branch no branch BHS re 8Same as BCC BITA opr8i BITA opr8a BITA opr16a BITA oprx0_xysppc BITA oprx9 xysppc BITA oprx16 xysppc BITA D xysppc BITA oprx16 xysppc Branch if higher unsigned if C Z 0 then PC 2 rel gt PC Branchifhigherorsame unsigned if C 0 then PC 2 rel PC Bit test A A e M or A eimm 854i 95 dd B5hh11 A5 xb A5xbff A5xbee ff A5 xb A5xbee ff PP branch no branch PP branch no branch pD rPf rPO rP rPO frPP fIfrPf fIPrPf BITB opr8i BITB opr8a BITB opr16a BITB oprx0_xysppc BITB oprx9 xysppc BITB oprx16 xysppc BITB D xysppc BITB oprx16 xysppc BLO rel8Same as BCS Bit test B B e M or B eimm Branchif lt 0 signed ifZ N V 1 then PC 2 rel gt PC Branch if lower unsigned if C 1 then PC 2 rel gt PC Codi D5 dd F5hh11 E5xb E5xb ff E5 xbee ff E5 xb E5 xbee ff P rPf TPO rPf rPO frPP fIfrPf fIPrPf PP branch no branch P branch no branch BLS rel8 Branch if lower or same unsigned if C Z 1 then PC 2 rel gt PC Branch if lt 0 signed if NOV 1 then PC 2 rel gt PC Branch if minus if N 1 then PC 2 rel gt PC PP branch no branch PP b
142. mul V C 1 and Rx FFFE 6 3 f No bus access Adjust X X 2 pointer to rule list TED max V 1 and Rx FFFE or FFFF 6 1 x IFA gt FRx write A to Rx else no bus acces 7 3 f No bus access If Rx FFFE and V 0 andC 1 then TMP2 TMP2 1 No bus access A min A FRx Continue to interrupt stacking Ry FF end of rules Yes Read program word if 3B misaligned No bus access Begin multiply of wt 1 x A gt A B Continue multiply Adjust PC to point at next instruction If C 1 weights enabled Y TMP2 1 Read rule word D Xy No bus access Finish multiply Figure B 10 REVW Instruction Flow Diagram After all rules are processed cycle 7 0 updates the PC to point at the next instruction If weights are enabled Y is updated to point at the location that immediately follows the last rule weight For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 B 7 WAV Instruction Details The WAV instruction performs weighted average calculations used in defuzzification The pseudoinstruction wavr resumes an interrupted weighted average operation WAV calculates the numerator and denominator sums using n Y SF system output n yr i 1 where n is the number of labels of a system output S are the singleton positions from the know
143. not change The X bit can be cleared as a result of a TAP but cannot be set if it was cleared prior to execution of the TAP If the I bit is cleared there is a one cycle delay before the system allows interrupt requests This delay prevents interrupts from occurring between instructions in the sequences CLI WAI and CLI SEI TAP assembles as TFR A CCR S X H I N Z V C a t a a a ala a Condition codes take on the value of the corresponding bit of accumulator A except that the X mask bit cannot change from 0 to 1 Software can leave the X bit set leave it cleared or change it from 1 to 0 but it can only be set by a reset or by recognition of an XIRQ interrupt Address Machine For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc TBA Transfer B to A TBA Operation CCR Effects Code and CPU Cycles B gt A Loads the value in B into A The former value in A is lost the value in B does not change Unlike the general transfer instruction TFR B A which does not affect condition code bits the TBA instruction affects the N Z and V bits N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Address Machine Code For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 T B E Q Test and Branch if Equal t
144. o nee tee eee ee eM eur ee ee A A 503 B 2 gt INTOdUCHON 20 sera AD nena se Sj Seed ESA AAN 503 E a is ln A By to a eE a a 503 B 3 1 FUZANMCANOA MENS seco A ENE 505 B 3 2 Rule Evaluation REV and REVW 0 0 0 eee eee 506 B 3 3 Defuzzification WAN costat a ot oi bake Di eins oes 508 B 4 Example Inference Kernel 0 000 cee eee 508 Bi MEM Instruction Detalls seisde rs att ida 510 B 5 1 Membership Function Definitions 000 00 eee ee 510 B 5 2 Abnormal Membership Function Definitions 0002e eee ee eee 511 B 6 REV REVW Instruction Details gig eek coo de lada nok Meno in hee 514 B 6 1 Unweighted Rule Evaluation REV ooooccoooccccocnnoo 514 B 6 2 Weighted Rule Evaluation REVW oooccccccccccoco eee 518 B 7 WAV Instruction Details ati Ai tes 523 B 7 1 Initialization Prior to Executing WAV 00000 cee eee 523 B 7 2 WAN Interrupt DetdllS 222s 8 oo et birds 523 B 7 3 Cycle by Cycle Details for WAV and WaWr ooooocccococccc eee 524 B 8 Custom Fuzzy Logic Programming esos dma dba daria dede 527 B 8 1 Fuzzification Variations e ss A o da le pelada AA to 527 B 8 2 Rule EVAN AORN ANAMON Se sig ce Mtoe E A eee Rae id ag 529 B 8 3 Defuzzification VANAlONS gt tocar Spee reat 36 Ow a aa ene oe Od 530 Appendix C M68HC11 to HCS12 Upgrade Cel Generalene A AAA E GE eee A AAA AS EA 531 C 2 Source Code Compatibility oooooccooooonrrnnooo
145. of FFFC An offset that points to the opcode can cause a branching bit condition instruction to repeat execution until the specified bit condition is satisfied Since branching bit condition instructions can consist of four five or six bytes depending on the addressing mode used the offset value that sets up a loop can vary For instance an offset of FC in a 4 byte BRCLR instruction sets up a loop that executes until all the bits in the tested memory byte are clear 4 2 7 Indexed Addressing Modes There are seven indexed addressing modes e 5 bit constant offset e Autodecrement increment e 9 bit constant offset For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 16 bit constant offset 16 bit constant offset indexed indirect Accumulator offset Accumulator D offset indexed indirect Features of indexed addressing include The stack pointer can be used as an indexing register in all indexed operations The program counter can be used as an indexing register in all but autoincrement and autodecrement modes A B or D accumulators can be used for accumulator offsets Automatic pre or postincrement or pre or postdecrement by 8 to 8 A choice of 5 9 or 16 bit signed constant offsets Two indexed indirect modes Indexed indirect mode with 16 bit offset Indexed indirect mode with accumulator D offset 4 2 7 1 Indexed Addressing Postbyte A po
146. of minimum and maximum operations that work with the fuzzy MIN MAX inference algorithm The problem with the fuzzy inference algorithm is that the min and max operations need to store their results differently so the min and max instructions must work differently or more than one variation of these instructions is needed The HCS12 CPU has min and max instructions for 8 or 16 bit operands with one operand in an accumulator and the other in a referenced memory location There are separate variations that replace the accumulator or the memory location with the result While processing rule antecedents in a fuzzy inference program a reference value must be compared to each of the referenced fuzzy inputs and the smallest input must end up in an accumulator The instruction EMIND 2 X process one rule antecedent automates the central operations needed to process rule antecedents The E stands for extended so this instruction compares 16 bit operands The D at the end of the mnemonic stands for the D accumulator which is both the first operand for the comparison and the destination of the result The 2 X is an indexed addressing specification that says X points to the second operand for the comparison When processing rule consequents the operand in the accumulator must remain constant in case there is more than one consequent in the rule and the result of the comparison must replace the referenced fuzzy output in RAM To do this use the
147. operation The C bit is not affected by the operation allowing the DEC instruction to be used as a loop counter in multiple precision computations N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Set if operation produces a two s complement overflow if and only if M was 80 before the operation cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles DEC opr16a EXT 73 hh 11 rPwO DEC oprx0_xysppc IDX 63 xb rPw DEC oprx9 xysppc IDX1 63 xb ff rPwO DEC oprx16 xysppc IDX2 63 xbee ff frPwP DEC D xysppc D IDX 63 xb fIfrPw DEC oprx16 xysppc IDX2 63 xbee ff fIPrPw For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 DECA Decrement A DECA Operation CCR Effects Code and CPU Cycles A 01 gt A Subtracts one from the value in A The N Z and V bits are set or cleared by the operation The C bit is not affected by the operation allowing the DEC instruction to be used as a loop counter in multiple precision computations N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Set if operation produces a two s complement overflow if and only if A was 80 before the operation cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles DECA INH 43 O For More Information On This Produc
148. oprx0_xysppc rPf SUBB oprx9 xysppc rPO SUBB oprx16 xysppc frPP SUBB D xysppc flfrPf SUBB oprx16 xysppc fIPrPf SUBD opr16i Subtract from D PO SUBD opr8a A B M M 1 gt A B RP SUBD opr16a or A B imm A B RPO SUBD oprx0_xysppc RP SUBD oprx9 xysppc RPO SUBD oprx16 xysppc f RPP SUBD D xysppc fIFRP SUBD oprx16 xysppc fIPRP Software interrupt SP 2SP VSPSSPSsP RTNyY RTN gt Mgp Mgp 1 SP 2 gt SP Yu YL Msp Mgp41 SP 2 gt SP Xy X_ Mgp Mgp 1 SP 2 SP B A Mgp Mgp 4 SP 1 SP CCR Mgp 1 gt 1 SWI vector PC The CPU also uses VSPSSPSsP for hardware interrupts and unimplemented opcode traps TAB Transfer A to B A B INH 18 0E 00 A Ayo Access Detail SXHINZVC Assembled as TFRA CCR TBA Transfer B to A B gt A INH 00 18 0F TBEQ abdxysp rel9 Test and branch if equal to 0 041lbrr PPP branch If counter 0 then PC 2 rel gt PC PPO no branch TAP Transfer A to CCR A gt CCR INH B7 02 P ATUTATATATATATA JaTa o TBL oprx0_xysppc Table lookup and interpolate 8 bit 18 3D xb ORff P M B x M 1 M A TBNE abdxysp rel9 Test and branch if not equal to 0 PPP branch If counter x0 then PC 2 rel gt PC PPO no branch TFR abcdxysp
149. or SP Transfers involving TMP2 and TMP3 are reserved for Motorola use S X H I N Z V C or S X H I N Z V C EEES CCR bits affected only when the CCR is the destination register The X bit cannot change from 0 to 1 Software can leave the X bit set leave it cleared or change it from 1 to 0 but X can only be set by a reset or by recognition of an XIRQ interrupt Address Machine Source Form Mode Code Hex CPU Cycles TFR abcdxysp abcdxysp INH B7 eb P For More Information On This Product Go to www freescale com TFR Freescale Semiconductor WOE Guide Transfer Register continued Transfer Postbyte eb Coding 12CPU15UG V1 2 TFR Source ran Transfer Postbyte Slee Transfer TFR A A 0000 X000 A gt A 0100 X000 B7 40 B gt A TFR A B A gt B 0100 X001 B7 41 B gt B TFR A CCR A CCR 0100 X010 B7 42 B gt CCR TFR A TMP2 sex A TMP2 0100 X011 B7 43 D TMP2 TFR A D sex A gt D 0100 X100 B7 44 D gt D TFR A X sex A gt X 0100 X101 B7 45 D gt xX TFR A Y sex A gt Y 0100 X110 B7 46 DY TFR A SP sex A gt SP 0100 X111 B7 47 D gt SP TFR B A B gt A 0101 X000 B750 XL A TFR B B B gt B 0101 X001 B751 X gt B TFR B CCR B CCR 0101 X010 B752 X_ CCR TFR B TMP2 sex B gt TMP2 0101 X011 8753 x TMP2 TFR B D sex B gt D 0101X100 8754 x 4p TFR B X sex B gt X 0101 X101 B755 x x TFR B Y sex B gt Y 0101 X110 B756 x sy TFR B SP sex B SP 0101X111 B757 X SP T
150. or bus On chip RAM Array select from Core to memory and or bus core_ramhal_t2 On chip RAM Array align signal from Core to memory and or bus core_eeregsel_t2 core_eearraysel_t2 On chip EEPROM Register select from Core to memory and or bus On chip EEPROM Array select from Core to memory and or bus core_feeregsel_t2 On chip Flash EEPROM Register select from Core to memory and or bus core_feearraysel_t2 On chip Flash EEPROM Array select from Core to memory and or bus ee_hold_t1 On chip EEPROM signal to Core to suspend CPU operation fee_hold_t1 On chip Flash EEPROM signal to Core to suspend CPU operation secreq Security mode request from applicable memory peri_ffxx_t3 Interrupt Bus from I P Bus Interface peri_rtifffoi_t3 Real Time Interrupt signal core_bdmact_t4 Core BDM active signal for I P Bus Interface freeze signal core_paind 7 0 External Bus Interface Signals Port A input data 7 0 core_pado 7 0 core_paobe 7 0 core_paibe_t2 Port A data output 7 0 o Port A output buffer enable 7 0 core_papue_t2 core_padse_t2 core_pbind 7 0 Port A input buffer enable Port A pullup enable O Port A drive strength enable core_pbdo 7 0 core_pbobe 7 0 core_pbibe_t2 Port B input data 7 0 Port B data output 7 0 O Port B output buffer enable 7 0 core_pbpue_t2 core_pbdse_t2 core_peind 7 0 Port B input buffer enable Port B pullup enab
151. rate The basic structure can easily be extended to a general purpose system with a larger number of inputs and outputs Lines 1 to 3 set up pointers and load the system input value into the A accumulator Line 4 sets the loop count for the loop in lines 5 and 6 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Lines 5 and 6 make up the fuzzification loop for seven labels of one system input The MEM instruction finds the y value on a trapezoidal membership function for the current input value for one label of the current input and then stores the result to the corresponding fuzzy input Pointers in X and Y are automatically updated by four and one so they point at the next membership function and fuzzy input respectively Line 7 loads the current value of the next system input Pointers in X and Y already point to the right places as a result of the automatic update function of the MEM instruction in line 5 Line 8 reloads a loop count Lines 9 and 10 form a loop to fuzzify the seven labels of the second system input When the program drops to line 11 the Y index register is pointing at the next location after the last fuzzy input which is the first fuzzy output in this system 01 2 FUZZIFY LDX INPUT_MFS Point at MF definitions 02 2 LDY FUZ_INS Point at fuzzy input table 03 3 LDAA
152. re 16 LBHI re 16 Long branch if gt 0 signed If NOVO then PC 4 rel gt PC Long branch if gt 0 signed If Z NOV 0 then PC 4 rel gt PC Long branch if higher unsigned If C Z 0 then PC 4 rel PC 182C gg rr 182E qq rr 1822qqrr p branch no branch PPP branch PO no branch PO no branch LBHS rel16Same as LBCC LBLE rel16 Long branch if higher or same unsigned If C 0 PC 4 rel gt PC Long branch if lt 0 signed if Z NOV 1 then PC 4 rel gt PC 1824gqq rr 18 2F qq rr P branch no branch PPP branch no branch O O O O O O O O O OPPP branch O O O O O O O O O LBLO rel16Same as LBCS Long branch if lower unsigned if REL 1825 qqrr PPP branch oe 9 a pe a pa C 1 then PC 4 rel gt PC PO no branch LBLS re 16 Long branch if lower or same REL 1823 qqrr PPP branch _ _ _ unsigned If C Z 1 then PO no branch PC 4 rel gt PC LBLT rel16 Long branch if lt 0 signed REL 182Dqqrr OPPP branch o alee If NOV 1 then PC 4 rel gt PC OPO no branch For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 Address Machine
153. register map which includes all Core sub blocks is included 3 1 Programming Model The Core CPU12 programming model shown in Figure 3 1 is the same as that of the 68HC12 and 68HC11 The register set and data types used in the model are covered in the subsections that follow 7 A 0 7 B O 8 BITACCUMULATORS A AND B 15 D O 16 BIT DOUBLE ACCUMULATOR D A B 15 X 0 INDEX REGISTER X 15 Y 0 INDEX REGISTER Y 15 SP 0 STACK POINTER 15 PC 0 PROGRAM COUNTER SIX H IIN Z V C CONDITION CODE REGISTER CARRY OVERFLOW ZERO NEGATIVE IRQ INTERRUPT MASK DISABLE HALF CARRY FOR BCD ARITHMETIC XIRQ INTERRUPT MASK DISABLE STOP DISABLE IGNORE STOP INSTRUCTION Figure 3 1 Programming Model 3 1 1 Accumulators General purpose 8 bit accumulators A and B hold operands and results of operations Some instructions use the combined 8 bit accumulators A B as a 16 bit double accumulator D with the most significant byte in A For More Information On This Product Go to www freescale com Core User Guide si2cpu Rf Scale Semiconductor Inc 7 6 5 4 3 2 1 0 Read Write Reset 0 0 0 0 0 0 0 0 Figure 3 2 Accumulator A 7 6 5 4 3 2 1 0 Read Write Reset 0 0 0 0 0 0 0 0 Figure 3 3 Accumulator B Most operations can use accumulator A or B interchangeably However there are a few exceptions Add subtract and compare instructions involving both A and B AB
154. registers were highlighted as being reserved BDM registers previously in this section of the guide The BDM instruction BDMIST register is written by the BDM hardware as a result of a BDM command sent to the system via the BKGD pin The individual bits decode into categories of BDM instruction The two descriptions of the BDMIST below show the instruction decode when categorized as hardware or firmware instructions All of the BDM registers are readable and writable in special peripheral mode on the parallel bus until the BDMACT bit in the BDMSTS register is cleared at which time the BDM resources are no longer accessible via the peripheral bus and require a reset to be restored A full summary of the registers associated with the BDM is shown in Figure 14 10 below Address Name Bit 7 6 5 4 3 2 1 Bit 0 FFOO BDMIST iss H F DATA RW BKGND WB BDU 0 FF01 BDMSTS hse ENBDM BDMACT ENTAG 0 FF02 BDMSHTH 2 s15 S8 write FF03 BDMSHTL 2 s7 SO write FF04 BDMADDH 924 A15 A8 write FFOS5 BDMADDL 4 a7 AO write FFO6 BDMCCR hie CCR7 CCRO sero7 BDMINR 920 REGIS REG14 REG13 REG12 REGTI 0 0 0 write Unimplemented X Indeterminate Figure 14 10 BDM Register Map For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc 14 8 2 BDM Instruction Register Hardware Address FFOO Bit 7 6 5 4
155. s s s asana aeaaaee 225 12 4 6 Detecting Access Type from External Signals snaa ansaa aana 226 12 4 7 Stretched Bus Cycles nnana anaana aaa 227 12 4 8 Modes of Operation y 00 utes a e beet ew 227 1249 Internal Visibilty srs 5 A AA Se ead 2988 231 12 4 10 Secure Mode ii A a bene e es 232 12 5 Low Power ODIOS puta ata 232 1225 1 RUN MOUS tai a o a oa 232 125 2 WatMode ter ania ata rte 232 ARS LOIS E A IS A ARAS a ae a a 232 12 6 Motorola Internal IntOrmalon 2 ceder ria ea 232 12 6 1 Peripheral Mode Operation oocccccccnnoconnrn na 232 126 2 Special est GlOCK as a dE a 233 Section 13 Breakpoint BKP Sel COVGNIOW 2 5 a das tata Abs eRe Reet taeda eek eee es 235 BAT ESAS a EN A LR BO E ere ya anne rere ote 235 Ie Block Diagram cence bs aatiee vee wen Gate ee daetie dees edema eect 236 13 2 Interface Signal Ss sete at Tae ee call e be Be ae da O a Re oh bt Ue ek a 238 13 3 gt RS AN aie et ere halle Ss 238 13 3 1 Breakpoint Control Register O BKPCTO 000 ccc eee 238 13 3 2 Breakpoint Control Register 1 BKPCT1 0 2 2c e eee eee 239 13 3 3 Breakpoint First Address Expansion Register BKPOX 00 242 For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc 13 3 4 Breakpoint First Address High Byte Register BKPOH 243 13 3 5 Breakpoint First Address Low B
156. security is off and the user can change the state of the secure bits in the on chip Flash EEPROM Note that if the user does not change the state of the bits to unsecured mode the system will be secured again when it is next taken out of reset 14 3 2 BDM CCR Holding Register Read All modes Write All modes Address FF06 Bit 7 6 5 4 3 2 1 Bit 0 Read CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR CCRO Write Reset 0 0 0 0 0 0 0 0 Figure 14 4 BDM CCR Holding Register BDMCCR NOTE When BDM is made active the CPU stores the value of the CCR register in the BDMCCR register However out of special single chip reset the BDMCCR is set to D8 and not D0 which is the reset value of the CCR register When entering background debug mode the BDM CCR holding register is used to save the contents of the condition code register of the user s program It is also used for temporary storage in the standard BDM firmware mode The BDM CCR holding register can be written to modify the CCR value For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 14 3 3 BDM Internal Register Position Register Address FFO7 Bit 7 6 5 4 3 2 1 Bit 0 Read REG15 REG14 REG13 REG12 REG11 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 14 5 BDM Internal Register Position BDMINR Read All modes Write Never REG15 RE
157. set changes offset each other to a certain extent Programming style also affects the rate at which instructions appear As a test the BUFFALO monitor an 8K byte M68HC11 assembly code program was reassembled for the HCS12 The resulting object code is six bytes smaller than the M68HC11 code It is fair to conclude that M68HC11 code can be reassembled with very little change in size Table C 2 Instructions with Smaller Object Code Instruction Comments Page 2 opcodes in M68HC11 but page 1 in HCS12 For values of n less than 16 the majority of cases Were on page 2 now are on page 1 Applies to BSET BCLR BRSET BRCLR NEG COM LSR ROR ASR ASL ROL DEC INC TST JMP CLR SUB CMP SBC SUBD ADDD AND BIT LDA STA EOR ADC ORA ADD JSR LDS and STS If X is the index reference and the offset is greater than 15 much less frequent than offsets of 0 1 and 2 the HCS12 instruction assembles to one byte more of object code than the equivalent M68HC11 instruction INST n Y Were on page 2 now are on page 1 Were on page 2 now are on page 1 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Table C 2 Instructions with Smaller Object Code Instruction Comments CPY n Y LDY n Y For values of n less than 16 the majority of cases Were on page 3 now are on page 1 STY n Y CPD Was on page 2 3 or 4 now on page 1 In the c
158. share the FFF8 FFF9 interrupt vector The RTI instruction is used to terminate all exception handlers including interrupt service routines RTI first restores the CCR B A X Y and the return address from the stack If no other interrupt is pending normal execution resumes with the instruction following the last instruction that executed prior to interrupt A summary of the interrupt instructions is given in Table 4 24 Table 4 24 Interrupt Instructions Mnemonic Function Operation Msp CCR SP 0001 SP Msp Mgp 4 B A SP 0002 SP Return from interrupt Mgp Mgp 1 Xy XL SP 0004 SP Mgp Mgp 1 gt PCy PC SP 0002 SP Msp Mgp 4 Yu YL SP 0004 SP 0002 gt SP RTNy RTN gt Mgp Mgp 4 1 0002 SP Yy YL Mgp Mgp 4 1 Software interrupt 0002 SP X XL Mgp Mgp y 0002 SP B A gt Mgp Mgp 1 0001 SP CCR Msp 1 gt For More Information On This Product Go to www freescale com Core User Guide siocpurmraRscale Semiconductor Inc 4 3 20 Index Manipulation Instructions Index manipulation instructions perform 8 bit and 16 bit operations on CPU registers or memory A summary of the index manipulation instructions is given in Table 4 25 Table 4 25 Index Manipulation Instructions Mnemonic Function Operation ABX Add B to X
159. slow memory Stack 16 bit data An s cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the SP is pointing to external memory There can be additional stretching if the address space is assigned to a chip select circuit programmed for slow memory An s cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access The internal RAM is designed to allow single cycle misaligned word access 8 bit data write A w cycle is stretched only when controlled by a chip select circuit programmed for slow memory 16 bit data write A w cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the corresponding data is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory A w cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access Unstack 8 bit data A w cycle is stretched only when controlled by a chip select circuit programmed for slow memory For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 Table 5 7 Access Detail Notation Continued Unstack 16 bit data A U cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data
160. stacks PPAGE value GACE Extenged indexed With RTC e allows easy access to gt 64K byte space CPS e reli d Compare stack pointer DBNE Relative Decrement and branch if equal to zero looping primitive DBEQ Relative Decrement and branch if not equal to zero looping primitive EDIV Inherent Extended divide Y D X Y Q and D R unsigned EDIVS Inherent Extended divide Y D X Y Q and D R signed EMACS Special Multiply and accumulate 16 x 16 32 signed EMAXD Indexed Maximum of two unsigned 16 bit values EMAXM Indexed Maximum of two unsigned 16 bit values EMIND Indexed Minimum of two unsigned 16 bit values EMINM Indexed Minimum of two unsigned 16 bit values EMUL Special Extended multiply 16 x 16 32 M idx D Y D EMULS Special Extended multiply 16 x 16 32 signed M idx D Y D ETBL Special Extended table lookup and interpolate 16 bit entries EXG Inherent Exchange register contents IBEQ Relative Increment and branch if equal to zero looping primitive For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 Table C 4 New HCS12 Instructions Mnemonic Addressing Modes Brief Functional Description IBNE Relative Increment and branch if not equal to zero looping primitive IDIVS Inherent Signed integer divide D X X Q and D R signed LBCC Relative Long branch if carry clear same as LBH
161. suo9 qg suooqg Jep 1sod SUOD GG Od d MG Dd e Od ElL dS ds e dS el NE A E MEL Xe xe dd ag aa do ag a6 ag az as av ae a JosHo y yesyo y ysuooqg suooqg oep jsod suo9 qg jsuo9qg deap jsod suo9 qg jsu09 qg Jap 1sod SUOD GG dV AV Dd p 9dZ dS v dS dS ZL Av At MEL Xv Xt 94 23 od 99 od 06 98 OL os Or 9 ol JpuqgL Jpurqg ysuooqg ysuodqg sap jsod suo9 qg jsuo09 qg Jap 1sod suO09 qG ysuoo qg dap 3sod JSUOD GG Od u ul Od g Od bh ds ds dS LL A G AS MEL X g X g gd ga ga go ga g6 g8 az gs av ge a suo9 q9 jsuo9 q9 jsuo9 qg jsuo9qg Jap 1sod jsuo9 qg suo qg Jap 1sod suo9 qg jsuodqg Jap 1sod ySUOD GG Od u AU Od 9 9d 0 dS 9 ds 9 ds 0l K 9 M9 MOL x 9 x o Va vg vd vo va V6 v8 WZ VS YY Ve Vi ysuoo q6 jsuo9q6 ysuodqg jsuo9qg 9dap jsod oap aid ysuodqg suooqg sap jsod oap aid jsuo9 qg j suo9qg lt sap jsod dap aid 1su09 qg 1su09 qG Od u A U Od Z 9d 6 dS Z ds Z ds ds 6 NZ AL Mi M6 XL XZ X L x6 64 63 6d 69 6g 6Y 66 68 64 69 6S 6t 6 63 6h 60 ysuoo q6 jsuo9q6 jsuoo qg suooqg Jap 3sod oap aid suo09qg suooqg Jap 1sod oap aid ysuodqg suo9qg Jap sod oap aid 1su09 qg 1suo9 qG Od u AU Od 8 9d 8 dS 8 ds 8 ds 8 ds 8 K 8 A 8 M8 M8 X8 x 8 x8 x s 84 83 8d 89 8g 8v 86 88 84 89 8g 8p 8 83 8 80 papu q pu q ysuod AG SUO9 AG 9u1 Isod oul aid 1su09 qg 1Su09 qG 9u1 3s0d oul aid su09 qg SUO0
162. the FFFF separator at the end of the list For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc R EVW Fuzzy Logic Rule Evaluation Weighted R EVW continued CCR Effects Code and CPU Cycles Y points to the current weighting factor REVW updates Y so that execution can resume after an interrupt After execution Y points to the last weighting factor used Y does not change in unweighted evaluation A holds intermediate results During antecedent processing a MIN function compares each fuzzy input to the value stored in A and writes the smaller value to A After evaluation of all antecedents A contains the smallest input value In unweighted evaluation this is the truth value for consequent processing In weighted evaluation it is multiplied by the quantity rule weight 1 and the upper eight bits of the result replace the value in A REVW reinitializes A with FF when it finds an FFFE separator After execution A holds the truth value for the last rule The V bit signals whether antecedents 0 or consequents 1 are being processed V must be initialized to 0 for processing to begin with the antecedents of the first rule The value of V changes as FFFE separators are found After execution V should equal 1 because the last element before the FF end marker should be a rule consequent If V is equal to 0 at the end of execution the rule list is incorr
163. the size of an integer data type The 16 bit C value would need to be sign extended into the upper 16 bits of the 32 bit EDIVS numerator before the divide operation Operand size is also a potential problem in the extended multiply operations but the difficulty can be minimized by putting the results in CPU registers Having higher precision math instructions is not necessarily a requirement for supporting high level language because these functions can be performed as library functions However if an application requires these functions the code is much more efficient if the CPU can use native instructions instead of relatively large slow routines 4 4 5 Conditional If Constructs In the HCS12 instruction set most arithmetic and data manipulation instructions automatically update the condition code register unlike other architectures that only change condition codes during a few specific compare instructions The HCS12 includes branch instructions that perform conditional branching based on the state of the indicators in the condition code register Short branches use a single byte relative offset that allows branching to a destination within about 128 locations from the branch Long branches use a 16 bit relative offset that allows conditional branching to any location in the 64K byte map For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 4 4 6 Case and Switch Statements
164. through the loop Between cycle 5 0 and 6 x the V bit determines which of two paths to take If V is zero antecedents are being processed and the CPU progresses to cycle 6 0 If V is one consequents are being processed and the CPU goes to cycle 6 1 During cycle 6 0 the min operation compares the current value in the A accumulator to the fuzzy input that was read in the previous cycle 4 0 and puts the lower value in the A accumulator If Ry is FE this is the transition between rule antecedents and rule consequents and the min operation is skipped although the cycle is still used Cycle 6 0 6 1 is an x cycle because it could be a byte write or a free cycle If an interrupt arrives while the REV instruction is executing REV can break between cycles 4 0 and 5 0 in an orderly fashion so that the rule evaluation operation can resume after the interrupt service Cycles 5 2 and 6 2 adjust the PC and X index register so the REV operation can recover after the interrupt In cycle 5 2 PC is decremented so that it points to the currently running REV instruction After the interrupt rule evaluation resumes but the stacked values for the index registers accumulator A and CCR cause the operation to pick up where it left off In cycle 6 2 the X index register is decremented by one because the last rule byte needs to be refetched when the REV instruction resumes After cycle 6 2 the REV instruction is finished and execution continues with the normal in
165. to www freescale com Core User Guide siocpuimtaRscale Semiconductor Inc Source Form ASR opr16a ASR oprx0_xysppc ASR oprx9 xysppc ASR oprx16 xysppc ASR D xysppc ASR oprx16 xysppc ASRA ASRB BCC rel8Same as BHS Operation Arithmetic shift right M b7 bo Arithmetic shift right A Arithmetic shift right B Branch if C clear if C 0 then PC 2 rel gt PC Address Mode Machine Coding Hex 77 hh il 67 xb 67 xb ff 67 xbee ff 67 xb 67 xbee ff 47 53 24 rr Access Detail rPwO rPw rPwO frPwP fIfrPw fIPrPw PP branch no branch SXHINZVC BCLR opr8a msk8 BCLR opr16a msk8 BCLR oprx0_xysppc msk8 BCLR oprx9 xysppc msk8 BCLR oprx16 xysppc msk8 BCS rel8Same as BLO Clear bit s in M M emask byte M Branch if C set if C 1 then PC 2 rel gt PC 4D dd mm 1D hh 11mm 0D xb mm OD xb ff mm OD xb ee ff mm PP branch no branch BEQ rel8 Branch if equal if Z 1 then PC 2 rel gt PC Branch if 2 0 signed if NOV 0 then PC 2 rel gt PC Enter background debug mode Branch if gt 0 signed if Z NOV 0 then PC 2 rel gt PC PP branch no branch PP branch P no branch PP branch no branch BHS re 8Same as BCC BITA opr8i BITA opr8a BITA opr1
166. to the Core that the system memory is in a secured state and that the Core should operate in secured mode 15 3 Registers There are no registers in the Core associated with the secured mode of operation Typically a non volatile memory block in the system will contain a register for programming the state of system security Please refer to the chip level and or memory block documentation for implementation details 15 4 Operation When the system is configured for secured mode of operation it will normally operate in either normal single chip mode or in an expanded mode executing from external memory The conditions imposed by secured mode for each of these operating modes is discussed in the subsections that follow as well as a description of the method to unsecure the system 15 4 1 Normal Single Chip Mode Normal single chip mode will be the most common operation of a system configured for secured mode The system functionality will appear just as an unsecured system with the exception imposed that the BDM operation will not be allowed and will be blocked This will prevent any access to the internal non volatile memory block contents 15 4 2 Expanded Mode To operate in secured mode and execute from external memory space the system should be correctly configured for secured mode and then reset into expanded mode The internal on chip Flash EEPROM and EEPROM blocks if applicable will be disabled and unavailable All BDM operation w
167. used during the fuzzification process During fuzzification current system input values are compared to stored input membership functions to determine the degree to which each label of each system input is true This is accomplished by finding the y value for the current input on a trapezoidal membership function for each label of each system input The MEM instruction performs this calculation for one label of one system input To perform the complete fuzzification task for a system several MEM instructions must be executed usually in a program loop structure For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc 4 3 14 2 Fuzzy Logic Rule Evaluation Instructions The REV and REVW instructions perform MIN MAX rule evaluations that are central elements of a fuzzy logic inference program Fuzzy input values are processed using a list of rules from the knowledge base to produce a list of fuzzy outputs The REV instruction treats all rules as equally important The REVW instruction allows each rule to have a separate weighting factor REV and REVW also differ in the way rules are encoded into the knowledge base Because they require a number of cycles to execute rule evaluation instructions can be interrupted Once the interrupt has been serviced instruction execution resumes at the point the interrupt occurred 4 3 14 3 Fuzzy Logic Averaging Instruction The WAV instruction calc
168. values from RAM to produce a list of fuzzy outputs in RAM These fuzzy outputs can be thought of as raw suggestions for what the system output should be in response to the current input conditions Before the results can be applied the fuzzy outputs must be further processed or defuzzified to produce a single output value that represents the combined effect of all of the fuzzy outputs There are two variations of the rule evaluation instruction The REV instruction provides for unweighted rules that are considered to be equally important The REVW instruction is similar but allows each rule to have a weighting factor which is stored in a separate parallel data structure in the knowledge base REV and REVW also differ in the way rules are encoded into the knowledge base An understanding of the structure and syntax of rules is needed to understand how a microcontroller performs the rule evaluation task The following is an example of a typical rule If temperature is warm and pressure is high then heat is should be off For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 At first glance it seems that encoding this rule in a compact form understandable to the microcontroller would be difficult but it is actually simple to reduce the rule to a small list of memory pointers The left portion of the rule is a statement of input conditions and the right portion of the rule is a s
169. was read in cycle 2 0 is available to the CPU Cycle 4 0 is the first cycle of the main three cycle rule evaluation loop Depending on whether rule antecedents or consequents are being processed the loop consists of cycles 4 0 5 0 and 6 0 or 4 0 5 0 and 6 1 This loop is executed once for every byte in the rule list including the FE separators and the FF end of rules marker At each cycle 4 0 a fuzzy input or fuzzy output is read except during the loop passes associated with the FE and FF marker bytes in which no bus access takes place during cycle 4 0 The read access uses the Y index register as the base address and the previously read rule byte Ry as an unsigned offset from Y The fuzzy input or output value read here is used during the next cycle 6 0 or 6 1 Besides being the offset from Y for this read the previously read Ry can be a separator character FE If Ry is FE and the V bit was one this indicates a switch from processing consequents of one rule to processing antecedents of the next rule At this transition the A accumulator is initialized to FF to prepare for the min operation to find the smallest fuzzy input Also if Ry is FE the V bit toggles to indicate the change from antecedents to consequents or consequents to antecedents During cycle 5 0 a new rule byte is read unless this is the last loop pass and Ry is FF marking the end of the rule list This new rule byte is not used until cycle 4 0 of the next pass
170. whether clk24 runs during CPU wait mode 0 peri clk24 runs during wait 1 clk24 ceases during wait System level wait signal controls whether system clocks run during CPU persyswaltta wait mode 0 all clocks run during wait 1 no clocks run during wait For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 8 3 Detailed Clock and Reset Signal Descriptions General descriptions of the Core clock and reset interface signals are given in the subsections below Also included are the stop and wait mode signals due to the necessary interaction with the clock and reset requirements For detailed descriptions of these signals including timing information please consult the HCS12 V1 5 Core Integration Guide 8 3 1 Clock and Reset Signals These descriptions apply to system level clock and reset signals needed by the Core 8 3 1 1 System Reset signal peri_reset_ta4 This single bit asynchronous input to the Core indicates the system reset condition 8 3 1 2 System level reset input data reset_pin_ind This active low single bit input is used within the Core as a load enable for the MODE pin logic on Port E of the system 8 3 1 3 System level clock for the Core peri_clk2 This clock input is one of the main clocks for the Core 8 3 1 4 System level clock for the Core peri_clk4 This clock input is one of the main clocks for the Core 8 3 1 5 System level clo
171. 0 This 8 bit wide output from the Core provides the Port A data output to the system port pad logic for Port A 7 2 2 3 Port A output buffer enable from Core core_paobe 7 0 This 8 bit wide output from the Core provides the bit by bit output buffer enable signal to the system port pad logic for Port A 7 2 2 4 Port A input buffer enable from Core core_paibe_t2 This single bit output from the Core provides the input buffer enable signal to the system port pad logic for Port A 7 2 2 5 Port A pullup enable from Core core _papue_t2 This single bit output from the Core indicates that the pullup devices within the system port pad logic for Port A should be enabled for all Port A pins 7 2 2 6 Port A drive strength enable from Core core_padse_t2 This single bit output from the Core indicates whether all Port A pins will operate with full or reduced drive strength 7 2 2 7 Port B Input Data to Core core_pbind 7 0 This 8 bit wide input to the Core provides the Core with the input data from the system port pad logic for Port B For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 7 2 2 8 Port B Output Data from Core core_pbdo 7 0 This 8 bit wide output from the Core provides the Port B data output to the system port pad logic for Port B 7 2 2 9 Port B output buffer enable from Core core_pbobe 7 0 This 8 bit wide output from the Core provides t
172. 0 Disable Flash protection by writing the FPROT register Write FFFE to address FFOE Write Program command 20 to FCMD register Clear CBIEF bit 7 it FSTAT register g Wait until Flash CCIF flag is set to 1 again monogs After this Flash programming sequence is complete the microcontroller can be reset into any mode the Flash has been unsecured In normal modes either SINGLE CHIP or EXPANDED the microcontroller may only be unsecured by using the backdoor key access feature This requires knowledge of the contents of the backdoor keys which must be written to the Flash memory space at the appropriate addresses in the correct order In addition in SINGLE CHIP mode the user code stored in the Flash must have a method of receiving the backdoor key from an external stimulus This external stimulus would typically be through one of the on chip serial ports After the backdoor sequence has been correctly matched the microcontroller will be For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 unsecured and all Flash commands will be enabled and the Flash security byte can be programmed to the unsecure state if desired Please note that if the system goes through a reset condition prior to successful configuration of unsecured mode the system will reset back into secured mode operation 15 5 Motorola Internal Information This subsection details information ab
173. 0 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 81 2666 8080 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 800 441 2447 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Version 1 2 17 August 2000 Core User Guide End Sheet RoHS compliant and or Pb free versions of Freescale products have the functionality and electrical characteristics of their non RoHS compliant and or non Pb free counterparts For further information see http www freescale com or contact your Freescale sales representative For information on Freescale s Environmental Products program go to http www freescale com epp Information in this document is provided solely to enable system and software implementers to use Fr
174. 0001 SP INX Increment X X 0001 X INY Increment Y Y 0001 Y For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 4 3 7 Compare and Test Instructions Compare and test instructions perform subtraction on a pair of CPU registers on a CPU register and memory or on a CPU register and an immediate value The result is not stored but the operation can affect condition codes in the CCR These instructions are used to establish conditions for branch instructions However most instructions update condition codes automatically so 1t is often unnecessary to include separate compare or test instructions A summary of the compare and test instructions is given in Table 4 9 Table 4 9 Compare and Test Instructions Mnemonic Function Operation CBA Compare A to B A B CMPA Compare A to memory A M Compare A to immediate value A imm CMPB Compare B to memory B M Compare B to immediate value B imm CPD Compare D to memory A B M M 1 Compare D to immediate value A B imm CPS Compare SP to memory SP M M 1 Compare SP to immediate value SP imm CPX Compare X to memory X M M 1 Compare X to immediate value X imm CPY Compare Y to memory Y M M 1 Compare Y to immediate value Y imm TST Test memory for zero or minus M 00 TSTA Test A for ze
175. 001 SP B gt Msp Decrements SP by one and loads the value in B into the address to which SP points Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine Complementary pull instructions can be used to restore the saved CPU registers just before returning from the subroutine Address Machine Source Form Mode Code Hex CPU Cycles PSHB INH 37 Os For More Information On This Product Go to www freescale com PSHC Operation CCR Effects Code and CPU Cycles Freescale Semiconductor WOE Guide SP 0001 SP Decrements SP by one and loads the value in CCR into the address to which the SP points Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine Complementary pull instructions can be used to restore the saved Push CCR onto Stack CPU registers just before returning from the subroutine Address Machine Source Form Mode Code Hex CPU Cycles PSHC INH 39 Os For More Information On This Product Go to www freescale com 12CPU15UG V1 2 PSHC Core User Guide si2cpu A A8gscale Semiconductor Inc PSHD Push D onto Stack PSHD Operation CCR Effects Code and CPU Cycles SP 0002 SP A B gt Msp Mgp 1 Decrements SP by two and loads the value in A into the address to which SP points Loads the value in B into the
176. 02 0 Special Test MODC B A write anytime but not to 1102 1 Emulation Wide no write MODC write never MODB A write once but not Normal Single Chip to 110 Normal Expanded Narrow no write Special Peripheral no write Normal Expanded Wide no write NOTES 1 No writes to the MOD bits are allowed while operating in a SECURE mode For more details refer to the security specification document 2 If you are in a special single chip or special test mode and you write to this register changing to normal single chip mode then one allowed write to this register remains If you write to normal expanded or emulation mode then no writes remain Table 12 3 Mode Select and State of Mode Bits Aen Input Input amp bit amp bit amp bit Mode Description MODC MODB MODA 0 0 0 Special Single Chip BDM allowed and ACTIVE BDM is allowed in all other modes but a serial command is required to make BDM active 0 0 1 Emulation Expanded Narrow BDM allowed For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Table 12 3 Mode Select and State of Mode Bits Input Input Input BKGD gbit amp bit Mode Description bit MODB MODA ae ee et ee Special Test Expanded Wide BDM allowed Emulation Expanded Wide BDM allowed 1 0 0 Normal Single Chip BDM allowed 1 0 1 Normal Expanded Narrow BDM al
177. 06 Y 16 Y 26 Y 36 Y 46 Y 56 Y 66 Y 76 Y 86 Y 96 Y A6 Y B6 Y DBEQ DBEQ DBNE DBNE TBEQ TBEQ TBNE TBNE IBEQ IBEQ IBNE IBNE E E G E E E 07 SP 17 SP 27 SP 37 SP 47 SP 57 SP 67 SP 77 SP 87 SP 97 SP A7 SP B7 SP DBEQ DBEQ DBNE DBNE TBEQ TBEQ TBNE TBNE IBEQ IBEQ IBNE IBNE G E E E Hex postbyte bit 3 is don t care E A Counter Mnemonic Sign of 9 bit relative branch offset lower eight bits are an extension byte following postbyte For More Information On This Product Go to www freescale com jsuoo qg e JOS JO JO d L xeJUAS 9po9 99JNOS w x0 00 e aj qisod xaH Freescale Semiconductes IAG Guide s12CPU15UG v1 2 yoolpul q joampur q jsuo9 qg jsuo9qg Jap 3sod oap aid suo9qg jsuo9qg Jap 1sod oap aid suo qg suo9qg Jap 1sod oap aid 1su09 qg su09 qG og al al Od I Od S dS ds dS I ds Sl AL AL MI ASL XL X Xi X S dd 33 dd 30 dg dV 36 38 d4 9 ds dv de d dl 30 josHo q syo q jsuo9 qg jsuo9qg Jap 3sod oap aid 1suo09qg jsuosqg Jep 1sod oap aid jsuo9 qg suooqg Jap 1sod oap aid 1su09 qg su09 qG Od d MA 9d 2 Od p as z as z dS e dsp NE A Z AZ AYL EXO X Z xX z Xp Jd 33 gd 39 34 Jv 36 38 gz 39 gs ov 3 gz 31 30 josHo g josHpo g 1su09 qg jsuo9qg ap 1sod suo9 qg jsuo09qg Jap 1sod
178. 09 qG ds u xu Dd p Idz dS dSt dS vl dsiz E AFE AYL AZ X x e Xbl XZ cd cg ca Zo cd cv 26 28 cL Z9 cS cv ce oo ch zo ysuoo q6 suooqe jsuoo qg jsuodqg oul sod oul aid suooqg 1su09 qG oul jsod oul eid ysuooqg SUO9 q9 oul sod oul aid suo9 qg su09 qG ds u xu d S 9d dS dst 2 ds Gl ds AE MEE AS ME XZ X Z xX Gl XL kd 13 La LO Ld LW 16 18 YA 19 LS Lv Le ke LL LO ysuoo q6 suooqe jsuodgg jsuodqg oul sod oul aid ysuooqg su09 qG oul jsod oul eid ysuooqg SUO9 q9 oul sod oul aid jsuo9 qg suo9 qG ds u x u Od 91 940 dS b dS b dS 9l ds 0 AL AYE A94 MO X XFL xX 94 x 0 04 03 od 09 og ov 06 08 OL 09 os ov 0 oz Ol 00 Buipo9u3 qx a1 q1sog Bulsseippy pexepu 8 p For More Information On This Product O MOTOROLA Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Section 5 Instruction Execution The CPU uses a three stage instruction queue to facilitate instruction fetching and increase execution speed This section provides a general description of the instruction queue during normal program execution and during changes in execution flow Operation of the queue is automatic and generally transparent to the user 5 1 Normal Instruction Execution Queue logic prefetches program information
179. 1 Peripheral Writes The Core supports both 8 bit and 16 bit writes of peripheral registers The timing relationship for a basic 8 bit write of a peripheral register is shown in Figure 7 8 and that of a basic 16 bit write in Figure 7 9 An example of the I P Bus read data bus timing is provided in the figures for further illustration purposes For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc peri_clk24 PIA TS TATU Teh UV AA A V V AV EN core_ab 12 X_addr1 addr3 A core_wdb_t4 datai data3 ipb_rdb K data1 X data2 JC data3 core_perisel_t2 IS ee core_rw_t2 wA A CA O A ia core_sz8_12 8_BIT seit T peri_clk34 e O po Pon ER Jo Figure 7 8 Basic 8 bit Peripheral Write Timing peri_clk24 PIA TS TA Tee V V VY VY V Ee core_ab_t2 X adari addr3 X core_wdb_t4 X data1 data3 ipb_rdb K data1 K data2 JC data3 core_perisel_t2 J core _rw_t2 CS A E AE O G core sz8t2 _16BIT 16BIrT peri_clk34 i Figure 7 9 Basic 16 bit Peripheral Write Timing 7 3 2 2 Memory Writes The timing relationship for a basic 8 bit write of a on chip memory register or array byte by the Core is shown in below in Figure 7 10 and that of a basic 16 bit write in Figure 7 11 As before the MEM_rdb_L12 signal represents any of the on chip
180. 101 X010 1101 X011 1101 X100 1101 X101 1101 X110 1101 X111 EXG Y A EXG Y B EXG Y CCR EXG Y TMP2 EXG Y D EXG Y X EXG Y Y EXG Y SP 1110 X000 1110 X001 1110 X010 1110 X011 1110 X100 1110 X101 1110 X110 1110 X111 EXG SP A 1111 X000 EXG SP B 1111 X001 EXG SP CCR 1111 X010 EXG SP TMP2 1111 X011 EXG SP D 1111 X100 EXG SP X 1111 X101 EXG SP Y 1111 X110 EXG SP SP 1111 X111 For More Information On This Product Go to www freescale com 12CPU15UG V1 2 EXG Exchange B gt A A gt B B gt B FF gt A B gt CCR FF CCR gt D DsTMP2 D amp D DeX DeY D amp SP XLA 00 A gt X X_ gt B FF B gt X X_ gt CCR FF CCR gt X XSTMP2 XeD XX Xey X amp SP YLA 00 A gt Y Y_ B FF B gt Y YL CCR FF CCR gt Y Y amp TMP2 YeD Y amp X YoY Y amp SP SP gt A 00 A gt SP SP gt B FF B gt SP SPL CCR FF CCR gt SP SPSTMP2 SPD SPeX SP amp Y SP amp SP Core User Guide siocpuimtaRscale Semiconductor Inc F D V Fractional Divide F D V Operation CCR Effects Code and CPU Cycles D X gt X remainder gt D Divides an unsigned 16 bit numerator in D by an unsigned 16 bit denominator in X Puts the unsigned 16 bit quotient in X and the unsigned 16 bit remainder in D If both the numerator and the denominator are assumed to have radix points in the same positions the radix point of the quotient is to the left of bit 15 The numerator must be less th
181. 12 2 1 1 Port A Input Data to Core core_paind 7 0 This 8 bit wide input to the Core provides the Core with the input data from the system port pad logic for Port A 12 2 1 2 Port A Output Data from Core core_pado 7 0 This 8 bit wide output from the Core provides the Port A data output to the system port pad logic for Port A For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc 12 2 1 3 Port A output buffer enable from Core core_paobe 7 0 This 8 bit wide output from the Core provides the bit by bit output buffer enable signal to the system port pad logic for Port A 12 2 1 4 Port A input buffer enable from Core core_paibe_t2 This single bit output from the Core provides the input buffer enable signal to the system port pad logic for Port A 12 2 1 5 Port A pullup enable from Core core_papue_t2 This single bit output from the Core indicates that the pullup devices within the system port pad logic for Port A should be enabled for all Port A pins 12 2 1 6 Port A drive strength enable from Core core_padse_t2 This single bit output from the Core indicates whether all Port A pins will operate with full or reduced drive strength 12 2 1 7 Port B Input Data to Core core_pbind 7 0 This 8 bit wide input to the Core provides the Core with the input data from the system port pad logic for Port B 12 2 1 8 Port B Output Data from Core core_pbdo 7 0
182. 12CPU15UG V1 2 Core User Guide s12cpu af Scale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuige s12cPU15UG V1 2 List of Tables Table 1 1 Addressing Mode Summary 0000 e eee eeee 28 Table 1 2 Instruction Set Summary 2000 0c 29 Table 1 3 Register and Memory Notation 2000000 43 Table 1 4 Source Form Notation seas weit eb cd ee awd wees 44 Table 1 5 Operation Notation 00 0c cece eee 45 Table 1 6 Address Mode Notation 000 cece eee eee 45 Table 1 7 Machine Code Notation 00 0 ce eee eee eee 46 Table 1 8 Access Detail Notati0NM ooooooooooo 47 Table 1 9 Condition Code State Notation o o o ooooo 49 Table 2 1 Symbols and Operators 20 cece eee ee 51 Table 3 1 Core Register Map Reference 000 eee 61 Table 4 1 Addressing Mode Summary 00000e scene 63 Table 4 2 Summary of Indexed Operations 00 68 Table 4 3 Load and Store Instructions 0 00000 ee eee eee 73 Table 4 4 Transfer and Exchange Instructions 74 Table 4 5 Move Instructions cidad ra 74 Table 4 6 Add and Subtract Instructions ooooooooo 75 Table 4 7 BCD Instructions sierra 76 Table 4 8 Decrement and Increment Instructions 76 Table 4 9 Compare and Test Instr
183. 18 prebyte which indicates that the opcode is on page 2 of the opcode map The CPU treats the prebyte as a special one byte instruction To maintain alignment in the two byte queue the first cycle of a long branch instruction is an optional cycle If the prebyte is not aligned the CPU does a program word access if the prebyte is aligned the first cycle is a free cycle Optional cycles align byte sized and misaligned instructions with aligned word length instructions Program information is always fetched as aligned 16 bit words When an instruction has an odd number of bytes and the first byte is not aligned with an even byte boundary the optional cycle makes an additional program word access that maintains queue order In all other cases the optional cycle is a free cycle In the branch not taken case the queue advances so that execution can continue with the next instruction The CPU does one program fetch and one optional fetch to refill the queue In the branch taken case the CPU calculates the effective address of the branch using the 16 bit relative offset contained in the second word of the instruction It loads the address into the program counter and then does three program word fetches at the new address to refill the queue 5 3 3 3 Bit Condition Branches A bit condition branch instruction reads a location in memory and branches if the bits in that location are in a certain state It can use direct extended or indexed addressing mod
184. 19 14 and ECS Signal Functionality If the EMK bit in the MODE register is set see 12 3 8 the PIX5 0 values will be output on XAB19 14 respectively Port K bits 5 0 when the system is addressing within the physical Program Page Window address space 8000 BFFF and is in an expanded mode When addressing anywhere else within the physical address space outside of the paging space the XAB19 14 signals will be assigned a constant value based upon the physical address space selected In addition the active low emulation chip select signal ECS will likewise function based upon the assigned memory allocation In the cases of 48K byte and 64K byte allocated physical Flash ROM space the operation of the ECS signal will additionally depend upon the state of the ROMHM bit see 11 3 4 in the MISC register Table 11 10 Table 11 11 Table 11 12 and Table 11 13 below summarize the functionality of these signals based upon the allocated memory configuration Again this signal information is only available externally when the EMK bit is set and the system is in an expanded mode Table 11 10 OK Byte Physical Flash ROM Allocated Address Space Page Window Access ROMHM ECS XAB19 14 0000 3FFF n a 3D 4000 7FFF n a 3E 8000 BFFF n a PIX5 0 C000 FFFF n a 3F Table 11 11 16K Byte Physical Flash ROM Allocated Address Space Page Window Access dt A XAB19 14 0000 3FFF n a 3D 4000 7F
185. 3 i nei bkad ind __y q scan mode Scan Control BDM ore_ secure i2 p BKGD ore bkod dout t4 MEBI egera Security Pin f Multiplexed External Bus Interface EAS Peripheral Interface lt 2 bkgd ihe t2 qo ore_bkgdpue t2 per rito s Bus Only Interface E Signals Sle Zla lo zlgl la x Sle Pla ls alellla o AE ls SES lla ER SO y 2 o EJES as la el8 Si8lale El8 8 Slafe l8 8 8laJe 2 Elsisisialele CIO Cc aya oyopojojo jo ojofojojojo E x lt E Ire ajajajaj aja oajajfajalaja ajajfajajajoa ajajfajajajaj x olololo olo elo lolo lolo olofo slo o o oo oleo oo ojo ojo ojo ojo ojojojo ojo lon Rom Kom nom ne ojo ojo ojojo ojo ojo ojo ojo ojojo jo ojo ojofojojo ojo ojo ojojo Port A 7 0 Port B 7 0 Port E 7 0 Port K 7 0 Interface Interface Interface Interface Figure 8 1 Core Interface Signals The Core interfaces with the system clock and reset generation block s in order to synchronize the actions of the HCS12 CPU with the rest of the system Through the interface signals the Core supports the use of a system Phase Locked Loop PLL Crystal Monitor COP Watchdog and Real Time Interrupt as well as clocking options during CPU wait and stop modes Each of these aspects are discussed in the subsections that follow 8 1 1 Basic Clock Relationship The basic system clock timing in shown in Figure 8 2 below The system clock generation block is required to provide the main Core clocks peri_clk24 peri_clk2
186. 3 2 1 Bit 0 Read 0 0 H F DATA R W BKGND W B BD U Write Reset 0 0 0 0 0 0 0 0 Figure 14 11 BDM Instruction Register BDMIST Read All modes Write All modes BDM hardware writes this register when a BDM command is received Hardware clears the register if 512 BDM clock cycles occur between falling edges from the host Firmware clears this register when exiting from BDM active mode H F Hardware firmware flag When the BDM is active standard BDM firmware checks for this bit to be set by the BDM hardware as part of a BDM instruction load 1 Hardware command 0 Firmware command DATA Data flag Shows that data accompanies the command 1 Data follows the command 0 No data R W Read write flag 1 Read 0 Write BKGND Enter active background mode 1 Hardware background command 0 Not a hardware background command W B Word byte transfer flag 1 Word transfer 0 Byte transfer BD U BDM map user map flag Indicates whether BDM access is to BDM registers and standard BDM firmware lookup table mapped to addresses FFOO to FFFF or the user resources in this range Used only by hardware read write commands 1 standard BDM firmware lookup table and registers in map 0 User resources in map For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 14 8 3 BDM Instruction Register Firmware Address FFOO Bit 7 6 5 4 3 2 1 Bit 0 R
187. 40 For More Information On This Product Go to www freescale com 12CPU15UG V1 2 Core User Guide s12cpu af Scale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Section 1 Introduction 1 1 Core Overview The HCS12 V1 5 Core is a 16 bit processing core using the 68HC12 instruction set architecture ISA This makes the Core instruction set compatible with currently available Motorola 68HC12 based designs and allows for Motorola 68HC11 source code to be directly accepted by assemblers used for the HCS12 Central Processing Unit CPU In addition the Core contains the Interrupt INT Module Mapping Control MMC Multiplexed External Bus Interface MEBI Breakpoint BKP and Background Debug Mode BDM sub blocks providing a tightly coupled structure to maximize execution efficiency for integrating into a System on a Chip SoC design These sub blocks handle all system interfacing with the Core including interrupt and reset processing register and memory mapping memory and peripheral interfacing external bus control and source code debug for code development A complete functional description of each sub block is included in later sections of this guide 1 2 Features The main features of the Core are e High speed 16 bit processing with the same programming model and instruction set as the Motorola 68HC12 CPU e Full 16 bit data path
188. 6 Address Mode Notation INH Inherent no operands in instruction stream Immediate operand immediate value in instruction stream Direct operand is lower byte of address from 0000 to 00FF Operand is a 16 bit address Two s complement relative offset for branch instructions Indexed no extension bytes includes 5 bit constant offset from X Y SP or PC Pre post increment decrement by 1 8 Accumulator A B or D offset IDX1 9 bit signed offset from X Y SP or PC 1 extension byte IDX2 16 bit signed offset from X Y SP or PC 2 extension bytes IDX2 Indexed indirect 16 bit offset from X Y SP or PC D IDX Indexed indirect accumulator D offset from X Y SP or PC For More Information On This Product Go to www freescale com Core User Guide s 2cpu ASR Scale Semiconductor Inc 1 8 5 Machine Code Notation In the Machine Code Hex column of the summary in Table 1 2 digits 0 9 and upper case letters A F represent hexadecimal values Pairs of lower case letters represent 8 bit values as shown in Table 1 7 Table 1 7 Machine Code Notation dd 8 bit direct address from 0000 to 00FF high byte is 00 ES High byte of a 16 bit constant offset for indexed addressing b Exchange transfer postbyte Low eight bits of a 9 bit signed constant offset in indexed addressing or low byte of a 16 bit constant offset in indexed addressing High byte of a 16 bit extended address 8 bit i
189. 6a BITA oprx0_xysppc BITA oprx9 xysppc BITA oprx16 xysppc BITA D xysppc BITA oprx16 xysppc Branch if higher unsigned if C Z 0 then PC 2 rel gt PC Branchifhigherorsame unsigned if C 0 then PC 2 rel PC Bit test A A e M or A eimm 854i 95 dd B5hh11 A5 xb A5xbff A5xbee ff A5 xb A5xbee ff PP branch no branch PP branch no branch pD rPf rPO rP rPO frPP fIfrPf fIPrPf BITB opr8i BITB opr8a BITB opr16a BITB oprx0_xysppc BITB oprx9 xysppc BITB oprx16 xysppc BITB D xysppc BITB oprx16 xysppc BLO rel8Same as BCS Bit test B B e M or B eimm Branchif lt 0 signed ifZ N V 1 then PC 2 rel gt PC Branch if lower unsigned if C 1 then PC 2 rel gt PC Codi D5 dd F5hh11 E5xb E5xb ff E5 xbee ff E5 xb E5 xbee ff P rPf TPO rPf rPO frPP fIfrPf fIPrPf PP branch no branch P branch no branch BLS rel8 Branch if lower or same unsigned if C Z 1 then PC 2 rel gt PC Branch if lt 0 signed if NOV 1 then PC 2 rel gt PC Branch if minus if N 1 then PC 2 rel gt PC PP branch no branch PP branch P no branch p branch no branch BRA relg8 Branch if not equal to 0 if Z 0 then PC 2 rel PC Branch if plus if N 0 then PC 2 rel gt PC Branch always For More Information On T
190. 7 The only way to exit peripheral mode is to change the mode pin configuration and pull reset It is not possible to enter exit peripheral mode by writing the MODx bits in the MODE register Table 12 7 Peripheral Mode Pin Configuration MODC BKGD MODB PE6 MODA PE5 1 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Peripheral mode is a special mode immediately out of reset It may be changed to a normal mode by writing the PNORME bit in the MTST1 register of the MMC sub block to 1 In peripheral mode the direction of the address and data buses is reversed compared to other modes of operation Address R W and SZ8 all come from the external test system and drive the bus interface pins of Ports A B and E of the system The data bus is configured to pass data directly through Ports A and B to the internal data bus Accesses are all initiated by the external test system The burden of deciding which port to access for 8 bit data or swapped data is the responsibility of the external test system The MEBI does not modify peripheral mode accesses in any way Misaligned 16 bit accesses are not allowed to blocks that require two cycles to complete such as system peripherals Misaligned 16 bit accesses are allowed to blocks that can handle fast transfers such as a RAM memory block 12 6 2 Special Test Clock When the peri_test_clk_enable signal at th
191. 8 01 340 39 0l ajot Ari9te gelem az v alz 30 z Hz Hie His Hlle Hie He He He Hille Hie Hz He air use als x3 al dVYL dvel dVel dvel dvel dVHL dvel dVel dvel dvel oval dvel Tal 1187 ANIN gAONW or dalot ajo aallot aojo aaor aviol aslo agol aziol agiol dasol avg dele aziz alls ao Z HIZ Hie Hie Hie Hilfe Hilfe Hie Hz Hi Hie Hz Hie asv Hise alo xa dVHL dvel dVel dvel dvel dVHL dvel dVel dVHL dvel dvel dvel AVM 3987 WXVW IAOW Ol a0 alot alot OO 0l ogor vlot 06 01 glor OZ Ol glor OS Ol OrluUL elem zl OL9 00 Z Hz Hz Hz Hlle Hie Hez Hz Hez Hz Hie Hille Hiz asv His al s xII dVedl dvel dVel dvel dvel dVHL dvel dVel dvel dvel oval dvel MA38 IWaT ONINI SAOWN ot galor gajo galor gojol ggol viol gelor geol ego geo gejot grueugge ley gz z S v ally g0 Z Hie HZ HZ HZ Hz Hz Hz Hz He He He Hz asv alse ally ara dvedl dvel dVel dvel dvel dVHL dvel dVel dvel dvel dvel dvel Ad8 Tada OXVIN3 SAOW Ol valot vajo valot vVOlOl valor vylo velot vyslo VWZ Ol vojo vS Ol vue velem VZ Z S Y VIS VO z Hz Hie Hz Hilfe Hez He Hz He Hz He Hz H Hr wee alls ang dVHL dvel dVel dvel dVel dVHL dvel dVel dvel dvel dVHL dvel dVel SA91 VNIN SAOW Ol 64 Ol 63 0 6gqgol 60 0 6glol 6viol 66 0 68 01 6 0 69 01 6slol 6riOl 6ele p 6z Z S p B S 60 Z He HZ HZ Hie Hz Hz Hz Hz Hz Hiz Hil Hz Ht alse aly amni dVedl dvel dVel dvel dvel dVHL dvel
192. 8 01 xb hh 1 OPRPW MOVW oprx0_xysppc opr16a IDX EXT 18 05 xb hh 1 ORPWP MOVW oprx0_xysppc oprx0_xysppc IDX IDX 18 02 xb xb ORPWO NOTES 1 The first operand in the source code statement specifies the source for the move For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 M U L Multiply Unsigned M U L Operation CCR Effects Code and CPU Cycles A x B gt A B Multiplies the 8 bit unsigned value in A by the 8 bit unsigned value in B and places the 16 bit unsigned result in D The carry flag allows rounding the high byte of the result through the sequence MUL ADCA 0 C R7 set if bit 7 of the result is set cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles MUL INH 12 O For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc NEG Negate M NEG Operation 0 M M 1 M Replaces the value in M with its two s complement A value of 80 does not change CCR Effects S XH I N ZV C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V R7 e R6 e R5 e R4 e R3 e R2 e R1 e RO set if there is a two s complement overflow from the implied subtraction from 0 cleared otherwise two s complement overflow occurs if and only if M 80 C R7 R6 R5 R4 R3 R2 R1 RO set i
193. 9 qG oul sod oul aid ysuodqg su09 qg ds a al Od 6 Od Z dS 8 dS 8 ds 6 ds Z K 8 A 8 M6 ML x 8 x 8 x6 XL d 4 a ZO g A A 46 Z8 ZL 19 PAS Lv Ze Ze ZI 40 yesyo q yesyoq jsuo9 qg su09 q9 oul sod oul aid ysuodqg SUO9 qG Oul sod oul aid ysuodqg jsuo0d qG oul sod oul aid su09 qg SUO9 qG ds a xQ Od 0l 9d 9 dS Z dSt Z dS 0l ds 9 L AVL AOL M9 X X Z x Ol x9 94 93 9d 99 9g 9v 96 98 94 99 96 9v 9 93 94 90 josHo g yesyo g suo9 qg su09 q9 oul sod oul aid suo9 qg su09 qG oul jsod oul eid su09 qg SUO09 q9 oul sod oul aid jsuo9 qg suo09 qG ds d xg Dd Ll Od S dS 9 dst 9 dS L l ds g K 9 AF9 ALL MG x9 x 9 Xb x s Sd sg sa gO sg sv g6 98 GZ S9 SS Sv Ge Ge SL sO JosHo y yesyo y 1su09 qG SUO9 q9 oul sod oul aid 1suo9 qg ysuooqg oul jsod oul eid ysuooqgg SUO9 q9 oul sod oul aid suo9 qg 1su09 qu dSs v xv d z Ody dS S ds S dS tl ds v ASG MEG Mel Mv X Xt X Zl xv td va va vo va vv v6 v8 bl v9 YS LAA ve ve vl v0 JPU QQ Jpuqg ysuoo gg suo9 qu oul sod oul aid jsuooqg su09 qu oul sod oul aid jsuodqg suo9 qG oul sod oul eid jsuooqg ysuooqg ds u pu Od El Od dS v ds y ds l ase A V Atv AEL NE xy x y xXel XE d 3 q 9 eg ev 6 8 el 9 EG ev E Ez L 0 ysuoo qg suo9 q9 jsuo9 qg jsuos qu oul sod oul aid suooqg su09 qg oul jsod oul eid ysuoo qg su09 q9 oul sod oul aid suo9 qg su
194. A x S2 FF MEM Membership A contains current crisp input value evaluation X points to 4 byte data structure describing trapezoidal membership function as base intercept points and slopes P1 P2 S1 S2 Y points to fuzzy input RAM location Find smallest rule input MIN Store to rule outputs unless fuzzy output is larger MAX Rules are unweighted REV m FA Each rule input is 8 bit offset from base address in Y valuation Each rule output is 8 bit offset from base address in Y FE separates rule inputs from rule outputs FF terminates rule list REV can be interrupted Find smallest rule input MIN Multiply by rule weighting factor optional Weighted Store to rule outputs unless fuzzy output is larger MAX Each rule input is 16 bit address of a fuzzy input REVW eee Each rule output is 16 bit address of fuzzy output Address FFFE separates rule inputs from rule outputs FFFF terminates rule list evaluation i y Weights are 8 bit values in separate table REVW can be interrupted Calculate numerator sum of products and denominator sum of weights B Weighted y SF gt Y D WAV average ipl calculation Y FX i 1 Put results in correct CPU registers for EDIV immediately after WAV Return to wavr es Recover intermediate results from stack rather than initializing to zero instruction 4 3 14 Maximum and Minimum Instructions 4 3 14 1 Fuzzy Logic Membership Instruction The MEM instruction is
195. A SBA and CBA only operate in one direction so it is important to verify that the correct operand is in the correct accumulator The decimal adjust accumulator A DAA instruction is used after binary coded decimal BCD arithmetic operations There is no equivalent instruction to adjust accumulator B 3 1 2 Index Registers X and Y 16 bit index registers X and Y are used for indexed addressing In indexed addressing the contents of an index register are added to a 5 bit 9 bit or 16 bit constant or to the contents of an accumulator to form the effective address of the instruction operand Having two index registers is especially useful for moves and in cases where operands from two separate tables are used in a calculation Read Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3 4 Index Register X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 3 5 Index Register Y For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Read Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3 5 Index Register Y 3 1 3 Stack Pointer SP The stack stores system context during subroutine calls and interrupts and can also be used for temporary data storage It can be located anywhere in the standard 64K byte address space and can grow to any size up to the total amount of memory available in the system SP holds the 16 bit address of the last stack location used
196. A7 e M7 e R7 set if a two s complement overflow resulted from the operation cleared otherwise C A7 M7 M7 e R7 R7 e A7 set if the value in M is larger than the value in A cleared otherwise Machine Source Form Code Hex CPU Cycles SUBA opr8i SUBA opr8a SUBA opr16a SUBA oprx0_xysppc SUBA oprx9 xysppc SUBA oprx16 xysppc SUBA D xysppc SUBA oprx16 xysppc AO xb ee ff For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 SUBB Subtract from B SUBB Operation CCR Effects Code and CPU Cycles B M gt B or B mm gt B Subtracts either the value in M or an immediate value from the value in B Puts the result in B The C bit represents a borrow S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V B7 e M7 e R7 B7 M7 e R7 set if a two s complement overflow resulted from the operation cleared otherwise C B7 M7 M7 e R7 R7 e B7 set if the value in M is larger than the value in B cleared otherwise Machine Source Form Code Hex CPU Cycles SUBB opr8i CO ii SUBB opr8a DO dd SUBB opr16a FO hh 11 SUBB oprx0_xysppc E0 xb SUBB oprx9 xysppc EO xb ff SUBB oprx16 xysppc EQ xb ee ff SUBB D xysppc E0 xb SUBB oprx16 xysppc EO xb ee ff For More Information On This Product Go to www freescale com Core
197. AF xbee ff PO RP RPO RP RPO TRPE fIfRP fIPRP PO RP RPO RP RPO fRPP fIfRP fIPRP CPY opr16i CPY opr8a CPY opr16a CPY oprx0_xysppc CPY oprx9 xysppc CPY oprx16 xysppc CPY D xysppc CPY oprx16 xysppc Compare Y Y M M 1 or Y imm PO RP RPO RP RPO fRPP fIfRP fIPRP DAA Decimal adjust A for BCD DBEQ abdxysp rel9 Decrement and branch if equal to 0 counter 1 gt counter if counter 0 then branch branch no branch DBNE abdxysp rel9 Decrement andbranch if not equal to 0 counter 1 gt counter if counter 0 then branch PP branch PO no branch DEC opr16a Decrement M M 1 M EXT 73hh11 rPwO Talalay DEC oprx0_xysppc IDX 63 xb rPw DEC oprx9 xysppc IDX1 63 xb ff rPwO DEC oprx16 xysppc IDX2 63 xb ee ff frPwP DEC D xysppc D IDX 63 xb fIfrPw DEC oprx16 xysppc IDX2 63 xb ee ff fIPrPw DECA Decrement A A 1 gt A INH 43 O DECB Decrement B B 1 B INH 53 O DESSame as LEAS 1 SP Decrement SP SP 1 SP IDX 1B 9F Pf A O O O O O O E DEX Decrement X X 1 X INH 09 O 11H N G DEY Decrement Y Y 1 Y INH 03 O Tal_ _ EDIV Extended divide unsigned 32by16 INH 11 ffffffffffo J TATATATA to 16 bit Y D X Y re
198. AX oprx9 xysppc 1A xb ff LEAX oprx16 xysppc 1A xb ee ff For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 LEAY Load Effective Address into Y LEAY Operation Effective address gt Y Loads Y with an effective address specified by the program The effective address can be any indexed addressing mode operand address except an indirect address Indexed addressing mode operand addresses are formed by adding an optional constant supplied by the program or an accumulator value to the current value in X Y SP or PC When Y is the indexing register a predecrement or preincrement LEAY loads Y with the changed value A postdecrement or postincrement LEAY does not affect the value in Y CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex LEAY oprx0_xysppc 19 xb LEAY oprx9 xysppc 19 xb ff LEAY oprx16 xysppc 19 xb ee ff For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc LSL Operation CCR Effects Code and CPU Cycles Logical Shift Left M L S L same as ASL b7 b6 o5 4 b3 b2 bt bo je o0 M Shifts all bits of the M one place to the left Loads bit 0 with 0 Loads the C bit from the most significant bit of M S X H I N Z V C 4 4 4 4 N Set if MSB of result is set cleared
199. Alternate Write data bus EBLAlternate Read data bus CPU Address bus ere CPU Read Data bus CPU Write Data bus Se oa P CPU Contro gt BUS CONTROL mmc_secure a Port K Interface p memory space select s peripheral select gt Core select s Alternate Address bus BDM pe BDM Alternate Write data bus BDM ig __ _ _ Alternate Read data bus BDM Figure 11 1 Module Mapping Control Block Diagram 11 2 Interface Signals All interfacing with the MMC sub block is done within the Core For More Information On This Product Go to www freescale com 11 3 Registers Freescale Semiconductor WOE Guide 12CPU15UG V1 2 A summary of the registers associated with the MMC sub block is shown in Figure 11 2 below Detailed descriptions of the registers and bits are given in the subsections that follow Address 0010 0011 0012 0013 0014 0017 001C 001D 0030 0031 Name INITRM INITRG INITEE MISC Reserved Reserved MEMSIZO MEMSIZ1 PPAGE Reserved read write read write read write read write read write read write read write read write read write read write Bit 7 6 5 4 3 2 1 Bit 0 RAM15 RAM14 RAM13 RAM12 RAM11 5 Y RAMAL REG14 REG13 RE
200. B X gt X ABY Add B to Y B 1 Y CPS Compare SP to memory SP M M 1 CPX Compare X to memory X M M 1 CPY Compare Y to memory Y M M 1 LDS Load SP from memory M M 1 SP LDX Load X from memory M M 1 X LDY Load Y from memory M M 1 gt Y LEAS Load effective address into SP Effective address SP LEAX Load effective address into X Effective address X LEAY Load effective address into Y Effective address Y STS Store SP in memory SP MM 1 STX Store X in memory X gt MM 1 STY Store Y in memory Y gt M M 1 TFR Transfer registers A B CCR D X Y or SP gt A B CCR D X Y or SP TSX Transfer SP to X SP gt TSY Transfer SP to Y SP gt TXS Transfer X to SP X SP TYS Transfer Y to SP Y SP EXG Exchange registers A B CCR D X Y or SP amp A B CCR D X Y or SP XGDX Exchange D with X D e X XGDY Exchange D with Y D e Y For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPuU15UG v1 2 4 3 21 Stacking Instructions There are two types of stacking instructions e Stack pointer manipulation e Stack operation saving and retrieving CPU register contents A summary of the stacking instructions is given in Table 4 26 Table 4 26 Stacking Instructions Mnemonic Type Function Oper
201. B A B A ABX Add B to X B X X ABY Add B to Y B Y Y ADCA Add memory and carry to A A M C gt A Add immediate value and carry to A A imm C gt A ADCB Add memory and carry to B B M C gt B Add immediate value and carry to B B imm C gt B ADDA Add memory to A A M gt A Add immediate value to A A imm gt A ADDB Add memory to B B M gt B Add immediate value to B B imm B ADDD Add memory to D A B M M 1 A B Add immediate value to D A B imm gt A B SBA Subtract B from A A B gt A SBCA Subtract memory and carry from A A M C gt A Subtract immediate value and carry from A A imm C gt A SBCB Subtract memory and carry from B B M C B Subtract immediate value and carry from B B imm C gt B SUBA Subtract memory from A A M gt A Subtract immediate value from A A imm gt A SUBB Subtract memory from B B M gt B Subtract immediate value from B B imm gt B SUBD Subtract memory from D A B M M 1 gt A B Subtract immediate value from D A B imm gt A B For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc 4 3 5 Binary Coded Decimal Instructions To add binary coded decimal BCD operands use addition instructions that set the half carry bit H in the CCR Then adjust the result with the DAA instruction A summary of the BCD instructions is give
202. B AB AB AB AB AB with IVIS amp Periph DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 AB15 amp AB14 amp ABI3 amp ABi2 amp ABi1 amp ABIO amp AB94 AB8 amp Expanded Narrow DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Figure 12 3 Port A Data Register PORTA Read anytime when register is in the map Write anytime when register is in the map Port A bits 7 through 0 are associated with address lines A15 through A8 respectively and data lines D15 D7 through D8 DO respectively When this port is not used for external addresses such as in single chip mode these pins can be used as general purpose l O Data Direction Register A DDRA determines the primary direction of each pin DDRA also determines the source of data for a read of PORTA This register is not in the on chip memory map in expanded and peripheral modes CAUTION To ensure that you read the value present on the PORTA pins always wait at least one cycle after writing to the DDRA register before reading from the PORTA register For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 12 3 2 Data Direction Register A DDRA Address Base 2 BIT 7 6 5 4 3 2 1 BIT O Read Bit 7 6 5 4 3 2 1 Bit O Write Reset 0 0 0 0 0 0 0 0 Figure 12 4 Data Direction Register A DDRA Read anytime when register is in the map Write anytime when register is in the map Thi
203. B CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the CPU register value is less than the value in M After CBA or SBA the branch occurs if the value in B is less than the value in A Rel is a 16 bit two s complement offset for branching forward or backward in memory Branching range is 8000 to 7FFF 32768 to 32767 from the address following the last byte of object code in the instruction CCR Effects S XH N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex LBLT re 16 REL 18 2D qq rr OPPP branch OPO no branch Branch Complementary Branch amp ommen Mnemonic Mnemonic Opcode Test LBLT O LBLO LBCS LBHS LBCC Unsigned For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc dE B M Long Branch if Minus L B M Operation CCR Effects Code and CPU Cycles If N 1 then PC 0004 rel PC Tests the N bit and branches if N 1 Rel is a 16 bit two s complement offset for branching forward or backward in memory Branching range is 8000 to 7FFF 32768 to 32767 from the address following the last byte of object code in the instruction S X H I N Z V C Address Machine Source Form Mode Code Hex CPU Cycles LBMI rel16 REL 18 2B qq rr OPPP branch OPO no branch Branch Comple
204. BDM status BDMSTS register is described in 14 3 1 In addition it is readable and writable in special peripheral mode on the parallel bus BDMACT BDM active status BDMACT is set by the BDM and is cleared in the exit sequence of the standard BDM firmware BDMACT can be written to in special peripheral mode via the peripheral bus It cannot be written to via BDM hardware commands in any mode that is it cannot be written to if the H F bit in the BDMIST register 1s set Clearing BDMACT causes the standard BDM firmware lookup table and registers to be removed from the memory map and BDM to become inactive Setting BDMACT in special peripheral mode via the peripheral bus causes BDM to become active but does not put the standard BDM firmware lookup table and registers into the memory map therefore BDMACT should not be set in this manner but should instead be set by resetting the system For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 14 8 5 BDM Shift Register Address FF02 Bit 15 14 13 12 11 10 9 Bit 8 Read 15 S14 13 12 11 S10 S9 S8 Write Reset Figure 14 13 BDM Shift Register BDMSHTH Address FF03 Bit 7 6 5 4 3 2 1 Bit 0 Read S7 S6 5 S4 S3 S2 S1 So Write Reset Figure 14 14 BDM Shift Register BDMSHTL Read All modes Write All modes The 16 bit BDM shift register contains data being received or transmitted via the serial i
205. BOhh11 rPO SUBA oprx0_xysppc AO xb rPf SUBA oprx9 xysppc AO xb ff rPO SUBA oprx16 xysppc AO xbee ff frPP SUBA D xysppc AO xb flfrPf SUBA oprx16 xysppc AO xbee ff fIPrPf SUBB opr8i Subtract from B j P SUBB opr8a B M B rPf SUBB opr16a or B imm gt B rPO SUBB oprx0_xysppc rPf SUBB oprx9 xysppc rPO SUBB oprx16 xysppc frPP SUBB D xysppc flfrPf SUBB oprx16 xysppc fIPrPf SUBD opr16i Subtract from D PO SUBD opr8a A B M M 1 gt A B RP SUBD opr16a or A B imm A B RPO SUBD oprx0_xysppc RP SUBD oprx9 xysppc RPO SUBD oprx16 xysppc f RPP SUBD D xysppc fIFRP SUBD oprx16 xysppc fIPRP Software interrupt SP 2SP VSPSSPSsP RTNyY RTN gt Mgp Mgp 1 SP 2 gt SP Yu YL Msp Mgp41 SP 2 gt SP Xy X_ Mgp Mgp 1 SP 2 SP B A Mgp Mgp 4 SP 1 SP CCR Mgp 1 gt 1 SWI vector PC The CPU also uses VSPSSPSsP for hardware interrupts and unimplemented opcode traps TAB Transfer A to B A B INH 18 0E 00 A Ayo Access Detail SXHINZVC Assembled as TFRA CCR TBA Transfer B to A B gt A INH 00 18 0F TBEQ abdxysp rel9 Test and branch if equal to 0 041lbrr PPP branch If counter 0 then PC 2 rel gt PC PPO no branch TAP Transfer A to CCR A gt CCR INH B7 02 P ATUTATATATATATA
206. Branch if Not Equal to Zero D B N E Operation CCR Effects Code and CPU Cycles counter 1 counter If counter not 0 then PC 0003 rel PC Subtracts one from the counter register A B D X Y or SP Branches to a relative destination if the counter register does not reach zero Rel is a 9 bit two s complement offset for branching forward or backward in memory Branching range is 100 to OFF 256 to 255 from the address following the last byte of object code in the instruction S X H I N ZV C Address Machine Source Form Mode Code Hex CPU Cycles REL 04 lb rr PPP branch DBNE abdxysp rel9 9 bit PPO no branch Loop Primitive Postbyte 1b Coding Counter Postbyte Register 0010 X000 A B D xX Y DBNE SB rel9 SP DBNE A rel9 0011 X000 04 30 rr A DBNE B rel9 0011 X001 04 31 rr B DBNE D rel9 0011 X100 04 34 rr D da DBNE X rel9 0011 X101 04 35 rr x 9 DBNE Y rel9 0011 X110 G4 etr Y DBNE SP rel9 0011 X111 04 37 rr SP NOTES 1 Bits 7 6 5 select DBEQ or DBNE bit 4 is the offset sign bit bit 3 is not used bits 2 1 0 select the counter register For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc DEC Decrement M DEC Operation CCR Effects Code and CPU Cycles M 01 gt M Subtracts one from the value in M The N Z and V bits are set or cleared by the
207. C controls the address bus and data buses that interface the Core with the rest of the system This includes the multiplexing of the input data buses to the Core onto the main CPU read data bus and control of data flow from the CPU to the output address and data buses of the Core In addition the MMC handles all CPU read data bus swapping operations 11 4 2 Address Decoding As data flows on the Core address bus the MMC decodes the address information determines whether the internal Core register or firmware space the peripheral space or a memory register or array space is being addressed and generates the correct select signal This decoding operation also interprets the mode of operation of the system and the state of the mapping control registers in order to generate the proper select The MMC also generates two external chip select signals Emulation Chip Select ECS and External Chip Select XCS For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc 11 4 2 1 Select Priority and Mode Considerations Although internal resources such as control registers and on chip memory have default addresses each can be relocated by changing the default values in control registers Normally I O addresses control registers vector spaces expansion windows and on chip memory are mapped so that their address ranges do not overlap The MMC will make only one select signal active at any gi
208. CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the CPU register value is greater than the value in M After CBA or SBA the branch occurs if the value in B is greater than the value in A Rel is a 16 bit two s complement offset for branching forward or backward in memory Branching range is 8000 to 7FFF 32768 to 32767 from the address following the last byte of object code in the instruction S X H I N Z V C Address Machine Source Form Mode Code Hex CPU Cycles LBGT rel16 REL 18 2E qq rr OPPP branch OPO no branch Branch Complementary Branch Comment Mnemonic Opcode Test Mnemonic Opcode Test R gt M R lt M or or LBGT 18 2E B gt A LBLE 18 2F B lt A Signed Z N V 0 Z N V R gt M R lt M or or LBHI 18 22 B gt A LBLS 1823 B lt A Unsigned C Z 0 C Z For More Information On This Product Go to www freescale com Core User Guide siocpuimtaRscale Semiconductor Inc LBHI Long Branch if Higher LBHI Operation CCR Effects Code and CPU Cycles If C I Z 0 then PC 0004 rel PC LBHI can be used to branch after subtracting or comparing unsigned values After CMPA CMPB CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the CPU register value is greater than the value in M After CBA or SBA the branch occurs if the value in B is greater t
209. Core with the input data from the system port pad logic for Port K 12 2 1 21 Port K Output Data from Core core_pkdo 7 0 This 8 bit wide output from the Core provides the Port K data output to the system port pad logic for Port K For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc 12 2 1 22 Port K output buffer enable from Core core_pkobe 7 0 This 8 bit wide output from the Core provides the bit by bit output buffer enable signal to the system port pad logic for Port K 12 2 1 23 Port K input buffer enable from Core core_pkibe_t2 This single bit output from the Core provides the input buffer enable signal to the system port pad logic for Port K 12 2 1 24 Port K pullup enable from Core core_pkpue_t2 This single bit output from the Core indicates that the pullup devices within the system port pad logic for Port K should be enabled for all Port K pins 12 2 1 25 Port K drive strength enable from Core core_pkdse_t2 This single bit output from the Core indicates whether all Port K pins will operate with full or reduced drive strength For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 12 3 Registers A summary of the registers associated with the MEBI sub block is shown in Figure 12 2 below Detailed descriptions of the registers and bits are given in the subsections that follow
210. D Operation CCR Effects Code and CPU Cycles MIN D M M 1 D Subtracts an unsigned 16 bit value in M M 1 from an unsigned 16 bit value in D to determine which is larger Puts the smaller value in D If the values are equal the Z bit is set If the value in M M 1 is larger the C bit is set If the value in D is larger the C bit is cleared when the value in M M 1 replaces the value in D EMIND accesses memory with indexed addressing modes for flexibility in specifying operand addresses Autoincrement and autodecrement functions can facilitate finding the smallest value in a list of values S X H I N Z V C 4 4 4 a4 N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V D15 e M15 e R15 D15 M15 e R15 set if the operation produces a two s complement overflow cleared otherwise C D15 e M15 M15 R15 R15 e D15 set if M M 1 is larger than D cleared otherwise Condition code bits reflect internal subtraction R D M M 1 Address Machine Source Form Mode Code Hex CPU Cycles EMIND oprx0_xysppc IDX 18 1B xb ORPf EMIND oprx9 xysppc IDX1 18 1B xb ff ORPO EMIND oprx16 xysppc IDX2 18 1B xb ee ff OfRPP EMIND D xysppc D IDX 18 1B xb OfIfRPf EMIND oprx16 xysppc IDX2 18 1B xb ee ff OfIPRPf For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale
211. Debug Mode BDM sub block of the Core 14 1 Overview The Background Debug Mode BDM sub block is a single wire background debug system implemented in on chip hardware for minimal CPU intervention All interfacing with the BDM is done via the BKGD pin 14 1 1 Features e Single wire communication with host development system e Active out of reset in special single chip mode e Nine hardware commands using free cycles if available for minimal CPU intervention e Hardware commands not requiring active BDM e 15 firmware commands execute from the standard BDM firmware lookup table e Instruction tagging capability e Software control of BDM operation during wait mode e Software selectable clocks e BDM disabled when secure feature is enabled For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc 14 1 2 Block Diagram The block diagram of the BDM is shown in Figure 14 1 below 16 BIT SHIFT REGISTER gt ADDRESS _ INSTRUCTION DECODE BUS INTERFACE AND AND EXECUTION eee CLOCKS SDV standard BDM firmware ENBDM LOOKUP TABLE Figure 14 1 BDM Block Diagram 14 2 Interface Signals A single wire interface pin is used to communicate with the BDM system Two additional pins are used for instruction tagging These pins are part of the Multiplexed External Bus Interface MEBI sub block and all interfacing between the MEBI and BDM is done with
212. E8 xbee ff E8 xb E8 xbee ff h fractional part of lookup value initialize index register to point to first tal P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf ORRffffffP EXG abcdxysp abcdxysp Exchange register contents r1 e r2 r1 and r2 same size 00 r1 r2r1 8 bit r2 16 bit 11 e r2 r1 16 bit r2 8 bit INH B7 eb Fractional divide D X X remainder D 16 by 16 bit For More Information On This Product Go to www freescale com OffffffffffO Core User Guide siocpuimtaRscale Semiconductor Inc Source Form IBEQ abdxysp rel9 IBNE abaxysp rel9 Operation Increment and branch if equal to 0 counter 1 counter If counter 0 then branch Increment and branch if not equal to 0 counter 1 counter If counter 0 then branch Address Mode Machine Coding Hex Access Detail branch no branch PPP branch PPO no branch SXHINZVC IDIVS Integer divide unsigned D X gt X Remainder D 16 by 16 bit Integer divide signed D X X Remainder D 16 by 16 bit 18 Offffffffffo OLTELFEEEELO INC opr16a INC oprx0_xysppc INC oprx9 xysppc INC oprx16 xysppc INC D xysppc INC
213. EAX B X ABYSame as LEAY B Y ADCA opr8i ADCA opr8a ADCA opr16a ADCA oprx0_xysppc ADCA oprx9 xysppc ADCA oprx16 xysppc ADCA D xysppc ADCA oprx16 xysppc Add Bto X X B gt X Add Bto Y Y B gt Y Add with carry to A A M C A or A imm C A IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 89ii 99 dd B9hh11 A9xb A9xb ff A9xbee ff A9xb A9xbee ff For More Information On This Product Go to www freescale com rPf rPO rPt rPO frPP fIfrPf fIPrPf Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Source Form ADCB opr8i ADCB opr8a ADCB opr16a ADCB oprx0_xysppc ADCB oprx9 xysppc ADCB oprx16 xysppc ADCB D xysppc ADCB oprx16 xysppc ADDA Hopr8i ADDA opr8a ADDA opr16a ADDA oprx0_xysppc ADDA oprx9 xysppc ADDA oprx16 xysppc ADDA D xysppc ADDA oprx16 xysppc Operation Add with carry to B B M C B or B imm C B Add to A A M A or A imm gt A Address Mode Machine Coding Hex Access Detail P rPf rPO rPf TPO frPP fIfrPf fIPrPf P TFE rPO rPf rPO TEPE fIfrPf fIPrPf SXHINZVC ADDB opr8i ADDB opr8a ADDB opr16a ADDB oprx0_xysppc ADDB oprx9 xysppc ADDB oprx16 xysppc ADDB D xysppc ADDB oprx16 xysppc ADDD opr16i ADDD opr8a ADDD opr16a ADDD oprx0_xysppc ADDD oprx9 xysppc ADDD oprx16 xysppc
214. EAY oprx9 xysppc LEAY oprx16 xysppc Load effective address into Y EA Y Pf PO PP LSL opr16aSame as ASL LSL oprx0_xysppc LSL oprx9 xysppc LSL oprx16 xysppc LSL D xysppc LSL oprx16 xysppc LSLASame as ASLA LSLBSame as ASLB LSLDSame as ASLD Logical shift left M Pa C b7 Logical shift left A Logical shift left B Logical shift left D LH Cc MH b7 A b0 rOPw rPw rPOw frPPw fIfrPw fIPrPw LSR opr16a LSR oprx0_xysppc LSR oprx9 xysppc LSR oprx16 xysppc LSR D xysppc LSR oprx16 xysppc LSRA LSRB Logical shift right M o gt H b7 bo C Logical shift right A Logical shift right B Logical shift right D o gt b7 A bO b7 B 74hh 11 64 xb 64xb ff 64xbee ff 64 xb 64xbee ff 44 54 rPwO rPw rPwO frPwP fIfrPw fIPrPw MAXA oprx0_xysppc MAXA oprx9 xysppc MAXA oprx16 xysppc MAXA D xysppc MAXA oprx16 xysppc Maximum in A put larger of 2 unsigned 8 bit values in A MAX A M gt A N Z V C bits reflect result of internal compare A M OrPf OrPO OfrPP OfIfrPf OfIPrPf MAXM oprx0_xysppc MAXM oprx9 xysppc MAXM oprx16 xysppc MAXM D xysppc MAXM oprx16 xysppc Maximum in M put large
215. EXT 18 0B ii MOVB opr8i oprx0_xysppc Memory to memory 8 bit byte move IMM IDX 18 08 x MOVB opr16a opr16a M1 Mo EXT EXT 18 0Ch MOVB opr16a oprx0_xysppc First operand specifies byte to move EXT IDX 18 09 x MOVB oprx0_xysppc opr16a IDX EXT 18 0D x MOVB oprx0_xysppc oprx0_xysppc IDX IDX 18 0A x MOVW oprx16 opr16a Move word IMM EXT 18 03 jj MOVW opr16i oprx0_xysppc Memory to memory 16 bitword move IMM IDX 18 00 x MOVW opr16a opr16a My My 1 gt M gt M gt 1 EXT EXT 18 04h MOVW opr16a oprx0_xysppc First operand specifies word to move EXT IDX 18 01 x MOVW oprx0_xysppc opr16a IDX EXT 18 05x MOVW oprx0_xysppc oprx0_xysppc IDX IDX 1802x MUL Multiply unsigned 12 A x B gt A B 8 by 8 bit NEG opr16a Negate M 0 M M or M 1 M 70hh11 rPwO NEG oprx0_xysppc 60 xb rPw NEG oprx9 xysppc 60 xb ff rPwO NEG oprx16 xysppc 60xbee ff frPwP NEG D xysppc 60 xb flfrPw NEG oprx16 xysppc _ 60xbee ff fIPrPw NEGA Negate A 0 A A or A 1 A 40 NEGB Negate B 0 B 8B or B 1 gt B 50 NOP No operation A7 ORAA opr8i OR accumulator A 8Aii ORAA opr8a A M gt A 9A dd rPf ORAA opr16a or A imm A BAhh 11 rPO ORAA oprx0_xysppc AA xb rPf ORAA oprx9 xysppc AA xb ff rPO ORAA oprx16 xysppc AAxbee ff frPP ORAA D xysppc AA xb flfrPf ORAA oprx16 xysppc AAxbee ff fIPrPf ORAB opr8i OR acc
216. EXT IDX 18 09 xb hh 11 OPrPw MOVB oprx0_xysppc opr16a IDX EXT 118 0D xb hh 11 OrPwP MOVB oprx0_xysppc oprx0_xysppc IDX IDX 18 0A xb xb OrPwO NOTES 1 The first operand in the source code statement specifies the source for the move For More Information On This Product Go to www freescale com Core User Guide MOVW Operation CCR Effects Code and CPU Cycles si2cpu A A8gscale Semiconductor Inc Move Word MOVW My Mi 1 gt M M gt 1 Moves the value in one 16 bit memory location M M 1 to another 16 bit memory location M gt M 1 The value in M M 1 does not change Move instructions can use different addressing modes to access the source and destination of a move These combinations of addressing modes are supported IMM EXT IMM IDX EXT EXT EXT IDX IDX EXT and IDX IDX IDX operands allow indexed addressing mode specifications that fit in a single postbyte including 5 bit constant accumulator offsets and autoincrement decrement modes Nine bit and 16 bit constant offsets would require additional extension bytes and are not allowed Indexed indirect modes for example D r are also not allowed S X H l N Z V C 1 Address Machine Source Form Mode Code Hex CPU Cycles MOVW opr16i opr16a IMM EXT 18 03 jj kk hh 11 OPWPO MOVW opr16i oprx0_xysppc IMM IDX 18 00 xb jj kk OPPW MOVW opr16a opr16a EXT EXT 18 04 hh 11 hh 11JORPWPO MOVW opr16a oprx0_xysppc EXT IDX 1
217. Eh w ws fab fae fb0 fb1 Fh Fh h Fh fb2 fb5 fb7 fb8 Fh FH h Fh Hh fb9 foc Hh f fbe ffbf ffc0 b7 84 80 2b c5 26 57 27 TE c6 T2 05 Le 6c 20 fc b7 20 fc b7 20 fe 20 a7 a7 fd 20 a7 a7 ff 20 48 48 05 01 07 02 be 20 37 ff b8 ff 07 fd Ef 21 a4 ff ES 9d EE b4 96 ff 91 ff 8a ff 83 fc 00 01 10 f6 02 02 02 02 02 02 Freescale Semiconductor WOE Guide NOT_EXE tfra b Duplicate command in B anda 07 Strip all but 3 bit reg code suba 2 codes 0 1 illegal or unused bmiINST_DONE branch if A now negative bitb 20 Check R W bit bne COMP_GOTO Go decode read command was beq tp 3 30 WAIT_DATA tstINSTR Check for new command beqINST_LOOP Need escape if old command aborted brclrSTATUS 10 WAIT_DATA Wait for data ready ldab 7 mul 7B 7 reg_cod 1 jmpb pc Calculated GOTO Each write command corresponding to reg code 2 7 takes exactly 7 bytes For command 2 write next word the jump will GOTO 0 pc or the location immediately after the jump For command 7 write SP the jump will go to 5 7 pc Each command ends with a branch to the main command loop XT_WRD S t 1ddSHIFTER Get data to write std2 x pre inc x by 2 and store word INST_DONE1 braINST_DONE Intermediate branch to loop top WRITE_PC
218. FF n a 3E 8000 BFFF n a PIX5 0 C000 FFFF n a 3F Table 11 12 48K Byte Physical Flash ROM Allocated Address Space Page Window Access ROMHM 0000 3FFF n a 4000 7FFF n a For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc Table 11 12 48K Byte Physical Flash ROM Allocated Address Space Page Window Access ROMHM ECS XAB19 14 external 8000 BFFF PIX5 0 internal C000 FFFF n a 3F Table 11 13 64K Byte Physical Flash ROM Allocated Address Space Page Window Access ES XAB19 14 0 0000 3FFF n a 3D 4000 7FFF n a 3E ternal 8000 BFFF sti PIX5 0 internal C000 FFFF n a 3F A graphical example of a memory paging for a system configured as 1M byte on chip Flash ROM with 64K allocated physical space is given in Figure 11 12 below for illustration For More Information On This Product Go to www freescale com 0000 4000 8000 16K FLAS Paged C000 16K FLAS Unpaged FFOO FFFF NORMAL SINGLE CHIP Freescale Semiconductor WOE Guide 12CPU15UG V1 2 One 16K FLASH ROM Page accessible at a time selected by PPAGE 0 to 63 These 16K FLASH ROM pages accessi ble from 0000 to 7FFF if selected by the ROMHM bit in the MISC register Figure 11 12 Memory Paging Example 1M Byte On Chip Flas
219. FR CCR A CCR gt A 0110X000 B760 YL A TFR CCR B CCR gt B 0110 X001 B761 Y gt B TFR CCR CCR CCR CCR 0110 X010 B7 62 YL CCR TFR CCR TMP2 sex CCR TMP2 0110X011 B763 ly TMP2 TFR CCR D sex CCR D 0110X100 B764 ly gt D TFR CCR X sex CCR gt X 0110X101 B765 lyx TFR CCR Y sex CCR gt Y 0110X110 B766 ly y TFR CCR SP 0010 X111 sex CCR SP 0110 X111 B7 67 Y SP TFR TMP3 A 0011 X000 TMP3 A 0111 X000 B770 SPL A TFR TMP3 B TMP3 gt B 0111 X001 B7 71 SPL gt B TFR TMP3 CCR TMP3 CCR 0111 X010 B772 SP CCR TFR TMP3 TMP2 TMP3 TMP2 0111X011 B773 SP TMP2 TFR TMP3 D TMP3 D 0111 X100 B774 sp3pD TFR TMP3 X TMP3 X 0111 X101 B7 75 SP X TFR TMP3 Y TMP3 Y 0111 X110 B776 SP Y TFR TMP3 SP 0011 X111 TMP3 gt SP 0111X111 8777 sp gt sSpP For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc T PA Transfer CCR to A T PA same as TFR CCR A Operation CCR A Transfers the value in CCR to A The CCR value does not change TPA assembles as TFR CCR A CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex TPA INH B7 20 P For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 T R A P Unimplemented Opcode Trap T R A p Operation CCR Effects Code and CPU Cycles SP 0002 gt SP RITNy
220. For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 C 5 2 Autoincrement Autodecrement Indexing The HCS12 provides greatly enhanced autoincrement and autodecrement modes of indexed addressing In the HCS12 the index modification may be specified before the index is used pre or after the index is used post and the index can be incremented or decremented by any amount from one to eight independent of the size of the operand accessed X Y and SP can be used as the index reference but this mode does not allow PC to be the index reference Modifying PC would interfere with proper program execution This addressing mode can be used to implement a software stack structure or to manipulate data structures in lists or tables rather than manipulating bytes or words of data Anywhere an M68HC11 program has an increment or decrement index register operation near an indexed mode instruction the increment or decrement operation can be combined with the indexed instruction with no cost in object code size as shown in the following code comparison 18A600 LDAAO Y 1808 INY A671 LDAA2 Y 1808 INY The M68HC11 object code takes seven bytes while the HCS12 takes only two bytes to accomplish the same functions Three bytes of M68HC11 code are due to the page prebyte for each Y related instruction 18 HCS12 postincrement indexing capability allows the two INY instructions to be abs
221. Freescale Semiconductor Inc POCUMENT NUMBER S12CPU15UG D HCS12 V1 5 Core User Guide Version 1 2 Original Release Date 12 May 2000 Revised 17 August 2000 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Revision History Release Number Date Author Summary of Changes 1 2 17 August 2000 Update allocated RAM space table 12 13 October 2000 Security enhancements add core_exp 12 core_per t2 outputs and peri_clk2 peri_clk4 and ram_fmts inputs 1 1 21 July 2000 Correct access detail for LSL instruction in appendix B 1 0 12 May 2000 Original draft Distributed only within Motorola Version 1 2 17 August 2000 HCS12 V1 5 Core For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide Table of Contents Section 1 Introduction 1 1 1 2 1 3 1 4 1 5 1 6 1 6 1 1 6 2 1 7 1 8 1 8 1 1 8 2 1 8 3 1 8 4 1 8 5 1 8 6 1 8 7 ORG COVE VOY a O E toe neue ewes BSA CS eee greet a red ain A a a ead a es ab ac aac armani blvd ye ua caine NN Bloek Diagra mM aat 2a 5ec snuck pubis take OSs Seek bau aN See a Arne cual Summary TA EE ES ca aie IT eat ied Oe Prodramiming Model cto ore dr as Data Format Summa iie ieira a kea o o a as O a eb O Be d O od Data TDS si eS ere alts Sei Memory Organization aon voted A A o A a bea Addressing modes cool Aa de ia eta Instruction Set Overview a A ao Register and Memory N
222. Fuzzification MEM During the fuzzification step the current system input values are compared to stored input membership functions to determine the degree to which each label of each system input is true This is accomplished by finding the y value for the current input value on a trapezoidal membership function for each label of each system input The MEM instruction performs this calculation for one label of one system input To perform the complete fuzzification task for a system several MEM instructions must be executed usually in a program loop structure Figure B 2 shows a system of three input membership functions one for each label of the system input The x axis of all three membership functions represents the range of possible values of the system input The vertical line through all three membership functions represents a specific system input value The y axis represents degree of truth and varies from completely false 00 or 0 to completely true FF or 100 The y value where the vertical line intersects each of the membership functions is the degree to which the current input value matches the associated label for this system input For example the expression temperature is warm is 25 true 40 The value 40 is stored to a RAM location and is called a fuzzy input in this case the fuzzy input for the temperature is warm There is a RAM location for each fuzzy input for each label of each system input When the
223. G11 Internal register map position These five bits show the state of the upper five bits of the base address for the system s relocatable register block BDMINR is a shadow of the INITRG register which maps the register block to any 2K byte space within the first 32K bytes of the 64K byte address space 14 4 Operation The BDM receives and executes commands from a host via a single wire serial interface There are two types of BDM commands namely hardware commands and firmware commands Hardware commands are used to read and write target system memory locations and to enter active background debug mode see 14 4 3 Target system memory includes all memory that is accessible by the CPU Firmware commands are used to read and write CPU resources and to exit from active background debug mode see 14 4 4 The CPU resources referred to are the accumulator D X index register X Y index register Y stack pointer SP and program counter PC Hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted in 14 5 below Firmware commands can only be executed when the system is in active background debug mode BDM 14 4 1 Security If the user resets into special single chip mode with the system secured a secured mode BDM firmware lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table The secure BDM firmware verifies that the on chip EEPROM and Fla
224. G12 REG11 i e EE15 EE14 EE13 EE12 EE11 E 9 EEON y EXSTR1 EXSTRO ROMHM ROMON Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_swO rom_sw1 rom_sw0 0 0 0 0 pag_sw1 pag_sw0 E 9 PIX5 PIX4 PIX3 PIX2 PIX1 PIXO 0 0 0 0 0 0 0 0 Unimplemented X Indeterminate Figure 11 2 Module Mapping Control Register Summary For More Information On This Product Go to www freescale com Core User Guide si2cpu Rf Scale Semiconductor Inc 11 3 1 Initialization of Internal RAM Position Register INITRM Address Base 10 Bit 7 6 5 4 3 2 1 Bit O Read 0 0 RAM RAM15 RAM14 RAM13 RAM12 RAM11 Write HAL rite Reset 0 0 0 0 1 0 0 1 Unimplemented Figure 11 3 INITRM Register Read Anytime Write Once in Normal and Emulation Modes anytime in Special Modes NOTE Writes to this register take one cycle to go into effect This register initializes the position of the internal RAM within the on chip system memory map RAMI5 RAMI Internal RAM Map Position These bits determine the upper five bits of the base address for the system s internal RAM array RAMHAL RAM High align RAMHAL specifies the alignment of the internal RAM array 0 Aligns the RAM to the lowest address 0000 of the mappable space 1 Aligns the RAM to the higher address SFFFF of the mappable spac
225. GISUCT Sie Be OS ANNA 181 11 3 1 Initialization of Internal RAM Position Register INITRM 182 11 3 2 Initialization of Internal Registers Position Register INITRG 182 113 3 Initialization of Internal EEPROM Position Register INITEE 183 11 3 4 Miscellaneous System Control Register MISC 000002 eee eee 184 11 3 5 Reserved Test Register Zero MTSTO 2 000 eee eee 185 11 3 6 Reserved Test Register One MTST1 2 0000s 185 11 3 7 Memory Size Register Zero MEMSIZO 0 000 cee ee 186 11 3 8 Memory Size Register One MEMSIZ1 0 0 0000 ee 187 11 3 9 Program Page Index Register PPAGE 000 eee eee 188 14d Operation ao ar E Bite ee a a a aa RS Nee Me 189 Malo BUS COMMON store E EA AA R 189 11 4 2 Address Decoding insegue ta ORS oh Be sa 189 Tsao Memory EXPANSION so SS AS Se eae 8 191 11 5 Motorola Internal Information 0000 ee 196 1311 Test Registers a thea AE RN Ea 196 11 5 2 MMC Bus Control oc ieee as ico 198 Section 12 Multiplexed External Bus Interface MEBI 12 O AA A EN 201 At i E 201 12 1 2 Block Diagram nr A Se Ree ere ee eed ny beens Bie Bye erica Dye wed Syn ened ye Bal 202 12 2 Interface SIS ars Ae aaa aire 202 12 2 1 MEBI Signal Descriptions 0 0 2 eee ee 203 2 3 Register Sennen 20 eee Se dk yk Oe be ene eee ee tite one hem yan ea te 207 12 3 1 Port A Data Register
226. Go to www freescale com Core User Guide BLT Operation CCR Effects Code and CPU Cycles si2cpu A A8gscale Semiconductor Inc Branch if Less Than Zero B LT If N O V 1 then PC 0002 rel gt PC BLT can be used to branch after subtracting or comparing signed two s complement values After CMPA CMPB CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the CPU register value is less than the value in M After CBA or SBA the branch occurs if the value in B is less than the value in A Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction S X H I N Z V C Address Machine Source Form Mode Code Hex CPU Cycles BLT rela REL 2D rr PPP branch P no branch Branch Complementary Branch Comment Mnemonic Opcode Mnemonic Opcode Test BLT 2C BLO BCS BHS BCC For More Information On This Product Go to www freescale com BMI Operation CCR Effects Code and CPU Cycles Freescale Semiconductor WOE Guide Branch if Minus If N 1 then PC 0002 rel PC Tests the N bit and branches if N 1 Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from
227. Guide si2cpu A A8gscale Semiconductor Inc 5 4 1 Register and Memory Notation Aora An Table 5 2 Register and Memory Notation Accumulator A Bit n of accumulator A Borb Accumulator B Bit n of accumulator B Accumulator D Bit n of accumulator D Index register X High byte of index register X Low byte of index register X Bit n of index register X Index register Y High byte of index register Y Low byte of index register Y Bit n of index register Y Stack pointer Bit n of stack pointer Program counter High byte of program counter Low byte of program counter CCR or c Condition code register M Mn Address of 8 bit memory location Bit n of byte at memory location M Rn Bit n of the result of an arithmetic or logical operation In RTNy Bit n of the intermediate result of an arithmetic or logical operation High byte of return address RTN Low byte of return address 0 Contents of For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 5 4 2 Source Form Notation The Source Form column of the summary in Table 5 1 gives essential information about assembler source forms For complete information about writing source files for a particular assembler refer to the documentation provided by the assembler vendor Everything in the Source Form column except expressions in it
228. Hz Hz alle Hil Hz Hiv Wir asr arai dVHL dvel dVel dvel dvel dVHL dvel dVel dvel dvel dvel dvel dvul IHa7 SOVWa MAOW Ol zalot zajo zajol zojol zajol zwiol zelot zeol zo zelol zslol zbriol zele zze el zljg zo Z Hz Hez He Hille He Hilfe Hse Hie Hz He Hilfe Hi He ule HIS ars dVYL dvel dVel dvel dvel dVHL dvel dVel dvel dvel dval dvel dvel Nugl AIGS MON Ol talot salot alot tolor ralo twiol elot glot IZ OL ojob tglol plot tele tzzl tig to Z Hie HZ HZ Hi Hz Hz Hz Hz alle alle Hie Hz Hiv wie Hle amni dvedl dvel dVel dvel dvel dVHL dvel dVel dvel dvel dvel dvel dvel ysg Nal MON Ol ox3 0r O3 0 OG Ol 090 Oglol oOwviol 06 0 Ogjol OZ O 09 01 OS Ol Oriol oe y 0z zL Ol y 00 98 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide ds 4 6 Transfer and Exchange Postbyte Encoding 12CPU15UG V1 2 Transfers TMP3 gt A YLA B CCR CCR gt CCR TMP3 gt B TMP3 CCR B CCR X_ gt CCR Y B SP CCR SEX A SP SEX B SP SEX CCR SP 3 sex A gt TMP2 sex B TMP2 sex CCRTMP2 TMP3 TMP2 D TMP2 X TMP2 Y TMP2 SP TMP2 4 CAD ECO cab TMP3 gt D D D xD Y gt D SPD 5 alan EN eee TMP3 gt X D gt X X X Y gt Xx SP X
229. Inc LBLS Long Branch if Lower or Same LBLS Operation CCR Effects Code and CPU Cycles If C Z 1 then PC 0004 rel gt PC LBLS can be used to branch after subtracting or comparing unsigned values After CMPA CMPB CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the CPU register value is less than or equal to the value in M After CBA or SBA the branch occurs if the value in B is less than or equal to the value in A Rel is a 16 bit two s complement offset for branching forward or backward in memory Branching range is 8000 to 7FFF 32768 to 32767 from the address following the last byte of object code in the instruction S X H I N Z V C Address Machine Source Form Mode Code Hex CPU Cycles LBLS rel16 REL 18 23 qq rr OPPP branch OPO no branch Branch Complementary Branch Comment Mnemonic Opcode Test Mnemonic Opcode Test R lt M R gt M or or LBLS 18 23 B lt A LBHI 18 22 B gt A Unsigned C Z 1 R lt M or LBLE 182F B lt A LBGT 18 2E Signed Z NOV 1 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 LBLT Long Branch if Less Than Zero LBLT Operation IfN O V 1 PC 0004 rel gt PC LBLT can be used to branch after subtracting or comparing signed two s complement values After CMPA CMP
230. Indexed indirect 16 bit offset INST oprx9 xysp INST oprx16 xysp INST oprx16 xysp IDX2 Effective address is the value in X Y SP or PC plus a 9 bit signed constant offset Effective address is the value in X Y SP or PC plus a 16 bit constant offset The value in X Y SP or PC plus a 16 bit constant offset points to the effective address Indexed indirect D accumulator offset INST D xysp 1 8 Instruction Set Overview D IDX The value in X Y SP or PC plus the value in D points to the effective address All memory and I O are mapped in a common 64K byte address space allowing the same set of instructions to access memory I O and control registers Load store transfer exchange and move instructions facilitate movement of data to and from memory and peripherals There are instructions for signed and unsigned addition division and multiplication with 8 bit 16 bit and some larger operands Special arithmetic and logic instructions aid stacking operations indexing BCD calculation and condition code register manipulation There are also dedicated instructions for multiply and accumulate operations table interpolation and specialized mathematical calculations for fuzzy logic operations A summary of the CPU instruction set is given in Table 1 2 below A detailed overview of the entire instruction set is covered in Section 4 of this guide along with an instruction by instruction de
231. K LSTRB R W IRQ and XIRQ A single control bit enables the pullups for all of these pins when they are configured as inputs This register is not in the on chip map in peripheral mode or in expanded modes when the EME bit is set For More Information On This Product Go to www freescale com Core User Guide si2cpu ERA Scale Semiconductor Inc CAUTION lt is unwise to write PORTE and DDRE as a word access If you are changing Port E pins from being inputs to outputs the data may have extra transitions during the write It is best to initialize PORTE before enabling as outputs CAUTION To ensure that you read the value present on the PORTE pins always wait at least one cycle after writing to the DDRE register before reading from the PORTE register 12 3 6 Data Direction Register E DDRE Address Base 9 BIT 7 6 5 4 3 2 1 BIT O Read 0 0 Bit 7 6 5 4 3 Bit 2 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 12 8 Data Direction Register E DDRE Read anytime when register is in the map Write anytime when register is in the map Data Direction Register E is associated with Port E For bits in Port E that are configured as general purpose I O lines DDRE determines the primary direction of each of these pins A 1 causes the associated bit to be an output and a 0 causes the associated bit to be an input Port E bit 1 associated with IRQ and bit 0 associated with XIRQ cannot be configured as ou
232. KK KKK KKK KKK KKK KKK KKK RARAS Copyright C 1997 by Motorola Inc 6501 William Cannon Drive West Advanced MCU HC11 Group Austin TX 78735 8598 F All rights reserved No part of this software may be sold or distributed For More Information On This Product Go to www freescale com in any form or b Motorola Inc MOTOROLA C PRR RRR RAR RAR RAR RARA Freescale Semiconductor ING Guide s12cPU15UG v1 2 y any means without the prior written permission of ONFIDENTIAL PROPRIETARY INFORMATION KKK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KKK KEK KKK KKK KKK KKK KKK KKK KKK KKK Started from UDR H VERSION HISTORY C12 BDM ROM code Design Strategy standard There are Those area special ca items to B CAUTION 1 CAUTION 2 CAUTION 3 CAUTION 4 CAUTION 5 CAUTION 6 CAUTION 7 CAUTION 8 CAUTION 9 CAUTION 10 BDM firmware for M68HC12 MANY traps that someone modifying this code MUST be aware of s that have traps that we have fallen into and requiring re have been marked with CAUTION Here is a list of EWARE of Review this list after ANY ROM code changes There is an inherent cpudead cycle that we rely on in the INST_LOOP loop when that ldaa instruction falls on an even address For this reason an ALIGN directive MUST be used at that location See AR 156 The first event that occurs in code that may interfere with user code is the savin
233. LDAB D xysppc flfrPf LDAB oprx16 xysppc fIPrP LDD opr16i Load D j PO LDD opr8a M M 1 A B RP LDD opr16a or imm gt A B RPO LDD oprx0_xysppc RP LDD oprx9 xysppc RPO LDD oprx16 xysppc fRPP LDD D xysppc fIfRPf LDD oprx16 xysppc fIPRPf LDS opr16i Load SP PO LDS opr8a M M 1 SP RPf LDS opr16a or imm SP RPO LDS oprx0_xysppc RP LDS oprx9 xysppc RPO LDS oprx16 xysppc RPP LDS D xysppc fIfRPf LDS oprx16 xysppc fIPRPf LDX opr16i Load X j PO LDX opr8a M M 1 gt X RPf LDX opr16a or imm gt X RPO LDX oprx0_xysppc RPf LDX oprx9 xysppc RPO LDX oprx16 xysppc fRPP LDX D xysppc fIfRPf LDX oprx16 xysppc fIPRPf LDY opr16i Load Y IMM CD jj kk PO l lala o LDY opr8a M M 1 gt Y DIR DD dd RPf LDY opr16a or imm gt Y EXT FDhh11 RPO LDY oprx0_xysppc IDX ED xb RPf LDY oprx9 xysppc IDX1 ED xb ff RPO LDY oprx16 xysppc IDX2 ED xbee ff fRPP LDY D xysppc D IDX ED xb fIfRP LDY oprx16 xysppc IDX2 ED xbee ff fIPRP For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Source Form LEAS oprx0_xysppc LEAS oprx9 xysppc LEAS oprx16 xysppc LEAX oprx0_xysppc LEAX oprx9 xysppc LEAX oprx16 xysppc Operation Load effective address into SP EA gt SP Load effective address into X EA gt X Address Mode Machine Coding Hex Access Detail SXHINZVC PE PO PP LEAY oprx0_xysppc L
234. M or B imm IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 Clii D1 dd Flh El x El x El x Elx El x ALL bff bee ff bee ff rPf rPO rPf rPO frPP fIfrPf fIPrPf P TP E rro rPf rPO frPP fIfrPf fIPrPf For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Source Form COM opr16a COM oprx0_xysppc COM oprx9 xysppc COM oprx16 xysppc COM D xysppc COM oprx16 xysppc COMA COMB Operation Complement M M FF M M Complement A A FF A gt A B eo Complement B B 5FF B gt B Address Mode Machine Coding Hex 71hh11 61 xb 61 xb ff 61xbee ff 61 xb 61xbee ff 41 51 Access Detail SXHINZVC rPwO rPw rPwO frPwP fIfrPw fIPrPw O O CPD opr16i CPD opr8a CPD opr16a CPD oprx0_xysppc CPD oprx9 xysppc CPD oprx16 xysppc CPD D xysppc CPD oprx16 xysppc Compare D A B M M 1 or A B imm 8C jj kk 9C dd BChh11 AC xb AC xb ff AC xbee ff AC xb AC xbee ff PO RPf RPO RP RPO fRPP fIfRP fIPRP CPS opr16i CPS opr8a CPS opr16a CPS oprx0_xysppc CPS oprx9 xysppc CPS oprx16 xysppc CPS D xysppc CPS oprx16 xysppc CPX opr16i CPX opr8a CPX o
235. M INT BDM Interrupt BKGD Background Pin Debug BKP Mode Breakpoint MEBI Multiplexed External Bus Interface Port B 8 bit Port E 8 bit Port K 8 bit Port A 8 bit Figure 1 1 Core Block Diagram The main sub blocks of the Core are e Central Processing Unit CPU 68HC12 ISA compatible e Interrupt INT e Module Mapping Control MMC e Multiplexed External Bus Interface MEBI e Breakpoint BKP e Background Debug Mode BDM For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc 1 4 Architectural Summary As briefly discussed previously the Core consists of the HCS12 Central Processing Unit CPU along with the Interrupt INT Module Mapping Control MMC Multiplexed External Bus Interface MEBI Breakpoint BKP and Background Debug Mode BDM sub blocks The CPU executes the 68HC12 CPU ISA with a three stage instruction queue to facilitate a high level of code execution efficiency The INT sub block interacts with the CPU to provide 2 to 122 I bit maskable configured at system integration 1 X bit maskable and 2 nonmaskable CPU interrupt vectors 3 reset vectors and handles waking up the system from wait or stop mode due to a serviceable interrupt The MMC sub block controls address space mapping and generates memory selects and a single peripheral select to be decoded by the I P Bus as well as multiplexing the a
236. M hardware upon entry into BDM It can only be cleared by the standard BDM firmware lookup table upon exit from BDM active mode CLKSW can only be written via BDM hardware or standard BDM firmware write commands All other bits while writable via BDM hardware or standard BDM firmware write commands should only be altered by the BDM hardware or standard firmware lookup table as part of BDM command execution ENBDM should only be set via a BDM hardware command if the BDM firmware commands are needed This does not apply in Special Single Chip Mode ENBDM Enable BDM This bit controls whether the BDM is enabled or disabled When enabled BDM can be made active to allow firmware commands to be executed When disabled BDM cannot be made active but BDM hardware commands are still allowed 1 BDM enabled 0 BDM disabled NOTE ENBDM is set by the firmware immediately out of reset in special single chip mode In secure mode this bit will not be set by the firmware until after the EEPROM and FLASH erase verify tests are complete BDMACT BDM active status For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 This bit becomes set upon entering BDM The standard BDM firmware lookup table is then enabled and put into the memory map BDMACT is cleared by a carefully timed store instruction in the standard BDM firmware as part of the exit sequence to return to u
237. Mgp 1 mode 7 SP 2 gt 8P B A gt Msp Msp 1 aoe stop SP 1 gt SP CCR Msp 00 if stop mode Stop all clocks disabled by S 1 STS opr8a Store SP DIR 5F dd PW Ja a o STS opr16a SPy SP gt M M 1 EXT 7Fhh11 PWO STS oprx0_xysppc IDX 6F xb PW STS oprx9 xysppc IDX1 6F xb ff PWO STS oprx16 xysppc IDX2 6F xbee ff PWP STS D xysppc D IDX 6F xb PIFW STS oprx16 xysppc IDX2 6F xbee ff PIPW STX opr8a Store X DIR 5E dd PW JaJa o STX opr16a Xy X_ M M 1 EXT JE hh 11 PWO STX oprx0_xysppc IDX 6E xb PW STX oprx9 xysppc IDX1 6E xb ff PWO STX oprx16 xysppc IDX2 6Exbee ff PWP STX D xysppc D IDX 6Exb PIFW STX oprx16 xysppc IDX2 6Exbee ff PIPW For More Information On This Product Go to www freescale com Core User Guide si2cPu ERA Scale Semiconductor Inc R Address Machine Source Form Operation Mode Coding Hex STY opr8a Store Y 5D dd STY opr16a YH Y M M 1 7Dhh11 STY oprx0_xysppc 6D xb STY oprx9 xysppc 6D xb ff STY oprx16 xysppc 6Dxbee ff STY D xysppc 6D xb STY oprx16 xysppc 6Dxbee ff SUBA opr8i Subtractfrom A 80ii P SUBA opr8a A M gt A 90 dd rPf SUBA opr16a or A imm gt A BOhh11 rPO SUBA oprx0_xysppc AO xb rPf SUBA oprx9 xysppc AO xb ff rPO SUBA oprx16 xysppc AO xbee ff frPP SUBA D xysppc AO xb flfrPf SUBA oprx16 xysppc AO xbee ff fIPrPf SUBB opr8i Subtract from B j P SUBB opr8a B M B rPf SUBB opr16a or B imm gt B rPO SUBB
238. Mode or Full Mode 0 Dual Address Mode enabled 1 Full Breakpoint Mode enabled BKBDM Breakpoint Background Debug Mode Enable This bit determines if the breakpoint causes the system to enter Background Debug Mode BDM or initiate a Software Interrupt SWI 0 Go to Software Interrupt on a compare 1 Go to BDM on a compare BKTAG Breakpoint on Tag This bit controls whether the breakpoint will cause a break on the next instruction boundary force or on a match that will be an executable opcode tagged Non executed opcodes cannot cause a tagged breakpoint 0 On match break at the next instruction boundary force 1 On match break if the match is an instruction that will be executed tagged 13 3 2 Breakpoint Control Register 1 BKPCT1 Read anytime Write anytime For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc Address 0029 Bit 7 6 5 4 3 2 1 Bit O Read BKOMBH BKOMBL BK1MBH BK1MBL BKORW BKORW BKIRW BK1RW Write E E Reset 0 0 0 0 0 0 0 0 Figure 13 4 Breakpoint Control Register 1 BKPCT1 This register is used to configure the functionality of the Breakpoint sub block within the Core BKOMBH BKOMBL Breakpoint Mask High Byte and Low Byte for First Address In Dual or Full Mode these bits may be used to mask disable the comparison of the high and low bytes of the first address breakpoint The fun
239. Normally SP is initialized by one of the first instructions in an application program The stack grows downward from the address pointed to by SP Each time a byte is pushed onto the stack the stack pointer is automatically decremented and each time a byte is pulled from the stack the stack pointer is automatically incremented When a subroutine is called the address of the instruction following the calling instruction is automatically calculated and pushed onto the stack Normally a return from subroutine RTS is executed at the end of a subroutine The return instruction loads the program counter with the previously stacked return address and execution continues at that address Read Write Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Figure 3 6 Stack Pointer SP When an interrupt occurs the CPU e Completes execution of the current instruction e Calculates the address of the next instruction and pushes it onto the stack e Pushes the contents of all the CPU registers onto the stack e Loads the program counter with the address pointed to by the interrupt vector and begins execution at that address The stacked CPU registers are referred to as an interrupt stack frame The Core stack frame is the same as that of the CPU For More Information On This Product Go to www freescale com Core User Guide si2cPu Rf Scale Semiconductor Inc 3 1 4 Program Counter PC PC is a 16 bit register that h
240. On Chip Control gore neck 12 core feearraysel OM gore vector fetch t4 q rdb_L12 15 0 Interface Vector eri_rstv_reques ecto ty Request peri_xmonv_requegs core ab 12 19 0 y Acknowledge_peri copy reg esp core wdb t4 15 0 que stop t24 core rw t2 Common Bus Stop and ue mati24 INT core 528 12 y Interface Wait Mode gore wakeup ta BDM Interrupt core exp 12 Signals Control _owai Memory and berl_ewal 18 pp Background na Peripherals Status peri syswai t3 y Debug core smod 12 pi peri test_cik_enabjg Mode BKP core perisel t2 gt PEE Breakpoint core_bdmact t4 p eri plisel t3 i nei bkgd ind gt ot scan mode Scan Control BDM a BKGD eqoiebkgd douti4_ MEBI qe Security Pin i Multiplexed External Bus Interface Peripheral Interface 2re bkgd ibhe 12 a Bus Onl ore bkgdpue_t2 pei rtifffOi_t3 den nly GSS ntertace E Signals SlelElajel Shale lau ls 2la Ela Is SlalEla a AE ls SES lla ER SO y 2 o EJES as la el8 Si8lale El8 8 Slafe l8 8 8laJe 2 Elsisisialele ojo ojo aja Soegpojojojo e ojo ojojojoa E x lt x x x x S ajajajaj aja ajajajaja ja ajajfajajajoa l a a a a a 3 a olofofo lolo ofofolo lolo elo oo lo plo plo ojo olo o ojo ojo ojo ojo ojojojo ojo lon Rom Kom nom ne ojo ojo ojojo ojo ojo ojo ojo ojojo jo ojo ojofojojo ojo ojo ojojo Port A 7 0 Port B 7 0 Port E 7 0 Port K 7 0 Interface Interface Interface Interface Figure 7 1 Core Interface Signals 7 1 1 Signal Summ
241. POE bit in PEAR CLKTO System Clock Test Output Only available in special modes PIPOE 1 overrides this function The enable for this function is in the clock module At the rising edge on RESET the state of this pin is registered into the MODA bit MODA to set the mode PE5 IPIPEO MODA PE5 General purpose I O pin see PORTE and DDRE registers IPIPEO Instruction pipe status bit O enabled by PIPOE bit in PEAR PE4 General purpose I O pin see PORTE and DDRE registers Bus timing reference clock can operate as a free running clock at the system PE4 ECLK ECLK clock rate or to produce one low high clock per visible access with the high period stretched for slow accesses ECLK is controlled by the NECLK bit in PEAR the IVIS bit in MODE and the ESTR bit in EBICTL For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc Table 12 4 External System Pins Associated With MEBI Pin Name Pin Functions Description PES General purpose I O pin see PORTE and DDRE registers LSTRB Low strobe bar 0 indicates valid data on D7 DO PE3 LSTRB S78 In peripheral mode this pin is an input indicating the size of the data transfer TAGLO 0 16 bit 1 8 bit In expanded wide mode or emulation narrow modes when instruction tagging is TAGLO on and low strobe is enabled a 0 at the falling edge of E tags the low half of the instruction word b
242. PORTA cuca A a eee ees 208 12 3 2 Data Direction Register A DDRA 002 0000 ee 209 12 3 3 Port B Data Register PORTB cepas rra 210 12 3 4 Data Direction Register B DDRB ci ea Boake ae Meee wes wees 210 123 5 Port E Data Register PORTE 0 2 00 es 211 12 3 6 Data Direction Register E DDRE 2 002 eee eee 212 12 3 7 Port E Assignment Register PEAR 000 eee 213 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide S12CPU15UG V1 2 12 3 8 MODE Register MODE 400030 oye See beh Om Re ok Piet ei et Ge ne 215 12 3 9 Pullup Control Register PUCR 0 2424 ade a SEES Eee wey 218 12 3 10 Reduced Drive Register RDRIV 0 000 eee 219 12 3 11 External Bus Interface Control Register EBICTL 00005 220 12 3 12 IRQ Control Register ROGER Ls ti tee GR id dec wR RE S 220 123 13 Reserved Register Sa mii ae dr ete eke meet ten es 222 12 3 14 Port K Data Register PORUMK s 6 20 acter pees te 222 12 3 15 Port K Data Direction Register DDRK 000 200s 223 124 Operan ot Ba BE el ca le ohio toos Mt thie oie SA arte dd oe Mite tate ia REGA 224 124 1 External BUS CONTO ii occas dies ie ds Wis ener cig 224 12 4 2 External Data Bus Interface 0 02 es 224 TES CONOS Noumea los E Ses oe Be en IS eee 224 T244 REJSIE Sn OS RAN 224 12 4 5 External System Pin Functional Descriptions
243. PU register value is greater than or equal to the value in M After CBA or SBA the branch occurs if the value in B is greater than or equal to the value in A BHS is not for branching after instructions that do not affect the C bit such as increment decrement load store test clear or complement Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction S X H I N ZV C Address Machine Source Form Mode Code Hex CPU Cycles PPP branch H P no branch Mnemonic Opcode BHS BCC BGE For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPuU15UG V1 2 BITA Bit Test A BITA Operation CCR Effects Code and CPU Cycles A M or A imm Performs a logical AND of either the value in M or an immediate value with the value in A CCR bits reflect the result The values in A and M do not change N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Machine Source Form Code Hex CPU Cycles BITA opr8i 85 ii BITA opr8a 95 dd BITA opr16a B5 hh 11 BITA oprx0_xysppc A5 xb BITA oprx9 xysppc A5 xb ff BITA oprx16 xysppc A5 xb ee ff BITA D xysppo AS xb BITA oprx16 xysppc AS xbee ff For More Inf
244. Peripheral Test Mode indicator core_per_t2 This single bit Core output indicates that the Core is in Peripheral Test Mode In this mode the cpu is disabled and the direction of the bus interface is switched such that the on chip peripherals can be addressed directly This mode is used for factory test only 7 2 1 11 Core Special Mode indicator core_smod_t2 This single bit Core output indicates that the Core is in Special Mode i e the Core has been configured in Special Mode via the MODE pins 7 2 1 12 Core Secure Mode indicator core_secure_t2 This single bit Core output indicates that the Core is operating in secured mode Please see Section 15 of this guide for functional details 7 2 1 13 Peripheral select signal core_perisel_t2 This single bit Core output indicates that the Core is accessing an address within the peripheral space of the system memory map 7 2 1 14 On Chip RAM register space select signal core_ramregsel_t2 This single bit Core output indicates that the Core is accessing an address within the on chip RAM register space of the system memory map 7 2 1 15 On Chip RAM array select signal core_ramarraysel_t2 This single bit Core output indicates that the Core is accessing an address within the on chip RAM array space of the system memory map For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 7 2 1 16 On Chip RAM array align signal
245. Pf fIPrPf For More Information On This Product Go to www freescale com Core User Guide si2cpu A R8gscale Semiconductor Inc Source Form COM opr16a COM oprx0_xysppc COM oprx9 xysppc COM oprx16 xysppc COM D xysppc COM oprx16 xysppc COMA COMB Operation Complement M M FF M M Complement A A FF A gt A B eo Complement B B 5FF B gt B Address Mode Machine Coding Hex 71hh11 61 xb 61 xb ff 61xbee ff 61 xb 61xbee ff 41 51 Access Detail rPwO rPw rPwO frPwP fIfrPw fIPrPw O O SXHINZVC CPD opr16i CPD opr8a CPD opr16a CPD oprx0_xysppc CPD oprx9 xysppc CPD oprx16 xysppc CPD D xysppc CPD oprx16 xysppc Compare D A B M M 1 or A B imm 8C jj kk 9C dd BChh11 AC xb AC xb ff AC xbee ff AC xb AC xbee ff PO RPf RPO RP RPO fRPP fIfRP fIPRP CPS opr16i CPS opr8a CPS opr16a CPS oprx0_xysppc CPS oprx9 xysppc CPS oprx16 xysppc CPS D xysppc CPS oprx16 xysppc CPX opr16i CPX opr8a CPX opr16a CPX oprx0_xysppc CPX oprx9 xysppc CPX oprx16 xysppc CPX D xysppc CPX oprx16 xysppc Compare SP SP M M 1 or SP imm Compare X X M M 1 or X imm 8F jj kk 9F dd BFhh11 AF xb AF xb ff AF xbee ff AF xb
246. PuU15UG V1 2 Section 2 Nomenclature This section describes the conventions and notation used to describe the Core operation 2 1 References This document uses the Sematech Official Dictionary and the JEDEC EIA Reference Guide to Letter Symbols for Semiconductor Devices as references for terminology and symbology 2 2 Units and Measures SIU units and abbreviations are used throughout this guide 2 3 Symbology The symbols and operators used throughout this guide are shown in Table 2 1 Table 2 1 Symbols and Operators Symbol Function Accion Subtraction two s complement or negation i Multiplication gt Greater IET e Equal or greater a er AAA Not equal AND Inclusive OR OR Exclusive OR EOR NOT Complementation 7 Exchanged ts e Ox0F Hexadecimal value 2 4 Terminology Logic level one is a voltage that corresponds to Boolean true 1 state For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc Logic level zero is a voltage that corresponds to Boolean false 0 state To set a bit or bits means to establish logic level one on them To clear a bit or bits means to establish logic level zero on them A signal is an electronic construct whose state or changes in state convey information A pin is an external physical connection The same pin can be used to connect a number of signals Asserted mean
247. R RDRIV and the EBI reserved registers In emulation modes if the EMK bit in the MODE register see 12 3 8 is set the data and data direction registers for Port K are removed from the on chip memory map and become external accesses 11 4 2 2 Emulation Chip Select Signal When the EMK bit in the MODE register see 12 3 8 is set Port K bit 7 is used as an active low emulation chip select signal ECS This signal is active when the system is in Emulation mode the EMK bit is set and the Flash EEPROM or ROM space is being addressed subject to the conditions outlined in 11 4 3 2 below When the EMK bit is clear this pin is used for general purpose I O 11 4 2 3 External Chip Select Signal When the EMK bit in the MODE register see 12 3 8 is set Port K bit 6 is used as an active low external chip select signal XCS This signal is active only when the ECS signal described above is not active and when the system is addressing the external address space Accesses to unimplemented locations within the For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 register space or to locations that are removed from the map i e Ports A and B in Expanded modes will not cause this signal to become active When the EMK bit is clear this pin is used for general purpose I O 11 4 3 Memory Expansion The HCS12 Core architecture limits the physical address space available to 64K byt
248. R 40 X POSITION OF POINT _1 ADDR 1 DO X POSITION OF POINT_2 ADDR 2 08 SLOPE_1 FF X POS OF SATURATION POINT_1 ADDR 3 04 SLOPE_2 FF POINT_2 X POS OF SATURATION Figure B 4 Defining a Normal Membership Function A close examination of the MEM instruction algorithm shows how such membership functions are evaluated Figure B 5 is a complete flow diagram for the execution of a MEM instruction Each rectangular box represents one CPU bus cycle The number in the upper left corner corresponds to the cycle number and the letter corresponds to the cycle type refer to Appendix A Instruction Set and For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc Commands for details The upper portion of the box includes information about bus activity if any during this cycle The lower portion of the box which is separated by a dashed line includes information about internal CPU processes It is common for several internal functions to take place during a single CPU cycle In cycle 3 for example two 8 bit subtractions take place and a flag is set based on the results START Read word 0 X point_1 and point_2 Read word 0 X slope_1 and slope 2 Yo Y Y Yo 1 X X 2 No bus access 3a delta _1 ACCA point_1 3b delta _2 point_2 ACCA 3c If delta _1 or delta_2 lt O then flag_d12n 1 else flag_d12n 0 If misaligned then read progr
249. S LBCS Relative Long branch if carry set same as LBLO LBEQ Relative Long branch if equal if Z 1 LBGE Relative Long branch if greater than or equal to zero LBGT Relative Long branch if greater than zero LBHI Relative Long branch if higher LBHS Relative Long branch if higher or same same as LBCC LBLE Relative Long branch if less than or equal to zero LBLO Relative Long branch if lower same as LBCS LBLS Relative Long branch if lower or same LBLT Relative Long branch if less than zero LBMI Relative Long branch if minus LBNE Relative Long branch if not equal to zero LBPL Relative Long branch if plus LBRA Relative Long branch always LBRN Relative Long branch never LBVC Relative Long branch if overflow clear LBVS Relative Long branch if overflow set LEAS Indexed Load stack pointer with effective address LEAX Indexed Load X index register with effective address LEAY Indexed Load Y index register with effective address MAXA Indexed Maximum of two unsigned 8 bit values MAXM Indexed Maximum of two unsigned 8 bit values MEM Special Determine grade of fuzzy membership MINA Indexed Minimum of two unsigned 8 bit values MINM Indexed Minimum of two unsigned 8 bit values MOVB Combinations of immediate Move byte from one memory location to another MOVW extended and indexed Move word from one memory location to another ORCC Immediate OR CCR with mask replaces SEC SEI and SEV PSHC Inherent Push CCR onto stack PSHD Inherent Push double accumulat
250. SP 2 gt SP Msp Msp 1 gt X y XL SP 4 gt 8P Msp Msp 1 gt PCHy PCL SP 2 gt SP Msp Msp 1 gt YH YL SP 4 gt SP pending 76hh11 66 xb 66xb ff 66xbee ff 66 xb 66xbee ff 46 56 rPwO rPw rPwO frPwP fIfrPw fIPrPw O O uUnfPPP uUUUUPPP or uUUUUfVfPPP RTS Return from subroutine Msp Msp41 gt PCp PCL SP 2 SP SBCA opr8i SBCA opr8a SBCA opr16a SBCA oprx0_xysppc SBCA oprx9 xysppc SBCA oprx16 xysppc SBCA D xysppc SBCA oprx16 xysppc Subtract B from A A B A Subtract with carry from A A M C gt A or A imm C gt A IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 8211 92 dd B2hh11 A2xb A2xb ff A2 xbee ff A2 xb A2 xbee ff P rPf rPO rPf EPO frPP fIfrPf fIPrPf For More Information On This Product Go to www freescale com Freescale Semiconductor ME Guide E 12CPU15UG V1 2 Source Form Operation ete c ona iex Access Detail SXHINZVC SBCB opr8i Subtract with carry from B C2 ii P SBCB opr8a B M C B D2 d
251. SP twice To illustrate consider the operation of a PULX instruction With the next available M68HC11 stack if the SP 01F0 when execution begins the sequence of operations is SP SP 1 load X from 01F1 01F2 SP SP 1 and the SP ends up at 01F2 With the last used HCS12 stack if the SP 01F0 when execution begins the sequence is load X from 01F0 01F1 SP SP 2 and the SP again ends up at 01F2 The second sequence requires one less stack pointer adjustment The stack pointer change also affects operation of the TSX and TXS instructions In the M68HC11 TSX increments the SP by one during the transfer This adjustment causes the X index to point to the last stack location used The TXS instruction operates similarly except that it decrements the SP by one during the transfer HCS12 TSX and TXS instructions are ordinary transfers the HCS12 stack requires no adjustment For ordinary use of the stack such as pushes pulls and even manipulations involving TSX and TXS there are no differences in the way the M68HC11 and the HCS12 stacks look to a programmer However the stack change can affect a program algorithm in two subtle ways The LDS xxxx instruction is normally used to initialize the stack pointer at the start of a program In the M68HC11 the address specified in the LDS instruction is the first stack location used In the HCS12 however the first stack location used is one address lower than the address specified
252. STD D xysppc D IDX 6cC xb PI W STD oprx16 xysppc IDX2 6Cxbee ff PIPW STOP Stop processing SP 2 SP INH 18 3E oosssssf enter a ez pa re ge a RTNy RTN_ gt Mgp Mgp 4 stop mode SP 2 gt 8P Yy Y_ gt Mgp Mgp 4 paca exit stop SP 2 gt SP Xy X_ gt Mgp Mgp 1 mode y SP 2 gt 8P B A Mgp Mgp 4 ote stop SP 1 gt SP CCR gt Mgp 00 if stop mode Stop all clocks disabled by S 1 STS opr8a Store SP DIR 5F dd PW Ja a o STS opr16a SPy SP gt M M 1 EXT 7Fhh11 PWO STS oprx0_xysppc IDX 6F xb PW STS oprx9 xysppc IDX1 6F xb ff PWO STS oprx16 xysppc IDX2 6F xbee ff PWP STS D xysppc D IDX 6F xb PIFW STS oprx16 xysppc IDX2 6F xbee ff PIPW STX opr8a Store X DIR 5E dd PW JaJa o STX opr16a Xy X_ M M 1 EXT JE hh 11 PWO STX oprx0_xysppc IDX 6E xb PW STX oprx9 xysppc IDX1 6E xb ff PWO STX oprx16 xysppc IDX2 6Exbee ff PWP STX D xysppc D IDX 6Exb PIFW STX oprx16 xysppc IDX2 6Exbee ff PIPW For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 R Address Machine Source Form Operation Mode Coding Hex STY opr8a Store Y 5D dd STY opr16a YH Y M M 1 7Dhh11 STY oprx0_xysppc 6D xb STY oprx9 xysppc 6D xb ff STY oprx16 xysppc 6Dxbee ff STY D xysppc 6D xb STY oprx16 xysppc 6Dxbee ff SUBA opr8i Subtractfrom A 80ii P SUBA opr8a A M gt A 90 dd rPf SUBA opr16a or A imm gt A
253. Table 4 27 Table 4 27 Load Effective Address Instructions Mnemonic Function Operation LEAS Load effective address into SP e nA 5 ea LEAX Load effective address into X n x S S O ny D x LEAY Load effective address into Y a ES oe ee 4 3 23 Condition Code Instructions A summary of the condition code instructions is given in Table 4 28 Table 4 28 Condition Code Instructions Mnemonic Function Operation ANDCC Logical AND CCR with immediate value CCR imm CCR CLC Clear C bit 0 gt C CLI Clear bit 0 gt l CLV Clear V bit 0 gt V ORCC Logical OR CCR with immediate value CCR imm CCR PSHC Push CCR onto stack SP 0001 SP CCR Msp PULC Pull CCR from stack Msp CCR SP 0001 SP SEC Set C bit 1C SEI Set bit t SEV Set V bit 1 gt V TAP Transfer A to CCR A CCR TPA Transfer CCR to A CCR gt A For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 4 3 24 STOP and WAI Instructions The STOP and WAI instructions put the MCU in a standby state to reduce power consumption The STOP instruction stacks a return address and the values in the CPU registers then stops all system clocks halting program execution A reset or an external interrupt request recovers the stacked values and restarts the system clocks and program execution resumes The WAI instruction stacks a return ad
254. Timing Preliminary Targets Characteristic 2 Frequency of operation E clock Cycle time Pulse width E low Pulse width E high 31RG IVIS read data set up time Registers 31RM IVIS read data set up time RAM IVIS read data set up time SIEE EEPROM 31FL IVIS read data set up time FLASH 6 0 0 ns For More Information On This Product Go to www freescale com Core User Guide si2cPu RR Scale Semiconductor Inc Table 7 3 Expansion Bus Timing Preliminary Targets Num Characteristic 1 2 3 Symbol 16 MHz 20 MHz 25 MHz Unit IVIS read data hold time all NOTES 1 Crystal input is required to be within 45 to 55 duty 2 Reduced drive must be off to meet these timings 3 Unequal loading of pins will affect relative timing numbers 4 Affected by clock stretch add N x teye where N 0 1 2 or 3 depending on the number of clock stretches 5 Timing is tighter than other memories due to larger array size 7 3 5 Detecting Access Type from External Signals The external signals LSTRB R W and AO indicate the type of bus access that is taking place Accesses to the internal RAM are the only type of access that would produce LSTRB A0 1 because the internal RAM is specifically designed to allow misaligned 16 bit accesses in a single cycle In these cases the data for the address that was accessed is on the low half of the data bus and the data for address 1 is on the high half of th
255. V HSY gusv VYSV gHSd 039 usr usd 24love 23 Za Ot g o ZL Zip 44 9 9 AGL vlz elle elp tip 0 o e xal alz idje Wie xaz alz aja wie xaz ali Hit He Hfz Wie xge xa G aval aval aval aval wor val wal oval YOU HOH g HOH veOy VHSd ANd ysr dwr O e 94 DAE 9A 99 e 9g 9 v WWE 96 98 yv 94 9 99 99 Orie Ele oz ote 90 Pr e Xab diz idj e Wie X3ailvz diz gaje wie xaje aji Hit Hit Hje Were djre a 4 aug aua aua aua vug vLIg VLId vLIg 704 104 10H VION AHSd sog usr dnr Q S4 9 pe Gale sa soje Salove sv e 36 sg Y G e sg 1 sg Griz SE l e S2 Z S p SL 9pv e SO he e xXdire alz idje Wie xat alz ajz Wie xaz alt Hit Hit Hz We wie Ww Li gaNY dGNV SONV ANY VONV VONV VONV VONV ys1 HST g8s1 VYST XHSd 29989 2040 doo e t4 ve vale va pole valgv e tve 6 pg yv ple vt pg pric vele pelt vile vo e xal alza laje wie xaz alz iaje wie xaz alt Hit Hit Hi Tet HIE HI aaay aaay adav adav aans aans aans aans 930 930 goad Yo3a ama Sa IMAZ aga e e4 9pecale edlz o e glgveeve se e z 8b ez e e9 e s l Erle elie zjg l l 0 e xaipvz alz aja wie xat alz ajz wije xaz ali Hije Hit ae Tt alt HI ggs aoas ayas ayas voas voas voas voas ONI ONI g0NI Y NI VINd Hg NIN ANI e Z4 9 ve z3 za ZD Zal9v e zy e z6 28 Z4 9 Z9 ZS zZz z3elle zz Z Z0 e xal alz aja wie xaz alz ajz wije xaz ali Hit at
256. X X remainder D IDIV 16 by 16 integer divide unsigned D X X remainder D IDIVS 16 by 16 integer divide signed D X X remainder D 4 3 11 Bit Test and Bit Manipulation Instructions These operations use a mask value to test or change the value of individual bits in an accumulator or in memory BITA and BITB provide a convenient means of testing bits without altering the value of either operand A summary of the bit test and bit manipulation instructions is given in Table 4 13 Table 4 13 Bit Test and Bit Manipulation Instructions Mnemonic Function Operation BCLR Clear bit s in memory M e mask byte M BITA Bit test A A e M BITB Bit test B B e M BSET Set bits in memory M mask byte M For More Information On This Product Go to www freescale com 12CPU15UG V1 2 Core User Guide si2cru Rf Scale Semiconductor Inc 4 3 12 Shift and Rotate Instructions There are shifts and rotates for accumulators and memory bytes For multiple byte operations all shifts and rotates pass the shifted out bit through the carry bit C Because logical and arithmetic left shifts are identical there are no separate logical left shift operations LSL mnemonics are assembled as ASL operations A summary of the shift and rotate instructions is given in Table 4 14 Table 4 14 Shift and Rotate Instructions
257. X111 B7 27 00 or FF CCR SP For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 STAA Store Accumulator A STAA Operation A gt M Stores the value in A in M The value in A does not change CCR Effects S XH I N ZV C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Code and CPU Source Form Code Hex CPU Cycles Cycles STAA opr8a 5A dd Pw STAA opr16a 7A hh 11 PwO STAA oprx0_xysppc 6A xb Pw STAA oprx9 xysppc 6A xb ff PwO STAA oprx16 xysppc 6A xb ee ff PwP STAA D xysppc 6A xb PIfw STAA oprx16 xysppc 6A xb ee ff PIPw For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc STAB Store Accumulator B STAB Operation B gt M Stores the value in B in M The value in B does not change CCR Effects S XH I N ZV C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Code and CPU Source Form Code Hex CPU Cycles Cycles STAB opr8a 5B dd Pw STAB opr16a 78 hh 11 PwO STAB oprx0_xysppc 6B xb Pw STAB oprx9 xysppc 6B xb ff PwO STAB oprx16 xysppc 6B xb ee ff PwP STAB D xysppc 6B xb Plfw STAB oprx16 xysppc 6B xb ee ff PIPw For More Information On This Product Go to www freescale com STD Operation CCR Effects Code and CPU Cycles Fr
258. Y to SP Y SP EXG Exchange registers A B CCR D X Y or SP gt A B CCR D X Y or SP XGDX Exchange D with X D e X XGDY Exchange D with Y D e Y SEX Sign extend 8 bit operand 00 A B or CCR or FF A B or CCR D X Y or SP 4 3 3 Move Instructions These instructions move bytes or words from a source in memory M or M Mj 1 to a destination in memory M or M gt M 1 Six combinations of immediate extended and indexed addressing can specify source and destination addresses IMM EXT IMM IDX EXT EXT EXT IDX IDX EXT and IDX IDX A summary of the move instructions is given in Table 4 5 Table 4 5 Move Instructions Mnemonic Function Operation MOVB Move byte 8 bit My M2 MOVW Move word 16 bit M1 M 1 gt M gt M 1 For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 4 3 4 Add and Subtract Instructions Signed and unsigned 8 bit and 16 bit addition and subtraction can be performed on CPU registers on a CPU register and memory or on a CPU register and an immediate value Special instructions support index calculation Instructions that add or subtract the carry bit C in the CCR facilitate multiple precision computation A summary of the add and subtract instructions is given in Table 4 6 Table 4 6 Add and Subtract Instructions Mnemonic Function Operation ABA Add A to
259. Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V Cleared Machine Source Form Code Hex CPU Cycles LDD opr16i CC jj kk LDD opr8a DC dd LDD opr16a FC hh 11 LDD oprx0_xysppc EC xb LDD oprx9 xysppc EC xb ff LDD oprx16 xysppc EC xb ee ff LDD D xysppc EC xb LDD oprx16 xysppc EC xb ee ff For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc LDS Operation CCR Effects Code and CPU Cycles Load SP L DS M M 1 SP or imm gt SP Loads the high byte of SP with the value in M and the low byte with the value in M 1 or loads SP with an immediate value S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V Cleared Machine Source Form Code Hex CPU Cycles LDS opr16i CF jj kk LDS opr8a DF dd LDS opr16a FF hh 11 LDS oprx0_xysppc EF xb LDS oprx9 xysppc EF xb ff LDS oprx16 xysppc EF xb ee ff LDS D xysppc EF xb LDS oprx16 xysppc EF xb ee ff For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 LDX Load x LDX Operation CCR Effects Code and CPU Cycles M M 1 gt X or imm gt X Loads the high byte of X with value in M and low byte with the value in M 1 or loads X with an immediate value S X H I N Z V C
260. _rdb_L12 data0 X data1 K data2 Xdata3 core_MSEL_t2 A A nn ER A Cee core_rw_t2 a S A RC AA core_sz8_t 2 16 BIT 16 BIT 16 BIT peri_clk34 Figure 7 5 Basic 16 bit Memory Read Timing 7 3 1 3 Internal Core Register Reads The timing for basic 8 bit and 16 bit reads of internal Core registers are shown in Figure 7 6 and Figure 7 7 respectively For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 peri_clk24 TAT TATTA UV V AV VA V ey he core_ab_t2 addr0 adari rdb_t4 data0 N data1 y data2 K data3 core _RSEL_t4 S ey S AAA OS core_rw_t2 eS AS E CS S Co AS core_sz8_t2 wo Oye E CS A Figure 7 6 Basic 8 bit Core Register Read Timing peri_clk24 LTA TS TAD TA S7 V V VYA Ae V AAVA core_ab t2 addrOX adar1 rdb_t4 datad Y data1 K data2 XK data3 core RSEL t4 core wt ll J Il f f core sz8 O A NS Aa S Figure 7 7 Basic 16 bit Core Register Read Timing 7 3 2 Write Operations All write data exits the Core via the Core write data bus core_wdb_t4 15 0 The subsections below briefly discuss each of peripheral on chip memory register and array element and internal core register writes In each of the figures used in these subsections the write sequences are separated by read sequences to better illustrate the timing edges 7 3 2
261. al peripheral select to be decoded by the Motorola I P Bus when the Core is addressing a portion of the peripheral register map space All bus related data flow and multiplexing for the Core is handled within the MMC as well Finally the MMC contains logic to determine the state of system security 11 1 1 Features e Registers for mapping of address space for on chip RAM EEPROM and Flash EEPROM or ROM memory blocks and associated registers Memory mapping control and selection based upon address decode and system operating mode e Core Address Bus control e Core Data Bus control and multiplexing e Core Security state decoding Emulation Chip Select signal generation ECS External Chip Select signal generation XCS Internal memory expansion e Miscellaneous system control functions via the MISC register e Reserved registers for test purposes e Configurable system memory options defined at integration of Core into the System on a Chip SOC For More Information On This Product Go to www freescale com Core User Guide 11 1 2 Block Diagram The block diagram of the MMC is shown in Figure 11 1 below siocpuiataRscale Semiconductor Inc secure gt bdm_unsecure p Stop Wait gt Read amp Write Enables Bien Clocks Reset gt Mode Information EBI Alternate Address bus MMC SECURITY A ADDRESS DECODE REGISTERS INTERNAL MEMORY EXPANSION Eje EBI
262. alic characters is literal information which must appear in the assembly source file exactly as shown The initial 3 to 5 letter mnemonic is always a literal expression All commas pound signs parentheses square brackets or plus signs minus signs and the register designation A B D are literal characters The groups of italic characters shown in Table 5 3 represent variable information to be supplied by the programmer These groups can include any alphanumeric character or the underscore character but cannot include a space or comma For example the groups xysppc and oprx0_xysppc are both valid but the two groups oprx0 xysppc are not valid because there is a space between them Table 5 3 Source Form Notation abc Register designator for A B or CCR ad Register designator for Borb abdxysp Register designator for A B D X Y or SP Some assemblers require the symbol before the mask value 8 bit immediate value 16 bit immediate value 8 bit address value used with direct address mode opr16a 16 bit address value oprx0_xysp Indexed addressing postbyte code oprx3 xysp Predecrement X Y or SP by 1 8 oprx3 xysp Preincrement X Y or SP by 1 8 oprx3 xysp Postdecrement X Y or SP by 1 8 oprx3 xysp Postincrement X Y or SP by 1 8 oprx5 xysppc 5 bit constant offset from X Y SP or PC abd xysppc Accumulator A B or D offset from X Y SP or PC
263. am word to fill instruction queue else no bus access grade_1 slope_1 x delta_1 grade_2 slope_2 x delta_2 4a If slope_2 0 or grade_2 gt FF and flag_d12n 0 then member_init FF else member_init grade_2 4b If slope_1 0 or grade_1 gt FF and flag_d12n 0 then membership member_init else membership grade_1 If flag_d12n 1 then write 00 0 Yo else write membership 0 Y9 fuzzy input result grade Figure B 5 MEM Instruction Flow Diagram Consider 4a If slope_2 0 or grade_2 gt FF and flag_d12n 0 The flag_d12n is zero as long as the input value in accumulator A is within the trapezoid Everywhere outside the trapezoid one or the other delta term is negative and the flag equals one Slope_2 equals zero indicates the right side of the trapezoid has infinite slope so the resulting grade should be FF everywhere in the trapezoid including at point_2 as far as this side is concerned The term grade_2 greater than FF means the value is far enough into the trapezoid that the right sloping side of the trapezoid has crossed above the FF cutoff level and the resulting grade should be FF as far as the right sloping side is concerned 4a decides if the value is left of the right sloping side grade FF or on the sloping portion of the right side of the trapezoid grade grade_2 4b could still override this tentative value in grade In 4b slope_1 is zero if the left side
264. an external tester system PA7 A15 D15 D7 High order bidirectional data lines multiplexed during ECLK high in expanded thru D15 D8 wide modes peripheral mode amp visible internal accesses IVIS 1 in emulation PAO A8 D8 DO expanded narrow mode Direction of data transfer is generally indicated by R W D15 D7 thru Alternate high order and low order bytes of the bidirectional data lines D8 DO multiplexed during ECLK high in expanded narrow modes and narrow accesses in wide modes Direction of data transfer is generally indicated by R W PB7 PBO General purpose I O pins see PORTB and DDRB registers A7 AO Low order address lines multiplexed during ECLK low Outputs except in special PB7 A7 D7 peripheral mode where they are inputs from an external tester system thru PBO AO DO Low order bidirectional data lines multiplexed during ECLK high in expanded wide modes peripheral mode amp visible internal accesses with IVIS 1 in D7 DO i S emulation expanded narrow mode Direction of data transfer is generally indicated by RAW PE7 General purpose I O pin see PORTE and DDRE registers PE7 NOACC NOACC CPU No Access output Indicates whether the current cycle is a free cycle Only available in expanded modes At the rising edge of RESET the state of this pin is registered into the MODB bit MODB to set the mode PE6 IPIPE1 PE6 General purpose I O pin see PORTE and DDRE registers MODB CLKTO IPIPE1 Instruction pipe status bit 1 enabled by PI
265. an interrupt is Rotate right M Dl bO Rotate right A Rotate right B Return from call Msp PPAGE SP 1 SP Msp Msp 1 gt PCH PCL SP 2 gt SP Return from interrupt Msp CCR SP 1 SP Msp Msp 1 gt B A SP 2 gt SP Msp Msp 1 gt X y XL SP 4 gt 8P Msp Msp 1 gt PCHy PCL SP 2 gt SP Msp Msp 1 gt YH YL SP 4 gt SP pending 76hh11 66 xb 66xb ff 66xbee ff 66 xb 66xbee ff 46 56 rPwO rPw rPwO frPwP fIfrPw fIPrPw O O uUnfPPP uUUUUPPP or uUUUUfVfPPP RTS Return from subroutine Msp Msp41 gt PCp PCL SP 2 SP SBCA opr8i SBCA opr8a SBCA opr16a SBCA oprx0_xysppc SBCA oprx9 xysppc SBCA oprx16 xysppc SBCA D xysppc SBCA oprx16 xysppc Subtract B from A A B gt A Subtract with carry from A A M C gt A or A imm C gt A IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 8211 92 dd B2hh11 A2xb A2xb ff A2 xbee ff A2 xb A2 xbee ff P rPf rPO rPf EPO frPP fIfrPf fIPrPf For More Information On This Product Go to www freescale com Core User Guide siocpuimtaRscale Semiconductor Inc
266. an the denominator In the case of overflow denominator is less than or equal to the numerator or division by 0 the quotient is set to FFFF and the remainder is indeterminate FDIV is equivalent to multiplying the numerator by 21 and then performing 32 x 16 bit integer division The result is interpreted as a binary weighted fraction which resulted from the division of a 16 bit integer by a larger 16 bit integer A result of 0001 corresponds to 0 000015 and FFFF corresponds to 0 9998 The remainder of an IDIV instruction can be resolved into a binary weighted fraction by an FDIV instruction The remainder of an FDIV instruction can be resolved into the next 16 bits of binary weighted fraction by another FDIV instruction S X H I N Z V C 4 4 4 Z Set if quotient is 0000 cleared otherwise V Set if the denominator X is less than or equal to the numerator D cleared otherwise C X15 e X14 e X13 e X12 e X3 o X2 0 X1 e X0 set if denominator is 0000 cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles FDIV INH 18 11 OffffffffffO For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 B EQ Increment and Branch if Equal to Zero B EQ Operation CCR Effects Code and CPU Cycles counter 1 counter If counter 0 then PC 0003 rel PC Adds one to the counter register A
267. anch if higher or same R M C 0 Unsigned LBLO Long branch if lower R lt M Z 1 LBLS Long branch if lower or same R lt M C Z 1 LBGE Long branch if greater than or equal R gt M Nev 0 LBGT Sianed Long branch if greater than R gt M Z N V 0 igne LBLE J Long branch if less than or equal R lt M Z N V 1 LBLT Long branch if less than R lt M N V 1 4 3 17 3 Bit Condition Branch Instructions Bit condition branches are taken when bits in a memory byte are in a specific state A mask operand is used to test the location If all bits in that location that correspond to ones in the mask are set BRSET or cleared BRCLR the branch is taken The numeric range of 8 bit offset values is 80 128 to 7F 127 from the address of the next memory location after the offset value A summary of the bit condition branch instructions is given in Table 4 21 Table 4 21 Bit Condition Branch Instructions Mnemonic Function Condition Equation BRCLR Branch if selected bits clear M e mm 0 BRSET Branch if selected bits set M mm 0 For More Information On This Product Go to www freescale com Core User Guide si2cru ERA Scale Semiconductor Inc 4 3 17 4 Loop Primitive Instructions Loop primitive instructions test a counter value in a CPU register A B D X Y or SP for a zero or nonzero value as a branch condition There are predecrement preincrement and test only versions of these instructions
268. and siocpuintaRscale Semiconductor Inc Memory Notation Table A 2 Register and Memory Notation Aora An Borb Accumulator A Bit n of accumulator A Accumulator B Bit n of accumulator B Accumulator D Bit n of accumulator D Index register X High byte of index register X Low byte of index register X Bit n of index register X Index register Y High byte of index register Y Low byte of index register Y Bit n of index register Y Stack pointer Bit n of stack pointer Program counter PCL CCRorc High byte of program counter Low byte of program counter Condition code register M Address of 8 bit memory location Mn Rn Bit n of byte at memory location M Bit n of the result of an arithmetic or logical operation In Bit n of the intermediate result of an arithmetic or logical operation RTNy RTN High byte of return address Low byte of return address Contents of For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 A 2 3 Address Mode Notation Table A 3 Address Mode Notation INH Inherent no operands in instruction stream IMM Immediate operand immediate value in instruction stream DIR Direct operand is lower byte of address from 0000 to 00FF EXT Operand is a 16 bit address Two s complement relative offset for branch instructions IDX Indexed no extensi
269. and positions it for sequential execution one instruction at a time The relationship between bus cycles and execution cycles is straightforward and facilitates tracking and debugging There are three 16 bit stages in the instruction queue Instructions enter the queue at stage1 and roll out after stage 3 Each byte in the queue is selectable An opcode prediction algorithm determines the location of the next opcode in the instruction queue Each instruction refills the queue by fetching the same number of bytes that the instruction uses Program information is fetched in aligned 16 bit words Each program fetch indicates that two bytes need to be replaced in the instruction queue Each optional fetch indicates that only one byte needs to be replaced For example an instruction composed of five bytes does two program fetches and one optional fetch If the first byte of the five byte instruction was even aligned the optional fetch is converted into a free cycle If the first byte was odd aligned the optional fetch is executed as a program fetch Two external pins IPIPE 1 0 provide time multiplexed information about instruction execution and data movement in the queue Decoding and using the IPIPE signals is discussed in 5 2 Execution Sequence All queue operations are defined by two basic queue movement cycles Queue movement cycles are only one factor in instruction execution time and should not be confused with bus cycles 5 2 1 No Movemen
270. and the high bit on IPIPE1 Data movement information is available when E clock is high or on falling edges of the E clock execution start information is available when E clock is low or on rising edges of the E clock as shown in Figure 5 1 Data movement information refers to data on the For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 bus Execution start information is delayed one bus cycle to guarantee the indicated opcode is in stage three Table 5 9 summarizes the information encoded on the IPIPE 1 0 pins CPU CLOCK T4 T2 T4 T2 T4 T2 E CLOCK EX DM EX DM EX DM PIPE 0 00 o X10 Xo X X n NONE ALD 4 SEV NONE soD c ALD DATA 15 0 PROGRAM DATA OPERAND OR FREE CYCLE PROGRAM DATA STAGE ONE O ALD Advance and load data lt SEV Start even instruction E SOD Start odd instruction a Figure 5 1 Queue Status Signal Timing Data movement status is valid when the E clock is high and is represented by two states No movement There is no data shifting in the queue e Advance and load from data bus The queue shifts up one stage with stage one being filled with the data on the read data bus Execution start status is valid when the E clock is low and is represented by four states e No start Execution of the current instruction continues e Start interrupt An interrupt sequence has begun NOTE The start interrupt state is ind
271. ary A brief summary of the Core interface signals is given in Table 7 1 below For detailed descriptions and timing information please consult the HCS12 V1 5 Core Integration Guide Signal Name Type Table 7 1 Core Interface Signal Definitions Functional Description core_ab_t2 19 0 Internal Bus Interface Signals Core 16 bit Address Bus 19 0 peri_rdb_L12 15 0 16 bit Read Data Bus data from Peripheral block ram_rdb_L12 15 0 ee_rdb_L12 15 0 16 bit Read Data Bus data 16 bit Read Data Bus data from on chip RAM array from on chip EEPROM array fee_rdb_L12 15 0 16 bit Read Data Bus data array from on chip Flash EEPROM or ROM core_wdb_t4 15 0 core_rw_t2 O Core Read Write signal a Core 16 bit Write Data Bus 15 0 ctive low Write For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Table 7 1 Core Interface Signal Definitions Signal Name Type Functional Description Core bus data size requested signal core_sz8 t2 0 16 bit access 1 8 bit access core_exp_t2 Expanded Mode selected signal core_per_t2 Peripheral Test Mode selected signal core_smod_t2 core_secure_t2 Special Mode selected signal Core secure mode signal core_perisel_t2 Core peripheral select to I P Bus Interface core_ramregsel_t2 core_ramarraysel_t2 On chip RAM Register select from Core to memory and
272. ase of indexed with offset greater than 15 HCS12 and M68HC11 object code are the same size The relative size of code for M68HC11 vs code for HCS12 has also been tested by rewriting several smaller programs from scratch In these cases the HCS12 code is typically about 30 smaller These savings are mostly due to improved indexed addressing A C program compiled for the HCS 12 is about 30 smaller than the same program compiled for the M68HC11 The savings are largely due to better indexing C 3 Programmer s Model and Stacking The HCS12 programming model and stacking order are identical to those of the M68HC11 C 4 True 16 Bit Architecture The M68HC11 is a direct descendant of the M6800 one of the first microprocessors which was introduced in 1974 The M6800 was strictly an 8 bit machine with 8 bit data buses and 8 bit instructions As Motorola devices evolved from the M6800 to the M68HC11 a number of 16 bit instructions were added but the data buses remained eight bits wide so these instructions were performed as sequences of 8 bit operations The HCS12 is a true 16 bit implementation but it retains the ability to work with the mostly 8 bit M68HC11 instruction set The larger ALU of the HCS12 is used to calculate 16 bit pointers and to speed up math operations C 4 1 Bus Structures The HCS12 is a 16 bit processor with 16 bit data paths Typical HCS12 devices have internal and external 16 bit data paths but some derivatives inc
273. ated pin Port E bit 3 is a general purpose I O pin This bit has no effect in single chip peripheral or normal expanded narrow modes NOTE LSTRBis used during external writes After reset in normal expanded mode LSTRB is disabled to provide an extra I O pin If LSTRB is needed it should be enabled before any external writes External reads do not normally need LSTRB because all 16 data bits can be driven even if the system only needs 8 bits of data RDWE Read Write Enable Normal write once For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Emulation write never Special write anytime 1 The associated pin Port E bit 2 is configured as the R W pin 0 The associated pin Port E bit 2 is a general purpose I O pin This bit has no effect in single chip or peripheral modes NOTE RAW is used for external writes After reset in normal expanded mode R W is disabled to provide an extra I O pin If R is needed it should be enabled before any external writes 12 3 8 MODE Register MODE Address Base B BIT 7 6 5 4 3 2 1 BIT O Read 0 0 MODC MODB MODA IVIS EMK EME Write Reset 0 0 0 0 0 0 0 0 Special esai Single chip 4 Emulation Reset 0 0 1 0 1 0 1 1 Exp Nar Special Reset 0 1 0 0 1 0 0 0 Test Emulation Reset 0 1 1 0 1 0 1 1 Exp Wide Normal Reset 1 0 0 0 0 0 0 0 Single Chip Reset 1 0 1 0 0
274. ation CPS Compare SP to memory SP M M 1 DES Decrement SP SP 0001 SP INS Increment SP SP 0001 SP LDS Load SP M M 1 gt SP LEAS Stack pointer Load effective address into SP Effective address SP STS manipulation Store SP SP gt M M 1 TSX Transfer SP to X SP gt TSY Transfer SP to Y SP gt TXS Transfer X to SP X SP TYS Transfer Y to SP Y SP PSHA Push A SP 0001 SP A Msp PSHB Push B SP 0001 SP B Msp PSHC Push CCR SP 0001 SP CCR Msp PSHD Push D SP 0002 SP A B Mgp Mgp PSHX Push X SP 0002 SP X Mgp Mgp 4 PSHY A Push Y SP 0002 SP Y Mgp Mgp 4 4 Stack operation PULA Pull A Msp A SP 1 SP PULB Pull B Msp B SP 1 SP PULC Pull CCR Msp CCR SP 1 SP PULD Pull D Msp Mgp 1 A B SP 2 SP PULX Pull X Msp Mgp 4 X SP 2 gt SP PULY Pull Y Msp Mgp 1 Y SP 2 gt SP For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc 4 3 22 Load Effective Address Instructions Load effective address instructions add a constant or the value in an accumulator to the value in an index register the stack pointer or the program counter The constant can be a 5 8 or 16 bit value The accumulator can be A B or D A summary of the load effective address instructions is given in
275. ation The built in fuzzy instructions use 8 bit resolution and some systems may require finer resolution The rule evaluation instructions support only variations of MIN MAX rule evaluation Other methods have been discussed in fuzzy logic literature The weighted average of singletons is not the only defuzzification technique The HCS12 CPU has several instructions and addressing modes that can be helpful in developing custom fuzzy logic systems B 8 1 Fuzzification Variations The MEM instruction supports trapezoidal and several other membership functions including functions with vertical infinite slope sides Triangular membership functions are a subset of trapezoidal functions Some practitioners refer to s z and Tr shaped membership functions These refer to trapezoids butted against the right left or neither end of the x axis Many other membership function shapes are possible with sufficient memory space and processing bandwidth Tabular membership functions offer total flexibility in shape and very fast evaluation time However tables take as many as 256 bytes of memory space per system input label This makes them impractical for most microcontroller based fuzzy systems The HCS12 instruction set includes two instructions TBL and ETBL for lookup and interpolation of compressed tables The TBL instruction uses 8 bit table entries y values and returns an 8 bit result The ETBL instruction uses 16 bit table entries y values and re
276. ation On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc 14 5 2 Special Operation 14 5 2 1 Special single chip mode BDM is enabled and active immediately out of reset This allows programming a system with blank memory 14 5 2 2 Special peripheral mode BDM is enabled and active immediately out of reset BDM can be disabled by clearing the BDMACT bit in the BDM status BDMSTS register The BDM serial system should not be used in special peripheral mode 14 5 3 Emulation Modes In emulation modes the BDM operates as in all normal modes 14 6 Low Power Options 14 6 1 Run Mode The BDM does not include disable controls that would conserve power during run mode 14 6 2 Wait Mode The BDM cannot be used in wait mode if the system disables the clocks to the BDM 14 6 3 Stop Mode The BDM is completely shutdown in stop mode 14 7 Interrupt Operation The BDM does not generate interrupt requests 14 8 Motorola Internal Information This subsection details information about the BDM sub block that is for Motorola use only and should not be published in any form outside of Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 14 8 1 Registers This section gives detailed descriptions of all internally accessible registers and bits that are either not available or not disclosed to users external to Motorola These
277. ations include the carry bit to allow extension of shift and rotate operations to multiple bytes For example to shift a 24 bit value one bit to the right the sequence LSR HIGH ROR MID ROR LOW could be used where LOW MID and HIGH refer to the low middle and high bytes of the 24 bit value respectively CCR Effects S XH I N ZV C A A A A N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C NeC Ne C for N and C after the shift cleared otherwise C AO set if the LSB of A was set before the shift cleared otherwise Code and CPU CPU Cycles Cycles Source Form Mts Code Hex pom For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc RO R B Rotate Right B RO R B Operation pp 7 6 oa oa e2 or eoe B Shifts all bits of B one place to the right Bit 7 is loaded from the C bit The C bit is loaded from the least significant bit of B Rotate operations include the carry bit to allow extension of shift and rotate operations to multiple bytes For example to shift a 24 bit value one bit to the right the sequence LSR HIGH ROR MID ROR LOW could be used where LOW MID and HIGH refer to the low middle and high bytes of the 24 bit value respectively CCR Effects S XH I N ZV C A A A A N Set if MSB of result is set cleared othe
278. bit so it is suitable for use in BCD arithmetic operations see DAA instruction for additional information CCR Effects S X H I E A A A H A3 M3 M3 e R3 R3 e A3 set if there is a carry from bit 3 cleared otherwise N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V A7 e M7 e R7 A7 e M7 e R7 set if the operation produces a two s complement overflow cleared otherwise C A7 M7 M7 e R7 R7 e A7 set if there is a carry from the MSB of the result cleared otherwise Code and CPU Source Form pr rate code Hew CPU Cycles Cycles ADCA opr8i IMM 89 ii P ADCA opr8a DIR 99 dd rPf ADCA opr16a EXT B9 hh 11 rPo ADCA oprx0_xysppc IDX A9 xb rPf ADCA oprx9 xysppc IDX1 A9 xb ff rPO ADCA oprx16 xysppc IDX2 A9 xb ee ff frPP ADCA D xysppc D IDX A9 xb FIfrpf ADCA oprx16 xysppc IDX2 A9 xb ee ff IPrbf For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc ADCB Add with Carry to B ADCB Operation B M C gt B or B imm C gt B Adds either the value in M and the C bit or an immediate value and the C bit to the value in B Puts the result in B This instruction affects the H bit so it is suitable for use in BCD arithmetic operations see DAA instruction for additional information CCR Effects S X H I
279. ble pullup devices for all Port B input pins 0 Port B pullups are disabled PUPAE Pullup Port A Enable 1 Enable pullup devices for all Port A input pins 0 Port A pullups are disabled For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 12 3 10 Reduced Drive Register RDRIV Address Base D BIT 7 6 5 4 3 2 1 BIT O Read 0 0 0 0 RDPK RDPE RDPB RDPA Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 12 12 Reduced Drive Register RDRIV Read anytime provided this register is in the map Write anytime provided this register is in the map This register is used to select reduced drive for the pins associated with the core ports This gives reduced power consumption and reduced RFI with a slight increase in transition time depending on loading This feature would be used on ports which have a light loading The reduced drive function is independent of which function is being used on a particular port This register is not in the on chip map in emulation and peripheral modes RDPK Reduced Drive of Port K 1 All Port K output pins have reduced drive enabled 0 All Port K output pins have full drive enabled RDPE Reduced Drive of Port E 1 All Port E output pins have reduced drive enabled 0 All Port E output pins have full drive enabled RDPB Reduced Drive of Port B 1 All Port B output pins have reduced drive enabled
280. branches All branch instructions affect the queue similarly but there are differences in cycle counts between the various types Loop primitive instructions are a special type of branch instruction for implementing counter based loops For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 A branch instruction has two execution cases Either the branch condition is satisfied and a change of flow takes place or the condition is not satisfied and no change of flow occurs 5 3 3 1 Short Branches The branch not taken case for a short branch is simple Since the instruction consists of a single word containing both an opcode and an 8 bit offset the queue advances the CPU fetches another program word and execution continues with the next instruction The branch taken case for a short branch requires that the queue be refilled so that execution can begin at anew address First the CPU calculates the effective address of the destination using the relative offset in the instruction Then it loads the address into the program counter and performs three program word fetches at the new address to refill the queue 5 3 3 2 Long Branches The branch not taken case for a long branch requires three cycles while the branch taken case requires four cycles This is due to differences in the amount of program information needed to fill the queue A long branch instruction begins with a
281. broutines The BSR and JSR instructions are for accessing subroutines in the normal 64K byte address space The CALL instruction is for accessing subroutines in expanded memory BSR uses relative addressing mode to generate the effective address of the subroutine while JSR can use other addressing modes Both instructions calculate a return address stack the address then do three program word fetches to refill the queue A subroutine in the normal 64K byte address space ends with a return from subroutine instruction RTS RTS unstacks the return address and does three program word fetches from that address to refill the queue CALL is similar to JSR MCUs with expanded memory treat the 16K bytes of addresses from 8000 to BFFF as an expanded memory window An 8 bit PPAGE register switches the memory pages in the window CALL calculates and stacks a return address along with the current PPAGE value and writes a new instruction supplied value to PPAGE Then it calculates the subroutine address and fetches three program words from that address to refill the queue A subroutine in expanded memory ends with a return from call instruction RTC RTC unstacks the PPAGE value and the return address and does three program word fetches from that address to refill the queue 5 3 3 Branches A branch instruction changes the execution flow when a specific condition exists There are short conditional branches long conditional branches and bit condition
282. bus and the SP is pointing to external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory A U cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access The internal RAM is designed to allow single cycle misaligned word access 16 bit vector fetch Vectors are always aligned 16 bit words A v cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the program is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory 8 bit conditional read A t cycle is either a data read cycle or a free cycle depending on the data and flow of the REVW instruction A t cycle is stretched only when controlled by a chip select circuit programmed for slow memory 16 bit conditional read A T cycle is either a data read cycle or a free cycle depending on the data and flow of the REV or REVW instruction A T cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the corresponding data is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory A T cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cyc
283. by multiplying the minimum rule antecedent value 00 FF by the weight plus one 001 100 This method of weighting rules allows an 8 bit weighting factor to represent a value between zero and one inclusive The 8 bit A accumulator holds intermediate calculation results during execution of the REVW instruction During antecedent processing A starts out at FF and is replaced by any smaller fuzzy input that is referenced by a rule antecedent If the C bit is one rule weights are enabled and the rule truth value is multiplied by the rule weight just before consequent processing starts During consequent processing A holds the weighted or unweighted truth value for the rule This truth value is stored to any fuzzy output that is referenced by a rule consequent unless that fuzzy output is already larger MAX Before executing REVW initialize A with FF the largest 8 bit value because rule evaluation always starts with processing of the antecedents of the first rule For subsequent rules in the list A is automatically set to FF when the instruction detects the FFFE marker word between the last consequent of the previous rule and the first antecedent of a new rule For More Information On This Product Go to www freescale com Core User Guide si2cPu Rf Scale Semiconductor Inc Both the C and V bits must be initialized before starting a REVW instruction Once the REVW instruction starts the C bit remains constant and the value in th
284. by mode If the clock reference crystal also stops during low power mode crystal startup delay lengthens recovery time If XIRQ is asserted while the X mask bit 0 XIRQ interrupts enabled execution resumes with a vector fetch for the XIRQ interrupt If the X mask bit 1 XIRQ interrupts disabled a 2 cycle recovery sequence including an O cycle adjusts the instruction queue and execution continues with the next instruction after STOP S X H I N ZV C Address Machine Source Form Mode Code Hex CPU Cycles OOSSSSsf enter stop mode E fVfPPP exit stop mode rer dl pee f continue stop mode oo if stop mode disabled by S 1 For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG v1 2 STS Store SP STS Operation SPy SP gt M M 1 Stores the high byte of SP in M and the low byte in M 1 CCR Effects S XH I N ZV C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V Cleared Code and CPU Source Form Code Hex CPU Cycles Cycles STS opr8a oF dd STS opr16a 7F hh 11 STS oprx0_xysppc 6F xb STS oprx9 xysppc 6F xb ff STS oprx16 xysppc 6F xb ee ff STS D xysppc 6F xb STS oprx16 xysppc 6F xb ee ff For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc STX Store x STX Operation
285. byte of Y from the address to which SP points plus one Then increments SP by two Pull instructions are commonly used at the end of a subroutine to restore the contents of CPU registers that were pushed onto the stack before subroutine execution Address Machine Source Form Mode Code Hex CPU Cycles PULY INH 31 UfO For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 R EV Fuzzy Logic Rule Evaluation R EV Operation MIN MAX rule evaluation Performs an unweighted evaluation of a list of rules using fuzzy inputs to produce fuzzy outputs REV can be interrupted so it does not adversely affect interrupt latency REV uses an 8 bit unsigned offset from a base address stored in Y to determine the address of each fuzzy input and fuzzy output Each rule in the knowledge base must consist of a table of 8 bit antecedent offsets followed by a table of 8 bit consequent offsets The value FE marks boundaries between antecedents and consequents and between successive rules The value FF marks the end of the rule list REV begins with the address pointed to by the first rule antecedent and evaluates successive fuzzy input values until it finds an FE separator Operation is similar to that of a MINA instruction The smallest input value is the truth value of the rule Then beginning with the address pointed to by the first rule consequent REV compares the tr
286. c LBRN Long Branch Never LBRN Operation CCR Effects Code and CPU Cycles PC 0004 PC Never branches LBRN is effectively a 4 byte NOP that requires three cycles LBRN is included in the instruction set to provide a complement to the LBRA instruction LBRN is useful during program debug to negate the effect of another branch instruction without disturbing the offset byte A complement for LBRA is also useful in compiler implementations S X H I N ZV C Address Machine Source Form Mode Code Hex CPU Cycles LBRN rel16 REL 18 21 qq rr OPO Branch Complementary Branch F Comment Mnemonic Opcode Test Mnemonic Opcode Test LBRN 18 21 Never LBRA 18 20 Always Simple For More Information On This Product Go to www freescale com Operation CCR Effects Code and CPU Cycles Freescale Semiconductor WOE Guide 12CPU15UG V1 2 i B VC Long Branch if V Clear L B VC If V 0 then PC 0004 rel PC Tests the V bit and branches if V 0 LBVC causes a branch when a previous operation on two s complement binary values does not cause an overflow That is when LBVC follows a two s complement operation a branch occurs when the result of the operation is valid Rel is a 16 bit two s complement offset for branching forward or backward in memory Branching range is 8000 to 7FFF 32768 to 32767 from the address following the last byte of object
287. cally sets the X and I bits in the CCR to disable XIRQ and maskable interrupt requests during the XIRQ interrupt service routine An RTI instruction at the end of the interrupt service routine restores the cleared X bit to the CCR re enabling XIRQ interrupt requests 1 XIRQ interrupt requests disabled 0 XIRQ interrupt requests enabled H Half Carry Bit The H bit indicates a carry from bit 3 of the result during an addition operation The DAA instruction uses the value of the H bit to adjust the result in accumulator A to BCD format ABA ADD and ADC are the only instructions that update the H bit 1 Carry from bit 3 after ABA ADD or ADC instruction 0 No carry from bit 3 after ABA ADD or ADC instruction I Interrupt Mask Bit Clearing the I bit enables maskable interrupt sources Reset sets the I bit To enable maskable interrupt requests software must clear the I bit Maskable interrupt requests that occur while the I bit is set remain pending until the I bit is cleared When the I bit is clear and a maskable interrupt request occurs the CPU stacks the cleared I bit It then automatically sets the I bit in the CCR to prevent other maskable interrupt requests during the interrupt service routine An RTI instruction at the end of the interrupt service routine restores the cleared I bit to the CCR reenabling maskable interrupt requests The I bit can be cleared within the service routine but implementing a
288. ccessing memory MOVW 2 X 4 Y Using a predecrement increment version of LEAS LEAX or LEAY when SP X or Y is the respective indexing register changes the value in the indexing register Using a postdecrement increment version of LEAS LEAX LEAY when SP X or Y is the respective indexing register has no effect 4 2 7 7 Accumulator Offset Indexed Addressing This addressing mode calculates the effective address by adding the value in the indexing register to an unsigned offset value in one of the accumulators The value in the indexing register is not changed The indexing register can be X Y SP or PC and the accumulator can be A B or D Example LDAA B X This instruction adds B to X to form the address from which A will be loaded B and X are not changed by this instruction This example is similar to the following two instruction combination in an M68HC11 4 2 7 8 Accumulator D Indexed Indirect Addressing This addressing mode calculates address of a pointer to the effective address It adds the value in D to the value in the indexing register X Y SP or PC The value in the indexing register does not change The square brackets distinguish this addressing mode from D accumulator offset indexing In this example accumulator D indexed indirect addressing is used in a computed GOTO JMP D PC Gol DC W PLACE1 GO2 DC W PLACE2 GO3 DC W PLACE3 The values beginning at GO1 are addresses of potential destinat
289. ce the REV instruction is essentially a list processing instruction execution time is dependent on the number of elements in the rule list The REV instruction is interruptible typically within three bus cycles so 1t does not adversely affect worst case interrupt latency Since all intermediate results and instruction status are held in stacked CPU registers the interrupt service code can even include independent REV and REVW instructions For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 B 6 1 1 Initialization Prior to Executing REV Some CPU registers and memory locations need to be initialized before executing the REV instruction X and Y index registers are index pointers to the rule list and the fuzzy inputs and outputs The A accumulator holds intermediate calculation results and needs to be initially set to FF The V bit is an instruction status indicator showing whether antecedents or consequents are being processed Initially the V bit is cleared to indicate antecedents are being processed The fuzzy outputs in working RAM locations need to be cleared to 00 Improper initialization produces erroneous results The X index register is set to the address of the first element in the rule list in the knowledge base The REV instruction automatically updates this pointer so that the instruction can resume correctly if it is interrupted After the REV instruction finishes
290. ck for the Core peri_clk24 This clock input is one of the main clocks for the Core 8 3 1 6 System level clock for peripheral blocks peri_clk34 This clock input is the main clock source for all peripheral blocks integrated in the system and accessed by the Core through the I P Bus Interface 8 3 1 7 System ECLK clock peri_clk23 This clock input is the main clock source used by the Core to generate the system ECLK 8 3 1 8 Divided Down System Oscillator Clock peri_phase_oscdX This clock input to the Core is used within the Core by the Background Debug Mode sub block to keep the BDM synchronized For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc 8 3 1 9 System Test Clock enable peri_test_clk_enable This single bit input to the Core indicates that the phase locked loop PLL test clock should be output on the system Port E bit 6 pin when the PIPOE bit is zero 8 3 1 10 System Test Clock peri_test_clk This clock input to the Core is the PLL test clock 8 3 1 11 System clock source select signal peri_pllsel_t3 This single bit input to the Core indicates whether clocks within the system are derived from the crystal or PLL 8 3 1 12 ECLK load enable signal core_eclk_load This single bit output from the Core is the load enable signal for the system external clock ECLK 8 3 1 13 ECLK disable signal core_neclk_t2 This single bit output from the Core i
291. clock speed that is active during the data portion of the command will occur before the new clock source is guaranteed to be active The start of the next BDM command uses the new clock for timing subsequent BDM communications 1 BDM system operates with bus rate 0 BDM system operates with alternate clock WARNING The BDM will not operate with CLKSW 0 if the frequency of the alternate clock source peri_phase_oscdX is greater than one half of the bus frequency Please refer to the users guide for the clock generation module to determine if this condition can occur UNSEC Unsecure For More Information On This Product Go to www freescale com Core User Guide siocpuimtaRscale Semiconductor Inc This bit is only writable in special single chip mode from the BDM secure firmware and always gets reset to zero It is in a zero state as secure mode is entered so that the secure BDM firmware lookup table is enabled and put into the memory map along with the standard BDM firmware lookup table The secure BDM firmware lookup table verifies that the on chip EEPROM and Flash EEPROM are erased This being the case the UNSEC bit is set and the BDM program jumps to the start of the standard BDM firmware lookup table and the secure BDM firmware lookup table is turned off If the erase test fails the UNSEC bit will not be asserted 1 the system is in a unsecured mode 0 the system is in a secured mode WARNING When UNSEC is set
292. code in the instruction S X H I N ZV C Address Machine Source Form Mode Code Hex CPU Cycles LBVC rel16 18 28 qq rr OPPP branch OPO no branch Complementary Branch opcode Test mnemonic opcode Test No overflow Overflow Comment Mnemonic LBVC Simple For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc LBVS Long Branch if V Set LBVS Operation CCR Effects Code and CPU Cycles If V 1 then PC 0004 rel PC Tests the V bit and branches if V 1 LBVS causes a branch when a previous operation on two s complement values causes an overflow That is when LBVS follows a two s complement operation a branch occurs when the result of the operation is invalid Rel is a 16 bit two s complement offset for branching forward or backward in memory Branching range is 8000 to 7FFF 32768 to 32767 from the address following the last byte of object code in the instruction S X H I N Z V C Aaa aaa Address Machine Source Form Mode Code Hex CPU Cycles LBVS rel16 18 29 qq rr OPPP branch OPO no branch Complementary Branch opcode Test mnemonic opcode Test Overflow No overflow 7 Comment Mnemonic LBVS Simple For More Information On This Product Go to www freescale com Operation CCR Effects Code and CPU Cycles Freescale S
293. conductor WOE Guide 12CPU15UG V1 2 0032 PORTK initrg 4 0 mmc_ab_t2 15 11 amp ebi_emul_t2 8 4 0033 DDRK ebi_narrow_t2 8 ebi_emk_t2 All Others 0 Table 11 15 summarizes the different access types where the data is on the internal or external read data bus and where the CPU is expecting the data The source of the CPU s read data bus for external accesses is the ebi_extrdb and for internal accesses is the rdb_t2 IMS refers to the Internal Memory Select signal 1 Internal 0 External FMTS refers to the Fast Memory Transfer Select signal which asserts anytime an access is made to the RAM except for the last byte of the array Table 11 15 Read Data Bus Swapping 2 Q g Win Plols Read Data Bus MODE 2 S E N m CYCLES Internal or External ai c e gt CPU Read Data Bus rdbh gt core_rdbh dl a ee Melle rdbl gt core_rdbl 1 rdbl gt core_rdbh e i o e i e 2 rdbh gt core_rdbl Single Chip IS lt A O E 1 rdbh gt core_rdbl X 1 X 1 1 1 rdbl gt core_rdbl rdbl gt core_rdbh X q 1 ei 1 1 rdbh gt core_rdbl 1 extrdbh gt core_rdbh X 0 7 0 p 2 2 extrdbl gt core_rdbl 1 extrdbl gt core _rdbh 0 a 0 1 2 2 extrdbh gt core_rdbl X 0 X 1 0 1 extrdbh gt core_rdbl il 1 extrdbl gt core_rdbl Normal rdbh gt core_rdbh Expanded X 0 1 rdbl gt core_rdbl Narrow 1 rdbl gt core_rdbh A A 2 2 rdbh
294. ction BRN is useful during program debug to negate the effect of another branch instruction without disturbing the offset byte A complement for BRA is also useful in compiler implementations Execution time is longer when a conditional branch is taken than when it is not because the instruction queue must be refilled before execution resumes at the new address Since the BRN branch condition is never satisfied the branch is never taken and only a single program fetch is needed to update the instruction queue CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex BRN rel8 REL 21 rr P Branch Complementary Branch Comment Mnemonic Opcode Test Mnemonic Opcode Test BRN 21 Never BRA 20 Always Simple For More Information On This Product Go to www freescale com BRSET Operation CCR Effects Code and CPU Cycles Freescale Semiconductor WOE Guide 12CPU15UG V1 2 BRSET Branch if Bit s Set If M mask byte 0 then PC 0002 rel gt PC Performs a logical AND of the value of M and the mask value supplied with the instruction Branches if all the ones in M correspond to ones in the mask byte Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction
295. ction With this information and knowledge of the type and speed of memory in the system you can determine the execution time for any instruction in any system Simply count the code letters to determine the execution time of an instruction in a best case system An example of a best case system is a single chip 16 bit system with no 16 bit off boundary data accesses to any locations other than on chip RAM A single letter code in represents a single CPU access cycle An upper case letter indicates a 16 bit access For More Information On This Product Go to www freescale com Core User Guide si2cpu A f8gscale Semiconductor Inc Table A 7 CPU Cycle Notation Free cycle During an cycle the CPU does not use the bus An cycle is always one cycle of the system bus clock An cycle can be used by a queue controller or the background debug system to perform a single cycle access without disturbing the CPU Read PPAGE register A g cycle is used only in CALL instructions and is not visible on the external bus Since PPAGE is an internal 8 bit register a y cycle is never stretched Read indirect pointer Indexed indirect instructions use the 16 bit indirect pointer from memory to address the instruction operand An I cycle is a 16 bit read that can be aligned or misaligned An I cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the corresponding data is stored in external memory
296. ctionality is as given in Table 13 1 below Table 13 1 Breakpoint Mask Bits for First Address BKOMBH BKOMBL Address Compare BKPOX BKPOH BKPOL x 0 Full Address Compare Yes Yes Yes 0 1 256 byte Address Range No 1 1 16K byte Address Range No NOTES 1 If page is selected The x 0 case is for a Full Address Compare When a program page is selected the full address compare will be based on bits for a 20 bit compare The registers used for the compare are BKPOX 5 0 BKPOH 5 0 BKPOL 7 0 When a program page is not selected the full address compare will be based on bits for a 16 bit compare The registers used for the compare are BKPOH 7 0 BKPOL 7 0 The 1 0 case is not sensible because it would ignore the high order address and compare the low order and expansion addresses Logic forces this case to compare all address lines effectively ignoring the BKOMBH control bit The 1 1 case is useful for triggering a breakpoint on any access to a particular expansion page This only makes sense if a program page is being accessed so that the breakpoint trigger will occur only if BKPOX compares BK1MBH BKIMBL Breakpoint Mask High Byte and Low Byte of Data Second Address For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 In Dual Mode these bits may be used to mask disable the comparison of the high and or low bytes of the second address b
297. ctors start SWIV fdbSTART SWI vector normal entry point ILLOPV fdbFIXSP Illegal opcode vector For More Information On This Product Go to www freescale com fffa ff 24 fffc ff 24 fffe ff 20 Freescale Semiconductor ME Guide COPV fdbSTAR COP watchdog error vector CMONV fdbSTAR Clock monitor error vector RESETV fdbAFTER_RST Reset vector Sgl chip special ARI RRA end KKK KK KARA RAR RARA RRA RRA KARA RRA RAR RRA ARA RAR RAR 14 8 9 Secured Mode BDM Firmware Listing 7 EA RK K K k k A k k k A ke k k A e k ke a e k k e e k A Fe RARA RAR KKK KKK RK KKK KKK KK RK KKK RAR RIERA RRA RAR Copyright C 1999 by Motorola Inc MTC S CORE Design Group 7600 C Capitol of Texas Highway Austin TX 78731 All rights reserved No part of this software may be sold or distributed in any form or by any means without the prior written permission of Motorola Inc MOTOROLA CONFIDENTIAL PROPRIETARY INFORMATION RRR RRR RRR KKK KR KERR EK KKK KK RK KR KKK KR KK RK KK KKK EK KK KKK EK KKK KKK RRR KKK KKK ERK RK KK KK KEK EK File secure_firm s Target HCS12 Version 1 5 Author John_Langan RMAG10 email sps mot com Creation date June 28 1999 Comments This code is contained in the secure ROM of the BDM VERSION HISTORY Ver 000 John Langan orig July 02 1999 update bug found by Lloyd EERPOM size spec changes Aug 27 1999 Ver 001George Gr
298. culties associated with bank switching are eliminated On HCS12 systems with expanded memory capability bank numbers are specified by on chip control registers Since the addresses of these control registers may not be the same in all systems the HCS12 has a dedicated control line to the on chip integration module that indicates when a memory expansion register is being read or written This allows the CPU to access the PPAGE register without knowing the register address The indexed indirect versions of the CALL instruction access the address of the called routine and the destination page value indirectly For other addressing mode variations of the CALL instruction the destination page value is provided as immediate data in the instruction object code CALL and RTC execute correctly in the normal 64K byte address space thus providing for portable code For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 Core User Guide End Sheet For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Home Page www freescale com email support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 800 521 6274 48
299. cumulator by TBL in the D accumulator by ETBL is the y value of the beginning point plus the signed intermediate delta y value A summary of the table interpolation instructions is given in Table 4 18 Table 4 18 Table Interpolation Instructions Mnemonic Function Operation M M 1 B x M 2 M 3 M M 1 gt D 16 bit table lookup and interpolate Initialize B and index before ETBL indirect addressing not allowed Effective address points to the first 16 bit table entry M M 1 B is fractional part of lookup value M B x M 1 M A 8 bit table lookup and interpolate Initialize B and index before TBL indirect addressing not allowed Effective address points to the first 8 bit table entry M B is fractional part of lookup value TBL For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc 4 3 17 Branch Instructions A branch instruction causes a program sequence change when specific conditions exist There are three types of branch instructions short long and bit conditional Branch instructions can also be classified by the type of condition that must be satisfied in order for a branch to be taken e Unary branch instructions are always executed e Simple branch instructions are executed when a specific bit in the condition code register is in a specific state as a result of a previous operati
300. d write INTE 0 reg_sw0 0 ram_sw1 ram_sw0 rom_sw1 rom_sw0 pag_swi pag_sw0 0 IRQE IRQEN PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 o Reserved for Peripheral Block Registers BKEN BKFULL BKBDM BKTAG 0 0 ss BKOMBH BKOMBL BK1MBH BK1MBL BKORWE 0 0 BKOV5 BKOV4 BKOV3 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 Bit 0 PIXO 0 0 0 Bit 7 6 Bit 0 Bit 7 6 Bit 0 Reserved for Peripheral Block Registers For More Information On This Product Reserved for Flash EEPROM or ROM Registers Go to www freescale com 0110 to 011B 011C to 011F 0120 to 07FF FFOO FFO1 FFO2 FFOS FFO4 FFO5 FFO6 FFO7 Freescale Semiconductor ME Guide Zz 12CPU15UG V1 2 Reserved Reserved for EEPROM Registers Reserved Reserved for RAM Registers Reserved Reserved for Peripheral Block Registers read x X X X X X 0 0 Reserved write Bpmsts a4 write Reserved eae write Reserved reag write Reserved toag write Reserved rean write BpMccR e39 write BDMINR read REG12 REG11 write a a o Unimplemented X Indeterminate Figure 3 9 Core Register Map Summary Table 3 1 Core Register Map Reference Address Name Sub block Description 0000 PORTA MEBI Port A 8 bit Data Register MEBI Port B 8
301. d Low Byte 1 0 0 Compare No Yes Yes 0 1 High Byte No Yes No Low Byte No Compare NOTES 1 Expansion addresses for breakpoint 1 are not available in this mode BKORWE R W Compare Enable For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc Enables the comparison of the R W signal for first address breakpoint This bit is not useful in tagged breakpoints 0 R W is not used in the comparisons 1 R W is used in comparisons BKORW R W Compare Value When BKORWE 1 this bit determines the type of bus cycle to match on first address breakpoint When BKORWE 0 this bit has no effect 0 Write cycle will be matched 1 Read cycle will be matched BKIRWE R W Compare Enable In Dual Mode this bit enables the comparison of the R W signal to further specify what causes a match for the second address breakpoint This bit is not useful on tagged breakpoints or in Full Mode and is therefore a don t care 0 R W is not used in comparisons 1 R W is used in comparisons BKIRW R W Compare Value When BKIRWE 1 this bit determines the type of bus cycle to match on the second address breakpoint When BK1RWE 0 this bit has no effect 0 Write cycle will be matched 1 Read cycle will be matched 13 3 3 Breakpoint First Address Expansion Register BKPOX Read anytime Write anytime Address 002A Bit 7 6 5 4 3 2 1 Bit 0 Bkovs Bkov4
302. d address data on low byte even address data on high byte WRITE_BD WORD cc 16 bit address Write to memory with standard BDM firmware lookup table in map 16 bit data in Must be aligned access 16 bit address Write to memory with standard BDM firmware lookup table out of is oo 16 bit data in map Odd address data on low byte even address data on high byte 16 bit address Write to memory with standard BDM firmware lookup table out of MANE MORO ce 16 bit data in map Must be aligned access The READ_BD and WRITE_BD commands allow access to the BDM register locations These locations are not normally in the system memory map but share addresses with the application in memory To distinguish between physical memory locations that share the same address BDM memory resources are enabled just for the READ_BD and WRITE_BD access cycle This allows the BDM to access BDM locations unobtrusively even if the addresses conflict with the application memory map 14 4 4 Standard BDM Firmware Commands Firmware commands are used to access and manipulate CPU resources The system must be in active BDM to execute standard BDM firmware commands see 14 4 2 Normal instruction execution is suspended while the CPU executes the firmware located in the standard BDM firmware lookup table The hardware command BACKGROUND is the usual way to activate BDM As the system enters active BDM the standard BDM firmware lookup table and BDM regist
303. d for the loop count are A B D X Y or SP The branch range is a 9 bit signed value 512 to 511 which gives these instructions twice the range of a short branch instruction C 7 5 Long Branches All of the branch instructions from the M68HC11 are also available with 16 bit offsets which allows them to reach any location in the 64K byte address space For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 C 7 6 Minimum and Maximum Instructions Control programs often need to restrict data values within upper and lower limits The HCS12 facilitates this function with 8 and 16 bit versions of MIN and MAX instructions Each of these instructions has a version that stores the result in either the accumulator or in memory For example in a fuzzy logic inference program rule evaluation consists of a series of MIN and MAX operations The MIN operation determines the smallest rule input and stores the running result in an accumulator The MAX operation stores the largest rule truth value in an accumulator or stores the previous fuzzy output value from a RAM location in the fuzzy output in RAM The following code demonstrates how MIN and MAX instructions can be used to evaluate a rule with four inputs and two outputs LDY OUT1 Point at first output LDX IN1 Point at first input value LDAA SFF start with largest 8 bit number in A MINA 1 X A MIN A IN1 MINA
304. d rPf SBCB opr16a or B imm C B F2hh11 rPO SBCB oprx0_xysppc E2 xb rPf SBCB oprx9 xysppc E2 xb ff rPO SBCB oprx16 xysppc E2xbee ff frPP SBCB D xysppc E2 xb flfrPf SBCB oprx16 xysppc E2 xbee ff fIPrPf SECSame as ORCC 01 Set C bit 1401 SEISame as ORCC 10 Set bit SEVSame as ORCC 02 Set V bit SEX abc dxyspSame as TFRr1 r2 Sign extend 8 bit r1 to 16 bit r2 00 r1 r2 if bit 7 of r1 is O FF r1 r2 if bit 7 of r1 is 1 STAA opr8a Store accumulator A DIR 5Add Pw JaJa o STAA opr16a A M EXT 7Ahh11 PwO STAA oprx0_xysppc IDX 6A xb Pw STAA oprx9 xysppc IDX1 6A xb ff PwO STAA oprx16 xysppc IDX2 6Axbee ff PwP STAA D xysppc D IDX 6Axb PIfw STAA oprx16 xysppc IDX2 6Axbee ff PIPw STAB opr8a Store accumulator B DIR 5Bdd Pw Ja a o STAB opr16a B M EXT 7Bhh11 PwO STAB oprx0_xysppc IDX 6B xb Pw STAB oprx9 xysppc IDX1 6Bxb ff PwO STAB oprx16 xysppc IDX2 6Bxbeeff PwP STAB D xysppc D IDX 6B xb PIfw STAB oprx16 xysppc IDX2 6B xb ee ff PIPw STD opr8a Store D DIR 5C dd PW Ja a o STD opr16a A B gt M M 1 EXT 7Chh11 PWO STD oprx0_xysppc IDX 6C xb PW STD oprx9 xysppc IDX1 6C xb ff PWO STD oprx16 xysppc IDX2 6C xbee ff PWP STD D xysppc D IDX 6C xb PIFW STD oprx16 xysppc IDX2 6Cxbee ff PIPW STOP Stop processing SP 2 gt SP INH 18 3E oosssssf enter a ez pa re ge a RTNy RTN_ gt Mgp Mgp 4 stop mode SP 2 gt 8P Yy Y_ gt Mgp Mgp 4 ae exit stop SP 2 gt SP Xy X_ gt Mgp
305. dVel dvel dvel dVHL dvel dVel 9A9I YXYN IAOW Ol 84 01 83 0 egol 80 0 geglol sviOl 96 01 98 01 jot 989 01 geslol eriOl ee ey 8Z Z S v Blip 80 Z Hz Hie Hz Hlle Hie Hille Hz He Hz Hie Hz He Hr tule Hie H dVHL dvel dVHL dvel dvel dVHL dvel dVel dvel dvel dval dvel dvul OJAI veo vva Ol zalot za o zalot zojol za o Zviol zelo zglob ZzZ 0Ol Z9 0l ZS ol plob elem zz LZbie 20 Z He HZ Hie Hie Hz Hz alle Hz Hz Hiz ale Hz ally we He H dVHL dvel dVel dvel dvel dVHL dvel del dvel dvel dvel dvel dVel 3Ngl vas vav Ol 94 01 95 0 egol 990 01 94 01 eviol 96 01 98 01 ezo 99 01 9S 0l op ol ele gzj z 9 2 90 Z Hz Hz Hz Holle He Hilfe Hz He Hz Hie Hie Hz Hr tule HIS xa dVedl dvel dVel dvel dvel dVHL dvel dVul dVHL dvel dVHL dvel dvul sog SAIdI MAOW Ol salot salot salot so o salo cviol selot sgol sos cool selob Splot See szizt stig so Z Hie HZ HZ Hie Hz Hz Hz Hz Hz Hiz alle Hz ally We Hla dVUL dvel dVel dvel dvel dVHL dvel dVel dvel dvel dvel dvel dvel 2091 saaa MAOW Ol valot valot palot poor valol pylor velot gjor pjotr velol pslol wriol velei vz zk vii9 0 Z Hz Hege He n Hne He Heze Hne Hne nz Alle He Hr Hz HI 9X3MI dVedl dvel dVel dvel dvel dVHL dvel dVul dvel dvel dVHL dvel dvel s91 STAWI MAON Ol salot salot egol so ot ealo eviol selot egol ezo 9 01 eslol plot elem eze eils o Z He HZ HZ HZ Hz Hz Hz
306. ddress and data signals for proper interaction with the CPU The MEBI sub block functions as the external bus controller with four 8 bit ports A B E and K as well as handling mode decoding and initialization for the Core The BKP sub block serves to assist in debugging of software by providing for hardware breakpoints The BKP supports dual address and full breakpoint modes for matching on either of two address or on an address and data combination respectively to initiate a Software Interrupt SWD or put the system into Background Debug Mode The BKP also supports tagged or forced breakpoints for breaking just before a specific instruction or on the first instruction boundary after a match respectively The BDM sub block provides for a single wire background debug communication system implemented within the Core with on chip hardware The BDM allows for single wire serial interfacing with a development system host The Core is a fully synthesizable single clock design with full Mux D scan test implementation It is designed to be synthesized and timed together as a single block for optimizing speed of execution and minimizing area 1 5 Programming Model The HCS12 V1 5 Core CPU12 programming model shown in Figure 1 2 is the same as that of the 68HC12 and 68HC11 For a detailed description of the programming model and associated registers please refer to Section 3 of this guide For More Information On This Product Go to www freescale com
307. ddress that it points to Finally the CPU checks the location that TMP2 points to If the value stored in that location is 00 the BGND opcode TMP2 is incremented so that the instruction that follows the BGND instruction is the first instruction executed when normal program execution resumes For all other types of BDM entry the CPU performs the same sequence of operations as for a BGND instruction but the value stored in TMP2 already points to the instruction that would have executed next had BDM not become active If active BDM is triggered just as a BGND instruction is about to execute the BDM firmware does increment TMP2 but the change does not affect resumption of normal execution While BDM is active the CPU executes debugging commands received via a special single wire serial interface BDM is terminated by the execution of specific debugging commands Upon exit from BDM the background boot ROM and registers are disabled the instruction queue is refilled starting with the return address pointed to by TMP2 and normal processing resumes BDM is normally disabled to avoid accidental entry While BDM is disabled BGND executes as described but the firmware causes execution to return to the user program S X H I N ZV C Address Machine Source Form Mode Code Hex CPU Cycles BGND For More Information On This Product Go to www freescale com Core User Guide BGT Operation CCR Effects Code and CPU
308. de LSTRB would also be needed to fully understand system activity Development systems where pipe status signals are monitored would typically use special test mode or occasionally emulation expanded narrow mode The PE4 ECLK pin is initially configured as ECLK output with stretch The E clock output function depends upon the settings of the NECLK bit in the PEAR register the VIS bit in the MODE register and the ESTR bit in the EBICTL register In normal expanded narrow mode the E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system The PE2 R W pin is initially configured as a general purpose input with a pullup but this pin can be reconfigured as the R W bus control signal by writing 1 to the RDWE bit in PEAR If the expanded narrow system includes external devices that can be written such as RAM the RDWE bit would need to be set before any attempt to write to an external location If there are no writable resources in the external system PE2 can be left as a general purpose I O pin For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 12 4 8 7 Special Test Mode In expanded wide modes Ports A and B are configured as a 16 bit multiplexed address and data bus and Port E provides bus control and status signals In special test mode the write protection of many control bits is lifted so that th
309. der If the first byte is aligned the o cycle is an cycle The 18 prebyte for a page two opcode is treated as a special one byte instruction If the prebyte is misaligned the o cycle at the beginning of the instruction becomes a P cycle to maintain queue order If the prebyte is aligned the O cycle is an cycle If the instruction has an odd number of bytes it has a second O cycle at the end If the first o cycle is a P cycle prebyte misaligned the second o cycle is an f cycle If the first o cycle is an cycle prebyte aligned the second o cycle is a P cycle An o cycle that becomes a P cycle can be extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the program is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory An o cycle that becomes an cycle is never stretched P Program word access Program information is fetched as aligned 16 bit words A P cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the program is stored externally There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory r 8 bit data read An r cycle is stretched only when controlled by a chip select circuit programmed for slow memory R 16 bit data read An R cycle is extended to two bus cycles if the MCU is op
310. dexing register changes before indexing takes place When postdecremented or postincremented the indexing register changes after indexing takes place This addressing mode adjusts the indexing value without increasing execution time by using an additional instruction In this example the instruction compares X with the value that X points to and then increments X by one CPX 1 X The next two examples are equivalent to common push instructions In the first example the instruction predecrements the stack pointer by one and then stores A to the address contained in the stack pointer STAA 1 SP equivalent to PSHA STX 2 SP equivalent to PSHX The next two examples are equivalent to common pull instructions In the first example the instruction loads X from the address in the stack pointer and then postincrements the stack pointer by two LDX 2 SP equivalent to PULX LDAA 1 SP equivalent to PULA For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 The next example demonstrates how to work with data structures larger than bytes and words With this instruction in a program loop it is possible to move words of data from a list having one word per entry into a second table that has four bytes per table element The instruction postincrements the source pointer after reading the data from memory and preincrements the destination pointer before a
311. ditional stretching when the address space is assigned to a chip select circuit programmed for slow memory A w cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access Unstack 8 bit data A w cycle is stretched only when controlled by a chip select circuit programmed for slow memory Unstack 16 bit data A U cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the SP is pointing to external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory A U cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access The internal RAM is designed to allow single cycle misaligned word access 16 bit vector fetch Vectors are always aligned 16 bit words A v cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the program is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory 8 bit conditional read A t cycle is either a data read cycle or a free cycle depending on the data and flow of the REVW instruction A t cycle is stretched only when controlled by a chip select circuit programmed for slow memory Special No 16 bit conditional read A T c
312. dress and the values in the CPU registers then stops the CPU clocks halting program execution A reset or any enabled interrupt request recovers the stacked values and restarts the CPU clocks and program execution resumes Although recovery from STOP or WAI takes the same number of clock cycles restarting after STOP requires extra time for the oscillator to reach operating speed A summary of the STOP and WAI instructions is given in Table 4 29 Table 4 29 STOP and WAI Instructions Mnemonic Function Operation SP 0002 SP RTNy RTN Mgp Mgp 1 SP 0002 gt SP Yy YL Mgp Mgp 4 SP 0002 SP Xy X _ gt Mgp M oe ele pl 0002 SP ei Mee Moo SP 0001 SP CCR Msp Stop all clocks SP 0002 SP RTNy RTN Mgp Mgp y SP 0002 gt SP Yy YL gt Mgp Mgp 4 A SP 0002 SP Xy X_ gt Msp M WAI Wait for interrupt z000 SP a A vei ene SP 0001 SP CCR Msp Stop CPU clocks 4 3 25 Background Mode and Null Operation Instructions Executing the BGND instruction when BDM is enabled puts the MCU in background debug mode for system development and debugging Null operations are often used to replace other instructions during software debugging Replacing conditional branch instructions with BRN for instance permits testing a decision making routine without actually taking the branches A summary of the background mode and null op
313. dress of the first singleton value in the knowledge base Index register Y is a pointer to the fuzzy outputs F Y must have the address of the first fuzzy output for this system output Accumulator B contains the iteration count n and must be initialized with the number of labels for this system output B 7 2 WAV Interrupt Details The WAV instruction includes an 8 cycle processing loop for each label of the system output Within this loop the CPU checks to see whether a qualified interrupt request is pending If an interrupt request is detected the CPU registers and the current values of the internal temporary registers for the 24 bit and 16 bit sums are stacked and the interrupt is serviced For More Information On This Product Go to www freescale com Core User Guide si2crui Rf Scale Semiconductor Inc A special processing sequence is executed when an interrupt is detected during a weighted average calculation This exit sequence adjusts the PC so that it points to the second byte of the WAV object code 3C before the PC is stacked Upon return from the interrupt the 3C value is interpreted as a wavr pseudoinstruction The wavr pseudoinstruction causes the CPU to execute a special WAV resumption sequence The wavr recovery sequence adjusts the PC so that it looks as it did during execution of the original WAV instruction then jumps back into the WAV processing loop If another interrupt request occurs before the weighted average ca
314. ductor Inc RO R Rotate Right M R O R Operation ea a 7 os os oa es Toe vs eoc M Shifts all bits of M one place to the right Bit 7 is loaded from the C bit The C bit is loaded from the least significant bit of M Rotate operations include the carry bit to allow extension of shift and rotate operations to multiple bytes For example to shift a 24 bit value one bit to the right the sequence LSR HIGH ROR MID ROR LOW could be used where LOW MID and HIGH refer to the low middle and high bytes of the 24 bit value respectively CCR Effects S XH I N ZV C A A A A N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N o C Ne C for N and C after the shift cleared otherwise C MO set if the LSB of M was set before the shift cleared otherwise Code and CPU Source Form ddr codo Hen CPU Cycles Cycles ROR opr16a 76 hh 11 rPwO ROR oprx0_xysppc 66 xb rPw ROR oprx9 xysppc 66 xb ff rPwO ROR oprx16 xysppc 66 xb ee ff frPwP ROR D xysppc 66 xb fIfrPw ROR oprx16 xysppc 66 xb ee ff fIPrPw For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPuU15UG V1 2 RORA Rotate Right A RORA Operation gt ea or os oe es ea o oHe A Shifts all bits of A one place to the right Bit 7 is loaded from the C bit The C bit is loaded from the least significant bit of A Rotate oper
315. dy active meaning the CPU is executing out of BDM firmware Breakpoints are not allowed In addition while in BDM trace mode tagging into BDM is not allowed If BDM is not active the Breakpoint will give priority to BDM requests over SWI requests This condition applies to both forced and tagged breakpoints In all cases BDM related breakpoints will have priority over those generated by the Breakpoint sub block This priority includes breakpoints enabled by the TAGLO and TAGHI external pins of the system that interface with the BDM directly and whose signal information passes through and is used by the Breakpoint sub block NOTE BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM Even if the ENABLE bit in the BDM is negated the CPU actually executes the BDM firmware code It checks the ENABLE and returns if enable is not set If the BDM is not serviced by the monitor then the breakpoint would be re asserted when the BDM returns to normal CPU flow There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled 13 5 Motorola Internal Information The Breakpoint sub block does not contain any information that is considered to be for Motorola use only For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPuU15UG V1 2 Section 14 Background Debug Mode BDM This section describes the functionality of the Background
316. e 11 3 2 Initialization of Internal Registers Position Register INITRG Address Base 11 Bit 7 6 5 4 3 2 1 Bit 0 gt REG14 REG13 REG12 REG11 Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 11 4 INITRG Register Read Anytime Write Once in Normal and Emulation modes and anytime in Special modes For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 This register initializes the position of the internal registers within the on chip system memory map The registers occupy either a 1K byte or 2K byte space and can be mapped to any 2K byte space within the first 32K bytes of the system s address space REG14 REG11 Internal Register Map Position These four bits in combination with the leading zero supplied by bit 7 of INITRG determine the upper five bits of the base address for the system s internal registers i e the minimum base address is 0000 and the maximum is 7FFF 11 3 3 Initialization of Internal EEPROM Position Register INITEE Address Base 12 Bit 7 Bit 0 EE15 EE14 EE13 EE12 EE11 EEON Write Reset 0 1 Unimplemented Figure 11 5 INITEE Register Read Anytime Write Once in Normal and Emulation modes with the exception of the EEON bit which can be written anytime and write anytime in Special modes NOTE Writes to this register take one cycle to go into effect This register initializes the positio
317. e 00 OK byte 01 16K byte 10 48K byte 11 64K byte 1 The ROMHM software bit in the MISC register determines the accessibility of the Flash EEPROM ROM memory space Please refer to 11 3 4 for a detailed functional description of the ROMHM bit For More Information On This Product Go to www freescale com Core User Guide si2cPu Rf Scale Semiconductor Inc pag_swl pag_sw0 Allocated Off Chip Flash EEPROM or ROM Memory Space The allocated off chip Flash EEPROM or ROM memory space size is as given in Table 11 5 below Table 11 5 Allocated Off Chip Memory Options pag_sw1 pag_sw0 Off Chip Space On Chip Space 00 876K byte 128K byte 01 768K byte 256K byte 10 512K byte 512K byte 11 OK byte 1M byte NOTE As stated the bits in this register provide read visibility to the system memory space and on chip off chip partitioning allocations defined at system integration The actual array size for any given type of memory block may differ from the allocated size Please refer to the chip level documentation for actual sizes 11 3 9 Program Page Index Register PPAGE Address Base 30 Bit 7 6 5 4 3 2 1 Bit O Read 0 0 PIX5 PIX4 PIX3 PIX2 PIX1 PIXO Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 11 11 Program Page Index Register PPAGE Read Anytime Write Anytime The HCS12 Core architecture limits the physical address space available to 64K bytes
318. e Indexed operations require varying amounts of information to determine the effective address so instruction length varies with the addressing mode The amount of program information fetched also varies with instruction length To shorten execution time the CPU does one program word fetch in anticipation of the branch taken case The data from this fetch is ignored if the branch is not taken and the CPU refills the queue according to the instruction length If the branch is taken the CPU refills the queue from the new address according to the instruction length For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc 5 3 3 4 Loop Primitive Instructions A loop primitive instruction tests a counter value in a register or accumulator If the test condition is met the CPU branches to an address specified by a 9 bit relative offset contained in the instruction There are autoincrement and autodecrement versions of the instructions The test and increment decrement operations are performed on internal CPU registers and require no additional program information To shorten execution time the CPU does one program word fetch in anticipation of the branch taken case The data from this fetch is ignored if the branch is not taken and the CPU does one program fetch and one optional fetch to refill the queue If the branch is taken the CPU refills the queue with two additional program word
319. e CPU to recover its previous context from the stack and the REV instruction is resumed as if it had not been interrupted When a REV instruction is interrupted the stacked value of the program counter PC points to the REV instruction rather than the instruction that follows This causes the CPU to try to execute a new REV instruction upon return from the interrupt Since the CPU registers including the V bit in the condition code register indicate the current status of the interrupted REV instruction the rule evaluation operation resumes where it was interrupted B 6 1 3 Cycle by Cycle REV Details The central element of the REV instruction is a three cycle loop that is executed once for each byte in the rule list There is a small amount of housekeeping activity to get this loop started as REV begins and a small sequence to end the instruction If an interrupt comes there is a special small sequence to save CPU status on the stack before servicing the requested interrupt Figure B 9 is a REV instruction flow diagram Each box represents one CPU clock cycle Decision blocks and connecting arrows are considered to take no time at all The letters in the upper left corner of each box are execution cycle codes refer to Appendix A Instruction Set and Commands for details When a value is read from memory it cannot be used by the CPU until the second cycle after the read takes place This is due to access and propagation delays Since there
320. e Core interface is asserted in special modes the peri_test_clk signal will be driven out on Port E bit 6 when PIPOE 0 For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Section 13 Breakpoint BKP This section describes the functionality of the Breakpoint BKP sub block of the Core 13 1 Overview The Breakpoint sub block of the Core provides for hardware breakpoints that are used to debug software on the CPU by comparing actual address and data values to predetermined data in setup registers A successful comparison will place the CPU in Background Debug Mode or initiate a software interrupt SWI The Breakpoint sub block contains two modes of operation e Dual Address Mode where a match on either of two addresses will cause the system to enter Background Debug Mode or initiate a Software Interrupt SWI e Full Breakpoint Mode where a match on address and data will cause the system to enter Background Debug Mode or initiate a Software Interrupt SWI There are two types of breakpoints forced and tagged Forced breakpoints occur at the next instruction boundary if a match occurs and tagged breakpoints allow for breaking just before a specific instruction executes Tagged breakpoints will only occur on addresses Tagging on data is not all
321. e Register 0 to allow capability to read the state of the system memory configuration switches BKPCTO HPRIO Highest Priority Interrupt Register optional Breakpoint Control Register O to configure mode of operation of breakpoint functions MEMSIZ1 MMC Memory Size Register 1 to allow capability to read the state of the system memory configuration switches IRQCR MEBI IRQ Control Register to configure IRQ pin functionality 002D BKP1X 002E BKP1H Second Address Memory Expansion Breakpoint Register to assign second address match value for expanded addresses Second Address High Byte Breakpoint Register to assign high byte of first address within system memory space to be matched MM MM MM INT INT INT KP KP KP KP KP KP KP KP BKPCT1 B Breakpoint Control Register 1 to configure mode of operation of breakpoint functions First Address Memory Expansion Breakpoint Register to assign BKPOX B x first address match value for expanded addresses First Address High Byte Breakpoint Register to assign high byte of BKPOH B ie first address within system memory space to be matched BKPOL B First Address Low Byte Breakpoint Register to assign low byte of B M first address within system memory space to be matched Second Address Low Byte Breakpoint Register to assign low byte of first address within system memory space to be matched M Program Page Index Register to configure the active memory page viewed throug
322. e V bit is automatically maintained as FFFE separator words are detected The final requirement to clear all fuzzy outputs to 00 is part of the MAX algorithm Each time a rule consequent references a fuzzy output the fuzzy output is compared to the weighted truth value for the current rule If the current truth value is larger it is written over the previous value in the fuzzy output After all rules are evaluated the fuzzy output contains the truth value for the most true rule referencing that fuzzy output After REVW finishes accumulator A holds the weighted truth value for the last rule in the rule list The V bit should be one because the last element before the FFFF end marker should be a rule consequent If V is zero after executing REVW it indicates the rule list is structured incorrectly B 6 2 2 Interrupt Details The REVW instruction includes a three cycle processing loop for each word in the rule list This loop expands to five cycles between antecedents and consequents to allow time for multiplication by the rule weight Within this loop is a check to see if any qualified interrupt request is pending If an interrupt is detected the CPU registers are stacked and the interrupt request is serviced When the interrupt service routine finishes an RTI instruction causes the CPU to recover its previous context from the stack and the REVW instruction resumes as if it had not been interrupted When a REVW instruction is interrupted th
323. e and CPU Cycles CCR 01 CCR Performs a logical inclusive OR of the value in the CCR and 01 Puts the result in the CCR setting the C bit SEC assembles as ORCC 01 SEC can be used to initialize the C bit prior to a shift or rotate instruction involving the C bit S X H I N ZV C SSeS C Set Address Machine Source Form Mode Code Hex CPU Cycles For More Information On This Product Go to www freescale com Core User Guide SEI Operation CCR Effects Code and CPU Cycles si2cpu A A8gscale Semiconductor Inc ea SEI Same as ORCC 10 CCR 10 CCR Performs a logical inclusive OR of the value in the CCR and 10 Puts the result in the CCR setting the I bit SEI assembles as ORCC 10 When the I bit is set all I maskable interrupts are inhibited Address Machine Source Form Mode Code Hex CPU Cycles SEI IMM 14 10 P For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPuU15UG V1 2 S EV same ee 02 S EV Operation CCR I 02 CCR Performs a logical inclusive OR of the value in the CCR and 02 Puts the result in the CCR setting the V bit SEV assembles as ORCC 02 CCR Effects S XH I N ZV C eee sien V Set Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex SEV IMM 14 02 P For More Information On This P
324. e counter register does not reach zero Rel is a 9 bit two s complement offset for branching forward or backward in memory Branching range is 100 to OFF 256 to 255 from the address following the last byte of object code in the instruction CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex 04 lb rr PPP branch IBNE abdxysp rel9 REL PPO no branch Loop Primitive Postbyte 1b Coding Source Counter Form Postbyte Register IBNE A rel9 1010 X000 A IBNE B rel9 1010 X001 B IBNE D rel9 1010 X100 D IBNE X rel9 1010 X101 X IBNE Y rel9 1010 X110 Y IBNE SP rel9 1010 X111 SP IBNE A rel9 1011 X000 04 BO rr A IBNE B rel9 1011 X001 04 B1 rr B IBNE D rel9 1011 X100 04 B4 rr D Negative IBNE X rel9 1011 X101 04 B5 rr X IBNE Y rel9 1011 X110 04 B6 rr Y IBNE SP rel9 1011 X111 04 B7 rr SP NOTES 1 Bits 7 6 5 select IBEQ or IBNE bit 4 is the offset sign bit bit 3 is not used bits 2 1 0 select the counter register For More Information On This Product Go to www freescale com IDIV Operation CCR Effects Code and CPU Cycles Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Integer Divide Unsigned D IV D X gt X remainder gt D Divides an unsigned 16 bit dividend in D by an unsigned 16 bit divisor in X Puts the unsigned 16 bit quotient in X and the unsigned 16 bit remainder in D If both t
325. e data bus This operation only occurs when internal visibility is on Table 7 4 shows the relationship between these signals and the type of access Table 7 4 Access Type vs Bus Control Pins R W Type of Access 8 bit read of an even address 8 bit read of an odd address 8 bit write of an even address 8 bit write of an odd address 16 bit read of an odd address low high data swapped 16 bit write to an odd address low high data swapped For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPuU15UG V1 2 Section 8 Core Clock and Reset Connections This section details the HCS12 V1 5 Core external clock connections In addition this section will discuss the reset timing needs of the Core since this is associated very closely with the external clocking requirements 8 1 Clocking Overview The HCS12 V1 5 Core is implemented as a single clock source design with complete Mux D scan test implementation Since the Core is compatible with the feature set of the MHC12 microcontroller product family many signal and timing requirements exist for the system clock and reset generation block s to support these features Many of these requirements are driven by the interaction of the Core with the clock and reset generation block s in the system due to CPU wait and stop mode functionality and the various time based reset and interrupt functions such as Crystal Monitor a
326. e logic level at system integration HENO On chip Flash EEPROM or ROM size select switch bit O to be tied to the appropriate logic level at system integration For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Table 7 1 Core Interface Signal Definitions Signal Name Type Functional Description Reset state of the ROMON bit in the MISC Register to be tied to the appropriate literal logic level at system integration i e tied level is the state out of reset and not inverted Scan Control Interface Signals ipt_scan_mode Scan mode select signal 7 2 Signal Descriptions romon_exp_state General descriptions of the Core interface signals are given in the subsections below The clock reset and wait and stop mode signals are discussed in Section 8 of this guide For detailed descriptions of these signals including timing information please consult the HCS12 V1 5 Core Integration Guide 7 2 1 Internal Bus interface Signals These descriptions apply to the Core signals that interface with the on chip memories either directly or through the Core bus and with the system peripheral blocks through the I P Bus Interface 7 2 1 1 Core 20 bit Address Bus core_ab_t2 19 0 This 20 bit wide Core output provides the Core Address Bus to the system memory and peripheral blocks 7 2 1 2 16 bit Read Data Bus from system peripheral blocks peri_rdb_L12 15 0
327. e rE bare M0 C b7 A bO b7 B bO rPwO rPw rPwO frPwP fIfrPw fIPrPw For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Source Form ASR opr16a ASR oprx0_xysppc ASR oprx9 xysppc ASR oprx16 xysppc ASR D xysppc ASR oprx16 xysppc ASRA ASRB BCC rel8Same as BHS Operation Arithmetic shift right M o b7 bo Arithmetic shift right A Arithmetic shift right B Branch if C clear if C 0 then PC 2 rel gt PC Address Mode Machine Coding Hex 77 hh il 67 xb 67 xb ff 67 xbee ff 67 xb 67 xbee ff 47 53 24 rr Access Detail rPwO rPw rPwO frPwP fIfrPw fIPrPw PP branch no branch SXHINZVC BCLR opr8a msk8 BCLR opr16a msk8 BCLR oprx0_xysppc msk8 BCLR oprx9 xysppc msk8 BCLR oprx16 xysppc msk8 BCS rel8Same as BLO Clear bit s in M M emask byte M Branch if C set if C 1 then PC 2 rel gt PC 4D dd mm 1D hh 11mm 0D xb mm OD xb ff mm OD xb ee ff mm PP branch no branch BEQ rel8 Branch if equal if Z 1 then PC 2 rel gt PC Branch if 2 0 signed if NOV 0 then PC 2 rel gt PC Enter background debug
328. e stacked value of the program counter PC points to the REVW instruction rather than the instruction that follows This causes the CPU to try to execute a new REVW instruction upon return from the interrupt Since the CPU registers including the C and V bits in the condition code register indicate the status of the interrupted REVW instruction the rule evaluation operation resumes where it was interrupted B 6 2 3 Cycle by Cycle REVW Details The central element of the REVW instruction is a three cycle loop that is executed once for each word in the rule list This loop takes five cycles in the special case pass in which weights are enabled C 1 and the FFFE separator word is read between the rule antecedents and the rule consequents There is a small amount of housekeeping activity to get this loop started as REVW begins and a small sequence to end the instruction If an interrupt request comes there is a special small sequence to save CPU status on the stack before the interrupt is serviced Figure B 10 is a detailed flow diagram for the REVW instruction Each rectangular box represents one CPU clock cycle Decision blocks and connecting arrows are considered to take no time at all The letters in the small rectangles in the upper left corner of each box correspond to the execution cycle codes refer to Appendix A Instruction Set and Commands for details In cycle 2 0 the first element of the rule list a 16 bit address is read from memor
329. e statements that describe the actions a human expert would take to solve the application problem Rules and membership functions can be reduced to relatively simple data structures the knowledge base stored in nonvolatile memory A fuzzy inference kernel can be written by a programmer who does not know how the application system works All that the programmer needs to do with knowledge base information is store it in the memory locations used by the kernel SYSTEM INPUTS KNOWLEDGE BASE FUZZY INFERENCE KERNEL E A INP UT MEMBERSHIP gt FUZZIFICATION RULES as Tp TTT IN RAM 7 RULE LIST RULE EVALUATION ruz gurur A IN RAM OUTPUT MEMBERSHIP gt DEFUZZIFICATION FUNCTIONS Y SYSTEM OUTPUTS Figure B 1 Block Diagram of a Fuzzy Logic System One execution pass through the fuzzy inference kernel generates system output signals in response to current input conditions The kernel is executed as often as needed to maintain control If the kernel is executed more often than needed processor bandwidth and power are wasted On the other hand delaying too long between passes can cause the system to get too far out of control Choosing a periodic rate for a fuzzy control system is the same as it would be for a conventional control system For More Information On This Product Go to www freescale com Freescale Semiconductor MG truide si2cpuisuG v1 2 B 3 1
330. ead H F DATA R W TTAGO RNEXT Write Reset 0 0 0 0 0 0 0 0 Figure 14 12 BDM Instruction Register BDMIST Read All modes Write All modes BDM hardware writes this register when a BDM command is received Hardware clears the register if 512 BDM clock cycles occur between falling edges from the host Firmware clears this register when exiting from BDM active mode H F Hardware firmware flag When the BDM is active standard BDM firmware checks for this bit to be set by the BDM hardware as part of a BDM instruction load 1 Hardware command 0 Firmware command DATA Data flag This bit indicates that data accompanies the command 1 Data follows the command 0 No data R W Read write flag 1 Read 0 Write TTAGO Trace tag go bits The decoding of TTAGO is shown in Table 14 4 below Table 14 4 TTAGO Decoding TTAGO value Instruction 00 gt 01 GO 10 TRACE1 11 TAGGO RNEXT Register next bits For More Information On This Product Go to www freescale com Core User Guide si2cru ERA Scale Semiconductor Inc Indicates which register is being affected by a command In the case of a READ_NEXT or WRITE_NEXT command index register X is pre incremented by 2 and the word pointed to by X is then read or written The decoding of RNEXT is shown in Table 14 5 below Table 14 5 RNEXT Decoding RNEXT value Instruction READ WRITE NEXT 14 8 4 BDM Status Register The
331. ead Operations All read data coming into the Core is implemented by multiplexing the various input read data buses peri_rdb_L12 15 0 ram_rdb_L12 15 0 ee_rdb_L12 15 0 and fee_rdb_L12 15 0 onto the main internal Core read data bus The active input read data bus is defined by the select signal that is active during the Core read cycle The subsections below briefly discuss each of peripheral on chip memory register and array element and internal core register reads In each of the figures used in these subsections the read sequences are separated by write sequences to better illustrate the timing edges 7 3 1 1 Peripheral Reads The Core supports both 8 bit and 16 bit reads of peripheral registers The timing relationship for a basic 8 bit read of a peripheral register is shown in Figure 7 2 and that of a basic 16 bit read in Figure 7 3 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 The Core clock peri_clk24 provides the timing reference within the Core for all data transfers with the peripherals The peripheral clock peri_clk34 is the timing reference for all peripherals within the system tied to the I P Bus peri_clk24 TATI TATA Tete V V V VY VY VY WV core_ab_t2 addr0 _ adari peri_rdb_L12 data0 K data1 K data2 data3 core_perisel_t2 P o o wW O o S A E E core rwt2 A f f XA S AA core_sz8_t2 8 BIT 8BT A 8BIT
332. eakpoint support for forced or tagged breakpoints with two modes of operation Dual Address Mode to match on either of two addresses Full Breakpoint Mode to match on address and data combination Single wire background debug system implemented in on chip hardware Secured mode of operation Fully synthesizable design Single Core clock operation Full Mux D scan test implementation The HCS12 V1 5 Core is designed to interface with the system peripherals through the use of the I P Bus and its interface defined by the Motorola Semiconductor Reuse Standards MSRS The Core communicates with the on chip memory blocks either directly through the Core interface signals or via the STAR bus Interfacing with memories external to the system is provided for through the MEBI sub block of the Core and the corresponding port pad logic it is connected to within the system For More Information On This Product Go to www freescale com Freescale Semiconductor guide s12CPU15UG V1 2 1 3 Block Diagram A block diagram of the Core within a typical SoC system is given in Figure 1 1 below This diagram is a general representation of the Core its sub blocks and the interfaces to the rest of the blocks within the SoC design The signals related to BKGD Port A Port B Port E and Port K are direct interfaces to port pad logic at the top level of the overall system STAR Bus ai CPU MMC Central Module Processing Mapping Unit Control BD
333. ect V Set unless rule structure is incorrect C 1 selects weighted rule evaluation 0 selects unweighted rule evaluation Address Machine Source Form Mode Code Hex CPU Cycles OR tTxo or REVW Special 18 3B OREETERLO ffff ORE NOTES 1 Weighting not enabled the 3 cycle t Tx loop is executed once for each element in the rule list 2 Weighting enabled the 3 cycle t Tx loop expands to tTfR for separators 3 These are additional cycles caused by an interrupt f f is a 4 cycle exit sequence and ORf is a 3 cycle re entry sequence Execution resumes with a prefetch of the last ante cedent or consequent being processed at the time of the interrupt For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 RO L Rotate Left M R O L Operation pay Co 07 os os ess ez Jos Joo M Shifts all bits of M one place to the left Bit O is loaded from the C bit The C bit is loaded from the most significant bit of M Rotate operations include the carry bit to allow extension of shift and rotate operations to multiple bytes For example to shift a 24 bit value one bit to the left the sequence ASL LOW ROL MID ROL HIGH could be used where LOW MID and HIGH refer to the low middle and high bytes of the 24 bit value respectively CCR Effects S XH I N ZV C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared o
334. ed si2cpu A A8gscale Semiconductor Inc CLRB Address Machine Source Form Mode Code Hex CPU Cycles CLRB INH C7 For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 C LV same RAD S FD C LV Operation 0 V bit Clears the V bit CLV assembles as ANDCC FD CCR Effects S XH I N ZV C 0 2 V Cleared Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc CMPA Compare A CMPA Operation CCR Effects Code and CPU Cycles A M or A imm Compares the value in A to either the value in M or an immediate value CCR bits reflect the result The values in A and M do not change N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V A7e M7 e R7 A7 e M7 e R7 set if the operation produces a two s complement overflow cleared otherwise C A7 M7 M7 R7 R7 e A7 set if there is a borrow from the MSB of the result cleared otherwise Machine Source Form Code Hex CPU Cycles CMPA opr8i CMPA opr8a CMPA opr16a CMPA oprx0_xysppc CMPA oprx9 xysppc CMPA oprx16 xysppc CMPA D xysppc CMPA oprx16 xysppc 81 91 B Al Al Al Al Al For More Information On This Product Go to
335. ed 16 bit value in M M 1 from an unsigned 16 bit value in D to determine which is larger Puts the larger value in D If the values are equal the Z bit is set If the value in M M 1 is larger the C bit is set when the value in M M 1 replaces the value in D If the value in D is larger the C bit is cleared EMAXD accesses memory with indexed addressing modes for flexibility in specifying operand addresses Autoincrement and autodecrement functions can facilitate finding the largest value in a list of values S X H I N Z V C 4 4 4 a4 N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V D15 e M15 e R15 D15 M15 e R15 set if the operation produces a two s complement overflow cleared otherwise C D15 e M15 M15 R15 R15 e D15 set if M M 1 is larger than D cleared otherwise Condition code bits reflect internal subtraction R D M M 1 Addr Machin Source Form a Code H an CPU Cycles EMAXD oprx0_xysppc IDX 18 1A xb ORPf EMAXD oprx9 xysppc IDX1 18 1A xb ff ORPO EMAXD oprx16 xysppc IDX2 18 1A xb ee ff OfRPP EMAXD D xysppc D IDX 18 1A xb OfIfRPf EMAXD oprx16 xysppc IDX2 18 1A xb ee ff OfIPRP For More Information On This Product Go to www freescale com Core User Guide siocpuiataRscale Semiconductor Inc EMAXM ss exendeimaximmian EMAXM Operation CCR Effects Code and CPU Cycles MAX
336. ed otherwise V A7e M7 e R7 A7 e M7 e R7 set if the operation produces a two s complement overflow cleared otherwise C A7 M7 M7 R7 R7 e A7 set if M is larger than A cleared otherwise Condition code bits reflect internal subtraction R A M Address Machine Source Form Mode Code Hex CPU Cycles MAXA oprx0_xysppc IDX 18 18 xb OrPf MAXA oprx9 xysppc IDX1 18 18 xb ff OrPO MAXA oprx16 xysppc IDX2 18 18 xbee ff OfrPP MAXA D xysppc D IDX 18 18 xb OfIfrPf MAXA oprx16 xysppc IDX2 18 18 xbee ff OfIPrPf For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide MAXM MAX A M gt M Operation CCR Effects Code and CPU Cycles Subtracts an unsigned 8 bit value in M from an unsigned 8 bit value in A to determine which is larger Puts the larger value in M If the values are equal the Z bit is set If the value in M is larger the C bit is set If the value in A is larger the C bit is cleared when the Maximum in M value in A replaces the value in M MAXM accesses memory with indexed addressing modes for flexibility in specifying operand addresses Autoincrement and autodecrement functions can facilitate controlling the values in a list of values N Z V C A AJTAJA N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V A7 M7 e R7 A7 e M7 e R7 set if the ope
337. ed otherwise undefined after overflow or division by 0 V Set if the quotient is greater than 7FFF or less than 8000 cleared otherwise undefined after division by 0 C X15 e X14 e X13 e X12 o e X3 e X2 X1 e XQ set if denominator is 0000 cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles IDIVS INH 1815 OffffffffffO For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 INC Increment M INC Operation M 01 gt M Adds one to the value in M The N Z and V bits reflect the result of the operation The C bit is not affected by the operation thus allowing the INC instruction to be used as a loop counter in multiple precision computations When operating on unsigned values only BEQ BNE LBEQ and LBNE branches can be expected to perform consistently When operating on two s complement values all signed branches are available CCR Effects S XH I N ZV C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Set if the operation produces a two s complement overflow if and only if M was 7F before the operation cleared otherwise Code and CPU Source Form Code Hex CPU Cycles Cycles rPwO rPw rPwO INC opr16a INC oprx0_xysppc INC oprx9 xysppc INC oprx16 xysppc frPwP INC D xysppc fIfrPw INC oprx16 xysppc fIPrPw For More Information On This P
338. eescale Semiconductor WOE Guide 12CPU15UG V1 2 store D STD A B gt M M 1 Stores the value in A in M and the value in B in M M 1 The values in A and B do not change S X H N ZV C a a o N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V Cleared Address Machine Source Form Mode Code Hex CPU Cycles STD opr8a DIR 5C dd PW STD opr16a EXT 7C hh 11 PWO STD oprx0_xysppc IDX 6C xb PW STD oprx9 xysppc IDX1 6C xb ff PWO STD oprx16 xysppc IDX2 6C xb ee ff PWP STD D xysppc D IDX 6C xb PIfW STD oprx16 xysppc IDX2 6C xb ee FF PIPW For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc STOP dores STOP Operation CCR Effects Code and CPU Cycles SP 0002 gt SP RTNg RTNL gt Msp Msp 1 SP 0002 gt SP Y y Y gt Mgp Msgp 1 SP 0002 gt SP Xq Xz gt Msp Msp 1 SP 0002 SP B A gt Msp Msp y 1 SP 0001 SP CCR Msp Stop all clocks When the S bit is set STOP is disabled and operates like a 2 cycle NOP instruction When S is cleared STOP stacks CPU registers stops all system clocks and puts the device in standby mode Standby mode minimizes power consumption The contents of registers and the states of I O pins do not change Asserting RESET XIRQ or IRQ ends stand
339. eescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death ma
340. eing read into the instruction queue PE2 General purpose I O pin see PORTE and DDRE registers PE2 R W RW Read write indicates the direction of internal data transfers This is an output except in peripheral mode where it is an input SS PE1 General purpose input only pin can be read even if IRQ enabled PE1 IRQ IRQ Maskable interrupt request can be level sensitive or edge sensitive PEO General purpose input only pin PEO XIRQ XIRQ Non maskable interrupt input PK7 General purpose I O pin see PORTK and DDRK registers PK7 ECS ECS emulation chip select PK6 General purpose I O pin see PORTK and DDRK registers PK6 XCS XCS external data chip select PK5 X19 thru PK5 PKO General purpose I O pins see PORTK and DDRK registers PKO X14 X19 X14 Memory expansion addresses At the rising edge on RESET the state of this pin is registered into the MODC bit MODC Hens to set the mode This pin always has an internal pullup BKGD MODC Pseudo open drain communication pin for the single wire background debug AT BKGD SF ics TAGHI mode There is an internal pullup resistor on this pin When instruction tagging is on a 0 at the falling edge of E tags the high half of the TAGHI A a A instruction word being read into the instruction queue 12 4 6 Detecting Access Type from External Signals The external signals LSTRB R W and ABO indicate the type of bus access that is taking place Accesses to the internal RAM module are the only t
341. elative offset in the byte that follows the opcode A long conditional branch instruction has an 8 bit prebyte an 8 bit opcode and a signed 16 bit relative offset in the two bytes that follow the opcode A branching bit condition instruction BRCLR or BRSET tests the state of one or more bits in a memory byte Direct extended or indexed addressing can determine the location of the memory byte The instruction includes an immediate 8 bit mask operand to test the bits and an 8 bit relative offset If the bits test true execution begins at the destination formed by adding the 8 bit offset to the address of the memory location after the offset If the bits do not test true execution continues with the instruction that follows the branch instruction Both 8 bit and 16 bit offsets are signed two s complement numbers to support branching upward and downward in memory The numeric range of short branch offset values is 80 128 to 7F 127 The numeric range of long branch offset values is 8000 32768 to 7FFF 32767 If the offset is zero the CPU executes the instruction that follows the branch instruction Since the offset is at the end of a branch instruction using a negative offset value can cause the PC to point to the opcode and initiate a loop For instance a branch always BRA instruction consists of two bytes so using an offset of FE sets up an infinite loop the same is true of a long branch always LBRA instruction with an offset
342. element in the rule list The denotes a check These are additional cycles caused by an interrupt f is the exit sequence and Orft for pending interrup t requests is the re entry sequence REVW Rule evaluation weighted rule weights optional find smallest rule input store to rule outputs unless fuzzy output is larger Special 18 3B ORf t Tx O or ORF r ffR O TLELFOREE FEEETORE TA SRF With weighting not enabled the t Tx loop is executed once for each element in the rule list The denotes a check for pending interrupt requests With weighting enabled the t Tx loop is replaced by r ffRf Additional cycles caused by an interrupt when weighting is not enabled ff ff is the exit sequence and ORft is the re entry sequence Additional cycles caused by an interrupt when weighting is enabled f ff is the exit sequence and ORfr is the re entry sequence ROL opr16a ROL oprx0_xysppc ROL oprx9 xysppc ROL oprx16 xysppc ROL D xysppc ROL oprx16 xysppc Rotate left M i H C b7 Rotate left A Rotate left B 75hh11 65 xb 65xb ff 65xbee ff 65 xb 65xbee ff 45 55 rPwO rPw rPwO frPwP fIfrPw fIPrPw O O ROR opr16a ROR oprx0_xysppc ROR oprx9 xysppc ROR oprx16 xysppc ROR D xysppc ROR oprx16 xysppc RORA RORB RTI takes 11 cycles if
343. embler source forms For complete information about writing source files for a particular assembler refer to the documentation provided by the assembler vendor Everything in the Source Form column except expressions in italic characters is literal information which must appear in the assembly source file exactly as shown The initial 3 to 5 letter mnemonic is always a literal expression All commas pound signs parentheses square brackets or plus signs minus signs and the register designation A B D are literal characters The groups of italic characters shown in Table 1 4 represent variable information to be supplied by the programmer These groups can include any alphanumeric character or the underscore character but cannot For More Information On This Product Go to www freescale com Core User Guide siocpuimtaRscale Semiconductor Inc include a space or comma For example the groups xysppc and oprx0_xysppc are both valid but the two groups oprx0 xysppc are not valid because there is a space between them Table 1 4 Source Form Notation abc Register designator for A B or CCR abcdxysp Register designator for A B CCR D X Y or SP abd abdxysp Register designator for A B or D Register designator for A B D X Y or SP Register designator for D X Y or SP 8 bit mask value Some assemblers require the symbol before the mask value 8 bit immediate value
344. ement values all signed branches are available N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared C Set for M6800 compatibility Address Machine Source Form Mode Code Hex CPU Cycles COM opr16a EXT 71 hh 11 rPwO COM oprx0_xysppc IDX 61 xb rPw COM oprx9 xysppc IDX1 61 xb ff rPwO COM oprx16 xysppc IDX2 61 xb ee ff frPwP COM D xysppc D IDX 61 xb fIfrPw COM oprx16 xysppc IDX2 61 xb ee ff IPrPw For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 COMA Complement A COMA Operation A FF A gt A Replaces the value in A with its one s complement Immediately after a COM operation on unsigned values only the BEQ BNE LBEQ and LBNE branches can be expected to perform consistently After operation on two s complement values all signed branches are available CCR Effects S XH I N ZV C i A_A 0 1 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared C Set for M6800 compatibility Code and CPU Source Form pr ea Code Hex CPU Cycles Cycles COMA INH 41 O For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc COMB Complement B COMB Operation CCR Effects Code and CPU Cycles B FF B gt B Replaces the value in B wi
345. ementary Branch Comment Mnemonic Opcode Mnemonic Opcode Test BLO BCS BHS BCC For More Information On This Product Go to www freescale com BLS Operation CCR Effects Code and CPU Cycles Freescale Semiconductor WOE Guide 12CPU15UG V1 2 BLS Branch if Lower or Same If C Z 1 then PC 0002 rel gt PC BLS can be used to branch after subtracting or comparing unsigned values After CMPA CMPB CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the CPU register value is less than or equal to the value in M After CBA or SBA the branch occurs if the value in B is less than or equal to the value in A BLS is not for branching after instructions that do not affect the C bit such as increment decrement load store test clear or complement Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction Address Mode Machine Code Hex CPU Cycles Source Form PPP branch BLS rel8 P no branch Branch Complementary Branch z Comment Mnemonic Opcode Test Mnemonic Opcode R lt M or BLS 23 B lt A BHI 22 Unsigned C Z 1 R lt M or BLE 2F B lt A BGT 2E Signed Z NOV 1 For More Information On This Product
346. emiconductor WOE Guide M A or imm gt A Loads A with either the value in M or an immediate value N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Source Form Address CPU Cycles LDAA opr8i 86 ii LDAA opr8a 96 dd rPf LDAA opr16a B6 hh 11 TPO LDAA oprx0_xysppc A6 xb rPf LDAA oprx9 xysppc A6 xb ff rPO LDAA oprx16 xysppc A6 xb ee ff frPP LDAA D xysppc A6 xb fIfrPf LDAA oprx16 xysppc A6 xb ee ff fIPrPf For More Information On This Product Go to www freescale com 12CPU15UG V1 2 LDAA Load A LDAA Core User Guide si2cpu RR Scale Semiconductor Inc LDAB Load B LDAB Operation CCR Effects Code and CPU Cycles M gt B or imm gt B Loads B with either the value in M or an immediate value N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Source Form LDAB opr8i LDAB opr8a LDAB opr16a LDAB oprx0_xysppc LDAB oprx9 xysppc LDAB oprx16 xysppc E6 xb ee ff LDAB D xysppc E6 xb LDAB oprx16 xysppc E6 xb ee ff For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 LDD Load D LDD Operation CCR Effects Code and CPU Cycles M M 1 A B or imm gt A B Loads A with the value in M and loads B with the value in M M 1 or loads A B with an immediate value S X H I N
347. emory space C000 FFFF Write Mass Erase command 41 to FCMD register Clear CBIEF bit 7 it FSTAT register Write ECLKDIV register to set the EEPROM clock for proper timing Disable protection in EEPROM by writing the EPROT register Write any data to EEPROM memory space Write Mass Erase command 41 to ECMD register Clear CBIEF bit 7 it ESTAT register Wait until all CCIF flags are set to 1 again roc poe rho pa z After all the CCIF flags are set to 1 again the Flash and EEPROM have been erased Reset the microcontroller into SPECIAL SINGLE CHIP mode The BDM secure ROM will verify that the nonvolatile memories are erased and then it will assert the UNSEC bit in the BDM Status register This will cause the core_secure_t2 signal to de assert and the microcontroller will be unsecure All BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state by any of the following methods 1 Send BDM commands to write to the MODE register and change to SPECIAL TEST mode send a BDM WRITE_PC followed by a BDM GO command to jump to a program at an external address This external program can then program the Flash security byte to the unsecure state 2 Send BDM commands to directly program the Flash security byte In all modes programming the security byte must have the following steps Write FCLKDIV register to set the Flash clock for proper timing Write 00 to FCNFG register to select Flash block
348. enable from Core core_pkobe 7 0 This 8 bit wide output from the Core provides the bit by bit output buffer enable signal to the system port pad logic for Port K 7 2 2 23 Port K input buffer enable from Core core_pkibe_t2 This single bit output from the Core provides the input buffer enable signal to the system port pad logic for Port K 7 2 2 24 Port K pullup enable from Core core_pkpue_t2 This single bit output from the Core indicates that the pullup devices within the system port pad logic for Port K should be enabled for all Port K pins 7 2 2 25 Port K drive strength enable from Core core_pkdse_t2 This single bit output from the Core indicates whether all Port K pins will operate with full or reduced drive strength 7 2 3 Clock and Reset Signals Please see Section 8 of this guide For More Information On This Product Go to www freescale com Freescale Semiconductor MS Guide s12cPu15UG V1 2 7 2 4 Vector Request Acknowledge Signals These descriptions apply to signals that provide for vector requesting to and corresponding acknowledgment from the Core 7 2 4 1 CPU vector fetch core_vector_fetch_t4 This Core output signal indicates that the CPU is executing a vector fetch as a result of a reset or interrupt sequence 7 2 4 2 System level reset vector request peri_rstv_request This input signal indicates to the Core that the system is requesting the external reset vector from the Core 7 2 4 3 System le
349. ence program shows how easy it is to incorporate fuzzy logic into general applications using the HCS12 CPU Code space and execution time are no longer serious factors in the decision to use fuzzy logic The next section begins a much more detailed look at the fuzzy logic instructions B 5 MEM Instruction Details This section provides a more detailed explanation of the membership function evaluation instruction MEM including details about abnormal special cases for improperly defined membership functions B 5 1 Membership Function Definitions Figure B 4 shows how a normal membership function is specified Typically a software tool is used to input membership functions graphically and the tool generates data structures for the target processor and software kernel Alternatively points and slopes for the membership functions can be determined and stored in memory with define constant assembler directives An internal CPU algorithm calculates the y value where the current input intersects a membership function This algorithm assumes the membership function obeys some common sense rules If the membership function definition is improper the results may be unusual B 5 2 Abnormal Membership Function Definitions discusses these cases The following rules apply to normal membership functions e 00 lt pointl lt FF e 00 lt point2 lt FF For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide
350. ended multiply and accumulate instructions produce 32 bit products 1 6 2 Memory Organization The standard HCS12 Core address space is 64K bytes However the CPU has special instructions to support paged memory expansion which increases the standard area by means of predefined windows within the available address space See Section 11 Module Mapping Control MMC for more information Eight bit values can be stored at any odd or even byte address in available memory Sixteen bit values occupy two consecutive memory locations the high byte is in the lowest address but does not have to be aligned to an even boundary Thirty two bit values occupy four consecutive memory locations the high byte is in the lowest address but does not have to be aligned to an even boundary All I O and all on chip peripherals are memory mapped No special instruction syntax is required to access these addresses On chip register and memory mapping are determined at the SoC level and are configured during integration of the Core into the system 1 7 Addressing modes A summary of the addressing modes used by the Core is given in Table 1 1 below The operation of each of these modes is discussed in detail in Section 4 of this guide Table 1 1 Addressing Mode Summary Addressing Mode Source Form Abbreviation Description INST Inherent no externally supplied INH Operands if any are in CPU registers operands INST oprei Operand is included in ins
351. er I bit maskable sources configured at integration of the Core into the SoC design The documentation for each system should provide more information 6 3 2 1 Unimplemented Opcode Trap TRAP Only 54 of the 256 positions on page 2 of the opcode map are used Attempting to execute one of the 202 unused opcodes on page 2 causes a nonmaskable interrupt without an interrupt request All 202 unused opcodes share the same interrupt vector FFF8 FFF9 TRAP processing stacks the CCR and then sets the I bit to prevent other interrupts during the TRAP service routine An RTI instruction at the end of the service routine restores the I bit to its preinterrupt state The CPU uses the next address after an unimplemented page 2 opcode as a return address This differs from the M68HC11 illegal opcode interrupt which uses the address of an illegal opcode as the return address The stacked return address can be used to calculate the address of the unimplemented opcode for software controlled traps 6 3 2 2 Software Interrupt Instruction SWI Execution of the SWI instruction causes a nonmaskable interrupt without an interrupt request SWI processing stacks the CCR and then sets the I bit to prevent other interrupts during the SWI service routine An RTI instruction at the end of the service routine restores the I bit to its preinterrupt state NOTE CPU processing of a TRAP or SWI cannot be interrupted Also TRAP and SWI are mutually exclusive instructio
352. er enable BDM BKGD pin input buffer enable BDM BKGD pin pullup enable Memory Configuration Signals bkgd_ind core_bkgd_dout_t4 core_bkgd_obe core_bkgd_ibe_t2 core_bkgdpue_t2 Register space size select switch to be tied to the appropriate logic level at system integration 0 1K byte register space aligned to lower address 1 2K byte register space reg_sw0 On chip memory size select switch bit 1 to be tied to the appropriate logic level at system integration O O On chip memory size select switch bit 0 to be tied to the appropriate pag_sw0 y logic level at system integration On chip RAM fast memory transfer select to be tied to the ram_fmts I l pag_sw1 appropriate logic level at system integration On chip RAM size select switch bit 2 to be tied to the appropriate logic level at system integration ram_sw2 On chip RAM size select switch bit 1 to be tied to the appropriate ram_sw1 A E logic level at system integration On chip RAM size select switch bit 0 to be tied to the appropriate ram_sw0 5 logic level at system integration On chip EEPROM size select switch bit 1 to be tied to the appropriate Gep sw logic level at system integration On chip EEPROM size select switch bit 0 to be tied to the appropriate Bap lee logic level at system integration On chip Flash EEPROM or ROM size select switch bit 1 to be tied to rom_sw1 y i the appropriat
353. er vendor The major contributors to the reduction appear to be improved indexed addressing and the universal transfer exchange instruction In some specialized areas the reduction is much greater A fuzzy logic inference kernel requires about 250 bytes in the M68HC11 and the same program for the HCS12 requires about 50 bytes The HCS12 fuzzy logic instructions replace whole subroutines in the M68HC11 version Table lookup instructions also greatly reduce code space Other HCS12 code space reductions are more subtle Memory to memory moves are one example The HCS12 move instruction requires almost as many bytes as an equivalent sequence of M68HC11 instructions but the move operations themselves do not require the use of an accumulator This means that the accumulator often need not be saved and restored which saves instructions Arithmetic on index pointers is another example The M68HC11 usually requires that the content of the index register be moved into accumulator D where calculations are performed then back to the index register before indexing can take place In the HCS12 the LEAS LEAX and LEAY instructions perform For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc arithmetic operations directly on the index pointers The pre post increment decrement variations of indexed addressing also allow index modification to be incorporated into an existing indexed instruc
354. erating with an 8 bit external data bus and the corresponding data is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory An R cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access s Stack 8 bit data An s cycle is stretched only when controlled by a chip select circuit programmed for slow memory For More Information On This Product Go to www freescale com Core User Guide S 12cru A f8g5scale Semiconductor Inc Table 1 8 Access Detail Notation Continued Stack 16 bit data An s cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the SP is pointing to external memory There can be additional stretching if the address space is assigned to a chip select circuit programmed for slow memory An s cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access The internal RAM is designed to allow single cycle misaligned word access 8 bit data write A w cycle is stretched only when controlled by a chip select circuit programmed for slow memory 16 bit data write A w cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the corresponding data is stored in external memory There can be ad
355. eration instructions is given in Table 4 30 Table 4 30 Background Mode and Null Operation Instructions Mnemonic Function Operation BGND Enter background debug mode If BDM enabled enter BDM else resume normal processing BRN Branch never Does not branch LBRN Long branch never Does not branch NOP Null operation Does nothing For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc 4 4 High Level Language Support Many programmers are turning to high level languages such as C as an alternative to coding in native assembly languages High level language HLL programming can improve productivity and produce code that is more easily maintained than assembly language programs Historically the most serious drawback to the use of HLL in microcontrollers has been the relatively large size of programs written in HLL Larger program memory space size requirements translate into increased system costs Motorola solicited the cooperation of third party software developers to assure that the HCS12 instruction set would meet the needs of a more efficient generation of compilers Several features of the HCS12 were specifically designed to improve the efficiency of compiled HLL and thus minimize cost This subsection identifies HCS12 instructions and addressing modes that provide improved support for high level language C language examples are provided to demonstrate how th
356. ere n is the number of bytes needed for local variables Notice that parameters are at positive offsets from the frame pointer while locals are at negative offsets In the M68HC11 the indexed addressing mode uses only positive offsets so the frame pointer always points to the lowest address of any parameter or local After the function subroutine finishes calculations are required to restore the stack pointer to the midframe position between the locals and the parameters before returning to the calling program The HCS12 CPU requires only the execution of TFR X S to deallocate the local storage and return The concept of a frame pointer is supported in the HCS12 through a combination of improved indexed addressing universal transfer exchange and the LEA instruction These instructions work together to achieve more efficient handling of frame pointers It is important to consider the complete instruction set as a complex system with subtle interrelationships rather than simply examining individual instructions when trying to improve an instruction set Adding or removing a single instruction can have unexpected consequences For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc 4 4 3 Increment and Decrement Operators In C the notation i or i is often used to form loop counters Within limited constraints the HCS12 loop primitives can speed up the loop count and bra
357. ers become visible in the on chip memory map at FF00 FFFF and the CPU begins executing the standard BDM For More Information On This Product Go to www freescale com Core User Guide siocpuimtaRscale Semiconductor Inc firmware The standard BDM firmware watches for serial commands and executes them as they are received The firmware commands are shown in Table 14 2 Table 14 2 Firmware Commands Command on Data Description READ_NEXT 62 16 bit data out Increment X by 2 X X 2 then read word X points to READ_PC 63 16 bit data out Read program counter READ_D 64 16 bit data out Read D accumulator READ_X 65 16 bit data out Read X index register READ_Y 66 16 bit data out Read Y index register READ_SP 67 16 bit data out Read stack pointer WRITE_NEXT 42 16 bit data in Boer X by 2 X X 2 then write word to location pointed to WRITE_PC 43 16 bit data in Write program counter WRITE_D 44 16 bit data in Write D accumulator WRITE_X 45 16 bit data in Write X index register WRITE_Y 46 16 bit data in Write Y index register WRITE_SP 47 16 bit data in Write stack pointer GO 08 none Go to user program TRACE1 10 none Execute one user instruction then return to active BDM TAGGO 18 none Enable tagging and go to user program 14 4 5 BDM Command Structure Hardware and firmware BDM commands start with an 8 bit opcode followed by a 16 bit address and or a 16 bit data word depending on the command A
358. es The Program Page Index Register allows for integrating up to 1M byte of Flash EEPROM or ROM into the system by using the six page index bits to page 16K byte blocks into the Program Page Window located from 8000 to BFFF in the physical memory space The paged memory space can consist of solely on chip memory or a combination of on chip and off chip memory This partitioning is configured at system integration through the use of the paging configuration switches pag_sw pag_sw0 at the Core boundary The options available to the integrator are as given in Table 11 8 below this table matches Table 11 5 but is repeated here for easy reference Table 11 8 Allocated Off Chip Memory Options pag_sw1 pag_sw0 Off Chip Space On Chip Space 00 876K byte 128K byte 01 768K byte 256K byte 10 512K byte 512K byte 11 OK byte 1M byte Based upon the system configuration the Program Page Window will consider its access to be either internal or external as defined in Table 11 9 below Table 11 9 External Internal Page Window Access pag_sw1 pag_sw0 Partitioning PIX5 0 Value Page Window Access 876K off Chip 00 37 external 128K on Chip 38 3F internal 768K off chip 00 2F external 256K on chip 30 3F internal 512K off chip 00 1F external 512K on chip 20 3F internal OK off chip external 1M on chip 00 3F internal NOTE The partitioning as defined in Table 11 9 above app
359. es that push the return address onto the stack 3 1 P This cycle is the first of three program word fetches to refill the instruction queue Instructions are fetched from the address pointed to by the vector 4 1 S This cycle pushes Y onto the stack 5 1 S For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc This cycle pushes X onto the stack This cycle is the second of three program word fetches to refill the instruction queue During this cycle the contents of the A and B accumulators are concatenated in the order B A making register order in the stack frame the same as that of the M68HC11 M6801 and the M6800 This cycle pushes the 16 bit word containing B A onto the stack 8 1 s and These are both s cycles 8 bit writes that push the 8 bit CCR onto the stack and then update the X and I mask bits When an XIRQ interrupt causes the exception both X and I are set to inhibit further interrupts during exception processing e When any other interrupt causes the exception the I bit is set to inhibit further I bit maskable interrupts during exception processing but the X bit is not changed For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 This cycle is the third of three program word fetches to refill the instruction queue It is the last cycle of exception processing After th
360. ese features support efficient HLL structures and concepts Since the HCS12 instruction set is a superset of the M68HC11 instruction set some of the discussions use the M68HC11 as a basis for comparison 4 4 1 Data Types The HCS12 CPU supports the bit sized data type with bit manipulation instructions that are available in extended direct and indexed variations The char data type is a simple 8 bit value that is commonly used to specify variables in a small microcontroller system because it requires less memory space than a 16 bit integer provided the variable has a range small enough to fit into eight bits The 16 bit HCS12 CPU can easily handle 16 bit integer types and the set of conditional branches including long branches allows branching based on signed or unsigned arithmetic results Some of the higher math functions allow for division and multiplication involving 32 bit values although it is somewhat less common to use such long values in a microcontroller system Special sign extension instructions allow easy type casting from smaller data types to larger ones such as from char to integer This sign extension is automatically performed when an 8 bit value is transferred to a 16 bit register 4 4 2 Parameters and Variables High level languages make extensive use of the stack both to pass variables and for temporary and local storage It follows that there should be easy ways to push and pull all CPU registers that stack pointer ba
361. eset_pin_ind signal timing follows that of the physical system reset pin indicating immediately when a system reset is requested for example when the RESET pin is pulled low externally This signal is used as a load enable on the MODE pins of the MEBI sub block to ensure that the Core mode of operation is known and set up immediately upon a system reset request The peri_reset_ta4 signal will generally be asserted logic 1 asynchronously by the reset generation block at the time that a system reset is requested Further the assumption is that this signal will stay asserted until such time that the clock generation block has determined that the clocks to the Core are stable and that the Core should proceed with a system reset sequence 8 1 3 Phase Locked Loop Interface The Core allows for the implementation of a on chip Phase Locked Loop PLL and interacts with it through the peri_pllsel_t3 peri_test_clk_enable and peri_test_clk input signals If a PLL is implemented the Core assumes it will operate on the peripheral clock peri_clk34 and thus the peri_pllsel_t3 signal must be asserted logic 1 on the phase three rising edge of this clock when the PLL is first engaged and to be negated logic 0 when the PLL is disabled The peri_test_clk and peri_test_clk_enable signals are provided in order to facilitate test features for the PLL When the peri_test_clk_enable signal is asserted logic 1 the Core will register the signal on the phase four ris
362. ess Mode Machine Coding Hex 18tn tn 30 39 or tn 40 FF F7hh11 E7 xb E7 xb ff E7 xbee ff E7 xb E7 xbee ff 97 D7 Access Detail SXHINZVC OVSPSSPSsP rPO rPf rPO frPP fIfrPf fIPrPf OSSSSsf before interrupt VfPPP after interrupt Calculate weighted average sum of products SOP and sum of weights SOW Initialize B X and Y B number of elements X points at first element in S list The frr ff ff sequence is the loop for one iteration of SOP and SOW accu Special Y points at Additional cycles caused by an interrupt SSS is the exit sequence and UUUrr is the first elementin F list mulation The denotes a che re entry sequence Intermediate values us OE TEESEELEJOR SSS UUUrro x x All S and F elements are 8 bit values ck for pending interrupt requests e six stack bytes wavr Resume executing interrupted WAV Special 3 DUUITESFELE ECOS EELLJOS SS UUUrr Pia A wavr is a pseudoinstruction that recovers intermediate results from the stack rather than initializing them to 0 The frr ffff sequence is the loop for one iteration of SOP and SOW recovery The denotes a check for pending interrupt requests These are additional
363. estores user info and resumes user program where it left to enter active BD mode EXIT_SEQ CAUTION 10 o per A CA CA A F F F F E CclrINSTR clear instruction tp 4 6 95 ldabCCRSAVE re entry value for CCR staaCCRSAVE will use movb to store to STATUS exgx t2 Swap X to Temp2 and User PC to X StxSHIFTER For later indirect jump exgx t2 Restore user X tfrb ccr Restore user CCR exgt3 d Restore user D reg movbCCRSAVE STATUS OrPwPO write w o chg to ccr El Critical timing cycle signature of above move is OrPwPO Exit timing referenced to the byte write in cycle 4 Cycle signatures of remaining instructions in exit seq are shown in the comments ROM switch from BD ROM to user map should occur at f cycle before PPP in exit jump If TRACE issue liufbdm at T4 of the second last P cycle of the exit jump OB P w P O EOD E POPLE 1 1 jmp SHIFTER 4 pc fIfPPP Exit to user PC In this exit jump the I cycle is a word read of the user PC from the SHIFTER register BD map The PPP cycles are word fetches of user program info to fill instruction queue from user s map The ROM switch must occur between I and PPP See also CAUTION 9 concerning this exit jump For More Information On This Product Go to www freescale com ff Tb ff7d ff7f ff81 ff83 ff85 ff87 ff8a ff8c ff91 ff93 ff94 Fh Fh h Fh oO oO WO Oo mh Fh mh Fh w og Fh
364. et request Crystal Monitor reset request and COP Watchdog reset request The type of reset exception request must be decoded by the system and the proper request made to the Core The INT will then provide the service routine address for the type of reset requested 10 4 3 Exception Priority The priority from highest to lowest and address of all exception vectors issued by the INT upon request by the CPU is shown in Table 10 1 below Table 10 1 Exception Vector Map and Priority Vector Address Source FFFE FFFF System reset FFFC FFFD Crystal Monitor reset FFFA FFFB COP reset FFF8 FFF9 Unimplemented opcode trap FFF6 FFF7 Software interrupt instruction SWI or BDM vector request FFF4 FFF5 XIRQ signal FFF2 FFF3 IRQ signal FFF0 FF00 PEA NE A maskable interrupt sources priority in For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 10 5 Modes of Operation The functionality of the INT sub block in various modes of operation is discussed in the subsections that follow 10 5 1 Normal Operation The INT operates the same in all normal modes of operation 10 5 2 Special Operation Interrupts may be tested in special modes through the use of the interrupt test registers as described in 10 3 1 and 10 3 2 previously 10 5 3 Emulation Modes The INT operates the same in emulation modes as in normal modes 10 6 Low Power Options
365. et if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V R7 e R6 e R5 e R4 e R3 e R2 e R1 e RO set if there is a two s complement overflow from the implied subtraction from 0 cleared otherwise two s complement overflow occurs if and only if B 80 C R7 R6 R5 R4 R3 R2 R1 RO set if there is a borrow in the implied subtraction from 0 cleared otherwise set in all cases except when B 00 Code and CPU Source Form ea Code Hex CPU Cycles Cycles For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 N O P Null Operation N O D Operation No operation This single byte instruction increments the PC and does nothing else No other CPU registers are affected NOP typically is used to produce a time delay although some software disciplines discourage CPU frequency based time delays During debug NOP instructions are sometimes used to temporarily replace other machine code instructions thus disabling the replaced instruction s CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex NOP INH A7 O For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc ORAA OR Accumulator A ORAA Operation CCR Effects Code and CPU Cycles A M A or A l imm gt A
366. exing register does not change The 16 bit offset allows access to any address in the 64K byte address space The address bus and the offset are both For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc 16 bits so it does not matter whether the offset is considered to be signed or unsigned FFFF may be thought of as 65 535 or as 1 4 2 7 5 16 Bit Constant Indexed Indirect Addressing This addressing mode calculates the address of a pointer to the effective address It adds a 16 bit offset in two extension bytes to the indexing register X Y SP or PC The value in the indexing register does not change The square brackets distinguish this addressing mode from 16 bit constant offset indexed addressng For this example assume X contains 1000 and the value at address 100A is 2000 LDAA 10 X The value 10 is added to the value in X to form the address 100A The CPU fetches the effective address pointer 2000 from address 100A and loads the value at address 2000 into A 4 2 7 6 Autodecrement Autoincrement Indexed Addressing This addressing mode calculates the effective address by adding an integer value between 8 and 1 or between 1 and 8 to the indexing register X Y or SP The indexing register retains its changed value NOTE Autodecrementing and autoincrementing do not apply to the program counter When predecremented or preincremented the in
367. ey can be thoroughly tested without needing to go through reset 12 4 8 8 Normal Expanded Wide Mode In expanded wide modes Ports A and B are configured as a 16 bit multiplexed address and data bus and Port E bit 4 is configured as the E clock output signal These signals allow external memory and peripheral devices to be interfaced to the system Port E pins other than PE4 ECLK are configured as general purpose I O pins initially high impedance inputs with internal pullup resistors enabled Control bits PIPOE NECLK LSTRE and RDWE in the PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose VO pins It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR but it would be unusual to do so in this mode Development systems where pipe status signals are monitored would typically use the emulation variation of this mode The Port E bit 2 pin can be reconfigured as the R W bus control signal by writing 1 to the RDWE bit in PEAR If the expanded system includes external devices that can be written such as RAM the RDWE bit would need to be set before any attempt to write to an external location If there are no writable resources in the external system PE2 can be left as a general purpose I O pin The Port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writing 1 to the LSTRE bit in PEAR The default condition of t
368. f Scale Semiconductor Inc Address 002D Bit 7 6 Bit O 5 4 3 2 1 BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1VO 0 0 0 0 0 0 Re 0 0 set Reserved or unimplemented Figure 13 8 Breakpoint Second Address Expansion Register BKP1X In Dual Mode this register contains the data to be matched against expansion address lines for the second address breakpoint when a page is selected In Full Mode this register is not used BK1V 5 0 Value of first breakpoint address to be matched in memory expansion space 13 3 7 Breakpoint Data Second Address High Byte Register BKP1H Read anytime Write anytime Address 002E Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 Write Re 0 0 0 0 0 0 0 0 set Figure 13 9 Breakpoint Data High Byte Register BKP1H In Dual Mode this register is used to compare against the high order address lines In Full Mode this register is used to compare against the high order data lines 13 3 8 Breakpoint Data Second Address Low Byte Register BKP1L Read anytime Write anytime For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 dress 002F Bit 7 6 5 4 3 2 1 Bit O Read Bit 7 6 5 4 3 2 1 Bit O Write Reset 0 0 0 0 0 0 0 0 Figure 13 10 Breakpoint Data Low Byte Register BKP1L In Dual Mode this register is used to compare against the low order address lines In Full
369. f data from 2000 to 1007 4 2 7 2 5 Bit Constant Offset Indexed Addressing This addressing mode calculates the effective address by adding a 5 bit signed offset in the postbyte to the indexing register X Y SP or PC The value in the indexing register does not change The 5 bit signed offset gives a range of 16 through 15 from the value in the indexing register The majority of indexed instructions use offsets that fit in the 5 bit offset range For these examples assume X contains 1000 and Y contains 2000 LDAA 0 X The value at address 1000 is loaded into A STAB 8Y The value in B is stored at address 2000 8 or 1FF8 4 2 7 3 9 Bit Constant Offset Indexed Addressing This addressing mode calculates the effective address by adding a 9 bit signed offset in an extension byte to the indexing register X Y SP or PC The value in the indexing register does not change The sign bit of the offset is in the postbyte The 9 bit offset gives a range of 256 through 255 from the value in the indexing register For these examples assume X contains 1000 and Y contains 2000 LDAA SFF X The value at address 10FF is loaded into A LDAB 20 Y The value at address 2000 14 or 1FEC is loaded into B 4 2 7 4 16 Bit Constant Offset Indexed Addressing This addressing mode calculates the effective address by adding a 16 bit offset in two extension bytes to the indexing register X Y SP or PC The value in the ind
370. f the associated Port E pins Port E bit 4 can be configured for a free running E clock output by clearing NECLK 0 Typically the only use for an E clock output while the system is in single chip modes would be to get a constant speed clock for use in the external application system For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 12 4 8 2 Emulation Expanded Narrow Mode Expanded narrow modes are intended to allow connection of single 8 bit external memory devices for lower cost systems that do not need the performance of a full 16 bit external data bus Accesses to internal resources that have been mapped external i e PORTA PORTB DDRA DDRB PORTE DDRE PEAR PUCR RDRIV will be accessed with a 16 bit data bus on Ports A and B Accesses of 16 bit external words to addresses which are normally mapped external will be broken into two separate 8 bit accesses using Port A as an 8 bit data bus Internal operations continue to use full 16 bit data paths They are only visible externally as 16 bit information if IVIS 1 Ports A and B are configured as multiplexed address and data output ports During external accesses address A15 data D15 and D7 are associated with PA7 address AO is associated with PBO and data D8 and DO are associated with PAO During internal visible accesses and accesses to internal resources that have been mapped external address A15 and data D15 is as
371. f there is a borrow in the implied subtraction from 0 cleared otherwise set in all cases except when M 00 Code and CPU Source Form Code Hex CPU Cycles Cycles NEG opr16a 70 hh 11 rPwO NEG oprx0_xysppc 60 xb rPw NEG oprx9 xysppc 60 xb ff rPwO NEG oprx16 xysppc 60 xb ee ff frPwP NEG D xysppc 60 xb flfrPw NEG oprx16 xysppc 60 xb ee ff fIPrPw For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 NEGA Negate A NEGA Operation 0 A A 1 A Replaces the value in A with its two s complement A value of 80 does not change CCR Effects S XH I N ZV C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V R7 e R6 e R5 e R4 e R3 e R2 e R1 e RO set if there is a two s complement overflow from the implied subtraction from 0 cleared otherwise two s complement overflow occurs if and only if A 80 C R7 R6 R5 R4 R3 R2 R1 RO set if there is a borrow in the implied subtraction from 0 cleared otherwise set in all cases except when A 00 Code and CPU Source Form ea Code Hex CPU Cycles Cycles For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc NEGB Negate E NEGB Operation 0 B B 1 B Replaces the value in B with its two s complement A value of 80 does not change CCR Effects S XH I N ZV C N S
372. fetches at the new address 5 3 4 Jumps JMP is the simplest change of flow instruction JMP can use extended or indexed addressing Indexed operations require varying amounts of information to determine the effective address so instruction length varies with the addressing mode The amount of program information fetched also varies with instruction length In all forms of JMP the CPU refills the queue with three program word fetches at the new address 5 4 Instruction Timing The Access Detail column of the summary in Table 5 1 shows how many bytes of information the CPU accesses while executing an instruction With this information and knowledge of the type and speed of memory in the system you can determine the execution time for any instruction in any system Simply count the code letters to determine the execution time of an instruction in a best case system An example of a best case system is a single chip 16 bit system with no 16 bit off boundary data accesses to any locations other than on chip RAM A description of the notation used in each column of the table is given in the subsections that follow including that of the Access Detail column This information as well as the summary in Table 5 1 is repeated from Section 1 of this guide for completeness Table 5 1 Instruction Set Summary Address Mode Machine Coding Hex SXHINZVC Source Form Operation Access Detail ABA Add Bto A A B gt A ABXSame as L
373. ffecting the Z bit CCR Effects S XH I N ZV C Z Set if result is 0000 cleared otherwise Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 DEY Decrement DEY Operation CCR Effects Code and CPU Cycles Y 0001 Y Subtracts one from Y The Z bit reflects the result The LEA Y 1 Y instruction does the same thing as DEY but without affecting the Z bit S X H I N Z V C Z Set if result is 0000 cleared otherwise Address Machine CPU Cycles Source Form Mode Code Hex For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc E D V Extended Divide Unsigned E D IV Operation CCR Effects Code and CPU Cycles Y D X gt Y remainder gt D Divides a 32 bit unsigned dividend by a 16 bit divisor producing a 16 bit unsigned quotient and an unsigned 16 bit remainder All operands and results are located in CPU registers Division by zero has no effect except that the states of the N Z and V bits are undefined S X H I N Z V C N Set if MSB of result is set cleared otherwise undefined after overflow or division by 0 Z Set if result is 0000 cleared otherwise undefined after overflow or division by 0 V Set if the result
374. formation On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc LDX TBL_START LDD DATA_IN TBL A X The notation A X causes the TBL instruction to use the A line segment in the table The low half of D B is used by TBL to calculate the exact data value from this line segment This type of table uses only 257 entries to approximate a table with 16 bits of resolution This type of table has the disadvantage of equal width line segments which means that just as many points are needed to describe a flat portion of the desired function as are needed for the most active portions Another type of table stores x y coordinate pairs for the endpoints of each linear segment This type of table may reduce the table storage space compared to the previous fixed width segments because flat areas of the functions can be specified with a single pair of endpoints This type of table is a little harder to use with the TBL and ETBL instructions because the table instructions expect y values for segment endpoints to be in consecutive memory locations Consider a table made up of an arbitrary number of x y coordinate pairs in which all values have eight bits The table is entered with the x coordinate of the desired point to lookup in the A accumulator When the table is exited the corresponding y value is in the A accumulator Figure B 12 shows one way to work with this type of table
375. freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc LSLB Logical Sift Left B LSLB Operation CCR Effects Code and CPU Cycles 07 b6 b5 ba ba p2 bt bo j 0 B Shifts all bits of B one place to the left Loads bit 0 with 0 Loads the C bit from the most significant bit of B S X H I N Z V C 4 4 4 a4 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C NeC N o C for N and C after the shift set if N is set and C is cleared or N is cleared and C is set cleared otherwise for values of N and C after the shift C B7 set if the LSB of B was set before the shift cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles LSLB INH 58 O For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 LSLD Logical Shift Left D LSLD Operation b7 b6 b5 04 b3 b2 bt po b7 b6 bs b4 b3 be b1 bo je 0 A B Shifts all bits of D one place to the left Loads bit O with 0 Loads the C bit from the most significant bit of A CCR Effects S XH I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V N C N o C N C for N and C after the shift set if N is set and C is cleared or N is cleared and C is set cleared otherw
376. freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 If the WAV instruction is interrupted the internal temporary registers TMP3 TMP2 and TMP1 need to be stored on the stack so that the operation can be resumed Since the WAV instruction includes initialization in cycle 2 0 the recovery path after an interrupt needs to be different The wavr pseudoinstruction has the same opcode as WAV but it is on the first page of the opcode map so it doesn t have the 18 page 2 prebyte that WAV has When WAV is interrupted the PC is adjusted to point at the second byte of the WAV object code so that it is interpreted as the wavr pseudoinstruction on return from the interrupt rather than the WAV instruction During the recovery sequence the PC is readjusted in case another interrupt comes before the weighted average operation finishes For More Information On This Product Go to www freescale com Core User Guide WAV Read program word if 18 misaligned 2 0 f No bus access TMP1 TMP2 TMP3 0000 No bus access B B 1 decrement iteration counter Y Y 1 point at next fuzzy output Read byte 0 Y fuzzy output F Read byte 0 X singleton S X X 1 point at next singleton si2cpu A A8gscale Semiconductor Inc Read word 0 SP unstack TMP1 Read word 0 SP unstack TMP2 Read word 0 SP unstack TMP3 Read byte 1 Y fuzzy output F
377. g e Provides control registers which allow testing of interrupts e Provides additional input signals which prevents requests for servicing I and X interrupts e Wakes the system from stop or wait mode when an appropriate interrupt occurs or whenever XIRQ is active even if XIRQ is masked e Provides asynchronous path for all I and X interrupts FF00 FFF4 e Optional Selects and stores the highest priority I interrupt based on the value written into the HPRIO register For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc 10 1 2 Block Diagram A block diagram of the Interrupt sub block is shown in Figure 10 1 below INT HPRIO OPTIONAL WRITE DATA BUS HIGHEST PRIORITY INTERRUPT INTERRUPTS INTERRUPT INPUT REGISTERS XMASK AND CONTROL REGISTERS READ DATA BUS IMASK WAKEUP a O E oO wi gt o QUALIFIED cr INTERRUPTS INTERRUPT PENDING RESET FLAGS PRIORITY DECODER VECTOR REQUEST VECTOR ADDRESS Figure 10 1 Interrupt Block Diagram 10 2 Interface Signals All interfacing with the Interrupt sub block is done within the Core The Interrupt does however receive direct input from the Multiplexed External Bus Interface MEBI sub block of the Core for the IRQ and XIRQ pin data For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 10 3 Re
378. g of all internal registers When this BDM code is entered all the internal registers such as CCR PC X etc MUST be saved so that they may be restored to the user s value upon an exit from this code DO NOT insert code that affects the user CCR value before it gets saved The code that saves the user CCR should be one of the very first items that occur at the beginning of this code See AR 166 The PC value MUST be checked to s if it was a BDM op 00 instruction that got us into BDM If so PC gets adjusted by 1 This works only if the user enters BDM from locations 0000 thru FEFF because locations S FFOO SFFFF are blocked out for the BDM So the BDM ROM is in the map and not the user s code Any unused space should be set to 00 to ensure ROM is plugged and verified properly Be careful to NOT OVERLAP vector space when filling unused space Using the ZMB directive helps because the assembler version we used just hangs up when code OVERLAPs BUT some other assembler version may not catch this The ROM code size is limited in available space Make sure that when instructions are added the vector space is not overwritten The reset vector was INST_DONE Added code so that after a reset the ccr value at reset is saved because th xit sequence was changing the CCR to the value that was saved before the reset occurred The user should really initialize the CCR but we do it here to avoid confusion he ENBDM bit MUST be set out of reset
379. gisters A summary of the registers associated with the Interrupt sub block is shown in Figure 10 2 below Detailed descriptions of the registers and associated bits are given in the subsections that follow Address Name Bit 7 6 5 4 3 2 1 Bit 0 0015 ITCR a Q 0 0 WRTINT ADR3 ADR2 ADR1 ADRO 0016 ITEST bee INTE INTC INTA INT8 INT6 INT4 INT2 INTO 001F HPRIO ee PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0 Unimplemented X Indeterminate Figure 10 2 Interrupt Register Summary 10 3 1 Interrupt Test Control Register Address 0015 Bit 7 6 5 4 3 2 1 Bit O Read 0 0 0 WRTINT ADR3 ADR2 ADR1 ADRO Write Reset 0 0 0 0 1 1 1 1 Figure 10 3 Interrupt Test Control Register ITCR Read see individual bit descriptions Write see individual bit descriptions WRTINT Write to the Interrupt Test Registers Read anytime Write only in special modes and with I bit mask and X bit mask set 1 Disconnect the interrupt inputs from the priority decoder and use the values written into the ITEST registers instead 0 Disables writes to the test registers reads of the test registers will return the state of the interrupt inputs NOTE Any interrupts which are pending at the time that WRTINT is set will remain until they are overwritten ADR3 ADRO Test register select bits For More Information On This Product Go to www freescale com Core User Guide
380. guage support is the ability to do arithmetic on the stack pointer for such things as allocating local variable space on the stack The LEAS 5 SP instruction is an example of how the compiler could easily allocate five bytes on the stack for local variables LDX 5 SP loads X with the value on the bottom of the stack and deallocates five bytes from the stack in a single operation that takes only two bytes of object code C 7 12 Support for Memory Expansion Bank switching is a common method of expanding memory beyond the 64K byte limit of a CPU with a 64K byte physical address space but there are some known difficulties associated with bank switching For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 One problem is that interrupts cannot take place during the bank switching operation This increases worst case interrupt latency and requires extra programming space and execution time Some HCS12 Core includes a built in bank switching scheme that eliminates many of the problems associated with external switching logic The HCS12 includes CALL and return from call RTC instructions that manage the interface to the bank switching system These instructions are analogous to the JSR and RTS instructions except that the bank page number is saved and restored automatically during execution Since the page change operation is part of an uninterruptable instruction many of the diffi
381. gure 14 2 below Registers are accessed by host driven communications to the BDM hardware using READ_BD and WRITE_BD commands Detailed descriptions of the registers and associated bits are given in the subsections that follow Address FFOO FFO1 FFO2 FFOS FFO4 FFO5 FFO6 FFO7 Register Name Reserved BDMSTS Reserved Reserved Reserved Reserved BDMCCR BDMINR Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Bit 7 6 4 3 2 1 Bit 0 0 A A A ae EP A ENBOM BDMACT SDV TRACE CLKSW USES 9 X a eee ee AA X X X X X X X XIX X i AN A AAA PA ee X X X X X X X eee REG14 peons AEST REG11 0 0 0 E Unimplemented X Indeterminate Figure 14 2 BDM Register Map Summary For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc 14 3 1 BDM Status Register Address FFO1 Bit 7 6 5 4 3 2 1 Bit 0 Read UNSEC 0 ENBDM BDMACT ENTAG SDV TRACE CLKSW Write Reset Special single chip mode 0 4 0 0 0 0 0 0 Special peripheral mode 0 4 0 0 0 0 0 0 All other modes 0 0 0 0 0 0 0 0 Unimplemented Figure 14 3 BDM Status Register BDMST5 Read All modes through BDM operation Write All modes but subject to the following BDMACT can only be set by BD
382. h ROM 64K Allocation For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc 11 5 Motorola Internal Information The subsection aspects of the MMC that are considered to be for Motorola internal use only 11 5 1 Test Registers There are two test registers for the MMC MTST 1 0 These registers are used for internal test purposes to gain visibility into the module select logic In all modes if the FLAGSE bit in MTST1 is set accesses to internal registers or memory will cause the associated flag to assert For example an access into the RAM array will cause the MTO1 bit Bit lin MTSTO RAM Array bit to set These registers can be read in any mode If the FLAGSE bit is set reading the register will cause it to be cleared A write will have no effect in all modes 11 5 1 1 Mapping Test Register 0 MTSTO Address Base 14 Read MTO7 MT06 MTO5 MT04 MTO3 MT02 MT01 MTOO 0 0 0 0 0 0 Unimplemented Figure 11 13 Mapping Test Register Zero MTSTO Write Reset 0 0 Read Anytime Write No effect MTO 7 0 Mapping Test 0 The individual bits are assigned as follows MTO07 Core MTO06 Peripheral MTOS EE Array MT04 EE Register MTOS Flash Array MTO2 Flash Register MTOI RAM Array MTO0 RAM Register This flag bit will not get set when you are accessing any of the MTST registers For More Information On This Product Go to
383. h the program page window from 8000 BFFF MEBI Port K 8 bit Data Register 0033 DDRK MEBI Port K 8 bit Data Direction Register FF01 FF06 C BDMSTS BDM BDM Status Register BDMCCR BDM BDM CCR Holding Register for interaction of BDM with CPU M EFO7 BDMINR BD BDM Internal Register Position Register to configure BDM register mapping For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPuU15UG V1 2 Section 4 Instructions This section describes the instruction set of the Core This discussion includes descriptions of instructions grouped by type the addressing modes used and the opcode map Please refer to Appendix A of this guide for a detailed instruction by instruction description of each opcode 4 1 Instruction Types All memory and I O are mapped in a common 64K byte address space allowing the same set of instructions to access memory I O and control registers Load store transfer exchange and move instructions facilitate movement of data to and from memory and peripherals There are instructions for signed and unsigned addition division and multiplication with 8 bit 16 bit and some larger operands Special arithmetic and logic instructions aid stacking operations indexing BCD calculation and condition code register manipulation There are also dedicated instructions for multiply and accumulate operations table interpolation and specialized
384. han the value in A Rel is a 16 bit two s complement offset for branching forward or backward in memory Branching range is 8000 to 7FFF 32768 to 32767 from the address following the last byte of object code in the instruction S X H I N Z V C Address Machine Source Form Mode Code Hex CPU Cycles LBHI rel16 REL 18 22 qq rr OPPP branch OPO no branch Branch Complementary Branch Comment Mnemonic Opcode Test Mnemonic Opcode Test R gt M R lt M or or LBHI 18 22 B gt A LBLS 18 23 B lt A Unsigned C Z 0 C Z 1 R gt M R lt M or or LBGT 182E B gt A LBLE 18 2F B lt A Signed Z NOV 0 Z NOV 1 For More Information On This Product Go to www freescale com LBHS If C 0 then PC 0004 rel PC Operation CCR Effects Code and CPU Cycles LBHS can be used to branch after subtracting or comparing unsigned values After CMPA CMPB CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the CPU register value is greater than or equal to the value in M After CBA or SBA the Freescale Semiconductor WOE Guide Long Branch if Higher or Same same as LBCC branch occurs if the value in B is greater than or equal to the value in A Rel is a 16 bit two s complement offset for branching forward or backward in memory Branching range is 8000 to 7FFF 32768 to 32767 from the add
385. he 16 bit value 0067 because the CPU expects a 16 bit value in the instruction stream BRSET FOO 03 THERE In this example extended addressing is used to access the operand FOO immediate addressing is used to access the mask value 03 and relative addressing is used to identify the destination address of a branch in case the branch taken conditions are met BRSET is listed as an extended mode instruction even though immediate and relative modes are also used 4 2 4 Direct Addressing Mode This addressing mode is sometimes called zero page addressing because it accesses operands in the address range 0000 through 00FF Since these addresses always begin with 00 only the low byte of the address needs to be included in the instruction which saves program space and execution time A system can be optimized by placing the most commonly accessed data in this area of memory The low byte of the operand address is supplied with the instruction and the high byte of the address is assumed to be zero LDAA 55 The value 55 is taken to be the low byte of an address in the range 0000 through 00FF The high byte of the address is assumed to be zero During execution the CPU combines the value 55 from the instruction with the assumed value of 00 to form the address 0055 which is then used to access the data to be loaded into accumulator A LDX 20 In this example the value 20 is combined with the assumed value of 00 to f
386. he bit by bit output buffer enable signal to the system port pad logic for Port B 7 2 2 10 Port B input buffer enable from Core core_pbibe_t2 This single bit output from the Core provides the input buffer enable signal to the system port pad logic for Port B 7 2 2 11 Port B pullup enable from Core core_pbpue_t2 This single bit output from the Core indicates that the pullup devices within the system port pad logic for Port B should be enabled for all Port B pins 7 2 2 12 Port B drive strength enable from Core core_pbdse_t2 This single bit output from the Core indicates whether all Port B pins will operate with full or reduced drive strength 7 2 2 13 Port E Input Data to Core core_peind 7 0 This 8 bit wide input to the Core provides the Core with the input data from the system port pad logic for Port E When the system has an external IRQ pin implemented the input signal from the IRQ pin pad logic must be tied to Port E Input Data Bit 1 Likewise when the system has an external XIRQ pin implemented the input signal from the XIRQ pin pad logic must be tied to Port E Input Data Bit 0 Both the IRQ and XIRQ signals are active low i e their asserted state is logic 0 7 2 2 14 Port E Output Data from Core core_pedo 7 0 This 8 bit wide output from the Core provides the Port E data output to the system port pad logic for Port E 7 2 2 15 Port E output buffer enable from Core core_peobe 7 0 This 8 bit wide output
387. he divisor and the dividend are assumed to have radix points in the same positions the radix point of the quotient is to the right of bit 0 In the case of division by 0 the quotient is set to SFFFF and the remainder is indeterminate S X H I N Z V C Z Set if quotient is 0000 cleared otherwise V Cleared C X15 e X14 X13 e X12 e X3 e X2 e X1 e X0 set if denominator is 0000 cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles IDIV INH 18 10 OffffffffffO For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc D IVS Integer Divide Signed D IVS Operation CCR Effects Code and CPU Cycles D X gt X remainder gt D Divides a signed 16 bit dividend in D by a signed 16 bit divisor in X Puts the signed 16 bit quotient in X and the signed 16 bit remainder in D If division by 0 is attempted the values in D and X do not change but the N Z and V bits are undefined Other than division by 0 which is not legal and sets the C bit the only overflow case is 2000 _ 92780 _ sso But the highest positive value that can be represented in a 16 bit two s complement number is 32 767 7FFFF S X H I N Z V C 4 4 4 a4 N Set if MSB of quotient is set cleared otherwise undefined after overflow or division by 0 Z Set if quotient is 0000 clear
388. hen transfers control to a subroutine Uses the address of the instruction following the JSR as a return address Decrements SP by two to allow the two bytes of the return address to be stacked Stacks the return address SP points to the high byte of the return address Calculates an effective address according to the rules for extended direct or indexed addressing Jumps to the location determined by the effective address Subroutines are normally terminated with an RTS instruction which restores the return address from the stack S X H I N Z V C Address Machine Source Form Mode Code Hex CPU Cycles JSR opr8a DIR 17 dd SPPP JSR opr16a EXT 16 hh 11 SPPP JSR oprx0_xysppc IDX 15 xb PPPS JSR oprx9 xysppc IDX1 15 xb ff PPPS JSR oprx16 xysppc IDX2 15 xb ee ff fPPPS JSR D xysppc D IDX 15 xb fIfPPPS JSR oprx16 xysppc IDX2 15xbee ff fIfPPPS For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 LBCC mal ena LBCC Operation If C 0 then PC 0004 rel PC Tests the C bit and branches if C 0 CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex LBCC rel16 18 24 qq rr OPPP branch OPO no branch Branch Complementary Branch Comment Mnemonic Mnemonic Opcode Test O LBCC LBHS LBCS LBLO Unsigned LBGE For More Information On This Product
389. his Product Go to www freescale com P branch no branch PP branch P no branch Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Source Form BRCLR opr8a msk8 rel8 BRCLR opr16a msk8 rel8 BRCLR oprx0_xysppc msk8 rel8 BRCLR oprx9 xysppc msk8 rel8 BRCLR oprx16 xysppc msk8 rel8 BRN rel8 Operation Branch if bit s clear if M e mask byte 0 then PC 2 rel gt PC Branch never Address Mode Machine Coding Hex 4F dd mm rr 1F hh11mmrr OF xb mm rr OF xb ff mmrr OF xb ee ff mmrr 21r E Access Detail SXHINZVC BRSET opr8 msk8 rel8 BRSET opr16a msk8 rel8 BRSET oprx0_xysppc msk8 rel8 BRSET oprx9 xysppc msk8 rel8 BRSET oprx16 xysppc msk8 rel8 Branch if bit s set if M e mask byte 0 then PC 2 rel gt PC 4E dd mm rr 1Ehh11mmrr OE xb mm rr OE xb ff mmrr OE xb ee ff mmrr BSET opr8 msk8 BSET opr16a msk8 BSET oprx0_xysppc msk8 BSET oprx9 xysppc msk8 BSET oprx16 xysppc msk8 Set bit s in M M mask byte M 4C dd mm 1C hh 11mm OC xb mm OC xb f f mm OC xb ee f f mm BSR rel8 Branch to subroutine SP 2 SP RTNy RTN_ gt Mgp Mgp 4 PC 2 rel gt PC Branch if V clear if V 0 then PC 2 rel gt PC 07 r r PPP branch P no branch
390. his allows enough time for the requested data to be made available in the BDM shift register ready to be shifted out For firmware write commands the external host must wait 32 target clock cycles after sending the data to be written before attempting to send anew command This is to avoid disturbing the BDM shift register before the write has been completed The external host should wait 64 target clock cycles after a TRACE1 or GO command before starting any new serial command This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the user code Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table Figure 14 6 represents the BDM command structure The command blocks illustrate a series of eight bit times starting with a falling edge The bar across the top of the blocks indicates that the BKGD line idles in the high state The time for an 8 bit command is 8 x 16 target clock cycles 8 BITS 16 BITS 150 TC 16 BITS AT 16TC BIT AT 16 TC BIT DELAY AT 16 TC BIT HARDWARE NEXT READ COMMAND ADDRESS COMMAND 150 TC DELAY HARDWARE NEXT WEE COMMAND ADDRESS DATA COMMAND 32 TC DELAY FIRMWARE NEXT READ COMMAND COMMAND 32 TC DELAY FIRMWARE NEXT WRITE COMMAND DATA COMMAND 64 TC DELAY GO NEXT TRACE COMMAND COMMAND TC TARGET CLOCK CYCLES Figure 14 6 BDM Command Structure NOTES
391. his pin is a general purpose input because the LSTRB function is not needed in all expanded wide applications The Port E bit 4 pin is initially configured as ECLK output with stretch The E clock output function depends upon the settings of the NECLK bit in the PEAR register the VIS bit in the MODE register and the ESTR bit in the EBICTL register The E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system 12 4 9 Internal Visibility Internal visibility is available when the system is operating in expanded wide modes special test mode or emulation narrow mode It is not available in single chip peripheral or normal expanded narrow modes Internal visibility is enabled by setting the VIS bit in the MODE register If an internal access is made while E R W and LSTRB are configured as bus control outputs and internal visibility is off IVIS 0 E will remain low for the cycle R W will remain high and address data and the LSTRB pins will remain at their previous state When internal visibility is enabled IVIS 1 certain internal cycles will be blocked from going external to prevent possible corruption of external devices Specifically during cycles when the BDM is selected R W will remain high data will maintain its previous state and address and LSTRB pins will be updated For More Information On This Product Go to www freescale com Core User
392. ible this eliminates the need to separately mask off interrupts during the context switch The HCS12 has dedicated signal lines that allow the CPU to access the bank page register without having to use an address in the normal 64K byte address space This eliminates the need for the program to know where the page register is physically located The RTC instruction is similar to the RTS instruction except that RTC uses the byte of information that was saved on the stack by the corresponding CALL instruction to restore the bank page register to its old value A CALL RTC pair can be used to access any function subroutine on any page But when the called subroutine is on the current page or in an area of memory that is always visible it is more efficient to access it with JSR RTS instructions Push and pull instructions can be used to stack some or all the CPU registers during a function call The HCS12 CPU can push and pull any of the CPU registers A B D CCR X Y or SP 4 4 9 Instruction Set Orthogonality One very helpful aspect of the HCS12 instruction set orthogonality is difficult to quantify in terms of direct benefit to an HLL compiler Orthogonality refers to the regularity of the instruction set A completely orthogonal instruction set would allow any instruction to operate in any addressing mode would have identical code sizes and execution times for similar operations and would include both signed and unsigned versions of all mathe
393. icated when an interrupt request or tagged instruction alters program flow SWI and TRAP instructions are part of normal program flow and are indicated as start even or start odd depending on their alignment Since they are present in the queue they can be tracked in an external queue rebuild An external event that interrupts program flow is indeterministic Program data is not present in the queue until after the vector jump e Start even instruction The current opcode is in the high byte of stage three of the queue e Start odd instruction The current opcode is in the low byte of stage three of the queue Table 5 9 IPIPE 1 0 Decoding when E Clock is High Data Movement capture at E fall Mnemonic Meaning 0 0 No movement For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc Table 5 9 IPIPE 1 0 Decoding when E Clock is High Data Movement 1 1 capture at E fall Mnemonic Meaning 0 1 Reserved 1 0 ALD Advance queue and load from bus Reserved Table 5 10 IPIPE 1 0 Decoding when E Clock is Low reo eo Mnemonic Meaning 0 0 No start 0 1 INT Start interrupt sequence 1 0 SEV Start even instruction 1 1 SOD Start odd instruction The execution start status signals are delayed by one E clock cycle to allow a lagging program fetch and queue advance Therefore the execution start stat
394. ich uses 16 bit input operands and accumulates the sum to a 32 bit memory location One benefit of the WAV instruction is that both a sum of products and a sum of weights are maintained while the fuzzy output operand is only accessed from memory once Since memory access time is such a significant part of execution time this provides a speed advantage over conventional instructions The weighted average of singletons is the most commonly used technique in microcontrollers because it 1s computationally less difficult than most other methods The simplest method is called max defuzzification which simply uses the largest fuzzy output as the system result However this approach does not take into account any other fuzzy outputs even when they are almost as true as the chosen max output Max defuzzification is not a good general choice because it only works for a subset of fuzzy logic applications The HCS12 CPU is well suited for more computationally challenging algorithms than weighted average A 32 bit by 16 bit divide instruction takes eleven or twelve 8 MHz cycles for unsigned or signed variations A 16 bit by 16 bit multiply with a 32 bit result takes only three 8 MHz cycles The EMACS instruction uses 16 bit operands and accumulates the result in a 32 bit memory location taking only twelve 8 MHz cycles per iteration including accessing all operands from memory and storing the result to memory For More Information On This Product Go to ww
395. ides the input buffer enable signal to the system port pad logic for the BDM BKGD pin 7 2 6 5 BKGD pin pullup enable from Core core_bkgdpue_t2 This single bit output from the Core indicates that the pullup device within the system port pad logic for the BKGD pin should be enabled for the BKGD pin 7 2 7 Memory Configuration Signals These input signals to the Core establish the system memory configuration Each of these signals is to be tied off to the appropriate logic state at integration of the Core into the SoC design in order to configure the Core memory partitioning according to the needs of the system Please consult the HCS12 V1 5 Core Integration Guide for details on defining the states of these signals 7 2 8 Scan Control Interface Signals These descriptions apply to the Core Scan test control signals 7 2 8 1 Scan mode enable ipt_scan_mode This single bit input indicates to the Core that the system is in Scan test mode and all logic within the Core that needs special conditions for Scan test mode will be handled appropriately 7 3 Interface Operation The subsections below give general descriptions of basic read and write operations of the Core These operations include interfacing with system peripheral registers on chip memory registers and array elements internal Core registers and external bus interface For more detailed descriptions and timing information please consult the HCS12 V1 5 Core Integration Guide 7 3 1 R
396. ied to Port E Input Data Bit 0 Both the IRQ and XIRQ signals are active low i e their asserted state is logic 0 12 2 1 14 Port E Output Data from Core core_pedo 7 0 This 8 bit wide output from the Core provides the Port E data output to the system port pad logic for Port E 12 2 1 15 Port E output buffer enable from Core core_peobe 7 0 This 8 bit wide output from the Core provides the bit by bit output buffer enable signal to the system port pad logic for Port E 12 2 1 16 Port E input buffer enable from Core core_peibe_t2 This single bit output from the Core provides the input buffer enable signal to the system port pad logic for Port E 12 2 1 17 Port E pullup enable from Core core_pepue_t2 This single bit output from the Core indicates whether or not the pullup devices within the system port pad logic for Port E should be enabled for all Port E pins except the MODA PE5 and MODB PE6 pins 12 2 1 18 Port E MODE pin pullup enable from Core core_mdrste This single bit output from the Core indicates that the pullup devices within the system port pad logic for the MODA PES and MODB PE6 pins within Port E should be enabled 12 2 1 19 Port E drive strength enable from Core core_pedse_t2 This single bit output from the Core indicates whether all Port E pins will operate with full or reduced drive strength 12 2 1 20 Port K Input Data to Core core_pkind 7 0 This 8 bit wide input to the Core provides the
397. if BDM becomes active before or after execution of the next instruction NOTE Ifan attempt is made to activate BDM before being enabled the CPU resumes normal instruction execution after a brief delay If BDM is not enabled any hardware BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed In active BDM the BDM registers and standard BDM firmware lookup table are mapped to addresses FFOO to FFFF BDM registers are mapped to addresses FFOO to FFO7 The BDM uses these registers which are readable anytime by the BDM These registers are not however readable by user programs 14 4 3 BDM Hardware Commands Hardware commands are used to read and write target system memory locations and to enter active background debug mode Target system memory includes all memory that is accessible by the CPU such as on chip RAM EEPROM Flash EEPROM I O and control registers and all external memory Hardware commands are executed with minimal or no CPU intervention and do not require the system to be in active BDM for execution although they can still be executed in this mode When executing a hardware command the BDM sub block waits for a free CPU bus cycle so that the background access does not disturb the running application program If a free cycle is not found within 128 clock cycles the CPU is momentarily frozen so that the BDM can steal a cycle When the BDM finds a free cycle the operation does not intrude on normal CPU
398. if C set if C 1 then PC 4 rel gt PC Long branch if equal if Z 1 then PC 4 rel gt PC 1824gqq rr 1825qq rr 1827 qqrr p branch no branch P branch no branch P branch no branch LBGE rel16 LBGT re 16 LBHI re 16 Long branch if gt 0 signed If NOVO then PC 4 rel gt PC Long branch if gt 0 signed If Z NOV 0 then PC 4 rel gt PC Long branch if higher unsigned If C Z 0 then PC 4 rel PC 182C gg rr 182E qq rr 1822qqrr p branch no branch PPP branch PO no branch PO no branch LBHS rel16Same as LBCC LBLE rel16 Long branch if higher or same unsigned If C 0 PC 4 rel gt PC Long branch if lt 0 signed if Z NOV 1 then PC 4 rel gt PC 1824gqq rr 18 2F qq rr P branch no branch PPP branch no branch O O O O O O O O O OPPP branch O O O O O O O O O LBLO rel16Same as LBCS Long branch if lower unsigned if REL 1825 qqrr PPP branch oe 9 a pe a pa C 1 then PC 4 rel gt PC PO no branch LBLS re 16 Long branch if lower or same REL 1823 qqrr PPP branch _ _ _ unsigned If C Z 1 then PO no branch PC 4 rel gt PC LBLT rel16 Long branch if lt 0 signed REL 182Dqqrr OPPP branch o alee If NOV 1 then PC 4 rel gt PC OPO no bra
399. ill be blocked In addition while in secured mode all internal visibility VIS and CPU pipe IPIPE information will be blocked from output 15 4 3 Unsecuring The System To unsecure a system that is configured for secured mode the internal on chip Flash EEPROM and EEPROM must be fully erased This can be performed using one of the following methods 1 Reset the microcontroller into SPECIAL TEST mode execute a program which writes the Mass Erase command sequence into the Flash and EEPROM Command registers 2 Reset the microcontroller into SPECIAL SINGLE CHIP mode delay while the erase test is performed by the BDM secure ROM Send BDM commands to write the Mass Erase command sequence into the Flash and EEPROM Command registers 3 Reset the microcontroller into SPECIAL PERIPHERAL mode using SPM commands write the Mass Erase command sequence into the Flash and EEPROM Command registers For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc In all modes the mass erase command sequence must have the following steps a Write FCLKDIV register to set the Flash clock for proper timing b Write 00 to FCNFG register to select Flash block 0 c Write 10 to FTSTMOD register to set WRALL bit with WRALL set all of the following writes to banked Flash registers will affect all Flash blocks Disable Flash protection by writing the FPROT register Write any data to Flash m
400. immer 26 July 2000 Enable BDM hardware commands when NVM erase verify fails BDM commands will remain disabled if Flash security bits 01 Design Strategy This code determines if the FLASH and EEPROM are erased If they are both erased the program releases security else it hangs branches to self KKK KKK KKK KKK KKK KKK KK KKK KK KKK KKK KKK KKK KKK KK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK Equates here KKK KKK KKK KKK KKK KK KKK KK KKK KKK KKK KKK KKK KKK KK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK 001c 0030 0012 ff01 ff20 fff6 MEMSIZO equ 001C PPAGE equ 0030 INITEE equ 0012 BDMSTS equ SFFOL BDMSTAR equ SFF20 VECTORS equ SFFF6 KKK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KEK KKK KK KKK KKK KKK KKK KKK KK KK For More Information On This Product Go to www freescale com 12CPU15UG V1 2 Core User Guide siocpursuen scale Semiconductor Inc Code starts here ff80 org SFF80 ff80 START equ x Verify the FLASH is erased all ones Initialization ff80 ce 00 00 ldx 0000 needed for indexing ff83 86 3f ldaa 3F ff85 5a 30 staa PPAGE start with last page ff87 cc bf fe ldd FSBFFE last word in page A We check every 128th word then change Page ff8a ed e6 FLOOP ldy D X read word from FLASH ff8c 02 iny erased will become 0000 ff8d 26 36 bne FAIL not blank gt done
401. in the Core interface boundary The functional descriptions of the pins are provided below for completeness e BKGD Background interface pin e TAGHI High byte instruction tagging pin e TAGLO Low byte instruction tagging pin BKGD and TAGHI share the same pin TAGLO and LSTRB share the same pin 14 2 1 Background Interface Pin BKGD Debugging control logic communicates with external devices serially via the single wire background interface pin BKGD During reset this pin is a mode select input which selects between normal and special modes of operation After reset this pin becomes the dedicated serial interface pin for the background debug mode 14 2 2 High Byte Instruction Tagging Pin TAGHI This pin is used to tag the high byte of an instruction When instruction tagging is on a logic 0 at the falling edge of the external clock ECLK tags the high half of the instruction word being read into the instruction queue For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 14 2 3 Low Byte Instruction Tagging Pin TAGLO 12CPU15UG V1 2 This pin is used to tag the low byte of an instruction When instruction tagging is on and low strobe is enabled a logic 0 at the falling edge of the external clock ECLK tags the low half of the instruction word being read into the instruction queue 14 3 Registers A summary of the registers associated with the BDM is shown in Fi
402. ine Source Form CPU Cycles Cycles Mode Code Hex TSTA INH 97 O For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc TSTB Test B TSTB Operation CCR Effects Code and CPU Cycles B 00 Subtracts 00 from the value in B The condition code bits reflect the result The value in B does not change The TSTB instruction provides limited information when testing unsigned values Since no unsigned value is less than 0 BLO and BLS have no utility following TSTB While BHI can be used after TST it performs the same function as BNE which is preferred After testing signed values all signed branches are available S X H l N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared C Cleared Address Machine Source Form Mode Code Hex CPU Cycles TSTB INH D7 O For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPuU15UG V1 2 TSX Transfer SP to X TSX same as TFR SP X Operation SP X Transfers the value in SP to X The value in SP does not change After a TSX instruction X points at the last value that was stored on the stack TSX assembles as TFR SP X CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex TSX INH B7 75 P
403. ing allowed Exclusive ORA A M gt A or A imm gt A Exclusive ORB B M gt B or B imm gt B Extended table lookup and interpolate 16 bit M M 1 B x M 2 M 3 M M 1 gt D D8 dd F8hh11 E8 xb E8 xb ff E8 xbee ff E8 xb E8 xbee ff h fractional part of lookup value initialize index register to point to first tal P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf ORRffffffP EXG abcdxysp abcdxysp Exchange register contents r1 e r2 r1 and r2 same size 00 r1 r2r1 8 bit r2 16 bit 11 e r2 r1 16 bit r2 8 bit INH B7 eb Fractional divide D X X remainder D 16 by 16 bit For More Information On This Product Go to www freescale com OffffffffffO Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Source Form IBEQ abdxysp rel9 IBNE abaxysp rel9 Operation Increment and branch if equal to 0 counter 1 counter If counter 0 then branch Increment and branch if not equal to 0 counter 1 counter If counter 0 then branch Address Mode Machine Coding Hex Access Detail SXHINZVC branch no branch PPP branch PPO no branch IDIVS Integer divide unsigned D
404. ing edge of peri_clk24 and will then output the clock signal being input on peri_test_clk directly on Port E Bit 6 of the system This test feature is only valid in Special modes and setting of the PIPOE bit in the PEAR register overrides the clock output For More Information On This Product Go to www freescale com Core User Guide si2cpu ERA Scale Semiconductor Inc 8 1 4 HCS12 CPU Wait and Stop Modes The Core inputs peri_cwai_t3 and peri_syswai_t3 indicate to the Core what the state of the system clocks will be during CPU wait mode with the former reflecting the Core clock peri_clk24 state and the latter the state of all system clocks These inputs typically come from the clock and reset generation block s and could either be hard wired to a given logic value or reflect the state of software bits controlling the clock functionality The Core assumes that the asserted logic 1 state indicates that the clock s will cease during wait mode and that the negated logic 0 state indicates that the clock s will run during wait mode The Core will reflect the CPU mode through the state of the core_wait_t24 and core_stop_t24 signals The core_wait_t24 or core_stop_t24 signal will assert when the CPU executes a WAI or STOP instruction respectively and both will remain negated logic 0 during normal operation In the case of exit from either wait or stop mode due to a valid interrupt the core_wakeup_ta signal will assert logic 1 asynchronous
405. ion CCR Effects Code and CPU Cycles A B gt A si2cpu A A8gscale Semiconductor Inc Subtract B from A S B A Subtracts the value in B from the value in A and puts the result in A The value in B is not affected The C bit represents a borrow S X H I N Z V C A AJTAJA N Set if MSB of result is set cleared otherwise Z Set if result is 0 0 cleared otherwise V A7 B7 R7 A7 B7 e R7 set if a two s complement overflow resulted from the operation cleared otherwise C A7 B7 B7 R7 R7 e A7 set if the absolute value of B is larger than the absolute value of A cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles SBA INH 18 16 00 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 SBCA Subtract with Cary from A SBCA Operation CCR Effects Code and CPU Cycles A M C gt A or A imm C gt A Subtracts either the value in M and the C bit or an immediate value and the C bit from the value in A Puts the result in A The C bit represents a borrow S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V A7e M7 e R7 A7 e M7 e R7 set if a two s complement overflow resulted from the operation cleared otherwise C A7 e M7 M7 R7 R7 A7 set if the absolute value of the content of me
406. ion byte IDX2 16 bit signed offset from X Y SP or PC 2 extension bytes IDX2 Indexed indirect 16 bit offset from X Y SP or PC D IDX Indexed indirect accumulator D offset from X Y SP or PC For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 5 4 5 Machine Code Notation In the Machine Code Hex column of the summary in Table 5 1 digits 0 9 and upper case letters A F represent hexadecimal values Pairs of lower case letters represent 8 bit values as shown in Table 5 6 Table 5 6 Machine Code Notation dd 8 bit direct address from 0000 to 00FF high byte is 00 ES High byte of a 16 bit constant offset for indexed addressing b Exchange transfer postbyte Low eight bits of a 9 bit signed constant offset in indexed addressing or low byte of a 16 bit constant offset in indexed addressing High byte of a 16 bit extended address 8 bit immediate data value High byte of a 16 bit immediate data value Low byte of a 16 bit immediate data value Loop primitive DBNE postbyte Low byte of a 16 bit extended address 8 bit immediate mask value for bit manipulation instructions bits that are set indicate bits to be affected Log Program page or bank number used in CALL instruction qq High byte of a 16 bit relative offset for long branches tn Trap number from 30 to 39 or from 40 to FF Signed relative offset 80
407. ional constant supplied by the program or an accumulator value to the current value in X Y SP or PC LEAS does not alter condition code bits This allows stack modification without disturbing CCR bits changed by recent arithmetic operations When SP is the indexing register a predecrement or preincrement LEAS loads SP with the changed value A postdecrement or postincrement LEAS does not affect the value in SP CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex LEAS oprx0_xysppc 1B xb LEAS oprx9 xysppc 1B xb ff LEAS oprx16 xysppc 1B xbee ff For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc LEAX Load Effective Address into X LEAX Operation Effective address gt X Loads X with an effective address specified by the program The effective address can be any indexed addressing mode operand address except an indirect address Indexed addressing mode operand addresses are formed by adding an optional constant supplied by the program or an accumulator value to the current value in X Y SP or PC When X is the indexing register a predecrement or preincrement LEAX loads X with the changed value A postdecrement or postincrement LEAX does not affect the value in X CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex LEAX oprx0_xysppc 1A xb LE
408. ions of the jump instruction At the time the JMP D PC instruction is executed PC points to the address GO1 and D holds one of the values 0000 0002 or 0004 determined by the program some time before the JMP Assume that the value in D is 0002 The JMP instruction adds the values in D and PC to form the address of GO2 Next the CPU reads the address PLACE2 from memory at GO2 and jumps to PLACE2 The locations of PLACE through PLACE3 were known at the time of program assembly but the destination of the JMP depends upon the value in D computed during program execution 4 2 8 Instructions Using Multiple Modes Several instructions use more than one addressing mode in the course of execution For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc 4 2 8 1 Move Instructions Move instructions can use one addressing mode to access the source of the move and another addressing mode to access the destination There are move variations for most combinations of immediate extended and indexed addressing modes The only combinations of addressing modes that are not allowed are those with an immediate mode destination the operand of an immediate instruction is data not an address For indexed moves the indexing register can be X Y SP or PC Move instructions do not have indirect modes or 9 bit or 16 bit offset modes 4 2 8 2 Bit Manipulation Instructions Bit manipulati
409. is cycle the CPU begins the interrupt service routine by executing the instruction at the head of the instruction queue At the end of the interrupt service routine an RTI instruction restores the stacked registers and the CPU returns to the return address RTI is an 8 cycle instruction when no other interrupt is pending and an 11 cycle instruction when another interrupt is pending In either case the first five cycles are used to pull the CCR B A X Y and the return address from the stack If no other interrupt is pending at this point three program words are fetched to refill the instruction queue from the area of the return address and processing proceeds from there If another interrupt is pending after registers are restored a new vector is fetched and the stack pointer is adjusted to point at the CCR value that was just recovered SP SP 9 This makes it appear that the registers have been stacked again After the SP is adjusted three program words are fetched to refill the instruction queue starting at the address the vector points to Processing then continues with execution of the instruction at the head of the queue 6 2 Exception Vectors Each exception has a 16 bit vector that points to the memory location where the routine that handles the exception is located Vectors are stored in the upper 128 bytes of the standard 64K byte address map and are prioritized as shown in Table 6 1 below from highest system reset to lowe
410. ise for values of N and C after the shift C D15 set if the MSB of D was set before the shift cleared otherwise Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc LSR Operation CCR Effects Code and CPU Cycles Logical Shift Right M LS R o b7 e bS ba b3 b2 bt o0 M Shifts all bits of M one place to the right Loads bit 7 with 0 Loads the C bit from the least significant bit of M S X H I N Z V C o 4 4 a N Cleared Z Set if result is 00 cleared otherwise V NO C N e C N C for N and C after the shift set if N is set and C is cleared or N is cleared and C is set cleared otherwise for values of N and C after the shift C MO set if the LSB of M was set before the shift cleared otherwise Machine Source Form Code Hex CPU Cycles LSR opri6a hh 11 rPwO LSR oprx0_xysppc xb rPw LSR oprx9 xysppc xb ff rPwO LSR oprx16 xysppc xb ee ff frPwP LSR D xysppc xb flfrPw LSR oprx16 xysppc xb ee ff fIPrPw For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 LS RA Logical Shift Right A LS RA Operation 0 b7 b6 b5 b4 b3 b2 bt bo A Shifts all bits of A one place to the right Loads bit 7 with 0 Loads the
411. ister is writable one time This allows a user program to change the bus mode to narrow or wide expanded mode and or turn on visibility of internal accesses Port E bit 4 can be configured for a free running E clock output by clearing NECLK 0 Typically the only use for an E clock output while the system is in single chip modes would be to get a constant speed clock for use in the external application system 12 4 8 6 Normal Expanded Narrow Mode This mode is used for lower cost production systems that use 8 bit wide external EPROMs or RAMs Such systems take extra bus cycles to access 16 bit locations but this may be preferred over the extra cost of additional external memory devices Ports A and B are configured as a 16 bit address bus and Port A is multiplexed with data Internal visibility is not available in this mode because the internal cycles would need to be split into two 8 bit cycles Since the PEAR register can only be written one time in this mode use care to set all bits to the desired states during the single allowed write The PE3 LSTRB pin is always a general purpose I O pin in normal expanded narrow mode Although it is possible to write the LSTRE bit in PEAR to 1 in this mode the state of LSTRE is overridden and Port E bit 3 cannot be reconfigured as the LSTRB output It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR but it would be unusual to do so in this mo
412. ithin the page allows values calculated at run time rather than immediate values that must be known at the time of assembly The RTC instruction terminates subroutines invoked by a CALL instruction RTC unstacks the PPAGE value and the return address and refills the queue Execution resumes with the next instruction after the CALL During the execution of an RTC instruction the CPU e Pulls the old PPAGE value from the stack e Pulls the 16 bit return address from the stack and loads it into the PC e Writes the old PPAGE value into the PPAGE register For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 e Refills the queue and resumes execution at the return address This sequence is uninterruptable an RTC can be executed from anywhere in memory even from a different page of extended memory in the expansion window The CALL and RTC instructions behave like JSR and RTS except they use more execution cycles Therefore routinely substituting CALL RTC for JSR RTS is not recommended JSR and RTS can be used to access subroutines that are on the same page in expanded memory However a subroutine in expanded memory that can be called from other pages must be terminated with an RTC And the RTC unstacks a PPAGE value So any access to the subroutine even from the same page must use a CALL instruction so that the correct PPAGE value is in the stack 11 4 3 2 Extended Address XAB
413. k is shown in Figure 13 2 below Detailed descriptions of the registers and bits are given in the subsections that follow Address Name 0028 BKPCTO 0029 BKPCT1 002A BKPOX 002B BKPOH 002C BKPOL 002D BKP1X 002E BKP1H 002F BKPIL read write read write read write read write read write read write read write read write Bit 7 6 5 4 3 2 1 Bit 0 BKEN BKFULL BKBDM BKTAG 0 y BKOMBH BKOMBL BK1MBH BK1MBL BKORWE BKORW BK1RWE BK1RW y BKOV5 BKOV4 BKOV3 BKOV2 BKOV1 BKOVO Bt7 6 5 4 Bit 0 E 2 BK1V5 BK1V4 BKiva exive Bkivi BK1VO Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit O Unimplemented X Indeterminate Figure 13 2 Breakpoint Register Summary 13 3 1 Breakpoint Control Register 0 BKPCTO Read anytime Write anytime For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Address 0028 Bit 7 6 5 4 3 2 1 Bit 0 BKEN BKFULL BKBDM BKTAG Reset 0 0 0 0 0 0 0 0 Reserved or unimplemented Figure 13 3 Breakpoint Control Register 0 BKPCTO This register is used to set the breakpoint modes BKEN Breakpoint Enable This bit enables the module 0 Breakpoint module off 1 Breakpoint module on BKFULL Full Breakpoint Mode Enable This bit controls whether the breakpoint module is in Dual
414. l find smallest rule input store to rule outputs unless fuzzy output is larger Special 18 3B ORf t Tx O or ORF r ffR O TLELFOREE FEEETORE TA SRF With weighting not enabled the t Tx loop is executed once for each element in the rule list The denotes a check for pending interrupt requests With weighting enabled the t Tx loop is replaced by r ffRf Additional cycles caused by an interrupt when weighting is not enabled ff ff is the exit sequence and ORft is the re entry sequence Additional cycles caused by an interrupt when weighting is enabled f ff is the exit sequence and ORfr is the re entry sequence ROL opr16a ROL oprx0_xysppc ROL oprx9 xysppc ROL oprx16 xysppc ROL D xysppc ROL oprx16 xysppc Rotate left M i H C b7 Rotate left A Rotate left B 75hh11 65 xb 65xb ff 65xbee ff 65 xb 65xbee ff 45 55 rPwO rPw rPwO frPwP fIfrPw fIPrPw O O ROR opr16a ROR oprx0_xysppc ROR oprx9 xysppc ROR oprx16 xysppc ROR D xysppc ROR oprx16 xysppc RORA RORB RTI takes 11 cycles if an interrupt is Rotate right M Dl bO Rotate right A Rotate right B Return from call Msp PPAGE SP 1 SP Msp Msp 1 gt PCH PCL SP 2 gt SP Return from interrupt Msp CCR SP 1 SP Msp Msp 1 gt B A
415. last rule The V bit signals whether antecedents 0 or consequents 1 are being processed V must be initialized to O for processing to begin with the antecedents of the first rule The value of V changes as FE separators are encountered After execution V should equal 1 because the last element before the FF terminator should be a rule consequent If V is O at the end of execution the rule list is incorrect CCR Effects S XH I N ZV C V Set unless rule structure is incorrect Code and eye o Sowcerorm ego cdots ePUCyetes CPU Cycles Cycles Mode Code Hex Orfttxot ial 1 A NOTES 1 The 3 cycle ttx loop is executed once for each element in the rule list 2 These are additional cycles caused by an interrupt f is a 2 cycle exit sequence and Orf is a 3 cycle re entry sequence Execution resumes with a prefetch of the last antecedent or consequent being processed at the time of the interrupt For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 R EVW Fuzzy Logic Rule Evaluation Weighted R EVW Operation MIN MAX rule evaluation with optional rule weighting Performs either weighted or unweighted evaluation of a list of rules using fuzzy inputs to produce fuzzy outputs REVW can be interrupted so it does not adversely affect interrupt latency Each rule in the knowledge base must consist of a table of 16 bit antecedent pointers follo
416. lculation finishes the PC is adjusted again as it was for the first interrupt WAV can be interrupted any number of times and additional WAV instructions can be executed while a WAV instruction is interrupted B 7 3 Cycle by Cycle Details for WAV and wavr The WAV instruction is unusual in that the logic flow has two separate entry points The first entry point is the normal start of a WAV instruction The second entry point resumes the weighted average operation after a WAV instruction has been interrupted This recovery operation is called the wavr pseudoinstruction Figure B 11 is a flow diagram of the WAV instruction including the wavr pseudoinstruction Each box in this figure represents one CPU clock cycle Decision blocks and connecting arrows are considered to take no time at all The letters in the small rectangles in the upper left corner of the boxes are execution cycle codes refer to Appendix A Instruction Set and Commands for details In terms of cycle by cycle bus activity the 18 page select prebyte is treated as a one byte instruction In cycle 1 0 of the WAV instruction one word of program information is fetched into the instruction queue if the 18 is located at an odd address If the 18 is at an even address the instruction queue cannot advance so there is no bus access in this cycle Cycle 2 0 clears three internal 16 bit temporary registers in preparation for summation operations The WAV instruction maintains a 32 bit su
417. le O Port B drive strength enable Port E input data 7 0 NOTE PE1 is IRQ pin input PEO is XIRQ pin input core_pedo 7 0 Port E data output 7 0 core_peobe 7 0 core_peibe_t2 Port E output buffer enable 7 0 Port E input buffer enable core_pepue_t2 Port E pullup enable core_mdrste core_pedse_t2 Enable signal for EBI Mode pin pullups at the pad O Port E drive strength enable For More Information On This Product Go to www freescale com Core User Guide siocpursuen scale Semiconductor Inc Table 7 1 Core Interface Signal Definitions Signal Name Type Functional Description core_pkind 7 0 Port K input data 7 0 core_pkdo 7 0 Port K data output 7 0 core_pkobe 7 0 Port K output buffer enable 7 0 core_pkibe_t2 Port K input buffer enable core_pkpue_t2 core_pkdse_t2 Port K pullup enable Port K drive strength enable Clock and Reset Signals See Section 8 of this guide Vector Request Acknowledge Signals core_vector_fetch_t4 O Core CPU vector request peri_rstv_request System level reset vector request peri_xmonv_request l System level Crystal Monitor reset vector request peri_copv_request System level COP Watchdog reset vector request Stop and Wait Mode Control Status Signals See Section 8 of this guide Background Debug Mode BDM Interface Signals BDM BKGD pin input data Data output for BDM BKGD pin BDM BKGD pin output buff
418. le Semiconductor Inc ANDA AND with A ANDA Operation CCR Effects Code and CPU Cycles A M gt A or A imm gt A Performs a logical AND of either the value in M or an immediate value with the value in A Puts the result in A N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Machine Source Form Code Hex CPU Cycles ANDA opr8i ANDA opr8a ANDA opr16a ANDA oprx0_xysppc ANDA oprx9 xysppc ANDA oprx16 xysppc ANDA D xysppc ANDA oprx16 xysppc For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 ANDB AND with B ANDB Operation CCR Effects Code and CPU Cycles B M gt B or B imm gt B Performs a logical AND of either the value in M or an immediate value with the value in B Puts the result in B N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Machine Source Form Code Hex CPU Cycles ANDB opr8i ANDB opr8a ANDB opr16a ANDB oprx0_xysppc ANDB oprx9 xysppc ANDB oprx16 xysppc ANDB D xysppc ANDB oprx16 xysppc For More Information On This Product Go to www freescale com Core User Guide siocpurmtaRscale Semiconductor Inc ANDCC AND with COR ANDCC Operation CCR Effects Code and CPU Cycles CCR e imm CCR Performs a logical
419. le misaligned access 8 bit conditional write An x cycle is either a data write cycle or a free cycle depending on the data and flow of the REV or REVW instruction An x cycle is stretched only when controlled by a chip select circuit programmed for slow memory Special No PPP P tation for Branch Taken Not Taken A short branch requires three cycles if taken one cycle if not taken Since the instruction consists of a single word containing both an opcode and an 8 bit offset the not taken case is simple the queue advances another program word fetch is made and execution continues with the next instruction The taken case requires that the queue be refilled so that execution can continue at a new address First the effective address of the destination is determined then the CPU performs three program word fetches from that address OPPP OPO A long branch requires four cycles if taken three cycles if not taken An o cycle is required because all long branches are page two opcodes and thus include the 18 prebyte The prebyte is treated as a one byte instruction If the prebyte is misaligned the O cycle is a P cycle if the prebyte is aligned the o cycle is an cycle As a result both the taken and not taken cases use one 0 cycle for the prebyte In the not taken case the queue must advance so that execution can continue with the next instruction and another o cycle is required to maintain the queue The taken case re
420. ledge base 8 bit values F are the fuzzy outputs from RAM 8 bit values The 8 bit B accumulator holds the iteration count n Internal temporary registers hold intermediate sums 24 bits for the numerator and 16 bits for the denominator This makes this instruction suitable for n values up to 255 although eight is a more typical value The final long division is performed with a separate EDIV instruction immediately after the WAV instruction The WAV instruction returns the numerator and denominator sums in the correct registers for the EDIV EDIV performs the unsigned division Y Y D X remainder in D Execution time for this instruction depends on the number of iterations which equals the number of labels for the system output WAV is interruptible so that worst case interrupt latency is not affected by the execution time for the complete weighted average operation WAV includes initialization for the 24 bit and 16 bit partial sums so the first entry into WAV looks different than a resume from interrupt operation The CPU handles this difficulty with a pseudo instruction wavr which is specifically intended to resume an interrupted weighted average calculation Refer to B 7 3 Cycle by Cycle Details for WAV and wavr for details B 7 1 Initialization Prior to Executing WAV Before executing the WAV instruction index registers X and Y and accumulator B must be initialized Index register X is a pointer to the S singleton list X must have the ad
421. lies only to the allocated memory space and the actual memory sizes implemented in the system may differ Please refer to the chip level documentation for actual sizes The PPAGE register holds the page select value for the Program Page WIndow The value of the PPAGE register can be manipulated by normal read and write instructions as well as the CALL and RTC instructions For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc Control registers vector spaces and a portion of on chip memory are located in unpaged portions of the 64K byte physical address space The stack and I O addresses should also be in unpaged memory to make them accessible from any page The starting address of a service routine must be located in unpaged memory because the 16 bit exception vectors cannot point to addresses in paged memory However a service routine can call other routines that are in paged memory The upper 16K byte block of memory space C000 FFFE is unpaged It is recommended that all reset and interrupt vectors point to locations in this area 11 4 3 1 CALL and Return from Call Instructions CALL and RTC are uninterruptable instructions that automate page switching in the program expansion window CALL is similar to a JSR instruction but the subroutine that is called can be located anywhere in the normal 64K byte address space or on any page of program expansion memory CALL calculate
422. ligned the second o cycle is an f cycle If the first o cycle is an cycle prebyte aligned the second o cycle is a P cycle An o cycle that becomes a P cycle can be extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the program is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory An o cycle that becomes an cycle is never stretched Program word access Program information is fetched as aligned 16 bit words A P cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the program is stored externally There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory 8 bit data read An r cycle is stretched only when controlled by a chip select circuit programmed for slow memory 16 bit data read An R cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the corresponding data is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory An R cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access Stack 8 bit data An s cycle is stretched only when controlled by a chip select circuit programmed for
423. ll as the requirement to initialize A to FF Once the REV instruction starts the value in the V bit is automatically maintained as FE separator characters are detected The final requirement to clear all fuzzy outputs to 00 is part of the MAX algorithm Each time a rule consequent references a fuzzy output that fuzzy output is compared to the truth value for the current rule If the current truth value is larger it is written over the previous value in the fuzzy output After all rules have been evaluated the fuzzy output contains the truth value for the most true rule that referenced that fuzzy output After REV finishes A holds the truth value for the last rule in the rule list The V bit should be one because the last element before the FF end marker should have been a rule consequent If V is zero after executing REV it indicates the rule list was structured incorrectly B 6 1 2 Interrupt Details The REV instruction includes a three cycle processing loop for each byte in the rule list including antecedents consequents and special separator characters Within this loop a check is performed to see For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc if any qualified interrupt request is pending If an interrupt is detected the current CPU registers are stacked and the interrupt is serviced When the interrupt service routine finishes an RTI instruction causes th
424. ll the read commands return 16 bits of data despite the byte or word implication in the command name NOTE NOTE 8 bit reads return 16 bits of data of which only one byte will contain valid data If reading an even address the valid data will appear in the MSB If reading an odd address the valid data will appear in the LSB 16 bit misaligned reads and writes are not allowed If attempted the BDM will ignore the least significant bit of the address and will assume an even address from the remaining bits For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 For hardware data read commands the external host must wait 150 target clock cycles after sending the address before attempting to obtain the read data This is to be certain that valid data is available in the BDM shift register ready to be shifted out For hardware write commands the external host must wait 150 target clock cycles after sending the data to be written before attempting to send a new command This is to avoid disturbing the BDM shift register before the write has been completed The 150 target clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a free cycle before stealing a cycle For firmware read commands the external host must wait 32 target clock cycles after sending the command opcode before attempting to obtain the read data T
425. long branches are page two opcodes and thus include the 18 prebyte The prebyte is treated as a one byte instruction If the prebyte is misaligned the O cycle is a P cycle if the prebyte is aligned the o cycle is an cycle As a result both the taken and not taken cases use one 0 cycle for the prebyte In the not taken case the queue must advance so that execution can continue with the next instruction and another o cycle is required to maintain the queue The taken case requires that the queue be refilled so that execution can continue at a new address First the effective address of the destination is determined then the CPU performs three program word fetches from that address For More Information On This Product Go to www freescale com Freescale Semiconductor ING Guide s12cPU15UG V1 2 1 8 7 Condition Code State Notation Table 1 9 Condition Code State Notation Not changed by operation Cleared by operation Set by operation Set or cleared by operation May be cleared or remain set but not set by operation May be set or remain cleared but not cleared by operation oe se May be changed by operation but final state not defined Used for a special purpose For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12c
426. lowed 4 4 0 Peripheral BDM allowed but bus operations would cause bus conflicts must not be used 1 1 1 Normal Expanded Wide BDM allowed IVIS Internal Visibility for both read and write accesses This bit determines whether internal accesses generate a bus cycle that is visible on the external bus Normal write once Emulation write never Special write anytime 1 Internal bus operations are visible on external bus 0 No visibility of internal bus operations on external bus Reference Section 12 4 9 for mode availability of this bit EMK Emulate Port K Normal write once Emulation write never Special write anytime 1 If in any expanded mode PORTK and DDRK are removed from the memory map 0 PORTK and DDRK are in the memory map so Port K can be used for general purpose I O In single chip modes PORTK and DDRK are always in the map regardless of the state of this bit In peripheral modes PORTK and DDRK are never in the map regardless of the state of this bit EME Emulate Port E Normal and Emulation write never Special write anytime 1 If in any expanded mode or special peripheral mode PORTE and DDRE are removed from the memory map Removing the registers from the map allows the user to emulate the function of these registers externally 0 PORTE and DDRE are in the memory map so Port E can be used for general purpose I O In single chip modes PORTE and DDRE are always in the map regardless of the state of
427. lues After CMPA CMPB CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the CPU register value is greater than or equal to the value in M After CBA or SBA the branch occurs if the value in B is greater than or equal to the value in A Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction S X H I N ZV C Address Machine Source Form Mode Code Hex CPU Cycles BGE rel8 REL 2C rr PPP branch P no branch Branch Complementary Branch Comment Mnemonic Opcode Mnemonic Opcode Test R lt M BHS BCC BLO BCS For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 B G N D Enter Background Debug Mode B G N D Operation CCR Effects Code and CPU Cycles PC TMP2 BDM vector PC BGND operates like a software interrupt except that no registers are stacked First the current PC value is stored in internal CPU register TMP2 Next the BDM ROM and background register block become active The BDM ROM contains a substitute vector mapped to the address of the software interrupt vector which points to routines in the BDM ROM that control background operation The substitute vector is fetched and execution continues from the a
428. ly upon receiving the valid interrupt request This signal will then negate logic 0 asynchronously once the interrupt source is negated indicating that the interrupt has been serviced and is no longer being requested 8 2 Signal Summary Each of the Core I O signals that interface with the system clock and reset generation block s are listed in Table 8 1 below with the signal type and a brief functional description for completeness Table 8 1 Core Clock and Reset Interface Signals Signal Name Type Functional Description Clock and Reset Signals System reset signal peri_reset_ta4 reset_pin_ind System level reset pin input data peri_clk2 System clock clk2 for Core peri_clk4 System clock clk4 for Core peri_clk24 System clock clk24 for Core peri_clk34 System clock clk34 for peripherals on I P Bus Interface peri_clk23 System clock clk23 used by Core to generate ECLK peri_phase_oscdX Oscillator Clock divided by X PLL test feature clock enable signal peri_test_clk_enable peri_test_clk peri_pllsel_t3 core_eclk_load PLL test feature clock signal PLL selected signal External clock load enable signal core_neclk_t2 External clock disable signal Stop and Wait Mode Control Status Signals core stop t24 O Core CPU stop mode signal core_wait_t24 Core CPU wait mode signal core_wakeup_ta 5 Core wakeup from stop or wait mode due to interrupt eri cwai t3 Core wait signal controls
429. m of products in TMP3 TMP2 and a 16 bit sum of weights in TMP1 Keeping these sums inside the CPU reduces bus accesses and optimizes the WAV operation for high speed Cycles 3 0 through 9 0 form the seven cycle main loop for WAV The value in the 8 bit B accumulator counts the number of loop iterations B is decremented at the top of the loop in cycle 3 0 and the test for zero is located at the bottom of the loop after cycle 9 0 Cycles 4 0 and 5 0 fetch the 8 bit operands for one iteration of the loop The X and Y index registers are used to access these operands The index registers are incremented as the operands are fetched Cycle 6 0 accumulates the current fuzzy output into TMP3 Cycles 7 0 and 8 0 perform the eight by eight multiply of F times S TMP1 TMP2 accumulates the product during cycles 8 0 and 9 0 Even though the sum of products does not exceed 24 bits the sum is maintained in the 32 bit combined TMP1 TMP2 register because it is easier to use existing 16 bit operations than to create a new smaller operation to handle the high bits of this sum Since the weighted average operation could be quite long it is made to be interruptible The usual longest latency path is from very early in cycle 6 0 through cycle 9 0 to the top of the loop in cycle 3 0 and through cycle 5 0 to the interrupt check The three cycle 6 1 through 8 1 exit sequence gives this latency path a total of 10 cycles For More Information On This Product Go to www
430. m one memory area to another LOOP MOVW 2 X gt 2 Y move a word and update pointers DBNE B LOOP repeat B times The move immediate to extended is a convenient way to initialize a register without using an accumulator or affecting condition codes C 7 3 Universal Transfer and Exchange The M68HC11 has only eight transfer instructions and two exchange instructions The HCS12 has a universal transfer exchange instruction that can be used to transfer or exchange data between any two CPU registers The operation is obvious when the two registers are the same size and some of the other combinations provide very useful results For example when an 8 bit register is transferred to a 16 bit register a sign extend operation is performed Other combinations can be used to perform a zero extend operation These instructions are used often in HCS12 assembly language programs Transfers can be used to make extra copies of data in another register and exchanges can be used to temporarily save data during a call to a routine that expects data in a specific register This is sometimes faster and produces more compact object code than saving data to memory with pushes or stores C 7 4 Loop Construct The HCS12 instruction set includes a new family of six loop primitive instructions These instructions decrement increment or test a loop count in a CPU register and then branch based on a zero or nonzero test result The CPU registers that can be use
431. mainder gt D For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Source Form EDIVS Operation Extended divide signed 32 by 16 to 16 bit Y D X gt Y remainder gt D Address Mode INH Machine Coding Hex Access Detail Offffffffffo0 SXHINZVC EMACS opr16a EMAXD oprx0_xysppc EMAXD oprx9 xysppc EMAXD oprx16 xysppc EMAXD D xysppc EMAXD oprx16 xysppc Extended multiply and accumulate signed Mx Myx 1 x My My 1 M M 3 M M 3 16 by 16 to 32 bit Extended maximum in D put larger of 2 unsigned 16 bit values in D MAX D M M 1 gt D N Z V C bits reflect result of internal compare D M M 1 Special IDX IDX1 IDX2 D IDX IDX2 D D x x ORROf f fRR WWP ORP ORPO OfRPP OfIfRP OfIPRP EMAXM oprx0_xysppc EMAXM oprx9 xysppc EMAXM oprx16 xysppc EMAXM D xysppc EMAXM oprx16 xysppc Extended maximum in M put larger of 2 unsigned 16 bit values in M MAX D M M 1 gt M M 1 N Z V C bits reflect result of internal compare D M M 1 IDX IDX1 IDX2 D IDX IDX2 cc al ORPW ORPWO OfRPWP OfIfRPW OfIPRPW EMIND oprx0_xysppc EMIND oprx9 xysppc EMIND oprx16 xysppc EMIND D xysppc EMIND oprx16 xysppc EMINM oprx0_xysp
432. matical instructions Greater regularity of the instruction set makes it For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc possible to implement compilers more efficiently because operation is more consistent and fewer special cases must be handled For More Information On This Product Go to www freescale com N 5 anejo TY paxepul AI saj q jo Jequiny L HI apow sselppy ayelpawwi WI pepuelxe x3 O ansa ONUOUISUIN jeioads dS juajayul HI 199 119 q suonenaqqe pow ssalppy a sejo o JO JOQUINN G 00 apoodo xaH ANGL 10 0391 ANGI ANGA OIA suoonsjsu alld doo ay yo auo 104 S po P00dO gt e Xalvz die laje Wye xalvz al a laje Wye xaje afe la gaje Hije WS xaj a o sal sal sal sal Sd9 Sd9 Sdo SdO S1S SIS SIS yia IMS 18 41089 47099 A _ d4 pe sale alz a 9 e 4g v Avie 46 z SBE 3 b2 AD S GS ap 6 Ele az s 3L9p 40 D e xaivz alz laje wie xat alz iaje wije xajre alz aj idj t Hie wis xalo al xal xal xal xal XdO XdO XdO XdO XLS XLS XLS 13889 IVM 19g 3s8e 1asy e JHlv33e aaz 30 salve avie 3612 38 Adie 392 ASip Avl9td geje azjs Alay 30 o e X3aibz diz iaje Wie xXajre diz iaje wie xaje dz iaje ijt Hie Wr xas a a Aq Aq Aq Aq AdO AdO Ado Ado ALS ALS AS ula Sia ne us yo 5 e QdJogved3e addjz age aalgvedwe a6lz age atv ajz aSip aprlS de le adzi
433. mation On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 6 1 1 Reset Processing 2 0 f This cycle sets the S X and I bits 3 0 P through These cycles are program word fetches that refill the instruction queue Fetches start at the address pointed to by the reset vector When the fetches are completed reset processing ends and the CPU starts executing the instruction at the head of the instruction queue 6 1 2 Interrupt Processing The SWI and TRAP interrupts have no mask or interrupt request and are always recognized An XIRQ interrupt request is recognized any time after the X bit is cleared An enabled I bit maskable interrupt request is recognized any time after the I bit is cleared The CPU responds to an interrupt after it completes the execution of its current instruction Interrupt latency depends on the number of cycles required to complete the instruction After the vector fetch the CPU calculates a return address The return address depends on the type of exception e When an X bit maskable or I bit maskable interrupt causes the exception the return address points to the next instruction that would have been executed had processing not been interrupted e When an SWI opcode or TRAP causes the exception the return address points to the next address after the SWI opcode or to the next address after the unimplemented opcode 2 1 S and These are both S cycles 16 bit writ
434. mentary Branch F Comment Mnemonic Opcode Test Mnemonic Opcode Test Negative Positive LBMI 18 2B LBPL 18 2A Simple For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 i B N E Long Branch if Not Equal to Zero L B N E Operation If Z 0 then PC 0004 rel PC Tests the Z bit and branches if Z 0 Rel is a 16 bit two s complement offset for branching forward or backward in memory Branching range is 8000 to 7FFF 32768 to 32767 from the address following the last byte of object code in the instruction CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex LBNE rel16 REL 18 26 qq rr OPPP branch OPO no branch Branch Complementary Branch Comment Mnemonic Opcode Test Mnemonic Opcode Test R M R M or or Signed LBNE 1826 R zero LBEQ 18 27 unsigned or simple For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc L B p L Long Branch if Plus L B P L Operation CCR Effects Code and CPU Cycles If N 0 then PC 0004 rel gt PC Tests the N bit and branches if N 0 Rel is a 16 bit two s complement offset for branching forward or backward in memory Branching range is 8000 to 7FFF 32768 to 32767 from the addres
435. mmediate data value High byte of a 16 bit immediate data value Low byte of a 16 bit immediate data value Loop primitive DBNE postbyte Low byte of a 16 bit extended address 8 bit immediate mask value for bit manipulation instructions bits that are set indicate bits to be affected Log Program page or bank number used in CALL instruction qq High byte of a 16 bit relative offset for long branches tn Trap number from 30 to 39 or from 40 to FF Signed relative offset 80 128 to 7F 127 relative to the byte following the relative offset byte E A or low byte of a 16 bit relative offset for long branches xb Indexed addressing postbyte For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 1 8 6 Access Detail Notation A single letter code in the Access Detail column of Table 1 2 represents a single CPU access cycle An upper case letter indicates a 16 bit access Table 1 8 Access Detail Notation Free cycle During an f cycle the CPU does not use the bus An cycle is always one cycle of the system bus clock An cycle can be used by a queue controller or the background debug system to perform a single cycle access without disturbing the CPU g Read PPAGE register A g cycle is used only in CALL instructions and is not visible on the external bus Since PPAGE is an internal 8 bit register a y cycle is ne
436. mment Mnemonic For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPuU15UG V1 2 BVS Branch if V Set BVS Operation If V 1 then PC 0002 rel gt PC Tests the V bit and branches if V 1 BVS causes a branch when a previous operation on two s complement values causes an overflow That is when BVS follows a two s complement operation a branch occurs when the result of the operation is invalid Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex PPP branch erage P no branch Complementary Branch opcode Test Wemonic opcode Test No overflow Comment Mnemonic BVS Simple For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc CA L L Call Subroutine in Expanded Memory CA L L Operation CCR Effects Code and CPU Cycles SP 0002 gt SP RTNg RTN gt Msp Mgp 1 SP 0001 gt SP new page value gt PPAGE Subroutine address PC Sets up conditions to return to normal program flow then transfers control to a subroutine in expanded memory Uses the addre
437. mory plus previous carry is larger than the absolute value of A cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles SBCA opr8i SBCA opr8a SBCA opr16a SBCA oprx0_xysppc SBCA oprx9 xysppc SBCA oprx16 xysppc SBCA D xysppc SBCA oprx16 xysppc For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc SBCB Subtract with Cary from B SBCB Operation CCR Effects Code and CPU Cycles B M C gt B or B imm C gt B Subtracts either the value in M and the C bit or an immediate value and the C bit from the value in B Puts the result in B The C bit represents a borrow S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V B7 M7 e R7 B7 M7 e R7 set if a two s complement overflow resulted from the operation cleared otherwise C B7 e M7 M7 R7 R7 B7 set if the absolute value in M plus previous carry is larger than the absolute value in B cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles SBCB opr8i SBCB opr8a SBCB opr16a SBCB oprx0_xysppc SBCB oprx9 xysppc SBCB oprx16 xysppc SBCB D xysppc SBCB oprx16 xysppc For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 S E C same ONCE 01 S E C Operation CCR Effects Cod
438. mplement and negate operations replace the value with its two s complement A summary of the clear complement and negate instructions is given in Table 4 11 Table 4 11 Clear Complement and Negate Instructions Mnemonic Function Operation CLV COM One s complement memory FF NEG Two s complement memory NEGB Two s complement B For More Information On This Product Go to www freescale com 4 3 10 Multiply and Divide Instructions The multiply instructions perform signed and unsigned 8 bit and 16 bit multiplication An 8 bit Freescale Semiconductor WOE Guide multiplication gives a 16 bit product A 16 bit multiplication gives a 32 bit product An integer divide or fractional divide instruction has a 16 bit dividend divisor quotient and remainder Extended divide instructions use a 32 bit dividend and a 16 bit divisor to produce a 16 bit quotient and a 16 bit remainder A summary of the multiply and divide instructions is given in Table 4 12 Table 4 12 Multiplication and Division Instructions Mnemonic Function Operation EMUL 16 by 16 multiply unsigned Y x D Y D EMULS 16 by 16 multiply signed Y x D Y D MUL 8 by 8 multiply unsigned A x B A B EDIV 32 by 16 divide unsigned Y D X quotient Y remainder D EDIVS 32 by 16 divide signed Y D X quotient Y remainder D FDIV 16 by 16 fractional divide unsigned D
439. mplete the picture for system debugging it is also necessary to include program information and associated addresses in the reconstructed queue The instruction queue and cycle by cycle activity can be reconstructed in real time or from trace history captured by a logic analyzer However neither scheme can be used to stop the CPU at a specific instruction By the time an operation is visible outside the system the instruction has already begun execution A separate instruction tagging mechanism is provided for this purpose A tag follows the information in the queue as the queue is advanced During debugging the CPU enters active background debug mode when a tagged instruction reaches the head of the queue rather than executing the tagged instruction For more information about tagging refer to 14 4 8 Instruction Tagging 5 5 1 Instruction Queue Status Signals The IPIPE 1 0 signals carry time multiplexed information about data movement and instruction execution during normal operation The signals are available on two multifunctional device pins During reset the pins are mode select inputs MODA and MODB After reset information on the pins does not become valid until an instruction reaches stage two of the queue To reconstruct the queue the information carried by the status signals must be captured externally In general data movement and execution start information are considered to be distinct two bit values with the low bit on IPIPEO
440. n 531 C 3 Programmer s Model and Stacking vienesa a 533 C 4 True 16 Bit Architecture n n aannaaien 533 C 4 1 BUS Str ct reS ieo Ets A AAA AAA 533 42 Instuction Queues ri A EA A O E 533 C 4 3 LACK PUNCHOM ts Es EA aaa aoa EEEE 534 6507 Improved Indexing vt a ts Garett ee ihe ob tate A AE AL 535 For More Information On This Product Go to www freescale com C 5 1 C 5 2 C 5 3 C 5 4 C 6 C 6 1 C 6 2 C 6 3 C 7 C 7 1 C 7 2 C 7 3 C 7 4 C 7 5 C 7 6 C 7 7 C 7 8 C 7 9 C 7 10 C 7 11 C 7 12 Freescale Semiconductor ING cuide s12cPuU15UG V1 2 Constant Offset Indexing 2 e a y e al atajos Cde 536 Autoincrement Autodecrement Indexing o ooccoocccccnn nooo 537 Accumulator Offset Indexing ooooooccocccocn eee 537 Indirect NASA set coed es Gg id A he oe ie 538 Improved Porton ia 538 Reduced Cycle Coums 245 53 15 6 n et tateneas seed 538 Fast Mathei A ities a ae cite Sa steerage hearer ah aoe use E E a a NE a paa Bids 538 Code Size Meduchonyss 6tse tanec caters eeartnds sad 539 Additional FUNCION A ak Ak bits Shter te 5 deny A ald Skis Sha are te Atak thE 540 NOW INST UCHONS 224 esis ora Ar ot saa ite Boe etn SS aio 540 Memory to Memory Moves 00 00 e cece eee eee 542 Universal Transfer and Exchange 2 s00 ceo ge oye Pee ade SORE Meee Der 542 AR A aea E Te Nether a aan ard de tee ae ad 542 LONG Branches insinte eet ae a la eee Phe eee 542 Minimum and Maximum Instructions
441. n in Table 4 7 Table 4 7 BCD Instructions Mnemonic Function Operation ABA Add Bto A A B gt A ADCA Add memory and carry to A A M C gt A Add immediate value and carry to A A imm C gt A ADCB Add memory and carry to B B M C gt B Add immediate value and carry to B B imm C gt B ADDA Add memory to A A M gt A Add immediate value to A A imm gt A ADDB Add memory to B B M B Add immediate value to B B imm B DAA Decimal adjust A A 10 A 4 3 6 Decrement and Increment Instructions These instructions are optimized 8 bit and 16 bit addition and subtraction operations They are used to implement counters Because they do not affect the carry bit C in the CCR they are particularly well suited for loop counters in multiple precision computation routines See 4 3 17 4 Loop Primitive Instructions for information concerning automatic counter branches A summary of the decrement and increment instructions is given in Table 4 8 Decrement and Increment Instructions Table 4 8 Decrement and Increment Instructions Mnemonic Function Operation DEC Decrement memory M 01 gt M DECA Decrement A A 01 gt A DECB Decrement B B 01 B DES Decrement SP SP 0001 gt SP DEX Decrement X X 0001 X DEY Decrement Y Y 0001 Y INC Increment memory M 01 M INCA Increment A A 01 A INCB Increment B B 01 B INS Increment SP SP
442. n in Figure 6 1 below Relevant points within the flow are detailed in the paragraphs that follow During the vector fetch cycle the CPU indicates to the system that it is requesting that the vector address of the pending exception having the highest priority be driven onto the address bus The CPU does not provide this address The vector points to the address where the exception service routine begins Exception vectors are stored in a table at the top of the memory map FFB6 FFFF The CPU begins using the vector to fetch instructions in the third cycle of the exception processing sequence After the vector fetch the CPU selects one of the three processing paths based on the source of the exception e Reset e X bit maskable and I bit maskable interrupt request e SWI and TRAP For More Information On This Product Go to www freescale com Core User Guide si2cpu Rf Scale Semiconductor Inc START Yes No SWI or TRAP Yes No Push return address Address of next instruction that would have been executed Push return address Address of instruction after SWI or unimplemented opcode Set S X and bits and clear all other bits in programmer s model Fetch program word TAN pram wori z Start filling instruction queue BE TS Finish filling instruction queue Finish filling instruction queue Figure 6 1 Exception Processing Flow For More Infor
443. n of the internal EEPROM within the on chip system memory map EE15 EE11 Internal EEPROM map position These bits determine the upper five bits of the base address for the system s internal EEPROM array For More Information On This Product Go to www freescale com Core User Guide si2cru a fscale Semiconductor Inc 11 3 4 Miscellaneous System Control Register MISC Address Base 13 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 EXSTR1 EXSTRO ROMHM ROMON Write o 0 0 0 0 0 1 Reset Peripheral or Single 0 0 0 0 1 1 0 1 Chip Reset EA Unimplemented Figure 11 6 Miscellaneous System Control Register MISC NOTES 1 The reset state of this bit is determined at the chip integration level Read Anytime Write As stated in each bit description below NOTE Writes to this register take one cycle to go into effect This register initializes miscellaneous control functions EXSTR1 0 External Access Stretch Bits 1 amp 0 Write Once in Normal and Emulation modes and anytime in Special modes This two bit field determines the amount of clock stretch on accesses to the external address space as shown in Table 11 1 below In Single Chip and Peripheral modes these bits have no meaning or effect Table 11 1 External Stretch Bit Definition Stretch bit EXSTR1 Stretch bit EXSTRO Number of E Clocks Stretched ROMHM Flash EEPROM or ROM only in second half of memory map Write
444. n range from 0 0 x A to 1 0 x A After 8 2 flow continues to the next loop pass at cycle 4 0 At cycle 4 0 if Ry is FFFE and V was one a change from consequents to antecedents of a new rule is taking place so accumulator A must be reinitialized to FF During processing of rule antecedents A is updated with the smaller of A and the current fuzzy input cycle 6 0 Cycle 5 0 usually reads the next rule word and updates the pointer in X This read is skipped if the current Ry is the end of rules mark FFFF If this is a weight multiply pass the read is delayed until cycle 7 2 During processing of consequents cycle 6 1 optionally updates a fuzzy output if the value in accumulator A is larger For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc START Read program word if 18 misaligned X X 2 point at next rule element Read byte 0 X rule element Rx 3 0 f No bus access TMP2 Y 1 weight pointer kept in TMP2 Update Rx with value read in cycle 2 or 5 If Rx FFFE then TMP2 TMP2 1 If Ry FFFF If Rx other If V 0 and C 1 then read rule weight TMP2_ then no bus access then read byte Rx fuzzy in out FRx else no bus access Toggle V bit if V now 0 A FF No Interrupt pending tes If Ry FFFF then read rule word X 5 3 f No bus access Adjust PC to point at current REVW instruction
445. n the fuzzy output because the rules are connected by an implied fuzzy or In the case of rule weighting the truth value for a rule is determined as usual by finding the smallest rule antecedent Before applying this truth value to the consequents for the rule the value is multiplied by a fraction from zero rule disabled to one rule fully enabled The resulting modified truth value is then applied to the fuzzy outputs The end result of the rule evaluation step is a table of suggested or raw fuzzy outputs in RAM These values were obtained by plugging current conditions fuzzy input values into the system rules in the knowledge For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc base The raw results cannot be supplied directly to the system outputs because they may be ambiguous For instance one raw output can indicate that the system output should be medium with a degree of truth of 50 while at the same time another indicates that the system output should be low with a degree of truth of 25 The defuzzification step resolves these ambiguities B 3 3 Defuzzification WAV The final step in the fuzzy logic program combines the raw fuzzy outputs into a composite system output Instead of the trapezoidal shapes used for inputs singletons are typically used for output membership functions As with the inputs the x axis represents the range of possible values for a sy
446. naa annan 61 Queue Status Signal TIMING cisco 127 Core Interface SignalS ooooooocommmooo o 142 Basic 8 bit Peripheral Read TiMiNQ 153 Basic 16 bit Peripheral Read TiMiNQ 153 Basic 8 bit Memory Read Timing 005 154 Basic 16 bit Memory Read Timing 24 154 Basic 8 bit Core Register Read Timing 155 Basic 16 bit Core Register Read Timing 155 Basic 8 bit Peripheral Write Timing 156 Basic 16 bit Peripheral Write Timing 156 Basic 8 bit Memory Write TiMiNQ 157 Basic 16 bit Memory Write TimiNg 157 Basic 8 bit Core Register Write Timing 158 Basic 16 bit Core Register Write Timing 158 General External Bus Timing 5 159 General Internal Read Visibility Timing 161 Core Interface SiIQnalS 01 tasca See eed 164 System Clock Timing Diagram 000 0055 165 Interrupt Block DiadrdlT sutorariorn estes eas 172 Interrupt Register Summary 00000 e eee eee 173 Interrupt Test Control Register ITCR 173 Interrupt TEST Registers ITEST 174 For More Information On This Product Go to www freescale com 12CPU15UG V1 2 Core User Guide s12cpu af Scale Semiconductor Inc Figure 10 5 Highest Priority Interrupt Register HPRIO
447. nch For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc Address Machine Source Form Operation Mode Coding Hex Access Detail SXHINZVC LBMI re 16 Long branch if minus 18 2Baqqrr PPP branch If N 1 then PC 4 rel gt PC PO no branch LBNE re 16 Long branch if not equal to 0 1826qqrr p branch If Z 0 then PC 4 rel gt PC no branch LBPL re 16 Long branch if plus 18 2Aqqrr PPP branch If N 0 then PC 4 rel gt PC no branch LBRA rel16 Long branch always 18 20 qqrr LBRN rel16 Long branch never 18 21 qqrr LBVC rel16 Long branch if V clear 1828 qqrr OPPP branch If V 0 then PC 4 rel gt PC OPO no branch LBVS rel16 Long branch if V set 1829qqrr OPPP branch If V 1 then PC 4 rel gt PC OPO no branch LDAA opr8i LoadA 8644 P LDAA opr8a M gt A 96 dd rPf LDAA opr16a orimm gt A B6hh11 rPO LDAA oprx0_xysppc A6 xb rPf LDAA oprx9 xysppc A6 xbff rPO LDAA oprx16 xysppc A6 xbee ff frPP LDAA D xysppc A6 xb flfrPf LDAA oprx16 xysppc A6 xbee ff fIPrP LDAB opr8i LoadB j P LDAB opr8a M B rPf LDAB opr16a or imm gt B rPO LDAB oprx0_xysppc rPf LDAB oprx9 xysppc rPO LDAB oprx16 xysppc frPP
448. nch function The HCS12 includes a set of six basic loop control instructions that decrement increment or test a loop count register and then branch if the register is either equal to zero or not equal to zero The loop count register can be A B D X Y or SP A or B could be used if the loop count fits in an 8 bit char variable the other choices are all 16 bit registers The relative offset for the loop branch is a 9 bit signed value so these instructions can be used with loops as long as 256 bytes In some cases the pre or postincrement operation can be combined with an indexed instruction to eliminate the cost of the increment operation This is typically done by postcompile optimization because the indexed instruction that could absorb the increment decrement operation may not be apparent at compile time 4 4 4 Higher Math Functions In the HCS12 CPU subtle characteristics of higher math operations such as IDIVS and EMUL are arranged so a compiler can handle inputs and outputs more efficiently The most apparent case is the IDIVS instruction which divides two 16 bit signed numbers to produce a 16 bit result While the same function can be accomplished with the EDIVS instruction a 32 by 16 divide doing so is much less efficient because extra steps are required to prepare inputs to the EDIVS and because EDIVS uses the Y index register EDIVS uses a 32 bit signed numerator and the C compiler would typically want to use a 16 bit value
449. nd BKxRWE bits in the BKPCT1 register select whether the type of bus cycle to match is a read write or both when performing forced breakpoints 13 4 1 2 Full Breakpoint Mode Full Breakpoint Mode requires a match on address and data for a breakpoint to occur Upon a successful match the system will enter Background Debug Mode or initiate a software interrupt based upon the state of the BKBDM bit in the BKPCTO Register being logic one or logic zero respectively BDM requests have a higher priority than SWI requests R W matches are also allowed in this mode For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc The BKTAG bit in the BKPCTO register selects whether the breakpoint mode is forced or tagged If the BKTAG bit is set in BKPCTO then only address is matched and data is ignored The BKOMBH L bits in the BKPCT1 register select whether or not the breakpoint is matched exactly is a range breakpoint or is in page space The BK1MBH L bits in the BKPCT register select whether the data is matched on the high byte low byte or both bytes The BKORW and BKORWE bits in the BKPCT 1 register select whether the type of bus cycle to match is a read or a write when performing forced breakpoints BK1RW and BKIRWE bits in the BKPCT I register are not used in Full Breakpoint Mode 13 4 2 Breakpoint Priority Breakpoint operation is first determined by the state of BDM If BDM is alrea
450. nd COP Watchdog resets and Real Time Interrupt functions available on the HCS12 family of products A diagram of the Core interface signals is given in Figure 8 1 below For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc Memory Configuration Switches S fe a ol z el 2 al cle Shel cle 3 33353333332 el did 3 s 5 5 peri _ reset ta4 gt Resets re iiih core ramregsel ta On Chip core ramarraysel RAM peri_clk2 core ramhal t2 gt Interface Clocks peri_clk4 vam _rdb_L12 15 0 peri_clk24 core eeregsel 2y On Chip peri_clk34 CPU MMC core_eearraysel 5 EEPROM ja Central Module qee r b L12115 01 Interface bel bhasa 220 Processing Mapping ee hold t1 ECLK quiesci load_ Ent Control core feeregsel 12y On Chip Control core feearraysel Flash qki EEPROM ore vector fetei i q rdb_L 12 15 0 Interface Vector eri_rstv_requ ecto ty Request peri_xmonv_requegs core ab 12 19 0 y Acknowledge_peri copy reg esp core wdb t4 15 0 que stop 124 core rw t2 Common Bus Stop and ue mati24 INT core 528 12 y Interface Wait Mode gore wakeup ta BDM Interrupt core exp 12 gt Signals Control per_cwait3__p Bara De Memory and S i Background ore pet 12 p Peripherals tatus peri syswai i3 y Debug core smod 12 pi peri test_cik_enabjg Mode BKP core perisel t2 gt PEE pen tesi ek y Breakpoint core bdmact t4 p peri plisel t
451. nd O cycle at the end If the first o cycle is a P cycle prebyte misaligned the second o cycle is an f cycle If the first o cycle is an cycle prebyte aligned the second o cycle is a P cycle An o cycle that becomes a P cycle can be extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the program is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory An o cycle that becomes an cycle is never stretched Program word access Program information is fetched as aligned 16 bit words A P cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the program is stored externally There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory 8 bit data read An r cycle is stretched only when controlled by a chip select circuit programmed for slow memory 16 bit data read An R cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the corresponding data is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory An R cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access Stack 8 bit data An s cycle is s
452. nd address buses C 4 3 Stack Function Both the M68HC11 and the HCS12 stack nine bytes for interrupts Since this is an odd number of bytes there is no practical way to assure that the stack will stay aligned To assure that instructions take a fixed number of cycles regardless of stack alignment the internal RAM in HCS12 systems is designed to allow single cycle 16 bit accesses to misaligned addresses As long as the stack is located in this special RAM stacking and unstacking operations take the same amount of execution time regardless of stack alignment For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 If the stack is located in an external 16 bit RAM a PSHX instruction can take two or three cycles depending on the alignment of the stack This extra access time is transparent to the CPU because the integration module freezes the CPU clocks while it performs the extra 8 bit bus cycle required for a misaligned stack operation The HCS12 has a last used stack rather than a next available stack like the M68HC11 CPU That is the stack pointer points to the last 16 bit stack address used rather than to the address of the next available stack location This generally has very little effect because it is very unusual to access stacked information using absolute addressing The change allows a 16 bit word of data to be removed from the stack without changing the value of the
453. nested interrupt scheme requires great care and seldom improves system performance 1 Maskable interrupt requests disabled 0 Maskable interrupt requests enabled For More Information On This Product Go to www freescale com Core User Guide si2cPu ERA Scale Semiconductor Inc N Negative Bit The N bit is set when the MSB of the result is set N is most commonly used in two s complement arithmetic where the MSB of a negative number is one and the MSB of a positive number is zero but it has other uses For instance if the MSB of a register or memory location is used as a status bit the user can test the bit by loading an accumulator 1 MSB of result set 0 MSB of result clear Z Zero Bit The Z bit is set when all the bits of the result are zeros Compare instructions perform an internal implied subtraction and the condition codes including Z reflect the results of that subtraction The INX DEX INY and DEY instructions affect the Z bit and no other condition bits These operations can only determine and 1 Result all zeros 0 Result not all zeros V Overflow Bit The V bit is set when a two s complement overflow occurs as a result of an operation 1 Overflow 0 No overflow C Carry Bit The C bit is set when a carry occurs during addition or a borrow occurs during subtraction The C bit also acts as an error flag for multiply and divide operations Shift and rotate instructions operate
454. nic Function Operation Branch to subroutine SP 0002 SP RTNy RTNL Mgp Mgp 1 Subroutine address PC Call subroutine SP 0002 SP RTNY RTN Mgp Mgp 4 SP 0001 SP in expanded memory PPAGE Msp page PPAGE subroutine address PC Jump Subroutine address PC JMP Jump to subroutine SP 0002 gt SP RTNY RTN Mgp Mgp Subroutine address PC an ene arena a gt PPAGE SP 0001 gt SP Mgp Mgp 4 gt PCy PC SP 0002 SP Return from call Mgp Mgp 1 gt PCy PC SP 0002 gt SP 4 3 19 Interrupt Instructions Interrupt instructions handle transfer of control to and from interrupt service routines The SWI instruction initiates a software interrupt It stacks the return address and the values in the CPU registers Then execution begins at the address pointed to by the SWI vector The SWI instruction causes an interrupt without an interrupt request The global mask bits I and X in the CCR do not inhibit SWI SWI sets the I bit inhibiting maskable interrupts until the I bit is cleared The TRAP instruction The CPU uses the software interrupt for unimplemented opcode trapping There are opcodes in all 256 positions in the page 1 opcode map but only 54 of the 256 positions on page 2 of the opcode map are used If the CPU attempts to execute one of the unimplemented opcodes on page 2 an opcode trap interrupt occurs Traps are essentially interrupts that
455. nimum and maximum instructions is given in Table 4 16 Table 4 16 Minimum and Maximum Instructions Mnemonic Function Operation Put smaller of two unsigned 16 bit values in D MIN D M M 1 D Put smaller of two unsigned 16 bit values in memory MIN D M M 1 M M 1 Put smaller of two unsigned 8 bit values in A MIN A M A Put smaller of two unsigned 8 bit values in memory MIN A M M Put larger of two unsigned 16 bit values in D MAX D M M 1 D Put larger of two unsigned 16 bit values in memory MAX D M M 1 M M 1 MAXA Put larger of two unsigned 8 bit values in A MAX A M A MAXM Put larger of two unsigned 8 bit values in memory MAX A M M For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 4 3 15 Multiply and Accumulate Instruction The EMACS instruction multiplies two 16 bit operands stored in memory and accumulates the 32 bit result in a third memory location EMACS can be used to implement simple digital filters and defuzzification routines that use 16 bit operands The WAV instruction incorporates an 8 bit to 16 bit multiply and accumulate operation that obtains a numerator for the weighted average calculation The EMACS instruction can automate this portion of the averaging operation when 16 bit operands are used A summary of the multiply and accumulate instructions is gi
456. ns with no relative priority 6 3 2 3 Nonmaskable External Interrupt Request Pin XIRQ Driving the XIRQ pin low generates an external interrupt request subject initially to masking by the X bit Reset sets the X bit masking XIRQ interrupt requests Software can unmask XIRQ interrupt requests once after reset by clearing the X bit with an instruction such as ANDCC BF After the X bit has been cleared it cannot be set and XIRQ interrupt requests are nonmaskable until another reset occurs XIRQ interrupt request processing stacks the CCR and then sets both the X and I bits to prevent other interrupts during the XIRQ service routine An RTI instruction at the end of the service routine restores the X and I bits to their preinterrupt states 6 3 2 4 Maskable External Interrupt Request Pin IRQ Driving the IRQ pin low generates an external interrupt request subject to masking by the I bit IRQ interrupt request processing stacks the CCR and then sets the I bit to prevent other interrupts during the IRQ service routine An RTI instruction at the end of the service routine restores the I bit to its preinterrupt state For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 The Interrupt sub block of the Core INT also has a control bit to disconnect the IRQ input Please see Section 10 of this guide for a more detailed description 6 3 2 5 System Peripheral Block In
457. nsfers control to a subroutine Uses the address of the instruction after the BSR as a return address Decrements the SP by two to allow the two bytes of the return address to be stacked Stacks the return address the SP points to the high byte of the return address Branches to a location determined by the branch offset Subroutines are normally terminated with an RTS instruction which restores the return address from the stack S X H I N ZV C Address Machine Source Form Mode Code Hex CPU Cycles BSR rel8 For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc BVC Branch if V Clear BVC Operation CCR Effects Code and CPU Cycles If V 0 then PC 0002 rel gt PC Tests the V bit and branches if V 0 BVC causes a branch when a previous operation on two s complement binary values does not cause an overflow That is when BVC follows a two s complement operation a branch occurs when the result of the operation is valid Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction S X H I N ZV C Address Machine Source Form Mode Code Hex CPU Cycles PPP branch EOIR P no branch Complementary Branch Opcode Test Mnemonic Opcode Test Co
458. nstruction causes the on chip oscillator to stop This may be undesirable in some applications When the S bit is set the CPU treats the STOP instruction as a no operation NOP instruction and continues on to the next instruction Reset sets the S bit 1 STOP instruction disabled 0 STOP instruction enabled For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 X XIRQ Mask Bit Clearing the X bit enables interrupt requests on the XIRQ pin The XIRQ input is an updated version of the nonmaskable interrupt NMJ input found on earlier generations of Motorola microcontroller units MCUs Nonmaskable interrupts are typically used to deal with major system failures such as loss of power However enabling nonmaskable interrupts before a system is fully powered and initialized can lead to spurious interrupts The X bit provides a mechanism for masking nonmaskable interrupts until the system is stable Reset sets the X bit As long as the X bit remains set interrupt service requests made via the XIRQ pin are not recognized Software must clear the X bit to enable interrupt service requests from the XIRQ pin Once software clears the X bit enabling XIRQ interrupt requests only a reset can set it again The X bit does not affect I bit maskable interrupt requests When the X bit is clear and an XIRQ interrupt request occurs the CPU stacks the cleared X bit It then automati
459. nt_1 to point_2 Within this interval the tentative values for grade_1 and grade_2 calculated in cycle 3 fall on the crossed sloping sides In step 4a grade gets set to the grade_2 value but in 4b this is overridden by the grade_1 value which ends up as the result of the MEM instruction One way to say this is that the result follows the left sloping side until the input passes point_2 where the result goes to 00 Memory Definition 60 80 04 04 Point_1 Point_2 Slope_1 Slope_2 Graphical Representation How Interpreted P1 P1 P2 Figure B 6 Abnormal Membership Function Case 1 ABN MEM 1 If point_1 was to the right of point_2 flag_d12n would force the result to be 00 for all input values In fact flag_d12n always limits the region of interest to the space greater than or equal to point_1 and less than or equal to point_2 B 5 2 2 Abnormal Membership Function Case 2 Like the previous example the membership function in case 2 is abnormal because the sloping sides cross below the FF cutoff level but the left sloping side reaches the FF cutoff level before the input gets to point_2 In this case the result follows the left sloping side until it reaches the FF cutoff level At this point the grade_1 gt FF term of 4b kicks in making the expression true so grade equals grade no overwrite The result from here to point_2 becomes controlled by the else part of 4a grade grade_2 and the result follows the right slo
460. nterface It is also used by the standard BDM firmware for temporary storage For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc 14 8 6 BDM Address Register Address FF04 Bit 15 14 13 12 11 10 9 Bit 8 Read A15 A14 A13 A12 A11 A10 AQ A8 Write Reset Figure 14 15 BDM Address Register BDMADDH Address FFO5 Bit 7 6 5 4 3 2 1 Bit 0 Figure 14 16 BDM Address Register BDMADDL Read All modes Write Can only be written by BDM hardware In secure mode if the BDM hardware commands have been enabled by the secure firmware the upper 5 bits of the address register will always be forced to the value from the BDMINR register This restricts access of the hardware commands to the register space only The 16 bit address register is loaded with the address to be accessed by BDM hardware commands 14 8 7 Special Peripheral Mode In Special Peripheral Mode the BDM is enabled and active immediately out of reset BDM can be disabled by clearing the BDMACT bit in the BDM status BDMSTS register see 14 8 4 This allows testing the BDM memory space as well as the user s program memory space The BDM serial system should not be used in special peripheral mode since the CPU which in other modes relinquishes control of the bus during a free cycle or a steal operation is not operating in this mode 14 8 8 Standard BDM Firmware Listing KKK KKK KKK KKK KKK KK K
461. o Zero T B E Q Operation CCR Effects Code and CPU Cycles If counter 0 then PC 0003 Rel PC Tests the counter register A B D X Y or SP Branches to a relative destination if the counter register reaches zero Rel is a 9 bit two s complement offset for branching forward or backward in memory Branching range is 100 to OFF 256 to 255 from the address following the last byte of object code in the instruction S X H I N Z V C Machine Source Form Code Hex CPU Cycles PPP branch TBEQ abdxysp rel9 PPO no branch Source Form Offset TBEQ A rel9 0100 X000 A TBEQ B rel9 0100 X001 B TBEQ D rel9 0100 X100 D Positive TBEQ X rel9 0100 X101 xX TBEQ Y rel9 0100 X110 Y TBEQ SP rel9 0100 X111 SP TBEQ A rel9 0101 X000 A TBEQ B rel9 0101 X001 B TBEQ D rel9 0101 X100 D Negative TBEQ X rel9 0101 X101 x TBEQ Y rel9 0101 X110 Y TBEQ SP rel9 0101 X111 SP NOTES 1 Bits 7 6 5 select TBEQ or TBNE bit 4 is the offset sign bit bit 3 is not used bits 2 1 0 select the counter register For More Information On This Product Go to www freescale com Core User Guide TBL Operation CCR Effects Code and CPU Cycles si2cpu A A8gscale Semiconductor Inc Table Lookup and Interpolate T B L M B x M 1 M A Linearly interpolates and stores in A one of 256 values between a pair of data entries Y1 and Y2 in a look
462. o Zero T B N E Operation CCR Effects Code and CPU Cycles If counter 0 then PC 0003 Rel PC Tests the counter register A B D X Y or SP Branches to a relative destination if the counter does not reach zero Rel is a 9 bit two s complement offset for branching forward or backward in memory Branching range is 100 to OFF 256 to 255 from the address following the last byte of object code in the instruction S X H I N Z V C Machine Source Form Code Hex CPU Cycles PPP branch TBNE abdxysp rel9 PPO no branch Source Form Offset TBNE A rel9 0110 X000 TBNE B rel9 0110 X001 TBNE D rel9 0110 X100 Positive TBNE X rel9 0110 X101 TBNE Y rel9 0110 X110 TBNE SP rel9 0110 X111 o o L lt xouw gt S lt xuw gt TBNE A rel9 0111 X000 TBNE B rel9 0111 X001 TBNE D rel9 0111 X100 Negative TBNE X rel9 0111 X101 TBNE Y rel9 0111 X110 TBNE SP rel9 0111 X111 NOTES 1 Bits 7 6 5 select TBEQ or TBNE bit 4 is the offset sign bit bit 3 is not used bits 2 1 0 select the counter register For More Information On This Product Go to www freescale com Core User Guide TFR Operation CCR Effects Code and CPU Cycles si2cpu A A8gscale Semiconductor Inc Transfer Register T F R See the table on the next page Transfers the value in a source register A B CCR D X Y or SP to a destination register A B CCR D X Y
463. o highest priority of the I bit maskable interrupts To promote an interrupt the user writes the least significant byte of the associated interrupt vector address to this register If an unimplemented vector address or a non I bit masked vector address value higher than F2 is written IRQ SFFF2 will be the default highest priority interrupt 10 4 Operation The Interrupt sub block processes all exception requests made by the CPU These exceptions include interrupt vector requests and reset vector requests Each of these exception types and their overall priority level is discussed in the subsections below 10 4 1 Interrupt Exception Requests As shown in Figure 10 1 above the INT mainly contains a register block to provide interrupt status and control an optional Highest Priority I Interrupt HPRIO block and a priority decoder to evaluate whether pending interrupts are valid and assess their priority 10 4 1 1 Interrupt Registers The INT registers are accessible only in special modes of operation and function as described in 10 3 1 and 10 3 2 previously 10 4 1 2 Highest Priority bit Maskable Interrupt When the optional HPRIO block is implemented the user is allowed to promote a single I bit maskable interrupt to be the highest priority I interrupt The HPRIO evaluates all interrupt exception requests and passes the HPRIO vector to the priority decoder if the highest priority I interrupt is active For More Information On This
464. ocoornnr re 95 AS COS Mais reia AA e AAA 97 4 6 Transfer and Exchange Postbyte Encoding s s s sassa aeaea 99 47 Loop Primitive Posibyte lb Encoding 22525 2ccdi ent iced terca are 100 4 8 Indexed Addressing Postbyte xb Encoding 0 cee eee eee 101 Section 5 Instruction Execution 5 1 Normal Instruction Execution n aaan naaa aaea eee eee 103 5 2 Execution Sequence ia ee yen egies Bie eal ce ede weet 103 5 2 1 No MOVE a e Aine aras A ade 103 5 2 2 Advance and Load from Data BUS 2 anaana aana eee eee 103 33 Whanges OF OWN dave be Cee ans oa e 104 5 3 1 Exceptions Sera Se een ee anita kh poate ee ee tae me DA 104 5 3 2 MUBFOUTIMNGS s Ch on wie a a Ae ole ad e go ee Mo Rh Ae oh DA e do Map nhl LA te 104 5 3 3 o O SO 104 5 3 4 A Y A 106 DA MASIROCHON TIMO ar eN E 106 5 4 1 Register and Memory Notation 0 000 eee ee 120 5 4 2 SOURCE FORM NOTA HON sii ee Be ee ee ot Bee Se Pests Se ee Skew 121 5 4 3 Op ration Notation ii ees oes andere TEA ade dere etek 122 5 4 4 Address Mode Notation 2 aa darias oie 122 5 4 5 Machine Code Notation descuida a bie oe ata a Mau oe be ae Ad ad 123 5 4 6 ACCESS Detail NOTA ON IS Sok RS ee es Mee 123 5 4 7 Condition Code State Notation 0 0 0c cee 126 5 5 External Visibility Of Instruction Queue 2 ees 126 5 5 1 Instruction Queue Status Signals 0 00 ee 126 For More Information On This Product Go to www freescale com Co
465. of the Multiplexed External Bus Interface MEBI sub block of the Core 12 1 Overview The MEBI sub block of the Core serves to provide access and or visibility to internal Core data manipulation operations including timing reference information at the external boundary of the Core and or system Depending upon the system operating mode and the state of bits within the control registers of the MEBI the internal 16 bit read and write data operations will be represented in 8 bit or 16 bit accesses externally Using control information from other blocks within the system the MEBI will determine the appropriate type of data access to be generated 12 1 1 Features e External bus controller with four 8 bit ports A B E and K e Data and data direction registers for ports A B E and K when used as general purpose I O e Control register to enable disable alternate functions on Port E and Port K e Mode control register e Control register to enable disable pullups on Ports A B E and K e Control register to enable disable reduced output drive on Ports A B E and K e Control register to configure external clock behavior e Control register to configure IRQ pin operation e Logic to capture and synchronize external interrupt pin inputs For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc 12 1 2 Block Diagram The block diagram of the MEBI sub block is shown in Figure 12 1 bel
466. of the trapezoid has infinite slope vertical If so the result grade should be FF at and to the right of point_1 everywhere within the trapezoid as far as the left side is concerned The grade_1 greater than FF term corresponds to the input being to the right of where the left sloping side passes the FF cutoff level If either of these conditions is true the result grade is left at the For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 value it got from 4a The else condition in 4b corresponds to the input falling on the sloping portion of the left side of the trapezoid or possibly outside the trapezoid so the result is grade equals grade_1 If the input is outside the trapezoid flag_d12n is one and grade_1 and grade_2 would have been forced to 00 in cycle 3 The else condition of 4b sets the result to 00 The following special cases represent abnormal membership function definitions The explanations describe how the specific algorithm in the HCS12 CPU resolves these unusual cases The results are not all intuitively obvious but rather fall out from the specific algorithm Remember these cases should not occur in a normal system B 5 2 1 Abnormal Membership Function Case 1 This membership function is abnormal because the sloping sides cross below the FF cutoff level The flag_d12n signal forces the membership function to evaluate to 00 everywhere except from poi
467. olds the address of the next instruction to be executed The address in PC is automatically incremented each time an instruction is executed Read Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3 7 Program Counter PC 3 1 5 Condition Code Register CCR CCR has five status bits two interrupt mask bits and a STOP instruction mask bit It is named for the five conditions indicated by the status bits The status bits reflect the results of CPU operations The five status bits are half carry H negative N zero Z overflow V and carry borrow C The half carry bit is used only for BCD arithmetic operations The N Z V and C status bits allow for branching based on the results of a CPU operation Most instructions automatically update condition codes so it is rarely necessary to execute extra instructions to load and test a variable The condition codes affected by each instruction are shown in Appendix A of this guide The following paragraphs describe common uses of the condition codes There are other more specialized uses For instance the C status bit is used to enable weighted fuzzy logic rule evaluation Specialized usages are described in the relevant portions of this guide and in Appendix A Bit 7 6 5 4 3 2 1 Bit O Read X H l N Z V C Write Reset 1 1 0 1 0 0 0 0 Figure 3 8 Condition Code Register CCR S STOP Mask Bit Clearing the S bit enables the STOP instruction Execution of a STOP i
468. om Core User Guide s12cpu af Scale Semiconductor Inc This register 1s not in the on chip map in emulation and peripheral modes NOACCE CPU No Access Output Enable Normal write once Emulation write never Special write anytime 1 The associated pin Port E bit 7 is output and indicates whether the cycle is a CPU free cycle 0 The associated pin Port E bit 7 is general purpose I O This bit has no effect in single chip or peripheral modes PIPOE Pipe Status Signal Output Enable Normal write once Emulation write never Special write anytime 1 The associated pins Port E bits 6 5 are outputs and indicate the state of the instruction queue 0 The associated pins Port E bits 6 5 are general purpose I O This bit has no effect in single chip or peripheral modes NECLK No External E Clock Normal and Special write anytime Emulation write never 1 The associated pin Port E bit 4 is a general purpose I O pin 0 The associated pin Port E bit 4 is the external E clock pin External E clock is free running if ESTR 0 External E clock is available as an output in all modes LSTRE Low Strobe LSTRB Enable Normal write once Emulation write never Special write anytime 1 The associated pin Port E bit 3 is configured as the LSTRB bus control output If BDM tagging is enabled TAGLO is multiplexed in on the rising edge of ECLK and LSTRB is driven out on the falling edge of ECLK 0 The associ
469. on e Unsigned branch instructions are executed when a comparison or test of unsigned quantities results in a specific combination of bit states in the condition code register e Signed branch instructions are executed when a comparison or test of signed quantities results in a specific combination of bit states in the condition code register Some branch instructions belong to more than one type 4 3 17 1 Short Branch Instructions When a specified condition is met a short branch instruction adds a signed 8 bit offset to the value in the program counter Program execution continues at the new address The numeric range of short branch offset values is 80 128 to 7F 127 from the address of the next memory location after the offset value A summary of the short branch instructions is given in Table 4 19 Table 4 19 Short Branch Instructions Mnemonic Type Function Condition Equation BRA Branch always 1 1 BRN Branch never 1 0 BCC Branch if carry clear C 0 BCS Branch if carry set C 1 BEQ Branch if equal Z 1 BMI Branch if minus N 1 BNE Branch if not equal Z 0 BPL Branch if plus N 0 BVC Branch if overflow clear V 0 BVS Branch if overflow set V 1 BHI Branch if higher R gt M C Z 0 BHS f Branch if higher or same R gt M C 0 Unsigned BLO Branch if lower R lt M C 1 BLS Branch if lower or same R lt M C Z 1 BGE Branch if greater than or equal R gt M Nev 0 BGT
470. on bytes includes 5 bit constant offset from X Y SP or PC Pre post increment decrement by 1 8 Accumulator A B or D offset IDX1 9 bit signed offset from X Y SP or PC 1 extension byte IDX2 16 bit signed offset from X Y SP or PC 2 extension bytes IDX2 Indexed indirect 16 bit offset from X Y SP or PC D IDX Indexed indirect accumulator D offset from X Y SP or PC A 2 4 Operator Notation Table A 4 Operator Notation Add Subtract e AND OR Exclusive OR x Multiply Divide Concatenate Transfer lt Exchange A 2 5 Machine Code Notation In the Machine Code Hex column on the glossary pages digits 0 9 and upper case letters A F represent hexadecimal values Pairs of lower case letters represent 8 bit values as shown in Table A 5 For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc Table A 5 Machine Code Notation b Exchange transfer postbyte Low eight bits of a 9 bit signed constant offset in indexed addressing or low byte of a 16 bit constant offset in indexed addressing High byte of a 16 bit extended address 8 bit immediate data value High byte of a 16 bit immediate data value Low byte of a 16 bit immediate data value Loop primitive DBNE postbyte Low byte of a 16 bit extended address 8 bit immediate mask value for bit manipulation in
471. on instructions use a combination of two or three addressing modes A BCLR or BSET instruction has an 8 bit mask to clear or set bits in a memory byte The mask is an immediate value supplied with the instruction Direct extended or indexed addressing determines the location of the memory byte A BRCLR or BRSET instruction has an 8 bit mask to test the states of bits in a memory byte The mask is an immediate value supplied with the instruction Direct extended or indexed addressing determines the location of the memory byte Relative addressing determines the branch address A signed 8 bit offset must be supplied with the instruction For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 4 3 Instruction Descriptions A brief discussion of the CPU instructions group by type is given in the subsections below For a detailed instruction by instruction description please consult Appendix A of this guide 4 3 1 Load and Store Instructions Load instructions copy a value in memory or an immediate value into a CPU register The value in memory 1s not changed by the operation Load instructions except LEAS LEAX and LEAY affect condition code bits so no separate test instructions are needed to check the loaded values for negative or zero conditions Store instructions copy the value in a CPU register to memory The CPU register value is not changed by the operation Store instr
472. operation provided that it can be completed in a single cycle However NOTES 1 BDM is enabled and active immediately out of special single chip reset see 14 5 2 2 This method is only available on systems that have a a Breakpoint sub block For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 if an operation requires multiple cycles the CPU is frozen until the operation is complete even though the BDM found a free cycle The BDM hardware commands are listed in Table 14 1 Table 14 1 Hardware Commands Opcode ita Command hex Data Description BACKGROUN 90 None Enter background mode if firmware is enabled 16 bit address Read from memory with standard BDM firmware lookup table in map READ BD BYTE a 16 bit data out Odd address data on low byte even address data on high byte READ BD WORD EC 16 bit address Read from memory with standard BDM firmware lookup table in map 16 bit data out Must be aligned access READ BYTE EO 16 bit address Read from memory with standard BDM firmware lookup table out of 16 bit data out map Odd address data on low byte even address data on high byte bi Read from memory with standard BDM firmware lookup table out of READ_WORD E8 16 bit address y p 16 bit data out map Must be aligned access 16 bit address Write to memory with standard BDM firmware lookup table in map ATE BD SYTE En 16 bit data in Od
473. opr16i Load SP PO LDS opr8a M M 1 SP RPf LDS opr16a or imm SP RPO LDS oprx0_xysppc RP LDS oprx9 xysppc RPO LDS oprx16 xysppc RPP LDS D xysppc fIfRPf LDS oprx16 xysppc fIPRPf LDX opr16i Load X j PO LDX opr8a M M 1 gt X RPf LDX opr16a or imm gt X RPO LDX oprx0_xysppc RPf LDX oprx9 xysppc RPO LDX oprx16 xysppc fRPP LDX D xysppc fIfRPf LDX oprx16 xysppc fIPRPf LDY opr16i Load Y IMM CD jj kk PO l lala o LDY opr8a M M 1 gt Y DIR DD dd RPf LDY opr16a or imm gt Y EXT FDhh11 RPO LDY oprx0_xysppc IDX ED xb RPf LDY oprx9 xysppc IDX1 ED xb ff RPO LDY oprx16 xysppc IDX2 ED xbee ff fRPP LDY D xysppc D IDX ED xb fIfRP LDY oprx16 xysppc IDX2 ED xbee ff fIPRP For More Information On This Product Go to www freescale com Core User Guide siocpuimtaRscale Semiconductor Inc Source Form LEAS oprx0_xysppc LEAS oprx9 xysppc LEAS oprx16 xysppc LEAX oprx0_xysppc LEAX oprx9 xysppc LEAX oprx16 xysppc Operation Load effective address into SP EA gt SP Load effective address into X EA gt X Address Mode Machine Coding Hex Access Detail PE PO PP SXHINZVC LEAY oprx0_xysppc LEAY oprx9 xysppc LEAY oprx16 xysppc Load effective address into Y EA Y Pf PO PP LSL opr16aSame as ASL LSL oprx0_xysppc LSL oprx9 xysppc LSL oprx16 xysppc LSL D xysppc LSL oprx16 xysppc LSLASame as ASLA LSLBSame as ASLB
474. oprx16 xysppc INCA INCB Increment M M 1 gt M Increment A A 1 gt A Increment B B 1 gt B 72hh11 62 xb 62 xb ff 62 xbee ff 62 xb 62 xbee ff 42 52 rPwO rPw rPwO frPwP fIfrPw fIPrPw O O INSSame as LEAS 1 SP Increment SP SP 1 SP 1B 81 Pf INX Increment X X 1 gt X 08 INY Increment Y Y 1 gt Y 02 JMP opr16a JMP oprx0_xysppc JMP oprx9 xysppc JMP oprx16 xysppc JMP D xysppc JMP oprx16 xysppc Jump Subroutine address gt PC 06hh11 05 xb 05xbff 05 xbeeff 05 xb 05 xbeeff U HH U0 0 g PPP JSR opr8a JSR opr16a JSR oprx0_xysppc JSR oprx9 xysppc JSR oprx16 xysppc JSR D xysppc JSR oprx16 xysppc Jump to subroutine SP 2 gt SP RTNy RTN gt Mgp Mgp 4 Subroutine address gt PC 17 dd 16hh11 15 xb 15xb ff l5xbee ff 15 xb 15xbee ff p p S S PS PPPS PPPS h UU WM hh th FO FO tU FU U O tU tU Fh Fh HH Fy Fh LBCC re 16Same as LBHS LBCS re 16Same as LBLO LBEQ rel16 Long branch if C clear if C 0 then PC 4 rel gt PC Long branch if C set if C 1 then PC 4 rel gt PC Long branch if equal if Z 1 then PC 4 rel gt PC 1824gqq rr 1825qq rr 1827 qqrr P branch no branch P branch no branch P branch no branch LBGE rel16 LBGT
475. or onto stack PULC Inherent Pull CCR from stack PULD Inherent Pull double accumulator from stack REV Special Fuzzy logic rule evaluation REVW Special Fuzzy logic rule evaluation with weights Restore program page and return address from stack used with puke Inherent CALL instruction allows easy access to extended space SEX Inherent Sign extend 8 bit register into 16 bit register TBEQ Relative Test and branch if equal to zero looping primitive TBL Inherent Table lookup and interpolate 8 bit entries TBNE Relative Test register and branch if not equal to zero looping primitive TFR Inherent Transfer register contents to another register WAV Special Weighted average fuzzy logic support For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc C 7 2 Memory to Memory Moves The HCS12 has both 8 and 16 bit variations of memory to memory move instructions The source address can be specified with immediate extended or indexed addressing modes The destination address can be specified by extended or indexed addressing mode Indexed addressing for move instructions is limited to direct indexing modes that require no extension bytes 9 and 16 bit constant offsets are not allowed This leaves the 5 bit signed constant offset accumulator offset and the autoincrement decrement modes The following simple loop is a block move routine capable of moving up to 256 words of information fro
476. orbed into the LDAA indexed instruction The replacement code is not identical to the original three instruction sequence because the Z bit is affected by the M68HC11 INY instructions while the Z bit in the HCS12 is determined by the value loaded into A C 5 3 Accumulator Offset Indexing This indexed addressing variation allows the programmer to use either an 8 bit accumulator A or B or the 16 bit D accumulator as the offset for indexed addressing This allows for a program generated offset which is more difficult to achieve in the M68HC11 The following code compares the M68HC11 and HCS12 operations C6 05 LDAB 05 2 CE 10 00 LOOP LDX 1000 3 c6 05 LDAB 05 1 3A ABX 3 CE 10 00 LDX 1000 2 A6 00 LDAA 0 X 4 A6 E5 LOOP LDAA B X 3 5A DECB 2 04 31 FB DBNE B LOOP 3 26 F7 BNE LOOP 3 The HCS12 object code is only one byte smaller but the LDX instruction is outside the loop It is not necessary to reload the base address in the index register on each pass through the loop because the LDAA B X instruction does not alter the index register This reduces the loop execution time from 15 cycles to six cycles For More Information On This Product Go to www freescale com Core User Guide si2cru ERA Scale Semiconductor Inc C 5 4 Indirect Indexing The HCS12 allows some forms of indexed indirect addressing in which the instruction points to a location in memory where the address of the operand is stored This is an
477. ore For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 6 3 1 3 COP Reset A Computer Operating Properly COP sub block helps protect against software failures When the COP is enabled software might for example write a particular code sequence to a specific address in order to keep a watchdog timer from timing out If software fails to execute the sequence properly the sub block will typically then request a reset vector from the Core 6 3 2 Interrupts The Core supports the following types of interrupt sources e nonmaskable interrupt requests Unimplemented Opcode Trap Software Interrupt instruction XIRQ pin interrupt request e Maskable interrupt requests Optional highest priority maskable interrupt defaults to IRQ pin IRQ pin interrupt request System peripheral block I bit maskable interrupt requests A block or blocks within the SoC design must evaluate the system peripheral block I bit maskable interrupt sources and request the proper interrupt vector from the Core All other interrupt requests are handled within the Core Once the CPU receives the request it then fetches the vector to the proper interrupt service routine The CPU will then calculate and stack a return address and the contents of the CPU registers Finally it will set the I bit and the X bit if XIRQ is the source and fill the instruction queue from the addres
478. orm the address 0020 Since the LDX instruction requires a 16 bit value a 16 bit word of data is read from addresses 0020 and 0021 After execution the X index register has the value from address 0020 in its high byte and the value from address 0021 in its low byte 4 2 5 Extended Addressing Mode In extended addressing the full 16 bit address of the memory location to be operated on is provided in the instruction Extended addressing can access any location in the 64K byte memory map LDAA FO3B For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc The value from address F03B is loaded into the A accumulator 4 2 6 Relative Addressing Mode Relative addressing is for branch instructions only Relative addressing determines the branch destination The short and long versions of conditional branch instructions use relative addressing exclusively The branching bit condition instructions BRSET and BRCLR use multiple addressing modes including relative mode A conditional branch instruction tests a status bit in the condition code register If the bit tests true execution begins at the destination formed by adding an offset to the address of the memory location after the offset If the bit does not test true execution continues with the instruction that follows the branch instruction A short conditional branch instruction has an 8 bit opcode and a signed 8 bit r
479. ormation On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc BITB Bit Test B BITB Operation CCR Effects Code and CPU Cycles B M or B imm Performs a logical AND of either the value in M or an immediate value with the value in B CCR bits reflect the result The values in B and M do not change N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Machine Source Form Code Hex CPU Cycles BITB opr8i c5 ii BITB opr8a D5 dd BITB opr16a F gt hh 11 BITB oprx0_xysppc E5 xb BITB oprx9 xysppc E5 xb ff BITB oprx16 xysppc E5 xb ee ff BITB D xysppc E5 xb BITB oprx16 xysppc E5 xb ee ff For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 B L E Branch if Less Than or Equal to Zero B L E Operation IfZ N V 1 then PC 0002 rel gt PC BLE can be used to branch after subtracting or comparing signed two s complement values After CMPA CMPB CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the CPU register value is less than or equal to the value in M After CBA or SBA the branch occurs if the value in B is less than or equal to the value in A Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address foll
480. orporate operating modes that allow for an 8 bit data bus so that a system can be built with low cost 8 bit program memory HCS12 based systems include an on chip block in the Core that manages the external bus interface When the CPU makes a 16 bit access to a resource that is served by an 8 bit bus the Core performs two 8 bit accesses freezes the CPU clocks for part of the sequence and assembles the data into a 16 bit word As far as the CPU is concerned there is no difference between this access and a 16 bit access to an internal resource via the 16 bit data bus This is similar to the way an M68HC11 can stretch clock cycles to accommodate slow peripherals C 4 2 Instruction Queue The CPU has a three word instruction queue for storing program information All program information is fetched from memory as aligned 16 bit words even though there is no requirement for instructions to begin or end on even word boundaries There is no penalty for misaligned instructions If a program begins on an odd boundary if the reset vector is an odd address program information is fetched to fill the For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc instruction queue beginning with an aligned word read at the natural boundary of the misaligned reset vector The instruction queue logic starts execution with the opcode in the low half of this word The instruction queue makes three byte
481. otation 22 002 abbess 24240405 20h ada Source Form Notation sis a AAA ARANA E da Operation Notation soda circadiano d Address Mode Notation li A a A A Dita Eo e Machine Code NO ton 2 3 ese as Dit SE eater te eee et dls Access Detail Notation 0900 be ce Dio Die a Roe OS tale dm did paren ede Oe Se Condition Code State Notation ste oe oti e eee San wo eed Section 2 Nomenclature 2 1 2 2 2 3 2 4 A A irate QS GO hides Planck A amarante dies Xe Lis ad MEASURES acond hee ee eines ohn babe ee eerie tees oaks So A s Ea A E S SEE E ESE A a ar a EE ENRE EESE EE OA Gea ema See PSH Terminology e 2220 nents oad ua pet SA Aa a Ce Section 3 Core Registers 3 1 3 1 1 3 1 2 3 1 3 3 1 4 3 1 5 3 2 Programming Models it AS a AAA eR RS A cakes o A Beta Lucca eienaar SRG De Den JOOS Mey Se IS Bos wie dee ai BG ee wl Index Registers X and Mires Hey Yue be oe eG barks He Rent cine Maes sa ee Stack Pointer A EE Daa ia Tai a BE AASE E EO AEE a a A E REENA EE Program Gounod 0266 45 45 Gein dr Condition Code Register OEA ide wee a eb ere EE Gore Register MaDi cons idear For More Information On This Product Go to www freescale com 12CPU15UG V1 2 Core User Guide si2cpu A A8gscale Semiconductor Inc Section 4 Instructions 4 1 4 2 4 2 1 4 2 2 4 2 3 4 2 4 4 2 5 4 2 6 4 2 7 4 2 8 4 3 4 3 1 4 3 2 4 3 3 4 3 4 4 3 5 4 3 6 4 3 7 4 3 8 4 3 9 4 3 10 4 3 11 4 3 12 4 3 13 4 3 14 4 3 15 4 3 16 4 3 17
482. otherwise Z Set if result is 00 cleared otherwise V NO C N e C N C for N and C after the shift set if N is set and C is cleared or N is cleared and C is set cleared otherwise for values of N and C after the shift C M7 set if the LSB of M was set before the shift cleared otherwise Source Form Code Hew CPU Cycles LSL opr16a 78 hh 11 rPwO LSL oprx0_xysppc 68 xb rPw LSL oprx9 xysppc 68 xb ff rPwO LSL oprx16 xysppc 68 xb ee ff frPPw LSL D xysppc 68 xb flfrPw LSL oprx16 xysppc 68 xb ee ff fIPrPw For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 LSLA Logical Shift Left A LSLA Operation CCR Effects Code and CPU Cycles 57 v6 b5 ba ba p2 bt bo j 0 A Shifts all bits of A one place to the left Loads bit 0 with 0 Loads the C bit is from the most significant bit of A S X H N Z V C 4 Aa a A N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C NeC NC for N and C after the shift set if N is set and C is cleared or N is cleared and C is set cleared otherwise for values of N and C after the shift C A7 set if the LSB of A was set before the shift cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles LSLA INH 48 O For More Information On This Product Go to www
483. otherwise it won t pass the brset STATUS 80 INST_LOOP test and the user gets kicked out of background unintentionally The Dev Tools PRU relies on the BDM entry point START being at location FF24 They also rely on the exit point being at location FF77 the exit jump Any changes to the start and exit points MUST be reviewed with them Be careful that the BDMACT bit in the STATUS register is h ct For More Information On This Product Go to www freescale com Core User Guide si2crui HABg SCale Semiconductor Inc not unintentionally changed from a 1 to a 0 during 16 bit manipulation of the INSTRUCTION register race condition because BDMACT 0 will disable the standard BDM firmware This will cause a ROM while the CPU is executing this firmware This is a list of instructions which use the temp2 List as of 7 27 94 instructions temp wai wav 2 execution of BDM ROM t2 Gotten from Tom Poterek s BDMcode and temp3 t3 KKK KKK KKK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KEK KKK KKK KKK RARA RARA KKK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KKK KKK KKK KK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK fff6 ff00 ff00 EQUATES BDMVE equsfff6 org ff00 INSTR rmb1 s w H S DATA R W hdw H S DATA R W Reg codes R2 R1 R0O 0 0 0 Illegal 0 0
484. out the Core secured mode of operation that is for Motorola use only and should not be published in any form outside of Motorola 15 5 1 BDM Secured Mode Firmware When the Core is operating in secured mode and the system is reset into special single chip mode alternate BDM firmware is invoked in place of the standard BDM firmware A listing of this secured mode firmware is given in 14 8 9 of this guide For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 Appendix A Instruction Set and Commands A 1 General This glossary contains entries for all assembler mnemonics in alphabetical order Each entry describes the operation of the instruction its effect on the condition code register and its syntax A 2 Glossary Notation A 2 1 Condition Code State Notation Table A 1 Condition Code State Notation Not changed by operation Cleared by operation Set by operation Set or cleared by operation May be cleared or remain set but not set by operation May be set or remain cleared but not cleared by operation May be changed by operation but final state not defined Used for a special purpose v gt DP gt po lI For More Information On This Product Go to www freescale com Core User Guide A 2 2 Register
485. ow 16 8 altab 15 0 SSS SS 16 8 lt a _ PAZ PAO A15 A08 x lo gt D15 08 Ha S D7 DO altwdb 15 0 External PB7 PBO altrdb 15 0 8 LATAO Data Bus ES DDR B PORT B db 15 0 Interface clock A reg_select reset Registers mdrste lt 4 ab 15 0 int_mem_sel External rw cpu Pipe 0 Bus Conve wi 6 PE7 PE2 J A E gt bus sigs altsz3 4 aja altrw Q Ss on ab e PE1 R xirq_t4 sync capture l PEO XIRO 28 QE gt BKGD extbdm N L m S 8 Port K She 8 mmecs ort oc E le Y py PK7 PKO mmexa f Control O 5 CS XA ao Figure 12 1 MEBI Block Diagram In the figure the signals on the right hand side represent pins that are accessible externally to the Core and or system 12 2 Interface Signals Much of the interfacing with the MEBI sub block is done within the Core however many of the MEBI signals pass through the Core boundary and interface with the system port pad logic for Ports A B E and For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 K The Core interface signals associated with the MEBI are shown in Table 12 1 below The functional descriptions of the signals are provided below for completeness Table 12 1 MEBI Interface Signal Definitions Signal Name Type Functional Description core_paind 7
486. owed however if this occurs nothing will happen within the BKP The BKP allows breaking within a 256 byte address range and or within expanded memory It allows matching of the data as well as the address and to match 8 bit or 16 bit data Forced breakpoints can match on a read or a write cycle 13 1 1 Features e Full or Dual Breakpoint Mode Compare on address and data Full Compare on either of two addresses Dual e BDM or SWI Breakpoint Enter BDM on breakpoint BDM Execute SWI on breakpoint SWI e Tagged or Forced Breakpoint Break just before a specific instruction will begin execution TAG Break on the first instruction boundary after a match occurs Force e Single Range or Page address compares Compare on address Single Compare on address 256 byte Range For More Information On This Product Go to www freescale com Core User Guide siocpursuea scale Semiconductor Inc Compare on any 16K Page Page e Compare address on read or write on forced breakpoints e High and or low byte data compares 13 1 2 Block Diagram A block diagram of the Breakpoint sub block is shown in Figure 13 1 below The Breakpoint contains three main sub blocks the Register Block the Compare Block and the Control Block The Register Block consists of the eight registers that make up the Breakpoint register space The Compare Block performs all required address and data signal comparisons The Control Block
487. owing the last byte of object code in the instruction CCR Effects S XH I N ZV C Code and CPU Source Form derma Object Code CPU Cycles Cycles BLE rel8 REL 2F rr PPP branch P no branch Branch Complementary Branch Comment Mnemonic Opcode Test R gt M Mnemonic Opcode BLE Unsigned For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc BLO Branch if Lower BLO Operation CCR Effects Code and CPU Cycles If C 1 then PC 0002 rel PC BLO can be used to branch after subtracting or comparing unsigned values After CMPA CMPB CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the CPU register value is less than the value in M After CBA or SBA the branch occurs if the value in B is less than the value in A BLO is not for branching after instructions that do not affect the C bit such as increment decrement load store test clear or complement Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction S X H I N Z V C Address Machine Source Form Mode Code Hex CPU Cycles BLO rel8 REL 25 rr PPP branch P no branch Branch Compl
488. pc IDX2 68 xbee ff IPrPw For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc ASLA ee ASLA Operation CCR Effects Code and CPU Cycles 157 v6 b5 ba ba b2 bt bo j 0 A Shifts all bits of A one bit position to the left Bit 0 is loaded with a 0 The C bit is loaded from the most significant bit of A N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V NO C setif Nis setand C is cleared after the shift or Nis cleared and C is set after the shift cleared otherwise C A7 set if the MSB of A was set before the shift cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles ASLA INH 48 O For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 ASLB dad ASLB Operation CCR Effects Code and CPU Cycles 57 v6 bs ba ba p2 bt bo j 0 B Shifts all bits of B one bit position to the left Bit 0 is loaded with a 0 The C bit is loaded from the most significant bit of B N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V NO C set if N is set and C is cleared after the shift or N is cleared and C is set after the shift cleared otherwise C B7 set if
489. pc EMINM oprx9 xysppc EMINM oprx16 xysppc EMINM D xysppc EMINM oprx16 xysppc Extended minimum in D put smaller of 2 unsigned 16 bit values in D MIN D M M 1 gt D N Z V C bits reflect result of internal compare D M M 1 Extended minimum in M put smaller of 2 unsigned 16 bit values in M MIN D M M 1 M M 1 N Z V C bits reflect result of internal compare D M M 1 IDX IDX1 IDX2 D IDX IDX2 IDX IDX1 IDX2 D IDX IDX2 ORP ORPO OfRPP OfIfRP OfIPRP ORPW ORPWO OfRPWP OfIfRPW OfIPRPW EMUL Extended multiply unsigned D x Y Y D 16 by 16 to 32 bit INH ffO EMULS Extended multiply signed D x Y Y D 16 by 16 to 32 bit INH Of0 Of 0 if followed by page 2 instruction EORA opr8i EORA opr8a EORA opr16a EORA oprx0_xysppc EORA oprx9 xysppc EORA oprx16 xysppc EORA D xysppc EORA oprx16 xysppc EORB opr8i EORB opr8a EORB opr16a EORB oprx0_xysppc EORB oprx9 xysppc EORB oprx16 xysppc EORB D xysppc EORB oprx16 xysppc ETBL oprx0_xysppc Before executing ETBL initialize B wit indirect addressing allowed Exclusive ORA A M gt A or A imm gt A Exclusive ORB B M gt B or B imm gt B Extended table lookup and interpolate 16 bit M M 1 B x M 2 M 3 M M 1 gt D D8 dd F8hh11 E8 xb E8 xb ff
490. peration E 7 es oa Tor oo 6 B Shifts all bits of B one place to the right Bit 7 is held constant Bit 0 is loaded into the C bit This operation effectively divides a two s complement value by two without changing its sign The carry bit can be used to round the result CCR Effects S X H I A A A N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V NO C set if N is set and C is cleared after the shift or N is cleared and C is set after the shift cleared otherwise C BO set if the LSB of B was set before the shift cleared otherwise Code and CPU Source Form arbi code Hew CPU Cycles Cycles For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc BCC ment Sar BCC same as BHS Operation If C 0 then PC 0002 rel PC Tests the C bit and branches if C 0 Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction CCR Effects S XH IN ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex BCC rel8 REL 24 rr PPP branch P no branch Branch Complementary Branch Comment Mnemonic Opcode Mnemonic Opcode Test BCC BHS BCS BLO
491. ping side For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc Memory Definition 60 C0 04 04 Point_1 Point_2 Slope_1 Slope_2 Graphical Representation How Interpreted WA P1 Left Side P2 Crosses FF CERAS Figure B 7 Abnormal Membership Function Case 2 B 5 2 3 Abnormal Membership Function Case 3 The membership function in case 3 is abnormal because the sloping sides cross below the FF cutoff level and the left sloping side has infinite slope In this case 4a is not true so grade equals grade_2 4b is true because slope_1 is zero so 4b does not overwrite grade Memory Definition 60 80 00 04 Point_1 Point_2 Slope_1 Slope _2 Graphical Representation How Interpreted P1 P2 P1 P2 Figure B 8 Abnormal Membership Function Case 3 ABN MEM 3 B 6 REV REVW Instruction Details This section provides a more detailed explanation of the rule evaluation instructions REV and REVW The data structures that specify rules are somewhat different for the weighted versus unweighted versions of the instruction One uses 8 bit offsets in the encoded rules while the other uses full 16 bit addresses This affects the size of the rule data structure and execution time B 6 1 Unweighted Rule Evaluation REV This instruction implements basic min max rule evaluation CPU registers are used for pointers and intermediate calculation results Sin
492. ppc oprx0_xysppc IDX IDX 18 0A x MOVW oprx16 opr16a Move word IMM EXT 18 03 jj MOVW opr16i oprx0_xysppc Memory to memory 16 bitword move IMM IDX 18 00 x MOVW opr16a opr16a My My 1 gt M gt M gt 1 EXT EXT 18 04h MOVW opr16a oprx0_xysppc First operand specifies word to move EXT IDX 18 01 x MOVW oprx0_xysppc opr16a IDX EXT 18 05x MOVW oprx0_xysppc oprx0_xysppc IDX IDX 1802x MUL Multiply unsigned 12 A x B gt A B 8 by 8 bit NEG opr16a Negate M 0 M M or M 1 M 70hh11 rPwO NEG oprx0_xysppc 60 xb rPw NEG oprx9 xysppc 60 xb ff rPwO NEG oprx16 xysppc 60xbee ff frPwP NEG D xysppc 60 xb flfrPw NEG oprx16 xysppc _ 60xbee ff fIPrPw NEGA Negate A 0 A A or A 1 A 40 NEGB Negate B 0 B 8B or B 1 gt B 50 NOP No operation A7 ORAA opr8i OR accumulator A 8Aii ORAA opr8a A M gt A 9A dd rPf ORAA opr16a or A imm A BAhh 11 rPO ORAA oprx0_xysppc AA xb rPf ORAA oprx9 xysppc AA xb ff rPO ORAA oprx16 xysppc AAxbee ff frPP ORAA D xysppc AA xb flfrPf ORAA oprx16 xysppc AAxbee ff fIPrPf ORAB opr8i OR accumulator B CAii P ORAB opr8a B M gt B DA dd rPf ORAB opr16a or B imm B FAhh11 rPO ORAB oprx0_xysppc EA xb rPf ORAB oprx9 xysppc EA xb ff rPO ORAB oprx16 xysppc EA xb ee ff frPP ORAB D xysppc EA xb flfrPf ORAB oprx16 xysppc EA xbee ff fIPrPf ORCC opr
493. pr16a CPX oprx0_xysppc CPX oprx9 xysppc CPX oprx16 xysppc CPX D xysppc CPX oprx16 xysppc Compare SP SP M M 1 or SP imm Compare X X M M 1 or X imm 8F jj kk 9F dd BFhh11 AF xb AF xb ff AF xbee ff AF xb AF xbee ff PO RP RPO RP RPO TRPE fIfRP fIPRP PO RP RPO RP RPO fRPP fIfRP fIPRP CPY opr16i CPY opr8a CPY opr16a CPY oprx0_xysppc CPY oprx9 xysppc CPY oprx16 xysppc CPY D xysppc CPY oprx16 xysppc Compare Y Y M M 1 or Y imm PO RP RPO RP RPO fRPP fIfRP fIPRP DAA Decimal adjust A for BCD DBEQ abdxysp rel9 Decrement and branch if equal to 0 counter 1 gt counter if counter 0 then branch branch no branch DBNE abdxysp rel9 Decrement andbranch if not equal to 0 counter 1 gt counter if counter 0 then branch PP branch PO no branch DEC opr16a Decrement M M 1 M EXT 73hh11 rPwO Talalay DEC oprx0_xysppc IDX 63 xb rPw DEC oprx9 xysppc IDX1 63 xb ff rPwO DEC oprx16 xysppc IDX2 63 xb ee ff frPwP DEC D xysppc D IDX 63 xb fIfrPw DEC oprx16 xysppc IDX2 63 xb ee ff fIPrPw DECA Decrement A A 1 gt A INH 43 O DECB Decrement B B 1 B INH 53 O DESSame as LEAS
494. priority and vector addresses assigned to these reset sources are shown in Table 6 2 below Please note that the inclusion of Crystal Monitor and COP reset requests is based upon the two most common and predominately used requests historically implemented in HC12 based systems It is assumed that all systems will have a system reset Each SoC integration of the Core will determine whether the system contains both requests one or the other or neither request Each source is described in the subsections that follow Table 6 2 Reset Sources Reset Exception Vector Source Priority Address System reset 1 FFFE FFFF Crystal Monitor block 2 FFFC FFFD Computer Operating Properly COP block 3 FFFA FFFB 6 3 1 1 System reset All systems generally have a block or sub block within the system that determines the validity and priority of all possible sources of a system reset request When a valid system reset request becomes active the block or sub block will request the appropriate reset vector from the Core The Core will then acknowledge the request and provide the vector 6 3 1 2 Crystal Monitor Reset A Crystal Monitor sub block typically contains a mechanism to determine whether or not the system clock frequency is above a predetermined limit If the clock frequency falls below the limit when the Crystal Monitor is enabled the sub block will typically request the reset vector that is associated with this function from the C
495. pt For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc WAV Calculate Weighted Average W AV Operation CCR Effects Code and CPU Cycles Partial product M pointed to by X x M pointed to by Y Sum of products 24 bit SOP previous SOP partial product Sum of weights 16 bit SOW previous SOW M pointed to by Y X 0001 X Y 0001 Y B 01 gt B Repeat until B 00 leave SOP in Y D SOW in X Calculates weighted averages of values in memory Uses indexed X addressing to access one source operand list and indexed Y addressing mode to access another source operand list Accumulator B is the counter that controls the number of elements to be included in the weighted average For each data point pair a 24 bit SOP and a 16 bit SOW accumulates in temporary registers When B reaches zero no more data pairs the SOP goes in Y D The SOW goes in X To get the final weighted average divide Y D by X with an EDIV after the WAV WAV can be interrupted If an interrupt occurs the intermediate results six bytes are stacked in the order SOW 5 9 SOP 15 0 00 SOP 93 16 The wavr pseudoinstruction resumes WAV execution The interrupt mechanism is reentrant new WAV instructions can be started and interrupted while a previous WAV instruction is interrupted Z Set H N V and C may be altered by
496. quires that the queue be refilled so that execution can continue at a new address First the effective address of the destination is determined then the CPU performs three program word fetches from that address For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc 5 4 7 Condition Code State Notation Table 5 8 Condition Code State Notation Not changed by operation Cleared by operation Set by operation Set or cleared by operation May be cleared or remain set but not set by operation May be set or remain cleared but not cleared by operation May be changed by operation but final state not defined Used for a special purpose s gt E o 5 5 External Visibility Of Instruction Queue The instruction queue buffers program information and increases instruction throughput The queue consists of three 16 bit stages Program information is always fetched in aligned 16 bit words Normally at least three bytes of program information are available to the CPU when instruction execution begins Program information is fetched and queued a few cycles before it is used by the CPU In order to monitor cycle by cycle CPU activity it is necessary to externally reconstruct what is happening in the instruction queue Two external pins IPIPE 1 0 provide time multiplexed information about data movement in the queue and instruction execution To co
497. r Guide si2cpu ERA Scale Semiconductor Inc L B G E Long Branch if Greater Than or Equal to L B G E Zero Operation IfN V 0 PC 0004 rel PC LBGE can be used to branch after subtracting or comparing signed two s complement values After CMPA CMPB CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the CPU register value is greater than or equal to the value in M After CBA or SBA the branch occurs if the value in B is greater than or equal to the value in A Rel is a 16 bit two s complement offset for branching forward or backward in memory Branching range is 8000 to 7FFF 32768 to 32767 from the address following the last byte of object code in the instruction CCR Effects S XH N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex 18 2C qq rr OPPP branch LBGE rel16 REL OPO no branch Branch Complementary Branch Comment Mnemonic Opcode Test R lt M Mnemonic Opcode LBHS LBCC LBLO LBCS For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 L B G T Long Branch if Greater Than Zero L B G T Operation CCR Effects Code and CPU Cycles If Z N V 0 then PC 0004 rel gt PC LBGT can be used to branch after subtracting or comparing signed two s complement values After CMPA CMPB
498. r More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc D B EQ Decrement and Branch if Equal to Zero D B EQ Operation counter 1 counter If counter 0 then PC 0003 rel PC Subtracts one from the counter register A B D X Y or SP Branches to a relative destination if the counter register reaches zero Rel is a 9 bit two s complement offset for branching forward or backward in memory Branching range is 100 to O0FF 256 to 255 from the address following the last byte of object code in the instruction CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex REL 04 lb rr PPP branch DBEQ abdxysp rel9 9 bit PPO no branch Loop Primitive Postbyte 1b Coding Source Counter Form Postbyte Register DBEQ A rel9 0000 X000 A DBEQ B rel9 B D xX Y DBEQ SP rel9 SP DBEQ A rel9 0001 X000 04 10 rr A DBEQ B rel9 0001 X001 04 11 rr B DBEQ D rel9 0001 X100 04 14 rr D Negative DBEQ X rel9 0001 X101 04 15 rr X DBEQ Y rel9 0001 X110 0416rr Y DBEQ SP rel9 0001 X111 0417rr SP NOTES 1 Bits 7 6 5 select DBEQ or DBNE bit 4 is the offset sign bit bit 3 is not used bits 2 1 0 select the counter register For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 D B N E Decrement and
499. r of 2 unsigned 8 bit values in M MAX A M gt M N Z V C bits reflect result of internal compare A M Determine grade of membership u grade gt My X 4 gt X Y 1 gt Y If A lt P1 or A gt P2 then u 0 else u MIN A P1 xS1 P2 A xS2 FF A current crisp input value X points at 4 data bytes P1 P2 S1 S2 ofa trapezoidal membership function Y points at fuzzy input RAM location Special OrPw OrPwO OfrPwP OfIfrPw OfIPrPw MINA oprx0_xysppc MINA oprx9 xysppc MINA oprx16 xysppc MINA D xysppc MINA oprx16 xysppc MINM oprx0_xysppc MINM oprx9 xysppc MINM oprx16 xysppc MINM D xysppc MINM oprx16 xysppc Minimum in A put smaller of 2 unsigned 8 bit values in A MIN A M gt A N Z V C bits reflect result of internal compare A M Minimum in N put smaller of two unsigned 8 bit values in M MIN A M gt M N Z V C bits reflect result of internal compare A M For More Information On This Product Go to www freescale com OrPf OrPO OfrPP OfIfrPf OfIPrPf OrPw OrPwO OfrPwP OfIfrPw OfIPrPw Core User Guide si2cru ERA Scale Semiconductor Inc Address Machine Source Form Operation Mode Coding Hex Access Detail SXHINZVC MOVB opr8 opr16a Move byte IMM
500. r the M68HC11 For offsets of 0 to 15 from the Y index register the object code is one byte smaller than it was for the M68HC11 C 5 1 Constant Offset Indexing The HCS12 offers three variations of constant offset indexing in order to optimize the efficiency of object code generation The most common constant offset is zero Offsets of 1 2 4 are used fairly often but with less frequency than zero The 5 bit constant offset variation covers the most frequent indexing requirements by including the offset in the postbyte This reduces a load accumulator indexed instruction to two bytes of object code and matches the object code size of the smallest M68HC11 indexed instructions which can only use X as the index register The HCS12 can use X Y SP or PC as the index reference with no additional object code size cost The signed 9 bit constant offset indexing mode covers the same positive range as the M68HC11 8 bit unsigned offset The size was increased to nine bits with the sign bit ninth bit included in the postbyte and the remaining 8 bits of the offset in a single extension byte The 16 bit constant offset indexing mode allows indexed access to the entire normal 64K byte address space Since the address consists of 16 bits the 16 bit offset can be regarded as a signed 32 768 to 32767 or unsigned 0 to 65 535 value In 16 bit constant offset mode the offset is supplied in two extension bytes after the opcode and postbyte
501. ranch P no branch p branch no branch BRA relg8 Branch if not equal to 0 if Z 0 then PC 2 rel PC Branch if plus if N 0 then PC 2 rel gt PC Branch always For More Information On This Product Go to www freescale com P branch no branch PP branch P no branch Core User Guide siocpuimtaRscale Semiconductor Inc Source Form BRCLR opr8a msk8 rel8 BRCLR opr16a msk8 rel8 BRCLR oprx0_xysppc msk8 rel8 BRCLR oprx9 xysppc msk8 rel8 BRCLR oprx16 xysppc msk8 rel8 BRN rel8 Operation Branch if bit s clear if M e mask byte 0 then PC 2 rel gt PC Branch never Address Mode Machine Coding Hex 4F dd mm rr 1F hh11mmrr OF xb mm rr OF xb ff mmrr OF xb ee ff mmrr 21r E Access Detail SXHINZVC BRSET opr8 msk8 rel8 BRSET opr16a msk8 rel8 BRSET oprx0_xysppc msk8 rel8 BRSET oprx9 xysppc msk8 rel8 BRSET oprx16 xysppc msk8 rel8 Branch if bit s set if M e mask byte 0 then PC 2 rel gt PC 4E dd mm rr 1Ehh11mmrr OE xb mm rr OE xb ff mmrr OE xb ee ff mmrr BSET opr8 msk8 BSET opr16a msk8 BSET oprx0_xysppc msk8 BSET oprx9 xysppc msk8 BSET oprx16 xysppc msk8 Set bit s in M M mask byte M 4C dd mm 1C hh 11mm OC xb mm OC xb f f mm OC
502. range of one set and into the range of an adjacent set the first set becomes progressively less true while the second set becomes progressively more true Fuzzy logic has membership functions that emulate human perceptions such as temperature is warm in which humans recognize gradual boundaries This perception seems to be important to the human ability to solve certain types of complex problems that elude traditional control methods Fuzzy sets are a means of using linguistic expressions such as temperature is warm as labels in rules that can be evaluated with a high degree of numerical precision and repeatability A specific set of input conditions always produces the same result just as a conventional control system does For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc A microcontroller based fuzzy logic control system has two parts e A fuzzy inference kernel which is executed periodically to determine system outputs based on current system inputs A knowledge base which contains membership functions and rules Figure B 1 is a block diagram of this kind of fuzzy logic system The knowledge base can be developed by an application expert without any microcontroller programming experience Membership functions are simply expressions of the expert s understanding of the linguistic terms that describe the system to be controlled Rules are ordinary languag
503. ration produces a two s complement overflow cleared otherwise C A7 M7 M7 e R7 R7 e A7 set if M is larger than A cleared otherwise Condition code bits reflect internal subtraction R A M Address Machine Source Form Mode Code Hex CPU Cycles MAXM oprx0_xysppc IDX 18 1C xb OrPw MAXM oprx9 xysppc IDX1 18 1C xb ff OrPwO MAXM oprx16 xysppc IDX2 18 1C xb ee ff OfrPwP MAXM D xysppc D IDX 18 1C xb OfIfrPw MAXM oprx16 xysppc IDX2 18 1C xb ee ff OfIPrPw For More Information On This Product Go to www freescale com 12CPU15UG V1 2 MAXM Core User Guide si2cpu A A8gscale Semiconductor Inc M E M Determine Grade of Membership M E M Fuzzy Logic Operation CCR Effects Code and CPU Cycles Grade of membership gt My Y 0001 gt Y X 0004 gt X Before executing MEM initialize A X and Y Load A with the current crisp value of a system input variable Load Y with the fuzzy input RAM location where the grade of membership is to be stored Load X with the first address of a 4 byte data structure that describes a trapezoidal membership function The data structure consists of e Point_1 The x axis starting point for the leading side at Mx e Slope_1 The slope of the leading side at My 1 e Point_2 The x axis position of the rightmost point at Mx y 9 e Slope_2 The slope of the trailing side at Mx 3 A slope_1 or slope_2 value of 00 is a
504. re User Guide si2cpu Rf Scale Semiconductor Inc 5 5 2 No Moyement 0 0 eta cto aa a e a a OM a E aa 128 5 5 3 ALD Advance and Load from Data Bus 1 0 2020 0055 128 5 5 4 INT Start Interrupt 0 1 nanaonan A a oa a E 128 5 5 5 SEV Start Even Instruction 1 0 anaana aaae 128 5 5 6 SOD Start Odd Instruction 1 1 a aana anaa 129 Section 6 Exception Processing 6 1 Exception Processing Overview 000 aeaea 131 6 1 1 Reset PIOCESSING cs ee eS ee te A RE R 133 6 1 2 idos panies 6 autos spare 8 mutt arate NS BO RAS Bee as Cyeri oaice wae aOR Ee 133 6 2 Exception VECIOIS cos ue tects a bp tare tines ols od a a ec tie ees a 135 6 3 Exception TIPS A ene cage Saree ee es bm die ae DS 136 6 3 1 RESES ci itt staba A Et eens ents 136 6 3 2 VEST NOUS a A ESA A RR 137 Section 7 Core Interface fle Gore Interiace OvVeEWwiew inatit sip At ee 141 7 1 1 SIGNS UNI AY a A ATA AAA RL ene re 142 ia A O 145 7 2 1 Internal Bus Interface Signals 1 0000 ls bev lali a 145 7 2 2 External Bus Interface ION Sa ia AOS Weds wee x 148 7 2 3 Clock and Reset Signals Lawes al o Caged A A eae 150 7 2 4 Vector Request Acknowledge Signals 000 eee eee eee eee 151 7 2 5 Stop and Wait Mode Control Status Signals 000 0c eee eee 151 7 2 6 Background Debug Mode BDM Interface SignalS ooooo 151 7 2 1 Memory Configuration Signals naes E ie Mon a lee SRE
505. read If the DDR bit is one output the associated port data register bit state is read This register is not in the on chip map in expanded and peripheral modes It is reset to 00 so the DDR does not override the three state control signals DDRB7 0 Data Direction Port B 1 Configure the corresponding I O pin as an output 0 Configure the corresponding I O pin as an input 12 3 5 Port E Data Register PORTE Address Base 8 BIT 7 6 5 4 3 2 1 BIT O Read Bit 1 Bit O Bit 7 6 5 4 3 2 Write Reset MODBor ttt IPIPE1 MODAor LSTRB Alt Pin Function NOACC a IPIPEO ECLK or TAG R W IRQ XIRQ CLKTO Ee SS Unimplemented Figure 12 7 Port E Data Register PORTE Read anytime when register is in the map Write anytime when register is in the map Port E is associated with external bus control signals and interrupt inputs These include mode select MODB IPIPE1 MODA IPIPEO E clock size LSTRB TAGLO read write R W IRQ and XIRQ When not used for one of these specific functions Port E pins 7 2 can be used as general purpose I O and pins 1 0 can be used as general purpose input The Port E Assignment Register PEAR selects the function of each pin and DDRE determines whether each pin is an input or output when it is configured to be general purpose I O DDRE also determines the source of data for a read of PORTE Some of these pins have software selectable pullups PE7 ECL
506. reakpoint The functionality is as given in Table 13 2 below Table 13 2 Breakpoint Mask Bits for Second Address Dual Mode BK1MBH BK1MBL Address Compare BKP1X BKP1H BKP1L x 0 Full Address Compare Yes Yes Yes 256 byte Address Range 16K byte Address Range NOTES 1 If page is selected The x 0 case is for a Full Address Compare When a program page is selected the full address compare will be based on bits for a 20 bit compare The registers used for the compare are BKP1X 5 0 BKP1H 5 0 BKP1L 7 0 When a program page is not selected the full address compare will be based on bits for a 16 bit compare The registers used for the compare are BKP1H 7 0 BKP1L 7 0 The 1 0 case is not sensible because it would ignore the high order address and compare the low order and expansion addresses Logic forces this case to compare all address lines effectively ignoring the BK1MBH control bit The 1 1 case is useful for triggering a breakpoint on any access to a particular expansion page This only makes sense if a program page is being accessed so that the breakpoint trigger will occur only if BKP1X compares In Full Mode these bits may be used to mask disable the comparison of the high and or low bytes of the data breakpoint The functionality is as given in Table 13 3 below Table 13 3 Breakpoint Mask Bits for Data Breakpoints Full Mode BK1MBH BK1MBL Data Compare BKP1X BKP1H BKP1L i High an
507. red otherwise C Set if result can be rounded up cleared otherwise Code and CPU Source Form ES Code Hex CPU Cycles Cycles ETBL oprx0_xysppc IDX 18 3F xb ORRffffffP For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc E XG Exchange Register Contents E XG Operation CCR Effects Code and CPU Cycles rl S 12 when rl and r2 are the same size 00 r1 12 when r1 is 8 bits and r2 is 16 bits r1 S 12 when rl is 16 bits and r2 is 8 bits See the table on the next page Exchanges the values between a source register A B CCR D X Y or SP and a destination register A B CCR D X Y or SP Exchanges involving TMP2 and TMP3 are reserved for Motorola use S X H l N Z V C or S X H l N Z V C A U A TATATA TATA CCR bits affected only when the CCR is the destination register The X bit cannot change from 0 to 1 Software can leave the X bit set leave it cleared or change it from 1 to 0 but X can only be set by a reset or by recognition of an XIRQ interrupt Address Machine Source Form Mode Code Hex CPU Cycles EXG abcdxysp abcdxysp INH B7 eb P For More Information On This Product Go to www freescale com EXG EXGA A EXG A B EXG A CCR EXG A TMP2 EXG A D EXG A X EXG A Y EXG A SP 1000 X000 1000 X001 1000 X010 1000 X011 1000 X100 1000 X101 1000 X110 1000 X111 EXG B A EXG B B EXG B CCR
508. red otherwise Z Set if result is 00 cleared otherwise V NO C set if N is set and C is cleared after the shift or N is cleared and C is set after the shift cleared otherwise C MO set if the LSB of M was set before the shift cleared otherwise Code and CPU Source Form code Hew CPU Cycles Cycles ASR opr16a rPwO ASR oprx0_xysppc rPw ASR oprx9 xysppc rPwO ASR oprx16 xysppc frPwP ASR D xysppc fIfrPw ASR oprx16 xysppc fIPrPw For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc AS RA Arithmetic Shift Right A AS RA Operation E 7 es oee e e2 Tor oo 6 A Shifts all bits of A one place to the right Bit 7 is held constant Bit 0 is loaded into the C bit This operation effectively divides a two s complement value by two without changing its sign The carry bit can be used to round the result CCR Effects S X H I A A A N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V NO C set if N is set and C is cleared after the shift or N is cleared and C is set after the shift cleared otherwise C AO set if the LSB of A was set before the shift cleared otherwise Code and CPU Source Form acy code Hew CPU Cycles Cycles For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 AS R B Arithmetic Shift Right B AS R B O
509. reescale com Core User Guide ff44 Mh Fh Ph Fh Fh Fh Mh Mh h Fh H ol D w o Fh Fh h Fh a a wo N 5d 60 63 66 68 f 6b f6d fof 71 Fh FH FH Ph eh h Ph Fh Fh b6 2f 85 27 81 27 2b 86 20 86 20 86 79 f6 Ta b7 Te b7 b7 b7 18 EL fb 18 2e 10 06 08 a0 06 88 02 80 EL ff EE d3 BE d3 12 b4 Oc 00 00 06 06 02 ff 06 ff ff 77 05 fb ff 87 si2cpui HABg SCale Semiconductor Inc CAUTION 10 Top of main loop to wait for a software instruction 7 CAUTION 1 ALIGN 1 Make sure the following loop starting with ldaa is ALWAYS on an even boundary See AR 156 for more details INST_LOOP TRACI GO ldaaINSTR Wait for non zero non hdw command bleINST_LOOP 00 is null command MSB of A set neg is hdw command bita 18 TAGGO TRACE or GO commands beqNOT_EXE Branch if not execution command cmpa 10 TRACE 1 0 tp 4 7 95 beqTRACE bmiGO If not GO it s TAG GO Fall through from TAG_GO is 4th of 4 ways to exit to user code ldaa A0 enBDM TAG bits in STATUS braEXI EQ Controlled exit 3 of 4 uN E ldaa 88 enBDM TRACE bits in STATUS braEXI Q Controlled exit 2 of 4 uN ldaa 80 enBDM bit only in STATUS Upon entry to EXIT_SEQ A contains a value to be written to the STATUS register Seq r
510. related to the internal and I P bus interfacing appear on the right side of the Core block in the diagram In addition to bus interfacing the Core receives reset and clock inputs from the system and provides signals for interacting with the CPU for vector request and acknowledge and for functional operation of the stop and wait modes The Core interacts with the external blocks of the overall system through the port pad logic for Ports A B E which include the physical IRQ and XIRQ pins and K and the BDM BKGD pin interfaces The memory configuration switches shown in the diagram are inputs to the Core block that are tied to a constant logic state at the time of integration into the SoC design to correctly define the on chip memory configuration for proper Core operation within the system For More Information On This Product Go to www freescale com Core User Guide siocpuimtaRscale Semiconductor Inc Memory Configuration Switches 2 E 5 ol el 2 al lt el Shel cle 3 AE 3 El Bl 3 4 3 3 3 peri_reset ta4 gt Resets reset pin indy core ramregsel ta On Chip core ramarraysel RAM peri_clk2 core ramhal t2 gt Interface Clocks peri_clk4 vam _rdb_L12 15 0 periclked iy core eeregsel 2 On Chip peri_clk34 gt CPU MMC core eearraysel t2 EEPROM Ls Central Module qee r b L12115 01 Interface eri phase _oscd Processing Mapping ee hold t1 ECLK g e load Unit Control core feeregsel t2
511. ress and CPU registers Y X B A and CCR decrementing SP before each item is stacked Sets the I bit and loads PC with the SWI vector Instruction execution resumes at the address to which the vector points SWI is not affected by the I bit CCR Effects S XH I N ZV C Ae l Set Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex NOTES 1 The CPU also uses the SWI processing sequence for hardware interrupts and unimplemented opcode traps A variation of the sequence VfPPP is used for resets For More Information On This Product Go to www freescale com Core User Guide TAB Operation CCR Effects Code and CPU Cycles si2cpu A A8gscale Semiconductor Inc Transfer A to B TA B A gt B Loads the value in A into B The former value in B is lost the value in A does not change Unlike the general transfer instruction TFR A B which does not affect condition code bits the TAB instruction affects the N Z and V bits N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Address Machine TAB INH 18 OF For More Information On This Product Go to www freescale com TAP Operation CCR Effects Code and CPU Cycles Freescale Semiconductor ING cuide s12cPuU15UG V1 2 Transfer A to CCR TA p same as TFR A CCR A CCR Loads the value in A into the CCR The value in A does
512. ress following the last byte of object code in the instruction S X H I N Z V C Address Machine Source Form Mode Code Hex CPU Cycles LBHS rel16 REL 18 24 qq rr OPPP branch OPO no branch Branch Complementary Branch F s Comment Mnemonic Opcode Mnemonic Opcode Test R lt M or LBHS LBCC LBLO LBCS 18 25 B lt A Unsigned For More Information On This Product Go to www freescale com 12CPU15UG V1 2 LBHS Core User Guide LBLE Operation CCR Effects Code and CPU Cycles si2cpu A A8gscale Semiconductor Inc LBLE Long Branch if Less Than or Equal to Zero If Z N V 1 then PC 0004 rel PC LBLE can be used to branch after subtracting or comparing signed two s complement values After CMPA CMPB CPD CPS CPX CPY SBCA SBCB SUBA SUBB or SUBD the branch occurs if the CPU register value is less than or equal to the value in M After CBA or SBA the branch occurs if the value in B is less than or equal to the value in A Rel is a 16 bit two s complement offset for branching forward or backward in memory Branching range is 8000 to 7FFF 32768 to 32767 from the address following the last byte of object code in the instruction S X H I N Z V C Address Machine Source Form Mode Code Hex CPU Cycles LBLE rel16 peL 18 2F qarr OPPP branch OPO no branch
513. ress lines A7 through AO respectively and data lines D7 through DO respectively When this port is not used for external addresses such as in single chip mode these pins can be used as general purpose I O Data Direction Register B DDRB determines the primary direction of each pin DDRB also determines the source of data for a read of PORTB This register 1s not in the on chip map in expanded and peripheral modes CAUTION To ensure that you read the value present on the PORTB pins always wait at least one cycle after writing to the DDRB register before reading from the PORTB register 12 3 4 Data Direction Register B DDRB Address Base 3 BIT 7 6 5 4 3 2 1 BIT O Read Bit 7 6 5 4 3 2 1 Bit O Write Reset 0 0 0 0 0 0 0 0 Figure 12 6 Data Direction Register B DDRB Read anytime when register is in the map Write anytime when register is in the map For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 This register controls the data direction for Port B When Port B is operating as a general purpose I O port DDRB determines the primary direction for each Port B pin A 1 causes the associated port pin to be an output and a 0 causes the associated pin to be a high impedance input The value in a DDR bit also affects the source of data for reads of the corresponding PORTB register If the DDR bit is zero input the buffered pin input state is
514. ro or minus A 00 TSTB Test B for zero or minus B 00 For More Information On This Product Go to www freescale com Core User Guide 4 3 8 siocpuimtaRscale Semiconductor Inc Boolean Logic Instructions These instructions perform a logic operation on the A or B accumulator and a memory value or immediate value or on the CCR and an immediate value A summary of the boolean logic instructions is given in Table 4 10 Table 4 10 Boolean Logic Instructions Mnemonic Function Operation RIGA AND A with memory A M A AND A with immediate value A e imm gt A A OS AND B with memory B e M B AND B with immediate value B e imm gt B ANDCC AND CCR with immediate value to clear CCR bits CCR imm gt CCR EORA Exclusive OR A with memory A 9 M gt A Exclusive OR A with immediate value A imm gt A EORB Exclusive OR B with memory B M gt B Exclusive OR B with immediate value B imm gt B ORAA OR A with memory A M gt A OR A with immediate value A imm gt A ORAB OR B with memory B M B OR B with immediate value B imm B ORCC OR CCR with immediate value to set CCR bits CCR imm CCR 4 3 9 Clear Complement and Negate Instructions These instructions perform binary operations on values in an accumulator or in memory Clear operations clear the value complement operations replace the value with its one s co
515. roduct Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc SEX Sign Extend SEX Operation CCR Effects Code and CPU Cycles If rl bit 7 0 then 00 r1 gt 12 If rl bit 7 1 then FF r1 r2 Transfers the two s complement value in A B or CCR to the low byte of D X Y or SP Loads the high byte with 00 if bit 7 is O or FF if bit 7 is 1 The result is the 16 bit sign extended version of the original 8 bit value SEX is an alternate mnemonic for the TFR r1 r2 instruction The value in the original register does not change except in the case of SEX A D D is A B Address Machine Source Form Mode Code Hex CPU Cycles SEX abc dxysp INH B7 eb P Sign Extend Postbyte eb Coding Source Sign Form Postbyte Extension SEX A TMP2 0000 X011 00 or FF A TMP2 SEX A D 0000 X100 00 or FF A D SEX A X 0000 X101 00 or FF A X SEX A Y 0000 X110 00 or FF A Y SEX A SP 0000 X111 00 or FF A SP SEX B TMP2 0001 X011 B7 13 00 or FF B TMP2 SEX B D 0001 X100 B7 14 00 or FF B D SEX B X 0001 X101 B7 15 00 or FF B X SEX B Y 0001 X110 B7 16 00 or FF B Y SEX B SP 0001 X111 B7 17 00 or FF B SP SEX CCR TMP2 0010 X011 B7 23 00 or FF CCR TMP2 SEX CCR D 0010 X100 B7 24 00 or FF CCR D SEX CCR X 0010 X101 B7 25 00 or FF CCR X SEX CCR Y 0010 X110 B7 26 00 or FF CCR Y SEX CCR SP 0010
516. roduct Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc INCA Increment A INCA Operation A 01 gt A Adds one to the value in A The N Z and V bits reflect the result of the operation The bit is not affected by the operation thus allowing the INC instruction to be used as a loop counter in multiple precision computations When operating on unsigned values only BEQ BNE LBEQ and LBNE branches can be expected to perform consistently When operating on two s complement values all signed branches are available CCR Effects S XH I N ZV C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Set if the operation produces a two s complement overflow if and only if A was 7F before the operation cleared otherwise Code and CPU Source Form aa Code Hex CPU Cycles Cycles For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 INCB Increment B INCB Operation B 01 gt B Adds one to the value in B The N Z and V bits reflect the result of the operation The C bit is not affected by the operation thus allowing the INC instruction to be used as a loop counter in multiple precision computations When operating on unsigned values only BEQ BNE LBEQ and LBNE branches can be expected to perform consistently When operating on two s complement values all signed branches
517. roduct Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 EORA Exclusive OR A EORA Operation CCR Effects Code and CPU Cycles A M gt A or A imm gt A Performs a logical exclusive OR of the value in A and either the value in M or an immediate value Puts the result in A S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Machine Source Form Code Hex CPU Cycles EORA opr8i 88 ii EORA opr8a 98 dd EORA opr16a B8 hh 11 EORA oprx0_xysppc A8 xb EORA oprx9 xysppc A8 xb ff EORA oprx16 xysppc A8 xb ee ff EORA D xysppc A8 xb EORA oprx16 xysppc AS xb ee ff For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc EORB Exclusive OR B with M EORB Operation CCR Effects Code and CPU Cycles B M gt B or B imm gt B Performs a logical exclusive OR of the value in B and either the value in M or an immediate value Puts the result in B S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared Machine Source Form Code Hex CPU Cycles EORB opr8i c8 ii EORB opr8a D8 dd EORB opr16a F8 hh 11 EORB oprx0_xysppc E8 xb EORB oprx9 xysppc E8 xb ff EORB oprx16 xysppc E8 xb ee ff EORB D xysppc E8 xb EORB oprx16 xysppc E8 xb ee ff
518. rt branch to subroutine BSR a jump to subroutine JSR or an expanded memory call CALL can be used to initiate subroutines There is no long branch to subroutine instruction LBSR but a PC relative JSR performs the same function A return address is stacked then execution begins at the subroutine address Subroutines in the normal 64K byte address space are terminated with an RTS instruction RTS unstacks the return address so that execution resumes with the instruction after BSR or JSR The CALL instruction is intended for use with expanded memory CALL stacks the value in the PPAGE register and the return address then writes a new value to PPAGE to select the memory page where the subroutine resides The page value is an immediate operand in all addressing modes except indexed indirect modes in these modes an operand points to locations in memory where the new page value and subroutine address are stored The RTC instruction ends subroutines in expanded memory RTC unstacks the PPAGE value and the return address so that execution resumes with the next instruction after CALL For software compatibility CALL and RTC operate correctly on devices that do not have expanded addressing capability For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 A summary of the jump and subroutine instructions is given in Table 4 23 Table 4 23 Jump and Subroutine Instructions Mnemo
519. rwise Z Set if result is 00 cleared otherwise V N C NeC Ne C for N and C after the shift cleared otherwise C BO set if the LSB of B was set before the shift cleared otherwise Code and CPU Cycles Cycles Mode Code Hex pom For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPuU15UG V1 2 RTC Return from Call RTC Operation Msp gt PPAGE SP 0001 SP Mgp Mogp 1 gt PCy PC SP 0002 gt SP Terminates subroutines in expanded memory invoked by the CALL instruction Returns execution flow from the subroutine to the calling program The program overlay page PPAGE register and the return address are restored from the stack program execution continues at the restored address For code compatibility purposes CALL and RTC also execute correctly in MCUs that do not have expanded memory capability CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex RTC INH OA uUnfPPP For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc RTI Return from Interrupt RTI Operation CCR Effects Code and CPU Cycles Msp CCR SP 0001 SP Msp Msp 1 gt B A SP 0002 SP Msp Msp D gt Xp Xz SP 0004 SP Msp Msp D gt PCy PC SP 0002 SP Mgp
520. s Since no unsigned value is less than 0 BLO and BLS have no utility following TST While BHI can be used after TST it performs the same function as BNE which is preferred After testing signed values all signed branches are available CCR Effects S XH I N ZV C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared C Cleared Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex TST opr16a EXT F7 hh 11 rPO TST oprx0_xysppc IDX E7 xb PPE TST oprx9 xysppc IDX1 E7 xb ff rPO TST oprx16 xysppc IDX2 E7 xb ee ff frPP TST D xysppc D IDX E7 xb fIfrPf TST oprx16 xysppc IDX2 E7 xbee ff fIPrPf For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 TSTA Test A TSTA Operation A 00 Subtracts 00 from the value in A The condition code bits reflect the result The value in A does not change The TSTA instruction provides limited information when testing unsigned values Since no unsigned value is less than 0 BLO and BLS have no utility following TSTA While BHI can be used after TST 1t performs the same function as BNE which is preferred After testing signed values all signed branches are available CCR Effects S XH I N ZV C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared C Cleared Code and CPU Address Mach
521. s of object code the opcode and a one byte offset Using Y as the reference the same instruction assembles into three bytes a page prebyte the opcode and a one byte offset Analysis of M68HC11 source code indicates that the offset is most frequently zero and very seldom greater than four The HCS12 indexed addressing scheme uses a postbyte plus 0 1 or 2 extension bytes after the instruction opcode These bytes specify which index register is used determine whether an accumulator is used as the offset implement automatic pre post increment decrement of indices and allow a choice of 5 9 or 16 bit signed offsets This approach eliminates the differences between X and Y register use and dramatically enhances indexed addressing capabilities Major improvements that result from this new approach are e Stack pointer can be used as an index register in all indexed operations e Program counter can be used as index register in all but autoinc dec modes e Accumulator offsets allowed using A B or D accumulators e Automatic pre or post increment or decrement by 8 to 8 e 5 bit 9 bit or 16 bit signed constant offsets e 16 bit offset indexed indirect and accumulator D offset indexed indirect The change completely eliminates pages three and four of the M68HC11 opcode map and eliminates almost all instructions from page two of the opcode map For offsets of 0 to 15 from the X index register the object code is the same size as it was fo
522. s Machine Source Form CPU Cycles Cycles Mode Code Hex BCS rel8 REL 25 rr PPP branch P no branch Branch Complementary Branch Comment Mnemonic Opcode Mnemonic Opcode Test BCS BLO BCC BHS For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 B E Q Branch if Equal B E Q Operation CCR Effects Code and CPU Cycles If Z 1 then PC 0002 rel PC Tests the Z bit and branches if Z 1 Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction S X H I N Z V C Address Machine Source Form Mode Code Hex CPU Cycles BEQ rel8 REL Nal PPP branch P no branch Branch Complementary Branch Comment Mnemonic Opcode Test Mnemonic Opcode Test R M R M or or Signed BEQ 27 R zero BNE 26 R zero Unsigned or For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc B G E Branch if Greater Than or Equal to Zero E G E Operation CCR Effects Code and CPU Cycles If N O V 0 then PC 0002 rel gt PC BGE can be used to branch after comparing or subtracting signed two s complement va
523. s and stacks a return address stacks the current PPAGE value and writes a new instruction supplied value to PPAGE The PPAGE value controls which of the 64 possible pages is visible through the 16K byte expansion window in the 64K byte memory map Execution then begins at the address of the called subroutine During the execution of a CALL instruction the CPU e Writes the old PPAGE value into an internal temporary register and writes the new instruction supplied PPAGE value into the PPAGE register e Calculates the address of the next instruction after the CALL instruction the return address and pushes this 16 bit value onto the stack e Pushes the old PPAGE value onto the stack e Calculates the effective address of the subroutine refills the queue and begins execution at the new address on the selected page of the expansion window This sequence is uninterruptable there is no need to inhibit interrupts during CALL execution A CALL can be performed from any address in memory to any other address The PPAGE value supplied by the instruction is part of the effective address For all addressing mode variations except indexed indirect modes the new page value is provided by an immediate operand in the instruction In indexed indirect variations of CALL a pointer specifies memory locations where the new page value and the address of the called subroutine are stored Using indirect addressing for both the new page value and the address w
524. s following the last byte of object code in the instruction S X H I N Z V C Address Machine Source Form Mode Code Hex CPU Cycles LBPL rel16 REL 18 2A qq rr OPPP branch OPO no branch Branch Complementary Branch z Comment Mnemonic Opcode Test Mnemonic Opcode Test Positive Negative LBPL 18 2A LBMI 18 2B Simple For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPuU15UG V1 2 LBRA Long Branch Always LBRA Operation PC 0004 rel PC Branches unconditionally Rel is a 16 bit two s complement offset for branching forward or backward in memory Branching range is 8000 to 7FFF 32768 to 32767 from the address following the last byte of object code in the instruction Execution time is longer when a conditional branch is taken than when it is not because the instruction queue must be refilled before execution resumes at the new address Since the LBRA branch condition is always satisfied the branch is always taken and the instruction queue must always be refilled CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex Complementary Branch Opcode Test Mnemonic Opcode Test Comment Mnemonic For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor In
525. s for efficient arithmetic operation and high speed mathematical execution e Allows instructions with odd byte counts including many single byte instructions for more efficient use of program memory space e Three stage instruction queue to buffer program information for more efficient CPU execution e Extensive set of indexed addressing capabilities including Using the stack pointer as an indexing register in all indexed operations Using the program counter as an indexing register in all but auto increment decrement mode Accumulator offsets using A B or D accumulators Automatic index pre decrement pre increment post decrement and post increment by 8 to 8 5 bit 9 bit or 16 bit signed constant offsets 16 bit offset indexed indirect and accumulator D offset indexed indirect addressing e Provides 2 to 122 I bit maskable interrupt vectors 1 X bit maskable interrupt vector 2 nonmaskable CPU interrupt vectors and 3 reset vectors e Optional register configurable highest priority I bit maskable interrupt e On chip memory and peripheral block interfacing with internal memory expansion capability and external data chip select e Configurable system memory and mapping options For More Information On This Product Go to www freescale com Core User Guide siocpuimtaRscale Semiconductor Inc External Bus Interface 8 bit or 16 bit multiplexed or non multiplexed Multiple modes of operation Hardware br
526. s of program information starting with the instruction opcode directly available to the CPU at the beginning of every instruction As each instruction executes it performs enough additional program fetches to refill the space it took up in the queue Alignment information is maintained by logic in the instruction queue The CPU provides signals that tell the queue logic when to advance a word of program information and when to toggle the alignment status The CPU is not aware of instruction alignment The queue logic sorts out the information in the queue to present the opcode and additional bytes of information as CPU inputs A control algorithm determines whether the opcode is in the even or odd half of the word at the head of the queue The execution sequence for all instructions is independent of the alignment of the instruction The only situation in which alignment can affect the number of cycles an instruction takes occurs in devices that have a narrow 8 bit external data bus and is related to optional program fetch cycles Optional cycles are always performed but serve different purposes determined by instruction size and alignment Each instruction includes one program fetch cycle for every two bytes of object code Instructions with an odd number of bytes can use an optional cycle to fetch an extra word of object code If the queue is aligned at the start of an instruction with an odd byte count the last byte of object code shares a que
527. s pointed to by the vector The vector mapping for all interrupt sources is shown in Table 6 3 below with detailed descriptions given in the sub sections that follow Table 6 3 Interrupt Sources Interrupt Exception Mask Vector Source Priority Address Unimplemented opcode trap TRAP Software interrupt instruction SWI Nonmaskable external interrupt pin XIRQ pin it FFF4 FFF5 Highest priority l Maskable interrupt defaults to IRQ pin i FFxx FFxx 1 Maskable external interrupt pin IRQ pin i FFF2 FFF3 System peripheral block interrupt requests gt i FFFO FFOO Interrupts can be classified according to their maskability TRAP and SWI are nonmaskable The XIRQ pin is masked at reset by the X bit but once software clears the X bit the XIRQ pin is nonmaskable until another reset occurs The remaining interrupt sources can be masked by the I bit I bit maskable interrupt For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc requests come from the IRQ pin and peripheral blocks within the system such as timers and serial ports These I bit maskable sources have default priorities that follow the address order of the interrupt vectors the higher the address the higher the priority of the interrupt request The IRQ pin is initially assigned the highest I bit maskable interrupt priority The system can give one I bit maskable source priority over oth
528. s register controls the data direction for Port A When Port A is operating as a general purpose I O port DDRA determines the primary direction for each Port A pin A 1 causes the associated port pin to be an output and a 0 causes the associated pin to be a high impedance input The value in a DDR bit also affects the source of data for reads of the corresponding PORTA register If the DDR bit is zero input the buffered pin input state is read If the DDR bit is one output the associated port data register bit state is read This register is not in the on chip map in expanded and peripheral modes It is reset to 00 so the DDR does not override the three state control signals DDRA7 0 Data Direction Port A 1 Configure the corresponding I O pin as an output 0 Configure the corresponding I O pin as an input For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc 12 3 3 Port B Data Register PORTB Address Base 1 BIT 7 6 5 4 3 2 1 BITO Read Bit 7 6 5 4 3 2 1 Bit O Write Reset Single Chip PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO Exp Wide Emul Nar 21087 AB DB6 AB DB5 AB DB4 AB DB3 AB DB2 AB DB1 AB DBO with IVIS 8 Periph Expanded Narrow AB7 AB6 AB5 AB4 AB3 AB2 AB ABO Figure 12 5 Port B Data Register PORTB Read anytime when register is in the map Write anytime when register is in the map Port B bits 7 through O are associated with add
529. s that a discrete signal is in active logic state e Active low signals change from logic level one to logic level zero e Active high signals change from logic level zero to logic level one Negated means that an asserted discrete signal changes logic state e Active low signals change from logic level zero to logic level one e Active high signals change from logic level one to logic level zero LSB means least significant bit or bits MSB means most significant bit or bits References to low and high bytes or words are spelled out Memory and registers use big endian ordering The most significant byte byte 0 of word 0 is located at address 0 Bits within a word are numbered downward from the MSB bit 15 Signal bit field and control bit mnemonics follow a general numbering scheme e A range of mnemonics is referred to by mnemonic and numbers that define the range from highest to lowest For example p_addr 4 0 are lines four to zero of an address bus A single mnemonic stands alone or includes a single numeric designator when appropriate For example m_rst is a unique mnemonic while p_addr 5 represents line 15 of an address bus For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Section 3 Core Registers This section provides detailed descriptions of the Core programming model registers and accumulators In addition a general description of the complete Core
530. s the disable signal for the system external clock ECLK 8 3 2 Stop and Wait Mode Control Status Signals These descriptions apply to signals that provide for controlling some of the functionality and status indication of CPU stop and wait modes 8 3 2 1 CPU stop mode indicator core_stop_t24 This Core output signal indicates whether the CPU is in stop mode 8 3 2 2 CPU wait mode indicator core_wait_t24 This Core output signal indicates whether the CPU is in wait mode 8 3 2 3 Core wakeup indicator for wait and stop mode core_wakeup_ta This asynchronous Core output signal indicates that the CPU has received an interrupt request and is ready to resume normal operation 8 3 2 4 Core wait signal from system clock generation block peri_cwai_t3 This Core input signal indicates to the CPU whether the main Core clock peri_clk24 will run during CPU wait mode 8 3 2 5 System level wait signal peri_syswai_t3 This Core input signal indicates to the Core whether all system clocks will run during CPU wait mode For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG v1 2 Section 9 Core Power Connections This section details the HCS12 V1 5 Core power connections 9 1 Power Overview The HCS12 V1 5 Core operates from a single power and a single ground connection 9 1 1 Power and Ground Summary The Core requires a single power typically termed VDD and a single ground t
531. s the external addresses 12 4 2 External Data Bus Interface The external data bus interface block manages data transfers from to the external pins to from the internal read and write data buses This block selectively couples 8 bit or 16 bit data to the internal data bus to implement a variety of data transfers including 8 bit 16 bit 16 bit swapped and 8 bit external to 16 bit internal accesses Modes addresses chip selects etc affect the type of accesses performed during each bus cycle 12 4 3 Control The control block generates the register read write control signals and miscellaneous port control signals 12 4 4 Registers The register block includes the fourteen 8 bit registers and five reserved register locations associated with the MEBI sub block For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 12 4 5 External System Pin Functional Descriptions In typical SoC implementations the MEBI sub block of the Core interfaces directly with external system pins Table 12 4 below outlines the pin names and functions and gives a brief description of their operation Table 12 4 External System Pins Associated With MEBI Pin Name Pin Functions Description PA7 PAO General purpose I O pins see PORTA and DDRA registers High order address lines multiplexed during ECLK low Outputs except in special A15 A8 f peripheral mode where they are inputs from
532. scale Semiconductor WOE Guide 12CPU15UG V1 2 Table 11 3 Allocated RAM Memory Space ram_sw2 ram_sw0 Allocated RAM Space RAM mappable region INITRM bits used 12k Byte 16k Byte RAM15 RAM14 14k Byte 16k Byte RAM15 RAM14 16k Byte 16k Byte RAM15 RAM14 NOTES 1 Ae of the Allocated RAM space within the RAM mappable region is dependent on the value of NOTE As stated the bits in this register provide read visibility to the system physical memory space allocations defined at system integration The actual array size for any given type of memory block may differ from the allocated size Please refer to the chip level documentation for actual sizes 11 3 8 Memory Size Register One MEMSIZ1 Address Base 1D Read rom_swt1 rom sw0 0 0 0 0 pag_sw1 pag_sw0 Write Reset Unimplemented Figure 11 10 Memory Size Register One Read Anytime Write Writes have no effect The MEMSIZ1 register reflects the state of the Flash EEPROM or ROM physical memory space and paging switches at the Core boundary which are configured at system integration This register allows read visibility to the state of these switches rom_swl rom_sw0 Allocated System Flash EEPROM or ROM Physical Memory Space The allocated system Flash EEPROM or ROM physical memory space is as given in Table 11 4 below Table 11 4 Allocated Flash EEPROM ROM Physical Memory Space rom_sw1 rom_sw0 OL ROM Spac
533. se for values of N and C after the shift C A7 set if the MSB of A was set before the shift cleared otherwise Code and CPU Source Form sag code Hew CPU Cycles Cycles ROLA INH 45 O For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 RO L B Rotate Left B R O L B Operation pay Co 7 99 es ess ez Jos Joo B Shifts all bits of B one place to the left Bit O is loaded from the C bit The C bit is loaded from the most significant bit of B Rotate operations include the carry bit to allow extension of shift and rotate operations to multiple bytes For example to shift a 24 bit value one bit to the left the sequence ASL LOW ROL MID ROL HIGH could be used where LOW MID and HIGH refer to the low middle and high bytes of the 24 bit value respectively CCR Effects S XH I N ZV C A A A A N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C NeC NC for N and C after the shift set if N is set and C is cleared or N is cleared and C is set cleared otherwise for values of N and C after the shift C B7 set if the MSB of B was set before the shift cleared otherwise Code and CPU Source Form deba code Hew CPU Cycles Cycles ROLB INH 55 O For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semicon
534. se instructions were one byte on M68HC11 and two bytes on HCS12 TFR A CCR TFR CCR A TFR S X TFR S Y TFR X S TFR Y S EXG D X EXG D Y The M68HC11 had a small collection of specific transfer and exchange instructions HCS12 expanded this to allow transfer or exchange between any two CPU registers For all but TSY and TYS which take two bytes on either CPU the HCS12 transfer exchange costs one extra byte compared to the M68HC11 The substitute instructions execute in one cycle rather than two All of the translations produce the same amount of or slightly more object code than the original M68HC11 instructions However there are offsetting savings in other instructions Y indexed instructions in particular assemble into one byte less object code than the same M68HC11 instruction The HCS12 has a two page opcode map rather than the four page M68HC11 map This is largely due to redesign of the indexed addressing modes Most of pages 2 3 and 4 of the M68HC11 opcode map are required because Y indexed instructions use different opcodes than X indexed instructions Approximately two thirds of the M68HC11 page 1 opcodes are unchanged in HCS12 and some M68HC11 opcodes have been moved to page 1 of the HCS12 opcode map Object code for each of the moved instructions is one byte smaller than object code for the equivalent M68HC11 instruction Table C 2 shows instructions that assemble to one byte less object code on the HCS12 Instruction
535. sed T word doesn t need to use X rmb1 Save user CCR value while in BDM briefly to hold exit value for status during exit sequen AFTER_RST START ROM_INC RES_X_T2 Above is 1 of 4 wa INST_DONE ce to return to user code orgff20 BDM ROM start X CAUTION 7 X X XCAUTION 8 bset STATUS 80 Set the ENBDM bit to pass the brset test below CCR immediately after rst is SXHINZVC 11x1xxxx CCR after this bset is SXHINZVC 11x1100x This is o k because the SXI bits are not j affected CAUTION 2 X X XCAUTION 9 exgt3 d Save D without affecting CCR This exg t3 d instruction MUST occur before the following 7 EEE GOE a instruction CAUTION 3 tfrccr a staaCCRSAVE Save user CCR value exgx t2 pe into x CAUTION 4 cpx FF00 Check to see if user PC overlaps BDM 7 ROM bhsROM_INC If so increment regardless tst0 x Test next opcode This instruction affects CCR so it MUST occur AFTER saving the user s CCR bneRES_X_T2 if not 00 restore inx else inc then restore This instruction affects CCR so it MUST occur AFTER saving the user s CCR exgx t2 restore pc to temp 2 brsetSTATUS 80 INST_LOOP Check if BDM allowed clra Exit if BDM not allowed braEXIT_SEO ys to exit BDM to user code clrINSTR clear INSTR then wait for new inst For More Information On This Product Go to www f
536. sed indexing should be allowed and that direct arithmetic manipulation of the stack pointer value should be allowed The HCS12 instruction set provides for all of these needs with improved indexed addressing the addition of an LEAS instruction and the addition of push and pull instructions for the D accumulator and the CCR 4 4 2 1 Register Pushes and Pulls The M68HC11 has push and pull instructions for A B X and Y but requires separate 8 bit pushes and pulls of accumulators A and B to stack or unstack the 16 bit D accumulator the concatenated combination A B The PSHD and PULD instructions allow directly stacking the D accumulator in the expected 16 bit order For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Adding PSHC and PULC improved orthogonality by completing the set of stacking instructions so that any of the CPU registers can be pushed or pulled These instructions are also useful for preserving the CCR value during a function call subroutine 4 4 2 2 Allocating and Deallocating Stack Space The LEAS instruction can be used to allocate or deallocate space on the stack for temporary variables EAS 10 S Allocate space for 5 16 bit integers EAS 10 S Deallocate space for 5 16 bit ints The de allocation can even be combined with a register push or pull as in the following example LDX 8 S Load return value and deallocate X is loaded
537. ser code and remove the BDM memory from the map 1 BDM active 0 BDM not active ENTAG Tagging enable This bit indicates whether instruction tagging in enabled or disabled It is set when the TAGGO command is executed and cleared when BDM is entered The serial system is disabled and the tag function enabled 16 cycles after this bit is written BDM cannot process serial commands while tagging is active 1 Tagging enabled 0 Tagging not enabled or BDM active SDV Shift data valid This bit is set and cleared by the BDM hardware It is set after data has been transmitted as part of a firmware read command or after data has been received as part of a firmware write command It is cleared when the next BDM command has been received or BDM is exited SDV is used by the standard BDM firmware to control program flow execution 1 Data phase of command is complete 0 Data phase of command not complete TRACE TRACE BDM firmware command is being executed This bit gets set when a BDM TRACE firmware command is first recognized It will stay set as long as continuous back to back TRACE commands are executed This bit will get cleared when the next command that is not a TRACE command is recognized 1 TRACE1 command is being executed 0 TRACE command is not being executed CLKSW Clock switch The CLKSW bit controls which clock the BDM operates with It is only writable from a hardware BDM command A 150 cycle delay at the
538. sh EEPROM are erased This being the case the UNSEC bit will get set The BDM program jumps to the start of the standard BDM firmware and the secured mode BDM firmware is turned off If the EEPROM and FLASH do not verify as erased the BDM firmware sets the ENBDM bit without asserting UNSEC and the firmware enters a loop This For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc causes the BDM hardware commands to become enabled but does not enable the software commands This allows the BDM hardware to be used to erase the EEPROM and FLASH 14 4 2 Enabling and Activating BDM The system must be in active BDM to execute standard BDM firmware commands BDM can be activated only after being enabled BDM is enabled by setting the ENBDM bit in the BDM status BDMSTS register The ENBDM bit is set by writing to the BDM status BDMSTS register via the single wire interface using a hardware command such as WRITE_BD_BYTE After being enabled BDM is activated by one of the following e Hardware BACKGROUND command BDM external instruction tagging mechanism e CPU BGND instruction e Breakpoint sub block s force or tag mechanism When BDM is activated the CPU finishes executing the current instruction and then begins executing the firmware in the standard BDM firmware lookup table When BDM is activated by the breakpoint sub block the type of breakpoint used determines
539. so each line segment is effectively divided into 256 pieces During execution of the TBL or ETBL instruction the difference between the end point y value and the beginning point y value a signed byte for TBL or a signed word for ETBL is multiplied by the B accumulator to get an intermediate delta y term The result is the y value of the beginning point plus this signed intermediate delta y value C 7 9 Extended Bit Manipulation The M68HC11 CPU only allows direct or indexed addressing This typically causes the programmer to dedicate an index register to point at some memory area such as the on chip registers The HCS12 allows all bit manipulation instructions to work with direct extended or indexed addressing modes C 7 10 Push and Pull D and CCR The HCS12 includes instructions to push and pull the D accumulator and the CCR It is interesting to note that the order in which 8 bit accumulators A and B are stacked for interrupts is the opposite of what would be expected for the upper and lower bytes of the 16 bit D accumulator The order used originated in the M6800 an 8 bit microprocessor developed long before anyone thought 16 bit single chip devices would be made The interrupt stacking order for accumulators A and B is retained for code compatibility C 7 11 Compare SP This instruction was added to the HCS12 instruction set to improve orthogonality and high level language support One of the most important requirements for C high level lan
540. sociated with PA7 and address AO and data DO is associated with PBO The bus control related pins in Port E PE7 NOACC PE6 MODB IPIPE1 PES MODA ITPIPEO PE4 ECLK PE3 LSTRB TAGLO and PE2 R W are all configured to serve their bus control output functions rather than general purpose I O Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted The main difference between emulation modes and normal modes is that some of the bus control and system control signals cannot be written in emulation modes 12 4 8 3 Peripheral Mode This mode is intended for Motorola factory testing of the system In this mode the CPU is inactive and an external tester bus master drives address data and bus control signals in through Ports A B and E In effect the whole system acts as if it was a peripheral under control of an external CPU This allows faster testing of on chip memory and peripherals than previous testing methods Since the mode control register is not accessible in peripheral mode the only way to change to another mode is to reset the system into a different operating mode 12 4 8 4 Emulation Expanded Wide Mode In expanded wide modes Ports A and B are configured as a 16 bit multiplexed address and data bus and Port E provides bus control and status signals These signals allow external memory and peripheral devices to be interfaced to the system These signals can also be used by a logic anal
541. special case in which the membership function either starts with a grade of FF at input point_1 or ends with a grade of FF at input point_2 infinite slope During execution the value of A remains the same X is incremented by four and Y is incremented by one Address Machine Source Form Mode Code Hex CPU Cycles MEM Special 01 RRfOw For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 MINA Minimum in A MINA Operation MIN A M gt A Subtracts an unsigned 8 bit value in M from an unsigned 8 bit value in A to determine which is larger Puts the smaller value in A If the values are equal the Z bit is set If the value in M is larger the C bit is set If the value in A is larger the C bit is cleared when the value in M replaces the value in A MINA accesses memory with indexed addressing modes for flexibility in specifying operand addresses Autoincrement and autodecrement functions can facilitate finding the smallest value in a list of values CCR Effects S XH I N Z V C A A A A N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V A7e M7 e R7 A7 e M7 e R7 set if the operation produced a two s complement overflow cleared otherwise C A7 M7 M7 e R7 R7 e A7 set if the value of the value in M is larger than the value in A cleared other
542. sponds to a misaligned access to a memory that is not designed for single cycle misaligned access 8 bit conditional write An x cycle is either a data write cycle or a free cycle depending on the data and flow of the REV or REVW instruction An x cycle is stretched only when controlled by a chip select circuit programmed for slow memory Special No PPP P tation for Branch Taken Not Taken A short branch requires three cycles if taken one cycle if not taken Since the instruction consists of a single word containing both an opcode and an 8 bit offset the not taken case is simple the queue advances another program word fetch is made and execution continues with the next instruction The taken case requires that the queue be refilled so that execution can continue at a new address First the effective address of the destination is determined then the CPU performs three program word fetches from that address OPPP OPO A long branch requires four cycles if taken three cycles if not taken An o cycle is required because all long branches are page two opcodes and thus include the 18 prebyte The prebyte is treated as a one byte instruction If the prebyte is misaligned the O cycle is a P cycle if the prebyte is aligned the o cycle is an cycle As a result both the taken and not taken cases use one O cycle for the prebyte In the not taken case the queue must advance so that execution can continue with the next instruc
543. ss of the instruction following the CALL as a return address For code compatibility CALL also executes correctly in devices that do not have expanded memory capability Decrements SP by two allowing the two return address bytes to be stacked Stacks the return address SP points to the high byte of the return address Decrements SP by one allowing the current PPAGE value to be stacked Stacks the value in PPAGE Writes a new page value supplied by the instruction to PPAGE Transfers control to the subroutine In indexed indirect modes the subroutine address and PPAGE value are fetched in the order M high byte M low byte and new PPAGE value Expanded memory subroutines must be terminated by an RTC instruction which restores the return address and PPAGE value from the stack S X H l N Z V C Address Machine Source Form Mode Code Hex CPU Cycles CALL opr16a page EXT 4A hh 11 pg gnSsPPP CALL oprx0_xysppc page IDX 4B xb pg gnSsPPP CALL oprx9 xysppc page IDX1 4B xb ff pg gnSsPPP CALL oprx16 xysppc page IDX2 4B xb ee ff pg fgnSsPPP CALL D xysppc D IDX 4B xb flignSsPPP CALL oprx16 xysppc IDX2 4B xb ee ff flignSsPPP For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 CBA Compare B to A CBA Operation CCR Effects Code and CPU Cycles A B Compares the value in A with the value in B Condition code bits affected by the
544. st lowest priority I maskable interrupt Table 6 1 Exception Vector Map and Priority Vector Address Source FFFE FFFF System reset FFFC FFFD Crystal Monitor reset FFFA FFFB COP reset FFF8 FFF9 Unimplemented opcode trap FFF6 FFF7 Software interrupt instruction SWI or BDM vector request FFF4 FFF5 XIRQ signal FFF2 FFF3 TRQ signal FFFO FFOO psec aay a maskable interrupt sources priority in The six highest vector addresses are used for resets and nonmaskable interrupt sources The remaining vectors are used for maskable interrupts All vectors must be programmed to point to the address of the appropriate service routine For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc 6 3 Exception Types As stated previously the Core supports exceptions from resets within the system as well as interrupt requests Each of these exception types are discussed in the subsections that follow 6 3 1 Resets A block or blocks within the SoC design must evaluate any all reset sources and request the proper reset vector from the Core The CPU then fetches a vector determined by the source of the reset configures the CPU registers to their reset states and fills the instruction queue from the address pointed to by the vector There are three reset sources supported by the Core e System reset e Crystal Monitor reset e COP Watchdog reset The
545. stbyte follows all indexed addressing opcodes There may be 0 1 or 2 extension bytes after the postbyte The postbyte and extensions do the following tasks 1 2 3 Select a register for indexing X Y SP PC A B or D Enable automatic pre or postincrementing or decrementing of X Y or SP and select the pre or postincrement value Select 5 bit 9 bit or 16 bit signed constant offsets Table 4 2 shows how the postbyte enhances indexed addressing capabilities For More Information On This Product Go to www freescale com Core User Guide si2cPu Rf Scale Semiconductor Inc Table 4 2 Summary of Indexed Operations 5 bit constant offset indexed addressing IDX 7 6 5 4 3 2 1 0 Postbyte rr 0 5 bit signed offset Effective address 5 bit signed offset X Y SP or PC Accumulator offset addressing IDX 7 6 5 4 3 2 1 0 Postbyte 1 1 1 rr 1 aa Effective address X Y SP or PC A B or D Autodecrement autoincrement indexed addressing IDX 7 6 5 4 3 2 1 0 Postbyte rri 1 p 4 bit inc dec value Effective address X Y or SP 1 to 8 9 bit constant offset indexed addressing IDX1 5 4 3 7 6 2 1 0 Postbyte EA Effective address s offset extension byte X Y SP or PC 16 bit constant offset indexed addressing IDX2 7 6 5 4 3 2 1 0 Postbyte 1 1 1 rr o 1 0 Effective address two offset extension bytes X Y SP or PC 16
546. stem output Singleton membership functions consist of the x axis position for a label of the system output Fuzzy outputs correspond to the y axis height of the corresponding output membership function The WAV instruction calculates the numerator and denominator sums for weighted average of the fuzzy outputs according to the formula n Y SF System Output t LF i 1 where n is the number of labels of a system output S are the singleton positions from the knowledge base F are the fuzzy outputs from RAM For a common fuzzy logic program n is eight or less though this instruction can handle any value to 255 and S and F are 8 bit values The final divide is performed with a separate EDIV instruction placed immediately after the WAV instruction Before executing WAV an accumulator must be loaded with the number of iterations n one index register must be pointed at the list of singleton positions in the knowledge base and a second index register must be pointed at the list of fuzzy outputs in RAM If the system has more than one system output the WAV instruction is executed once for each system output B 4 Example Inference Kernel Figure B 3 is a complete fuzzy inference kernel written in assembly language Numbers in square brackets are cycle counts The kernel uses two system inputs with seven labels each and one system output with seven labels The program assembles to 57 bytes It executes in about 54 us at an 8 MHz bus
547. ster IRQCR Read see individual bit descriptions below Write see individual bit descriptions below For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 IRQE IRQ select edge sensitive only Special read or write anytime Normal read anytime write once Emulation read anytime write never 1 IRQ configured to respond only to falling edges Falling edges on the IRQ pin will be detected anytime IRQE 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt i e vector FFF2 0 IRQ configured for low level recognition IRQEN External IRQ enable Normal emulation and special modes read or write anytime 1 External IRQ pin is connected to interrupt logic 0 External IRQ pin is disconnected from interrupt logic NOTE In this state the edge detect latch is disabled For More Information On This Product Go to www freescale com Core User Guide si2cru ERA Scale Semiconductor Inc 12 3 13 Reserved Registers Address Base 4thru 7 BIT 7 6 5 4 3 2 1 BIT O Read 0 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Address Base F Read 0 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 12 15 Reserved Registers These register locations are not used reserved All unused registers and bits in this block return logic zeros when read Writes to these registers
548. structions bits that are set indicate bits to be affected Log Program page or bank number used in CALL instruction qq High byte of a 16 bit relative offset for long branches tn Trap number from 30 to 39 or from 40 to FF Signed relative offset 80 128 to 7F 127 relative to the byte following the relative offset byte or low byte of a 16 bit relative offset for long branches xb Indexed addressing postbyte A 2 6 Source Form Notation The Source Form column on the glossary pages gives essential information about assembler source forms For complete information about writing source files for a particular assembler refer to the documentation provided by the assembler vendor Everything in the Source Form column except expressions in italic characters is literal information which must appear in the assembly source file exactly as shown The initial 3 to 5 letter mnemonic is always a literal expression All commas pound signs parentheses square brackets or plus signs minus signs and the register designation A B D are literal characters The groups of italic characters shown in Table A 6 represent variable information to be supplied by the programmer These groups can include any alphanumeric character or the underscore character but cannot include a space or comma For example the groups xysppc and oprx0_xysppc are both valid but the two groups oprx0 xysppc are not valid because
549. t There is no data movement in the instruction queue during the cycle This occurs during execution of instructions that must perform a number of internal operations such as division instructions 5 2 2 Advance and Load from Data Bus The content of queue stage 1 advances to stage 2 stage 2 advances to stage 3 and stage 1 is loaded with a word of program information from the data bus For More Information On This Product Go to www freescale com Core User Guide si2cru Rf Scale Semiconductor Inc 5 3 Changes of Flow Most of the time the instruction queue operates in a continuous sequence of queue movement cycles When program flow changes because of an exception subroutine call branch or jump the queue automatically adjusts its movement sequence to accommodate the change in program flow 5 3 1 Exceptions Exceptions include three types of reset an unimplemented opcode trap a software interrupt instruction X bit maskable interrupts and I bit maskable interrupts To minimize the effect of queue operation on exception handling e The exception vector fetch is the first part of exception processing e Fetches to refill the queue from the new address are interleaved with the context stacking operations so that program access time does not delay the switch Please see Section 6 of this guide for more detailed information on exception processing 5 3 2 Subroutines The CPU can branch to BSR jump to JSR or CALL su
550. t Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc DECB Decrement B DECB Operation CCR Effects Code and CPU Cycles B 01 B Subtracts one from the value in B The N Z and V bits are set or cleared by the operation The C bit is not affected by the operation allowing the DEC instruction to be used as a loop counter in multiple precision computations N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Set if operation produces a two s complement overflow if and only if B was 80 before the operation cleared otherwise Address Machine Mode Code Hex CPU Cycles Source Form For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG v1 2 DES Dee sr DES same as LEAS 1 SP Operation SP 0001 SP Subtracts one from SP DES assembles as LEAS 1 SP DES does not affect condition code bits as DEX and DEY do CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex DES IDX 1B 9F Pf For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc DEX Decrement X DEX Operation X 0001 X Subtracts one from X The Z bit reflects the result The LEAX 1 X instruction does the same thing as DEX but without a
551. t Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 E M U L Extended Multiply Unsigned E M U L Operation D x Y gt Y D Multiplies an unsigned 16 bit value in D by an unsigned 16 bit value in Y Puts the high 16 bits of the unsigned 32 bit result in Y and the low 16 bits of the result in D The C bit can be used to round the low 16 bits of the result CCR Effects S XH I N Z V C N Set if the MSB of the result is set cleared otherwise Z Set if result is 00000000 cleared otherwise C Set if bit 15 of the result is set cleared otherwise Code and CPU Source Form ariei Code Hex CPU Cycles Cycles For More Information On This Product Go to www freescale com Core User Guide si2cPu RR Scale Semiconductor Inc E M U LS Extended Multiply Signed E M U LS Operation D x Y gt Y D Multiplies a signed 16 bit value in D by a signed 16 bit value in Y Puts the high 16 bits of the 32 bit signed result in Y and the low 16 bits of the result in D The C bit can be used to round the low 16 bits of the result CCR Effects S XH I N Z V C N Set if the MSB of the result is set cleared otherwise Z Set if result is 00000000 cleared otherwise C Set if bit 15 of the result is set cleared otherwise Code and CPU Source Form oS Code Hex CPU Cycles Cycles NOTES 1 EMULS has an extra free cycle if it is followed by another page two instruction For More Information On This P
552. t for REV consists of 8 bit offsets from this base address to particular fuzzy inputs or fuzzy outputs The special value FE is interpreted by REV as a marker between rule antecedents and consequents Line 16 initializes the A accumulator to the highest 8 bit value in preparation for finding the smallest fuzzy input referenced by a rule antecedent The LDAA FF instruction also clears the V bit in the condition code register so the REV instruction knows it is processing antecedents During rule list processing the V bit is toggled each time an FE is detected in the list The V bit indicates whether REV is processing antecedents or consequents Line 17 is the REV instruction a self contained loop to process successive elements in the rule list until an FF character is found For a system of 17 rules with two antecedents and one consequent each the REV instruction takes 259 cycles but it is interruptible so it does not cause a long interrupt latency Lines 18 through 20 set up pointers and an iteration count for the WAV instruction Line 21 is the beginning of defuzzification The WAV instruction calculates a sum of products and a sum of weights Line 22 completes defuzzification The EDIV instruction performs a 32 bit by 16 bit divide on the intermediate results from WAV to get the weighted average Line 23 moves the EDIV result into the double accumulator Line 24 stores the low 8 bits of the defuzzification result This example infer
553. t fuzzy logic programs These instructions have a very small impact on the size of the CPU and even less impact on the cost of a complete MCU At the same time these instructions dramatically reduce the object code size and execution time for a fuzzy logic inference program A kernel written for the M68HC11 required about 250 bytes The HCS12 kernel uses about 50 bytes For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc C 7 8 Table Lookup and Interpolation The HCS12 instruction set includes two instructions TBL and ETBL for lookup and interpolation of compressed tables Consecutive table values are assumed to be the x coordinates of the endpoints of a line segment The TBL instruction uses 8 bit table entries y values and returns an 8 bit result The ETBL instruction uses 16 bit table entries y values and returns a 16 bit result An indexed addressing mode is used to identify the effective address of the data point at the beginning of the line segment and the data value for the end point of the line segment is the next consecutive memory location byte for TBL and word for ETBL In both cases the B accumulator represents the ratio of the x distance from the beginning of the line segment to the lookup point to the x distance from the beginning of the line segment to the end of the line segment B is treated as an 8 bit binary fraction with radix point left of the MSB
554. t if the operation produces a two s complement overflow cleared otherwise A7 M7 M7 e R7 R7 e A7 set if there is a carry from the MSB of the result cleared otherwise lt NZL C Address Machine Code Source Form Mode Hex CPU Cycles ADDA opr8i IMM 8B ii P ADDA opr8a DIR 9B dd rPf ADDA opr16a EXT BB hh 11 rPO ADDA oprx0_xysppc IDX AB xb rPf ADDA oprx9 xysppc IDX1 AB xb ff rPO ADDA oprx16 xysppc IDX2 AB xb ee ff frPP ADDA D xysppc D IDX Jap xb fIfrPf ADDA oprx16 xysppc IDX2 AB xb ee ff IPrbf For More Information On This Product Go to www freescale com Core User Guide si2cpu af Scale Semiconductor Inc ADDB Add 108 ADDB Operation CCR Effects Code and CPU Cycles B M gt B or B imm gt B Adds either the value in M or an immediate value to the value in B and places the result in B This instruction affects the H bit so it is suitable for use in BCD arithmetic operations see DAA instruction for additional information B3 M3 M3 e R3 R3 e B3 set if there is a carry from bit 3 cleared otherwise Set if MSB of result is set cleared otherwise Set if result is 00 cleared otherwise B7 M7 R7 B7 e M7 e R7 set if the operation produces a two s complement overflow cleared otherwise B7 M7 M7 e R7 R7 e B7 set if there is a carry from the MSB of the result cleared otherwise lt NZL O
555. t the condition codes while the M68HC11 instructions update the Z bit according to the result of the decrement or increment Table C 1 shows M68HC11 instruction mnemonics that are automatically translated into equivalent HCS12 instructions This translation is performed by the assembler so there is no need to modify an old M68HC11 program in order to assemble it for the HCS12 In fact the M68HC11 mnemonics can be used in new HCS12 programs Table C 1 Translated M68HC11 Mnemonics M68HC11 Equivalent Mnemonic HCS12 Instruction Comments Since HCS12 has accumulator offset indexing ABX and ABY are rarely used in new HCS12 programs ABX was one byte on M68HC11 but ABY was two bytes The LEA substitutes are two bytes CLC ANDCC FE CLI ANDCC EF ANDCC and ORCC now allow more control over the CCR CLV ANDCC FD including the ability to set or clear multiple bits in a single SEC ORCC 01 instruction These instructions took one byte each on M68HC11 SEI ORCC 10 while the ANDCC and ORCC equivalents take two bytes each SEV ORCC 02 For More Information On This Product Go to www freescale com Core User Guide si2cru RR Scale Semiconductor Inc Table C 1 Translated M68HC11 Mnemonics M68HC11 Equivalent Mnemonic HCS12 Instruction Comments Unlike DEX and INX DES and INS did not affect CCR bits in the LEAS 1 S M68HC11 so the LEAS equivalents in HCS12 duplicate the LEAS 1 S function of DES and INS The
556. tailed description in Appendix A Table 1 2 Instruction Set Summary Address Mode Machine Coding Hex SXHINZVC Source Form Operation Access Detail ABA Add Bto A A B gt A ABXSame as LEAX B X ABYSame as LEAY B Y ADCA opr8i ADCA opr8a ADCA opr16a ADCA oprx0_xysppc ADCA oprx9 xysppc ADCA oprx16 xysppc ADCA D xysppc ADCA oprx16 xysppc Add Bto X X B gt X Add Bto Y Y B gt Y Add with carry to A A M C A or A imm C A IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 894i 99 dd B9h A9X A9X A9X A9X A9X hil b bff beeff b bee ff For More Information On This Product Go to www freescale com rPf rPO IPE rPO frPP fIfrPf fIPrPf Core User Guide si2cpu A R8gscale Semiconductor Inc Source Form ADCB opr8i ADCB opr8a ADCB opr16a ADCB oprx0_xysppc ADCB oprx9 xysppc ADCB oprx16 xysppc ADCB D xysppc ADCB oprx16 xysppc ADDA Hopr8i ADDA opr8a ADDA opr16a ADDA oprx0_xysppc ADDA oprx9 xysppc ADDA oprx16 xysppc ADDA D xysppc ADDA oprx16 xysppc Operation Add with carry to B B M C B or B imm C B Add to A A M A or A imm gt A Address Mode Machine Coding Hex Access Detail P rPf rPO rPf TPO frPP fIfrPf fIPrPf P TFE rPO rPf rPO TEPE fIfrPf fIPrPf SXHINZVC
557. tally driven signals For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPuU15UG V1 2 CLOCK TARGET SYSTEM HOST TRANSMIT 1 HOST E S TRANSMIT 0 A i AS l l l l T l l l l ERAS PERCEIVED TARGET SENSES BIT A i START OF BIT TIME 10 CY CLE S EADLIFSI TART OF SYNCHRONIZATION NEXT BIT UNCERTAINTY Figure 14 7 BDM Host to Target Serial Bit Timing The receive cases are more complicated Figure 14 8 shows the host receiving a logic 1 from the target system Since the host is asynchronous to the target there is up to one clock cycle delay from the host generated falling edge on BKGD to the perceived start of the bit time in the target The host holds the BKGD pin low long enough for the target to recognize it at least two target clock cycles The host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time The host should sample the bit level about 10 target clock cycles after it started the bit time CLOCK TARGET SYSTEM HOST DRIVE TO BKGDPIN TARGET SYSTEM SPEEDUP PULSE PERCEIVED START OF BIT TIME O Oe EA a E BKGD PIN E I 1 l l I I I I I I I Sane ie L 10 CYCLES po 10 CYCLES gt A EARLIEST START OF HOST SAMPLES NEXT BIT BKGD PIN Figure 14 8 BDM Target to Host Serial Bit Timing Logic 1 For More
558. tatement of output actions The left portion of a rule is made up of one or more in this case two antecedents connected by a fuzzy and operator Each antecedent expression consists of the name of a system input followed by is followed by a label name The label must be defined by a membership function in the knowledge base Each antecedent expression corresponds to one of the fuzzy inputs in RAM Since and is the only operator allowed to connect antecedent expressions there is no need to include these in the encoded rule The antecedents can be encoded as a simple list of pointers to or addresses of the fuzzy inputs to which they refer The right portion of a rule is made up of one or more in this case one consequents Each consequent expression consists of the name of a system output followed by is followed by a label name Each consequent expression corresponds to a specific fuzzy output in RAM Consequents for a rule can be encoded as a simple list of pointers to or addresses of the fuzzy outputs to which they refer The complete rules are stored in the knowledge base as a list of pointers or addresses of fuzzy inputs and fuzzy outputs In order for the rule evaluation logic to work there must be some means of knowing which pointers refer to fuzzy inputs and which refer to fuzzy outputs There also must be a way to know when the last rule in the system has been reached One method of organization is to have a fixed number of rules wi
559. tem and host provide brief driven high speedup pulses to drive BKGD to a logic 1 The source of this speedup pulse is the host for transmit cases and the target for receive cases The timing for host to target is shown in Figure 14 7 and that of target to host in Figure 14 8 and Figure 14 9 below All four cases begin when the host drives the BKGD pin low to generate a falling edge Since the host and target are operating from separate clocks it can take the target system up to one full clock cycle to recognize this edge The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle earlier Synchronization between the host and target is established in this manner at the start of every bit time Figure 14 7 shows an external host transmitting a logic and transmitting a logic 0 to the BKGD pin of a target system The host is asynchronous to the target so there is up to a one clock cycle delay from the host generated falling edge to where the target recognizes this edge as the beginning of the bit time Ten target clock cycles later the target senses the bit level on the BKGD pin Internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission Since the host drives the high speedup pulses in these two cases the rising edges look like digi
560. tended to two bus cycles if the MCU is operating with an 8 bit external data bus and the SP is pointing to external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory A U cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access The internal RAM is designed to allow single cycle misaligned word access 16 bit vector fetch Vectors are always aligned 16 bit words A v cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the program is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory 8 bit conditional read A t cycle is either a data read cycle or a free cycle depending on the data and flow of the REVW instruction A t cycle is stretched only when controlled by a chip select circuit programmed for slow memory 16 bit conditional read A T cycle is either a data read cycle or a free cycle depending on the data and flow of the REV or REVW instruction A T cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the corresponding data is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory A T cycle is also stretched if it corre
561. ter BDMCCR 252 Figure 14 5 BDM Internal Register Position BDMINR 253 Figure 14 11 BDM Instruction Register BDMIST 264 Figure 14 12 BDM Instruction Register BDMIST 265 Figure 14 13 BDM Shift Register BDMSHTH 267 Figure 14 14 BDM Shift Register BDMSHTL 267 Figure 14 15 BDM Address Register BDMADDh 268 Figure 14 16 BDM Address Register BDMADDL 268 Figure 15 1 Security Implementation Block Diagram 280 Figure B 1 Block Diagram of a Fuzzy Logic SysteM 504 Figure B 2 Fuzzification Using Membership Functions 506 Figure B 3 Fuzzy Inference Engine o oooocccocccccn 509 Figure B 4 Defining a Normal Membership Function 511 Figure B 5 MEM Instruction Flow Diagram 005 512 Figure B 6 Abnormal Membership Function Case 1 513 Figure B 7 Abnormal Membership Function Case 2 514 Figure B 8 Abnormal Membership Function Case 3 514 Figure B 9 REV Instruction Flow Diagram 0 005 517 Figure B 10 REVW Instruction Flow Diagram 205 522 Figure B 11 WAV and wavr Instruction Flow Diagram 526 Figure B 12 Endpoint Table Handling oooccooooccoooo 528 For More Information On This Product Go to www freescale com
562. terrupt processing flow B 6 2 Weighted Rule Evaluation REVW This instruction implements a weighted variation of min max rule evaluation The weighting factors are stored in a table with one 8 bit entry per rule The weight is used to multiply the truth value of the rule minimum of all antecedents by a value from zero to one to get the weighted result This weighted result is then applied to the consequents just as it would be for unweighted rule evaluation For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Since the REVW instruction is essentially a list processing instruction execution time depends on the number of rules and the number of elements in the rule list The REVW instruction is interruptible typically within three to five bus cycles so it does not adversely affect worst case interrupt latency Since intermediate results and instruction status are held in stacked CPU registers the interrupt service code can even include independent REV and REVW instructions The rule structure is different for REVW than for REV For REVW the rule list is made up of 16 bit elements rather than 8 bit elements Each antecedent is represented by the full 16 bit address of the corresponding fuzzy input Each rule consequent is represented by the full address of the corresponding fuzzy output The marker separating antecedents from consequents is the reserved 16 bit value FFFE
563. terrupt Requests Some system peripheral blocks can generate interrupt requests that are subject to masking by the I bit Processing of an interrupt request from one of these sources stacks the CCR and then sets the I bit to prevent other interrupts during the service routine An RTI instruction at the end of the service routine restores the I bit to its preinterrupt state Interrupt requests from a system peripheral block may also be subject to masking by interrupt enable bits in control registers In addition there may be interrupt flags with register read write sequences required for flag clearing The documentation for the system peripheral block should provide a detailed functional description For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor IN guide s12cPU15UG V1 2 Section 7 Core Interface This section provides a brief description of the Core interface to the rest of the SoC design Detailed information on the Core interface such as more complete descriptions of all signals and timing information is provided in the HCS12 V1 5 Core Integration Guide 7 1 Core Interface Overview The Core is designed to be integrated into a SoC design as a fully synthesizable block The Core interface is shown in Figure 7 1 below with the interface signals grouped by function All signals
564. th a specific number of antecedents and consequents A second method employed in Motorola Freeware M68HC11 kernels is to mark the end of the rule list with a reserved value and use a bit in the pointers to distinguish antecedents from consequents A third method of organization used in the HCS12 CPU is to mark the end of the rule list with a reserved value and separate antecedents and consequents with another reserved value This permits any number of rules and allows each rule to have any number of antecedents and consequents subject to availability of system memory Each rule is evaluated sequentially but the rules as a group are treated as if they were all evaluated simultaneously Two mathematical operations take place during rule evaluation The fuzzy and operator corresponds to the mathematical minimum operation and the fuzzy or operation corresponds to the mathematical maximum operation The fuzzy and is used to connect antecedents within a rule The fuzzy or is implied between successive rules Before evaluating any rules all fuzzy outputs are cleared meaning not true at all As each rule is evaluated the smallest minimum antecedent is taken to be the overall truth of the rule This rule truth value is applied to each consequent of the rule by storing this value to the corresponding fuzzy output unless the fuzzy output is already larger maximum If two rules affect the same fuzzy output the rule that is most true governs the value i
565. th its one s complement Each bit of B is complemented Immediately after a COM operation on unsigned values only the BEQ BNE LBEQ and LBNE branches can be expected to perform consistently After operation on two s complement values all signed branches are available N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Cleared C Set for M6800 compatibility Address Machine Source Form Mode Code Hex CPU Cycles COMB INH 51 O For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 CPD Compare D CPD Operation CCR Effects Code and CPU Cycles A B M M 1 or A B imm Compares the value in D to either the value in M M 1 or an immediate value CCR bits reflect the result The values in D and M M 1 do not change Z Set if MSB of result is set cleared otherwise Set if result is 0000 cleared otherwise V D15 e M15 e R15 D15 M15 e R15 set if the operation produces a two s complement overflow cleared otherwise C D15 M15 M15eR15 R15 D15 set if the absolute value of M M 1 is larger than the absolute value of D cleared otherwise N Address Machine Source Form Mode Code Hex CPU Cycles CPD opr16i CPD opr8a CPD opr16a CPD oprx0_xysppc CPD oprx9 xysppc CPD oprx16 xysppc CPD D xysppc CPD oprx16 xysppc AC xb ee ff For
566. th of time write data is valid is extended in the case of a stretched bus cycle Read data would not be captured by the system until the E clock falling edge In the case of a stretched bus cycle read data is not required until the specified setup time before the falling edge of the stretched E clock The external address chip selects and R W signals remain valid during the period of stretching throughout the stretched E high time 12 4 8 Modes of Operation The MEBI sub block controls the mode of the Core operation through the use of the BKGD MODB and MODA external system pins which are captured into the MODC MODB and MODA controls bits respectively at the rising edge of the system RESET pin The setup and hold times associated with these pins are given in Table 12 6 below Table 12 6 Mode Pin Setup and Hold Timing Characteristic Timing Mode programming setup time time before reset is detected high that mode pins 2 bus clock must hold their state to guarantee the proper state is entered cycles For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc Table 12 6 Mode Pin Setup and Hold Timing Characteristic Timing Mode programming hold time after reset is detected high that mode pins must hold their state to guarantee the proper state is entered The four 8 bit Ports A B E and K associated with the MEBI sub block can serve as general purpose I O
567. the MSB of B was set before the shift cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles ASLB INH 58 O For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc ASLD des ASLD Operation b7 b6 b5 b4 o3 b2 p1 bo je p7 b6 o5 b4 b3 b2 bt bo j 0 A B Shifts all bits of D one bit position to the left Bit 0 is loaded with a 0 The C bit is loaded from the most significant bit of D CCR Effects S X H I Al A N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V NO C set if N is set and C is cleared after the shift or N is cleared and C is set after the shift cleared otherwise C D15 set if the MSB of D was set before the shift cleared otherwise Code and CPU Address Machine Source Form CPU Cycles H Cycles Mode Code Hex For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 AS R Arithmetic Shift Right M AS R Operation E 7 es oa e Tor oo 6 M Shifts all bits of M one place to the right Bit 7 is held constant Bit 0 is loaded into the C bit This operation effectively divides a two s complement value by two without changing its sign The carry bit can be used to round the result CCR Effects S X H I A_A A N Set if MSB of result is set clea
568. the address following the last byte of object code in the instruction S X H I N ZV C Address Machine Source Form Mode Code Hex CPU Cycles BMI relg REL 2Brr PPP branch P no branch Branch Complementary Branch F Comment Mnemonic Opcode Test Mnemonic Opcode Test Negative Positive BMI 2B BPL 2A Simple For More Information On This Product Go to www freescale com 12CPU15UG V1 2 BMI Core User Guide si2cpu RR Scale Semiconductor Inc B N E Branch if Not Equal to Zero B N E Operation If Z 0 then PC 0002 rel PC Tests the Z bit and branches if Z 0 Rel is an 8 bit two s complement offset for branching forward or backward in memory Branching range is 80 to 7F 128 to 127 from the address following the last byte of object code in the instruction CCR Effects S XH IN ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex BNE rel8 REL 26 rr PPP branch P no branch Branch Complementary Branch Comment Mnemonic Opcode Test Mnemonic Opcode Test R M R M or or Signed BNE 26 R zero BEQ 27 R zero unsigned or For More Information On This Product Go to www freescale com BPL Operation CCR Effects Code and CPU Cycles Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Branch
569. there is a space between them For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Table A 6 Source Form Notation abc Register designator for A B or CCR abd Register designator for A B or D 8 bit mask value Some assemblers require the symbol before the mask value 8 bit immediate value 16 bit immediate value opr8a 8 bit address value used with direct address mode opr16a 16 bit address value oprx0_xysp Indexed addressing postbyte code oprx3 xysp Predecrement X Y or SP by 1 8 oprx3 xysp Preincrement X Y or SP by 1 8 oprx3 xysp Postdecrement X Y or SP by 1 8 oprx3 xysp Postincrement X Y or SP by 1 8 oprx5 xysppc 5 bit constant offset from X Y SP or PC abd xysppc Accumulator A B or D offset from X Y SP or PC Any positive integer from 1 to 8 for pre post increment decrement Any integer from 16 to 15 Any integer from 256 to 255 Any integer from 32 768 to 65 535 8 bit value for PPAGE register Some assemblers require the symbol before this value Label of branch destination within 256 to 255 locations rel16 Any label within the 64 Kbyte memory space xysppc Register designator for X or Y or SP or PC A 2 7 CPU Cycles Notation The CPU Cycles column on the glossary pages shows how many bytes of information the CPU accesses while executing an instru
570. therwise V NO C N e C NC for N and C after the shift set if N is set and C is cleared or N is cleared and C is set cleared otherwise for values of N and C after the shift C M7 set if the MSB of M was set before the shift cleared otherwise Code and CPU Source Form Code Hex CPU Cycles Cycles ROL opri6a 75 hh 11 rPwO ROL oprx0_xysppc 65 xb rPw ROL oprx9 xysppc 65 xb ff rPwO ROL oprx16 xysppc 65 xb ee ff frPwP ROL D xysppc 65 xb fIfrPw ROL oprx16 xysppc 65 xb ee ff fIPrPw For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc ROLA Rotate Left A ROLA Operation ee re far mos oa foe on A Shifts all bits of A one place to the left Bit O is loaded from the C bit The C bit is loaded from the most significant bit of A Rotate operations include the carry bit to allow extension of shift and rotate operations to multiple bytes For example to shift a 24 bit value one bit to the left the sequence ASL LOW ROL MID ROL HIGH could be used where LOW MID and HIGH refer to the low middle and high bytes of the 24 bit value respectively CCR Effects S XH I N ZV C A A A A N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C NeC N o C for N and C after the shift set if N is set and C is cleared or N is cleared and C is set cleared otherwi
571. this bit For More Information On This Product Go to www freescale com Core User Guide si2cPu ERA Scale Semiconductor Inc 12 3 9 Pullup Control Register PUCR Address Base C BIT 7 6 5 4 3 2 1 BITO Read 0 0 0 0 PUPKE PUPEE PUPBE PUPAE Write Reset 1 0 0 1 0 0 0 0 Unimplemented Figure 12 11 Pullup Control Register PUCR NOTES 1 The reset state of this register may be controlled by an instantiation parameter as described in the HCS12 V1 5 Core Integration Guide The default value of this parameter is shown Please refer to the spe cific device User s Guide to determine the actual reset state of this register Read anytime provided this register is in the map Write anytime provided this register is in the map This register is used to select pullup resistors for the pins associated with the core ports Pullups are assigned on a per port basis and apply to any pin in the corresponding port that is currently configured as an input This register is not in the on chip map in emulation and peripheral modes NOTE These bits have no effect when the associated pin s are outputs The pullups are inactive PUPKE Pullup Port K Enable 1 Enable pullup devices for Port K input pins 0 Port K pullups are disabled PUPEE Pullup Port E Enable 1 Enable pullup devices for Port E input pins bits 7 4 0 0 Port E pullups on bit 7 4 0 are disabled PUPBE Pullup Port B Enable 1 Ena
572. this instruction Address Machine Source Form Mode code Hox CPU Cycles 1 WAV Special 18 3c Seaman SSStuuvrr NOTES 1 The 7 cycle loop frrffff is the loop for one iteration of SOP and SOW accumulation 2 These are additional cycles caused by interrupt sss is a three cycle exit sequence and UUUrr is a five cycle re entry sequence Six extra bytes of stack are used for intermediate values For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 XGDX emex XGDX same as EXG D X Operation D X Exchanges the value in D with the value in X XGDX assembles as EXG D X CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex XGDX For More Information On This Product Go to www freescale com Core User Guide si2cpuI af Scale Semiconductor Inc XGDY comer XGDY same as EXG D Y Operation D S Y Exchanges the value in D with the value in Y XGDY assembles as EXG D Y CCR Effects S XH I N ZV C Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex XGDY For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Appendix B Fuzzy Logic Support B 1 General This section describes the use of fuzzy logic in control systems discusses the fuzzy logic instructions and provides examples of
573. through the C bit to facilitate multiple word shifts 1 Carry or borrow 0 No carry or borrow 3 2 Core Register Map The Core registers are those that are part of the sub blocks that support the CPU to makeup the entire Core block In addition to the registers contributed by the Core sub blocks sections of the Core space are reserved for registers contributed by the system peripherals and memory sub blocks These registers are configured at integration of the Core into the SoC design The Core register map summary is shown in Figure 3 9 below The Core registers with the exception of those associated with the BDM sub block addresses FFOO through FF07 can be mapped to any 2K byte block within the first 32K byte space of the standard 64K byte address area by configuring the INITRG register For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 For detailed descriptions of the Core register and bit functionality please refer to Core sub block description sections of this guide To assist in locating this more detailed information Table 3 1 below lists the Core registers the sub block they are associated with and a brief description of function Address 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 Name PORTA PORTB DDRA DDRB Reserved Reserved
574. tion and another o cycle is required to maintain the queue The taken case requires that the queue be refilled so that execution can continue at a new address First the effective address of the destination is determined then the CPU performs three program word fetches from that address For More Information On This Product Go to www freescale com Core User Guide s1ocpuiataRscale Semiconductor Inc A 3 Glossary ABA Add Bto A ABA Operation CCR Effects Code and CPU Cycles A B gt A Adds the value in B to the value in A and places the result in A The value in B does not change This instruction affects the H bit so it is suitable for use in BCD arithmetic operations see DAA instruction for additional information H A3 o B3 B3 o R3 R3 e A3 set if there is a carry from bit 3 cleared otherwise N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V A7 B7 o R7 A7 B7 e R7 set if the operation produces a two s complement overflow cleared otherwise C A7 B7 B7 o R7 R7 e A7 set if there is a carry from the MSB of the result cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles ABA INH 18 06 OO For More Information On This Product Go to www freescale com ABX Operation CCR Effects Code and CPU Cycles Freescale Semiconductor WOE Guide X
575. tion rather than performing the index modification as a separate operation Transfer and exchange operations often allow register contents to be temporarily saved in another register rather than having to save the contents in memory Some HCS12 instructions such as MIN and MAX combine the actions of several M68HC11 instructions into a single operation C 7 Additional Functions The HCS12 offers many new functions over that of the M68HC11 These new features are discussed in the subsections below C 7 1 New Instructions The HCS12 incorporates a number of new instructions that provide added functionality and code efficiency Among other capabilities these new instructions allow efficient processing for fuzzy logic applications and support subroutine processing in extended memory beyond the standard 64K byte address map for HCS12 systems incorporating this feature Table C 4 is a summary of these new instructions Subsequent paragraphs discuss significant enhancements Table C 4 New HCS12 Instructions Mnemonic Addressing Modes Brief Functional Description ANDCC Immediate AND CCR with mask replaces CLC CLI and CLV BCLR Extended Bit s clear added extended mode BGND Inherent Enter background debug mode if enabled BRCLR Extended Branch if bit s clear added extended mode BRSET Extended Branch if bit s set added extended mode BSET Extended Bit s set added extended mode Similar to JSR except also
576. tion On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 DA A Decimal Adjust A for BCD D A A Operation DAA adjusts the value in A and the state of the C bit to represent the correct binary coded decimal BCD sum and the associated carry when a BCD calculation is performed To execute DAA the value in A the state of the C bit and the state of the H bit must all be the result of performing an ABA ADD or ADC on BCD operands with or without an initial carry The table below shows DAA operation for all legal combinations of input operands The first four columns represent the results of ABA ADC or ADD operations on BCD operands The correction factor in the fifth column is added to the accumulator to restore the result of an operation on two BCD operands to a valid BCD value and to set or clear the C bit All values are in hexadecimal C Value A 7 6 5 4 Value H Value A 3 2 1 0 Value Correction Corrected C bit 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 0 A F 0 0 9 60 1 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 CCR Effects S XH I N Z V A A N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise C Represents BCD carry Code and CPU Source Form aTe Code Hex CPU Cycles Cycles DAA INH 18 07 OfO Fo
577. tion codes reflect internal subtraction R A M Address Machine Source Form Mode Code Hex CPU Cycles MINM oprx0_xysppc IDX 18 1D xb OrPw MINM oprx9 xysppc IDX1 18 1D xb ff OrPwO MINM oprx16 xysppc IDX2 18 1D xb ee ff OfrPwP MINM D xysppc D IDX 18 1D xb OfIfrPw MINM oprx16 xysppc IDX2 18 1D xb ee ff OfIPrPw For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 MOVB Move Byte MOVB Operation CCR Effects Code and CPU Cycles M1 M Moves the value in one 8 bit memory location M4 to another 8 bit memory location M3 The value in My does not change Move instructions can use different addressing modes to access the source and destination of a move Supported addressing mode combinations are IMM EXT IMM IDX EXT EXT EXT IDX IDX EXT and IDX IDX IDX operands allow indexed addressing mode specifications that fit in a single postbyte including 5 bit constant accumulator offsets and autoincrement decrement modes Nine bit and 16 bit constant offsets would require additional extension bytes and are not allowed Indexed indirect modes for example D r are also not allowed S X H I N Z V C aaa Source Form ETA y eye Hex CPU Cycles MOVB opr8 opr16a IMM EXT 18 OB ii hh 11 OPwP MOVB opr8i oprx0_xysppc IMM IDX 18 08 xb ii OPwO MOVB opr16a opr16a EXT EXT 18 OC hh 11 hh 11 OrPwPO MOVB opr16a oprx0_xysppc
578. to a Motorola general purpose Core Much of the speed is due to an execution unit that can perform several operations simultaneously Table C 3 compares the speed of HCS12 and M68HC11 math instructions The HCS12 requires fewer cycles to perform an operation and the cycle time is half that of the M68HC11 For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Table C 3 Comparison of Math Instruction Speeds Instruction Math even soda A HCS12 Mnemonic Operation 250 ns 1 Cycle 250 ns 1 Cycle 125 ns 8x8 16 MUL signed 10 cycles 1 cycle 16x16 32 unsigned Po j EAS 16 x 16 32 signed 20 cycles 3 cycles 16 16 16 unsigned 41 cycles 12 cycles q 16 i 16 z unsigned 32 16 16 a aea 32 x 16 x 16 32 signed MAC 33 cycles 11 cycles 37 cycles 12 cycles EMACS 20 cycles 13 cycles The IDIVS instruction is included specifically for C compilers where word sized operands are divided to produce a word sized result unlike the 32 16 16 EDIV The EMUL and EMULS instructions place the result in registers so a C compiler can choose to use only 16 bits of the 32 bit result C 6 3 Code Size Reduction HCS12 assembly language programs written from scratch tend to be 30 smaller than equivalent programs written for the M68HC11 This figure has been independently qualified by Motorola programmers and an independent C compil
579. tputs Port E bits 1 and 0 can be read regardless of whether the alternate interrupt function is enabled The value in a DDR bit also affects the source of data for reads of the corresponding PORTE register If the DDR bit is zero input the buffered pin input state is read If the DDR bit is one output the associated port data register bit state is read This register is not in the on chip map in peripheral mode It is also not in the map in expanded modes while the EME control bit is set DDRE7 2 Data Direction Port E 1 Configure the corresponding I O pin as an output 0 Configure the corresponding I O pin as an input CAUTION lt is unwise to write PORTE and DDRE as a word access If you are changing Port E pins from inputs to outputs the data may have extra transitions during the write It is best to initialize PORTE before enabling as outputs For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 12 3 7 Port E Assignment Register PEAR Address Base A BIT 7 6 5 4 3 2 1 BIT O Read 0 0 0 mee PIPOE NECLK LSTRE RDWE Write Special Reset 0 0 0 0 0 0 0 0 Single Chip Reset 0 0 1 0 1 1 0 0 Special Test Reset 0 0 0 0 0 0 0 0 Peripheral Reset 1 0 1 0 4 4 0 0 Emulation Exp Nar Reset 1 0 1 0 1 4 0 0 Emulation i Exp Wide Normal Reset 0 0 0 1 0 0 0 0 Single Chip Normal Reset 0 0 0 0 0 0 0 0 Exp Nar Reset 0 0 0 0 0 0 0 0 Normal
580. tretched only when controlled by a chip select circuit programmed for slow memory Stack 16 bit data An s cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the SP is pointing to external memory There can be additional stretching if the address space is assigned to a chip select circuit programmed for slow memory An s cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access The internal RAM is designed to allow single cycle misaligned word access For More Information On This Product Go to www freescale com Freescale Semiconductor ING cuide s12cPU15UG V1 2 Table A 7 CPU Cycle Notation Continued 8 bit data write A w cycle is stretched only when controlled by a chip select circuit programmed for slow memory 16 bit data write A w cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the corresponding data is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory A w cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access Unstack 8 bit data A w cycle is stretched only when controlled by a chip select circuit programmed for slow memory Unstack 16 bit data A U cycle is ex
581. trol Register PUCR Figure 12 12 Reduced Drive Register RDRIV Figure 12 13 External Bus Interface Control Register EBICTL Figure 12 14 IRQ Control Register IRQCR oo ooooooooo Figure 12 15 Reserved RegisterS o ooococccoocccconn mo Figure 12 16 Port K Data Register PORTK o oooccooooccoooo Figure 12 17 Port K Data Direction Register DDRK Figure 13 1 Breakpoint Block DiagraM oooccooocccoooo Figure 13 2 Breakpoint Register SumMary o oooccocooccooo Figure 13 3 Breakpoint Control Register 0 BKPCTO Figure 13 4 Breakpoint Control Register 1 BKPCT1 Figure 13 5 Breakpoint First Address Expansion Register BKPOX For More Information On This Product Go to www freescale com Freescale Semiconductor ME Guide Figure 13 6 Breakpoint First Address High Byte Register BKPOH 243 Figure 13 7 Breakpoint First Address Low Byte Register BKPOL 243 Figure 13 8 Breakpoint Second Address Expansion Register BKP1X 244 Figure 13 9 Breakpoint Data High Byte Register BKP1H 244 Figure 13 10 Breakpoint Data Low Byte Register BKP1L 245 Figure 14 1 BDM Block Diagram 2 20 cee eee eee 248 Figure 14 2 BDM Register Map Summary 0000 2005 249 Figure 14 3 BDM Status Register BDMSTS 24 250 Figure 14 4 BDM CCR Holding Regis
582. truction stream 8 bit or immediate ee IMM 16 bit size implied by context INST opr16i prec Dy i Direct INST opr8a DIR Operand is the lower 8 bits of an address in the range Extended INST opr16a 0000 00FF Operand is a 16 bit address Relative INST rel8 or INST rel16 Effective address is the value in PC plus an 8 bit or 16 bit relative offset value Indexed 5 bit offset Indexed predecrement INST oprx5 xysp INST oprx3 xys IDX Effective address is the value in X Y SP or PC plus a 5 bit signed constant offset Effective address is the value in X Y or SP autodecremented by 1 to 8 For More Information On This Product Go to www freescale com Freescale Semiconductor ME Guide 12CPU15UG V1 2 Table 1 1 Addressing Mode Summary Addressing Mode Indexed preincrement Source Form INST oprx3 xys Abbreviation Description Effective address is the value in X Y or SP autoincremented by 1 to 8 Indexed postdecrement Indexed postincrement Indexed accumulator offset INST oprx3 xys INST oprx3 xys INST abd xysp Effective address is the value in X Y or SP The value is postdecremented by 1 to 8 Effective address is the value in X Y or SP The value is postincremented by 1 to 8 Effective address is the value in X Y SP or PC plus the value in A B or D Indexed 9 bit offset Indexed 16 bit offset
583. turns a 16 bit result Indexed addressing identifies the effective address of the data point at the beginning of the line segment The data value for the end point of the line segment is the next consecutive memory location The data values are bytes for TBL and words for ETBL In both cases the B accumulator contains the ratio x distance from beginning of line segment to lookup point x distance from beginning to end of line segment The value in B is treated as an 8 bit binary fraction with radix point left of the MSB so each line segment can effectively be divided into 256 pieces During execution of the TBL or ETBL instruction the difference between the end point y value and the beginning point y value a signed byte TBL or word ETBL is multiplied by the B accumulator to get an intermediate delta y term The result is the y value of the beginning point plus this signed intermediate delta y value Because indexed addressing identifies the starting point of the line segment of interest there is a great deal of flexibility in constructing tables A common method is to break the x axis range into 256 equal width segments and store the y value for each of the resulting 257 endpoints The 16 bit D accumulator is then the x input to the table The upper eight bits in A are used as a coarse lookup to find the line segment of interest and the lower eight bits in B are used to interpolate within this line segment In the program sequence For More In
584. uctions o o o oooooo 77 Table 4 10 Boolean Logic InstructiONS oooooooooooo 78 Table 4 11 Clear Complement and Negate Instructions 78 Table 4 12 Multiplication and Division Instructions 79 Table 4 13 Bit Test and Bit Manipulation Instructions 79 Table 4 14 Shift and Rotate Instructions o oooooooooo 80 Table 4 15 Fuzzy Logic Instructions 0 00 cc eee eee eee 81 Table 4 16 Minimum and Maximum Instructions 82 Table 4 17 Multiply and Accumulate Instruction 83 Table 4 18 Table Interpolation Instructions o oo oo 83 Table 4 19 Short Branch Instructi0NS oooooooooo 84 Table 4 20 Long Branch Instructions 0 00 e eee eee eee 85 Table 4 21 Bit Condition Branch Instructi0NS 85 Table 4 22 Loop Primitive Instructions 0 0000 eee eee eee 86 For More Information On This Product Go to www freescale com Core User Guide Table 4 23 Table 4 24 Table 4 25 Table 4 26 Table 4 27 Table 4 28 Table 4 29 Table 4 30 Table 5 1 Table 5 2 Table 5 3 Table 5 4 Table 5 5 Table 5 6 Table 5 7 Table 5 8 Table 5 9 Table 5 10 Table 6 1 Table 6 2 Table 6 3 Table 7 1 Table 7 2 Table 7 3 Table 7 4 Table 8 1 Table 10 1 Table 11 1 Table 11 2 Table 11 3 Table 11 4 Table 11 5 Table 11 6 Table 11 7 Table 11 8 Table
585. uctions automatically update the N and Z condition code bits which can eliminate the need for a separate test instruction in some programs A summary of the load and store instructions is given in Table 4 3 Table 4 3 Load and Store Instructions Mnemonic Function Operation LDAA Load A from memory M A Load A with immediate value imm gt A LDAB Load B from memory M B Load B with immediate value imm gt B LDD Load D from memory M gt A M 1 gt B Load D with immediate value immy gt A imm gt B LDS Load SP from memory M SPy M 1 gt SPL Load SP with immediate value immy gt SPy imm gt SPL LDX Load X from memory M gt Xy M 1 gt XL Load X with immediate value immy gt Xy imm gt XL LDY Load Y from memory M gt Yh M 1 gt YL Load Y with immediate value immy gt Yp imm gt YL LEAS Load effective address into SP Effective address SP LEAX Load effective address into X Effective address X LEAY Load effective address into Y Effective address Y STAA Store A in memory A M STAB Store B in memory B M STD Store D in memory A gt M B gt M 1 STS Store SP in memory SP M SPL gt M 1 STX Store X in memory Xh gt M X gt M 1 STY Store Y in memory Yu M YL gt M 1 For More Information On This Product Go to www freescale com Core User Guide si2cru ERA Scale Semiconductor Inc 4 3 2 Transfer and Exchange Instructions
586. ue word with the opcode of the next instruction Since this word holds part of the next instruction the queue cannot advance after the odd byte executes or the first byte of the next instruction would be lost In this case the optional cycle appears as a free cycle since the queue is not ready to accept the next word of program information If this same instruction had been misaligned the queue would be ready to advance and the optional cycle would be used to perform a program word fetch In a single chip system or in a system with the program in 16 bit memory both the free cycle and the program fetch cycle take one bus cycle In a system with the program in an external 8 bit memory the optional cycle takes one bus cycle when it appears as a free cycle but it takes two bus cycles when used to perform a program fetch In this case the on chip integration module freezes the CPU clocks long enough to perform the cycle as two smaller accesses The CPU handles only 16 bit data and is not aware that the 16 bit program access is split into two 8 bit accesses In order to allow development systems to track events in the HCS12 instruction queue two status signals IPIPE 1 0 provide information about data movement in the queue and about the start of instruction execution A development system can use this information along with address and data information to externally reconstruct the queue This representation of the queue can also track both the data a
587. uide si2cpu A f8gscale Semiconductor Inc Table 4 1 Addressing Mode Summary Addressing Mode Indexed postincrement Source Form INST oprx3 xys Abbreviation Description Effective address is the value in X Y or SP The value is postincremented by 1 to 8 Indexed accumulator offset Indexed 9 bit offset Indexed 16 bit offset INST abd xysp INST oprx9 xysp INST oprx16 xysp IDX2 Effective address is the value in X Y SP or PC plus the value in A B or D Effective address is the value in X Y SP or PC plus a 9 bit signed constant offset Effective address is the value in X Y SP or PC plus a 16 bit constant offset Indexed indirect 16 bit offset Indexed indirect D accumulator offset INST oprx16 xysp INST D xysp 4 2 1 Effective Address IDX2 The value in X Y SP or PC plus a 16 bit constant offset points to the effective address The value in X Y SP or PC plus the value in D points to the effective address Every addressing mode except inherent mode generates a 16 bit effective address The effective address 1s the address of the memory location that the instruction acts on Effective address computations do not require extra execution cycles 4 2 2 Inherent Addressing Mode Instructions that use this addressing mode either have no operands or all operands are in internal CPU registers In either case the CPU does not need to
588. ulates weighted averages In order to be usable the fuzzy outputs produced by rule evaluation must be defuzzified to produce a single output value which represents the combined effect of all of the fuzzy outputs Fuzzy outputs correspond to the labels of a system output and each is defined by a membership function in the knowledge base The CPU typically uses singletons for output membership functions rather than the trapezoidal shapes used for inputs As with inputs the x axis represents the range of possible values for a system output Singleton membership functions consist of the X axis position for a label of the system output Fuzzy outputs correspond to the y axis height of the corresponding output membership function The WAV instruction calculates the numerator and denominator sums for a weighted average of the fuzzy outputs Because WAV requires a number of cycles to execute it can be interrupted The wavr pseudoinstruction causes execution to resume at the point where it was interrupted These instructions make comparisons between an accumulator and a memory location They can be used for linear programming operations such as Simplex method optimization or for fuzzification MAX and MIN instructions use accumulator A to perform 8 bit comparisons while EMAX and EMIN instructions use accumulator D to perform 16 bit comparisons The result maximum or minimum value can be stored in the accumulator or in the memory location A summary of the mi
589. umulator B CAii P ORAB opr8a B M gt B DA dd rPf ORAB opr16a or B imm B FAhh11 rPO ORAB oprx0_xysppc EA xb rPf ORAB oprx9 xysppc EA xb ff rPO ORAB oprx16 xysppc EA xb ee ff frPP ORAB D xysppc EA xb flfrPf ORAB oprx16 xysppc EA xbee ff fIPrPf ORCC opr i OR CCR CCR imm gt CCR Push A SP 1 gt SP A gt Mgp Push B SP 1 gt SP B gt Mgp Push CCR SP 1 gt SP CCR Mgp Push D SP 2 gt 8P A B gt Mgp Mgp Push X SP 2 SP Xy X_ gt Msp Mgp 4 Push Y SP 2 gt SP Yu Y_ gt Msp Mgp 4 Pull A Msp gt A SP 1 gt SP Pull B Mgp B SP 1 gt SP Pull CCR Mgp CCR SP 1 gt SP PULD Pull D INH 3A U O SEE Msp Msp 1 gt A B SP 2 gt SP For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Source Form Operation Pull X Mgp Mgp 4 gt X X_ SP 2 gt SP Pull Y Msp Mgp41 gt Y H YL SP 2 SP Address Mode INH Machine Coding Hex Access Detail UfO SXHINZVC Rule evaluation unweighted find smallest rule input store to rule outputs unless fuzzy output is larger Special Orf t tx O ELFOLEE The t tx loop is executed once for each
590. up table Data entries represent y coordinates of line segment endpoints Table entries and interpolated results are 8 bit values Y2 Before executing TBL point an indexing register at the Y1 value closest to but less than or equal to the Y value to interpolate Point to Y1 using any indexed addressing mode except indirect 9 bit offset YE and 16 bit offset The next table entry after Y1 is Y2 Load B with a binary fraction radix point to the left of the MSB representing the Y1 o Xi XL xo TAUG XL X1 X2 X1 where X1 Yl and X2 Y2 XL is the x coordinate of the value to interpolate The 8 bit unrounded result YL is calculated using the expression YL Y1 B x Y2 Y1 where Y1 8 bit data entry pointed to by the effective address Y2 8 bit data entry pointed to by the effective address plus one The 16 bit intermediate value B x Y2 Y1 has a radix point between bits 7 and 8 The result in A is the sum of the upper 8 bits the integer part of the intermediate 16 bit value and the 8 bit value Y1 S X H l N Z V C EARR Se N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise C Set if result can be rounded up cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 T B N E Test and Branch if Not Equal t
591. us always refers to the data in stage three of the queue The advance and load from bus signal can be used as a load enable to capture the instruction word on the data bus This signal is effectively the queue advance signal inside the CPU Program data is registered into stage one on the rising edge of t4 when queue advance is asserted 5 5 2 No Movement 0 0 The 0 0 state at the falling edge of E indicates that there is no data movement in the instruction queue during the current cycle The 0 0 state at the rising edge of E indicates continuation of an instruction or interrupt sequence during the previous cycle 5 5 3 ALD Advance and Load from Data Bus 1 0 The three stage instruction queue is advanced by one word and stage one is refilled with a word of program information from the data bus The CPU requested the information two bus cycles earlier but due to access delays the information was not available until the E cycle immediately prior to the ALD 5 5 4 INT Start Interrupt 0 1 This state indicates program flow has changed to an interrupt sequence Normally this cycle is a read of the interrupt vector However in systems that have interrupt vectors in external memory and an 8 bit data bus this cycle reads only the lower byte of the 16 bit interrupt vector 5 5 5 SEV Start Even Instruction 1 0 This state indicates that the instruction is in the even high half of the word in stage three of the instruction queue
592. us is the write data source in peripheral mode 11 5 2 3 Read Data Bus The MMC provides the control to split 16 bit accesses into two cycle operations when needed The CPU is paused during the second cycle of the two cycle access For reads the MMC takes care of swapping and holding the read data bus so that the CPU will receive the data on the correct location of its read data bus An access may also take two cycles when the Interrupt or BDM is driving the address bus if the system is in a narrow mode and the 16 bit access is to external memory space In these cases AB 0 will be forced high during the second cycle The MMC will also force those accesses that would normally be two cycle operations into a single cycle operation based upon the Wide Bus Enable signal This signal will assert when performing a 16 bit access in narrow mode to those locations that are removed from the memory map as summarized by Table 11 14 Table 11 14 Wide Bus Enable Signal Generation Register Address Names Conditions mmc_widebuse_t2 PORTA 0000 PORTB initrg 4 0 mmc_ab_t2 15 11 amp ebi_emul_t2 8 0003 DDRA ebi_narrow_t2 DDRB 0008 PORTE initrg 4 0 mmc_ab_t2 15 11 amp ebi_emul_t2 8 0009 DDRE ebi_narrow_t2 8 ebi_eme_t2 PEAR 000A MODE initrg 4 0 mmc_ab_t2 15 11 amp ebi_emul_t2 8 000D PUCR ebi_narrow_t2 RDRIV For More Information On This Product Go to www freescale com Freescale Semi
593. uted This facilitates stepping or tracing through the user code one instruction at a time If an interrupt is pending when a TRACE1 command is issued the interrupt stacking operation occurs but no user instruction is executed Once back in standard BDM firmware execution the program counter points to the first instruction in the interrupt service routine 14 4 8 Instruction Tagging The instruction queue and cycle by cycle CPU activity are reconstructible in real time or from trace history that is captured by a logic analyzer However the reconstructed queue cannot be used to stop the CPU at a specific instruction because execution already has begun by the time an operation is visible outside the system A separate instruction tagging mechanism is provided for this purpose For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 The tag follows program information as it advances through the instruction queue When a tagged instruction reaches the head of the queue the CPU enters active BDM rather than executing the instruction NOTE Tagging is disabled when BDM becomes active and BDM serial commands are not processed while tagging is active Executing the BDM TAGGO command configures two system pins for tagging The TAGLO signal shares a pin with the LSTRB signal and the TAGHI signal shares a pin with the BKGD signal Table 14 3 shows the functions of the two tagging pins
594. uth value to successive fuzzy output values until it finds another FE separator If the truth value is greater than the current output value REV writes it to the output Operation is similar to that of a MAXM instruction Rule processing continues up to the FF terminator Before executing REV clear fuzzy outputs and initialize A CCR X and Y Load A with FF Clear the V bit Load X with the address of the first 8 bit rule element in the list Load Y with the base address for fuzzy inputs and fuzzy outputs X points to the element in the rule list that is being evaluated REV updates X so that execution can resume correctly in case of an interrupt After execution X points to the address after the FF separator at the end of the rule list Y points to the base address for the fuzzy inputs and fuzzy outputs The value in Y does not change during execution For More Information On This Product Go to www freescale com Core User Guide si2cpu RR Scale Semiconductor Inc R EV Fuzzy Logic Rule Evaluation R EV continued A holds intermediate results During antecedent processing a MIN function compares each fuzzy input to the value in A and writes the smaller value to A After evaluation of all antecedents A contains the smallest input value This is the truth value used during consequent processing For subsequent rules REV reinitializes A with FF when it finds an FE separator After execution A contains the truth value for the
595. ution of the CLI instruction CCR Effects S XH I N Z V C 0 l Cleared Code and CPU Address Machine Source Form CPU Cycles Cycles Mode Code Hex CLI IMM 10 EF P For More Information On This Product Go to www freescale com Core User Guide CLR Operation CCR Effects Code and CPU Cycles Clear M 00 gt M Clears all bits in M S X H l N Z V C N Cleared Z Set V Cleared C Cleared si2cpu A A8gscale Semiconductor Inc CLR Address Machine Source Form Mode Code Hex CPU Cycles CLR opr16a EXT 79 hh 11 PwO CLR oprx0_xysppc IDX 69 xb Pw CLR oprx9 xysppc IDX1 69 xb ff PwO CLR oprx16 xysppc IDX2 69 xb ee ff PwP CLR D xysppc D IDX 69 xb PIfw CLR oprx16 xysppc IDX2 69 xbee ff PIPw For More Information On This Product Go to www freescale com CLRA Operation CCR Effects Code and CPU Cycles Freescale Semiconductor WOE Guide 12CPU15UG V1 2 CLRA Clear A 00 gt A Clears all bits in A S X H I N Z V C o 1 0o0 0 N Cleared Z Set V Cleared C Cleared Address Machine Source Form Mode Code Hex CPU Cycles CLRA INH 87 For More Information On This Product Go to www freescale com Core User Guide CLRB Operation CCR Effects Code and CPU Cycles Clear B 00 gt B Clears all bits in B S X H l N Z V C N Cleared Z Set V Cleared C Clear
596. vel Crystal Monitor reset vector request peri_xmonv_request This input signal indicates to the Core that the system is requesting the Crystal Monitor reset vector from the Core 7 2 4 4 System level COP Watchdog reset vector request peri_copv_request This input signal indicates to the Core that the system is requesting the COP Watchdog reset vector from the Core 7 2 5 Stop and Wait Mode Control Status Signals Please see Section 8 of this guide 7 2 6 Background Debug Mode BDM Interface Signals These descriptions apply to the Core BDM sub block interface with the system BKGD pad logic Please see Section 14 of this guide for further functional details of the BDM 7 2 6 1 BKGD pin Input Data to Core bkgd_ind This single bit input to the Core provides the Core with the input data from the system port pad logic for BDM BKGD pin 7 2 6 2 BKGD pin Output Data from Core core_bkgd_dout_t4 This single bit output from the Core provides the BKGD pin data output to the system port pad logic for the BDM BKGD pin 7 2 6 3 BKGD pin output buffer enable from Core core_bkgd_obe This single bit output from the Core provides the output buffer enable signal to the system port pad logic for the BDM BKGD pin For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc 7 2 6 4 BKGD pin input buffer enable from Core core_bkgd_ibe_t2 This single bit output from the Core prov
597. ven in Table 4 17 Table 4 17 Multiply and Accumulate Instruction Mnemonic Function Operation Multiply and accumulate signed 16 x 16 bit gt 32 bit My My 4 x My My 4 M M 1 M 2 M 3 gt MM 1 M 2 M 3 4 3 16 Table Interpolation Instructions The TBL and ETBL instructions interpolate values from tables stored in memory Any function that can be represented as a series of linear equations can be represented by a table Interpolation can be used for many purposes including tabular fuzzy logic membership functions TBL uses 8 bit table entries and returns an 8 bit result ETBL uses 16 bit table entries and returns a 16 bit result Indexed addressing modes provide flexibility in structuring tables Consider each of the successive values stored in a table as y values for the endpoint of a line segment The value in the B accumulator before instruction execution begins represents change in x from the beginning of the line segment to the lookup point divided by total change in x from the beginning to the end of the line segment B is treated as an 8 bit binary fraction with radix point left of the MSB so each line segment is effectively divided into 256 smaller segments During instruction execution the change in y between the beginning and end of the segment a signed byte for TBL or a signed word for ETBL is multiplied by the value in B to obtain an intermediate delta y term The result stored in the A ac
598. ven time This activation is based upon the priority outlined in Table 11 7 below If two or more blocks share the same address space only the select signal for the block with the highest priority will become active An example of this is if the registers and the RAM are mapped to the same space the registers will have priority over the RAM and the portion of RAM mapped in this shared space will not be accessible The expansion windows have the lowest priority This means that registers vectors and on chip memory are always visible to a program regardless of the values in the page select registers Table 11 7 Select Signal Priority Priority Address Space Highest BDM internal to Core firmware or register space Internal register space RAM memory block EEPROM memory block ie On chip Flash EEPROM or ROM Lowest Remaining external space In expanded modes all address space not used by internal resources is by default external memory space The data registers and data directions registers for Ports A and B are removed from the on chip memory map and become external accesses If the EME bit in the MODE register see 12 3 8 is set the data and data direction registers for Port E are also removed from the on chip memory map and become external accesses In Special Peripheral mode the first 16 registers associated with bus expansion are removed from the on chip memory map PORTA PORTB DDRA DDRB PORTE DDRE PEAR MODE PUC
599. ver stretched I Read indirect pointer Indexed indirect instructions use the 16 bit indirect pointer from memory to address the instruction operand An I cycle is a 16 bit read that can be aligned or misaligned An I cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the corresponding data is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory An I cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access i Read indirect PPAGE value An i cycle is used only in indexed indirect CALL instructions The 8 bit PPAGE value for the CALL destination is fetched from an indirect memory location An i cycle is stretched only when controlled by a chip select circuit that is programmed for slow memory n Write PPAGE register An n cycle is used only in CALL and RTC instructions to write the destination value of the PPAGE register and is not visible on the external bus Since the PPAGE register is an internal 8 bit register an n cycle is never stretched o Optional cycle An o cycle adjusts instruction alignment in the instruction queue An o cycle can be a free cycle or a program word access cycle P When the first byte of an instruction with an odd number of bytes is misaligned the o cycle becomes a P cycle to maintain queue or
600. w freescale com Core User Guide si2cru Rf Scale Semiconductor Inc 11 3 7 Memory Size Register Zero MEMSIZO Address Base 1C Read reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0 Write Reset Unimplemented Figure 11 9 Memory Size Register Zero Read Anytime Write Writes have no effect The MEMSIZO register reflects the state of the register EEPROM and RAM memory space configuration switches at the Core boundary which are configured at system integration This register allows read visibility to the state of these switches reg_sw0 Allocated System Register Space 1 Allocated system register space size is 2K byte 0 Allocated system register space size is 1K byte eep_swl eep_sw0 Allocated System EEPROM Memory Space The allocated system EEPROM memory space size is as given in Table 11 2 below Table 11 2 Allocated EEPROM Memory Space eep_sw1 eep_sw0 Allocated EEPROM Space 00 OK byte 01 2K byte 10 4K byte 11 8K byte ram_sw2 ram_sw0 Allocated System RAM Memory Space The allocated system RAM memory space size is as given in Table 11 3 below Table 11 3 Allocated RAM Memory Space ram_sw2 ram_sw0 Allocated RAM Space RAM mappable region INITRM bits used 4k Byte RAM15 RAM12 8k Byte RAM15 RAM13 8k Byte RAM15 RAM13 100 10k Byte 16k Byte RAM15 RAM14 For More Information On This Product Go to www freescale com Free
601. w freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Appendix C M68HC11 to HCS12 Upgrade C 1 General This appendix discusses aspects of upgrading system software from one based upon the Motorola 68HC11 to one using the HCS12 CPU In general the HCS12 is a proper superset of the M68HC11 instruction set as was the HC12 CPU prior to the HCS12 C 2 Source Code Compatibility Every M68HC11 instruction mnemonic and source code statement can be assembled directly with a HCS12 assembler with no modifications The HCS12 supports all M68HC11 addressing modes and includes several new variations of indexed addressing HCS12 instructions affect condition code bits in the same way as M68HC11 instructions HCS 12 object code is similar to but not identical to M68HC11 object code Some primary objectives such as the elimination of the penalty for using Y could not be achieved without object code differences While the object code has been changed the majority of the opcodes are identical to those of the M6800 which was developed more than 20 years earlier The HCS12 assembler automatically translates a few M68HC11 instruction mnemonics into functionally equivalent HCS12 instructions For example the HCS12 does not have an increment stack pointer INS instruction so the INS mnemonic is translated to LEAS 1 S The HCS12 does provide single byte DEX DEY INX and INY instructions because the LEAX and LEAY instructions do not affec
602. wed by a table of 16 bit consequent pointers The value FFFE marks boundaries between antecedents and consequents and between successive rules The value FFFF marks the end of the rule list In weighted evaluation a table of 8 bit weighting factors one per rule must be stored in memory REVW begins with the address pointed to by the first rule antecedent and evaluates successive fuzzy input values until it finds an FFFE separator Operation is similar to that of a MINA instruction The smallest input value is the truth value of the rule If weighted evaluation is enabled the truth value is modified Then beginning with the address pointed to by the first consequent REVW compares the truth value to successive fuzzy output values until it finds another FFFE If the truth value is greater than the current output value REVW writes it to the output Operation is similar to that of a MAXM instruction Rule processing continues up to the FFFF terminator Before executing REVW clear fuzzy outputs and initialize A CCR X and Y Load A with FF Clear the V bit Set or clear the C bit for weighted or unweighted evaluation For weighted evaluation load Y with the first item in a table of 8 bit weighting factors Load X with the address of the first 16 bit element in the list X points to the element in the list that is being evaluated REVW updates X so that execution can resume after an interrupt After execution X points to the address after
603. west order bits of the data input to the table Some fuzzy theorists have suggested that membership functions should be shaped like normal distribution curves or other mathematical functions This may be correct but the processing requirements to solve for an intercept on such a function would be unacceptable for most microcontroller based fuzzy systems Such a function could be encoded into a table of one of the previously described types For many common systems the thing that is most important about membership function shape is that there is a gradual transition from nonmembership to membership as the system input value approaches the central range of the membership function Let us examine the human problem of stopping a car at an intersection We might use rules like If intersection is close and speed is fast apply brakes The meaning of the labels close and fast reflected in membership function shape and position is different for a teenager than it is for a grandmother but both can accomplish the goal of stopping It makes intuitive sense that the exact shape of a membership function is much less important than the fact that it has gradual boundaries B 8 2 Rule Evaluation Variations The REV and REVW instructions expect fuzzy input and fuzzy output values to be 8 bit values Ina custom fuzzy inference program higher resolution may be desirable although this is not a common requirement The HCS12 CPU includes variations
604. wise Condition codes reflect internal subtraction R A M Code and CPU Source Form Denda Code Hex CPU Cycles Cycles MINA oprx0_xysppc IDX 18 19 xb OrPf MINA oprx9 xysppc IDX1 18 19 xb ff OrPO MINA oprx16 xysppc IDX2 1819 xb ee ff OfrPP MINA D xysppc D IDX 18 19 xb OfIfrPf MINA oprx16 xysppc IDX2 18 19 xb ee ff OfIPrPf For More Information On This Product Go to www freescale com Core User Guide siocpuiataRscale Semiconductor Inc MINM Minimum in M MINM Operation CCR Effects Code and CPU Cycles MIN A M M Subtracts an unsigned 8 bit value in M from an unsigned 8 bit value in A to determine which is larger Puts the smaller value in M If the values are equal the Z bit is set If the value in M is larger the C bit is set when the value in A replaces the value in M If the value in A is larger the C bit is cleared MINM accesses memory with indexed addressing modes for flexibility in specifying operand addresses Autoincrement and autodecrement functions can facilitate controlling the values in a list of values S X H I N Z V C a a a a N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V A7e M7 e R7 A7 M7 e R7 set if the operation produced a two s complement overflow cleared otherwise C A7 M7 M7 e R7 R7 e A7 set if the value in M is larger than the value in A cleared otherwise Condi
605. with the 16 bit integer value at the top of the stack and the stack pointer is adjusted up by eight to deallocate space for eight bytes worth of temporary storage Postincrement indexed addressing is used in this example but all four combinations of pre post increment decrement are available offsets from 8 to 8 inclusive from X Y or SP This form of indexing can often be used to get an index or stack pointer adjustment for free during an indexed operation the instruction requires no more code space or cycles than a zero offset indexed instruction 4 4 2 3 Frame Pointer In the C language it is common to have a frame pointer in addition to the CPU stack pointer The frame is an area of memory within the system stack which is used for parameters and local storage of variables used within a function subroutine The following is a description of how a frame pointer can be set up and used First parameters typically values in CPU registers are pushed onto the system stack prior to using a JSR or CALL to get to the function subroutine At the beginning of the called subroutine the frame pointer of the calling program is pushed onto the stack Typically an index register such as X is used as the frame pointer so a PSHX instruction would save the frame pointer from the calling program Next the called subroutine establishes a new frame pointer by executing a TFR S X Space is allocated for local variables by executing an LEAS n S wh
606. ww freescale com WAI Operation CCR Effects Code and CPU Cycles Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Wait for Interrupt WAI SP 0002 gt SP RTNg RTNr gt Msp Msp 1 SP 0002 gt SP Y y Y gt Msp Mgp 1 SP 0002 SP Xp XL gt Msp Mgp 1 SP 0002 SP B A gt Msp Mgp 1 SP 0001 SP CCR Msp Stop CPU clocks Puts the CPU into a wait state Uses the address of the instruction following WAI as a return address Stacks the return address and CPU registers Y X B A and CCR decrementing SP before each item is stacked The CPU then enters a wait state for an integer number of bus clock cycles During the wait state CPU clocks are stopped but other MCU clocks can continue to run The CPU leaves the wait state when it senses an interrupt that has not been masked Upon leaving the wait state the CPU sets the appropriate interrupt mask bit s and fetches the vector corresponding to the interrupt sensed Program execution continues at the location to which the vector points S X H l N Z V C Although the WAI instruction itself does not alter the condition codes the interrupt that causes the CPU to resume processing causes the bit and the X bit if the interrupt was XIRQ to be set as the interrupt vector is fetched Address Machine CPU Cycles Source Form Mode Code Hex osssssf before interrupt WAI INH 3E V PPP after interru
607. www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 CMPB Compare B CMPB Operation CCR Effects Code and CPU Cycles B M or B imm Compares the value in B to either the value in M or an immediate value CCR bits reflect the result The values in B and M do not change N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V B7 M7 e R7 B7 M7 e R7 set if the operation produces a two s complement overflow cleared otherwise C B7 M7 M7 e R7 R7 e B7 set if there is a borrow from the MSB of the result cleared otherwise Address Machine Source Form Mode Code Hex CPU Cycles CMPB opr8i IMM Cl ii p CMPB opr8a DIR D1 dd rPf CMPB opr16a EXT F1 hh 11 rPO CMPB oprx0_xysppc IDX El xb rPf CMPB oprx9 xysppc IDX1 El xb ff TRO CMPB oprx16 xysppc IDX2 El xb ee ff frPP CMPB D xysppc D IDX lez xb fIfrpf CMPB oprx16 xysppc IDX2 El xb ee ff IPrbf For More Information On This Product Go to www freescale com Core User Guide si2cpu A A8gscale Semiconductor Inc COM Complement M COM Operation CCR Effects Code and CPU Cycles M FF M gt M Replaces the value in M with its one s complement Immediately after a COM operation on unsigned values only the BEQ BNE LBEQ and LBNE branches can be expected to perform consistently After operation on two s compl
608. xb ee f f mm BSR rel8 Branch to subroutine SP 2 SP RTNy RTN_ gt Mgp Mgp 4 PC 2 rel gt PC Branch if V clear if V 0 then PC 2 rel gt PC 07 r r PPP branch P no branch CALL opr16a page CALL oprx0_xysppc page CALL oprx9 xysppc page CALL oprx16 xysppc page CALL D xysppc CALL oprx16 xysppc CLCSame as ANDCC FE Branch if V set if V 1 then PC 2 rel gt PC Call subroutine in expanded memory SP 2 gt SP RTNy RTN gt Mgp Mgp 4 SP 1 SP PPG gt Mgp pg PPAGE register subroutine address gt PC Compare A to B A B Clear C bit 4Ahh1llpg 4Bx 4Bx 4Bx 4Bx 4Bx O pg b ff pg bee ff pg b bee ff PPP branch P no branch gnSsPPP gnSsPPP gnSsPPP fgnSsPPP flignSsPPP flignSsPPP CLISame as ANDCC EF Clear bit CLR opr16a CLR oprx0_xysppc CLR oprx9 xysppc CLR oprx16 xysppc CLR D xysppc CLR oprx16 xysppc CLRA CLRB CLVSame as ANDCC FD CMPA opr8i CMPA opr8a CMPA opr16a CMPA oprx0_xysppc CMPA oprx9 xysppc CMPA oprx16 xysppc CMPA D xysppc CMPA oprx16 xysppc CMPB Hopr8i CMPB opr8a CMPB opr16a CMPB oprx0_xysppc CMPB oprx9 xysppc CMPB oprx16 xysppc CMPB D xysppc CMPB oprx16 xysppc Clear M 00 gt M Clear A 00 gt A Clear B 00 gt B Clear V Compare A A M or A imm Compare B B
609. y Due to propagation delays this value cannot be used for calculations until two cycles later in cycle 4 0 The X index register is incremented by two to point to the next element of the rule list The operations performed in cycle 4 0 depend on the value of the word read from the rule list FFFE is a special token that indicates a transition from antecedents to consequents or from consequents to For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 antecedents of a new rule The V bit toggles at every FFFE encountered and indicates which transition is taking place If V is zero a change from antecedents to consequents is taking place and it is time to apply weighting if weighting is enabled The address in TMP2 derived from Y is used to read the weight byte from memory In this case there is no bus access in cycle 5 0 but the index into the rule list is updated to point to the next rule element The old value of X Xo is temporarily held on internal nodes so it can be used to access a rule word in cycle 7 2 The read of the rule word is timed to start two cycles before it is used in cycle 4 0 of the next loop pass The multiply takes place in cycles 6 2 through 8 2 The 8 bit weight from memory is incremented possibly overflowing to 100 before the multiply and the upper eight bits of the 16 bit internal result are the weighted result By using weight 1 the result ca
610. y altlo p ao e xal alz iale wie xal alz iaje wie xajre alz iaje idj t asiz Jul xX3 S ai E aal aal aal aal ado ado ado ado als als ais 1389 em 39g asa 13sg e OJg9veoxje az 09 oOal9veowe 0612 098 z z 092 OSip 0b6 Ole Oz iyp Ol l9 p 00 2 e xXalre diz ld Wie X3alvz diz iaje wie xaje diz iaj s2 art Hije Wire ait Hi 25 gaay gaay gaay gaav vada vaav vaay vady avis avis avis TIVO GHSd 8 Sv31 LL o eJioveg3e adit sole gagvegve dell age azire agiz easjoelay yz ge le aziz al lle g0 sl e xaivz alz lajz wie xat alz ajz wie xaz alz aj xal Hille Wire ali Hi Q aveo aveo aveo aveo VWHO VWveO VWWHO WWHO vvlS WW1S WWLS TIVO Ad da Xv31 Ole E e WiYWvev3ge val vole valopevvie veil V8ge VZ b 3 Voz VS Z vwrle Velie vee wie vo S e Xa diz idj e Wie xXalre diz iaje wie xaje aji Hit HL Hz Were djt Hi S gay gay g9ay g9ay voavy voav voav v avy 10 419 aisy GHST OHSd saga Aval Xaq o e 6xJ Ybve63e 6ajl 690 6algve6ve 66 1 68 6 iy 3 69 6S L 6pZz_ 6 le 623 6lL L 60 1 e xaivz alz lajz wie xaz alz aj wie xaz ali Hit alt alle aj il HI e g403 g403 g403 gu03 VHOS VEO VHOS VHOS SV isv gisv visv OiMd Ag zebed XNI e ejoveg3e eajl 8oe geglgvegve B6 l gepv BZ 9E 891 g8s l Brie seje szj Brit 80 0 e xXalre dit Hit Hz Hit Ht Hit He xaje ait Hit HL Alle Wie ld Tu Y ISL ISL 1S4 a470 DX 841 dON VISL VID HS
611. y occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part of e freescale semiconductor HCS12 V1 5 Core For More Information On This Product Go to www freescale com
612. ycle is either a data read cycle or a free cycle depending on the data and flow of the REV or REVW instruction A T cycle is extended to two bus cycles if the MCU is operating with an 8 bit external data bus and the corresponding data is stored in external memory There can be additional stretching when the address space is assigned to a chip select circuit programmed for slow memory A T cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single cycle misaligned access 8 bit conditional write An x cycle is either a data write cycle or a free cycle depending on the data and flow of the REV or REVW instruction An x cycle is stretched only when controlled by a chip select circuit programmed for slow memory tation for Branch Taken Not Taken PPP P OPPP OPO A short branch requires three cycles if taken one cycle if not taken Since the instruction consists of a single word containing both an opcode and an 8 bit offset the not taken case is simple the queue advances another program word fetch is made and execution continues with the next instruction The taken case requires that the queue be refilled so that execution can continue at a new address First the effective address of the destination is determined then the CPU performs three program word fetches from that address A long branch requires four cycles if taken three cycles if not taken An o cycle is required because all
613. ype of access that would produce LSTRB ABO0 1 because the internal RAM is specifically designed to allow misaligned 16 bit accesses in a single cycle In these cases For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 the data for the address that was accessed is on the low half of the data bus and the data for address 1 is on the high half of the data bus Table 12 5 Access Type vs Bus Control Pins LSTRB ABO R W Type of Access 1 0 1 8 bit read of an even address 8 bit read of an odd address 0 1 0 8 bit write of an odd address 0 0 1 16 bit read of an even address 16 bit read of an odd address low high data swapped 0 0 0 16 bit write to an even address 16 bit write to an odd address low high data swapped 12 4 7 Stretched Bus Cycles In order to allow fast internal bus cycles to coexist in a system with slower external memory resources the HCS12 supports the concept of stretched bus cycles module timing reference clocks for timers and baud rate generators are not affected by this stretching Control bits in the MISC register in the MMC sub block of the Core specify the amount of stretch 0 1 2 or 3 periods of the internal bus rate clock While stretching the CPU state machines are all held in their current state At this point in the CPU bus cycle write data would already be driven onto the data bus so the leng
614. ypically termed VSS connection that is implicit when integrating into a synthesized design There are no signals at the Core interface for power and ground For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor WOE Guide 12CPU15UG V1 2 Section 10 Interrupt INT This section describes the functionality of the Interrupt INT sub block of the Core 10 1 Overview The Interrupt sub block decodes the priority of all system exception requests and provides the applicable vector for processing the exception The INT supports I bit maskable and X bit maskable interrupts a nonmaskable Unimplemented Opcode Trap a nonmaskable software interrupt SWI or Background Debug Mode request and three system reset vector requests All interrupt related exception requests are handled by the Interrupt 10 1 1 Features e Provides 2 to 122 I bit maskable interrupt vectors FFOO FFF2 e Provides 1 X bit maskable interrupt vector SFFF4 e Provides a nonmaskable Unimplemented Opcode Trap TRAP vector SFFF8 e Provides a nonmaskable software interrupt SWI or Background Debug Mode request vector SFFF6 e Provides 3 system reset vectors SFFFA FFFE e Determines the appropriate vector and drives it onto the address bus at the appropriate time e Signals the CPU that interrupts are pendin
615. yte Register BKPOL o oo 243 13 3 6 Breakpoint Second Address Expansion Register BKP1X 243 13 3 7 Breakpoint Data Second Address High Byte Register BKP1H 244 13 3 8 Breakpoint Data Second Address Low Byte Register BKP1L 244 182 ONG AON ott dorada ld eta ae 245 3 41 Modes of OPS a DE Sr E e 245 A ll A ceaGe Se See GAR aut ga E E Game 246 13 5 Motorola Internal Inforimatlon e us tr ve nee day wate dante Mo he Rea Mie eee tae ee 246 Section 14 Background Debug Mode BDM 14 OVCIMIGW ss E E eee cate taa ces 247 e A A AO 247 14 12 Block Diagram nur ge re totes Sk eae cae Sa cheer See ras eB WAT erate alana vine rad cake Se a 248 14 2 interface Signal resar pee E AAA 248 14 2 1 Background Interface Pin BKGD 00 2 0 cee eee 248 14 2 2 High Byte Instruction Tagging Pin TAGHI 00 0 0 cee cece ee eee 248 14 2 3 Low Byte Instruction Tagging Pin TAGLO 0 00 ccc cece eae 249 143 ASIS iaa OA Sate ee mee Oe A ORS eee 249 14 3 1 BDM Status Register a eee ine a a a ait aco loza 250 14 3 2 BDM CCR Holding Register c222ccts2d ies tient bond dai ab 252 14 3 3 BDM Internal Register Position Register 00 00 e eee eee oo 253 TAA DA cde Koren eee Kee emai Shes POSE Ee ee tee ae oe RAPE ee 253 TAAT SECUN e a a Ea Ih ee de e Gita da Ae oh ae 253 14 4 2 Enabling and Activating BDM cts cue rs 254 14 4 3 BDM Hardware Commands
616. yzer to monitor the progress of application programs The bus control related pins in Port E PE7 NOACC PE6 MODB IPIPE1 PES MODA ITPIPEO PE4 ECLK PE3 LSTRB TAGLO and PE2 R W are all configured to serve their bus control output functions rather than general purpose I O Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted The main difference between emulation modes and normal modes is that some of the bus control and system control signals cannot be written in emulation modes For More Information On This Product Go to www freescale com Core User Guide s12cpu af Scale Semiconductor Inc 12 4 8 5 Normal Single Chip Mode There is no external expansion bus in this mode All pins of Ports A B and K are configured as general purpose I O pins Port E bits 1 and 0 are available as general purpose input only pins with internal pullups and the other remaining pins are bidirectional I O pins that are initially configured as high impedance inputs with internal pullups enabled The pins associated with Port E bits 6 5 3 and 2 cannot be configured for their alternate functions IPIPE1 IPIPEO LSTRB and R W while the system is in single chip modes The associated control bits PIPOE LSTRE and RDWE respectively are reset to zero Writing the opposite state into them in this mode does not change the operation of the associated Port E pins In normal single chip mode the MODE reg

HCS12 V1.5 Core User Guide Version 1.2

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