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CP6010 User's Guide - CBU Documentation Portail

1. Active Low Signal D 10 CP6010 User s Guide 0 18 1 1 2 1 GND 6 BUSMODE1 INTD_P64PMC GND CLK66_PMC GND P64REQ _PMC VCC P64AD28 P64AD25 GND P64AD22 P64AD19 64 GND P64DEVSEL GND RSV P64PAR VCC P64AD12 AD9 GND P64AD6 P64AD4 VCC P64AD2 P64AD0 GND Active Low D 11 12V INTA_P64PMC INTC_P64PMC VCC N C VCC3E GND P64GNT _PMC VCC P64AD31 P64AD27 GND P64C BE 3 P64AD21 VCC P64AD17 GND P64IRDY VCC P64LOCK SBO GND P64AD15 P64AD11 VCC P64C CBEO P64AD5 GND P64AD3 P64AD1 VCC P64REQ64 CP6010 User s Guide 0 19 2 2 2 2 RSV GND N C BMODE2 PCIRST VCC3 N C P64AD30 GND P64AD24 IDSEL_PMC VCC3 P64AD18 P64AD16 GND P64TRDY GND P64PERR VCC3 P64C BE1 P64AD14 P64M66EN P64AD8 P64AD7 VCC3 N C N C GND P64ACK64 GND Active Low RSV N C GND N C N C VCC3 BMODE3 BMODE4 GND P64AD29 P64AD26 VCC3 P64AD23 P64AD20 GND P64C BE2 N C VCC3 P64STOP GND P64SERR GND P64AD13 P64AD10 VCC3 N C N C GND N C N C VCC3 N C D 12 CP6010 User s Guide 0 20 GND P64C BE6 P64C BE4 VCC3 P64AD63 P64AD61 GND P64AD59 P64AD57 VCC3 P64AD55 P64AD53 GND P64AD51 P64AD49 GND P64AD47 P
2. nna 1 9 1 7 Compatibility with Kontron Products uu 1 12 2 On board Features 2 1 Block uie nie pae eU ui Ve Era Re 2 1 NN 2 2 2 3 ESBS SOUL adii REDI Cad canteens 2 5 2 4 Super IPO ostii vr 2 9 2 5 Ethernet VIO ed 2 12 2 6 System Management 2 14 2 7 Video E YE RA 2 16 2 8 E 2 17 2 0 2 19 2 10 Debugging Fedblress 2 23 2 11 Miscellaneous Ide eu he 2 25 i CP6010 User s Guide 3 Installing the Board 3 1 Se t rig e esie 3 1 3 2 3 3 33 Memo me 3 3 3 4 On board 3 5 3 5 BACKUP Battery va dap eur AT OS EUR 3 7 3 5 Back p daa eei 3 7 3 6 Board Hot Swap and Installation sued ier voee OE ccs VES RN Ea Vere XE VIO nU E ER REA 3 8 4 Building a CPCI System 4 1 Building CPCI System 4 1 4 2 veste ote ex REED SEPA 4 6 5 Softwar
3. 5 v i RxD 14 a OTR DSR 4 DTR 2 a 5 RTS 8 RTS 2 CTS 4 18 E CTS B DCD 4 pep GND __ GND 5 27 CP6010 User s Guide Appendix Contents A Memory amp 1 0 Maps ccce 1 Interrupt 1 C Kontron Extension Registers 22222 C 1 D Connector 2 5 3 eo ieas D 1 E BIOS Setup Error Codes E 1 F BIOS Update amp Emergency F 1 Getting Teese G 1 1 CP6010 User s Guide MEMORY amp 1 0 MAPS 1 MEMORY MAPPING FFFFFh System BIOS E0000h 1MB to top of DRAM i Optional ROM Free LAN BIOS if activated 30KB See Note 1 SCSI BIOS 18 at runtime See Note 2 Optional ROM Free mM Video BIOS 100000h C0000h See detailed map to the right 0000h Video DRAM 0 640KB DRAM A0000h Note 1 LAN BIOS address may vary Note 2 SCSI BIOS address may vary Size is only 2KB if no device Address 00000 9FFFF A0000 BFFFF C0000 C7FFF C8000 DBFFF E0000 FFFFF 100000 PCI Memory PCI memory 4GB 4GB and up Function 0 640 KB DRAM Video DRAM Video BIOS Optional ROM Free LAN BIOS around 30KB if activated address may vary Exter
4. Debugging Miscellaneous Features 2 0 Block Dagia CANTI BOGGS o Gp rk OVER eee Ethernet Interfaces System Management Features Video Interface oce e rie tee e eher too CP6010 User s Guide 2 1 Block Diagram e ServerWorks E CIOB X2 intg 182546 Dual Gigabit Ethernet LANO LANI 0 J1 cPCI J2 2 1 Mezzanine CP6010 User s Guide 2 2 System Core 2 2 1 Processors CP6010 system board supports Intel s LV Low voltage Xeon processors as well as the standard voltage Xeon in the FC uPGA2 604 pin package Single and dual CPU configurations are supported In the option list you will see a list of possible configurations Both 400MHz and 533MHz front side buses are supported Major CPU features include e LV low voltage CPU e Intel NetBurst micro architecture e Hyper Threading technology support e 400 or 533MHz front side bus 512KB of L2 cache at full core speed e 64GB addressing range is cacheable e SSE2 instruction set support e Internal thermal monitor and clock speed throttling for CPU protection Please call Kontron to get the available CPU speed and con
5. WDNMIEN Enable NMI generation for watchdog WDNMI Watchdog NMI request Will clear itself on a watchdog trigger SWNMIEN Enable NMI generation for CPCI handle switch SWNMI Handle switch NMI request Cleared by disabling SWNMIEN 019BH BACKPLANE INFORMATION CPLD Address Action D7 READ ST2 019Bh WRITE NU State of hardware pins GA 4 0 Geographical address ST 2 0 Segment type As defined in PICMG2 0R3 0 ECR 2 000 Nominal left 001 Nominal right 111 Backplane do not provide segment type other reserved C 5 CP6010 User s Guide C 10 019 BMC CPLD Address Action D7 D6 D5 04 03 02 01 00 READ TEST NU NU POST BMC TAKE COM BMC COM RST PRG 0x19C WRITE NU NU NU POST NU BMC COM RST TEST If set the SBC is inserted in a CPCI test backplane This is used for Kontron test platform POST COM When 1 COM2 is used to output post code BMC TAKE COM When 1 BMC request COM2 usage BMC COM When 1 the SIO is connected to BMC When 0 the SIO is connected to output buffer This bit is ignored if BHC TAKE COM 1 BMC RST When 1 BMCis in reset Write 1 to this register to put BMC in reset Reading this bit read the actual signal state which can be held in reset by a jumper BMC PRG When 1 set BMC in program mode COM is redirected to BMC to allow bootstrapping the microcontroller Signal routing follow this table POST COM BMC PRG BMC TAKE
6. IDE1 ACT 1 1 0 IDE1 10CS16 IDE1 A0 A2 B21 D21 A21 IDE1 CSO CS1 D22 B22 1 4 11 Description Reset signal Disk Data These signals are used to transfer data to or from the IDE device Disk DMA Request This signal is directly driven from the IDE device DMARQ signal It is asserted by the IDE device to request a data transfer Disk 1 0 Write In normal IDE mode this is the command to the IDE device that it may latch data from data lines Disk 1 0 Read In normal IDE mode this is the command to the IDE device that it may drive data on SDD lines 1 0 Channel Ready This input signal is negated to extend the host transfer cycle of any host register read write access when the drive is not ready to respond to a data transfer request When not negated it is in a high impedance state DMA Acknowledge This signal directly drives the IDE device DMACK signal It is asserted to indicate to IDE DMA slave devices that a given data transfer cycle is a DMA data transfer cycle Activity indicator IRQ line 1 0 Chip Select Indicates to the host that the 16 bit data port has been addressed and the drive is prepared to send receive a 16 bit data word Disk Address These signals indicates which byte in either the ATA command block or control block is being addressed Chip Select For ATA control register Diagnostic Will be asserted by Drive 1 to indicate to Drive 0 that it
7. 2 9 3 1 IPMI KCS Support in Different OS IPMIis still an emerging standard for system management There are few easy to used tools as of today Linux An open source KCS driver is available for Linux at http openipmi sourceforge net This driver includes all the necessary functionality and more to communicate with the firmware Intel provides some Linux KCS reference drivers they are available at the following address http www intel com desiqn servers ipmi ipmi_driver htm Contact Kontron s technical support for additional tools or help with Linux IPMI tools Windows Intel provides some Windows KCS reference drivers they are available at the following address http www intel com design servers ipmi ipmi driver htm 2 22 CP6010 User s Guide 2 9 3 2 Firmware Update A DOS IPMI tool package is available from Kontron and includes the utility zpmifwu IPMI firmware update This utility allows you to upload a new binary file to the Management Controller Consult the ipmifwu usage display for complete utility options by running ipmifwu h Visit the Kontron Web site for package and firmware availability or call Kontron Technical Support Firmware update procedure 1 BootDOS 2 Place both firmware binary and utility ipmifwu exe on a floppy 3 Insertthe floppy and run the following ipmifwu f firmware bin p r WARNING Some firmware might not be compatible with some BIOS versions Always upgrade the BIOS a
8. A mezzanine card that supports CompactFlash or 2 5 inch hard drives is attached to the system processor If more storage devices or DVD floppy drives are needed 6U form factor storage modules are supported with the XL VHDS system 3U SCSI trays also are supported in VHDS for very high storage capacity and very high MTBF This requires a SCSI PMC Consult you system s manual for available storage device 4 1 4 Power Supply Use of 3U or 6U Compact PCI power supplies is strongly recommended with the CP6010 Although you can use other power supply types make sure they can handle the power requirement current transient and voltage tolerance Use of an ATX power supply is not recommended 3U and 6U CompactPCI power supply modules feature load sharing redundant mode and hot swap capabilities which allow on site replacements of defective modules while the system remains on 4 1 5 Connector Keying CompactPCI connectors support guide lugs to ensure correct polarized mating A proper mating is enhanced by the use of color coded keys for 3 3V and 5V operation Color coded keys prevent inadvertent installation of a 5V peripheral system board in a 3 3V slot The CP6010 is universal in this respect so there is no color key in J1 However always key backplanes in accordance to their VIO settings Note that 5V signaling forces a 33MHz PCI bus mode When operating at 3 3V all PCI frequencies are valid Signaling Voltage Key Color 3 3V Cadmium Ye
9. Function F1 or lt Alt H gt General Help windows See 4 1 2 2 Esc Exit this menu lt gt arrow keys Select a different menu Home or End Move cursor to top or bottom of window lt gt or lt PgDn gt Move cursor to top or bottom of window F5 or lt gt Select the Previous Value for the field F6 or lt gt or Space Select the Next Value for the field F9 Load the Default Configuration values for all menus lt F10 gt Save and exit lt Enter gt Execute Command display possible value for this field or select the submenu To select an item use the arrow keys to move the cursor to the field your want Then use the plus and minus value keys to select a value for that field To save values commands in the Exit Menu save the values currently displayed in all the menus To display a submenu use the arrow keys to move the cursor to the submenu your want Then press lt Enter gt A pointer marks all submenus 5 1 2 2 Field Help Window The help window on the right side of each menu displays the help text for the currently selected field It updates as you move the cursor to each field 5 3 CP6010 User s Guide 5 1 2 3 General Help Windows Pressing F1 or lt Alt H gt on any menu brings up the General Help window that describes the legend keys and their alternates General Help Setup changes system behaviour by modifying the BIOS configuration Selecting incorrect val
10. 3 5 25 Backup Battery IRSE 3 7 25 ee eee 3 7 3 6 Board Hot Swap and Installation 3 8 3 0 CP6010 User s Guide 3 1 1 3 1 Setting Jumpers Jumper Description Description CompactFlash Setting Clear CMOS Test Mode VT 100 Access BMC Reset Serial COM2 Termination On board Video Reserved PMC PCI Maximum speed Backplane PCI On board Battery Configure Compact Flash or 2 5 hard disk in master mode On position 1 2 all CMOS information is cleared This jumper is not set by default This jumper must be installed to force a BIOS Flash update with the hot key sequence Ctrl E 2 is used to output post code Also prevents BMC from generating interrupts Used for Kontron s test environment only When enabled allows VT100 or ANSI terminal connection data serial download from a remote computer Enables or disables the BMC Use these jumpers to connect or disconnect the termination resistors on from Serial COM2 when set RS 422 RS 485 operation mode 0 Use this jumper to disable the on board video feature When installed board will turn on without power from mezzanine This option is used in Kontron s production tests Sets the maximum speed 66 100 133MHz of PCI bus located W13 W14 W15 on the Mezzanine Sets the maximum speed 33 66MHz ofthe PCI bus located W16 W17 W18 on the backplane Connects or disconnects the battery to from board
11. 5 key inserts Push the DIMM in angle right side first into the socket until the left retaining clip snap on Repeat these steps to add other memory sockets To remove a DIMM from a socket push downw the left retaining clip of the socket Pull the module up from the left to remove Note lt gt The right ejector won t move during the operation because of mechanical restrictions due to the mezzanine 3 4 CP6010 User s Guide 3 4 3 4 1 On board Interconnectivity On board Connectors and Headers Description CompactPCI Bus CompactPCI 1 0 CompactPCI I 0 CompactPCI 1 0 CompactPCI I 0 Serial Port A USB2 VGA Ethernet LAN1 Ethernet LAN2 Reset CPU Sockets Memory Sockets Hot Swap POST Code Power Storage Mezzanine PCI Mezzanine Battery Connector J3 34 SCSI 34 PIM 35 36 27 38 29 210 51 213 214 215 218 J20 J21 J22 J23 JN1 JN4 BT1 Comments J1 CPCI bus signals and power J2 64 bit extension arbitration clocks reset and power Serial Ports A and B LAN 0 and 1 PS 2 Keyboard and Mouse VGA and USB SCSI SCSI board version Mezzanine signals PIM board version Legacy connections IDE and Floppy Supports standard 9 pin DSUB male connector faceplate 4 pin USB connector faceplate Supports standard 15 pin DSUB female connector faceplate RJ 45 connector with built in activity and link indicators faceplate RJ 45
12. Ox1AB WRITE NU NU OPEN TXACK NU SCL SDA V1 VO BUSY OPEN TXACK RXACK SCL SDA Version of the I2C engine Currently 0 0 This may be used for future enhancement and to ease software usability from one Kontron product to the other When one the I2C engine is busy When one a transaction is proceeding User must clear this bit to send a STOP condition at the end of a transaction When one send a NACK when reading the next byte If zero send an ACK When one last write ended with a NACK when zero it ends with an ACK Reading reflects the state of the pin Writing may be used to implement bit banging interface Reading reflects the state of the pin Writing may be used to implement bit banging interface C 9 CP6010 User s Guide D Connector Pinouts D 1 CONNECTORS AND HEADERS SUMMARY Connector Description 91 CPCI Bus connector J2 CPCI Bus connector J3 1 0 connector CPCII O connector J5 1 0 connector 96 1 RS 232 Faceplate front panel configuration only J7 USB2 Faceplate front panel configuration only J8 CRT VGA Connector Faceplate front panel configuration only J9 J10 Ethernet LAN2 and LAN1 connectors Front panel configuration only 213 214 CPU Sockets J15 J18 DIMM Sockets J20 Hot Swap switch J21 POST Code J22 Power Connector J23 IDE Mezzanine card JN1 JN4 64Bit PCIX Mezzanine 5 1 Reset Switch BT1 CMOS Battery Backup connector D 1 CP6010 User
13. Y CP6010 User s Guide 60 CompactPCI 64 bit Universal Dual Processor Document Revision 1 2 G kontron Ref 6010 TECH 2 October2006 Customer Service Contact Information Kontron Canada Inc 616 Cur Boivin Boisbriand Qu bec Canada J7G 2A7 Tel 450 437 5682 800 354 4223 Fax 450 437 8053 E mail support 2ca kontron com Visit our site at www kontron com 2006 Kontron an International Corporation rights reserved The information in this user s guide is provided for reference only Kontron does not assume any liability arising out of the application or use of the information or products described herein This user s guide may contain or reference information and products protected by copyrights or patents and does not convey any license under the patent rights of Kontron nor the rights of others Kontron is a registered trademark of Kontron All trademarks registered trademarks and trade names used in this user s guide are the property of their respective owners All rights reserved Printed in Canada This user s guide contains information proprietary to Kontron Customers may reprint and use this user s guide in other publications Customers may alter this user s guide and publish it only after they remove the Kontron name cover and logo Kontron reserves the right to make changes without notice in product or component design as warranted by evolution in user needs or progress in en
14. s Guide 0 2 5 21 Ui BP Ww Q Ui KR W Active Low VCC5E RSV INTA IPMB_PWR RSV REQO AD30 AD26 CBE3 AD21 AD18 VCC3E DEVSEL VCC3E SERR VCC3E AD12 VCC3E AD7 VCC3E AD1 VCCE 12VE VCCE INTB HEALTHY RSV PCI_PRESENT AD29 GND IDSEL GND AD17 FRAME PCIXCAP IPMBO_SCL GND AD15 GND AD9 GND AD4 VCCE REQ64 ROWC RSV RSV INTCH VI O RST VCC3E 4028 VI O AD23 VCC3E AD16 KEY AREA IRDY 0 IPMBO SDA VCC3E AD14 0 AD8 VCC3E AD3 VI O ENUM Long pins 3D 4C 5D 6C 7D 9D 10D 17D 19D 22C 23D 24C Short pins 9B 15D ROW D BD_SEL STOP GND PAR GND AD11 M66EN AD6 VCCE ADO VCC3E TRDY LOCK PERR CBE1 AD13 AD10 CBEO AD5 AD2 ACK64 VCCE CP6010 User s Guide 0 3 5 22 Not Used Active Low ROW B ROW REQ14 SYSEN GNT3 VI O AD61 VI O AD54 VI O 047 VI O 040 VI O 4033 FALH DEGH PRSTH RSV IMPB1_SDA RSV RSV GA2 ROW D GNT1 GNT2 REQ4 GND CBE4 GND AD58 GND AD51 GND AD44 GND AD37 GND REQ5 GND REQ6 GND SMB1_SCL GND RSV GA1 REQ2 REQ3 GNT4 CBE6 PAR64 AD60 AD57 AD53 AD50 AD46 AD43 AD39 AD36 AD32 GNT5 RSV GNT6 RSV SMB_ALERT RSV RSV GAO CP6010 User s Guide 0 4 CPCI Bus 23 1 2 3
15. 1 Product Description Contents 11 Product 1 1 1 2 tle 1 1 13 Board 1 2 16 CompactPCI Cia esee 1 5 1 5 Hot Swap Capability 1 6 1 6 Interfacing with the Environment 1 69 1 7 Compatibility with Kontron Products 1 9 1 0 CP6010 User s Guide 1 1 Product Overview Kontron s CP6010 can accommodate the endless demands for increased bandwidth among mission critical voice messaging Computer Telephony Integration CTI and Internet Intranet server applications This board is a state of the art Dual CPU High Performance Serverworks based CompactPCI 6U 8HP system or peripheral processor It complements Kontron s current family of 6U CompactPCI processor boards offering by addressing the very high performance needs of the data telecommunication and CTI server The CP6010 packs new power onto a single board computer SBC by incorporating two Intel PIV Xeon processors at speeds of 1 6GHz 2 0GHz 2 4GHz and 2 8GHz a front side bus of 400 533MHz and up to 8GB of DDR system memory Its performance is further enhanced by using one 64 bit 133MHz PCI X bus which effectively increase by four the PCI bandwidths over previous products The CP6010 is fully hot swappable and meets all the requirement needed to build high availability CPCI systems In addition the CP6010 can communic
16. Active high When 1 will put line PMC_TRST to OV TMS JTAG TMS TCK JTAG clock TDO TDO of JTAG chain an input for us TDI TDI of JTAG chain an output for us 01A8H I2C ADDRESS FPGA Address Action D7 READ NU 0 1 8 6 Writing to this register sends start condition on the I2C bus and sends the address and R W bit over the wire The user must read RXACK bit from status register to verify the device is responding The user also may read the receive register to make sure no collisions occurred I2C support is not recommended for multimaster environment 01A9H I2C TRANSMIT FPGA Address Action D 0 0 0 7 D6 D5 D4 D3 D2 D1 DO READ NU NU NU NU NU NU NU NU 0 0 0 0 0 Writing to this register sends the data byte The user must read the RXACK bit from status register to verify if the target can receive more data Data can be read back from receive register to make sure no collisions occurred 1 2 RECEIVE FPGA Address Action 04 03 READ 04 03 Ox1AA WRITE A write trigger reception Writing to this register triggers the reading process The user must write the TXACK bit before writing to this register to signal to the target the end of the transfer After the busy bit has fallen the data is ready to be read from this register C 8 CP6010 User s Guide C 19 01ABH I2C FLAGS FPGA Address Action D7 D5 04 03 02 01 00 READ V1 BUSY OPEN TXACK RXACK SCL pin SDA pin
17. BIOS Settings Software Usage Cautions and Warnings The following is an example of each type of advisory Use caution when servicing electrical components Note a PEN e Indicates information that is important for you to know Signal Paths Indicates the places where you can find the signal on the board Related Jumpers Indicates the jumpers that are related to this sections g i BIOS Settings PETS Indicates where you can setthis option in the BIOS fo Software Usage Indicates how you can access this feature through software WARNING Indicates the potential for bodily harm and tells you how to avoid the problem CAUTION A Indicates potential damage to hardware and tells you how to avoid the problem A Disclaimer We have tried to identify all situations that may pose a warning or a caution condition in this user s guide However Kontron does not claim to have covered all situations that might require the use of a Caution or a Warning xiii CP6010 User s Guide Unpacking Follow these recommendations while unpacking Remove all items from the box If any items listed on the purchase order are missing notify Kontron customer service immediately Inspectthe product for damage If there is damage notify Kontron customer service immediately Save the box and packing material for possible future shipment Powering Up the System Before any installation or setup ensure that the board is unplugged f
18. Display CPU type and speed Initialize EISA board Test keyboard Set key click if enabled USB initialization legacy support Enable Keyboard Test for unexpected interrupts Initialize POST display service Display prompt Press DEL to enter SETUP Disable CPU cache Test RAM between 512 and 640 KB Test extended memory Test extended memory address lines Jump to UserPatch1 Configure advanced cache registers Early Initialize of Multi Processor APIC Enable external and CPU caches Setup System Management Mode SMM area Display external L2 cache size Load custom defaults optional Display shadow area message Clear Memory Display error messages Test for configuration error detected Test RTC Check for keyboard errors Set up hardware interrupt vectors Intelligent System Monitoring initialization Initialize coprocessor if present Disable onboard Super 1 0 ports and IRQs for Auto detection Late POST device initialization Detect and install external RS232 ports Configure non Motherboard Configurable Device IDE controllers Detect and install external parallel ports Initialize PC compatible PnP ISA devices CP6010 User s Guide Code Beeps POST Routine Description Re initializes onboard 1 0 ports Configure Motherboard Configurable Devices optional Initialize BIOS Data Area Enable Non Maskable Interrupts NMIs Initialize Extended BIOS Data Area Test and initialize PS 2 mouse Initialize floppy controller
19. For other operating system drivers and installation instructions or for more information visit our Web site at www kontron com or our FTP site at ftp kontron ca support or you may also contact Kontron Technical Support 5 25 CP6010 User s Guide 5 3 Console Redirection VT100 Mode The VT100 operating mode allows remote setup of the board This configuration requires a remote terminal that must be connected to the board through a serial communication link 5 3 1 Requirements The terminal should emulate a VT100 or ANSI terminal Terminal emulation programs such as Telix Procom can also be used 5 3 2 Setup amp Configuration To set up the VT100 mode 1 Connecta monitor and a keyboard to your board and turn on the power Enter the CMOS Setup program in the Advanced page Console Redirection menu Select the VT100 mode and the appropriate COM port and save your setup Connect the communications cable Configure your terminal to communicate using the same parameters as in the CMOS Setup Install the VT100 jumper or use BIOS Setup See section 5 1 2 5 5 Rebootthe board Use the remote keyboard and display to setup the BIOS OY OR W Related Jumpers Install W4 to enable VT 100 access Note a If you do not require a full cable for your terminal you can set up a partial cable by using only the TXD and RXD lines To ignore control lines loop them back as shown in VT100 Partial Setup cable diagram
20. Provide odd parity for data lines Differential Sense Detects the voltage level of a SCSI signal to determine whether it is a single ended or LVD 5V 3 3V Ground Reserved for Kontron internal use 4 9 CP6010 User s Guide 4 2 2 2 PIM Interface Pin Assignment Description PIM1 to PIM 10 A25 025 B25 E25 A24 D24 B24 E24 A22 D22 PIM11 to PIM20 B22 E22 A21 021 B21 E21 A19 019 B19 E19 PIM21 to PIM30 A18 018 B18 E18 A16 D16 B16 E16 A15 015 PIM31 to PIM40 B15 E15 11 011 B11 E11 A10 D10 B10 E10 PIM Interface PIM41 to PIM50 A8 D8 B8 E8 A7 D7 B7 E7 A5 D5 51 to 60 B5 5 4 D4 B4 E4 2 02 B2 E2 PIM61 to PIM64 A1 D1 B1 E1 VCC B23 5V VCC3 E23 3 3V A3 A6 A9 17 A20 B3 B6 B9 B17 B20 C1to C25 D3 D6 D9 017 020 E6 E9 E17 E20 Ero GND 4 2 2 3 Mezzanine Connector 2 4 Pin Assignment Description P14 to P32 1 2 5 6 9 10 13 14 17 18 21 22 25 26 29 30 33 34 37 38 41 42 45 46 49 50 53 54 57 58 61 62 3 4 7 8 1112 15 16 1920723 242728131 32 35 36 39 40 43 44 47 48 51 52 55 56 59 60 63 64 4 10 CP6010 User s Guide 4 2 3 J5 Signal Specification 4 2 3 1 IDE Interface Pin Assignment IDE RESET E15 A18 D18 A17 D17 A16 D16 A15 D15 DEUS B15 E16 B16 E17 B17 E18 B18 E19 IDE1 DMARQ 019 IDE1 10W IDE1 IORH IDE1 IORDY IDE1 DMACK
21. SEL REQ N C D8 D10 ROW B D1 D3 D5 GND D7 TERMPWR7 TERMPWR4 TERMPWR2 GND BSY RST GND SEL REQ KEY AREA D13 D15 GND DO D2 GND D4 D6 GND DPL TERMPWR8 TERMPWR5 ATN GND ACK MSG GND CD 10 09 011 GND DPL TERMPWR9 TERMPWR6 ATN GND ACK MSG GND CP6010 User s Guide 0 7 5 25 00 BP B FP Active Low RSV RSV RSV RSV RSV RSV RSV RSV RSV FD MSENO FD MTRO FD DIR FD TRKO FD DSKCHG IDE1 D6 IDE1 D4 IDE1 D2 IDE1 DO IDE1 IOR IDE1 10CS16 IDE1 A2 IDE1 ACT ROW B RSV RSV RSV RSV RSV RSV RSV RSV RSV FD MSEN1 FD INDEX FD MTR1 FD WGATE FD HDSEL IDE1 D8 IDE1 D10 IDE1 D12 IDE1 D14 IDE1 10W IDE1 IRQ IDE1 A0 IDE1 CS1 ROWC RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV FD FDEDIN FD DSELO FD WDATA FD RDATA IDE1 D7 IDE1 D5 IDE1 D3 IDE1 D1 IDE1 DMARQ IDE1 DMACK IDE1 A1 IDE1 CSOR RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV FD DENSEL FDE DSEL1 FD STEPH FD WRPROT IDE1 RESET IDE1 D9 IDE1 D11 IDE1 D13 IDE1 D15 IDE1 IORDY IDE1 PDIAG RSV CP6010 User s Guide 0 8 SERIAL PORTO RS 232 26 D 9 USB2 LOCATED ON FACEPLATE 27 D 10 CRT VGA INTERFACE J8 Analog GND Analog GND Analog GND D 11 ETHERNET LAN 2
22. 4 5 6 7 8 9 ple mI pd U COM1 RTS COM1 RI COM2 RTS COM2 RI VGA BLUE VGA RED IDO USBO DATA USB1 DATA USB1 VCC RSV RSV LANO ACT LANO LINK LAN1 DB LAN1 DA LANO DB LANO DA VCC COM1 RXD COM1 DTR COM2 RXD COM2 DTR VGA HSYNC VGA GREEN 102 USBO DATA USB1 DATA USBO VCC RSV RSV LAN1 ACT LAN1 LINK LAN1 DB LAN1 DA LANO DB LANO DA VCC COM1 DSR COM1 CTS COM2 DSR COM2 CTS VGA VSYNC VGA SDA ID3 RSV RSV RSV RSV RSV RSV LAN CT GND GND GND GND VCC3 COM1 DCD COM1 TXD COM2 DCD COM2 TXD VGA SCL POST CLK RSV RSV RSV RSV RSV RSV RSV LAN1 DD LAN1 DC LANO DD LANO DC 12V 101 MOUSE CLK MOUSE DATA KB DATA KB CLK POST DATA SPEAKER RSV RSV RSV RSV RSV RSV RSV LAN1 DD LAN1 DC LANO DD LANO DC 12V CP6010 User s Guide 0 5 CPCI Bus 24 ROW 0 HR W N e KEY AREA B m no WU N e n2 ul D 5 CP6010 User s Guide 0 6 CPCI Bus SCSI 24 Eo c gt ro m BS Ui KR WY 012 014 GND 01 GND 03 05 GND 07 DIFFSENS TERMPWR3 TERMPWR1 GND BSY RST GND
23. AND LAN 1 29 210 Yellow A Note These two LEDs might be reversed Green 8 uUi HR UU N e D 12 HorSwaP SwrrcH J20 VCC3E SW SW CLOSER Active Low Signal D 8 CP6010 User s Guide 0 13 PowER 322 0 14 IDE MEZZANINE 323 64 MEZ2 GND CLK66 MEZ 64 MEZ 64 MEZ INT BRDG MEZ INTD_P64MEZZ INTC_P64MEZZ 64 MEZ2 IDEO CS14 IDEO DA2 GND IDEO PDIAG IDEO DA1 GND IDEO IORDY IDEO IOR BD_SEL_MEZZ IDEO DO IDEO D1 VCCUF IDEO D2 IDEO D3 VCCUF IDEO D4 IDEO D5 VCCUF IDEO D6 IDEO D7 VCCUF IDE RESET Active Low IPMBO_SDA IPMBO_SCL GND CLK66_PMC_8HP GND INTB_P64MEZZ INTA_P64MEZZ MEZZ_ENUM IDEO MS SLV IDEO ACT GND IDEO CSO IDEO DAO GND IDEO IRQ IDEO DMACK GND IDEO IOW IDEO DMARQ HEALTHY amp IDEO D15 IDEO D14 VCCUF IDEO D13 IDEO D12 VCCUF IDEO D11 IDEO D10 VCCUF IDEO D9 IDEO D8 VCCUF CP6010 User s Guide 0 15 SwrrcH SW1 D 16 Battery 4 Battery D 17 COMPACTFLASH J3 ON MEZZANINE 518 DMACK DMARQ PDIAG IRQ15 VCC GND RESET CSEL Al AO DO D1 D2 IOCS16
24. COM2 BMC COM Routing SIO to buffers SIO to BMC BMC to buffer SIO to BMC Post code to buffer 115200 baud C 11 0190 PCI STATUS REGISTER CPLD Address Action D7 D6 D5 04 03 02 01 00 READ NU HEALTH 2 SPEED1 SPEEDO JMP2 JMP1 JMPO WRITE NU NU NU NU NU JMP2 JMP1 JMPO Reset U Power up Latch from jumper JMP 2 0 Jumper settings to define the maximum allowable speed SPEED 2 0 Detected bus speed according to PCIXCAP and M66EN PCI signals HEALTH Healthy condition on bridge If 0 the bridge is disabled Description for JMP 2 0 Description for SPEED 2 0 Maximum speed is PCI 33MHz Current speed is PCI 33MHz Maximum speed is PCI 66MHz Current speed is PCI 66MHz Reserved Reserved Reserved Reserved Disable bridge in 1 0 slot Reserved Reserved Reserved Disable bridge Reserved Reserved Reserved C 6 CP6010 User s Guide C 12 01 INTERRUPT NUMBER FPGA Address Action D 7 D6 D5 04 03 02 01 00 READ NU NU NU NU INT X X X X Oh This register holds the interrupt number on which the FPGA CPLD is mapped It is written by the BIOS on boot and read by the software application This is a legacy ISA interrupt so the range is from 0 to 15 Valid values in this register are 5 and 7 7 4 Undefined 3 0 Interrupt number Oh to Fh Other than 5h and 7h are invalid and disable interrupt C 13 01A1H INTERRUPT ENABLE FPGA Address Action D7 D2 D1 DO READ NU SW EN WD EN EN 0 1 1 WRITE NU SW EN WD E
25. It is not electrically safe to hot swap a board in a powered system Basic hot swap The board has the minimum feature set to allow electrically safe insertion in a live system It is up to the system operator to use and configure the board after it is inserted Full hot swap In addition to the basic hot swap feature there are additional provisions for automatic software control over the connection process This gives the broadest range of system capability Boards in this class provide the following signals ENUM BDSEL HEALTHY Full hot swap boards also provide a blue LED and a switch in the lower ejector for interaction with the operator 1 5 2 System Level At this level hot swap capability depends on the boards and on the chassis Type of board Description Non hot swap There is not any hot swap capability in this class of system live insertion of any type of board is unsafe Basic hot swap It is electrically safe to insert a basic or full hot swap board in the chassis However the operator must do the software connection process Full hot swap This adds automatic software connection process to the basic hot swap model A signal ENUM is used to notify the system slot when a peripheral board is newly inserted or when board is about to be extracted High availability This is strictly system dependent A full hot swap board already meets the electrical requirement for a High Availability system but the system itself may fa
26. PMC adapter with front connector Rear 1 0 Connectors 23 24 25 Rear panel transition module 80 2 available separately CRT Serial Ports 2 USB 2 Speaker I F Reset Switch Ethernet 2 PS 2 Mouse amp Keyboard SCSI with PMC EIDE Floppy disk I F PCI Mezzanine Card PMC On board Expansions Proprietary mezzanine CompactFlash Interfaces on 23 24 25 1 3 CP6010 User s Guide Board Specifications BIOS Features Supervisory OS Compatibility Hardware Compatibility Mechanical Power Requirements Phoenix BIOS in Boot Block Flash with recovery code save CMOS in Flash option and boot from LAN capability Auto configuration extended setup and VGA disable by jumper Diskless keyboardless and videoless operation extensions System video and LAN BIOS shadowing Memory remapping to avoid PCI space memory hole Programmable memory wait states DMI amp HDD S M A R T support Advanced Configuration and Power Interface ACPI 1 0 Intelligent System Monitoring advanced thermal management such as resume overheat alarm and auto slow down Setup console redirection to serial port VT100 mode with CMOS setup access Support the Intelligent Platform Management Interface via an on board micro controller Two stage software programmable watchdog timer time out from 16msecto 4 5min Silicon Serial ID TAG for unique board identification accessible via software Hardware system monitor on SM bus
27. Thermal Audio Alarm Hardware Monitor Temperature Hardware Monitor Voltage Inputs Control Temperature Events Control Voltage Events Feature Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled This is a submenu see section 5 1 2 6 1 1 This is a submenu see section 5 1 2 6 1 2 This is a submenu see section 5 1 2 6 1 3 This is a submenu see section 5 1 2 6 1 4 5 1 2 6 1 1 Hardware Monitor Temperature System board Temperature Description Enables Disables the Intelligent System Monitor device When enabled the system will monitor some system states such as temperature and power supplies Enables Disables the generation of interrupts when an event occurs This must be set to DISABLED when programs such as LANDesk are loaded onto the system Produces beep codes when ISM events occur for Voltages events One long beep plus 4 short beeps This alarm may not be supported by the Operating System When the Thermal Management option and this option are enabled a continuous audible alarm is sounded when the temperature specified in the Overheat Alarm options is reached This alarm may not be supported by the operating system Description Current Temperature CPU 1 Die Temperature CPU 2 Die Temperature Current Temperature Hidden if only one processor is present 5 18 CP6010 User s Guide Feature Vcore Sense CPU 1 Vcore Sense CPU 2 Vcore Vcc3 3
28. VHDS 4HP Configuration Tes Bs pm 99 amp ES E E J6 2 USB 1 J9 3 PS 2 MOUSE amp 55 KEYBOARD J7 J8 5 2 8 HP 15 12 000000 SCSI Internal lt 420 Us 1H 2 20 Mezzanine Mounting holes Bracket Mounting holes SCSI External VHDCI 414 415 LAN2 416 LAN1 gt 1 SCSI VHDCI Rev Ell 8HP Configuration Mezzanine Board Top View 9 2 9 J D m 1571 9 DES Wi J5 Floppy 5 3 33nj 9 wom 9 9 9 PS 2 MOUSE COM2 Mezzanine Mounting holes G 3 5 Hard Disk mounting holes CP6010 User s Guide 4 1 3 Storage Devices
29. Watchdog After POST 1 111 e Watchdog Duration FPGAIRQ Software Usage 40 e registers 0x190 and 0x196 description in Appendix C for details e Application Note for watchdog timer usage 2 15 CP6010 User s Guide 2 7 Video Interface The video controller CT69030 with its integrated 4Meg of high performance SDRAM is capable of CRT resolutions up to 1600 x 1200 x 65K colors 4MB RAM The video interface features 64 bit 2D graphics engine 64 bit GUI accelerator engine with multiple window video acceleration Signal Paths um In front 1 0 configuration 28 on the faceplate rear 1 0 configuration J3 CPCI connector Related Jumpers W8 enables or disables the on board VGA feature See Section 3 1 Jumper Settings im BIOS Settings 04104 Section 5 1 2 5 2 Advanced Menu selection PCI Configuration Default Primary Video Adapter Front Plate Configuration VGA interface signals are available on the J8 connector the standard VGA connector located on the faceplate if the board has front access operations This configuration allows direct connection of CRT display to the board CPCI I O Configuration VGA interface signals are available on the 33 CPCI 1 0 connector if the board has rear panel output operations 2 7 1 Supported Resolutions The maximum video resolution and performance depend directly on the drivers running with your software application Resolution and number
30. and monitoring using IPMB interface permits access to sensors regardless of SBC state e Sensor threshold fully configurable e Complete IPMI watchdog functionality e Complete SEL SDR repository and FRU functionality Master Read Write I2C supports for external I2C devices communications FRU EEPROM FAN e Firmware can be updated in the field e Firmware fully customizable per customer needs Interoperable with other IPMI solution 2 9 2 2 Sensors Implemented on CP6010 The IPMI firmware includes many sensors This product implements 37 sensors some for voltage and current monitoring and others for pass fail type signal monitoring Each sensor s description is built in the IPMI firmware and is accessible to the SMS The following signals are implemented on the CP6010 Sensors Precision Description Voltage 5V Voltage 3 3V Voltage 2 5V Voltage 1 5V Voltage 12V Voltage 12V Voltage battery Current Icc 5V Current Icc 3 3V Balance Icc 5V Balance Icc 3 3V Board 5V supply Board 3 3V volts supply On board DC DC converter from 3 3V Mainly used for memory On board DC DC converter from 3 3V Mainly used by chipset and Ethernet controller Board 12V supply 1 Board 12V supply 1 Board RTC battery 1 Total current from baseboard and mezzanine on 5V supply Total current from baseboard and mezzanine on 3 3V supply Difference between baseboard and mezzanine current on 5V supply Difference bet
31. and thumb at each side of the battery and gently pull out the battery 2 Insertanew one firmly in place with respect to the positive and negative location ofthe pins CROSS SECTIONNAL VIEW Negative outer pin 3 6V S Lithium Battery a N Positive es center pin Onboard Battery Connector WARNING There is a danger of explosion if you replace the battery incorrectly Replace the battery with the same or equivalent type recommended by the manufacturer Dispose of used batteries according to the manufacturer s instructions When you receive a board remove the on board battery jumper to enable the battery See Section 3 Jumper settings 3 7 CP6010 User s Guide 3 5 1 Operation and Preventative Maintenance The operational battery voltage must be between 2 9 and 3 6 volts When the board is stored and is kept in it s original package the battery must be replaced when the battery voltage is below 2 9 volts For preventive operational maintenance we recommend to verify the battery voltage after 4 years After that period we recommend that the safety voltage is checked more often The normal battery life expectancy depends on the utilisation of the board e Kontron ordering 100 001 e Tadiran ordering 15 51 86 420 007 TL 5186 3 6 Board Hot Swap and Installation Because ofthe high density pinout of the hard metric connector some precautions must be taken when con
32. circuitry 3 1 CP6010 User s Guide 3 1 2 Setting Jumper amp Locations w4 100 W5 Onboard IPMI n W W7 COM Terminations pin in Without termination out out Onboard Video ww M 3 2 6010 User s Guide 3 2 Processor This product ships with the CPU installed and a thermal solution Because the thermal solution is a custom one and the thermal interface is critical for passive cooling Kontron does not guarantee thermal performance if the heat sink is removed and then reinstalled by the end user If you need to upgrade the CPU contact Kontron s technical support 3 3 Memory Only use validated memory with this product Currently recommended part numbers are Manufacturer Part Number Description Company M312L6420CTO CA200 DIMM ECC RSDRAM 512MB 64M 72 DDR266 1 2 SAMSUNG M312L6420DTO CA200 DIMM ECC RSDRAM 512MB 64M 72 008266 1 2 SAMSUNG UG764D7584KM EZKA DIMM ECC RSDRAM 512MB 64M 72 DDR266 1 2 UNIGEN VM383L6420E A2S DIMM ECC RSDRAM 512MB 64M 72 008266 1 2 VIRTIUM UG7128D7584KV EZKA DIMM ECC RSDRAM 1GB 128M 72 DDR266 1 2 UNIGEN M312L2828DT0 CA200 DIMM ECC RSDRAM 1GB 128M 72 DDR266 1 2 SAMSUNG 31212828 0 200 DIMM ECC RSDRAM 1GB 128M 72 DDR266 1 2 SAMSUNG VM383L2826E A2S DIMM ECC RSDRAM 1GB 128M 72 DDR266 1 2 VIRTIUM M312L3223DTO0 CA200 DIMM ECC RSDRAM 256MB 32M 72 DDR266 1 2 SAMSUNG U
33. connector with built in activity and link indicators faceplate These connectors are Reset Switch faceplate mPGA604 sockets DIMM 184 pin Registered DDR 200 266 SDRAM Hot Swap Switch 4 pin locking not populated 2 pin non locking VCC3 Supports Kontron s module dedicated to CompactFlash disks 64 Bit PCIX Mezzanine CMOS backup battery connector 3 5 CP6010 User s Guide located on faceplate Option Front Plate Connectors and Indicators Blue LED Green LED Description Serial Port A 0582 Reset Button Video Connector LAN1 and LAN2 Ready to Swap HDD Activity Mezzanine Comments Standard 9 pin DSUB male connector 4 pin standard USB connector Use small tool to press the button and proceed to a hardware reset of the board Activity and Standard 15 pin DSUB female connector link indicator Ethernet RJ 45 connectors with built in activity and link indicators or SFF LC optical transceiver Lights when the board is ready to be m swapped Activity and link indicator for LAN1 Indicates an activity on IDE The front plate supports a PMC cutout and a cap that also acts as an EMI shield when there are no PMC devices installed Optical Option 3 6 CP6010 User s Guide 3 5 Backup Battery An on board 3 6V lithium battery is provided to back up BIOS setup values and the real time clock RTC When replacing the battery must be connected as follows 1 Place your index
34. events handling This option enables voltage events handling You can make the following selections on the DMI Event Logging submenu Feature Options Description Event log validity Event log capacity View DMI event log Clear all DMI event logs Enter Yes NO Enabled Disabled Enabled Disabled Event Logging ECC Event Logging Mark DMI events as read valid or Invalid Space Available or Full Report the validity of the DMI Event log buffer in ESCD Flash area Report the space available in the DMI event log If set to Full the event log has no more available space to store DMI events View the contents of the DMI event log Setting this to yes will clear the DMI event log after rebooting Select Enabled to allow logging of DMI events Select Enabled to allow logging of ECC events Press Enter to mark all DMI events in the event log as read 5 20 CP6010 User s Guide 5 1 2 6 3 IPMI System Management You can make the following selections on the IPMI System Management submenu Use the submenus for other selections Feature Options Description IPMI Device and Firmware Information FRU Board Information KCS SMM SMI Sensor Refresh Rate KCS SMS IRQ Dual Port IPMB Redundancy Management Controller Configuration Clear SEL IPMIWatchdog Timer Use BIOS Timer Countdown OS Load Timer Countdown OS Load Timer Action This is a s
35. has passed diagnostics Following a power on reset or software reset Drive 1 will negate PDIAG within 1 msec to indicate to Drive 0 that it is busy CP6010 User s Guide 4 2 3 2 Floppy Disk Interface FD INDEX FD MTRO 1 FD DSEL 0 1 FD DIR FD STEP FD WDATA FD WGATE FD TRKO FD WRPROT FD RDATA FD HDSEL FD DSKCHG FD DENSEL FD MSENO FD MSEN1 FD FDEDIN Pin Assignment B11 A11 B12 012 E12 A12 E13 4 2 3 3 Ground and Reserved Pins Pin Assignment Row C1 C22 A1 A9 1 9 01 010 E1 E10 E22 Description Index Motor 0 1 enable Drive 0 1 select Direction Step pulse Write disk data Write gate Track 0 Write protected Read disk data Head select Disk change Also named DRVDENO Density select Indicate the drive and media selected Automatic media sense Also named DRVDEN1 Used along DENSEL Indicates the drive and media selected Description Ground Reserved for Kontron internal use 4 12 CP6010 User s Guide 5 Software Setup Contents U1 1 PHOENIX BIOS Setup 5 1 Installing Drivers oni 5 25 Console Redirection VT100 Mode 5 26 N 5 0 CP6010 User s Guide 5 1 PHOENIX BIOS Setup Program All relevant information for operating the board and connecting peripherals is stored in the CMOS memory A battery backed up memory holds this information when the board
36. limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generated uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encourage to try to correct the interference by one or more of the following measures e Reorient or relocate the receiving antenna e Increase the separation between the equipment and receiver e Connect the equipment into an outlet on a circuit different from that to which the receiver is connected e Consult the dealer or an experience radio TV technician for help WARNING This is a Class B product If not installed in a properly shielded enclosure and used in accordance with this User s Guide this product may cause radio interference in which case users may need to take additional measures at their own expense Changes or modifications not expressly approved by the party responsible for compliance could void the user s authority to operate this product xv CP6010 User s Guide UL Certification This product bears the combined UL Recognized Component Mark for Canada and U S It indicate
37. of colors specification are listed below Resolution Number of Colors 640x480 800x600 1024x768 1280x1024 1600x1200 256 8 bits 640x480 800x600 1024x768 1280x1024 1600x1200 65 536 16 bits 640x480 800x600 1024x768 1280x1024 16 8 million 24 bits 640x480 800x600 1024x768 16 8 million 32 bits 2 16 CP6010 User s Guide 2 7 2 Major Features Description VGA Compatibility The video controller includes all registers and data paths required for the VGA controller and supports extensions to VGA including resolutions up to 1600 x 1200 x 65K colors non interlaced The 24 bit images are displayed at up to 1280x1024 resolution 2D Graphics Engine The 2D graphics engine is an advanced 32 bit three operand engine that accelerates BitBLTs as line draws polygon draw and polygon fill The 2D graphics engine also performs video and bitmap scaling and data overlay 2 8 CPCI Features 2 8 1 X Universal Bridge PLX6540 This cPCI product s access to the backplane bus runs through the PLX PCI to PCI universal bridge The feature set of this bridge is similar to the HB6 and HB8 which is used on Kontron cPCI products The PLX can operate in either 32 or 64 bits bus width and with any PCI frequency up to 66MHz 2 8 1 1 Transparent Mode When the CP6010 is inserted in the system slot of a backplane the bridge is configured in transparent mode and performs like any other bridge You can configure important registers from
38. remove a card from your chassis please follow carefully these steps Unscrew the top and the bottom screw of the front panel Push the red handle latch until the ejector fall free Using both ejectors disengage the board from the backplane Pull the board out of the chassis 3 6 3 Installing a Card To install a PMC card 1 2 3 Remove the mezzanine from the baseboard Unscrew the four screws that retain the mezzanine to the board Carefully pull out the mezzanine to disengage all connectors To install the PMC on the mezzanine 1 2 Carefully push the PMC to mate the four connectors Screw the four screws at the bottom of the PMC to fix it to the mezzanine To reinstall the mezzanine 1 2 Carefully engage the front plate part of the PMC into the baseboard s face plate opening Push the mezzanine to engage the IDE extension connector which is the more fragile of the connector set Put back the four screws to hold the mezzanine in place 3 9 CP6010 User s Guide 3 6 4 Installing a CompactFlash or Hard Drive This product supports all type I and type II CompactFlash modules WARNING N Never install or remove the compact flash while the board is on To install the CompactFlash 1 Removethe plastic retainer 2 Insertthe CompactFlash in place 3 Reinstall the plastic retainer To remove the CompactFlash 1 Removethe plastic retainer A 2 Pullthe CompactFlash module o
39. s compatibility with the CP6010 J1 and J2 connectors must be compatible with PICMG2 0R3 0 Note J1 and J2 are de facto industry standard as defined by PICMG2 0R3 0 The J3 connectors is user defined Pinouts vary from vendor to vendor Backplanes should be feed through with the lt gt exception of PICMG2 16R1 0 compliant system which routes Ethernet signals into the backplane J4 and J5 are defined by users and vary from vendor to vendor and should be feed through Systems that do not meet this requirement may permanently damage the CP6010 Contact Kontron Technical Support to verify pinout compatibility with other chassis backplanes 4 2 CP6010 User s Guide 4 1 2 Rear Panel 1 0 This feature is intended to issue the 1 0 capabilities of the CP6010 to the rear of the enclosure using a 1 0 80 2 1 0 module gathers all the 1 0 signals of the CPU board and makes them easily accessible through standard headers and connectors located at the rear of enclosure The cTM80 2 transition module is illustrated below Note The CP6010 can detect older RTMs such as the cTM80 2 which forces the CP6010 to remain off This protection only works with older RTMs from Kontron Canada WARNING Always used the right RTM with your front board or permanent damage could occur A Note e For most PICMG2 16 systems XL PSB and XL LP42 you need to use a special RTM The limitation does not apply to the XL
40. same or equivalent type recommended by the manufacturer Dispose of used batteries following manufacturer s instructions ATTENTION Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du m me type ou d un type quivalent recommand par le constructeur Mettre au rebut les batteries usag es conform ment aux instructions du fabriquant ACHTUNG Explosionsgefahr bei falschem Batteriewechsel Verwenden Sie nur die empfohlenen Batterietypen des Herstellers Entsorgen Sie die verbrauchten Batterien laut Gebrauchsanweisung des Herstellers ATENCION Puede explotar si la pila no este bien reemplazada Solo reemplazca la pila con tipas equivalentes segun las instrucciones del manifacturo Vote las pilas usads segun las instrucciones del manifacturo gt gt gt bbb x CP6010 User s Guide Preface Contents How to Use This Guide RH Exp t xii Customer COMMONS xiii Advisory Conventions rebua E xiii us bar DR Powering Up the System atr xiv Adapter au xiv SLOTIBO DOSES ue Cid va cl cue Regulatory Compliance Statements Limitted Warranty xvi xi CP6010 User s Guide How to Use This Guide This user s guide provides step
41. the BIOS setup 2 8 1 2 Nontransparent Mode If the SBC is inserted in a peripheral slot the PLX will be configured in nontransparent mode and Will be seen as an I O device By default it will appear with vendor ID 10B5h and device ID 6540h The PLX will always claim a 16MB window unless the default is changed in the EEPROM settings 2 8 1 3 Busless Operation When used in a busless slot as in some PICMG2 16 systems the bridge will be disabled and will disappear from the PCI device list 2 8 1 4 Using the EEPROM If you use this product as 1 0 board you can assign different vendor ID and device ID to the PLX and can configure the PCI resources that will be claimed at boot up This allows the CP6010 to act as 1 0 board like any other peripheral device SCSI Ethernet and to load proper drivers Please contact Kontron s technical support if you need to configure the EEPROM 2 17 CP6010 User s Guide Related Jumpers adi W15 W16 W18 allow you to set maximum bus speed or disable the bridge ii Bios Settings 0404 Section 5 1 2 5 2 3 Advanced Menu Selection PCI Configuration PCI Performance settings HB8 related options 2 8 2 Hot Swap 2 8 2 1 Power Ramping and Overcurrent Protection This product has electrical components that control current ramp up on the board when the board is hot swapped in the chassis Current transient upon insertion follows the PICMG2 1R2 0 specification The hot swap circuit also protect
42. voltages temperature CPU temperature monitor alarm board temperature sensor power failure low battery detector 12V 12V 5V 3 3V VBAT Vcore 2 5V 1 5V and 1 25V voltage supervisor Current monitoring on 5V and 3 3V through IPMI controller Front Panel LEDs IDE Ethernet activity amp link Microsoft Windows 2000 family Microsoft Windows XP Linux Red Hat 9 0 FreeBSD 4 5 QNX Momentics 6 2 1 MS DOS 6 22 Requires advance server version for more than 4GB memory Supports only 4GB memory Single CPU only limited memory support e Upgrade path for many previous Kontron s boards DXS64 DMXP64GX DMXS64GX e CPCIJ3 J4 and J5 pinouts is the same as the DXS64 but has been changed from previous boards Do not use older Rear Transition Modules RTMs with this board Use only the CTM80 2 RTM or contact technical support for other RTM availability 266 7 x 160x 41 mm 10 5 x 6 3 x 1 6 in 6U x 8HP dual slot Conforms with PICMG2 0R3 0 Supply Voltage 3 3V 5 3 5V 5 3 12V 45 12V 5 ICC typ 5V 12 ICC typ 3 3V 15A ICC typ 12V 260 ICC typ 12V lt 10 using Dual LV Xeon 2 0GHz with 6GB DDR200 running CPU and memory intensive application 1 4 CP6010 User s Guide Board Specifications continued Operating Storage and Transit Temperature 0 559 32 1319 40 to 70 C 40 to 158 F with 1 6 GHz Air Flow TBD Humidity 5 to 95 40 C 104 F 5 to 95 40 C
43. will be remapped above 4GB Memory scrubbing This feature allows the CMIC LE to automatically correct ECC errors and write back the good data into memory without the CPU intervening This is done in hardware ChipKill CMIC LE supports ChipKill memory technology which allows the system to function normally even with one bad DDR SDRAM device This bad DDR SDRAM device must be an X4 device ChipKill memory technology works by reordering the data from the DDR SDRAMs so that if a DDR SDRAM device should fail correctable ECC errors are generated instead of uncorrectable ECC errors With correctable ECC errors the system functions normally without corrupting data 2 4 CP6010 User s Guide 2 3 CSB5 South Bridge 2 3 1 Enhanced IDE Interface The EIDE interface is part of the CSB5 south bridge The interface conforms to the ATA specification and supports ATA100 for 100MB s burst transfers The board features two channel bus master PCI EIDEs that are dedicated to primary and secondary IDE logical interfaces The secondary channel is available only from the RTM Each channel supports up to two IDE devices including CD ROMs hard disks CompactFlash on the primary IDE interface and offers independent timings in master slave combination The IDE interfaces support PIO Mode 4 transfers up to 16 6MB sec and bus master IDE transfers up to 100MB sec ultra DMA 100 Signal Paths The primary IDE interface is only available through the Mezzanine
44. 1 1 IPMI 1 1 and PICMG2 9R1 0 specifications It uses a 16 bits micro controller Hitachi H8 2148 to run an IPMI firmware 2 9 1 Technical Background IPMIis an extensible and open standard that defines autonomous system monitoring It is autonomous because all satellite devices send warnings and critical events to a baseboard management controller BMC that logs it to a system event log SEL This standardized management interface also allows the user s system management software SMS to discover a system s components and to build a database of all present sensors to monitor them and detect critical condition You can find more information about the IPMI at the following Web sites http www intel com design servers ipmi spec htm http www intel com design servers ipmi http www intel com platforms applied eiacomm papers 25133701 pdf 2 9 1 1 IPMI Glossary IPMI Intelligent Platform Management Interface Baseboard Management Controller In a compact PCI chassis there can be only one BMC present The BMC includes de SEL and the SDRR for the complete system The BMC is connected to the other blades in the system via the dual port IPMB interface The board firmware can be set in BMC by selecting the option in the BIOS setup menu In a compact PCI chassis threre can be many satellites Each satellite is connected to the other blades via Satellite the dual port IPMB interface The board firmware can be set in satellite mode by se
45. 104 F Environmental non condensing non condensing Altitude 4 000 m 13 123 ft 15 000 49 212 ft 56 each axis Bellcore GR 63 CORE Section 4 3 Vibration 1 0G 5 500Hz each axis 2 0G 5 50Hz 3 06 50 500Hz each axis MTBF 2110 000 hrs Whole board protected by active breaker Reliabili S USB voltage protected by an active breaker e Mouse keyboard voltage protected by self resetting fuses Designed to meet or exceed Safety EMC e Safety UL 60950 3 Ed CSA C22 2 60950 00 EN 60950 2000 IEC60950 1 EMI EMC FCC 47 CFR Part 15 Class B CE Mark to 55022 55024 Warranty Two year limited warranty 1 4 Compact PCI Compliance This product conforms to the following specifications e PICMG2 0R3 0 core specification e PICMG2 1R2 0 hot swap specification e PICMG2 9R1 0 system management e PICMG2 10R1 0 keying of CPCI boards e PICMG2 16R1 0 packet switching 1 5 CP6010 User s Guide 1 5 Hot Swap Capability The CP6010 supports Full Hot Swap capability as per PICMG2 1R2 0 The T6010 can be removed from or installed in the system while it is on without powering down the system Please refer to the PICMG2 1R2 0 specification for additional details The following paragraphs describe some of the most important features of the hot swap system 1 5 1 Board Level You may encounter these types of boards Type of board Description Non hot swap The board has of the features required for hot swap
46. 11 I0 D22 E22 REQ A22 B22 CD D21 E21 SEL A21 B21 MSG 019 19 RST A19 B19 ACK 018 E18 BSY 18 B18 016 E16 010 10 A4 B4 DIFFSENS E23 A3 A6 A9 A17 A20 B3 B6 B9 B17 B20 C1 to C25 D3 D6 D9 D17 D20 E3 E6 E9 E17 E20 A23 D23 J4 Signal Specification Description SCSI data The SCSI data lines drive the ID during arbitration and selection and command and data information as well as status and messages Termination power In Out Indicates the in direction when asserted and the out direction when not asserted Request A target will assert REQ to indicate a byte is ready or is needed by the target Command Data Indicates Command or message phase when asserted and data phase when not asserted SCSI Select The line is driven after a successful arbitration to select as an initiator or reselect as a target and otherwise it is received SCSI Message Indicates a message phase when asserted and command or data phase when not asserted Reset Signal is interpreted as a hard reset and will clear all commands pending on the SCSI bus Acknowledge Indicates a byte is ready for or was received from the target Busy Handshake signal used during arbitration Attention This line is activated when a special condition occurs SCSIHigh Parity Provide odd parity for data lines SCSILow Parity
47. 2 6 Monitoring Menu Selection You can make the following selections on the Monitoring Menu Use the submenus for other selections Feature Options Description This is a submenu see ystem section 5 1 2 6 1 Monitoring DMI Event This is a submenu see View and modify DMI event logs Logging section 5 1 2 6 2 IPMI System m NOTE the submenu is not available if the BMC reset jumper is ManagementOR 515 submenu see installed W5 The BIOS setup will in that case show Check the BMC Device is section 5 1 2 6 3 1 BMC reset jumper and the IPMI Firmware version update not available Enables the watchdog circuit after the POST sequence Watchdog After Disabled POST Enabled Application software must refresh the watchdog to prevent system reset Watcha 16 seconds A 1 minute Select the duration time of the watchdog timing circuitry 4 minutes Display and Enabled Enable disable Display FPGA Reset History in Summary Screen clear Reset Disabled and Clear FPGA Histo History DNE Disabled Select FPGA IRQ for SWITCH WATCHDOG and ENUM events FPGA IRQ IRQ5 07 If is shown this is already used by KCS SMS IRQ 5 17 CP6010 User s Guide 5 1 2 6 1 Intelligent System Monitoring You can make the following selections on the Intelligent System Monitoring submenu Use the submenus for other selections Feature Intelligent System Monitoring Interrupt Generation Beep codes for non thermal events
48. 3V Vcc 5V Vin 2 5V Vtt Vin 1 5V Vbat Vin 12V Vin 12 Feature Displays a Status and limits 5 1 2 6 1 2 Hardware Monitor Voltage Inputs Description Vcore at CPU 1 Display a Status and limits Hidden if only Vcore at CPU 1 one processor present Display a status and limits 5 1 2 6 1 3 Control Temperature Events Options Description Automatic Thermal Control Circuit CPU 1 Temperature Interrupt CPU 2 Temperature Interrupt Resume Alarm Overheat Alarm Shutdown Alarm Enabled Disabled Enabled Disabled Enabled Disabled 10 C to 70 with step of 4 C 30 C to 90 C with step of 4 C 60 C to 95 C with step of 5 C The Thermal Control Circuit TCC will be activated when the processor s internal thermal sensor determines the processor is about to exceed its maximum operating temperature When the TCC is activated the processors clocks will be modulated typically 30 50 Each processor on dual processor set up has it s own TCC that can modulate the clocks separately This option enables temperature events handling Itis NOT recommended to use this feature while the Automatic Thermal Control Circuit is used This option enables temperature events handling Itis NOT recommended to use this feature while the Automatic Thermal Control Circuit is used Hidden if only one processor is present Full speed Normal mode will be resumed
49. 6010 with HDD Mezzanine 1 11 CP6010 User s Guide 1 7 Compatibility with Kontron Products The CP6010 system processor is a member of Kontron s CompactPCI product family When building a basic environment around the CP6010 the platform can be composed of any of the following devices XL VHDS CP6010 6U system board up to 8 including other Kontron cPCI SBCs CTM80 2 6Ux8HPx80mm RTM for CP6010 Third party CPCI 1 0 board with as needed Storage module with 2 5 inch hard disk and DVD or floppy Up to 12 hot swappable SCSI drives Up to six 3U 250W power supply Up to two Ethernet switches PICMG2 16 Up to two SMC system management cards AC or DC redundant 48 volts power input CP6010 6U system board up to six including other Kontron cPCI SBC CTM80 2 6Ux8HPx80mm Rear Transition Module for CP6010 Third party CPCI 1 0 board with as needed Up to two 6U 300W power supplies Two Ethernet switches PICMG2 16 AC power input CP6010 6U system board up to four including other Kontron cPCI SBCs CTM80 2 6Ux8HPx80mm RTM for CP6010 Third party CPCI 1 0 board with as needed Up to three 3U 250W power supplies Two Ethernet switches PICMG2 16 Up to one system management card AC power input 1 12 CP6010 User s Guide 2 On board Features Contents Ww ID 2 79 ct 79
50. 64AD45 VCC3 P64AD43 P64AD41 GND P64AD39 P64AD37 GND P64AD35 P64AD33 VCC3 N C N C GND Active Low P64C BE7 P64C BES GND P64PAR64 P64AD62 GND P64AD60 P64AD58 GND P64AD56 P64AD54 GND P64AD52 P64AD50 GND P64AD48 P64AD46 GND P64AD44 P64AD42 GND P64AD40 P64AD38 GND P64AD36 P64AD34 GND P64AD32 N C GND N C D 13 CP6010 User s Guide 0 21 2 4 2 4 Active Low D 14 CP6010 User s Guide BIOSSetup Error Codes E 1 POST BEEP Recoverable POST Errors Whenever a recoverable error occurs during POST Phoenix BIOS displays an error message describing the problem Phoenix BIOS also issues a beep code one long tone followed by two short tones during POST if the video configuration fails no card installed or faulty or if an external ROM module does not properly checksum to zero An external ROM module e g VGA can also issue audible errors usually consisting of one long tone followed by a series of short tones E 1 1 Terminal POST Errors There are several POST routines that issue a POST Terminal Error and shut down the system if they fail Before shutting down the system the terminal error handler issues a beep code signifying the test point error writes the error to port 80h attempts to initialize the video and writes the error in the upper left corner of the screen using both mono and color adapters The routine derives the bee
51. 80 Whenever you are not sure about a setting refer to the list of default values The list is provided in the event that a value has been changed and you wish to set this option to its original value Loading the SETUP defaults affects all parameters and will reset options previously altered The Setup Defaults values provide optimum performance settings for all devices and system features Note lt gt CMOS setup option is based on BIOS Version 3 1 The options and default settings can change in a new BIOS release CAUTION A These parameters have been provided to give control over the system However A the values for these options should be changed only if the user has a full understanding of the timing relationships involved 5 2 CP6010 User s Guide 5 1 2 Menu Bar The Menu Bar at the top of the window lists these selections Menu Selection Description Main Use this menu for basic system configuration Advanced Use this menu to set the Advanced Features available on your system Monitoring Use this menu to configure Monitoring features Boot Use this menu to determine the booting device order Exit Use this menu to exit the BIOS Use the left and right lt and gt arrows keys to make a selection 5 1 2 1 Legend Bar Use the keys listed in the legend bar on the bottom to make your selections or exit the current menu The chart on the following page describes the legend keys and their alternates
52. B Voltage Differential power Level for USB 0 and 1 port 4 2 1 5 Keyboard Pin Assignment KB DATA KB CLK 4 2 1 6 Mouse Pin Assignment MOUSE DATA MOUSE CLK 4 2 1 7 Speaker Signal Pin Assignment Description Keyboard Data Keyboard Clock Description Mouse Data Mouse Clock Description SPEAKER E7 Speaker signal 4 7 CP6010 User s Guide 4 2 1 8 05 Pin Assignment Description POST DATA POST data POST CLK POST clock 4 2 1 9 Video Pin Assignment Description VGA HSYNC Horizontal synchronization VGA VSYNC Vertical synchronization VGA SCLK Video serial clock line VGA SDATA Video serial data line VGA RED Analog red video signal VGA GREEN Analog green video signal VGA BLUE Analog blue video signal 4 2 1 10 ID Signal Pin Assignment Description 100 104 A7 E1 B7 C7 07 4 2 1 11 Power Pin Assignment Description A19 B19 5V Supply voltage C19 3 3 Supply voltage D19 12V Supply voltage E19 12V Supply voltage C15 C18 Ground 4 2 1 12 ID Pin Assignment Description A11 A12 B11 B12 Reserved for Kontron internal use C8 C13 08 014 E8 E14 4 8 CP6010 User s Guide 4 2 2 4 2 2 1 SCSI Interface Pin Assignment 04 5 05 A7 D7 8 08 A10 DUIS A24 D24 D22 D25 A1 D1 A2 D2 E4 B5 E5 B7 E7 B8 EB B10 B24 E24 825 E25 B1 E1 B2 E2 TERMPWRI to TERMPWRO A16 B16 A15 B15 D15 E15 B11 D11 E
53. BC Only use Kontron s RTM with the CP6010 cTM 80 is compatible with the RTM RTMs are not designed to be hot swapped when a front board is present Make sure that either the system is shut off or that the front board of the RTM is unpowered before removing or installing a RTM Note A In front 1 0 configurations the following 1 0 signals are available on the faceplate SVGA Serial Port COM1 USB Port 2 Ethernet 1 and 2 other I Os connect to J3 and J5 B Rear I 0 configurations all 1 0 signals connect to 33 J4 and J5 1 9 CP6010 User s Guide 1 6 3 mezzanine is a hardware interface used to increase 1 0 connectivity of the CP6010 while respecting the dual slot 6U form factor restrictions It is built around three sets of connectors e Mezzanine connector handling IDE signals additional PCI slots and arbitration signals 5V power e Mezzanine connector the four baseboard connector that handles a complete PCI signal set including the REQ GNT arbitration signal pair e A two pin power connector to bring additional 3 3V on the baseboard These connectors represent an open door for future development of expansion and 1 0 mezzanine cards The following 1 0 5 are available on the T6507 mezzanine PMCconnector supporting PCIX up to 133MHz 64 bits with interface Note lt gt If you encounter problem with the GB Ethernet LAN adapter s
54. C is a bit banging interface Use of register 1A8h to 1ABh is recommended as the new interface to onboard I2C memory Address Action NU IDCHIP NU SCL pin SDA pin 0x193 NU IDCHIP SCL IDCHIP ID Chip serial number control Open drain output with pin readback 2 SCL I2C clock Totem pole output 2 SDA 2 data Open drain output with pin readback C 4 CP6010 User s Guide C 7 C 8 C 9 0196 WATCHDOG CONTROL FPGA This is a Kontron SBC standard dual stage watchdog However the second stage time increases from 1ms to 16ms to ease the interrupt handling when using ISA interrupt So either a NMI or a legacy interrupt will generate after the specified timeout Then the watchdog must be triggered either by writing the WDD 2 0 bits or by clearing the interrupt bit in the 1A2h register Failure to trigger the watchdog within 16ms will reset the system If interrupts are disabled the watchdog reverts to a single stage one Address Action D7 D6 D5 04 READ WDEN WDD2 WDD1 WDDO 0x196 WRITE WDEN WDD2 WDD1 WDDO WDEN Enable Lockable with bit LOCK WDD 2 0 Timeout selection A write to this register triggers the watchdog Timeout as follow 000 0 016s 001 0 065s 010 0 262s 011 1 048s 100 4 194s 101 16 78s 110 67 11s 111 268 4s 0197 NMI ENABLES AND SOURCES FPGA Address Action READ BATFEN BATFLT FANFEN FANFLT SWNMIEN SWNMI WDNMIEN WDNMI 0x197 WRITE BATFEN NU FANFEN NU SWNMIEN NU WDNMIEN NU
55. CK NU 0x1A8 NU 0x1A8 address 0x19C NU NU POST_COM BMC COM BMC RST BMC PRG C 2 CP6010 User s Guide FPGA CPLD registers continued Address 0 1 9 Write Data 0 1 9 NU Read data Ox1AA Write trigger read cycle Ox1AB BUSY OPEN TXACK RXACK SCL pin SDA pin Ox1AB NU OPEN TXACK NU SCL C 3 0190H COM2 RS232 422 485 BUFFER CONTROL FPGA Address Action READ RS485 RS232 0x190 WRITE RS485 RS232 RS485 RS232 Description RS232 mode default RS485 422 point to point mode RX is always enable TX enabled when COM2 RTS is asserted RS485 party line mode RX enabled when 2 RTS is deasserted TX enabled when COM2 RTS is asserted Illegal This puts the buffers in RS232 mode Illegal This puts the buffers in RS232 mode C 4 0191 RESET HISTORY FPGA About debug LED The idea is that the LED will light red when in reset This is hardware As soon as the FPGA is programmed the LED lights yellow if in reset and the FPGA is enabled for post code display see below If the BIOS fails it is possible to read the last post code If the BIOS succeeds it will disable the post code and enable HD activity on the green LED When neither post code or the hard disk LED is enabled software can control LED state with Bit 1 and 2 If both the post code and hard drive activity are enabled the LED control is given to BMC on rev 1 only How to read the 8 bit post code e Yellow start of post s
56. Continued Primary Slave Secondary Master Secondary Slave POST Errors System Memory Extended Memory Options Description IDE Removable Same choices as CD ROM Other ATAPI Same choices as CD ROM USER Same as Primary Master Same as Primary Master Enabled Disabled N A N A Cylinders Heads Sectors Maximum Capacity Multi Sector Transfers LBA mode Control 32 BitI O Transfer Mode Ultra DMA Mode Cylinders Setthe number of cylinders Heads Setthe number of heads Choices are 1to 16 Sectors Setthe number of sectors per track Maximum Capacity Maximum capacity is displayed according to the cylinders heads and sectors selected Multi Sector Transfers Choices are Disabled 2 4 8 and 16 sectors Specify the number of sectors per block for multiple sector transfers MAX refers to the size the disk returns when queried LBA Mode Control Choices are Enabled Disabled Enabling LBA cause Logical Block Addressing to be used in place of Cylinders Heads and Sectors 32 BitI O Choices are Enabled Disabled This setting enables or disables 32 bit IDE data transfers Transfer Mode Choices are Standard Fast PIO 1 Fast PIO 2 Fast PIO 3 Fast PIO 4 FPIO 3 DMA 1 FPIO 4 DMA2 Select the method for moving data to from the drive Autotype the drive to select the optimum transfer mode Ultra DMA Mode Choices are Disabled Mode 0 to 5 Select the Ultra DMA mode used fo
57. DE channel Configure the CompactFlash as master with W1 removed 3 Never install or remove the CompactFlash on a powered board 2 3 1 2 Hard drive Interface on Mezzanine You can order this product with a 2 5 inch hard drive on the mezzanine With this option there is no CompactFlash and PMC bus support This option is useful when many gigabytes of storage are needed but performance and MTBF requirement are not high The 2 5 inch hard disk is meant for portable computers and is not designed for server type workload This option also limits the airflow in the CPU area lowering the maximum ambient operating temperature 2 6 CP6010 User s Guide 64 bit PCI Mezzanine ry 9c 1 ERI nEE K 03 58 esse HE lessee 9 EDCBA Related Jumpers Install W1 when using the hard drive Note When using the hard disk the maximum ambient operating temperature depends on the system s airflow Signal Paths The IDE port is available through IDEO channel 0 2 7 CP6010 User s Guide 2 3 2 USB Interfaces USB strengths include e Capability to daisy chain as many as 127 devices per interface e Fast bi directional Isochronous asynchronous interface e 12MBPS transfer rate e Standardization of peripheral interfaces into a sin
58. Determine number of ATA drives optional Initialize hard disk controllers auto detect IDE drives Initialize local bus hard disk controllers Jump to UserPatch2 Build MPTABLE for multi processor boards Install CD ROM for boot Clear huge ES segment register Fixup Multi Processor table Search for option ROMs One long two short beeps on checksum failure Check for SMART Drive optional Set up Power Management Initialize security engine optional Enable hardware interrupts Determine number of ATA and SCSI drives optional Set time of day Initialize Typematic rate Erase DEL prompt Scan for DEL key stroke Enter SETUP Clear Boot flag Check for errors POST done prepare to boot operating system One short beep before boot Terminate QuietBoot optional Check password optional ACPI initialization Prepare Boot Initialize DMI parameters Clear parity checkers Display MultiBoot menu Clear screen optional Display Summary Screen Try to boot with INT 19 Initialize POST Error Manager PEM E 4 CP6010 User s Guide Code Beeps POST Routine Description Save the current boot type into CMOS Initialize error logging Check the requested boot type Cold or Warm Initialize error display function Initialize system error handler Install the IRQ1 vector for BIOS Hot Keys PnP NoteDock dual CMOS optional Mark the fact that we are no longer in POST Console Redirection SIO Initialize Remove Console Redirection Force Eme
59. Enabled Disabled Description Select Enabled to allow logging of Processor Data Bus Error events Select Enabled to allow logging of Processor Address Bus Error events Select Enabled to allow logging of Processor Bus Protocol Error events Select Enabled to allow logging of BINIT Sampled Asserted events Select Enabled to allow logging of Received Master Abort on PCI Bus events Select Enabled to allow logging of Address Parity Error PAR incorrect with received data and C BE lines on PCI Master Transaction events Select Enabled to allow logging of Received Data Parity Error PAR incorrect with received data from PCI target device as a result of IMB Bus to PCI Read events Select Enabled to allow logging of Transmitted Data Parity Error PERR asserted by PCI target device during IMB Bus to PCI write access events Select Enabled to allow logging of Received Target Abort on PCI Bus events Select Enabled to allow logging of IMB Parity CRC Error events Select Enabled to allow logging of IMB Training Logic Failure to train the link events Select Enabled to allow logging of CIOB being the Target of Split Completion Message with SCE bit set events Select Enabled to allow logging of CIOB being the Target of an unexpected Split Completion events Select Enabled to allow logging of CIOB Initiating Split Completion Message with SCE bit set events CIOB generates a SCM cycle when it de
60. G732D7588KZ DZKA DIMM ECC RSDRAM 256MB 32M 72 008266 1 2 UNIGEN M312L3223DT0 CBO DIMM ECC RSDRAM 256MB 32M 72 DDR266 1 2 SAMSUNG VM383L3223E BOS DIMM ECC RSDRAM 256MB 32M 72 DDR266 1 2 VIRTIUM 31213223 0 200 DIMM ECC RSDRAM 256MB 32 72 008266 1 2 SAMSUNG UG7256D7504MQ EZKA DIMM ECC RSDRAM 2GB 256M 72 DDR266 1 2 UNIGEN VM383L5626E A2S DIMM ECC RSDRAM 2GB 256M 72 DDR266 1 2 VIRTIUM 31215628 0 200 DIMM RSDRAM 2GB 256M 72 DDR266 1 2 SAMSUNG Memory should have the following characteristics DDR200 or DDR266 2 5Vonly e Single sided or double sided X4 or X8 configuration supported e Serial Presence Detect SPD EEPROM e 64 bit and 72 bit DIMMs supported e 1 2 inch maximum height 3 3 CP6010 User s Guide WARNING Because static electricity can cause damage to electronic devices take the following precautions e Keep the board in its anti static package until you are ready to install memory e Wear a grounding wrist strap before removing the board from its package this will discharge any static electricity that may have built up in your body Handle the board by the faceplate or its edges 3 3 1 Installing Memory On an anti static plane place the board so that you face the DIMM sockets and the faceplate is facing you Insert the DIMM into J17 and J18 then in J15 and J16 The memory must be installed in pairs To install a DIMM align the notche on the module with the
61. LTHY signal indicates the healthiness of the board 1 8 CP6010 User s Guide 1 5 5 1 Bus less Operation When the on board bridge is disabled the CP6010 is considered bus less In such cases the SBC can be hot swapped in CPCI bus but will not try to participate on the bus Then BDSEL and HEALTHY preserve their functionality but PCIRST is ignored The blue LED mechanism is disabled because the on board bridge and system host cannot handle it However it is possible to read the handle switch and control the blue LED through register 0x192 Note S When the bridge is disabled stand alone operation the user can read the hot swap switch and drive blue LED by using register 0x192 1 6 Interfacing with the Environment 1 6 1 CPCI The CP6010 system peripheral processor board is provided for rack mounted systems to offer the highest modularity Through the J1 J2 segment the board can drive up to seven external CompactPCI slots supporting individual REQ GNT arbitration pair signals and the clock The CP6010 supports all PCI modes for operation up to 66MHz giving a theoretical throughput of 512MB s Possible PCI modes of the CP6010 with Kontron systems XL VHDS 1 XL PSB XL CXP XL LP42 CP6010 PCI 33 PCI 33 PCI 33 PCI 33 PCI 66 PCI 66 1 Using a five slot backplane 1 6 2 RTM I Os can be accessed through a rear transition module RTM RTMs use proprietary pinouts in 93 34 35 to bring out all 1 05 of the S
62. N I2C EN Enable I2C interrupt on falling edge of BUSY bit 1ABh SW EN Enable interrupt on switch event WD EN Enable watchdog interrupt ENUM EN Enable ENUM interrupt The interrupt is generated for both onboard CPCI interface and the mezzanine CPCI interface If more than one software driver access this register take care to race condition Atomic modify write may be needed C 14 01A2H PCI INTERRUPT STATUS FPGA Address Action D7 D3 D2 D1 DO READ NU NU SWITCH WDOG ENUM Ox1A2 WRITE NU NU SWITCH WDOG NU I2C A one indicates the BUSY bit has transition from 1 to 0 thus the I2C engine is ready for new data Write a one to clear this interrupt SWITCH A one indicates a switch event has occurred Switch state can be read on 0191h bit 5 Write a one to this bit clear the interrupt WDOG A one indicates a watchdog interrupt has occurred Writing a one to this bit clears the watchdog and clears the interrupt Reset will occur 16ms after the interrupt ENUM A one indicates an ENUM has occurred on either the onboard CPCI interface or the mezzanine interface Writing a one to this register does nothing The interrupt condition must be cleared in the source PCI device C 7 CP6010 User s Guide C 15 C 16 C 17 C 18 01 JTAG FPGA Address Action D7 D5 D3 READ NU JEN TMS 0 1 WRITE NU JEN TMS JEN JTAG enable All JTAG signals are 3 state when this bit is 0 TRST JTAG TRST
63. P6010 User s Guide C 2 OVERVIEW FPGA CPLD registers 0x190 RS485 RS232 51 NU NU 0x190 5485 RS232 51 NU NU 0x191 ENPOST ACT RED GREEN PFO 0x191 NU ENPOST ACT RED GREEN NU 0x192 NU NU LOCK NU CLRHIS 0x192 NU NU NU LOCK NU CLRHIS 0x193 NU NU NU NU IDCHIP NU 120 I2C DATA 0x193 NU NU NU NU IDCHIP NU 120 I2C DATA 0x194 CND3 CIS3 1 530 CBAS3 1 53 0 NU NU NU 0x194 CND3 153 1 530 CBAS3 1 53 0 NU NU NU 0x195 04 154 1 540 CBAS4 1 54 0 NU NU NU 0x195 04 154 1 540 541 54 0 NU NU NU 0x196 WDEN WDD2 WDD1 WDDO NU NU NU NU 0x196 WDEN WDD2 WDD1 WDDO NU NU NU NU 0x197 BATFEN BATFLT FANFEN FANFLT SWNIMEN SWNMI WODNMIEN 0x197 BATFEN NU FENFEN NU SWNMIEN NU WDNMIEN NU 0x198 NU NU NU NU NU NU NU NU 0x198 NU NU NU NU NU NU NU NU 0x199 NU NU NU NU NU NU NU NU 0x199 NU NU NU NU NU NU NU NU 0x19A NU NU NU NU NU NU NU NU 0x19A NU NU NU NU NU NU NU NU 0x19B GA4 GA3 GA2 GA1 GAO 0x19B NU NU NU NU NU NU NU NU BMC_TAKE _COM 0x19C NU NU POST_COM NU BMC_COM BMC_RST BMC_PRG 0x19D HEALTHY SPEED2 SPEED1 SPEEDO JMP2 JMP1 JMPO 0x19D NU RSV RSV RSV RSV RSV RSV 0 19 NU NU NU NU NU NU NU Ox19E NU NU NU NU NU NU NU Ox19F NU NU NU NU NU NU NU Ox19F NU NU NU NU NU NU NU 0x1A0 0 0 0 Interrupt number 0x1A0 NU NU NU Interrupt number 0 1 1 NU SW EN WD EN EN 0 1 1 NU SW EN WD EN EN 0x1A2 NU NU SWITCH WDOG ENUM 0x1A2 NU NU SWITCH WDOG 0x1A3 NU TRST TCK TDO 0x1A3 NU TRST T
64. S initiated by CMIC LE for every assertion of signal By having higher values of Clumping the I O devices are given higher priority on processor bus over processors Determines the Maximum Number of Pages opened by the Memory Controller Device Minimum Active to Precharge Time tRAS SPD byte 30 Auto will set tRAS to 5 Clocks if supported by all DIMMs present at the current DDR Bus speed Device Minimum RAS to CAS delay tRCD SPD byte 29 Auto will set tRCD to 2 Clocks if supported by all DIMMs present at the current DDR bus speed Device Minimum Row Precharge Time tRP SPD byte 27 Auto will set tRP to two clocks if supported by all DIMMs present at the current DDR bus speed DRAM RAS Cycle Time tRAS Auto will set six clocks if supported by all DIMMs present at the current DDR bus speed DRAM RAS Cycle Time after Refresh tRFC tRAS tRP 1 Auto will set 8 Clocks if supported by all DIMMs present at the current DDR bus speed 5 12 CP6010 User s Guide Feature Memory Read Byte Count Memory Read Byte Count Stray Read to Stream IMB Transmit Arbiter Slots Buffer Manager Dual Request 5 1 2 5 4 2 CIOB Settings You can make the following selections on the CIOB Settings submenu 512 1K 2K or Bytes 512 1K 2K or Bytes Enabled Disabled 10 2 Enabled Disabled 5 1 2 5 4 3 Error Command Settings Description Sets the maximum byte coun
65. Save the setup exit and disconnect the remote computer from the board to operate in stand alone configuration Console Redirection is done by refreshing the video address 2 B8000h at the selected baud rate This means that a low baud rate refreshes the screen slowly but the CPU time is maximized for applications A high baud rate refreshes the screen rapidly but the CPU is frequently interrupted by the serial port 5 26 CP6010 User s Guide Console Redirection provided by Phoenix based BIOS offers escape sequences to emulate keyboard function keys The following table lists the escape sequences Function Function Escape sequence Escape sequence Esc Del Warm Reset Esc 64 Ctrl F1 Esc O P F1 Esc 657 Ctrl F2 EscO Q F2 Esc 66 Ctrl F3 EscOR F3 Esc 67 Ctrl F4 EscO S F4 Esc 68 7 Ctrl F5 Esc 0 Esc 69 Ctrl F6 EscOx F4 Esc 70 7 Ctrl F7 EscOt F5 Esc 717 Ctrl F8 EscOu F6 Esc 72 7 Ctrl F9 EscOq F7 Esc 73 Ctrl F10 EscOr F8 Esc 74 7 Ctrl F11 Ctrl F12 EscO p F10 Esc 75 Running without a Terminal The board can boot up without a screen or terminal attached If the speed is set to Auto and no terminal is connected the speed is set to 115 200 bauds You can run the board without a console by not enabling VT100 mode and by disabling the on board video Full Setup Partial Setup COM COM Connector Connector TXD gt RxD RXD
66. T ID Speaker and USB CPCI J2 Connector 64 bit extension arbitration clocks reset and power CPCI Ji Connector Supports CPCI bus signals and power 4 5 CP6010 User s Guide 4 2 CPCI I O Signals 4 2 1 Signal Specification 4 2 1 1 Ethernet Pin Assignment Description LANO 1 ACT A13 B13 Transmit receive activity LED signal LANO 1 LINK A14 B14 Link integrity LED signal LAN CT LAN1 DA LANO DA LAN1 DA LANO DB LAN1 DB LANO DB LAN1 DB LANO DC LAN1 DC LANO DC LAN1 DC LANO DD LAN1 DD LANO DD LAN1 DD Ethernet differential signals 4 2 1 2 Serial Port 0 COM1 Signal Pin Assignment Description COM1 DCD D1 Data Carrier Detect COM1 RXD B1 Receive Data COM1 DSR C1 Data Set Ready COM1 TXD D2 Transmit Data COM1 RTS Al Ready To Send COM1 CTS C2 Clear To Send COM1 RI A2 Ring Indicator COM1 DTR B2 Data Terminal Ready 4 6 CP6010 User s Guide 4 2 1 3 Serial Port 1 0 2 Pin Assignment COM2 DCD COM2 RXD COM2 DSR COM2 TXD COM2 RTS COM2 CTS COM2 RI COM2 DTR 4 2 1 4 USBO USB1 Pin Assignment USBO DATA DATA B8 A8 USB1 DATA DATA B9 9 USBO 1 VCC B10 A10 Description Data Carrier Detect Receive Data Data Set Ready Transmit Data Ready To Send Clear To Send Ring Indicator Data Terminal Ready Description USB Data Differential data path for USB 0 port USB Data Differential data path for USB 1 port US
67. TUP items Save Changes Save Setup Data to CMOS 5 1 2 8 Boot Utilities Phoenix Boot Utilities are e Phoenix QuietBoot e Phoenix MultiBoot Phoenix QuietBoot displays a graphic illustration rather than the traditional POST messages while keeping you informed of diagnostic problems Phoenix MultiBoot is a boot screen that displays a selection of boot devices from which you can boot your operating system 5 23 CP6010 User s Guide 5 1 2 9 Phoenix Quiet Boot Right after you turn on or reset the computer Phoenix QuietBoot displays the QuietBoot Screen a graphic illustration created by the computer manufacturer instead of the text based POST screen which displays a number of PC diagnostic messages To exit the QuietBoot screen and run Setup display the Multiboot menu or simply display the PC diagnostic messages you can simply press one ofthe hot keys described below The QuietBoot Screen stays up until just before the operating system loads unless e You press lt ESC gt to display the POST screen e You press Del to enter Setup e POST issues an error message e The BIOS or an option ROM requests keyboard input The following explains each of these situations 5 1 2 10 Press lt 5 gt Pressing lt 5 gt switches the POST screen The boot process continues with the text based POST screen until the end of POST and then displays the BootFirst Menu with these options e Load the operating system f
68. abled Description Enables Disables On board Ethernet Controller on Bus 01 Device 04 Functions 0 amp 1 Initialize device expansion ROM 5 9 CP6010 User s Guide Option ROM Enable Master Latency Timer Feature PCI Cache Line Size On board PCI PCI Bridge settings Force 64 bit Control Smart Prefetch Mechanism Smart Prefetch Timeout Prefetching scheme PCI Primary Initial Prefetch count PCI Sec Initial Prefetch count 5 1 2 5 2 2 Mezzanine PMC Expansion Slot Enabled Disabled Enabled Disabled Default 0020h 0040h 0060h 0080h 00COh or OOEOh 5 1 2 5 2 3 PCI Performance Settings 0 1 2 4 8or 16 DWORDS Disabled Both Secondary Primary Enabled Disabled 32 64 128 or 256 PCICLK EEPROM Aggressive Normal Manual PCICLS 2 4 8 or 16 Dwords 8 16 or 32 Dwords Description Initialize device expansion ROM Enable selected device as a PCI bus master Minimum guaranteed time slice allotted for bus master in units of PCI bus clocks Description Setthe Cache Line Size in DWORDS Sets the Cache Line Size Register in the Configuration Space of PCI devices Following options control the behaviour of the On board PCI X bridge The Bridge has an EEPROM to initialize the registers If it s content is valid the options will be shown in grey and are not available for change 32 bit Prefetchable read
69. annels BMC the board is the central management controller Satellite the Board is a Satellite Management Controller under the control of an external central Management Controller The BMC manages the interface between system management and the platform management hardware Select YES if you want to clear all contents of the IPMI System Event Log on next boot only Indicates the current use assigned to the Watchdog Timer BIOS POST Watchdog Timer used by the BIOS POST OS Load OS Load Timeout This mode requires SMS or OS support Initial BIOS Timer Countdown Value Initial OS Load Timer Countdown Value Initial OS Load timeout action None no action Hard Reset Power Down Power cycle 5 21 CP6010 User s Guide 5 1 2 6 3 1 IPMI Device and Firmware Information Feature Static information Description Kontron board identifier Product ID om Provide a numeric value that identifies a particular System or board type IPMI specification version IPMI Version This field holds the version of the IPMI specification that the controller is compatible with Subject to change IPMI implementation ID used with this product ID Device ID Es Provide numeric value that identifies a particular controller type Firmware IPMIfirmware revision Revision Subject to change Sensor Data Records package revision DR Revisi 3 id Subjectto change 5 1 2 6 3 2 FRU Board Informati
70. ate at 4Gb s over two full duplex gigabit Ethernet links with other processor boards using a CompactPCI 2 16 backplane XL PSB VHDS Platform for high density and high reliability clustering applications The CP6010 offers a natural growth path to high performance high availability as well as hot swappable and scalable multiprocessing technology 1 2 What s Included This board is shipped with the following items e 010 board e One quick reference sheet e Cables that have been ordered If any item is missing or damaged contact the supplier 1 1 CP6010 User s Guide 1 3 Board Specifications Dual Intel Low Voltage Processor at 400 533MHz front side bus FSB Supported Microprocessors Supports Hyper Threading NetBurst Architecture 512K L2 on die cache 12KB 8KB Instruction Data Level 1 ServerWorks GC LE server chipset with CSB5 South Bridge Chipset ServerWorks CIOB X2 for dual PCI X 133MHz interface National PC87417 super 1 0 Front side bus at 400 533 MHz 64 bit data 36 bit address Memory bus at 200 266 MHz 144 bit data 2 channel One on board 64 bit 133MHz PCI X bus One on board 64 bit 66MHz PCI bus CPCI PCI 64 bit 66MHz with universal bridge One on board 32 bit 33MHz bus for video interface Up to 8GB on 4 x 184 pin latching DIMM sockets 64 72 bit Two DDR channels 72 bit 133MHz for Interleave operation PC 1600 PC 2100 DDR registered SDRAM non ECC ECC mode ECC error correction up to a nib
71. ble IRQ 15 Secondary IDE or available All functions marked with an asterisk can be disabled or reconfigured 1 Available lines service on board and external PCI ISA PnP devices or a Legacy ISA device B 2 PCISERIAL INTERRUPTS Signal PCIIRO System slot Peripheral slot S64_INTA cPCI backplane 564 cPCI backplane S64 cPCI backplane S64 INTDi cPCI backplane LAN_INTA Dual 1000Base T chip LAN_INTB Dual 1000Base T chip MEZ_INTA Mezzanine MEZ_INTB Mezzanine MEZ_INTC Mezzanine MEZ_INTD Mezzanine PMC_INTA PMC PMC_INTB PMC PMC_INTC PMC PMC_INTD PMC VGA_INT Video chip int BRGP_INT cPCI bridge primary side int MBRG_INT Mezzanine bridge interrupt 0 1 2 3 4 5 6 7 8 9 6 not used not used B 1 CP6010 User s Guide C Kontron Extension Registers 1 FPGA CPLD REGISTERS DEFINITION Unused shaded bits are reserved is strongly recommended not to modify unused bit to insure compatibility with other product The base address is fixed Bits marked NU are not used on this board Writing to such bit does nothing and reading is undefined either 0 or 1 may be returned Bits with name in green and italics are for reference only they are used on other Kontron CPCI SBC but not on this board Legend Symbol Signification Unchanged stay unchanged after reset Not Defined bit not used on this board Not Used C 1 C
72. ble error detection for more than a nibble all eight GB cacheable 512 for BIOS field upgrade on X BUS 32KB user serial EEPROM Cache Memory Bus Interface System Memory Flash Memory 1 2 CP6010 User s Guide Board Specifications continued Description Front Plate Rear 1 0 Mezzanine Video F R USB Serial PS 2 Mouse PS 2 Keyboard Ethernet F R Hard Disk SCSI optional Compact Flash Floppy Reset Button e N e n N N Front or Rear PCI video controller C amp T 69030 with 4MB video memory Supports CRT with resolution up to 1600 x 1200 65K colors On faceplate female D sub 15 pin USB USB 1 1 compliant Serial COM1 RS232 2 configurable as RS 232 RS 422 485 Ethernet PCI 10Base T 100Base T 1000Base T or 1000Base SX using Intel 82546 On faceplate two RJ 45 for copper with link activity indicators or optical transceiver On rear access PICMG 2 16 compliant copper interface Hard Disk PCI EIDE Ultra DMA 100 Mezzanine Channel 0 Rear I 0 Channel 1 SCSI Dual Channel Ultra 160 320 SCSI using PMC CompactFlash Can be installed on EIDE channel 0 through a connector on the mezzanine exclusive with 2 5 inch drive Clock Calendar e Real time clock with 256 byte battery backup CMOS RAM Front Plate CRT 15 pin D Sub Connectors in Front COM1 9 pin D Sub configuration Ethernet 1 and 2 2 x RJ 45 or 2 x SFF LC optical transceiver 05 2 1 4 USB female Optional SCSI
73. by step instructions for installation and serves as a reference for operation troubleshooting and upgrades You can find the latest release of this User s Guide at ftp ftp kontron ca support For the circuits descriptions and tables indicated Kontron assumes no responsibility as far as patents or other rights of third parties are concerned The following is a summary of chapter contents Chapter 1 Product Description Chapter 2 On board Features Chapter 3 Installing the board Chapter 4 Building a CPCI System Chapter 5 Software Setup Appendix A Memory amp 1 0 Maps Appendix Interrupt Lines Appendix Kontron Extension Registers Appendix D Board Diagrams AppendixE Connector Pinouts Appendix BIOS Setup Error Codes Appendix G BIOS Update amp Emergency Procedure Appendix Getting Help xii CP6010 User s Guide Customer Comments If you have any difficulties using this user s quide discover an error or just want to provide some feedback please send us a message at Tech Writer ca kontron com Detail any errors you find We will correct the errors or problems as soon as possible and post the revised user s guide in our online Support Library Thank you Advisory Conventions Seven types of advisories are used throughout the user guides to provide helpful information or to alert you to the potential for hardware damage or personal injury They are Note Signal Paths Related Jumpers
74. codes a PCI Read cycle crossing an address boundary Select Enabled to allow logging of Split Completion Initiated by CIOB terminated with Master Abort or Target abort events Select Enabled to allow logging of CIOB s internal Split Response Timer Expired before Split Completion is received events 5 14 CP6010 User s Guide 5 1 2 5 5 Console Redirection You can make the following selections on the Console Redirection submenu Feature Description If enabled console redirection works without the VT100 jumper Console Disabled to use the console redirection Redirection Enabled This option is only used when jumper is not present Com Port On board COMA Tf enabled it will use a port on the motherboard Address On board COMB Install the VT100 jumper to use the console redirection 300 1200 2400 9600 Baud Rate 19 2K 38 4K 57 6K Enables specified baud rate 115 2K Parity None Fix setting No Parity Data Bits Fix setting 8 Data Bits Stop Bit s 1 Fix setting 1 Stop Bit VT100 VT100 8bit PC ANSI 7bit PC ANSI None Flow Control XON XOFF Enables flow control CTS RTS Console Direct Indicates whether the console is connected directly to the system connection Via modem or a modem is used to connect Continue C R after POST Console Type Enables specified console type Off On Enables console redirection after OS has loaded 5 1 2 5 6 Advanced Processor Options You can make the following selections o
75. connector The secondary IDE interface is only available through the CPCI 1 0 connector Related Jumpers W1 must removed when CompactFlash is used W1 must be installed when 2 5 inch drive used Tur BIOS Settings Section 5 1 2 5 Advanced Menu Selection CAUTION A Two master devices or two slave devices must not be installed on the same A interface at the same time 2 3 1 1 CompactFlash Interface The board supports an IDE compatible flash disk by using a CompactFlash module CompactFlash C Flash disks are the industry standard ATA IDE subsystem for application data image and audio storage They have the same functionality and capabilities as intelligent disk drives but with the advantages of being very compact rugged typical MTBF is 1 000 000 hours and use low power The CompactFlash disk connects on the CP6010 via the IDE Mezzanine 2 5 CP6010 User s Guide 64 bit PCI Mezzanine 2 9112 1 CompactFlash f 63 6311144 141121 H a 644 Signal Paths J3 CompactFlash connector on Mezzanine Related Jumpers ETT W1 must be removed to set the CompactFlash disk as master BIOS Settings Section 4 1 2 4 Main Menu Selection Hard Disk auto detection to set the type of hard disk CAUTION 1 When using a CompactFlash the ambient operating temperature must not A exceed 50 122 2 Only one device can be on the primary I
76. e ftp ftp kontron ca Support the FAQ section The CP6010 BIOS requires that the CMOS content be invalidated to force a BIOS update in Emergency mode Install Jumper W2 to clear the CMOS EMERGENCY PROCEDURES Symptoms e Board does not boot even after usual hardware and connection verifications At power up there is a floppy disk LED activity which is one sign that the BIOS has detected a corrupted BIOS CRC prior POST and went back to Emergency Recovery Mode looking for the floppy emergency disk Please go to the Kontron FTP site to get the latest Emergency Recovery BIOS for that specific product You can find the BIOS at Ftp Ftp Kontron ca Support The Emergency Recovery Procedure is included within the Zip file of the emergency BIOS F 1 CP6010 User s Guide Getting Help At Kontron we take great pride in our customers successes We believe in providing full support at all stages of your product development If at any time you encounter difficulties with your application or with any of our products or if you simply need guidance on system setups and capabilities contact our Technical Support at CANADIAN HEADQUARTERS Tel 450 437 5682 Fax 450 437 8053 If you have any questions about Kontron our products or services visit our Web site at www kontron com You also can contact us by E mail at support ca kontron com Or at the following address Kontron Canada Inc 616 Cur Bo
77. e Setup 521 PHOENIX BIOS Setup Program 5 1 5 2 Installing Drivers ooer c ecc detis v Pub gu hte 5 25 5 3 Console Redirection VT100 Mode eyed te xu 5 26 ii CP6010 User s Guide MEMORY amp 1 0 MAPS A 1 A 1 e e Pase eee A 1 A 2 VU Mapping oseere A 2 B Interrupt Lines n 1 Te ME B 1 B 2 PCE Seral Interrupts rne 1 C Kontron Extension C 1 C 1 FPGA CPLD Registers Definition 1 2 OVETVICW C 2 C 3 0190h COM2 RS232 422 485 Buffer Control 4 2 044 220112 C 3 4 019Th Reset history FPGA e C 3 C 5 0192h Bracket Switch Blue LED Lock and History FPGA amp CPLD C4 C 6 0193h ID Chip and I2C C4 C 7 0196h Watchdog Control C 5 C 8 0197h NMI Enables and Sources C 5 C 9 019Bh Backplane Information C 5 10 019Chz BMC Control CRUD erecto Ph dau cos reo soles rea coda eeu e
78. e component s antistatic packing material until you are ready to install the component in a computer Just before unwrapping the antistatic packaging be sure you are at an ESD workstation or grounded This will discharge any static electricity that may have built up in your body When transporting a sensitive component first place it in an antistatic container or packaging Handle all sensitive components at an ESD workstation If possible use antistatic floor pads and workbench pads Handle components and boards with care Don t touch the components or contacts on a board Hold a board by its edges or by its metal mounting bracket Do not handle or store system boards near strong electrostatic electromagnetic magnetic or radioactive fields viii CP6010 User s Guide Working with Batteries Care and Handling Precautions for Lithium Batteries Your computer board has a standard non rechargeable lithium battery To preserve the battery s lifetime the battery enable jumper has been removed for shipping Donotshort circuit Donotheatorincinerate Donotcharge Do deform or disassemble Donotapply solder directly Do not mix different types or partially used batteries together Always observe proper polarities ix CP6010 User s Guide Replacing Lithium Batteries Exercise caution while replacing lithium batteries WARNING Danger of explosion if battery is incorrectly replaced Replace only with the
79. e eae E D 9 0 15 ResetSwitcli 0 10 0 16 CMOS Battery Backup Connector 1 0 10 0 17 CompactFlash 33 on 2 0 10 0 18 0 11 iii CP6010 User s Guide 0 19 INZ PMC JIN2 0 12 0 20 INS MER 0 13 0 14 E BIOS Setup Error 1 1 POST Beep sie 1 2 POST Messages 6 3 Error Messages 7 BIOS Update amp Emergency Procedure F 1 F 1 BIOS UPDATE PROCEDURES 1 F 2 EMERGENCY PROCEDURES 53s eco nea ne ea nre eoa F1 b Getand 6 1 6010 User s Guide Safety Instructions Contents Before You Begin iaces sir aono basura eara vi When Working Inside a Computer vii Preventing Electrostatic Discharge viii Working with Batteries ix CP6010 User s Guide Before You Begin Before handling the board read the instructions and safety guidelines on the following pages to prevent damage to the product and to ensure your own personal safety Refer to the Advisories section in the Preface for advisory conventions used
80. e or telecommunications lines from the computer In addition take note of these safety guidelines when appropriate Tohelp avoid possible damage to system boards wait five seconds after turning off the computer before removing a component removing a system board or disconnecting a peripheral device from the computer When you disconnect a cable pull on its connector or on its strain relief loop not on the cable itself Some cables have a connector with locking tabs If you are disconnecting this type of cable press in on the locking tabs before disconnecting the cable As you pull connectors apart keep them evenly aligned to avoid bending any connector pins Also before connecting a cable make sue both connectors are correctly oriented and aligned CAUTION A Do not attempt to service the system yourself except as explained in this user s A guide Follow installation and troubleshooting instructions closely vii CP6010 User s Guide Preventing Electrostatic Discharge Static electricity can harm system boards Perform service at an ESD workstation and follow proper ESD procedure to reduce the risk of damage to components Kontron strongly encourages you to follow proper ESD procedure which can include wrist straps and smocks when servicing equipment Takethe following steps to prevent damage from electrostatic discharge ESD When unpacking a static sensitive component from its shipping carton do not remove th
81. efinitely the last postcode blink sequence defined below Blink simultaneously RED and GREEN one time start of the sequence Blink RED times while GREEN stays off range from 0 to 15 Blink GREEN G times while RED stays off G range from 0 to 15 Repeat the sequence See step 1 is the first most significant digit of the post code value in hexadecimal while G is the second digit i e post code value is RGh Some examples are shown in the following figure 2 10 1 2 Application Software Use of the Debug LED A status LED can be very useful for software development and for system level troubleshooting Consult register 0x19A description for software usage Appendix C 2 10 2 Serial Post Codes The 8 bit content of 1 0 address 80h is serialized into a proprietary protocol and output on J3 connector In manufacturing Kontron use a display board to deserialize and display the post code value on 7 segment LEDs modules This approach enables you to see post codes before PCI initialization and avoid using a PCI postcode display board The display board is not offered with this product It is used for manufacturing Postcodes can useful tool when debugging application software If the display board 15 interesting you please ask your Kontron representative for it 2 24 CP6010 User s Guide 2 10 3 Reset History When an unwanted reset of the board occurs itis intere
82. equence Red blink This is the high nibble 0 to 15 blinks represent hexadecimal 0 to F e Green blink This is the low nibble 0 to 15 blinks represent hexadecimal 0 to Address Action D7 READ PBRST WDO ENPOST ACT RED GREEN PFO WRITE ENPOST ACT RED GREEN NU Reset Power up C 3 CP6010 User s Guide C 5 C 6 PBRST Pushbutton reset WDO Watchdog reset ENPOST Enable usage of the debug LED to display the last post code of the boot ACT Setting this bit will tie IDE ACT to the red LED RED Setthis bitto turn on the red LED GREEN Set this bit to turn on the green LED History can be cleared by toggling the CLRHIS bit in register 192h 0192 BRACKET SWITCH BLUE LED LOCK AND History FPGA amp CPLD Address Action D7 D6 D5 D4 D3 D2 D1 00 READ BL ST BL EN SW 0 NU NU LOCK NU CLRHIS 0 192 WRITE BL_ST BL_EN NU NU NU LOCK NU CLRHIS BL_ST Blue LED state BL_EN Blue LED control enable Bios should enable this bit if the onboard bridge is disabled or in system slot SW 0 When 1 the bracket switch is open LOCK When 1 the enable bit of the watchdog WDEN can t be modified CLRHIS Clear and bring back to 1 to clear the reset history 0193 ID CHIP AND 12 LINK FPGA ID chip is a single wire interface This chip can also be read by the onboard BMC microcontroller It is recommended that if you use the IPMI function on the T6010 use the standard IPMI interface to retrieve board ID I2
83. es to PCI devices or installing or removing a device driver and any other task Some of the above functionalities may be implemented in the OS others may need specific application software 1 7 CP6010 User s Guide Hot Swap Switch is in the lower ejector It allows the operator to inform the system about the intention to extract the board A blue LED located on the board s faceplate illuminates when it is safe to extract the board This LED indicates that the system software has been placed in a state for orderly extraction of a board The hardware connection layer provides protection only for the hardware during insertions and extractions This method allows the operator to insert or to extract boards without reconfiguring the system with the console Note To detect handle switch activity and to signal board status with the blue LED the host must have a proper hot swap driver gt end user must know that adding PCI device to a live system requires allocating PCI resources The OS does not do this the hot swap driver does However many configurations can be done only from the BIOS Consult Kontron s technical support if you need additional information WARNING All actions are initiated by the operator and must be performed in the correct sequence for proper system operation Full Hot Swap boards present the following resources to software executing on the system host nominally implementing the Hot Plug Se
84. ese media format 2 88 MB 3 1 25MB 3 1 2 diskette requires 3 Mode floppy disk drive Additional IDE 010 255 ms Additional Delay after IDE soft reset for auto Reset Delay detect the drives None No booting device installed Multi Sector Transfers Choices Disabled 2 4 8 and 16 sectors Any selection except Disabled determines the number of sectors transferred per block Standard is 16 sectors per block LBA Mode Control Choices Disabled Enabled Enabling LBA causes Logical Block Addressing to be used in place of Cylinders heads and Sectors 32 BitI O Multi Sector Choices Disabled Enabled Transfers Enables 32 bit communication between CPU and IDE card Requires PCI or local bus LBA Mode Control Transfer Mode Primary Master Type CD ROM 35 BIT 1 0 Choices Standard Fast 1 Fast 2 Fast PIO 3 Fast PIO 4 FPIO 3 DMA 1 FPIO 4 DMA2 Transfer Mode Selects the method for transferring the data between the hard disk and system memory Ultra DMA Mode The Setup menu only lists those options supported by the drive and platform Ultra DMA Mode Choices Disabled Mode 0 1 2 3 4 5 Select the Ultra DMA mode used for moving data to from the drive Autotype the drive to select the optimum transfer mode IDE SMART Monitoring Choices Enable Disable ATAPI Removable Same choices as CD ROM 5 5 CP6010 User s Guide Main Menu Selection continued Feature Primary Master
85. et the PMC bus to PCI 66 There is performance degradation e CompactFlash connector supporting Type 1 and 2 modules IDE connector for 2 5 inch hard disk exclusive with PMC and CompactFlash See Kontron s mezzanine offering for additional I O capabilities 1 6 3 1 CompactFlash Hard disk Feature Using a mezzanine the CP6010 board also supports standard CompactFlash disk through a CompactFlash module or a 2 5 inch hard drive 1 6 3 2 Provides Additional Power The CP6010 is a high performance CPU board that needs more current than what one CPCI slot can provide To overcome this part of the required current comes from the mezzanine s J1 connector 1 6 3 3 PMC Expansion The mezzanine increases the 1 0 capability of the CP6010 by providing a slot Up to 133MHZ 64 bits are supported for up to 1GB of I 0 bandwidth Note The CP6010 requires a mezzanine for proper operation Without a mezzanine the board remains without power and the blue LED will stay on A The CP6010 requires a slot either system peripheral or bus less for the mezzanine Many systems that have a system slot at the right of a backplane fail to meet this requirement preventing the use of the CP6010 as a system host controller 1 10 CP6010 User s Guide The capability of the CP6010 to connect with other devices is enforced by PCI Mezzanine Cards PMC A fully equipped CP6010 board may appear as follows CP6010 with SCSI Mezzanine CP
86. f the board has the front access option e Copper Option Activity and link indicators are built in the connector e Optical Option Two external LEDs per interface indicate the link and activity status Both signals are combined on a single LED The LED lights when a link is established and blinks with activity 2 13 CP6010 User s Guide 2 5 2 1 0 Configuration In rear access or 2 16 configuration the two Ethernet ports are available from a a PICMG2 16 system CAUTION 1 Frontand rear panel configurations are not supported 2 When using a PICMG2 16 system LAN cannot be used the RTM 3 You cannot use a standard RTM with most PICMG2 16 systems See your system s manual Signal Paths i The Ethernet Ports signal paths depends on the output configuration you have ordered for the board Example Front configuration Ethernet ports are available at J9 and J10 on the faceplate Ethernet Ports are always available through the RTM BIOS Settings Section 4 1 2 5 Advanced Menu Selection On board Device Configuration Ethernet 2 6 System Management Features 2 6 1 Thermal Management The SBC includes a user defined temperature sensor alarm function which provides thermal monitoring of the processor using the ADM1026 In addition the Pentium 4 includes an active thermal control circuit TCC that can automatically throttle the CPU clock when exceeding the maximum operat
87. figuration See Intel s Web site for additional details about Xeon architecture and instruction set 2 2 2 Chipset Feature The CP6010 is based on the GC LE chipset which include the following high performance devices CMIC LE memory controller CPU interface 400 533MHz CPU interface with parity and 36 bit addressing for up to 4 2GB s data transfer rate e Support for multiple processors Memory e 200 266MHz memory interface 144 bits wide synchronous with CPU bus interface for up to 4 2GB s data transfer rate e Support two channels of DDR memory for interleaved operation e ECC support with correction for up to a nibble four bits and detection for multiple nibble e Upto 16GB support 8GB for CP6010 with four DIMMs 2 2 CP6010 User s Guide e Memory scrubbing support chipset automatically scans memory and corrects ECC errors Support 12 deep for in order queue e Eight cache line read buffers eight cache line write buffers e Support for read around write IMB Inter Module Bus 800MHz IMB for 3 2GB s transfer rate between CMIC LE and CIOB X2 CRC protected IMB Multiple IOAPIC support Allow concurrency between IMB and CPU interface transaction CIOB X2 PCI X bus interface Support 800MHz IMB Parity protection on PCI PCI X Allow concurrency between PCI PCI X bus and IMB Eight deep outbound request queue for IMB to PCI PCI X transaction Eight deep IMB to PCI PCI X memory write posting transaction Caching of PCI to
88. gineering or manufacturing technology Changes that affect the operation of the unit will be documented in the next revision of this user s guide i CP6010 User s Guide Contents Customer Service Safety instructions Before You When Working Inside a vii Preventing Electrostatic DISCHSTOBs teta ya Medos DR bit oo viii Working WIEN Batteries cete tte sas ix Preface Howto Use This ETT NT xii Customer cc WO M cfe le OE VER ES LEA xiii Advisory CONVENTIONS aedes ceo cA Ht ars axo e Bote dam xiii VG RTT ET LI I T xiv Powerng Up th RU da xiv Adapter Storing ao Regulatory Compliance Statements erba dro ca T aiebat a rut eds xvi 1 Product Description 121 Prod CEOVelVIGw 1 1 1 2 Whats Inel det ico asd csv cas patulae dex deed 1 1 1 3 Board ds 1 2 Compact PCI Comp lances 1 5 1 5 Hob Swap 1 6 1 6 Interfacing with the
89. gle format USB supports Plug and Play and hot swapping operations 05 level These features allow USB devices to be automatically attached configured and detached without reboot or running setup Pin _ Signal VCC DATA DATA GND Hn Signal Paths USBO signals are available on the faceplate from the J7 connector Both USB 0 and USB 1 signals are available through the connector 23 BIOS Settings 1 92 Advanced Legacy USB Support keyboard and mouse The CP6010 board supports the standard open host controller interface OHCI and uses standard software drivers that are OHCI compatible 2 8 CP6010 User s Guide 2 4 1 0 PC87471 2 4 1 Floppy Disk Interface The on board floppy disk controller is IBM PC XT AT compatible It handles 3 5 low and high density disks can support up to two drives in any combination Signal Paths The floppy disk controller interface is available through the J5 connector BIOS Settings sm Section 5 1 2 4 Main Menu Selection Legacy Diskette A Section 5 1 2 5 3 Advanced Menu Selection On board Device Configuration Floppy Disk Controller 2 4 2 5 2 Keyboard PS 2 Mouse Interface The on board keyboard controller is compatible with 8042 software Signal Paths 8 PS 2 keyboard and PS 2 mouse signals available through the J3 CPCI 1 0 connector Keyboard J3 Row E pin 2 3 See appendix for com
90. h dor deo C 6 11 019Dh PCI Status Register C 6 C12 o1AOh Interr pt number FPGA areren C 7 13 O1ALh Interrupt enable ERU NE E DR ege eats C 7 C314 O21A2h PCLInterruptstatus FPGA erreneren arisini reiter aR EE C 7 15 QTA3hi JTAG P rt FPGA 252550 e er ee ce eere rtu rev C 8 16 01A8h I2 C Address FPGA 25 encre reete C 8 C17 gt transmit FPGA C 8 C8 12 receive FPGA i esee ertet eren dues C 8 C19 122 flags FPGA i i etie eoe ee eR aree en eu nn ea ex PLE do Ne TAY Pea Vg Fa uo cee C 9 D Connector Pinouts 0 1 0 1 Connectors and Headers 5 0 1 0 2 CPCI BUS 1 dice D 2 D 3 6 2 ERE D 3 D 4 CPL BUS 93 E 0 4 0 5 CPCLBus PIM 0 5 0 6 SCSI 04 EN 0 6 0 7 0 7 0 8 Serial Port 0 RS 232 36 D 8 D 9 USB located J7 D 8 0 10 Interface 18 D 8 D 11 Ethernet LAN 2 and 1 1 29 10 D 8 0 12 H tSwap Switch 220 16e D 8 DIS 22 inert E RYE Dev PEE NN NUI R D 9 0 14 IDEMEZZANINE 023 ee sods ee a eaa ee Eee e Y CAN eee Ye H
91. in this user s guide including the distinction between Warnings Cautions Important Notes and Notes Always use caution when handling operating the computer Only qualified experienced authorized electronics service personnel should access the interior of the computer The power supplies produce high voltages and energy hazards which can cause bodily harm Use extreme caution when installing or removing components Refer to the installation instructions in this user s guide for precautions and procedures If you have any questions please contact Kontron Post Sales Technical Support WARNING High voltages are present inside the chassis when the unit s power cord is plugged into an electrical outlet Turn off system power turn off the power supply and then disconnect the power cord from its source before removing the chassis cover Turning off the system power switch does not remove power to components WARNING This product contain CLASS 1 LASER PRODUCT CP6010 User s Guide When Working Inside a Computer Before taking covers off a computer perform the following steps Turn off the computer and any peripherals Disconnect the computer and peripherals from power sources or subsystems to prevent electric shock or system board damage This does not apply to when hot swapping parts Follow the guidelines provided in Preventing Electrostatic Discharge on the following page Disconnect telephon
92. ing temperature The current CPU temperature can be read by software or by a user application Use the IPMIfor increased system management If you would like more information please consult the IPMI section im BIOS Settings Section 5 1 2 6 1 3 Monitoring Menu Selection Intelligent System Monitoring Control Temperature Events CPU overheating may happen if the system fans fail In the advent of catastrophic overheating the SBC will power down itself Note lt If the CPU overheats the CPU asserts the THERMTRIP signal which stops power You need to cycle BDSEL or remove and insert the board to restart the board 2 14 CP6010 User s Guide 2 6 2 Power Supply Monitoring All on board supplies are monitored any low power rail holds the board in reset Most power rails also can be monitored though the SM bus by using the ADM1026 or by using the embedded IPMI controller 141 05 Settings Section 5 1 2 6 1 2 Monitoring Menu Selection Intelligent System Monitoring Hardware Monitor Voltage Inputs 2 6 3 Programmable Dual Stage Watchdog A two stage digital watchdog timer with software programmable time out period is available Following a reset of any source the watchdog is disabled Software enables the watchdog Bios Settings 940 e Section 5 1 2 6 Monitoring Menu Selection e Enable watchdog automatically before OS launch Bios Settings e Section 5 1 2 6 Monitoring Menu Selection ai e
93. is powered off the BIOS setup program is required to make changes to the setup 5 1 1 Accessing the BIOS Setup Program The system Basic Input Output System BIOS provides an interface between the operating system and the hardware of the CP6010 processor board The CP6010 uses the Phoenix Setup program a setup utility in flash memory that is accessed by pressing the DELETE key at the appropriate time during system boot This utility is used to set configuration data in CMOS RAM CAUTION A Before modifying CMOS setup parameters ensure that the W19 battery selection A jumper is installed to enable the CMOS battery back up See Section 3 To run the Phoenix Setup program incorporated in the ROM BIOS 1 on or reboot the system 2 When you get the following message hit DELETE key to enter SETUP Phoenix ServerBIOS 3 Release 6 0 Copyright 1985 2001 Phoenix Technologies Ltd Rights Reserved KONTRON CP6010 BIOS Version 3 1 5 1 CP6010 User s Guide main menu of the Phoenix BIOS CMOS Setup Utility appears on the screen Advanced Monitoring System Time 9 39 8 00 mes Ox System Date 01 01 2002 Enter selects field Legacy Diskette A 1144 1265 Mi Additional IDE Reset Delay Primary Master None Primary Slave None Secondary Master None Secondary Slave None POST Errors Enabled System Memory 640 KB Extended Memory 2620
94. ith the Copper or with the Optical Option Each interface supports 10Base T 100Base TX 1000Base T with auto negotiation and automatic crossover cable detection either in rear or front access depending on the ordered option With the optical option 1000Base SX is available for front access configuration The 82546 features high performance with TCP IP and UDP IP checksum offloading for IPv4 and IPv6 packet filtering and jumbo frame up to 16K The CP6010 has boot from LAN capability PXE on both ports either in the copper or fiber mode Enable the option from the BIOS Setup Program Please refer to Section 4 1 PHOENIX BIOS Setup Program WARNING This product contain CLASS 1 LASER PRODUCT See Kontron s Web site http www kontron com for the latest drivers See Intel s Web site http www intel com for the latest drivers for the 82546EB and for additional information on the Ethernet controller 2 12 CP6010 User s Guide Pin Signal 1000 Signal 10 100 Signal Paths The J9 and 310 RJ45 connectors are on the faceplate if the product was ordered with front access The J9 and J10 RJ45 connectors are on the J3 connector if the produce was ordered with rear access BIOS Settings 04101 Section 5 1 2 5 2 1 Advanced Menu PCI Configuration On board Ethernet Controller 2 5 1 Front Plate Configuration Ethernet 1 and 2 signals are available on the frontplate connectors J9 and J10 i
95. ivin Boisbriand Qu bec J7G 2A7 Canada G 1 CP6010 User s Guide RETURNING DEFECTIVE MERCHANDISE If your Kontron product malfunctions please do the following before returning any merchandise 1 Call our Technical Support department in Canada at 450 437 5682 or at 1 800 354 4223 Make certain you have the following at hand The Kontron Invoice number Your purchase order number The serial number of the defective board 2 Give the serial number found on the back of the board and explain the nature of your problem to a service technician 3 Ifthe problem cannot be solved over the telephone the technician will further instruct you on the return procedure 4 Prior to returning any merchandise make certain you receive RMA number from Kontron s Technical Support and clearly mark this number on the outside of the package you are returning To request a number follow these steps e copy of the request form on the following page e Fill out the form and be as specific as you can about the board s problem e Faxittous 5 When returning goods please include the name and telephone number of a person whom we can contact for further explanations if necessary Where applicable always include all duty papers and invoice s associated with the item s in question 6 When returning a Kontron board 1 Make certain that the board is properly packed Place it in an antistatic plastic bag and
96. ize Power Management Load alternate registers with initial POST values Restore CPU control word during warm boot Initialize PCI Bus Mastering devices Initialize keyboard controller BIOS ROM checksum Initialize cache before memory autosize 8254 timer initialization 8237 DMA controller initialization Reset Programmable Interrupt Controller Test DRAM refresh Test 8742 Keyboard Controller Set ES segment register to 4 GB Enable A20 line Autosize DRAM Initialize POST Memory Manager Clear 512 KB base RAM Enhanced COMS init RAM failure on address line xxxx RAM failure on data bits xxxx of low byte of memorybus Enable cache before system BIOS shadow RAM failure on data bits xxxx of high byte of memory bus Test CPU bus clock frequency Initialize Phoenix Dispatch Manager CMOS test on Suspend to Disk resume Register re initialization Warm start shut down Shadow system BIOS ROM Cache re initialization Autosize cache Advanced configuration of chipset registers Load alternate registers with CMOS values Initialize interrupt vectors POST device initialization Check ROM copyright notice Check video configuration against CMOS CP6010 User s Guide Code Beeps POST Routine Description Initialize PCI bus and devices 1 0 81h PCI Bus tested Initialize all video adapters in system QuietBoot logo start Shadow video BIOS ROM Display BIOS copyright notice Multi Boot Boot menu support Initialization
97. layed if the BIOS detects an error during the POST CMOS BATTERY HAS FAILED 1 Ifitisthe first boot check for the onboard battery jumper W19 The board is shipped with W19 jumper set to OFF onboard battery disconnected This jumper must be shorted ON for proper battery operation 2 CMOS battery is no longer functional It should be replaced Consult the Intelligent System Monitoring in BIOS Setup to verify Vbat value CMOS CHECKSUM ERROR Checksum of CMOS is incorrect This indicates that CMOS has become corrupt This error may have been caused by a weak battery Check the battery and replace if necessary OPERATING SYSTEM NOT FOUND No boot device was found This could mean either a boot drive was not detected or the drive does not contain proper system boot files Insert a system disk into Floppy Drive A and press Enter If you assumed the system would boot from the hard drive make sure the controller is inserted correctly and all cables are properly attached Also be sure the disk is formatted as a boot device Then reboot the system EXPANSION ROM NOT INITIALIZED Cannot initialize the PCI expansion ROM There is not enough free conventional memory for expansion ROM C0000h to DFFFFh Expansion ROM not required to boot should be disabled E 7 CP6010 User s Guide F BIOS Update Emergency Procedure F 1 F 2 BIOS UPDATE PROCEDURES The BIOS update procedure can be found with the Emergency Recovery procedure at our FTP sit
98. le ACPI Remap Memory above 4GB Reset Configuration Data Boot time Diagnostic Screen Extended RAM Test Step Summary Screen Delay Save CMOS in FLASH Retry Boot Sequence PS 2 Mouse Multiprocessor Specification Other Win95 Win98 WinMe Win2000 Yes No DIMM Remapping Chipset Remapping Disabled No Yes Enabled Disabled Every Location First KB First 64 KB None 5 seconds Disabled Enabled Disabled Enabled Disable Enabled 1 1 1 4 Description Other General Settings Win95 Win98 WinMe Win2000 Specific Settings Note An incorrect setting can cause some operating systems to display unexpected behaviour Enable Disable ACPI BIOS Advance Configuration and Power Interface The default option in the BIOS is set to DIMM remapping DIMM remapping under nearly all cases will give less memory in a 468 system than Chipset Remapping Chipset Remapping is also faster having scored a memory bandwidth of 3078 MB s vs 2830 MB s for DIMM remapping benchmark was done with Sisoftware Sandra 2005 under Windows 2003 Server in PAE mode The DIMM Remapping feature was done to allow CPU MTRRs to be set for PCI bursting When doing Chipset Remapping or no remapping and there gt 4GB the MTRR are set so that an Uncacheable region is set over all PCI memory up to 4GB When a range is declared uncacheable it can t be changed to improve performance PCI bursting Select Yes if y
99. lecting the option in the BIOS menu System Event Log SEL The SEL repository is present only in the BMC If an event occurs in any blade the sensor event is sent throught the IPMB bus if SEL is not local and stored in the BMC SEL repository SDR Sensor Data Record Sensor Data Record Repository SDRR The SDRR is only present in the BMC Normally the SDRR contains all sensor records ofthe chassis A utility named fillsf exe is provided the IPMI DOS tool package to make a full chassis discovery and fill the SDRR with the found sensor records A new board contains all the local sensors in the SDRR IPMB Intelligent Platform Management Bus KCS Keyboard Controller Style Field Replaceable Units A FRU is available in BMC or satellite mode The FRU contains information about the product such as the part number and the serial number See PICMG Specification 2 9 for complete details on the FRU byte structure Use Fillsf exe to update the FRU FRU System Management Software 2 19 CP6010 User s Guide 2 9 1 2 IPMI in Compact PCI Chassis IPMI implementation in cPCI environment is defined by the PCMIG2 9R1 0 specification The specification gives the pinout of J1 and J2 as well as the addressing scheme There should be only one BMC in the chassis or at least on the IPMIB segment The BMC may reside either on an SBC blade or on an external system management card SMC the specification gives full latitude over this BMC Satel
100. lite Satellite Satellite IPMB Address IPMB Address IPMB Address IPMB Address Fix 20h Boh Satellite Satellite Satellite Satellite IPMB Address IPMB Address IPMB Address IPMB Address Beh Bahn BAnO BCh 1 IPMB address for satellite is determined via the location ofthe slot in the chassis 2 9 1 3 IPMI Setup To use the IPMI resources in a system some steps are needed The system operator must take Step 1 The SMS application performs Steps 2 and 3 1 Electa BMC by setting the mode to BMC in the BIOS Setup Menu By default all Kontron s CPCI blades are configured in satellite mode 2 Fillthe SDRR with all the present sensors in the chassis This step may be done using the fillsf exe utility in DOS The SDRR must be rebuild each time there is a configuration change in the chassis 3 Probethe BMC SEL for event or any other available information using the SMS of your choice or by sending the command directly using the available tools 2 9 2 IPMI Implementation of CP6010 2 9 2 1 Features e Compliant with IPMI specification 1 0 revision 1 1 e Compliant with PICMG 2 9 specification e be configured as BMC or Satellite by software from the BIOS Setup Menu 2 20 CP6010 User s Guide e Firmware designed and specially made for compact PCI implementation e KCSSMS interface with interrupt support Dual Port IPMB configurable as two independent channels or in redundant mode BIOS Setup Menu Outof band management
101. ll in the Full Hot Swap category if it is not controlling the hardware connection process In addition to the automatic software connection process a High Availability system adds more control over the hardware such as reset and power control of each slot of the system The following signals are used BDSEL This is a short pin It is the last to mate or the first to break contact This signal allows the system to detect the presence of a board and also to controlits power state Systems other than High Availability have this pin grounded HEALTHY This is a normal length pin Peripheral boards are required to drive this signal low when they are ready to join the PCI bus This signal will not be asserted when 1 6 CP6010 User s Guide the current operating mode of the bus 15 not compatible when the back end power is not good or for any other reason PCIRST This signal resets the PCI bus when driven low High availability can implement this signal as a radial signal from the Hot Swap Controller HSC to further control the electrical connection Platforms that do this must OR the system host s reset signal with the slot specific signal to maintain the bused signal s function M66EN On a High Availability platform compatible with 2 0 of PICMG2 1 the signal may be radial from the HSC This allows the platform to accept 33MHz only peripheral boards that comply with R 1 of the specification Note a Hot Swap of the system s
102. llow 5V Brilliant Blue Universal board 5V and 3 3V None Keying also is defined in the J4 connector to determine its usage CP6010 supports user 1 0 on J4 so itis keyed with the nut brown key Backplanes that feed through J4 also have a brown key Other J4 usages have their key defined in PICMG2 10R1 0 J4 Usage Key Color User 1 0 Nut Brown H 110 Strawberry Red Standard switch Blue Lilac Extended switch Ocher Yellow Cavity keying within the card guide and handle is used to protect J2 J3 and J5 usage The CP6010 is keyed accordingly to PICMG2 10R1 0 and PICMG2 16R1 0 Few systems support this keying so you must take care to verify the type of slot before installing the board XL VHDS features complete keying and offers the greatest protection against pinout mismatch 4 4 6010 User s Guide 4 1 6 Bus Mastering The CP6010 provides seven pairs of REQ GNT 0 6 arbitration signals through the secondary PCI bus This means that the board can drive up to seven CPCI slots with PCI bus master capabilities 0 Signals This section describes integrated feature signals available on rear panel CPCI 1 0 connectors 23 J4 and J5 4 1 7 CompactPCI Connectors CPCI J5 Connector Legacy connections IDE Floppy CPCI Connector SCSI Ultra 160 320 connections SCSI board version or PIM connections PIM board version CPCI J3 Connector LANO and LAN1 Serial Ports A and B PS 2 Keyboard and Mouse VGA POS
103. lot is not defined in the PICMG2 1R2 0 specification It is electrically possible to hot swap the CP6010 in a system slot but system functionality is lost and the PCI bus will float WARNING It can be harmful for some PCI peripheral devices to remove system slots because the PCI bus floats At least PCIRST should be asserted but not all platforms detect this condition and hold the system in reset when a system board is not present Please consult your chassis manual 1 5 3 Hot swap Compatibility with Kontron Systems XL VHDS XL PSB XL CXP XL LP42 CP6010 High availability Full hot swap CP6010 is not High availability 1 supported in this 2 chassis 1 When system management card used 2 No supported for radial RESET and radial M66EN Note lt gt CP6010 always has mezzanine installed to provide enough power In HA platforms the hot swap controller HSC needs to assert BDSEL board select for both slots used by the CP6010 1 5 4 Full Hot swap Mechanism Full Hot Swap boards such as the CP6010 in peripheral mode drive the ENUM signals to the system host to indicate a service request When the CP6010 is the system host it can generate interrupts when the ENUM state changes This signal notifies the system host that either a board has been inserted or is about to be extracted and that the configuration of the system has or will change Then the system host performs maintenance such as assigning resourc
104. main memory transaction for each PCI bus Peer to peer transaction support PCIX bus error reporting CSB5 South bridge c N Supports thin IMB interface for 100MB s transfer in both directions 32 bits 33MHz PCI bus Provide legacy functions 8237 DMA 8259 PIC 8254 timer PCI to LPC bridge USB 1 1 interfaces Two ATA 100 EIDE interface Note Many errors can be monitored by setting the DMI event BIOS menu such as ECC errors parity errors on all PCI PCI X buses and more See the BIOS section for details 2 3 CP6010 User s Guide 2 2 3 Memory Interface This product supports up to eight Gigabytes all 8GB is cacheable on 4 x 184 pin latching DIMM sockets Supported memory includes PC 1600 PC 2100 DDR 2 5V registered SDRAM non ECC ECC mode The CMIC LE memory controller is capable of up to a nibble error correction and multiple nibble error detection via There are two DDR channels 72 bit 133MHz for interleave operation to match the bandwidth of the CPU front side bus The memory controller is optimized for applications that use huge amounts of memory and have the following high end feature Memory remapping Memory remapping allows mapping memory that is usually below 4GB at a higher address This has the advantage of freeing a physical memory area for PCI devices below the 4GB boundary without losing physical memory to overlapping If your OS does not support memory capacity above 4GB disable this feature in the BIOS Memory
105. n Serial Port A signals are available from the J3 CPCI I O connector and on the faceplate Serial Port B signals are available only though the J3 CPCI1 0 connector 2 4 3 1 2 CPCII O Configuration The complete signal set is tied to the J3 CPCI I O connector and is available through the RTM 2 10 CP6010 User s Guide 2 4 4 Serial Port B Serial Port B is buffered directly for RS 232 operations and is 16 550 PC compatible The interface includes the complete signal set for handshaking modem control interrupt generation and data transfer This port is 100 compatible with the IBM AT serial port Signal Paths Serial Port B signals are only available through the 33 1 0 connector Related Jumpers W6 W7 insert both jumper if Serial Port is used RS 422 RS 485 mode and need termination resistors Termination resistors are 120 Bios Settings Section 5 1 2 5 2 1 Advanced Menu Selection On board Device Configuration Ethernet Upon a power up or reset the Serial Port B interface circuits is automatically configured for the operation mode setup in the BIOS This Serial Port signal assignation on the J3 1 0 connector depends on the operation mode RS 232 RS 422 or RS 485 it has been set J3 Connector RS 232 RS 422 RS 485 RSV RX TX RSV RSV RX TX RSV RSV RSV 2 4 4 1 RS 232 Protocol When configured for RS 232 operation mode the serial po
106. n the Advanced Processor Options Menu Use the submenus for other selections Feature Description This is a submenu see Determines how to configure specified block of memory section 5 1 2 5 6 1 Cache Memory Variable based on the Selects the internal frequency multiplier of the CPU Frequency Ratio Ratios available of the By default the maximum ratio will be selected installed Processor s This option is hidden if the CPU ratio is fixed Enabled for Windows XP and Linux 2 4 x 0 optimized for Hyper Threading Technology Hyper Enabled Threading Technology Disabled Disabled for other OS 05 not optimized for Hyper Threading Technology 5 15 CP6010 User s Guide 5 1 2 5 6 1 You can make the following selections on the Cache Memory submenu Feature Memory Cache Cache System BIOS area Cache Video BIOS area Cache Base 0 512K Cache Base 512K 640K Cache Extended Memory Area Enabled Disabled Uncached Write Protect Uncached Write Protect Uncached Write Through Write Protect Write Back Uncached Write Through Write Protect Write Back Uncached Write Through Write Protect Write Back Description Sets the state of memory cache Controls caching of system BIOS area Controls caching of video BIOS area Controls caching of 512K base memory Controls caching of 512K 640K base memory Controls caching of system memory 5 16 CP6010 User s Guide 5 1
107. nal SCSI BIOS 18KB 64KB address may vary DMI SMBIOS Structures 16K at D8000h if USB Legacy Support is not disabled else 16K at DCO00h USB BIOS Legacy Support 16K at DCOOOh if not disabled System BIOS DRAM available Hole for PCI memory APIC and BIOS flash device DRAM available A 1 CP6010 User s Guide 2 1 0 MAPPING Address Optional Optional Optional Function Address Address Address 000 01F DMA Controller 1 020 03F Interrupt Controller 1 040 05F Timer 060 06F Keyboard 070 07F Real time clock 080 09F DMA Page Register 0 0 0 Interrupt Controller 2 0CO ODF DMA Controller 2 OFO OF1 OF8 OFF Math Coprocessor 190 1AB Kontron Control Port 1F0 1F7 3F6 Primary IDE 170 177 376 Secondary IDE 3F0 3F7 Floppy Disk 3F8 3FF COM1 2F8 2FF COM2 Serial Port 1 COM1 by default 2F8 2FF COM2 3F8 3FF COM1 Serial Port 2 COM2 by default 400 0FFF Chipset Reserved A 2 CP6010 User s Guide B Interrupt Lines B 1 IRQ LINES The board is fully PC compatible with interrupt steering for PCI plug and play compatibility Controller 1 Controller 2 00 Timer Output 0 Real Time Clock IRQ 1 Keyboard Output Buffer Full IRQ 9 Available IRQ2 Cascade Controller 2 IRQ 10 Available IRQ 3 Serial Port 2 Available IRQ 4 Serial Port 1 IRQ 12 PS 2 Mouse 5 Available IRQ 13 Coprocessor Error IRQ 6 Floppy Controller IRQ 14 Primary IDE or available IRQ 7 Availa
108. nd firmware as recommended 2 10 Debugging Features 2 10 1 Bi color Debug LED The board has bi color LED that 15 very useful to debug Consult the quick reference sheet The significance of the LED is context dependent and is shown below Time During reset and prior to FPGA programming After reset during the boot process After the boot process while the operating system loads While the application software runs Software Usage LED usage RED is ON No blinking Postcode blinker blinking GREEN reflects hard disk activity RED is not used Application software does not use the LED GREEN reflects hard disk activity and RED is not used Application software uses the LED to display status information See register 19 description in Appendix C for details 2 23 CP6010 User s Guide 2 10 1 1 Post Code Blinker The postcode blinker circuit uses a blinking sequence to display the current post code value This sequence restarts every time the post codes value changes Because post codes changes all the time during a normal boot process the blinker does not have enough time to complete its sequence and the debug LED blinks meaninglessly Ifthe boot process succeeds the post code value has no interest and the BIOS will disable the post code blinker before the operating system launches Ifthe boot sequence fails or the CPU hangs the postcode blinker remains operational and repeats ind
109. necting or disconnecting a board to from a backplane 1 Railguides must be installed on the enclosure to slide the board to the backplane 2 Donotforce the board if there is mechanical resistance while inserting the board 3 Screwthe frontplate to the enclosure to firmly attach the board to its enclosure 4 Useextractor handles to disconnect and extract the board from its enclosure N Note 22 Hot swap of the CP6010 in a system slot is not defined This results a cold start of the system WARNING Always use a grounding wrist wrap before installing or removing the board from a chassis WARNING Removing the system host in a running system can harm some PCI I O devices because the bus remains floating At least PCI reset should stay asserted but not all systems detect this condition and hold reset active when no system slot is present 3 8 CP6010 User s Guide 3 6 1 Installing the Card in the Chassis To install a card in a chassis Remove the filler panel of the slot or see Removing the Card below Ensure the board is configured properly Carefully align the PCB edges in the bottom and top card guide Insert the board in the system until it makes contact with the backplane connectors Using both ejector handles engage the board in the backplane connectors until both ejectors are locked Fasten screws at the top and bottom of the faceplate 3 6 2 Removing the Board If you would like to
110. on Feature Static information Description Board Product Number i I tory information aboutthe board Board Serial 1000123456 nven oy abou a Number Board Serial and Part Numbers are examples only Board Part T601048A4A 1000 Number Feature Description Hard Drive Keys used to view or configure devices Bootable Add in Cards Enter expands or collapses devices with or Primary Master lt Ctrl Enter gt expands all Removable Devices lt Shift 1 gt enables or disables a device Legacy Floppy Drives lt gt or lt gt moves the device up or down Hard Drive n May move removable device between Hard Disk or Bootable Add in Cards Removable Disk ATAPI CD ROM Drive d Remove a device that is not installed Network Boot Note The hard drives and SCSI drives detected will be listed in this section and the first drive in the listwillbe boot drive 5 22 CP6010 User s Guide 5 1 2 7 Exit Menu Selection Feature Description Exit Saving Changes Yes No Exit Saving Changes Exit Discarding Yes No Setup and save your changes to CMOS h Changes Yes No Exit Discarding Changes Yes No Exit utility without saving Setup data to CMOS Yes No Load Setup Defaults Saves Changes Exit utility without saving Setup data to CMOS Load Setup Defaults Discard Changes Load Setup Defaults Load default values for all SETUP items Discard Changes Load previous values from CMOS for all SE
111. ou wantto clear the Extended System Configuration Data ESCD area Displays the Diagnostic Screen during boot Always enabled when console redirection is activated Select how to perform extended memory tests First KB Test First KB of each MB First 64 KB Test First 64 KB of each MB Delay to display the system configuration at boot time Saving 5 memory content into Flash Memory will prevent losing CMOS options when battery fails Enable this option to Retry the Boot sequence until a successful boot infinite retry Disabled prevents installed PS 2 mouse from functioning but frees up IRQ 12 Enabled forces PS 2 mouse port to be enabled regardless if a mouse is present Configures the multiprocessor specification MPS revision level Some operating systems will require revision 1 1 for compatibility 5 8 CP6010 User s Guide 5 1 2 5 2 PCI Configuration You can make the following selections on the PCI Configuration submenu Use the submenus for other selections Feature On board Ethernet Controller Mezzanine PMC Expansion Slot PCI Performance Settings PCI Reset on Warm Boot Default Primary Video Adapter Delay before PCI Initialization Local Bus IDE adapter USB Host Controller USB BIOS Legacy Support 5 1 2 5 2 1 On board Ethernet Controller Feature On board Ethernet Controller Option ROM This is a submenu see section 5 1 2 5 2 1 This is a submen
112. p code from the test point error as follows 1 The8 bit error code is broken down to four 2 bit groups Discard the most significant group if it is 00 2 Each group 15 made one based 1 through 4 by adding 1 3 Short beeps are generated for the number in each group Example Test point 01Ah 00 01 10 10 1 2 3 3 beeps Test Points and Beep Codes Atthe beginning of each POST routine the BIOS outputs the test point error code to 1 0 address 80h Use this code during troubleshooting to establish at what point the system failed and what routine was being performed If the BIOS detects a terminal error condition it halts POST after issuing a terminal error beep code See above and attempting to display the error code on upper left corner of the screen and on the port 80h LED display If the system hangs before the BIOS can process the error the value displayed at the port 80h is the last test performed In this case the screen does not display the error code Code Beeps POST Routine Description Verify Real Mode Disable Non Maskable Interrupt NMI Get CPU type Initialize system hardware De shadow BIOS code Initialize chipset with initial POST values Set IN POST flag Verify CMOS and RTC validity E 1 CP6010 User s Guide Code Beeps POST Routine Description Initialize CPU registers Enable CPU cache Initialize caches to initial POST values Initialize I 0 component Initialize the local bus IDE Initial
113. pack it in a rigid cardboard box ii Ship prepaid to but not insured since incoming units are insured by Kontron Kontron Canada Inc 616 Cur Boivin Boisbriand Qu bec J7G 2A7 Canada G 2 CP6010 User s Guide G kontron Street Address City Return to Manufacturer Authorization Request Province State Country Postal Zip Code Phone Number Extension Fax Number E Mail P 0 Serial Number Failure or Problem Description if not under warranty Kontron Canada Inc 616 Cur Boivin Boisbriand Qu bec Canada 76 2A7 Fax this form to Kontron s Technical Support department in Canada at 450 437 8053 G 3 CP6010 User s Guide
114. plete pinout description of J3 Mouse 93 Row E pin 4 5 BIOS Settings getti Section 5 1 2 5 1 Advanced Boot Settings Configuration Menu Selection PS 2 Mouse 2 4 3 Serial Ports Two fully functional serial ports are provided on the board for asynchronous serial communications They 160550 high speed UART compatible and support 16 byte FIFO buffers for transfer rates from 50bps to 115Kbps Each serial port is specified as follows Designation Communication Mode Output Path Serial Port A 1 85 232 Front Plate DB 9 J6 CPCI J3 Serial Port B 2 RS 232 RS422 RS485 CPCI J3 UART registers are individually addressable and fully programmable 2 9 CP6010 User s Guide 2 4 3 1 SERIAL PORT A Serial Port A is buffered directly for RS 232 operation Signals include the complete signal set for handshaking modem control interrupt generation and data transfer When assigned as Serial Port A the port is 100 compatible with the IBM AT serial port in RS 232 mode Pin Signal UL Signal Paths The Serial Port A signal path depends on the output configuration you have ordered Example Front configuration Serial Port A is available at J6 on the faceplate Serial Port A is always available through RTM BIOS Settings tud Section 4 1 2 5 Advanced Menu Selection On board Device Configuration Serial COM1 2 4 3 1 1 Front Plate Configuratio
115. r moving data to from the drive Autotype the drive to select the optimum transfer mode BIOS autodetects the hard disk installed Same as Primary Master Pauses and displays SETUP entry or resumes boot prompt if error occurs on boot If disabled system always attempts to boot Displays amount of conventional memory detected during boot up Displays the amount of RAM memory detected during boot up minus the base memory 1 MB CP6010 User s Guide 5 1 2 5 Advanced Menu Selection You make the following selections on the Advanced Menu Use the submenus for other selections Feature Description Boot Settings This is a submenu see onal b section 5 1 2 5 1 Additional setup menus to configure boot settings Configuration PCI This is a submenu see Configuration section 5 1 2 5 2 Additional setup menus to configure PCI devices On Board Device This is a submenu see Peripheral Configuration Configuration section 5 1 2 5 3 Advanced This is a submenu see ChipsetControl section5 1 2 5 4 Console This is a submenu see AME iti t fi le Redirection section 5 1 2 5 5 Additional setup menus to configure console Advanced Processor Options This is a submenu see section 5 1 2 5 6 5 7 CP6010 User s Guide 5 1 2 5 1 Boot Settings Configuration You can make the following selections on the Boot Settings Configuration submenu Use the submenus for other selections Feature Installed 0 S Enab
116. rgency Flash update check Ctrl E and bad CMOS Test Gate A20 Extended checksum optional Install Console Redirection Interrupt Handler Extended BIOS data Fail BIOS stack initialization Unknown interrupt Setup WAD reserved memory used by BIOS Get CPU string Software SMI failure during POST CP6010 User s Guide For Boot Block in Flash ROM Initialize the chipset Initialize the bridge Initialize the CPU Initialize system timer Initialize system 1 0 Check force recovery boot Checksum BIOS ROM Go to BIOS Set Huge Segment Initialize Multi Processor Initialize OEM special code Initialize PIC and DMA Initialize Memory type Initialize Memory size Shadow Boot Block System memory test Initialize interrupt vectors Initialize Run Time Clock Initialize video Initialize System Management Mode Output one beep before boot Boot to Mini DOS Clear Huge Segment Boot to Full DOS Test SIO Clock Validity Check TEST Jumper for POST to COM see Extension Registers Reset System for Erratas Hyper Threading Early Boot Block Initialize completed E 2 POST MESSAGES During the Power On Self Test POST if the BIOS detects an error requiring you to do something to fix it will either sound a beep code or display a message If a message is displayed it will be accompanied by PRESS F1 TO CONTINUE DEL TO ENTER SETUP E 6 CP6010 User s Guide E 3 ERROR MESSAGES One or more of the following messages may be disp
117. rom a boot device of your choice e Enter Setup Exit the Boot First Menu with lt ESC gt and load the operating system from the boot devices in the order specified in Setup 5 1 2 11 Press Del Pressing lt Del gt at any time during POST enter Setup 5 1 2 12 Keyboard Input Request If the BIOS or an Option ROM add on card requests keyboard input QuietBoot switches over to the POST screen and the Option ROM displays prompts for entering the information POST continues from there with the regular POST screen 5 24 CP6010 User s Guide 5 1 2 13 Phoenix Multiboot Phoenix Multiboot expands your boot options by letting you choose your boot device which could be a hard disk floppy disk CDROM Flash Disk SCSI or LAN You can select your boot device in Setup or you can choose a different device each time you boot during POST by selecting your boot device in The Boot First Menu ESC key Multiboot consist of Setup Boot Menu e Boot First Menu 5 2 Installing Drivers 5 2 1 Video Drivers Various drivers are provided for different operating systems and software To installa driver refer to the setup program located on the CD ROM which is provided with your board 5 2 2 Ethernet Drivers Various drivers are provided for different operating systems and software To install driver use the setup program and the ReadMe bat file located on the CD ROM which is provided with your board 5 2 3 Other Drivers
118. rom power sources or subsystems If you encounter a problem verify the following items Makesure that all connectors are properly connected Verify your boot devices Ifthe system does not start properly try booting with only the video monitor connected to the board and without any other 1 0 peripherals attached including Compact PCI or PMC adapters If you still cannot start your system please refer to the Emergency Procedure in the Appendix Section of this User s Guide If you are still not able to get your board running contact our Technical Support for assistance Make sure your system provides the minimum DC voltages required at the board s slot especially if cables carry DC power xiv CP6010 User s Guide Adapter Cables Because adapter cables come from various manufacturers pinouts can differ The direct crimp design offered by Kontron allows the simplest cable assembly All cables are available from Kontron Storing Boards Electronic boards are sensitive devices Do not handle or store device near strong electrostatic electromagnetic magnetic or radioactive fields Regulatory Compliance Statements This section provides the FCC compliance statement for Class B devices and describes how to keep the system CE compliant FCC Compliance Statement for Class B Devices This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to Part 15 of the FCC Rules These
119. rt is 100 compatible with the IBM AT serial port signals 2 11 CP6010 User s Guide 2 4 4 2 RS 422 Protocol The RS 422 protocol Full Duplex uses both RX and TX lines during a communication session CAUTION A In RS 422 mode install W6 and W7 jumper caps to connect the 120 Ohm A termination resistors See the Jumper Settings section 2 4 4 3 RS 485 Protocol The RS 485 protocol Half Duplex also uses differential signals during a communication session It differs from the RS 422 mode because it offers the ability to transmit and receive over the same pair of wires and allows a shared communication line by multiple stations This configuration also known as Party Line allows only one system to take control of the communication line at a time In RS 485 mode the RX lines are used as the transceiver lines and the RTS signal controls the direction of the RS 485 buffer When set for RS 485 mode in the BIOS upon power up or reset the transceiver is by default in receiver mode to prevent unwanted perturbation on the line Party line operation mode requires termination resistors to be installed at both ends of the network CAUTION A When installing the board at one end of the network connect the W6 and W7 A jumper caps at the 120 ohms termination resistors See Setting Jumpers 2 5 Ethernet Interfaces The Ethernet Intel 82546 controller resides on the Primary PCI bus and runs at 66MHz at 64 bit wide The board can be ordered w
120. rvice and Hot Plug System Driver signal which is an open collector open drain bused signal it signals a change in the board status A switch actuated with the lower ejector handle indicates the beginning of the extraction process or the end of the insertion process A LED indicates the status of the software connection process A set of four control and status bits hot swap register in PCI configuration space each board allows the system host s software to determine the source of the ENUM signal and control the LED 1 5 5 High Availability Mechanism When using a High Availability system such as XL VHDS and XL LP42 the system has more control over the hardware connection process compared to the full hot swap model When a board is inserted in the system the Hot Swap Controller HSC detects the insertion before powering up the newly inserted board When the HSC is ready to power up card it asserts BDSEL and monitors the signal for that card This flexibility gives the possibility to the operator for example to cycle the power state of a problematic I O board or to reset only a particular slot Please refer to your system manual for more details on how to use the High Availability feature of the system In addition to the resources a board present on a Full Hot Swap system the following ones are usable on HA systems e ABDSELI signal controls the power state of the board e AHEA
121. s 2 to 64 Dwords Enabled Disabled Controls Incremental Read Prefetch Dwords count When an entry s remaining Prefetch Dword count falls below this value the bridge will prefetch an additional PCI Sec Incremental Prefetch count Dwords no effect when in PCI X mode The count must not exceed half the value in the PCI Sec Maximum Prefetch count Otherwise no Incremental Prefetch will be performed Controls the maximum count of prefetcheable Dwords that are allocated to one entry on the Secondary when flow through for that entry was not achieved no effect when in PCI X mode Exception 0 256 bytes 64 Dwords maximum programmable count When enabled if read to secondary bus fail SERR will be asserted NOTE Available only with board revision 2 5 1 2 5 3 On board Device Configuration You can make the following selections on the On board Device Configuration submenu Feature Serial port A Base 1 0 address Serial port B Mode 1 0 address Floppy Disk Controller Enabled Disabled Auto 3F8 IRQ4 2F8 IRQ3 3E8 IRQ4 or 2E8 IRQ3 Enabled Disabled Auto RS 422 RS 485 RS 232 3F8 IRQ4 2F8 IRQ3 3E8 IRQ4 or 2E8 TRQ3 Enabled Disabled Description Configure Serial Port A using options Disabled No configuration Enabled User configuration Auto BIOS or OS chooses configuration Sets the base 1 0 address for Serial Port A Configure Serial Port B using options Di
122. s from overcurrent If for any reason current requirements increase to an abnormal level the board will shut down Power cycling or board select BDSEL signal cycling restarts the board 2 8 2 2 Hardware Connection Process If you would like more information please see Section 1 5 4 for technical background This section explains how to use the ENUM signal When the board is used in a system slot it is possible to detect insertion and pending extraction of a compliant peripheral cPCI card WARNING 1 Some mechanical parts of the guide rail are fragile shield contacts and clips Do not use force to insert and connect a CompactPCI module 2 If there is any mechanical resistance while you insert a module ensure there is no mechanical obstacle and verify that all parts are well aligned 2 8 3 Bus Mode The PICMG2 0R3 0 specification and PICMG2 1R2 0 specification do not dictate how to support a PCI X card This product implements a solution that is the best candidate for the next revision of this specification Bus speed negotiation is always done on a PCI reset Inserting a board in a live system will never make the bus not function with compliant hardware A peripheral card will have a problem if the bus is faster than the card s capability In other cases the card should initialize itself with the current bus mode 2 18 CP6010 User s Guide 2 9 This product fully supports Intelligent Platform Management Interface
123. s investigations to the UL Standard for Safety of US Information Technology Equipment Including Electrical Business Equipment It is designated to be used in end product equipment where the acceptability of the combination is determined by Underwriters Laboratories Inc CE Certification C The product s described in this user s guide complies with all applicable European Union CE directives if it has a CE marking For computer systems to remain CE compliant only CE compliant parts may be used Maintaining CE compliance also requires proper cable and cabling techniques Although Kontron offers accessories the customer must ensure that these products are installed with proper shielding to maintain CE compliance Kontron does not offer engineering services for designing cabling systems In addition Kontron will not retest or recertify systems or components that have been reconfigured by customers LIMITED WARRANTY Kontron Canada Inc The seller warrants its boards to be free from defects in material and workmanship for a period of two 2 years commencing on the date of shipment The liability of the seller shall be limited to replacing or repairing at the seller s option any defective units Equipment or parts which have been subject to abuse misuse accident alteration neglect or unauthorized repair are not covered by this warranty This warranty is in lieu of all other warranties expressed or implied xvi CP6010 User s Guide
124. s or 32 bit Posted Memory Write cycles on one side will be converted to 64 bit cycles on completion to target side if target supports 64 bit transfers After a prefetch command the remaining prefetched data will NOT be discarded but will be available for the next Read Command with consecutive address When Smart Prefetch is Enabled the prefetched data is only discarded upon a Timeout Controls Secondary PCI bus Prefetch behaviour no effect when in PCI X mode Ifsetto By EEPROM the values shown are taken from the Bridge and are not available for change This happens if a valid EEPROM content is detected and were loaded by the Bridge The default aggressive Prefetching may affect the overall performance with some PCI Masters that cannot prefetch a lot of data due to limited buffers size or other reasons If set to Manual the options can be changed for optimum performance which depends on the PCI device s present Controls initial Prefetch Cache Lines count on the Primary bus during reads to prefetchable memory space Uses size defined in PCI Cache Line Size when setting is set to PCICLS Controls initial Prefetch Dwords count on the Secondary bus during reads initiated from the primary port no effect when in PCI X mode 5 10 CP6010 User s Guide PCI Sec Incremental Prefetch count PCI Sec Maximum Prefetch count On board Bridge Enable P SERRE event None 4 8 12 16 20 24 28 or 32 Dword
125. sabled No configuration Enabled User configuration Auto BIOS or OS chooses configuration Set mode for Serial Port B Sets the base 1 0 address for Serial Port B Configure the floppy disk controller 5 11 CP6010 User s Guide 5 1 2 5 4 Advanced Chipset Control You can make the following selections on the Advanced Chipset Control submenu Use the submenus for other selections Feature Description CMIC LE advanced chipset setup DRAM configuration CIOB advanced chipset setup PCII O configuration This is a submenu see section 5 1 2 5 4 1 CMIC LE Settings This is a submenu see section 5 1 2 5 4 2 This is a submenu see section 5 1 2 5 4 3 Error Command 1 t setup Settings System errors detection and management setup 5 1 2 5 4 1 CMIC LE Settings You can make the following selections on the CMIC LE Settings submenu Feature PCI Write Posting Defer Reads amp Writes Clumping Mode Maximum Pages Open Activate to Deactivate Activate to Read Write RAS Precharge Time RAS Cycle Time RAS Cycle Time after Refresh Enabled Disabled Enabled Disabled Disabled 2 4 or 8 1to 63 Auto 6 Clocks Auto 3 Clocks Auto 7 80r 9 Clocks Auto 9 or 10 Clocks Description Enable Disable Write Posting for Processor to PCI Writes Enable Disable Deferred cycles for Processor to PCI reads and writes Clumping is the number of requests AD
126. sting to know the reset source The reset history circuit logs reset sources There are two ways to obtain the reset history Letthe BIOS read and clear the reset history and display the reset source in the summary screen e End user software reads and clears the reset history In addition the IPMI controller sends events to the system s baseboard management controller BMC By reading the SEL you can determine which event resets the board Please consult the IPMI section for further details BIOS Settings a e Monitoring Setup Selection 14111 e Display and Clear Reset History ff Software Usage See registers 0x191 and 0x192 description in appendix C for details 2 11 Miscellaneous Features 2 11 1 Simple I C Controller CP6010 offers a simple master only I C controller It can be used to access an on board EEPROM A bit banging interface also is provided Software Usage registers 0 1 8 through Ox1AC in Appendix C for details e Application Note ANO30024 for I C controller usage and a software example 2 11 2 Serial Number 052401 silicon serial number comes standard on the CP6010 It can be read from register 0x193 See appendix C 2 25 CP6010 User s Guide 3 Installing the Board Contents 3 1 3 0 3 3 221 3 3 3 4 On board Interconnectivity
127. t the device uses when initiating a sequence with one ofthe Burst Memory Read Commands CIOB Function 0 On board LAN and PCIX to PCIX Bridge Sets the maximum Byte Count the Device uses when initiating a sequence with one ofthe Burst Memory Read Commands CIOB Function 2 Bridge PMC Mezzanine When Enabled conventional PCI Mode Memory Read Commands Stray commands are treated as Stream Commands Memory Read Multiple Memory Read Line Commands The I O Cache uses the stream prefetching algorithms for these commands Select how many slots the IMB Transmit Arbiter will allocate for Primary PCI Bus Commands in per arbitration window If Enabled the Buffer Manager generates two 128 byte requests per arbitration window If disabled the buffer manager generates one 128 byte request per arbitration window You can make the following selections on the Error Command Settings submenu Feature ECC Config ECC Threshold Scrubbing Action after Uncorrectable ECC IMBus Error Enabled Disabled Disabled 4 8 16 32 64 128 or 254 Enabled Disabled Continue Halt or Reboot Enabled Disabled Description If all memory in the system supports ECC then use this option to enable or disable ECC support The limit number of ECCs allowed by CMIC for each row before it asserts When the threshold is reached the ALERT is used to log into the DMI log the number of ECC errors detected for each ro
128. u see section 5 1 2 5 2 2 This is a submenu see section 5 1 2 5 2 3 None All PCI Bus External On board Both Disabled Enabled Auto Enabled Auto Enabled Disabled Enabled Disabled Description Additional setup menus to configure embedded Ethernet Controller Additional setup menus to configure PMC Expansion Slot Additional setup menus to configure PCI Performance settings Select if RST signalis to be asserted on Warm Boot Select External to have a PCI video card must be installed to be set as the Boot Display Device Select On board to have the On board video controller as the Boot Display Device Delay in seconds before PCI Initialization Some external cards may require a minimum delay after reset before they can be accessed Cards with on board CPU that emulate a PCI Controller ex RAID are more likely to require a delay Enabled the integrated local bus IDE adapter Enables or Disables the USB hardware Disabled resources will be freed up for other uses Select Auto to automatically enable USB Host Controller if NO PS 2 Keyboard If a PS 2 Keyboard is present the USB Host Controller will be disabled Enables or Disables support for USB keyboards and mice Enable for use with a non USB aware Operating System such as DOS or UNIX Auto for automatically enabling USB BIOS Legacy Support if no PS 2 keyboard If a PS 2 keyboard is present the USB BIOS Legacy Support will be dis
129. ubmenu see section 5 1 2 6 3 1 This is a submenu see section 5 1 2 6 3 2 Enabled Disabled 5seconds 30 seconds 1 minute 5 minutes or 1 hour Enabled Disabled Enabled Disabled BMC Satellite Yes No None BIOS POST OS Load Both 30 sec 1 min 2 min or 4 min 30 sec 1 min 2 min or 4 min None Hard Rst Pwr Down or Pwr Cycle Intelligent Platform Management Interface IPMI information Field Replaceable Unit FRU information about board Allow Baseboard Management Controller BMC SMI handler for the initialization or startup of certain functions in the Management Controllers such as setting the initial timestamp time WARNING option forced to Disabled if the TEST jumper W3 is installed If this is the case it will be impossible to enable this SMI Handler only option available will be Disabled Select the refresh rate at which some sensor values will be sent to Management Controller Sending sensor from BIOS takes CPU time from OS Select BMC IRQ for the System Management Software SMS SMS takes platform management information and links it into other aspects of systems management such as software management and distribution alerting and remote console access If is shown this IRO is already used by FPGA IRQ Intelligent Platform Management Bus IPMB Enabled IPMB1 is hidden behind IPMBO and used as a Redundancy channel Disabled IPMBO and IPMB1 operate as separate ch
130. ues may cause system boot failure load Setup Default values to recover Up Down arrows select fields in current menu lt PgUp PgDn gt moves to previous next page on scrollable menus Home End moves to top bottom item of current menu Within a field F5 lt gt selects next lower value and F6 lt gt or Space selects next higher value lt Left Right gt arrows select menus on menu bar Enter displays more options for items marked with x F9 loads factory installed Setup Default values lt F10 gt saves current settings and exists Setup Esc or Alt X exits Setup in submenus pressing these keys returns to the previous menu F1 or lt Alt H gt displays General Help this screen 5 4 CP6010 User s Guide 5 1 2 4 Main Menu Selection The scroll bar on the right of any windows indicates that there is more than one page of information in the windows Use gt and lt PgDn gt to display all the pages Pressing Home and End displays the first and last page You can make the following selections on the Main Menu itself Use the submenus for other selections Feature Description System Time HH MM SS Setthe system time System Date MM DD YYYY Setthe system date Select the type of floppy disk drive installed in Legacy Diskette Disabted 720 31 2 Note 1 25 3 1 2 referencesa 1024 1 44 1 25 MB 3 1 2 byte sector Japan
131. ut If itis needed remove the PMC mezzanine before removing the CompactFlash If you have to remove the PMC consult the previous section 3 Install a new CompactFlash module 4 Reinstall the plastic retainer CP6010 User s Guide 4 Building CPCI System Contents 4 1 Building a CPCI SUBEST tav eA Ka dae 4 1 4 6 4 0 CP6010 User s Guide 4 1 Building System basic components needed to build a CompactPCI system include e Chassis e Backplanes e Power supplies e Ventilation unit e System peripheral or busless boards following application requirements e Other accessories such as storage modules Ethernet switches system management cards and RTM See your system s manual for more details 4 1 CP6010 User s Guide 4 1 1 Backplane The CP6010 board draws a lot of power from the backplane For that purpose the mezzanine should always fall in a slot where J1 is populated In other cases the board will not power up This imposes some restrictions on the backplane which you can use with the CP6010 For example the CP6010 cannot be used in the system slot of an eight slot right adjusted backplane unless there is a ninth slot for the mezzanine The CP6010 is fully compatible with the XL PSB XL LP42 and XL VHDS When building a XL VHDS configuration allow a slot for the mezzanine If using a third party system consult you system s manual determine the system
132. ween baseboard and mezzanine current on 3 3V supply Temperature board Current board temperature under CPU1 1 Temperature CPU1 Current CPU temperature on die thermal diode 1 2 21 CP6010 User s Guide Temperature CPU2 LAN heartbeat LANO link LAN heartbeat LAN1 link Oem reset Watchdog 2 Processor 1 status Processor CPU2 status Processor CPU1 hot Processor CPU2 hot Power supply PSU status Power supply board select Power supply power good Power supply switcher en Processor CPU VID good Entity presence system slot Critical interrupt NMI Critical interrupt SMI timeout Module board board ejector Cable interconnect IPMB1 alert Cable interconnect IPMBO stuck Cable interconnect IPMB1 stuck OEM firmware IPMI info 1 OEM firmware IPMI info 2 OEM RunInitAgent Agent err Current CPU temperature on die thermal diode 1 LANO link status PCI bus 1 device 5 function 0 LAN1 link status PCI bus 1 device 5 function 1 Indicates current source holding board in reset IPMI watchdog Presence indication of CPU1 Presence indication of CPU2 Thermal over heat indication Thermal over heat indication Reflect board select input signal status Reflect goodness of various on board supply Can be false if two CPU with difference VID are installed Indicated is board is in a system slot PICMG 2 9 required sensor PICMG 2 9 required sensor PICMG 2 9 required sensor 2 9 3 Software Support
133. when the temperature comes down to the selected temperature The CPU slows Doze mode when it reaches a selected temperature The CPU halts when it reaches the selected temperature The system will have to be restarted 5 19 CP6010 User s Guide 5 1 2 6 1 4 Control Voltage Events Note Any alteration done in this menu will take effect after the board is re started Feature Options Description Vcore Sense CPU 1 Voltage Int Vcore Sense CPU 2 Voltage Int Vcore Voltage Interrupt Vcc3 3 3V Voltage Interrupt Vcc 5V Voltage Interrupt Vin 2 5V Voltage Interrupt Vtt Voltage Interrupt Vin 1 5V Voltage Interrupt Vbat Voltage Interrupt Vin 12V Voltage Interrupt Vin 12 Voltage Interrupt Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled 5 1 2 6 2 DMI Event Logging This option enables voltage events handling This option enables voltage events handling Hidden if only one processor is present This option enables voltage events handling This option enables voltage events handling This option enables voltage events handling This option enables voltage events handling This option enables voltage events handling This option enables voltage events handling This option enables voltage events handling This option enables voltage
134. ws of DRAM When Enabled CMIC LE writes back the ECC corrected Memory Data back to the DRAM Select what the system will do when an uncorrectable ECC error has been detected Continue Log the error if not fatal to the system into the DMI log and try to resume process Halt Log the error if not fatal to the system into the DMI log and halt The system will appear stuck and must be reset Reboot Log the error if not fatal to the system into the DMI log and do a PCI reset to restart the system Select Enabled to allow logging of IMBus Error events The CMIC LE and CIOB are interfaced with a high speed Inter Module Bus IMB 5 13 CP6010 User s Guide Feature Processor Data Bus Error Processor Address Bus Error Processor Bus Protocol Error BINIT Sampled Asserted Received Master Abort Address Parity Error Received Data Parity Error Transmitted Data Parity Error Received Target Abort IMB Parity CRC Error IMB Training Logic Failure Target of a SCM with SCE set Target of an unexpected SC Initiate SCM with SCE set Split Completion Discard Split Response Timer Expired Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled

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