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GEZEL v2 Simulator User Manual

1. 47 48 system S 49 euclid sys 505 Jj The test bench for the GCD processor is shown in lines 34 50 We will apply the con stant values 2332 and 654 as test values This GEZEL description can be simulated with the fdlsim simulation tool To simulate 25 cycles from this description execute the command line fdlsim euclid fdl 25 cycle 0 m 912 n 28 cycle 22 gcd 6 The simulator reports that the GCD of the two test values is 6 and that this value is obtained at cycle 22 of the simulation This line is printed using a simulation directive as shown on line 17 of Listing 1 An interesting feature of GEZEL is that it does not require a compilation phase When the simulator starts it will parse in the GEZEL description and immediately start the simula tion This way the design and evaluation of hardware models becomes interactive The GEZEL parser generates error messages immediately when it encounters an error For example when line 12 of Listing 1 contains sff reduce then the following error message appears fdlsim euclid fdl 25 line 13 Syntax Error 9 sfg flags done m 0 n 0 10 sfg shiftm m m gt gt 1 CUT sfg shiftn n n gt gt 1 12 gt gt gt sff reduce m m gt n m n m Failed to parse euclid fdl When the Euclid design simulates correctly the same code can be converted into VHDL A companion tool for the GEZEL standalone simulator is a GEZEL to V
2. datap 9 int data 0 6 int i 7 datap unsigned int 0x80000008 8 9 for i 0 i 5 i 10 datap data 0x80000000 11 printf Sender sends d n data TZ datatt 1 535 14 data amp Ox7FFFFFFF 125 datap data 16 printf Sender sends d n data d s datatt 18 19 return 0 20 LISTING 16 A Receiver C program of the two ARM multiprocessor include lt stdio h gt 1 2 3 int main 4 volatile unsigned int datap im int data 0 6 int i 7 datap unsigned int 0x80000008 8 9 for i20 i 5 itt 10 do 11 data datap 12 while data amp 0x80000000 1 35 14 do 15 data datap 16 while data amp 0x80000000 17 18 printf Receiver complete last data d n data 19 return 0 GEZEL V2 0 Simulator User Manual 47 Cosimulating GEZEL with Instruction Set Simulators August 1 2005 The gplatform tool 20 The simulation of this multiprocessor proceeds as follows First compile each of the sender and receiver programs into statically linked ARM ELF executables gt usr local arm bin arm linux gcc static N listinl5 c o listingl5 gt usr local arm bin arm linux gcc static listingl6 c o listingl6 Next run gplatform with the GEZEL file as command line argument gplatform will then load the ARM executables the GEZEL description and start the simulation In the output messages printed b
3. ns 8 reg a ns 8 r r The signals flowgraph of expressions that implements this equation can be as follows always al dl a sl di a a2 d2 a s2 d2 a yl al gt s2 s2 al y2 sl gt a2 a2 S1 The keyword always indicates that the group of expressions following it will execute each clock cycle A signal flow graph can hold an arbitrary number of expressions All expressions within a single signal flow graph are concurrent within one clock cycle The order in which expressions are evaluated is independent of the order in which they appear in the GEZEL program i e it is independent of their lexical order Rather the order is determined by the data precedences of signals and registers A register can always be read at any moment during a clock cycle As discussed in Section 2 1 on page 9 a register has both a current value and a next value For a signal this is not the case A signal has only an immediate value valid within a single clock cycle Thus a signal has to be written GEZEL V2 0 Simulator User Manual 13 Creating hardwired datapaths August 1 2005 Named signal flow graphs first before it can be read It has to be written the first time within a clock cycle based on values in registers and constants As a consequence of this property of signals and regis ters the order of expressions within a signal flow graph becomes irrelevant For example if you would write al
4. It is possible to write sO if cl then if c2 then sfgl gt s0 else sfg2 gt s0 else if c3 then sfg3 gt s0 else sfg4 gt so or equivalently as a chained else if condition like sO if cl amp c2 then sfgl gt s0 else if cl amp c2 then sfg2 gt s0 else if cl amp c3 then sfg3 gt sO else if cl amp c3 then sfg4 gt s0 GEZEL V2 0 Simulator User Manual 26 Creating sequential designs August 1 2005 Choosing a controller style 3 4 Choosing a controller style An FSMD consist of two coupled state machines one playing the role of datapath and one playing the role of controller The FSMD model introduces control steps in a descrip tion and allows the GEZEL description to move from a structural description to a beha vioral description A GEZEL description is called structural if it uses only a single signal flow graph for a datapath that is executed at each clock cycle cfr the alway signal flow graph A behavioral description is one in which there are multiple s g in a datapath which are executed over multiple clock cycles A structural description will always have only a single assignment per state variable a register while a behavioral description can have more Each control step of a behavioral description a different assignment can be done A behavioral description avoids writing multiplexers when multiple assignments are done to the same state variable in
5. The output shows the number of evaluations and the number of net togglecounts per oper ation type The toggle_alledge part of the option directive enables toggle counting of 0 gt 1 as well as 1 gt 0 transitions For example the output shows that 17 additions have been performed over 10 clock cycles and that these additions result in 31 signal transi tions These signal transitions are measured as hamming distances at the output of the operations in subsequent clock cycles For example when in two consecutive clock cycles the pattern 0010 and 0100 would appear then that would contribute 2 transitions It is also possible to obtain the number of signal transitions per clock cycle by using the directive Soption profile cycles alledge operations In this case the output becomes accumulates the operations and toggle counts over each clock cycle gt fdlsim listing05 fdl 10 fdlsim listing05 fdl 10 Profile Cycle L 10 evals 3 toggles Profile Cycle 2 11 evals 12 toggles Profile Cycle 34 11 evals 12 toggles Profile Cycle 4 10 evals 20 toggles Profile Cycle 5 10 evals 18 toggles Profile Cycle 63 11 evals 16 toggles Profile Cycle Ts 11 evals 15 toggles Profile Cycle 8 10 evals 21 toggles Profile Cycle 9 10 evals 23 toggles Profile Cycle TO 11 evals 20 toggles Both profile directives have also upedge counterparts These restrict the toggle count ing to positive toggles only 0
6. amp tc 1 15 mul acc 16 mul done ctl 4 17 display mul mul mul done mul done 18 ADs ty A Galois Field multiplier Both descriptions behave exactly the same yet they are modeled differently Listing 7 is a behavioral description and uses an f sm to model control of the datapath Listing 8 shows a hardwired datapath Listing 8 introduces an extra variable over Listing 7 namely the register ct 1 This register implements a one hot controller At the start of a control cycle a 1 is injected in this shift register When it reaches the end the algorithm is completed The operations on registers like acc and sr2 use the value of the ct 1 register to multi plex two expressions in one assignment One can verify that in Listing 7 these assign ments are located in different s g ini and calc They are integrated by the control steps executed in the control FSM description GEZEL V2 0 Simulator User Manual 30 Simulating standalone GEZEL designs August 1 2005 The simulation algorithm 4 0 Simulating standalone GEZEL designs This chapter covers GEZEL simulations Besides the use of the simulation tool the use of simulation directives is discussed as well as the use of the debug flag 4 1 The simulation algorithm GEZEL uses a cycle true simulation algorithm with an evaluate phase and a register update phase For each simulated clock cycle the GEZEL kernel takes the following actions in se
7. sysbresen 79 The Bresenham datapath accepts two coordinate tuples indicating the starting resp end ing points of the vector to be drawn The bulk of the calculation of the algorithm takes place in an initialization phase for which a single sfg is created lines 13 34 Basi cally the Bresenham algorithm works with three accumulators one for the x coordinate register x one for the y coordinate register y and one error accumulator register e At runtime the error accumulator is evaluated to decide on the required increments in the x and y accumulators Not all vectors have the same length and the Bresenham algorithm only takes a single step horizontal vertical or diagonal per iteration Because each clock only a single iteration of the Bresenham algortihm is executed a complete line takes a variable number of clock cycles to generate a vector Lines 37 39 contain a loop test that decide when to terminate a loop The actual loop body which contains the error accumulations is shown in lines 43 48 GEZEL V2 0 Simulator User Manual 25 Creating sequential designs August 1 2005 Finite state machines The FSM controller of the Bresenham algorithm is shown in lines 52 60 After initializa tion the algorithm takes a first iteration of the loop and evaluates the end of loop flag on line 56 From then on the FSM takes conditional state transitions which will take it back each time from state s2 to state s2 line 5
8. 36 datareg data 37 38 sfg rcv 39 display data received data cycle Scycle 40 41 42 fsm F2 D2 43 initial s0 44 state sl s2 45 sO read sendack gt sl 46 sl if regreg then read rcv sendidle gt s2 47 else read sendack gt sl 48 s2 if regreg then read sendidle gt 2 49 else read sendack gt sl 50 51 52 dp sysD2 53s sig r a ns 8 54 sig d ns 32 DOT use myarm 56 use D2 r a d 5 use bl a 58 use b2 r 59 use b3 d 60 61 62 connect hardware to cosimulation interfaces 63 system S 64 sysD2 65 A GEZEL file for cosimulation will in general include the following elements One or more cores which will be simulated using an instruction set simulator GEZEL V2 0 Simulator User Manual 42 Cosimulating GEZEL with Instruction Set Simulators August 1 2005 The gplatform tool data 0x8000008 software hardware ARM req 0x8000004 GEZEL ack 0x8000004 data i wait for req 1 req 1 wait for ack 1 ack 1 req 0 wait for req 0 wait for ack 0 i dnd complete complete FIGURE 5 6 Two phase full handshake protcol between software running on an ARM and hardware described in GEZEL One or more cosimulation interfaces that provide communication channels from GEZEL to the application programs on the core For the hardware part of the cosimulation a ha
9. You gave me 3 3 0x00 0x03 OxFF OxFF 0x00 0x02 OxFF OxFF 0x01 0x02 OxFF OxFF 9753 Hello You gave me 2 2 0x00 0x02 OxFF OxFF 0x00 0x01 OxFF OxFF 0x01 0x01 OxFF OxFF 9894 Hello You gave me 1 1 0x00 0x01 OxFF OxFF 0x00 0x01 OxFF 0x55 Total Cycles 9987 GEZEL V2 0 Simulator User Manual 50 Cosimulating GEZEL with Instruction Set Simulators August 1 2005 Things to keep in mind with cosimulation The output of the simulation shows the display output from GEZEL in addition to a value change trace of the 8051 s ports PO to P3 The 8051 uses many clock cycles there is one machine cycle for each 12 clock cycles Typically a single instruction can execute in one machine cycle Outlook for gplatform The goal of gplatform is to support a wide range of system architectures including single processor systems loosely coupled as well as tightly coupled multiprocessor architec tures and homogeneous as well as heterogeneous systems In a loosely coupled system each core has a private memory program space In a tightly coupled system multiple cores will share a single program space The current version of gplatform supports loosely coupled multiprocessor systems including an arbitrary configuration of ARM and 18051 cores 5 3 Things to keep in mind with cosimulation In general the speed of a good instruction set simulator is far higher than that of the GEZEL kernel This is because an ISS is developed with the architectu
10. also have familiarity with the concept of logic simulation In order to use the cosimulator the reader must be familiar with the C programming language and with C compilation and linking To customize GEZEL the reader must be familiar with the C programming lan guage If changes to the syntax must be done familiarity with flex and or bison are required July 18 2005 9 41 am Authors Patrick Schaumont UCLA Doris Ching UCLA Herwin Chan UCLA Jorgen Steensgaard Madsen DTU Andreas Vad Lorentzen DTU Acknowledgements Much of what GEZEL is today was defined by the users of the tool We would like to acknowledge the contributions of the following people alphabetically for their early adoption of the tool their feedback on the tool their contributions to the tool and their comments on the manual Alessandro Traficante Politecnico di Milano Sara Bocchio ST David Hwang UCLA Bocheng Lai UCLA Per Larsen DTU Jan Madsen DTU Bjarne Mathiesen DTU Yusuke Matsuoka Renesas Technology Corp Wei Qin Boston University Kazuo Sakiyama KUL Peter Verner Bojsen Sorensen DTU Students of the Spring 2003 EE201A class at UCLA Students of the Spring 2005 02130 class at DTU Oreste Villa Politecnico di Milano Ingrid Verbauwhede UCLA and KUL Shenglin Yang UCLA Overview August 1 2005 1 0 Overview GEZEL is a language and open environment LGPL for exploration simulation and implementation of doma
11. are needed GEZEL provides a cloning operation to create such an identical copy of a single datapath The next example shows how three identical AND gates can be created by defining one and then cloning the first AND gate two times dp andgate in a b ns 1 out q ns 1 always g sa amp b dp andgate2 andgate dp andgate3 andgate Cloning creates an identical but independent copy If the parent datapath includes a regis ter then the cloned datapath will contain its own register This completes basic modeling techniques for datapaths The next section covers the mod eling of controllers that enable the use of datapath with multiple signal flowgraphs Regarding the system statement Before GEZEL 1 7 the system statement was used to express the toplevel interconnect Starting with GEZEL 1 7 this practice is however deprecated and it is suggested to use system blocks with only a single datapath To express datapath interconnections make use of structural hierarchy such as for example shown in Listing 4 The main motivation to do so is to make the modeling style more consis tent and to enable future GEZEL tools to perform type checking on the interconnect This modification was done as a result of discussions with Jorgen Steens gaard Madsen DTU GEZEL V2 0 Simulator User Manual 19 Creating sequential designs August 1 2005 FSMD models 3 0 Creating sequential designs This section covers the link
12. between a datapath with multiple signal flowgraphs instruc tions and a controller Information on how to model datapaths and signal flowgraphs can be found in Section 2 0 Creating hardwired datapaths on page 9 The generic model of control is FSMD This section covers this model by itself as well as the representation of this model in GEZEL 3 1 FSMD models The control datapath model of GEZEL is based on a more generic form of register transfer level modeling called Finite State Machine and Datapath or FSMD for short An FSMD model expresses both datapath operations as well as control operations It makes a clear distinction however between what is control and what is data processing Recall from Section 1 1 on page 2 that an FSMD consists of two cross coupled state machines One plays the role of the controller the other plays the role of the datapath Information exchange between the two includes conditions going from the datapath to the controller and instructions going from the controller to the datapath An FSMD provides separate modeling for data processing and for control processing That is for a good reason in practice there are many differences between the controller and the datapath First the modeling style for the two is different Datapaths are modeled with expressions on signals and registers Controllers are modeled with state transition graphs Secondly the logic implementation style of the two also shows differen
13. build include gezel main rtl cpp o main rtl o The link command that creates the cosimulator is as follows gt g g stimulus o display o fir fsm o fir data o N main rtl o L home guest gezel build lib lgzlsysc lfdl lgzlsysc L home guest systemc 2 0 1 lib linux lsystemc N lgmp o systemc_cosim 6 4 Why GEZEL with SystemC The goals of GEZEL and SystemC are not the same GEZEL focuses on easy modeling of cycle true micro architectures SystemC focuses on solving system integration problems Both have their place in the design of a complete system GEZEL will be particularly useful when any of the following is an issue or critical requirement for you Compilation Time GEZEL does not need to be compiled it is parsed and interpreted Compiling a model over and over again for each modification takes time even if it s only a few seconds for each iteration For example in the above FIR filter example if we make a small modification inside of the SystemC model in ir data cpp then recompiling that file and relinking the SystemC model takes 2 5 seconds on a 3GHz Pentium PC Making a modification to ir fdl on the other hand and reload ing the file takes less then 0 1 seconds In addition the authors have shown in their research that GEZEL achieves the same simulation speed at cycle true level as SystemC So interpreted does not have to mean slow Code Generation GEZEL has a build in path to VHDL implement
14. cross compiler for the AVR such as avr gcc Then compile and run the examples in the usual way make opt IBMJava2 142 bin javac classpath home schaum avrora bin home schaum gezel devel build share hwsw java make sim avr gcc mmcu atmegal28 ggdb simple c o app out avr objdump zhD app out gt app od export LD LIBRARY PATH home schaum gezel devel build lib opt IBMJava2 142 bin java classpath home schaum avrora bin home Schaum gezel devel build share avrora Main colors fals plat form hwsw app od Avrora Beta 1 4 0 c 2003 2005 UCLA Compilers Group This simulator and analysis tool is provided with absolutely no war ranty either expressed or implied It is provided to you with the hope that it be useful for evaluation of and experimentation with microcontroller and sensor network programs For more information about the license that this software is provided to you under spec ify the license option hwsw platform javasource set variable PAO javasource set variable PA1 javasink set variable PA2 javasink set variable PA3 Simulation events Node Time Event bits 8 7 buf 0 1 bits 7 6 buf 1 2 bits 6 5 buf 2 5 bits 5 4 buf 5 a bits 4 3 buf a 15 bits 3 2 buf 15 2a GEZEL V2 0 Simulator User Manual 82 Received data aa aa Received data aa aa Received data aa aa Received data aa aa August 1 2005 Simulated time 147 Time for simulatio
15. oriented constructs as a class library implemented in standard C Its use spans design and verification from concept to implementation in hardware and software SystemC provides an interoperable modeling platform which enables the development and exchange of very fast system level C models It also provides a stable platform for development of system level tools GEZEL blocks can be embedded in a SystemC simulation SystemC is used as a simula tion backbone but can support modules described in GEZEL FSMD This is convenient to add hardware scripting to a particular environment Each time the SystemC simulator starts it can parse a new GEZEL description The cosimulation uses SystemC 2 0 1 available from http www systemc org You need to install this package before creating the cosimulator You can build it as fol lows gt tar zxfv systemc 2 0 1 tgz gt cd systemc 2 0 1 gt configure make make install The installation is done by default under Systemc 2 0 1 We will assume this location in the following The cosimulator in GEZEL is a C library with cosimulation interfaces It is created as follows We configure GEZEL with the nable systemccosim flag You also need to indicate the location where the SystemC library can be found with the with systemc 1lib configuration flag The library path of SystemC is dependent on the host machine type We assume a Linux machine here gt cd gezel configur nable
16. systemccosim with systemc lib home guest systemc 2 0 1 1lib linux If you happen to have the GMP library installed in a non standard location do not forget to include CPPFLAGS and LDFLAGS for that one as well For example configur nable systemccosim with systemc lib home guest systemc 2 0 1 lib linux N GEZEL V2 0 Simulator User Manual 79 August 1 2005 CPPFLAGS I opt gmp include N LDFLAGS L opt gmp lib Next make and install the cosimulator in GEZEL This will create a library 1ibgzl sysc a gt make make install The systemc cosimulation can be tested on the examples in test systemc Compile the program as for a normal SystemC program The include path should contain both the SystemC include path as well as the GEZEL include path gt g g 03 Wall c N I home schaum systemc 2 0 1 include I devel build include gezel N accum SC CXX 0 accum sc o After compilation link with the SystemC library the GEZEL library the library with cosimulation interfaces and finally the gmp library gt g g accum sc o L devel build lib N lgzlsysc lfdl lgzlsysc L home guest systemc 2 0 1 lib linux lsystemc lgmp o systemc_cosim Note the link order for gzlsysc and fdl They are cross dependent and therefore 19z1 sysc is provided twice in the link command The cosimulation can then be run as any other SystemC simulation systemc cosim Sy
17. under your Thumb Xilinx Xcell Online Winter 2003 P Schaumont K Sakiyama Y Fan D Hwang B Lai A Hodjat S Yang I Verbau whede Testing ThumbPod softcore bugs are hard to find IEEE International High Level Design Validation and Test Workshop HLDVT November 2003 D Hwang P Schaumont Y Fan A Hodjat B C Lai K Sakiyama S Yang I Verbau whede Design flow for HW SW acceleration transparency in the ThumbPod secure embedded system 2003 Design Automation Conference pp 60 65 Los Angeles June 2003 B 3 Publications on SimIT ARM ARM Cosimulators W Qin S Malik Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation Proceedings of 2003 Design Automation and Test in Europe Conference DATE 03 Mar 2003 pp 556 561 W Qin S Malik Automated Synthesis of Efficient Binary Decoders for Retargetable Software Toolkits Proceedings of the 40th Design Automation Conference DAC 03 June 2003 pp 764 769 GEZEL V2 0 Simulator User Manual 86
18. 1 iptype systemcsink ipparm var output data ready The cosimulation interfaces at the SystemC side are complementary to the above ones They are represented as SC MODULE of the type gezel inport or gezel outport These module types are declared in an include file systemc itf h which is part of the standard GEZEL installation The counterparts for the above interfaces in SystemC are defined as follows include systemo itf h gezel inport blockl block1 sample blockl datain sample int gezel outport block2 block2 output data ready block2 dataout output data ready int The SystemC modules accept two parameters the first being the SystemC module name and the second the name of the interface variable The SystemC modules each define also an input resp output port as dat ain resp dataout In the current version of the GEZEL SystemC cosimulation interface the type of these ports is fixed to sc int 32 The SystemC GEZEL cosimulation gives SystemC control over the GEZEL file that should be used as well as over the clock that should be used for the simulation A Sys temC module called geze1 module is used for this purpose This module is declared in systemc itf h as well GEZEL V2 0 Simulator User Manual 53 Cosimulating GEZEL with SystemC August 1 2005 A FIR filter Assuming that clock is an sc_clock then the following SystemC definition will read in the GEZEL file fir fa1 upon sim
19. 1 transitions GEZEL V2 0 Simulator User Manual 39 Cosimulating GEZEL with Instruction Set Simulators August 1 2005 Cosimulation Interfaces and Interface Protocols 5 0 Cosimulating GEZEL with Instruction Set Simulators GEZEL designs can be cosimulated with instruction set simulators Such designs can include coprocessors that implement graphics networking and or cryptographic functions The GEZEL cosimulation engine is called gplat form It supports cosimulations with one or more ARM cores as well with one or more 8051 microcontrollers The general characteristics of the cosimulation design flow are outlined first followed by a discussion of each of the two cosimulation environments in more detail 5 1 Cosimulation Interfaces and Interface Protocols The cosimulation of GEZEL with an instruction set simulator requires besides a GEZEL program also an executable program that can run on the instruction set simulator These executables can be created using a compiler When a compiler runs on a different host machine e g a linux PC than the target execution environment e g an ARM instruction set simulator a cross compiler is required In this discussion the C programming lan guage and a C cross compiler will be used to create the executables The interactions between the GEZEL program and the executables running on the instruc tion set simulators are captured in a cosimulation interface which is an abstracted version of the re
20. 32 bit data word wr input ns 1 write asserted high rd input ns 1 read asserted high idata input tc 32 input data bus odata output tc 32 output data bus for val ues bytes input ns log2 size holding the address of a 4 bytes code sequence fetch input ns 1 read asserted high byteval output ns 32 output data bus for code Parameters size number of locations file name of file with initial contents sp initial value of register stack pointer register lv initial value of local variables register cpp initial value of constant pool pointer register filesource Function The filesource block allows to fetch stimuli from an external file Wordlength and representation base are parametrizable The block has a variable number of data ouputs When the user wires this block up with for example two outputs then two values will be read from a file for each clock cycle of simulation GEZEL V2 0 Simulator User Manual 67 GEZEL Library Blocks August 1 2005 Catalog of Library Blocks IO dl first output d2 optional second output up to 10 optional outputs are supported Parameter file string name of the file to read wl integer wordlength base interger base in which values in the file are expressed Symbols of the set 0 9a z are used to represent values in non decimal bases rand16 Function A 16 bit random number generator IO Oo output data Library Blocks in gplatform Section 5 2 on page 41 armsystem
21. 4 8 222 SAR DA 41 95 18 13 Ar ELS 10 reg rdy ns 1 dle reg rreset ns 1 12x reg rsample tc 32 135 reg acc ote619 14 reg shft0 shftl shft2 shft3 te 6 15 reg shft4 shft5 shft6 shft7 te 6 16 reg shft8 shft9 shft10 shftll te 6 Ly reg shftl12 shft13 shftl14 shft15 te 6 18 sfg read 19 rsample sample rdy input valid rreset reset 20 21 sfg rst 22 acc 0 shft0 0 shft1 0 shft2 0 shft3 0 23 shft4 0 shft5 0 shft6 0 shft7 0 24 shft8 0 shft9 0 shft10 0 shft11 0 25 shft12 0 shft13 0 shft 14 0 shft15 0 26 2e sfg shft 28 shft0 rsample shftl shft0 shft2 shft1 shft3 shft2 29 shft4 shft3 shft5 shft4 shft6 shft5 shft7 shft6 30 shft8 shft7 shft9 shft8 shft10 shft9 shftll shft10 31 shftl2 shftl11 shft13 shft12 shftl4 shft13 shft1l5 shft14 2d 83 sfg phi0 34 acc shft14 coefs 15 shft13 coefs 14 35 4 shft12 coefs 13 shftll coefs 12 36 sample coefs 0 37 38 sfg phil 394 acc acc shft10 coefs 11 shft9 coefs 10 40 shft8 coefs 9 shft7 coefs 8 41 42 sfg phi2 43 acc acc shft6 coefs 7 shft5 coefs 6 44 shft4 coefs 5 shft3 coefs 4 45 46 sfg phi3 47 result acc shft2 coefs 3 shftl coefs 2 48 shftO0 coefs 1 49 output_data_ready 1 50 51 sfg noout result 0 out
22. 8 reg acc ns 9 sfg phase0 acc i o 0 sfg phasel2 acc acc i o 0 sfg phase3 o acc i gt gt 2 sequencer h avg avg phase0 phasel2 GEZEL V2 0 Simulator User Manual 21 Creating sequential designs August 1 2005 Sequencer datapath controllers 9 phasel2 10 phase3 11 12 dp tst in i ns 8 out o ns 8 13 reg a ns 8 14 always bos o sa 16 a a 2 Ts display C cycle i o o i 18 19 20 21 dp sysavg 22 sig i o ns 8 2oy use avg i o 24 use tst o i 25 26 27 system S 28 SySavg 29 An averaging filter has four phases As the datapath in lines 1 6 illustrates there is an initialization instruction phase0O an accumulation instruction phase12 and a termi nation instruction phase3 The controller for this datapath is a sequencer with four steps as shown in lines 7 10 Lines 12 19 show a simple testbench that will feed a string of even numbers to this four phase averager Finally lines 21 29 show the system interconnect function This description can be simulated for 10 clock cycles to yield the following output One can verify that indeed 0 2 4 6 4 is 3 gt fdlsim listing5 fdl 10 Cl i 0 C22 4 C3 C4 G5 C6 Gs Co GO CIO O O O O O O O O ll OoOoootcoocococo H H H H H H H H ll 2oomooooxlt n o N o 0 0 p O An im
23. 8 or else terminate the loop into state s3 line 57 The test e01 checks when the end of loop flag becomes true This test is taken on the value in a register so it actually checks the end of loop condition of the previous itera tion For this reason the instruction of the transition into s3 is an initialization instruction line 57 When the output of eo1 is high the x and y accumulators are already at there target position and no more increments should be done Finally lines 63 79 show a simple testbench for the vector generator The test will evalu ate pixels from the vector running from 5 2 to 18 8 line 66 The output of this simula tion with fdisim is shown next Register values are printed out as tuples These correspond to output input of a register gt fdlsim bresen fdl 20 Cycle 2 Plot point 5 6 2 2 Cycle 3 Plot point 6 7 2 3 Cycle 4 Plot point 7 8 3 3 Cycle 5 Plot point 8 9 3 4 Cycle 6 Plot point 9 a 4 4 Cycle 7 Plot point a b 4 5 Cycle 8 Plot point b c 5 5 Cycle 9 Plot point c d 5 6 Cycle 10 Plot point d e 6 6 Cycle 11 Plot point e f 6 7 Cycle 12 Plot point f 10 7 7 Cycle 13 Plot point 10 11 7 8 Cycle 14 Plot point 11 12 8 8 Cycle 15 Plot point 12 13 8 8 The algorithm needs 14 cycles to complete the drawing This corresponds to the largest dimension of the vector in this case along the X axis State transition conditions can also be nested hierarchically
24. D model The GEZEL syntax is introduced as well GEZEL V2 0 Simulator User Manual 4 Overview August 1 2005 The Euclid algorithm 8 Use M 0 and N 0 to select one of a9M M 21 N N 1 factor b M M gt gt 1 c N N gt gt 1 5 s d M 2 M 2N M N M 1 8 N N M N M N A if M 0 N 0 we are done a Gy b FIGURE 1 4 The Euclid GCD Algorithm a Datapath and b Controller 1 2 The Euclid algorithm In this section a simple processor that evaluates the greatest common divisor GCD using Euclid s algorithm will be modeled into GEZEL modeling and simulation The particular variant used here is the version defined by Silver and Tersion 1962 This processor deter mines the GCD of two numbers M and N as follows e f M and N are even then GCD M N 2 GCD M 2 N 2 e f M is even and N is odd then GCD M N GCD M 2 N If M is odd and N is even then GCD M N GCD M N 2 e f M and N are odd then assuming M gt N GCD M N GCD M N N GEZEL models are written at the register transfer RT level of abstraction An example of such a model that evaluates the GCD algorithm is shown in Figure 1 4 The datapath holds three registers Two of them M and N hold the values of M and N in the GCD algo rithm Each clock cycle M and N are subtracted shifted left or unchanged This is deter mined by the control step of the Euclid algorithm An FSM controller is used to express cond
25. EL simulator into SystemC However the signal types of the testbench do no correpond to the types supported by the cosimulation interfaces A possible solution is to insert type translation modules in the SystemC simulation For example the following block converts boo1 such as needed for input valid into an sc int 32 SC MODULE bool2int32 Sc in bool din Sc out sc int 32 dout SC CTOR bool2int32 SC METHOD run sensitive din GEZEL V2 0 Simulator User Manual 54 Cosimulating GEZEL with SystemC void if run din read dout write 1 August 1 2005 A FIR filter else dout write 0 While not particularly compact nor fast this glue code will do the job until the cosimula tion interfaces will support a wider range of types Now substitute the original ir top inmain rtl cpp with a GEZEL version as follows include int sc_main sc_signal sc_signal lt sc_int lt 32 gt sc_signal lt sc_int lt 32 gt sc_signal lt sc_int lt 32 gt sc_signal lt sc_int lt 32 gt boo boo int2int32 int322int gezel gezel geze geze geze 12int32 b1 b1 bl din reset 12int32 b2 b2 b2 din input int322bool b3 b3 b3 din output data ready int b4 DA b4 din sampl b5 b5 systemc_itf h valid int argc char argv l lt sc_int lt 32 gt gt reset_int gt input valid int output data ready int gt sampl
26. FIR filter result The filter has the same data I O as the set of interfaces in the SystemC main function lines 2 5 The filter coeffcients are included as a lookup array line 6 9 The design also includes registers for condition flags as well as for an accumulator and filter taps for the FIR lines 10 17 The datapath is composed of a series of instructions that can evaluate the 16 filter taps in four clock cycles lines 18 52 Thus there are four multiply accu mulates per instruction The filter controller description starts from line 53 The sequencing is dependent on the reset input which will reset the set of filter taps and the input available input GEZEL V2 0 Simulator User Manual 57 Cosimulating GEZEL with SystemC August 1 2005 Why GEZEL with SystemC As soon as this control signal is asserted the filter will go into one iteration of the algo rithm and evaluated the 16 taps of the filter in four subsequent instructions The SystemC interfaces are expressed in lines 65 80 These interfaces are simply the couterparts of the ones we have added in main_rt1 cpp Finally a system block con nects the filter core to the interfaces Now you can compile the SystemC description link the cosimulator and start the simula tion The compile command for main rtl cpp assuming an installation under home guest looks as follows gt g 03 Wall c I home guest systemc 2 0 1 include N I home guest gezel
27. Function ARM Core program memory The ISS is SimIt ARM IO Parameters exec Name of the statically linked ELF binary to be executed on the ARM verbose When set to 1 this ARM will execute in verbose debug mode visualizing all system calls as they proceed period Relative clock period default 1 When set to e g 2 the ARM will run at half speed relative to the system gezel clock armsystemsource Function Memory mapped cosimulation interface for an ARM core intercepting memory writes on this core IO data data output ns 32 Parameters core Name of the armsystem block this cosimulation interface 1s connected to address Address decoded by this cosimulation interface armsystemsink Function Memory mapped cosimulation interface for an ARM core intercepting memory reads from this core IO data data input ns 32 Parameters core Name of the armsystem block this cosimulation interface 1s connected to address Address decoded by this cosimulation interface armsystemprobe Function This block allows the application software running on the ARM ISS to send messages directly to another ipblock through the probe function as discussed in Section 8 4 on page 75 IO t GEZEL V2 0 Simulator User Manual 68 GEZEL Library Blocks August 1 2005 Catalog of Library Blocks Parameters probe Address of the ARM address space that points to the command string for the probe block Target library block that this probe must send messages to i805 s
28. GEZEL v2 Simulator User Manual Version August 1 2005 Copyright c 2004 2005 Patrick Schaumont pschaumont gmail com Doris Ching doris kc gmail com Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distrib uted for profit or commercial advantage and that copies bear this notice and the full citation on the first page To copy otherwise or republish to post on servers or to redistribute to lists requires prior specific permission and or a fee The only way an EDA tool can improve is by interacting with users July 18 2005 9 41 am Table of Contents Listings iii Roadmap to the v2 Simulator User Manual iv Authors v Acknowledgements v 1 0 Overview 1 1 The FSMD model of computation 1 2 The Euclid algorithm 2 0 Creating hardwired datapaths 2 1 Registers and signals 2 2 Expressions 2 3 Signal flow graphs 2 4 Named signal flow graphs 2 5 Datapath modules 2 6 Structural Hierarchy 2 Datapath cloning 3 0 Creating sequential designs 3 1 FSMD models 3 2 Sequencer datapath controllers 3 3 Finite state machines 3 4 Choosing a controller style 3 5 A Galois Field multiplier 4 0 Simulating standalone GEZEL designs 4 1 The simulation algorithm 4 2 The fdlsim tool 4 3 Simulation directives 44 The debug flag 4 5 Value Change Dump VCD files 4 6 Operation profiling and toggle counting 5 0 Cosimu
29. HDL code gener ator called ivna The tool is run from the command line as illustrated next fdlvhd euclid fdl Pre processing System Output VHDL source Generate file euclid vhd Generate file test euclid vhd Generate file system vhd GEZEL V2 0 Simulator User Manual 7 Overview August 1 2005 The Euclid algorithm euclid test_euclid component process system vhd FIGURE 1 5 Component Hierarchy and Process of the generated VHDL code Three files are generated and the component process hierarchy is illustrated in Figure 1 5 Each datapath module in GEZEL is created in a separate file A synchronous VHDL modeling strategy creates separate processes for combinatorial logic and for regis ters The datapath and controller FSM are each created as separate sets of processes GEZEL V2 0 Simulator User Manual Creating hardwired datapaths August 1 2005 Registers and signals 2 0 Creating hardwired datapaths Datapaths are the basic building blocks in GEZEL similar to a module in Verilog or an entity in VHDL First the essential datapath elements are considered registers and sig nals and expressions Then datapath definitions are introduced that can embed these expressions Finally the different methods of datapath composition are discussed either by creating interconnections between ports or else by structural hierarchy encapsulating one datapath into another one 2 1 Regis
30. L description of hardware side of hardware software handshake 41 Listing 13 A C description of software side of hardware software handshake 44 Listing 14 GEZEL interconnect description for a two ARM system 45 Listing 15 A Sender C program of the two ARM multiprocessor 47 Listing 16 A Receiver C program of the two ARM multiprocessor 47 Listing 17 A GEZEL description of the 8051 hello coprocessor 48 Listing 18 8051 Driver program for the Hello coprocessor 49 Listing 19 A FIR algorithm in GEZEL 56 Listing 20 A GEZEL counter interfacing to JAVA 61 Listing 21 JAVA driver for GEZEL counter 62 Listing 22 A RAM library block testbench 65 Listing 23 A runlength encoder library block for GEZEL 72 Listing 24 A runlength encoder testbench 74 iii July 18 2005 9 41 am Roadmap to the v2 Simulator User Manual While this user manual can be read front to back not all chapters are mandatory before you can do something useful with GEZEL After reading Sections 1 to 4 you will be able to develop and simulate stand alone GEZEL designs Sections 6 and 7 consider cosimula tion of GEZEL with other environments Section 8 discusses customization of GEZEL by means of adding your own simulation primitives library blocks Section 1 0 Overview summarizes what GEZEL is about and presents a taste of the GEZEL modeling language Section 2 0 Creating hardwired datapaths explains how to model datapaths and how cycle true code is developed u
31. Lai S Yang P Schaumont I Verbauwhede A Side Channel Leakage Free Coprocessor IC in 18um CMOS for Embedded AES Based Cryp tographic and Biometric Processing Proc 2005 Design Automation Conference DAC 2005 June 2005 GEZEL V2 0 Simulator User Manual 85 August 1 2005 H Chan P Schaumont I Verbauwhede A secure multithreaded coprocessor interface 3th Workshop on Optimizations for DSP and Embedded Systems March 2005 Available from workshop website O Villa M Monchiero G Palermo P Schaumont I Verbauwhede Fast Dynamic Mem ory Integration in Co Simulation Frameworks for Multiprocessor System on Chip Pro ceeding In DATE 2005 Design Automation and Test in Europe Designers Forum 2005 D Ching P Schaumont I Verbauwhede Integrated Modeling and Generation of A Reconfigurable Network On Chip 2004 Reconfigurable Architectures Workshop RAW 2004 April 2004 Y Matsuoka P Schaumont K Tiri and I Verbauwhede Java cryptography on KVM and its performance and security optimization using HW SW co design techniques Proc Int Conference on Compilers Architecture and Synthesis for Embedded Systems CASES 2004 pp 303 311 September 2004 P Schaumont K Sakiyama A Hodjat I Verbauwhede Embedded software integration for coarse grain reconfigurable architectures 2004 Reconfigurable Architectures Work shop RAW 2004 April 2004 P Schaumont I Verbauwhede ThumbPod puts security
32. Qua OM AUN OS 17 18 dd 20 dp tst out a b c d ns 1 21 reg n ns 4 22 always 23 n sn ds 24 a n 0 b n 1 c n 2 d n 3 DE 26 27 28 dp sysandgate 29 sig a b c d q ns 1 30 use tst a b c d 3X use fourinputand a b c d q 32 gt Bou 34 system S 354 sysandgate 36 Lines 10 18 define a four input AND gate using three two input AND gates A use statement allows to include a two input AND gate inside of the four input AND gate Connections can be made to datapath inputs outputs or local signals Of course the semantic requirements enumerated earlier must be obeyed Lines 20 26 define a testbench that enumerates all 4 bit input patterns by decomposing the bits of a counter Finally lines 28 32 interconnect the testbench to the four input AND gate in a system block We can now simulate this design for 16 clock cycles and observe all combinations of the AND gate to verify it works correctly gt devel build bin fdlsim listing4 fdl 16 0 20 20 Q 26 0 1000 250 0 00 20 1 1 00 0 OO TO gt 0 1 01 0 0 0 qoe 1 1 1 0 0 OOIO TY 1 30 07x20 0 0 1 gt 0 1 SION HS fem x 0 0 1 1 0 GEZEL V2 0 Simulator User Manual 18 Creating hardwired datapaths August 1 2005 Datapath cloning FOR PRO PRP V PRP ld V v FOO 2 7 Datapath cloning Sometimes multiple copies of one and the same datapath
33. ZEL as one or more modules SC MODULE in SystemC e A single module is required to couple the GEZEL kernel to the SystemC kernel In the resulting simulation GEZEL is a slave simulator attached to a SystemC clock e One additional module is required for each data channel from GEZEL to SystemC or the other direction The same remarks as made in Section 5 1 on page 40 hold the cosimulation interfaces for data exchange do not guarantee synchronization of the GEZEL application with the Sys temC application A synchronization protocol might still be required GEZEL uses a scripted approach for designs while SystemC uses a compiled approach Therefore running a cosimulation must be done in two separate steps 1 A SystemC program must be written that uses the GEZEL cosimulation interface included in the C library 11bgzlsysc a This library is part of the standard GEZEL release provided it has been configured with SystemC support See Section A 3 on page 79 This SystemC program must be compiled and linked into an executable The resulting program will have a module the GEZEL model which is defined by means of a filename say mygezel fdl 2 When running the SystemC executable the GEZEL description included in myge zel fdl will be parsed in before the SystemC simulation starts as part of the simula tor initialization Once the SystemC executable is created step 2 can be taken many times and each time the GEZEL description can
34. a source for GEZEL These blocks define an output port on the library block where data that is received from the ARM can be retrieved GEZEL V2 0 Simulator User Manual 43 Cosimulating GEZEL with Instruction Set Simulators August 1 2005 The gplatform tool Both armsystemsink and armsystemsource define two parameters using the ipparm field The first parameter is the name of the ARM core they belong to The sec ond parameter is the address value of the ARM memory location that is shared between the GEZEL hardware block and the ARM core Lines 24 50 define an example hardware module that can accept values from the soft ware running on the ARM The module executes a two phase full handshake protocol which uses two control lines an input req and an output ack The operations of the pro tocol are illustrated in Figure 5 6 At the start of the two phase full handshake protocol the hardware module is waiting for the req control signal to become high lines 46 47 Before driving this signal high the software will first set the data value to a stable value At that moment the second phase of the handshake protocol is entered and an inverse but symmetric handshake sequence is executed First the software will drive req to zero after which the GEZEL hardware model will respond by driving ack to zero lines 48 49 A software program that executes this handshake sequence on the ARM is shown next LISTING 13 A C description of software sid
35. al hardware software interface The cosimulation interfaces of GEZEL are cycle true models of the real implementations There are various forms of cosimulation interfaces depending on the I O mechanisms pro vided by the core instruction set simulator A commonly used type of interface is a memory mapped interface in which a set of addresses in the address space of the core is shared between the hardware and the software running on the core There can also be spe cialized coprocessor or I O interfaces which are supported by dedicated instructions on the core The main advantage of a memory mapped interface is that it is almost core inde pendent Therefore C code and GEZEL code written for one type of processor can be ported to another processor with only minimal changes The main advantage of the spe cialized interface on the other hand is that it provides a dedicated non shared and usually high bandwidth data channel between the core and the hardware A cycle true cosimulation interface by itself provides only a mechanism to transfer data between a C program and GEZEL This data transfer proceeds between two concurrent entities a core and a hardware block To avoid that data values get lost when one party is unware of the others activities synchronization is required Such synchronization will be provided in a synchronization protocol A synchronization protocol defines a signalling sequence on one or more control signals in addition
36. alised Mic 1 microcontrol store The contents may come from a file generated by the microprogram assembler provided by Ray Ontko Beware of possible endianness problems 1f you want to generate the contents differently IO address input ns log2 size holding an address of the least number of 8 bit bytes capa ble of holding one word of wl bits left justified rd input ns 1 read asserted high GEZEL V2 0 Simulator User Manual 66 GEZEL Library Blocks August 1 2005 Catalog of Library Blocks odata output ns wl output data Parameters size number of locations wl wordlength file name of file with initial contents startbyte default 4 number of bytes to skip in file ijvm Function Contributed by A V Lorentzen and J Steensgaard Madsen DTU Denmark s Technical University Originating from an implementation of Andrew Tanenbaum s Mic 1 that con forms to Ray Ontko s Java simulator for it The ipblock may represent a Mic 1 store with an ijvm pro gram preloaded The file from which the preloaded program is read may be generated by the ijvm assembler provided by Ray Ontko The current version conforms completely to Ray s programs including the restriction to just two code sections Parameters Sp 1v and cpp must be bound to the initial values of the Mic 1 registers with these names They do not need to be set to the values chosen in Ray Ontko s Java simu lator IO address input ns log2 size holding the address of a
37. are now ready to run You need to make sure the JAVA virtual machine will be able to find the GEZEL JAVA shared library that contains the GEZEL simulator This can be done through the environment variable LD_LIBRARY_PATH You also need to make sure the native classes for the GEZEL interface can be found by selecting an appropriate classpath parameter With these two paths correctly set the simulation generates the following output gt export LD LIBRARY PATH build lib java classpath build share counter3 javasource set variable myinput counter 0 5 counter 5 a counter a f counter f 14 counter 14 19 counter 19 1e GEZEL V2 0 Simulator User Manual 62 Cosimulating GEZEL with JAVA August 1 2005 counter le 3 counter 3 8 counter 8 d counter d 12 7 3 Cosimulation with AVRORA Cosimulation with AVRORA The JAVA cosimulation interface can be used to cosimulate GEZEL with the AVRORA simulator an instruction set simulator for the Atmel AVR developed by B Titzer at UCLA http compilers cs ucla edu avrora Some examples of AVR GEZEL cosimula tion are provided in the examples directory of GEZEL test java arvorax In order to use the AVR cosimulator you will need to download and configure the AVRORA tools as well as a cross compiler for the AVR GEZEL V2 0 Simulator User Manual 63 GEZEL Library Blocks August 1 2005 Library Blocks Definition 8 0 GEZEL Library Blocks GEZEL su
38. ased representation of a sequence of numbers For example if a run length encoder reads the number string Then it would produce a tuple sequence with value count tuples as 1 3 3 1 4 2 6 4 We will use an outline that looks as follows ipblock my rle in data ns 8 out tupdat ns 8 out tupnum ns 8 iptype rle ipparm maxlen 32 The block reads 8 bit data input values and performs runlength encoding on them The block has two outputs that will provide runlength encoded data The type of the block is rle runlength encoder and it supports one parameter call maxlen This number holds the maximum runlength that we ll allow before a codeword is forced In the example we allow a maximum runlength of 32 This means that if the input data would consist of 34 GEZEL V2 0 Simulator User Manual 70 GEZEL Library Blocks August 1 2005 Custom Library Blocks consecutive zeroes then we expect the output to consist of two runlength tuples one 0 32 and the next 0 2 There is still one issue to address Library blocks are cycle true functions This means we need to develop the function in such a way that it can read input and produce output each clock cycle For a runlength encoder an output will not be available each clock cycle how ever We will deal with this situation in our runlength encoder by producing dummy out put tuples for which tupnum equals to zero We thus can express the behavior of the run
39. atapaths August 1 2005 Structural Hierarchy LISTING 3 A number of erroneous datapaths 1 WRONG output v is not always defined 2 dp badl out v ns 1 3 always 4 M 6 WRONG a combinatorial loop between signals 7 dp bad2 8 sig a b ns 1 9 always 10 a b 1 a defines b b defines a 14 b a 1 and both are signals not registers 12 155 7 14 15 WRONG dangling signal 16 dp bad3 LPs sig a b ns 1 18 always 19 a b 1 bis unknown 20 21 7 22 23 WRONG a signal is assigned more than once 24 dp bad4 25 sig a ns 1 26 always 27 a s1 28 a 5 29 30 2 6 Structural Hierarchy Datapaths can be included inside of other datapaths thus implementing structural hierar chy For this purpose GEZEL provides the keyword use Consider the example of a 4 input AND gate LISTING 4 A 4 input AND gate using structural hierarchy and three 2 input AND gates dp andgate in a b ns 1 out q ns 1 always q sa amp b dp andgate2 andgate dp andgate3 andgate HOON DOA WH H 0 dp fourinputand in a b c d ns 1 out q ns 1 GEZEL V2 0 Simulator User Manual 17 Creating hardwired datapaths August 1 2005 Structural Hierarchy 11 sig sl s2 ns 1 12 use andgate a b sl Dr use andgate2 c d s2 14 use andgate3 sl s2 q To always 16 Sdisplay ay My By M My GR MM
40. ath gfmu1 changes value from Oxd to 0x9 Or in cycle 5 the FSM of g mul ct1 moves from state s4 to state s5 gt fdlsim d listingl1l fdl 10 gt Cycle 1 gfmul ctl gfmul ctl s0 gfmul ctl s1 0 9 gfmul sr2 0 3 gfmul fpr 0 d gfmul rl 0 1 gfmul mul st cmd 0 1 TB ctl Cycle 2 gfmul ctl gfmul_ctl sl gt gfmul ctl s2 0 d gfmul acc 9 2 gfmul sr2 L 2 TBsctl gt Cycle 3 GEZEL V2 0 Simulator User Manual 37 Simulating standalone GEZEL designs August 1 2005 Value Change Dump VCD files gfmul ctl gfmul ctl s2 gfmul_ctl s3 d 9 gfmul acc 2 4 gfmul sr2 2 3 TB ctl Cycle 4 gfmul ctl gfmul ctl s3 gt gfmul ctl s4 9 1 gfmul acc 4 8 gfmul sr2 3 4 TB ctl gt Cycle 5 gfmul ctl gfmul ctl s4 gfmul ctl s5 1 f gfmul acc 8 0 gfmul sr2 4 STB Gt Cycle 6 gfmul ctl gfmul ctl s5 gfmul_ctl sl finish reached 4 5 Value Change Dump VCD files When there are trace statements in your code and you run the simulator in debug mode d flag then a VCD trace file will be generated as well This file called TRACE vcd can be read by digital waveform viewing tools such as GTKWave http www geda seul org tools gtkwave The VCD file will contain only the signals for which you have written t race statements The debug mode generates a lot of output on the terminal For this reason it is also possi ble to enable disable the debug mode and the VCD file generation independen
41. ath instruction one or more sfg can be executed A state transition can be conditional In that case the condition is based on the values of registers in the datapath or on logical expressions directly derived from it When state transitions are conditional then the set of conditions must be complete This means that for every if true branch there must be a complimentary e se false branch Consider the following simple example of FSM modeling The sequencer of Listing 5 can also be written as an FSM as follows fsm h avg avg initial s0 state sl s2 s3 Qs0 phaseO gt sl sl phasel2 gt s2 s2 phasel2 gt s3 s3 phase3 gt s0 This description creates four states called s0 s1 s2 and s3 s0 is the initial state the others are normal states A state transition indicates the start state with the symbol and the target state with an arrow gt In between a datapath instruction is indicated A sin gle sfg can be written as such a group of sfg is specified as a comma separated list in between round brackets GEZEL V2 0 Simulator User Manual 23 Creating sequential designs August 1 2005 Finite state machines Next is an example with slightly more complicated FSM control The example is a raster line drawing routine known as the Bresenham Algorithm The strong point of this algorithm is that it can draw lines of arbitrary slope on a discrete X Y grid and without the use of floating point arithme
42. ation Error Messages GEZEL generates error messages directly upon parsing and directly in terms of the FSMD model A SystemC design generates C error messages This difference has important consequences on readability and is most easy to demonstrate by means of an example Next are two error messages for a similar type of error The first one is from SystemC GEZEL V2 0 Simulator User Manual 58 Cosimulating GEZEL with SystemC August 1 2005 Why GEZEL with SystemC main_gezel cpp 95 error no match for call to sc_out lt sc_dt sc_int lt 32 gt gt sc_signal lt bool gt amp home schaum systemc 2 0 1 include systemc communication SC port h 230 error candidates are void sc port b IF operator IF amp with IF sc signal inout ifssc dt sc int 32 gt home schaum systemc 2 0 1 include systemc communication SC port h 239 error void sc port b IF operator sc port b IFP amp with IF sc signal inout if sc dt sc int 32 gt make main gezel o Error 1 And here is the error message for a similar offense from GEZEL Error Signal has no driver S reset Context 96 97 98 system S 99 gt gt gt fir reset input_valid sample output_data_ready result 100 systemc_reset output_data_ready 101 systemc input valid input valid Without going into the details of the exact error cause the issue we are pointing at is easy t
43. b gobe p True if the value of a is different from the value of b a lt b True if the value of a is smaller than the value of b a gt b True if the value of a is bigger than the value of b a lt b True if the value of a is smaller than or equal to the value of b a gt True if the value of a is bigger than or equal to the value of b Arithmetic Operations Arithmetic Operations do calculations on all of the bits of a signal or register treated as an unsigned number or else a two s complement signed number a b a is shifted left over b positions The wordlength of the result is equal to the wordlength of a plus 2 to the power wordlength of b a gt gt b a is shifted right over b positions The wordlength and the sign of the result are equal to that of a arithmetic shift a b a is added to b a b b is subtracted from a GEZEL V2 0 Simulator User Manual 11 Creating hardwired datapaths August 1 2005 Expressions a b a and b are multiplied a b modulo the remainer of the division of a by b The sign of the divisor is ignored The result is always positive at b Bit concatenation Equivalent to a lt lt wordlength b b sa Negate the value in a this operation has higher precedence than all two operand operations Cast Operation A cast operation converts the value of a signal into one with another type This way it is possible to convert for example a 5 bit unsigned number into a 6 bit sign
44. be changed Typically the GEZEL parse times are only a fraction of the SystemC compilation times When a module is interactively being debugged GEZEL offers a more responsive way of working than the compiled approach 6 2 GEZEL SystemC Cosimulation Interfaces As with C based cosimulation discussed in Section 5 2 on page 41 a cosimulation inter face has two sides one side in GEZEL and one side in the cosimulated environment The GEZEL V2 0 Simulator User Manual 52 Cosimulating GEZEL with SystemC August 1 2005 GEZEL SystemC Cosimulation Interfaces cosimulation interfaces on the GEZEL side will be captured in an ipblock The cosimu lation interfaces on the SystemC side will be captured in SC_MODULE GEZEL interfaces are unidrectional and must specify the symbolic name of the interface variable they capture An interface that transports data from GEZEL to SystemC is cap tured ina systemcsink An interface that transports data from SystemC to GEZEL is captured ina systemcsource This example presents an interface to transport 32 bit signed numbers from SystemC to GEZEL The symbolic interface name is sample this is the name that SystemC will refer to ipblock systemc sample out data tc 32 iptype systemcsource ipparm var sample This example presents an interface to transport 1 bit numbers from GEZEL to SystemC The symbolic interface name is output data ready ipblock systemc output data ready in data ns
45. ces A datapath with operators typically exhibits a regular logic style Think for example of a rip ple carry chain adder A controller on the other hand exhibits an irregular logic style The FSMD concepts map as follows to the GEZEL model Instructions are created by selecting one or more sfg out of a datapath A single sfg can be directly referred to by its name A set of sfg is enumerated as a comma sepa rated list in between brackets For example assume a datapath is defined as follows dp adp out a ns 3 sig k ns 2 sfg fl a 3 sfg f2 k 2 a 2 sfg f3 k 1 Then the following are valid instructions fI f2 fl 3 Examples of invalid instruction are GEZEL V2 0 Simulator User Manual 20 Creating sequential designs August 1 2005 Sequencer datapath controllers 3 1 f2 These are invalid because the violate the semantic requirements for datapath models See Section 2 5 Datapath modules on page 14 When an instruction is executed during a particular control step of a controller then that will imply execution of the sfg included in the instruction as well Conditions are created out of logical expressions on registers in the datapath When conditions are extracted out of datapath inputs or signals the GEZEL parser will issue a warning The reason is that GEZEL selects the instruction to execute right at the start of a clock cycle Before this can be done any required
46. conditions need to be defined At the start of a clock cycle however the only stable values are constants and register out puts A user can still continue the simulation despite the presence of this warning How ever one must realize at that moment there is a potential risk for anticausal simulation effects e g using the value of a signal before it is available Therefore when this warning occurs one must consider if the code can be written such that no warnings appear The connection between a datapath and a controller is established by refering the name of the datapath while creating the controller Some earlier examples of this could be seen with the hardwired controller dp adp out a ns 3 hardwired h_adp adp f1 In this example a controller called h_adp is created and attached to datapath adp 3 2 Sequencer datapath controllers Besides the trivial hardwired controller See Section 2 5 on page 14 the simplest con troller is the sequencer As the name indicates a sequencer will execute a set of instructions sequentially without taking any conditions into account A typical case where sequencers are useful is for static fixed schedules Consider for example a 4 tap decimating averaging filter Such a filter reads four subsequent samples integrates and dumps the sum of the samples at every fourth sample AND AA WHE LISTING 5 A 4 tap decimating averager using a sequencer dp avg in i ns 8 out o ns
47. d to reset the accumulator register During this reset operation we will also drive the output of the datapath to zero Not all datapath definitions that one can write down in GEZEL are valid There are four rules to which a datapath definition must conform When any of those rules are violated then either the GEZEL parser will reject your code or else a runtime error message will be triggered The four rules are enumerated below 1 During any clock cycle all datapath outputs are defined 2 During any clock cycle no combinatorial loop between signals can exist This happens when there is a circular dependence on signal values i e signal a is used to define sig nal b and signal b is used to define signal a This implies that all signal values will eventually only be dependent during any clock cycle on datapath inputs datapath reg isters and constant values 3 If an expression uses the value of a signal during a particular clock cycle then that sig nal must also appear at the left hand side of an assignment expression in the same clock cycle 4 Neither registers nor signals or datapath outputs can be assigned more than once dur ing a clock cycle A special case of this is that a datapath input cannot be assigned inside of a datapath because a datapath input must be driven by the output of another datapath Here are a few examples of erroneous signal flowgraphs GEZEL V2 0 Simulator User Manual 16 Creating hardwired d
48. dlsim is located in home guest bin fdlsim then the scripting feature is used as LISTING 10 A cycle count printing program as a script home guest bin fdlsim dp mydp always Sdisplay Cycle Scycle system S mydp WOMAN DGS WH NH H The GEZEL parser will treat line 1 starting with as a comment To run this GEZEL program directly from the command line first turn on the executable flag of listinglO fdl gt chmod x listinglO fdl After that we can run 3 cycles as gt listingi10 fdl 3 Cycle 1 Cycle 2 Cycle 3 A line that starts with is considered as a comment line in GEZEL This way it is possi ble to use the C preprocessor on your GEZEL code before simulation The C preprocessor enables the use of macro s and include files To run the simulator together with the C pre processor use the command line gt cpp P listinglO fdl fdlsim 4 3 Simulation directives The simulation output can be modified with the use of simulation directives These direc tives are embedded in the GEZEL datapath and controller descriptions Display directives print out variable values and messages during simulation A display directive is embedded inside of an s g and will be executed when the s g executes The format of the display directive is Sdisplay arg arg arg The arguments of a display directive can be expressions or strings For example if the variables a and b are de
49. ds data values required to evaluate the actual expressions of the algorithm The next state function 1 can be decomposed into a f1d to evaluate datapath state and a f1c to evaluate the control state The datapath state machine uses the control step to implement instructions The control state machine uses datapath state to implement condi tional control steps Thus both state machines are cross coupled The first phase of the cycle simulation algorithm now becomes next data state fld data state control state inputs next control state flc data state control state data output f2 data state control state inputs GEZEL V2 0 Simulator User Manual 3 Overview August 1 2005 The FSMD model of computation The second phase of the cycle simulation algorithm now becomes data_state next_data_state control_state next_control_state A graphical representation of these equations Figure 1 3 shows that an FSMD consists of two cross coupled finite state machines one playing the role of controller and the other playing the role of datapath Information exchange between the two includes conditions going from the datapath to the controller and instructions going from the controller to the datapath An FSMD offers important advantages over the basic FSM model when it comes to con venient modeling and mapping of algorithms The explicit distinction of control and datapath state is something that a designer already does nat
50. e tuplenum 39 break 40 case 2 41 return isoutput dir amp amp isname tname tupledata 42 break 43 44 return false 45 46 void setparm char _name 47 gval v make_gval 32 0 48 if matchparm name maxlen v 49 maxlen v toulong 50 else Dd printf Error rke does not recognize parameter sNn name 52 53 bool cannotSleepTest 54 return false 55 56 The constructor lines 8 12 and the runtime function lines 13 31 correspond to the initialization part and the execution part of the pseudocode shown earlier The data type of the ioval array is gval defined in gval h of the GEZEL release The functions assignulong and toulong provide conversions from and to C data types Of course these conversions can loose precision if the GEZEL wordlength exceeds that of the wordlength of a C 1ong The port verification method checkterminal in lines 32 45 checks if the port names chosen by the GEZEL user correspond to the ones we have chosen for the runlength encoder outline as shown earlier The setparm method in lines 46 52 accepts parameters if any The function call matchparm is amember of aipblock and helps in parsing the parameters Finally the GEZEL V2 0 Simulator User Manual 73 GEZEL Library Blocks August 1 2005 Custom Library Blocks function cannotSleepTest illustrates the minimal implementation for a block that does not affect the sleep
51. e int gt result int bl dout reset int b2 dout input valid int b3 dout output data ready e b5 din result int L module G G clk clock signal gezel block fir fdl inport inport inport outport geze outport Fir sampl fir resul fir reset fir in val b4 dout sample int b5 dout resul my 0 fir reset reset fir reset datain reset int id fir in valid input data valid Fir in valid datain input valid int Fir sample fir sampl le datain sample int Fir output data ready fir output data ready output data ready fir output data ready dataout output data ready int Fir result fir result lt dataout result int e sample result Five extra signals are created of type sc int 32 These are connected to the GEZEL interfaces and conversion blocks to resolve the type conversion issues discussed earlier The fir_top1 module will be replaced by a GEZEL file defined in fir fd1 This file will replace ir data cppand fir fsm cpp GEZEL V2 0 Simulator User Manual 55 Cosimulating GEZEL with SystemC August 1 2005 A FIR filter LISTING 19 A FIR algorithm in GEZEL 1 dp fir in reset ns 1 2 in input_valid ns 1 d in sample tc 32 4 out output data ready ns 1 54 out result tc 32 6 lookup coefs tc 9 6 4 1 35 16 7 18 41 23 15
52. e is comparable in functionality to the previous example but uses two ARM processors instead of an ARM processor and a hard ware module The system is configured according to the following GEZEL description LISTING 14 GEZEL interconnect description for a two ARM system 1 ipblock myarml Ze iptype armsystem GEZEL V2 0 Simulator User Manual 45 Cosimulating GEZEL with Instruction Set Simulators August 1 2005 The gplatform tool 25 ipparm exec listingl5 ipblock myarm2 iptype armsystem ipparm exec listingl6 ipparm period 2 ARM clock 1 2 system clock ipblock channelsrcl out data ns 32 iptype armsystemsource ipparm core myarml ipparm address 0x80000008 ipblock channelsnk2 in data ns 32 iptype armsystemsink ipparm core myarm2 ipparm address 0x80000008 dp sys sig srcl snk2 ns 32 26 Z4 28 29 30 use myarml use myarm2 use channelsrcl srcl use channelsnk2 snk2 ILs 32 33 34 35s 36 Sw 38 a always snk2 srcl system S SYS The two cores are called myarm1 and myarm2 respectively Two memory mapped inter faces enable a direct connection between these two processors The cores and interfaces are described using the library block mechanism Lines 1 22 in a similar fashion as in the previous example The interconnection network is described using GEZEL semantics and consists of a ver
53. e of hardware software handshake 1 int main 2 volatile unsigned char regp ackp 3 volatile unsigned int datap 4 int data 0 De int i 6 7 8 9 reqp volatile unsigned char 0x80000004 ackp volatile unsigned char 0x80000000 E datap volatile unsigned int 0x80000008 10 VN for i20 i 10 itt 12 datap data 13 data t t 14 15 redp 1 16 while ackp 17 18 reqp 0 1 9 while ackp 20 21 return 0 22 The memory mapped hardware software interfaces are included in lines 2 3 as pointers of the volatile type Such pointers are treated with caution by a compiler optimizer In particular no assumption is made about the persistence of the memory location that is being pointed at by this pointer The pointers are initialized in lines 7 9 with values cor responding to the memory addresses used in the GEZEL description GEZEL V2 0 Simulator User Manual 44 Cosimulating GEZEL with Instruction Set Simulators August 1 2005 The gplatform tool In lines 11 20 a simple loop is shown that executes the software side of the two phase full handshake protocol Lines 15 and 18 illustrate why the volatile declaration is impor tant An optimizing C compiler would conclude that reqp is simply overwritten in the body of the loop In addition the resulting value is loop invariant and can be hoisted out side of the loop body The resulting optimized code would w
54. eatest common divisor GCD 1 dp euclid in m in n in ns 16 2 out gcd ns 16 3 reg m n ns 16 4 reg done ns 1 Di reg factor ns 16 6 T s sfg init m m in n n in factor 0 done 0 8 Sdisplay cycle Scycle m m in n 2 sfg flags done m 0 n 0 10 sfg shiftm m m gt gt 1 Tis sfg shiftn n n gt gt 1 12 sfg reduce m m gt n m n m T3 n n gt m n m n 14 fg shiftf factor factor 1 15 fg outidle gcd 0 16 sfg complete gcd m gt n m n lt lt factor T Sdisplay cycle Scycle gcd gcd 18 19 20 fsm euclid_ctl euclid 2I initial s0 22 state sl s2 29 24 sO init outidle gt sl 25 sl if done then complete 26 else if m 0 amp n 0 then reduce outidle flags 27 else if m 0 amp n 0 then shiftn outidle flags 28 else if m 0 amp n 0 then shiftm outidle flags 29 else shiftn shiftm 30 shiftf outidle flags 34 s2 outidle s2 32 33 34 dp test euclid out m n ns 16 3 5 sfg run 36 m 2322 3 n 654 38 HD v 40 hardwired h test euclid test euclid run 41 42 dp euclid_sys 43 sig m n gcd ns 16 44 use euclid m n gcd 45 use test euclid m n n in S2 sl sl sl S1 GEZEL V2 0 Simulator User Manual Overview August 1 2005 The Euclid algorithm 46
55. ect a description style Structural Behavioral The expressions in a data include both scheduling contain only data pro path description as well as data process cessing ing The expressions ina data are harder to reuse with are easier to reuse with path description different schedules different schedules GEZEL V2 0 Simulator User Manual 27 Creating sequential designs The state assignment of the controller This writing style is use ful for August 1 2005 is chosen by the designer high throughput or area sensitive designs that require full designer control A Galois Field multiplier is chosen by the logic synthesis tool cycle true descriptions that put as much work as possible on the logic syn thesis tools 3 5 A Galois Field multiplier The look and feel of a structural vs behavioral description style is illustrated by imple menting a 4 bit bit serial Galois Field Multiplier in each of the description styles A Galois Field Multiplier multiplies elements of the field GF 2 This finite field consists of 16 elements and is created out of the 2 element field GF 2 The representation of the elements is done using four bits in terms of a field basis The field basis that will be used is the polynomial basis in which the individual bits represent coefficients of a polynomial In this case the four bits aga a5a4 are assumed to be coefficients of a polynomial g t
56. ed number When the target type has enough bits no precision will be lost For two s complement signed numbers a concept called sign extension is applicable Sign extension preserves the sign of a two s complement number when the wordlength increases When the tar get type has insufficient bits some precision can be lost Bits are chopped off at the most significant side The resulting bitpattern is interpreted as a signed unsigned num ber of the targeted wordlength For example if a is ns 8 and holds the value 7 and b is tc 4 then b tc 3 a will leave the binary pattern 0b1111 in b which is interpreted as 1 typespec expr Converts the type of expr to typespec Unary Operations A unary operation has a single operand There is a bitwise NOT operator and a negation operation see Bitwise Operations and Arithmetic Operations Bit Selection Operation A bit selection operation extracts part of a bitpattern in a word There is a single bit for mat as well as a bitvector format a n Returns bit n from a asa ns 1 number n has to be a pos itive constant If n is bigger than the wordlength of a 0 is returned a m n Return bitvector from bit m to bit n n gt m from aasa ns n m 1 number n and m have to be positive constants If a bit index goes out of the wordlength range of a 0 is returned for that bit Lookup Table Operation A Lookup Table Operation offers access to a constant array w
57. ent and Selection GEZEL V2 0 Simulator User Manual 10 Creating hardwired datapaths August 1 2005 Expressions The assignment operation updates the value of a signal or register The selection opera tion conditionally extracts the value of a signal or register a expression The assignment operations assigns the value of epxres sion into a At the moment of assignment the value of expression is casted in a cfr the casting operation pou s The selection operation implements choice The value of b is evaluated When it is nonzero the expression evaluates to c When it is zero the result is d Bitwise Logical Operations Bitwise logical operations combine two bitpatterns into a new bitpattern The bits at corresponding indices are combined using a single bit logical operations The logical operations are Inclusive Or Exclusive Or and And bloc The bit pattern in b is IOR ed with the bit pattern in c be The bit pattern in b is XOR ed with the bit pattern in c b amp c The bit pattern in b is AND ed with the bit pattern in c eb The bit pattern in b is inverted This operation has higher precedence than all two operand operations Comparison Operations Comparison operations compare the value of two expressions and yield a true or false result The value true or false is represented as a 1 bit unsigned number ns 1 with 1 indicating true and 0 indicating false a True if the value of a is equal to the value of
58. erbauwhede Domain specific Co design for Embedded Security IEEE Computer April 2003 P Schaumont I Verbauwhede Domain specific tools and methods for application in security processor design Kluwer Journal for Design Automation of Embedded Systems pp 365 383 November 2002 B 2 Publications on applications that have used GEZEL S Yang P Schaumont I Verbauwhede Microcoded Coprocessor for Embedded Secure Biometric Authentication Systems International Conference on Hardware Software Codesign and System Synthesis September 2005 B C Lai P Schaumont I Verbauwhede Energy and Performance Analysis of Mapping Parallel Multi threaded Tasks for An On Chip Multi Processor System IEEE Interna tional Conference on Computer Design ICCD 2005 October 2005 I Verbauwhede P Schaumont Skiing the embedded systems mountain accepted for publication in ACM Transactions on Embedded Computing Systems Special issue on embedded systems education P Schaumont D Hwang I Verbauwhede Platform based design for an embedded fin gerprint authentication device accepted for publication in IEEE Transactions on Com puter Aided Design of Integrated Circuits and Systems P Schaumont B C Lai W Qin I Verbauwhede Cooperative multithreading on embed ded multiprocessor architectures enables energy scalable design Proc 2005 Design Automation Conference DAC 2005 June 2005 K Tiri D Hwang A Hodjat B C
59. erbound for the amount of cycles to simulate By default the cosimulation will run until all instruction set simulators have completed exe cution of their application program these stopping conditions may vary from core to core Example 1 Cosimulation with a single ARM Here is a small example of a hardware software cosimulation consisting of a synchro nized data transfer Below is the hardware description in GEZEL LISTING 12 A GEZEL description of hardware side of hardware software handshake 1 ARM core running program listingl13 2 ipblock myarm 3 iptype armsystem 4 ipparm exec listingl3 35 6 7 Cosimulation interfaces 8 ipblock bl in data ns 8 9 iptype armsystemsink 10 ipparm core myarm 11 ipparm address 0x80000000 22 3 13 ipblock b2 out data ns 8 14 iptype armsystemsource 15 ipparm core myarm 16 ipparm address 0x80000004 GEZEL V2 0 Simulator User Manual 41 Cosimulating GEZEL with Instruction Set Simulators August 1 2005 The gplatform tool 17 18 ipblock b3 out data ns 32 19 iptype armsystemsource 20 ipparm core myarm 21 ipparm address 0x80000008 PA 23 24 hardware receiver 25 dp D2 in req ns 8 out ack ns 8 in data ns 32 26 reg reqreg ns 8 27 reg datareg ns 32 28 sfg sendack 29 ack 1 30 Su sfg sendidle 32 ack 0 235 34 sfg read 35 reqreg req
60. es 10 34 The first five loca tions of the RAM are first written with an increasing number sequence and next these five locations are read out again 8 2 Catalog of Library Blocks The following table enumerates the different library blocks Some library blocks such as cosimulation interfaces are part of a particular simulator configuration Library Blocks in the GEZEL Kernel available for all programs ram Function The RAM block implements a RAM cell with separate read and write control strobes and a separate data input and data output One read and one write access is possible per clock cycle IO address input ns log2 size holding the address for the RAM wr input ns 1 write asserted high rd input ns 1 read asserted high idata input ns wl input data bus odata output ns wl output data bus Parameters wl wordlength of data bus wl gt 0 size number of RAM locations tracer Function The tracer block implements equivalent functionality as the Strace directive and records the values of a signal into a file at each clock cycle IO data input ns userdefined data input Parameters file quoted string with filename wl wordlength of numbers in file rom Function Contributed by A V Lorentzen and J Steensgaard Madsen DTU Denmark s Technical University Originating from an implementation of Andrew Tanenbaum s Mic 1 that con forms to Ray Ontko s Java simulator for it The ipblock may represent an initi
61. esult cannot be stored in a GEZEL will throw out bits at the most significant side of the result overflow If b c is 260 then the resulting value in a will be 4 260 256 4 In some expressions intermediate values will occur In the above expression b c is such an intermediate value A more obvious example is a b b c c Here brackets are used to indicate the order in which this expression is to be evaluated First the sums b b and c c are obtained These two intermediate values are combined and assigned to a Intermediate values need a type too GEZEL uses a default type rule to choose the type of intermediate results This is rule con sists of two parts a the result of an operation is the maximum wordlength of the oper ands and b if any of the operands is signed then the result will be signed as well There are exceptions to this rule which will be indicated later Expressions combine signals and registers with operators Operators have a precedence a preferred order of evaluation For example in an expression such as a b t bse NE the multiplications will be performed before the additions because multiplication has a higher precedence than addition Precedence rules can be modified by using round brackets The following bullets introduce the different operators that can be used in expressions starting at the ones with low precedence and going up to high precedence operations Assignm
62. fined and available in the datapath we can write Sdisplay The value of a b is a b GEZEL V2 0 Simulator User Manual 33 Simulating standalone GEZEL designs August 1 2005 Simulation directives The default printing format of a and b is hexadecimal This format can be changed using a modifier directive Values can be printed in hexadecimal hex decimal dec or binary Sbin After a modifier directive is used it stays in effect until a new one is applied Thus for the following three values the first two will be hex while the second two will be in binary Sdisplay a b Sbin atb a b Apart from strings and expressions also a number of meta variables are available Such variables cannot interact with registers or signals but they can be printed to reveal runt ime dependend information For this purpose meta variables are formatted as directives Scycle returns the current cycle count dp returns the name of the datapath in which the display directive is used And sfg_ returns the name ofthe s g in which the display directive is used Control directives affect the course of the simulation There is one control directive finish It can be used inside of a signal flow graph s definition and will terminate the simulation when this s g 1s executed Trace directives are used record stimuli files Such a directive is used to create test vector files for future simulations The format for a trace directive 1
63. g t azt F atz 3s a t a0 EQ 3 The multiplication of two elements out of the field GF 2 is defined by the multiplication of two polynomials a t and b t modulo the irreducible field polynomial d t This is a polynomial of degree 4 The simplest irreducible field polynomial for GF 2 is d t t t 1 EQ 4 As an example consider the multiplication of a 1001 with b 0110 In polynomial format this becomes c t a t b t mod d t EQ 5 c t t 1 t 1 mod t t 1 EQ 6 c t C t 4 2 1 mod t t 1 EQ 7 The coefficients of this multiplication are elements of the field GF 2 and they are evalu ated with modulo 2 arithmetic Thus the multiplication result can be simplified to c t t 1 t t 1 t 1 mod t 9 t 1 2 t 1 EQ 8 The multiplication result corresponds to the bitstring c 0011 The next two listings implement this algorithm in a bit serial fashion That is the multipli cations of the b operand execute bit by bit and accumulate into the a operand When the partial results exceeds 4 bits the resulting polynomial is reduced modulo f t 1 This is done by modulo 2 addition of this polynomial to the partial result GEZEL V2 0 Simulator User Manual 28 Creating sequential designs August 1 2005 A Galois Field multiplier LISTING 7 A Galois Field multiplier in behavioral style description 1 dp D in fp il i2 ns 4 out mul
64. h to a GezelOutport class GEZEL is assumed to be configured as a slave simulator i e the GEZEL clock will be controlled out of JAVA A GezelModule is initialized using a GEZEL source file as argument This file is parsed during instantiation of the JAVA object Once the object is instantiated the GEZEL simulation can be advanced one clock cycle by calling t ick In the present implemen tation of the cosimulation interface only a single GezelModule class is allowed per JAVA program This class can of course contain multiple FSMD modules that each have their own interface to the JAVA program class GezelModule public native void loadfile String filename public native void tick GezelModule String filename loadfile filename A GezellInport is a communication channel from JAVA to GEZEL During construc tion of such a port a symbolic name must be given to this part This symbolic name can be referred to from within GEZEL to link up to corresponding library block Once the port class is created data can be send to GEZEL using the write method Communication is always immediate and will be available to GEZEL during the next clock cycle class GezelInport int portId static int glbPortId public native void portname String portname public native void write int n GezellInport String _portname portlId glbPortId GEZEL V2 0 Simulator User Manual 60 Cosimulating GEZEL with JAVA A
65. he value obtained when reading from the register The next value is the value at the input of the register so it is the value that is being written into the register A register is created in the same way as a signal but uses the reg keyword A 16 bit unsigned register for example is created as reg r ns 16 The register lies at the basis of clock cycle true behavior There are implicit simulation semantics tied to the register At the start of each clock cycle the next value of the previ ous clock cycle is copied into the current value of the current clock cycle In between clock edges the next value is updated based on the current value constants and inputs This way it is possible to create clock cycle true descriptions without mentioning the clock explicitly GEZEL V2 0 Simulator User Manual 9 Creating hardwired datapaths August 1 2005 Expressions The initial value of a register is zero 0 while the initial value of a signal is undefined 2 2 Expressions Expressions enable calculations with signals and registers Expressions are formed using operators that reference the names of signals and registers For example an addition of two signals b and c into signal a looks like a btc When a has insufficient precision to hold all possible combinations of the sum b c precision loss can occur For example assume the following types for a b and c sig a b c ns 8 Clearly when D c is bigger than 256 the r
66. hich is defined earlier in the code The lookup table content needs to be defined first after which it can be accessed using a lookup table operation A Lookup Table definition is done by enumerating all the elements in the lookup table in a comma separated list as follows GEZEL V2 0 Simulator User Manual 12 Creating hardwired datapaths August 1 2005 Signal flow graphs lookup a ns 8 15 22 36 Ox4f This defines a lookup table a which holds elements of type ns 8 The table holds 4 elements The element at index position 0 is 15 and the element at index position 3 is Ox4f 79 The lookup table access operation simply access the array using the index in between round brackets For example to access the third element of a one would use a 2 2 3 Signal flow graphs The cycle true execution model of GEZEL expresses concurrency by allowing multiple expressions to be evaluated in the same clock cycle A set of expressions that execute together in the same clock cycle are grouped together in a signal flowgraph Consider the design of a Viterbi Butterfly operation a well known operation in convolu tional decoding This operation processes tuples of data according to an operation called add compare select y min d a d5 a EQ 1 y2 min dy a d a EQ 2 Assume the following set of signals and registers intermediate signals input and output tuple Sig al sl a2 s2 ns 8 reg dl d2 yl y2
67. in specific micro architectures GEZEL can help with the design of multiprocessor networks and embedded hardware It has also been used as a teaching tool in class projects on VLSI architecture design Highlights of the environment are as follows A specialized language called GEZEL allows compact representation of the micro architecture of domain specific processors GEZEL uses cycle true semantics with dedicated modeling of control structures FSMD e The simulation environment is scripted for fast edit load simulate cycles The simulation back end is an open C library that enables easy integration of GEZEL into different host environments Cosimulation interfaces are available to sev eral instruction set simulators as well as to SystemC and Java GEZEL can be customized with user supplied custom library blocks in C Those blocks can be provided as dynamic libraries those providing an excellent basis for exchange of intellectual property simulation models e A design in the GEZEL language can be automatically translated to synthesizable code In addition extra support for stimuli capture is available so that GEZEL simulations can be replayed on the hardware models As a standalone environment it works as a hardware exploration environment When linked with an instruction set simulator it becomes a co design environment A typical application of GEZEL would be the design of a coprocessor shown in Figure 1 1 In thi
68. ion 2 6 on page 17 The next program fills up the RAM module defined above and next reads it out again LISTING 22 A RAM library block testbench 1 ipblock M in address ns 5 2 in wr rd ns 1 3 in idata ns 8 4 out odata ns 8 DY iptype ram 6 ipparm w1 8 Js ipparm size 32 8 9 10 dp tmac out address ns 5 ds out wr rd ns 1 T2 out idata ns 8 13 in odata ns 8 14 reg ar ns 5 qus reg idr odr ns 8 16 T 75 sfg write wr 1 rd 0 idata idr odr odata address ar 18 display cycle ar ar idata idata 19 20 sfg read wr 0 rd 1 address ar odr odata idata idr 21 display cycle ar ar odata odata 22 Z3 sfg incadr ar ar 1 idr idr 1 24 sfg clraddr ar 0 25 3 26 27 fsm ftmac tmac 28 state sl 2 9 initial s0 30 sO if ar 4 then write clraddr gt sl Su else write incadr gt s0 32 sl if ar 4 then read clraddr gt s50 33 else read incadr gt sl 34 BO 36 dp sysRAM EHA sig adr ns 5 38 sig w r ns 1 39 sig i o ns 8 40 use M adr Wy Xy 16 0 41 use tmac adr w r i o 42 43 GEZEL V2 0 Simulator User Manual 65 GEZEL Library Blocks August 1 2005 Catalog of Library Blocks 44 system S 45 SySRAM 46 The testbench that drives the RAM module is included in lin
69. itional sequencing GEZEL allows a description close to Figure 1 4 The program in Listing 1 shows a proces sor that evaluates the GCD with one iteration per cycle The processor has a data process ing part dp and a control part sm It also has a test bench that generates two test values The test bench is connected to the processor in the system interconnect descrip tion The datapath description is in lines 1 20 This datapath has two 16 bit input ports m in and n in and one 16 bit output port gcd In contrast to Figure 1 4a this is not a struc tural description The datapath consists of a number of signal flow graphs indicated with sfg An sfg expresses a single clock cycle of behavior on the datapath You can think of an sfg as an instruction that can be executed by the datapath The signal flow graphs col lect expressions that operate on the datapath registers created in lines 3 6 GEZEL V2 0 Simulator User Manual 5 Overview August 1 2005 The Euclid algorithm The controller is shown in lines 22 32 This is a finite state machine description that has three states one of which is the initial state Line 25 shows an unconditional state transi tion starting at state sO and ending at state s1 During this state transition the datapath will execute sfg init and outidle A conditional state transition is expressed using if then else logic such as shown in lines 26 30 LISTING 1 A GEZEL Program to evaluate gr
70. latform tool 2 enum ins_idle ins hello 3 void sayhello char d 4 Pl d Da PO ins hello 6 PO ins idle dev 8 void terminate 9 special command to stop simulator 10 P3 0x55 de vy 12 void main 13 sayhello 3 14 sayhello 2 IROA sayhello 1 16 terminate 17 The program transfers a values to the GEZEL coprocessor using sayhello in lines 3 8 The include file on line 1 is specific for this 8051 processor Unlike a standard C pro gram a C program on the 8051 never terminates and there is no concept of standard C library Consequently there are no printf functions and so on these would be of little use within a micro controller The include file 8051 h contains several defintions including those of ports PO to P3 The special function terminate in lines 8 to 11 is used to stop the cosimulation It writes the hex value 55 to port P3 this is a specific con vention for this simulator The simulation proceeds as follows First compile the 8051 program using the Small Devices C Compiler sdcc sdcc listingl8 c The compiler creates several intermediate files as well as a hex dump format of the com piled code in Intel Hex format 1isting18 ihx Next run the gplat form simulator to execute the cosimulation gt gplatform lsitingl7 fdl i8051system loading executable listing18 ihx OxFF 0x03 OxFF OxFF 0x01 0x03 OxFF OxFF 9612 Hello
71. lating GEZEL with Instruction Set Simulators 5 1 Cosimulation Interfaces and Interface Protocols 5 2 The gplatform tool 5 3 Things to keep in mind with cosimulation 6 0 Cosimulating GEZEL with SystemC 6 1 Cosimulation Setup 62 GEZEL SystemC Cosimulation Interfaces 63 A FIR filter July 18 2005 9 41 am 64 Why GEZEL with SystemC 7 0 Cosimulating GEZEL with JAVA 7 1 The GEZEL JAVA Native Interface 72 Asmall example 7 3 Cosimulation with AVRORA 8 0 GEZEL Library Blocks 8 1 Library Blocks Definition 8 2 Catalog of Library Blocks 8 3 Custom Library Blocks 8 4 Other member functions for aipblock Appendix A Installing GEZEL Appendix B References 58 60 60 61 63 64 64 66 70 75 76 85 July 18 2005 9 41 am Listings Listing 1 A GEZEL Program to evaluate greatest common divisor GCD 6 Listing 2 A 2 bit counter as a hardwired datapath 15 Listing 3 A number of erroneous datapaths 17 Listing 4 A 4 input AND gate using structural hierarchy and three 2 input AND gates 17 Listing 5 A 4 tap decimating averager using a sequencer 21 Listing 6 The Bresenham line drawing algorithm as an FSMD 24 Listing 7 A Galois Field multiplier in behavioral style description 29 Listing 8 A Galois Field multiplier in structural style description 29 Listing 9 A cycle count printing program 32 Listing 10 A cycle count printing program as a script 33 Listing 11 A Galois Field multiplier testbench 35 Listing 12 A GEZE
72. length encoder in pseudocode as follows intialize previous input data not a number runlength 0 execute read input data tuplenum tupledata 0 0 if input_data previous_input_data runlength runlength 1 if runlength maxlen tuplenum tupledata runlength input data runlength 0 else if runlength 0 tuplenum tupledata runlength previous data runlength 1 previous_input_data input_data write tuplenum tupledata Step 2 Design the C implementation We are now ready to design the block into a GEZEL library block Library blocks are derived from a baseclass aipblock This block has a number of virtual functions that can be user defined in derived classes class aipblock protected enum iodir input output public vector lt gval gt ioval aipblock char _name virtual aipblock virtual void run virtual void setparm char name virtual bool checkterminal int n char tname iodir dir virtual bool needsWakeupTest virtual bool cannotSleepTest virtual void touch GEZEL V2 0 Simulator User Manual 71 GEZEL Library Blocks August 1 2005 Custom Library Blocks The vector ioval contains the values appearing on the actual ports The first element of this vector corresponds to the first port the second element to the second port and so on The function run is called each clock cycle to e
73. lowing GEZEL definition creates a RAM block of 32 positions of 8 bit words ipblock M in address ns 5 in wr rd ns 1 in idata ns 8 out odata ns 8 iptype ram ipparm w1 8 ipparm size 32 A library block with name is created It defines five ports including the address bus address write and read control strobes wr rd an input data bus idata and an output data bus odata Next is an indication of the library block type in the ipt ype statement Then a number of library block parameters can be given These are dependent on the type of the library block For a RAM the worldlength of the databus w1 and the number of memory loca tions size can be specified GEZEL will issue a warning when a parameter field is found that is not supported by the library block The names as well as the order of the ports of a library block are determined by the type For a particular type there is only one ordered set of names with each port having a pre defined direction For a library block of type ram for example the first port must be called address and it must be an input GEZEL will issue a warning when there is a mismatch GEZEL V2 0 Simulator User Manual 64 GEZEL Library Blocks August 1 2005 Library Blocks Definition detected Once a library block is instantiated it can be used like any other datapath mod ule Library blocks can be included within other datapaths using the use statement Sect
74. lways signal flow graph but it can have multiple named sig nal flow graphs GEZEL V2 0 Simulator User Manual 14 Creating hardwired datapaths August 1 2005 Datapath modules A datapath is the smallest GEZEL unit that can be simulated So subsequent examples will be fully self contained programs rather than snippets Here is an example of a 2 bit counter as a hardwired datapath LISTING 2 A 2 bit counter as a hardwired datapath 1 dp counter out value ns 2 2 reg c ns 2 Su always 4 value c Ja C 1 6 display Cycle cycle counter value Ta 8 Di 10 system S lil counter 12 This datapath has a single output port called value An output port also has a type indi cated after the colon following the port name The ports define the outline of the datapath The only way an outsider can access the datapath is by reading writing values on the datapath ports On line 2 we create a 2 bit register This register is local to the datapath counter It can be accessed only from within the datapath On line 3 7 we define a signal flowgraph called run It contains besides expressions also a directive on line 6 A GEZEL directive does affect how the simulator behaves but it does not affect the simulation outcome In this case we are using the display directive which is used to print out values on the datapath One special variable that is accessed is called Scycle Thi
75. mode mechanism of the GEZEL simulator Step 3 Integrate the block and test it The final step is to integrate the C code of the library block into GEZEL We show one possible way to integrate the block as part of the GEZEL code GEZEL supports dynamically linked library blocks You can compile the C code into a shared library At runtime the GEZEL kernel will link in these library blocks at the moment you need them Compilation into a shared library block proceeds as follows In these commands BUILD must be substituted with the path the the GEZEL installation gt g fPIC 03 Wall c IBUILD include gezel iprle cc gt g shared 03 Wl rpath Wl BUILD lib iprle o BUILD lib libi pconfig so BUILD lib libfdl so lgmp ldl o librle so This will create a shared library librle so When you run the GEZEL simulation fdlsim or gplatform this library must be available in the directory where the simulation is run It will be automatically read in at the moment the rle ipblock is used by your simulation An example GEZEL program that uses the runlength encoder program is shown LISTING 24 A runlength encoder testbench 1 ipblock my_rle in data ns 8 2 out tuplenum ns 8 3 out tupledata ns 8 4 iptype rle oy ipparm maxlen 32 62 ym 8 dp senddata out data ns 8 9 in tuplenum ns 8 10 in tupledata ns 8 dd lookup T ns 8 1 1 1 3 4 4 6 6 6 6 12 reg c n
76. multiple sfg When the same functionality needs to be migrated from a behavioral to a structural description these multiplexers need to be introduced by hand using the ternary operator veo bos ay The absence or presence of the control step concept also has an important implication on the operation to resource binding Indeed in a structural description each operation is executed at each clock cycle Therefore each operation will reguire an individual opera tor The word operator indicates the resource that implements an operation In a behav ioral description several operations can share the same operator provided that these operations are executed in different control steps The GEZEL code generator creates VHDL code in such a way that this sharing is possible Still there are design cases in which structural descriptions are preferable over behavioral ones In particular when creating highly constrained implementations such as very fast or very area sensitive hardware it can be necessary to control all aspects of the implementa tion Thus any design can be created in either design style structural and behavioral Which of the two description styles is the better one The answer to this question depends on the actual design case and on the designer Both have their strengths and weaknesses and ultimately it is the designer who must select the better option Here a number of statements that illustrate a few design considerations to sel
77. n Simulator throughpu 1 cycles 0 024 seconds t 0 061291665 mhz A 6 Catalog of examples Tool Example Function gezel aes Advanced Encryption Standard block bresen Example of a Bresemham line drawing algorithm euclid Euclid s GCD algorithm gf8inv Galois Field inversion block with subfields ipchecksum Checksum evaluation block for IP packets Ifsr Linear Feedback Shift Register ramblock Illustration of writing and reading into a RAM ipblock scripted Example of alternative invocation of fdlsim gplatform arm2arm Two way handshake in a dual ARM system gfmul 8051 based GF multiplier connected to an ARM driver aes8051 AES coprocessor attached to an 8051 core aesarm AES coprocessor attached to an ARM core euclid GCD coprocessor attached to an ARM core ramprobe An example of the probing function to query the contents of a RAM ipblock out of software running on the ARM cyclecount An example of making GEZEL print out current cycle count in a cosimulation hello51 Simple handshake on a 8051 core helloarm Simple handshake on an ARM core ssidehsk One way handshake in a dual ARM system java avroral Serial to parallel conversion in GEZEL as AVR coprocessor avrora2 Example of port input output on an AVR platform counter A GEZEL counter counter2 A JAVA readable GEZEL counter counter3 A JAVA readable and controllable GEZEL counter euclid Euclid s algorithm as a GEZEL coprocessor systemc accum Multiply accumulate in GEZEL called o
78. ns it is best to study one of the cosimulation interfaces of the GEZEL tools For example file arm itf cxx in armcosim Listing 23 shows how to program the runlength encoder as a derived class from the base class aipblock LISTING 23 A runlength encoder library block for GEZEL dinclude ipblock h 1 V 3 class rle public aipblock 4 int previous data value 5 int runlength 6 int maxlen 7 public 8 rle char name aipblock name 9 previous data value 1 10 runlength 0 ATs maxlen 256 T2 13 void run 14 ioval 1 assignulong 0 1155 ioval 2 assignulong 0 16 if ioval 0 toulong unsigned previous data value 17 runlength runlength 1 GEZEL V2 0 Simulator User Manual 72 GEZEL Library Blocks August 1 2005 Custom Library Blocks 18 if runlength maxlen 19 ioval 1 assignulong runlength 20 ioval 2 assignulong ioval 0 toulong 21 runlength 0 22 23 else 24 if runlength 0 25 ioval 1 assignulong runlength 26 ioval 2 assignulong previous data value 27 28 runlength 1 2 9 30 previous data value ioval 0 toulong S 32 bool checkterminal int n char tname aipblock iodir dir E switch n 34 case 0 35 return isinput dir amp amp isname tname data 364 break S case 1 38 return isoutput dir amp amp isname tnam
79. ns 4 25 in mul st ns 1 3 out mul done ns 1 4 reg acc sr2 fpr rl ns 4 54 reg mul st cmd ns 1 6 sfg ini initialization 7 fpr fp 8 Ed il 95 sr2 i2 10 acc 0 11 mul st cmd mul st T2 138 sfg calc calculation 14 sr2 sr2 lt lt 1 15 acc acc lt lt 1 rl amp tc 1 sr2 3 add a if b 1 16 fpr amp tc 1 acc 3 reduction if carry LY 18 sfg omul output inactive 19 mul acc 20 mul done 1 21 display done mul mul 22 23 sfg noout output active 24 mul 0 255 mul done 0 26 27 28 fsm F D 29 state sl s2 s3 s4 s5 30 initial s0 31 sO ini noout sl 32 s1 if mul st cmd then calc noout gt s2 33 else ini noout gt Sil 34 s2 calc noout gt s3 35 4 s3 calc noout gt s4 36 s4 calc noout gt s5 37 s5 ini omul sl 38 LISTING 8 A Galois Field multiplier in structural style description 1 dp D in fp il i2 ns 4 out mul ns 4 2 in mul_st ns 1 3x out mul done ns 1 4 reg ctl ns 5 Ga reg acc sr2 fpr ri ns 4 6 f always 8 ctl mul st 1 ctl lt lt 1 one hot control 9 fpr fp 10 rl il 11 sr2 ctl 0 12 sr2 lt lt 1 GEZEL V2 0 Simulator User Manual 29 Creating sequential designs August 1 2005 12 acc ctl 0 0 acc lt lt T 13 rl amp tc 1 14 fpr
80. o see Simplicity GEZEL has simple FSMD semantics easy to learn and to remember Sim ple is not always better but if the task is well defined as the creation of a micro archi tecture using FSMD then GEZEL may be just the tool you need Deterministic Simulation GEZEL hardware does not and cannot generate race con ditions A semantically correct GEZEL model will never generate an X during hard ware simulation GEZEL V2 0 Simulator User Manual 59 Cosimulating GEZEL with JAVA August 1 2005 The GEZEL JAVA Native Interface 7 0 Cosimulating GEZEL with JAVA GEZEL supports cosimulation with JAVA by means of a few native interface classes This is useful if you need to integrate GEZEL into a JAVA based simulation environment In this chapter the native interface classes are presented as well as a few examples Before you start working with JAVA make sure you have correctly set up a working JAVA environment and that you have enabled to JAVA cosimulation capabilities of GEZEL See Section A 4 on page 80 7 1 The GEZEL JAVA Native Interface In JAVA the interface between GEZEL and JAVA is based in three classes GezelMod ule enables to load GEZEL code and GezelInport and GezelOutport enable communication for writing to GEZEL and reading from GEZEL respectively In GEZEL the interface between GEZEL and JAVA is based on two library blocks one that will attach to a GezelInport class and another one that will attac
81. ocation you will need to define CPPFLAGS and LDFLAGS as arguments to configure For example assuming the GMP library 1ibgmp a so is installed under opt gmp 1ib and the include files for GMP are under opt gmp include then you would run configure CPPFLAGS I opt gmp include LDFLAGS L opt gmp lib GEZEL V2 0 Simulator User Manual 76 August 1 2005 If you want to select an installation directory use the prefix option of configure The default installation directory is the build subdirectory from where you installed the GEZEL source Use the help option in configure to see a list of available command line options Next type make followed by make install The default configuration will create the library the stand alone simulator and the code generation The standalone simulator is call fdlsim You can test the simulator on one of the examples in the test directory For example 8 cycles from the Bresenham vector generator application can be simulated using gt cd test gezel build bin fdlsim bresen fdl 8 Cycle 2 Plot point 5 5 2 1 Cycle 3 Plot point 5 5 1 0 Cycle 4 Plot point 5 5 0 1 Cycle 5 Plot point 5 5 1 2 Cycle 6 Plot point 5 5 2 3 Cycle 7 Plot point 5 5 3 4 Cycle 8 Plot point 5 5 4 5 A 2 gplatform Cosimulator GEZEL can be cosimulated with instruction set simulators using the C API on the backend of GEZEL Installing the ARM in
82. occurence of three runtime conditions During clock cycle N none of the datapath registers has changed state During clock cycle N none of the controllers has changed state e During clock cycle N none of the library blocks has indicated a change of state When all of these conditions are simultaneously true it is easy to see that the simulation result of clock cycle N 1 cannot produce a result that is different from clock cycle N Consequently the GEZEL simulator enters sleep mode If this happens in standalone sim ulation mode then the simulation might as well terminate because the simulator cannot leave sleep mode However the sleep mode will be useful in cosimulations in which a processor instruction set simulator can wakeup the GEZEL simulation dynamically GEZEL V2 0 Simulator User Manual 31 Simulating standalone GEZEL designs August 1 2005 The fdlsim tool 4 2 The fdlsim tool The standalone simulator for GEZEL is call dlsim The command line for dlsim is as follows fdlsim d lt design fdl gt lt cyclecount gt Parameters in between square brackets are optional When the design filename is not pro vided fdlsim will read the design from standard input until an end of file is encoun tered The d is a debug flag When it is enabled the simulator provides a more detailed account of the activities during simulation When the command line executes the GEZEL kernel will first parse the design If any
83. p www ee ucla edu schaum gezel GEZEL can be downloaded as a source only package A precompiled package is available for Linux as well The source package consists of several components A standalone simulator for GEZEL code e A cosimulator for SystemC 2 0 1 A platform simulator for ARM and 18051 A cosimulator for JAVA code A test subdirectory with several examples for each cosimulator After downloading the package uncompress it using t ar gt tar xfvz gezel 2 x tar gz On Linux gt cd gezel 2 x A 1 Standalone tools GEZEL is written in C and compiles under a standard GNU build environment using the GNU C compiler GCC The package has automatic configuration Apart from GCC you will also need the following e GNU Multiprecision Library http www swox com gmp e The Bison YACC parser generator http www gnu org software bison bison htm1 in case you make modifications to the fa1 y parser e The Flex Lex lexical analyzer http www gnu org software flex in case you make modifications to the d1 11 scanner or if the installed version of flex is imcompatible with the version installed on the build machine In most cases including common Linux distributions these tools will already be avail able on your system and you do not need to download any extra packages To create the makefiles on your system execute configure If the GNU Multiprecision library is not installed in a standard l
84. parsing errors are encountered the simulation will be aborted If the design is parsed suc cessfully the simulation will run It will terminate on one of the following conditions a the target cycle count is reached b a runtime error occurs or c the finish directive is executed The target cyclecount is a positive number long or the value 1 to indicate infinity i e the target cycle count will never be reached There are three alternative methods by which the GEZEL simulator can parse and simu late GEZEL designs Let us consider the following code which simply counts clock cycles and prints them on the screen LISTING 9 A cycle count printing program 1 dp mydp 2 always Sdisplay Cycle S cycle SPR 4 5 system S 6 mydp 7 A first method of simulation is to use the command line The program can be run as fol lows to execute 3 clock cycles gt fdlsim listing9 fdl 3 Cycle 1 Cycle 2 Cycle 3 A second method is use standard input to The first is to use the command line as shown above The second is to use standard input and pipe the design into the simulator gt cat listing9 fdl fdlsim 3 Cycle 1 Cycle 2 Cycle 3 GEZEL V2 0 Simulator User Manual 32 Simulating standalone GEZEL designs August 1 2005 Simulation directives The third method is to make use of the scripting feature of the shell In that case the loca tion of dlsim must be provided in the code Assume f
85. plains the FSMD model of computation FSMD modeling will be covered later A model of computation helps to support a particular design style by providing simulation semantics to a program The model of computation of a C program is that of a procedural sequentially executed language The model of computation used for GEZEL is hardware oriented and is called FSMD Finite State Machine with Datapath Figure 1 2 illustrates that GEZEL designs contain of a set of modules connected by wires A module can be an FSMD or else a library block An FSMD is expressed in the GEZEL language using FSMD semantics A library block on the other hand is a build in simula tion primitive provided by the GEZEL simulator Memory cells and cosimulation inter faces are examples of library blocks An FSMD is a cycle true model of a datapath with a controller The datapath contains registers and hardware operators and the controller sequences operations in the datapath Consider first a cycle true simulation of a hardware module with only registers and opera tors and no controller i e a fully hardwired datapath Each register in the module is simu lated in terms of two values one being the next state value at the register input and the other being the state value at the register output A cycle true hardware simulation algo rithm takes two simulation phases per clock cycle During the first phase the next state of GEZEL V2 0 Simulator User Manual 2 Over
86. portant motivation for developing FSMD models instead of plain hardwired datap aths is that an FSMD allows to express operation sharing in an elegant way Consider the descriptions in phase0 phase12 and phase3 They specify two assignments on an accumulator register and three assignments to an output port without the use of a multi plexer When the same behavior would be represented in a single s fg it would look like this GEZEL V2 0 Simulator User Manual 22 Creating sequential designs August 1 2005 Finite state machines reg phase ns 2 sfg singlephase acc phase 0 i acc i o phase 3 acc i gt gt 2 0 phase phase 1 This description style gives you precise control over how the implementation will look like but requires more modeling as the control operations have to be written down explic itly as expression We will discuss the tradeoff between single sfg multiple sfg descrip tion styles in Section 3 4 Choosing a controller style on page 27 3 3 Finite state machines A Finite State Machine implements conditional control sequencing on a datapath The control model is captured by a state transition graph A Finite State Machine can be in a well defined number of states One of these states is the initial state it is the state the FSM is in when it first initializes A Finite State Machine will take one state transition per clock cycle During this state tran sition a datap
87. pports predesigned library blocks At the outside these look like datapath mod ules and they can be used in the same way However their inside is not written in GEZEL code Instead the behavior of library blocks is written in C and compiled directly into the GEZEL kernel This enables blocks that run much faster than cycle true models in GEZEL for example by raising the simulation abstraction level It also allows to intro duce features in a GEZEL simulation that are not supported in GEZEL code such as spe cial types of IO or host system function calls This chapter presents the use of GEZEL library blocks This includes the general model ing and usage properties of library blocks as well as a catalog of available library blocks And finally you can also introduce your own library blocks into the GEZEL kernel 8 1 Library Blocks Definition GEZEL library blocks are created with the keyword ipblock They define three ele ments First they define their IO interface just as a datapath module does Second they define their type And third they define an optional number of parameters Consider the RAM library block as an example This block is part of the standard configuration GEZEL kernel and is used to simulate a RAM memory It has an outline that correponds to RAM cell it define an address bus a data input and output bus and read write control lines The RAM library block is parametrizable in size and wordlengh as well The fol
88. presents the JAVA inter face Lines 10 13 The javasource library block transports data from JAVA to GEZEL This particular block has the symbolic variable name myinput Line 12 The JAVA code that uses this counter block is shown in Listing 21 LISTING 21 JAVA driver for GEZEL counter 1 class counter3 2 public static void main String args 3 System loadLibrary gzljava gezel java interface 4 GezelModul m new GezelModule counter3 fdl Dig Gezellnport p new GezelInport myinput 6 7 p write 5 8 for int i20 i lt 10 i 9 m tick EO TA 12 The JAVA GEZEL interface makes use of native class implementations which must be read in and linked at runtime A shared library gz1 java is loaded for this purpose at line 3 Lines 4 and 5 illustrate how a GEZEL module is instantiated and a communication channel is established The GEZEL file is parsed during construction of the GezelMod ule class Lines 4 10 give a small example how the GEZEL counter is exercised An increment value of 5 is provided and the GEZEL simulation is run for 10 clock cycles To compile and run this cosimulation first compile the JAVA code into a class file The class path is set up to point to the location of the native classes for the GEZEL interface This path will vary depending on the location where you have installed the GEZEL envi ronment gt javac classpath build share counter3 java You
89. put data ready 0 527 GEZEL V2 0 Simulator User Manual 56 Cosimulating GEZEL with SystemC August 1 2005 53 fsm cfir fir 54 initial s0 DO state sl s2 s3 s4 56 5 QGsO read noout phi0 gt sl 58 sl if rreset then read rst noout gt sl 59 else if rdy then read noout phil gt s2 60 else read noout phi0 gt sl 61 s2 noout phi2 gt 83 62 Qs3 phi3 shft read gt sl 63 57 64 65 interfaces 66 ipblock systemc reset out data ns 1 67 iptype systemcsource ipparm var reset 68 1 69 ipblock systemc input valid out data ns 1 70 iptype systemcsource ipparm var input data valid Yes 72 ipblock systemc sample out data tc 32 73 iptype systemcsource ipparm var sample 74 75 ipblock systemc_output_data_ready in data ns 1 76 iptype systemcsink ipparm var output data ready abu 78 ipblock systemc result in data tc 32 79 iptype systemcsink ipparm var result 80 81 82 dp sysfir 83 sig reset input valid output data ready ns 1 84 sig sample result tc 32 85 use fir reset input_valid sample output_data_ready 86 use systemc_reset reset 87 use systemc input valid input valid 88 use systemc sample sample 89 use systemc output data ready output data ready 90 use systemc_result result 9T ag 22 system S 934 sysfir 94 A
90. quence 1 In each of the controllers in the system hardwired sequencer FSM select the control step to execute Selection of the control step also chooses which sfg should be exe cuted and as a result which expressions should be executed in the evaluate phase of this clock cycle 2 For each datapath module evaluate the outputs and the inputs of the registers contained in that datapath The evaluation process makes use of all expressions which are enabled according to the active control step Also the evaluation process obeys data prece dences between signals and can trigger evaluation of dependent expressions if needed 3 Evaluate all ipblock library blocks The concept of library blocks is treated in Section 8 0 GEZEL Library Blocks on page 64 4 Evalute all Sdisplay trace and finish directives that appear inside of an sfg that is currently being executed Directives are discussed in Section 4 3 on page 33 5 Update all registers in the simulation by copying the next value to the current value This simulation algorithm shows the sequence of activities while the GEZEL simulator is in awake mode As this name suggests there is an alternate mode called sleep mode At runtime the GEZEL simulator switches automatically between these two modes based on the activities in your design In sleep mode none of the steps 1 to 5 discussed above are executed the simulator is effectively inactive Sleep mode is triggered by the
91. rbose 1 24 25 26 ipblock my8051 ins out data ns 8 2 iptype i8051systemsource 28 ipparm core my8051 29 ipparm port P0 30 3T 32 ipblock my8051_datain out data ns 8 S iptype i8051systemsource 34 ipparm core my8051 355 ipparm port P1 Sort 374 38 dp sys 39 sig ins din ns 8 40 41 use my8051 42 use my8051 ins ins 43 use my8051 datain din 44 use hello decoder ins din 45 N 46 47 system S 48 sys 49 The first part of the program lines 1 17 is a one way handshake that accepts data val ues and prints them Of particular interest for this example are the hardware software interfaces in lines 26 36 The cosimulation interfaces with an 8051 are not memory mapped but rather port mapped The 8051 has four ports labeled PO to P3 which are mapped to its internal memory space but which are available as IO ports on the core These ports are intended to attach peripherals and in this case are used to attach a GEZEL processor To learn more about the 8051 refer to the UCR Dalton project http www cs ucr edu dalton i8051 or the numerous other sources of 8051 infor mation on the web Here is a driver program in C for this coprocessor LISTING 18 8051 Driver program for the Hello coprocessor 1 include lt 8051 h gt GEZEL V2 0 Simulator User Manual 49 Cosimulating GEZEL with Instruction Set Simulators August 1 2005 The gp
92. rdware description using FSMD seman tics The first two bullets cores and cosimulation interfaces are expressed with the GEZEL library block mechanism ipblock An ipblock is a library block with similar semantics as a datapath dp Library blocks are discussed in detail in Section 8 0 on page 64 For the purpose of this discussion suffices to say that a library block as a type and one or more parameters A library block s type is expressed using the ipblock state ment while a library block s parameters are expressed using the ipparm statement Lines 1 5 in Listing 12 include an ARM core in the simulation It has type armsystem which means it is a complete instruction set simulator including its program memory The application program that must be loaded into the program memory is given as a parameter to this library block on Line 4 In this case we specify the application program is stored in the executable 1istingl3 Lines 6 22 define three cosimulation interfaces between GEZEL and the ARM These interfaces are unidirectional memory mapped interfaces There are two types of memory mapped interfaces armsystemsink blocks such as in lines 8 12 These are channels from GEZEL to the ARM they are a data sink for GEZEL These blocks define an input port on the library block where data to be send to the ARM is provided armsystemsource blocks such as in lines 18 22 These are channels from the ARM to GEZEL they are a dat
93. re of the processor it must model in mind which is not possible for the GEZEL kernel Also the GEZEL ker nel uses scripted simulation rather than compiled simulation As an optimization the GEZEL simulator uses a strategy of sleep awake modes as was discussed in Section 4 1 on page 31 This mode switching is also important for cosimula tion If this is possible a user should develop the GEZEL hardware model in such a way that periods of idle or inactive operation also imply no datapath register changes and no state changes in the GEZEL controllers This will result not only in a more energy effi cient implementation less useless toggling nets but also in improved simulation speed GEZEL V2 0 Simulator User Manual 51 Cosimulating GEZEL with SystemC August 1 2005 Cosimulation Setup 6 0 Cosimulating GEZEL with SystemC GEZEL supports cosimulation with SystemC a C library for hardware modeling as well as system level simulation created by the Open SystemC Initiative SystemC can be downloaded from http www systemc org A detailed reference manual for Sys temC is included in the release available from that website This chapter presents the cosimulation interfaces between GEZEL and SystemC This cosimulation interface allows users with legacy SystemC code to try out GEZEL model ing without leaving their existing system level environment 6 1 Cosimulation Setup The coupling between GEZEL and SystemC is done by integrating GE
94. rite the value 0 once in reap and never change it afterwards By declaring reqp to be a volatile pointer the compiler will refrain from such optimizations Everything is now ready to run the cosimulation Start by compiling the ARM program using a cross compiler The static flag creates a statically linked executable a requirement for the ARM ISS gt usr local arm bin arm linux gcc static hshakedriver c o hshakedriver Next run the cosimulation with gplatform gt gplatform listingl2 fdl armsystem loading executable listing13 armsystemsink set address 2147483648 data received 0 cycle 29365 data received 1 cycle 29527 data received 2 cycle 29563 data received 3 cycle 29599 data received 4 cycle 29635 data received 5 cycle 29671 data received 6 cycle 29707 data received 7 cycle 29743 data received 8 cycle 29779 data received 9 cycle 29815 Total Cycles 32450 The simulation initializes and then prints a series of data received messages which are generated by the GEZEL program The round trip execution time of the protocol takes 36 clock cycles a rather high value because we are working with an unoptimized C program and an unoptimized handshake protocol Example 2 Dual ARM Cosimulation An example of a system with two ARM processors follows next where data is shipped from one ARM to the next using a dedicated communication bus and an optimized two phase single sided handshake protocol The exampl
95. ruction set simulator The 8051 cosimulator is based on the instruction set simulator from the Dalton project at UC Riverside http www cs ucr edu dalton i8051 The instruction set simulator itself is included in the source code and contains a few small modifications to include the cosimulation interfaces The 8051 programs for geze151 are provided in Intel Hex format They can be created using the Small Devices C Compiler available from http sdcc source forge net Refer to that page for download and installation instructions of the sdcc compiler Installing the gplatform cosimulator Once you have prepared the ARM ISS you can configure GEZEL to enable compilation of gplatform Use the enable gplat form flag for this If required also use the with simit flag to indicate the path the the ARM ISS gt configure enable gplatform with simit opt Simit build gt make gt make install To test the installation run one of the examples of gplat form under the test direc tory for example gt make usr local arm 3 3 2 bin arm linux gcc static hello c o hello gt make sim build bin gplatform hellomodel fdl armsystem loading executable hello GEZEL V2 0 Simulator User Manual 78 August 1 2005 armsystem loading executable hello Hello Jefke Piet and Pol Hello Jefke Piet and Pol Total Cycles 43653 A 3 SystemC Cosimulator SystemC adds hardware
96. ry Blocks August 1 2005 Custom Library Blocks 8 3 Custom Library Blocks Finally you can add custom library blocks to the GEZEL kernel Adding custom library blocks allows you to cope with a variety of design problems Some examples are as fol lows Including legacy C code jpeg code crypto libraries in a GEZEL simulation e Adding new cosimulation interfaces for example including socket or IPC communica tion primitives to enable network based cosimulation Adding advanced I O capabilities for example formatting blocks that create graphical output either directly on the screen or else into a file Adding advanced runtime analysis capabilities such as a block that records the histo gram of values on a bus There are three steps to take in order to create a new custom library block First you must decide how the outline of the block looks like as well the parameter set you will support with it Next you have to develop the behavior of the block in C And finally you have to integrate the block into GEZEL recompile the GEZEL kernel and relink it to your application Step 1 Design the outline and functionality The first step is to decide on the outline of the block Indeed before starting to write C code it is useful to write out in GEZEL code how the block will look like and think about the desired behavior As an example we will develop a runlength encoding block A runlength encoder creates a compact tuple b
97. s Strace expression filename txt This directive must be placed just after the signal and register definitions inside of a data path The default output format for a trace directive is binary There can be multiple trace directives active at the same time In that case each of them should write to a different file Another format of the trace directive is to use it in the state transition definition of an FSM In this case a message will be printed to standard output when the state transition is executed An example of a trace directive in a state transition is sO sfgl sfg2 Strace gt sl A summary of all the directives is as follows Sdisplay arg Used inside of an sfg Prints strings expressions and meta variables cycle Used as a display argument Returns current clock cycle first cycle 1 Seta Used as a display argument Returns the name of the current sfg Sdp Used asa display argument Returns the name of the current datapath GEZEL V2 0 Simulator User Manual 34 Simulating standalone GEZEL designs August 1 2005 The debug flag Shex Sbin dec Usedasa display argument Changes the base of the next argument to hexadecimal binary or decimal Sfinish Used inside of an s g Aborts the simulation Strace expres Used after register signal definitions in dp sion file txt Records value of expression each clock cycle in file txt Strace Used as an instruction in an FSM sta
98. s 4 in mul st ns 1 out mul done ns 1 2 35 1 4 reg acc sr2 fpr rl ns 5 6 7 1 4 reg mul st cmd ns 1 trace acc acc txt GEZEL V2 0 Simulator User Manual 35 Simulating standalone GEZEL designs August 1 2005 The debug flag 8 9 sfg ini initialization 10 fpr fp dis r1 il T2 sr2 12 13 acc 0 14 mul st cmd mul st 15 16 sfg calc calculation ds sr2 Sp2 cob 18 acc acc lt lt 1 19 rl amp tc 1 sr2 3 fpr amp tc 1 acc 3 20 display acc bin acc 21 22 sfg omul output inactive 23r mul acc 24 mul done 1 25 display done mul mul 26 finish 27 28 sfg noout output active 29 mul 0 30 mul_done 0 BAS 32 33 fsm gfmul ctl gfmul 34 state S1 s2 s3 s4 s5 35 initial s0 36 sO ini noout gt sl 37 s1 if mul st cmd then calc noout gt s2 38 else ini noout gt sl 39 s2 calc noout s3 40 s3 calc noout gt s4 41 s4 calc noout gt s5 42 s5 ini Strace omul sl 43 44 45 dp TB out fp il i2 ns 4 out mul st ns 1 46 reg ctl ns 4 47 always 48 ctl ctl 1 49 fp 0b0011 50 il 0b1101 51 i2 0b1001 52 mul st ctl 0 1 0 53 54 55 56 dp sysgfmul 57 sig fp il i2 mul ns 4 58 sig mul done mul st ns 1 59 use gfmul fp il i2 m
99. s 8 13 14 always T5 c c 9 0 c 1 16 data T c 17 display Scycle data gt tuplenum tupledata n 18 I9 i 20 21 dp sysrle 22 sig i tn td ns 8 23 use my rle i tn td 24 use senddata i tn td 25 1 26 GEZEL V2 0 Simulator User Manual 74 GEZEL Library Blocks August 1 2005 Other member functions for aipblock 27 system S 28 sysrle 29 The program generates the following output to confirm the correct operation of the run length encoder gt fdlsim rle fdl 15 1 1 gt 0 0 2 1 0 0 3 1 gt 0 0 As 8 sr 35 A 5 4 gt 1 3 6 4 gt 0 0 7 6 gt 2 4 8 6 gt 0 0 9 6 gt 0 0 10 6 0 0 11 1 4 6 12 1 gt 0 0 13 1 gt 0 0 14 3 gt 3 1 15 4 gt I 3 Activity on 1 registers 100 15 15 8 4 Other member functions for aipblock virtual void aipblock stop This function is called in gplat form see Section 5 2 on page 41 when the simulation terminates virtual void aipblock probe char This is a probing function to be used in combination with a cosimulation interface It allows an external simulator such as an ISS to query specific GEZEL ipblocks An example of a library block that calls this function is armsimprobe GEZEL V2 0 Simulator User Manual 75 August 1 2005 Appendix A Installing GEZEL The homepage URL for GEZEL is at htt
100. s application one writes GEZEL code for the hardware coprocessor and evaluates the performance of the design in the intended target architecture using cosimula tion The simulation is cycle true but because of the cosimulation technology many times faster than a similar system model in V HDL Embedded instructions aes decoder T x i i i hy Y y data_in oe p ts f aes_top Plaintext AES ECB gt data_out 0x800000004 FSMD model of hardware HW SW Interfaces Library Blocks NW GEZEL Model Instruction set Simulator FIGURE 1 1 A GEZEL based coprocessor simulation GEZEL V2 0 Simulator User Manual 1 Overview August 1 2005 The FSMD model of computation controller datapath FIGURE 1 2 A sample GEZEL model GEZEL has also been used in multiprocessor simulations to connect several heteroge neous cores with a network on chip VHDL code generated out of GEZEL has been mapped onto FPGA as well as onto ASIC The publications list in Section B on page 85 enumerates several papers that describe applications where GEZEL was used In this manual GEZEL features are discussed from a user perspective There is also a Language Reference Manual LRM where a more formal treatment of the GEZEL lan guage and semantics is given 1 1 The FSMD model of computation The GEZEL language models hardware according to the semantics of a finite state machine with a datapath FSMD This section ex
101. s variable returns the current simulation cycle Thus the effect of the display directive will be to print out the current simulation cycle as well as the output value of the counter Finally on lines 10 11 the toplevel of the system is expressed A GEZEL file must always have a system statement The counter of Listing 2 can be simulated by means of the fdlsim standalone GEZEL simulator To simulate 6 clock cycles we execute fdlsim listing2 fdl 6 Cycle 1 counter 0 Cycle 2 counter 1 Cycle 3 counter 2 Cycle 4 counter 3 Cycle 5 counter 0 Cycle 6 counter 1 As expected the counter counts up to three and then wraps around GEZEL V2 0 Simulator User Manual 15 Creating hardwired datapaths August 1 2005 Datapath modules A datapath definition thus consists of three elements An IO definition a definition of local signals and registers and a set of signal flowgraphs The IO definition can create input as well as output ports For example a simple ALU that can add subtract and accumulate would look as follows dp alu in x y ns 8 out z ns 8 reg acc ns 8 sfg add ZEF Vi z x y sfg accumulate acc acc x Z acc x sfg rst acc 0 Z 0 There are four named signal flowgraphs in this example The datapath has two inputs x and y and one output z There is an internal accumulator register acc There is one sig nal flowgraph call rst This will be use
102. sing signals and registers Section 3 0 Creating sequential designs explains the various options for the design of datapath controllers Section 4 0 Simulating standalone GEZEL designs goes into the details of GEZEL simulation and explains the various options for tracing and debugging Section 5 0 Cosimulating GEZEL with Instruction Set Simulators explains how GEZEL is used in cosimulation Section 6 0 Cosimulating GEZEL with SystemC discusses the integration of GEZEL into a SystemC simulation Section 7 0 Cosimulating GEZEL with JAVA gives an overview of existing GEZEL library blocks such as RAM cells and also explains how you can create your own Section 8 0 GEZEL Library Blocks explains how you can add your own Library blocks to GEZEL and how to convert those into dynamically linked libraries that can be linked into the GEZEL simulator Appendix A Installing GEZEL explains how to download configure and compile GEZEL This includes the GEZEL kernel as well as various cosimulators that are included in the release Appendix B References is a publication list for GEZEL and related tools like the instruction set simulators used for cosimulation The reader should have some familiarity with the following concepts l The reader must be familiar with basic hardware design concepts registers and signals gates logic functions digital arithmetic and design of combinatorial and sequential logic The reader must
103. stemC 2 0 1 Sep 15 2003 14 48 27 Copyright c 1996 2002 by all Contributors ALL RIGHTS RESERVED systemcsource set variable varl systemcsink set variable var2 Sim starts data 2 value is data 2 value is data 2 value is data 2 value is data 2 value is etc tes NWR OO The creation of SystemC cosimulations is discussed in Section 6 0 on page 52 A 4 JAVA Cosimulator The GEZELkernel is also accessible to JAVA applications through a set of three JAVA classes You can download a JAVA developer kit from SUN http java sun com or IBM GEZEL V2 0 Simulator User Manual 80 August 1 2005 http www 106 ibm com developerworks java jdk linux140 if it is not available in the machine you are working on The location of the javac and javah tools which are used to compile the JAVA gezel link must be set in the Makefile am under the java subdirectory of the GEZEL distribution You have to make this modification before running configure The default values on this line are JAVAC opt IBMJava2 142 bin javac JAVAH opt IBMJava2 142 bin javah After confirming the paths are properly configured run automake to regenerate the Makefiles Next compile the java GEZEL classes as well as the shared library that links them to the GEZEL kernel by running configure using the enable java flag configure enable java make make install To confirm that the JAVA class library works try one ofthe e
104. stepy 30 yinc2 asdx gt asdy 0 stepy 3d initialize registers 32 x xlin y yl in 33 e Se 34 35 36 end of loop test check if we reach target 37 sfg looptest 38 ol x x2 in amp y y2 in 39 40 41 loop body adjust x y and error accumulator 42 use error value to decide straight or diagonal step GEZEL V2 0 Simulator User Manual 24 Creating sequential designs August 1 2005 Finite state machines 43 sfg loop 44 x e gt 0 x xincl x xinc2 45 y e gt 0 y yincl y yinc2 46 e gt 0 e eincl e einc2 47 display hex Cycle cycle Plot point x y 48 49 50 controller for bresenham algorithm 51 initializes draws one line and then waits in state s3 52 fsm f bresen bresen 5 3 initial s0 54 state sl s2 s3 554 sO init gt sl 56 s1 loop looptest S2 57 s2 if eol then init gt 83 58 else loop looptest gt s2 59 s3 init gt 83 60 61 62 testbench 63 dp test bresen out x1 yl x2 y2 tc 12 64 sig sx tc 12 65 sfg run 66 x1 5 x2 18 yl 2 y2 8 67 68 69 hardwired h test bresen test bresen run 70 71 dp sysbresen 72 sig xl yl x2 y2 tc 12 Tas use bresen xl yl x2 y2 74 use test bresen xl yl x2 y2 Ls 76 77 system S 78
105. struction set simulator The homepage for SimIt ARM is http sourceforge net projects simit arm The cosimulation is written on top of Version 2 0 or later of SimIt ARM After you have downloaded SimIT ARM unpack it tar zxfv SimIt ARM 2 0 tgz SimIT ARM 2 0 has a built in cosimulation interface that must be enabled with the macro COSIM STUB while the packge is configured and installed gt cd SimIt ARM 2 0 gt configure CPPFLAGS DCOSIM STUB gt make GEZEL V2 0 Simulator User Manual 77 August 1 2005 gt make install This will install the SimIt ARM ISS as stand alone libraries as well as executables under SimIt ARM 2 0 build If you plan to install the cosimulators in a different location than the standard build subdirectory use the prefix command line option with con figure gt configure CPPFLAGS DCOSIM STUB prefix my_target_dir In particular it is not a good idea to copy executables from the build directory to a target directory by hand This is because SimIt ARM hard codes the default path to the floating point emulator that it relies on nwpfe bin To run the armcosim cosimulator you need to provide a GEZEL file and an ARM ELF executable The ARM ELF executable must be statically linked These executables can be created using an ARM cross compiler This compiler can be downloaded for example from the ARM Linux FTP site ftp ftp arm linux org uk Installing the i8051 inst
106. te transition Echoes the state transision to the screen Soption string Includes optional simulator profiling string is one of debug vcd profile_toggle_upedge_cycles Le_ profile_toggle_alledge_operations profile_toggle_upedge_operations profile_toggle_alledge_cycles See below for details 4 4 The debug flag The main use of the GEZEL standalone simulator is validation of your GEZEL designs In fact before taking any GEZEL code into a cosimulation as will be discussed later it is a good idea to verify the design first in a small standalone simulation fdlsim provides a debug mode of operation that can be enabled using the d flag on the command line The effect of the d flag is twofold It will print out the GEZEL symbol table in a file called d1 symbols For each clock cycle it will print out all register changes in the datapaths and control lers using a value change format This means that if a register is not changing in a par ticular clock cycle it will not be printed The use of the debug flag will be illustrated on the Galois Field Multiplier from Section 3 5 on page 28 A small testbench was added after line 50 to multiply 1101 with 1001 Also various directives were added in the simulation such as on lines 7 trace 20 and 25 display 26 finish and 42 trace LISTING 11 A Galois Field multiplier testbench dp gfmul in fp il i2 ns 4 out mul n
107. ters and signals GEZEL models synchronous single clock designs Yet a clock signal is not present in GEZEL language it is implicit in the design description By looking at a GEZEL program you can say precisely how it will behave as a clock cycle true description You can do this by looking at the kind of variables it uses in calculations GEZEL has two kinds of vari ables signals and registers A signal can hold a value within a single clock cycle It has the same meaning as a wire in an actual implementation A signal also has a name and a type and is created with the sig keyword For example a signal with name v12 and type ns 12 is created as follows sig v12 ns 12 This type ns 12 stands for a 12 bit unsigned number Signal v12 can hold values from 0 to 4095 When you force this signal to hold values outside of this range precision loss will occur This will be discussed in Section 2 2 Expressions on page 10 There is one other type available for values called tc n This type represents arbitrary length signed numbers with two s complement representation For example to create the equivalent of a C integer on a 32 bit machine use the following definition sig aCinteger tc 32 Registers are used to store values over multiple clock cycles In contrast to signals regis ter variables have two values a current value and a next value The current value is the value available at the output of a register so it is t
108. tic The complete GEZEL listing illus trates how a slightly more complicated design looks like x LISTING 6 The Bresenham line drawing algorithm as an FSMD 1 Bresenham line plotter for points in an arbitrary octant 2 dp bresen in xl in yl in x2 in y2 in tc 12 35 reg x y tc 12 current plot position 4 reg e tc 12 accumulated error 5 reg eol tc 1 end of loop flag 6 reg eincl einc2 tc 12 increments ya reg xincl xinc2 tc 12 8 reg yincl yinc2 tc 12 g sig se sdx sdy te 12 10 sig asdx asdy te 12 11 sig stepx stepy o e6 12 5 12 13 sfg init 14 evaluate range of pixels and their absolute value WAGE sdx x2 in xl in asdx sdx 0 sdx sdx 16 sdy y2_in yl in asdy sdy lt 0 sdy sdy 17 determine direction of x and y increments 18 stepx sdx 0 1 1 19 stepy sdy lt 0 1 1 20 initial error 21 se asdx gt asdy 2 asdy asdx 2 asdx asdy 22 error increment for straight eincl and diagonal einc2 step 23 eincl asdx gt asdy asdy asdx asdx asdy 24 einc2 asdx gt asdy asdy asdx 25 increment in x direction for straight and diagonal steps 26 xincl asdx gt asdy stepx stepx 27 xinc2 asdx gt asdy stepx 0 28 increment in y direction for straight and diagonal step 29 yincl asdx gt asdy stepy
109. tly The statement Soption debug at the top of your file will enable only the debug mode that prints values of registers as they change to the terminal The statement Soption vcd at the top of your file will enable only the VCD mode that creates the TRACE vcd file 4 6 Operation profiling and toggle counting GEZEL provides a simple facility for operation profiling and toggle counting Operation profiling returns the number of times each operation kind has executed over the course of a simulation This is useful to estimate the computational complexity of a design Toggle counting returns an estimate on the number of signal transitions that occur per clock cycle in a particular simulation This is useful to estimate the immediate dynamic power con sumption of a design GEZEL V2 0 Simulator User Manual 38 Simulating standalone GEZEL designs August 1 2005 Operation profiling and toggle counting Operation profiling and toggle counting are enabled with the Soption directive This directive is given at the top of a GEZEL file before all datapath definitions Consider Listing 5 again and insert the directive for operation profiling at line 1 Soption profile toggle alledge operations This directive produces the following output for 10 clock cycles of simulation gt fdlsim listing05 fdl 10 FDL Cycles 10 Type Evals Toggles dpinput 10 16 dpoutput 20 26 com reg 18 34 assign op 38 50 shl op 2 3 add op 17 31
110. to the data transfer channel between C and GEZEL This signalling sequence ensures that the communicating parties achieve synchronization Both the control signals and data transfer channel can be implemented using the same cosimulation interfaces For example you can use a memory mapped interface for both of them GEZEL V2 0 Simulator User Manual 40 Cosimulating GEZEL with Instruction Set Simulators August 1 2005 The gplatform tool 5 2 The gplatform tool The gplatform tool is able to do everything what you can do with armcosim armz illa and geze151 It was introduced as of GEZEL 1 7 to start consolidating the amount of cosimulation tools supported in the GEZEL release without trimming down on the flexibility or capabilities Eventually gplatform will support a wide range of system architectures including single processor systems loosely coupled as well as tightly coupled multiprocessor architec tures and homogeneous as well as heterogeneous systems In a loosely coupled system each core has a private memory program space In a tightly coupled system multiple cores will share a single program space The current version of gplatform supports loosely coupled multiprocessor systems including an arbitrary configuration of ARM and 18051 cores The command line of gplatform is as follows gplatform d c max cycles gezel fil The system configuration is fully contained within gezel_file The c flag allows to indicate an upp
111. ugust 1 2005 A small example portname _portname A GezelOutport is a communication channel from GEZEL to JAVA During construc tion of this object a symbolic name must be given that can be referred to from within GEZEL Once the object is created data can be read from GEZEL using the read method Communication is immediate and will return the value evaluated by GEZEL in the present clock cycle class GezelOutport int portId static int glbPortId public native void portname String portname public native int read GezelOutport String _portname portlId glbPortId portname _portname 7 2 A small example We present the case of a counter in GEZEL integrated into a JAVA simulation The incre ment value of the counter will be programmed out of JAVA First consider the GEZEL description of the counter LISTING 20 A GEZEL counter interfacing to JAVA 1 dp mycounter in v ns 32 2 reg a ns 5 3 always run 4 a sa H v D Sdisplay counter a 6 Fa 8 9 ipblock myjavasource out data ns 32 10 iptype javasource TE ipparm var myinput 1214 7 13 14 dp syscounter T5 sig a ns 32 16 use mycounter a T7 use myjavasource a 18 T9 20 system S 21 syscounter 22 GEZEL V2 0 Simulator User Manual 61 Cosimulating GEZEL with JAVA August 1 2005 A small example A counter block Lines 1 8 is attached to a library block that re
112. ul mul st mul done 60 use TB fp il i2 mul st 61 GEZEL V2 0 Simulator User Manual 36 Simulating standalone GEZEL designs August 1 2005 The debug flag 62 63 system S 64 sysgfmul 65 The output of the simulation is gt fdlsim listingll fdl 10 acc 0000 1101 acc 1101 1001 acc 1001 0001 acc 0001 1111 gfmul ctl gfmul ctl s5 gfmul_ctl sl done mul f finish reached The output of the first four lines was generated by the display directive in line 20 The next line originates from a t race line 42 telling that the controller gfmul ctl makes a tran sition from state s5 to state s1 The result is displayed with another display and finally the simulation is terminated as a result of the inish directive During the sim ulation a tracefile is created for the acc register in acc txt The content of this file shows that the simulation ran 6 clock cycles The file of acc is stored as binary ASCII numbers gt Gat acc txt 0000 0000 1101 1001 0001 1111 Now run the simulation again commenting out all display and trace directives but enabling the debug mode The simulation can be monitored clock cycle by clock cycle Lines indicating register changes include the previous register value the new regis ter value and the register name including a pathname that identifies the datapath where the register is located For example we can see that in clock cycle 3 the acc register in datap
113. ulation startup and connect the GEZEL simulator to clock This means that each upgoing positive edge in clock will result in a single cycle of GEZEL simulation gezel module G gezel block fir fdl G clk clock signal In the current version of the GEZEL SystemC cosimulation interface only a single GEZEL file can be read in a SystemC simulation 6 3 A FIR filter To illustrate the use of the interface design a FIR filter starting from the FIR filter included in the current SystemC 2 0 1 release This example is a 16 bit FIR filter included under examples systemc fir The goal is to substitute the FIR core in SystemC with an identical FIR in GEZEL while keeping the surrounding testbench identical First look at the way the SystemC version of the filter is integrated file main rtl cpp in sc main Sc clock clock Sc signal bool reset sc signal bool input valid sc signal int sample Sc signal bool output data ready Sc signal int result fir top fir topl process body fir topl RESET reset fir topl IN VALID input valid fir topl SAMPLE sample fir topl OUTPUT DATA READY output data ready fir topl RESULT result fir topl CLK clock signal The block has three input ports and two output ports Each of these ports will map to either a gezel inport or a gezel outport In addition a gezel module will be required to hook up the GEZ
114. urally At the highest level datapath state is naturally present in the state variables of an algorithm Control state is introduced as a consequence of mapping the algorithm execution onto a time axis of clock cycles e A datapath and a controller have different modeling concepts Datapaths are created by composition of expressions to make calculations These expressions look like the ones from the C programming language Controllers on the other hand are created by com position of state transition graphs A datapath and a controller have different logic implementation styles Datapaths are reg ular and can be created hierarchically as a composition of smaller elements Controllers are irregular and harder to create hierarchically An excellent reference on the underlying principles of FSMD modeling can be found in Chapters 10 to 14 of the digital system book by Davio Unfortunately this reference is out of print More recently SpecC has also introduced FSMD modeling Davio Deschamps Thayse Digital Systems with Algorithm Implementation Wiley and Sons 1983 e Doemer Gerstlauer Gajski SpecC Language Reference Manual v 2 0 2002 avail able online from lt http www cecs uci edu doemer publications SpecC_LRM_ 20 pdf gt The relation between controllers and datapaths in GEZEL will be elaborated further in Section 3 0 on page 20 The next subsection presents a small example on the mapping of an algorithm into the FSM
115. ut of SystemC A 7 Reporting Problems GEZEL is an open source environment distributed under the GNU Lesser Public License Basically this gives you a free license to use GEZEL LGPL also means that GEZEL GEZEL V2 0 Simulator User Manual 83 August 1 2005 comes with no warranty nor are we liable for the consequences of your use of GEZEL The LGPL license in the file COP YING gives you all the details Still this does not mean we don t want to hear from you The preferred way of feedback to GEZEL is through the GEZEL email list http groups yahoo com group gezel If you have a very specific problem or question you can also contact the developers We appreciate your feedback a lot Patrick Schaumont schaum ee ucla edu The only way an EDA tool can improve is by interacting with users GEZEL V2 0 Simulator User Manual 84 August 1 2005 Appendix B References B 1 Publications on the GEZEL language and tools P Schaumont D Ching I Verbauwhede An interactive codesign environment for domain specific coprocessors submitted to ACM Transactions on Design Automation for Embedded Systems P Schaumont I Verbauwhede The descriptive power of GEZEL Technical Report Jan 30 2005 Available online on the GEZEL homepage P Schaumont I Verbauwhede Interactive Cosimulation with Partial Evaluation 2004 Design Automation and Test in Europe DATE 2004 Februari 2004 P Schaumont I V
116. view August 1 2005 The FSMD model of computation controller 9 conditions y gt N y instructions datapath ma outputs inputs to f1d f2 FIGURE 1 3 The GEZEL FSMD Model consists of two cross coupled finite state machines the registers as well as the outputs of the datapath are evaluated based on the state of the registers as well as the inputs to the datapath next state fl state inputs output f2 state inputs During the second phase the newly obtained next state values are copied into the state values so that the simulation of the next clock cycle can begin state next state A digital cycle true simulator executes these two phases in an alternating fashion The behavior of the module therefore is completely defined by the functions 1 and 2 They specify a finite state machine FSM Depending on the exact form of 2 one distin guishes a Moore type FSM and a Mealy type FSM In a Moore FSM the output value is only dependent on the previous state not on the current input An FSMD is a refined form of the above model that makes a distinction between two kinds of state in the hardware module The first is called control state and the other is called datapath state Control state represents the storage to work with control steps Many algorithms when mapped into digital hardware decompose in a sequence of con trol steps Datapath state on the other hand hol
117. ways yl al gt s2 s2 al y2 sl gt a2 a2 S1 al dl a sl dl a a2 d2 a s2 d2 a then when evaluating y1 the GEZEL simulator will notice that none of the signals a1 a2 s1 and s2 are available yet Consequently it would first find a current value for these signals So this signal flow graph behaves exactly the same as the one we described before that 2 4 Named signal flow graphs Besides the unnamed always signal flow graph you can create signal flow graphs with a name using the s g keyword For example the previous signal flow graph could be writ ten as sfg mysfg yl al gt s2 s2 al y2 sl gt a2 a2 S1 al dl a sl di a a2 d2 a s2 d2 a The difference between a named signal flowgraph sfg and the unnamed always is that the former does not automatically execute each clock cycle GEZEL will allow you to create a controller that schedules the named signal flowgraph Controller design will be discussed in Section 3 0 on page 20 2 5 Datapath modules A datapath corresponds to a module in Verilog or an entity in VHDL It is a piece of hard ware logic that is treated as a single entity by subsequent RT and logic synthesis tools A datapath combines a number of named signal flow graphs with a list of input and output signals A signal flow graph can be thought of as an instruction for that datapath A datap ath can have only a single a
118. xamples under test java Also here the path the javac and javah must be provided This is done in test java Makefile rules gt cd test java counterl gt make opt IBMJava2 142 bin javac classpath java counterl java make sim export LD LIBRARY PATH build lib opt IBMJava2 142 bin java classpath build share counterl counter 0 1 counter 1 2 counter 2 3 counter 3 4 counter 4 5 counter 5 6 counter 6 7 counter 7 8 counter 8 9 counter 9 a A 5 AVRORA Cosimulator One application of the JAVA cosimulation interface is a cosimulation with the AVRORA instruction set simulator AVRORA simulates the Atmel AVR and is developed by B Titzer at the compilers group at UCLA http compilers cs ucla edu avrora GEZEL V2 0 Simulator User Manual 81 August 1 2005 The examples under test java avrora illustrate an integration between GEZEL and AVRORA based on the Platform class from AVRORA To run this example first download and install the AVRORA class library The path the the AVRORA ISS needs to be indicated in test java Makefile rules JAVAC opt IBMJava2 142 bin javac JAVA opt IBMJava2 142 bin java AVRORACLS home schaum avrora bin GEZ LE CLS home schaum gezel devel build share GEZ LIB home schaum gezel devel build lib In order to run the examples under test java avrorax you also need to install a
119. xecute the block The function setparm is called when the GEZEL parser finds a field ipparm The argument of this function contains the quoted string that is found in the GEZEL code For example when the GEZEL code contains ipparm maxlen 32 then the argument of setparm will be maxlen 32 The function checkterminal is called by GEZEL for each port It allows to verify that the user of the GEZEL block has used the correct names and directions of the ports of this block The function returns a boolean which must return true of no problem is found The arguments of the function correspond to the data found in the GEZEL program n holds the port index with the first port having index 0 tname holds the name the user of the block has used for the port dir indicates if it is an input or an output The functions needsWakeupTest and cannotSleepTest are used to support the sleep mode of the GEZEL simulator See Section 4 1 on page 31 When the simulator is running each clock cycle the function cannot SleepTest is called This function needs to return t rue if sleep mode cannot be started Once the simulator is in sleep mode the function needsWakeupTest is called every skipped clock cycle The function returns t rue when the GEZEL simulation needs to wake up again The function touch is used in the context of cosimulation interfaces to force the next call to needsWake upTest to return t rue To get insight into these different functio
120. y simple point to point connection Lines 24 38 The software running on each of the cores is shown in Listing 15 and Listing 16 The hand shaking protocol ilustrated here is an optimized version of the two phase full handshake protocol described in Section 5 2 on page 41 The optimizations include the following Convert the two way request acknowledge handshake with a one way request only handshake going from the sender to the receiver This optimization is possible when the receiver is faster than the sender because the sender can not verify the status of the receiver and thus must assume it is always safe to send data GEZEL V2 0 Simulator User Manual 46 Cosimulating GEZEL with Instruction Set Simulators August 1 2005 The gplatform tool e Trigger the handshaking on signal level changes rather than signal levels This effec tively doubles the communication bandwith with respect to a level triggered case e Merge the request and data signals into a single shared memory address This looses one bit of the useful data bandwidth but at the same time reduces the number of mem ory accesses by the ARM Ina RISC processor memory bus badnwidth is a very scarce resource In the examples below the most significant bit of the data word is used as the request bit for the single side handshake protocol LISTING 15 A Sender C program of the two ARM multiprocessor include lt stdio h gt 1 2 3 int main 4 volatile unsigned int
121. y the sender are interleaved with messages from the GEZEL program gplatform listingl4 fdl armsystem loading executable 1listing15 armsystem loading executable 1listing16 armsystemsink set address 2147483656 Sender sends Sender sends Sender sends Sender sends Sender sends Sender sends Sender sends Sender sends Sender sends Sender sends 9 Receiver complete last data 9 Total Cycles 64971 OO JOU DUN HO Example 3 8051 Cosimulafion Now let s consider a small example of an 8051 cosimulation a program that will simply transfer data values from the 8051 microcontroller to the GEZEL simulation LISTING 17 A GEZEL description of the 8051 hello coprocessor 1 dp hello_decoder in ins ns 8 De in din ns 8 Bis reg insreg ns 8 4 reg dinreg ns 8 D sfg decode insreg ins 6 dinreg din 7 sfg hello display cycle Hello You gave me dinreg 8 9 10 fsm fhello decoder hello decoder 11 initial s0 12 state sl s2 T3 Gs0 decode gt sl GEZEL V2 0 Simulator User Manual 48 Cosimulating GEZEL with Instruction Set Simulators August 1 2005 The gplatform tool 14 sl if insreg 1 then hello decode gt s2 15 else decode gt sl 16 s2 if insreg 0 then decode gt sd 17 else decode S2 18 19 20 ipblock my8051 21s iptype i8051system 22 ipparm exec driver ihx 23 ipparm ve
122. ystem Function 18051 core program memory IO Parameters exec Name of the intel hex formatted 18051 binary to execute verbose When set to 1 run the ISS in verbose debug mode period Relative clock period default 1 When set to e g 2 the 8051 will run at half speed relative to the system gezel clock i8051systemsourc Function Port mapped cosimulation interface to transport data from e 8051 to GEZEL IO data output ns 32 data output Parameters core name of the 18051system core this port mapped interface belongs to port quoted string one of PO P1 P2 P3 18051systemsink Function Port mapped cosimulation interface to transport data from GEZEL to 8051 to GEZEL IO data input ns 32 data input Parameters core name of the 18051system core this port mapped interface belongs to port quoted string one of PO P1 P2 P3 Library Block in Libgzlsys a SystemC cosimulator Section 6 2 on page 52 systemcsource Function Cosimulation interface to transport data from SystemC to GEZEL IO data output ns 32 data channel from Sys temC to GEZEL Parameters var string indicates the symbolic name of the corresponding SystemC channel systemcsink Function Cosimulation interface to transport data from GEZEL to Sys temC IO data input ns 32 data channel from GEZEL to SystemC Parameters var string indicates the symbolic name of the corresponding SystemC channel GEZEL V2 0 Simulator User Manual 69 GEZEL Libra

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