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MC9S12DT256 Device User Guide V03.03 Covers also

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1. 0040 007F ECT Enhanced Capture Timer 16 Bit 8 Channels Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read 0053 mel BU 6 5 4 3 2 1 Bit 0 4 Read 3 0054 TC2 h 15 14 13 12 11 10 9 Bit 8 Read 0055 TC2 o mel Bit 6 5 4 3 2 1 Bit 0 Read 4 0056 TC3 h 15 14 13 12 11 10 9 Bit 8 Read 0057 TC3 o Bit 6 5 4 3 2 1 Bit 0 x Read f 0058 TC4 hi 8815 14 13 12 11 10 9 Bit 8 Read 0059 4 0 Bit 6 5 4 3 2 1 Bit 0 Read 005A 8815 14 13 12 11 10 9 8 Read 005 TC5 o Bit 6 5 4 3 2 1 Bit 0 Read f 005 TC6 h Bit15 14 13 12 11 10 9 Bit 8 Read 50050 TC6 Bit 6 5 4 3 2 1 Bit O 7 Read 4 005 Bit15 14 13 12 11 10 9 Bit 8 Read 005 TC7 Bit 6 5 4 3 2 1 Bit 0 Read 0 0060 PACTL PAEN PAMOD PEDGE CLKO PAOVI PAI 0061 oad 9 9 PAIF Write Read 0062 PACNS Bit 6 5 4 3 2 1 Bit 0 Read 0063 PACN2 0 el Bit7 6 5 4 3 2 1 Bit 0 Read 0064 PACN h Bit7 6 5 4 3 2 1 Bit 0 Read 0065 0 Bit7 6 5 4 3 2 1 Bit 0 0066 16984 RDMCL 0 0 1 Write ICLAT FLMC jee Read
2. 17 Table 0 3 Specification Change Summary for Maskset LIIN 17 Table 1 1 Device Memory ee en in 24 Table 1 2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout 43 Table 1 3 Assigned Part ID Numbers 50 Table 1 4 Memory size registers 50 2 1 Signal PrOperlles 2 0 284 35 Baar In QU dent DNS ERR 53 Table 2 2 MC9S12DP256 Power and Ground Connection Summary 67 Table4 T Mode Selection ewes hs 71 Table 4 2 Clock Selection Based on PE7 71 Table 4 3 Voltage Regulator VREGEN esee ben ee RR re 72 Table 5 1 Interrupt Vector Locations 75 Table A 1 Absolute Maximum Ratings 91 Table 2 ESD and Latch up Test Conditions 92 Table A 3 ESD and Latch Up Protection Characteristics 92 Table A 4 Operating GoFDGlHOFis xo ran a Ar RR e E a HER 93 Table A 5 Thermal Package Characteristics 95 Table A 6 Ch racleristies uus eR ot tex Ree een 96 Table 7 Supply Current Characteristics 98 Table 8
3. Write Read D 0091 ATDODROL 1984 Bit ite 0 0 0 Write 14 1 12 11 1 Bi 00092 2 Write Bit Bi 0093 ATDODRIL noan it 6 0 0 0 0 0 0 Write Bit 14 1 12 11 1 Bi Write Bit Bi 0095 ATDODR2L noad it 6 0 0 0 0 0 0 Write Read Bit 14 1 12 11 1 Bit8 00952 ee ES S Write Read D 0097 10984 Bi 0 2 0 2 0 Write Bitt 14 1 12 11 1 Bi Suge EE Write Read Bit7 Bi 0 0099 ArDopR4L 1984 Bit te 0 2 0 0 Write Read Biti 14 1 12 11 1 Bit8 009A ATDODR5H a ee 34 M MOTOROLA 0080 009 Address 009B 009C 009D 009E 009F 00A0 Address 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AA 00AB 00AC 00AD 00AE 00AF 00B0 M MOTOROLA Name ATDODRSL ATDODR6H ATDODR6L ATDODR7H ATDODR7L 00C7 Name PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL PWMTST Test Only PWMPRSC PWMSCLA PWMSCLB PWMSCNTA PWMSCNTB PWMCNTO PWMCNT1 PWMCNT2 PWMCNT3 PWMCNT4 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write
4. 1 7 Part ID Assignments The part ID is located in two 8 bit registers PARTIDH and PARTIDL addresses 001A and 001B after reset The read only value is a unique part ID for each revision of the chip Table 1 3 shows the assigned part ID number Table 1 3 Assigned Part ID Numbers Device Mask Set Number Part ID MC9S12DT256 0191 0030 NOTES 1 The coding is as follows Bit 15 12 Major family identifier Bit 11 8 Minor family identifier Bit 7 4 Major mask set revision number including FAB transfers Bit 3 0 Minor non full mask set revision The device memory sizes are located in two 8 bit registers MEMSIZO and MEMSIZI addresses 001C and 001D after reset Table 1 4 shows the read only values of these registers Refer to section Module Mapping and Control MMC of HCS12 Core User Guide for further details Table 1 4 Memory size registers Register name MEMSIZO 25 MEMSIZ1 81 50 M MOTOROLA MC9S12DT256 Device User Guide V03 03 Section 2 Signal Description This section describes signals that connect off chip It includes a pinout diagram a table of signal properties and detailed discussion of signals It is built from the signal description sections of the Block User Guides of the individual IP blocks on the device 2 1 Device Pinout The 95120 256 951201256 951200256 and 9512 256 is available in a 112 pin low profile quad flat pack LQFP and M
5. Rating Symbol Min Typ Max Unit Reference Potential 1 Low Vssa VppA 2 V High Ven 2 V 2 Differential Reference Voltage Vay VAL 4 50 5 00 5 25 V 3 ATD Clock Frequency ATDCLK 0 5 2 0 MHz ATD 10 Bit Conversion Period 4 D Clock Cycles 10 14 28 Cycles Conv Time at 2 0MHz ATD Clock fATDCLK 0 7 14 us ATD 8 Bit Conversion Period 5 Clock Cycles Conv Time at 2 0MHz ATD Clock 6 D Recovery Time 5 0 Volts 7 P Reference Supply current 2 ATD blocks 8 P Reference Supply current 1 ATD block NOTES 1 Full accuracy is not guaranteed when differential voltage is less than 4 50V 2 The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks 2 2 Factors influencing accuracy Three factors source resistance source capacitance and current injection have an influence on the accuracy of the ATD A 2 2 1 Source Resistance Due to the input pin leakage current as specified in Table A 6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input The maximum source resistance Rg M MOTOROLA 99 MC9S12DT256 Device User Guide V03 03 specifies results in an error of less than 1 2 LSB 2 5mV at the maximum leakage current If device or
6. EXTAL XT AL Oscillator Pins uo rase eoe dee een RESET External Reset Pin sa see aaa teen VREGEN Voltage Regulator Enable PLL Loop Filter Pin sure a NER nel ih BKGD TAGHI Background Debug Tag High and Mode Pin PAD15 AN15 ETRIG1 Port AD Input Pin of ATD1 PAD 14 08 AN 14 08 Port AD Input Pins of ATD1 ANO ETRIGO Port AD Input Pin of PAD 06 00 AN 06 00 Port AD Input Pins of ATDO PA 7 0 ADDR 15 8 DATA 15 8 Port A I O Pins PB 7 0 ADDR 7 0 DATA 7 0 Port B Pins PEZ NOAGG XCLKS Port 7 PE6 MODB 1 1 1 PES MODA 1 1 0 5 PE4 ECLK Port E VO Pin 6 52 pute ss Vo En Re Rte o Re P ha PES LSTRB TAGLO Pott R W Port SUR ROCHE ROC Y CR a ated dec FETZIRO Por E Input Pin Terss ss ses er eure PEO XIRQ Port E Input Pin 0 M MOTOROLA MC9S12DT256 Device User Guide V03 03
7. 79 6 5 512 Background Debug Block Description 79 6 6 HCS12 Breakpoint BKP Block Description 80 Section 7 Clock and Reset Generator CRG Block Description 7 17 Device specific information rater near 80 7 1 1 2 PEL 80 Section 8 Enhanced Capture Timer Block Description Section 9 Analog to Digital Converter ATD Block Description Section 10 Inter IC Bus Block Description Section 11 Serial Communications Interface SCI Block Description Section 12 Serial Peripheral Interface SPI Block Description Section 13 J1850 BDLC Block Description Section 14 Pulse Width Modulator PWM Block Description Section 15 Flash EEPROM 256K Block Description Section 16 EEPROM Block Description Section 17 RAM Block Description Section 18 MSCAN Block Description Section 19 Port Integration Module PIM Block Description Section 20 Voltage Regulator VREG Block Description 8 M MOTOROLA MC9S12DT256 Device User Guide V03 03 Appendix A Electrical Characteristics AL DEDIT DE 89 1 1 Parameter ses 2 pte Se 89 1 2 nw MP 89 A 1 3 PINS a hM red 90 A 1 4 Current Injection ES te o RR DRE pP Ui deb at di wea 91 A 1 5 Absolute Maximum s me Ese P REOR
8. Read Bit 15 14 13 12 11 10 9 Bit 8 007E TC3H hi Read Bit7 6 5 4 3 2 1 Bit 0 007F 0 0080 009 Analog to Digital Converter 10 8 Channel Address Name 0080 ATDOCTLO 0081 ATDOCTL1 M MOTOROLA 33 MC9S12DT256 Device User Guide V03 03 0080 009F ATDO Analog to Digital Converter 10 Bit 8 Channel Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read ASCIF 0082 ATDOCTL2 282 ADPU AFFC AWAI ETRIGLE ETRIGP ETRIG ASCIE Read 0 0083 ATDOCTL qr S8C SAC S2C S1C FRZi FRZO 0084 ATDOCTL4 iin SRES8 SMP1 SMPO PRS4 PRS3 PRS2 PRS1 PRSO Read 0 0085 ATDOCTLS Wire DJM DSGN SCAN MULT 2 1 0086 ATDOSTATO doin SCF ETORF FIFOR 0 GG SCO Read 0 0 0 0 0 0 0 0 0087 Reserved Write R 0 0088 ATDOTESTO 1984 0 0 0 2 0 0 0 Write Read 0 0 0 0 0 0 0 0089 ATDOTESTI 26 SC Write Read 0 0 0 0 0 0 0 0 008A Reserved Write F7 F4 F F2 F1 F 50088 CCF6 CCF5 CC CCF3 CC CC CCFO Write Read 0 0 0 0 0 0 0 0 008C Reserved Wie 008D ATDODIEN 189 6 5 4 3 2 1 Bit 0 Write Read 0 0 0 0 0 0 0 0 008E Reserved Write rl Read 4 2 1 BIT 0 SUUS Pope SE Write Read Biti 14 1 12 11 1 Bits UGG
9. Total Input Capacitance 2 Sampling Sampling 3 Disruptive Analog Input Current 4 Coupling Ratio positive current injection 5 Coupling Ratio negative current injection 100 M MOTOROLA MC9S12DT256 Device User Guide V03 03 A 2 3 ATD accuracy Table A 10 specifies the ATD conversion performance excluding any errors due to current injection input capacitance and source resistance Table A 10 Conversion Performance Conditions are shown in Table A 4 unless otherwise noted VRer Vay 5 12V Resulting to one 8 bit count 20mV and one 10 bit count 5mV fATDCLK 2 0MHz Mum c L D L D Ws e 5 2 10 Bit Differential Nonlinearity 3 10 Bit Integral Nonlinearity 4 10 Bit Absolute Error 5 8 Resolution SB NL INL AE SB NL INL AE Counts Counts Counts mV 5 3 PB Sn ron riw Tom 5 L7 permenon m 8 395 Tome 8 1 5 8 Absolute Error 1 5 1 0 Counts NOTES 1 These values include the quantization error which is inherently 1 2 count for any A D converter ELI NETS EUX 1 2 0 For following definitions see also Figure 1 Differential Non Linearity DNL 15 defined as the difference between two adjacent switching steps Nous DNL i 1 1LSB The Integral Non Linearit
10. 91 A 1 6 ESD Protection and Latch up 92 A 1 7 Operating Gondit NS PLE be Step QE 93 A 1 8 Power Dissipation and Thermal Characteristics 93 A 1 9 s ete duca ae deca ode art 95 A 1 10 Supply ee P PE 97 A2 sense seen rab rx Te kon Da aes te ee 99 A 2 1 ATD Operating Characteristics 99 A 2 2 Factors influencing ACC rACy sis enr hes niet edd 99 2 3 ATD cete TRE RT 101 AS NVM Flash and EEPROM ur de ee DINI NE mE 103 A 3 1 NVM timing SS aie ah oles oi COR t 103 2 NIV BIBIT is ty te ee ee eS es a rete Nue id 105 A 4 Voltage 107 A5 Reset Oscillator and PLL i item ait CE Crete te 109 A 5 1 Sera cua sap LITE IU M DEN SE 109 A 5 2 22432342222 Gs ak EIE AE a E 110 A 5 3 Phase L cked Boro o UTERE 111 Oe Pee De on doc ns 115 SOP laa Bik vlr LS 117 A 7 1 Mast r Moder re a a ee hs 117 7 2 Sl
11. ue m I pas ar EE EXTAL ATDO 1 SCIO SCI1 CANO 1 2 3 4 gt oscillator clock XTAL Figure 3 1 Clock Connections 69 M MOTOROLA MC9S12DT256 Device User Guide V03 03 70 44 MOTOROLA MC9S12DT256 Device User Guide V03 03 Section 4 Modes of Operation 4 1 Overview Eight possible modes determine the operating configuration of the MC9S12DT256 Each mode has an associated default memory map and external bus configuration controlled by a further pin Three low power modes exist for the device 4 2 Chip Configuration Summary The operating mode out of reset is determined by the states of the MODC MODB and MODA pins during reset Table 4 1 The MODC MODB and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation The states of the MODB and MODA pins are latched into these bits on the rising edge of the reset signal The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map ROMON 1 mean the Flash is visible in the memory map The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal Table 4 1 Mode Selection BKGD PE6 PE5 7 ROMON MODA ROMCTL Bit Mode Description Special Single Ch
12. Ge ce EU AXE 0145 CANORIER iin CSCIE RSTATE1 TSTATE1 TSTATEO OVRIE RXFIE 0146 CANOTFLG TE 9 TXE2 TXE1 0147 CANOTIER 0 0 0 TXEIE2 TXEIE1 TXEIEO 0148 0 ABTRG2 ABTRQ ABTRQO Read ABTAK2 ABTAK1 ABTAK 0149 198 0 0 0 2 0 Write 014A CANOTBSEL 0 0 0 TX2 TX1 TXO 014B iind 9 0 IDAM1 IDAMO 0 Read 0 0 0 0 0 0 0 0 014 Write Read 0 0 0 0 0 0 0 0 014D Reserved Write Read RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 2 RXERR 014E CANORXERR Wa 0 Read TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR 014F CANOTXERR 0150 CANOIDARO Read 0153 CANOIDAR3 Write 0154 CANOIDMRO Read 0157 CANOIDMR3 Write 0158 CANOIDAR4 Read 015B CANOIDAR7 Write 015C CANOIDMR4 Read 015F CANOIDMR7 Write AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AM7 AM6 5 4 AM2 1 7 6 5 4 2 1 7 6 5 4 AM2 1 Read FOREGROUND RECEIVE BUFFER see Table 1 2 SIG CANORXFG OREGROU C U see Table Write SUR CANOTXFG e FOREGROUND TRANSMIT BUFFER see Table 1 2 Table 1 2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Bit
13. Bus SPI2 EEPROM IBCR IBIE SPIE SPTIE SP2CR1 SPIE SPTIE ECNFG CCIE CBEIE BE BC FFB8 FFB9 FLASH FCNFG CCIE CBEIE FFB6 FFB7 CANO wake up CANORIER WUPIE FFB4 FFB5 CANO errors CANORIER CSCIE OVRIE FFB2 FFB3 CANO receive CANORIER RXFIE B2 FFBO FFB1 CANO transmit CANOTIER TXEIE2 TXEIEO BO FFAE FFAF wake up I Bit WUPIE AE FFAC FFAD errors I Bit CANTRIER CSCIE OVRIE AC FFAA FFAB receive I Bit RXFIE AA FFA8 FFA9 transmit I Bit CAN1TIER TXEIE2 TXEIEO A8 FFA6 FFA7 FFA4 FFA5 FFA2 FFA3 FFAO FFA1 SFF9E SFF9F Reserved FF9C FF9D FF9A FF9B FF98 FF99 FF96 FF97 wake up I Bit CANARIER WUPIE 96 FF94 FF95 errors I Bit CANARIER CSCIE OVRIE 94 FF92 FF93 receive I Bit CANARIER RXFIE 92 FF90 FF91 CANA transmit I Bit CANATIER TXEIE2 TXEIEO 90 FF8E FF8F Port P Interrupt PTPIF PTPIE FF8C FF8D PWM Emergency Shutdown PWMSDN PWMIE FF80 to 7 FF8B eserve 76 M MOTOROLA MC9S12DT256 Device User Guide V03 03 5 3 Effects of Reset When a reset occurs MCU registers and control bits are changed to known start up states Refer to the respective module Block User Guides for register reset states 5 3 1
14. 59 External Glock Connections 7 0 60 Clock Connections a a hee eee 69 Recommended PCB Layout for 1121 QFP Colpitts Oscillator 84 Recommended PCB Layout for 80QFP Colpitts Oscillator 85 Recommended PCB Layout for 112LQFP Pierce Oscillator 86 Recommended PCB Layout for 80QFP Pierce Oscillator 87 ATD Accuracy Definitions 102 Basic PLE functional diagram 111 Jitter DefiMmtionS a ee ded ne 113 Maximum bus clock jitter approximation 113 SPI Master Timing 0 117 SPI Mast r TmnNg GPHA T uat etch RSS omiies se 118 SPI Slave Timing 0 119 SPI Slave Timing 1 120 General External Bus 0 122 112 pin mechanical dimensions case no 987 126 80 pin Mechanical Dimensions case no 841B 127 11 MC9S12DT256 Device User Guide V03 03 12 44 MOTOROLA MC9S12DT256 Device User Guide V03 03 List of Tables Table 0 1 Derivative Differences 15 Table 0 2 Document
15. is a general purpose input pin and maskable interrupt request input that provides a means of applying asynchronous interrupt requests This will wake up the MCU from STOP or WAIT mode 2 3 20 PEO XIRQ Port E Input Pin 0 PEO is a general purpose input pin and the non maskable interrupt request input that provides a means of applying asynchronous interrupt requests This will wake up the MCU from STOP or WAIT mode 2 3 21 PH7 KWH7 SS2 Port H Pin 7 PH7 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as slave select pin SS of the Serial Peripheral Interface 2 SPD 2 3 22 PH6 KWH6 SCK2 Port I O Pin 6 PH6 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 SPD 2 3 23 PH5 KWH5 MOSI2 Port H I O Pin 5 PHS is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 2 SPD 2 3 24 PHA MISO2 Port I O Pin 2 PH4 is a general purpose input or output pin It can be configured to generate an interrupt causing the MC
16. 55 MC9S12DT256 Device User Guide V03 03 Internal Pull Pin Name Pin Name Pin Name Pin Name Pin Power Resistor Description Funct 1 2 Funct 3 Funct 4 Funct 5 Supply Reset CTRL State VDDX Port P I O Interrupt Channel 4 of Disabled PWM MISO2 of SPI2 VDDX Dres Port P I O Interrupt Channel 3 of isabled SS of VDDX Port P I O Interrupt Channel 2 of Disabled PWM SCK of SPI1 VDDX Port P I O Interrupt Channel 1 of Disabled MOSI of SP11 VDDX CET Port P I O Interrupt Channel 0 of isabled PWM MISO2 of SPI1 VDDX Up Port S I O SS of SPIO VDDX Port S I O of SPIO VDDX Port S 1 0 MOSI of SPIO VDDX Port S I O MISO of SPIO VDDX Port S I O TXD of SCI1 VDDX Port S I O RXD of SCI1 VDDX Port S I O TXD of SCIO PERS PSO RXDO VDDX Up Port S RXD of SCIO PPSS PERT PT 7 0 10C 7 0 VDDX Disabled Port T Timer channels 2 3 Detailed Signal Descriptions 2 3 1 EXTAL XTAL Oscillator Pins EXTAL and XTAL are the crystal driver and external clock pins On reset all the device clocks are derived from the EXTAL input frequency XTAL is the crystal output 2 3 2 RESET External Reset Pin An active low bidirectional control signal it acts as an input to initialize the MCU to a known start up state and an output when an internal MCU function
17. Operating Characteristics 99 Table 9 Electrical 100 Table 10 Conversion Performance 101 Table A 11 NVM Timing 5 104 Table A 12 NVM Reliability 5 105 Table A 13 Voltage Regulator Recommended Load Capacitances 107 Table A 14 Startup Characteristics 109 Table A 15 Oscillator Characteristics am sea rer RR 110 Table A 16 PLL Characteristics 114 Table 17 MSCAN Wake up Pulse Characteristics 115 Table 18 Measurement Conditions 117 Table A 19 SPI Master Mode Timing Characteristics 118 Table 20 SPI Slave Mode Timing Characteristics 120 M MOTOROLA 13 MC9S12DT256 Device User Guide V03 03 Table A 21 Expanded Bus Timing Characteristics 123 14 M MOTOROLA MC9S12DT256 Device User Guide V03 03 Derivative Differences and Document References Derivative Differences Table 0 1 shows the availability of peripheral modules on the various derivatives For details about the
18. Low strobe delay time Low strobe valid time to E rise PWg sp Low strobe hold time D NOACC valid time to E rise PWg tNov ns M MOTOROLA 123 MC9S12DT256 Device User Guide V03 03 Table A 21 Expanded Bus Timing Characteristics Conditions are shown in Table 4 unless otherwise noted 50pF Num Rating Symbol Min Typ Max Unit IPIPO 1 0 valid time to E rise PWg tpop IPIPO 1 0 delay time PWg tp vy IPIPO 1 0 valid time to E fall NOTES 1 Affected by clock stretch add N x where N 0 1 2 or 3 depending on the number of clock stretches 124 M MOTOROLA MC9S12DT256 Device User Guide V03 03 Appendix B Package Information B 1 General This section provides the physical dimensions of the MC9S12DT256 packages M MOTOROLA 125 MC9S12DT256 Device User Guide V03 03 B 2 112 pin LQFP package as Samen X L MORN u ii r 0 13 LMIN SECTION J1 J1 A1 ROTATED 90 COUNTERCLOCKWISE x s1 NOTES 1 MENSIONING AND TOLERANCING PER SME Y14 5M 1994 MENSIONS IN MILLIMETERS ATUMS L M AND N TO BE DETERMINED AT EATING PLANE DATUM T MENSIONS S AND V TO BE DETERMINED AT EATING PLANE DATUM T MENSIONS A AND B DO NOT INCLUDE OLD PROTRUSION ALLOWABLE ROTRUSION IS 0 25 PER SIDE DIMENSIONS AND B INCLUDE MOLD MISMATCH MENSION D D
19. Read Write Read Write MC9S12DT256 Device User Guide V03 03 CRG Clock and Reset Generator Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 RTIBYP COPBYP 0 PLLBYP FCM TCTL7 TCTL6 TCTL4 TCLT3 TCTL2 TCTL1 TCTLO 0 0 0 0 0 0 0 0 Bit 7 6 5 4 2 1 Bit 0 ECT Enhanced Capture Timer 16 Bit 8 Channels Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 087 1056 1055 0894 1083 1082 1051 1050 0 0 0 0 0 0 0 0 FOC7 FOC6 5 FOC4 FOC3 FOC2 1 FOCO OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7MO OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7DO Bit 15 14 18 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 TEN TSWAI TSFRZ 0 0 TOV7 Tove TOV5 TOV4 TOV3 TOV2 OM7 OL7 OM6 OL6 5 OL5 OM4 OL4 OM3 OL3 OM2 OL2 OM1 OL1 OMO OLO EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDGOB C5l cal C2l Col TOI 2 TCRE PR2 PR1 PRO C7F C6F C5F 4 2 1 T E 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 15 14 13 12 11 10 9 Bit 8 31 MC9S12DT256 Device User Guide V03 03
20. Read 0 0 0 0 0 0 0 0 00 6 Reserved Write cc a Read 0 0 0 0 0 0 0 0 00F7 Reserved Write 00F8 00FF SPI2 Serial Peripheral Interface Address Bt7 Bits Bits Bt2 Bit Bit 0 00F8 SPI2CR1 nt SPIE SPE MSTR SSOE LSBFE 00F9 SPI2CR2 BIDIROE 0 spiswai 00FA SPI2BR 2 8 sppro 0 spre 1 sPRO 0 SPTEF MODF 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 00FC Reserved wir EC 00FD 1984 6 5 4 3 2 1 Bito Write Read 0 0 0 0 0 0 0 0 00FE Reserved Write Read 0 0 0 0 0 0 0 0 00FF Reserved Write SSS SS 50100 010F Flash Control Register fts256k Address Bt7 5 Bits Bt2 Bit Bit 0 0100 FCLKDIV ee PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIVO v egeo Read NVS NVA NV3 NV2 SECI SECO Write 0102 FTSTMOD 192 g 0 ee Write 0103 FCNFG 1 Kkevacch 2 1 0 BKSEL1 BKSELO M MOTOROLA 39 MC9S12DT256 Device User Guide V03 03 0100 010F Flash Control Register fts256k Address Bt7 Bits Bits Bit2 Bit Bi
21. compatibility within the MC9S12D Family refer also to engineering bulletin EB386 Table 0 1 Derivative Differences core MC9S12A256 MC9S12DT256 MC9S12DJ256 MC9S12DG256 of CANs 3 2 2 CANO V J1850 BDLC 7 ur Package 112 LQFP 80 112 LQFP 80 112 LOFP 80 QFP 112 LOFP 80 Mask set L91N L91N L91N L91N Temp Options C PV FU PV FU PV FU PV FU An errata exists An errata exists An errata exists An errata exists Notes contact Sales contact Sales contact Sales contact Sales Office Office Office Office The following figure provides an ordering number example for the MC9S12H Family devices MC9S12 DT256 C FU Temperature Options 40 C to 85 C gt Package Option 40 C to 105 C Temperature Option M 40 C to 125 C Device Title Package Options gt Controller Family FU 800 PV 112 LQFP lt a nn M Figure 0 1 Order Partnumber Example M MOTOROLA MC9S12DT256 Device User Guide V03 03 The following items should be considered when using a derivative Table 0 1 e Registers Do not write or read CANO registers after reset address range 0140 017F if using a derivative without CANO Do not write or read CAN Iregisters after reset address range 0180 01 BP if using a derivative without CANI Do not write or read CANA registers after
22. 0 0 0 POLF3 POLF2 POLF1 POLFO Write 0068 ICPAR c 0 PA3EN PA2EN PA1EN PAOEN 0069 pier eo LL 2 9 DLYi Write 006A ICOVW c NOVW7 Novwe Novws Novwa NOVW3 NOVW2 NOVW1 NOVWO 006B ICSYS SH37 SH26 15 SH04 TFMOD PACMX BUFEN LATQ 32 M MOTOROLA MC9S12DT256 Device User Guide V03 03 0040 007F ECT Enhanced Capture Timer 16 Bit 8 Channels Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Read 006C Reserved Write Seb TIMTST Read 0 0 0 0 0 0 0 Test Only Write Read 006E Reserved Write Read 006F Reserved Write 0070 RG Write 0071 PRG ONE Write Read Bit7 6 5 4 3 2 1 Bit 0 0072 PA3H Wie 0073 PA2H dan Bit 7 6 5 4 3 2 1 Bit 0 Write Read Bit7 6 5 4 3 2 1 Bit 0 0074 PA1H Write PEERS eee Read Bit7 6 5 4 3 2 1 Bit 0 0075 PAOH eg 0076 hi Bit 15 14 13 12 11 10 9 Bit 8 Read i 0077 0 pl Bit 6 5 4 3 2 1 Bit 0 Read Bit 15 14 13 12 11 10 9 Bit 8 0078 TCOH hi Read Bit7 6 5 4 3 2 1 Bit 0 0079 TCOH Read Bit 15 14 13 12 11 10 9 Bit 8 007 TCIH hi Write Read Bit7 6 5 4 3 2 1 Bit 0 007B m Read Bit 15 14 13 12 11 10 9 Bit 8 007C TC2H hi Read Bit7 6 5 4 3 2 1 Bit 0 007D TCH o wi
23. 2 3 21 2 3 22 2 3 23 2 3 24 2 3 25 2 3 26 2 3 27 2 3 28 2 3 29 2 3 30 2 3 31 2 3 32 2 3 33 2 3 34 2 3 35 2 3 36 2 3 37 2 3 38 2 3 39 2 3 40 2 3 41 2 3 42 2 3 43 2 3 44 2 3 45 2 3 46 2 3 47 2 3 48 2 3 49 2 3 50 2 3 51 2 3 52 2 3 53 2 3 54 2 3 55 2 3 56 KWH7 882 H 7 61 PH6 KWH6 SCK2 H VO 6 61 KWH5 MOSI2 Port H 5 61 PH4 KWH4 MISO2 Port H 2 61 PH3 KWH3 881 Port Pin 61 PH2 KWH2 5 1 2 62 KWH1 Port H I O Pin 1 62 PHO KWHO MISO1 Port H 0 62 PJ7 KWJ7 SCL PORT J 7 62 PJ6 KWJ6 SDA PORT J Pin 6 62 PJ 1 0 KWJ 1 0 Port J VO Pins 1 0 62 7 ECS ROMONE 7 62 PK 5 0 XADDR 19 14 Port K I O Pins 5 0 63 7 4 Port PiN 7 63 PM6 RXCAN4 Port 6
24. 63 PM5 SCKO Port M I O Pin5 63 PM4 RXCANO RXCAN4 MOSIO Port Pin4 63 1 880 Port Pin3 63 PM2 MISO0 Port Pin 2 63 1 TXB Port M I O 1 64 RXCANO RXB Port 0 64 KWP7 PWM7 SCK2 Pot Pin 7 64 PP6 KWP6 PWM6 SS2 Port P Pin 6 64 PP5 KWP5 PWM5 MOSI2 Port P I O Pin5 64 KWP4 PWM4 MISO2 Port P Pin 4 64 PP3 KWP3 PWM3 881 Port 64 PP2 KWP2 PWM2 SCK1 Port Pin 2 65 1 KWP1 PWM1 Port Pin 1 65 KWPO PWMO MISO1 Port P I O Pin 0 65 PS7ISSH Port 5 dan E IR tes 65 PS6 SCKO Port 6 65 PS5 5 0 5 5 65 PS4 MISO0 Port STO Pin ns e are 65 Port OO Rin ae SO em un a eden ob dos 65 PS2
25. MOTOROLA 50110 011B Address 0119 011A 011B 011C Address 011C 011D 011E 011F Name EADDRLO EDATAHI EDATALO 011F Name Reserved Reserved Reserved Reserved 0120 013F Address 0120 0121 0122 0123 0124 0125 0126 0127 0128 0129 012A 012B 012C M MOTOROLA Name ATD1CTLO ATD1CTL1 ATD1CTL2 ATD1CTL3 ATD1CTL4 ATD1CTL5 ATD1STATO Reserved ATD1TESTO ATD1TEST1 Reserved ATD1STAT1 Reserved Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S12DT256 Device User Guide V03 03 EEPROM Control Register eets4k Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Reserved for RAM Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATD1 Analog to Digital Converter 10 8 Channel Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
26. MOTOROLA MC9S12DT256 Device User Guide V03 03 Component Purpose Type Value C1 VDD1 filter cap ceramic X7R 100 220nF C2 VDD2 filter cap ceramic X7R 100 220nF VDDA filter cap ceramic X7R VDDR filter cap X7R tantalum VDDPLL filter cap ceramic X7R filter cap X7R tantalum OSC load cap OSC load cap PLL loop filter cap See PLL specification chapter PLL loop filter cap Colpitts mode only if recommended by quartz manufacturer PLL loop filter res See PLL Specification chapter Pierce mode only Quartz The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself The following rules must be observed Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins C1 C6 Central point of the ground star should be the VSSR pin Use low ohmic low inductance connections between VSS1 VSS2 and VSSR VSSPLL must be directly connected to VSSR Keep traces of VSSPLL EXTAL and XTAL as short as possible and occupied board area for C7 C8 C11 and 1 as small as possible Do not place other signals or supplies underneath area occupied by C7 C8 C10 and 1 and the connection area to the MCU Central power input should be fed in at the VDDA VSSA pins M MOTOROLA 83 MC9S12DT256 Device User Guide V03 03 Figure 20 1 Recommended PCB Layout for 112
27. No external DC load is allowed Table A 13 Voltage Regulator Recommended Load Capacitances Rating Symbol Min Typ Max Unit Load Capacitance on VDD1 2 Civpp 220 nF Load Capacitance on VDDPLL 220 nF M MOTOROLA 107 MC9S12DT256 Device User Guide V03 03 108 44 MOTOROLA MC9S12DT256 Device User Guide V03 03 A5 Reset Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase Locked Loop PLL A 5 1 Startup Table A 14 summarizes several startup characteristics explained in this section Detailed description of the startup behavior can be found in the Clock and Reset Generator CRG Block Guide Table A 14 Startup Characteristics Conditions are shown in Table A 4 unless otherwise noted Rating T POR release level T POR assert level 0 97 GT Rea piri imm TTE NINE Startup from Reset 5 Interrupt pulse width IRQ mode 20 ns 6 Wait recovery startup time 14 A 5 1 1 POR The release level and the assert level are derived from Vpp Supply They are also valid if the device is powered externally After releasing the POR reset the oscillator and the clock quality check are started If after a time valid oscillation is detected MCU will start using the internal self clock The fas
28. RDRH2 RDRH1 RDRHO 0264 PERH c PERH7 PERH6 PERH5 PERH4 PERH2 PERH1 PERHO 0265 PPSH PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSHO 47 M MOTOROLA MC9S12DT256 Device User Guide V03 03 0240 027F PIM Port Integration Module PIM 9DP256 Address Bt7 Bits Bits Bit2 Bit Bit 0 0266 PIEH PIEH7 PIEH6 5 PIEH4 PIEH3 PIEH2 PIEH1 0267 PIFH PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 0268 PTJ ie PTJ7 PTJ6 0 PTJ1 PTJO Read PTIJ7 PTIT en ead J J6 0 0 0 0 J 10 Write 026A DDRJ i DDRJ7 DDRJ7 DDRJO 026B RDRJ ue RDRJ7 RDRJ6 RDRJ1 RDRJO 026C PERJ iis PERJ7 PERJ6 0 PERJ1 PERJO 026D PPSJ ee PPSJ7 PPSJ6 PPSJ1 PPSJO 026E PIEJ PIEJ6 2 2 0 PIEJ1 PIEJO Write 026F PIFJ Head pips PIE PIFJO Write 0270 027 Reserved Read 0280 02BF Motorola Scalable CAN MSCAN Address Bt7 Bits Bits Bits 2 Bit Bit 0 0280 e EPXACT cswai time wure si PRO INITRO 0281 dd CLKSRC Loops LISTEN 9
29. Write Read Bi 0 0 0 0137 19204 Bit 2 0 Write Read 14 1 12 11 1 9 Bits 0138 1984 gt Write Read Bit7 Bi 40139 ArDipR4L 1984 Bi 19 2 2 0 0 0 Write Read 14 1 12 11 10 9 Bits 013A ATDIDR5H 1949 Bits 3 l Write Read Bi 0 0 0 0138 ATDIDRSL 1084 Bi 1 0 2 0 Write Read 14 1 12 11 10 9 Bits 013C 1949 15 gt Write Read Bi 0 0 0 013D 1084 3 0 Write Read 14 1 12 11 10 9 Bits 013E ATDIDR7H 1984 Write Read Bit7 Bi 0 013F ATDIDR7L 1084 IS 0 0 0 Write 0140 017F Motorola Scalable CAN MSCAN Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0140 CANOCTLO ie HAT LSYNCH tive wUPE SLPRO INITRO 0141 CANOCTLI 1 CLKSRC Loops LISTEN 9 INIT 0142 CANOBTRO SJWi SJWO BRP5 4 BRP3 BRP2 1 42 M MOTOROLA MC9S12DT256 Device User Guide V03 03 0140 017F CANO Motorola Scalable CAN MSCAN Address Name Bit 7 Bit 6 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0143 1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 0144 CANORFLG m WORE cser STADT ROTTO TOATI
30. asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power on STOP or oscillator fail specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected The quality check also determines the minimum oscillator start up time typosc The device also features a clock monitor Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fcMFA Table A 15 Oscillator Characteristics Conditions are shown in Table A 4 unless otherwise noted Rang Symbol Min Crystal oscillator range Colpitts 0 5 16 Crystal oscillator range Pierce 14 0 5 Startup Current Oscillator start up time Colpitts Clock Quality check time out Clock Monitor Failure Assert Frequency External square wave input frequency 4 External square wave pulse width low E P C D P P D D External square wave pulse width high External square wave rise time External square wave fall time Input Capacitance EXTAL XTAL pins Cin DC Operating Bias in Colpitts Configuration on EXTAL Pin Voceias NOTES 1 Depending on the crystal a damping series resistor might be necessary 2 4MHz 22pF 3 Maximum value is for extreme cases using high low frequency crystals 4 XCLKS 0 during r
31. lOC1 PT1 6 PADO4 AN04 IOC2 PT2 17 IOC3 PT3 18 PADO2 ANO2 VDD1 PADO1 ANO1 VSS1 MC9S12DJ256 IOC4 PT4 80 QFP VSS2 5 VDD2 IOC6 PT6 PA7 ADDR15 DATA15 IOC7 PT7 PAG ADDR14 DATA14 MODC TAGHI BKGD PAS ADDR13 DATA13 ADDRO DATAO PBO PA4 ADDR12 DATA12 ADDR1 DATA1 PB1 PA3 ADDR1 1 DATA1 1 ADDR2 DATA2 PB2 PA2 ADDR10 DATA10 ADDR3 DATA3 PB3 PAt ADDR9 DATA9 ADDR4 DATA4 PB4 PAO ADDR8 DATA8 5 5 5 9e 0m CO xt LO OR AN f ork NN CV N N NN e 05 r ow t I 5 mE m to Bd ua gt 93 io GIE 25 co 9 E o 5 Gaon atu gt c 22 lt lt 02 Figure 2 2 Pin Assignments 80 for MC9S12DJ256 2 2 Signal Properties Summary Table 2 1summarizes the pin functionality Signals shown in bold are not available in the 80 pin package Table 2 1 Signal Properties M MOTOROLA 53 MC9S12DT256 Device User Guide V03 03 Internal Pull Pin Name Pin Name Pin Pin Name Pin Power Resistor Description Funct 1 Funct 2 Funct Funct 4 Funct 5 Supply Reset State Oscillator Pins External Reset A Test Inpu
32. state of the ROMHM bit 8000 16K Page Window 16 x 16K Flash EEPROM pages C000 16K Fixed Flash Page 3F 63 00 BER us if active Hed VECTORS ER 905 m FFFF EXPANDED NORMAL SPECIAL SINGLE CHIP SINGLE CHIP Assuming that a 0 was driven onto port K bit 7 during MCU is reset into normal expanded wide or narrow mode 26 M MOTOROLA 1 6 Detailed Register MC9S12DT256 Device User Guide 03 03 The following tables show the detailed register map of the MC9S12DT256 0000 000F Address 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F Name PORTA PORTB DDRA DDRB Reserved Reserved Reserved Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved 0010 0014 Address 0010 0011 M MOTOROLA Name INITRM INITRG Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MEBI map 1 of 3 Core User Guide Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0
33. 0 0 Write Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write BKP Core User Guide Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Head SKEN BKFULL BKBDM Write s BKOMBH BKOMBL BK1MBH BK1MBL BKORWE BKORW BKTRWE BK1RW BKOV5 BKOV4 BKOV2 Read Bid 14 13 12 11 10 9 Bit 8 Write Read BIET 6 5 4 3 2 1 Bit 0 29 MC9S12DT256 Device User Guide V03 03 0028 002F BKP Core User Guide Address Bt7 5 Bits Bt2 Bit 0 002D BKP1X iii BK1V5 BKiV4 BK1V3 BK1V2 002E 1924 pi45 14 13 12 11 10 9 Bit 8 Write 002F Bkpip 16989 gi 6 5 4 3 2 1 Bit 0 Write 0030 0031 MMC map 4 of 4 Core User Guide Address 5 Bits Bt2 Bit 0 0030 PPAGE 0 0 Pixs PIX3 PIX PIXO Read 0 0 0 0 0 0 0 0 0031 Reserved Write 0032 0033 MEBI map 3 of 3 Core User Guide Address SUE ul We 2 EN ids Write Read i 0034 003F CRG Clock and Reset Generat
34. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 Biti Bito Bit 7 6 5 4 3 Bit 2 0 0 0 0 NOACCE PIPOE NECLK LSTRE RDWE MODC MODB MODA 0 IVIS 0 PUPKE 0 PUPEE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMC 1 of 4 Core User Guide Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 15 14 RAM13 12 RAM11 0 0 RAMHAL 0 REG14 REG13 REG12 REG11 0 0 0 27 MC9S12DT256 Device User Guide V03 03 0010 0014 MMC map 1 of 4 Core User Guide Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0012 INITEE EE15 14 1 EE11 9 0013 MISC 1 0 EXSTR EXSTRO ROMHM ROMON Read 0 0 0 0 0 0 0 0 0014 Reserved Write 0015 0016 INT map 1 of 2 Core User Guide Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0015 ITCR m 0 0 0 WRINT ADR3 ADR2 ADR1 Read 0016 ITEST Write INTE INTC INTA INT8 INT6 INT4 INT2 INTO 0017 0017 MMC map 2 of 4 Core User Guide Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read 0 0 0 0 0 0 0 0 0017 Reserved Write 0018 001B Miscellaneous Peripherals Device User Guide Ta
35. Funct 2 Funct Funct 4 Funct 5 Supply Reset CTRL State VDDR Disabled Port H 1 0 Interrupt MISO of SPI2 VDDR Disabled Port I O Interrupt SS of SPI1 VDDR Disabled Port H 1 0 Interrupt SCK of SPI1 MOSI1 VDDR Disabled Port H I O Interrupt MOSI of SPI MISO1 VDDR Disabled Port H I O Interrupt MISO of SPI TXCANA TXCANO VDDX Port J I O Interrupt TX of CANA UP SCL of IIC TX of CANO P KWJ6 RXCAN4 VDDX Port J I O Interrupt RX of CANA ae SDA of RX of CANO PJ 1 0 KWJ 1 0 VDDX Port J I O Interrupts PIG ECS ROMONE VDDX Port I O Emulation Chip Select ROM On Enable Pkis o XADDR ac VDDX PUCR Port K I O Extended Addresses PERM PERN Disabled Port M TX of CANA RXCAN4 Disabled Port M 1 0 RX of CANA TXCANO 1 TXCAN4 TXCANO Disabled PPSM Disabled Disabled Port M of SPIO Port M I O CANO CAN4 MOSI of SPIO Port M I O TX of CAN1 CANO SS of SPIO RXCAN1 RXCANO Disabled Disabled Disabled Port M I O RX of CAN1 CANO MISO of SPIO Port M I O TX of CANO TX of BDLC Port M I O RX of CANO RX of BDLC MOSI2 Disabled Disabled Disabled Port P I O Interrupt Channel 7 of PWM SCK of SPI2 Port P I O Interrupt Channel 6 of PWM SS of SPI2 Port P Interrupt Channel 5 of PWM MOSI of SPI2 M MOTOROLA
36. Guide if using a derivative without CANO Donot write MODRR3 and MODRR2 bits of Module Routing Register 9DP256 Block Guide if using a derivative without CANA Document References 16 M MOTOROLA MC9S12DT256 Device User Guide V03 03 The Device Guide provides information about the MC9S12DT256 device made up of standard HCS 12 blocks and the HCS12 processor core This document is part of the customer documentation A complete set of device manuals also includes the HCS12 Core User Guide and all the individual Block Guides of the implemented modules In a effort to reduce redundancy all module specific information is located only in the respective Block Guide If applicable special implementation details of the module are given in the block description sections of this document See Table 0 2 for names and versions of the referenced documents throughout the Device User Guide Table 0 2 Document References User Guide Version Document Order Number CPU12 Reference Manual CPU12RM AD HCS12 Multiplexed External Bus Interface MEBI Block Guide HCS12 Module Mapping Control MMC Block Guide HCS12 Interrupt INT Block Guide HCS12 Background Debug Block Guide HCS12 Breakpoint BKP Block Guide S12BKPV1 D Clock and Reset Generator CRG Block User Guide S12CRGV4 D 1 1 Enhanced Capture Timer ECT 16 8 Block User Guide 1 S12ECT16B8CV1 D 1 1 V04 V04 VO VO Analog to Digital Converter 10 Bit 8
37. IRQEN FFFO FFF1 FFEE FFEF FFEC FFED FFEA FFEB Real Time Interrupt Enhanced Capture Timer channel 0 Enhanced Capture Timer channel 1 Enhanced Capture Timer channel 2 CRGINT RTIE FFE8 FFE9 Enhanced Capture Timer channel 3 FFE6 FFE7 Enhanced Capture Timer channel 4 FFE4 FFES FFE2 FFE3 FFEO FFE1 Enhanced Capture Timer channel 5 Enhanced Capture Timer channel 6 Enhanced Capture Timer channel 7 Bit 2 RES TIE C71 FFDE FFDF Enhanced Capture Timer overflow TSRC2 TOF FFDC FFDD Pulse accumulator A overflow PACTL PAOVI FFDA FFDB Pulse accumulator input edge PACTL PAI FFD8 FFD9 SPIO SPIE SPTIE SCOCR2 FFD6 FFD7 SCIO I Bit TIE TCIE RIE ILIE D6 SC1CR2 FFD4 FFD5 SCI1 I Bit TIE TCIE RIE ILIE D4 FFD2 FFD3 ATDO I Bit ATDOCTL2 ASCIE D2 M MOTOROLA 75 MC9S12DT256 Device User Guide V03 03 FFDO FFD1 ATD1 I Bit ATD1CTL2 ASCIE DO FFCE FFCF Port J I Bit PTJIF PTJIE CE FFCC FFCD Port H I Bit PTHIF PTHIE CC FFCA FFCB Modulus Down Counter underflow MCCTL MCZI CA FFC8 FFC9 Pulse Accumulator B Overflow PBCTL PBOVI C8 FFC6 FFC7 CRG PLL lock CRGINT LOCKIE FFC4 FFC5 CRG Self Clock Mode CRGINT SCMIE FFC2 FFC3 BDLC DLCBCR IE FFCO FFC1 FFBE FFBF FFBC FFBD FFBA FFBB
38. Interface 6 3 1 Device specific information e PUCR Reset State 90 6 4 HCS12 Interrupt INT Block description Consult the INT Block guide for information on HCS12 Interrupt block 6 5 HCS12 Background Debug BDM Block Description Consult the BDM Block guide for information on HCS12 Background Debug block M MOTOROLA 79 MC9S12DT256 Device User Guide 03 03 6 6 HCS12 Breakpoint BKP Block Description Consult the BKP Block guide for information on HCS12 breakpoint block Section 7 Clock and Reset Generator CRG Block Description Consult the CRG Block User Guide for information about the Clock and Reset Generator module 7 1 Device specific information 7 1 1 XCLKS The XCLKS input signal is active low see 2 3 13 PE7 NOACC XCLKS Port E I O Pin 7 Section 8 Enhanced Capture Timer ECT Block Description Consult the ECT 16B8C Block User Guide for information about the Enhanced Capture Timer module When the ECT 16B8C Block Guide refers to freeze mode this is equivalent to active mode Section 9 Analog to Digital Converter ATD Block Description There are two Analog to Digital Converters ATD1 and 0 implemented on the MC9S12DT256 Consult the 10 8 Block User Guide for information about each Analog to Digital Converter module When the 10B8C Block Guide refers to freeze mode this is equivalent to active mode Section 10 Inter IC Bus Block Description Cons
39. M note SLAVE MSB OUT BIT6 1 X SLAVE LSB OUT ir MOSI INPUT NOTE Not defined Figure A 8 SPI Slave Timing CPHA 1 In Table A 20 the timing characteristics for slave mode are listed Table A 20 SPI Slave Mode Timing Characteristics Num Characteristic Symbol Min Typ Max Unit 1 SCK Frequency fsck DC 1 4 fous 1 SCK Period lsck 4 thus 2 Enable Lead Time tlead 4 tous 3 Enable Lag Time tlag 4 tous 4 Clock SCK High or Low Time twsck 4 tous 5 Data Setup Time Inputs tsu ee ee ns 6 Data Hold Time Inputs thi ee ee ee ns 7 Slave Access Time time to data active ta 20 ns 8 Slave MISO Disable Time 22 ns 9 Data Valid after Edge tysck 30 tpus ns 10 Data Valid after SS fall ns 11 Data Hold Time Outputs tho 20 ns 12 Rise and Fall Time Inputs 8 ns 13 Rise and Fall Time Outputs 8 ns NOTES 1 tbus added due to internal synchronization delay 120 M MOTOROLA MC9S12DT256 Device User Guide 03 03 A 8 External Bus Timing A timing diagram of the external multiplexed bus is illustrated in Figure A 9 with the actual timing values shown on table Table A 21 AII major bus signals are included in the diagram While both a data write and data read cycle are shown only one or the other would occur on a particular bus cycle A 8 1
40. MOTOROLA User Guide Sheet M MOTOROLA MC9S12DT256 Device User Guide V03 03 129 MC9S12DT256 Device User Guide V03 03 FINAL PAGE OF 130 PAGES 130 M MOTOROLA MC9S12DT256 Device User Guide V03 03 Section 1 IntroductionMC9S12DT256 1 1 Overview The MC9S12DT256 microcontroller unit MCU is a 16 bit device composed of standard on chip peripherals including a 16 bit central processing unit HCS12 CPU 256K bytes of Flash EEPROM 12K bytes of RAM 4 bytes of EEPROM two asynchronous serial communications interfaces SCT three serial peripheral interfaces SPD an 8 channel IC OC enhanced capture timer two 8 channel 10 bit analog to digital converters ADC an 8 channel pulse width modulator PWM a digital Byte Data Link Controller BDLC 29 discrete digital I O channels Port A Port B Port K and Port E 20 discrete digital I O lines with interrupt and wakeup capability three CAN 2 0 A B software compatible modules MSCAN12 and an Inter IC Bus The MC9S12DT256 has full 16 bit data paths throughout However the external bus can operate in an 8 bit narrow mode so single 8 bit wide memory can be interfaced for lower cost systems The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements 1 2 Features e HCS12 Core 16 bit HCS12 CPU i Upward compatible with M68HC11 instruction set ii Interrupt stacking and programmer s model id
41. Regulator Reference VDDPLL VSSPLL VSSA z Voltage Regulator 5V amp VDDR VSSR M MOTOROLA gt XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19 Signals shown in Bold are not available on the 80 Pin Package 23 MC9S12DT256 Device User Guide V03 03 1 5 Device Memory Map Table 1 1 and Figure 1 2 show the device memory map of the MC9S12DT256 after reset Note that after reset the bottom 1k of the EEPROM 0000 03FF are hidden by the register space 24 Table 1 1 Device Memory Map Address Module Bytes 0000 0017 CORE Ports A B E Modes Inits Test 24 0018 0019 Reserved 2 001A 001B Device ID register PARTID 2 001C 001F CORE MEMSIZ IRQ HPRIO 4 0020 0027 Reserved 8 0028 002F CORE Background Debug Mode 8 0030 0033 CORE PPAGE Port K 4 0034 003F Clock and Reset Generator PLL RTI COP 12 0040 007F Enhanced Capture Timer 16 bit 8 channels 64 0080 009F Analog to Digital Converter 10 bit 8 channels ATDO 32 00A0 00C7 Pulse Width Modulator 8 bit 8 channels PWM 40 00C8 00CF Serial Communications Interface SCIO 8 00D0 00D7 Serial Communications Interface SCI1 8 00D8 00DF Serial Peripheral Interface SPIO 8 00 0 00E7 Inter IC Bus 8 00E8 00EF Byte Data Link Controller BDLC 8 5000 00F7 S
42. operating conditions are less than worst case or leakage induced error is acceptable larger values of source resistance is allowed A 2 2 2 Source Capacitance When sampling an additional internal capacitor is switched to the input This can cause a voltage drop due to charge sharing with the external and the pin capacitance For a maximum sampling error of the input voltage ILSB then the external filter capacitor 2 1024 Cins A 2 2 3 Current Injection There are two cases to consider 1 A current is injected into the channel being converted The channel being stressed has conversion values of 3FF FF 8 bit mode for analog inputs greater than and 000 for values less than unless the current is higher than specified as disruptive condition 2 Current is injected into pins in the neighborhood of the channel being converted A portion of this current is picked up by the channel coupling ratio K This additional current impacts the accuracy of the conversion depending on the source resistance The additional input voltage error on the converted channel be calculated as Vggg Rg With being the sum of the currents injected into the two pins adjacent to the converted channel Table A 9 ATD Electrical Characteristics Conditions are shown in Table A 4 unless otherwise noted Num Rating Symbol Min Typ Max Unit 1 input Source Resistance Rs 1
43. pins Refer to the HCS12 Core User Guides for mode dependent pin configuration of port E and out of reset Refer to the PIM Block User Guide for reset configurations of all peripheral module ports NOTE For devices assembled in 80 pin QFP packages all non bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs Refer to Table 2 1 for affected pins 5 3 2 Memory Refer to Table 1 1 for locations of the memories depending on the operating mode after reset The RAM array is not automatically initialized out of reset 77 M MOTOROLA MC9S12DT256 Device User Guide V03 03 78 44 MOTOROLA MC9S12DT256 Device User Guide V03 03 Section 6 HCS12 Core Block Description 6 1 CPU12 Block Description Consult the CPU12 Reference Manual for information on the CPU When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock Periods 6 2 HCS12 Module Mapping Control MMC Block Description Consult the MMC Block User Guide for information on the Module Mapping Control Block 6 2 1 Device specific information Reset state 01 Bits 11 15 are writeable once in Normal and Emulation Mode e PPAGE Reset state 00 Register is writeable anytime in all modes 6 3 HCS12 Multiplexed External Bus Interface MEBI Block Description Consult the MEBI Block Guide for information on Multiplexed External Bus
44. 0 IOC 7 0 Port T I O Pins 7 0 PT7 PTO are general purpose input or output pins They can be configured as input capture or output compare pins IOC7 IOCO of the Enhanced Capture Timer ECT 2 4 Power Supply Pins MC9S12DT256 power and ground pins are described below NOTE All VSS pins must be connected together in the application 2 4 1 VDDX VSSX Power amp Ground Pins for Drivers External power and ground for I O drivers Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible Bypass requirements depend on how heavily the MCU pins are loaded 2 4 2 VDDR VSSR Power amp Ground Pins for Drivers amp for Internal Voltage Regulator External power and ground for I O drivers and input to the internal voltage regulator Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible Bypass requirements depend on how heavily the MCU pins are loaded 66 MOTOROLA MC9S12DT256 Device User Guide V03 03 2 4 3 VDD1 VDD2 VSS1 VSS2 Core Power Pins Power is supplied to the MCU through VDD and VSS Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequ
45. 0 00E2 IBCR MSSE TXRX TXAK a IBSWAI DE ut Read IAAS m 0 SRW Write 00E4 IBDR Read b7 D6 D5 D4 D3 D2 D1 DO Write Read 0 0 0 0 0 0 0 00E5 Reserved Write Read 0 0 0 0 0 0 0 0 00E6 Reserved Write Read 0 0 0 0 0 0 0 0 00E7 Reserved Write 00E8 00EF BDLC Bytelevel Data Link Controller J1850 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00E8 DLCBCRI e IMSG CLKS IE WCM 0 0 13 12 T 10 0 0 Write 00EA DLCBCR2 c SMRST DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFRO 00EB DLCBDR 07 06 05 04 03 02 D1 DO 00EC DLCBARD c RXPOL 0 0 BO3 BO2 0 00ED DLCBRSR 0 5 R4 R3 R2 R1 RO 00EE DLCSCR 1929 DO BDLCE 9 0 gt Write En 0 0 0 0 0 0 IDLE Write 38 M MOTOROLA MC9S12DT256 Device User Guide V03 03 00F0 00F7 Serial Peripheral Interface Address Bt7 Bits Bits Bt2 Biti Bit 0 00FO SPIICRI 2 SPIE SPE MSTR SSOE LSBFE 00F SPIHCR2 BIDIROE 0 spiswai 00F2 2 8 sppro 0 spre 1 sPRO 0 SPTEF 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 00 4 Reserved 00F5 spipR 1984 pit 6 5 4 3 2 1 Bito Write
46. 0 100 C Operating Ambient Temperature Range Ta 40 27 85 C MC9S12DT256V Operating Junction Temperature Range 40 120 C Operating Ambient Temperature Range Ta 40 27 105 C MC9S12DT256M Operating Junction Temperature Range 40 140 C Operating Ambient Temperature Range 40 27 125 C NOTES 1 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I O supply The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external Source 2 Please refer to Section A 1 8 Power Dissipation and Thermal Characteristics for more details about the rela tion between ambient temperature T4 and device junction temperature A 1 8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related The user must assure that the maximum operating junction temperature is not exceeded The average chip junction temperature Ty in can be obtained from M MOTOROLA 93 MC9S12DT256 Device User Guide V03 03 Tj Ta Pp ja Junction Temperature C T Ambient Temperature C P D Total Chip Power Dissipation W Package Thermal Resistance C W The total power dissipation can be calculated from Pp PINT Chip Internal Power Dissipation W Two cases with internal voltage regulator enabled and disabled m
47. 0 mA P only RTI enabled 1 5 Pseudo Stop Current RTI and COP disabled 2 C 40 370 27 400 500 70 450 3 C 85 C 550 C Temp Option 100 C DDPS 600 1600 105 650 V Temp Option 120 800 2100 C 125 C 850 P Temp Option 140 C 1200 5000 Pseudo Stop Current RTI and COP enabled 1 2 C 40 C 570 C 27 C 600 C 70 C 650 PRES 750 105 850 125 1200 140 1500 Stop Current C 40 C 12 P 27 25 100 70 100 85 130 Pp C Temp Option 100 C PPS 160 1200 C 105 C 200 P V Temp Option 120 C 350 1700 C 125 C 400 140 600 5000 NOTES 1 PLL off 2 At those low power dissipation levels Ta be assumed 98 MOTOROLA MC9S12DT256 Device User Guide V03 03 A 2 ATD Characteristics This section describes the characteristics of the analog to digital converter 2 1 ATD Operating Characteristics The Table A 8 shows conditions under which the ATD operates The following constraints exist to obtain full scale full range results Vssa lt lt lt lt Vppa This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to If the input level goes outside of this range it will effectively be clipped Table A 8 ATD Operating Characteristics Conditions are shown in Table A 4 unless otherwise noted
48. 0CD 00CE 00CF Name SCIOBDH SCIOBDL SCIOCR1 SCIOCR2 SCIOSR1 SCIOSR2 SCIODRH SCIODRL 00D0 00D7 Address 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 Name SCI1BDH SCHBDL SCI1CR1 SCHCR2 SCHSR1 SCHSR2 SCHDRH SCHDRL 00D8 00DF Address 00D8 00D9 00DA 00DB M MOTOROLA Name SPIOCR1 SPIOCR2 SPIOBR SPIOSR Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write SCIO Asynchronous Serial Interface Bit 7 0 SBR7 LOOPS TIE TDRE R8 R7 T7 SCI Asynchronous Serial Interface Bit 7 0 SBR7 LOOPS TIE TDRE R8 R7 T7 Bit 6 0 SBR6 SCISWAI TCIE TC 0 T8 R6 T6 Bit 6 0 SBR6 SCISWAI TCIE TC 0 T8 R6 T6 Bit 5 0 SBR5 RSRC RIE RDRF 0 0 R5 T5 Bit 5 0 SBR5 RSRC RIE RDRF 0 0 R5 T5 MC9S12DT256 Device User Guide V03 03 Bit 4 SBR12 SBR4 M ILIE IDLE R4 T4 Bit 4 SBR12 SBR4 M IDLE R4 T4 Bit 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 Bit 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 SPIO Serial Perip
49. 1 5 2 66 PS1 TXDO 15 1 66 MC9S12DT256 Device User Guide V03 03 2 357 PS0 RXDO Port S VORN Qd uo Dos a hee eee ee k her 66 2358 7 0 1 7 0 Port T I O Pins 7 0 RE cte 66 24 Power oupplyPIBSs vascos ths Dus qa USE Send ate 66 2 4 1 VDDX VSSX Power amp Ground Pins for I O Drivers 66 2 4 2 VDDR VSSR Power amp Ground Pins for I O Drivers amp for Internal Voltage Regulator 66 2 4 3 VDD1 VDD2 VSS1 VSS2 Core Power 67 2 4 4 VDDA VSSA Power Supply Pins for and VREG 67 2 4 5 VRL Reference Voltage Input Pins 67 2 4 6 VDDPLL VSSPLL Power Supply Pins for _ 67 2 4 7 VREGEN On Chip Voltage Regulator Enable 68 Section 3 System Clock Description Sel rd ER 69 Section 4 Modes of Operation 45 mel oh hobs heated eed Dare a LE A 71 42 Chip Configuration Summary bandes dere Rte um Re ES eee ee 71 2 3 aa uL 72 4 3 1 Securing the Microcontroller 72 4 3 2 Operation of
50. 1 20000 mass NVMOP The setup time can be ignored for this operation A 3 1 5 Blank Check The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non blank word starting at relative address zero It takes one bus cycle per word to verify plus a setup of the command t check location 10 Table 11 NVM Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted Num Rating Symbol Min Typ Max Unit 1 D External Oscillator Clock MC9S12DT256C lt V M fNvMOSC 0 5 501 2 2 D Bus frequency for Programming or Erase Operations fNvmuBus 4 P Single Word Programming Time 5 D Burst Programming consecutive word us 6 D Flash Burst Programming Time for 32 Words 4 us 7 Sector Erase Time 9 D Blank Check Time Flash per block we 10 D Blank Check Time EEPROM per block tcheck 2058 1 Restrictions for oscillator in crystal mode apply 2 Minimum Programming times are achieved under maximum NVM operating frequency and maximum bus frequency fous 104 MOTOROLA MC9S12DT256 Device User Guide V03 03 3 Maximum Erase and Programming times are achieved under particular combinations of fyymor and bus frequency fpus Refer to formulae in Sections A 3 1 1 A 3 1 4 for guidance 4 Burst Programming ope
51. 12DT256 Device User Guide V03 03 CAN1 Motorola Scalable CAN MSCAN Bit 7 RXFRM CANE SJW1 SAMP WUPIF WUPIE 0 0 0 RXERR7 TXERR7 AC7 AC7 AC7 AC7 AM7 AM7 AM7 AM7 AC7 Bit 6 RXACT CLKSRC SJWO TSEG22 CSCIF CSCIE 0 0 0 RXERR6 TXERR6 AC6 AC6 AC6 AC6 6 6 6 6 6 Bit 5 CSWAI LOOPB BRP5 TSEG21 RSTAT1 RSTATE1 0 0 RXERR5 TXERR5 AC5 AC5 AC5 AC5 5 5 5 5 5 Bit 4 SYNCH LISTEN BRP4 TSEG20 RSTATO RSTATEO 0 0 RXERR4 TXERR4 ACA ACA ACA ACA AM4 AM4 AM4 AM4 ACA Bit 3 TIME 0 BRP3 TSEG13 TSTAT1 TSTATE1 0 0 0 RXERR3 TXERR3 Bit 2 WUPM BRP2 TSEG12 TSTATO TSTATEO TXE2 TXEIE2 ABTRQ2 ABTAK2 TX2 IDHIT2 0 0 RXERR2 TXERR2 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 AC2 Bit 1 SLPRQ SLPAK BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 1 1 TX1 IDHIT1 0 0 RXERR1 TXERR1 AC1 AC1 1 1 1 1 1 1 1 Bit 0 INITRQ INITAK BRPO TSEG10 RXF RXFIE TXEO TXEIEO ABTRQO ABTAKO TXO IDHIT
52. 4 Maximum bus clock jitter approximation M MOTOROLA 113 MC9S12DT256 Device User Guide V03 03 This is very important to notice with respect to timers serial modules where a pre scaler will eliminate the effect of the jitter to a large extent Table A 16 PLL Characteristics Conditions are shown in Table A 4 unless otherwise noted ating Te Mec Unt LCS 2 VCO locking range fvco 8 50 3 Lock Detector transition from Acquisition to Tracking rel 3 4 mode Lock Detection lALockl 1 5 p Lock Detector transition from Tracking to Acquisition unt mode PLLON Total Stabilization delay Auto Mode 9 tstab PLLON Acquisition mode stabilization delay 2 tacq PLLON Tracking mode stabilization delay 2 tal CS fn Fitting parameter loop frequency Charge pump current acquisition mode Lich 38 5 Charge pump current tracking mode ien 3 5 EXIIT I TIC EE 15 Jitter fit parameter 22 lo 96 NOTES 1 96 deviation from target frequency 2 4 fgus 25MHz equivalent fyco 50MHz REFDV 03 018 Cs 4 7nF Cp 470pF Rs 10KQ 114 M MOTOROLA MC9S12DT256 Device User Guide V03 03 A 6 MSCAN Table 17 MSCAN Wake up Pulse Characteristics Conditions are shown in Table A 4 unless otherwise noted Num Rating Symbol Min Typ Max Unit 1 Wake up
53. 5 PLANE CHT MOLD PROTRUSION ALLOWABLE J 013 023 PROTRUSION IS 0 25 PER SIDE DIMENSIONS A AND DO INCLUDE MOLD MISMATCH 065 0 95 AND ARE DETERMINED AT DATUM PLANE H L 12 35 REF 7 DIMENSION D DOES NOT INCLUDE DAMBAR M 109 PROTRUSION ALLOWABLE DAMBAR N 17 PROTRUSION SHALL 0 08 TOTAL IN 0 13 0 EXCESS OF THE D DIMENSION AT MAXIMUM 0 325 BSC Q MATERIAL CONDITION DAMBAR CANNOT Q oo 79 BE LOCATED ON THE LOWER RADIUS OR 013 030 THE FOOT S 1695 1745 T 0 18 DETAIL C Wl sl 1695 1745 W 035 045 X 1 6 REF Figure B 2 80 pin QFP Mechanical Dimensions case no 841B M MOTOROLA 127 MC9S12DT256 Device User Guide V03 03 128 44 MOTOROLA
54. 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Extended ID Read 1028 ID27 ID26 ID25 ID24 ID23 ID22 ID21 Standard ID Read 1010 ID9 ID8 07 06 05 04 ID3 CANxRIDRO Write Extended ID 1020 019 1018 SRR 1 IDE 1 017 016 015 xxx1 Standard ID Read ID2 ID1 IDO RTR IDE 0 CANXRIDR1 Write M MOTOROLA 43 MC9S12DT256 Device User Guide V03 03 Table 1 2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Extended ID Read 1014 ID13 ID12 ID11 ID10 ID9 ID8 ID7 xxx2 Standard ID Read CANXRIDR2 Write Extended ID Read ID6 ID5 04 ID3 ID2 ID1 00 RTR xxx3 Standard ID Read CANXRIDR3 Write xxx4 CANXRDSRO Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO xxxB CANXRDSR7 Write oxC CANRXDLR 1980 DLC3 DLC2 DLCO Write Read xxxD Reserved Write oxE CANXRTSRH ind TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 oxF We TSR7 TSR6 TSR5 TSR4 TSR3 1662 TSR1 TSRO Extended ID Read CANXTIDRO Write Standard ID Read Write Extended ID Read CANXTIDR1 Write Standard ID Read Write Extended ID Read CANXTIDR2 Write Standard ID Read Write Extended ID Read CANXTIDR3 Write Standard ID Read Write 14 CANXTDSRO Read 1 CANXTDSR7 Write xx1C CANxTDLR e DLC3 DLC2 0 CONXTTBPR ii
55. ADDR4 DATA4 PB4 28 PAO ADDR8 DATA8 amp UUUUUUUUUUU UU UU UU UU UU UU UU 0 CO LZ SA SBAKSOZGG BEEsssschig ES 2 6662 e erpo9ssoss 22558 555 3522258 25222 222 Signals shown Bold are available on the 80 Pin Package Figure 2 1 Pin Assignments in 112 pin 52 M MOTOROLA MC9S12DT256 Device User Guide V03 03 oS e 2288 gt 2322383 2 zo o lt lt lt FOUR von gt lt x ox gt gt gt 2 SEE 16265 Sosy reox x oo 22222206 lt O N lt lt lt lt lt lt roo OQOOCOOCO 5zoaonno lt lt lt lt nO 0 9 I zx ss LU OS A gt gt gt gt gt gt gt gt gt gt O t LO st r m m rnm rr rc e cO co SST PWM3 KWP3 PP3 1 VRH SCK1 PWM2 KWP2 PP2 2 VDDA MOSI1 PWM1 KWP1 PP1 13 PADO7 ANO7 ETRIGO MISO1 PWMO KWPO PPO C 4 PADO6 ANO6 IOCO PTO 5 PADO5 AN05
56. Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADPU AFFC ETRIGLE ETRIGP ETRIG LAS 58 54 S2C S1C FIFO FRZ1 FRZO SRES8 SMP1 PRS4 PRS3 PRS2 PRS1 PRSO DJM DSGN SCAN MULT CC CB CA SCF 0 ETORF FIFOR 0 CC2 CC1 CCO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCF7 CCF6 CCF5 CCF4 CCF2 CCF1 CCFO 0 0 0 0 0 0 0 0 41 MC9S12DT256 Device User Guide V03 03 0120 013F ATD1 Analog to Digital Converter 10 Bit 8 Channel Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 50120 ATDIDIEN 108 gi 6 5 4 3 2 1 Bit 0 Write Read 0 0 0 0 0 0 0 0 012E Reserved Write Read 4 2 1 BIT 0 012F 1984 Bit 2 Write Read 14 1 12 11 10 9 Bits 0130 ATDiDROH 1924 Bits 3 l Write Read Bi 0 0 0131 ATDIDROL 10984 Bi 19 0 0 0 Write Read 14 1 12 11 1 9 Bits 0132 1084 gt Write Read 0 0133 ATDIDRIL 10984 Bi 0 0 0 0 0 Write Read 14 1 12 11 1 9 Bits 0134 ATDIDR2H 1984 5 0 Write Read 0 0135 2 1984 Bit IS 0 0 2 Write Read 14 1 12 11 10 9 Bits 0136 ATD1DR3H 1949 15 3 l
57. C9S12DJ256 MC9S 12DG256 and 9512 256 is also available in a 80 pin quad flat pack QFP Most pins perform two or more functions as described in the Signal Descriptions Figure 2 1 and Figure 2 2 show the pin assignments M MOTOROLA 51 MC9S12DT256 Device User Guide V03 03 8 2885 NO 9 22220 0 gt 210 co lt lt lt lt 20299902 5 2222 2 zz 55545525 988555856 an RAPPEL RRRELTOANE ESEE SSSR DO 2 D 0O C 0 0 0 0 0 0 0 0 0 0 gt z SS1 PWM3 KWP3 PP3 I m ame en nn VRH SCK1 PWM2 KWP2 PP2 VDDA MOSI1 PWM1 KWP1 PP1 PAD15 AN15 ETRIG1 MISO1 PWMO KWPO PPO PADO7 ANO7 ETRIGO XADDR17 PK3 PAD14 AN14 XADDR16 PK2 PADO6 AN06 XADDR15 PK1 PAD13 AN13 XADDR14 PKO PADO5 AN05 IOCO PTO PAD12 AN12 IOC1 PT1 04 4 IOC2 PT2 PAD11 AN11 IOC3 PT3 PADO3 AN03 VDD1 PAD10 AN10 551 MC9S12DT256 MC9S12A256 PADO2 ANO2 IOC4 PT4 MC9S12DJ256 MC9S12DG256 PADO9 ANO9 5 PADO1 ANO1 IOC6 PT6 08 IOC7 PT7 PADOO ANOO XADDR19 PK5 VSS2 XADDR18 PK4 VDD2 KWJ1 PJ1 PA7 ADDR15 DATA15 KWJ0 PJ0 PA6 ADDR14 DATA14 MODC TAGHI BKGD PA5 ADDR13 DATA13 ADDRO DATAO PBO PA4 ADDR12 DATA12 ADDR1 DATA1 PB1 PA3 ADDR11 DATA11 ADDR2 DATA2 PB2 PA2 ADDR10 DATA10 ADDR3 DATA3 PB3 PA1 ADDR9 DATA9
58. Channels 10 8 Block User Guide S12ATD10B8CV2 D V03 VO V03 S12MEBIV3 D S12MMCV4 D S121NTV1 D 12BDMV4 D LE Inter IC Bus S12SPIV3 D Serial Peripheral Interface 5 1 Block User Guide V02 S12EETS4KV2 D 4K Byte EEPROM EETS4K Byte Level Data Link Controller J1850 BDLC Motorola Scalable CAN MSCAN Block User Guide 2 S12MSCANV2D Block User Guide S12VREGV1 D Block User Guide S12PIM9DP256V3 D voz 510800 TT Le a Block User Guide Block User Guide Voltage Regulator VREG Port Integration Module 9DP256 Oscillator Table 0 3 shows the Specification Change Summary Maskset LOIN Table 0 3 Specification Change Summary for Maskset L91N Block Spec Change MCU 9DT256 removed CAN2 and HCS12 V1 5 The Background Debug Module includes an Acknowledge Protocol two additional hardware commands ENABLE ACK DISABLE The state of PK7 ROMCTL is latched into ROMON Bit during RESET into Emulation Mode or Normal Expanded Mode CRG Maskset includes an additional Pierce Oscillator HCS12 V1 5 17 M MOTOROLA MC9S12DT256 Device User Guide V03 03 Table 0 3 Specification Change Summary for Maskset L91N Block Spec Change EETSAK FTS256K Reliability Specification for Non Volatile Memories PIM 9DP256 CANO can be routed to PORTJ 18 M
59. DGV3 D Revision History ies Author Description of Changes V03 00 24 March Initial version for Maskset L91N based on MC9S12DP256B 2003 V02 11 e added new HCS12 core documentation 1 30 June e added cumulative program erase cycle limitation 2003 to Table A 12 for EEPROM updated Table 0 2 Document References removed cumulative program erase cycle limitation from Table A 12 for EEPROM vos o2 24 July 2008 added LRAE generic load and execute info to section 15 V03 03 207 e Added MC9S12DT256 in QFP 80 to Table 0 1 Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all c
60. DOCUMENT NUMBER 9S12DT256DGV3 D MC9S12DT256 Device User Guide V03 03 Covers also 9512 256 MC9S12DJ256 951200256 Original Release Date 24 March 2003 Revised 26 July 2003 Motorola Inc Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part M MOTOROLA DOCUMENT NUMBER 9S12DT256
61. DRM4 DDRM3 DDRM2 DDRM1 DDRMO 0253 RDRM no RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 1 RDRMO 0254 PERM PERM7 6 PERM5 PERM4 PERM3 PERM2 1 PERMO 0255 PPSM se PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 1 PPSMO 0256 WOMM 1 WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMMO 0257 MODRR ii 0 MODRR6 MODRRS MODRR4 MODRR3 MODRR2 MODRR1 MODRRO Read 0258 PTP Wite PTP6 PTPS 2 PTPO Read PTIP7 6 PTIP2 0259 PTIP eag Write 025A DDRP e DDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRPO 025B RDRP iis RDRP7 RDRP6 5 RDRP4 RDRP3 RDRP2 RDRP1 RDRPO 025C PERP Te PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERPO 025D PPSP PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSSO Read 025E PIEP PIEP7 PIEPG PIEPS PIEP4 PIEP2 Read 025F PIFP Wate PIFP7 PIFP6 PIFPS PIFP4 PIFP3 PIFP2 PIFPT PIFPO Read 0260 PTH PTH6 PTHS PTH4 PTH2 PTHi PTHO Read PTIH7 PTIHe PTIHS PTIH3 PTIH2 0261 PTIH eag 5 Write 0262 DDRH ne DDRH7 DDRH7 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRHO 0263 RDRH RDRH7 RDRH6 RDRH5 RDRH4
62. DRT2 RDRT1 RDRTO 0244 PERT PERT7 PERT6 PERT5 PERT3 PERT2 PERTO 0245 PPST joe PPST7 PPST6 5 5 4 PPST3 PPST2 1 PPSTO Read 0 0 0 0 0 0 0 0 0246 Reserved Write Read 0 0 0 0 0 0 0 0 0247 Reserved Write 0248 PTS 4 PTS7 PTS6 PTS5 PTS4 PTS3 52 51 PTSO Read PTIS7 PTIS4 PTIS2 pris 25249 Pris ead S S6 S5 S S3 S S 50 Write 024A DDRS WE DDRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRSO 024B RDRS RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRSO 024C PERS no PERS7 PERS6 PERSS PERS4 PERS3 PERS2 PERS1 PERSO 46 MOTOROLA 0240 027 MC9S12DT256 Device User Guide 03 03 Port Integration Module 9DP256 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 024D PPSS nie PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSSO 024E WOMS e WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMSO Read 0 0 0 0 0 0 0 0 024F Reserved Write 0250 PTM PTM7 6 5 4 PTM3 PTM2 1 PTMO Read PTIM7 PTIM6 5 PTIM4 PTIM2 0251 PTIM eag Write 0252 DDRM DDRM7 DDRM7 DDRM5 D
63. General Muxed Bus Timing The expanded bus timings are highly dependent on the load conditions The timing parameters shown assume a balanced load across all outputs 121 M MOTOROLA MC9S12DT256 Device User Guide V03 03 1 2 gt 3 lt 4 ECLK PE4 Addr Data read PA PB Addr Data write PA PB Non Multiplexed Addresses PK5 0 ECS PK7 RW PE2 Figure A 9 General External Bus Timing 122 M MOTOROLA MC9S12DT256 Device User Guide 03 03 Table A 21 Expanded Bus Timing Characteristics Conditions are shown in Table 4 unless otherwise noted 50pF Num Rating Symbol Min Typ Max Unit Frequency of operation E clock fo 0 25 0 MHz GT rue Pulse width E low 4 Pulse width high 5 Address delay time 6 Address valid time to E rise PWEL tap 7 Muxed address hold time ER Address hold to data valid 10 Read data setup time 11 Read data hold time 12 Write data delay time 14 Write data setup time PWeH tppw ipsw 15 Address access time tacca pr Non multiplexed address delay time Non muxed address valid to E rise PWg tNAp Non multiplexed address hold time Chip select delay time Chip select access time teye tesp tosr Chip select hold time Read write hold time
64. J7 SCL PORT J I O Pin 7 PJ7 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as the transmit pin TXCAN for the Motorola Scalable Controller Area Network controller 4 CANA or the serial clock pin SCL of the IIC module 2 3 30 PJ6 KWJ6 RXCANA SDA PORT J I O Pin 6 PJ6 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as the receive pin RXCAN for the Motorola Scalable Controller Area Network controller 4 CANA or the serial data pin SDA of the module 2 3 31 PJ 1 0 KWJ 1 0 Port J I O Pins 1 0 PJ1 and PJO are general purpose input or output pins They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 32 PK7 ECS ROMONE Port K I O Pin 7 PK7 is a general purpose input or output pin During MCU expanded modes of operation this pin is used as the emulation chip select output ECS During MCU normal expanded wide and narrow modes of operation this pin is used to enable the Flash EEPROM memory in the memory map ROMONE At the rising edge of RESET the state of this pin is latched to the ROMON bit 62 MOTOROLA MC9S12DT256 Device User Guide V03 03 2 3 33 PK 5 0 XADDR 19 14 Port I O Pins 5 0 5 are general purpose in
65. LQFP Colpitts Oscillator 84 M MOTOROLA MC9S12DT256 Device User Guide 03 03 Figure 20 2 Recommended PCB Layout for 80QFP Colpitts Oscillator M MOTOROLA 85 MC9S12DT256 Device User Guide V03 03 Figure 20 3 Recommended PCB Layout for 112 Pierce Oscillator 86 M MOTOROLA MC9S12DT256 Device User Guide V03 03 Figure 20 4 Recommended PCB Layout for 80QFP Pierce Oscillator M MOTOROLA 87 MC9S12DT256 Device User Guide V03 03 88 44 MOTOROLA MC9S12DT256 Device User Guide 03 03 Appendix Electrical Characteristics A 1 General NOTE The electrical characteristics given in this section are preliminary and should be used as a guide only Values cannot be guaranteed by Motorola and are subject to change without notice This supplement contains the most accurate electrical information for the MC9S12DT256 microcontroller available at the time of publication The information should be considered PRELIMINARY and is subject to change This introduction is intended to give an overview on several common topics like power supply current injection etc A 1 1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate NOTE This clas
66. O 0 0 RXERRO TXERRO ACO ACO ACO ACO AMO AMO AMO AMO ACO 45 MC9S12DT256 Device User Guide V03 03 0180 01BF CAN1 Motorola Scalable CAN MSCAN Address Bit 7 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0199 CAN1IDAR5 iid AC7 AC6 5 4 2 1 Read 019 CAN IDARG un AC6 5 AC2 1 Read 019B 7 un AC6 5 2 1 019C 2 AM7 AM6 5 AM4 AM2 AMO 019D CAN1IDMR5 se AM7 6 AM5 AM4 AM3 AM2 AM1 AMO 019E CAN1IDMRG e AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO 019F CANTIDMR7 ius AM7 AM6 4 2 AMI AMO 01A0 Caninxre Read FOREGROUND RECEIVE BUFFER see Table 1 2 01AF Write SOTBO Gange Pead FOREGROUND TRANSMIT BUFFER see Table 1 2 01BF Write 0240 027F PIM Port Integration Module PIM_9DP256 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0240 PTT 7 PTT6 PTT5 4 1 Read PTIT7 PTIT6 5 PTITA PTITS PTIT2 PTIT PTIT 0241 PTIT 0 Write 0242 DDRT ES DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRTO 0243 RDRT ish RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 R
67. OES NOT INCLUDE DAMBAR ROTRUSION ALLOWABLE DAMBAR ROTRUSION SHALL NOT CAUSE THE D MENSION TO EXCEED 0 46 2 gt 8 4 VDOROO gt O 5 SEATING PLANE 0 25 22 000 BSC GAGE PLANE 11 000 BS ruo 886 LA LB B1 D LE L6 LK LP LS LS1 Lz 02 es 11 VIEW Figure B 1 112 pin LQFP mechanical dimensions case no 987 126 M MOTOROLA MC9S12DT256 Device User Guide V03 03 B 3 80 pin QFP package DETAIL A 0 20 OIDO DETAIL DETAIL 0200 AB 9 DO DATUM VIEW ROTATED 90 SEATING PLANE NOTES MILLIMETERS DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 DIM MIN MAX 2 CONTROLLING DIMENSION MILLIMETER A 1390 14 10 3 DATUM PLANE H IS LOCATED AT BOTTOM OF B 1390 14 10 LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC C 215 245 BODY AT THE BOTTOM OF THE PARTING LINE D 022 038 4 DATUMS A B D TO BE 2 00 240 DETERMINED AT DATUM PLANE 022 033 5 DIMENSIONS 5 V TO DETERMINED 5 DATUM 6 DIMENSIONS A AND 8 DO NOT INCLUDE E H 0 2
68. PRIO7 PRIO6 5 PRIO4 PRIO2 PRIO1 PRIOO Read TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 Write Read TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSRO Write ID28 027 026 025 024 ID23 ID22 021 xx10 ID10 ID9 ID8 ID7 06 05 04 ID3 ID20 ID19 ID18 SRR 1 IDE 1 ID17 ID16 ID15 10 ID2 ID1 IDO RTR IDE 0 014 1013 1012 1011 1010 09 108 107 12 106 105 104 103 102 101 00 RTR xx13 DB7 DB6 DB5 084 DB3 DB2 DB1 080 CANXTTSRH xx1F CANxTTSRL 44 M MOTOROLA 0180 Address 0180 0181 0182 0183 0184 0185 0186 0187 0188 0189 018A 018B 018C 018D 018E 018F 0190 0191 0192 0193 0194 0195 0196 0197 0198 M MOTOROLA 01BF Name CAN1CTLO CAN1CTL1 CAN1BTRO CAN1RFLG CAN1RIER CAN1TFLG CAN1TIER CAN1TARQ CAN1TAAK CAN1TBSEL CAN1IDAC Reserved Reserved CAN1RXERR CAN1TXERR CAN1IDARO CAN1IDAR1 CAN1IDAR2 CAN1IDAR3 CAN1IDMRO CAN1IDMR1 CAN1IDMR2 CAN1IDMR3 CAN1IDAR4 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S
69. Read Write Read Write Read Write Read Write Read Write Read Write Read Write ATDO Analog to Digital Converter 10 Bit 8 Channel MC9S12DT256 Device User Guide V03 03 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit7 Bit6 0 0 0 0 0 0 Biti5 14 13 12 11 10 9 Bits Bit7 Bit6 0 0 0 0 0 0 Biti5 14 13 12 11 10 9 Bits Bit7 Bit6 0 0 0 0 0 0 PWM Pulse Width Modulator 8 Bit 8 Channel Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWME7 PWME6 5 PWME4 PWME3 PWME2 PWME1 PWMEO PPOL7 PPOL6 15 PPOL4 PPOL3 PPOL2 PPOL1 PPOLO PCLK7 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLKO PCKB2 PCKB1 PCKA2 PCKA1 PCKAO CAE7 CAES CAE4 CAE3 2 CAE CAEO CON67 CON45 CON23 CONO PSWAI PFRZ 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 35 MC9S12DT256 Device User Guide V03 03 00A0 00C7 PWM Pulse Width Modulator 8 Bit 8 Channel Add
70. S12DT256 Device User Guide V03 03 2 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I O supply The absolute maximum ratings apply when the device is powered from an external source 3 All digital I O pins are internally clamped to Vssx and Vppx Vssr and Vppr Or Vssa and Vppa 4 Those pins are internally clamped to and 5 This pin is clamped low to but not clamped high This pin must be tied low in applications A 1 6 ESD Protection and Latch up Immunity ESD testing is in conformity with CDF AEC Q100 Stress test qualification for Automotive Grade Integrated Circuits During the device qualification ESD stresses were performed for the Human Body Model HBM the Machine Model MM and the Charge Device Model A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature unless specified otherwise in the device specification Table A 2 ESD and Latch up Test Conditions Model Description Symbol Value Unit Series Resistance R1 1500 Ohm Storage Capacitance C 100 pF Puman Number of Pulse per pin 3 negative 3 Series Resistance R1 0 Storage Capacitance C 200 pF Machine Number of P
71. Table 6 5V Characteristics Conditions are shown in Table A 4 unless otherwise noted Rating Symbol Min Typ Max Unit 1 P Input High Voltage 0 65 Vpps V T Input High Voltage VDD5 0 3 V 2 Low Voltage VL 0 35 Vppg V T Input Low Voltage VSS5 0 3 3 Input Hysteresis Vuys mV Input Leakage Current pins in high impedance input u 4 Vin Vpps 9 Output High Voltage pins in output mode Partial Drive 2 Output High Voltage pins in output mode 6 Eull Drive 10mA Von Output Low Voltage pins in output mode V 7 Partial Drive IOL 2mA Output Low Voltage pins in output mode Full Drive loj 10mA Internal Pull Up Device Current 9 tested at Vj Max Internal Pull Up Device Current 10 tested at Min PUH Internal Pull Down Device Current 11 P tested at Min PDH Internal Pull Down Device Current 12 C tested at V Max PDL 10 13 10 Input Capacitance Cin 6 Injection current 14 T Single Pin limit lics 2 5 2 5 mA Total Device Limit Sum of all injected currents 25 25 15 Port J P Interrupt Input Pulse filtered tPULSE 3 us 16 PortH J P Interrupt Input Pulse passed tPULSE 10 us NOTES 1 Maximum leakage current occurs at maximum operating t
72. U to exit STOP or WAIT mode It can be configured as master input during master mode or slave output during slave mode pin MISO of the Serial Peripheral Interface 2 5 12 2 3 25 PH3 KWH3 SS1 Port Pin PH3 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as slave select pin SS of the Serial Peripheral Interface 1 5 M MOTOROLA 61 MC9S12DT256 Device User Guide V03 03 2 3 26 PH2 KWH2 SCK1 Port I O Pin 2 PH2 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 5 2 3 27 1 KWH1 MOSI1 H I O Pin 1 is a general purpose input or output pin It can be configured to generate an interrupt causing MCU to exit STOP or WAIT mode It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 1 SPI1 2 3 28 PHO KWHO MISO1 Port H I O Pin 0 PHO is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as master input during master mode or slave output during slave mode pin MISO of the Serial Peripheral Interface 1 SPIL 2 3 29 PJ7 KW
73. WUPM 90282 2 SJWi SJWO BRP5 BRP4 BRP3 BRP2 1 BRPO 0283 s SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 90284 CAN4RFLG dins esci LES TTC TSTAT Tere ovale aXe 0285 CAN4RIER e CSCIE RSTATE1 RSTATEO TSTATE1 TSTATEO OVRIE RXFIE 0286 CANATFLG 1 0 TXE2 1 0287 CANATIER a 0 0 0 TXEIE2 TXEIE1 TXEIEO 0288 e 0 0 0 ABTRG2 ABTRQ ABTRQO sS 0 0 0 2 Write 028A CANATBSEL E 0 0 0 TX2 TXi 028B 0 IDAM1 IDAMO 0 DENE 48 M MOTOROLA 0280 Address 028C 028D 028E 028F 0290 0291 0292 0293 0294 0295 0296 0297 0298 0299 029A 029B 029C 029D 029E 029F 02A0 02AF 02B0 02BF M MOTOROLA 02BF Name Reserved Reserved CANARXERR CANATXERR CAN4IDARO CAN4IDAR1 CAN4IDAR2 CAN4IDAR3 CAN4IDMRO CAN4IDMR1 CAN4IDMR2 CAN4IDMR3 CAN4IDAR4 CAN4IDAR5 CAN4IDAR6 CAN4IDAR7 CAN4IDMR4 CAN4IDMR5 CAN4IDMR6 CAN4IDMR7 CAN4RXFG CAN4TXFG Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Re
74. ad Write Read Write Read Write Read Write Read Write Read Write MC9S12DT256 Device User Guide V03 03 CAN4 Motorola Scalable CAN MSCAN Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXERR7 RXERR6 RXERR5 RXERR4 RXERRS RXERR2 RXERR1 RXERRO TXERR7 TXERR6 TXERRS TXERR4 TXERRS TXERR2 TXERR1 TXERRO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AC7 6 AC5 ACA 2 1 7 6 AC5 ACA 2 1 7 6 5 4 AM2 1 7 6 5 4 AM2 1 AM7 6 5 4 2 1 7 6 5 4 AM2 1 7 6 AC5 ACA 2 1 7 6 AC5 ACA 2 1 7 6 AC5 ACA 2 1 7 6 AC5 ACA 2 1 7 6 5 4 AM2 1 7 AM6 5 4 AM2 1 7 6 5 4 2 1 7 6 5 4 AM2 1 FOREGROUND RECEIVE BUFFER see Table 1 2 FOREGROUND TRANSMIT BUFFER see Table 1 2 49 MC9S12DT256 Device User Guide V03 03 02C0 03FF Reserved space Address Name 02C0 8900 0 o SOSFF write
75. ave MODO o bus c Leen aha a Ko tat agde es ge a QS 119 A3 External oo om ern copo vaga tree 121 A 8 1 General Muxed Bus aaa Mae qd ve ES EUR ES 121 Appendix B Package Information Generals ne td ta DC 125 B CW2 pI EORP package ania en an MEE RI EM CSS 126 B 3 80 QFP package eet eR oe eth RU Bom ont bote ee Whe d 127 M MOTOROLA 9 MC9S12DT256 Device User Guide V03 03 10 44 MOTOROLA MC9S12DT256 Device User Guide 03 03 List of Figures Figure 0 1 Figure 1 1 Figure 1 2 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 3 1 Figure 20 1 Figure 20 2 Figure 20 3 Figure 20 4 Figure A 1 Figure A 2 Figure A 3 Figure A 4 Figure A 5 Figure A 6 Figure A 7 Figure A 8 Figure A 9 Figure B 1 Figure B 2 M MOTOROLA Order Partnumber 15 MC9S12DT256 Block 23 MC9S12DT256 Memory 26 Pin Assignments 112 52 Pin Assignments in 80 QFP for MC9812DJ256 53 PLL Loop Hier 57 Colpitts Oscillator Connections 7 1 59 Pierce Oscillator Connections 7 0
76. be configured as slave select pin SS of the Serial Peripheral Interface 1 SPI1 64 MOTOROLA MC9S12DT256 Device User Guide V03 03 2 3 47 2 KWP2 PWM2 SCK1 Port P I O Pin 2 PP2 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 2 output It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 SPIL 2 3 48 PP1 KWP1 PWM1 Port P I O Pin 1 1 isa general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 1 output It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 1 5 2 3 49 KWP0 PWMO MISO1 Port P I O Pin 0 PPO is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 0 output It can be configured as master input during master mode or slave output during slave mode pin MISO of the Serial Peripheral Interface 1 5 2 3 50 PS7 550 Port S I O Pin 7 PS6 is a general purpose input or output pin It can be configured as the slave select pin SS of the Serial Peri
77. ble 1 3 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read 0 0 0 0 0 0 0 0 0018 Reserved Write Read 0 0 0 0 0 0 0 0 0019 Reserved Write 0016 T Read ID15 ID14 1013 1012 1011 1010 109 108 Write 9018 Read 1 7 06 05 104 103 102 101 100 Write 001C 001D MMC map 3 of 4 Core and Device User Guide Table 1 4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 001C MEMSIZO id reg swO 0 eep_sw1 sw0 0 ram sw2 ram_sw1 swO 001D MEMSIZ1 sw swO 0 0 0 0 sw1 swO 28 M MOTOROLA 001 001E Address 001E Name INTCR 001F 001F Address 001F Name HPRIO 0020 0027 Address 0020 0021 0022 0023 0024 0025 0026 0027 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0028 002F Address 0028 0029 002A 002B 002C M MOTOROLA Name BKPCTO BKPCT1 BKPOX BKPOH BKPOL MC9S12DT256 Device User Guide V03 03 MEBI map 2 of 3 Core User Guide Read ae 9 I 0 0 0 0 9 Write ae eae SS INT map 2 of 2 Core User Guide Read Write PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0
78. causes a reset 56 M MOTOROLA MC9S12DT256 Device User Guide 03 03 2 3 3 TEST Test Pin This input only pin is reserved for test NOTE The TEST pin must be tied to VSS in all applications 2 3 4 VREGEN Voltage Regulator Enable Pin This input only pin enables or disables the on chip voltage regulator 2 3 5 XFC PLL Loop Filter Pin PLL loop filter Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements Any current leakage on this pin must be avoided XFC R 0 Cp MCU VDDPLL VDDPLL Figure 2 3 PLL Loop Filter Connections 2 3 06 BKGD TAGHI MODC Background Debug Tag High and Mode Pin The BKGD TAGHI MODC pin is used as a pseudo open drain pin for the background debug communication In MCU expanded modes of operation when instruction tagging is an input low on this pin during the falling edge of E clock tags the high half of the instruction word being read into the instruction queue It is used as a MCU operating mode select pin during reset The state of this pin is latched to the MODC bit at the rising edge of RESET This pin has a permanently enabled pull up device 2 3 7 PAD15 15 ETRIG1 Port AD Input Pin of ATD1 15 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD1 It can act as an external trigger input for the ATDI 2 3 8 PAD 14 08 AN 14 08 Port AD Inpu
79. dominant pulse filtered 2 us 2 MSCAN Wake up dominant pulse pass twup 5 us M MOTOROLA 115 MC9S12DT256 Device User Guide V03 03 116 44 MOTOROLA MC9S12DT256 Device User Guide V03 03 A 7 SPI This section provides electrical parametrics and ratings for the SPI In Table A 18 the measurement conditions are listed Table A 18 Measurement Conditions Description Value Unit Drive mode full drive mode Load capacitance C 50 on all outputs Thresholds for delay 20 80 VDDX V measurement points A 7 1 Master Mode In Figure A 5 the timing diagram for master mode with transmission format CPHA 0 is depicted 551 OUTPUT SCK 4 0 OUTPUT 4 SCK 1 OUTPUT 1 LSB IN gt 0 MOSI N OUTPUT MSB OUT BIT6 1 LSBOUT 1 1 configured as an output 2 LSBF 0 For LSBF 1 bit order is LSB bit 1 bit 6 MSB Figure A 5 SPI Master Timing CPHA 0 In Figure A 6 the timing diagram for master mode with transmission format CPHA 1 is depicted M MOTOROLA 117 MC9S12DT256 Device User Guide V03 03 551 OUTPUT SCK 0 OUTPUT SCK 1 OUTPUT MISO INPUT OUTPUT PORT DATA 1 1 configured as output 2 LSBF 0 For LSBF 1 bit order is LSB bit 1 bit 6 Figure A 6 SPI Master Ti
80. e Real Time Interrupt RTI or Watchdog COP sub module can stay active Other peripherals are turned off This mode consumes more current than the full STOP mode but the wake up time from this mode is significantly shorter 4 4 3 Wait This mode is entered by executing the CPU WAI instruction In this mode the CPU will not execute instructions The internal CPU signals address and databus will be fully static All peripherals stay active For further power consumption the peripherals can individually turn off their local clocks M MOTOROLA 73 MC9S12DT256 Device User Guide V03 03 4 4 4 Run Although this is not a low power mode unused peripheral modules should not be enabled in order to save power 74 MOTOROLA Section 5 Resets and Interrupts 5 1 Overview MC9S12DT256 Device User Guide V03 03 Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and interrupts 5 2 Vectors 5 2 1 Vector Table Table 5 1 lists interrupt sources and vectors in default order of priority Table 5 1 Interrupt Vector Locations FFFA FFFB FFF8 FFF9 COP failure reset Unimplemented instruction trap CCR HPRIO Value Vector Address Interrupt Source Mask Local Enable to Elevate FFFE FFFF Reset None None FFFD Clock Monitor fail reset None PLLCTL CME SCME COP rate select FFF6 FFF7 SWI None FFF4 FFF5 XIRQ None FFF2 FFF3 IRQ IRQCR
81. e of RESET This pin is shared with the instruction queue tracking signal IPIPE1 This pin is an input with a pull down device which is only active when RESET is low 2 3 15 PE5 MODA IPIPEO Port E I O Pin 5 PES is a general purpose input or output pin It is used as a MCU operating mode select pin during reset The state of this pin is latched to the MODA bit at the rising edge of RESET This pin is shared with the instruction queue tracking signal IPIPEO This pin is an input with a pull down device which is only active when RESET is low 2 3 16 4 Port E I O Pin 4 is a general purpose input or output pin It can be configured to drive the internal bus clock ECLK ECLK can be used as a timing reference 2 3 17 LSTRB TAGLO Port I O Pin PE3 is a general purpose input or output pin In MCU expanded modes of operation LSTRB can be used for the low byte strobe function to indicate the type of bus access and when instruction tagging is on TAGLO is used to tag the low half of the instruction word being read into the instruction queue 60 MOTOROLA MC9S12DT256 Device User Guide V03 03 2 3 18 PE2 R W Port E I O Pin 2 PE2 is a general purpose input or output pin In MCU expanded modes of operations this pin drives the read write output signal for the external bus It indicates the direction of data on the external bus 2 3 19 PE1 IRQ Port E Input Pin 1
82. e user must be reminded that part of the security must lie with the user s code An extreme example would be user s code that dumps the contents of the internal program This code would defeat the purpose of security At the same time the user may also wish to put a back door in the user s program An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters stored in EEPROM 4 3 1 Securing the Microcontroller Once the user has programmed the FLASH and EEPROM if desired the part can be secured by programming the security bits located in the FLASH module These non volatile bits will keep the part secured through resetting the part and through powering down the part The security byte resides in a portion of the Flash array Check the Flash Block User Guide for more details on the security configuration 4 3 2 Operation of the Secured Microcontroller 4 3 2 1 Normal Single Chip Mode This will be the most common usage of the secured part Everything will appear the same as if the part was not secured with the exception of BDM operation The BDM operation will be blocked 72 MOTOROLA MC9S12DT256 Device User Guide 03 03 4 3 2 2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller This is accomplished by resetting directly into expanded mode The internal FLASH and EEPROM will be disabled BDM operati
83. emperature Current decreases by approximately one half for each 8 C to 12 C in the temperature range from 50 C to 125 C 2 Refer to Section A 1 4 Current Injection for more details 3 Parameter only applies in STOP or Pseudo STOP mode 96 M MOTOROLA MC9S12DT256 Device User Guide V03 03 A 1 10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements 1 10 1 Measurement Conditions measurements are without output loads Unless otherwise noted the currents are measured in single chip mode internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode Production testing is performed using a square wave signal at the EXTAL input A 1 10 2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address data and control signals as well as on the duty cycle of those signals No generally applicable numbers can be 97 M MOTOROLA MC9S12DT256 Device User Guide V03 03 given A very good estimate is to take the single chip currents and add the currents due to the external loads Table A 7 Supply Current Characteristics Conditions are shown in Table A 4 unless otherwise noted 1 Run supply currents mA Single Chip Internal regulator enabled Ipps 65 Wait Supply current 2 P All modules enabled PLL on Ippw 4
84. ency characteristics and place them as close to the MCU as possible This 2 5V supply is derived from the internal voltage regulator There is no static load on those pins allowed The internal voltage regulator is turned off if VREGEN 15 tied to ground NOTE No load allowed except for bypass capacitors 2 4 4 VDDA VSSA Power Supply Pins for ATD and VREG VDDA VSSA are the power supply and ground input pins for the voltage regulator and the analog to digital converter It also provides the reference for the internal voltage regulator This allows the supply voltage to the ATD and the reference voltage to be bypassed independently 2 4 5 VRH VRL ATD Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog to digital converter 2 4 6 VDDPLL VSSPLL Power Supply Pins for PLL Provides operating voltage and ground for the Oscillator and the Phased Locked Loop This allows the supply voltage to the Oscillator and PLL to be bypassed independently This 2 5V voltage is generated by the internal voltage regulator NOTE No load allowed except for bypass capacitors Table 2 2 MC9S12DP256 Power and Ground Connection Summary Pin Number Nominal ice Mnemonic Description 112 pin Voltage 2 13 65 2 5 Internal power and ground generated by internal regulator Vss1 2 14 66 OV 41 5 0 V External power and ground supply to pin drivers a
85. entical to M68HC11 iii Instruction queue iv Enhanced indexed addressing Multiplexed External Bus Interface MMC Module Mapping Control INT Interrupt control Breakpoints BDM Background Debug Mode CRG Low current Colpitts or Pierce oscillator PLL COP watchdog Real time interrupt Clock Monitor e 8 bit and 4 bit ports with interrupt functionality Digital filtering M MOTOROLA 19 MC9S12DT256 Device User Guide V03 03 20 Programmable rising or falling edge trigger Memory 256K Flash EEPROM 4K byte EEPROM 12K byte RAM Two 8 channel Analog to Digital Converters 10 bit resolution External conversion trigger capability Three 1M bit per second CAN 2 0 A B software compatible modules Five receive and three transmit buffers Flexible identifier filter programmable as 2 x 32 bit 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Rx Tx error and wake up Low pass filter wake up function Loop back for self test operation Enhanced Capture Timer 16 bit main counter with 7 bit prescaler 8 programmable input capture or output compare channels Four 8 bit or two 16 bit pulse accumulators 8 PWM channels Programmable period and duty cycle 8 61 8 channel or 16 bit 4 channel Separate control for each pulse width and duty cycle Center aligned or left aligned outputs Progra
86. erial Peripheral Interface SP11 8 00F8 00FF Serial Peripheral Interface SPI2 8 0100 010F Flash Control Register 16 0110 011 EEPROM Control Register 12 011C 011F Reserved 4 0120 013F Analog to Digital Converter 10 bit 8 channels ATD1 32 0140 017F Motorola Scalable Can 64 0180 01BF Motorola Scalable Can 64 01C0 01FF Reserved 64 0200 023F Reserved 64 0240 027F Port Integration Module PIM 64 0280 02BF Motorola Scalable Can 64 02C0 03FF Reserved 320 0000 0FFF EEPROM array 4096 MOTOROLA M MOTOROLA MC9S12DT256 Device User Guide V03 03 Table 1 1 Device Memory Map Address 1000 3FFF Module RAM array Size Bytes 12288 4000 7FFF Fixed Flash EEPROM array incl 0 5K 1K 2K or 4K Protected Sector at start 16384 8000 BFFF 5 000 FFFF Flash EEPROM Window Fixed Flash EEPROM array incl 0 5K 1K 2K or 4K Protected Sector at end and 256 bytes of Vector Space at FF80 FFFF 16384 16384 25 MC9S12DT256 Device User Guide V03 03 Figure 1 2 MC9S12DT256 Memory Map oe REGISTERS 0400 Mappable to any 2k Block within the first 32K 4K Bytes EEPROM 1000 Mappable to any 4K Block 12K Bytes RAM Mappable to any 16K and alignable to top or 4000 bottom 16K Fixed Flash Page 3E 62 This is dependant on the
87. eripheral Interface 2 SPI2 2 3 43 PP6 KWP6 6 552 Port P I O Pin 6 PP6 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 6 output It can be configured as slave select pin SS of the Serial Peripheral Interface 2 SPI2 2 3 44 PP5 KWP5 PWM5 MOSI2 Port P I O Pin 5 PP5 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 5 output It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 2 SPI2 2 3 45 4 PWM4 MISO2 Port P I O Pin 4 PP4 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 4 output It can be configured as master input during master mode or slave output during slave mode pin MISO of the Serial Peripheral Interface 2 SPI2 2 3 46 PP3 KWP3 PWM3 551 Port P I O Pin PP3 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 3 output It can
88. eset po 2 3 4 5 6 7 8 9 10 11 110 M MOTOROLA MC9S12DT256 Device User Guide V03 03 A 5 3 Phase Locked Loop The oscillator provides the reference clock for PLL The PLL s Voltage Controlled Oscillator VCO is also the system clock source in self clock mode A 5 3 1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics VDDPLL Pin VCO 1 fref refdv 1 Detector femp Loop Divider Figure A 2 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for f and iy from Table A 16 The grey boxes show the calculation for 50MHz and fief IMHz E g these frequencies are used for fosc 4MHz and a 25MHz bus clock The VCO Gain at the desired VCO frequency is approximated by 60 50 100 7 9 90 48 The phase detector relationship is given icn Ky 316 7Hz Q 15 the current in tracking mode M MOTOROLA 111 MC9S12DT256 Device User Guide V03 03 The loop bandwidth should be chosen to fulfill the Gardner s stability criteria by at least a factor of 10 typical values are 50 G 0 9 ensures a good transient response That 1 fref SS 10 le x 195 0 9 n ga dt 0 fc lt 25kHz And fi
89. heral Interface Bit 7 SPIE 0 0 SPIF Bit 6 SPE 0 SPPR2 Bit 5 SPTIE 0 SPPR1 SPTEF Bit 4 MSTR MODFEN SPPRO MODF Bit 3 CPOL BIDIROE 0 0 Bit 2 SBR10 SBR2 BRK13 R2 T2 Bit 2 SBR10 SBR2 BRK13 R2 T2 Bit 2 CPHA SPR2 Bit 1 SBR9 SBR1 PE RWU FE TXDIR R1 T1 Bit 1 SBR9 SBR1 PE RWU FE TXDIR R1 T1 Bit 1 SSOE SPISWAI SPR1 0 RAF RAF Bit 0 SBR8 SBRO PT SBK PF RO TO Bit 0 SBR8 SBRO PT SBK PF RO TO Bit 0 LSBFE SPCO SPRO 37 MC9S12DT256 Device User Guide V03 03 00D8 00DF SPIO Serial Peripheral Interface Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read 0 0 0 0 0 0 0 0 00DC Reserved Write 00DD sriopr 1984 6 5 4 3 2 1 Bito Write Read 0 0 0 0 0 0 0 0 00DE Reserved Write Read 0 0 0 0 0 0 0 0 00DF Reserved Write 00 0 00E7 Inter IC Bus Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0 IBAD nn ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR 0 Read 00E1 IBFD 1807 IBC6 IBC5 IBC4 IBC3 IBC2 IBCO Read CN Hee 0
90. imum injection current This will be the greatest risk when the MCU is not consuming power e g if no system clock is present or if clock rate is very low which would reduce overall power consumption A 1 5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only A functional operation under or outside those maxima is not guaranteed Stress beyond those limits may affect the reliability or cause permanent damage of the device This device contains circuitry protecting against damage due to high static voltage or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level e g either Vsss or Table A 1 Absolute Maximum Ratings 1 Regulator and Analog Supply Voltage E NE ME MES 2 Digital Logic Supply Voltage 2 V 3 Supply Voltage 2 V 4 Voltage difference VDDX to VDDR and VDDA V 5 Voltage difference VSSX to VSSR and VSSA 6 Digital I O Input Voltage 6 0 V 7 Analog Reference 6 0 V 8 XFC EXTAL XTAL inputs 3 0 V 9 TEST input 10 0 V due em M A s 13 Storage Temperature Range stg 65 155 C NOTES 1 Beyond absolute maximum ratings device might be damaged M MOTOROLA 91 MC9
91. ip BDM allowed and ACTIVE BDM is 0 0 0 X 1 allowed in all other modes but a serial command is required to make BDM active 0 1 0 0 1 1 0 Emulation Narrow allowed 0 1 0 X 0 Special Expanded Wide BDM allowed 0 1 0 1 1 1 Emulation Expanded Wide BDM allowed 1 0 0 X 1 Normal Single Chip allowed 0 0 1 0 1 1 1 Normal Expanded Narrow BDM allowed Peripheral BDM allowed but bus operations would cause 1 1 0 X 1 bus conflicts must not be used 0 0 1 1 1 a qr Normal Expanded Wide allowed For further explanation on the modes refer to the Core User Guide Table 4 2 Clock Selection Based on PE7 PE7 XCLKS Description 1 Colpitts Oscillator selected M MOTOROLA 71 MC9S12DT256 Device User Guide V03 03 Table 4 2 Clock Selection Based on PE7 PE7 XCLKS Description BEN IM Pierce Oscillator external clock selected Table 4 3 Voltage Regulator VREGEN VREGEN Description Internal Voltage Regulator enabled Internal Voltage Regulator disabled VDD1 2 and VDDPLL must be supplied externally with 2 5V 4 3 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents This feature allows e Protection of the contents of FLASH e Protection of the contents of EEPROM Operation in single chip mode Operation from external memory with internal FLASH and EEPROM disabled Th
92. laims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part M MOTOROLA MC9S12DT256 Device User Guide 9S12DT256DGV3 D V03 03 MOTOROLA 3 MC9S12DT256 Device User Guide 9S12DT256DGV3 D V03 03 4 44 MOTOROLA MC9S12DT256 Device User Guide V03 03 Table of Contents Section 1 IntroductionMC9S12DT256 1 1 1 2 1 3 1 4 1 5 1 6 1 7 VILI bodie up ee uu E eee Br Block Di Amendes riesen Device Memory Detailed Register Part ASSISUIGDIS ae De REE ree Stra afud e ud Section 2 Signal Description 2 1 2 2 2 3 2 3 1 2 3 2 2 3 3 2 3 4 2 3 5 2 3 6 2 3 7 2 3 8 2 3 9 2 3 10 2 3 11 2 3 12 2 3 13 2 3 14 2 3 15 2 3 16 2 3 17 2 3 18 2 3 19 2 3 20 Device PIDE cibis uu owe ae ha a Signal PropertiesSummay ana ute bre sut SAPE bU CDS S Detailed Signal Descriptions
93. ming CPHA 1 In Table A 19 the timing characteristics for master mode are listed Table A 19 SPI Master Mode Timing Characteristics PORT DATA Num Characteristic Symbol Min Typ Max Unit 1 SCK Frequency fsck 1 2048 fous 2 Enable Lead Time tlead 1 2 tsck 3 Enable Lag Time 1 2 tsck 4 Clock SCK High or Low Time twsck 1 2 tsck 5 Data Setup Time Inputs tsu ns 6 Data Hold Time Inputs thi ns 9 Data Valid after SCK Edge 5 10 Data Valid after SS fall CPHA 0 tvss ns 11 Data Hold Time Outputs tho ns 12 Rise and Fall Time Inputs ns 13 Rise and Fall Time Outputs ns 118 M MOTOROLA MC9S12DT256 Device User Guide V03 03 A 7 2 Slave Mode In Figure A 7 the timing diagram for slave mode with transmission format CPHA 0 is depicted den A lt 1 gt 13 3 INPUT Lo Lo HOT 2 8 cpoL er 8 O Mais D MISO OUTPUT suweisBoUr X VL cal MOSI NOTE Not defined Figure A 7 SPI Slave Timing CPHA 0 In Figure 8 the timing diagram for slave mode with transmission format CPHA 1 is depicted M MOTOROLA 119 MC9S12DT256 Device User Guide V03 03 55 INPUT SCK 0 INPUT SCK 1 INPUT gt 8
94. mmable clock select logic with a wide range of frequencies Fast emergency shutdown input Usable as interrupt inputs Serial interfaces Two asynchronous Serial Communications Interfaces SCI Three Synchronous Serial Peripheral Interface SPI Byte Data Link Controller BDLC SAE 71850 Class Data Communications Network Interface Compatible and ISO Compatible for Low Speed lt 125 Kbps Serial Data Communications in Automotive Applications Inter IC Bus MOTOROLA MC9S12DT256 Device User Guide V03 03 Compatible with I2C Bus standard Multi master operation Software programmable for one of 256 different serial clock frequencies e 112 LQFP package I O lines with 5V input and drive capability 5V A D converter inputs Operation at SOMHz equivalent to 25MHz Bus Speed Development support Single wire background debug mode BDM On chip hardware breakpoints 1 3 Modes of Operation User modes e Normal and Emulation Operating Modes Normal Single Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Operating Modes Special Single Chip Mode with active Background Debug Mode Special Test Mode Motorola use only Special Peripheral Mode Motorola use only Low power modes Stop Mode e Pseudo Stop Mode Wait Mode M MOTOROLA 21 MC9S12DT256 Device User Guide 03 03 1 4 Block Diag
95. nally the frequency relationship 15 defined as fvco f 2 synr 1 50 ref With the above values the resistance can be calculated The example is shown for a loop bandwidth fc 10kHz 2 n n fe R K 2 x 50 10kHz 316 7Hz 0 29 9kOz 10k The capacitance C now be calculated as 2 26 0516 5 19nF 4 7nF sco Ro The capacitance C should be chosen in range of 0 20 lt C lt C 10 C 470pF A 5 3 2 Jitter Information The basic functionality of the PLL is shown in Figure 2 With each transition of the clock femp the deviation from the reference clock 15 measured and input voltage to the VCO is adjusted accordingly The adjustment is done continuously with no abrupt changes in the clock output frequency Noise voltage temperature and other factors cause slight variations in the control loop resulting in a clock jitter This jitter affects the real minimum and maximum clock periods as illustrated in Figure A 3 112 MOTOROLA MC9S12DT256 Device User Guide V03 03 Figure A 3 Jitter Definitions The relative deviation of thom 18 at its maximum for one clock period and decreases towards zero for larger number of clock periods N Defining the jitter as max N t nom N t nom J N mad For lt 100 the following equation is a good fit for the maximum jitter fax XN J N 1 5 10 20 Figure
96. ncy a full program or erase transition is not assured The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively The frequency of this clock must be set within the limits specified as The minimum program and erase times shown in Table A 11 are calculated for maximum fyyyop and maximum The maximum times are calculated for minimum fyymop and a fy of 2MHz A 3 1 1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency and can be calculated according to the following formula t HC NM 25 snp fous A 3 1 2 Burst Programming This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst programming by keeping the command pipeline filled The time to program a consecutive word can be calculated as 1 1 an NVMOP bus tbwpgm The time to program a whole row is torpgm swpgm 31 Ipwpgm Burst programming is more than 2 times faster than single word programming M MOTOROLA 103 MC9S12DT256 Device User Guide V03 03 A 3 1 3 Sector Erase Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes 1 a 4000 NVMOP The setup time can be ignored for this operation A 3 1 4 Mass Erase Erasing a NVM block takes
97. nd internal 40 0 voltage regulator 107 5 0 V uw External power and ground supply to pin drivers Vssx 106 OV VDDA 83 5 0 V Operating voltage and ground for the analog to digital converters and the reference for the internal voltage regulator Vesa 86 OV allows the supply voltage to the A D to be bypassed independently VRL 85 OV Reference voltages for the analog to digital converter 84 5 0 V M MOTOROLA 67 MC9S12DT256 Device User Guide V03 03 Mnemonic Pin Number 112 pin Nominal Voltage Description VDDPLL 43 2 5 Provides operating voltage and ground for the Phased Locked Loop This allows the supply voltage to the PLL to be VssPLL 45 OV bypassed independently Internal power and ground generated by internal regulator VREGEN 97 5V Internal Voltage Regulator enable disable 2 4 7 VREGEN On Chip Voltage Regulator Enable Enables the internal 5V to 2 5V voltage regulator If this pin is tied low VDD1 2 and VDDPLL must be supplied externally 68 M MOTOROLA MC9S12DT256 Device User Guide V03 03 Section 3 System Clock Description 3 1 Overview The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules Figure 3 1 shows the clock connections from the CRG to all modules Consult the CRG Block User Guide for details on clock generation 812 CORE p EE am Eu m
98. notes the sum of the currents flowing into VDDX and pins VDD is used for VDDI VDD2 and VDDPLL VSS is used for VSS1 VSS2 and VSSPLL IDD is used for the sum of the currents flowing into VDDI and VDD2 A 1 3 Pins There are four groups of functional pins A 1 3 1 5V I O pins Those I O pins have a nominal level of 5V This class of pins is comprised of all port I O pins the analog inputs BKGD and the RESET pins The internal structure of all those pins is identical however some of the functionality may be disabled E g for the analog inputs the output drivers pull up and pull down resistors are disabled permanently A 1 3 2 Analog Reference This group is made up by the VRH and VRL pins A 1 3 3 Oscillator The pins XFC EXTAL XTAL dedicated to the oscillator have a nominal 2 5V level They are supplied by VDDPLL A 1 3 4 TEST This pin is used for production testing only A 1 3 5 VREGEN This pin is used to enable the on chip voltage regulator 90 M MOTOROLA 1 4 Current Injection Power supply must maintain regulation within operating Vpps or range during instantaneous and MC9S12DT256 Device User Guide V03 03 operating maximum current conditions If positive injection current Vi gt is greater than Ipps the injection current may flow out of VDDS5 and could result in external power supply going out of regulation Ensure external VDD5 load will shunt current greater than max
99. oller Area Network controllers 1 or 0 or CANO It can be configured as the slave select pin SS of the Serial Peripheral Interface SPIO 2 3 39 2 RXCAN1 RXCANO MISOO Port M I O Pin 2 PM2 is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 1 or 0 CANO It can be configured as the master input during master mode or slave output pin during slave mode MISO for the Serial Peripheral Interface 0 SPIO M MOTOROLA 63 MC9S12DT256 Device User Guide V03 03 2 3 40 PM1 TXCANO TXB Port I O Pin 1 is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 CANO It can be configured as the transmit pin TXB of the BDLC 2 3 41 RXCANO RXB Port M I O Pin 0 PMO is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 CANO It can be configured as the receive pin RXB of the BDLC 2 3 42 PP7 KWP7 PWM7 SCK2 Port P I O Pin 7 PP7 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 7 output It can be configured as serial clock pin SCK of the Serial P
100. ons will be blocked 4 3 3 Unsecuring the Microcontroller In order to unsecure the microcontroller the internal FLASH and EEPROM must be erased This can be done through an external program in expanded mode Once the user has erased the FLASH and EEPROM the part can be reset into special single chip mode This invokes a program that verifies the erasure of the internal FLASH and EEPROM Once this program completes the user can erase and program the FLASH security bits to the unsecured state This is generally done through the BDM but the user could also change to expanded mode by writing the mode bits through the BDM and jumping to an external program again through BDM commands Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state the part will be secured again 4 4 Low Power Modes The microcontroller features three main low power modes Consult the respective Block User Guide for information on the module behavior in Stop Pseudo Stop and Wait Mode An important source of information about the clock system is the Clock and Reset Generator User Guide CRG 4 4 1 Stop Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode Wake up from this mode can be done via reset or external interrupts 4 4 2 Pseudo Stop This mode is entered by executing the CPU STOP instruction In this mode the oscillator is still running and th
101. or Address Bt7 Bits Bits Bt2 Biti Bit 0 0034 SYNR et SYN5 SYN4 SYN3 SYN2 SYN 0035 REFDV c REFDV3 REFDV2 REFDV1 REFDVO R CTFLG Read TOUT7 TOUT6 TOUTS TOUT4 TOUT3 TOUT2 TOUTI TOUTO TESTONLY Write 0037 CRGFLG e PROF D al lock TRAC sen 0038 CRGINT Im RTIE 0 0 Lockie 0 SCMIE gt 0039 CLKSEL e PLLSEL PSTP SYSWAI ROAWAI PLLWAI RTIWAI COPWAI Read 0 003A 225 CME PLLON AUTO PRE PCE SCME Read 0 003B RTIETE 2542 RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTRO 008C COPCTL ao wcop 9 0 0 CRI CRO 30 M MOTOROLA 0034 003F Address 003D 003E 003F Name FORBYP TEST ONLY CTCTL TEST ONLY ARMCOP 0040 007F Address 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 004A 004B 004C 004D 004E 004F 0050 0051 0052 M MOTOROLA Name TIOS CFORC OC7M OC7D TCNT hi TCNT lo TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 TCO hi TCO lo TC1 hi Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write
102. or whether Pierce oscillator external clock circuitry is used The state of this pin is latched at the rising edge of RESET If the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator If input is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL Since this pin is an input with a pull up device during reset if the pin is left floating the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL 58 M MOTOROLA MC9S12DT256 Device User Guide V03 03 Figure 2 4 Colpitts Oscillator Connections PE7 1 Crystalor ceramic resonator VSSPLL Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal Please contact the crystal manufacturer for crystal DC Figure 2 5 Pierce Oscillator Connections PE7 0 T Crystal or ceramic resonator Rs can be zero shorted when use with higher frequency crystals Refer to manufacturer s data 59 M MOTOROLA MC9S12DT256 Device User Guide V03 03 Figure 2 6 External Clock Connections PE7z0 EXTAL CMOS COMPATIBLE EXTERNAL OSCILLATOR VDDPLL Level MCU XTAL not connected 2 3 14 PE6 MODB IPIPE1 Port Pin 6 is a general purpose input or output pin It is used as a MCU operating mode select pin during reset The state of this pin is latched to the MODB bit at the rising edg
103. pheral Interface 0 SPIO 2 3 51 PS6 SCKO Port S I O Pin 6 PS6 is a general purpose input or output pin It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 SPIO 2 3 52 PS5 MOSIO Port S I O Pin 5 PS5 is a general purpose input or output pin It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 0 SPIO 2 3 53 PS4 500 Port 5 I O Pin 4 PS4 is a general purpose input or output pin It can be configured as master input during master mode or slave output pin during slave mode MOSI of the Serial Peripheral Interface 0 SPIO 2 3 54 PS3 TXD1 Port S I O Pin PS3 is a general purpose input or output pin It can be configured as the transmit pin TXD of Serial Communication Interface 1 SCI1 M MOTOROLA 65 MC9S12DT256 Device User Guide 03 03 2 3 55 PS2 RXD1 Port S I O Pin 2 PS2 is a general purpose input or output pin It can be configured as the receive pin RXD of Serial Communication Interface 1 SCI1 2 3 56 PS1 TXD0 Port S I O Pin 1 PS1 is a general purpose input or output pin It can be configured as the transmit pin TXD of Serial Communication Interface 0 SCIO 2 3 57 PSO Port S I O Pin 0 PSO is a general purpose input or output pin It can be configured as the receive pin RXD of Serial Communication Interface 0 SCIO 2 3 58 PT 7
104. put or output pins In MCU expanded modes of operation these pins provide the expanded address XADDR 19 14 for the external bus 2 3 34 PM7 TXCAN4 Port M I O Pin 7 PM7 is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 4 CANA 2 3 35 PM6 RXCANA Port I O Pin 6 PM6 is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 4 CANA 2 3 36 5 TXCANA SCKO Port M I O Pin 5 PMS is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 0 or 4 CANO or CANA It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 SPIO 2 3 37 PM4 RXCANO RXCAN4 MOSIO Port M I O Pin 4 is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 0 or 4 CANO or CANA It can be configured as the master output during master mode or slave input pin during slave mode MOSI for the Serial Peripheral Interface 0 SPIO 2 3 38 1 SSO Port I O Pin is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the Motorola Scalable Contr
105. r and if not required it must simply be erased prior to flash programming For more details of the 512 LRAE and its implementation please see the 512 LREA Application Note AN2546 D It is planned that most HC9S12 devices manufactured after Q1 of 2004 will be shipped with the S12 LRAE programmed in the Flash Exact details of the changeover i e blank to programmed for each product will be communicated in advance via GPCN and will be traceable by the customer via datecode marking on the device Please contact Motorola SPS Sales if you have any additional questions Consult the FTS256K Block User Guide for information about the flash module Section 16 EEPROM 4K Block Description M MOTOROLA 81 MC9S12DT256 Device User Guide V03 03 Consult the EETSAK Block User Guide for information about the EEPROM module Section 17 RAM Block Description This module supports single cycle misaligned word accesses Section 18 MSCAN Block Description There are three MSCAN modules and CANO implemented on the MC9S12DT256 Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module Section 19 Port Integration Module PIM Block Description Consult the PIM 9DP256 Block User Guide for information about the Port Integration Module Section 20 Voltage Regulator VREG Block Description Consult the VREG Block User Guide for information about the dual output linear voltage regulator 82
106. ram Figure 1 1 shows a block diagram of the MC9S12DT256 device 22 M MOTOROLA MC9S12DT256 Device User Guide V03 03 Figure 1 1 MC9S12DT256 Block Diagram Voltage Regulator VRH VRL VDDA VSSA VRH VRL VDDA VSSA ATDO ATD1 Single wire Background Debug Module Periodic Interrupt XFC VDDPLL n and eset VSSPLL PEL Generation Watchdog Clock Monitor RESET Breakpoints XIRQ PE1 R W System ISTRE integration PEA ECLK odule SIM 5 PE6 MODB PE7 5 Multiplexed Address Data Bus Enhanced Capture Timer BDLC RXB 41850 PM1 CANO Txcan 22222922 CAN1 PXCAN D TXCAN PM4 er RON QN tc crecer ccc 5 Sasascsas 00000000 oooooaoaoo 6 lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt PM7 Did oi ioe Multiplexed lt lt lt lt lt lt lt lt lt lt lt 4 lt lt lt lt Wide Bus EEEEEEEE EEEEEEEE Toan Multiplexed 22 28 xg EEEEEEEE Narrow Buss a S X X Xa X Internal Logic 2 5V Driver 5V VDD1 2 VDDX VSS1 2 VSSX ails 1 A D Converter 5V amp PLL 2 5V Voltage
107. rations are not applicable to EEPROM 5 Minimum Erase times are achieved under maximum NVM operating frequency 6 Minimum time if first word in the array is not blank 7 Maximum time to complete check on an erased block A 3 2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification constant process monitors and burn in to screen early life failures The failure rates for data retention and program erase cycling are specified at the operating conditions noted The program erase cycle count on the sector is incremented every time a sector or mass erase event is executed NOTE All values shown in Table A 12 are target values and subject to further extensive characterization Table A 12 NVM Reliability Characteristics Conditions are shown in Table A 4 unless otherwise noted 1 C Data Retention at an average junction temperature of Tis 70 INVMRET 15 Years 2 Flash number Program Erase cycles 1000 10 000 Cycles C EEPROM number of Program Erase cycles 10 000 40 T lt 0 n N C EEPROM number of Program Erase cycles m 100 000 0 Ty 140 C M MOTOROLA 105 MC9S12DT256 Device User Guide V03 03 106 44 MOTOROLA 4 Voltage Regulator MC9S12DT256 Device User Guide V03 03 The on chip voltage regulator is intended to supply the internal logic and oscillator circuits
108. reset address range 0280 02BF if using a derivative without CANA Do not write or read BDLC registers after reset address range 00 8 00EF if using a derivative without BDLC e Interrupts the four CANO interrupt vectors SFFBO FFB7 according to your coding policies for unused interrupts if using a derivative without CANO Fill the four CANI interrupt vectors FFAS8 FFAF according to your coding policies for unused interrupts if using a derivative without CANI Fill the four CANA interrupt vectors SFF90 FF97 according to your coding policies for unused interrupts if using a derivative without CANA Hil the BDLC interrupt vector SFFC2 FFC3 according to your coding policies for unused interrupts if using a derivative without BDLC Ports The CANO pin functionality TXCANO RXCANO is not available on port PJ7 PJ6 5 PM4 PM3 PM2 PMI and if using a derivative without CANO CANI pin functionality TXCAN1 is not available on port and PM2 if using a derivative without CANI The CAN4 pin functionality TXCAN4 RXCANA is not available on port PJ7 PJ6 5 PM6 5 and PM4 if using a derivative without CANO The BDLC pin functionality TXB RXB is not available on port PM1 and PMO if using a derivative without BDLC Donot write MODRRI and MODRRO bits of Module Routing Register PIM 9DP256 Block
109. ress Bt7 Bits Bits Bits Bit2 Bit Bit 0 Read Bit7 6 5 4 3 2 1 Bit 0 PWMONTS 7G 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 VOOR 7 Write 270 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 SUB ENDICISET Auer 50 0 0 0 0 0 0 0 0084 PwMPERO 192 pi 6 5 4 3 2 1 Bit 0 Write 0085 PWMPERi 1932 6 5 4 3 2 1 Bit 0 Write 0086 PWMPER2 19 6 5 4 3 2 1 Bit 0 Write 0087 PwMPER3 1929 pi 6 5 4 3 2 1 Bit 0 Write 0088 PWMPER4 1932 pi 6 5 4 3 2 1 Bit 0 Write 0089 PWMPERS 1929 pi 6 5 4 3 2 1 Bit 0 Write 008BA PWMPERe 192 pi 6 5 4 3 2 1 Bit 0 Write 00BB PWMPER7 1932 pi 6 5 4 3 2 1 Bit 0 Write 008C 192 pi 6 5 4 3 2 1 Bit 0 Write 90080 PwMDTvi 19 6 5 4 3 2 1 Bit 0 Write 00BE PwMDrv2 1932 pi 6 5 4 3 2 1 Bit 0 Write 00BF PwMpTva 192 pi 6 5 4 3 2 1 Bit 0 Write 00C0 PWMDTY4 19 pi 6 5 4 3 2 1 Bit 0 Write 0061 PWMDTY5 192 pi 6 5 4 3 2 1 Bit 0 Write 00c2 PWMDTY6 192 pi 6 5 4 3 2 1 Bit 0 Write 0003 PWMDTYZ 19 pi 6 5 4 3 2 1 Bit 0 Write Read PWMRS 0 PWM7IN PWM7E 0004 PWMSDN 282 PWMIF PWMIE PWMLVL PWMZIN T ar Read 0 0 0 0 0 0 0 0 00C5 Reserved Write Read 0 0 0 0 0 0 0 0 00C6 Reserved Write Read 0 0 0 0 0 0 0 0 00C7 Reserved Write 36 M MOTOROLA 00 8 00 Address 00C8 00C9 00CA 00CB 00CC 0
110. sification is shown in the column labeled in the parameter tables where appropriate Those parameters are guaranteed during production testing on each individual device Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted values shown in the typical column are within this category Those parameters are derived mainly from simulations A 1 2 Power Supply The MC9S12DT256 utilizes several pins to supply power to the I O ports A D converter oscillator and PLL as well as the digital core The VDDA VSSA pair supplies the A D converter and the resistor ladder of the internal voltage regulator M MOTOROLA 89 MC9S12DT256 Device User Guide V03 03 The VDDX 55 VDDR and VSSR pairs supply the I O pins supplies also the internal voltage regulator VDDI VSS1 VDD2 and VSS2 are the supply pins for the digital logic VDDPLL VSSPLL supply the oscillator and the PLL VSS1 and VSS2 are internally connected metal VDDX VDDR as well as VSSA VSSX VSSR are connected by anti parallel diodes for ESD protection NOTE the following context VDDS is used for either VDDA VDDR VDDX VSSS is used for either VSSA VSSR and VSSX unless otherwise noted 205 de
111. t VREGEN Voltage Regulator Enable Input XFC PLL Loop Filter Background Debug Tag High Mode Input Port AD Input Analog Input AN7 of ATD1 External Trigger Input of ATD1 BKGD PAD 15 1 7 ETRIG1 VDDA Port AD Inputs Analog Inputs PAD 14 8 AN1 6 0 VDDA AN 6 0 of ATD1 Port AD Input Analog Input AN7 of PAD 7 ANO 7 ETRIGO VDDA ATDO External Trigger Input of ATDO ANOIS VDDA Port AD Inputs Analog Inputs 6 0 0 6 0 6 0 of ADDR 15 8 PA 7 0 DATA 15 8 VDDR Disabled Port A I O Multiplexed Address Data ADDR 7 0 PE7 NOACC XCLKS VDDR PUCR Up Port E I O Access Clock Select While RESET IPIPE1 VDDR pin is low Port E I O Pipe Status Mode Input Down While RESET VDDR pin is low Port E Pipe Status Mode Input Down Port E Bus Clock Output Port E Byte Strobe Tag Low Port R W in expanded modes Port E Input Maskable Interrupt EL VDDR PUCR Up Port E Input Non Maskable Interrupt VDDR Disabled Port I O Interrupt SS of SPI2 VDDR Disabled Port H 1 0 Interrupt SCK of SPI2 VDDR Disabled Port H 1 0 Interrupt MOSI of SPI2 54 M MOTOROLA MC9S12DT256 Device User Guide V03 03 Internal Pull Pin Pin Name Pin Name Pin Name Pin Power Resistor Description Funct 1
112. t 0 0104 FPROT ne FPOPEN NV6 FPHDIS 1 FPHSO FPLDIS FPLS1 FPLSO 0105 FSTAT ve accERR 0 BLANK 0 0106 FCMD d 0 CMDB5 0 0 0107 Reserved Read 0 0 0 0 0 0 0 0 Factory Test Write 0108 FADDRH 194 0 54 13 12 11 10 9 Bit 8 Write 0109 FADDRLO 1929 6 5 4 3 2 1 Bit 0 Write 0108 FDATAHI 1930 Bit 15 14 13 12 11 10 9 Bit 8 Write 0108 FDATALO 1932 6 5 4 3 2 1 Bit 0 Write Read 0 0 0 0 0 0 0 0 01 0 Reserved Write Read 0 0 0 0 0 0 0 0 01 00 Reserved Write pN Read 0 0 0 0 0 0 0 0 01 OE Reserved Write zb ge SS SS Read 0 0 0 0 0 0 0 0 01 Reserved Write SS 0110 011B Control Register eets4k Address Bt7 Bits Bits Bt2 Biti Bit 0 0110 ECLKDIV PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIVi EDIVO Read 0 0 0 0 0 0 0 0 01 11 Reserved Write nz 0112 Reserved for Read 0 0 0 0 0 0 0 0 Factory Test Write 0113 ecnra Read CCIE gt 0 0 0 0 Write 0114 EPROT 1 Ye Eppis Ep2 1 0115 ESTAT re 0 BLANK 9 0 0116 ECMD 4 0 9 0 0 0117 Reserved for Read 0 0 0 0 0 0 0 0 Factory Test Write solls SEADDHEE 9 Bit 8 Write 40 M
113. t Pins of ATD1 PAD14 PADOS are general purpose input pins and analog inputs AN 6 0 of the analog to digital converter ATDI M MOTOROLA 57 MC9S12DT256 Device User Guide V03 03 2 3 9 PAD7 ANO7 ETRIGO Port AD Input Pin of ATDO is a general purpose input pin and analog input AN7 of the analog to digital converter ATDO It can act as an external trigger input for the ATDO 2 3 10 PAD 06 00 AN 06 00 Port AD Input Pins of ATDO PADO6 PADOO are general purpose input pins and analog inputs AN 6 0 of the analog to digital converter ATDO 2 3 11 PA 7 0 ADDR 15 8 DATA 15 8 Port A I O Pins PA7 PAO are general purpose input or output pins In MCU expanded modes of operation these pins used for the multiplexed external address and data bus 2 3 12 PB 7 0 ADDR 7 0 DATA 7 0 Port B I O Pins PB7 PBO are general purpose input or output pins In MCU expanded modes of operation these pins are used for the multiplexed external address and data bus 2 3 13 XCLKS Port E I O Pin 7 PE7 is a general purpose input or output pin During MCU expanded modes of operation the NOACC signal when enabled is used to indicate that the current bus cycle is an unused or free cycle This signal will assert when the CPU is not using the bus The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts low power oscillator is used
114. test startup time possible is given by nyposc 5 1 2 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU preventing the CPU from executing code when VDDS is out of specification limits the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set A 5 1 3 External Reset When external reset is asserted for a time greater than the CRG module generates an internal reset and the CPU starts fetching the reset vector without doing a clock quality check if there was an oscillation before reset A 5 1 4 Stop Recovery Out of STOP the controller can be woken up by an external interrupt A clock quality check as after POR is performed before releasing the clocks to the system M MOTOROLA 109 MC9S12DT256 Device User Guide V03 03 A 5 1 5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes The controller can be woken up by internal or external interrupts After twrs the CPU starts fetching the interrupt vector A 5 2 Oscillator The device features an internal Colpitts and Pierce oscillator The selection of Colpitts oscillator or Pierce oscillator external clock depends on the XCLKS signal which is sampled during reset By asserting XCLKS input during reset this oscillator can be bypassed allowing the input of a square wave Before
115. the Secured Microcontroller 72 4 3 3 Unsecuring the Microcontroller 73 44 Cow Power Modes I S ho Lie aint STET 73 4 4 1 SIOD rn ae x ded dome ng wee rotulum A alt 73 4 4 2 rr 73 4 4 3 NV all ae De D diete tcr 73 4 4 4 coto Ear er EOM Cur Ra ERROR NER 74 Section 5 Resets and Interrupts 5 1 qu SEIEN 75 527 MECIONS ETE De tod re ded 75 5 2 1 Vector 22 5 2252 S IRE Pn breeds Rude ew 75 222 Effects t uos Sn nn da ah Pate ee Qus ye thee grs 77 5 3 1 DING CT eT 77 5 3 2 Memo a DN TL SUL 77 Section 6 HCS12 Core Block Description M MOTOROLA 7 MC9S12DT256 Device User Guide V03 03 6 1 CPU12 Block Description seeen S Sut dte 79 6 2 512 Module Mapping Control MMC Block Description 79 6 2 1 Device specific information 79 6 3 HCS12Multiplexed External Bus Interface MEBI Block Description 79 6 3 1 Device specific information 79 6 4 HCS12 Interrupt INT Block description
116. ulse per pin positive 3 negative 3 Minimum input voltage limit 2 5 V Latch up Maximum input voltage limit 7 5 V Table A 3 ESD and Latch Up Protection Characteristics EE Rating Symbol Min Max Unit EE Human Body Model HBM 2000 C Machine Model MM VMM 200 V C Charge Device Model CDM 500 V Latch up Current at Ta 125 C 4 positive ILAT 100 5 mA negative 100 Latch up Current at T 27 C 5 C positive 200 negative 200 92 M MOTOROLA MC9S12DT256 Device User Guide V03 03 A 1 7 Operating Conditions This chapter describes the operating conditions of the device Unless otherwise noted those conditions apply to all the following data NOTE Please refer to the temperature rating of the device C V M with regards to the ambient temperature T4 and the junction temperature For power dissipation calculations refer to Section A 1 8 Power Dissipation and Thermal Characteristics Table 4 Operating Conditions Rating Symbol Min Typ Max Unit Regulator and Analog Supply Voltage 5 4 5 5 5 25 V Digital Logic Supply Voltage Vpp 2 35 25 2 75 V PLL Supply Voltage 1 VDDPLL 2 35 25 2 75 V Voltage Difference VDDX to VDDR and VDDA 0 1 0 0 1 V Voltage Difference VSSX to VSSR and VSSA Avssx 0 1 0 0 1 V Oscillator fosc 0 5 16 MHz Bus Frequency fous 0 5 25 MHz MC9S12DT256C Operating Junction Temperature Range 4
117. ult the Block User Guide for information about the Inter IC Bus module Section 11 Serial Communications Interface SCI Block Description 80 MOTOROLA MC9S12DT256 Device User Guide V03 03 There are two Serial Communications Interfaces 5 and SCIO implemented on the MC9S12DT256 device Consult the SCI Block User Guide for information about each Serial Communications Interface module Section 12 Serial Peripheral Interface SPI Block Description There are three Serial Peripheral Interfaces SPI2 SPI1 and SPIO implemented on MC9S12DT256 Consult the SPI Block User Guide for information about each Serial Peripheral Interface module Section 13 J1850 BDLC Block Description Consult the BDLC Block User Guide for information about the J1850 module Section 14 Pulse Width Modulator PWM Block Description Consult the 8B8C Block User Guide for information about the Pulse Width Modulator module When the PWM SB8CBlock Guide refers to freeze mode this is equivalent to active mode Section 15 Flash EEPROM 256K Block Description The S12 LRAE is a generic Load RAM and Execute LRAE program which will be programmed into the flash memory of this device during manufacture This LRAE program will provide greater programming flexibility to the end users by allowing the device to be programmed directly using CAN or SCI after it is assembled on the PCB Use of the LRAE program is at the discretion of the end use
118. ust be considered 1 Internal Voltage Regulator disabled Pint Ypo VbpPLL 2 is sum of all output currents on I O ports associated with VDDX and VDDR For Rpson is valid R outputs driven low DSON P respectively V V RDSON en for outputs driven high 2 Internal voltage regulator enabled Pint YDDA Ippg is current shown in Table 7 and not overall current flowing into VDDR which additionally contains the current flowing into the external loads with output high 2 is sum of all output currents on I O ports associated with VDDX VDDR 94 M MOTOROLA MC9S12DT256 Device User Guide V03 03 Table A 5 Thermal Package Characteristics Rating Unit C W C W Thermal Resistance LQFP 80 double sided PCB 9 _ an with 2 internal planes JA 41 NOTES 1 The values for thermal resistance are achieved by package simulations 2 PC Board according to EIA JEDEC Standard 51 2 3 PC Board according to EIA JEDEC Standard 51 7 A 1 9 Characteristics This section describes the characteristics of all 5V I O pins parameters are not always applicable e g not all pins feature pull up down resistances M MOTOROLA 95 MC9S12DT256 Device User Guide V03 03
119. y INL is defined as the sum of all DNLs n V V _ n 0_ INL n L DNL rsg 101 M MOTOROLA MC9S12DT256 Device User Guide V03 03 3FF 3FE 3FD 3FC 3FB 3FA 3F9 3F8 3F7 3F6 3F5 3F4 3F3 10 Bit Resolution DNL LSB Vi 10 Absolute Error Boundary 8 Bit Absolute Error Boundary un N N N N deal Transfer Curve FD 100 8 Bit Resolut N 7 4 10 Transfer N 8 Bit Transfer Curve Un 50 Figure A 1 ATD Accuracy Definitions gt 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120 Vin mV NOTE Figure A 1 shows only definitions for specification values refer to Table A 10 102 M MOTOROLA MC9S12DT256 Device User Guide V03 03 A 3 NVM Flash and EEPROM NOTE Unless otherwise noted the abbreviation NVM Non Volatile Memory is used for both Flash and EEPROM A 3 1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator A minimum oscillator frequency fyymosc is required for performing program or erase operations The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum Attempting to program or erase the NVM modules at a lower freque

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