Home

MC9S12DT256 Device User Guide V03.07 Covers also

1. 91 1 5 Absolute Maximum Ratings 3 91 1 6 ESD Protection Latch up 92 A 1 7 Operating Conditions 93 A 1 8 Power Dissipation and Thermal Characteristics 93 A 1 9 VO Characteristics AE NM ca eee 95 A 1 10 Supply So 97 A 2 ATD Characteristigs gt M oe AN AY Re 99 A 2 1 Operating Characteristics 99 A 2 2 Factors influencing 99 A 2 3 5 2 3 OM RE ee OM 101 A 33 Flash and EERROM DOG 103 A 3 1 NVIWtiming AN ARN CY CNN 103 A 3 2 NVM Reliability f QM S eS ah 105 Voltage Regulator x Y Og zoe 109 ResetlOscillat r and SM cate 111 A 5 1 iux oes ANNI Net 0 NN 111 A 5 2 lt N cope INIT x her ee NUS 112 A 5 3 Phase LockecLoop 8 eter 113 117 QU SEIN
2. 73 44 PowerModes lt NBI I eee NM RE 73 4 4 1 S Co cuo s an ss A 73 4 4 2 Pseudo Stop 1 Y N 73 4 4 3 Wall ad anes sae eae 73 4 4 4 ean eee MEET mE AN 74 Section 5 Resets and Interrupts 5 1 Overview 7 WANN ow ee ee lt N 75 5 2 aN a 75 5 2 1 NMU 75 5 3 Effects of Reset 77 5 3 1 VO Bins Ne ees 77 5 3 2 Mem eH eRe 77 Section 6 HCS12 Core Block Description MOTOROLA 7 MC9S12DT256 Device User Guide V03 07 6 1 CPU12 Block Description as 79 6 2 512 Module Mapping Control MMC Block 79 6 2 1 Device specific information 79 6 3 512 Multiplexed External Bus Interface MEBI Block Description 79 6 3 1 Device specific information 79 6 4 HCS12 Interrupt INT Block description 79 6 5 HCS12 Background Debug BDM Block Description 79 6 6 HC
3. Table 0 3 shows the Specification Change Summary for Maskset L91N Table 0 3 Speci cation Chang e Summary for Maskset L91N Block Spec Change MCU 9DT256 removed and CAN3 HCS12 V1 5 The Background Debug Module includes an Acknowledge Protocol two additional hardware commands ACK ENABLE ACK DISABLE HCS12 V1 5 The state of PK7 ROMCTL is latched into ROMON Bit during RESET into Emulation Mode or Normal Expanded Mode CRG Maskset includes an additional Pierce Oscillator MOTOROLA MC9S12DT256 Device User Guide V03 07 Table 0 3 Speci cation Chang e Summary for Maskset L91N Block Spec Change EETS4K FTS256K Reliability Speci cation f or Non Volatile Memories PIM_9DP256 CANO can be routed to PORTJ 18 MOTOROLA MC9S12DT256 Device User Guide 03 07 Section 1 IntroductionMC9S12DT256 1 1 Overview The MC9S12DT256 microcontroller unit MCU is a 16 bit device composed of standard on chip peripherals including a 16 bit central processing unit HCS12 CPU 256K bytes of Flash EEPROM 12K bytes of RAM 4K bytes of EEPROM two asynchronous serial communications interfaces SCI three serial peripheral interfaces SPI an 8 channel IC OC enhanced capture timer two 8 channel 10 bit analog to digital converters ADC an 8 channel pulse width modulator PWM a digital Byte Data Link Controller BDLC 29 discrete digital I O channels Port A Port B Port K and Port E 20 discr
4. gt gt 2 9 o gt o 0 0 0 0 ole alale eo Rip eo 0 25 m ce 11 000 BSC 22 000 BSC 11 000 BSC 0 250 REF 1 000 REF GAGE PLANE lt 1 o o 2 do ae e o 4 48 o B B1 D E 0 090 K 0500 P 325 R1 R2 S1 7 01 92 03 11 13 VIEW AB Figure B 1 112 pin LQFP mechanical dimensions case no 987 128 MOTOROLA MC9S12DT256 Device User Guide 03 07 B 3 80 pin QFP package it A H 886 3 5753170 86 21 54151736 WERE JJ HL 86 755 83298787 Http www 100y com tw DETAIL A 02000 p 5 DETAIL 0 20 C aB p i SECTION B B PLANE VIEW ROTATED 90 a 7 Ea 21010 PLANE NOTES MILLIMETERS 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 DIM MIN 2 CONTROLLING DIMENSION MILLIMETER 1390 14 10 3 DATUM PLANE H IS LOCATED ar BOTTOM OF B 1390 1410 LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS TH
5. eet es es edo S 119 A 7 1 amp 3 AN I AM oA EE NS 119 A 7 2 Mode QOS ANT 121 8 External NR 2 a MN YI NN eee 123 A 8 1 General Muxed Bus 123 Appendix B Package Information General nl ae ce cee AZ I eese 127 2 112 pin SQFP pacRage 128 80 a AUT 0 I 129 MOTOROLA 9 MC9S12DT256 Device User Guide V03 07 F 886 3 5753170 JE JJ 86 21 54151736 WEED 86 755 83298787 Http www 100y com tw 10 MOTOROLA MC9S12DT256 Device User Guide 03 07 List of Figures Figure 0 1 15 Figure 1 1 MC9S12DT256 Block 23 Figure 1 2 MC9S12DT256 Memory 26 Figure 2 1 Pin Assignments 112 pin 2 52 Figure 2 2 Pin Assignments in 80 pin QFP for 9512 256 53 Figure 2 3 PLL Loop Filter 2 22 5 Br Figure 2 4 Colpitts Oscillator Connections 7 1 59 Figur
6. eee 53 MC9S12DP256 Power Ground Connection 67 1 M A M Ave ak 71 Clock Selection Based on PEZ 71 Voltage Regulator WREGEN 4 AN AND GME 72 Interrupt Vector Locations 75 Absolute Maximum Ratings 91 ESD and Latch up Test Conditions 92 ESD and Latch Up Protection 5 92 Operating Conditions Qe 93 Thermal Package Characteristics 95 5V I O Characteristics Net ee 96 Supply Current Characteristics Nw c Qed ae ee 98 Operating Characteristics 99 ATD Electrical 5 100 Conversion Performance 101 NVM Timing 70 d 104 NVM Reliability 5 106 Voltage Regulator Recommended Load Capacitances 109 Startup Characteristics 8 AN U UN 111 Oscillator Characteristics
7. 112 PLL OltaractgslstiGS ea 116 MSCAN Wake up Pulse 5 117 Measurement 119 SPI Master Mode Timing 5 120 SPI Slave Mode Timing 122 MOTOROLA 13 MC9S12DT256 Device User Guide V03 07 Table A 21 Expanded Bus Timing Characteristics 125 14 MOTOROLA MC9S12DT256 Device User Guide 03 07 Derivative Differences and Document References Derivative Differences Table 0 1 shows the availability of peripheral modules on the various derivatives For details about the compatibility within the MC9S12D Family refer also to engineering bulletin EB386 Table 0 1 Derivative Differences oa MC9S12A256 MC9S12DT256 MC9S12DJ256 MC9S12DG256 3 2 2 of CANs CANO CAN1 CAN4 J1850 BDLC Package 112 LQFP 80 QFP 112 LOFP 80 QFP 112 LOFP 80 QFP 112 LOFP 80 Mask set L91N LO1Y L91N LO1Y L91N LO1Y L91N LO1Y Temp Options C M V C V C M V C Package PV FU PV FU PV FU PV FU Code An errata exists An errata exists An errata exists An errata exists Notes contact Sales contact Sales contact Sales contact Sales Of ce Of ce Of ce Of ce The following figure provides an ordering number example for the M
8. 3 20 gt 9 gt OUTPUT note X X BIT6 1 SLAVELSBOUT X d MOSI NOTE Not defined Figure A 8 SPI Slave Timing CPHA 0 In Figure A 9 the timing diagram for slave mode with transmission format CPHA 1 is depicted MOTOROLA 121 MC9S12DT256 Device User Guide V03 07 SS INPUT SCK 0 INPUT MISO See SCK CPOL 1 INPUT pO OUTPUT note ASLAVE MSB OUT MOSI INPUT ir NOTE Not defined N Neo X SLAVELSBOUT Figure A 9 SPI Slave Timing CPHA 1 In Table A 20 the timing characteristics for slave mode are listed Table A 20 SPI Slave Mode Timing Characteristics Num Characteristic Symbol Min Typ Max Unit 1 SCK Frequency fsck DC 1 4 fous 1 SCK Period 4 tous 2 Enable Lead Time tlead 4 tous 3 Enable Lag Time tlag 4 sy tous 4 Clock SCK High or Low Time twsck 4 tous 5 Data Setup Time Inputs tsu 9 LOS ANN ns 6 Data Hold Time Inputs i AN ns 7 Slave Access Time time to data active ns 8 Slave MISO Disable Time ns 9 Data Valid after SCK Edge ns 10 Data Valid after SS fall ns 11 Data Hold Time Outputs ns 12 Rise and Fall Time Inputs ns 13 Rise and Fall Time Outputs ns NOTES 1 tbus added due to internal synchronization delay 122 4 ZH 886 3 5753170
9. 1924 16 Write 14 13 12 11 10 9 Bit8 0134 ATDipRou Head 5 Write Read Bit 0 0 0 0 0 0135 ArDipmaL 1934 us D Write Read Biti 14 13 12 11 10 9 Bit8 0136 ATDipRau 1924 Bills Write Read Bit6 0 0 0 0 0 0 50137 ArDipRaL 162 Write Read 14 13 12 11 10 9 Bit8 0138 ATDipR4u 1924 8115 Write Read Bit 0 0 0 0 0 0139 ArDipn4L 1924 Bi ite 0 Write Read 14 13 12 11 10 9 Bit8 013A ATDiDRsH 1924 Bit Write Read Bit 0 0 0 0 0 0 013B 1934 Write Read 14 13 12 11 10 9 Bit8 013C ATDibReu 1929 Write Read Bit 0 0 0 0 0 0 013D ArDiDReL 1924 Bi ite Write Read 5 14 13 12 11 10 9 Bit8 013E ArDipR7zH 1924 Write Read Bit6 0 0 0 0 0 0 013F ArDipnzL 1924 Write 0140 017F CANO Motorola Scalable CAN MSCAN Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0140 CANOCTLO ane LEXACT LSYNCH tive WUPE SLPRO INITRO 50141 CANOCTL1 Mey CLKSRC LOOPB LISTEN 0 wupm INITAK 0142 MN SJW1 SJWO BRP2 42 MOTOROLA 50140 Address 0143 0144 0145 0146 0147 0148 0149 014A 014B 014C 014D 014E
10. 5 Write O 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 80082 PWMCNT6 Write 0 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 0083 PWMCNT7 Write 0 0 0 0 0 0 0 0 Read 0084 PWMPERO Bit 7 6 5 4 3 2 1 Bit 0 Write 0085 1984 6 5 4 3 2 1 Bit 0 Write 50086 PwMPER2 16984 gi 6 5 4 3 2 1 Bit 0 Write 60087 PwMPER3 1984 gi 6 5 4 3 2 1 Bit 0 Write 0088 PWMPER4 198 6 5 4 3 2 1 Bit 0 Write 0089 PwMPERs 1984 6 5 4 3 2 1 Bit 0 Write PwMPERe 1984 gi 6 5 4 3 2 1 Bit 0 Write 60088 PwMPER7 198 6 5 4 3 2 1 Bit 0 Write sooBc PwMDTYo 198 6 5 4 3 2 1 Bit 0 Write 80080 PwMpTvi 19324 6 5 4 3 2 1 Bit 0 Write sooBE 2 198 6 5 4 3 2 1 Bit 0 Write 500 PwMDTYs 198 6 5 4 3 2 1 Bit 0 Write 60000 PwMDTY4 168 gi 6 5 4 3 2 1 Bit 0 Write 00c1 PWMDTYs 198 6 5 4 3 2 1 Bit 0 Write 60002 PwMDTYe 198 6 5 4 3 2 1 Bit 0 Write 0003 PwMDTv7 198 6 5 4 3 2 1 Bit 0 Write Read PWMRS 0 PWM7IN PWM7E 0004 PWMSDN PWMIF PWMIE Tar PWMLVL PWMZIN T NA R 00C5 Reserved Sa 1 1 0 Write R 00 6 Reserved sai Q 9 0 Write R 00C7 Reserved 0 0 9 Write 36 MOTOROLA MC9S12DT256 Device User Guide 03 07 00 8 00CF SCIO Asy
11. VDDX PJ 1 0 KWJ 1 0 VDDX Port J I O Interrupts Port K I O Emulation Chip Select ROM On Enable VDDX PUCR Port K I O Extended Addresses PK7 ECS ROMONE VDDX XADDR PK 5 0 19 14 PERM VDDX PPSM Disabled Port M I O TX of CANA RXCAN4 Disabled Port M I O RX of CAN4 Port M I OCANO of SPIO RXCANA VDDX Port I O MOSI of RXCANO 0 PPSM isabled SPIO ub t Port M I O TX CANO SS TXCAN1 TXCANO Disabled of SPIO TXCANO TXCAN4 Disabled Port M I O RX of CAN1 CANO RXCAN1 RXCANO Disabled MISO of SPIO Disabled Port M I O TX of CANO of BDLC RXCANO Disabled Port I O RX of RX of BDLC Port P I O Interrupt Channel 7 of PWM SCK of SPI2 VDDX eana P UO InjerruptuChannel 6 of ppsp 0180 0 pwm SS of SP12 SI vppx Port Interrupt Channel 5 of Hi AS MN ppsp Disabled pwm MOSI of SP12 KWP7 Disabled 55 MC9S12DT256 Device User Guide V03 07 Internal Pull Pin Name Pin Name Pin Name Pin Name Pin Name Power Resistor Description Funct 1 Funct 2 Funct 3 Funct 4 Funct 5 Supply Reset CTRL State DD Port P I O Interrupt Channel 4 of Disabled MISO2 of SP12 VE Port P I O Interrupt Channel 3 of Disabled SS of
12. _ Write R 00F7 Reserved NS el NT NU UN Write 00F8 00FF SPI2 Serial Peripheral Interface Address 5 Bt2 Biti Bit 0 00F8 SPI2CR1 NS SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 00F9 SPI2CR2 was ________ ______ ____ BIDIROE 0 sPISWAI SPCO 00FA SPI2BR SPPR2 SPPR1 sPPRO 0 spre SPR SPRO SPIF PTEF MODF 4689 _ Oi k Write R 00FC Reserved Write 00oFD _ 5 1929 pir 6 5 4 3 2 1 Bito Write R 00FE Reserved NN a O Write R 00FF Reserved S M ii Write 0100 010F Flash Control Register fts256k Address Bite 5 Bt4 Bt2 Biti Bit 0 0100 FCLKDIV ee PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIVO Read KEYEN1 KEYENO NV NV4 NV NV2 EC1 E 0101 FSEC pad EKOUT LAM BR LSU MB SUM Write 0100 Feat o 0 D Write 0103 FCNFG nd CBEIE CCIE KEYACC k22 BKSEL1 BKSELO MOTOROLA 39 886 3 5753170 MC9S12DT256 Device User Guide V03 07 ERA 86 21 54151736 WE Hi GUI 86 755 83298787 0100 010F Flas
13. 0079 007A 007B 007C 007D 007E 007F Name Reserved TIMTST Test Only Reserved Reserved PBCTL PBFLG PA3H PA2H PA1H PAOH hi lo TCOH hi TCOH lo TC1H hi TC1H lo TC2H hi TC2H lo TC3H hi TC3H lo 0080 009F Address 0080 0081 M MOTOROLA Name ATDOCTLO ATDOCTL1 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S12DT256 Device User Guide V03 07 ECT Enhanced Capture Timer 16 Bit 8 Channels Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBOVF 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 ATDO Analog to Digital Converter 10 Bit 8 Channel 33 MC9S12DT256 Device User Guide V03 07 0080 0
14. 66 MC9S12DT256 Device User Guide 03 07 208 97 P amp 07RXDG Port S ROY INO cc ec ee 66 2 3 58 7 0 1 7 0 Port T I O 1 5 7 0 66 a4 Supply amp 66 2 4 1 VDDX VSSX Power amp Ground Pins for I O Drivers 66 2 4 2 VDDR VSSR Power amp Ground Pins for I O Drivers amp for Internal Voltage Regulator 66 2 4 3 VDD1 VDD2 VSS1 VSS2 Core Power 67 2 4 4 VDDA VSSA Power Supply Pins for and VREG 67 2 4 5 VRL Reference Voltage Input Pins 67 2 4 6 VDDPLL VSSPLL Power Supply Pins for PLL 67 2 4 7 VREGEN On Chip Voltage Regulator 68 Section 3 System Clock Description 3 1 Overview 7 iar ANTES NM eu 69 Section 4 Modes of Operation 41 Ov rview N N AY OM 71 4 2 Chip Configuration 71 4 3 5 72 4 3 1 Securing the Microcontroller 72 4 3 2 Operation of the Secured Microcontroller 72 4 3 3 Unsecuring the Microcontroller
15. I O 4 63 1 550 63 2 RXCAN1 MISOO Port 2 63 1 TXCANO TXB Port M I O Pin 1 64 RXCANO Port I O Pin 0 64 KWP7 PWM7 SCK2 Port P I O Pin 7 64 PP6 KWP6 PWM6 552 Port P 6 64 5 KWP5 5 5 2 Pin 5 64 KWP4 MISO2 Port P I O Pin 4 64 PWM3 S81 P Pin 3 64 2 KWP2 PWM2 SCK1 Port P I O Pin 2 65 PP1 KWP1 PWM1 MOSI Port P I O Pin 1 65 KWPO PWMO MISO1 Port P I O Pin 0 65 PSIN SSO Por Sd Ping W NNI ee RR 65 PS6 SOKO SJ Pin 6 se e 4 2 65 PS5 MQSIO 5 _ NY MILIA eie 65 PS4 MISOO Port SIOPin4 65 53 ARXD1 Port 65 PS2 POS 2 77 AM OM QS 66 PS1 TXDQ Port SWO Pim W NS
16. i NIN 1LSB The Integral Non Linearity INL is defined as the sum of all DNLs n Vo V INL n Y gt DNL i WB ud i 1 DNL i MOTOROLA 101 MC9S12DT256 Device User Guide V03 07 DNL 10 Bit Absolute Error Boundary A e Vi SEEK 8 Bit Absolute Error Boundary 7 3FE 7 3FD 7 7 3FB 7 3FA y 3F9 7 3F8 3F7 7 3F6 7 3F5 3F4 7 FD 10n 3F3 7 deat Transfer Curve Z i 7 7 Z 77 AIO Bit Transfer Curve 8 Bit Resolut N 10 Bit Resolution 1 NI N N 8 Bit Transfer Curve 50 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120 Vin N P ui 9i _ tA gt N 9 v mV Figure A 1 ATD Accuracy Definitions NOTE Figure A 1 shows only definitions for specification values refer to Table A 10 102 MOTOROLA MC9S12DT256 Device User Guide V03 07 A 3 NVM Flash and EEPROM NOTE Unless otherwise noted the abbreviation NVM Non Volatile Memory is used for both Flash and EEPROM A 3 1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator A minimum oscillator frequency fyymosc is required for performing program or erase opera
17. 000D 000E 000F Name PORTA PORTB DDRA DDRB Reserved Reserved Reserved Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved 0010 0014 Address 0010 0011 M MOTOROLA Name INITRM INITRG Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MEBI map 1 of 3 Core User Guide Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 Bit 7 6 5 4 3 Bit 2 lt 0 0 0 PIPOE NECLK LSTRE RDWE MODC MODB MODA 9 IVIS PUPBE PUPAE RDPK gt RDPE lt RDPB RDPA 0 0 0 0 0 0 0 EE 0 0 0 0 0 0 0 0 MMC map 1 of 4 Core User Guide Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 RAM15 RAM14 RAM13 12 RAM11 0 RAMHAL REG14 REG13 REG12 REG11 9 27 MC9S12DT256 Device User Guide V03 07 28 0010 0014 Address Name 0012 INITEE 0013 MISC 0014 Reserved 0015 0016 Address Name 0015
18. A 3 1 3 Sector Erase Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes 1 4000 te ra NVM OP The setup time can be ignored for this operation A 3 1 4 Mass Erase Erasing a NVM block takes 1 tmass 20000 NVMOP The setup time can be ignored for this operation A 3 1 5 Blank Check The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non blank word starting at relative address zero It takes one bus cycle per word to verify plus a setup of the command t location t 10 Table A 11 NVM Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted Num Rating Symbol Min Typ Max Unit 1 D External Oscillator Clock MC9S12DT256C lt V fNvMOSC 0 5 50 MHz 2 D Bus frequency for Programming or Erase Operations fNvwBus 4 P Single Word Programming Time 5 D Flash Burst Programming consecutive word us 6 D Flash Burst Programming Time for 32 Words us 7 Sector Erase Time lera 9 D Check Time Flash per block Pee 10 D Blank Check Time EEPROM per block tcheck 20587 NOTES 1 Restrictions for oscillator in crystal mode apply 2 Minimum Programming times are achieved under maximum NVM operating frequency and maximum bus frequency fpus 104 MOTOROLA MC9S12DT256 Device User Guide V03 07
19. 00DF SPIO Serial Peripheral Interface Address Bt5s Bt4 Bt2 Bit 0 0008 SPIOCR1 d SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0009 SPIOCR2 wis ________ ______ ____ BIDIROE 0 sPISWAI SPCO Read 0 0 00DA SPIOBR 22 pem SPPR2 SPPR1 SPPRO fm SPR2 SPRI SPRO Read SPIF PTEF MODF 0008 SPIOSR M C ed BRE CES LS MOTOROLA 37 MC9S12DT256 Device User Guide V03 07 50008 00DF SPIO Serial Peripheral Interface Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R 00DC Reserved Mick Q Write 0002 splopR 1944 pi 6 5 4 3 2 1 Bito Write R 00DE Reserved pad 9 Q 9 Write R 00DF Reserved e 0 Write 00E0 00E7 Inter Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0 IBAD os ADR7 ADR6 5 ADR4 ADR2 0 Read 00E1 IBFD Were BE 6 5 4 IBC3 IBC2 IBC1 IBCO Read 0 0 00E2 IBCR MSE TX RX TXAK IBSWAI Sones Read 5 mm 0 SRW Write 00E4 D6 D5 D4 D3 D2 D1 Write R 50025 Res
20. ABTAK2 TX2 IDHIT2 0 RXERR2 TXERR2 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 AC2 Bit 1 SLPRQ SLPAK BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 ABTRQ1 ABTAK1 TX1 IDHIT1 0 RXERR1 TXERR1 AC1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 AC1 Bit 0 INITRQ INITAK BRPO TSEG10 RXF RXFIE TXEO TXEIEO ABTRQO ABTAKO TXO IDHITO 0 RXERRO TXERRO ACO ACO ACO ACO AMO AMO AMO AMO ACO 45 MC9S12DT256 Device User Guide V03 07 0180 01BF Motorola Scalable CAN MSCAN Address Name Bt7 Bits 2 Bit 0 0199 CANTIDARS aie AC6 5 ACA AC2 AC1 ACO Read 019 CANIIDAR6 AC6 AC5 AC1 ACO Read 019B CANIIDAR7 6 AC5 ACA AC2 AC1 ACO Read 019C CANIIDMR4 AM7 6 AMS AM4 AM2 AMO Read 0190 CANIIDMRS 022 AM7 6 AMS AM4 AM2 AMO Read S019E AM7 AM6 AMS AM3 AM2 AMO Read S019F ame AMS AM4 AM2 AMO 01A0 Read FOREGROUND RECEIVE BUFFER see Table 1 2 CANIRXFG Write 01B0 cANITXFG
21. C1 VDD1 Iter cap ceramic X7R 100 220nF C2 VDD2 Iter cap ceramic X7R 100 220nF VDDA Iter cap ceramic X7R VDDR Iter cap X7R tantalum VDDPLL Iter cap ceramic X7R VDDX Iter cap X7R tantalum OSC load cap OSC load cap PLL loop Iter cap See PLL speci cation chapter PLL loop Iter cap Colpitts mode only if recommended by PE cule quartz manufacturer PLL loop Iter res See PLL Speci cation chapter Pierce mode only Quartz The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself The following rules must be observed Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins C1 C6 Central point of the ground star should be the VSSR pin Use low ohmic low inductance connections between VSS1 VSS2 and VSSR VSSPLL must be directly connected to VSSR Keep traces of VSSPLL EXTAL and XTAL as short as possible and occupied board area for C7 C8 C11 and QI as small as possible Do not place other signals or supplies underneath area occupied by C7 C8 C10 and Q1 and the connection area to the MCU Central power input should be fed in at the VDDA VSSA pins M MOTOROLA 83 MC9S12DT256 Device User Guide V03 07 Figure 20 1 Recommended PCB Layout for 112LQFP Colpitts Oscillator 84 MOTOROLA MC9S12DT256 Device User Guide 03 07 Fi
22. FF8D FF80 to FF8B Port P Interrupt PWM Emergency Shutdown PTPIF PTPIE PWMSDN PWMIE Reserved FFB2 FFB3 CANO receive CANORIER RXFIE B2 FFBO FFB1 CANO transmit CANOTIER TXEIE2 TXEIEO BO FFAE FFAF wake up I Bit CANTRIER WUPIE AE FFAC FFAD errors I Bit CAN1RIER CSCIE OVRIE AC FFAA FFAB receive I Bit RXFIE AA FFA8 FFA9 transmit I Bit CAN1TIER TXEIE2 TXEIEO A8 FFA6 FFA7 4 FFA5 FFA2 FFA3 FFAO FFA1 SFF9E SFFOF Reserved 9 FF9D FF9A FF9B FF98 FF99 FF96 FF97 wake up I Bit WUPIE 96 FF94 FF95 errors I Bit CAN4RIER CSCIE OVRIE 94 FF92 FF93 receive I Bit RXFIE 92 FF90 FF91 transmit I Bit CANATIER TXEIE2 TXEIEO 90 76 MOTOROLA MC9S12DT256 Device User Guide V03 07 5 3 Effects of Reset When a reset occurs MCU registers and control bits are changed to known start up states Refer to the respective module Block User Guides for register reset states 5 3 1 I O pins Refer to the HCS12 Core User Guides for mode dependent pin configuration of port A B E and K out of reset Refer to the PIM Block User Guide for reset configurations of all peripheral module ports NOTE For devices assembled in 80 packages all non bonded out pins should be configured as outputs after
23. Maximum Erase and Programming times are achieved under particular combinations of fyymop and bus frequency fpus Refer to formulae in Sections A 3 1 1 A 3 1 4 for guidance Burst Programming operations are not applicable to EEPROM Minimum Erase times are achieved under maximum NVM operating frequency fyymop Minimum time if first word in the array is not blank Maximum time to complete check on an erased block O MOTOROLA 105 MC9S12DT256 Device User Guide V03 07 A 3 2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification constant process monitors and burn in to screen early life failures The program erase cycle count on the sector is incremented every time a sector or mass erase event is executed Table A 12 NVM Reliability Characteristics Conditions are shown in Table A 4 unless otherwise noted Rating Symbol Min Typ Max unit Flash Reliability Characteristics Data retention after 10 000 program erase cycles at iuncti 15 100 an average junction temperature of T Javg lt 85 C tri RET Years Data retention with 100 program erase cycles at an 2 C 5 20 1002 average junction temperature T lt 85 C slo Number of program erase cycles 15 000 40 C Tj lt 090 np Cycles Number program erase cycles 10 000 3 0 C Ty 140 C 100 099 EEPROM Reliability
24. Three 1M bit per second CAN 2 0 A B software compatible modules Five receive and three transmit buffers Flexible identifier filter programmable as 2 x 32 bit 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Rx Tx error and wake up Low pass filter wake up function Loop back for self test operation Enhanced Capture Timer 16 bit main counter with 7 bit prescaler 8 programmable input capture or output compare channels Four 8 bit or two 16 bit pulse accumulators 8 PWM channels Programmable period and duty cycle 8 61 8 channel or 16 bit 4 channel Separate control for each pulse width and duty cycle Center aligned or left aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Usable as interrupt inputs Serial interfaces Two asynchronous Serial Communications Interfaces SCI Three Synchronous Serial Peripheral Interface SPI Byte Data Link Controller BDLC SAEJI1850 Class Data Communications Network Interface Compatible and ISO Compatible for Low Speed 125 Kbps Serial Data Communications in Automotive Applications Inter IC Bus IIC MOTOROLA MC9S12DT256 Device User Guide 03 07 Compatible with I2C Bus standard Multi master operation Software programmable for one of 256 different serial clock frequencies l12 Pin LQFP package I O lines with 5V input and d
25. 2 RDRJ1 RDRJO 026C PERJ vo PERJ7 PERJ6 PERJ1 PERJO 026D PPSJ wan PPSJ7 PPSJ6 9 PPSJ1 PPSJO 026E PIEJ Head 7 D 9 9 PIEJO Write 026F PIFJ Head gt 9 PIFJ1 PIFJO Write 0270 Wi as oo 027 Reserved Read 0280 502 Motorola Scalable CAN Address Bt4 Bt2 Biti Bit 0 0280 ind LRXACT LSYNCH time WUPE sr pna INITRO 0281 CANACTL1 d CLKSRC Loops LISTEN 0 WUPM SERA 0282 sJw1 SJWO 5 4 BRP3 2 BRP1 BRPO 0283 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 0284 CANA4RFLG e RSTATO 5 ATSTATO Ovai SN 0285 CANARIER NC CSCIE RSTATE1 RSTATEO TSTATE1 TSTATEO OVRIE RXFIE 0286 CANATFLG aA Q TXE2 TXE1 TXEO 0287 he 9 O 2 TXEIE1 TXEIEO 0288 Mc 0 2 ABTRQ1 ABTRQO Read 2 ABTAK1 ABTAK 0289 1989 0 9 Write 028A 9 0 TX2 TXi TXO 028B M IDAM1 IDAMO IDL DIS IDEO 48 MOTOROLA 50280 Address 028C 028D 028E 028F 0
26. 5 2 AC1 ACO AC7 AC6 5 2 AC1 ACO AC7 AC6 5 2 AC1 ACO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO FOREGROUND RECEIVE BUFFER see Table 1 2 FOREGROUND TRANSMIT BUFFER see Table 1 2 49 MC9S12DT256 Device User Guide V03 07 02 0 03FF Reserved space Address Name 80280 served Rea 0 0 Write QN GP A NN 1 7 Part ID Assignments The part ID is located in two 8 bit registers PARTIDH and PARTIDL addresses 001A and 001B after reset The read only value is a unique part ID for each revision of the chip Table 1 3 shows the assigned part ID number Table 1 3 Assigned Part ID Numbers Device Mask Set Number Part ID MC9S12DT256 OL91N 0030 MC9S12DT256 1L91N 0031 MC9S12DT256 3L91N 0032 MC9S12DT256 4L91N 0034 MC9S12DT256 OLO1Y 0033 NOTES 1 The coding is as follows Bit 15 12 Major family identifier Bit 11 8 Minor family identifier Bit 7 4 Major mask set revision number including FAB transfers Bit 3 0 Minor non full mask set revision The device memory sizes are located in two 8 bit registers MEMSIZO and MEMSIZI addresses 001C and 001D after reset Table 1 4 shows the read only values of these registers Refer to section Module Mapping and Control
27. Bit 7 6 5 4 3 2 1 Bit 0 Reserved for RAM Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATD1 Analog to Digital Converter 10 8 Channel Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADPU ETRIGLE ETRIGP ETRIG SCE ssc sac 520 sic FIFO FRZ FRZO SRES8 SMP1 SMPO PRS4 PRS3 PRS2 PRS1 PRSO DJM DSGN SCAN MULT CC CB CA SCF 0 ETORF FIFOR 0 GP CC1 CCO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D 0 55 0 0 0 0 0 0 0 0 CCF7 CCF6 CCF4 CCF3 CCF2 CCF1 CCFO 0 0 0 0 0 0 0 0 41 MC9S12DT256 Device User Guide V03 07 0120 013F ATD1 Analog to Digital Converter 10 Bit 8 Channel Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 50120 ATDiDIEN 180 6 5 4 3 2 1 Bit 0 Write Read 0 0 0 0 0 0 0 0 012E Reserved Write Read 6 5 4 3 2 1 BIT O 012F 1 1924 Write Read Biti 14 13 12 11 10 9 Bit8 0130 ATDiDRou 1924 Bit Write Read Bit6 0 0 0 0 0 0 0131 ead Write Read 14 13 12 11 10 9 Bit8 0132 ATDipRig 19824 Bits Write Read Bit 0 0 0 0 0 0133
28. Maghine Number of Pulse per pin positive 3 negative 3 Minimum input voltage limit 2 5 V Latch up Maximum input voltage limit 7 5 V Table A 3 ESD and Latch Up Protection Characteristics Rating Symbol Min Max Unit Human Body Model HBM TUER 2000 2 C Machine Model MM VMM 200 V C Charge Device Model CDM 500 2 V Latch up Current at 125 C 4 C positive ILAT 100 negative 100 Latch up Current at 27 C 5 C positive li 200 mA negative 200 92 MOTOROLA MC9S12DT256 Device User Guide V03 07 A 1 7 Operating Conditions This chapter describes the operating conditions of the device Unless otherwise noted those conditions apply to all the following data NOTE Please refer to the temperature rating of the device C V M with regards to the ambient temperature T4 and the junction temperature For power dissipation calculations refer to Section A 1 8 Power Dissipation and Thermal Characteristics Table A 4 Operating Conditions Rating Symbol Min Typ Max Unit Regulator and Analog Supply Voltage Vpps 4 5 5 5 25 V Digital Logic Supply Voltage 2 35 2 5 2 75 V PLL Supply Voltage VppPLL 2 35 2 5 2 75 V Voltage Difference VDDX to VDDR and VDDA 0 1 0 0 1 V Voltage Difference VSSX to VSSR and VSSA Avssx 0 1 0 0 1 V Oscillator fosc 0 5 16 MHz Bus Frequency fous 0 5 25 MHz MC9S12DT256C Operat
29. NEN 57 2 3 6 BKGD Background Debug Tag High and Mode Pin 57 2 3 7 PAD15 15 ETRIG1 Port AD Input Pin of ATD1 57 2 3 8 PAD 14 08 AN 14 08 Port AD Input Pins of ATD1 57 2 3 9 AN07 ETRIGO Port AD Input Pin of 58 2 3 10 PAD 06 00 AN 06 00 Port AD Input Pins of 58 2 311 PA 7 0 ADDR 15 8 DATA 15 8 Port A I O Pins 58 2 3 12 PB 7 0 ADDR 7 0 DATA 7 0 Port B I O Pins 58 2 3 13 7 5 7 58 2 314 6 MODB IPIPE1 Port 60 2 3 15 5 1 0 5 60 2 3 16 PE4 ECLK Port E VO PIN 4 lt 60 2 317 PE3 LSTRB TAGLO Port E VO Pin3 7 3 60 2 318 R W EWO PIN NV 2 61 2 319 PE1 IRQ Port E Input Pin 1 gt 61 2 3 20 XIRQ Port E Input Pin0 61 MOTOROLA 5 MC9S12DT256 Device User Guide V03 07 2 3 21 2 3 22 2 3 23 2 3 24 2 3 25 2 3 26 2 3 27 2 3 28 2 3 29 2 3 30 2 3 31 2 3 32 2 3 33 2 3 34 2 3 35 2 3 36 2 3 37
30. can be configured as slave select pin SS of the Serial Peripheral Interface 2 SPI2 2 3 44 PP5 KWP5 PWM5 MOSI2 Port P I O Pin 5 PP5 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 5 output It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 2 SPI2 2 3 45 4 PWM4 MISO2 Port P I O Pin 4 PP4 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 4 output It can be configured as master input during master mode or slave output during slave mode pin MISO of the Serial Peripheral Interface 2 SPI2 2 3 46 PP3 KWP3 PWM3 551 Port P I O Pin PP3 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP WAIT mode It can be configured as Pulse Width Modulator PWM channel 3 output It can be configured as slave select pin SS of the Serial Peripheral Interface 1 SPI1 64 MOTOROLA MC9S12DT256 Device User Guide V03 07 2 3 47 2 KWP2 PWM 2 SCK1 Port P I O Pin 2 PP2 is a general purpose input or output pin It can be configured to generate an interrupt ca
31. sy PLLON AUTO PRE PCE SCME Read 0 003B RTR6 RTR5 RTR4 RTR3 RTR2 RTRO 008C COPCTL NS wcoP 0 CR2 CRO 30 MOTOROLA 50034 003F Address 003D 003E 003F Name FORBYP TEST ONLY CTCTL TEST ONLY ARMCOP 0040 007F Address 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 004A 004B 004C 004D 004E 004F 0050 0051 0052 M MOTOROLA Name TIOS CFORC OC7M OC7D TCNT hi TCNT lo TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 TCO hi TCO lo TC1 hi Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S12DT256 Device User Guide 03 07 CRG Clock and Reset Generator Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 RTIBYP COPBYP PLLBYP FCM ICTL7 TCTL6 TCTL5 TCTL4 TCLT3 TCTL2 TCTL1 TCTLO 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 ECT Enhanced
32. t oo CN amp gt gt lt gt gt amp lt lt S m u co 9 anco 2 3 Gaonmunmnmt ts a e ra lt lt 3 Figure 2 2 Pin Assignments in 80 pin QFP for MC9S12DJ256 2 2 Signal Properties Summary Table 2 1summarizes the pin functionality Signals shown in bold are not available in the 80 pin package Table 2 1 Signal Properties M MOTOROLA 53 MC9S12DT256 Device User Guide V03 07 Internal Pull Pin Pin Name Pin Pin Pin Power Resistor Description Funct 1 Funct 2 Funct 3 Funct 4 Funct 5 Supply Reset PIRE State VDDPLL Oscillator Pins VDDR External Reset N A Test Input VREGEN VDDX Voltage Regulator Enable Input XFC VDDPLL PLL Loop Filter Background Debug Tag High Mode Input Port AD Input Analog Input AN7 of ATD1 External Trigger Input of ATD1 BKGD VDDR PAD 15 1 7 ETRIG1 VDDA Port AD Inputs Analog Inputs PAD 14 8 AN1 6 0 VDDA AN 6 0 of ATD1 Port AD Input Analog Input AN7 of ANO 7 ETRIGO VDDA ATDO External Trigger Input of ATDO Port AD Inputs Analog Inputs PAD 6 0 ANO 6 0 VDDA ANI6 0 of ADDR 15 8 PA 7 0 DATA 15 8 VDDR Disabled Port I O Multiplexed Addre
33. 00 AN 06 00 Port AD Input Pins of PAD06 PADOO are general purpose input pins and analog inputs AN 6 0 of the analog to digital converter ATDO 2 3 11 PA 7 0 ADDR 15 8 DATA 15 8 Port A I O Pins PA7 PAO are general purpose input or output pins In MCU expanded modes of operation these pins used for the multiplexed external address and data bus 2 3 12 PB 7 0 ADDR 7 0 DATA 7 0 Port B I O Pins PB7 PBO are general purpose input or output pins In MCU expanded modes of operation these pins are used for the multiplexed external address and data bus 2 3 13 PE7 NOACC XCLKS Port E I O Pin 7 PE7 is a general purpose input or output pin During MCU expanded modes of operation the NOACC signal when enabled is used to indicate that the current bus cycle is an unused or free cycle This signal will assert when the CPU is not using the bus The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts low power oscillator is used or whether Pierce oscillator external clock circuitry is used The state of this pin is latched at the rising edge of RESET If the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator If input is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL Since this pin is an input with a pull up device during reset if the pin is left floating the default con
34. 10 9 Bit 8 Write Read 6 5 4 3 2 1 Bit 0 29 MC9S12DT256 Device User Guide V03 07 0028 002F BKP Core User Guide Address Name Bite 5 Bt2 Bit 0 002D BKP1X anne BK1V5 BK1V3 2 BKiV1 BK1VO 002E BkPiH 192 Bit as 14 13 12 11 10 9 Bit 8 Write 002F Read 6 5 4 3 2 1 Bit 0 Write 0030 0031 MMC map 4 of 4 Core User Guide Address Name 2 Bit 0 0030 PPAGE ae E C PIX5 PIX4 PIX Read 0031 Reserved 9 Write 0032 0033 MEBI map 3 of 3 Core User Guide Address Write Write 0034 003F CRG Clock and Reset Generator Address Bite Bt5s Bt2 Bit 0 0034 SYNR M SYN5 SYN4 SYN3 SYN2 SYN1 SYNO 0035 REFDV REFDV3 REFDV2 REFDV1 5195 CTFLG Read TOUT7 TOUT6 TOUTS TOUT4 TOUT3 TOUT2 TOUTI TOUTO TEST ONLY Write 0037 CRGFLG RTIF PROF LOORI QUOS SCMIF 50038 craint 192 gm 0 LOCKIE e SCMIE 2 Write 0039 CLKSEL es PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI Read 0 PLLCTL
35. ITCR 0016 ITEST 0017 0017 Address Name 0017 Reserved 0018 001B Address Name 0018 Reserved 0019 Reserved 001A PARTIDH 001B PARTIDL 001C 001D Address Name 001C MEMSIZO 001D MEMSIZ1 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MMC map 1 of 4 Core User Guide Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EE15 EE14 EE13 EE12 EE11 9 2 9 D d EXSTR1 EXSTR0 ROMHM ROMON 0 0 0 0 0 0 0 0 INT map 1 of 2 Core User Guide Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Q WRINT ADR3 ADR ADR1 ADRO INTE INTC INTA INT8 INT6 4 2 INTO MMC map 2 of 4 Core User Guide Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 Miscellaneous Peripherals Device User Guide Table 1 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 IDO MMC map 3 of 4 Core and Device User Guide Table 1 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 reg swO 0 sw1 eep_sw0 0 ram sw2 ram sw1 ram swO sw1 rom
36. Modes Inits Test 24 0018 0019 Reserved 2 001A 001B Device ID register PARTID 2 001C 001F CORE MEMSIZ IRQ HPRIO 4 0020 0027 Reserved 8 0028 002F CORE Background Debug Mode 8 0030 0033 CORE PPAGE Port K 4 0034 003F Clock and Reset Generator PLL RTI COP 12 0040 007F Enhanced Capture Timer 16 bit 8 channels 64 0080 009F Analog to Digital Converter 10 bit 8 channels ATDO 32 00A0 00C7 Pulse Width Modulator 8 bit 8 channels PWM 40 00C8 00CF Serial Communications Interface SCIO 8 0000 0007 Serial Communications Interface SCI1 8 50008 00DF Serial Peripheral Interface SPIO 8 00 0 00E7 Inter IC Bus 8 00E8 00EF Byte Data Link Controller BDLC 8 00FO0 00F7 Serial Peripheral Interface SP11 8 00F8 00FF Serial Peripheral Interface SP12 8 0100 010F Flash Control Register 16 0110 011B EEPROM Control Register 12 011C 011F Reserved 4 0120 013F Analog to Digital Converter 10 bit 8 channels ATD1 32 0140 017F Motorola Scalable Can CANO 64 0180 01BF Motorola Scalable Can 64 01C0 01FF Reserved 64 0200 023F Reserved 64 0240 027F Port Integration Module PIM 64 0280 502 Motorola Scalable Can 64 02C0 03FF Reserved 320 0000 OFFF EEPROM array 4096 MOTOROLA MOTOROLA MC9S12DT256 Device User Guide 03 07 Table 1 1 Devic
37. The selection of Colpitts oscillator or Pierce oscillator external clock depends on the XCLKS signal which is sampled during reset By asserting the XCLKS input during reset this oscillator can be bypassed allowing the input of a square wave Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power on STOP or oscillator fail specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected The quality check also determines the minimum oscillator start up time typosc The device also features a clock monitor A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA Table A 15 Oscillator Characteristics Conditions are shown in Table A 4 unless otherwise noted Numjc Symbol Mn Crystal oscillator range Colpitts 0 5 Crystal oscillator range Pierce 10 0 5 Startup Current Oscillator start up time Colpitts Clock Quality check time out Clock Monitor Failure Assert Frequency External square wave input frequency 4 External square wave pulse width low E P C D P P D D External square wave pulse width high External square wave rise time External square wave fall time Input Capacitance EXTAL XTAL pins C IN DC Operating Bias in Colpitts Con
38. VSS is used for VSS1 VSS2 and VSSPLL IDD is used for the sum of the currents flowing into VDDI and VDD2 A 1 3 Pins There are four groups of functional pins A 1 3 1 5V I O pins Those I O pins have a nominal level of 5V This class of pins is comprised of all port I O pins the analog inputs BKGD and the RESET pins The internal structure of all those pins is identical however some of the functionality may be disabled E g for the analog inputs the output drivers pull up and pull down resistors are disabled permanently A 1 3 2 Analog Reference This group is made up by the VRH and VRL pins A 1 3 3 Oscillator The pins XFC EXTAL XTAL dedicated to the oscillator have a nominal 2 5V level They are supplied by VDDPLL A 1 3 4 TEST This pin is used for production testing only A 1 3 5 VREGEN This pin is used to enable the on chip voltage regulator 90 MOTOROLA A 1 4 Current Injection Power supply must maintain regulation within operating Vpps or Vpp range during instantaneous and MC9S12DT256 Device User Guide V03 07 operating maximum current conditions If positive injection current Vi gt Vpps is greater than Ipps the injection current may flow out of VDD5 and could result in external power supply going out of regulation Ensure external VDD5 load will shunt current greater than maximum injection current This will be the greatest risk when the MCU is not consuming power e g if no system clock is present
39. device or operating conditions are less than worst case or leakage induced error is acceptable larger values of source resistance is allowed A 2 2 2 Source Capacitance When sampling an additional internal capacitor is switched to the input This can cause a voltage drop due to charge sharing with the external and the pin capacitance For a maximum sampling error of the input voltage 1LSB then the external filter capacitor 2 1024 Cyyg A 2 2 3 Current Injection There are two cases to consider 1 Acurrent is injected into the channel being converted The channel being stressed has conversion values of 3FF FF in 8 bit mode for analog inputs greater than and 000 for values less than unless the current is higher than specified as disruptive condition 2 Current is injected into pins in the neighborhood of the channel being converted A portion of this current is picked up by the channel coupling ratio K This additional current impacts the accuracy of the conversion depending on the source resistance The additional input voltage error on the converted channel can be calculated as K Rg With being the sum of the currents injected into the two pins adjacent to the converted channel Table A 9 ATD Electrical Characteristics Conditions are shown in Table A 4 unless otherwise noted Num Rating Symbol Min Typ Max Unit 1 input Source Resistance R
40. gur ation on V EXTAL Pin NOTES 1 Depending on the crystal a damping series resistor might be necessary 2 fos 4MHz C 22 3 Maximum value is for extreme cases using high Q low frequency crystals 4 XCLKS 0 during reset 2 3 4 5 6 7 8 9 10 11 112 MOTOROLA MC9S12DT256 Device User Guide V03 07 A 5 3 Phase Locked Loop The oscillator provides the reference clock for the PLL The PLL s Voltage Controlled Oscillator is also the system clock source in self clock mode 5 3 1 Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics VDDPLL Phase VCO fosc 1 fref refdv 1 Detector fomp Loop Divider Figure A 3 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for and i from Table A 16 The grey boxes show the calculation for fyco 50MHz and IMHz E g these frequencies used for fosc 4MHz and a 25MHz bus clock The VCO Gain at the desired VCO frequency is approximated by fi fuco 60 50 Ky K e 7 5 100 9 99 48MHz V The phase detector relationship is given by Ko 316 7Hz Q ich 15 the current in tracking mode M MOTOROLA 113 MC9S12DT256 Device User Guide V03 07 The loop bandwidth fc sho
41. mmm mmm B0q0gq0g0000 lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt aou Multiplexed X Z 22 222524532 Bqgqgggh600 l a ae Re Multiplexed z 2398 x i oc 4444444 Internal Logic 2 5V Driver 5V VDD1 2 VDDX VSS1 2 VSSX L i A D Converter 5V amp PLL 2 5V Voltage Regulator Reference VDDPLL VDDA VSSPLL VSSA 4 Voltage Regulator 5V amp VDDR VSSR MOTOROLA ATDO Enhanced Capture VRH VRL VDDA VSSA Timer BDLC RXB 11850 1 4 ATD1 VRH VRL VDDA VSSA XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19 Signals shown in Bold are not available on the 80 Pin Package 23 MC9S12DT256 Device User Guide V03 07 1 5 Device Memory Map Table 1 1 and Figure 1 2 show the device memory map of the MC9S12DT256 after reset Note that after reset the bottom 1k of the EEPROM 0000 03FF are hidden by the register space 24 Table 1 1 Device Memory Map Address Module Bytes 0000 0017 CORE Ports A B E
42. or if clock rate is very low which would reduce overall power consumption A 1 5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only A functional operation under or outside those maxima is not guaranteed Stress beyond those limits may affect the reliability or cause permanent damage of the device This device contains circuitry protecting against damage due to high static voltage or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level e g either Vgg5 or Vpps Table A 1 Absolute Maximum Ratings 2 Digital Logic Supply Voltage 2 V 3 Supply Voltage 2 VDDPLL V 4 Voltage difference VDDX to VDDR and VDDA V 5 Voltage difference VSSX to VSSR and VSSA 6 Digital Input Voltage 6 0 V 7 Analog Reference 6 0 V 8 XFC EXTAL XTAL inputs 3 0 V 9 TEST input 10 0 V 10 Instant ngo s Maximum 425 mA Single pin limit for all digital I O pins Instantaneous Maximum Current 11 AE 4 25 mA Single pin limit for XFC EXTAL XTAL Instantaneous Maximum Current 12 Ny 0 mA Single pin limit for TEST 13 Storage Temperature Range stg 65 155 C NOTES 1 Beyond absolute maximum ratings device might be damaged M MOTOROLA 9
43. pin It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 0 SPIO 2 3 53 PS4 5 0 Port S I O Pin 4 PS4 is a general purpose input or output pin It can be configured as master input during master mode or slave output pin during slave mode MOSI of the Serial Peripheral Interface 0 SPIO 2 3 54 PS3 TXD1 Port S I O Pin 3 PS3 is a general purpose input or output pin It can be configured as the transmit pin TXD of Serial Communication Interface 1 SCIL MOTOROLA 65 MC9S12DT256 Device User Guide V03 07 2 3 55 PS2 RXD1 Port S I O Pin 2 PS2 is a general purpose input or output pin It can be configured as the receive pin RXD of Serial Communication Interface 1 SCI1 2 3 56 PS1 TXD0 Port S I O Pin 1 PS1 is a general purpose input or output pin It can be configured as the transmit pin TXD of Serial Communication Interface 0 SCIO 2 3 57 PSO RXD0 Port S I O Pin 0 PSO is a general purpose input or output pin It can be configured as the receive pin RXD of Serial Communication Interface 0 SCIO 2 3 58 PT 7 0 IOC 7 0 Port T I O Pins 7 0 PT7 PTO are general purpose input or output pins They can be configured as input capture or output compare pins IOC7 IOCO of the Enhanced Capture Timer ECT 2 4 Power Supply Pins 951207256 power and ground pins are described below NOTE All VSS
44. pin SCL of the IIC module 2 3 30 PJ6 KWJ6 RXCANA SDA PORT J I O Pin 6 PJ6 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as the receive pin RXCAN for the Motorola Scalable Controller Area Network controller 4 CANA or the serial data pin SDA of the IIC module 2 3 31 PJ 1 0 KWJ 1 0 Port J Pins 1 0 and PJO are general purpose input or output pins They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 32 PK7 ECS ROMONE Port I O Pin 7 PK7 is a general purpose input or output pin During MCU expanded modes of operation this pin is used as the emulation chip select output ECS During MCU normal expanded wide and narrow modes of operation this pin is used to enable the Flash EEPROM memory in the memory map ROMONE At the rising edge of RESET the state of this pin is latched to the ROMON bit 62 MOTOROLA MC9S12DT256 Device User Guide V03 07 2 3 33 PK 5 0 XADDR 19 14 Port K I O Pins 5 0 5 are general purpose input or output pins In MCU expanded modes of operation these pins provide the expanded address XADDR 19 14 for the external bus 2 3 34 PM7 TXCAN4 Port M I O Pin 7 PM7 is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network
45. pins must be connected together in the application 2 4 1 VDDX VSSX Power amp Ground Pins for I O Drivers External power and ground for I O drivers Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible Bypass requirements depend on how heavily the MCU pins are loaded 2 4 2 VDDR VSSR Power amp Ground Pins for I O Drivers amp for Internal Voltage Regulator External power and ground for I O drivers and input to the internal voltage regulator Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible Bypass requirements depend on how heavily the MCU pins are loaded 66 MOTOROLA MC9S12DT256 Device User Guide 03 07 2 4 3 VDD1 VDD2 VSS1 VSS2 Core Power Pins Power is supplied to the MCU through VDD and VSS Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible This 2 5V supply is derived from the internal voltage regulator There is no static load on those pins allowed The internal voltage regulator is turned off if VREGEN is tied to ground NOTE No load allowed except for bypass
46. reset in order to avoid current drawn from floating inputs Refer to Table 2 1 for affected pins 5 3 2 Memory Refer to Table 1 1 for locations of the memories depending on the operating mode after reset The RAM array is not automatically initialized out of reset MOTOROLA 77 MC9S12DT256 Device User Guide V03 07 78 44 MOTOROLA MC9S12DT256 Device User Guide 03 07 Section 6 HCS12 Core Block Description 6 1 CPU12 Block Description Consult the CPU12 Reference Manual for information on the CPU When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock Periods 6 2 HCS12 Module Mapping Control MMC Block Description Consult the MMC Block User Guide for information on the Module Mapping Control Block 6 2 1 Device specific information Reset state 01 Bits EE11 EE15 are writeable once in Normal and Emulation Mode Reset state 00 Register is writeable anytime in all modes 6 3 HCS12 Multiplexed External Bus Interface MEBI Block Description Consult the MEBI Block Guide for information on Multiplexed External Bus Interface 6 3 1 Device specific information PUCR Reset State 90 6 4 HCS12 Interrupt INT Block description Consult the INT Block guide for information on HCS12 Interrupt block 6 5 HCS12 Background Debug BDM Block Description Consult the BDM Block guide for information on HCS12 Background Debug bl
47. swO 0 0 0 0 pag swl swO MOTOROLA 001E 001E Address 001E Name INTCR 001F 001F Address 001F Name HPRIO 0020 0027 Address 0020 0021 0022 0023 0024 0025 0026 0027 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0028 002F Address 0028 0029 002A 002B 002C M MOTOROLA Name BKPCTO BKPCT1 BKPOX BKPOH BKPOL MC9S12DT256 Device User Guide 03 07 MEBI map 2 of 3 Core User Guide Read OS ov 0 Write N INT map 2 2 Core User Guide Read bee PSEL6 PsELS PsEL4 PSEL3 PSEL2 2 Write Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Read O 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 0 Write BKP Core User Guide Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read SKEN BKFULL BKBEM Write BKOMBL BKORWE BKORW BK1RWE BK1RW 5 BKOV4 BKOV2 BKOVO Read Bias 14 13 12 11
48. to the A D to be bypassed independently 85 OV Reference voltages for the analog to digital converter 84 5 0 V M MOTOROLA 67 MC9S12DT256 Device User Guide V03 07 Mnemonic Pin Number 112 pin QFP Nominal Voltage Description VDDPLL 43 2 5V Provides operating voltage and ground for the Phased Locked Loop This allows the supply voltage to the PLL to be 45 OV bypassed independently Internal power and ground generated by internal regulator VREGEN 97 5V Internal Voltage Regulator enable disable 2 4 7 VREGEN On Chip Voltage Regulator Enable Enables the internal 5V to 2 5V voltage regulator If this pin is tied low VDD1 2 and VDDPLL must be supplied externally 68 MOTOROLA MC9S12DT256 Device User Guide 03 07 Section 3 System Clock Description 3 1 Overview The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules Figure 3 1 shows the clock connections from the CRG to all modules Consult the CRG Block User Guide for details on clock generation 512 CORE ATDO 1 SCIO SCI1 1 2 3 4 EXTAL lll CRG oscillator clock XTAL Figure 3 1 Clock Connections MOTOROLA 69 MC9S12DT256 Device User Guide V03 07 70 44 MOTOROLA MC9S12DT256 Device User Guide 03 07 Section 4 Modes of Operation 4 1 Overview Eight possibl
49. to your coding policies for unused interrupts if using a derivative without BDLC Ports The CANO pin functionality TXCANO RXCANO is not available on port PJ7 PJ6 5 3 2 and PMO if using a derivative without CANO CANI pin functionality TXCAN1 is not available on port and PM2 if using a derivative without CANI The pin functionality TXCAN4 RXCANA is not available on port PJ7 PJ6 5 PM7 PM6 5 and if using a derivative without CANO BDLC pin functionality TXB RXB is not available on port and PMO if using a derivative without BDLC Donot write MODRRI and MODRRO bits of Module Routing Register PIM 9DP256 Block Guide if using a derivative without CANO Donot write MODRR3 and MODRR2 bits of Module Routing Register 9DP256 Block Guide if using a derivative without CANA Document References 16 MOTOROLA MC9S12DT256 Device User Guide 03 07 The Device Guide provides information about the MC9S12DT256 device made up of standard HCS12 blocks and the HCS12 processor core This document is part of the customer documentation A complete set of device manuals also includes the HCS12 Core User Guide and all the individual Block Guides of the implemented modules In a effort to reduce redundancy all module specific information is located only in the respective Block Guide If applicable spe
50. valid if the device is powered externally After releasing the POR reset the oscillator and the clock quality check are started If after a time valid oscillation is detected the MCU will start using the internal self clock The fastest startup time possible is given by Nypose A 5 1 2 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU preventing the CPU from executing code when VDDS is out of specification limits the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set A 5 1 3 External Reset When external reset is asserted for a time greater than the CRG module generates an internal reset and the CPU starts fetching the reset vector without doing a clock quality check if there was an oscillation before reset A 5 1 4 Stop Recovery Out of STOP the controller can be woken up by an external interrupt A clock quality check as after POR is performed before releasing the clocks to the system MOTOROLA 111 MC9S12DT256 Device User Guide V03 07 A 5 1 5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes The controller can be woken up by internal or external interrupts After twrs the CPU starts fetching the interrupt vector A 5 2 Oscillator The device features an internal Colpitts and Pierce oscillator
51. 014F 0150 0153 0154 0157 0158 015B 015C 015F 0160 016F 0170 017F 017F Name CANORFLG CANORIER CANOTFLG CANOTIER CANOTARQ CANOTAAK CANOTBSEL CANOIDAC Reserved Reserved CANORXERR CANOTXERR CANOIDARO CANOIDARS CANOIDMRO CANOIDMR3 CANOIDAR7 CANOIDMR7 CANORXFG CANOTXFG Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S12DT256 Device User Guide V03 07 CANO Motorola Scalable CAN MSCAN Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 WUPIF CSCIF RSTAT1 RSTATO TSTAT1 TSTATO OVRIE RXF WUPIE CSCIE RSTATE1 RSTATEO 1 OVRIE RXFIE 0 9 9 TXE2 TXE1 TXEO 9 0 D 0 TXEIE2 TXEIE1 TXEIEO 9 0 2 9 2 2 ABTRQ1 ABTRQO 0 0 0 0 0 ABTAK2 ABTAK1 ABTAKO 2 2 0 TX2 TX1 TXO 0 0 IDAM1 IDAMO 0 IDHIT2 IDHIT1 IDHITO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXERR7 RXERR6 RXERR4 RXERR2 RXERR1 RXERRO TXERR7 TXERR6 TXERR5 TXE
52. 09F ATDO Analog to Digital Converter 10 Bit 8 Channel Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read ASCIF 0082 ATDOCTL2 Wwe ADPU AFFC ETRIGLE ETRIGP ETRIG ASCIE Read 0 50083 S8C S4C 52 516 FIFO FRZ FRZO 0084 ATDOCTL4 Ne SRES8 SMP1 SMPO PRS4 PRS3 PRS2 PRS1 PRSO Read 0 0085 ATDOCTLS DYM DSGN SCAN MULT CC CB CA 0086 ATDOSTATO ETORF FIFOR Dos SI coo R 50087 Reserved gad 2 Write R 0088 Peedi 0 8 2 0 Write Read 0 0 0 0 0 0 0 0089 ATDOTEST1 2 SC Write R BOOSA Riesen Write Read F7 F F F4 F F2 F1 F arpostan eed 06 cere 5 CC Write R doc Reserved lt gt Write 50080 ArDoDIEN 198 6 5 4 3 2 1 Bit 0 Write Read 0 0 0 0 0 0 0 0 008E Reserved write rite Read 4 2 1 BIT 068 papa Write Read Biti 14 1 12 11 1 Bit 0090 ATDODROH Bad Biti5 14 13 12 1 10 9 Bi Write Read 40085 Write Read 14 1 12 11 1 ongeN Y Write Read Bit7 Bit oggs WW Write Read Bitt 14 1 12 11 1 5009
53. 1 FFDE FFDF Enhanced Capture Timer channel 5 Enhanced Capture Timer channel 6 Enhanced Capture Timer channel 7 Enhanced Capture Timer over o w TIE TSRC2 TOF FFDC FFDD Pulse accumulator A over w PACTL PAOVI FFDA FFDB Pulse accumulator input edge PACTL FFD8 FFD9 SPIO SPOCR 1 SPIE SPTIE SCOCR2 FFD6 FFD7 SCIO I Bit TIE TCIE RIE ILIE D6 SC1CR2 FFD4 FFD5 SC I Bit TIE TCIE RIE ILIE 04 FFD2 FFD3 ATDO I Bit ATDOCTL2 ASCIE D2 75 MC9S12DT256 Device User Guide V03 07 FFDO FFD1 ATD1 I Bit ATD1CTL2 ASCIE DO FFCE FFCF Port J I Bit PTJIF PTJIE CE FFCC FFCD Port H I Bit PTHIF PTHIE CC FFCA FFCB Modulus Down Counter under o w MCCTL MCZI CA FFC8 FFC9 Pulse Accumulator B Over o w PBCTL PBOVI C8 FFC6 FFC7 CRG PLL lock CRGINT LOCKIE FFC4 FFC5 CRG Self Clock Mode CRGINT SCMIE FFC2 FFC3 BDLC DLCBCR1 IE FFCO FFC1 FFBE FFBF FFBC FFBD FFBA FFBB Bus SPI2 EEPROM IBCR IBIE SPIE SPTIE SP2CR1 SPIE SPTIE ECNFG CCIE CBEIE BE BC FFB8 FFB9 FLASH FCNFG CCIE CBEIE FFB6 FFB7 CANO wake up CANORIER WUPIE FFB4 FFB5 CANO errors CANORIER CSCIE OVRIE FF8F FF8C
54. 1 MC9S12DT256 Device User Guide V03 07 2 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I O supply The absolute maximum ratings apply when the device is powered from an external source 3 All digital I O pins are internally clamped to Vssx and Vssa 4 Those pins are internally clamped to and Vpppi 5 This pin is clamped low to but not clamped high This pin must be tied low in applications A 1 6 ESD Protection and Latch up Immunity All ESD testing is in conformity with CDF AEC Q100 Stress test qualification for Automotive Grade Integrated Circuits During the device qualification ESD stresses were performed for the Human Body Model HBM the Machine Model MM and the Charge Device Model A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature unless specified otherwise in the device specification Table A 2 ESD and Latch up Test Conditions Model Description Symbol Value Unit Series Resistance R1 1500 Ohm Storage Capacitance C 100 pF roman Body Number of Pulse per pin positive 3 negative 3 Series Resistance R1 0 Ohm Storage Capacitance C 200 pF
55. 100 120 140 Operating Temperature T C MOTOROLA 107 MC9S12DT256 Device User Guide V03 07 108 44 MOTOROLA A 4 Voltage Regulator MC9S12DT256 Device User Guide 03 07 The on chip voltage regulator is intended to supply the internal logic and oscillator circuits No external DC load is allowed Table A 13 Voltage Regulator Recommended Load Capacitances Rating Symbol Min Typ Max Unit Load Capacitance on VDD1 2 Civpp 220 nF Load Capacitance on VDDPLL CiyDDfcPLL 220 nF MOTOROLA 109 MC9S12DT256 Device User Guide V03 07 110 44 MOTOROLA MC9S12DT256 Device User Guide V03 07 A 5 Reset Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase Locked Loop PLL A 5 1 Startup Table A 14 summarizes several startup characteristics explained in this section Detailed description of the startup behavior can be found in the Clock and Reset Generator CRG Block Guide Table A 14 Startup Characteristics Conditions are shown in Table A 4 unless otherwise noted Rating T POR assert level 0 97 opens rn m Startup from Reset Nose 5 Interrupt pulse width IRQ edge sensitive mode 20 ns 6 Wait recovery startup time 14 A 5 1 1 POR The release level and the assert level are derived from the Vpp Supply They are also
56. 1984 FOREGROUND TRANSMIT BUFFER see Table 1 2 01BF Write 0240 027F PIM Port Integration Module PIM 9DP256 Address Name Bt5 2 Bit 0 0240 PTT 1 PTT6 PTT4 1 PTTO Read PTIT7 6 PTIT4 PTIT3 PTIT2 0241 PTIT 5 Write 0242 DDRT DDRT7 DDRT7 DDRTS DDRT3 DDRT2 DDRT1 0243 RDRT 522 RDRT7 RDRTS RDRT4 RDRT2 RDRT1 RDRTO 0244 PERT HEN PERT7 PERT6 5 PERT4 PERT3 PERT2 PERTO 0245 PPST s PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPSTO Read 0 0 0 0 0 0 0 0 0246 Reserved write rite R 0247 Reserved sai q 2 9 0 Write 0248 PTS a PTS7 PTS6 85 PTS4 PTS3 PTS2 51 PTSO Read PTIS7 PTIS4 PTI PTIS2 PTIS1 Sus ead PTIS S6 S5 S S3 S S 30 Write 024A DDRS M DDRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRSO 024B RDRS AN RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRSO 024C PERS KAS PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERSO 46 MOTOROLA MC9S12DT256 Device User Guide 03 07 0240 027F PIM Port Integration Mod
57. 2 3 38 2 3 39 2 3 40 2 3 41 2 3 42 2 3 43 2 3 44 2 3 45 2 3 46 2 3 47 2 3 48 2 3 49 2 3 50 2 3 51 2 3 52 2 3 53 2 3 54 2 3 55 2 3 56 PH7 KWH7 7 552 Port 7 61 PH6 KWH6 SCK2 Port H I O PiN 6 61 KWH5 MOSI2 H 5 61 PHA KWHA MISO2 Port 2 61 9851 Port H Pin 237 61 PH2 KWH2 SCK1 Port HI OPin2 62 PH1 KWH1 MOSI1 Port H Pin 1 62 PHO KWH0 MISO1 Port 0 62 PJ7 KWJ7 SCL PORT J 7 62 KWJ6 SDA PORT J I O 62 PJ 1 0 KWJ 1 0 Port J I O Pins 1 0 62 7 62 PK 5 0 XADDR 19 14 Port K I O Pins 5 0 63 PM7 TXGAN4 Port M LG Pin 7 63 PM6 RXCAN4 Port 6 63 5 SCKO Port M 5 63 RXCANO RXCAN4 MOSIO
58. 290 0291 0292 0293 0294 0295 0296 0297 0298 0299 029A 029B 029C 029D 029E 029F 02A0 02AF 02B0 02BF 02BF Name Reserved Reserved CAN4RXERR CAN4TXERR CAN4IDARO CAN4IDAR1 CAN4IDAR2 CAN4IDAR3 CAN4IDMRO CANAIDMR1 CANAIDMR2 CAN4IDMR3 CAN4IDAR4 CANAIDAR5 CAN4IDAR6 CAN4IDAR7 CAN4IDMR4 CAN4IDMR5 CAN4IDMR6 CAN4IDMR7 CAN4RXFG CAN4TXFG M MOTOROLA Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S12DT256 Device User Guide 03 07 CAN4 Motorola Scalable CAN MSCAN Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXERR7 RXERR6 RXERR4 RXERR2 RXERR1 RXERRO TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERRO AC7 5 AC4 AC3 AC2 AC1 ACO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO AM7 AM6 AM5 AM4 AM3 AM2 AM1 AMO AC7 AC6
59. 4 ATDODR2H a Bitis 14 13 12 1 10 9 Bi Write Read Bit 0095 ATDODR2L wee k ABitz Bite OO Gm Write Read Biti 14 1 12 11 1 50096 ATDODR3H 14 13 12 1 10 9 Bi Write Read 50097 ATDODR3L Bad 4666 0 _ Write Read Biti 14 1 12 11 1 Bit 0098 ATDODR4H nad Bitis 14 13 12 1 10 9 BIB Write Read Bit 40099 EL __ AN OO lt 0 _ Write Read Biti 14 1 12 11 1 5009 ATDODRSH 34 MOTOROLA 50080 Address 009B 009C 009D 009E 009F 00A0 Address 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AA 00AB 00AC 00AD 00AE 00AF 00BO M MOTOROLA 009F Name ATDODRSL ATDODR6H ATDODR6L ATDODR7H ATDODR7L 00C7 Name PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL PWMTST Test Only PWMPRSC PWMSCLA PWMSCLB PWMSCNTA PWMSCNTB PWMCNT1 PWMCNT2 PWMCNT3 PWMCNT4 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write ATDO Analog to Dig
60. 4 TSR3 TSR2 TSR1 TSRO Write Extended ID Read CANXTIDRO Write Standard ID Read Write Extended ID Read Write Standard ID Read Write Extended ID Read CANXTIDR2 Write Standard ID Read Write Extended ID Read CANXTIDR3 Write Standard ID Read Write 14 5 Read xx1B CANxTDSR7_ Write CANxTDLR dw DLC3 DLC2 xx1D bru PRIO7 PRIO6 PRIO5 4 PRIO2 PRIO1 PRIOO CANxTTSRH 25 TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 xx1F CANxTTSRL d TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSRO xxxD Reserved ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 xx10 ID10 ID9 ID8 ID7 ID6 ID5 04 ID3 ID20 ID19 ID18 SRR 1 IDE 1 017 ID16 ID15 xx10 ID2 ID1 IDO RTR IDE 0 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 xx12 ID6 ID5 104 103 102 101 IDO RTR xx13 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 44 MOTOROLA 50180 Address 0180 0181 0182 0183 0184 0185 0186 0187 0188 0189 018A 018B 018C 018D 018E 018F 0190 0191 0192 0193 0194 0195 0196 0197 0198 01BF Name CAN1CTLO CAN1CTL1 CAN1RFLG CANITIER CAN1TARQ CAN1TAAK CAN1TBSEL CAN1IDAC R
61. 6 Wi E PEYI 86 755 83298787 Http www 100y com tw 126 MOTOROLA MC9S12DT256 Device User Guide 03 07 Appendix B Package Information B 1 General This section provides the physical dimensions of the MC9S12DT256 packages 7 886 3 5753170 Ji JJ 86 21 54151736 WEA FREYI 86 755 83298787 Http www 100y com tw MOTOROLA 127 MC9S12DT256 Device User Guide V03 07 4 7 1 886 3 5753170 86 21 54151736 2 112 LQFP package Http www 100y com tw Soa r u N anes GS 020 X L MORN AUS E r 0 13 L M N SECTION 91 91 1A1 ROTATED 90 COUNTERCLOCKWISE 51 NOTES 1 MENSIONING AND TOLERANCING PER SME Y14 5M 1994 MENSIONS IN MILLIMETERS ATUMS L AND TO BE DETERMINED EATING PLANE DATUM T MENSIONS S AND V TO BE DETERMINED AT EATING PLANE DATUM T MENSIONS A AND B DO NOT INCLUDE 2 3 C0 C9 CO CO C2 22 CJ 4 5 OLD PROTRUSION ALLOWABLE ROTRUSION IS 0 25 PER SIDE DIMENSIONS AND B INCLUDE MOLD MISMATCH DIMENSION D DOES NOT INCLUDE DAMBAR ROTRUSION ALLOWABLE DAMBAR ROTRUSION SHALL NOT CAUSE THE D MENSION TO EXCEED 0 46 lt m gt ODIO SEATING PLANE e 2 co
62. 6 Device User Guide V03 07 551 OUTPUT SCK 0 OUTPUT SCK CPOL 1 OUTPUT MISO INPUT OUTPUT PORT DATA 1 If configured as output MASTER MSB OUT 2 LSBF 0 For LSBF 1 bit order is LSB bit 1 bit 6 MSB MASTER LSB OUT PORT DATA Figure A 7 SPI Master Timing CPHA 1 In Table A 19 the timing characteristics for master mode are listed Table A 19 SPI Master Mode Timing Characteristics Num Characteristic Symbol Unit Min Typ Max 2 Enable Lead Time tlead 1 2 3 Enable Lag Time 1 2 4 Clock SCK High or Low Time twsck 1 2 5 Data Setup Time Inputs tsu 1 0 ns 6 Data Hold Time Inputs thi SOUS ns 9 Data Valid after SCK Edge ns 10 Data Valid after SS fall CPHA 0 luss ns 11 Data Hold Time Outputs tho ns 12 Rise and Fall Time Inputs t ns 13 Rise and Fall Time Outputs ns 886 3 5753170 WEE EFEX 86 21 54151736 WERE JJ HA 3I 86 755 83298787 Http www 100y com tw 120 MOTOROLA MC9S12DT256 Device User Guide 03 07 A 7 2 Slave Mode In Figure A 8 the timing diagram for slave mode with transmission format CPHA 0 is depicted 55 INPUT N lt 1 gt 2 13 3 5 INPUT 2 2 2 12 gt
63. 7 128 Figure 2 80 pin QFP Mechanical Dimensions case 841 129 F 4 886 3 5753170 Ji JJ ETLER 86 21 54151736 WE E PREI 86 755 83298787 Http www 100 com tw MOTOROLA 11 MC9S12DT256 Device User Guide V03 07 886 3 5753170 Ji JJ 86 21 54151736 Ji REDD 86 755 83298787 Http www 100y com tw 12 MOTOROLA MC9S12DT256 Device User Guide 03 07 List of Tables db 886 3 5753170 Table 0 1 Table 0 2 Table 0 3 Table 1 1 Table 1 2 Table 1 3 Table 1 4 Table 2 1 Table 2 2 Table 4 1 Table 4 2 Table 4 3 Table 5 1 Table A 1 Table A 2 Table A 3 Table A 4 Table A 5 Table A 6 Table A 7 Table A 8 Table A 9 Table A 10 Table A 11 Table A 12 Table A 13 Table A 14 Table A 15 Table A 16 Table A 17 Table A 18 Table A 19 Table A 20 JJ 86 21 54151736 ERED Hk GRU 86 755 83298787 Http www 100y com tw Derivative Differences Document References Specification Change Summary for Maskset L91N 17 Device Memory 24 Detailed MSCAN Foreground Receive and Transmit Buffer Layout 43 Assigned Part ID Numbers 50 Memory size registers 2 2 50 Signal
64. 7 TXCAN4 SCL PP7 KWP7 PWM7 SCK2 PS5 MOSIO PS2 RXD1 PS1 TXDO 89 850 00 PM6 RXCAN4 PM7 TXCAN4 95 PS6 SCKO Tow Wwe mom 7 q MC9S12DT256 MC9S12A256 MC9S12DJ256 MC9S12DG256 2B e e eo span gor 20 lt o I 9 C C C C Xr XP XP 5 16 10 10 10 10 16 16 LO XO XO st r f r O G mw m mtem zr Z Z ui lli Ui LL co O u iL lt t Z Z Z Z t Li ti Il D amp Ra amp amp 0 g co r0 7 G x x H amp 8 2 0 n 0 0 5 U S gt gt a c5 Wi E lt lt lt I I I Z O uu cc 1 EEE gt o mI gt lt S G 8 lt x x x 9 EE Z T ETDS gt PAD15 AN15 ETRIG1 PADO7 ANO7 ETRIGO PAD14 AN14 PAD06 AN06 PAD13 AN13 5 PAD12 AN12 PADO4 AN04 PAD11 AN11 PAD10 AN10 PAD02 ANO2 9 9 PADO1 ANO1 PAD08 AN08 0 VSS2 VDD2 PA7 ADDR15 DATA15 PA6 ADDR14 DATA14 PA5 ADDR13 DATA13 PA4 ADDR12 DATA12 PA3 ADDR11 DATA11 PA2 ADDR10 DATA10 PA1 ADDR9 DATA9 PAO ADDR8 DATA8 Signals shown in Bold are not available
65. 9S12 devices manufactured after Q1 of 2004 will be shipped with the 512 LRAE programmed in the Flash Exact details of the changeover 1 e blank to programmed for each product will be communicated in advance via GPCN and will be traceable by the customer via datecode marking on the device Please contact Motorola SPS Sales if you have any additional questions Consult the FTS256K Block User Guide for information about the flash module Section 16 EEPROM 4K Block Description M MOTOROLA 81 MC9S12DT256 Device User Guide V03 07 Consult the EETS4K Block User Guide for information about the EEPROM module Section 17 RAM Block Description This module supports single cycle misaligned word accesses Section 18 MSCAN Block Description There are three MSCAN modules and CANO implemented on the MC9S12DT256 Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module Section 19 Port Integration Module PIM Block Description Consult the PIM_9DP256 Block User Guide for information about the Port Integration Module Section 20 Voltage Regulator VREG Block Description Consult the VREG Block User Guide for information about the dual output linear voltage regulator 7 886 3 5753170 JE EE JJ 86 21 54151736 86 755 83298787 Http www 100y com tw 82 MOTOROLA MC9S12DT256 Device User Guide 03 07 Component Purpose Type Value
66. AN of the Motorola Scalable Controller Area Network controllers 1 or 0 CANO It can be configured as the master input during master mode or slave output pin during slave mode MISO for the Serial Peripheral Interface 0 SPIO M MOTOROLA 63 MC9S12DT256 Device User Guide V03 07 2 3 40 PM1 TXCANO TXB Port I O Pin 1 is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 CANO It can be configured as the transmit pin TXB of the BDLC 2 3 41 RXB Port M I O Pin 0 is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 CANO It can be configured as the receive pin RXB of the BDLC 2 3 42 PP7 KWP7 PWM7 SCK2 Port P I O Pin 7 PP7 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 7 output It can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 SPI2 2 3 43 PP6 KWP6 PWM6 552 Port P I O Pin 6 PP6 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP WAIT mode It can be configured as Pulse Width Modulator PWM channel 6 output It
67. BLANK 0116 ECMD oui 0 __ CMDB6 0 __ 0 Reserved for Read 0 0 0 0 0 0 0 0 50117 Factory Test Write 0118 EADBRHI O O ig 9 Bit 8 Write 40 MOTOROLA 0110 50118 Address 0119 011A 011B 011C Address 011C 011D 011E 011F Name EADDRLO EDATALO 011F Name Reserved Reserved Reserved Reserved 0120 013F Address 0120 0121 0122 0123 0124 0125 0126 0127 0128 0129 012A 012B 012C M MOTOROLA Name ATD1CTLO ATD1CTL1 ATD1CTL2 ATD1CTL3 ATD1CTL4 ATD1CTL5 ATD1STATO Reserved ATD1TESTO ATD1TEST1 Reserved ATD1STAT1 Reserved Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S12DT256 Device User Guide 03 07 EEPROM Control Register eets4k Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8
68. Bit 0 Write 0058 toa 1880 Bit 15 14 13 12 11 10 9 Bit 8 Write 0059 10 Bit Z 6 5 4 3 2 1 Bit 0 Write 005 TC5 h 192 Bit 15 14 13 12 11 10 9 Bit 8 Write 005B Tes 10 6 5 4 3 2 1 Bit 0 Write 005C 162 Bit 15 14 13 12 11 10 9 Bit 8 Write 005D TC6 o 192 6 5 4 3 2 1 Bit 0 Write 005E hi P994 piis 14 13 12 11 10 9 Bit 8 Write 005F f r o 88 6 5 4 3 2 1 Bit 0 Write Read 0 0060 Ane PAEN PAMOD PEDGE CLK1 CLKO 0061 1 9 Write 0062 192 Bit 7 6 5 4 3 2 1 Bit 0 Write 0063 PACN2 192 6 5 4 3 2 1 Bit 0 Write 0064 h 192 Bit 7 6 5 4 3 2 1 Bit 0 Write 0065 PACNO lo 192 6 5 4 3 2 1 Bit 0 Write 0066 1944 mozi RDMCL 2 MCPR1 MCPRO Write ICLAT FLMC EC true Pee 0 0 0 POLF3 POLF2 POLF1 POLFO Write 0068 ICPAR PA2EN PAOEN 0069 59524 00 S lt 0 DLY1 DLYO Write 006A ICOVW i NOVW7 NOVW6 Novws Novw4 Novws NOVW2 Novw1 NOVWO 006B ICSYS S HM SH37 SH26 SH15 5 04 TFMOD BUFEN LATQ 32 MOTOROLA 0040 007F Address 006C 006D 006E 006F 0070 0071 0072 0073 0074 0075 0076 0077 0078
69. C9S12H Family devices MC9S12 DT256 FU Temperature Options Package Option 40 C to 85 C 40 C to 105 C ae Option 40 C to 125 C evice Title Package Options Controller Family FU 80QFP PV 112 LQFP Figure 0 1 Order Partnumber Example MOTOROLA 15 MC9S12DT256 Device User Guide V03 07 The following items should be considered when using a derivative Table 0 1 Registers Do not write or read CANO registers after reset address range 0140 017F if using a derivative without CANO Do not write or read CAN registers after reset address range 0180 01BF if using a derivative without not write or read registers after reset address range 0280 502 if using a derivative without CAN4 Do not write or read BDLC registers after reset address range 00E8 00 if using a derivative without BDLC Interrupts the four CANO interrupt vectors SFFBO FFB7 according to your coding policies for unused interrupts if using a derivative without CANO the four CANI interrupt vectors SFFA8 FFAF according to your coding policies for unused interrupts if using a derivative without CANI the four interrupt vectors SFF90 FF97 according to your coding policies for unused interrupts if using a derivative without CANA the BDLC interrupt vector SFFC2 FFC3 according
70. Capture Timer 16 Bit 8 Channels Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1057 1056 1055 1054 1053 1052 1051 1080 0 0 0 0 0 0 0 0 FOC7 FOC6 FOC5 4 FOC2 FOC1 FOCO OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7MO OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7DO Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 TEN TSWAI TSFRZ TFFCA E 7 TOve TOV5 TOV4 TOV3 TOV2 Tovi TOVO OM7 OL7 6 OL6 OMS OL5 OL4 OM3 OL3 OM2 OL2 OM1 OL1 OMO OLO EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDGOB EDGOA 7 5 C2l 1 Col 0 9 PR2 PR1 PRO C7F C6F C5F C4F C3F C2F COF 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 31 MC9S12DT256 Device User Guide V03 07 0040 007F ECT Enhanced Capture Timer 16 Bit 8 Channels Address Bite 5 Bt2 Bit 0 0053 194 6 5 4 3 2 1 Bit 0 Write 0054 ad Bit 15 14 13 12 11 10 9 Bit 8 Write 0055 10 6 5 4 3 2 1 Bit 0 Write 0056 hi piis 14 13 12 11 10 9 Bit 8 Write 0057 1880 6 5 4 3 2 1
71. Characteristics Data retention after up to 100 000 program erase 5 cycles at an average junction temperature of 15 100 ES TJavg S 85 C tEEPRET Years Data retention with 100 program erase cycles at an 6 iuncti 20 1002 average junction temperature T lt 85 C Number of program erase cycles 7 C 10 000 40 C T lt 090 NOTES Cycles B c Number of program erase cycles x oon p 0 C lt Tj lt 140 C 300 000 1 TJavg will not exeed 85 C considering a typical temperature profile over the lifetime of a consumer industrial or automotive application 2 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de rated to 25 C using the Arrhenius equation For additional information on how Freescale defines Typical Data Retention please refer to Engineering Bulletin EB618 3 Spec table quotes typical endurance evaluated at 25 C for this product family typical endurance at various temperature can be estimated using the graph below For additional information on how Freescale defines Typical Endurance please refer to Engineering Bulletin EB619 106 MOTOROLA MC9S12DT256 Device User Guide V03 07 Figure A 2 Typical Endurance vs Temperature 500 450 400 350 300 250 200 150 Typical Endurance 10 Cycles 100 50 40 20 0 20 40 60 80
72. DOCUMENT NUMBER 9S 12DT256DGV3 D MC9S12DT256 Device User Guide V03 07 Covers also 9512 256 MC9S12DJ256 MC9S12DG256 Original Release Date 24 March 2003 Revised 2 January 2006 Freescale Semiconductor Inc 44 7 886 3 5753170 86 21 54151736 WE 86 755 83298787 Http www 100 com tw 2 freescale semiconductor DOCUMENT NUMBER 9S 12DT256DGV3 D aw M F 7 886 3 5753170 Revision History PLEN 86 21 54151736 WE 45 86 755 83298787 Http www 100y com tw VD dn Rve Author Description of Changes 03 00 24 March Initial version for Maskset 191 based MC9S12DP256B 2003 V02 11 added new HCS12 core documentation 1 30 June added cumulative program erase cycle limitation 2003 to Table A 12 for EEPROM updated Table 0 2 Document References removed cumulative program erase cycle limitation from Table A 12 for EEPROM 03 02 24 July added LRAE generic load and execute info to section 15 03 03 Added MC9S12DT256 QFP 80 to Table 0 1 4 19 March Added Masksets 01 01 and 4L91N 2004 April Changed NVM data retention specification 2005 Table 12 Corrected Flash Burst Programming Time Table 12 Oct A 1 1 V03 06 2005 gt NVM Reliability Spec Table 12 Figure A 2 vo3 07 02Jan Corrected Flash Burst Pr
73. E PLASTIC 215 45 BODY AT THE BOTTOM OF THE PARTING LINE 022 0 38 4 DATUMS B AND D TO BE E 200 240 T DETERMINED AT DATUM PLANE H E 022 038 5 DIMENSIONS S AND n TO BE DETERMINED DATUM HT 6 DIMENSIONS A AND B DO NOT INCLUDE H 025 PLANE R MOLD PROTRUSION ALLOWABLE J 0413 023 PROTRUSION 15 0 25 PER SIDE DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH K 065 0 95 AND ARE DETERMINED AT DATUM PLANE H L 12 35 REF 7 DIMENSION D DOES NOT INCLUDE DAMBAR M 50 105 PROTRUSION ALI LOWABLE DAMBAR NT PROTRUSION SHALL 0 08 TOTAL IN EXCESS OF THE 0 DIMENSION AT MAXIMUM 0 325 BSC BE ne On HE LONER ISU of ele 013 0 30 THE FOOT 1695 1745 T 013 DETAIL C U 0 1695 1745 w 035 045 X 1 6 REF Figure B 2 80 pin QFP Mechanical Dimensions case no 841B MOTOROLA 129 MC9S12DT256 Device User Guide V03 07 F 7 4 886 3 5753170 WERE 86 21 54151736 3 3I 86 755 83298787 Http www 100y com tw 130 MOTOROLA MC9S12DT256 Device User Guide 03 07 User Guide End Sheet 4 4 886 3 5753170 Egg 86 21 54151736 Wi 47 B 3I 86 755 83298787 Http www 100y com tw MOTOROLA 131 F 7 4 886 3 5753170 86 21 54151736 WEED Hi HEH 86 755 83298787 www 100y com tw How to Reach Us Home Page
74. LA MC9S12DT256 Device User Guide 03 07 A 6 MSCAN Table 17 MSCAN Wake up Pulse Characteristics Conditions are shown in Table A 4 unless otherwise noted Num Rating Symbol Min Typ Max Unit 1 MSCAN Wake up dominant pulse Itered 2 us 2 P MSCAN Wake up dominant pulse pass twuP 5 us MOTOROLA 117 MC9S12DT256 Device User Guide V03 07 118 44 MOTOROLA MC9S12DT256 Device User Guide 03 07 SPI This section provides electrical parametrics and ratings for the SPI In Table A 18 the measurement conditions are listed Table A 18 Measurement Conditions Description Value Unit Drive mode full drive mode L it oad capacitance gap 50 pF on all outputs Thresholds for delay 20 80 VDDX y measurement points 7 1 Master Mode In Figure A 6 the timing diagram for master mode with transmission format CPHA 0 is depicted 551 OUTPUT N lt 2 702 13 9 SCK 4 0 OUTPUT 4 SCK Oe CPOL 1 OUTPUT x Nein MSBI b BIT6 1 LSB IN pO 02 BIT6 1 LSBOUT 1 if configured as an output 2 LSBF 0 For LSBF 1 bit order is LSB bit 1 bit 6 MSB Figure A 6 SPI Master Timing CPHA 0 In Figure A 7 the timing diagram for master mode with transmission format 1 is depicted M MOTOROLA 119 MC9S12DT25
75. M allowed Peripheral BDM allowed but bus operations would cause 1 1 0 X 1 bus con icts ust be used 0 0 1 1 1 1 Normal Expanded Wide BDM allowed For further explanation on the modes refer to the Core User Guide Table 4 2 Clock Selection Based on PE7 PE7 XCLKS Description 1 Colpitts Oscillator selected M MOTOROLA 71 MC9S12DT256 Device User Guide V03 07 Table 4 2 Clock Selection Based on PE7 PE7 XCLKS Description Pierce Oscillator external clock selected Table 4 3 Voltage Regulator VREGEN VREGEN Description Internal Voltage Regulator enabled Internal Voltage Regulator disabled VDD1 2 and VDDPLL must be supplied externally with 2 5V 4 3 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents This feature allows Protection of the contents of FLASH Protection of the contents EEPROM Operation in single chip mode Operation from external memory with internal FLASH and EEPROM disabled The user must be reminded that part of the security must lie with the user s code An extreme example would be user s code that dumps the contents of the internal program This code would defeat the purpose of security At the same time the user may also wish to put a back door in the user s program An example of this is the user downloads a key through the SCI which allo
76. MMC of HCS12 Core User Guide for further details Table 1 4 Memory size registers Register name MEMSIZO 25 MEMSIZ1 81 50 MOTOROLA MC9S12DT256 Device User Guide 03 07 Section 2 Signal Description This section describes signals that connect off chip It includes a pinout diagram a table of signal properties and detailed discussion of signals It is built from the signal description sections of the Block User Guides of the individual IP blocks on the device 2 1 Device Pinout The MC9S 12DT256 MC9S 12DJ256 MC9S 12DG256 and MC9S12A256 is available in a 112 pin low profile quad flat pack LQFP and MC9S12DJ256 MC9812DG256 9512 256 is also available in a 80 pin quad flat pack QFP Most pins perform two or more functions as described in the Signal Descriptions Figure 2 1 and Figure 2 2 show the pin assignments MOTOROLA 51 MC9S12DT256 Device User Guide V03 07 52 SST PWMS KWP3 PP3 SCK1 PWM2 KWP2 PP2 MOSI1 PWM1 KWP1 PP1 MISO1 PWMO KWPO PPO XADDR17 PK3 XADDR16 PK2 XADDR15 PK1 XADDR14 PKO IOC1 PT1 IOC2 PT2 IOC3 PT3 VDD1 VSS1 IOC4 PT4 IOC5 PT5 IOC6 PT6 IOC7 PT7 XADDR19 PK5 XADDR18 PK4 KWJ1 PJ1 KWJ0 PJO MODC TAGHI BKGD ADDRO DATAO PBO ADDR1 DATA1 PB1 ADDR2 DATA2 PB2 ADDR3 DATA3 PB3 ADDR4 DATA4 PB4 PK7 ECS VDDX PM2 RXCAN1 RXCANO MISOO PM3 TXCAN1 TXCANO SSO PJ6 KWJ6 RXCAN4 SDA PP4 KWP4 PWM4 MISO2 PP5 KPW5 PWM5 MOSI2 98 PU7 KWJ
77. P3 PPSP2 PPSP1 PPSSO 025E PIEP dw PIEP7 6 PIEP4 PIEP3 PIEP2 PIEP1 PIEPO 025F PIFP E PIFP7 PIFPe 5 PIFP3 PIFP2 PIFP1 PIFPO Read 0260 PTH PTH6 PTHS PTH4 PTH2 PTH1 PTHO Read PTIH7 PTIH6 5 PTIH2 0261 PTIH oat Write 0262 DDRH DDRH7 DDRH7 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 0263 RDRH Judi RDRH7 RDRH6 5 RDRH3 RDRH2 RDRH1 0264 PERH Win PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 0265 PPSH SH PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSHO M MOTOROLA 47 MC9S12DT256 Device User Guide V03 07 0240 027F PIM Port Integration Module PIM_9DP256 Address Bite Bt4 Bt2 Bit 0 0266 PIEH ans PIEH7 PIEH6 PIEHS PIEH4 PIEH2 PIEH1 0267 PIFH Rare PIFH7 PIFH6 PIFHS PIFH2 PIFH1 0268 PTJ Ne PTJ7 PTJ6 Q 9 PTJ1 PTJO M Read PTU6 0 0 0 0 PTIJO Write 026A DDRJ MOn DDRJ7 DDRJ7 9 i DDRJO 50268 RDRJ is RDRJ7 RDRJ6
78. RR3 TXERR2 TXERR1 TXERRO 7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AM7 AM6 AM5 AM4 AM3 AM2 1 AMO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AM7 AM6 5 AM4 AM3 AM2 1 AMO FOREGROUND RECEIVE BUFFER see Table 1 2 FOREGROUND TRANSMIT BUFFER see Table 1 2 Table 1 2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address xxx0 xxx1 Name Extended ID Standard ID CANxRIDRO Extended ID Standard ID MOTOROLA Read Read Write Read Read Write Bit 7 1028 1010 1020 102 6 1027 129 1019 101 5 026 ID8 ID18 IDO Bit 4 025 ID7 SRR 1 RTR Bit 3 1024 106 IDE 1 IDE 0 Bit 2 ID23 ID5 ID17 Bit 1 ID22 104 1016 Bit 0 1021 103 1015 43 MC9S12DT256 Device User Guide V03 07 Table 1 2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Extended ID 1014 ID13 ID12 ID11 ID10 ID9 ID8 ID7 xxx2 Standard ID Read Write Extended ID Read ID6 ID5 ID4 ID3 ID2 ID1 IDO RTR xxx3 Standard ID Read Write xxx4 CANxRDSRO Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO xxxB CANxRDSR7_ Write xxxC CANRxDLR Read DLC3 DLC2 DLC1 DLCO Write Read Write xxxE CANxRTSRH a TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 xxxF CANxRTSRL Read TSR7 TSR6 TSR5 TSR
79. S12 Breakpoint Block Description 80 Section 7 Clock and Reset Generator CRG Block Description 7 1 Device specific information 80 7 1 1 XCLKS NI AMA GMO 80 Section 8 Enhanced Capture Timer ECT Block Description Section 9 Analog to Digital Converter ATD Block Description Section 10 Inter IC Bus IIC Block Description Section 11 Serial Communications Interface Block Description Section 12 Serial Peripheral Interface SPI Block Description Section 13 J1850 BDLC Block Description Section 14 Pulse Width Modulator PWM Block Description Section 15 Flash EEPROM 256K Block Description Section 16 EEPROM 4K Block Description J 886 3 5753170 Section 17 RAM Block Description 86 21 54151736 WERE GI 86 755 83298787 Section 18 MSCAN Block Description Http www 100 com tw Section 19 Port Integration Module PIM Block Description Section 20 Voltage Regulator VREG Block Description 8 MOTOROLA MC9S12DT256 Device User Guide 03 07 Appendix A Electrical Characteristics AAN OGenetak NN ce nated ocd nue cn a ee ee ee 89 A 1 1 Parameter Classification AR eee 89 A 1 2 Bower Supply usos i CO i eem deal e 89 A 1 3 EAST OE ib Cre NN ner irs 90 A 1 4 Current
80. SPI1 ane 3 Port P I O Interrupt Channel 2 of Disabled PWM SCK SPI1 Port P I O Interrupt Channel 1 of Disabled MOSI of SPI1 VEDX Port P I O Interrupt Channel 0 of Disabled PWM MISO2 of SPI1 VDDX Up Port S I O SS of SPIO VDDX Port S I O SCK of SPIO VDDX Port S I O MOSI of SPIO VDDX Port S I O MISO of SPIO VDDX Port S I O TXD of SCI1 VDDX Port S I O RXD of SCI1 VDDX Port S TXD of SCIO PERS PSO RXDO VDDX Up Port S RXD of SCIO PPSS PERT PT 7 0 IOC 7 0 VDDX PPST Disabled Port T I O Timer channels 2 3 Detailed Signal Descriptions 2 3 1 EXTAL XTAL Oscillator Pins EXTAL and XTAL are the crystal driver and external clock pins On reset all the device clocks are derived from the EXTAL input frequency XTAL is the crystal output 2 3 2 RESET External Reset Pin An active low bidirectional control signal it acts as an input to initialize the MCU to a known start up state and an output when an internal MCU function causes a reset 56 MOTOROLA MC9S12DT256 Device User Guide 03 07 2 3 3 TEST Test Pin This input only pin is reserved for test NOTE The TEST pin must be tied to VSS in all applications 2 3 4 VREGEN Voltage Regulator Enable Pin This input only pin enables or disables the on chip voltage regulator 2 3 5 XFC PLL Loop Filter Pin PLL loop filter Please ask your Motorola representative
81. There are two Serial Communications Interfaces and SCIO implemented on the MC9S12DT256 device Consult the SCI Block User Guide for information about each Serial Communications Interface module Section 12 Serial Peripheral Interface SPI Block Description There are three Serial Peripheral Interfaces SPI2 SPI1 and SPIO implemented on MC9S12DT256 Consult the SPI Block User Guide for information about each Serial Peripheral Interface module Section 13 J1850 BDLC Block Description Consult the BDLC Block User Guide for information about the J1850 module Section 14 Pulse Width Modulator PWM Block Description Consult the PWM_8B8C Block User Guide for information about the Pulse Width Modulator module When the PWM _8B8CBlock Guide refers to freeze mode this is equivalent to active mode Section 15 Flash EEPROM 256K Block Description The S12 LRAE is a generic Load RAM and Execute LRAE program which will be programmed into the flash memory of this device during manufacture This LRAE program will provide greater programming flexibility to the end users by allowing the device to be programmed directly using CAN or SCI after it is assembled on the PCB Use of the LRAE program is at the discretion of the end user and if not required it must simply be erased prior to flash programming For more details of the S12 LRAE and its implementation please see the S12 LREA Application Note AN2546 D It is planned that most HC
82. WER 86 21 54151736 HE JJ 7 69 86 755 83298787 Http www 100y com tw MOTOROLA MC9S12DT256 Device User Guide 03 07 A 8 External Bus Timing A timing diagram of the external multiplexed bus is illustrated in Figure A 10 with the actual timing values shown on table Table A 21 All major bus signals are included in the diagram While both a data write and data read cycle are shown only one or the other would occur on a particular bus cycle A 8 1 General Muxed Bus Timing The expanded bus timings are highly dependent on the load conditions The timing parameters shown assume a balanced load across all outputs 4 7 886 3 5753170 86 21 54151736 WERE J 86 755 83298787 Http www 100 com tw MOTOROLA 123 MC9S12DT256 Device User Guide V03 07 lt 1 2 gt lt 3 lt 4 PE4 Addr Data read PA PB Addr Data write PA PB Non Multiplexed Addresses PK5 0 ECS PK7 R W PE2 IPIPOO Figure A 10 General External Bus Timing J 886 3 5753170 WE JJ 86 21 54151736 WE PREY 86 755 83298787 Http www 100y com tw 124 MOTOROLA MC9S12DT256 Device User Guide 03 07 Table A 21 Expanded Bus Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted Num Rating Symbol Min Typ Max U
83. capacitors 2 4 4 VDDA VSSA Power Supply Pins for ATD and VREG VDDA VSSA are the power supply and ground input pins for the voltage regulator and the analog to digital converter It also provides the reference for the internal voltage regulator This allows the supply voltage to the ATD and the reference voltage to be bypassed independently 2 4 5 VRH Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog to digital converter 2 4 6 VDDPLL VSSPLL Power Supply Pins for PLL Provides operating voltage and ground for the Oscillator and the Phased Locked Loop This allows the supply voltage to the Oscillator and PLL to be bypassed independently This 2 5V voltage is generated by the internal voltage regulator NOTE load allowed except for bypass capacitors Table 2 2 MC9S12DP256 Power and Ground Connection Summary Pin Number Nominal Mnemonic Description 112 pin QFP Voltage D Vpp1 2 13 65 2 5V Internal power and ground generated by internal regulator Vss1 2 14 66 OV VppR 41 5 0V External power and ground supply to pin drivers and internal 40 0 voltage regulator Vppx 107 5 0 V External power ground supply to pin drivers Vssx 106 OV VppA 83 5 0V voltage and ground for the analog to digital converters and the reference for the internal voltage regulator Vssa 86 OV allows the supply voltage
84. ce User Guide 9S12DT256DGV3 D V03 07 F 4 886 3 5753170 MEJ 0 86 21 54151736 WE 45 JJ 7 08 86 755 83298787 Http www 100y com tw MOTOROLA MC9S12DT256 Device User Guide 03 07 Table of Contents ME jk J ML OH 886 3 5753170 WE JJ 86 21 54151736 WERE 7 di 86 755 83298787 Http www 100y com tw Section 1 IntroductionMC9S12DT256 TAIN Overview 19 1 2 Features CC CM 19 1 3 Modes 7 IA eee 21 14 BleackDiagrant 97 NIS NT eee 22 1 5 aN NN JU GAN 24 1 6 Detailed OY 27 Par ID Assignments lt 50 Section 2 Signal Description 2 1 Device Pinotti 5 hee ee A ct ht eek 51 2 2 Signal Properties Summary g gt AN 53 23 Detailed Signal Desetiptioris CM Ql eee eh ea AND LL OMe 56 2 3 1 EXTAL XTAL Oscillator Pins 56 2 3 2 RESET External A set PINN 56 2 3 3 TESTS Test Pin aa QW Qs WN nce 57 2 3 4 VREGEN Voltage Regulator Enable 57 2 3 5 PLINLoop Filter Pin
85. cial implementation details of the module are given in the block description sections of this document See Table 0 2 for names and versions of the referenced documents throughout the Device User Guide Table 0 2 Document References User Guide Version Document Order Number CPU12 Reference Manual V04 CPU12RM AD HCS12 Multiplexed External Bus Interface MEBI Block Guide S12MEBIVS3 D HCS12 Module Mapping Control MMC Block Guide 04 S12MMCV4 D HCS102 Interrupt INT Block Guide V01 S121NTV1 D HCS12 Background Debug BDM Block Guide V04 HCS12 Breakpoint BKP Block Guide V01 S12BKPV1 D Clock and Reset Generator CRG Block User Guide V04 Enhanced Capture Timer ECT_16B8C Block User Guide 01 Analog to Digital Converter 10 Bit 8 Channels 10 8 Block User Guide 12ATD10B8CV2 D Inter Bus Block User Guide Asynchronous Serial Interface SCI Block User Guide V02 Serial Peripheral Interface SPI Block User Guide S12SPIV3 D Pulse Width Modulator 8 Bit 8 Channel PWM 8 8 Block User Guide 01 256 Byte Flash 5256 Block User Guide V03 4K Byte EEPROM EETSAK Block User Guide V02 S12EETS4KV2 D Byte Level Data Link Controller J1850 BDLC Block User Guide V01 Motorola Scalable CAN MSCAN Block User Guide Voltage Regulator VREG Block User Guide V01 S12VREGV1 D Port Integration Module PIM_9DP256 Block User Guide Oscillator OSC Block Guide S120SCV2 D
86. controller 4 2 3 35 PM6 RXCAN4 Port M I O Pin 6 PM6 is a general purpose input or output pin It can be configured as the receive pin of the Motorola Scalable Controller Area Network controller 4 2 3 36 5 TXCANA SCKO Port M I O Pin 5 is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 0 or 4 CANO or CANA It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 SPIO 2 3 37 PM4 RXCANO MOSIO Port M I O Pin 4 is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 0 or 4 CANO or It can be configured as the master output during master mode or slave input pin during slave mode MOSI for the Serial Peripheral Interface 0 SPIO 2 3 38 1 TXCANO 550 Port M I O Pin is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 1 or 0 CANI or CANO It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 SPIO 2 3 39 2 RXCAN1 RXCANO MISOO Port M I O Pin 2 PM2 is a general purpose input or output pin It can be configured as the receive pin RXC
87. de select pin during reset The state of this pin is latched to the MODA bit at the rising edge of RESET This pin is shared with the instruction queue tracking signal IPIPEO This pin is an input with a pull down device which is only active when RESET is low 2 3 16 PE4 ECLK Port E I O Pin 4 is a general purpose input or output pin It can be configured to drive the internal bus clock ECLK ECLK can be used as a timing reference 2 3 17 LSTRB TAGLO Port E I O Pin PE3 is a general purpose input or output pin In MCU expanded modes of operation LSTRB can be used for the low byte strobe function to indicate the type of bus access and when instruction tagging is on TAGLO is used to tag the low half of the instruction word being read into the instruction queue 60 MOTOROLA MC9S12DT256 Device User Guide V03 07 2 3 18 PE2 R W Port E I O Pin 2 PE2 is a general purpose input or output pin In MCU expanded modes of operations this pin drives the read write output signal for the external bus It indicates the direction of data on the external bus 2 3 19 PE1 IRQ Port E Input Pin 1 PE is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests This will wake up the MCU from STOP or WAIT mode 2 3 20 PEO XIRQ Port E Input Pin 0 PEO is a general purpose input pin and the non maskable interrupt request input
88. e 2 5 Pierce Oscillator Connections 7 0 59 Figure 2 6 External Clock Connections PE720 60 Figure 3 1 Clock 69 Figure 20 1 Recommended PCB Layout for 112LQFP Colpitts Oscillator 84 Figure 20 2 Recommended PCB Layout for 80QFP Colpitts Oscillator 85 Figure 20 3 Recommended PCB Layout for 112LQFP Pierce Oscillator 86 Figure 20 4 Recommended PCB Layout for 80QFP Pierce Oscillator 87 Figure A 1 ATD Accuracy Definitions 102 Figure A 2 Typical Endurance vs 107 Figure A 3 Basic PLL functional diagram 113 Figure A 4 _ Jitter Definitions NN wast aeee e e a 115 Figure 5 Maximum bus clock jitter approximation 115 Figure 6 SPI Master Timing 0 2 2 2 119 Figure A 7 SPI Master Timing 1 120 Figure A 8 SPI Slave Timing 0 121 Figure 9 SPI Slave Timing 1 122 Figure A 10 General External Bus 0 124 Figure B 1 112 LQFP mechanical dimensions case no 98
89. e Memory Map Address 1000 3FFF Module RAM array Size Bytes 12288 4000 7FFF Fixed Flash EEPROM array incl 0 5K 1K 2K or 4K Protected Sector at start 16384 8000 BFFF C000 FFFF Flash EEPROM Page Window Fixed Flash EEPROM array incl 0 5K 1K 2K or Protected Sector at end and 256 bytes of Vector Space at FF80 FFFF 16384 16384 25 MC9S12DT256 Device User Guide V03 07 Figure 1 2 MC9S12DT256 Memory Map 5400 REGISTERS 0400 Mappable to any 2k Block within the first 32K 4K Bytes EEPROM 1000 Mappable to any 4K Block 12K Bytes RAM Mappable to any 16K and alignable to top or 4000 bottom 16K Fixed Flash Page 3E 62 This is dependant on the state of the ROMHM bit 8000 16K Page Window 16 x 16K Flash EEPROM pages 000 16K Fixed Flash Page 3F 63 lt BDM 4 VECTORS 2220222 920152929294 NORMAL SPECIAL SINGLE CHIP SINGLE CHIP Assuming that a 0 was driven onto port K bit 7 during MCU is reset into normal expanded wide or narrow mode 26 MOTOROLA 1 6 Detailed Register MC9S12DT256 Device User Guide 03 07 The following tables show the detailed register map of the MC9S12DT256 0000 000F Address 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C
90. e modes determine the operating configuration of the MC9S12DT256 Each mode has an associated default memory map and external bus configuration controlled by a further pin Three low power modes exist for the device 4 2 Chip Configuration Summary The operating mode out of reset is determined by the states of the MODC MODB and MODA pins during reset Table 4 1 The MODC MODB and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation The states of the MODC MODB and MODA pins are latched into these bits on the rising edge of the reset signal The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map ROMON mean the Flash is visible in the memory map The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal Table 4 1 Mode Selection BKGD 5 7 MODB MODA ROMCTL Bit Mode Qescription Special Single Chip BDM allowed and ACTIVE BDM is 0 0 0 X 1 allowed in all other modes but a serial command is required to make BDM active 0 1 0 0 1 1 0 Emulation Expanded Narrow allowed 0 1 0 X 0 Special Test Expanded Wide BDM allowed 0 1 0 1 1 1 7 Emulation Expanded Wide allowed 1 0 0 X 1 Normal Single Chip BDM allowed 0 0 1 0 1 1 1 Normal Expanded Narrow BD
91. enabled and disabled must be considered 1 Internal Voltage Regulator disabled Pint pp t ppPLL VpppLL VpDA 2 PIOS gt Ppsow 10 is the sum of all output currents on I O ports associated with VDDX and For is valid V OL outputs driven low DSON OL respectively V V DD5 OH RDSON Io CORN outputs driven high 2 Internal voltage regulator enabled Pint VppR ppA Ippg is current shown in Table 7 and not the overall current flowing into which additionally contains the current flowing into the external loads with output high 2 Pio gt Fpson io 15 the sum of all output currents on I O ports associated with VDDX and VDDR 94 MOTOROLA MC9S12DT256 Device User Guide 03 07 Table A 5 Thermal Package Characteristics Num Rating EA Min Typ Max Unit C W C W Thermal Resistance LQFP 80 double sided PCB Y E with 2 internal planes 41 C W NOTES 1 The values for thermal resistance are achieved by package simulations 2 PC Board according to EIA JEDEC Standard 51 2 3 PC Board according to EIA JEDEC Standard 51 7 A 1 9 I O Characteristics This section describes the characteristics of all 5V I O pins All parameters are not always applicable e g not all pins feature pull up down resistances MOTOROLA 95 MC9S12DT256 D
92. erved Write R 00E6 Reserved gs 0 Write R 00E7 Reserved aan Q lt Write 00E8 00EF BDLC Bytelevel Data Link Controller J1850 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00E8 DLCBCR1 dw IMSG CLKS 2 IE WCM Read 2 11 00E90 Read 0 0 9 4 Write 00EA DLCBCR2 ays SMRST DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFR0 Read 00EB DLCBDR Write 07 D6 D5 D4 D3 02 D1 Do 00EC DLCBARD RxPoL Bo2 BOO 00ED DLCBRSR ee d R5 R4 R3 R2 R1 RO 1910 9 0 9 2 Write Read IDLE o0EF DLcBsTAr eed 0 Write 38 MOTOROLA MC9S12DT256 Device User Guide 03 07 500 0 00F7 Serial Peripheral Interface Address Bite BS Bt2 Bit 0 8000 SPHCR1 us SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0081 SPHCR2 was ma F MODFEN BIDIROE sPISWAI SPCO 00F2 SPHBR Yo SPPR2 SPPR1 sPPRO 2 spri SPRO Read SPIF PTEF MODF 00F3 SRNR LO PK Write R 00F4 Reserved qaw WAI Write 00F5 spipR 1939 6 5 4 3 2 1 Bito Write R 00F6 Reserved HX PPS SS
93. eserved Reserved CAN1RXERR CAN1TXERR CAN1IDARO CAN1IDAR1 CAN1IDAR2 CAN1IDAR3 CAN1IDMRO CAN1IDMR1 CAN1IDMR2 CAN1IDMR3 CAN1IDAR4 M MOTOROLA Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S12DT256 Device User Guide V03 07 Motorola Scalable CAN MSCAN Bit 7 RXFRM CANE SJW1 SAMP WUPIF WUPIE 0 0 RXERR7 TXERR7 AC7 AC7 AC7 AC7 AM7 AM7 AM7 AM7 AC7 Bit 6 RXACT CLKSRC SJWO TSEG22 CSCIF CSCIE 0 0 RXERR6 TXERR6 AC6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 AC6 Bit 5 CSWAI LOOPB BRP5 TSEG21 RSTAT1 RSTATE1 0 RXERR5 TXERR5 AC5 AC5 AC5 AC5 5 5 5 5 5 Bit 4 SYNCH LISTEN BRP4 TSEG20 RSTATO RSTATEO 0 RXERR4 TXERR4 AC4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 AC4 Bit 3 TIME 0 BRP3 TSEG13 TSTAT1 TSTATE1 0 0 RXERRS3 TXERR3 AC3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 AC3 Bit 2 WUPE WUPM BRP2 TSEG12 TSTATO TSTATEO TXE2 TXEIE2 ABTRQ2
94. ete digital I O lines with interrupt and wakeup capability three CAN 2 0 A B software compatible modules MSCAN12 and an Inter IC Bus The MC9S12DT256 has full 16 bit data paths throughout However the external bus can operate in an 8 bit narrow mode so single 8 bit wide memory can be interfaced for lower cost systems The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements 1 2 Features e HCSI2 Core 16 bit HCS12 CPU i Upward compatible with M68HC11 instruction set ii Interrupt stacking and programmer s model identical to M68HC11 iii Instruction queue iv Enhanced indexed addressing Multiplexed External Bus Interface MMC Module Mapping Control Interrupt control Breakpoints Background Debug Mode CRG Low current Colpitts or Pierce oscillator PLL COP watchdog Real time interrupt Clock Monitor 8 bit and 4 bit ports with interrupt functionality Digital filtering M MOTOROLA 19 MC9S12DT256 Device User Guide V03 07 20 Programmable rising or falling edge trigger Memory 256K Flash EEPROM 4K byte EEPROM T 886 3 5753170 WEE tB 86 21 54151736 byte MEJ 86 755 83298787 Two 8 channel Analog to Digital Converters Http www 100y com tw 10 bit resolution External conversion trigger capability
95. evice User Guide V03 07 Table A 6 5V I O Characteristics Conditions are shown in Table A 4 unless otherwise noted Rating Symbol Min Typ Max Unit 1 PJ Input High Voltage Vin 0 65 Vpps V T Input High Voltage VDD5 0 3 V 2 Input Low Voltage Vib k 0 35 Vpps V T Input Low Voltage VSS5 0 3 V 3 Input Hysteresis Vays Input Leakage Current pins in high impedance input 4 P mode lin Vin 9 Vsss Output High Voltage pins output mode 5 C ahs Von V Partial Drive 2 Output High Voltage pins in output mode 6 P Ful Drive 10 X Output Low Voltage pins in output mode V 7 partial Drive IOL 2mA OL Output Low Voltage pins output mode 8 VoL V Full Drive loL 10 Internal Pull Up Device Current 9 tested at V PUL Internal Pull Up Device Current 10 C tested at Min PUH Internal Pull Down Device Current 11 P tested at V Min PDH Internal Pull Down Device Current 12 C tested at V Max PDL 10 1 7 HA 13 D Input Capacitance Cin 6 pF Injection current 14 Single Pin limit lics 2 5 2 5 mA Total Device Limit Sum of all injected currents licp 25 25 15 Port H J P Interrupt Input Pulse Itered tPULSE 3 us 16 P Port H J P Interrupt Input Pulse passed3 tPULSE 10 us NOTES 1 Ma
96. figuration 15 Colpitts oscillator circuit on EXTAL and XTAL 58 MOTOROLA MC9S12DT256 Device User Guide 03 07 Figure 2 4 Colpitts Oscillator Connections PE7 1 Crystal or ceramic resonator VSSPLL Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal Please contact the crystal manufacturer for crystal DC Figure 2 5 Pierce Oscillator Connections 7 0 SF LN Crystal or ceramic resonator Rs can be zero shorted when use with higher frequency crystals Refer to manufacturer s data MOTOROLA 59 MC9S12DT256 Device User Guide V03 07 Figure 2 6 External Clock Connections PE7 0 EXTAL CMOS COMPATIBLE EXTERNAL OSCILLATOR VDDPLL Level MCU XTAL not connected he 7 4 886 3 5753170 Ji JJ 86 21 54151736 HEJ E FREI 86 755 83298787 Http www 100y com tw 2 3 14 PE6 IPIPE1 Port E I O Pin 6 PE6 is a general purpose input or output pin It is used as a MCU operating mode select pin during reset The state of this pin is latched to the MODB bit at the rising edge of RESET This pin is shared with the instruction queue tracking signal IPIPE1 This pin is an input with a pull down device which is only active when RESET is low 2 3 15 5 MODA IPIPEO Port E I O Pin 5 PES is a general purpose input or output pin It is used as a MCU operating mo
97. for the interactive application note to compute PLL loop filter elements Any current leakage on this pin must be avoided XFC MCU d VDDPLL VDDPLL Figure 2 3 PLL Loop Filter Connections 2 3 6 BKGD TAGHI Background Debug Tag High and Mode Pin The BKGD TAGHI MODC pin is used as a pseudo open drain pin for the background debug communication In MCU expanded modes of operation when instruction tagging 15 on an input low on this pin during the falling edge of E clock tags the high half of the instruction word being read into the instruction queue It is used as a MCU operating mode select pin during reset The state of this pin is latched to the MODC bit at the rising edge of RESET This pin has a permanently enabled pull up device 2 3 7 PAD15 15 ETRIG1 Port AD Input Pin of ATD1 15 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD1 It can act as an external trigger input for the ATDI 2 3 8 PAD 14 08 AN 14 08 Port AD Input Pins of ATD1 PAD14 PADOS are general purpose input pins and analog inputs AN 6 0 of the analog to digital converter ATDI M MOTOROLA 57 MC9S12DT256 Device User Guide V03 07 2 3 9 ANO7 ETRIGO Port AD Input Pin of PAD7 is a general purpose input pin and analog input AN7 of the analog to digital converter ATDO It can act as an external trigger input for the ATDO 2 3 10 PAD 06
98. g the MCU to exit STOP or WAIT mode It can be configured as slave select pin SS of the Serial Peripheral Interface 1 5 M MOTOROLA 61 MC9S12DT256 Device User Guide V03 07 2 3 26 2 KWH2 SCK1 H I O Pin 2 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 5 2 3 27 PH1 KWH 1 MOSI1 Port H I O Pin 1 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 1 5 2 3 28 PHO KWHO MISO1 Port H I O Pin 0 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as master input during master mode or slave output during slave mode pin MISO of the Serial Peripheral Interface 1 SPI1 2 3 29 PJ7 KWJ7 SCL PORT J I O Pin 7 PJ7 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as the transmit pin TXCAN for the Motorola Scalable Controller Area Network controller 4 CANA or the serial clock
99. gure 20 2 Recommended PCB Layout for 80QFP Colpitts Oscillator MOTOROLA 85 MC9S12DT256 Device User Guide V03 07 Figure 20 3 Recommended PCB Layout for 112LQFP Pierce Oscillator 86 MOTOROLA MC9S12DT256 Device User Guide 03 07 Figure 20 4 Recommended PCB Layout for 80QFP Pierce Oscillator MOTOROLA 87 MC9S12DT256 Device User Guide V03 07 88 44 MOTOROLA MC9S12DT256 Device User Guide 03 07 Appendix A Electrical Characteristics A 1 General NOTE The electrical characteristics given in this section are preliminary and should be used as a guide only Values cannot be guaranteed by Motorola and are subject to change without notice This supplement contains the most accurate electrical information for the MC9S12DT256 microcontroller available at the time of publication The information should be considered PRELIMINARY and is subject to change This introduction is intended to give an overview on several common topics like power supply current injection etc A 1 1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate NOTE This classification is shown in the column labeled in the parameter tables where appropriate Those parameters a
100. h Control Register fts256k Http www 100 com tw Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0104 FPROT 1 FPOPEN NV6 FPHDIS FPHS1 FPHSO FPLDIS FPLS1 FPLSO 0105 FSTAT i 0 BLANK 2 2 0106 FCMD 0 __ CMDB6 0 __ 0 Reserved for Read 0 0 0 0 0 0 0 0 0107 Factory Test Write 0108 FADDRH 1844 0 13 12 11 10 9 Bit 8 Write 50109 FADDRLO 168 6 5 4 3 2 1 Bit 0 Write 010A 1984 giras 14 13 12 11 10 9 Bit 8 Write 0108 FDATALO 108 6 5 4 3 2 1 Bit 0 Write R 010C Reserved NL v LM 5 _ Write R 0100 Reserves PaL L O O 0 0 0 0 O Write R 010E Reseved L O O 0 0 O O O Write R 010F Reserved lee PS AMENS SPP ACT RP ONS Write 0110 011B EEPROM Control Register eets4k Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0110 ECLKDIV PRDIV8 5 EDIV4 EDIV2 EDIV1 EDIVO R 0111 Reserved long lt lt L SDN Write Reserved for Read 0 0 0 0 0 0 0 0 80112 H y O n n n oOIE kh Factory Test Write 0113 16984 Q 9 0 0 Write Read NV NV NV4 0114 EPROT rite EPOPEN 5 5 EPDIS 2 EP1 EPO 0115 ESTAT b ECF 0
101. ing Junction Temperature Range 40 100 Operating Ambient Temperature Range 2 40 27 85 C MC9S12DT256V Operating Junction Temperature Range 40 120 Operating Ambient Temperature Range 2 40 27 105 C MC9S12DT256M Operating Junction Temperature Range 40 140 Operating Ambient Temperature Range 2 40 27 125 C NOTES 1 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I O supply The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source 2 Please refer to Section A 1 8 Power Dissipation and Thermal Characteristics for more details about the rela tion between ambient temperature T4 and device junction temperature A 1 8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related The user must assure that the maximum operating junction temperature 15 not exceeded The average chip junction temperature in can be obtained from MOTOROLA 93 MC9S12DT256 Device User Guide V03 07 Tj Junction Temperature C TA Ambient Temperature P D Total Chip Power Dissipation W JA Package Thermal Resistance C W The total power dissipation can be calculated from Pp PiNT PINT Chip Internal Power Dissipation W Two cases with internal voltage regulator
102. ital Converter 10 Bit 8 Channel MC9S12DT256 Device User Guide V03 07 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit7 Bit6 0 0 0 0 0 0 PWM Pulse Width Modulator 8 Bit 8 Channel Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWME7 PWME6 PWME5 PWME4 PWME2 PWME1 PWMEO PPOL7 PPOL6 PPOLS PPOL4 PPOL3 PPOL2 PPOL1 PPOLO PCLK7 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLKO PCKB2 PCKB1 PCKBO PCKA2 PCKA1 PCKAO CAE7 6 5 4 CAE2 CAE1 CAEO CON67 5 CON23 CONO PFRZ 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 35 MC9S12DT256 Device User Guide V03 07 00A0 00C7 PWM Pulse Width Modulator 8 Bit 8 Channel Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read Bit7 6 5 4 3 2 1 Bit 0 00B1
103. nchronous Serial Interface Address Bite 5 Bt2 Bit 0 Read 0 0 0 008 SCIOBDH ro ppp SBRI2 5 11 SBRI0 SBR9 SBRE 50009 SCIOBDL jon SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBRO 00 SCIOCR1 m LOOPS SCISWAI RSRC M WAKE PE PT Read 50068 SCIOCR2 ILIE TE RE RWU SBK Read TDRE T RDRF IDLE R NF FE PF 0083 REL s Write 00CD lilii TXDIR Write R R 00CE SS Ta NL i IA il Write Read 7 R6 R5 R4 R3 R2 R1 RO 00CF SCIDDRL Wie Ts Te m 00DO 00D7 Asynchronous Serial Interface Address Bite BS Bt4 Bt2 Biti Bit 0 Read 0 0 0 50000 SCHBDH SBR11 SBRI0 SBR9 0001 SCHBDL 2 SBR7 SBR6 5885 5884 SBR3 SBR2 SBRI SBRO 0002 8 as LOOPS SCISWAI RSRC M WAKE PE PT Read 0003 SCHCR2 RIE ILIE TE RE RWU SBK Read TDRE RDRF IDLE R NF FE PF CMS Cri gry V ead NT LL Write b Ds lt Asciisma gt ood BRK13 TXDI Write R R ode 42 l A Write Read 7 R6 R5 R4 R3 R2 R1 RO 50007 SCHDRL write T Ts T4 Te 50008
104. nit 1 P Frequency of operation E clock fo 0 25 0 MHz 2 3 Pulse width E low 4 Pulse width E high 5 Address delay time 6 D Address valid time to E rise PWg tap 7 Muxed address hold time Address hold to data valid 10 Read data setup time 11 Read data hold time 12 Write data delay time KAO Si 14 Write data setup time PWey tppw tpsw 15 Address access time t tAp tpsg tacca Non multiplexed address delay time Non muxed address valid to E rise PWg NAD Non multiplexed address hold time Chip select delay time Chip select access time Chip select hold time Read write hold time Low strobe delay time Low strobe valid time to E rise sp Low strobe hold time 31 D NOACC valid time to E rise PWg tNov ns MOTOROLA 125 MC9S12DT256 Device User Guide V03 07 Table A 21 Expanded Bus Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted Cj 50pF Num Rating Symbol Min Typ Max Unit IPIPO 1 0 valid time to E rise IPIPO 1 0 delay time PWg te4y IPIPO 1 0 valid time to E fall NOTES 1 Affected by clock stretch add x ty where 0 1 2 or 3 depending on the number of clock stretches 7 886 3 5753170 T 86 21 5415173
105. nt 2 All modules enabled PLL on Ippw 40 mA P only RTI enabled 5 Pseudo Stop Current RTI and COP disabled 12 C 40 C 370 27 C 400 500 C 70 C 450 NI 85 550 A P C Temp Option 10090 PPPS 600 1600 H C 105 C 650 P Temp Option 120 C 800 2100 C 125 C 850 P M Temp Option 140 C 1200 5000 Pseudo Stop Current RTI and COP enabled 2 C 40 C 570 C 27 C 600 C 70 C 650 8526 PPPS 750 C 105 C 850 C 125 C 1200 C 140 C 1500 Stop Current 2 C 40 C 12 P 27 C 25 100 C 70 G 100 C 85 C 130 Temp Option 100 905 160 1200 H C 105 C 200 P V Temp Option 120 C 350 1700 C 125 C 400 Temp Option 140 C 600 5000 NOTES 1 PLL off 2 At those low power dissipation levels can be assumed 98 MOTOROLA MC9S12DT256 Device User Guide 03 07 A 2 ATD Characteristics This section describes the characteristics of the analog to digital converter 2 1 Operating Characteristics The Table A 8 shows conditions under which the ATD operates The following constraints exist to obtain full scale full range results VssA lt lt Vin lt lt Vppa This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to If the input level goes outside of this range it will effectively be clipped Table A 8 ATD Operating Characteristics Conditions are shown in Table A 4 unless other
106. ock M MOTOROLA 79 MC9S12DT256 Device User Guide V03 07 6 6 HCS12 Breakpoint BKP Block Description Consult the BKP Block guide for information on HCS12 breakpoint block Section 7 Clock and Reset Generator CRG Block Description Consult the CRG Block User Guide for information about the Clock and Reset Generator module 7 1 Device specific information 7 1 4 XCLKS The XCLKS input signal is active low see 2 3 13 PE7 NOACC XCLKS Port E I O Pin 7 Section 8 Enhanced Capture Timer ECT Block Description Consult the ECT 16B8C Block User Guide for information about the Enhanced Capture Timer module When the ECT 16B8C Block Guide refers to freeze mode this is equivalent to active mode Section 9 Analog to Digital Converter ATD Block Description There are two Analog to Digital Converters ATD1 ATDO implemented on the MC9S12DT256 Consult 10B8C Block User Guide for information about each Analog to Digital Converter module When the 10B8C Block Guide refers to freeze mode this is equivalent to active mode Section 10 Inter IC Bus IIC Block Description Consult the Block User Guide for information about the Inter IC Bus module Section 11 Serial Communications Interface SCI Block Description 4 886 3 5753170 WEE 86 21 54151736 WER JJ EREI 86 755 83298787 Http www 100y com tw 80 MOTOROLA MC9S12DT256 Device User Guide 03 07
107. ods N Defining the jitter as N t nom N t nom J N mad x tai N For N lt 100 the following equation is a good fit for the maximum jitter 1 5 10 20 Figure A 5 Maximum bus clock jitter approximation MOTOROLA 115 MC9S12DT256 Device User Guide V03 07 This is very important to notice with respect to timers serial modules where a pre scaler will eliminate the effect of the jitter to a large extent Table A 16 PLL Characteristics Conditions are shown in Table A 4 unless otherwise noted ating 2 VCO locking range 8 50 3 Lock Detector transition from Acquisition to Tracking 3 4 mode 4 Lock Detection 0 1 5 ULT LR o po D M transition from Tracking to Acquisition unt C PLLON Total Stabilization delay Auto Mode tstab 0 5 ms D PLLON Acquisition mode stabilization delay 2 lacq 0 3 ms D PLLON Tracking mode stabilization delay 2 tal 0 2 ms 11 Fitting parameter VCO loop frequency 60 MHz Charge pump current acquisition mode 38 5 uA Charge pump current tracking mode 3 5 epe E ELE EE E 15 Jitter t parameter 20 NOTES 1 96 deviation from target frequency 2 fosc 4MHZ 25MHz equivalent fyco 50MHz REFDV 8403 SYNR 018 Cs 4 7nF Cp 470pF Rs 10KQ 116 MOTORO
108. ogramming Time Table 2006 A 11 Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA MC9S12DT256 Device User Guide 9S12DT256DGV3 D V03 07 F 7 88863 5753170 Ji 86 21 54151736 WERE E PREY 86 755 83298787 Http www 100y com tw MOTOROLA 3 MC9S12DT256 Devi
109. on the 80 Pin Package Figure 2 1 Pin Assignments in 112 pin LQFP MOTOROLA MC9S12DT256 Device User Guide 03 07 CA e 2895 lt zozo z z e e gt lt lt lt lt FON 202090902 gt lt gt gt 2 lt 2 lt gt lt lt cETECEGO 22222206 lt lt lt lt lt lt Ge roo lt 2 lt Z Z x X x lt lt gt gt E r lt u Q co zx 10 qo lico SHH a On 0 2 2 gt Q RQ O OO r t CO LO r rm r r r r r pr rc SS1 PWM3 KWP3 PP3 1 VRH SCK1 PWM2 KWP2 PP2 2 VDDA MOSI1 PWM1 KWP1 PP1 3 PADO7 ANO7 ETRIGO MISO1 PWMO KWPO PPO 4 PAD06 ANO6 OCO PTO 5 5 OC1 PT1 6 PADO4 ANO4 OC2 PT2 7 OC3 PT3 8 2 2 VDD1 PADO1 ANO1 VSS1 MC9S12DJ256 PADOO ANOO OC4 PT4 80 QFP VSS2 OC5 PT5 VDD2 OC6 PT6 PA7 ADDR15 DATA15 OC7 PT7 PA6 ADDR14 DATA14 MODC TAGHI BKGD PA5 ADDR13 DATA13 ADDRO DATAO PBO PA4 ADDR12 DATA12 ADDR1 DATA1 PB1 PA3 ADDR11 DATA11 ADDR2 DATA2 PB2 PA2 ADDR10 DATA10 ADDR3 DATA3 PB3 PA1 ADDR9 DATA9 ADDR4 DATA4 PB4 PAO ADDR8 DATA8 ADDRS DATAS PBS 01 799 N CN CO st LO OR CO O or CN CN CN CN CN CN CN OD Cn C0 orn OW
110. re guaranteed during production testing on each individual device Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted All values shown in the typical column are within this category Those parameters are derived mainly from simulations A 1 2 Power Supply MC9S12DT256 utilizes several pins to supply power to the I O ports A D converter oscillator and PLL as well as the digital core The VDDA VSSA pair supplies the A D converter and the resistor ladder of the internal voltage regulator MOTOROLA 89 MC9S12DT256 Device User Guide V03 07 The VDDX VSSX VDDR and VSSR pairs supply the I O pins VDDR supplies also the internal voltage regulator VDD1 551 VDD2 and VSS2 are the supply pins for the digital logic VDDPLL VSSPLL supply the oscillator and the PLL VSS1 and VSS2 are internally connected by metal VDDA VDDX VDDR as well as VSSA VSSX VSSR are connected by anti parallel diodes for ESD protection NOTE In the following context VDDS is used for either VDDR VDDX VSS5 is used for either VSSA VSSR and VSSX unless otherwise noted 1205 denotes the sum of the currents flowing into VDDX and pins VDD is used for VDD1 VDD2 and VDDPLL
111. rive capability 5V A D converter inputs Operation at 50MHz equivalent to 25MHz Bus Speed Development support Single wire background debug mode On chip hardware breakpoints 1 3 Modes of Operation User modes Normal and Emulation Operating Modes Normal Single Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Operating Modes Special Single Chip Mode with active Background Debug Mode Special Test Mode Motorola use only Special Peripheral Mode Motorola use only Low power modes Stop Mode Pseudo Stop Mode Wait Mode MOTOROLA 21 MC9S12DT256 Device User Guide V03 07 1 4 Block Diagram Figure 1 1 shows a block diagram of the MC9S12DT256 device 22 MOTOROLA MC9S12DT256 Device User Guide 03 07 Figure 1 1 MC9S12DT256 Block Diagram 256K Byte Flash EEPROM 12K Byte RAM 4K Byte EEPROM Voltage Regulator Single wire Background Debug Module XFC VDDPLL Clock and VSSPLL PLE eee Periodic Interrupt EXTAL Module COP Watchdog Clock Monitor Breakpoints xp Es S SUN 1 LSTRB Module PE5 PE6 NOACC XCLKS Multiplexed Address Data Bus 10 x CO QN O nou s QN m 0 O 4 Q i0 S O
112. s 1 KQ Total Input Capacitance 2 T Non Sampling Sampling 3 Disruptive Analog Input Current 4 Coupling Ratio positive current injection 5 Coupling Ratio negative current injection F 4 886 3 5753170 WE JJ 86 21 54151736 B Y GX 9I 86 755 83298787 Http www 100 com tw 100 MOTOROLA MC9S12DT256 Device User Guide 03 07 2 3 accuracy Table A 10 specifies the ATD conversion performance excluding any errors due to current injection input capacitance and source resistance Table A 10 ATD Conversion Performance Conditions are shown in Table A 4 unless otherwise noted 5 12V Resulting to one 8 bit count 20mV and one 10 bit count 5mV 2 0MHz Symba Unit dC 1 2 L D 0 ss 2 10 Bit Differential Nonlinearity NL Counts 3 10 Bit Integral Nonlinearity INL Counts 4 10 Bit Absolute Error AE Counts 5 8 Bit Resolution SB mV INL AE 5 3 7m s ome o onn 8 P 8 Bit Absolute Error 1 5 21 0 1 5 Counts NOTES 1 These values include the quantization error which is inherently 1 2 count for any A D converter OS NER For following definitions see also Figure 1 Differential Non Linearity DNL is defined as the difference between two adjacent switching steps
113. s subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners The ARM POWERED logo is a registered trademark of ARM Limited ARM7TDMI S is a trademark of ARM Limited Java and all other Java based marks are trademarks or registered trademarks of Sun Microsystems Inc in the U S and other countries The Bluetooth trademarks are owned by their proprietor and used by Freescale Semiconductor Inc under license Freescale Semiconductor Inc 2006 All rights reserved 554 e 2 freescale semiconductor
114. signals address and databus will be fully static All peripherals stay active For further power consumption the peripherals can individually turn off their local clocks M MOTOROLA 73 MC9S12DT256 Device User Guide V03 07 4 4 4 Run Although this is not a low power mode unused peripheral modules should not be enabled in order to save power 74 MOTOROLA Section 5 Resets Interrupts 5 1 Overview MC9S12DT256 Device User Guide V03 07 Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and interrupts 5 2 Vectors 5 2 1 Vector Table Table 5 1 lists interrupt sources and vectors in default order of priority Table 5 1 Interrupt Vector Locations FFFA FFFB FFF8 FFF9 COP failure reset Unimplemented instruction trap CCR HPRIO Value Vector Address Interrupt Source Mask Local Enable to Elevate FFFE FFFF Reset None None FFFC FFFD Clock Monitor fail reset None PLLCTL CME SCME COP rate select FFF6 FFF7 SWI None FFF4 FFF5 XIRQ None FFF2 FFF3 IRQ IRQCR IRQEN FFFO FFF1 FFEE FFEF FFED FFEB Real Time Interrupt Enhanced Capture Timer channel 0 Enhanced Capture Timer channel 1 Enhanced Capture Timer channel 2 CRGINT RTIE FFE8 FFE9 Enhanced Capture Timer channel 3 FFE6 FFE7 Enhanced Capture Timer channel 4 FFE4 FFE5 FFE2 FFE3 FFEO FFE
115. ss Data 6 ADDR 7 0 PB 7 0 DATAI7 0 VDDR PUCR Disabled Port I O Multiplexed Address Data PE7 NOACC XCLKS VDDR PUCR Up Port E I O Access Clock Select While RESET IPIPE1 VDDR pin is low Port E I O Pipe Status Mode Input Down While RESET VDDR pin is low Port E I O Pipe Status Mode Input Down Port E Bus Clock Output Port E I O Byte Strobe Tag Low Port E R W in expanded modes Port E Input Maskable Interrupt PEO XIRQ Noe QUT VDDR PUCR Up Port E Input Non Maskable Interrupt VDDR Disabled Port H I O Interrupt SS of SPI2 VDDR Disabled Port H I O Interrupt SCK of SPI2 VDDR Disabled Port H I O Interrupt MOSI of SPI2 54 MOTOROLA MC9S12DT256 Device User Guide 03 07 Internal Pull Pin Pin Name Pin Name Pin Name Pin Name Power Resistor Description Funct 1 Funct 2 Funct 3 Funct 4 Funct 5 Supply Reset CTRL State VDDR Disabled Port H I O Interrupt MISO SPI2 VDDR Disabled Port I O Interrupt SS of SPI1 VDDR Disabled Port H I O Interrupt of SPI1 MOSH VDDR Disabled Port H I O Interrupt MOSI of SPI1 MISO1 VDDR Disabled Port H I O Interrupt MISO of SPI Port J I O Interrupt TX of CAN4 SCL of IIC TX of CANO Port J I O Interrupt RX of CAN4 SDA of IIC RX of CANO TXCAN4 TXCANO VDDX Up PJ6 KWJ6 RXCAN4
116. ternal FLASH and EEPROM Once this program completes the user can erase and program the FLASH security bits to the unsecured state This is generally done through the but the user could also change to expanded mode by writing the mode bits through the BDM and jumping to an external program again through BDM commands Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state the part will be secured again 4 4 Low Power Modes The microcontroller features three main low power modes Consult the respective Block User Guide for information on the module behavior in Stop Pseudo Stop and Wait Mode An important source of information about the clock system is the Clock and Reset Generator User Guide CRG 4 4 1 Stop Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode Wake up from this mode can be done via reset or external interrupts 4 4 2 Pseudo Stop This mode is entered by executing the CPU STOP instruction In this mode the oscillator is still running and the Real Time Interrupt RTI or Watchdog COP sub module can stay active Other peripherals are turned off This mode consumes more current than the full STOP mode but the wake up time from this mode is significantly shorter 4 4 3 Wait This mode is entered by executing the CPU WAI instruction In this mode the CPU will not execute instructions The internal CPU
117. that provides a means of applying asynchronous interrupt requests This will wake up the MCU from STOP or WAIT mode 2 3 21 PH7 KWH7 SS2 Port H I O Pin 7 PH7 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as slave select pin SS of the Serial Peripheral Interface 2 SPD 2 3 22 PH6 KWH6 SCK2 Port H I O Pin 6 PH6 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 SPD 2 3 23 PH5 KWH5 MOSI2 Port H I O Pin 5 is a general purpose input or output pin It can be configured to generate an interrupt causing MCU to exit STOP or WAIT mode It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 2 SPI2 2 3 24 PHA KWH4 MISO2 Port H I O Pin 2 PH4 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as master input during master mode or slave output during slave mode pin MISO of the Serial Peripheral Interface 2 SPI2 2 3 25 PH3 KWH3 551 Port H I O Pin PH3 is a general purpose input or output pin It can be configured to generate an interrupt causin
118. this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employee
119. tions The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively The frequency of this clock must be set within the limits specified as The minimum program and erase times shown in Table A 11 are calculated for maximum fyyyyop and maximum The maximum times are calculated for minimum fyyyop and a fy of 2MHz A 3 1 1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fnymop and be calculated according to the following formula t o 25 l SWPIN 3 1 2 Burst Programming This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst programming by keeping the command pipeline filled The time to program a consecutive word can be calculated as gh t b V PAR fNVMOP one The time to program a whole row is L swpgm 31 tbwpgm Burst programming is more than 2 times faster than single word programming M MOTOROLA 103 MC9S12DT256 Device User Guide V03 07
120. uld be chosen to fulfill the Gardner s stability criteria by at least a factor of 10 typical values are 50 G 0 9 ensures a good transient response 1 Fet lt le 41079 0 9 fc lt 25kHz And finally the frequency relationship is defined as f 2 synr 1 50 ref With the above values the resistance can be calculated The example is shown for a loop bandwidth fo 10kHz 2 50 10 2 316 7 2 9 9 9 10 The capacitance C can now be calculated as 2 _ 2 56 0516 5 19nF 4 7nF Cs fH 20 The capacitance C should be chosen in the range of 20 lt lt 10 470 5 3 2 Jitter Information The basic functionality of the PLL is shown in Figure A 3 With each transition of the clock femp the deviation from the reference clock is measured and input voltage to the VCO is adjusted accordingly The adjustment is done continuously with no abrupt changes in the clock output frequency Noise voltage temperature and other factors cause slight variations in the control loop resulting in a clock jitter This jitter affects the real minimum and maximum clock periods as illustrated in Figure A 4 114 MOTOROLA MC9S12DT256 Device User Guide 03 07 Figure A 4 Jitter Definitions The relative deviation of thom 15 at its maximum for one clock period and decreases towards zero for larger number of clock peri
121. ule PIM_9DP256 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 024D PPSS 1 PPSS7 PPSS6 555 554 PPSS3 PPSS2 PPSS1 PPSSO 024E WOMS e WOMS7 WOMS6 womss WOMS4 womss WOMS2 WOMS1 WOMSO R 024F Reserved ii Q Q 9 0 9 Write 0250 PTM SA 7 6 5 PTM4 PTM3 PTM2 PTM1 PTMO Read PTIM7 6 PTIM5 PTIM4 PTIM3 PTIM2 0251 PTIM Write 0252 DDRM ius DDRM7 DDRM7 5 DDRM4 DDRM3 DDRM2 DDRM1 DDRMO 0253 RDRM Pg RDRM7 RDRM4 RDRM3 RDRM2 RDRM1 RDRMO 0254 PERM AN 7 6 5 PERM2 PERM1 PERMO 0255 PPSM don PPSM7 6 5 PPSM4 PPSM3 PPSM2 PPSM1 PPSMO 0256 WOMM hes WOMM7 WOMM6 5 WOMM4 WOMM3 2 WOMM1 WOMMO 0257 MODRR MG 9 MODRR6 MODRR5 MODRR3 MODRR2 MODRR1 MODRRO 0258 PTP des PTP7 6 5 PTP1 PTPO Read PTIP7 PTIP6 PTIPS PTIP2 0259 PTIP d 0 Write 025A DDRP jas DDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRPO 025B RDRP A RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRPO 025C PERP Aa PERP7 PERP6 5 PERP4 PERP3 PERP2 PERPO 025D PPSP ans PPSP7 PPSP6 5 5 4 PPS
122. using the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 2 output It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 SPIL 2 3 48 PP1 KWP1 MOSI Port P I O Pin 1 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 1 output It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 1 SPI1 2 3 49 KWPO PWMO MISO1 Port P I O Pin 0 PPO is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 0 output It can be configured as master input during master mode or slave output during slave mode pin MISO of the Serial Peripheral Interface 1 SPI1 2 3 50 PS7 550 Port S I O Pin 7 PS6 is a general purpose input or output pin It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 SPIO 2 3 51 PS6 SCK0 Port S I O Pin 6 PS6 is a general purpose input or output pin It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 SPIO 2 3 52 PS5 MOSIO Port S I O Pin 5 PS5 is a general purpose input or output
123. wise noted Num Rating Symbol Min Typ Max Unit Reference Potential 1 Low Var Vssa Vppa 2 V High VppA 2 2 C Differential Reference Voltage 4 50 5 00 5 25 V 3 ATD Clock Frequency faTDCLK 0 5 2 0 MHz ATD 10 Bit Conversion Period 4 D Clock Cycles 10 14 28 Cycles Conv Time at 2 0MHz ATD Clock fATDCLK TcoNv10 7 14 us ATD 8 Bit Conversion Period 5 D Clock Cycles Conv Time at 2 0MHz Clock 6 D Recovery Time 5 0 Volts 7 P Reference Supply current 2 ATD blocks on 8 P Reference Supply current 1 block on NOTES 1 Full accuracy is not guaranteed when differential voltage is less than 4 50V 2 The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks A 2 2 Factors influencing accuracy Three factors source resistance source capacitance and current injection have an influence on the accuracy of the ATD A 2 2 1 Source Resistance Due to the input pin leakage current as specified in Table A 6 in conjunction with the source resistance there will be a voltage drop from the signal source to ATD input The maximum source resistance Rg M MOTOROLA 99 MC9S12DT256 Device User Guide V03 07 specifies results in an error of less than 1 2 LSB 2 5mV at the maximum leakage current If
124. ws access to a programming routine that updates parameters stored in EEPROM 4 3 1 Securing the Microcontroller Once the user has programmed the FLASH and EEPROM if desired the part can be secured by programming the security bits located in the FLASH module These non volatile bits will keep the part secured through resetting the part and through powering down the part The security byte resides in a portion of the Flash array Check the Flash Block User Guide for more details on the security configuration 4 3 2 Operation of the Secured Microcontroller 4 3 2 1 Normal Single Chip Mode This will be the most common usage of the secured part Everything will appear the same as if the part was not secured with the exception of BDM operation The BDM operation will be blocked 72 MOTOROLA MC9S12DT256 Device User Guide 03 07 4 3 2 2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller This is accomplished by resetting directly into expanded mode The internal FLASH and EEPROM will be disabled BDM operations will be blocked 4 3 3 Unsecuring the Microcontroller In order to unsecure the microcontroller the internal FLASH and EEPROM must be erased This can be done through an external program in expanded mode Once the user has erased the FLASH and EEPROM the part can be reset into special single chip mode This invokes a program that verifies the erasure of the in
125. www freescale com E mail support Q freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support Q freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in
126. ximum leakage current occurs at maximum operating temperature Current decreases by approximately one half for each 8 C to 12 C in the temperature range from 50 C to 125 C 2 Refer to Section A 1 4 Current Injection for more details 3 Parameter only applies in STOP or Pseudo STOP mode 96 MOTOROLA MC9S12DT256 Device User Guide V03 07 A 1 10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements A 1 10 1 Measurement Conditions All measurements are without output loads Unless otherwise noted the currents are measured in single chip mode internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode Production testing is performed using a square wave signal at the EXTAL input A 1 10 2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address data and control signals as well as on the duty cycle of those signals No generally applicable numbers can be MOTOROLA 97 MC9S12DT256 Device User Guide V03 07 given A very good estimate is to take the single chip currents and add the currents due to the external loads Table A 7 Supply Current Characteristics Conditions are shown in Table A 4 unless otherwise noted 1 P Run supply currents HA Single Chip Internal regulator enabled Ipps 65 Wait Supply curre

MC9S12DT256 Device User Guide V03.07 Covers also

Contents

Download Pdf Manuals

Related Search

Related Contents