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Xilinx UG230 Spartan-3E Starter Kit Board User Guide

1. NET FX2 IO 27 LOC A16 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IO 28 LOC B16 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IO 29 LOC E13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IO 30 LOC C4 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IO 31 LOC B11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IO 32 LOC All IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IO 33 LOC A8 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IO 34 LOC G9 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IP 35 LOC D12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IP 36 LOC C12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IP 37 LOC A15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IP 38 LOC B15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IO 39 LOC C3 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IP 40 LOC C15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 6 pin header Jl These are shared connections with the FX2 connector NET J1 lt 0 gt LOC B4 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J1 lt 1 gt LOC A4 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 SNET J1 lt 2 gt LOC D5 IOSTANDARD LVTTL
2. NET E MDIO LOC U5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E RX CLK LOC V3 IOSTANDARD LVCMOS33 NET E RX DV LOC V2 IOSTANDARD LVCMOS33 NET E RXD 0 LOC V8 IOSTANDARD LVCMOS33 NET E RXD 1 LOC T11 IOSTANDARD LVCMOS33 NET E RXD 2 LOC U11 IOSTANDARD LVCMOS33 NET E RXD 3 LOC V14 IOSTANDARD LVCMOS33 NET E RXD 4 LOC U14 IOSTANDARD LVCMOS33 NET E TX CLK LOC T7 IOSTANDARD LVCMOS33 NET E TX EN LOC P15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD 0 LOC R11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD 1 LOC T15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD 2 LOC R5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD 3 LOC T5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD 4 LOC R6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 FPGA Configuration Mode INIT B Pins FPGA NET FPGA MO LOC M10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET FPGA M LOC V11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET FPGA M2 LOC T10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET FPGA IN
3. EW SLOW EW SLOW DRIVI DRIVI DRIVI LOW DER DEP pu LEW LEW LEW LEW LEW FAST FAST FAST FAST FAST 164 www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006
4. 0101111 DACD Figure 9 4 SPI Communications Protocol to LTC2624 DAC UG230 c9 04 021806 The FPGA first sends eight dummy or don t care bits followed by a 4 bit command The most commonly used command with the board is COMMANDJ3 0 0011 which immediately updates the selected DAC output with the specified data value Following the command the FPGA selects one or all the DAC output channels via a 4 bit address field Following the address field the FPGA sends a 12 bit unsigned data value that the DAC converts to an analog value on the selected output s Finally four additional dummy or don t care bits pad the 32 bit command word Specifying the DAC Output Voltage As shown in Figure 9 2 each DAC output level is the analog equivalent of a 12 bit unsigned digital value D 11 0 written by the FPGA to the DAC via the SPI interface The voltage on a specific output is generally described in Equation 9 1 The reference voltage VREFERENCH is different between the four DAC outputs Channels A and B use a 3 3V reference voltage and Channels C and D use a 2 5V reference The reference voltages themselves have a 5 tolerance so there will be slight corresponding variances in the output voltage D 11 0 OUT 3096 VREFERENCE Equation 9 1 DAC Outputs A and B Equation 9 2 provides the output voltage equation for DAC out
5. Figure 5 5 Example Custom Checkerboard Character with Character Code 0x03 Command Set Table 5 3 summarizes the available LCD controller commands and bit definitions Because the display is set up for 4 bit operation each 8 bit command is sent as two 4 bit nibbles The upper nibble is transferred first followed by the lower nibble Table 5 3 LCD Character Display Command Set Upper Nibble Lower Nibble Function ml s a r o 398 888 a 3 224 Clear Display 0 0 0 0 0 0 0 0 0 1 Return Cursor Home 0 0 0 0 0 0 0 0 1 Entry Mode Set 0 0 0 0 0 0 0 1 I D S Display On Off 0 0 0 0 0 0 1 D C B Cursor and Display Shift 0 0 0 0 0 1 S C R L 46 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 EZ XILINX LCD Controller Table 5 3 LCD Character Display Command Set Continued o Upper Nibble Lower Nibble Function a n o 0 o 1412242 Function Set 0 0 0 0 1 0 1 0 Set CG RAM Address 0 0 0 1 A5 A4 A3 A2 A1 AO Set DD RAM Address 0 0 1 A6 A5 A4 A3 A2 Al AO Read Busy Flag and Address 0 1 BF A5 A4 A2 Al AO Write Data to CG RAM or DD RAM 1 0 D7 D6 D5 DA D3 D2 D1 DO Read Data from CG RAM or DD RAM 1 1 D7 D6 D5 04 D3 D2 D1 DO Disabled If the LCD_E enable signal
6. 65 Chapter 9 Digital to Analog Converter DAC SPI Communication 67 Interface SIS alS DT 905 68 Disable Other Devices on the SPI Bus to Avoid Contention 68 SPI Communication Details 69 Communication Protocol 69 Specifying the DAC Output Voltage 70 DAC Outputs A and B heu pr eR EG eod e ebd 70 DAC Outputs Cand eene tte entente n Re sasl bad na 70 UCF Location Constraints 71 Related ResourceSs 71 Chapter 10 Analog Capture Circuit Digital Outputs from Analog Inputs 74 Programmable Pre Amplifier 75 Inteface xe tro tete 7 Pea S Gnd qoe Area ace o ee edd 75 Programmable Esya aaa eR eae ee kota bolsa 75 SPI Control Interface ui espe ee ea Hause oe Ah a ER Yu 76 UCF Location Constraints 9 77 Analog to Digital Converter ADC 77 Interfacer oyuna a 77 SPI Control Interface 77 UGF Location Constrain
7. 107 Related ResourceS 107 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 EZ XILINX Chapter 14 10 100 Ethernet Physical Layer Interface Ethernet PHY Connections 110 MicroBlaze Ethernet IP Cores 111 UCF Location Constraints 112 Related Resources 112 Chapter 15 Expansion Connectors Hirose 100 pin FX2 Edge Connector 3 113 Voltage Supplies to the Connector 114 Connector Pinout and FPGA Connections 114 Compatible Board 2 2 eee tee ee eer HP ehe bee tes 116 Mating Receptacle Connectors 116 Differential T O 3133 bet er ES ED cet E x c D e esce eS 116 Using Differential Inputs pasaqa ene e RH RUE is hber de toa es 118 Using Differential Outputs cece n 119 UCF Location Constraints eet ettet nahe Rem hens 119 Six Pin Accessory Headers 121 Header z vow ERR REND ERAS REPE ere RE MERE NUES as 121 2 EG ERA A RR Ea CREER 121 Header e
8. 7 LTC 2624 DAC mm Header JS m ae I i it iA REFB i i i ou i B REF i i ic 2 5V gt i i 0 i i REF D pour i i Spartan 3E FPGA i i sei vosii be LI pene Dac cs CS LD i i i SCK SPI Control Interface i i C i VCC 1 3 3V DAC CLR i alcin i UG230_c9_02_021806 Figure 9 2 Digital to Analog Connection Schematics Interface Signals Table 9 1 lists the interface signals between the FPGA and the DAC The SPI MOSI SPI MISO and SPI SCK signals are shared with other devices on the SPI bus The DAC CS signal is the active Low slave select input to the DAC The DAC CLR signal is the active Low asynchronous reset input to the DAC Table 9 1 DAC Interface Signals Signal FPGA Pin Direction Description SPI MOSI T4 FPGA gt DAC Serial data Master Output Slave Input DAC CS N8 FPGA DAC Active Low chip select Digital to analog conversion starts when signal returns High SPI_SCK U16 FPGA gt DAC Clock DAC_CLR P8 FPGA DAC Asynchronous active Low reset input SPI_MISO N10 FPGA DAC Serial data Master Input Slave Output The serial data output from the DAC is primarily used to cascade multiple DACs This signal can be ignored in most applications although it does demonstrate full duplex communication over the SPI bus Disable Other Devices on the SPI Bus to Avoid Contention The SPI bus signals are shared by other d
9. LED lt 7 gt LOC F9 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 LED lt 6 gt LOC E9 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 ED lt 5 gt LOC D11 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 ED lt 4 gt LOC C11 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 ED lt 3 gt LOC F11 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 ED lt 2 gt LOC E11 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 ED lt 1 gt LOC E12 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 LED lt 0 gt LOC F12 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 Figure 2 11 UCF Constraints for Eight Discrete LEDs Rotary Encoder Interface for Spartan 3E Starter Kit Reference Design http www xilinx com s3estarter 20 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Chapter 3 Clock Sources Overview As shown in Figure 3 1 the Spartan 3E Starter Kit board supports three primary clock input sources all of which are located below the Xilinx logo near the Spartan 3E logo e The board includes an on board 50 MHz clock oscillator e Clocks can be supplied off board via an SMA style connector Alternatively the FPGA can generate clock signals or other high speed signals on the SMA style connector e Optionally install a separate 8 pin DIP style clock oscillator in the supplied socket Bank 0 Oscillator Voltage 8 Pin DIP
10. Spartan 3E Starter Kit Board User Guide www xilinx com 111 UG230 v1 0 March 9 2006 Chapter 14 10 100 Ethernet Physical Layer Interface XILINX The hardvvare evaluation versions of the Ethernet MAC cores operate for approximately eight hours in silicon before timing out To order the full version of the core visit the Xilinx vvebsite at http vvvvvv xilinx com ipcenter processor central processor ip 10 100emac 10 100emac order register htm UCF Location Constraints Figure 14 4 provides the UCF constraints for the 10 100 Ethernet PHY interface including the I O pin assignment and the I O standard used NET E COL LOC U6 IOSTANDARD LVCMOS33 NET E CRS LOC U13 IOSTANDARD LVCMOS33 NET E MDC LOC P9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E MDIO LOC UB IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E RX CLK LOC V3 IOSTANDARD LVCMOS33 NET E RX DV LOC V2 IOSTANDARD LVCMOS33 NET E RXD 0 LOC V8 IOSTANDARD LVCMOS33 NET E RXD 1 LOC T11 IOSTANDARD LVCMOS33 NET E RXD 2 LOC U11 IOSTANDARD LVCMOS33 NET E RXD 3 LOC V14 IOSTANDARD LVCMOS33 NET E RXD 4 LOC U14 IOSTANDARD LVCMOS33 NET E TX CLK LOC T7 IOSTANDARD LVCMOS33 NET E TX EN LOC P15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E_TXD lt 0 gt LOC
11. 9 91 Formatting an SPI Flash PROMFile 92 Downloading the Design to SPI Flash 96 Downloading the SPI Flash using XSPI 96 Download and Install the XSPI Programming Utility 96 Attach a JTAG Parallel Programming Cable 96 Insert Jumper on JP8 and Hold PROG BLow 97 Programming the SPI Flash with the XSPI Softvvare 98 Additional Design Details 99 Shared SPI Bus with Peripherals 99 Other SPI Flash Control Signals 100 Variant Select Pins VS 2 0 erret tasya y ss m etm en 100 Jumper Block 11 os ices eere ER ERR Ee reci ae ge RR 100 Programming Header 12 ese sek e em ne puasa saws 100 Multi Package Layout 100 Related Resources 102 Chapter 13 DDR SDRAM DDR SDRAM Connections 104 UCF Location Constraints 106 Address sr runs ee a ee 106 Dar 0 00000 br 0 106 ae ss ee 107 Reserve FPGA VREFTPins
12. LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE PPPPPPPPHF E PP gt gt gt PS SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW LEW LEW LEW LEW LEW c uuum SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW LOW SLOW un LOW LOW LOW LOW LOW m m uuu UCF Location Constraints for FPGA Connections to CPLD Figure 16 3 provides the UCF constraints for the CPLD including the I O pin assignment and the I O standard used NET XC WDT EN LOC NET XC CMD 1 LOC NET XC CMD 0 LOC NET XC D 2 LOC NET XC D 1 LOC NET XC D 0 LOC NET FPGA M2 LOC NET FPGA M1 LOC NET FPGA MO LOC NET XC CPLD EN LOC NET XC TRIG LOC NET XC DONE LOC NET XC PROG B LOC NET XC GCKO LOC NET GCLK10 LOC NET SPI SCK LOC SF 24 is the same NET SF A 24 LOC NET SF A 23 LOC NET SF A 22 LOC NET SF A 21 LOC NET SF A 20 LOC P16 P30 p29 P36 P34 p33 P8 P6 p5 P42 41 40 p39 p43 p1 p44 as FX2 p23 P22 p2
13. To search the Ansvver Database of silicon softvvare and IP questions and ansvvers or to create a technical support VVebCase see the Xilinx vvebsite at http vvvvvv xilinx com support 10 www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Chapter 1 Introduction and Overoiew Thank you for purchasing the Xilinx Spartan 3E Starter Kit You will find it useful in developing your Spartan 3E FPGA application Choose the Starter Kit Board for Your Needs Depending on specific requirements choose the Xilinx development board that best suits your needs Spartan 3E FPGA Features and Embedded Processing Functions The Spartan 3E Starter Kit board highlights the unique features of the Spartan 3E FPGA family and provides a convenient development board for embedded processing applications The board highlights these features e Spartan 3E specific features Parallel NOR Flash configuration MultiBoot FPGA configuration from Parallel NOR Flash PROM SPI serial Flash configuration e Embedded development MicroBlaze 32 bit embedded RISC processor PicoBlaze 8 bit embedded controller DDR memory interfaces Learning Xilinx FPGA CPLD and ISE Development Software Basics The Spartan 3E Starter Kit board is more advanced and complex compared to other Spartan development boards To learn the basics of Xilinx FPGA or CPLD design and how to use the Xilinx ISE deve
14. e A Hirose 100 pin edge connector with 43 associated FPGA user I O pins including up to 15 differential LVDS I O pairs and two Input only pairs e Three 6 pin Peripheral Module connections e Landing pads for an Agilent or Tektronix connectorless probe Jumper JP9 I O Bank 0 Voltage 4 Default is 3 3V set to 2 5V for differential VO Hirose 100 pin FX2 Connector J3 43 I O connections high performance 3 XILINX SPARTA 3 R J1 6 pin Accessory Header J6 Probe Landing Pads Connectorless logic analyzer probes J2 6 pin Accessory Header J4 6 pin Accessory Header UG230 12 01 030606 Figure 15 1 Expansion Headers Hirose 100 pin FX2 Edge Connector J3 A 100 pin edge connector is located along the right edge of the board see Figure 15 1 This connector is a Hirose FX2 100P 1 27DS header with 1 27 mm pitch Throughout the documentation this connector is called the FX2 connector As shown in Figure 15 2 43 FPGA I O pins interface to the FX2 connector All but five of these pins are true bidirectional I O pins capable of driving or receiving signals Five pins FX2 IP 38 35 and 2 IP 40 are Input only pins on the FPGA These pins are highlighted in light green in Table 15 1 and cannot drive the FX2 connector but can receive signals Spartan 3E Starter Kit Board User Guide www xilinx com 113 UG230 v1 0 March 9 2006 Chapter 15 Expansion Connectors XILINX Hirose 100 pi
15. LOC R10 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_D lt 1 gt LOC P10 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SPI_MISO LOC N10 IOSTANDARD LVCMOS33 DRIVE 6 SLEW SLOW Figure 11 3 UCF Location Constraints for StrataFlash Data I Os 86 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Setting the FPGA Mode Select Pins Control Figure 11 4 provides the UCF constraints for the StrataFlash control pins including the I O pin assignment and the I O standard used NET SF_BYTE LOC C17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF CEO LOC D16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_OE LOC C18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_STS LOC B18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_WE LOC D17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW Figure 11 4 UCF Location Constraints for StrataFlash Control Pins Setting the FPGA Mode Select Pins Set the FPGA configuration mode pins for either BPI Up or BPI down mode as shown in Table 11 4 See Table 11 4 Selecting BPI Up or BPI Down Configuration Modes Header J30 in Figure 4 2 Configuration Mode Pins FPGA Configuration Image in Mode M2 M1 MO StrataFlash Jumper Settings BPI Up 0 1 0 FPGA starts at address 0 and increments through address space The CPLD controls address
16. Operations Options Output Debug Ww J Eli x m as Program ey Verify fl Erase Compact Flash Integrity check UG230 c15 12 030206 Figure 12 13 Click Operations Generate File to Create the Formatted PROM File As shown in Figure 12 14 the iMPACT software indicates that the PROM file was successfully created The PROM Formatter creates an output file based on the settings shown in Figure 12 8 In this example the output file is called MySPIFlash mcs 16M 13 53 Full 35 5006 myfpgabitstream PROM File Generation Succeeded UG230 15 13 030206 Figure 12 14 PROM File Formatter Succeeded Spartan 3E Starter Kit Board User Guide www xilinx com 95 UG230 v1 0 March 9 2006 Chapter 12 SPI Serial Flash XILINX Downloading the Design to SPI Flash There multiple methods to program the SPI Flash as listed below e Use the XSPI programming software provided with XAPP445 Download the SPI Flash via the parallel port using a JTAG parallel programming cable not provided with the kit e Use the PicoBlaze based SPI Flash programmer reference designs Use a terminal emulator such as Hyperlink to download SPI Flash programming data via the PC s serial port to the FPGA The embedded PicoBlaze processor then programs the attached SPI serial Flash See Related Resources page 102 Via the FPGA sJTAG chain use a JTAG tool to program the SPI Flash connected to the FPGA See the link to the U
17. UG230 c10 03 030306 Figure 10 3 SPI Serial Interface to Amplifier The AMP DOUT output from the amplifier echoes the previous gain settings These values can be ignored for most applications The SPI bus transaction starts when the FPGA asserts AMP CS Low see Figure 10 4 The amplifier captures serial data on SP MOSI on the rising edge of the SPI SCK clock signal The amplifier presents serial data on AMP DOUT on the falling edge of SPI SCK AMP CS N 130 50 XE e Pp 30 I S 1 7 MAX XX HOON XR XC XR 85max i AMP DOUT Previous 7 AMA MAMMA AWA AMAA 3 AWW 2 MA All timing is minimum in nanoseconds unless otherwise noted Figure 10 4 SPI Timing When Communicating with Amplifier 76 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Analog to Digital Converter ADC The amplifier interface is relatively slow supporting only about a 10 MHz clock frequency UCF Location Constraints Figure 10 5 provides the User Constraint File UCF constraints for the amplifier interface including the I O pin assignment and I O standard used NET SPI MOSI LOC T4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 NET AMP CS LOC N7 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 NET SPI SCK LOC U16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET AMP SHDN LOC P7 IOSTANDARD LVCMOS33 SLEW SLOW DR
18. after which the host sends a second byte to set the repeat rate FE Resend Upon receiving a resend command the keyboard resends the last scan code sent FF Reset Resets the keyboard The keyboard sends commands or data to the host only when both the data and clock lines are High the Idle state Because the host is the bus master the keyboard checks whether the host is sending data before driving the bus The clock line can be used as a clear to send signal If the host pulls the clock line Low the keyboard must not send any data until the clock is released The keyboard sends data to the host in 11 bit words that contain a 0 start bit followed by eight bits of scan code LSB first followed by an odd parity bit and terminated with a 1 stop bit When the keyboard sends data it generates 11 clock transitions at around 20 to 30 kHz and data is valid on the falling edge of the clock as shown in Figure 8 2 Spartan 3E Starter Kit Board User Guide www xilinx com 63 UG230 v1 0 March 9 2006 Chapter 8 PS 2 Mouse Keyboard Port XILINX Mouse A mouse generates a clock and data signal when moved otherwise these signals remain High indicating the Idle state Each time the mouse is moved the mouse sends three 11 bit words to the host Each of the 11 bit words contains a 0 start bit followed by 8 data bits LSB first followed by an odd parity bit and terminated with a 1 stop bit Each
19. 11 Advanced Spartan 3 Generation Development Boards 11 Key Components and Features an nen 12 Design Trade Offs o croceo ea Ce eh de Lar ac ay e 13 Configuration Methods Galorel 13 Voltages for all Applications 9 99999 6631 13 Related Res uureei dar ashqa dra yar apr dpa cdidit 13 Chapter 2 Switches Buttons and Knob Slide Switches sss 4 22 be eae bh eee ENYN aa DRE E EX rr RR PEE eed 15 Locations and Labels s ze eb e t oe sc we ee een en 15 Operation ndash E Eden oe ele eene Paese bee ed 15 WCE Location Constraints esae Re rhe Xe 15 Push Button Svvitches 16 Locations and Labels 16 Operation sepa ee Ee eee ee p ea er ee 16 UCF Location Constraints entre ete tee RR RU CRI A gne whee lela 17 Rotary Push Button Svvitch 8 17 Locations and Labels 17 Operations EET 17 Push Button Switch zy sac oc EQ ka aaa e e ead Ee e ec e c e e dece 17 Rotary Shaft Encoder ig ace e aute a a 18 UCF Location Constraints 19 Discrete LEDS 19 Locations and Labels uu aa cd baya PE
20. 8 14 Engineer CC XNITIX pue z syueg 44 Appendix A Schematics yx XILINX Power Supply Decoupling IC10PWR represents the various voltage supply inputs to the FPGA and shows the power decoupling network Jumper JP9 defines the voltage applied to VCCO on I O Bank 0 The default setting is 3 3V See Voltage Control page 22 and Voltage Supplies to the Connector page 114 for additional details 146 www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 9002 6 Yen 0 14 oeeon epin5 s sn P eog 13 Wels 3e ueueds WOIXUNX MMM 291 9 V 6 19945 oneuieuos 908120 80 ev 0620 Vis PWR GND UCCAUX UCCAUX UCCAUX UCCAUX UCCAUX UCCAUX UCCAUX UCCAUX UCCINT UCCINT UCCINT UCCINT UCCINT UCCINT UCCINT UCCINT 5 w C92 C93 C94 47nF 47nF 47nF 5959 oo IS L2 il N Buadada IC1 PWR C144 C145 C146 C147 47nF 47nF 47nF 47nF C162 C163 C164 C165 47nF 47nF 47nF 47nF C136 C137 C148 C149 C150 C151 inF inF JinF inF C166 C167 C168 C169 inF inF inF inF I 0 Pouer Select o o o 9 DDR SDRAM C152 C153 C154 C155 156 C157 Pn inF fint inF inF 0 47uF 12uF C 70 C171 C172 C6173 16174 C175 o Ta inF inF inF inF 0 47uF 1 uF Spartan 3E Starter Board Digilent Inc Copyright 2005 2006 Engineer CC TITLE SIE
21. 8 lead MLP 9 219 5 UG230 15 18 030606 Figure 12 19 Multi Package Layout for the STMicroelectronics M25Pxx Family Spartan 3E Starter Kit Board User Guide www xilinx com 101 UG230 v1 0 March 9 2006 Chapter 12 SPI Serial Flash XILINX Related Resources XAPP445 Configuring Spartan 3E Xilinx FPGAs with SPI Flash Memories http www xilinx com xInx xweb xil_publications_display jsp category Application Notes FPGA Features and Design Configuration amp show xapp445 pdf XSPI SPI Flash Programming Utility http www xilinx com xInx xweb xil_publications_display jsp category Application Notes FPGA Features tand Design Configuration amp show xapp445 pdf Xilinx Parallel Cable IV with Flying Leads http www xilinx com xInx xebiz productview jsp sGlobalNavPick amp category 19314 Digilent JTAG3 Programming Cable http www digilentinc com Products Catalog cfm Nav1 Products amp Nav2 Cables amp Cat Cable STMicroelectronics M25P16 SPI Serial Flash Data Sheet http www st com stonline books pdf docs 10027 pdf AN1579 Compatibility between the SOS Package and the MLP Package for the M25Pxx in Your Application http www st com stonline products literature an 9540 pdf PicoBlaze SPI Serial Flash Programmer via RS 232 Reference Design http www xilinx com s3estarter Using Serial Flash on the Spartan 3E Starter Kit Board Reference Design http www xilinx com s3e
22. After this command all subsequentsubsequent read or write operations to the display are to or from DD RAM The addresses for displayed characters appear in Figure 5 3 Execution Time 40 us Read Busy Flag and Address Read the Busy flag BF to determine if an internal operation is in progress and read the current address counter contents BF 1 indicates that an internal operation is in progress The next instruction is not accepted until BF is cleared or until the current instruction is allowed the maximum time to execute This command also returns the present value of address counter The address counter is used for both CG RAM and DD RAM addresses The specific context depends on the most recent Set CG RAM Address or Set DD RAM Address command issued Execution Time 1 us Write Data to CG RAM or DD RAM Write data into DD RAM if the command follows a previous Set DD RAM Address command or write data into CG RAM if the command follows a previous Set CG RAM Address command Spartan 3E Starter Kit Board User Guide www xilinx com 49 UG230 v1 0 March 9 2006 Chapter 5 Character LCD Screen XILINX After the write operation the address is automatically incremented or decremented by 1 according to the Entry Mode Set command The entry mode also determines display shift Execution Time 40 us Read Data from CG RAM or DD RAM Read data from DD RAM if the command follows a previous Set DD RAM Address command or r
23. LOC P7 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE Pushbuttons BTN NET BTN EAST LOC H13 IOSTANDARD LVTTL PULLDOWN NET BTN NORTH LOC V4 IOSTANDARD LVTTL PULLDOWN NET BTN SOUTH LOC K17 IOSTANDARD LVTTL PULLDOWN NET BTN WEST OC D18 IOSTANDARD LVTTL PULLDOWN Clock inputs CLK NET CLK 50MHZ LOC C9 IOSTANDARD LVCMOS33 Define clock period for 50 MHz oscillator 40 60 duty cycle NET CLK 50MHZ PERIOD 20 0ns HIGH 40 NET CLK AUX LOC B8 IOSTANDARD LVCMOS33 NET CLK SMA LOC A10 IOSTANDARD LVCMOS33 Digital to Analog Converter DAC some connections shared with SPI Flash DAC ADC and AMP NET DAC CLR LOC P8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET DAC CS LOC N8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 1 Wire Secure EEPROM DS NET DS_WIRE LOC U4 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 d Ethernet PHY E NET E COL LOC U6 IOSTANDARD LVCMOS33 NET E CRS LOC U13 IOSTANDARD LVCMOS33 NET E MDC LOC P9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 www xilinx com 159 Appendix B Example User Constraints File UCF EZ XILINX
24. Switches Buttons and Knob XILINX NET SW lt 0 gt LOC L13 IOSTANDARD LVTTL PULLUP NET SW 1 LOC L14 IOSTANDARD LVTTL PULLUP NET SW lt 2 gt LOC H18 IOSTANDARD LVTTL PULLUP NET SwW lt 3 gt LOC N17 IOSTANDARD LVTTL PULLUP Figure 2 2 UCF Constraints for Slide Switches Push Button Switches Locations and Labels The Spartan 3E Starter Kit board has four momentary contact push button switches shown in Figure 2 3 The push buttons are located in the lower left corner of the board and are labeled BTN NORTH BTN EAST BTN SOUTH and BTN WEST The FPGA pins that connect to the push buttons appear in parentheses in Figure 2 3 and the associated UCF appears in Figure 2 5 Rotary Push Button Switch ROT A K18 Requires an internal pull up BTN NORTH ROT B G18 Requires an internal pull up V4 ROT CENTER V16 Requires an internal pull down BTN WEST BTN EAST D18 H13 BTN SOUTH K1 7 UG230 c2 02 021206 Notes 1 All BTN_ push button inputs require an internal pull down resistor 2 BTN SOUTH is also used as a soft reset in some FPGA applications Figure 2 3 Four Push Button Switches Surround Rotary Push Button Switch Operation Pressing a push button connects the associated FPGA pin to 3 3V as shown in Figure 2 4 Use an internal pull down resistor within the FPGA pin to generate a logic Low when the button is not pressed Figure 2 5 shows
25. UG230 v1 0 March 9 2006 9002 6 Yen 0 14 oeeon epin5 s sn P eog 13 815 3e ueueds C195 C196 C197 C198 C199 C200 C201 C202 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF MT46U16MI 6TG 75 m E ES R A10 AP E alt gt A12 A 2 Bel z CK_P z o CK N 2 CKE 2 cs 3 3 2 o e N UREF Decoupling Xilinx CoolRunner 2 C211 212 21 214 39pF 3spF 3spF 3spF 908120 LL ev oceeon NOTE Termination network for 1 20 the MT46V16M16TG 75 on sheet 14 6591 on 32Mbit E C203 C204 C205 C206 47nF 18nF 47nF 10nF C207 C208 47nF 18nF ooo n24 999 UPEN A22 A21 A20 A19 A18 a Ale A15 6414 a3 gt D15 D14 D13 28F256J3 TSOP56 Spartan 3E Starter Board Digilent Inc Copyright 2005 2026 SHEET DDR SDRAM and StrataFlash Author GMA TITLE S3E Starter Doct 500 087 Date 02 02 06 Sheet 12 14 Engineer CC INVHOS Hdd uoz liy pue Aowa 4521 HON 1 use qelens alu Appendix A Schematics yx XILINX Buttons Switches Rotary Encoder and Character LCD 154 SVVO SVV1 SW2 and SW3 are slide switches Push button switches W E S and N are located around the ROT1 push button switch rotary encoder LDO through LD7 are discrete LEDs See Chapter 2 Switches Buttons and Knob for additional information DISP1 is a 2x16 character LCD screen See Chapter 5 Character L
26. XILINX Chapter 17 1252432 1 Wire SHA 1 EEPROM The Spartan 3E Starter Kit board includes a Maxim DS2432 serial EEPROM with an integrated SHA 1 engine As shown in Figure 17 1 the DS2432 EEPROM uses the Maxim 1 Wire interface which as the name implies cleverly uses a single wire for power and serial communication The DS2432 EEPROM offers one of many possible means to copy protect the FPGA configuration bitstream making cloning difficult Xilinx application note XAPP780 listed under Related Resources provides one possible implementation method 3 3V Maxim DS2432 Spartan 3E FPGA SHA 1 EEPROM UG230 17 01 030906 Figure 17 1 SHA 1 EEPROM UCF Location Constraints Figure 17 2 provides the UCF constraints for the FPGA connections to the DS2432 SHA 1 EEPROM including the I O pin assignment and the I O standard used NET DS WIRE LOC U4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 Figure 17 2 UCF Location Constraints for DS2432 SHA 1 EEPROM Related Resources e Maxim DS2432 1 Wire EEPROM with SHA 1 Engine http www maxim ic com quick view2 cfm qv pk 2914 XAPP780 FPGA IFF Copy Protection Using Dallas Semiconductor Maxim DS2432 Secure EEPROMs http www xilinx com bvdocs appnotes xapp780 pdf Spartan 3E Starter Kit Board User Guide www xilinx com 129 UG230 v1 0 March 9 2006 Chapter 17 DS2432 1 Wire SHA 1 EEPROM XILINX 130 www xilinx com Spartan 3E Starter Kit B
27. including the FPGA pin number appears in Table 14 1 SMSC LAN83C185 Spartan 3E FPGA 10 100 Ethernet PHY E_TXD lt 3 0 gt See Table TXD 3 0 TX EN P15 E TX EN R4 E TXD lt 4 gt E TX CLK E RXD 3 0 TXD4 TX ER TX CLK RJ 45 RXD 3 0 ol Connector RX_DV E_RX_DV E RXD lt 4 gt E RX CLK E CRS E COL E MDC RXD4 RX ER RX CLK CRS COL MDC 25 000 MHz E MDIO MDIO UG230 c14 02 022706 Figure 14 2 FPGA Connects to Ethernet PHY via MII Table 14 1 FPGA Connections to the LAN83C185 Ethernet PHY FPGA Pin Signal Name Number Function E TXD 4 R6 Transmit Data to the PHY E TXD 4 is also the MII E TXD 35 T5 Transmit Error E_TXD lt 2 gt R5 E TXD 1 T15 E TXD 0 R11 E TX EN P15 Transmit Enable E TX CLK T7 Transmit Clock 25 MHz in 100Base TX mode and 2 5 MHz in 10Base T mode E RXD 4 U14 Receive Data from PHY E 3 V14 E RXD 2 U11 E_RXD lt 1 gt T11 E_RXD lt 0 gt V8 E RX DV V2 Receive Data Valid 110 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX MicroBlaze Ethernet IP Cores Table 14 1 FPGA Connections to the LAN83C185 Ethernet PHY Continued FPGA Pin Signal Name Number Function E RX CLK V3 Receive Clock 25 MHz in 100Base TX mode and 2 5 MHz in 10Base T mode E CRS U13 Carrier Sen
28. 0 March 9 2006 9002 6 Yen 0 14 oeeon epin5 s sn P eog 13 815 3e ueueds UJOO XUI DCAAWM 661 p V anbi S 19945 oneuieuos 908120 v0 0620 for Production TPS75003 IN 1620 151 EN a z 5 Sut TPS75003 ND C 65 180QuF 1 uF 00 Y x Be LTC3412 10 J21 10 J23 Current Sense R64 Ki o ao ANN JP 10 J24 Texas Instruments Triple Output Regulator DDR Regulators 1 Ol No Load for production J25 IHLP 2525CZ 01 ND 6 8uH AY Y QNR LTC1844ES5 J26No Load for production C69 10002 Spartan 3E Starter Board Digilent Inc Copyright 2005 2006 No Load for production No Load for production No Load for production 4 7uF 327 No Load for production Engineer CC SHEET Pouer Supply and Regulators Author GMA TITLE S3E Starter Doc 500 087 Date 02 02 06 Sheet 5 14 s ojein oy oBe3oA Appendix A Schematics yx XILINX FPGA Configurations Settings Platform Flash PROM SPI Serial Flash JTAG Connections 140 IC10MISC represents the various FPGA configuration connections IC11 is a 4 Mbit XCF048 Platform Flash PROM Landing pads for a second XCF045 PROM is shown as IC13 although the second PROM is not mounted on the XC3S500E version of the board Resistor R100 jumpers over the JTAG chain bypassing the second 45 PROM Jumper header J30 selects the FPGA s configuration mode See Table
29. 1017 R202 EX2 1018 100 EX2 1019 8203 EX2 1028 100 EX2 102 R294 EX2 1022 188 EX2 1023 R205 EX2 102 188 EX2 1025 R206 EX2 1026 188 EX2 1022 R207 FX2 1028 100 EX2 1035 R208 EX2 1036 188 EX2 1037 R209 EX2 1038 100 R210 EX2 CLKIN AMA EX gt CI KOUT 100 Spartan 3E Starter Board Digilent Inc Copyright 2005 2026 Engineer CC SHEET DDR Memory Signals Author GMA TITLE S3E Starter Sheet 14 14 XNITIX uoHnEuluH L jenuaJ9jJlg 10129uuo2 zx4 pue uoneguluuj91 S H S NYYAS Yaa Appendix A Schematics yx XILINX 158 www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Appendix B Example User Constraints File UCF HHH E HE HE HE HE HE FE FE FE HE FE FE FE FE FE HE FE FE HE HE EH HE FE HE EEE EE SPARTAN 3E STARTER KIT BOARD CONSTRAINTS FILE FEFE FE FE E HE HE ir HE HE HE HE FE ff FE HE HE FE FE FE tt HE HE FE HE ff FE FE HE FE HE FE FE HE HE FE FE ff FE HE FE HE ff F HE E HE HE HE HE HE Analog to Digital Converter ADC some connections shared with SPI Flash DAC ADC and AMP NET AD CONV LOC P11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 Programmable Gain Amplifier AMP some connections shared with SPI Flash DAC ADC and AMP NET AMP_CS LOC N7 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE NET AMP DOUT OC E18 IOSTANDARD LVCMOS33 NET AMP SHDN
30. 4 1 page 27 for additional information Header J28 is an alternate JTAG header IC12is a Maxim Dallas Semiconductor D52432 SHA 1 EEPROM See Chapter 17 DS2432 1 Wire SHA 1 EEPROM for more information IC14 and IC15 are alternate landing pads for the STMicro SPI serial Flash IC14 accepts the 16 pin SOIC package option while IC15 accepts either the 8 pin SOIC or MLP package option See Figure 12 19 page 101 for additional informaton www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 9002 6 Yen 0 14 oeeon JTAG Interface Header o o 0 P 7 m o Rzs TMS Q 100 R77 TDI 3 rt TCK O Uu GND 188 g UCC 76 77 C78 28 FPGA Control and Q Configuration 9 1uF 1uF 0 1uF c DO Functions o o MISC TMS 9 IP_L14P RDWR_B GCLK TCK c IO L3N MOSI CSI B TDI a IO L1P CSO B TDO N 9 g 5 IO 116 2 0 104_2 M1 x IP L14N 2 GCLK1 M2 m S 0 L23P 1 HDC e O_L23N_1 LDC I0_L26N_2 CCLK IO L24P 1 LDC1 DONE 0 L24N 1 LDC2 PROG B D IO L16N 2 DIN DO gt IO L1N 2 INIT B 1 IO L3P 2 DOUT BUSY s x 9 10_L25N_ HSWAP 2 v amp ICiOMISC x No x ez SSS Load gt x Load on 5006 o No Load on 1600E x ND o 3 3 o FPG Mode Select Jumpers o o o e o lt 29 O No Load for Production Q M25P16 SO16 SPI SDI SDO SCK shorting bloc
31. 57 UG230 v1 0 March 9 2006 Chapter 6 VGA Display Port 3 XILINX 58 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Chapter 7 RS 232 Serial Ports Overview As shown in Figure 7 1 the Spartan 3E Starter Kit board has two RS 232 serial ports a female DB9 DCE connector and a male DTE connector The DCE style port connects directly to the serial port connector available on most personal computers and workstations via a standard straight through serial cable Null modem gender changers or crossover cables are not required Use the DTE style connector to control other RS 232 peripherals such as modems or printers or perform simple loopback testing with the DCE connector Standard Standard 9 pin serial cable 9 pin serial cable DB9 Serial Port Connector front view DCE DTE Female DB9 Male DB9 RS 232 Voltage Translator IC2 RS232 DCE RXD RS232 DCE TXD RS232 DTE RS232 DTE TXD R7 M14 U8 M13 Spartan 3E FPGA UG230 c7 01 022006 Figure 7 1 RS 232 Serial Ports Spartan 3E Starter Kit Board User Guide www xilinx com 59 UG230 v1 0 March 9 2006 Chapter 7 RS 232 Serial Ports XILINX Figure 7 1 shovvs the connection betvveen the FPGA and the tvvo DB9 connectors The FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim
32. 6912 1 AMP mean x qn LTC 1407A 1 ADC REF 1 65V 1 o nie 131500 AGAIN B GAIN H H CHANNEL 1 CHANNEL 0 SCK SPI Control Interface SCK SPI Control Interface AD CONV AMP DOUT SPI MISO UG230 10 02 022306 Figure 10 2 Detailed View of Analog Capture Circuit Digital Outputs from Analog Inputs The analog capture circuit converts the analog voltage on VINA or VINB and converts it to a 14 bit digital representation D 13 0 as expressed by Equation 10 1 Vin 1 65V 125V The GAIN is the current setting loaded into the programmable pre amplifier The various allowable settings for GAIN and allowable voltages applied to the VINA and VINB inputs appear in Table 10 2 D 13 0 2 GAIN x x 8192 Equation 10 1 The reference voltage for the amplifier and the ADC is 1 65V generated via a voltage divider shown in Figure 10 2 Consequently 1 65V is subtracted from the input voltage on VINA or VINB The maximum range of the ADC is 1 25V centered around the reference voltage 1 65V Hence 1 25V appears in the denominator to scale the analog input accordingly 74 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Programmable Pre Amplifier Finally the ADC presents a 14 bit two s complement digital output A 14
33. A18 B18 A19 B19 A20 B20 A21 B21 A22 B22 A23 B23 A24 B24 A25 B25 A26 B26 A27 B27 Spartan 3E Starter Kit Board User Guide www xilinx com 123 Chapter 15 Expansion Connectors XILINX Related Resources Hirose connectors http www hirose connectors com FX2 Series Connector Data Sheet http vvvvvv hirose co ip cataloge hp e57220088 pdf Digilent Inc Peripheral Modules http vvvvvv digilentinc com Products Catalog cfm Nav1 Products amp Nav2 Peripheral amp Cat Peripheral Xilinx ChipScope Pro Tool http www xilinx com ise optional prod cspro htm Agilent B4655A FPGA Dynamic Probe for Logic Analyzer http www home agilent com USeng nav 536898189 536883660 pd html cmpid 92641 Agilent 5404 Pro Series Soft Touch Connector http vvvvvv home agilent com cgi bin pub agilent Product cp Product isp NAV ID 536898227 0 00 Tektronix P69xx Probe Module s vvith D Max Technology http vvvvvv tek com products accessories logic analyzers p6800 p6900 html 124 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Chapter 16 XC2C64A CoolRunner II CPLD The Spartan 3E Starter Kit board includes a Xilinx XC2C64A CoolRunner I CPLD The CPLD is user programmable and available for customer applications Portions of the CPLD are reserved to coordinate behavior between the various FPGA configuration memories namely the Xilinx Platf
34. Board User Guide www xilinx com 53 UG230 v1 0 March 9 2006 Chapter 6 VGA Display Port XILINX Table 6 1 3 Bit Display Color Codes VGA_RED VGA_GREEN VGA_BLUE Resulting Color 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 White VGA signal timing is specified published copyrighted and sold by the Video Electronics Standards Association VESA The following VGA system and timing information is provided as an example of how the FPGA might drive VGA monitor in 640 by 480 mode For more precise information or for information on higher VGA frequencies refer to documents available on the VESA website or other electronics websites see Related Resources page 57 Signal Timing for a 60 Hz 640x480 VGA Display CRT based VGA displays use amplitude modulated moving electron beams or cathode rays to display information on a phosphor coated screen LCDs use an array of switches that can impose a voltage across a small amount of liquid crystal thereby changing light permittivity through the crystal on a pixel by pixel basis Although the following description is limited to CRT displays LCDs have evolved to use the same signal timings as CRT displays Consequently the following discussion pertains to both CRTs and LCDs Within a CRT display current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a raster patte
35. Config EY Rerun all xi Stop ar Processes Open Without Updating UG230_c4_11_022706 Figure 4 10 Set Properties for Bitstream Generator Click Configuration Options as shown in Figure 4 11 Using the Configuration Rate drop list choose 25 to increase the internal CCLK oscillator to approximately 25 MHz the fastest frequency when using an 45 Platform Flash PROM Click OK when finished E Process Properties x Category Pe General Options Configuration Options Startup Options i Readback Options Configuration Rate Configuration Clk Configuration Pins Configuration Pin M Configuration Pin M1 Configuration Pin M2 Configuration Pin Program Configuration Pin Done JTAG Pin TCK v Property display level Standard vi Default 2 UG230 c4 12 022706 Figure 4 11 Set CCLK Configuration Rate under Configuration Options 32 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Programming the FPGA CPLD or Platform Flash PROM via USB To regenerate the programming file double click Generate Programming File as shown in Figure 4 12 Processes User Constraints Br Pa fy Syrithesize XST amp Fa Implement Design amming File Programming File Generatia Generate PROM or JTA Eb Configure Device k ar Processes UG230 c4 13 022706 Figure 4 12 Dou
36. DIP footprint Use this socket if the FPGA application requires a frequency other than 50 MHz Alternatively use the FPGA s Digital Clock Manager DCM to generate or synthesize other frequencies from the on board 50 MHz oscillator SMA Clock Input or Output Connector To provide a clock from an external source connect the input clock signal to the SMA connector The FPGA can also generate a single ended clock output or other high speed signal on the SMA clock connector for an external device UCF Constraints 22 Location The clock input sources require two different types of constraints The location constraints define the I O pin assignments and I O standards The period constraints define the clock period and consequently the clock frequency and the duty cycle of the incoming clock signal Figure 3 2 provides the UCF constraints for the three clock input sources including the I O pin assignment and the I O standard used The settings assume that jumper JP9 is set for 3 3V If JP9 is set for 2 5V adjust the IOSTANDARD settings accordingly www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Related Resources NET CLK_50MHZ LOC C9 IOSTANDARD LVCMOS33 NET CLK_SMA LOC A10 IOSTANDARD LVCMOS33 NET CLK AUX LOC B8 IOSTANDARD LVCMOS33 Figure 3 2 UCF Location Constraints for Clock Sources Clock Period Constraints The Xilinx ISE
37. Ethernet 4 FX2 Hirose FX2 Connector 1 ROM M25P16 6 SD SD RAM 12 SF StrataFlash 12 ST Soft Touch Connector 1 U USB 3 XC 9572 10 3 3U IO1 UREF 102 D5 103 105 T06 UREF O_L4P O_L4N 0 L5P 10 L5N 0 L7P O L7N IO_L9P 10 L9N IO L10P IO L180N IO L18P IO_Li8N IO LiS9P IO L19N UREF 10 L20P 10 L20N IO L22P R23 IO L22N R22 10_L24P A21 IO L24N R20 10_L25P VS2 A19 IO L25N US1 818 IO 1 26 50 817 IC10B2 NO LOAD R117 R11 UCC vor Bank 3 IP1 IP3 IP4 UREF IP5 IP6 IP IP8 IPS IP10 IP11 IP12 IP13 O_L11P LHCLK O_L11N LHCLK1 O_L12P LHCLK2 O_L12N LHCLK3 IRDY2 TO_L13P LHCLK4 TRDY2 O_L13N LHCLK5 O_L14P LHCLK6 O_L14N LHCLK 2 5U DDR 101 102 I0 L4P IO3 UREF IO L1P IO L1N I0 L2P I0 L2N UREF I0 L3P IO L3N I0 L5P I0 L5N I0 L P I0 L N UREF I0 L7P IO L7N 10_L8P IO L8N 10_L9P IO L9N 0 L10P O_LION 0_L15P O_LISN 0 116 O_LISN IO L17P IO L1ZN UREF 0_L18P O_L18N 0_L19P O_LISN IO L20P IO L20N 0_L21P O_L2IN 10_L23P 10_L23N 10_L24P IO L24N IC10B3 c PP oi os or oo 2 o1 fos co In RS ko Ir Joi Js JOT IR Is I N N INS I x Notes are for pins that very between 500 1200 1600 dies Spartan 3E Starter Board Digilent Inc Copyright 2005 2006 TITLE SIE Starter SHEET XC3SE Banks 2 and 3 Author GMA Docs 500 087 Date 02 02 06 Sheet
38. Ge we bie a waqa a yok EARN 19 Operation etx eeu la es 20 UCF Location Constraints 20 Related Resources 20 Chapter 3 Clock Sources 0240801667 77 21 Clock Connections 22 Voltage Control ee o ee ia d 22 50 MHz On Board Oscillator 22 Spartan 3E Starter Kit Board User Guide www xilinx com UG230 v1 0 March 9 2006 XILINX Auxiliary Clock Oscillator Socket 22 SMA Clock Input or Output Connector 22 UCF Consttaints u use aan e Eae es D RV ge Nn 22 Location ne ad nas uka were enge s s 22 Clock Period Constraints 23 Related Resources 23 Chapter 4 FPGA Configuration Options Configuration Mode Jumpers anna 26 PROG Push aita dee oq ray QR Ee CU GARI REC ARCH a 27 DONE Pin LED RE ERR ERR dor o ar de et beds 27 Programming the FPGA CPLD or Platform Flash PROM via USB 28 Connecting the USB Cable 28 Programming via MPACT 29 Programm
39. L14P R4 RHCLK6 I0 L20N IO L14N R3 RHCLK7 IO L21P IO L21N ICi B1 p p p p P x Notes are for pins that very between 500 1200 1600 dies Spartan 3E Starter Board Digilent Inc Copyright 2005 2026 Engineer CC SHEET XC3SE Banks 0 and 1 Clock ICs Author GMA TITLE S3E Starter Docs 500 087 Date 02 02 06 Sheet 7 14 eXNIIIX 10 e 19SQ pue 0 syueg V9d3 Appendix A Schematics yx XILINX FPGA VO Banks 2 and 3 IC10B2 represents the connections to I O Bank 2 on the FPGA Some of the I O Bank 2 connections are used for FPGA configuration and are listed as IC10MISC IC10B3 represents the connections to I O Bank 3 on the FPGA Bank 3 is dedicated to the DDR SDRAM interface and is consequently powered by 2 5V See Chapter 13 DDR SDRAM for additional information 144 www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 9002 6 Yen 0 14 oeeon epin5 s sn P eog 13 815 3e ueueds UJOO XUI DCAAWM 0 2 V einBij 8 199yS oneuieuos 908120 20 ev oceeon Ucc for Bank 2 101 1 2 Ip3 X Ip4 p_L2p IP_L2N P_L8P IP_L8N PLLI1P IP L11N UREF P_L17P IP_L17N P_L23P IP_L23N 104 10 6 I0 L N UpEF IO L21p IO L21N I0 L12P D7 8CLK12 10 L12N D6 GCLK13 10 L13P D4 GCLK14 10_L15P D2 GCLK2 10 L13N D3 GCLK15 I0 L15N D1 GCLK3 AD A D Converter 11 AMP Gain Amplifier 11 DAC D A converter 11 E
40. Mbit of DDR SDRAM x16 data interface 100 MHz 16 MByte 128 Mbit of parallel NOR Flash Intel StrataFlash FPGA configuration storage MicroBlaze code storage shadowing 16 Mbits of SPI serial Flash STMicro FPGA configuration storage MicroBlaze code shadowing 2 line 16 character LCD screen PS 2 mouse or keyboard port VGA display port 10 100 Ethernet PHY requires Ethernet MAC in FPGA Two 9 pin RS 232 ports DTE and DCE style On board USB based FPGA CPLD download debug interface 50 MHz clock oscillator SHA 1 1 wire serial EEPROM for bitstream copy protection Hirose FX2 expansion connector Three Digilent 6 pin expansion connectors Four output SPI based Digital to Analog Converter DAC Two input SPI based Analog to Digital Converter ADC with programmable gain pre amplifier ChipScope SoftTouch debugging port Rotary encoder with push button shaft Eight discrete LEDs Four slide switches 12 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Design Trade Offs e Four push button switches e SMA clock input 8 pin DIP socket for auxiliary clock oscillator Design Trade Offs A few system level design trade offs were required in order to provide the Spartan 3E Starter Kit board with the most functionality Configuration Methods Galore A typical FPGA application uses a single non volatile memory to store configuration images To demon
41. NET FX2 10 16 LOC C11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO lt 17 gt LOC F11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 18 LOC E11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 10 19 LOC E12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 10 20 LOC F12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 21 LOC A13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 22 LOC B13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 23 LOC A14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 24 LOC B14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 25 LOC C14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE B NET FX2 IO 26 LOC D14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO lt 27 gt LOC A16 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 10 28 LOC B16 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 29 LOC E13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 30 LOC CA IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 31 LOC B11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 32 LOC A11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 33 LOC A8 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 34 LOC G9 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IP 3
42. Products Semiconductor DisplayDriverIC MobileDDI BWSTN S6A0069X S6A0069X htm 52 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Chapter 6 VGA Display Port The Spartan 3E Starter Kit board includes a VGA display port via a DB15 connector Connect this port directly to most PC monitors or flat panel LCDs using a standard monitor cable As shown in Figure 6 1 the VGA connector is the left most connector along the top of the board DB15 VGA Connector front view DB15 Connector Bad 2700 AA A 4 8 o H14 VGA RED 2700 een Neo H15 VGA GREEN eus 2700 A A A 48 o 615 vGA BLUE f 82 50 Horizontal Sync vo F15 VGA HSYNC f 82 5Q Vertical Sync 4 F14 VGA VSYNC xx FPGA pin number UG230 c6 01 021706 Figure 6 1 VGA Connections from Spartan 3E Starter Kit Board The Spartan 3E FPGA directly drives the five VGA signals via resistors Each color line has a series resistor with one bit each for VGA RED VGA GREEN and VGA BLUE The series resistor in combination with the 75O termination built into the VGA cable ensures that the color signals remain in the VGA specified OV to 0 7V range The VGA HSYNC and VSYNC signals using LVTTL or LVCMOS33 I O standard drive levels Drive the VGA RED VGA GREEN and VGA BLUE signals High or Low to generate the eight colors shown in Table 6 1 Spartan 3E Starter Kit
43. R11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD 1 LOC T15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD 2 LOC R5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD 3 LOC T5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E_TXD lt 4 gt LOC R6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 Figure 14 4 UCF Location Constraints for 10 100 Ethernet PHY Inputs Related Resources Standard Microsystems SMSC LAN83C185 10 100 Ethernet PHY http www smsc com main catalog lan83c185 html Xilinx OPB Ethernet Media Access Controller EMAC v1 02a http www xilinx com bvdocs ipcenter data_sheet opb_ethernet pdf Xilinx OPB Ethernet Lite Media Access Controller v1 01a The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for applications the do not require support for interrupts back to back data transfers and statistics counters http www xilinx com bvdocs ipcenter data sheet opb ethernetlite pdf EDK 8 1i Documentation http www xilinx com ise embedded edk docs htm 112 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Chapter 15 Expansion Connectors The Spartan 3E Starter Kit board provides a variety of expansion connectors for easy interface flexibility to other off board components The board includes the following I O expansion headers see Figure 15 1
44. Rotary Shaft Encoder UG230_c2_06_030606 GND Figure 2 7 Basic example of rotary shaft encoder circuitry Closing a switch connects it to ground generating a logic Low When the switch is open a pull up resistor within the FPGA pin pulls the signal to a logic High The UCF constraints in Figure 2 9 describe how to define the pull up resistor The FPGA circuitry to decode the A and P inputs is simple but must consider the mechanical switching noise on the inputs also called chatter As shown in Figure 2 8 the chatter can falsely indicate extra rotation events or even indicate rotations in the opposite 18 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Discrete LEDs direction See the Rotary Encoder Interface reference design in Related Resources for an example Rising edge on A when B is Low indicates RIGHT clockwise rotation Switch opening chatter on A Rotating RIGHT gem s false clicks to the RIGHT C P a ii L NU an closing chatter on B injects false clicks to the LEFT B rising edge when A is Low UJ Detent Detent UG230 c2 07 030606 Figure 2 8 Outputs from Rotary Shaft Encoder May Include Mechanical Chatter UCF Location Constraints Figure 2 9 provides the UCF constraints for the four push button switches including the I O pin assignment and the I O standard used and defines a pull do
45. SCK SPI SS B CCLK U16 CSO B U3 UG230 15 01 030206 Figure 12 1 Spartan 3E FPGAs Have an Optional SPI Flash Configuration Interface Table 12 1 SPI Flash Interface Signals Signal FPGA Pin Direction Description SPI MOSI T4 FPGA SPI Serial data Master Output Slave Input SPI MISO N10 FPGA SPI Serial data Master Input Slave Output SPI SCK U16 FPGA gt SPI Clock SPI SS B U3 FPGA gt SPI Asynchronous active Low slave select input UCF Location Constraints Figure 12 2 provides the UCF constraints for the SPI serial Flash PROM including the I O pin assignment and the I O standard used some connections shared with SPI Flash DAC ADC and AMP NET SPI MISO LOC N10 IOSTANDARD LVCMOS33 NET SPI MOSI LOC T4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 NET SPI SCK LOC U16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 NET SPI SS B LOC U3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 NET SPI ALT CS JP11 LOC R12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 Figure 12 2 UCF Location Constraints for SPI Flash Connections Spartan 3E Starter Kit Board User Guide www xilinx com 89 UG230 v1 0 March 9 2006 Chapter 12 SPI Serial Flash XILINX Configuring from SPI Flash To configure the FPGA from SPI Flash the FPGA mode select pins must be set appropriately and the SPI Flash must contain a valid configur
46. SPI Serial Flash 1 AMP CS Programmable Pre Amplifier 1 DAC CS DAC 1 SF StrataFlash Parallel Flash PROM 1 FPGA INIT B Platform Flash PROM 1 Connecting Analog Inputs Connect AC signals to VINA or VINB via a DC blocking capacitor Related Resources e Amplifier and A D Converter Control for the Spartan 3E Starter Kit Reference Design http www xilinx com s3estarter e Xilinx PicoBlaze Soft Processor http www xilinx com picoblaze e LTC6912 Dual Programmable Gain Amplifiers with Serial Digital Interface http www linear com pc downloadDocument do navId H0 C1 C1154 C1009 C1121 P7596 D5359 LIC1407A 1 Serial 14 bit Simultaneous Sampling ADCs with Shutdown http www linear com pc downloadDocument do navId H0 C1 C1155 C1001 C1158 P2420 D1295 Spartan 3E Starter Kit Board User Guide www xilinx com 79 UG230 v1 0 March 9 2006 Chapter 10 Analog Capture Circuit 3 XILINX 80 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Chapter 11 Intel StrataFlash Parallel NOR Flash PROM As shown in Figure 11 1 the Spartan 3E Starter Kit boards includes a 128 Mbit 16 Mbyte Intel StrataFlash parallel NOR Flash PROM As indicated some of the StrataFlash connections are shared with other components on the board Spartan 3E FPGA SF CEO SF OE SF WE SF BYTE SF STS CoolRunne
47. Starter SHEET XC3SE Pouer Decoupling Author GMA Docs 500 087 Date 02 02 06 Sheet 9 14 XNITIX Buiidnoo q Ajddng 1omod Appendix A Schematics yx XILINX XC2C64A CoolRunner Il CPLD IC18 is a Xilinx XC2C64A CoolRunner II CPLD The CPLD primarily provides additional flexibility when configuring the FPGA from parallel NOR Flash and during MultiBoot configurations When the CPLD is loaded with the appropriate design JP10 enables a watchdog timer in the CPLD used during fail safe MultiBoot configurations See Chapter 16 XC2C64A CoolRunner II CPLD for more information 148 www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 9002 6 Yen 0 14 oeeon epin5 s sn P eog 13 Wels 3e ueueds 6v 0L1eeus oneureuos 6 v N 908120 60 ev oceon C176 C177 10nF 47nF C178 C179 10nF 47nF 19 c TMS TDI TDO TCK UCCIOXi ie 2 64 10103 10189 6T 1 10118 GTS 10111 GTS3 10112 6152 I0113 GSR 10201 10202 10205 10206 10287 GCK 10208 6 1 10212 6 2 10212 10213 X a z o UCCIOX2 C180 C181 C182 C183 10nF 47nF 180nF 47nF Spartan 3E Starter Board Digilent Inc Copyright 2005 2006 Engineer CC SHEET XC2C64 CPLD Author GMA TITLE S3E Starter Shest 18 14 XNIIX 0140 Ir1euungjoo 9 Appendix A Schematics yx XILINX Linear Technology ADC and DAC IC19 is a Linear Tech
48. T1 IOSTANDARD SSTL2 I Figure 13 2 UCF Location Constraints for DDR SDRAM Address Inputs Data Figure 13 3 provides the User Constraint File UCF constraints for the DDR SDRAM data pins including the I O pin assignment and I O standard used NET SD DQ 15 LOC H5 IOSTANDARD SSTL2 I NET SD DQ 14 LOC H IOSTANDARD SSTL2 I NET SD DQ 13 LOC G5 IOSTANDARD SSTL2 I NET SD DQ 12 LOC G6 IOSTANDARD SSTL2 I NET SD DQ 11 LOC F2 IOSTANDARD SSTL2 I NET SD DQ 10 LOC Fi IOSTANDARD SSTL2 I NET SD DQ 9 LOC El IOSTANDARD SSTL2 I NET SD DQ 8 LOC E2 IOSTANDARD SSTL2 I NET SD DQ 7 LOC M6 IOSTANDARD SSTL2 I NET SD DQ 6 LOC M5 IOSTANDARD SSTL2 I NET SD DQ 5 LOC M4 IOSTANDARD SSTL2 I NET SD DQ 4 LOC M3 IOSTANDARD SSTL2 I NET SD DQ 3 LOC L4 IOSTANDARD SSTL2 I NET SD DQ 2 LOC L3 IOSTANDARD SSTL2 I NET SD DQ 1 LOC L1 IOSTANDARD SSTL2 I NET SD DQ 0 LOC L2 IOSTANDARD SSTL2 I Figure 13 3 UCF Location Constraints for DDR SDRAM Data I Os 106 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 EZ XILINX Related Resources Control Figure 13 4 provides the User Constraint File UCF constraints for the DDR SDRAM control pins including the I O pin assignment and the I O stand
49. are shared with the Jl 6 pin accessory header NET FX2 IO 1 LOC BA IOSTANDARD LVCMOS33 SLEW FAST DRIVE B NET FX2_IO lt 2 gt LOC A4 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 3 LOC D5 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO lt 4 gt LOC C5 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 These four connections are shared with the J2 6 pin accessory header NET FX2 IO 5 LOC IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 6 LOC B6 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO lt 7 gt LOC ET IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 8 LOC F7 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 These four connections are shared with the J4 6 pin accessory header NET FX2 IO 9 LOC D7 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 10 10 LOC C7 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO lt 11 gt LOC F8 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 12 LOC E8 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 The discrete LEDs are shared with the following 8 FX2 connections NET FX2 IO 13 LOC F9 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 14 LOC EQ IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 10 15 LOC D11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8
50. as shown in Figure 12 10 Click Finish iMPALT File Generation Summary You have entered following information PROM Type SPI PROM File Format mes Fill Value FF PROM filename MySPIFlash Number of PROMs 1 Cancel UG230 c15 09 030206 Figure 12 10 Click Finish after Entering PROM Formatter Settings The PROM Formatter then prompts for the name s of the FPGA configuration bitstream file As shown in Figure 12 11 click OK to start selecting files Select an FPGA bitstream file bit Choose No after selecting the last FPGA file Finally click OK to continue Add Device d i Adding device File to the SPI PROM 1 UG230 15 10 030206 Figure 12 11 Enter FPGA Configuration Bitstream File s When PROM formatting is complete the iMPACT software presents the present settings by showing the PROM the select FPGA bitstream s and the amount of PROM space consumed by the bitstream Figure 12 12 shows an example for a single XC3S500E FPGA bitstream stored in an 45 Platform Flash PROM 94 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Configuring from SPI Flash 16M 13 53 Full xc3s5008 myTpgakitstream UG230 c15 11 030206 Figure 12 12 PROM Formatting Completed To generate the actual PROM file click Operations gt Generate File shown in Figure 12 13 iMPACT C dabta my wdesigns s3e starter kit s3e File Edit view
51. between the FPGA and the StrataFlash device Although the XC3S500E FPGA only requires just slightly over 2 Mbits per configuration image the FPGA to StrataFlash interface on the board support up to a 256 Mbit StrataFlash The Spartan 3E Starter Kit board ships with a 128 Mbit device Address line SF A24 is not used In general the StrataFlash device connects to the XC35500E to support Byte Peripheral Interface BPI configuration The upper four address bits from the FPGA A 23 19 do not connect directly to the StrataFlash device Instead the XC2C64 CPLD controls the pins during configuration As described in Table 11 1 and Shared Connections some of the StrataFlash connections are shared with other components on the board 82 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX StrataFlash Connections Table 11 1 FPGA to StrataFlash Connections Category Address StrataFlash FPGA Pin Signal Name Number Function SF_A24 All Shared with XC2C64A CPLD The CPLD S 0990 5 7 SF A22 V12 XC2C64A CoolRunner II CPLD Also 7 7 SF A20 T12 SF A19 V15 Connects to FPGA pins A 19 0 to support the SF A18 U15 BPI configuration SF A17 T16 SF A16 U18 SF A15 T17 SF A14 R18 SF A13 T18 SF A12 L16 SF A11 L15 SF A10 K13 SF A9 K12 SF A8 K15 SF A7 K14 SF A6 J17 SF_A5 He SF_A4 J15 SF J14 SF_A2
52. data transmission contains 33 total bits where bits 0 11 and 22 are 0 start bits and bits 10 21 and 32 are 1 stop bits The three 8 bit data fields contain movement data as shown in Figure 8 4 Data is valid at the falling edge of the clock and the clock period is 20 to 30 KHz Mouse status byte X direction byte T Y direction byte o al of s xsiysixvivvl P Lo xolxi xex lxd s xsixrl P N Start bit Idle state 2 d Stop bit Stop bit Stop bit Start bit Start bit Idle state UG230 c8 04 021806 Figure 8 4 PS 2 Mouse Transaction A PS 2 style mouse employs a relative coordinate system see Figure 8 5 wherein moving the mouse to the right generates a positive value in the X field and moving to the left generates a negative value Likewise moving the mouse up generates a positive value in the Y field and moving it down represents a negative value The XS and YS bits in the status byte define the sign of each value where a 1 indicates a negative value Y values YS 0 X values X values XS 1 XS 0 Y values YS 1 UG230_c8_05_021806 Figure 8 5 The Mouse Uses a Relative Coordinate System to Track Movement The magnitude of the X and Y values represent the rate of mouse movement The larger the value the faster the mouse is moving The XV and YV bits in the status byte indicate when the X or Y values exceed their maximum value an overflow condition A 1 indica
53. development software uses timing driven logic placement and routing Set the clock PERIOD constraint as appropriate An example constraint appears in Figure 3 3 for the on board 50 MHz clock oscillator The CLK 50MHZ frequency is 50 MHz which equates to a 20 ns period The output duty cycle from the oscillator ranges between 4096 to 60 Define clock period for 50 MHz oscillator NET CLK 50MHZ PERIOD 20 0ns HIGH 40 Figure 3 3 UCF Clock PERIOD Constraint Related Resources e Epson SG 8002JF Series Oscillator Data Sheet 50 MHz Oscillator http www eea epson com g0 Prod Admin Categories ERA QD C ystal Oscillators prog oscillators go Resources TestC2 SG8002 F Spartan 3E Starter Kit Board User Guide www xilinx com 23 UG230 v1 0 March 9 2006 Chapter 3 Clock Sources XILINX 24 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Chapter 4 FPGA Configuration Options The Spartan 3E Starter Kit board supports a variety of FPGA configuration options e Download FPGA designs directly to the Spartan 3E FPGA via JTAG using the on board USB interface The on board USB JTAG logic also provides in system programming for the on board Platform Flash PROM and the Xilinx XC2C64A CPLD SPI serial Flash and StrataFlash programming are performed separately e Program the on board 4 Mbit Xilinx XCF048 serial Platform Flash PROM then configure
54. different functions The switch shaft rotates and outputs values whenever the shaft turns The shaft can also be pressed acting as a push button switch Push Button Switch Pressing the knob on the rotary push button switch connects the associated FPGA pin to 3 3V as shown in Figure 2 6 Use an internal pull down resistor within the FPGA pin to generate a logic Low Figure 2 9 shows how to specify a pull down resistor within the UCF There is no active debouncing circuitry on the push button Spartan 3E Starter Kit Board User Guide www xilinx com 17 UG230 v1 0 March 9 2006 Chapter 2 Switches Buttons and Knob XILINX Rotary Push Button i FPGA I O Pin x ps ROT CENTER Signal V UG230_c2_05_021206 Figure 2 6 Push Button Switches Require Internal Pull up Resistor in FPGA Input Pin Rotary Shaft Encoder In principal the rotary shaft encoder behaves much like a cam connected to central shaft Rotating the shaft then operates two push button switches as shown in Figure 2 7 Depending on which way the shaft is rotated one of the switches opens before the other Likewise as the rotation continues one switch closes before the other However when the shaft is stationary also called the detent position both switches are closed A pull up resistor in each input pin generates a 1 for an open switch See the UCF file for details on specifying the pull up resistor A 0
55. is Low all other inputs to the LCD are ignored Clear Display Clear the display and return the cursor to the home position the top left corner This command writes a blank space ASCII ANSI character code 0x20 into all DD RAM addresses The address counter is reset to 0 location 0x00 in DD RAM Clears all option settings The I D control bit is set to 1 increment address counter mode in the Entry Mode Set command Execution Time 82 us 1 64 ms Return Cursor Home Return the cursor to the home position the top left corner DD RAM contents are unaffected Also returns the display being shifted to the original position shown in Figure 5 3 The address counter is reset to 0 location 0x00 in DD RAM The display is returned to its original status if it was shifted The cursor or blink move to the top left character location Execution Time 40 us 1 6 ms Entry Mode Set Sets the cursor move direction and specifies whether or not to shift the display These operations are performed during data reads and writes Execution Time 40 us Bit DB1 I D Increment Decrement 0 Auto decrement address counter Cursor blink moves to left 1 Auto increment address counter Cursor blink moves to right Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 www xilinx com 47 Chapter 5 Character LCD Screen XILINX This bit either auto increments or auto decremen
56. key is released an E0 F0 key up code is sent followed by the scan code 62 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 EZ XILINX Keyboard ESC 76 Shift e 12 Ctrl 14 7 Ej p 7 E ES ES lt a HI Pi Back Space gt 7 Ej p 7 ES HI Pi 66 074 TAB M 00 H EA El El D DE E El s 5B 5D 06B 7 7 Bi 7 d 7 El ll 1 7 2 7 7 7 Bi d 7 El ll 7 E07 E El bi El ki H Le B B B 7 H E Ki 4c E072 Z X EB 2 77 12 2 i EB ES ES E PA Alt Space Ctrl 11 29 Es es E014 UG230 c8 03 021806 N Figure 8 3 PS 2 Keyboard Scan Codes The host can also send commands and data to the keyboard Table 8 3 provides a short list of some often used commands Table 8 3 Common PS 2 Keyboard Commands Command ED Description Turn on off Num Lock Caps Lock and Scroll Lock LEDs The keyboard acknowledges receipt of an ED command by replying with an FA after which the host sends another byte to set LED status The bit positions for the keyboard LEDs are shown below Write a 1 to the specific bit to illuminate the associated keyboard LED 7 6 5 4 3 2 1 0 Ignored Caps Lock Num Lock Scroll Lock EE Echo Upon receiving an echo command the keyboard replies with the same scan code EE F3 Set scan code repeat rate The keyboard acknowledges receipt of an F3 by returning an FA
57. lines A 24 20 during BPI configuration BPI Down 0 1 1 FPGA starts at address xFF FFFF and decrements through address space The CPLD controls address lines A 24 20 during BPI configuration Related Resources e Intel J3 StrataFlash Data Sheet http www intel com design flcomp products j3 techdocs htm datasheets e Application Note 827 Intel StrataFlash Memory J3 to Xilinx Spartan 3E FPGA Design Guide http www intel com design flcomp applnots 307257 htm Spartan 3E Starter Kit Board User Guide www xilinx com 87 UG230 v1 0 March 9 2006 Chapter 11 Intel StrataFlash Parallel NOR Flash PROM 3 XILINX 88 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Chapter 12 SPI Serial Flash The Spartan 3E Starter Kit board includes a STMicroelectronics M25P16 16 Mbit SPI serial Flash useful in a variety of applications The SPI Flash provides an alternative means to configure the FPGA a new feature of Spartan 3E FPGAs as shown in Figure 12 1 The SPI Flash is also available to the FPGA after configuration for a variety of purposes such as e Simple non volatile data storage e Storage for identifier codes serial numbers IP addresses etc e Storage of MicroBlaze processor code that can be shadowed into DDR SDRAM STMicro M25P16 Spartan 3E FPGA SPI Serial Flash MOSI CSI B T4 DIN DO N10 SPI MOSI SPI MISO SPI
58. no previous data lingers The Verify option checks that the PROM was correctly programmed and matches the downloaded configuration bitstream Both these options are recommended even though they increase overall programming time The Load FPGA option immediately forces the FPGA to reconfigure after programming the Platform Flash PROM The FPGA s configuration mode pins must be set for Master Serial mode as defined in Table 4 1 page 27 Click OK when finished Spartan 3E Starter Kit Board User Guide www xilinx com 39 UG230 v1 0 March 9 2006 Chapter 4 FPGA Configuration Options XILINX IV Verify General CPLD And PROM Properties IV Erase Before Programming Read Protect T Prom CoolRunner ll Usercode 8 Hex Digits CPLD Specific Properties write Protect Functional Test On The Fly Program PLA UES Enter up to 13 characters PROM Specific Properties Paralel Mode Use D4 for CF ttes EL UG230 c4 27 022806 Figure 4 26 PROM Programming Options The iMPACT software indicates if programming was successful or not If programming was successful and the Load FPGA option was left unchecked push the PROG B push button switch shown in Figure 4 2 page 26 to force the FPGA to reconfigure from the newly programmed Platform Flash PROM If the FPGA successfully configures the DONE LED also shown in Figure 4 2 lights up 40 www xilinx com Spartan 3E Starter Kit Board User Guide UG2
59. the functionality of the PS 2 mouse and keyboard port e Chapter 9 Digital to Analog Converter DAC describes the functionality of the DAC e Chapter 10 Analog Capture Circuit describes the functionality of the A D converter with a programmable gain pre amplifier e Chapter 11 Intel StrataFlash Parallel NOR Flash PROM describes the functionality of the StrataFlash PROM Chapter 12 SPI Serial Flash describes the functionality of the SPI Serial Flash memory e Chapter 13 DDR SDRAM describes the functionality of the DDR SDRAM Chapter 14 10 100 Ethernet Physical Layer Interface describes the functionality of the 10 100Base T Ethernet physical layer interface e Chapter 15 Expansion Connectors describes the various connectors available on the Spartan 3E Starter Kit board e Chapter 16 XC2C64A CoolRunner II CPLD describes how the CPLD is involved in FPGA configuration when using Master Serial and BPI mode Chapter 17 DS2432 1 Wire SHA 1 EEPROM provides a brief introduction to the SHA 1 secure EEPROM for authenticating or copy protecting FPGA configuration bitstreams e Appendix A Schematics lists the schematics for the Spartan 3E Starter Kit board e Appendix B Example User Constraints File UCF provides example code from a UCF Additional Resources To find additional documentation see the Xilinx vvebsite at http vvvvvv xilinx com literature
60. 1 P20 19 10 lt 32 gt IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 i SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW tn m t m t t m LOW LOW LOW LOW LOW LOW LOW SLOW SLOW SLOW SLOW SLOW S S S LOW LOW LOW LOW LOW LOW S S S S LOW SLOW Figure 16 3 UCF Location Constraints for the XC2C64A CPLD Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 www xilinx com 127 Chapter 16 XC2C64A CoolRunner Il CPLD XILINX Related Resources CoolRunner II CPLD Family Data Sheet http direct xilinx com bvdocs publications ds090 pdf e XC2C64A CoolRunner I CPLD Data Sheet http direct xilinx com bvdocs publications ds311 pdf e Default XC2C64A CPLD Design for Spartan 3E Starter Kit Board http www xilinx com s3estarter 128 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006
61. 13 DDR SDRAM 3 XILINX The differential clock pin SD CK P is fed back into FPGA pin B9 in I O Bank 0 to have best access to one of the FPGA s Digital Clock Managers DCMs This path is required when using the MicroBlaze OPB DDR controller The MicroBlaze OPB DDR SDRAM controller IP core documentation is also available from within the EDK 8 1i development software see Related Resources page 107 DDR SDRAM Connections Table 13 1 shows the connections between the FPGA and the DDR SDRAM Table 13 1 FPGA to DDR SDRAM Connections DDR SDRAM FPGA Pin Category Signal Name Number Function SD A12 P2 Address inputs SD A11 N5 SD A10 T2 SD A9 N4 SD A8 H2 2 SD A7 H1 3 SD A6 H3 SD_A5 H4 SD_A4 F4 SD_A3 P1 SD_A2 R2 SD_A1 R3 SD A0 T1 104 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 T XILINX DDR SDRAM Connections Table 13 1 FPGA to DDR SDRAM Connections Continued DDR SDRAM FPGA Pin Category Signal Name Number Function SD DQ15 H5 Data input output SD DQ14 H6 SD DQ13 G5 SD DQ12 G6 SD DQ11 F2 SD DQ10 F1 SD DQ9 El 8 SD_DQ8 E2 A SD_DQ7 M6 SD DQ6 M5 SD 5 M4 SD DQ4 M3 SD DO3 I4 SD DQ2 L3 SD DQ1 Ll SD DOO I2 SD BA1 K6 Bank address inputs SD BAQ K5 SD RAS C1 Command inputs SD CAS C2 SD WE D1 SD
62. 16N IP_L22P IP_L22N 1 2 10 Lz1p 10 L21N IO L11P GCLK4 IO L11N GCLK5 IO L12P GCLK6 IO L12N GCLK7 IP L13P GCLK8 IP L13N GCLK9 IO L14P GCLK1O IO L14N GCLK11 102 103 UREF 104 105 107 108 IO L1P IO L1N IO L3P 10 L3N UREF IO L4P IO_L4N IO_L5P IO L5N UREF IO_L6P IO_L6N I0 L8P IO_L8N IO L9P IO_LSN IO L15P IO L15N IO L17P IO L17N IO L18P IO L18N UREF IO L19P IO L1S9N UREF I0 L20P 10 L20N I0 L23P I0 L23N UREF I0 L24P I0 L24N I0 L25P Socket 8 upp oe GND OUT IC16 S68002DC AMP Gain Amplifier 11 DAC D A converter 11 E Ethernet 4 FX2 Hirose FX2 Connector 1 ROM M25P16 6 SD SD RAM 12 SF StrataFlash 12 ST Soft Touch Connector 1 U USB 35 XC 9572 105 C NJ QJ amp OTOV NL OO CO CO NJ I WAJA NL OD 2S CO UW 1012 S68002JF UCC for Bank 1 IP1 IP3 IP4 IP5 IP6 IPZ UREF IP8 IPS IP10 IP11 UREF IP12 IP14 X 10_L22N 102 X 101 103 10 L1P R16 IO LIN R15 10 L2P R14 10 L2N R13 IO L3P 10 L3N UREF IO L5P 10 L5N UREF I0 L P IO L N IO L7P IO L7N IO L8P IO L8N I0 L9P 812 IO L9N R11 TO_L1 P IO LLON UREF I0 L15P 62 IO_LISN AL I0 L16P 10 L16N 68 10 112 10 L11P R10 RHCLKO IO L17N IO L11N RS RHCLK1 IO L18P IO L12P R8 RHCLK2 IO L18N IO L12N R7 RHCLK3 TRDY1 IO L19P 10 L13P R6 RHCLK4 IRDY IO L19N IO L13N R5 RHCLK5 I0 L20P IO
63. 2 1018 E11 IO L08P 0 I O Yes FX2 IO19 E12 IO L06N 0 I O Yes 10 R203 FX2 IO20 F12 TO L06P 0 I O Yes FX2 IO21 A13 IO L05P 0 I O Yes 11 R204 FX2 IO22 B13 IO L05N 0 I O Yes FX2 IO23 A14 TO LOAN 0 I O Yes 12 R205 FX2 IO24 B14 IO L04P 0 I O Yes FX2 IO25 C14 IO L03N 0 I O Yes 13 R206 FX2 IO26 D14 IO L03P 0 I O Yes FX2 IO27 A16 IO LOIN 0 I O Yes 14 R207 FX2 IO28 B16 IO L01P I O Yes FX2 IP35 D12 IP L07N 0 Input 15 R208 FX2 IP36 C12 IP 107 Input FX2 IP37 A15 IP LO2N 0 Input 16 R209 FX2 IP38 B15 IP 102 0 Input IO L11N 0 FX2 CLKIN E10 GCLK5 I O Yes 5 IO L11P 0 iss FX2 CLKOUT D10 GCLKA I O Yes Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 www xilinx com 117 Chapter 15 Expansion Connectors XILINX Using Differential Inputs LVDS and RSDS differential inputs require input termination Two options are available The first option is to use external termination resistors as shown in Figure 15 3a The board provides landing pads for external 1000 termination resistors The resistors are not loaded on the board as shipped The resistor reference designators are labeled on the silkscreen as listed in Table 15 2 The landing pads are located on both the top and bottom side of the board between the FPGA and the FX2 connector The resistors are not loaded on the board as shipped External termination is always required when using differential input pairs 15 and 16 The second option shown i
64. 30 v1 0 March 9 2006 XILINX Chapter 5 Character LCD Screen Overview The Spartan 3E Starter Kit board prominently features a 2 line by 16 character liquid crystal display LCD The FPGA controls the LCD via the 4 bit data interface shown in Figure 5 1 Although the LCD supports an 8 bit data interface the Starter Kit board uses a 4 bit data interface to remain compatible with other Xilinx development boards and to minimize total pin count Spartan 3E FPGA Character LCD SF D 11 3 SF D 105 SF D 95 SF D 8 DB7 DB6 Four bit data DB5 interface DB4 5 DB 3 0 Unused E Intel StrataFlash UG230 c5 01 022006 Figure 5 1 Character LCD Interface Once mastered the LCD is a practical way to display a variety of information using standard ASCII and custom characters However these displays are not fast Scrolling the display at half second intervals tests the practical limit for clarity Compared with the 50 MHz clock available on the board the display is slow A PicoBlaze processor efficiently controls display timing plus the actual content of the display Spartan 3E Starter Kit Board User Guide www xilinx com 41 UG230 v1 0 March 9 2006 Chapter 5 Character LCD Screen EZ XILINX Character LCD Interface Signals Table 5 1 shows the interface character LCD interface signals Table 5 1 Character LCD Interface Signal Name FPGA Pin Functio
65. 4 30 30 FX2_IO26 D14 3 31 2 1 27 A16 92 32 2 IO28 B16 33 33 FX2 IO29 E13 34 34 Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 www xilinx com 115 Chapter 15 Expansion Connectors Table 15 1 Hirose 100 pin FX2 Connector Pinout and FPGA Connections 43 Continued lt XILINX Shared Header Connections FX2 Connector A B Signal Name FPGA Pin LED J1 J2 JP4 J6 top bottom FPGA Pin FX2_IO30 C4 95 35 FX2 1 31 B11 36 36 FX2 1032 A11 37 5 FX2 1033 A8 38 38 FX2 1034 G9 39 39 2 IP35 D12 40 40 FX2_IP36 C12 41 41 2 IP37 A15 42 42 2 IP38 B15 43 43 2 IO39 C3 44 44 FX2_IP40 C15 45 45 GND 46 46 E10 FX2 CLKOUT D10 47 47 48 48 D9 49 49 50 50 Signal Name FX2_CLKIN GND FX2_CLKIO SHIELD Compatible Board The following board is compatible with the FX2 connector on the Spartan 3E Starter Kit board VDEC1 Video Decoder Board from Digilent Inc http vvvvvv digilentinc com Products Detail cfm Prod VDEC1 Mating Receptacle Connectors The Spartan 3E Starter Kit board uses a Hirose FX2 100P 1 27DS header connector The header mates with any compatible 100 pin receptacle connector including board mounted and non locking cable connectors Differential I O The Hirose FX2 connector header J3 supports up
66. 46V32M16 32M x 16 DDR SDRAM Data Sheet http download micron com pdf datasheets dram ddr 512M BDDRx4x8x16 pdf MicroBlaze OPB Double Data Rate DDR SDRAM Controller v2 00b http vvvvvv xilinx com bvdocs ipcenter data sheet opb ddr pdf Spartan 3E Starter Kit Board User Gui UG230 v1 0 March 9 2006 de www xilinx com 107 Chapter 13 DDR SDRAM XILINX 108 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Chapter 14 10 100 Ethernet Physical Layer Interface The Spartan 3E Starter Kit board includes a Standard Microsystems LAN83C185 10 100 Ethernet physical layer PHY interface and an RJ 45 connector as shown in Figure 14 1 With an Ethernet Media Access Controller MAC implemented in the FPGA the board can optionally connect to a standard Ethernet network All timing is controlled from an on board 25 MHz crystal oscillator RJ 45 Ethernet Connector J19 SMSC LAN83C185 10 100 Ethernet PHY UG230 c14 01 022706 25 MHz Crystal 10 100 Ethernet PHY with RJ 45 Connector Figure 14 1 Spartan 3E Starter Kit Board User Guide www xilinx com 109 UG230 v1 0 March 9 2006 Chapter 14 10 100 Ethernet Physical Layer Interface XILINX Ethernet PHY Connections The FPGA connects to the LAN83C185 Ethernet PHY using a standard Media Independent Interface MII as shown in Figure 14 2 A more detailed description of the interface signals
67. 4_21_022706 Figure 4 20 Click Operations gt Generate File to Create the Formatted PROM File The iMPACT software indicates that the PROM file was successfully created as shown in Figure 4 21 xcf 4s 54 13 56 Full xc3s500e myfpgabitstream PROM File Generation Succeeded UG230 c4 22 022706 Figure 4 21 PROM File Formatter Succeeded Programming the Platform Flash PROM To program the formatted PROM file into the Platform Flash PROM via the on board USB JTAG circuitry follow the steps outlined in this subsection Place the iMPACT software in the JTAG Boundary Scan mode either by choosing Boundary Scan in the iMPACT Modes pane as shown in Figure 4 22 or by clicking on the Boundary Scan tab Spartan 3E Starter Kit Board User Guide www xilinx com 37 UG230 v1 0 March 9 2006 Chapter 4 FPGA Configuration Options XILINX iMPACT C data my designs s3e starter kit s3e starter kit iph Sl File Edit View Operations Options Output Debug Window Help Jg H B B x BRIG G Boundary Scan i maSlveSed vm Q s annann S8SelectMAP g lDesktop Configu gt E SystemA CE xc3s500e toplevel bit file x TDO U U iMPACT Process Operations Boundary Scan Prom File Forma UG230 c4 23 022706 Figure 4 22 Switch to Boundary Scan Mode Assign the PROM file to the XCF048 Platform Flash PROM on the JTAG chain as shown i
68. 5 LOC D12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IP 36 LOC C12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IP lt 37 gt LOC A15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IP 38 LOC B15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 10 39 LOC C3 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IP 40 LOC C15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 Figure 15 7 UCF Location Constraints for Accessory Headers 120 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Six Pin Accessory Headers Six Pin Accessory Headers The 6 pin accessory headers provide easy I O interface expansion using the various Digilent Peripheral Modules see Related Resources page 124 The location of the 6 pin headers is provided in Figure 15 1 page 113 Header J1 The J1 header shown in Figure 15 8 is the top most 6 pin connector along the right edge of the board It uses a female 6 pin 90 socket Four FPGA pins connect to the J1 header 2 IO 4 1 These four signals are also shared with the Hirose FX2 connector The board supplies 3 3V to the accessory board mounted in the J1 socket on the bottom pin Spartan 3E FPGA Ji UG230_c12_07_022406 Figure 15 8 FPGA Connections to the J1 Accessory Header Header J2 The J2 header shown in Figure 15 9 is the bottom mos
69. ADC and AMP SPI MISO LOC N10 IOSTANDARD LVCMOS33 SPI MOSI LOC T4 IOSTANDARD LVCMOS33 SLEW SLOW SPI SCK LOC U16 IOSTANDARD LVCMOS33 SLEW SLOW SPI SS B LOC U3 IOSTANDARD LVCMOS33 SLEW SLOW SPI ALT CS 11 LOC R12 IOSTANDARD LVCMOS33 SLEW Slide Switches SW SW 0 LOC L13 IOSTANDARD LVTTL PULLUP SW 1 LOC L14 IOSTANDARD LVTTL PULLUP SW lt 2 gt LOC H18 IOSTANDARD LVTTL PULLUP SW lt 3 gt LOC N17 IOSTANDARD LVTTL PULLUP VGA Port VGA VGA BLUE LOC G15 IOSTANDARD LVTTL DRIVE 8 51 VGA GREEN LOC H15 IOSTANDARD LVTTL DRIVE 8 S HSYNC LOC F15 IOSTANDARD LVTTL DRIVE 8 51 VGA RED LOC H14 IOSTANDARD LVTTL DRIVE 8 51 VGA VSYNC LOC F14 IOSTANDARD LVTTL DRIVE 8 SI Xilinx CPLD XC XC CMD 0 LOC P18 IOSTANDARD LVTTL DRIVE 4 SL XC_CMD lt 1 gt LOC N18 IOSTANDARD LVTTL DRIVE 4 SL XC_CPLD_EN LOC B10 IOSTANDARD LVTTL XC_D lt 0 gt LOC G16 IOSTANDARD LVTTL DRIVE 4 SL XC_D lt 1 gt LOC F18 IOSTANDARD LVTTL DRIVE 4 SL XC_D lt 2 gt LOC F17 IOSTANDARD LVTTL DRIVE 4 SL XC_TRIG LOC R17 IOSTANDARD LVCMOS33 XC_GCKO LOC H16 IOSTANDARD LVCMOS33 DRIVE 4 GCLK10 9 IOSTANDARD LVCMOS33 DRIVE 4
70. AM command The 8 bit data value represents the look up address into the CG ROM or CG RAM shown in Figure 5 4 The stored bitmap in the CG ROM or CG RAM drives the 5 x 8 dot matrix to represent the associated character If the address counter is configured to auto increment as described earlier the application can sequentially write multiple character codes and each character is automatically stored and displayed in the next available location Continuing to write characters however eventually falls off the end of the first display line The additional characters do not automatically appear on the second line because the DD RAM map is not consecutive from the first line to the second Disabling the Unused LCD If the FPGA application does not use the character LCD screen drive the LCD E pin Low to disable it Also drive the LCD RW pin Low to prevent the LCD screen from presenting data Related Resources e Initial Design for Spartan 3E Starter Kit Reference Design http www xilinx com s3estarter Powerlip PC1602 D Character LCD Basic Electrical and Mechanical Data http www powertipusa com pdf pc1602d pdf Sitronix ST7066U Character LCD Controller http www sitronix com tw sitronix product nsf Doc ST7066U OpenDocument e Detailed Data Sheet on PowerTip Character LCD http vvvvvv rapidelectronics co uk images siteimg 57 0910e PDF e Samsung S6A0069X Character LCD Controller http vvvvvv samsung com
71. ANDARD LVTTL SLEW SLOW DRIVE 6 NET J1 1 LOC A4 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J1 lt 2 gt LOC D5 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J1 lt 3 gt LOC C5 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 6 pin header J2 These four connections are shared with the FX2 connector NET J2 0 LOC A6 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J2 lt 1 gt LOC B6 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J2 lt 2 gt LOC E7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J2 lt 3 gt LOC ET IOSTANDARD LVTTL SLEW SLOW DRIVE 6 6 pin header J4 These four connections are shared with the FX2 connector NET J4 lt 0 gt LOC D7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J4 lt 1 gt LOC C7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J4 lt 2 gt LOC F8 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 f NET J4 lt 3 gt LOC E8 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 Figure 15 11 UCF Location Constraints for Accessory Headers 122 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Connectorless Debugging Port Landing Pads 46 Connectorless Debugging Port Landing Pads 46 Landing pads for a connectorless debugging port are provided as header J6 shown in Figure 15 1 page 113 There is no physical connector on the board Instead a connectorless pr
72. ANDARD SSTL2 I SD CS LOC K4 IOSTANDARD SSTL2 I SD DQ 0 LOC L2 IOSTANDARD SSTL2 I SD_DQ lt 1 gt LOC L1 IOSTANDARD SSTL2 I SD 2 LOC L3 IOSTANDARD SSTL2 I SD DQ 3 LOC L4 IOSTANDARD SSTL2 I SD DQ 4 LOC M3 IOSTANDARD SSTL2 I SD DQ 5 LOC M4 IOSTANDARD SSTL2 I SD DQ 6 LOC IOSTANDARD SSTL2 I SD DQ 7 LOC M6 IOSTANDARD SSTL2 I SD_DQ lt 8 gt LOC E2 IOSTANDARD SSTL2 I SD DQ 9 LOC El IOSTANDARD SSTL2 I SD_DQ lt 10 gt LOC Fl IOSTANDARD SSTL2 I SD_DQ lt 11 gt LOC F2 IOSTANDARD SSTL2 I SD_DQ lt 12 gt LOC G6 IOSTANDARD SSTL2 I SD_DQ lt 13 gt LOC G5 IOSTANDARD SSTL2 I SD DQ 14 LOC H6 IOSTANDARD SSTL2 I SD DQ 15 LOC H5 IOSTANDARD SSTL2 I 162 www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 EZ XILINX NET SD LDM NET SD LDOQS NET SD RAS NET SD UDM NET SD UDQS NET SD WE Path to allow NET SD CK FB Prohibit VREF CONFIG PROHIBIT CONFIG PROHIBIT CONFIG PROHIBIT CONFIG PROHIBIT CONFIG PROHIBIT ri ri R SF A 0 SF_A lt 1 gt SF_A lt 2 gt SF A lt 3 gt SF_A lt 4 gt SF_A lt 5 gt SF_A lt 6 gt SF_A lt 7 gt SF_A lt 8 gt SF_A lt 9 gt S
73. Board Using Differential Outputs Differential input signals do not require any special voltage LVDS and RSDS differential outputs signals on the other hand require a 2 5V supply on I O Bank 0 The board provides the option to power I O Bank 0 with either 3 3V or 2 5V Figure 15 1 page 113 highlights the location of jumper JP9 If using differential outputs on the FX2 connector set jumper JP9 to 2 5V If the jumper is not set correctly the outputs switch correctly but the signal levels are out of specification PAD 54 LxxN Signal Jd x UG230 12 06 022406 Figure 15 6 Differential Outputs UCF Location Constraints Figure 15 7 provides the UCF constraints for the FX2 connector including the I O pin assignment and the I O standard used assuming that all connections use single ended I O standards These header connections are shared with the 6 pin accessory headers as shown in Figure 15 11 page 122 Spartan 3E Starter Kit Board User Guide www xilinx com 119 UG230 v1 0 March 9 2006 Chapter 15 Expansion Connectors XILINX FX2 Connector FX2 NET FX2 CLKIN LOC E10 IOSTANDARD LVCMOS33 NET FX2 CLKIO LOC D9 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 CLKOUT LOC D10 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 These four connections
74. By default this jumper is empty and the signal is pulled to a logic High The XC_PROG_B output from the CPLD if used must be configured as an open drain out i e either actively drives Low or floats to Hi Z never drives High This signal connects directly to the FPGA s PROG B programming pin The most siginficant StrataFlash PROM address bit SF A 24 is the same as the FX2 connector signal called FX2 TO 325 The 16 Mbyte StrataFlash PROM only physically uses the lower 24 bits SF A 23 0 The extra address bit SF A 24 is provided for upward density migration for the StrataFlash PROM Spartan 3E Starter Kit Board User Guide www xilinx com 125 UG230 v1 0 March 9 2006 Chapter 16 XC2C64A CoolRunner Il CPLD XILINX 3 3V JP10 XC2C64A VQ44 WDT EN CoolRunner Ill CPLD XC WDT EN Oo Vv Spartan 3E FPGA XC_CMD lt 1 gt XC_CMD lt 0 gt XC_D lt 2 gt XC D 1 XC D 0 FPGA M2 FPGA M1 FPGA MO XC CPLD EN XC TRIG XC DONE Required for Master Serial Mode Enable Platform Flash PROM when M 2 0 000 XCF04S Platform Flash PROM XC PROG B XC GCKO GCLK10 SPI SCK FX2_10 lt 32 gt F_A lt 24 gt SF_A lt 23 gt SF_A lt 22 gt SF_A lt 21 gt SF_A lt 20 gt During Configuration BPI Up 24 20 00000 BPI Down A 24 20 11111 After Configuration or Other Modes A 24 20 ZZZZ Intel StrataFla
75. CD Screen for additional information www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 9002 6 Yen 0 14 oeeon epin5 s sn P eog 13 815 3e ueueds UJOO 491 ZL Y anbl4 EL 19 9us oneuieuos 908120 L ev 0620 Suitches Buttons UCC3U3 e 390 R155 R156 390 390 R157 LCD Display pgr H ppg 5u 5 po e E gnon i N Pushbutton Rotary Encoder Spartan 3E Starter Board Digilent Inc Copyright 2005 2006 SHEET LCD and General IOs 0217 pue 4 po uz seuoims suollng Appendix A Schematics yx XILINX DDR SDRAM Series Termination and FX2 Connector Differential Termination 156 Resistors R160 through R201 represent the series termination resistors for the DDR SDRAM See Chapter 13 DDR SDRAM for additional information Resistors R202 through R210 are not loaded on the board These landing pads provide optional connections for 1000 differential termination resistors See Using Differential Inputs page 118 for additional information www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 9002 6 Yen 0 14 oeeon Spiny s sn P eog 13 15 3e ueueds UJOO XUI DCAAWM 281 1 v yl 19945 908120 L EV 0229 DDR Series Termination FX2 Differential Termination Not Loaded EX2
76. CK the data must be valid for at least 4 ns relative to the rising clock edge The LTC2624 DAC transmits its data on the SPI MISO signal on the falling edge of SPI SCK The FPGA captures this data on the next rising SPI SCK edge The FPGA must read the first SPI MISO value on the first rising SPI SCK edge after DAC CS goes Low Otherwise bit 31 is missed After transmitting all 32 data bits the FPGA completes the SPI bus transaction by returning the DAC CS slave select signal High The High going edge starts the actual digital to analog conversion process within the DAC Communication Protocol Figure 9 4 shows the communications protocol required to interface with the LTC2624 DAC The DAC supports both a 24 bit and 32 bit protocol The 32 bit protocol is shown Inside the D A converter the SPI interface is formed by a 32 bit shift register Each 32 bit command word consists of a command an address followed by data value As a new command enters the DAC the previous 32 bit command word is echoed back to the master The response from the DAC can be ignored although it is a useful to confirm correct communication Spartan 3E Starter Kit Board User Guide www xilinx com 69 UG230 v1 0 March 9 2006 Chapter 9 Digital to Analog Converter DAC XILINX SPI MISO Slave LTC2624 DAC 31 7777HHHEHELLL NE E mmn Spartan 3E Don t Care Don t Care 12 bit Unsigned DATA COMMAND ADDRESS
77. CK N JA Differential clock input _ SD CK P J5 SD CKE K3 Active High clock enable input SD CS K4 Active Low chip select input SD UDM JA Data Mask Upper and Lower data masks SD LDM J2 SD_UDQS G3 Data Strobe Upper and Lower data strobes SD_LDQS L6 SD_CK_FB B9 SDRAM clock feedback into top DCM within FPGA Used by some DDR SDRAM controller cores Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 www xilinx com 105 Chapter 13 DDR SDRAM XILINX UCF Location Constraints Address Figure 13 2 provides the User Constraint File UCF constraints for the DDR SDRAM address pins including the I O pin assignment and the I O standard used NET SD A 12 LOC P2 IOSTANDARD SSTL2 I NET SD A 11 LOC N5 IOSTANDARD SSTL2 I NET SD A 10 LOC T2 IOSTANDARD SSTL2 I NET SD A 9 LOC N4 IOSTANDARD SSTL2 I NET SD A 8 LOC H2 IOSTANDARD SSTL2 I NET SD A 7 LOC H1 IOSTANDARD SSTL2 I NET SD A 6 LOC H3 IOSTANDARD SSTL2 I NET SD_A lt 5 gt LOC H4 IOSTANDARD SSTL2 I NET SD_A lt 4 gt LOC F4 IOSTANDARD SSTL2 I NET SD A 3 P1 IOSTANDARD SSTL2 I NET SD A 2 R2 IOSTANDARD SSTL2 I NET SD_A lt 1 gt LOC R3 IOSTANDARD SSTL2 I NET SD A 0
78. DJ DE BJ DS 1 DS D AB D DS BJ DE D E BB D OD D PB D D BJ DUE d RP PP HS HS S S HS S HS IS S IS HS IS HS IS S IS S IS S IS S IS S IS S S IS S S S Ge HS HS HS IS HS Ga Ge 02 n n n 0 NN 0 n n n n n 0 n 0 0 n n 0 0 0 0 n n n 0 0 0 0 0 G 0 n 0 n 0 0 0 3 02 U EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW EW SLOW Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 www xilinx com 163 Appendix B Example User Constraints File UCF XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET SF_OE LOC C18 IOSTANDARD LVCMOS33 DRIVE 4 SF STS LOC B18 IOSTANDARD LVCMOS33 SF WE LOC D17 IOSTANDARD LVCMOS33 DRIVE 4 STMicro SPI serial Flash SPI some connections shared with SPI Flash DAC
79. F_A lt 10 gt SF_A lt 11 gt SF_A lt 12 gt SF_A lt 13 gt SF_A lt 14 gt SF A lt 15 gt SF_A lt 16 gt SF_A lt 17 gt SF_A lt 18 gt SF_A lt 19 gt SF_A lt 20 gt SF_A lt 21 gt SF_A lt 22 gt SF_A lt 23 gt SF_A lt 24 gt SF_BYTE SF_CEO SR D lt 1 gt SF_D lt 2 gt SF_D lt 3 gt SF_D lt 4 gt SF D lt 5 gt SF D lt 6 gt SF D 7 SF D B SF _ D lt 9 gt SF_D lt 10 gt SF_D lt 11 gt SF_D lt 12 gt SF_D lt 13 gt SF_D lt 14 gt SF_D lt 15 gt ri LOC J2 LOC 16 1 LOG gr LOC G3 LOC Di connection LOC B9 pins DA G4 J6 L5 R4 Intel StrataF IOSTANDARD SSTL2 I IOSTANDARD SSTL2 I IOSTANDARD SSTL2 I IOSTANDARD SSTL2 I IOSTANDARD SSTL2 I IOSTANDARD SSTL2 I to top DCM connection IOSTANDARD LVCMOS33 sh Parallel NOR Flash SF la LOC H17 LOC J13 LOC J12 LOC J14 LOC J15 LOC J16 LOC J17 LOC K14 LOC KLS LOC K12 LOC K13 OC oo 115 OC L16 LOC T18 LOC R18 LOC T17 LOC U18 LOC T16 LOC U15 LOC V15 LOC T12 LOC V13 LOC V12 LOC N11 LOC All LOC C YT LOC D16 LOC P10 LOC R10 LOC vg LOC U9 LOC R9 LOC M9 LOC N9 LOC R S LOC R16 LOC P17 LOC M15 LOC
80. IT B LOC T3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4 NET FPGA RDWR B LOC U10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4 NET FPGA HSWAP LOC B3 IOSTANDARD LVCMOS33 FX2 Connector FX2 NET FX2 CLKIN LOC E10 IOSTANDARD LVCMOS33 NET FX2 CLKIO LOC D9 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 CLKOUT LOC D10 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 These four connections are shared with the Jl 6 pin accessory header NET FX2 IO 1 LOC B4 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 2 LOC A4 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 3 LOC D5 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 4 LOC IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 These four connections are shared with the J2 6 pin accessory header NET FX2 IO 5 LOC IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 6 LOC B6 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 7 LOC E7 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 8 LOC F7 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 These four connections are shared with the J4 6 pin accessory header NET FX2 IO 9 LOC D7 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 10 LOC C7 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 11 LOC F8 IOSTANDARD LVCMOS33 SLEW FAST D
81. IVE 6 NET AMP DOUT LOC E18 IOSTANDARD LVCMOS33 Figure 10 5 UCF Location Constraints for the DAC Interface Analog to Digital Converter ADC The LTC1407A 1 provides two ADCS Both analog inputs are sampled simultaneously when the AD CONV signal is applied Interface Table 10 3 lists the interface signals between the FPGA and the ADC The SPI MOSI SPI MISO and SPI SCK signals are shared with other devices on the SPI bus The DAC CS signal is the active Low slave select input to the DAC The DAC CLR signal is the active Low asynchronous reset input to the DAC Table 10 3 ADC Interface Signals Signal FPGA Pin Direction Description SPI SCK U16 FPGA gt ADC Clock AD CONV Pil FPGA gt ADC Active High shutdown and reset SPI_MISO N10 FPGA ADC Serial data Master Input Serial Output Presents the digital representation of the sample analog values as two 14 bit two s complement binary values SPI Control Interface Figure 10 6 provides an example SPI bus transaction to the ADC When the AD CONV signal goes High the ADC simultaneously samples both analog channels The results of this conversion are not presented until the next time AD_CONV is asserted a latency of one sample The maxim sample rate is approximately 1 5 MHz The ADC presents the digital representation of the sampled analog values as a 14 bit two s complement binary value Spartan 3E Starter Kit Board U
82. J12 SF_A1 J13 SF_A0 H17 Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 www xilinx com 83 Chapter 11 Intel StrataFlash Parallel NOR Flash PROM EZ XILINX Table 11 1 FPGA to StrataFlash Connections StrataFlash FPGA Pin Category Signal Name Number Function SF D15 T8 Upper 8 bits of a 16 bit halfword when SE DIA R8 StrataFlash is SF D13 P6 configured for x16 data BEDS 7 SF BYTE High SF D11 M15 Connects to FPGA Signals SF_D lt 11 8 gt user I O connect to character SF_D10 S LCD pins DB 7 4 SF_D9 R16 SF_D8 R15 s SF D7 N9 Upper 7 bits of a data byte or lower 8 bits of a A SE D6 M9 16 bit halfword Connects to FPGA pins D 7 1 to support the BPI configuration SF_D5 R9 SF D4 U9 SF_D3 v9 SF_D2 R10 SF_D1 P10 SPI MISO N10 Bit 0 of data byte and 16 bit halfword Connects to FPGA pin D0 DIN to support the BPI configuration Shared with other SPI peripherals and Platform Flash PROM SF D16 StrataFlash Chip Enable Connects to FPGA pin LDCO to support the BPI configuration SF WE D17 StrataFlash VVrite Enable Connects to FPGA pin HDC to support the BPI configuration SF OE C18 StrataFlash Chip Enable Connects to FPGA pin LDC1 to support the BPI configuration 8 SE_BYTE C17 StrataFlash Byte Enable Connects to FPGA pin LDC2 to support the BPI configuration 0 x8 data 1 x16 data SF STS B18 StrataF
83. LEW SLOW NET SF A 20 LOC T12 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 19 LOC V15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 18 LOC U15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 17 LOC T16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 16 LOC U18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 15 LOC T17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 14 LOC R18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 13 LOC T18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 12 LOC L16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 11 LOC L15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 10 LOC K13 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 9 LOC K12 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 8 LOC K15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 7 LOC 14 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 6 LOC J17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 5 LOC J16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 4 LOC J15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 3 LOC J14 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 2
84. LOC J12 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 1 LOC J13 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 0 LOC H17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW Figure 11 2 UCF Location Constraints for StrataFlash Address Inputs Data Figure 11 3 provides the UCF constraints for the StrataFlash data pins including the I O pin assignment and the I O standard used NET SF D 15 LOC T8 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 14 LOC R8 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 13 LOC P6 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 12 LOC M16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 11 LOC M15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 10 LOC P17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 9 LOC R16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 8 LOC R15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 7 LOC N9 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 6 LOC M9 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 5 LOC R9 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 4 LOC U9 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_D lt 3 gt LOC V9 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_D lt 2 gt
85. M type as shown in Figure 12 8 Select from any of the PROM File Formats the Intel Hex format MCS is popular The PROM Formatter automatically swaps the bit direction as SPI Flash PROMs shift out the most significant bit MSB first Enter the Location of the directory and the PROM File Name Click Next gt when finished 92 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Configuring from SPI Flash iMPACT Prepare PROM Files fel EZ want to target a C Xilins PROM C Generic Parallel PROM 3rd Party SPI PROM PROM File Format M S C TEK E format C EX C B N St C HEX M Swap Bits Ehecksum Fill Value 2 Hex Digits FF PROM File Name MySPlFlash Location C data my_designs s3e_starter_kit Browse UG230_c15_07_030206 Figure 12 8 Choose the PROM Target Type the Data Format and File Location The Spartan 3E Starter Kit board has a 16 Mbit SPI serial Flash PROM Select 16M from the drop list as shown in Figure 12 9 Click Next gt iMPACT Specify SPI PROM Device ex mj E3 Auto Select PROM Density Select SPI PROM Density bits 128K lt Back Cancel UG230_c15_08_030206 Figure 12 9 Choose 16M Spartan 3E Starter Kit Board User Guide www xilinx com 93 UG230 v1 0 March 9 2006 Chapter 12 SPI Serial Flash XILINX The PROM Formatter then echoes the settings
86. M16 LOC P6 LOC R8 38 IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS IOS l ANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 TANDARD LVCMOS33 IOS TANDARD LVCMOS33 DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI DRIVI A D A DES DB D D D BJ DL DLE DS OD DS D BJ D
87. NET SF_D lt 11 gt LOC M15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW Discrete LEDs LED These are shared connections with the FX2 connector NET LED lt 0 gt LOC F12 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 1 gt LOC E12 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 2 gt LOC Ell IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 3 gt LOC F11 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 4 gt LOC Cli IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED 5 LOC D11 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 OO OO OO OO OO OO OO OO OO OO OO OO CO OO SLOW SLOW SLOW SLOW Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 www xilinx com 161 Appendix B Example User Constraints File UCF XILINX NET NET LED lt 6 gt LOC E9 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 LED lt 7 gt LOC F9 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 PS 2 Mouse Keyboard Port PS2 PS2 CLK LOC G14 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW PS2_DATA LOC G13 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW Rota
88. Oscillator Socket Controlled by Jumper JP9 CLK_AUX B8 Platfrm Flash L peers rg XILINX 1 SPA ETAN 3E 7 XILINX 4 AL 7 Bw Wu E SPARTA TAN 3E 7 A 7 4 Z On Board 50 MHz Oscillator SMA Connector CLK_50MHz C9 CLK_SMA A10 UG230_c3_01_030306 Figure 3 1 Available Clock Inputs Spartan 3E Starter Kit Board User Guide www xilinx com 21 UG230 v1 0 March 9 2006 Chapter 3 Clock Sources XILINX Clock Connections Each of the clock inputs connect directly to a global buffer input in I O Bank 0 along the top of the FPGA As shown in Table 3 1 each of the clock inputs also optimally connects to an associated DCM Table 3 1 Clock Inputs and Associated Global Buffers and DCMs Clock Input FPGA Pin Global Buffer Associated DCM CLK 50MHZ C9 GCLK10 DCM X0Y1 CLK AUX B8 GCLKS8 DCM X0Y1 CLK SMA A10 GCLK7 DCM X1Y1 Voltage Control The voltage for all I O pins in FPGA I O Bank 0 is controlled by jumper JP9 Consequently these clock resources are also controlled by jumper JP9 By default JP9 is set for 3 3V The on board oscillator is a 3 3V device and might not perform as expected when jumper JP9 is set for 2 5V 50 MHz On Board Oscillator The board includes a 50 MHz oscillator with a 4076 to 6096 output duty cycle The oscillator is accurate to 2500 Hz or 50 ppm Auxiliary Clock Oscillator Socket The provided 8 pin socket accepts clock oscillators that fit the 8 pin
89. Programmable Gain Each analog channel has an associated programmable gain amplifier see Figure 10 2 Analog signals presented on the VINA or VINB inputs on header J7 are amplified relative to 1 65V The 1 65V reference is generated using a voltage divider of the 3 3V voltage supply The gain of each amplifier is programmable from 1 to 100 as shown in Table 10 2 Table 10 2 Programmable Gain Settings for Pre Amplifier 2 1 A0 Input Voltage Range B3 B2 B1 B0 Minimum Maximum 0 0 0 0 0 1 0 0 0 1 0 4 29 2 0 0 1 0 1 025 2 275 Spartan 3E Starter Kit Board User Guide www xilinx com 75 UG230 v1 0 March 9 2006 Chapter 10 Analog Capture Circuit Table 10 2 Programmable Gain Settings for Pre Amplifier Continued EZ XILINX A3 A2 A1 A0 Input Voltage Range B3 B2 B1 BO Minimum Maximum 5 0 0 1 1 1 4 1 9 10 0 1 0 0 1 525 1 775 20 0 1 0 1 1 5875 1 7125 50 0 1 1 0 1 625 1 675 100 0 1 1 1 1 6375 1 6625 SPI Control Interface Figure 10 3 highlights the SPI based communications interface with the amplifier The gain for each amplifier is sent as an 8 bit command word consisting of two 4 bit fields The most significant bit B3 is sent first AMP_DOUT o Slave LTC2624 1 sls Bo B B2 Bo I I I A Gain B Gain SPI MOSI Spartan 3E AMP CS a FPGA SPI SCK Master
90. RIVE 8 NET FX2 IO 12 LOC E8 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 The discrete LEDs are shared with the following 8 FX2 connections ENET FX2_IO lt 13 gt LOC F9 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 ENET FX2 IO 14 LOC E9 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 FNET FX2 IO 15 LOC D11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 FNET FX2 IO 16 LOC C11 TOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 FNET FX2 IO 17 LOC F11 TOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 FNET FX2 IO 18 LOC Ell IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 FNET FX2 IO 19 LOC E12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 FNET FX2 IO 20 LOC F12 TOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 21 LOC A13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO lt 22 gt LOC B13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 23 LOC A14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO lt 24 gt LOC B14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 25 LOC C14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO lt 26 gt LOC D14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 160 www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 EZ XILINX
91. RXD1 RXD2 RXD3 RX_ER RXD4 TX_EN RX DU RX CLK TX_CLK COL CRS CLKIN XTAL1 XTAL2 CLK_FREQ Analog GND R47 49 9 7 c51 1 uF Bypass Capacitors 3U3 C36 C37 C38 39 C48 18nF 10nF 10nF 0 m 4 7uF 3U3 C43 C44 1 nF 4 Zur C45 C46 C47 C48 49 0 1 nF 1 nF 1 nF 1 nF 8 4 7uF Spartan 3E Starter Board Digilent Inc Copyright 2005 2006 Engineer CC SHEET Ethernet Interface Author GMA TITLE Doc S3E Starter 500 087 Date 02 02 06 Sheet 4 14 XNITIX 4o 2 uuo2 11 pue s n uBey AHd 19uJ8u13 Appendix A Schematics yx XILINX Voltage Regulators IC7 is a Texas Instruments TPS75008 triple output regulator The regulator provides 1 2V to the FPGA s VCCINT supply input 2 5V to the FPGA s VCCAUX supply input and 3 3V to other components on the board and to the FPGA s VCCO supply inputs on I O Banks 0 1 and 2 Jumpers JP6 and JP7 provide a means to measure current across the FPGA s VCCAUX and VCCINT supplies respectively IC8 is a Linear Technology LT3412 regulator providing 2 5V to the on board DDRSDRAM Resistors R65 and R67 create a voltage divider to create the termination voltage required for the DDR SDRAM interface IC9 is a 1 8V supply to the Embedded USB download debug circuit and to the CPLD s VCCINT supply input 138 www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1
92. SLEW SLOW DRIVE 6 NET J1 lt 3 gt LOC C5 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 6 pin header J2 These are shared connections with the FX2 connector NET J2 lt 0 gt LOC IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J2 lt 1 gt LOC B6 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J2 lt 2 gt LOC E7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J2 lt 3 gt LOC F7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 6 pin header J4 These are shared connections with the FX2 connector NET J4 lt 0 gt LOC D7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J4 lt 1 gt LOC C7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J4 lt 2 gt LOC IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J4 lt 3 gt LOC E8 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 Character LCD LCD NET LCD_E LOC M18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET LCD_RS LOC L18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET LCD_RW LOC L17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW LCD data connections are shared with StrataFlash connections SF_D lt 11 8 gt NET SF_D lt 8 gt LOC R15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW NET SF_D lt 9 gt LOC R16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW NET SF_D lt 10 gt LOC P17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW S
93. Spartan 3E Starter Kit Board User Guide Click a component to jump to the related documentation Not all UG230 v1 0 March 9 2006 components have active links Planie Flagi 3 nun P TEXAS INSTRUMENTS EXUNC k DIGILENT SSPARTAN 3E 4 Flash Memory altata uttu ada Alata XILINX gt XILINX Xilinx is disclosing this Document and Intellectual Property hereinafter the Design to you for use in the development of designs to operate on or interface with Xilinx FPGAs Except as stated herein none of the Design may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of the Design may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes Xilinx does not assume any liability arising out of the application or use of the Design nor does Xilinx convey any license under its patents copyrights or any rights of others You are responsible for obtaining any rights you may require for your use or implementation of the Design Xilinx reserves the right to make changes at any time to the Design as deemed desirable in the sole discretion of Xilinx Xilinx assumes no obligation to correct any errors contained herein
94. T SF D 8 LOC R15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_D lt 9 gt LOC R16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_D lt 10 gt LOC P17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_D lt 11 gt LOC M15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW Figure 5 2 UCF Location Constraints for the Character LCD LCD Controller The 2 x 16 character LCD has an internal Sitronix ST7066U graphics controller that is functionally equivalent with the following devices Samsung S6A0069X or KS0066U e Hitachi HD44780 SMOS SED1278 Memory Map The controller has three internal memory regions each with a specific purpose The display must be initialized before accessing any of these memory regions DD RAM The Display Data RAM DD RAM stores the character code to be displayed on the screen Most applications interact primarily with DD RAM The character code stored in a DD RAM location references a specific character bitmap stored either in the predefined CG ROM character set or in the user defined CG RAM character set Figure 5 3shows the default address for the 32 character locations on the display The upper line of characters is stored between addresses 0x00 and 0x0F The second line of characters is stored between addresses 0x40 and 0x4F Character Display Addresses z e a a
95. Z spi mso 3 AM 2 XL M 2 2 5 The A D converter sets its SDO output line to high impedance after 33 SPI SCK clock cycles UG230 c10 06 022306 Figure 10 7 Detailed SPI Timing to ADC UCF Location Constraints Figure 10 8 provides the User Constraint File UCF constraints for the amplifier interface including the I O pin assignment and I O standard used NET AD CONV LOC P11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 NET SPI SCK LOC U16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET SPI MISO LOC N10 IOSTANDARD LVCMOS33 Figure 10 8 UCF Location Constraints for the ADC Interface 78 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Disable Other Devices on the SPI Bus to Avoid Contention Disable Other Devices on the SPI Bus to Avoid Contention The SPI bus signals are shared by other devices on the board It is vital that other devices are disabled when the FPGA communicates with the AMP or ADC to avoid bus contention Table 10 4 provides the signals and logic values required to disable the other devices Although the StrataFlash PROM is a parallel device its least significant data bit is shared with the SPI MISO signal The Platform Flash PROM is only potentially enabled if the FPGA is set up for Master Serial mode configuration Table 10 4 Disable Other Devices on SPI Bus Signal Disabled Device Disable Value SPI SS B
96. ails Shared SPI Bus with Peripherals After configuration the SPI Flash configuration pins are available to the application On the Spartan 3E Starter Kit board the SPI bus is shared by other SPI capable peripheral devices as shown in Figure 12 18 To access the SPI Flash memory after configuration the FPGA application must disable the other devices on the shared PCI bus Table 12 3 shows the signal names and disable values for the other devices Table 12 3 Disable Other Devices on SPI Bus Signal Disabled Device Disable Value DAC CS Digital to Analog Converter DAC 1 AMP CS Programmable Pre Amplifier 1 AD CONV Analog to Digital Converter ADC 0 SF CEO StrataFlash Parallel Flash PROM 1 FPGA INIT B Platform Flash PROM 1 Spartan 3E Starter Kit Board User Guide www xilinx com 99 UG230 v1 0 March 9 2006 Chapter 12 SPI Serial Flash XILINX Other SPI Flash Control Signals The M25P16 SPI Flash has two additional control inputs The active Low write protect input W and the active Low bus hold input HLD are unused and pulled High via an external pull up resistor Variant Select Pins VS 2 0 When in SPI configuration mode the FPGA samples the value on three pins labeled VS 2 0 to determine which SPI read command to issue to the SPI Flash For the M25P16 Flash VS 2 0 lt 1 1 1 gt issues the correct command sequence The VS 2 0 pins are pulled High externally via pull up resistors t
97. application has full read write access to the LCD Conversely when LCD read operations are disabled LCD RW Low then the FPGA application has full read write access to the StrataFlash memory Table 5 2 LCD StrataFlash Control Interaction SF CEO SF BYTE LCD RW Operation 1 X X StrataFlash disabled Full read write access to LCD X X 0 LCD write access only Full access to StrataFlash X 0 X StrataFlash in byte wide x8 mode Upper data lines are not used Full access to both LCD and StrataFlash Notes 1 X indicates a don t care can be either 0 or 1 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX UCF Location Constraints If the StrataFlash memory is in byte wide x8 mode SF BYTE Low the FPGA application has full simultaneous read write access to both the LCD and the StrataFlash memory In byte wide mode the StrataFlash memory does not use the SF D 15 8 data lines UCF Location Constraints Figure 5 2 provides the UCF constraints for the Character LCD including the I O pin assignment and the I O standard used NET LCD E LOC M18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET LCD RS LOC L18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET LCD RW LOC L17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW The LCD four bit data interface is shared with the StrataFlash NE
98. ard used NET SD BA 0 BOG Ko IOSTANDARD SSTL2 I NET SD BA 1 LOC K6 IOSTANDARD SSTL2 I NET SD CAS LOC C2 IOSTANDARD SSTL2 I NET SD CK N LOC Ja IOSTANDARD SSTL2 I NET SD CK P LOC J5 IOSTANDARD SSTL2 I NET SD CKE LOC K3 IOSTANDARD SSTL2 I NET SD CS LOC KA IOSTANDARD SSTL2_I NET SD_LDM LOC 2 QA IOSTANDARD SSTL2 I NET SD LDQS LOC L6 IOSTANDARD SSTL2 I NET SD RAS LOG Cl IOSTANDARD SSTL2 I NET SD UDM LOC 1 IOSTANDARD SSTL2 I NET SD UDOQS LOC G3 IOSTANDARD SSTL2 I NET SD WE LOC Di IOSTANDARD SSTL2 I Path to allow connection to top DCM connection NET SD CK FB LOC B9 IOSTANDARD LVCMOS33 Figure 13 4 UCF Location Constraints for DDR SDRAM Control Pins Reserve FPGA VREF Pins Five pins in I O Bank 3 are dedicated as voltage reference inputs VREF These pins cannot be used for general purpose I O in a design Prohibit the software from using these pins with the constraints provided in Figure 13 5 Prohibit VREF CONFIG CONFIG CONFIG CONFIG CONFIG PROHIBIT PROHIBIT pins PROHIBIT PROHIBIT PROHIBIT D2 G4 J6 L5 R4 Figure 13 5 UCF Location Constraints for StrataFlash Control Pins Related Resources e Xilinx Embedded Design Kit EDK http www xilinx com ise embedded design prod platform studio htm MT
99. arter kit s3e starter kit ipf Boundary Scan File Edit View Operations Options Output Debug Window Help le B D 0X 29 w m 1 x B 9 Scan i SelectMAP n E 22 Desktop Configu Program E SystemACE 35 0 iMPACT Modes venit Get Device ID x TDO Get Device Signature Usercode Assign New Configuration File Available Operations are z Program Figure 4 6 Right Click to Assign a Configuration File to the Spartan 3E FPGA UG 230 c4 07 022406 Spartan 3E Starter Kit Board User Guide www xilinx com 29 UG230 v1 0 March 9 2006 Chapter 4 FPGA Configuration Options XILINX If the original FPGA configuration file used the default StartUp clock source CCLK iMPACT issues the warning message shown in Figure 4 7 This message can be safely ignored When downloading via JTAG the iMPACT software must change the StartUP clock source to use the TCK JTAG clock source WARNING iMPACT 2257 Startup Clock has been changed to JtagClk in the bitstream stored in memory but the original bitstream file remains unchanged UG230_c4_08_022406 Figure 4 7 iMPACT Issues a Warning if the StartUp Clock Was Not CCLK To start programming the FPGA right click the FPGA and select Program The iMPACT software reports status during programming process Direct programming to the FPGA takes a f
100. ation from the display Transferring 8 Bit Data over the 4 Bit Interface After initializing the display and establishing communication all commands and data transfers to the character display are via 8 bits transferred using two sequential 4 bit operations Each 8 bit transfer must be decomposed into two 4 bit transfers spaced apart by at least 1 us as shown in Figure 5 6 The upper nibble is transferred first followed by the lower nibble An 8 bit write operation must be spaced least 40 us before the next communication This delay must be increased to 1 64 ms following a Clear Display command Initializing the Display After power on the display must be initialized to establish the required communication protocol The initialization sequence is simple and ideally suited to the highly efficient 8 bit PicoBlaze embedded controller After initialization the PicoBlaze controller is available for more complex control or computation beyond simply driving the display Povver On lnitialization The initialization sequence first establishes that the FPGA application vvishes to use the four bit data interface to the LCD as follovvs Wait 15 ms or longer although the display is generally ready when the FPGA finishes configuration The 15 ms interval is 750 000 clock cycles at 50 MHz e Write SF_D lt 11 8 gt 0x3 pulse LCD E High for 12 clock cycles Wait 4 1 ms or longer which is 205 000 clock cycles at 50 MHz e Write SF_D lt 11 8
101. ation image Select SPI Mode using Jumper Settings Header J12 XSPI Programming Remove the top jumper insert the bottom two as shown Jumper J11 IL DONE Pin LED Lights up when FPGA successfully configured PROG B Push Button Switch f Jumper JP8 XSPI Press and release to restart configuration When programming SPI Flash using XSPI utility insert jumper to hold PROG B pin Low UG230 c5 02 030906 Figure 12 3 Configuration Options for SPI Mode Setting the FPGA Mode Select Pins Set the FPGA configuration mode pins for SPI mode as shown in Figure 12 4 The location of the configuration mode jumpers J30 appears in Figure 12 3 UG230 c15 03 030206 Figure 12 4 Set Mode Pins for SPI Mode 90 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Configuring from SPI Flash Creating an SPI Serial Flash PROM File The following steps describe how to format an FPGA bitstream for an SPI Serial Flash PROM Setting the Configuration Clock Rate The FPGA supports a 12 MHz configuration clock rate when connected to an M25P16 SPI serial Flash Set the Properties for Generate Programming File so that the Configuration Rate is 12 as shown in Figure 12 5 See Generating the FPGA Configuration Bitstream File in the FPGA Configuration Options chapter for a more detailed description Regenerate the FPGA bitstream programming file with the new settings E Process Propertie
102. bit two s complement number represents values between 213 and 213 1 Therefore the quantity is scaled by 8192 or 213 See Programmable Pre Amplifier to control the GAIN settings on the programmable pre amplifier The reference design files provide more information on converting the voltage applied on VINA or VINB to a digital representation see Related Resources page 79 Programmable Pre Amplifier The LTC6912 1 provides two independent inverting amplifiers with programmable gain The purpose of the amplifier is to scale the incoming voltage on VINA or VINB so that it maximizes the conversion range of the DAC namely 1 65 1 25V Interface Table 10 1 lists the interface signals between the FPGA and the amplifier The SPI MOSI SPI MISO and SPI SCK signals are shared with other devices on the SPI bus The AMP CS signal is the active Low slave select input to the amplifier Table 10 1 AMP Interface Signals Signal FPGA Pin Direction Description SPI MOSI T4 FPGA gt AD Serial data Master Output Slave Input Presents 8 bit programmable gain settings as defined in Table 10 2 AMP CS N7 FPGA gt AMP Active Low chip select The amplifier gain is set when signal returns High SPI SCK U16 FPGA gt AMP Clock AMP SHDN P7 FPGA gt AMP Active High shutdown reset AMP_DOUT E18 FPGA AMP Serial data Echoes previous amplifier gain settings Can be ignored in most applications
103. ble Click Generate Programming File Generating the PROM File After generating the program file double click Generate PROM ACE or JTAG File to launch the iMPACT software as shown in Figure 4 13 Processes User Constraints H R Spnthesize X5T 28 R f Implement Design E 20 Generate Programming File 2 Programming File Generation ar Processes UG230 c4 14 022706 Figure 4 13 Double Click Generate PROM ACE or JTAG File After iMPACT starts double click PROM File Formatter as shown in Figure 4 14 Spartan 3E Starter Kit Board User Guide www xilinx com 33 UG230 v1 0 March 9 2006 Chapter 4 FPGA Configuration Options XILINX IMPACT desif l File Edit view Operations 2m Slaves erial po TS electMAP Desktop Configu e E SystemACE IMPACT Modes UG230_c4_15_022706 Figure 4 14 Double Click PROM File Formatter Choose Xilinx PROM as the target PROM type as shown in Figure 4 15 Select from any of the PROM File Formats the Intel Hex format MCS is popular Enter the Location of the directory and the PROM File Name Click Next gt when finished iMPACT Prepare PROM Files Ale F want to target a Xilins PROM C Generic Parallel PROM C 3rd Party SPI PROM PROM File Format MCS C TEK fE format C EXO C BIN au C HEX Swap Bits Checksum Fill Value 2 Hex Digits FF PROM File Name MyPlatformFlash Locatio
104. ciated driver software E UG230 c4 05 030306 Figure 4 4 Connect the USB Type B Connector to the Starter Kit Board Connector When the USB cable driver is successfully installed and the board is correctly connected to the PC a green LED lights up indicating a good connection 28 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Programming the FPGA CPLD or Platform Flash PROM via USB Programming via iMPACT After successfully compiling an FPGA design using the Xilinx development software the design can be downloaded using the iMPACT programming software and the USB cable To begin programming connect the USB cable to the starter kit board and apply power to the board Then double click Configure Device iMPACT from within Project Navigator as shown in Figure 4 5 Processes E HAO Gere Programming File 140 Programming File Generation F HP Generate PROM ACE or JTA ar Processes UG230_c4_06_022406 Figure 4 5 Double Click to Invoke iMPACT If the board is connected properly the iMPACT programming software automatically recognizes the three devices in the JTAG programming file as shown in Figure 4 6 If not already prompted click the first device in the chain the Spartan 3E FPGA to highlight it Right click the FPGA and select Assign New Configuration File Select the desired FPGA configuration file and click OK iMPACT C data my designs s3e st
105. d User Guide UG230 v1 0 March 9 2006 5 XILINX Chapter 9 Digital to Analog Converter DAC The Spartan 3E Starter Kit board includes an SPI compatible four channel serial Digital to Analog Converter DAC The DAC device is a Linear Technology LTC2624 quad DAC with 12 bit unsigned resolution The four outputs from the DAC appear on the J5 header which uses the Digilent 6 pin Peripheral Module format The DAC and the header are located immediately above the Ethernet RJ 45 connector as shown in Figure 9 1 Linear Tech LTC2624 Quad DAC 6 pin DAC Header J5 SPI MOSI T4 SPI MISO N10 SPI SCK U16 DAC CS N8 DAC CLR P8 UG230 c9 01 030906 Figure 9 1 Digital to Analog Converter and Associated Header SPI Communication As shown in Figure 92 the FPGA uses a Serial Peripheral Interface SPI to communicate digital values to each of the four DAC channels The SPI bus is a full duplex synchronous character oriented channel employing a simple four wire interface A bus master the FPGA in this example drives the bus clock signal SPI SCK and transmits serial data SPI MOSI to the selected bus slave the DAC in this example At the same time the bus slave provides serial data SPI MISO back to the bus master Spartan 3E Starter Kit Board User Guide www xilinx com 67 UG230 v1 0 March 9 2006 Chapter 9 Digital to Analog Converter DAC XILINX
106. device which in turn converts the logic value to the appropriate RS 232 voltage level Likewise the Maxim device converts the RS 232 serial input data to LVITL levels for the FPGA A series resistor between the Maxim output pin and the FPGA s RXD pin protects against accidental logic conflicts Hardware flow control is not supported on the connector The port s DCD DTR and DSR signals connect together as shown in Figure 7 1 Similarly the port s RTS and CTS signals connect together UCF Location Constraints Figure 7 2 and Figure 7 3 provide the UCF constraints for the DTE and DCE RS 232 ports respectively including the I O pin assignment and the I O standard used NET RS232 DTE RXD LOC UB IOSTANDARD LVTTL NET RS232 DTE TXD LOC M13 IOSTANDARD LVTTL DRIVE 8 SLEW SLOW Figure 7 2 UCF Location Constraints for DTE RS 232 Serial Port NET RS232 DCE RXD LOC R7 IOSTANDARD LVTTL NET RS232 DCE TXD LOC M14 IOSTANDARD LVTTL DRIVE 8 SLEW SLOW Figure 7 3 UCF Location Constraints for DCE RS 232 Serial Port 60 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Chapter 8 PS 2 MouselKeyboard Port The Spartan 3E Starter Kit board includes a PS 2 mouse keyboard port and the standard 6 pin mini DIN connector labeled J14 on the board Figure 8 1 shows the PS 2 connector and Table 8 1 shows the signals on the connecto
107. displays support multiple display resolutions and the VGA controller dictates the resolution by producing timing signals to control the raster patterns The controller produces TTL level synchronizing pulses that set the frequency at which current flows through the deflection coils and it ensures that pixel or video data is applied to the electron guns at the correct time Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location The Spartan 3E Starter Kit board uses three bits per pixel producing one of the eight possible colors shown in Table 6 1 The controller indexes into the video data buffer as the beams move across the display The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel Spartan 3E Starter Kit Board User Guide www xilinx com 55 UG230 v1 0 March 9 2006 Chapter 6 VGA Display Port 3 XILINX As shovvnin Figure 6 2 the VGA controller generates the horizontal sync HS and vertical sync VS timings signals and coordinates the delivery of video data on each pixel clock The pixel clock defines the time available to display one pixel of information The VS signal defines the refresh frequency of the display or the frequency at which all information on the display is redrawn The minimum refresh frequency is a function of the display s phosphor and electron beam intensity with prac
108. e Data to CG RAM or DDRAM 49 Read Data from CG RAM or DD RAM 50 Sadoc 0000080000 77 50 Four Bit Data Interface 50 Transferring 8 Bit Data over the 4 Bit Interface 51 Initializing thelbisplay b s 51 Power On Initialization 51 Display Conti euration sii ce ees Er a xama pe icd ay ksi 51 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 EZ XILINX Writing Data to the Display 52 Disabling the Unused LCD 52 Related Resources 52 Chapter 6 VGA Display Port Signal Timing for a 60 Hz 640x480 VGA Display 54 VGA Signal Timing Ra dues e Ug iO etc e a H la 56 UCF Location Constraints 57 Related Resources 57 Chapter 7 RS 232 Serial Ports Chapter 8 PS 2 Mouse Keyboard Port Keyboard adda Cea op eit and be ab p Rare 62 huir ee nee ee ernsten 64 Voltage Supply c Oe BE RE 65 UCF Location Constraints 65 Related Resources
109. e a ee ERE SERE ab az ar s s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 re 40 Figure 5 3 DD RAM Hexadecimal Addresses No Display Shifting Spartan 3E Starter Kit Board User Guide www xilinx com 43 UG230 v1 0 March 9 2006 Chapter 5 Character LCD Screen XILINX The CG RAM address counter can either remain constant after read or write operations or auto increments or auto decrements by one location as defined by the I D set by the Entry Mode Set command Figure 5 5 provides an example creating a special checkerboard character The custom character is stored in the fourth CG RAM character location which is displayed when a DD RAM location is 0x03 To write the custom character the CG RAM address is first initialized using the Set CG RAM Address command The upper three address bits point to the custom character location The lower three address bits point to the row address for the character bitmap The Write Data to CG RAM or DD RAM command is used to write each character bitmap row A T lights a bit on the display A 0 leaves the bit unlit Only the lower five data bits are used the upper three data bits are don t care positions The eighth row of bitmap data is usually left as all zeros to accommodate the cursor Upper Nibble Lower Nibble Write Data to CG RAM or DD RAM A5 A4 A3 A2 A1 AO D7 D6 D5 D4 D3 D D1 DO Character Address Row Address Don t Care Character Bitmap
110. e amplifier AMP and two channel Analog to Digital Converter ADC The diagram in the lower left corner shows the JTAG chain See Chapter 15 Expansion Connectors for additional information 132 www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 9002 6 Yen 0 14 oeeon Spiny s sn P eog 13 15 3e ueueds UJOO XUI DCAAWM 661 1 V aniJ 1 us oneuieuos 908120 10 ev oecon 000 NO OI QN SPARTAN 3E Digilent Inc SPARTAN 3E Xilinx com 6 Pin Header Accesory OO NOA O O NO 399099 IC1 7416125 390099 tol c nr ICIPWR 7416125 e 390999 D A and A D header 399999 EEE tirir 1 2 3 4 5 6 7 8 9 2 1 2 3 4 5 6 7 8 9 2 1 2 3 4 5 6 7 8 9 40 5 m JTAG Scan Chain OOOOOOOOOO0009000000000000Q w N a o JT G gt b S3E FPGA gt XCF04S XCF04S 2 64 USB Dounload No Load on 5 die Spartan 3E Starter Board Digilent Inc Copyright 2005 2006 Engineer CC Author GMA Xx Intel Linear Texas Platform ST SMSC Strataflash Technology Instruments Flash Micro Doc 500 087 Date 02 02 06 Sheet 1 14 XNIIX JopeaH Ss lio1939uuoo pue sjepeaH uid 9 pp H uoisuedx3 zx4 Appendix A Schematics yx XILINX RS 232 Ports VGA Port and PS 2 Port IC2 is the Maxim LVTTL to RS 232 level converter One of the serial channels connects to a female DB9 DCE c
111. ead data from CG RAM if the command follows a previous Set CG RAM Address command After the read operation the address is automatically incremented or decremented by 1 according to the Entry Mode Set command However a display shift is not executed during read operations Execution Time 40 us Operation Four Bit Data Interface The board uses a 4 bit data interface to the character LCD Figure 5 6 illustrates a write operation to the LCD showing the minimum times allowed for setup hold and enable pulse length relative to the 50 MHz clock 20 ns period provided on the board cons sona N ve LCD_RW LCD_E Upper Lower 4 bits 4 bits LCD_RS N XCC xT SF D 11 8 NN I NN NN LCD RV N UZ U ED L 7 N U UZ LCDE IT I _______ 1 us 40 us UG230 c5 03 022006 Figure 5 6 Character LCD Interface Timing 50 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Operation The data values on SF_D lt 11 8 gt and the register select LCD_RS and the read write LCD RW control signals must be set up and stable at least 40 ns before the enable LCD E goes High The enable signal must remain High for 230 ns or longer the equivalent of 12 or more clock cycles at 50 MHz In many applications the LCD RW signal can be tied Low permanently because the FPGA generally has no reason to read inform
112. evices on the board It is vital that other devices are disabled when the FPGA communicates with the DAC to avoid bus contention Table 9 2 provides the signals and logic values required to disable the other devices Although the StrataFlash PROM is a parallel device its least significant data bit is shared with the SPI_MISO signal 68 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX SPI Communication Table 9 2 Disabled Devices on the SPI Bus Signal Disabled Device Disable Value SPI_SS_B SPI serial Flash 1 AMP_CS Programmable pre amplifier 1 AD_CONV Analog to Digital Converter ADC 0 SF StrataFlash Parallel Flash PROM 1 FPGA INIT B Platform Flash PROM 1 SPI Communication Details Figure 9 3 shows a detailed example of the SPI bus timing Each bit is transmitted or received relative to the SPI SCK clock signal The bus is fully static and supports clocks rate up to the maximum of 50 MHz However check all timing parameters using the LTC2624 data sheet if operating at or close to the maximum speed DAC CS SPI MOS XXXXX 31 AAA AAA 22 WWW SPI SCK _ NN N X sp uso ors roro o WW UG230 c9 03 021806 Figure 9 3 SPI Communication Waveforms After driving the DAC CS slave select signal Low the FPGA transmits data on the SPI MOSI signal MSB first The LTC2624 captures input data SPI MOSI on the rising edge of SPI S
113. ew seconds to less than a minute depending on the speed of the PC s USB port and the iMPACT settings iMPACT C data my_designs s3e_starter_kit s3e_starter_kit ipf Boundary Scan g File Edit View Operations Options Output Debug Window Help le Eli amp B x z x x xd 9 Boundary Scan i Gal laveSerial g l SeleciMAP t Gal Desktop Configu r ESwtemE gy k xc3s5t iMPACT Modes toplevel Get Device ID 7 Operations are my Program UG230_c4_09_022406 Figure 4 8 Right Click to Program the Spartan 3E FPGA TDO Get Device Signature Usercode Assign New Configuration File When the FPGA successfully programs the iMPACT software indicates success as shown in Figure 4 9 The FPGA application is now executing on the board and the DONE pin LED see Figure 4 2 lights up 30 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Programming the FPGA CPLD or Platform Flash PROM via USB iMPACT C data my designs s3e starter kit s3e starter kit ipf Boundary Scan File Edit View Operations Options Output Debug Window Help le H b eo Xxiii x 22 Boundary Scan t Gal SlaveS erial gt gaSelectMAP e g lDesktop Configu E E SystemACE gt xe3s500e xcf 4s 2 64 2 to
114. for the 32M x 16 DDR SDRAM e SMSC for the 10 100 Ethernet PHY e STMicroelectronics for the 16M x 1 SPI serial Flash PROM e Texas Instruments Incorporated for the three rail TPS75003 regulator supplying most of the FPGA supply voltages e Xilinx Inc Configuration Solutions Division for the XCF048 Platform Flash PROM and their support for the embedded USB programmer Xilinx Inc CPLD Division for the XC2C64A CoolRunner II CPLD Guide Contents This manual contains the following chapters e Chapter 1 Introduction and Overview provides an overview of the key features of the Spartan 3E Starter Kit board e Chapter 2 Switches Buttons and Knob defines the switches buttons and knobs present on the Spartan 3E Starter Kit board e Chapter 3 Clock Sources describes the various clock sources available on the Spartan 3E Starter Kit board e Chapter 4 FPGA Configuration Options describes the configuration options for the FPGA on the Spartan 3E Starter Kit board Spartan 3E Start Kit Board User Guide www xilinx com 9 UG230 v1 0 March 9 2006 Preface About This Guide XILINX e Chapter 5 Character LCD Screen describes the functionality of the character LCD screen e Chapter 6 VGA Display Port describes the functionality of the VGA port Chapter 7 RS 232 Serial Ports describes the functionality of the RS 232 serial ports Chapter 8 PS 2 Mouse Keyboard Port describes
115. ge ree pb ed RE dpa Rd een 146 XC2C64A CoolRunner II CPLD 148 Spartan 3E Starter Kit Board User Guide www xilinx com UG230 v1 0 March 9 2006 XILINX Linear Technology ADC and DAC 150 Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM 152 Buttons Switches Rotary Encoder and Character LCD 154 DDR SDRAM Series Termination and FX2 Connector Differential Termination 156 Appendix B Example User Constraints File UCF www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Preface About This Guide This user guide provides basic information on the Spartan 3E Starter Kit board capabilities functions and design It includes general information on how to use the various peripheral functions included on the board For detailed reference designs including VHDL or Verilog source code please visit the following web link Spartan 3E Starter Kit Board Reference Page http www xilinx com s3estarter Acknowledgements Xilinx wishes to thank the following companies for their support of the Spartan 3E Starter Kit board e Intel Corporation for the 128 Mbit StrataFlash memory e Linear Technology for the SPI compatible A D and D A converters the programmable pre amplifier and the power regulators for the non FPGA components e Micron Technology Inc
116. gh Impedance UG230 c15 15 030206 Figure 12 16 Installing the JP8 Jumper Holds the FPGA in Configuration State Re apply power to the Spartan 3E Starter Kit board Spartan 3E Starter Kit Board User Guide www xilinx com 97 UG230 v1 0 March 9 2006 Chapter 12 SPI Serial Flash XILINX Programming the SPI Flash with the XSPI Software Open a command prompt or DOS box and change to the XSPI installation directory The XSPI installation software also includes a short user guide in addition to XAPP445 Type xspi at the prompt to view quick help Type the following command at the prompt to program the SPI Flash using the SPI formatted Flash file generated earlier This verifies that the SPI Flash is indeed an M25P16 SPI Flash and then erases programs and finally verifies the Flash C xspi gt xspi spi dev m25p16 spi epv mcs i MySPIFlash mcs o output txt A disclaimer notice appears on the screen Press the Enter key to continue The entire programming process takes slightly longer than a minute as shown in Figure 12 17 lt Press ENTER to accept notice and continue gt Start Mon Feb 27 13 37 07 2006 gt Checking SPI device STMicro M25P16 ver 001001 ID code s density 120971521 bytes 1167772161 bits mfg code 0x20 memory type 0x20 density code 0x15 gt Operation Erase gt Operation Program and Verify using file MySPIFlash mcs Programmed 283776 of 283776 bytes w
117. gs Header J30 Select between three on board configuration sources DONE Pin LED PROG B Push Button Switch Lights up when FPGA successfully configured Press and release to restart configuration m f I 2 64 Macrocell Xilinx XC2C64A CoolRunner CPLD 4 Mbit Xilinx Platform Flash PROM Controller upper address lines in BPI mode and Configuration storage for Master Serial mode Platform Flash chip select User programmable UG230 c4 02 030906 Figure 4 2 Detailed Configuration Options The configuration mode jumpers determine which configuration mode the FPGA uses when power is first applied or whenever the PROG button is pressed The DONE pin LED lights when the FPGA successfully finishes configuration Pressing the PROG button forces the FPGA to restart its configuration process The 4 Mbit Xilinx Platform Flash PROM provides easy JTAG programmable configuration storage for the FPGA The FPGA configures from the Platform Flash using Master Serial mode The 64 macrocell XC2C64A CoolRunner II CPLD provides additional programming capabilities and flexibility when using the BPI Up BPI Down or MultiBoot configuration modes and loading the FPGA from the StrataFlash parallel Flash PROM The CPLD is user programmable Configuration Mode Jumpers As shown in Table 4 1 the J30 jumper block settings control the FPGA s configuration mode Inserting a jumper grounds the associated mode pin Insert or remove individual jumpers to
118. gt 0x3 pulse LCD E High for 12 clock cycles e Wait 100 us or longer which is 5 000 clock cycles at 50 MHz e Write SF_D lt 11 8 gt 0x3 pulse LCD E High for 12 clock cycles e Wait 40 us or longer which is 2 000 clock cycles at 50 MHz Write SF_D lt 11 8 gt 0x2 pulse LCD E High for 12 clock cycles e Wait 40 us or longer which is 2 000 clock cycles at 50 MHz Display Configuration After the power on initialization is completed the four bit interface is now established The next part of the sequence configures the display e Issue a Function Set command 0x28 to configure the display for operation on the Spartan 3E Starter Kit board e Issue an Entry Mode Set command 0x06 to set the display to automatically increment the address pointer e Issue a Display On Off command 0x0C to turn the display on and disables the cursor and blinking Spartan 3E Starter Kit Board User Guide www xilinx com 51 UG230 v1 0 March 9 2006 Chapter 5 Character LCD Screen XILINX e Finally issue a Clear Display command Allow at least 1 64 ms 82 000 clock cycles after issuing this command Writing Data to the Display To write data to the display specify the start address followed by one or more data values Before writing any data issue a Set DD RAM Address command to specify the initial 7 bit address in the DD RAM See Figure 5 3 for DD RAM locations Write data to the display using a Write Data to CG RAM or DD R
119. heral Modules http vvvvvv digilentinc com Products Catalog cfm Nav1 Products amp Nav2 Peripheral amp Cat Peripheral Spartan 3E Starter Kit Board User Guide www xilinx com 71 UG230 v1 0 March 9 2006 Chapter 9 Digital to Analog Converter DAC 3 XILINX 72 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 5 XILINX Chapter 10 Analog Capture Circuit The Spartan 3E Starter Kit board includes a two channel analog capture circuit consisting of a programmable scaling pre amplifier and an analog to digital converter ADC as shown in Figure 10 1 Analog inputs are supplied on the J7 header 6 pin ADC Header J7 Linear Tech LTC1407A 1 Dual A D SPI SCK U16 AD CONV P11 SPI MISO N10 Linear Tech LTC6912 1 Dual Amp SPI MOSI T4 AMP CS N7 SPI SCK U16 AMP SHDN P7 AMP DOUT E18 UG230 c10 01 030306 Figure 10 1 Two Channel Analog Capture Circuit The analog capture circuit consists of a Linear Technology LTC6912 1 programmable pre amplifier that scales the incoming analog signal on header J7 see Figure 10 2 The output of pre amplifier connects to a Linear Technology LTC1407A 1 ADC Both the pre amplifier and the ADC are serially programmed or controlled by the FPGA Spartan 3E Starter Kit Board User Guide www xilinx com 73 UG230 v1 0 March 9 2006 Chapter 10 Analog Capture Circuit XILINX Header J7 ge LTC
120. how to specify a pull down resistor within the UCF There is no active debouncing circuitry on the push button 16 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Rotary Push Button Switch Push Button FPGA I O Pin 3 3V n Mam rT BTN Signal UG230 c2 03 021206 Figure 2 4 Push Button Switches Require an Internal Pull Down Resistor in FPGA Input Pin In some applications the BTN SOUTH push button switch is also a soft reset that selectively resets functions within the FPGA UCF Location Constraints Figure 2 5 provides the UCF constraints for the four push button switches including the I O pin assignment and the I O standard used and defines a pull down resistor on each input NET BTN EAST LOC H13 IOSTANDARD LVTTL PULLDOWN NET BTN NORTH LOC V4 IOSTANDARD LVTTL PULLDOWN NET BTN SOUTH LOC K17 IOSTANDARD LVTTL PULLDOWN NET BTN WEST LOC D18 IOSTANDARD LVTTL PULLDOWN Figure 2 5 UCF Constraints for Push Button Switches Rotary Push Button Switch Locations and Labels The rotary push button switch is located in the center of the four individual push button switches as shown in Figure 2 3 The switch produces three outputs The two shaft encoder outputs are ROT A and ROT B The center push button switch is ROT CENTER Operation The rotary push button switch integrates two
121. ine control equipment in hazardous environments requiring fail safe controls such as in the operation of nuclear facilities aircraft navigation or communications systems air traffic control life support or weapons systems High Risk Applications Xilinx specifically disclaims any express or implied warranties of fitness for such High Risk Applications You represent that use of the Design in such High Risk Applications is fully at your risk 2002 2006 Xilinx Inc All rights reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc All other trademarks are the property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 03 09 06 1 0a Initial release Spartan 3E Starter Kit Board User Guide www xilinx com UG230 v1 0 March 9 2006 Table of Contents Preface About This Guide Acknowledgements sii sci oper RET CER ur CBE etc e rie e ER ACA 9 Guide Contents 9 Additional Resources 10 Chapter 1 Introduction and Overview Choose the Starter Kit Board for Your Needs 11 Spartan 3E FPGA Features and Embedded Processing Functions 11 Learning Xilinx FPGA CPLD and ISE Development Software Basics
122. ing Platform Flash PROM via USB 31 Generating the FPGA Configuration Bitstream File 31 Generating the PROM Eile Lu ase 220 nd Fue sulun 33 Programming the Platform Flash PROM 37 Chapter 5 Character LCD Screen OVERVIEW M D UE PI EE 41 Character LCD Interface Signals 42 Voltage Compatibility RE EE a Nap dU de un 42 Interaction with Intel StrataFlash 42 UCF Location Constraints 43 LCD Controller 43 Memory ui en 77 43 DORAM san sus a ken an daa ae ee o ee e D ds 43 CG ROM 5b aaa 44 CO RAM ee n ss ssa 45 Command Set u iiis uuu y dala a adla Bo a RIA a Lee Le 46 Disabled P 08000 aaa kaqkus kusaka 0 ee 47 Clear pis 47 Return Cursor H me a ae nee eine alaya ip etn d b 47 Entry Modeset ed 47 Display 0020101000 48 Cursorand Display Shift ann ee E ae 48 iah adan as 49 Set RAM Address 49 Set DDRAM Address nu e a lec dee s 49 Read Busy Flag and Address 49 Writ
123. irose 100 pin FX2 connector and the associated FPGA pin connections The FX2 connect has two rows of connectors both with 50 connections each shown in the table using light yellow shading Table 15 1 also highlights the shared connections to the eight discrete LEDs the three 6 pin Accessory Headers J1 J2 and J4 and the connectorless debugging header J6 114 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Hirose 100 pin FX2 Edge Connector J3 Table 15 1 Hirose 100 pin FX2 Connector Pinout and FPGA Connections J3 Shared Header Connections FX2 Connector Signal Name FPGA Pin LED J1 J2 JP4 J6 rem PEN FPGA Pin Signal Name 1 1 SHIELD 2 2 GND TMS_B 3 3 TDO_XC2C JTSEL 4 4 TCK_B TDO_FX2 5 5 FX2_IO1 B4 6 6 FX2 IO2 A4 7 7 FX2 1 D5 o o 8 8 FX2 IO4 C5 9 9 2 IO5 A6 10 10 FX2 IO6 B6 il 11 FX2 IO7 E7 12 12 FX2_IO8 F7 13 13 FX2 IO9 D7 14 14 2 IO10 C7 15 15 2 1011 F8 9 16 16 FX2 IO12 E8 Z 17 FX2_1013 F9 LD7 18 18 2 1014 9 LD6 19 19 2 1015 011 LD5 20 20 FX2 1016 C11 LD4 o 21 21 FX2 IO17 F11 LD3 22 22 FX2 IO18 Ell LD2 23 23 2 1019 12 24 24 2 1 20 F12 LDO 25 25 FX2 IO21 A13 26 26 FX2 IO22 B13 27 FX2 1023 A14 28 28 FX2 IO24 B14 29 29 FX2_IO25 C1
124. k must be installed between TDI and TDO on the JTAG header to complete the scan chain when the JTAG signals are being driven from a peripheral board position rather than the JTAG Interface Header or the Embedded Platform USB Cable Jumper Block Storage T Spartan 3E Starter Boar d 8 Digilent Inc Copyright 2005 2006 Engineer CC gt B SHEET XC3SE Contiguration and JT G Author GMA TITLE S3E Starter 8 Docs 500 087 Date 02 02 06 Sheet 6 14 A suonoeuuo HYLF 1881 2495 145 IWOHd USel4 sPunes suoneanfijuo v9d3 Appendix A Schematics yx XILINX FPGA VO Banks and 1 Oscillators IC10BO represents the connections to 1 O Bank 0 on the FPGA The VCCO input to Bank 0 is 3 3V by default but can be set to 2 5V using jumper JP9 IC10B1 represents the connections to I O Bank 1 on the FPGA IC17 is the 50 MHz clock oscillator Chapter 3 Clock Sources for additional information IC16 is an 8 pin DIP socket to insert an alternate clock oscillator with a different frequency 142 www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 9002 6 Yen 0 14 oeeon epin5 s sn P eog 13 815 3e ueueds XUI DCMMM v 9 v einBi4 2 18 us oneuieuos 908120 90 EV 0ez9N UCC for Bank is set Bu JP9 on Sheet 9 AD A D Converter 11 101 1P3 Ip4 X Ips IP L2P IP_L2N IP_L7P IP_L7N IP_L1QP IP L10N IP L16P IP L
125. lash Status signal Connects to FPGA user I O pin 84 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Shared Connections Shared Connections Besides the connections to the FPGA the StrataFlash memory shares some connections to other components Character LCD The character LCD uses a four bit data interface The display data connections are also shared with the SF_D lt 11 8 gt signals on the StrataFlash PROM As shown in Table 11 2 the FPGA controls access to the StrataFlash PROM or the character LCD using the SF_CE0 and LCD_RW signals Table 11 2 FPGA Control for StrataFlash and LCD SF CEO LCD RW Function 1 1 The FPGA reads from the character LCD 0 0 The FPGA accesses the StrataFlash PROM Xilinx XC2C64A CPLD The Xilinx XC2C64A CoolRunner CPLD controls the five upper StrataFlash address lines SF A 24 20 during configuration The four upper BPI mode address lines from the FPGA A lt 23 20 gt are not connected Instead four FPGA user I O pins connect to the StrataFlash PROM upper address lines SF A 23 0 See Chapter 16 XC2C64A CoolRunner II CPLD for more information The most significant address line SF A 24 is not physically used on the 16 Mbyte StrataFlash PROM It is provided for upward migration to a larger StrataFlash PROM in the same package footprint Likevvsie the SF A 24 signal is also connected to
126. lopment software consider using the High Volume Starter Kit Bundle which includes both a Spartan 3 FPGA development board and a Xilinx CoolRunner II XC9500XL CPLD development board at a very affordable price High Volume Starter Kit Bundle HW SPAR3 CPLD DK http www xilinx com xlInx xebiz designResources ip product details jsp key HW SPAR3 CPLD DK Advanced Spartan 3 Generation Development Boards The Spartan 3E Starter Kit board demonstrates the basic capabilities of the MicroBlaze embedded processor and the Xilinx Embedded Development Kit EDK For more Spartan 3E Starter Kit Board User Guide www xilinx com 11 UG230 v1 0 March 9 2006 Chapter 1 Introduction and Overview XILINX advanced development on a board with additional peripherals and FPGA logic consider the SP 305 Development Board Spartan 3 SP 305 Development Board HW SP305 xx http www xilinx com xlnx xebiz designResources ip_product_details jsp key HW SP305 US Also consider the capable boards offered by Xilinx partners Spartan 3 and Spartan 3E Board Interactive Search http www xilinx com products devboards index htm Key Components and Features The key features of the Spartan 3E Starter Kit board are Xilinx XC3S500E Spartan 3E FPGA Up to 232 user I O pins 320 pin FBGA package Over 10 000 logic cells Xilinx 4 Mbit Platform Flash configuration PROM Xilinx 64 macrocell XC2C64A CoolRunner CPLD 64 MByte 512
127. n C data my_designs s3e_starter_kit Browse lt Back Cancel UG230 c4 16 022706 Figure 4 15 Choose the PROM Target Type the Data Format and File Location 34 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Programming the FPGA CPLD or Platform Flash PROM via USB The Spartan 3E Starter Kit board has an XCF04S Platform Flash PROM Select xc 04s from the drop list as shown in Figure 4 16 Click Add then click Next gt iMPACT Specify Xilinx PROM Device I rg x Auto Select PROM Enable Revisioning Number of Revisions 1 Enable Compression Select a PROM sch xi xc 4s 524288 Add xcf 1s 131072 xcf 2s 262144 xcfOds 524288 xcf08p 1048575 xcfl6p 2097152 xcf32p 4194304 Delete All UG230_c4_17_022706 Figure 4 16 Choose the XCF04S Platform Flash PROM The PROM Formatter then echoes the settings as shown in Figure 4 17 Click Finish You have entered following information PROM Type Serial File Format mes Fill Value FF PROM filename MyPlatformFlash Number of PROMs 1 Elick Finish to start adding device files Cancel UG230_c4_18_022706 Figure 4 17 Click Finish after Entering PROM Formatter Settings The PROM Formatter then prompts for the name s of the FPGA configuration bitstream file As shown in Figure 4 18 click OK to start selecting files Select a
128. n SF D c115 M15 Data bit DB7 Shared with StrataFlash pins SF_D lt 10 gt P17 Data bit DB6 s p SF_D lt 9 gt R16 Data bit DB5 SF_D lt 8 gt R15 Data bit DB4 LCD E M18 Read Write Enable Pulse 0 Disabled 1 Read Write operation enabled LCD_RS L18 Register Select 0 Instruction register during write operations Busy Flash during read operations 1 Data for read or write operations LCD RW L17 Read Write Control 0 VVR TE LCD accepts data 1 READ LCD presents data Voltage Compatibility The character LCD is power by 5V The FPGA I O signals are powered by 3 3V However the FPGA s output levels are recognized as valid Low or High logic levels by the LCD The LCD controller accepts 5V TTL signal levels and the 3 3V LVCMOS outputs provided by the FPGA meet the 5V TTL voltage level requirements The 390 series resistors on the data lines prevent overstressing on the FPGA and StrataFlash I O pins when the character LCD drives a High logic value The character LCD drives the data lines when LCD RW is High Most applications treat the LCD as a write only peripheral and never read from from the display Interaction with Intel StrataFlash As shown in Figure 5 1 the four LCD data signals are also shared with StrataFlash data lines SF D 11 8 As shown in Table 5 2 the LCD StrataFlash interaction depends on the application usage in the design When the StrataFlash memory is disabled SF High then the FPGA
129. n Figure 4 23 Right click the PROM icon then click Assign New Configuration File Select a previously generated PROM format file and click OK TDI gun Erase Blank Check xc3s500e xcf toplevel bit file Readback Get Device ID Get Device Checksum Get Device Signature Usercode Assign New Configuration File b Figure 4 23 Assign the PROM File to the 45 Platform Flash PROM UG230 c4 24 022806 To start programming the PROM right click the PROM icon and then click Program 38 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Programming the FPGA CPLD or Platform Flash PROM via USB TL verify xc3sS e xc taplevel bit myplattor Ham Tr Blank Check Readhark Get Device ID Get Device Checksum Get Device Signature Usercode amp ssign Mew Configuration File UG230 c4 25 022806 Figure 4 24 Program the 45 Platform Flash PROM The programming software again prompts for the PROM type to be programmed Select xcf04s and click OK as shown in Figure 4 25 r Select PR M Part Name xc 4s vi Cancel Help UG230_c4_26_022806 Figure 4 25 Select XCF04S Platform Flash PROM Before programming choose the programming options available in Figure 4 26 Checking the Erase Before Programming option erases the Platform Flash PROM completely before programming ensuring that
130. n Expansion Spartan 3E FPGA Connector 43 FX2 10 34 1 See Table See Table FX2_IP lt 38 35 gt See Table C3 C15 E10 See Table FX2 10 395 FX2 IP 405 FX2 CLKIN FX2 CLKOUT FX2 CLKIO D10 D9 Bank 0 Supply JP9 UG230 c12 02 022406 Figure 15 2 FPGA Connections to the Hirose 100 pin Edge Connector Three signals are reserved primarily as clock signals between the board and FX2 connector although all three connect to full I O pins Voltage Supplies to the Connector The Spartan 3E Starter Kit board provides power to the Hirose 100 pin FX connector and any attached board via two supplies see Figure 15 2 The 5 0V supply provides a voltage source for any 5V logic on the attached board or alternately provides power to any voltage regulators on the attached board A separate supply provides the same voltage at that applied to the FPGA s I O Bank 0 All FPGA I Os that interface to the Hirose connector are in Bank 0 The I O Bank 0 supply is 3 3V by default However the voltage level can be changed to 2 5V using jumper JP9 Some FPGA I O standards especially the differential standards such as RSDS and LVDS require a 2 5V output supply voltage To support high speed signals across the connector a majority of pins on the B side of the FX2 connector are tied to GND Connector Pinout and FPGA Connections Table 15 1 shows the pinout for the H
131. n FPGA bitstream file bit Choose No after selecting the last FPGA file Finally click OK to continue Spartan 3E Starter Kit Board User Guide www xilinx com 35 UG230 v1 0 March 9 2006 Chapter 4 FPGA Configuration Options XILINX Add Device r i Start adding device File bo 4 Data Stream Add Device Would you like to add another device File to Data Stream Add Device r i You have completed the device File entry 4 Click ba continue UG230 c4 19 022706 Figure 4 18 Enter FPGA Configuration Bitstream File s When PROM formatting is complete the iMPACT software presents the present settings by showing the PROM the select FPGA bitstream s and the amount of PROM space consumed by the bitstream Figure 4 19 shows an example for a single XC35500E FPGA bitstream stored in an XCF04S Platform Flash PROM xcf dz 34 13 Full 355006 myfpaabitstream UG230 c4 20 022706 Figure 4 19 PROM Formatting Completed 36 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Programming the FPGA CPLD or Platform Flash PROM via USB To generate the actual PROM file click Operations gt Generate File asshovnin Figure 4 20 iMPACT C dabta my wdesigns s3e starter kit s3e File Edit View Operations Options Output Debug Ww J Eli x m as Program duy Verify fl Erase Compact Elash Integrity check UG230_c
132. n Figure 15 3b is a Spartan 3E feature called on chip differential termination which uses the DIFF TERM attribute available on differential I O signals Each differential I O pin includes a circuit that behaves like an internal termination resistor of approximately 1200 On chip differential termination is only available on I O pairs not on Input only pairs like pairs 15 and 16 in Table 15 2 Pads for 100 Differential termination B surface mount resistor LxxN LxxN Signal Signal LxxP 0 Hua g rt g a External 1000 termination resistor b On chip differential termination UG230 c12 03 022406 Figure 15 3 Differential Input Termination Options Figure 15 4 and Figure 15 5 show the locations of the differential input termination resistor landing pads on the top and bottom side of the board Table 15 2 indicates which resistor is associated with a specific differential pair r ur ES a un www xilinx con Seni X ICI 1 142 E gSPARTAN 3 entinc com int 2006 E 3 2 21226122 CI t z9 Zi a Peres 447 ey R n rd fT ST Flash UG230_c12_04_022406 Figure 15 4 Location of Termination Resistor Pads on Top Side of Board 118 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Hirose 100 pin FX2 Edge Connector 43 m R202 UG230 c12 05 022406 Figure 15 5 Location of Termination Resistor Pads on Bottom Side of
133. n SOIC and MLP packages is located in the top left corner However pin 1 for the 16 pin SOIC package is located in the top right corner because the package is rotated 90 The 16 pin SOIC package also have four pins on each side that do not connect on the board These pins must be left floating Why support multiple packages In a word flexibility The multi package layout provides Density migration between smaller and larger density SPI Flash PROMs Not all SPI Flash densities are available in all packages The SPI Flash migration strategy follows nicely with the pinout migration provided by Xilinx FPGAs e Consistent configuration PROM layout when migrating between FPGA densities The Spartan 3E FPGA s FG320 package footprint supports the XC3S500E the XC3S1200E and the XC3S1600E FPGA devices without modification The SPI Flash multi package layout allows comparable flexibility in the associated configuration PROM Ship the optimally sized SPI Flash memory for the FPGA mounted on the board 100 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Additional Design Details e Supply security If a certain SPI Flash density is not available in the desired package switch to a different package style or to a different density to secure availability I o Pin 1 i il 16 pin SOIC Do not connect VCC HOLD Do not connect S o ol Pin 1 8 pin SOIC
134. nd the host reads the data line when the clock signal is Low Table 8 2 PS 2 Bus Timing Symbol Parameter Min Max Tek Clock High or Low Time 30 us 50 us Tsy Data to clock Setup Time 5 Us 25 us Tup Clock to data Hold Time 5 Us 25 us Tek Tok Edge 0 Edge 10 HU dass 9 CLK PS2C J FT Teq 1 7 Hip DATA PS2D ng meni SOD DH UG230 c8 02 021806 Figure 8 2 PS 2 Bus Timing Waveforms The keyboard uses open collector drivers so that either the keyboard or the host can drive the two wire bus If the host never sends data to the keyboard then the host can use simple input pins A PS 2 style keyboard uses scan codes to communicate key press data Nearly all keyboards in use today are PS 2 style Each key has a single unique scan code that is sent whenever the corresponding key is pressed The scan codes for most keys appear in Figure 8 3 If the key is pressed and held the keyboard repeatedly sends the scan code every 100 ms or so When a key is released the keyboard sends an FO key up code followed by the scan code of the released key The keyboard sends the same scan code regardless if a key has different shift and non shift characters and regardless whether the Shift key is pressed or not The host determines which character is intended Some keys called extended keys send an E0 ahead of the scan code and furthermore they might send more than one scan code When an extended
135. niversal Scan SPI Flash programming tutorial in Related Resources page 102 e Additional programming support will be provided in the ISE 8 2i software Downloading the SPI Flash using XSPI The following steps describe how to download the SPI Flash PROM using the XSPI programming utility Download and Install the XSPI Programming Utility Download application note XAPP445 and the associated XSPI programming software see Related Resources page 102 Unzip the XSPI software onto the PC Attach a JTAG Parallel Programming Cable The XSPI programming utility uses a JTAG parallel programming cable such as e Xilinx Parallel Cable IV with flying leads Digilent JTAG3 programming cable These cables are not provided with the Spartan 3E Starter Kit board but can be purchased separately either from the Xilinx Online Store or from Digilent Inc see Related Resources page 102 First turn off the power on the Spartan 3E Starter Kit board If the USB cable is attached to the board disconnect it Simultaneously connecting both the USB cable and the parallel cable to the PC confuses the iMPACT software Connect one end of the JTAG parallel programming cable to the parallel printer port of the PC Connect the JTAG end of the cable to Header J12 as shown in Figure 12 15a The physical location of Header J12 is more clearly shown in Figure 12 3 page 90 The J12 header connects directly to the SPI Flash pins it is not connected
136. nology LTC1407A 1 two channel ADC IC20 is a Linear Technology LTC6912 programmable pre amplifier AMP to condition the analog inputs to the ADC See Chapter 10 Analog Capture Circuit for additional information IC21 is a Linear Technology LTC2624 four channel DAC See Chapter 9 Digital to Analog Converter DAC for additional information 150 www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 9002 6 Yen 0 14 oeeon Spiny s sn P eog 13 4815 3e ueueds LSL LL 3 us ILW YIS 0 V 2 6 908120 OF ev 0E29N SPI SDI SDO SCK SPI SDI SDO SCK LTC2624 SPI SDI SDO SCK DATA gt CLK CS LD SHDN OUTA VINA OUTB VINB 1 0640 gt AGND ND Thevenin Termination place at end of chain Spartan 3E Starter Board Digilent Inc Copyright 2005 2006 Engineer CC SHEET A D and D A Converters Author GMA TITLE S3E Starter Sheets 11 14 XNITIX 2va pue Jay A5ofouu l 1eeur Appendix A Schematics yx XILINX Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM 152 IC22 is a 128 Mbit 16 Mbyte Intel StrataFlash parallel NOR Flash PROM See Chapter 11 Intel StrataFlash Parallel NOR Flash PROM for additional information IC23 is a 512 Mbit 64 Mbyte Micron DDR SDRAM See Chapter 13 DDR SDRAM for additional information www xilinx com Spartan 3E Start Kit Board User Guide
137. o 3 3V The VS 2 0 pins are also parallel NOR Flash address lines A 19 17 in the FPGA s BPI configuration mode and these signals also connect to the StrataFlash parallel Flash PROM After SPI configuration the VS 2 0 pins become user programmable I O pins allowing full access to the StrataFlash PROM despite that the FPGA configured from SPI Flash Jumper Block J1 1 In SPI configuration mode the FPGA selects the attached SPI Flash by asserting the CSO B pin Low On the Spartan 3E Starter Kit board the CSO B pin drives into the jumper J11 block This jumper block provides the option to move the on board SPI Flash to a different select line SPI ALT CS JP11 This way a different SPI Flash device can be tested by changing the JP11 jumper settings and connecting the alternate SPI Flash on Header JP12 By default both jumpers are inserted on jumper block header J11 Programming Header J12 As shown in Figure 12 15 page 97 Header J12 accepts a JTAG parallel programming cable to program the on board SPI Flash Multi Package Layout STMicroelectronics was rather clever when they defined the package layout for the M25Pxx SPI serial Flash family The Spartan 3E Starter Kit board supports all three of the package types used for the 16 Mbit device as shown in Figure 12 19 By default the board ships with the 8 lead 8x6 mm MLP package The multi package layout also supports the 8 pin SOIC package and the 16 pin SOIC package Pin 1 for the 8 pi
138. oard User Guide UG230 v1 0 March 9 2006 XILINX Appendix A Schematics This appendix provides the following circuit board schematics FX2 Expansion Header 6 pin Headers and Connectorless Probe Header RS 232 Ports VGA Port and PS 2 Port Ethernet PHY Magnetics and RJ 11 Connector Voltage Regulators FPGA Configurations Settings Platform Flash PROM SPI Serial Flash JTAG Connections FPGA I O Banks 0 and 1 Oscillators FPGA I O Banks 2 and 3 Power Supply Decoupling XC2C64A CoolRunner CPLD Linear Technology ADC and DAC Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM Buttons Switches Rotary Encoder and Character LCD DDR SDRAM Series Termination and FX2 Connector Differential Termination Spartan 3E Start Kit Board User Guide www xilinx com 131 UG230 v1 0 March 9 2006 Appendix A Schematics yx XILINX FX2 Expansion Header 6 pin Headers and Connectorless Probe Header Headers 1 J2 and J4 are six pin connectors compatible with the Digilent Accessory board format Headers J3A and J3B are the connections to the FX2 expansion connector located along the right edge of the board Header J5 provides the four analog outputs from the Digital to Analog Converter DAC Header J6 is the landing pad for an Agilent or Tektronix connectorless probe Header J7 provides the two analog inputs to the programmable pr
139. obe such as those available from Agilent provides an interface to a logic analyzer This debugging port is intended primarily for the Xilinx ChipScope Pro software with the Agilent s FPGA Dynamic Probe It can however be used with either the Agilent or Tektronix probes without the ChipScope software using FPGA Editor s probe command Refer to Related Resources page 124 for more information on the ChipScope Pro tool probes and connectors Table 15 3 provides the connector pinout Only 18 FPGA pins attach to the connector the remaining connector pads are unconnected All 18 FPGA pins are shared with the FX2 connector J3 and the 6 pin accessory port connectors J1 J2 and 14 See Table 15 1 page 115 for more information on how these pins are shared Table 15 3 Connectorless Debugging Port Landing Pads J6 UG230 v1 0 March 9 2006 Connectorless Signal Name FPGA Pin Landing Pads FPGA Pin Signal Name FX2_IO1 B4 Al B1 FX2 IO2 A4 A2 B2 D5 FX2 IO3 GND GND A3 B3 C5 2 1 4 2 1 5 A6 A4 B4 GND GND FX2 IO6 B6 A5 B5 E7 FX2 IO7 GND GND A6 B6 F7 FX2 IO8 2 IO9 D7 A7 B7 GND GND FX2_IO10 C7 A8 B8 F8 FX2_IO11 GND GND A9 B9 E8 FX2 IO12 2 1013 F9 A10 B10 GND GND FX2 1014 E9 All B11 D11 2 1O15 GND GND A12 B12 C11 2 1016 2 1 17 F11 A13 B13 GND GND 2 IO18 E11 A14 B14 A15 B15 A16 B16 A17 B17
140. onnector 9 and the other connects to a male DB9 DTE connector 710 See Chapter 7 RS 232 Serial Ports for additional information Connector J14 is a PS 2 style mouse keyboard connector powered from 5 volts See Chapter 8 P5 2 Mouse Keyboard Port for additional information Connector J15 is a VGA connector suitable for driving most VGA compatible monitors and flat screen displays See Chapter 6 VGA Display Port for additional information Header J12 provides programming support for the SPI serial Flash Jumper J11 controls how the SPI serial Flash is enabled in the application See Chapter 12 SPI Serial Flash for additional information The SMA connector allows an external clock source to drive one of the FPGA s global clock inputs Alternatively the FPGA can provide a high performance clock to another board via the SMA connector See Chapter 3 Clock Sources for additional information 134 www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 9002 6 Yen 0 14 oeeon epin5 s sn P eog 13 815 3e ueueds UJOO XUI DCAAWM 461 Z Y 219945 oneuieuos 908120 20 ev 0622 ern 1 3 SPI Port CS Jumper Select 399099 SMA Clock 1200E 1600E Expansion Header 0 0 NO OI QN Load on 1600E No Load on 588E 102 e C2 3 47nF 1nF 11 10 Max3232 IC2 Keyboard PS2 connector O00000 Ground Test Storage Block
141. or to advise you of any correction if such be made Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design THE DESIGN IS PROVIDED AS IS WITH ALL FAULTS AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE WHETHER GIVEN BY XILINX OR ITS AGENTS OR EMPLOYEES XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DESIGN INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN WHETHER IN CONTRACT OR TORT OR OTHERWISE WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN YOU ACKNOWLEDGE THAT THE FEES IF ANY REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY The Design is not designed or intended for use in the development of on l
142. orm Flash PROM and the Intel StrataFlash PROM Consequently the CPLD must provide the following functions in addition to the user application When the FPGA is in the Master Serial configuration mode FPGA_M lt 2 0 gt 000 generate an active Low enable signal for the XCF048 Platform Flash PROM The Platform Flash PROM is disabled in all other configuration modes The CPLD helps reduce the number of jumpers on the board and simplifies the interaction of all the possible FPGA configuration memory sources e When the FPGA is actively in the BPI Up configuration mode FPGA_M lt 2 0 gt 010 DONE 0 set the upper five StrataFlash PROM address lines A 24 20 to 00000 binary When the FPGA is actively in the BPI Down configuration mode FPGA_M lt 2 0 gt 011 DONE 0 set the upper five StrataFlash PROM address lines A 24 20 to 11111 binary Set the upper five address lines to ZZZZZ for all non BPI configuration modes or whenever the FPGA s DONE pin is High This behavior is identifical to the way the FPGA s upper address lines function during BPI mode So why add a CPLD to mimic this behavior A future reference design demonstrates unique configuration capabilities In a typical BPI mode application the CPLD is not required Other than the required CPLD functionality there are between 13 to 21 user I O pins and 58 remaining macrocells available to the user application Jumper JP10 WDT EN defines the state on the CPLD s XC WDT EN signal
143. plevel bit file file TDO Available Operations are Program m Verify gt Get Device ID gt Get Device Signatur Check Idcode UG230 c4 10 022406 Figure 4 9 iMPACT Programming Succeeded the FPGA s DONE Pin is High Programming Platform Flash PROM via USB The on board USB JTAG circuitry also programs the Xilinx XCF048 serial Platform Flash PROM The steps provided in this section describe how to set up the PROM file and how to download it to the board to ultimately program the FPGA Generating the FPGA Configuration Bitstream File Before generating the PROM file create the FPGA bitstream file The FPGA provides an output clock CCLK when loading itself from an external PROM The FPGA s internal CCLK oscillator always starts at its slowest setting approximately 1 5 MHz Most external PROMs support a higher frequency Increase the CCLK frequency as appropriate to reduce the FPGA s configuration time The Xilinx XCF048 Platform Flash supports a 25 MHz CCLK frequency Right click Generator Programming File in the Processes pane as shown in Figure 4 10 Left click Properties Spartan 3E Starter Kit Board User Guide www xilinx com 31 UG230 v1 0 March 9 2006 Chapter 4 FPGA Configuration Options XILINX Processes E User Constraints E R f Synthesize XST H MD Implement Design Generate P E Progar ap Bun s Genera Rerun
144. polling Verified 283776 of 283776 bytes 0 errors gt Total byte mismatches 0 see temp txt Finish Mon Feb 27 13 38 22 2006 Elapsed clock time 00 01 15 75 seconds Figure 12 17 Programming the M25P16 SPI Flash with the XSPI Programming Utility After programming the SPI Flash remove jumper JP8 as shown in Figure 12 16a If properly programmed the FPGA then configures itself from the SPI Flash PROM and the DONE LED lights The DONE LED is shown in Figure 12 3 98 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Additional Design Details Additional Design Details Figure 12 18 provides additional details of the SPI Flash interface used on the Spartan 3E Starter Kit board In most applications this interface is as simple as that shown in Figure 12 1 The Spartan 3E Starter Kit board however supports of variety of configuration options and demonstrates additional Spartan 3E capabilities STMicro M25P16 SPI Serial Flash MOSI CSI B T4 SPI MOSI dim T16 VS2 A17 DIN DO N10 SP EMISO a U15 VS1 At8 CCLK U16 P SCK i V15 VS0 419 CSO B U3 SPI SS B dz Y Jumper J11 m g m o o e 20 o o m Programming Header J12 HEKHBEMH a 599858 UG230 15 17 030306 Figure 12 18 Additional SPI Flash Interface Design Det
145. puts A and B The reference voltage associated with DAC outputs A and B is 3 3V 576 7 D 11 0 OUTA 7 4096 x 3 3V 5 Equation 9 2 DAC Outputs C and D Equation 9 3 provides the output voltage equation for DAC outputs A and B The reference voltage associated with DAC outputs A and B is 2 5V 5 D 11 0 Voure 71096 lx 2 5V 596 Equation 9 3 70 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX UCF Location Constraints UCF Location Constraints Figure 9 5 provides the UCF constraints for the DAC interface including the I O pin assignment and the I O standard used NET SPI MISO LOC N10 IOSTANDARD LVCMOS33 NET SPI MOSI LOC T4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET SPI SCK LOC U16 TOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET DAC CS LOC N8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET DAC CLR LOC P8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 Figure 9 5 UCF Location Constraints for the DAC Interface Related Resources LTC2624 Quad DAC Data Sheet http www linear com pc downloadDocument do navId H0 C1 C1155 C1005 C1156 P2048 D2170 PicoBlaze Based D A Converter Control for the Spartan 3E Starter Kit Reference Design http www xilinx com s3estarter e Xilinx PicoBlaze Soft Processor http www xilinx com picoblaze Digilent Inc Perip
146. r Only pins 1 and 5 of the connector attach to the FPGA 2700 PS2 DATA G13 2700 PS2 CLK G14 UG230 c8 01 021806 Figure 8 1 PS 2 Connector Location and Signals Table 8 1 PS 2 Connector Pinout PS 2 DIN Pin Signal FPGA Pin 1 DATA PS2 DATA G13 p Reserved G13 3 4 ET 5 CLK PS2 CLK G14 6 Reserved G13 Both a PC mouse and keyboard use the tvvo vvire PS 2 serial bus to communicate with a host device the Spartan 3E FPGA in this case The PS 2 bus includes both clock and data Both a mouse and keyboard drive the bus with identical signal timings and both use 11 bit words that include a start stop and odd parity bit However the data packets are Spartan 3E Starter Kit Board User Guide www xilinx com 61 UG230 v1 0 March 9 2006 Chapter 8 PS 2 Mouse Keyboard Port XILINX Keyboard organized differently for a mouse and keyboard Furthermore the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the keyboard The PS 2 bus timing appears in Table 8 2 and Figure 8 2 The clock and data signals are only driven when data transfers occur otherwise they are held in the idle state at logic High The timing defines signal requirements for mouse to host communications and bidirectional keyboard communications As shown in Figure 8 2 the attached keyboard or mouse writes a bit on the data line when the clock signal is High a
147. r increments with each HS pulse and decoded values generate the VS signal This counter tracks the current display row These two continuously running counters form the address into a video display buffer For example the on board DDR SDRAM provides an ideal display buffer No time relationship is specified between the onset of the HS pulse and the onset of the VS pulse Consequently the counters can be arranged to easily form video RAM addresses or to minimize decoding logic for sync pulse generation www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX UCF Location Constraints UCF Location Constraints Figure 6 4 provides the UCF constraints for the VGA display port including the I O pin assignment the I O standard used the output slew rate and the output drive current NET VGA RED LOC H14 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA GREEN LOC H15 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA BLUE LOC G15 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA HSYNC LOC F15 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA VSYNC LOC F14 IOSTANDARD LVTTL DRIVE 8 SLEW FAST Figure 6 4 UCF Constraints for VGA Display Port Related Resources VESA http www vesa org e VGA timing information http www epanorama net documents pc vga_timing html Spartan 3E Starter Kit Board User Guide www xilinx com
148. r ll CPLD Figure 11 1 SF_D lt 15 12 gt SF_D lt 11 8 gt SF_D lt 7 1 gt SPI MISO SF A 19 0 SF A 24 20 Intel StrataFlash CE2 CE1 gt CEO gt OE WE BYTE gt STS D 15 12 D 11 8 D 7 1 D 0 A 24 20 A 19 0 esssssssssssesesssssossoesssesssoessossossosessssoesesss t 7 1 a 7 7 7 7 7 9 7 9 8 1 7 7 1 90 0 1 0 90 1 SPI Serial Flash s Qocssssssssssssssosoessoscssoscsssoessossosssssssssss es Platform Flash 7 4 Character LCD DB 7 4 UG230 c11 01 030206 Connections to Intel StrataFlash Flash Memory The StrataFlash PROM provides various functions Stores a single FPGA configuration in the StrataFlash device Stores two different FPGA configurations in the StrataFlash device and dynamically switch between the two using the Spartan 3E FPGA s MultiBoot feature Stores and executes MicroBlaze processor code directly from the StrataFlash device Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 www xilinx com 81 Chapter 11 Intel StrataFlash Parallel NOR Flash PROM XILINX Stores MicroBlaze processor code in the StrataFlash device and shadows the code into the DDR memory before executing the code e Stores non volatile data from the FPGA StrataFlash Connections Table 11 1 shows the connections
149. rn horizontally from left to right and vertically from top to bottom As shown in Figure 6 2 information is only displayed when the beam is moving in the forward direction left to right and top to bottom and not during the time the beam returns back to the left or top edge of the display Much of the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass 54 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 3 XILINX Signal Timing for a 60 Hz 640x480 VGA Display Current through the horizontal deflection coil time pixel 0 0 pixel 0 639 gt A q 640 pixels are displayed each time the beam traverses the screen VGA Display Retrace No information pixel 479 0 pixel 479 639 is displayed during this time gt Stable current ramp Information is displayed during this time Total horizontal time Horizontal display time retrace time tug 1001 front porch gt b front porch s Hi Se L Horizontal sync signal L back porch sets the retrace frequency UG230 c6 02 021706 Figure 6 2 CRT Display Timing Example The display resolution defines the size of the beams the frequency at which the beam traces across the display and the frequency at which the electron beam is modulated Modern VGA
150. rtan 3E Starter Kit Board User Guide www xilinx com 13 UG230 v1 0 March 9 2006 Chapter 1 Introduction and Overview 3 XILINX 14 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Chapter 2 Switches Buttons and Knob Slide Switches Locations and Labels The Spartan 3E Starter Kit board has four slide switches as shown in Figure 2 1 The slide switches are located in the lower right corner of the board and are labeled SW3 through SVVO Switch SW3 is the left most switch and SWO is the right most switch HIGH LOW SW3 SW2 SW1 SWO N17 H18 L14 L13 UG230 c2 01 021206 Figure 2 1 Four Slide Switches Operation When in the UP or ON position a switch connects the FPGA pin to 3 3V a logic High When DOWN or in the OFF position the switch connects the FPGA pin to ground a logic Low The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry although such circuitry could easily be added to the FPGA design programmed on the board UCF Location Constraints Figure 2 2 provides the UCF constraints for the four slide switches including the I O pin assignment and the I O standard used The PULLUP resistor is not required but it defines the input value when the switch is in the middle of a transition Spartan 3E Starter Kit Board User Guide www xilinx com 15 UG230 v1 0 March 9 2006 Chapter 2
151. ry Pushbutton Switch ROT ROT_A LOC K18 IOSTANDARD LVTTL PULLUP ROT_B LOC G18 IOSTANDARD LVTTL PULLUP ROT_CENTER LOC V16 IOSTANDARD LVTTL PULLDOWN RS 232 Serial Ports RS232 RS232 DCE RXD LOC R7 IOSTANDARD LVTTL RS232 DCE TXD LOC M14 IOSTANDARD LVTTL DRIVE 8 SLEW SLOW RS232 DTE RXD LOC U8 IOSTANDARD LVTTL RS232 DTE TXD LOC M13 IOSTANDARD LVTTL DRIVE 8 SLEW SLOW DDR SDRAM SD I O Bank 3 VCCO 2 5V SD_A lt 0 gt LOC Tl IOSTANDARD SSTL2 I SD A 1 LOC R3 IOSTANDARD SSTL2 I SD A 2 LOC R2 IOSTANDARD SSTL2 I SD_A lt 3 gt LOC Pl IOSTANDARD SSTL2 I SD A 4 F4 IOSTANDARD SSTL2 I SD A 5 LOC H4 IOSTANDARD SSTL2 I SD A 6 H3 IOSTANDARD SSTL2 I SD A 7 LOC Hl IOSTANDARD SSTL2 I SD A 8 LOC H2 IOSTANDARD SSTL2 I SD A 9 N4 IOSTANDARD SSTL2 I SD A 10 LOC T2 IOSTANDARD SSTL2 I SD A 11 LOC N5 IOSTANDARD SSTL2 I SD A 12 LOC P2 IOSTANDARD SSTL2 I SD BA 0 LOC K5 IOSTANDARD SSTL2 I SD BA 1 LOC K6 IOSTANDARD SSTL2 I SD CAS LOC C2 IOSTANDARD SSTL2 I SD CK N Loc J4 IOSTANDARD SSTL2 I SD CK P LOC J5 IOSTANDARD SSTL2 I SD CKE K3 IOST
152. s E an S an S an Female DCE DB9 Male DTE DBS aS 0 NO OON 0 NO OQ Q N c5 2 1ur 2 1ur G s UG Port OO NO O ON Spartan 3E Starter Board Digilent Inc Copuright 2005 2006 Engineer CC SHEET RS232 VGA PS2 and Parallel IU Author GMA TITLE S3E Starter Sheet 2 14 XNITX Mod 2 Sd pue 104 V DA SHOd z 2 SH Appendix A Schematics yx XILINX Ethernet PHY Magnetics and RJ 11 Connector 136 IC6 is an SMSC 10 100 Ethernet PHY with its associated 25 MHz oscillator The PHY requires an Ethernet MAC implemented within the FPGA J19 is the RJ 11 Ethernet connector associated with the 10 100 Ethernet PHY See Chapter 14 10 100 Ethernet Physical Layer Interface for additional information www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 0 March 9 2006 9002 6 Yen 0 14 oeeon epin5 s sn P eog 13 815 3e ueueds UJOO XUI DCAAWM 261 6 V einBij rt 199uS 908120 0 ev 0620 NO LORD R42 R44 56 2 R43 R44 56 2 R46 56 2 56 2 R48 R50 56 2 56 2 ND REG EN LAN83C185 RXN MODE MODE1 MODE2 TEST TEST GPOB MII GPO1 PHYAD4 GP02 SPD1 PHY LINKON PHY1 ACTIVITY PHY2 FDUPLEX PHY3 MDIO MDC NINT NRST EXRES HFJ11 2450E LS TXP TXN RXP TXD TXD1 TXD2 TXD3 TX ER TXD4 RXD
153. s x Category Pe General Options Configuration Options Startup Options Property Name Vdie 0 fA Configuration Rate 2 xi Configuration Clk Configuration Pins Default 1 Configuration Pin M 12 t Readback Options Configuration Pin M1 Configuration Pin M2 Configuration Pin Program Configuration Pin Done JTAG Pin TCK v Property display level Standard y Default Cancel Apply Help Z UG230_c15_04_030206 Figure 12 5 Set Configuration Rate to 12 MHz When Using the M25P16 SPI Flash Spartan 3E Starter Kit Board User Guide www xilinx com 91 UG230 v1 0 March 9 2006 Chapter 12 SPI Serial Flash XILINX Formatting an SPI Flash PROM File After generating the program file double click Generate PROM ACE or UTAG File to launch the iMPACT softvvare as shovvn in Figure 12 6 Processes User Constraints H 22 f Spnthesize XST f Implement Design B o Generate Programming File Be FEL LU File Generation ar Processes UG230 15 05 030206 Figure 12 6 Double Click Generate PROM ACE or JTAG File After iMPACT starts double click PROM File Formatter as shown in Figure 12 7 IMPACT C data my desi sb Eile Edit view Operations Slaves erial P 3UGelectMAP Desktop Configu IMPACT Modes UG230_c15_06_030206 Figure 12 7 Double Click PROM File Formatter Choose 3rd Party SPI PROMas the target PRO
154. se E COL U6 MII Collision Detect E MDC P9 Management Clock Serial management clock E MDIO U5 Management Data Input Output MicroBlaze Ethernet IP Cores The Ethernet PHY is primarily intended for use with MicroBlaze applications As such an Ethernet MAC is part of the EDK Platform Studio s Base System Builder Both the full Ethernet MAC and the Lite version are available for evaluation as shown in Figure 14 3 The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for applications that do not require support for interrupts back to back data transfers and statistics counters Base System Builder Configure Additional IO Interfaces The following external memory and l devices were found on your board Xilins Spartan 3E Starter Board Revision C Please select the ID devices which you would like to use ID devices DDR SDRAM 16 16 Data Sheet Peripheral OPB DDR Note V Ethemet MAC Data Sheet Peripheral OPB ETHERNET a Note OPB ETHERNET DMA Pres OPB ETHERNETLITE Na DMA UG230 c14 03 022706 Figure 14 3 Ethernet MAC IP Cores for the Spartan 3E Starter Kit Board The Ethernet MAC core requires design constraints to meet the required performance Refer to the OPB Ethernet MAC data sheet v1 02 for details The OPB bus clock frequency must be 65 MHz or higher for 100 Mbps Ethernet operations and 6 5 MHz or faster for 10 Mbps Ethernet operations
155. select the FPGA s configuration mode and associated configuration memory source 26 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 3 XILINX PROG Push Button Table 4 1 Spartan 3E Configuration Mode Jumper Settings Header J30 in Figure 4 2 Configuration Mode Pins Mode M2 M1 MO FPGA Configuration Image Source Jumper Settings Master Serial 0 0 0 Platform Flash PROM SPI 1 1 0 SPI Serial Flash PROM starting at see address 0 Chapter 12 SPISerial Flash BPI Up 0 1 0 StrataFlash parallel Flash PROM see starting at address 0 and Chapter 11 incrementing through address Intel space The CPLD controls address StrataFlash lines A 24 20 during BPI Parallel NOR configuration Flash PROM BPI Down 0 1 1 StrataFlash parallel Flash PROM see starting at address OxIFF FFFF and Chapter 11 decrementing through address Intel space The CPLD controls address StrataFlash lines A 24 20 during BPI Parallel NOR configuration Flash PROM JTAG 0 1 0 Downloaded from host via USB JTAG port PROG Push Button The PROG push button shown in Figure 4 2 page 26 forces the FPGA to reconfigure from the selected configuration memory source Press and release this button to restart the FPGA configuration process at any time DONE Pin LED The DONE pin LED shown in Figure 4 2 page 26 lights whenever the FPGA is s
156. ser Guide www xilinx com 77 UG230 v1 0 March 9 2006 Chapter 10 Analog Capture Circuit XILINX SPI_MISO Slave LTC1407A 1 A D Converter ge cow BEL Pe P P2 Pa Pa Ds De 07 De De D Da Ds 05 De f7 De p p papal 1 Z z SPILSCK Channel 1 Channel 0 Converted data is presented with a latency of one sample The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD CONV Sample The converted values is then presented after the next AD CONV pulse Sample point point AD CONV SPI SCK Bi Channel 0 Channel 1 h Channel 0 SPI MISO UG230 10 05 030306 Figure 10 6 Analog to Digital Conversion Interface Figure 10 7 shows detailed transaction timing The AD CONV signal is not a traditional SPI slave select enable Be sure to provide enough SPI SCK clock cycles so that the ADC leaves the SPI MISO signal in the high impedance state Otherwise the ADC blocks communication to the other SPI peripherals As shown in Figure 10 6 use a 34 cycle communications sequence The ADC 3 states its data output for two clock cycles before and after each 14 bit data transfer 4ns min l AD_CONV I r 19 6ns min I 3ns i ki i mi 1 1 I SPI SCK 1 2 3 4 5 6 a 8ns m Channel 0 SPI MISO High Z W o M o oU M AD CONV 45ns min 1 ra a 1 30 31 32 33 34 SPI SCK I 6ns e Channel 1 1 High
157. sh SF_A lt 19 0 gt A 23 20 Unconnected UG230 16 01 030906 Figure 16 1 XC2C64A CoolRunner ll CPLD Controls Master Serial and BPI Configuration Modes 126 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 3 XILINX UCF Location Constraints UCF Location Constraints There are two sets of constraints listed belovv one for the Spartan 3E FPGA and one for the XC2C64A CoolRunner II CPLD FPGA Connections to CPLD CPLD Figure 16 2 provides the UCF constraints for the FPGA connections to the CPLD including the I O pin assignment and the I O standard used NET XC CMDc15 LOC NET XC CMD 0 LOC NET XC D 2 LOC NET XC D 1 LOC NET XC D 0 LOC NET FPGA M2 LOC NET FPGA M1 LOC NET FPGA MO LOC NET XC CPLD EN LOC NET XC TRIG LOC NET XC GCKO LOC NET GCLK10 LOC NET SPI SCK LOC SF 24 is the same NET SF A 24 LOC NET SF A 23 LOC NET SF A 22 LOC NET SF A 21 LOC NET SF A 20 LOC Figure 16 2 N18 IOSTANDARD P18 IOSTANDARD F17 IOSTANDARD F18 IOSTANDARD G16 IOSTANDARD T10 IOSTANDARD V11 IOSTANDARD M10 IOSTANDARD B10 IOSTANDARD R17 IOSTANDARD H16 IOSTANDARD eo IOSTANDARD U16 IOSTANDARD as FX2 IO 32 All IOSTANDARD N11 IOSTANDARD V12 IOSTANDARD V13 IOSTANDARD T12 IOSTANDARD LVCMOS33 LVCMOS33
158. sos de eer ERRASSE ne ERE HEN Te an 122 UCF Location Constraints 122 Connectorless Debugging Port Landing Pads 6 123 Related Resources 124 Chapter 16 XC2C64A 1 CPLD UCF Location Constraints 127 FPGA Connections to CPLD 127 SPEI um l na sobob 127 Related ResourceS 128 Chapter 17 DS2432 1 VVire SHA 1 EEPROM UCF Location Constraints 129 Related ResourceSs 129 Appendix A Schematics FX2 Expansion Header 6 pin Headers and Connectorless Probe Header 132 RS 232 Ports VGA Port and PS 2 Port 134 Ethernet PHY Magnetics and RJ 11 Connector 136 Voltage ou oix pla e Reed reed a a ir aee adla 138 FPGA Configurations Settings Platform Flash PROM SPI Serial Flash JTAG Connections sna eer ret tecto E er ten ae oe CR 140 FPGA I O Banks 0 and 1 Oscillators 142 FPGA I O Banks 2and3 144 Power Supply Decoupling cei eoe Ier e
159. starter Universal Scan SPI Flash Programming via JTAG Training Video http vvvvvv ricreations com YTAG Softvvare Dovvnloads htm 102 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Chapter 13 DDR SDRAM The Spartan 3E Starter Kit boards includes a 512 Mbit 32M x 16 Micron Technology DDR SDRAM MT46V32M16 with a 16 bit data interface as shown in Figure 13 1 All DDR SDRAM interface pins connect to the FPGA s I O Bank 3 on the FPGA I O Bank 3 and the DDR SDRAM are both powered by 2 5V generated by an LTC3412 regulator from the board s 5V supply input The 1 25V reference voltage common to the FPGA and DDR SDRAM is generated using a resistor voltage divider from the 2 5V rail 5 0V 2 5V LTC3412 2 1 25V Spartan 3E FPGA Micron 512 Mb DDR SDRAM 2 SD A 12 05 See Table A 12 0 D DQ 15 v VREF Se DQ 15 0 VREF VCCO 3 See Table oes VDD E MN VDDQ SD CAS WN SD_WE AAN SD_UDM NW UQM MT46V32M16 SD_LDM Nv LaM 32Mx16 SD UDGS UDQS SULDAS LDQS b cs MN CS SD CKE ANN SD CK N ANN B9 GCLK9 SD CKP SD CK FB UG230 c13 01 022406 Figure 13 1 FPGA Interface to Micron 512 Mbit DDR SDRAM All DDR SDRAM interface signals are terminated Spartan 3E Starter Kit Board User Guide www xilinx com 103 UG230 v1 0 March 9 2006 Chapter
160. stored in the DD RAM beyond the 16th character on a line The cursor automatically moves to the second line when it shifts beyond the 40th character location of the first line The first and second line displays shift at the same time When the displayed data is shifted repeatedly both lines move horizontally The second display line does not shift into the first display line Execution Time 40 us 48 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX LCD Controller Table 5 4 Shift Patterns According to S C and R L Bits DB3 DB2 S C R L Operation 0 0 Shift the cursor position to the left The address counter is decremented by one 0 1 Shift the cursor position to the right The address counter is incremented by one Shift the entire display to the left The cursor follows the display shift The address counter is unchanged Shift the entire display to the right The cursor follows the display shift The address counter is unchanged Function Set Sets interface data length number of display lines and character font The Starter Kit board supports a single function set with value 0x28 Execution Time 40 us Set CG RAM Address Set the initial CG RAM address After this command all subsequent read or write operations to the display are to or from CG RAM Execution Time 40 us Set DD RAM Address Set the initial DD RAM address
161. strate new Spartan 3E capabilities the starter kit board has three different configuration memory sources that all need to function well together The extra configuration functions make the starter kit board more complex than typicalSpartan 3E applications The starter kit board also includes an on board USB based JTAG programming interface The on chip circuitry simplifies the device programming experience In typical applications the JTAG programming hardware resides off board or in a separate programming module such as the Xilinx Platform USB cable Voltages for all Applications The Spartan 3E Starter Kit board showcases a triple output regulator developed by Texas Instruments the TPS75003 specifically to power Spartan 3 and Spartan 3E FPGAs This regulator is sufficient for most stand alone FPGA applications However the starter kit board includes DDR SDRAM which requires its own high current supply Similarly the USB based JTAG download solution requires a separate 1 8V supply Related Resources e Xilinx MicroBlaze Soft Processor http www xilinx com microblaze e Xilinx PicoBlaze Soft Processor http www xilinx com picoblaze e Xilinx Embedded Development Kit http www xilinx com ise embedded design prod platform studio htm e Xilinx software tutorials http www xilinx com support techsup tutorials e Texas Instruments TPS75003 http focus ti com docs prod folders print tps75003 html Spa
162. t 6 pin connector along the right edge of the board It uses a female 6 pin 90 socket Four FPGA pins connect to the J2 header FX2_IO lt 8 5 gt These four signals are also shared with the Hirose FX2 connector The board supplies 3 3V to the accessory board mounted in the J2 socket on the bottom pin Spartan 3E FPGA UG230_c12_08_022406 Figure 15 9 FPGA Connections to the J2 Accessory Header Spartan 3E Starter Kit Board User Guide www xilinx com 121 UG230 v1 0 March 9 2006 Chapter 15 Expansion Connectors XILINX Header J4 The J4 header shown in Figure 15 10 is located immediately to the left of the J1 header It uses a 6 pin header consisting of 0 1 inch centered stake pins Four FPGA pins connect to the J4 header 2 IO 12 9 These four signals are also shared with the Hirose 2 connector The board supplies 3 3V to the accessory board mounted in the J4 socket on the bottom pin Spartan 3E FPGA UG230 12 09 022406 Figure 15 10 FPGA Connections to the J4 Accessory Header UCF Location Constraints Figure 15 11 provides the User Constraint File UCF constraints for accessory headers including the I O pin assignment and the I O standard used These header connections are shared with the FX2 connector as shown in Figure 15 7 page 120 4 6 pin header Jl These four connections are shared with the FX2 connector NET J1 lt 0 gt LOC B4 IOST
163. tes when an overflow occurs If the mouse moves continuously the 33 bit transmissions repeat every 50 ms or so The L and R fields in the status byte indicate Left and Right button presses A 1 indicates that the associated mouse button is being pressed 64 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Voltage Supply Voltage Supply The PS 2 port on the Spartan 3E Starter Kit board is powered by 5V Although the Spartan 3E FPGA is not a 5V tolerant device it can communicate with a 5V device using series current limiting resistors as shown in Figure 8 1 UCF Location Constraints Figure 8 6 provides the UCF constraints for the PS 2 port connecting including the I O pin assignment and the I O standard used NET PS2 CLK LOC G14 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW NET PS2 DATA LOC G13 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW Figure 8 6 UCF Location Constraints for PS 2 Port Related Resources PS 2Mouse Keyboard Protocol http www computer engineering org ps2protocol 5 2 Keyboard Interface http www computer engineering org ps2keyboard PS 2 Mouse Interface http www computer engineering org ps2mouse Spartan 3E Starter Kit Board User Guide www xilinx com 65 UG230 v1 0 March 9 2006 Chapter 8 PS 2 Mouse Keyboard Port 3 XILINX 66 www xilinx com Spartan 3E Starter Kit Boar
164. the FX2 IO 32 signal on the FX2 expansion connector SPI Data Line The least significant StrataFlash data line SF D 0 is shared with data output signals from serial SPI peripherals SPI MISO and the serial output from the Platform Flash PROM as shown in Table 11 3 To avoid contention the FPGA application must ensure that only one data source is active at any time Table 11 3 Possible Contention on SPI MISO SF D 0 Data Condition Function FPGA M2 Low Platform Flash outputs data on DO FPGA MI Low FPGA MO Low INIT B High SF CE0 Low StrataFlash outputs data SF OE Low AD CONV High Serial data is clocked out of the A D converter SPI SCK DAC CS Low DAC outputs previous command in response to SPI SCK transitions SPI SCK Spartan 3E Starter Kit Board User Guide www xilinx com 85 UG230 v1 0 March 9 2006 Chapter 11 Intel StrataFlash Parallel NOR Flash PROM XILINX UCF Location Constraints Address Figure 11 2 provides the UCF constraints for the StrataFlash address pins including the I O pin assignment and the I O standard used NET SF A 24 LOC All IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 23 LOC N11 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 22 LOC V12 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 21 LOC V13 IOSTANDARD LVCMOS33 DRIVE 4 S
165. the FPGA from the image stored in the Platform Flash PROM using Master Serial mode e Program the on board 16 Mbit ST Microelectronics SPI serial Flash PROM then configure the FPGA from the image stored in the SPI serial Flash PROM using SPI mode e Program the on board 128 Mbit Intel StrataFlash parallel NOR Flash PROM then configure the FPGA from the image stored in the Flash PROM using BPI Up or BPI Down configuration modes Further an FPGA application can dynamically load two different FPGA configurations using the Spartan 3E FPGA s MultiBoot mode See the Spartan 3E data sheet DS312 for additional details on the MultiBoot feature Figure 4 1 indicates the position of the USB download programming interface and the on board non volatile memories that potentially store FPGA configuration images Figure 4 2 provides additional details on configuration options 16 Mbit ST Micro SPI Serial Flash Serial Peripheral Interface SPI mode Configuration Options USB based Download Debug Port Uses standard USB cable PROG B button Platform Flash PROM mode pins z l 128 Mbit Intel StrataFlash Parallel NOR Flash memory N x R Byte Peripheral Interface BPI mode UG230 c4 01 022006 Figure 4 1 Spartan 3E Starter Kit FPGA Configuration Options Spartan 3E Starter Kit Board User Guide www xilinx com 25 UG230 v1 0 March 9 2006 Chapter 4 FPGA Configuration Options XILINX Configuration Mode Jumper Settin
166. tical refresh frequencies in the 60 Hz to 120 Hz range The number of horizontal lines displayed at a given refresh frequency defines the horizontal retrace frequency VGA Signal Timing The signal timings in Table 6 2 are derived for a 640 pixel by 480 row display using a 25 MHz pixel clock and 60 Hz x 1 refresh Figure 6 3 shows the relation between each of the timing symbols The timing for the sync pulse width Tpw and front and back porch intervals Tgp and Tgp are based on observations from various VGA displays The front and back porch intervals are the pre and post sync pulse times Information cannot be displayed during these times Table 6 2 640x480 Mode VGA Timing Vertical Sync Horizontal Sync Symbol Parameter Time Clocks Lines Time Clocks Ts Sync pulse time 16 7ms 416 800 521 32 us 800 Tprsp Display time 15 36 ms 384 000 480 25 6 us 640 Tpw Pulse width 64 us 1 600 2 3 84 us 96 Trp Front porch 320 us 8 000 10 640 ns 16 T p Back porch 928 us 23 200 29 1 92 us 48 gt T m Tdisp P I Tow op UG230_c6_03_021706 Figure 6 3 VGA Control Timing Generally a counter clocked by the pixel clock controls the horizontal timing Decoded counter values generate the HS signal This counter tracks the current pixel display location on a given row A separate counter tracks the vertical timing The vertical sync counte
167. to 15 differential I O pairs and two input only pairs using either the LVDS or RSDS I O standards as listed in Table 15 2 All I O pairs support differential input termination DIFF TERM as described in the Spartan 3E data sheet Select pairs have optional landing pads for external termination 116 resistors These signals are not routed with matched differential impedance as would be required for ultimate performance However all traces have similar lengths to minimize skew www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 EZ XILINX Hirose 100 pin FX2 Edge Connector J3 Table 15 2 Differential I O Pairs External Resistor Differential Pair Signal Name FPGA Pins FPGA Pin Name Direction DIFF_TERM Designator i FX2_IO1 B4 IO L24N 0 I O Yes FX2 IO2 A4 IO L24P 0 I O Yes FX2 IO3 D5 IO L23N 0 I O Yes 2 104 C5 IO L23P 0 I O Yes FX2_IO5 A6 IO L20N 0 I O Yes FX2 IO6 B6 IO L20P 0 I O Yes 1 2 1 7 E7 IO L19N 0 I O Yes 2 IO8 F7 IO L19P 0 I O Yes 5 2 109 7 IO L18N 0 I O Yes FX2 IO10 C7 IO L18P 0 I O Yes 2 1011 F8 IO L17N 0 I O Yes FX2 IO12 E8 IO L17P 0 I O Yes 5 FX2_IO13 F9 IP_L15N_0 I O Yes 2 1014 9 IP L15P 0 I O Yes FX2_IO15 D11 IP L09N 0 I O Yes FX2 IO16 C11 LO9P I O Yes FX2 IO17 F11 TO L08N 0 I O Yes 9 R202 FX
168. to the JTAG chain The JTAG3 cable directly mounts to Header J12 The labels on the JTAG3 cable face toward the J11 jumpers If using flying leads they must be connected as shown in Figure 12 15b and Table 12 2 Note the color coding for the leads The gray INIT lead is left unconnected 96 www xilinx com Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 XILINX Configuring from SPI Flash a JTAG3 Parallel Connector b Parallel Cable III or Parallel Cable IV with Flying Leads UG230 15 14 030206 Figure 12 15 Attaching a JTAG Parallel Programming Cable to the Board Table 12 2 Cable Connections to J12 Header Cable and Labels Connections J12 Header Label SEL SDI SDO SCK GND VCC JTAG3 Cable Label TMS TDI TDO TCK GND VCC Flying Leads Label TMS TDI TDO GND VREF Igel DIN ESOS GND VREF Insert Jumper on JP8 and Hold PROG B Low The JTAG parallel programming cable directly accesses the SPI Flash pins To avoid signal contention with the FPGA ensure that the connecting FPGA pins are high impedance Force the FPGA s PROG B pin Low by installing a jumper on JP8 next to the PROG push button as shown in Figure 12 16 See Figure 12 3 page 90 to locate jumper JP8 and surrounding landmarks E aoa 2 lt u 2 72 no z DEFAULT NO JUMPER 1 a No Jumper FPGA Operational default b Jumper Installed FPGA Held in Configuration State I Os in Hi
169. ts em ee esce gti ete adhe RR SCR aa 78 Disable Other Devices on the SPI Bus to Avoid Contention 79 Spartan 3E Starter Kit Board User Guide www xilinx com UG230 v1 0 March 9 2006 XILINX Connecting Analog Inputs dot a n C d be saws 79 Related Resourees ECHO OC 4 CE ROI e de ac RU dd 79 Chapter 11 Intel StrataFlash Parallel NOR Flash PROM StrataFlash Connections 82 Shared Connections 85 Character LED dede de d e dee dtd soni des o etcetera arent au au 85 Xilinx XC2C64A CPEHD oe eked exe oe aa du qe eg 85 SPL Data EINE ne ee 5057700 50 85 UCF Location Constraints 86 Qhip a sh aha 86 Jr 0 86 ODIO x sd eb ee 87 Setting the Mode Select Pins 87 Related Resources 87 Chapter 12 SPI Serial Flash UCF Location Constraints 89 Configuring from SPI Flash scies ya den 90 Setting the FPGA Mode Select Pins 90 Creating an SPI Serial Flash PROM File 91 Setting the Configuration Clock Rate
170. ts the DD RAM and CG RAM address counter by one location after each Write Data to CG RAM or DD RAM or Read Data from CG RAM or DD RAM command The cursor or blink position moves accordingly Bit DBO S Shift 0 Shifting disabled 1 During a DD RAM write operation shift the entire display value in the direction controlled by Bit DB1 I D Appears as though the cursor position remains constant and the display moves Display On Off Display is turned on or off controlling all characters cursor and cursor position character underscore blink Execution Time 40 us Bit DB2 D Display On Off 0 No characters displayed However data stored in DD RAM is retained 1 Display characters stored in DD RAM Bit DB1 C Cursor On Off The cursor uses the five dots on the bottom line of the character The cursor appears as a line under the displayed character 0 No cursor 1 Display cursor Bit DBO B Cursor Blink On Off 0 No cursor blinking 1 Cursor blinks on and off approximately every half second Cursor and Display Shift Moves the cursor and shifts the display without changing DD RAM contents Shift cursor position or display to the right or left without writing or reading display data This function positions the cursor in order to modify an individual character or to scroll the display window left or right to reveal additional data
171. uccessfully configured If this LED is not lit then the FPGA is not configured Spartan 3E Starter Kit Board User Guide UG230 v1 0 March 9 2006 www xilinx com 27 Chapter 4 FPGA Configuration Options XILINX Programming the FPGA CPLD or Platform Flash PROM via USB As shown in Figure 4 1 page 25 the Spartan 3E Starter Kit includes embedded USB based programming logic and an USB endpoint with a Type B connector Via a USB cable connection with the host PC the iMPACT programming software directly programs the FPGA the Platform Flash PROM or the on board CPLD Direct programming of the parallel or serial Flash PROMs is not presently supported Connecting the USB Cable The kit includes a standard USB Type A Type B cable similar to the one shown in Figure 4 3 The actual cable color might vary from the picture USB Type B Connector Connects to Starter Kit s USB connector USB Type A Connector Connects to computer s USB connector UG230 c4 04 030306 Figure 4 3 Standard USB Type A Type B Cable The wider and narrower Type A connector fits the USB connector at the back of the computer After installing the Xilinx software connect the square Type B connector to the Spartan 3E Starter Kit board as shown in Figure 4 4 The USB connector is on the left side of the board immediately next to the Ethernet connector When the board is powered on the Windows operating system should recognize and install the asso
172. wn resistor on each input NET ROT A LOC K18 IOSTANDARD LVTTL PULLUP NET ROT B LOC G18 IOSTANDARD LVTTL PULLUP NET ROT CENTER LOC V16 IOSTANDARD LVTTL PULLDOWN Figure 2 9 UCF Constraints for Rotary Push Button Switch Discrete LEDs Locations and Labels The Spartan 3E Starter Kit board has eight individual surface mount LEDs located above the slide switches as shown in Figure 2 10 The LEDs are labeled LED7 through LEDO LED7 is the left most LED LEDO the right most LED LED1 E12 LED5 D11 LED4 C11 LED3 F11 LED2 E11 LEDO F12 oo LL Ww an LI Lu l UG230 2 04 021206 Figure 2 10 Eight Discrete LEDs Spartan 3E Starter Kit Board User Guide www xilinx com 19 UG230 v1 0 March 9 2006 Chapter 2 Switches Buttons and Knob 3 XILINX Operation Each LED has one side connected to ground and the other side connected to a pin on the Spartan 3E device via a 390 current limiting resistor To light an individual LED drive the associated FPGA control signal High UCF Location Constraints Figure 2 11 provides the UCF constraints for the four push button switches including the I O pin assignment the I O standard used the output slew rate and the output drive current NET NET NET NET NET NET NET NET Related Resources

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