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MAX 10 NEEK User Manual 1 www.terasic.com August 3, 2015

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1. gt Operational Amplifier Figure 5 11 Block diagram of the ADC MIC LCD demonstration B Design Tools e Quartus II v15 0 64 bit B Demonstration Source Code Project directory Demonstrations adc Bitstream used adc lcd sof B Demonstration Batch File Demo batch file folder Demonstrationsxadc Icddemo batch Batch file test bat e FPGA configuration file lcd sof B Demonstration Setup Please make sure Quartus II is installed on the host PC Connect the NEEK10 board J8 to the host PC with USB cable and install the USB Blaster II driver Plug in the 5V adapter to the NEEK10 Board and power it up e Execute the demo batch file test bat from the directory adc Icd demo batch e The sound wave from the MIC can be observed on the LCD and probed through DAC SMA OUT from the oscilloscope or can also connect external speaker to Line out to hear the sound as Figure 5 12 The volume of the sound from the MIC 15 displayed digitally on LEDRO 9 as MAX 10 NEEK 61 WWW terasic com 1 4 51 August 3 2015 www terasic com AN S Figure 5 13 LeCroy W mave udi E 2 0 D M T Hew 1 TRY tht 1 il lil il Figure 5 12 The waveform of onboard MIC is displayed on both LCD and oscilloscope Its sound is played out from the speaker BL ter PIT Me 115561 Figure 5 13 LEDRO 9 displays the volume level o
2. Tre Parallel Port ANU S n VA D 10 Figure 3 24 Connections between the MAX 10 FPGA CSI 2 to parallel bridge device camera module Table 3 12 Pin Assignment of MIPI CSI 2 to parallel interface Signal Name PIXEL D 0 MIPI PIXEL D 1 PIXEL D 2 MIPI PIXEL D 3 PIXEL D 4 PIXEL D 5 MIPI PIXEL D 6 MIPI PIXEL D 7 MIPI PIXEL D 8 PIXEL D 9 PIXEL D 10 PIXEL D 11 PIXEL D 12 MIPI PIXEL D 13 PIXEL D 14 PIXEL D 15 PIXEL D 16 PIXEL D 17 PIXEL D 18 PIXEL D 19 PIXEL D 20 FPGA Pin No Description PIN U6 PIN W5 PIN V7 PIN V5 PIN W4 PIN V4 PIN W3 PIN W6 PIN W7 PIN Y3 PIN Y4 PIN Y5 PIN AB3 PIN 4 PIN AA5 PIN AB5 PIN AB7 PIN Y8 PIN 8 PIN AA7 PIN Y7 MAX 10 NEEK Tijasic www terasic com Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data Parallel Port Data 32 VO Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V
3. X Programmer F neek 10 dev matthew spider NEEK10 golden top NEEK10 golden top NEEK10 golden top cdf File Edit View Processing Tools Window Help 5 S tera co Set NCO se vode 4 Enable real time ISP to allow background programming when available File Device Checksum Usercode Program Verify Blank Examine Security Erase ISP ust Configure Check Bit CLAMP Ub e 10MSODAF484C6GES 00000000 00000000 QSPI 512Mb gi Auto Detect Hy Add File 23 Add Devic TDI 10M50DAF484ES TDO Figure 7 8 Auto Detect The QSPI Flash 1 e Right click on the 512Mb item and change the file to the final flash pof generated above Check the Program Configure button and start programming The programming will take a long time and the software is downloaded to the QSPI flash if successful e Add the app sel pof and program it into the onchip Flash e sure the CONFIG SEL is set to and re power up the board Q Note You can also use batch to restore the original binary file by executing the test bat under the application selectorMemo batch folder MAX 10 NEEK 111 WWW terasic com August 3 2015 www terasic com S n As Chapter 8 Programming the Configuration Flash Memory This tutorial provides comprehensive information that will help you understand how to configure MAX 10 NEEK Board using internal configuration mode The
4. MAX 10 NEEK FPGA Development Kit User Man EN WWW terasic com Copyright 2003 2015 Terasic Inc All Rights Reserved CONTENTS _ Chapter 1 MAX 10 NEEK Development 2 3 LUN BI Se e ru X TTE OmU 3 LUPA PES 10 NEEK System 4 ie Geine Help 4 Chapter 2 Introduction of the MAX 10 NEEK Board 5 2 1 Layout and ossi d lupe uidi Deos patei 5 2 2 Block Diagram of the MAX TO NEEK uetus aco head aeos 7 Chapter 3 Using the MAX 10 Board 10 3 1 Configuration of 10 FPGA on MAX 10 NEEK esee 10 0 2 Board SANUS Elements 16 XS LOCI Rr TL MIR 17 3 4 Peripherals Connected to the 00 0 000000 nnn nnns 18 Chapter 4 NEEK10 System Builder eee eee 43 OM NNI 43 Desin 43 23 Usme INTE ITO System BU E 45 Chapter 5 RTL Example GoOBS envi ruin ea UU Ris Rasa oia VR OCDE 50 S
5. Clock Input reset Reset Input Clock Input sD reset Rezet Input valen Memory Mapped Slave walen Memory Mapped Master ag ise mae Trigle Speed Ethernet control port clock connection a Input reset connection Reset Input contrel port Avalon Memory Mapped Slave pes tx clock connection ock Input tse mac pos mac comneetion Input tze mac mac rz clock connection UX pez rz clock connection sac status connection cemnection ICon amp si t ize mac mac comnectiom receive_clock commection Clock Input transei t_cleck_commection Clock Input receive Streaming Source transmit Avalon Stressing Sink mac medio cesnacti en dae mac mac mdio connection misc cesmmection i tse mac mac misc commection C sgdma tu ek ondait ise mac mac status conmeetion reset esr descriptor read descriptor write ear irq s read sut Ej sg na rx elk reset esr Avalon Memory Mapped Slave descriptor read valen Memory Mapped Master descriptor erite Avalen Memory Mapped Master esr irq Interrupt Sender in Avalon Streaming Sink s write Avalon Memory Mapped Master E descriptor memory ip Meecry GAN RON E slew periph bridge alea Clock Crossing Bridge timer i E high res timer E performance counter erfermsance Counter Unit B led pio Parallel 1 0 B dipss_pie Parallel 1 0 hc
6. Execute the demo batch file painter bat under the folder lcd painteremo batch The painter GUI will show up on the LCD panel 6 7 Digital Accelerometer Demonstration This demonstration shows a bubble level implementation based on a digital accelerometer We use protocol to control the ADXL345 digital accelerometer and the APDS 9301 Miniature Ambient Light Photo Sensor The LCD displays the interface of our demo When tilting the MAX 10 NEEK the ADXL345 measures the static acceleration of gravity In our Nios II software we compute the change of angle in the x axis and y axis and show the angle data on the LCD display The value of light sensor will change as the brightness changes around the light sensor Figure 6 32 shows the hardware system block diagram of this demonstration The system 15 clocked by an external 50M Hz Oscillator Through the internal PLL module the generated 100MHz clock is used for Nios II processor and other components and there is also 40M Hz for low speed peripherals MAX 10 NEEK 94 www terasic com Tijasic August 3 2015 www terasic com 50 MHz ouqe 4 uigjes S t 7 EF ADXL345 Controllers Le A b 4 y 4 APDS 9301 Figure 6 32 Block diagram of the digital accelerometer demonstration B Demonstration Source Code e Project directory gsensor lightsensor lcd e Bit stream
7. an an an B wser pie pushbta 10 Parallel 1 0 P WR current filter All Interfoces Cleek exported ext lk 50 pll 0 exported Base 010900 2400 10900 1800 x09 020000 0000 Figure 6 21 Qsys Builder Figure 6 22 shows the connections for programmable 10 100 1000Mbps 25 2 Osc 25 2 5 MHz Reference Clock Optional tie to 0 if not used 10 100 1000 PHY 125 25 2 5 MHz End 0x0900 248f Dx07 f ffff tx m tx d 3 0 m tx en m tx err gm tx d 7 0 gm tx en gm tx err eth mode set 10 100 1000 m_rx_d 3 0 m rx err gm rx d 7 0 gm rx dv gm rx err Ethernet Figure 6 22 PHY connected to the MAC via RGMII 86 TijasiC MAX 10 NEEK www terasic com Ethernet operation via www terasSic com August 3 2015 JA DTE n A V After the Qsys hardware project has been built develop the Qsys software project whose basic architecture is shown in Figure 6 23 The top block contains the Nios II processor and the necessary hardware to be implemented into the MAX 10 NEEK board The software device drivers contain the necessary device drivers needed for the Ethernet and other hardware components to work The HAL API block provides the interface for the software device drivers while the Micro C OS II provides communication services to the NicheStack and the Socket Server The Nic
8. 10 device on MAX 10 NEEK Board supports dual image boot This tutorial explains the details of the dual image boot The following sections provide a quick overview of the design flow 8 1 Internal Configuration The internal configuration scheme for all MAX 10 devices except for 10M02 device consists of the following mode e Dual Compressed Images configuration image is stored as image0 imagel in the configuration flash memory CFM e Single Compressed Image e Single Compressed Image with Memory Initialization e Single Uncompressed Image e Single Uncompressed Image with Memory Initialization In dual compressed images mode you can use the BOOT_SEL pin to select the configuration image The High Level Overview of Internal Configuration for MAX 10 Devices as shown in Figure 8 1 MAX 10 Device Configuration Data CRAM JTAG In System Programming Internal Configuration CFM Figure 8 1 High Level Overview of Internal Configuration for MAX 10 Devices MAX 10 NEEK 112 www terasic com August 3 2015 www terasic com JA DTE pA Before internal configuration we need to program the configuration data into the configuration flash memory CFM The CFM will be part of the programmer object file pof programmed into the internal flash through the JTAG In System Programming ISP During internal configuration MAX 10 devices load the configuration RAM CRAM with configuration data fro
9. 22 Add Device T up pu Down xs Figure 3 4 FPGA detected in Quartus programmer 4 Right click on the FPGA device and open the sof file to be programmed as highlighted in Figure 3 5 MAX 10 NEEK 12 www terasic com Tijasic August 3 2015 www terasic com JA DTE n AN dp Programmer Chain2 cdf Les a Xo ICI Enable real time ISP to allow background programming when available File Device Checksum Usercode Program Verify Blank Examine Security Erase ISP Configure Check Bit CLAMP E MEE lt none gt H0MSODAES TEES EE Select All Ctrl A Save File Add IPS Change 5 File Delete IPS File Add EKF File Change EKP File Delete EKP File Change PR Programming File Delete PR Programming File Chanae Flash Device Delete Flash Device __ 88 Add Device Figure 3 5 Open the sof file to be programmed into the FPGA device 5 Select the sof file to be programmed as shown in Figure 3 6 MAX 10 NEEK 13 www teraSic com asic August 3 2015 www terasic com JA DTE n AN ip Select New Programming File My Computer my first fpga pof my first fpga sof Files of type Programming Files sof pof jam jbc ekp jic Figure 3 6 Select the sof file to be programmed into the FPGA device 6 Click Program C
10. SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class WWw terasic com August 3 2015 ANU S nA o 3 4 8 QSPI Flash The MAX 10 NEEK supports a 512M bit serial NOR flash device for non volatile storage user data and program This device has a 4 bit data interface and uses 3 3V CMOS signaling standard Connections between MAX 10 FPGA and Flash are shown in Figure 3 21 Table 3 9 shows the DDR3 interface pin assignments U46 FLASH DATA 3 HOLD n DQ3 FLASH DATA 2 W n Vpp DQ2 NBD 8YAN FLASH DATA 1 DO FLASH DATA O0 MAX 1 0 FLASH DCLK FLASH NCSO FLASH RESET n FLASH Figure 3 21 Connections between MAX 10 FPGA and QSPI Flash Table 3 9 Pin Assignment of QSPI Flash Signal Name FPGA Pin No Description Standard FLASH DATA O0 PIN AB18 FLASH Data 0 3 3V FLASH DATA 1 PIN AA19 FLASH Data 1 3 3V FLASH DATA 2 PIN AB19 FLASH Data 2 3 3V FLASH DATA 3 PIN AA20 FLASH Data 3 3 3V FLASH DCLK PIN AB17 FLASH Data Clock 3 3V FLASH NCSO PIN AB21 FLASH Chip Enable 3 3V FLASH RESET n PIN AB20 FLASH Chip Reser 3 3V 3 4 9 Ethernet The board supports Gigabit
11. elf output lt you software name flash boot2 SOPC KIT NIOS2 components altera nios2 boot loader cfi srec e Convert the software flash file to binary file using the following command e Nios2 elf objcopy I srec O binary your software name gt flash your software name gt bin 2 e In the Input files to convert table choose the application_selector sof for the Page_O sof data Then add a sof item Page 1 sof data and choose the sof file of your design Enable the Create config data RPD checkbox as shown in Figure 7 6 Click the generate to convert the file 3 Output programming file Programming file type Programmer Object File pof 7 Options Boot info Configuration device 16 Mode Internal Configuration Z Advanced Remote Local update difference file IONE Create Memory Map File Generate test map V Create config data RPD Generate test auto rpd Input files to convert 4 SOF Data i application selector sof 10 500 484 5 4 SOF Data a hdmi rx sof 10 500 484 5 eo ae Figure 7 6 Setting Convert Programming File e In the project directory you will find the generated file test pof and test_auto rpd The rpd file is the raw program data file which is been written into the onchip flash Copy the application_hw exe in tool directory in application project path to your own project directory Double click the executable file then
12. 2015 www terasic com S n A B Design Tools e Quartus II v15 0 64 bit B Demonstration Source Code Project directory power monitor Bitstream used power monitor sof B Demonstration Batch File e Demo batch file folder Demonstrations power monitoridemo batch Batch file test bat FPGA configuration file power monitor sof B Demonstration Setup Please make sure Quartus II 1s installed on the host PC Connect the NEEK10 board 78 to the host PC with USB cable and install the USB Blaster II driver e Plug in the adapter to the NEEK10 Board and power it up e Execute the demo batch file test bat from the directory power monitorlemo batch e The two 7 segments on the NEEIO board will display mW of the bus chosen in decimal as Figure 5 3 _ 10 2 Panasonic Imm HH 4115 E Figure 5 3 Display power mW on the 7 segments and LED MAX 10 NEEK 54 WWW terasic com August 3 2015 www terasic com NOTES RA o e The SW 2 0 can choose which bus to be displayed on the two 7 segments according to the Table 5 2 Table 5 2 Switch setting for power SUB POWER SW 2 0 1 2VCC e 000 1 5VCCIO 001 2 5VCCIO 010 2 5VCORE 011 3 3 VCCIO 100 5 0VCC 101 5 3 ADC Potentiometer Nowadays voltage and current monitors play a significant role in high reliability system Most of applications can be implemented by an Analog to Digital Converter ADC MAXIO NEEK provi
13. 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www terasic com August 3 2015 AU S RYA o PIXEL D 21 PIN AB6 Parallel Port Data 3 3V MIPI PIXEL D 22 PIN AA6 Parallel Port Data 3 3V MIPI PIXEL D 23 PIN Y6 Parallel Port Data _ 3 3V MIPI RESET n PIN AA3 Master Reset signal for camera and bridge device 3 3V PIXEL 10 Parallel Port Clock signal 3 3V PIXEL PIN AA2 Parallel Port Horizontal Synchronization signal 3 3V MIPI PIXEL VS PIN 1 Parallel Port Vertical Synchronization signal 3 3V CS n PIN 07 Chip Select 3 3V REFCLK W17 Reference Clock Input of bridge device 3 3V 2 SCL 1 2 Clock for bridge device 3 3V 2 SDA 2 2 Data for bridge device 3 3V CAMERA PWDN R11 Power Down signal of MIPI camera 3 3V CAMERA I2C SCL PIN A20 2C Clock for camera 2 5V CAMERA I2C SDAPIN B19 2C Data for camera 2 5V 3 4 12 7 0 Inch Color LCD with 5 point Capacitive touch MAX 10 NEEK provides a 7 0 inch color LCD module which 15 an all purpose 5 point capacitive touch screen for FPGA applications Figure 3 25 shows the connection of 7 0 inch color LCD and MAX 10 FPGA The pin assignment associated to this 7 0 inch color LCD interface 1s shown in Table 3 12 S RYA MTLHSD MAX 10 MTL RI7 0 MTL G 7
14. Configure FPGA Create New NEEK10 System Builder Project Generate Quartus Project and Document Figure 4 1 Design flow of building a project from the beginning to the end MAX 10 NEEK 44 www terasic com Tijasic August 3 2015 www terasic com AN S n A e 4 3 Using NEEK10 System Builder This section provides the procedures in details on how to use the NEEK10 System Builder B Install and Launch the NEEK10 System Builder NEEK10 System Builder is located in the directory Tools ystemBuilder of the NEEKIO System CD Users can copy the entire folder to a host PC without installing the utility After the execution of the NEEKIO SystemBuilder exe on the host PC a window will pop up as shown in Figure 4 2 MAX 10 NEEK V1 0 0 2 NB SRYA System Configuration munaan Project Name 10 iv CLOCK iv Button x 5 LEDx10 Switch x 10 Seqment x2 iv Power Monitor En m G sensor Humidity Sensor MAD NEEK 10353 iv Light Sensor iv Audio Codec ESSERI 774 amp HDMI RX 9 microSD Card PS2 iv DAC iv QSPI Flash iv UART to USB DDRS SDRAM Ethernet CS2 Camera LCD Touch Panel Default Setting TMD 2x6 GPIO Header Save Setting Generate None Prefix Name Load Setting Exit Figure 4 2 The GUI of NEEK10 System Builder B Enter Project Name The pro
15. Figure 8 13 Add Hex Data Window e In the Input files to convert table choose the sof and generate the pof e Open the programmer tool and add the pof generated above to download into the onchip flash Power cycle the board the Nios II software will be running after the image has been loaded The Nios II processor can also load software from the QSPI flash on MAX 10 NEEK board Users can refer to Application Selector demonstration for how to design the Nios II processor load software from the QSPI flash MAX 10 NEEK 119 WWW terasic com August 3 2015 www terasic com Chapter 9 Appendix Revision History Change Log Initial Version Copyright Statement Copyright 2015 Terasic Inc All rights reserved MAX 10 NEEK 120 www terasic com 1 24 51 August 3 2015 www terasic com
16. PIN E10 PIN H11 PIN E6 Seven Segment Digit O 6 Seven Segment Digit 1 0 Seven Segment Digit 1 1 Seven Segment Digit 1 2 Seven Segment Digit 1 3 Seven Segment Digit 1 4 Seven Segment Digit 1 5 Seven Segment Digit 1 6 3 4 3 Power Monitor The MAX 10 NEEK has implemented three power monitor chips to monitor the FPGA core power and VCCIO power voltage and current Figure 3 16 shows the connection between the power monitor chip and 10 FPGA Through the serial interface the power monitor can be configured to measure remote voltage and remote current Programmable calibration value conversion times and averaging combined with an internal multiplier enable direct readouts of current in amperes and power in watts Table 3 5 shows the pin assignment of power monitor I2C 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V bus VCC 0 01 i i 2 Signal LTC2990 RYA Power Monitor SDA MAX 10 027 4 7K VCC3P3 Figure 3 16 Connections between the power monitor chip and the MAX 10 FPGA Table 3 5 Pin Assignment of Power Monitor I2C bus Signal Name FPGA Pin No Description Standard 2 SCL 8 Power Monitor SCL 3 3V 2 SDA 9 Power Monitor SDA 3 3V www terasic com MAX 10 NEEK 27 Tijasic August 3 2015 www terasic com ANU S RYAN 3 4 4 2x6 TMD Expansion Header The board has one 2x6 TMD Terasic Mini Digital expansion header The TMD header has 8
17. omm 3252 se eed ied ike gt li ADC IN2 m i EER 9 bs zit T CRE OMNES xe Ji Texas 04 7 8 4 EQ INSTRUMENTS 40 ip A DAC OUT 18 a Power die ic yo Monitor Panasonic im 2555 ti gt E G Sensor UART to USB QSPI Flash roug Dey i Micro SD Socket Touch 2 Connector foes ites Lene mee 1 iroda poe 1 ifte tenes i 5 8 5 8 _509 4 4 9 9 LED x10 t E Lor mes me m eem Big nek Humidity E E E iis Temperature me 5 Sensor 4 CONFIG SEL FPGA RST Button x5 DDR3 Switch x10 RECONFIG Figure 2 2 MAX 10 NEEK development board bottom view MAX 10 NEEK board has many features that allow users to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware is provided on the board Altera MAX 10 10 50 484 6 device USB Blaster II onboard for programming JTAG Mode 256MB DDR3 SDRAM 64 16 and 128 8 64MB QSPI Flash Micro SD card socket Five push buttons Ten slide switches Ten red user LEDs Two 7 segment displays Three 50MHz clock sources from the clock generator 24 bit CD quality audio CODEC with line in line out jacks On board microphone HDMI RX incorporates v1 4a features including 3D video supporting 800x480 7 0 inch Color
18. set 1 e 1 when the register content is renewed and cleared 1 e 0 when the register content is accessed Bit 6 of the MSB register is the sign bit Bit 5 through represent the result of bits D 13 8 two s complement conversion The LSB register holds the conversion bits D 7 0 The following equations are used to convert the register values to get the differential voltage VpirrenENTiAL D 14 0 19 42uV if Sign 0 VpIFFERENTIAL D 14 0 1 719 420 if Sign 1 REGISTER ADDRESS t DESCRIPTION 00h SINUS BUSY State Conversion Status Controls Mode Single Repeat Celsius Kelvin 02h Triggers an Conversion 09h NA unused Address 04h Tw MS R internal Temperature MSB 05h 080 internal Temperature LSB OFh Vec LSB Vee LSB wmm CAC WEM VE VO or Tar 88 wu 8 Figure 6 3 Register of LTC2990 Figure 6 4 shows the control register of LTC2990 The control register must be configured properly to measure the voltage difference V1 V2 Bits b 2 0 should be set to 110 for measuring voltage difference V1 V2 and V3 V4 Bits 4 3 should be set to 00 for all measurements MAX 10 NEEK 69 www terasic com August 3 2015 www terasic com ANU S n A s BiT NAME OPERATION b7 Temperature Reported In Celsius 0 Default Kelvin 1 b6 Repeated Acquisition 0 Default Single Acquisition 1 bs Reserved b 4 3 Mo
19. 6 the NEEKIO System Builder will generate the corresponding Quartus II files and documents as listed in Table 4 1 Files generated by the NEEK10 System Builder MAX 10 NEEK 48 www terasic com Tijasic August 3 2015 www terasic com AU S n A e MAX 10 NEEK V1 0 0 2 ATERA System Configuration airi adicit Project Name MAX 10 NEEK FPGA Board iv CLOCK iv Button x 5 iv LEDx10 iv Switch x 10 i Segment x2 iv Power Monitor orge z v G sensor v Humidity Sensor WAS NEEK 10 4 iv Light Sensor iw Audio Codec ys v HDMI microSD Card Iv PS2 iv DAC QSPI Flash UART to USB DDRS SDRAM Ethernet CS2 Camera LCD Touch Panel Default Setting TMD 2x6 GPIO Header Prefix Name Load Setting Exit Figure 4 6 Generate Quartus project Table 4 1 Files generated by the NEEK10 System Builder No Filename Description _ _ _ __ _ _ 1 lt Projectname gt v Top level Verilog HDL file for Quartus Il 2 Project name gt qpf Quartus II project file ul Project name gt qsf Quartus setting file Project name gt sdc Synopsis design constraints file for Quartus ll Project name gt htm Pin assignment document Users can add custom logic into the project and compile the project in Quartus II to generate the SRAM Object File sof MAX 10 NEEK 49 www terasic com Tijasic August 3 2015 www terasic com Ch
20. 72 Ports COM amp LPT re EY p a Processors DR 4 Sound video and game controllers gt System devices gt Universal Serial Bus controllers Figure 6 9 Check the Assigned Com Port Number On PC Open the putty software type in the parameter as shown in Figure 6 10 and click open button to open the terminal Here 15 a link for you to download the putty terminal Download Putty asic MAX 10 NEEK 74 www terasic com August 3 2015 ANU S RYA o PuTTY Configuration Category Session Terminal Keyboard gt Bell Features Window i Appearance Behaviour Translation z Selection i Colours Connection Data n Telnet z Rlogin SSH i Serial Basic options for your PuTTY session Specify the destination you want to connect to Serial line Speed Connection type Raw Telnet Hlogin SSH amp Seral Load save or delete a stored session Saved Sessions COMS COM Load COM13 COM14 15 3 COMT17 COM2 Delete COMS E Save Close window on exit Always Never Only on clean exit Cancel Figure 6 10 Putty Terminal Setup e sure Quartus and Nios II are installed on your PC e Connect an USB cable to the MAX 10 NEEK board J8 and install USB Blaster driver if necessary e Execute the demo batch
21. Help DM TP Catalog 5 ofo x fe System unsaved Path dusl boot lx System Contents 22 Proiect se on e Description T Component E clk 0 Clock Source BI System ck Clock Input eer 5 clk in reset Reset Input clk Clock Output clk reset Reset Output Arithmetic Bridges and Adaptors Clocks PLLs and Resets Configuration and Programn 4 c Clock Input e 7 Reset Input Avalon Memory Mapped Slave F m P B YS unssved unssved qsys Hj clk BD reset Gk clk 0 c B avalon lt nje Eid F WB Current filter All Interfaces Message BA 1 Warning A unsaved dual boot dual_boot avalon must be connected to an Avalon MM master 0 Errors 1 Warning A Figure 8 3 Rename and Connect Dual Boot IP e Save the Qsys as dual_boot qsys and generate the HDL files Add the dual_boot qip into the quartus setting file and add the qsys instance in the top design file as shown in Figure 8 4 MAX 10 NEEK 114 www terasic com August 3 2015 www terasic com AN S RYA o if Structural coding if dual boot u0 Clk clk 10 CLK1 50 if clk clk reset reset n l bl1 reset reset n ir Figure 8 4 Add the Qsys instance in Top e The configuration mode is set in Device and Pin Options window Choose Assignments gt Device to op
22. I PS2 Mouse DetHmofsttatlOID esee ono tt 9o EE aenea TEE UM UM RPM NM F 50 IPON r DION O E CMM MINER 53 SS ADC R 55 Domon NINO 57 5 5 ADE MIC LCD Demonstration RE UU 60 5 6 HDMI RX Demonstration 63 Chapter NIOS Based Example 6 2 2 67 MAX 10 NEEK 1 www terasic com Tijasic August 3 2015 www terasic com AN S RYA o 6 1 PO WEE MONO m 67 VARTO USB OO EED 72 6 3 SD Card AUdiOJDeIHODSCEHHODGu isis sette basi niea seva pila nosse ut basis enses Dile ose ue ne 75 04 DDR SDRAM Test Dy Nios M dias tosis a edendo urea 80 6 5 BPthernet sockel SCI VEL NON NC 83 EEDE In 90 6 7 Digital Accelerometer Demonstration nennen nnn nnns 94 6 8 Humidity Temperature Ses OF NER E TO T 96 69 LCD CAMERA Demonstration lt 99 Chapter 7 Application 105 TA Ready t R n SD Card dE es Sis UL Gee tieu asa Pod de Ld 105 7 22 Application Selector Details ETE EEEa OaE EENE 106 7 3 Running
23. Input SMA Connectors The MAX 10 NEEK board implements two analog input SMA connectors The analog inputs are amplified and translated by Texas Instruments INAI59 gain of 0 2 level translation difference amplifier then the amplifier s outputs are fed to dedicated single ended analog input pins for MAX 10 build in ADCI and ADC2 respectively With the amplifiers the analog input of two SMAs MAX 10 NEEK 24 www terasic com 1 4 5 August 3 2015 www terasic com S nA e support from 6 25V to 6 25V range Figure 3 19 shows the connection of SMA connectors to the FPGA Figure 3 19 Connection of SMA connectors to the FPGA 3 4 7 DDR3 Memory The board supports 256MB of DDR3 SDRAM comprising of one 16 bit 64 16 DDR3 device and one 8 bit 128Mx8 device The DDR3 devices shipped with this board are running at 300MHz with the soft IPof MAX 10 external memory interface solution Figure 3 20 shows the connections between the DDR3 and MAX 10 FPGA Table 3 8 shows the DDR3 interface pin assignments MAX 10 NEEK 23 WWW terasic com Tijasic August 3 2015 www terasic com Signal Name DDR3 A 0 DDR3 A 1 DDR3 A 2 DDR3 A 3 DDR3 A 4 DDR3 A 5 DDR3 A 6 DDR3 7 DDR3 8 DDR3 A 9 DDR3 A 10 DDR3 A 11 DDR3 A 12 DDR3 A 13 DDR3 A 14 DDR3 0 DDR3 BA 1 DDR3 BA 2 AM S RYAN MAX 10 Data x16 DDR3 SDRAM 64M x16 Address amp Command DDR3 SDRAM 128M x8 Data x8 Figure 3 20 Connections
24. LCD with 5 point Capacitive touch Gigabit Ethernet PHY with RJ45 connector UART to USB USB Mini B connector 8M pixel CS2 color camera input MAX 10 NEEK 6 www terasic com Tiasic August 3 2015 www terasic com JA DTE RA o One ambient light sensor One humidity and temperature sensor One accelerometer One external 16 bit digital to analog converter DAC device with SMA output Potentiometer input to ADC Two MAX 10 FPGA ADC SMA inputs One 2x10 ADC header with 16 analog inputs connected to MAX10 ADCs 2 2 Block Diagram of the MAX 10 NEEK Board Figure 2 3 is block diagram of the board the connections are established through the MAX I0 FPGA device to provide maximum flexibility for users Users can configure the FPGA to implement any system design USB Mini B Power Adaptor 2x5 Header x2 A JTAG x6 5V DC Jack MIP Connector x8 2x6 PMOD Camera Module Temperature Sensor SMA x2 2x10 ADC Header Potentiometer 512Mbits QSPI Flash 10M50DAF484C6G e 36 HDMI Connector USB Mini B RJ45 x31 7 Touch LCD 800x480 1 x14 Lf LI 7 Seg x2 x10 x10 x1 x1 x1 x5 9 280048484488 RECONFIC FPGA Push Button x5 LED x0 Button RST AAABAARABR Slide Switch x10 BOOL_SEL Figure 2 3 Block diagram of MAX 10 NEEK MAX 10 NEEK 4 www terasic com Tijasic Aug
25. Options Boot info Configuration device EPCE16 Mode 7 I Advanced Remote Local update difference file NONE V Create Memory Map File Generate dual boot map Create CvP files Generate dual boot periph pof and dual boot core rbf Create config data RPD Generate dual boot auto rpd Input files to convert File Data area Properties Start Address d Hex Dat SOF Data Page 0 auto Figure 8 6 Convert File Window Setting e In the Input files to convert table click Add File button to choose the sof file for image0 Then press the Add Sof Page button and add a sof for imagel as shown in Figure 7 Click generate button to generate the object file dual_boot pof Programming file type Programmer Object File pof Options Boot info Configuration device EPCE16 Mode Internal Configuration Y File name dual boot pof Advanced Remote Local update difference file NONE E Create Memory Map File Generate dual_boot map Create CvP files Generate dual_boot periph pof and dual_boot core rbf E Create config data RPD Generate dual boot auto rpd Input files to convert File Data area Properties Start Address Add Hex Data 4 SOF Data Page 0 auto m image0 sof 10M50DAF484ES TE 4 SOF Data Page 1 auto Add File iamge1 sof 10 500 484 5 Rer Figure 8 7 Add Sof Files e The final step is to download the pof into MAX10 FPGA Open the progra
26. Player Audio Stream Audio AudioConfig Audio 2 2 Memory SPI Codec rem Figure 5 14 Block Diagram of the HDMI RX demonstration Video data input would require a data buffer and we use DDR3 controller to communicate with the external DDR3 memory onboard The final video outputs to the multi touch panel The dot clock of this LCD panel is 33MHz and therefore it would require a PLL which can generate 33MHz When there 15 no video data the screen will display a color of blue representing no video data input MAX 10 NEEK 63 WWW terasic com August 3 2015 www terasic com JA DTE p AN The audio signal decrypted by HDMI RX ADV7011 will be sent to Audio Codec In order for the Audio Codec to play the audio proper settings would have to be made In this demo the setting has been pre written in the Audio memory The AudioConfig module in the block diagram will read out the data stored in the Audio Memory and use SPI protocol to configure the Audio Codec chip If you wish to change the Audio memory setting kindly refer to the following section Audio Memory Setting B Audio Memory Setting When you need to modify internal setting of audio memory you can open up the Loop hex file under Audio SPI directory using Quartus When opening up the file you will be requested to input the word size type in 16 and click OK and you will see Audio memory Table in Figure 5 15 From the Audio memory Table it can be seen the data is 010
27. Receiver chip The other 50MHz clock signal 15 connected to MAX CPLD of USB Blaster One IOMHz clock signal is connected to PLLI and PLL3 of FPGA the outputs of these two PLLs can drive ADC clock The associated pin assignment for clock inputs to FPGA I O pins is listed in Table 3 2 CDCE949 ANU RYAN MLAX 10 MAX10 CLK1 50 50MHz T MAX10 CLK2 50 50MHz CLK6N MAX10 CLK3 50 50MH ADEL LZ CLK2P 10 10MHz Ethernet CLK 25 25MHz Transceiver HDMI Receiver HDMI_CLK_28 28 63636MHz XTALP USB Controller UB2 CLK 24 24MHz of UB2 MAXII CLK 50 50MHz D II CPLD Figure 3 10 Block diagram of the clock distribution on MAX 10 NEEK MAX 10 NEEK 17 www terasic com Tijasic August 3 2015 www terasic com S nA e Table 3 2 Pin _ of Clock Inputs Signal Name EPGA Pin No Pin No VO Standard 10 CLK1 50 5 7 50MHzclock input 10 CLK2 50 V9 50 MHz clock input 10 CLK3 50 4 7 50MHzclock input ADC CLK 10 PIN 10MHzclock input 3 4 Peripherals Connected to the FPGA This section describes the interfaces connected to the FPGA User can control or monitor different interfaces with user logic from the FPGA 3 4 1 User Push buttons Switches LEDs The board has five push buttons connected to the FPGA as shown in Figure 3 11 MAX 10 devices support Schmitt trigger input on all I O pins A Schmitt trigge
28. USB of MAX 10 NEEK system CD Figure 3 30 shows the connections between the MAX 10 FPGA FT232R chip and the USB Mini B connector Figure 3 34 lists the pin assignment of UART interface connected to the MAX 10 FPGA MAX 10 NEEK 37 www terasic com Tijasic August 3 2015 www terasic com J18 FT232 DP FT232 DM rm PEL ci USB Mini B Connector UART RESET n FT232R Figure 3 30 Connections between the HPS and FT232R Chip Table 3 16 Pin Assignment of UART Interface Signal Name FPGA Pin Description IO Standard UART E16 FPGA UART Receiver 2 5V UART TX PIN E15 FPGA UART Transmitter 2 5V UART RESET n PIN D15 Reset Signal for UART Device 2 5 3 4 19 Ambient Light Sensor 10 NEEK has a Light to Digital Ambient Light Sensor APDS 9301 that converts light intensity to digital signal output capable of I2C interface with I2C digital interface and programmable event interrupt output The digital output of APDS 9301 will be input to the MAX 10 FPGA where illuminance I lux is derived using an empirical formula to approximate the human eye response Figure 3 35 shows the connection of APDS 9301 to the 10 FPGA Table 3 17 lists the Ambient Light Sensor pin assignments VCC3P3 U51 APDS 9301 ANU S RIAN MAX 10 SCL SDA ANT Figure 3 31 hows the connections between the MAX 10 FPGA and Ambient Light Sensor MAX 10 NEEK 38
29. a new file test_hw rpd will be generated e Create a new subdirectory and name it whatever you like for the title of your application to be shown in the application selector Using an SD card reader copy the directory onto an SD Card into a directory named Application Selector The directory structure on the SD Card should look like this Application SelectorVc application name gt lt application _name gt _sw bin lt application _name gt _hw rpd 4 e Place the SD card in the MAX 10 NEEK board and switch on the power The Application Selector will start up and you will now see your application appear as one of the selections Q Note 1 You can t use an initialized memory in the design for dual compressed image configuration mode or you will meet an error in the Quartus Fitter process MAX 10 NEEK 109 www terasic com Tijasic August 3 2015 www terasic com S n Ae 2 The users can convert the elf to bin with the batch file in elftobin batch directory Copy the elf file to the directory and rename the file to test elf Make sure the address for the OSPI flash is right and click test bat to convert the file automatically 3 The sof file of your design must be add to Page 1 sof data please double check it 4 If the sof file don t contain a Nios II processor it is not necessary to generate the your software name gt bin and copy it to your SD card 7 5 Restoring the Factory Image This section describes som
30. between the DDR3 and FPGA Table 3 8 Pin Assignment of FPGA DDR3 Memory FPGA Pin No PIN U20 PIN F19 PIN V20 PIN G20 PIN F20 PIN E20 PIN E21 PIN Y20 PIN C22 PIN D22 PIN J14 PIN E22 PIN G22 PIN D19 PIN C20 PIN W22 PIN 21 PIN Y22 MAX 10 NEEK asic www terasic com Description I O Standard DDR3 Address 0 SSTL 15 Class DDR3 Address 1 SSTL 15 Class DDR3 Address 2 SSTL 15 Class DDR3 Address 3 SSTL 15 Class DDR3 Address 4 SSTL 15 Class DDR3 Address 5 SSTL 15 Class DDR3 Address 6 SSTL 15 Class DDR3 Address 7 SSTL 15 Class DDR3 Address 8 SSTL 15 Class I DDR3 Address 9 SSTL 15 Class DDR3 Address 10 SSTL 15 Class DDR3 Address 11 SSTL 15 Class DDR3 Address 12 SSTL 15 Class DDR3 Address 13 SSTL 15 Class DDR3 Address 14 SSTL 15 Class DDR3 Bank Address 0 DDR3 Bank Address 1 DDR3 Bank Address 2 SSTL 15 Class SSTL 15 Class SSTL 15 Class 26 www teraSic com August 3 2015 AN S RYA o DDR3 CAS n DDR3 CKE DDR3 CLK n DDR3 CLK p DDR3 CS n DDR3 DM 0 DDR3 DM 1 DDR3 DQ 0 DDR3 DQ 1 DDR3 DQ 2 DDR3 DQ 3 DDR3 4 DDR3 DQ 5 DDR3 6 DDR3 DQ 7 DDR3 8 DDR3 DO 9 DDR3 DQ 10 DDR3 DQ 11 DDR3 DQ 12 DDR3 DQ 13 DDR3 DQ 14 DDR3 DQ 15 DDR3 DQ 16 DDR3 DQ 17 DDR3 DQ 18 DDR3 DQ 19 DDR3 DQ 20 DDR3 DQ 21 DDR3 DQ 22 DDR3 DQ 23 DDR3 DOS n 0 DDR3 n 1 DDR3 DOGS p 0 DDR3 p 1 DDR3 ODT DDR3
31. file uart usb bat under the batch file folder uart_usb demo_ batch e The result of Nios II terminal and putty terminal is shown in Figure 6 11 Initializing CPU cache if present OK Downloaded 88KB in 0 1s Verified OK Starting processor at address 0x01080240 nios2 terminal connected to hardware target using JTAG UART on cable nios2 terminal NEEK10 USB 1 device 1 instance 0 nios2 terminal Use the IDE stop button or Ctrl C to terminate MAX10 UART TO USB demo before you send the command you must ensure uart to usb driver has been installed on you computer and ensure a usb cable is connected between max10 and your computer please execute putty and setup parameter correctly ensure that you open the correct common port the baud rate should be 9600 the data bits should be 8 no verify bit and 1 stop bit you can send character to control the led state send 0 9 to toggle the related led send a or A to turn on all leds and n or N to turn off all Figure 6 11 Running Result of Uart USB Demo e n the putty terminal type any character to change the LED state Type a digital number to toggle the LEDR 9 0 state and type a A or n N to turn on off all LEDR 6 3 SD Card Audio Demonstration Many commercial media audio players use a large external storage device such as an SD Card or MAX 10 NEEK asic www terasic com 75 www terasic com August 3 2015 NOTES RA o CF card to store music or video files Su
32. focus function B Design Tools e Quartus II v15 0 e Nios II Eclipse 15 0 B Demonstration Source Code e Quartus project directory lcd camera e Nios II Eclipse project workspace lcd camera Noftware B Demonstration Batch File e Demo batch file folder demonstrationsNcd cameraMemo batch B Demonstration Setup Please follow the procedures below to setup the demonstration MAX 10 NEEK 103 WWW terasic com Tijasic August 3 2015 www terasic com www terasic com JA DTE RYA Connect a USB cable between the host PC and the USB connector 78 on the MAX10 NEEK board Power on the MAX10 NEEK board Please make sure Quartus II has been installed on the host PC Execute the demo batch file camera bat under the batch folder Icd_camera demo_ batch The LCD panel will start showing the video captured from the camera Use two point zoom in or zoom out gesture to perform zoom fucntion User single touch to specify the focus area User five point touch to stop the camera video streaming and any touch to resume the video streaming MAX 10 NEEK 104 www terasic com Tijasic August 3 2015 Chapter 7 Application Selector The application selector utility is the default code that powers on the FPGA and offers a graphical interface on the LCD allowing users to select and run different demonstrations that reside on one micro SD card 7 1 Ready to Run SD Card Demos You can find several ready to run demos in y
33. on that hardware a Nios II ELF file The critical steps are e The hardware design must contain a dual configuration IP in the Qsys design 1 e IF the sof contains a Nios II processor The hardware design must contain an Altera QSPI Flash MAX 10 NEEK 107 www terasic com 1 4 5 August 3 2015 www terasic com AN S RYA o controller as shown in Figure 7 3 Altera Generic QUAD SPI controller altera generic quad spi controller Parameters Configuration dewice type I250512A83GSF40F Choose I mode QUAD llumber of Chip Selects used Figure 7 3 Altera QSPI Flash Controller Setting In Qsys e The avl mem interface of the Altera QSPI Flash controller must be connected to the data master and instruction master interface of the Nios II CPU Set the CPU reset vector and exception vector to the QSPI flash zone with offset 0 as shown in Figure 7 4 Vectors Caches and Memory Interfaces Arithmetic Instructions MMU and MPU Settings Debug Advanced Features Keset Vector Reset vector memory ext flash ayl mem Reset vector offset 1200000000 Reset vector ax eOOO0O000 Exception Vector Exception vector memory mem if ddr3 avl Exception vector offset 7 00000020 Exception vector 7 00000020 Fast Miss Exception vector memory Fast ILE Miss Exception vector offset 00000000 Fast ILB Miss Exception vector 7 00000000 Figure 7 4 Nio
34. second error occurs the device waits for a reconfiguration source If the auto reconfig 1s enabled the device will reconfigure without waiting for any reconfiguration source 5 Reconfiguration is triggered by the following actions e Driving the nSTATUS low externally Asserting internal or external nCONFIG low Asserting RU_nCONFIG low MAX 10 NEEK 113 www terasic com August 3 2015 www terasic com ANU S n AN 8 2 Using Dual Compressed Images The internal configuration scheme for all MAX 10 devices except for 10M02 device consists of the following mode e Dual Compressed Images configuration image is stored as image 0 and image 1 in the configuration flash memory CFM e Single Compressed Image This section will just introduce how to use MAXIO device Dual Compressed Images feature If you don t need this feature skip this section Two main steps are necessary for a project support dual configuration mode e Add dual configuration IP e Modify Configuration Mode in device setting A Dual Configuration IP should be added in an original project so that the pof file can be programmed into CFM through it e Open Quartus project and choose Tools gt Qsys to open Qsys system wizard Create a new system and add the dual configuration IP Connect the logic as Figure 8 3 A Qsys unsaved asys D SVN DECA revC DECA_Dual_boot LedBreathe unsaved qsys Edit System Generate View Tools
35. selected The UFM zone is not used in this project and user can use it as a non volatile flash if necessary The software code for the image is stored in the QSPI flash memory offset 0x3c00000 address In addition the software code for the imagel is stored the QSPI flash memory offset 0x00 The Nios II processor loads the software from the QSPI flash after powering up so the reset vector of the CPU 15 set to the QSPI flash offset 0x3c00000 address 7 3 Running the Application Selector Connect power to the MAX 10 NEEK Insert the micro SD card with applications into the micro SD Card socket of MAX 10 NEEK Make sure the CONFIG SEL switch is set to 0 and Switch on the power SW 18 1 Scroll to select the demonstration to load using the side bar Tap on the Load button to load and run a demonstration 2 Q Note 1 If the board is already powered the application selector will boot from QPSI flash and a splash screen will appear while the application selector searches for applications on the SD Card 2 The application will begin loading and a window will be displayed showing the progress Loading will take about 1 minute according to size of the binary files 7 4 Creating Your Own Loadable Applications It is available to convert your own design into an application which is loadable by the Application Selector utility All you need 15 a program object image a POF file which contains the hardware and a software image which runs
36. the Application 107 7 4 Creating Your Own Loadable 5 107 7 5 Restoring he Factory a arni 110 Chapter 8 Programming the Configuration Flash 112 112 8 2 Using Compressed Eaa EE AEAEE R 114 Nios Load In sinele Boot 117 chapet o APPEND serenor EEE EE TEE 120 Revision 120 COPY AU ICM TT ETT 120 MAX 10 NEEK 2 www terasic com 1 4 5 August 3 2015 www terasic com Chapter 1 MAX 10 NEEK Development Kit MAX 10 NEEK from Terasic is a full featured embedded evaluation kit based upon the MAXIO family of Altera FPGAs It offers a comprehensive design environment with everything embedded developers need to create a processing based system The MAX 10 NEEK delivers integrated platform that includes hardware design tools intellectual property and reference designs for developing a wide range of audio video and many other exciting applications The fully integrated kit allows developers to rapidly customize their processor and IP to suit their specific needs rather than constraining their software around the fixed feature set of the processor The all in one embedded solution the MAX 10 NE
37. the block diagram of Power Monitor demonstration The ADC reference clock running at IOMHz is generated by PLL It feeds into ADC Hard IP in MAXIO device The analog voltage input comes from the VR controls the voltage level The control logic within the ADC Hard IP reads the digitized voltage data It then converts the data and displays the level value on two 7 segments Since none of the dot points of two 7 segments 15 connected to the MAX 10 so HEXI and HEXO shows the decimal point and the first digit after the decimal point respectively 50MHz 7 5 VR Analog Voltage Input Rae Logic Voltage Value Display Figure 5 6 Block diagram of ADC Potentiometer MAX 10 NEEK 56 www terasic com Tijasic oe August 3 2015 www terasic com ANU S n AN B Design Tools e Quartus II v15 0 64 bit B Demonstration Source Code Project directory Demonstrations adc_potentionmeter Bitstream used adc potentionmeter sof B Demonstration Batch File e Demo batch file folder Demonstrations adc_potentionmeter demo_batch Batch file test bat FPGA configuration file adc_potentionmeter sof B Demonstration Setup Please make sure Quartus II and USB Blaster II driver are installed on the host PC Connect the USB cable from the USB Blaster II port J8 on the NEEK board to the host PC Power on the NEEK board Execute the demo batch file test bat under the folder Demonstrations adc potentionmeter Memo batc
38. word clock WCLK are provided by the audio chip An OpenCore I2C controller is connected to the CODEC chip for the Nios II CPU to communicate with the CODEC chip Four PIO pins are connected to the micro SD Card socket SD 4 Bit Mode is used to access the micro SD Card and is implemented by software the other SOPC components in the block diagram are SOPC Builder built in components The PIO pins are also connected to the keys LEDs and switches MAX 10 NEEK 76 WWW terasic com August 3 2015 www terasic com ANU S p AN FPGA 50 MHz E e OpenCore 2 lt gt Controller 4 PIO Micro SD Controller LED KEY PLL System Intercoment Fabric switch Figure 6 13 Block diagram of SD Card Audio Demo Figure 6 14 shows the software stack of this demonstration SD 4 Bit Mode block implements the SD 4 Bit mode protocol for reading raw data from the SD Card The FAT block implements FAT16 FAT32 file system for reading wave files that are stored in the SD Card In this block only read function is implemented The WAVE Lib block implements WAVE file decoding function for extracting audio data from wave files The I2C block implements I2C protocol for configuring audio chip The Audio block implements audio FIFO checking function and audio signal sending receiving function The key and switch block acts as a control interface of the music player system MAX 10 NEEK 71 www terasic com Tijasi
39. 0 MTL B 7 0 MTL DCLK MTL VSD MTL INT E uL PL 7 Multi touch LCD MTL I2C SDA 800x480 lt gt Figure 3 25 Connections between 7 0 inch color LCD and MAX 10 FPGA Table 3 13 Pin Assignment of 7 0 inch LCD interface Signal Name FPGA Pin No MTL2 R 0 PIN U5 MTL2 R 1 PIN U4 MAX 10 NEEK www terasic com Description I O Standard Red Data LSB 3 3V Red Data 3 3V 33 www terasic com August 3 2015 AU S RYA o MTL2 R 2 PIN Red Data 3 3V MTL2 R 3 PIN W2 Red Data 3 3V MTL2 R 4 PIN U2 Red Data 3 3V MTL2 R 5 PIN V1 Red Data 3 3V MTL2 R 6 PIN T2 Red Data 3 3V MTL2 R 7 PIN T1 Red Data MSB 3 3V MTL2 G 0 PIN T5 Green Data LSB 3 3V MTL2 G 1 PIN T6 Green Data 3 3V MTL2 G 2 PIN R1 Green Data 3 3V MTL2 G 3 PIN R2 Green Data 3 3V MTL2 G 4 PIN R4 Green Data 3 3V MTL2 G 5 PIN P1 Green Data 3 3V MTL2 G 6 PIN R5 Green Data 3 3V MTL2 G 7 PIN R7 Green Data MSB 3 3V MTL2 0 PIN P4 Blue Data LSB 3 3V MTL2 B 1 PIN P5 Blue Data 3 3V MTL2 B 2 PIN N3 Blue Data 3 3V MTL2 B 3 PIN P8 Blue Data 3 3V MTL2 B 4 PIN N4 Blue Data 3 3V MTL2 B 5 PIN N8 Blue Data 3 3V MTL2 B 6 PIN N9 Blue Data 3 3V MTL2 B 7 PIN M8 Blue Data MSB 3 3V MTL2 DCLK PIN W1 Sample Clock 3 3V MTL2 HSD PIN N1 Horizontal Sync Input 3 3V MTL2 VSD PIN N2 Vertical Sync Input 3 3V MTL2 2 SCL PIN P9 2 Serial Clock for Touch Screen 3 3V MTL2 2 SDA PIN P10 2 Serial Data for Touch Screen 3 3V MTL2_INT PIN R
40. 0 at 00 2 position This means it will configure the Audio Codec Address 0x01 register the first 2bit to 0x00 the latter 2bit For more details on register settings please kindly refer to TLV320AIC3254 Application Reference Guide included in the System CD Add 0 41 42 44 7 ASCII 000108 0101 0100 0400 0851 OCZ 08 1100 3 02 1ES4 3FDS5 4000 4100 4200 447D 10 4508 46FF 0001 02C9 090C 0108 0201 0A40 18 0 08 0 08 1203 1303 0000 0000 0000 0000 Figure 5 15 Audio Memory Table B HDMI Receiver ADV7611 After you set up ADV7611 don t forget to set up EDID as well If you plan to use EDID RAM inside ADV7611 you would have to load relevant parameters More info on the internal EDID RAM can be referred to HDMIConfig I2C module B Audio Codec The audio format after being decrypted by HDMI RX 15 125 format default as shown in Figure 5 16 Audio Codec configuration setting can be divided to either pageO or pagel During the configuration process you would have to pay attention if the current setting is in pageO or pagel Paying attention to such details can help you set up Audio Codec more efficiently MAX 10 NEEK 64 www terasic com Tijasic August 3 2015 www terasic com 25134 125 Standard 16 bit per channel Figure 5 16 125 Standard Audio 16 bit per channel B Design Tools www terasic com Quartus II v15 0 64 bit Demonstration Source Code Project directory Dem
41. 0MHz clock source is expected to divide the MAC control register interface clock to produce the MDC clock output on the MDIO interface The MAC control register interface clock frequency is 100MHz and the desired MDC clock frequency is 2 5 so a host clock divisor of 40 should be used C E System maxll_qsys Fath Triple Speed Ethernet altera eth tse Example Design Core Configurations MAC Options FIFO Options Timestamp Options PCS Transceiver Options lt Ethernet MAC Options Enable MAC 10 100 half duplex support Enable local loopback on MII GMII RGMII Ensble supplemental MAC unicast addresses Include statistics counters Enable 64 bit statistics byte counters Include multicast hashtable Alien packet headers to 32 bit boundary Enable full duplex flow control Enable VLAN detection Enable magic packet detection Include MDIO module MDC MDIO Host clock divisor 40 Figure 6 20 MAC Options Configuration Once the Triple Speed Ethernet IP configuration has been set and necessary hardware connections have been made as shown in Figure 6 21 click on generate MAX 10 NEEK 85 WWW terasic com Tijasic August 3 2015 www terasic com E System sarl qeys Path nics gen Connections Dane Description Sext elk 50 Clock Source y Avalon ALTPLL ag mem if ddr3 emif DIRS SDRAM Contreller with Un cleck crossing bridge 0 alea Clock Crossing Bridge
42. 10 Interrupt Signal for Touch Screen 3 3V 3 4 13 2x10 ADC Header The board has a 2x10 ADC header with sixteen analog inputs connected to FPGA ADCI and ADC2 respectively The 1x3 header J12 1s used to select pin 18 of 2x10 header J7 or potentiometer input to be connected to the channel 8 of FPGA ADC2 Short pin and pin 2 of J12 to select potentiometer short pin 3 and pin 4 to select pin 18 of 2x10 header J7 The 1x3 header J13 is used to select pin 16 of 2x10 header J7 or on board microphone to be connected to the channel 7 of FPGA ADC2 Short pin and pin 2 of J13 to select on board microphone short pin 3 and pin 4 to select pin 16 of 2x10 header J7 Figure 3 26 shows the connection of 2x10 ADC header and MAX 10 FPGA MAX 10 NEEK 34 www terasic com 1 4 5 August 3 2015 www terasic com J7 ADCAIN 8 1 JNO YAN MAX 10 ADC2IN 6 1 J7 18 ADC2IN 8 TED P J7 16 11 Potentiometer U8 ADC2IN 7 OPA1612 Audio Operational J13 On board Amplofoer Microphone Figure 3 26 Connections between 2x10 ADC header potentiometer on board microphone and MAX 10 FPGA 3 4 14 Potentiometer Short pin 1 and 2 of J12 will select potentiometer for providing adjustable voltage to the channel 8 of FPGA ADC2 3 4 15 On board Microphone The board provides an on board microphone for audio applications Short pin 1 and pin 2 of J13 to select on board microphone to be connected to the cha
43. 15 0 e Nios II Eclipse 15 0 B Demonstration Source Code e Quartus project directory humidity temperature lcd e Nios II Eclipse project workspace humidity temperature lcd software B Demonstration File Locations MAX 10 NEEK 977 www terasic com asic August 3 2015 www terasic com JAN DTE RYA o Hardware project directory humidity temperature lcd Bitstream used humidity temperature lcd sof Software project directory humidity temperature lcd software Demo batch humidity temperature lcd demo_batch humidity temperature lcd bat B Demonstration Setup and Instructions Please follow the procedures below to set up the demonstration Make sure Quartus II and USB Blaster II driver are installed on your e Connect the USB cable to the USB Blaster II connector 78 on the 10 NEEK board and host PC e Power on the MAX 10 NEEK board Execute the demo batch file humidity temperature Icd bat under the batch file folder humidity temperature Nemo batch e NIOS terminal and LCD will display the humidity and temperature values Figure 6 35 shows the demonstration result 2 Figure 6 35 Humidity and Temperature Sensor Demo MAX 10 NEEK 98 www terasic com Tijasic August 3 2015 www terasic com ANU S8 RYA o 6 9 LCD CAMERA Demonstration This demonstration shows how to implement a camera demo on the Multi touch LCD module in Altera Qsys tool Altera VIP Video Image
44. 3V PS2 DAT2 PIN R3 PS 2 Data reserved for second PS 2 device 3 3V 3 4 17 Digital to Analog Converter DAC The board provides a Texas Instruments DAC8551 16 bit digital to analog converter DAC It is a small low power voltage output DAC The DAC8551 used a versatile 3 wire serial interface that operates at clock rates to 30M Hz and 16 compatible with standard SPI QSPI Microwire and DSP MAX 10 NEEK 36 WWW terasic com August 3 2015 www terasic com ANU S nA o interfaces The analog voltage output of DAC8551 is connected to a SMA connector Figure 3 27 shows the connection between DAC and MAX 10 FPGA The pin assignment associated to this DAC 15 shown in Table 3 15 DAC8551 DACSYNUn SYNC n J16 ND S RYAN DAC SCLK DAC E mL 0 apis DAC DATA SMA Figure 3 29 Connection between DAC and MAX 10 FPGA Table 3 15 Pin esa of DAC a D Standard PIN 2 7 Frame Sync Signal for Input Data 3 Serial Clock Input o Serial Data Input 3 4 18 UART to USB The board has UART interface connected for communication with the MAX 10 FPGA This interface doesn t support HW flow control signals The physical interface is implemented by UART USB onboard bridge from a FT232R chip to the host with an USB Mini B connector More information about the chip is available on the manufacturer s website or in the directory Datasheets UART TO
45. DR 4 PIN A4 LEDR 4 3 3V LEDR 5 PIN B4 LEDR 5 3 3V LEDR 6 PIN C4 LEDR 6 3 3V LEDR 7 PIN B5 LEDR 7 3 3V LEDR 8 PIN C5 LEDR 8 3 3V LEDR 9 PIN D5 LEDR 9 3 3V 3 4 2 7 segment Displays MAX 10 NEEK has two 7 segment displays These displays are paired to display numbers in various sizes Figure 3 15 shows the connection of seven segments common anode to pins on 10 FPGA The segment be turned on or off by applying a low logic level or high logic level from the FPGA respectively Each segment in a display is indexed from 0 to 6 with corresponding positions given in Figure 3 15 Table 3 4 shows the pin assignment of FPGA to the 7 segment displays HEXO 0 HEXO 1 HEXO 2 n w L MAX 10 HEXO 4 HEXO 5 a 6 Figure 3 15 Connections between the 7 segment display and the 10 FPGA Table 3 4 Pin Assignment of 7 segment Displays Signal Name FPGA Pin No Description Standard HEXO O0 PIN D6 Seven Segment Digit O 0 3 3V HEXO 1 PIN A5 Seven Segment Digit O 1 3 3V HEXO 2 PIN C5 Seven Segment Digit O 2 3 3V HEXO 3 PIN A6 Seven Segment Digit 0 3 3 3V HEXO 4 PIN F7 Seven Segment Digit O 4 3 3V HEXO 5 PIN D7 Seven Segment Digit 0 5 3 3V www terasic com MAX 10 NEEK 21 1 24 51 August 3 2015 www terasic com AU S RYA o HEXO 6 HEX1 0 HEX1 1 HEX1 2 HEX1 3 HEX1 4 HEX1 5 HEX1 6 PIN B7 PIN C7 PIN C8 PIN D8 PIN D10
46. EDs and MAX 10 FPGA Table 3 3 Figure 3 14 and Table 3 9 list the pin assignment of user push buttons switches and LEDs MAX 10 NEEK 19 www terasic com Tijasic August 3 2015 www terasic com Signal Name KEY 0 KEY 1 KEY 2 KEY 3 KEY 4 Signal Name SW 0 SW 1 SW 2 SW 3 SWI4 SW 5 SW 6 SW 7 SW 8 SW 9 Signal Name LEDR O LEDR 1 LEDR 2 RYA 10 LEDRO LEDR1 LEDR2 LEDR3 LEDR4 LEDR5 LEDR6 LEDR LEDR8 LEDR9 Figure 3 14 Connections between the LEDs and the MAX 10 FPGA Table 3 3 Pin Assignment of Push buttons FPGA Pin No PIN T22 PIN U22 PIN AA22 21 PIN R22 Description Push button 0 Push button 1 Push button 2 Push button 3 Push button 4 I O Standard 1 5V 1 5V 1 5V 1 5V 1 5V Table 3 4 Pin Assignment of Slide Switches FPGA Pin No PIN N22 PIN M22 PIN N21 PIN L22 PIN J22 PIN H22 PIN J21 PIN C21 PIN G19 PIN 21 Table 3 5 Pin Assignment of LEDs FPGA Pin No PIN C2 PIN B3 PIN A3 MAX 10 NEEK asic www terasic com Description Slide Switch 0 Slide Switch 1 Slide Switch 2 Slide Switch 3 Slide Switch 4 Slide Switch 5 Slide Switch 6 Slide Switch 7 Slide Switch 8 Slide Switch 9 Description LEDR 0 LEDR 1 LEDR 2 20 I O Standard 1 5V 1 5V 1 5V 1 5V 1 5V 1 5V 1 5V 1 5V 1 5V 1 5V I O Standard 3 3V 3 3V 3 3V www terasSic com August 3 2015 LEDR 3 PIN C3 LEDR 3 3 3V LE
47. EK combines a 5 point LCD touch panel and digital image module that provides developers an ideal platform for multimedia applications making the best use of the parallel nature of FPGAs 1 1 Package Contents Figure 1 1 shows a photograph of the MAX 10 NEEK package MAX 10 FPGA Kit Board MAX 10 FPGA Kit Quick Start Guide Type A to Mini B USB Cable 2 3 ge wie P iones 3 ns d cT o N gt Ww NFEK 10 r 4 cU 9 Ei TX us UA lt E Sort Type a uan cae or 0c Power Adapter sv 3a 4GB MicroSD Card Figure 1 1 The MAX 10 NEEK package contents MAX 10 NEEK 3 www terasic com August 3 2015 www terasic com S RYA o MAX 10 NEEK package includes The MAX 10 NEEK development board MAX 10 NEEK Quick Start Guide One USB cables Type A to Mini B for USB control and FPGA programming and control 5V DC power adapter Power Cable 1 2 MAX 10 NEEK System CD MAX 10 NEEK System CD contains all the documents and supporting materials associated with MAX 10 NEEK including the user manual system builder reference designs and device datasheets Users can download this system CD from the link http cd max 1 0 neek terasic com 1 3 Getting Help Here are the addresses where you can get help if you encoun
48. Ethernet transfer by an external Marvell 88E1111 PHY chip The 88 1111 chip with integrated 10 100 1000 Mbps Gigabit Ethernet transceiver support GMII MIU RGMII TBI MAC interfaces Figure 3 22 shows the connections between the MAX 10 FPGA Ethernet PHY and RJ 45 connector The pin assignment associated to Gigabit Ethernet MAX 10 NEEK 28 www terasic com 1 24 5 August 3 2015 www terasic com NOS n AN interface is listed Table 3 10 U32 J17 NET TX ER NET GTX CLK E TGTX CLK NET TX D 3 0 TXDI3 0 NET TX EN TX EN NET RST n NET TX CLK oie NET RX DI3 0 RXD a 0 MDI_P 3 0 MX 3 0 NET RX CLK RX CLK NET RX ER 2 RX DV Es py MAX 10 COL MDI N 3 0 MX 3 0 NET RX CRS ORE NET_MDC MDC NET_MDIO MDIO NET LINK100 LED LINK100 NET INT n mr NET CLK 25 XTAL1 88E1111 RJ45 Figure 3 22 Connections between the MAX 10 FPGA and Gigabit Ethernet Table 3 10 Pin Assignment of Ethernet PHY Signal Name FPGA Pin No Description Standard NET TX EN PIN C10 GMII and MII transmit enable 2 5V NET TX ER PIN C12 GMII and MII transmit error 2 5V NET TX CLK PIN E11 MII transmit clock 3 3V NET TX 0 0 PIN A12 MII transmit data 0 2 5V NET TX D 1 PIN B12 MII transmit data 1 2 5 NET TX 0 2 PIN A13 MII transmit data 2 2 5V NET TX D 3 PIN A14 MII transmit data 3 2 5 RX DV PIN A8 GMII and MII receive data valid 2 5V NET RX ER PIN B8 GMII and MII receive da
49. M HDMI_RX_DE e a HDMI_RX_HS l HDMI RX VS a RX_P 2 0 di 4 HDMI_RX_AP RX N 2 0 5 L 4 a ANU S RYA HDMI LRCK RX CLK P MAX 10 RX CLK N M s 4 HDMI SCLK e RESET n gt HDMI 12 SCL M e ee 12 SDA gt Figure 3 23 Connection between the MAX 10 FPGA and HDMI Receiver Table 3 11 Pin Assignment of HDMI RX Signal Name FPGA Pin No VO Standard HDMI_RX_DO PIN AA9 Video Pixel Output Port HDMI_RX_D1 PIN 9 Video Pixel Output Port HDMI_RX_D3 PIN_AA10 Video Pixel Output Port 3V Video Pixel Output Port MAX 10 NEEK 30 www terasic com Tijasic August 3 2015 www terasic com JA DTE RYA s HDMI_RX_D5 PIN_Y11 Video Pixel Output Port 3 3V HDMI_RX_D6 PIN AA11 Video Pixel Output Port 3 3V HDMI_RX_D7 PIN AB11 Video Pixel Output Port 3 3V HDMI RX D8 PIN Y14 Video Pixel Output Port 3 3V HDMI RX D9 PIN AB15 Video Pixel Output Port 3 3V HDMI_RX_D10 PIN AA15 Video Pixel Output Port 3 3V HDMI 011 PIN W14 Video Pixel Output Port 3 3V HDMI RX D12 PIN V14 Video Pixel Output Port 3 3V HDMI RX D13 PIN V15 Video Pixel Output Port 3 3V HDMI RX D14 PIN U15 Video Pixel Output Port 3 3V HDMI RX D15 PIN AB14 Video Pixel Output Port 3 3V HDMI_RX_D16 PIN AA14 Video Pixel Output Port 3 3V HDMI RX D17 PIN AB13 Video Pixel Output Port 3 3V HDMI RX D18 PIN Y13 Video Pi
50. NEEK 10 www terasic com Tijasic August 3 2015 www terasic com Mini USB Connector Figure 3 1 Path of the JTAG chain B Configure the FPGA in JTAG Mode The following shows how the FPGA is programmed JTAG mode step by step 1 Open the Quartus II programmer and click Auto Detect as circled in Figure 3 2 X Programmer Chaini cdf B File Edit Processing Tools Window 5 2 Hardware Setup NEEK10 USB 1 Enable real time ISP to allow background programming when available gt Start 00000000 glia Stop Delete 3 Add File Change File Save File Ti up Down Figure 3 2 Detect FPGA device in JTAG mode 2 Select detected device associated with the board as circled in Figure 3 3 MAX 10 NEEK 11 www terasic com Tijasic August 3 2015 www terasic com Found devices with shared JTAG ID for device 1 Please select your device 10M50DA 8 10M50DAES Figure 3 3 Select 10M50DAES device 3 FPGA is detected as shown in Figure 3 4 sip Programmer Chain2 cdf File Edit View Processing Tools Window 5 an mm Enable real time ISP to allow background programming when available Search altera com Verify Blank Examine Security Erase ISP Check Bit CLAMP 7 7 Start Stop Delete 3 Add File Change File zi Save File
51. Processing suite 16 used to display image on the LCD panel and a Nios II processor is used to configure the I2C devices There is a Camera IP from Terasic in Qsys which translates the Bayer pattern from camera to the RGB video steam format and feeds it to Altera VIP The other IP developed by Terasic for auto focus 1s used to find the optimized focus settings of user defined image area B System Block Diagram Figure 6 36 shows the system block diagram of camera demonstration on the LCD panel Camera mi MIPI CSI 2 to Module parallel Bridge FPGA QSYS _ me 50 MHz Terasic Camera IP Terasic AutoFocus Frame Buffer 800 x480 4 i ud pur Clocked Video bad MOutput 800x480 Multi Touch LCD ouqe uonoeuuooJ9ju DDR3 Figure 6 36 System block diagram of camera demonstration The camera module used includes an image sensor form OminiVision OV8865 and a VCM Voice Coil Motor driver IC VCM149C OV8865 is a low power high performance 8 megapixel image sensor The driver IC is used to control the focus of the camera The camera 15 configured to output a 4 lanes MIPI CSI 2 protocol in this demonstration MAX 10 NEEK 99 www terasic com Tijasic August 3 2015 www terasic com JA DTE n A The settings by default are Resolution 800x480 LCD resolution Frame Rate 60 fps Pixel Data RAWIO Bin Mode 1 2 4 a
52. RAS n DDR3 RESET n DDR3 WE n PIN U19 PIN V18 PIN E18 PIN D18 PIN W20 PIN J15 PIN N19 PIN J18 PIN H19 PIN K20 PIN H18 PIN K18 PIN H20 PIN K19 PIN J20 PIN L18 PIN M18 PIN M14 PIN N20 PIN L20 PIN M20 PIN M15 PIN L19 PIN T19 PIN R20 PIN R15 PIN P15 PIN P19 PIN P14 PIN R14 PIN P20 PIN K15 PIN L15 PIN K14 PIN L14 PIN V22 PIN N18 PIN B22 PIN W19 MAX 10 NEEK asic www terasic com DDR3 Column Address Strobe Clock Enable pin for DDR3 Clock n for DDR3 Clock p for DDR3 DDR3 Chip Select DDR3 Data Mask 0 DDR3 Data Mask 1 DDR3 Data 0 DDR3 Data 1 DDR3 Data 2 DDR3 Data 3 DDR3 Data 4 DDR3 Data 5 DDR3 Data 6 DDR3 Data 7 DDR3 Data 8 DDR3 Data 9 DDR3 Data 10 DDR3 Data 11 DDR3 Data 12 DDR3 Data 13 DDR3 Data 14 DDR3 Data 15 DDR3 Data 15 DDR3 Data 15 DDR3 Data 15 DDR3 Data 15 DDR3 Data 15 DDR3 Data 15 DDR3 Data 15 DDR3 Data 15 DDR3 Data Strobe n 0 DDR3 Data Strobe n 1 DDR3 Data Strobe p 0 DDR3 Data Strobe p 1 DDR3 On die Termination DDR3 Row Address Strobe DDR3 Reset DDR3 Write Enable 27 SSTL 15 Class SSTL 15 Class DIFFERENTIAL 1 5 V SSTL Class Differential 1 5 V SSTL Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class
53. U cdiff H HBH111U UCCSPS3_UCCIO 4 619420 8 664097 diff 4 8HH19U gt UCC2P5 CORE H H3i1H 7h H H7768U cdiff H HHBH31U UCC2P5 UCCIO H B8BH388R HB HBHO71U cdiff BH BHBBBAU UCCIPS5 UCCIO HB BBH777R HB H1165U Cdiff H HBHBHBS3U UCCIPZ UCC H 11869A 8 132835 cdiff H HH111U UCCSPS_UCCIO 4 619420 B 86409U diff 001905 Figure 6 6 Screenshot of power_monitor_nios demo ONES a www terasic com www terasic com August 3 2015 S n VAN 6 2 UART to USB control LED Many applications need communication with computer through common ports the traditional connector is RS232 which needs to connect to a RS232 cable However many personal computers nowadays don t have the RS232 connector which makes it very inconvenient to develop projects MAX 10 NEEK board is designed to support UART communication through USB cable The UART to USB circuit 1s responsible for converting the data format Developers can use a USB cable rather than RS232 cable to enable the communication between the FPGA and the host computer In this demonstration we will show you how to control the LEDRs by sending a command on the computer putty terminal The command is sent and received through a USB cable to the FPGA Note that in FPGA the information was received and sent through a UART IP Figure 6 7 shows the hardware block diagram of this demonstration The system requires a 50 MHz clock provided from the board The PLL ge
54. YS Last Song 2 Volume Up KE Y1 Volume Down Current Woluem 14 8 28 gt I2G core is enabledt Please insert SD card Find 5D card Husic Name MUSIC WAU Read OK Husic HMame music 4mhb vau Head OK HMusic Mame music longy wau Read Play Song MUSIC WAU sample rate 44160 Figure 6 15 Running SD Card Audio Demo 6 4 DDR3 SDRAM Test by Nios II Many applications use a high performance RAM such as a DDR3 SDRAM to provide temporary storage In this demonstration hardware and software designs are provided to illustrate how to perform DDR3 memory access in Qsys We describe how the Altera s DDR3 SDRAM Controller with UniPHY IP is used to access a DDR3 SDRAM and how the Nios II processor is used to read and write the SDRAM for hardware verification The DDR3 SDRAM controller handles the complex aspects of using DDR3 SDRAM by initializing the memory devices managing SDRAM banks and keeping the devices refreshed at appropriate intervals B System Block Diagram Figure 6 16 shows the system block diagram of this demonstration The system requires a 50 MHz clock provided from the board The DDR3 controller is configured as a 128 MB DDR3 300 controller The DDR3 IP generates one 300 MHz clock as SDRAM s data clock and one half rate system clock 150 MHz for those host controllers e g Nios II processor accessing the SDRAM In the Qsys Nios and the On Chip Memory are desig
55. ange on the data line in the next clock cycle If there s no change on the data line for one clock cycle the device will pull low the data line again as an acknowledgement which means that the data 1s correctly received After the power on cycle of the PS 2 mouse it enters into stream mode automatically and disable data transmit unless an enabling instruction is received Figure 5 1 shows the waveform while communication happening on two lines Sending command CLK Inhibit 15 2nd 10 11 CLK CLK CLK CLK CLK eooo DATA Mme gt Start bit BitO Bit7 Parity bit Stop Line bit control bit Receiving data CLK 15 2nd 10th 1 qth CLK CLK CLK CLK ee lI Start bit BitO Bit Parity bit Stop bit Figure 5 1 Waveform of Clock and Data Signals during Data Transmission MAX 10 NEEK 51 WWW terasic com August 3 2015 www terasic com ANU S nA e B Design Tools e Quartus II v15 0 64 bit B Demonstration Source Code e Project directory ps2 mouse e Bitstream used ps2 mouse sof B Demonstration Batch File Demo batch file folder Demonstrations ps2_mouse demo_batch Batch file ps2 mouse bat e FPGA configuration file ps2 mouse sof B Demonstration Setup e Please make sure Quartus II and USB Blaster II driver are installed on the host PC e Connect the USB cable from the USB Blaster II port 78 the NEEK board to the host PC and power on the NEEK board e Execute
56. apter 5 RTL Example Codes This chapter provides examples of advanced designs implemented by RTL on the DECA board These reference designs cover the features of peripherals connected to the FPGA such as PS 2 mouse Power monitor ADC DAC application HDMI input and display the associated files can be found in the directory Demonstrations of System CD Note The output files generated after compilation in Quartus II e g sof and pof files are saved in the folder output files under the directory of demo project 5 1 PS 2 Mouse Demonstration We offer this simple PS 2 controller coded in Verilog HDL to demonstrate bidirectional communication between PS 2 controller and the device the PS 2 mouse You can treat it as a how to basis and develop your own controller that could accomplish more sophisticated instructions like setting the sampling rate or resolution which need to transfer two data bytes More information about the PS 2 protocol can be found on various websites B Introduction PS 2 protocol uses two wires for bi directional communication One 15 the clock line and the other one is the data line The PS 2 controller always has total control over the transmission line but it 1s the PS 2 device which generates the clock signal during data transmission B Data Transmission from Device to the Controller After the PS 2 mouse receives an enabling signal at stream mode it will start sending out displacement data which cons
57. ave Conversion Setup Output programming file Programming file type Programmer Object File pof Options Boot info Configuration device EPCE16 Mode Internal Configuration File name my first niosII pof Advanced Remote Local update difference file NONE Create Memory Map File Generate my first niosIL map Create CvP files Generate my first niosII periph pof and my first niosII core rbf Create config data RPD Generate my first niosII auto rpd Input files to convert File Data area Properties Start Address Add Hex Data SOF Data Page 0 auto Figure 8 12 Convert File Window Setting e Click the Options Boot info button Choose the UFM source as the load memory file and click browse button to open the onchip flash hex file as shown in Figure 8 13 Press OK button asic MAX 10 NEEK 118 www terasic com Mgjas e August 3 2015 ANU S n A s to close the window Hr 10 Device Options Power On Reset scheme Set to weak pull up prior usermode Auto reconfiqure from secondary image when initial image fails 7 Use secondary image ISP data as default setting when available Security 7 verify protect E Allow encrypted POF only Dual Config Enable watchdog Watch walue User Flash Memory source Load memory file File path veorld O mem init onchip flash hex Description New memory file path used as UFM data
58. c August 3 2015 www terasic com JA DTE RYA Figure 6 14 Software Stack Of SD Card Audio Demo The audio chip should be configured before sending audio signal to the audio chip The main program uses I2C protocol to configure the audio chip working in master mode the audio output interface working 125 16 bits per channel and with sampling rate according to the wave file contents In audio playing loop the main program reads 512 byte audio data from the SD Card and then writes the data to DAC FIFO 1n the Audio Controller Before writing the data to the FIFO the program will verify 1f the FIFO is full While the demonstration is running users get the status information through Nios II terminal You can adjust the volume by pressing keyl or key2 And also you can choice the song by pressing keyO or key3 B Design Tools e Quartus II 15 0 e Nios II Eclipse 15 0 B Demonstration Source Code e Quartus Project directory audio e Nios II Eclipse project workspace sdcard audio Noftware B Nios II Project Compilation MAX 10 NEEK 78 www terasic com Tijasic August 3 2015 www terasic com AN S n A s Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse B Demonstration Batch File Demo Batch File Folder sdcard_audio demo_ batch The demo batch file includes followin
59. ch players may also include high quality DAC devices such that good audio quality can be produced The MAX 10 NEEK board provides the hardware and software needed for Micro SD Card access and professional audio performance so that it 1s possible to design advanced multimedia products using the MAX 10 NEEK board Figure 6 12 shows the diagram of this demonstration In this demonstration we show how to implement an SD Card Music Player on the 10 NEEK board in which the music files are stored in an SD Card and the board can play the music files via its high quality and low power audio DAC circuits We use the Nios II processor to read the music data stored in the SD Card and use the TLV320AIC3254 audio CODEC to play the music 8 1 pU Panasonic Figure 6 12 System of SD Card Audio Demo Figure 6 13 shows the hardware block diagram of this demonstration The system requires a 50 MHz clock provided from the board The PLL generates a 100MHz clock for Nios II processor and the other controllers The audio chip is controlled by the Audio Controller which is a user defined SOPC component The internal PLL in the CODEC chip can generate the clock rate according to the sample rate of the music A mater clock should be supplied for the CODEC The mater clock rate in this demonstration 15 19 2M provided by PLL block in FPGA The audio controller requires the audio chip working in master mode so the serial bit BCLK and the
60. chieved ZOOM IN ZOOM OUT function Users can change the settings base on their requirements A MIPI CSI 2 bridge chip TC358748XBG is used to decode the video data via MIPI interface from the camera module to the FPGA in parallel The camera module is configured as RAWIO in this demonstration so the data width of 24 bit parallel bus between CSI 2 bridge and FPGA 15 only 10 bit used For image process in FPGA the reference design is developed based on Altera s Video and Image Processing VIP suite The Terasic Camera IP translates the parallel Bayer pattern data into RGB data to meet the specification of Altera VIP video streaming The Frame Buffer from VIP is used for buffering image data in DDR3 and matching the frame rate from Terasic camera IP to the Clock Video Output of VIP It displays the final 800x480 RGB frame image on the LCD panel The auto focus IP by Terasic can be used to get a better image quality by finding the optimized focus setting The Nios II program running on on chip memory controls three I2C controllers to configure the image sensor motor driver MIPI CSI 2 Bridge IC and touch device First I2C controller is used to configure the camera module including OV8865 image sensor and 149 The second I2C controller is used to configure the Bridge IC TC358748XBG The third controller is used to retrieve the touch information from the touch device For better image quality with user defined area
61. d Power on the board if you find an unrecognized USB Serial Port in Device Manager as shown in Figure 6 8 you should install the UART to USB driver before you run the demonstration MAX 10 NEEK 73 www terasic com Tijasic August 3 2015 www terasic com niubility PC gt 4M Computer gt c Disk drives b Display adapters gt 4 2 DVD CD ROM drives Human Interface Devices xg IDE ATA ATAPI controllers X Keyboards JA Mice and other pointing devices Monitors Network adapters Other devices fg USB Serial Port 22 Ports COM amp LPT k y yo yoy ME Im Processors b Sound video and game controllers gt System devices b Universal Serial Bus controllers Figure 6 8 Unrecognized USB Serial Port on PC To install UART TO USB driver on your computer please select the USB Serial Port to update the driver software The driver file be downloaded from the following website http www ftdichip com Drivers V CP htm Open the Device Manager to ensure which common port is assigned to the UART to USB port as shown in Figure 6 9 The common number 9 COMO is assigned on this computer File View Help e g3 E Id amp 8 18 ees gt JE Computer gt sq Disk drives Jic Display adapters 5 DVD CD ROM drives xg IDE controllers gt JA Mice and other pointing devices gt Monitors gt Metwork adapters 4
62. de Description O 0 jnternal Temperature Only Defauit 0 1 Vi or V4 V2 Only per Mode 2 0 1 0 Tg V4 Only per Mode 2 0 1 1 2D AI Measurements per Mode 2 0 b 2 0 Mode 2 0 Mode Description V1 V2 Tre Default V1 V2 Tre V1 V2 V3 V4 V3 V4 Try V o 03 0 1 Tri ee Env Figure 6 4 Control register of LTC2990 Figure 6 5 shows the status register of LTC2990 Bit b2 should be checked before reading the voltage difference registers to make sure the measurement is finished and register values is the latest for reading b6 1 Vec Register Contains New Data 0 Vcc Register Read b5 1 V4 Register Contains New Data 0 V4 Register Read b4 V3 Taz V3 V4 Ready 1 V3 Register Contains New Data 0 V3 Register Data Old b3 V2 Ready 1 V2 Register Contains New Data 0 V2 Register Data Old b2 Vi Ta Vi V2Realy J t V1 Register Contains New Data 0 V1 Register Data Old 1 1 Tyr Register Contains New Data 0 Register Data Old 00 1 Conversion Process 0 Acquisition Cycle Complete Figure 6 5 tatus register of LTC2990 B Design Tools e Quartus II v15 0 64 bit e Nios II Eclipse 15 0 B Demonstration Source Code e Quartus project directory Demonstrationsvpower monitor nios e Nios II Eclipse project workspace Demonstrations power_monitor_nios software MAX 10 NEEK 70 WWW terasic com August 3 2015 www t
63. des a potentiometer demonstration using the ADC in MAX10 This ADC solution consists of hard IP blocks in MAX 10 device and soft logic through Altera Modular ADC IP core Figure 5 4 shows the block diagram of ADC hard IP block in MAX10 device PLL Clock In Dedicated ADC Hard IP Block Analog Input Sequencer 4 0 DOUT 11 0 ADC Analog Input Dual Function 16 1 Control Status Temperature Sensor Altera Modular ADC IP Core ADC Veer Internal Figure 5 4 Block diagram of ADC hard IP block This demo uses 2nd ADC of MAX10 on channel 8 The ADC settings are shown in Figure 5 5 MAX 10 NEEK 23 WWW terasic com August 3 2015 www terasic com ANU S8 p ANS Altera Modular ADC core k ma altera modular adc General Core Confi tion Core Variant ADC control core only gt Debug Path Enabled IP Generation Generate IP for which ADCs of this device 954 ADC w Clocks Input Clock 10 Mhz Reference Voltege Reference Voltage Source Intemal w Internal Reference Voltage 7 Channels CHO CH2 cus CH8 No TSD Channel 8 Use Channel 8 Channel 8 Prescaler Enable Prescaler for Channel 8 Figure 5 5 Settings of ADC hard IP 10 NEEK has a Variable Resistor VR onboard which acts as a potentiometer in this demonstration Figure 5 6 shows
64. digital GPIO user pins connected to the MAX 10 FPGA two 3 3V power pins and two ground pins There are two Transient Voltage Suppressor diode arrays used to implement ESD protection for 8 GPIO user pins Figure 3 17 shows the connection between the TMD header and 10 FPGA Table 3 9 shows the pin assignment of 2x6 TMD header VCC3P3 GPIO 7 0 Figure 3 17 Connections between the 2x6 TMD header and MAX 10 FPGA Table 3 6 Pin Assignment of 2x6 TMD Header Signal Name FPGA Pin No Description Standard GPIO 0 PIN Y17 GPIO Connection 0 3 3V GPIO 1 PIN AA17 GPIO Connection 1 3 3V GPIO 2 PIN V16 GPIO Connection 2 3 3V GPIO 3 PIN W15 GPIO Connection 3 3 3V GPIO 4 PIN AB16 GPIO Connection 4 3 3V GPIO 5 PIN AA16 GPIO Connection 5 3 3V GPIO 6 PIN Y16 GPIO Connection 6 3 3V GPIO 7 W16 GPIO Connection 7 3 3V 3 4 5 24 bit Audio CODEC The MAX 10 NEEK offers high quality 24 bit audio via the Texas Instruments TLV320AIC3254 audio CODEC Encoder Decoder This chip on MAX 10 NEEK supports line in line out and microphone in ports with adjustable sample rate from 8kHz to 192kHz The connection of the audio MAX 10 NEEK 23 www terasic com ijasic August 3 2015 www terasic com JA DTE n AN circuitry to the FPGA 15 shown in Figure 3 18 and the associated pin assignment to the FPGA 15 listed in Table 3 7 More information about the TLV320AIC3254 CODEC is available in its datasheet which can be fo
65. dr3_nios software MAX 10 NEEK 81 www terasic com Tijasic August 3 2015 www terasic com S n As B Nios II Project Compilation e Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse B Demonstration Batch File e Demo Batch File Folder ddr3 batch The demo batch folder includes following files e Batch Files ddr3 nios bat ddr3 nios sh e FPGA Configure File ddr3_nios sof e Nios II Program ddr3_nios elf B Demonstration Setup Please follow the procedures below to set up the demonstration Make sure Quartus II and Nios II are installed on your PC e Power on the MAX 10 NEEK board e Use an USB cable to connect PC and the MAX 10 NEEK board J8 and install USB Blaster driver if necessary e Execute the demo batch file ddr3 nios bat for USB Blaster II under the batch file folder ddr3_nios demo_ batch e After Nios II program is downloaded and executed successfully a prompt message will be displayed in Nios2 terminal e Press KEYA KEYO of the MAX 10 NEEK board to start SDRAM verify process Press KEYO for continued test e The program will display progress and result information as shown in Figure 6 17 MAX 10 NEEK 82 www terasic com Tijasic August 3 2015 www terasic com ANU RA o Altera Nios EDS 15 0 gcc4 Downloaded 1 in 0 15 Verifi
66. e Frame Reader VIP is used for reading data to be displayed from the associated video memory and the VIP Video Out is used to display the video data The data 1s drawn by the Nios II processor according to user input For multi touch processing whenever there is any touch activity occurring a I2C Controller IP is used to retrieve serial data from the I2C interface the associated touch information including multi touch gestures and 5 point touch coordinates can be calculated through the data in NIOS II Figure 6 31 shows the system generic block diagram of painter demonstration FPGA SOPC Touch PLL NIOS 1 4 Screen lt Avalon Interconnect Fabric LCD 800x480 Avalon Memory Mapped Bus Avalon Streaming Bus wm Figure 6 31 System Block Diagram of the Painter Demonstration B Design Tools e Quartus II v15 0 e Nios II Eclipse 15 0 B Demonstration Source Code MAX 10 NEEK 93 www terasic com Tijasic August 3 2015 www terasic com JA DTE p AN e Project directory lcd painter e Nios II Eclipse Project workspace painter software B Demonstration Batch File e Demo Batch File Folder Mcd painterdemo batch B Demonstration Setup Please follow the procedures below to set up the demonstration e Connect a USB cable between your computer and the USB connector J8 on MAX 10 NEEK board Power on the MAX 10 NEEK Board Please make sure Quartus II has been installed on the host PC
67. e details about the operation of restoring the Application Selector factory image B Combining factory recovery binary files In the factory settings you need to program Application Selector software code to the QSPI flash and the hardware binary to the onchip flash You should covert the hardware and software into separated pof for programming onchip Flash and the QSPI flash e Copy the elf and the boot loader cfi srec file into a common directory relying on your choice This directory is where you will convert the elf into a hex file e On your host PC launch a Nios H Command Shell from Start gt Programs gt Altera gt Nios II version gt EDS gt Nios II Command Shell e From the command shell navigate to where your elf file is located and create a flash file using the following commands listed below e elf2flash base20x07c00000 0 08000000 07 00000 input application seletcor elf output application selector flash boot boot loader cfi srec e Convert the flash into the hex file nios2 elf objcopy O ihex application selector flash application selector hex In Quartus convert programming file tool window set the options as Figure 7 7 Open Conversion Setup Data Save Conversion Setup Programming file type Programmer Object File pof Options Boot info Configuration device CFI 512Mb Mode File final fiash pof Advanced Remote Local update dif
68. ected to an external speaker The data will also be processed based on the volume to be displayed on the 10 LEDs onboard VCC5 C12 gt ADC VREF 10V Figure 5 10 Onboard microphone amplifier with Gain R24 R25 392 B Function Block Diagram Figure 5 11 is the function block diagram of this demonstration The built in MIC is amplified approximately 392 times via two operational amplifiers The signal 1s then feed into the ADC of MAX 10 device for conversion This demonstration uses the timing from the audio codec TLV320AIC3254 via 125 protocol to sync the entire system The module SPI sets the registers for the audio codec The module SOUND SUM syncs the digitized signal coming out of the ADC of the MAX 10 device with the system and converts the data format 1 e adjust unsign 12 bit to sign 16 bit etc The module SOUND2LCD converts the digitized sound signal into the format of LCD timing to the LCD panel to be displayed in graphical sound wave The module DACIO converts the digitized signal in parallel to 16 bit serial format for the DAC chip DAC8551 to the Line out via audio codec TLV320AIC3254 The module LED METER displays the volume of the sound on the 10 LEDs onboard MAX 10 NEEK 60 www terasic com Tijasic August 3 2015 www terasic com MAX 10 SPICIL iad TLV320A1C 3254 SOUND2LCD EU DACSMAOUT DAC8551 LED METER Speaker
69. ed OK Starting processor at address 0x00000250 nios2 terminal connected to hardware target using JTAG UART on cable nios2 terminal NEEK18 USB 1 device 1 instance nios2 terminal Use the IDE stop button or Ctrl C to terminate DDR3 Test Size 128MB CPU Clock 100000000 Press any KEV to start test KEVO for continued test DDR3 Testing Iteration 1 write 104 202 304 404 504 604 TOA 80 902 1004 read verify 104 204 304 404 504 60 TOA 80 90 1004 DDR3 test Pass 21 seconds Press any KEY to start test KEVO for continued test gt DDR3 Testing Iteration 1 Write 104 20 304 40 504 60 TOA 80 904 100 read verify 104 20 304 Figure 6 17 Display Progress and Result Information for the DDR3 Demo 6 5 Ethernet Socket server This design example demonstrates a socket server using the sockets interface of the NicheStack TCP IP Stack Nios II Edition with MicroC OS II to serve socket connection to the MAX 10 NEEK board The server can continuously listen for commands on a TCP IP port and operate the MAX 10 NEEK LEDs according to the commands from the telnet client As Part of the Nios II EDS NicheStack TCP IP Network Stack is a complete networking software suite designed to provide an optimal solution for network related applications accompanying Nios II Also to understand how this demo works we assume that you already have a basic knowledge of TCP IP protocols As indicated in the bl
70. en Device windows Click the Device and Pin Options and choose Dual Compressed Images in configuration table as shown in Figure 8 5 Then compile the project to generate the sof file 7 Device and Pin Options Icd_ General Configura tion Programming Files Specify the device configuration scheme and the configuration device Unused Pins Dual Purpose Pins Configuration scheme Capacitive Loading Board Trace Model Configuration mode Timing Configuration device Voltage Pin Placement Error Detection CRC Use configuration device CvP Settings Device Options Partial Reconfiguration Configuration device 1 0 voltage Force VCCIO to be compatible with configuration I O voltage Generate compressed bitstreams Active serial cock source Enable input tri state on active configuration pins in user mode The method used to load a design into the device Only one configuration scheme is available Internal Configuration use internal flash Figure 8 5 Set Dual Configuration Modes These procedures should be implemented both projects for dual boot e The next step is to convert the two sof files into a pof file for programming the 10 FPGA Open the convert programming Files tool in Quartus and set as Figure 8 6 asic MAX 10 NEEK 115 www terasic com August 3 2015 JA DTE RYA o Output programming file Programming file type Programmer Object File pof M
71. erasic com ANU S RYA o B Nios II Project Compilation Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse Demonstration Batch File Demo batch file folder Demonstrationspower monitor niosxdemo batch Batch file test bat FPGA configuration file power monitor nios sof Nios batch file test sh NIOS program nios app elf B Demonstration Setup Please follow the procedures below to set up the demonstration Please make sure Quartus II and USB Blaster II driver are installed on the host PC Connect the USB cable from the USB Blaster II port J8 on the NEEK board to the host PC Power on the NEEK board Execute the demo batch file test bat under the folder Demonstrations power monitor niosMemo batch Nios II terminal will display the measured power consumption measured as shown in Figure 6 6 ales demo batch B O E UCCZP5 CORE H H2913R8 H H7282U amp diff H HHH29U UCC2P5_UCCIO 194 B HBd85U cdiff H HBHBHBH2U UCCIP5 UCCIO H HB583BR 4 80874 Cdiff H HBHBHBGU UCCIP2 UCC H 11264hn H 13516U cdiff H HH113U UCC3P3 UCCIO H HB1748R BH BH5768U cdiff BH BHBBB1 7U UCCZP5 CORE H H2719n 0 667774 Cdiff H HBHBH27U UCCZPS UCCIO H BHBH388R HB HBHO71U cdiff H BHBBHBBAU UCCIP5 UCCIO B BB777h 8 81165 cdiff BH BHBBHBHBHSU UCC1P2 UCC H 11B8690n H 13283
72. f onboard MIC MAX 10 NEEK Tijasic 62 www terasic com www terasSic com August 3 2015 ANU S p AN 5 6 HDMI RX Demonstration We now provide more details on the HDMI Receiver ADV7611 on the MAX 10 NEEK We will show you how to use MAX 10 NEEK as a HDMI Display in this demo When the HDMI Receiver receives and decrypts the data the data can be divided into both audio and video parts where the audio part 1s played after being encrypted by Audio Codec TLV320AIC3254 0 and the video will be displayed on the multi touch LCD panel B Function Block Diagram Figure 5 14 shows the system block diagram of this reference design where 7 LCD refers to Terasic multi touch panel HDMI RX ADV7611 is a chip to decrypt HDMI video and audio data Before decrypting HDMI data a proper setting is necessary where HDMIConfig I2C module is used to configure the ADV7611 chip This demo uses the Video and Image Processing VIP IP provided by Altera which requires specific video data format Avalon ST Video image data format Video In module in the above block diagram is to convert the received video data to Avalon ST Video format Because MAX 10 NEEK Display has a resolution of 800x480 therefore no matter what the input video resolution 15 the output has to be 800x480 The Scalar module is to convert resolution of any kind to 800x480 10 Config DDR3 PLL 12C Controller HDMI_RX Frame Be Video E UD EJ ES E HDMI
73. ference file Create Memory Map File Generate final_flash map Figure 7 7 Generate The Final_flash Pof e Click the Add hex Data button and choose the application_selector hex file generated above then press generate button to generate the object file final_flash pof e To convert the sof file into pof just follow the steps for dual boot programming and make sure the sof for application selector is added to sof Page_O data Assuming the name of the pof is app_sel pof MAX 10 NEEK 110 www terasic com Tijasic August 3 2015 www terasic com ATERA Q 1 The original command for convert the elf into flash is e elf2flash input elf filename output flash file name basezflash base address flash end address resetzflash base address boot SOPC_KIT_NIOS2 components altera nios2 boot loader cfi srec 2 You can also convert the elf file into the hex data by executing test bat in the software batch directory in the project directory B Restoring the original binary file e To restore the original contents of the Application Selector perform the following steps e Copy Selector project into a local directory of your choice The Selector project is placed in DemonstrationsVapplication selector e Power on the MAX 10 NEEK board with the USB cable connected to the UBII JS port Download the max10 qpfl sof to the board Press Auto Detect button and a QSPI flash will be detected as shown in Figure 7 8
74. focused a simple auto focus algorithm is used and implemented as a Qsys IP The range of motor position which controls the focus is defined as 0 1023 The algorithm searches for the best focus position in two stages It takes images when the focus position is set to 0 6 12 etc in the first stage and calculates the contrast of these images to narrow down the search by finding the most clear image of all at focus position X It then starts to take images again when the focus position is set to X 3 X 2 X 1 X X 1 X 2 and X 3 in the second stage to come up with the best focus position after two iterations The Nios II processor is used to configure and trigger the IP Users can develop and implement a more efficient algorithm based on the auto focus IP provided in this demonstration Note The focus driver IC 149 in the camera module is configured by the Terasic auto focus IP through its own I2C master controller The image sensor in the camera module is also configured through the same I2C bus by its own I2C master controller The arbitration is implemented in the Nios II program to prevent the I2C bus occupied by the two I2C master controllers simultaneously Users must make sure there is only one I2C master used at the same one MAX 10 NEEK 100 www terasic com ijasic August 3 2015 www terasic com AN S n A e For ZOOM function the ZOOM IN and ZOOM OUT functions are implemented by configuring the bin mode of the image sen
75. g files Batch Files test bat test sh FPGA Configure File sdcard_audio sof Nios II Program sdcard audio elf B Demonstration Setup Please follow the procedures below to set up the demonstration www terasic com Format your Micro SD Card into FAT16 FAT32 format Place the wave files to the root directory of the Micro SD Card The provided wave files must have a sample rate of the following options 96K 48K 44 1K or 8K In addition the wave files must be stereo and 16 bits per channel Connect a headset or speaker to the MAX 10 NEEK board so you can hear the music played from the micro SD Card in later Insert the micro SD card into the micro SD socket on MAX 10 NEEK board Make sure Quartus II and Nios II are installed on your PC Power on the MAX 10 NEEK board Connect an USB cable to the MAX 10 NEEK board and install USB Blaster driver if necessary Execute the demo batch test bat under the batch file folder sdcard_audio Memo batch Press KEY3 on the MAXIO NEEK board to play the last music file stored in the micro SD Card and press KEYO to play the next song Press KEY2 and KEY to increase and decrease the output music volume respectively as shown in Figure 6 15 MAX 10 NEEK 79 www terasic com Tijasic August 3 2015 Played Wave Files Wave files on root directory Supported Media File Uncompressed WAU File Sample Rate tereo 16 hits Sample KEYH Next Song KE
76. h e Rotate the VR resistor with a screwdriver HEXO will display the voltage value 5 4 DAC Demonstration This demonstration uses the 16 bit Digital to analog converter DAC built in the MAX 10 device to generate square wave in 8 difference frequencies The signal coming out of the SMA connector on 10 board 15 transmitted to the oscilloscope The oscilloscope will display the square wave in different frequencies by switching SW 2 0 on the 10 board B Function Block Diagram Figure 5 7 15 the function block diagram of this demonstration The source data in parallel 15 converted to serial data by the DAC16 module The DAC chip DAC8551 then converts the serial data from digital to analog The analog signal coming out of the DAC SMA connector is connected to the oscilloscope and shown in square wave Users can switch SWO 2 to change the frequency MAX 10 NEEK 57 WWW terasic com 1 24 5 August 3 2015 www terasic com JA DERYA of the square wave FPGA NOTERA o MAX 10 DACIC DAC 7 551 50MHz SW2 SW1 SWO Figure 5 7 Block diagram of the DAC demo B Design Tools e Quartus II v15 0 64 bit B Demonstration Source Code e Project directory Demonstrations dac sma e Bitstream used sma sof B Demonstration Batch File e Demo batch file folder Demonstrations dac smaMemo batch Batch file test bat FPGA configuration fi
77. heStack TCP IP Stack software block provides networking services to the application block where it contains the tasks for Socket Server and also LED management Figure 6 23 Nios Il Software Routine Architecture Finally the detailed descriptions for Software flow chart of the Socket Server program are listed below Firstly the Socket Server program initiates the and net device then calls the get addr function to set the MAC addresses for the PHY Secondly it initiates the auto negotiation process to check the link between the PHY and gateway device If the link exists the PHY and gateway devices will broadcast their transmission parameters speed and duplex mode After the auto negotiation process has been finished the link will be established Next the Socket Server program will prepare the transmitting and receiving path for the link If the path is created successfully it will call the get addr function to set up the IP address for the network interface After the IP address is successfully distributed the NicheStackTM TCP IP Stack will start to run for Socket Server application MAX 10 NEEK 87 www terasic com Tijasic August 3 2015 www terasic com ANU S n A s Q your gateway should support DHCP because it uses DHCP protocol to request a valid IP from the Gateway or else you would need to reconfigure the system library to use static IP assignment Design Tools Quartus II v15 0 Nios II Ecli
78. ists of 33 bits The frame data is cut into three sections and each of them contains a start bit always zero eight data bits with LSB first one parity check bit odd check and one stop bit always one The PS 2 controller samples the data line at the falling edge of the PS 2 clock signal This is implemented by a shift register which consists of 33 bits but be cautious with the clock domain crossing problem MAX 10 NEEK 50 www terasic com ijasic August 3 2015 www terasic com ANU 8 p ANS B Data Transmission from the Controller to Device When the PS 2 controller wants to transmit data to device it first pulls the clock line low for more than one clock cycle to inhibit the current transmission process or to indicate the start of a new transmission process which is usually called as inhibit state It then pulls low the data line before releasing the clock line This 1s called the request state The rising edge on the clock line formed by the release action can also be used to indicate the sample time point as for a start bit The device will detect this succession and generates a clock sequence in less than 10ms time The transmit data consists of 12bits one start bit as explained before eight data bits one parity check bit odd check one stop bit always one and one acknowledge bit always zero After sending out the parity check bit the controller should release the data line and the device will detect any state ch
79. ject name entered in the circled area as shown in Figure 4 3 will be assigned automatically as the name of the top level design entity MAX 10 NEEK 45 WWW terasic com Tijasic August 3 2015 www terasic com IAN DERYA o r MAX 10 NEEK V1 0 0 System Configuration ATERA www terasic com Project Name MAX 10 NEEK FPGA Board MAX10 iv CLOCK iv Button x5 iv LEDx10 Switch x 10 iv i Segment x2 iv Power Monitor iv G sensor iv Humidity Sensor iv Light Sensor iv Audio Codec iv HDMI RX iv microSD Card PS2 DAC QSPI Flash UART to USB DDR3 SDRAM Ethernet CS2 Camera LCD Touch Panel Default Setting TMD 2x6 GPIO Header Save Setting Generate None Prefix Name Load Setting Exit Figure 4 3 Enter the project name B System Configuration Users are given the flexibility the System Configuration to include one or more onboard peripherals in the project as shown in Figure 4 4 If a component is enabled the NEEK10 System Builder will automatically generate its associated pin assignment including the pin name pin location pin direction and I O standard MAX 10 NEEK 46 WWW terasic com Tijasic August 3 2015 www terasic com AN S a MAX 10 NEEK V1 0 0 5 RYAN System Configuration www terasic com Project MAX 10 NEEK FPGA Board lt CLOCK Bu
80. ld be checked as shown in Figure 8 10 z Main Software Packages Drivers Linker Script Enable File Generation Target BSP Directory SOPC Information file 10 neek sopcinfo CPU name nios2 gen2 Operating system Altera HAL Version default BSP target directory F neek 10 dev_matthew camera software Camera_Test_bsp Settings custom newlib flags Common hal linker 4 allow code at reset V enable alt load V enable alt load copy rodata 7 enable alt load copy rwdata 7 enable alt load copy exceptions hal make Figure 8 10 BSP Advance Setting MAX 10 NEEK 117 WWW terasic com August 3 2015 www terasic com AN S RYA o e Make sure you have set your software s program memory text section in onchip Flash memory through BSP Editor Nios II SBT for Eclipse utility e Compile the target into initial flash format by choosing the mem init generate option in the Make Target window in Eclipse as shown in Figure 11 Make Targets a Make Targets for Camera_Test Target Location mem init install mem init generate help Figure 8 11 Make Target Setting e After clicking build button a onchip flash hex will be generated in the path software software_project mem_init e Open the convert programming file window in Quartus and set the window as shown in Figure 8 12 Conversion setup files Open Conversion Setup Data S
81. le dac sma sof B Demonstration Setup e Please make sure Quartus II 16 installed on the host e Connect the NEEK10 board 78 to the host PC with USB cable and install the USB Blaster driver e Plugin the 5V adapter to the NEEKIO Board and power it up Execute the demo batch file test bat from the directory dac smaMemo batch Connect the probe of the oscilliscope to the DAC SMA OUT of the NEEK 10 board and adjust MAX 10 NEEK 58 WWW terasic com 1 4 5 August 3 2015 www terasic com JA DTE RYA o the display until the square wave is visible as Figure 5 8 and Figure 5 9 Switch SW 2 0 from 000 to 111 and the frequency of the square will be changing The square wave frequency is twice higher When SWI2 0 2000 the square wave frequency is at about 2 6KHz When SW 2 0 111 the frequency is about 112KHz Figure 5 8 Use the oscilloscope to observe the square wave Figure 5 9 Probe DAC SMA OUT from the oscilloscope asic MAX 10 NEEK 59 www terasic com August 3 2015 ANU 8 S AN 5 5 ADC MIC LCD Demonstration There is a high sensitive microphone on the NEEK 10 board to receive the surrounding sound After the sound is collected and amplified approximately 392 times as shown in Figure 5 10 It is feed into the ADC of MAX 10 device The digitized waveform will be displayed on the LCD Meanwhile the signal will be sent to the Line out via audio codec and DAC SMA OUT connector Both of which can be conn
82. m stability Humidity and temperature results can be read out through the I2C compatible interface The LCD displays the interface of our game In our Nios II software we show temperature and humidity data on the LCD display The value of the sensor will change as the environment changes Figure 6 34 shows the block diagram of this demonstration In this demonstration a Nios II MAX 10 NEEK 96 www terasic com Tijasic August 3 2015 www terasic com AN S n A e processor is used to achieve 12c operation and display results on the Nios II console and LCD FPGA 50 MHz to p t eiae E lt joeuuooJeju HDC 1000 T Figure 6 34 Block diagram of Humidity and Temperature Sensor This demonstration shows basic function of HDC1000 and temperature and humidity reading in different acquisition modes HDC1000 can perform measurements of both humidity and temperature or either humidity only or temperature only The measurement resolution can be set to 8 11 or 14 bits for humidity 11 or 14 bits for temperature Different resolution setting results in a different conversion time When triggering the measurements operation should wait for the measurements to complete based on the conversion time Alternatively wait for the assertion of DRDYn In this demonstration a delay I2C function is adopted to simplify the process B Design Tools e Quartus II v
83. m the CFM Both of the application configuration images image 0 and image 1 are stored the CFM The MAX 10 device loads either one of the application configuration image from the CFM If an error occurs the device will automatically load the other application configuration image Remote System Upgrade Flow for MAX 10 Devices is shown in Figure 8 Reconfiguration Sample Reconfiguration BOOT Pin Boot_SEL 0 Boot_SEL 1 First Error Occurs e Second Error Occurs Reconfiguration Figure 8 2 Remote System Upgrade Flow for MAX 10 Devices The operation of the remote system upgrade feature detecting errors is as follows 1 After powering up the device samples the BOOT_SEL pin to determine which application configuration image to boot The BOOT_SEL pin setting can be overwritten by the input register of the remote system upgrade circuitry for the subsequent reconfiguration 2 If an error occurs the remote system upgrade feature reverts by loading the other application configuration image The following lists the errors that will cause the remote system upgrade feature to load another application configuration image e Internal CRC error e User watchdog timer time out 3 Once the revert configuration completes and the device is in the user mode you can use the remote system upgrade circuitry to query the cause of error and which application image failed 4 If a
84. mmer tool and add the dual_boot pof as shown in Figure 8 8 Click Start button to program the device when the hardware is set OK File Edit View Processing Tools Window Help 57 2 Hardware Setup NEEK10 USB 1 Enable real time ISP to allow background programming when available IPS File EKP File File Device Checksum Usercode Program Verify Configure dual boot pof 10 500 484 5 0032 00000000 CFMO CFM1 UFM M Change File e 9 ipi Save File TDI 4 Down v 10 500 484 5 TDO Figure 8 8 Download the pof Now you can set the BOOT SEL by SW16 you will find if you set BOOT_SEL 0 the image0 will be loaded and if you set BOOT_SEL 1 he imagel will be loaded asic MAX 10 NEEK 116 www terasic com August 9 2015 JA DTE RYAN 8 3 Nios Load In Single Boot Image After the internal configuration if a Nios II processor 15 contained in the image and the reset vector of the processor is set to onchip memory data section the CPU will load the code from the UFM in the onchip flash The CPU loading procedure occurs either in single image configuration mode or dual compressed image configuration mode You must make sure only one image contains the processor in dual compressed image configuration mode Users need to write the hardware and software binary into the nonvolatile flash memory for the MAX10 FPGA auto boot after
85. mperature sensor Accelerometer Power monitor Power e 5V 3A DC input MAX 10 NEEK 9 www terasic com www terasSic com August 3 2015 Chapter 3 Using the MAX 70 NEEK Board This chapter provides an instruction to use the board and describes the peripherals 3 1 Configuration of MAX 10 FPGA on MAX 10 NEEK There are two types of configuration method supported by MAX 10 NEEK 1 configuration configuration using JTAG ports JTAG configuration scheme allows you to directly configure the device core through JTAG pins TDI TDO TMS and TCK pins The Quartus II software automatically generates sof that are used for JTAG configuration with a download cable the Quartus II software programmer 2 Internal configuration configuration using internal flash Before internal configuration you need to program the configuration data into the configuration flash memory CFM which provides non volatile storage for the bit stream The information 1s retained within even if the MAX 10 NEEK board is turned off When the board is powered on the configuration data in the is automatically loaded into the MAX 10 FPGA B JTAG Chain on MAX 10 NEEK Board The FPGA device can be configured through JTAG interface on MAX 10 NEEK board but the JTAG chain must form a closed loop which allows Quartus II programmer to the detect FPGA device Figure 3 1 illustrates the JTAG chain on 10 NEEK board MAX 10
86. ned running with the 100MHz clock and the Nios II program is running in the on chip memory MAX 10 NEEK 80 www terasic com Tijasic August 3 2015 www terasic com AN S n A e FPGA 50 MHz TO nr M aca On Chip Memory D gt green Controller SDRAM i i System Intercoment Fabric Figure 6 16 Block Diagram of the DDR3 Basic Demo The system flow is controlled by a Nios II program First the Nios II program writes test patterns into the whole 128 MB of SDRAM Then it calls Nios II system function alt dache flush all to make sure all data has been written to SDRAM Finally it reads data from SDRAM for data verification The program will show progress in JTAG Terminal when writing reading data to from the SDRAM When verification process is completed the result is displayed in the JTAG Terminal B Altera DDR3 SDRAM Controller with UniPHY To use Altera DDR3 controller you need to perform 4 major steps e Create correct pin assignments for DDR3 Set up correct parameters in DDR3 controller dialog Perform Analysis and Synthesis by clicking Quartus menu Process Start Start Analysis amp Synthesis e TCL files generated by DDR3 IP by clicking Quartus menu Tools TCL Scripts B Design Tools e Quartus II 15 0 e Nios II Eclipse 15 0 B Demonstration Source Code e Quartus Project directory ddr3_nios e Nios II Eclipse Project workspace d
87. nerates a 100MHz clock for Nios II processor and the controller IP The LEDRs are controlled by the PIO IP The UART controller sends and receives command data and the command is sent through Putty terminal on the computer FPGA QSYS 50 2 KE e FTU Jac p m Mag e tt On Chip lt gt Memory p M ric lt gt USB Connector PIO qu Controller lt gt m lt gt UART Controller System Intercoment Fab Figure 6 7 Block Diagram of UART Control LED Demo B Design Tools e Quartus II 15 0 e Nios II Eclipse 15 0 MAX 10 NEEK T2 www terasic com Tijasic August 3 2015 www terasic com ANU S8 p ANS B Demonstration Source Code e Quartus Project directory uart usb e Nios II Eclipse project workspace uart_usb software B Nios II Project Compilation e Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse B Demonstration Batch File e Demo Batch File Folder uart usbdemo batch The demo batch file includes following files e Batch Files uart usb bat uart usb sh e FPGA Configure File usb sof e Nios Program usb elf B Demonstration Setup Please follow the procedures below to set up the demonstration e Connect a USB cable between your computer and the USB connector J18 on MAX 10 NEEK boar
88. nnel 7 of FPGA ADC2 The output audio signal from on board microphone will be pre amplified by audio operational amplifier OPA1612 then fed into the FPGA ADC Figure 3 26 shows the connection of on board microphone and MAX 10 FPGA 3 4 16 PS 2 Serial Port The MAX 10 NEEK comes with a standard PS 2 interface and a connector for a PS 2 keyboard or mouse Figure 3 27 shows the connection of PS 2 circuit to the FPGA Users can use the PS 2 keyboard and mouse on the MAX 10 NEEK simultaneously by a PS 2 Y Cable as shown in Figure 3 28 Instructions on how to use PS 2 mouse and or keyboard can be found on various educational MAX 10 NEEK 35 WWW terasic com Tijasic August 3 2015 www terasic com NOS n AN websites The pin assignment associated to this interface 1s shown in Figure 3 28 Q Note If users connect only one PS 2 equipment the PS 2 signals connected to the FPGA I O should be 52 CLK and PS2 DAT 4 PS2 CLK PS2 CLK2 U1 S4 f NIERA 2 MAX 10 4 P 92 DAT2 4 92 DAT Figure 3 27 Connections between the MAX 10 FPGA and PS 2 p N oF lt Figure 3 28 Y Cable for using keyboard and mouse simultaneously Table 3 14 Pin Assignment of PS 2 Signal Name FPGAPinNo Description VO Standard PS2_CLK V3 5 2 Clock 3 8V PS2 DAT PIN P3 PS 2 Data 3 8V PS2_CLK2 101 5 2 Clock reserved for second PS 2 device 3
89. ock SPI serial port clock 2 5 GSENSOR 15 Interrupt 1 2 5V GSENSOR_INT2 PIN 017 Interrupt pin 2 2 5V MAX 10 NEEK 40 www teraSic com asic August 3 2015 www terasic com ANU S n AN e 3 4 22 Micro SD Card Socket The board supports Micro SD card interface with x4 data lines It serves not only an external storage for the HPS but also an alternative boot option for MAX 10 NEEK board Figure 3 34 shows signals connected between the HPS and Micro SD card socket Table 3 20 lists the pin assignment of Micro SD card socket to the MAX 10 FPGA VCC2P5 VCCS3P3 SD U45 J21 LSF0108 MICRO SD DATO DATA AND S RYAN Level DAT2 MAX 10 Translator DAT3 CMD CLK Figure 3 34 Connections between the MAX 10 FPGA and SD card socket Table 3 20 Pin Assignment of Micro SD Card Socket Signal Name FPGA Pin No VO Standard D_CLK 6 SDClock 2 D CMD PIN C18 SD Command Line 2 2 2 MAX 10 NEEK 4 www terasic com Tijasic August 3 2015 www terasic com ANU S RYA e 3 4 23 Power Distribution System The 10 NEEK is powered by Linear Technology s power solution which provides high efficiency power management for FPGAs and SoCs Figure 3 35 shows the power tree of MAX 10 NEEK Switchin VOSA 12 2562 MAX1O VCC 1 2V 2227mA LTC3612 Up to 3A VCCD DC Power Jack CMOS Sensor Switching SOME 3 3 01073 MAX10 VCCIO LTC3612 U
90. ock diagram in Figure 6 18 the Nios II processor is used to communicate with the Client via SSEIT1II RGMII MII interface Ethernet Device MAX 10 NEEK 83 www terasic com Tijasic August 3 2015 www terasic com S n VA e 1000 100 10 Mbps CAT 5 amp Gateway with DHCP FPGA Ethernet Driver E Nios Il Simple Socket Server Figure 6 18 Block Diagram We will now cover the Qsys system in this demo which contains Nios II processor DDR3 memory JTAG UART timer Triple Speed Ethernet Scatter Gather DMA controller and other peripherals etc In the Core Configuration Tab of the Altera Triple Speed Ethernet Controller users need to set the MAC interface as RGMII as shown in Figure 6 19 System maxl qsys Path mac Triple Speed Ethernet altera eth tse Example Design Core Configurations Core variation 10 100 1000Mb Ethernet MAC Enable ECC protection 10 100 1 th Interface RGMII Use clock enable for MAC Use internal FIFO lumber of ports Transceiver type one Figure 6 19 Select RGMII Interface under MAC Configuration asic MAX 10 NEEK 84 www terasic com August 3 2015 JA DTE RYA o In the MAC Options tab See Figure 6 20 users should set up proper values for the PHY chip 88E1111 The MDIO Module should be included as it is used to generate a 2 5MHz MDC clock for the PHY chip from the controller s source clock here a 10
91. of this demonstration The NIOS program is stored in the onchip memory and the Nios II processor is running at 50 MHz The library is located in the files named I2C core cpp and I2C core h The I2C OpenCore IP is located in the folder 1 2 opencores under the project directory MAX 10 NEEK 67 www terasic com Tijasic August 3 2015 www terasic com AN S n A e FPGA QSYS LTC2990 pie Opencore dGe 4 129uuo219 u ulgjes gS LTC2990 LTC2990 Figure 6 1 Block diagram of Power Monitor demonstration Figure 6 2 illustrates the idea of how to measure the current for each power rail A current sense resistor RsENsE is added to the path of each power rail LTC2990 measures the voltage difference V1 V2 and calculate the current based on the formula below Current V1 V2 RsENSE The power consumption can be calculated by the following formula Power Consumption Vcc x Current Vcc x V1 V2 RsENSE Figure 6 2 Schematic of current sense MAX 10 NEEK 68 WWW terasic com Tijasic August 3 2015 www terasic com JA DTE n AN Figure 6 3 shows the register content of LTC2990 The voltage difference V1 V2 measured are written into two registers MSB register 06h and LSB register 07h The most significant bit 7 bit of MSB register is the data valid bit which indicates whether the current register content has been accessed since the result was last written to the register This bit will be
92. omes with a digital accelerometer sensor module ADXL345 commonly known as G sensor This G sensor is a small thin ultralow power assumption 3 axis accelerometer with high resolution measurement Digitalized output is formatted as 16 bit two s complement and be accessed through interface The I2C address of accelerometer is 0xA6 0xA7 More information about this chip can be found in its datasheet which is available on manufacturer s website or in the directory Datasheet folder of MAX 10 NEEK system CD Figure 3 33 shows the connections between the MAX 10 FPGA and accelerometer Table 3 19 lists the pin assignment of accelerometer to the MAX 10 FPGA VCC2P5 D U36 ADXL345 2 2K GSENSOR SCLK SCL_SCLK GSENSOR_SDI ANU S RYA GSENSOR CS n eme MAX 10 ENSOR SD gt CS_ n 00 ALT ADDRESS GSENSOR_INT1 GSENSOR INT2 nee Accelerometer Figure 3 33 shows the connections between the MAX 10 FPGA and accelerometer sensor Table 3 19 Pin Assignment of Accelerometer Sensor Signal Name FPGA Pin No Description Standard GSENSOR_SDI PIN C15 I2C serial data SPI serial data 2 5V E input 3 wire interface serial dta output GSENSOR SDO PIN B16 SPI serial data output I2C less 2 5V significant bit of the device address GSENSOR CS n PIN C16 SPI enable 2 5 mode selection 1 2 5 SPI idle mode I2C communication enabled 0 SPI communication mode I2C disabled GSENSOR SCLK PIN A15 I2C serial cl
93. onfigure check box and then click Start button to download the sof file into the FPGA device as shown in Figure 3 7 MAX 10 NEEK 14 www terasic com Tijasic August 3 2015 www terasic com p Programmer Chain2 cdf File Edit View Processing Tools Window Help iJ Hardware Setup Enable real time ISP to allow background programming when available NT File i Usercode Program Verify Blank Examine Security Erase ISP uu Start Configure Check Bit CLAMP F NEEK1O trunk cd syst 10MS0DAF484C6G Li m Figure 3 7 Program sof file into the FPGA device B Internal Configuration e The configuration data to be written to CFM will be part of the programmer object file pof This configuration data 1s automatically loaded from the into the 10 devices when the board 1s powered up e Please refer to Chapter 8 Programming the Configuration Flash Memory CFM for the basic programming instruction on the configuration flash memory MAX 10 Device Internal JTAG 4 Configuration In System Programming CFM Figure 3 8 High Level Overview of Internal Configuration for MAX 10 Devices MAX 10 NEEK 15 WWW terasic com Tijasic August 3 2015 www terasic com ANU S n AN e 3 2 Board Status Elements In addition to the 10 LEDs that FPGA device can control there are 4 indicators which can indicate the board status See Figure 3 9
94. onstrations hdmi rx lcd Bitstream used hdmi lcd sof Demonstration Batch File Demo batch file folder Demonstrations hdmi rx Memo batch Batch file test bat FPGA configuration file hdmi lcd sof Demonstration Setup Make sure both Quartus II and USB Blaster II driver are installed on your PC Use a HDMI DVD player and use HDMI cable to connect the MAX 10 NEEK to the player Power on the MAX 10 NEEK board Use File Manager to locate the hdmi lcd emo batch folder Launch the configuration and program download process by double clicking test bat batch file This will configure the FPGA download the demo application to the board and start its execution After it s done the screen should look like the one shown in Figure 5 17 Tilasic 96A Bn mw terasic com August 3 2015 D Wser Desktop NEEKI RA_UIPN demo_batchoC altera 15 0 1 45 quartus bin64 quartus_pgm exe m jtag c 1 o p NEEK18 golden top sof D Wser Desktop NEEK16 R amp _UIP demo_batch gt pause Figure 5 17 Launching The hdmi rx Demo If there is no video input the screen will display a color of blue Once there is video input the screen will show the video One thing to note 16 that we do not provide the HDCP KEY and this would cause issues to some specific high resolution video which not being able to play correctly Therefore in that scenario we would suggest you contac
95. orrect bank voltage setting or pin assignment e Board is malfunctioned because of wrong device chosen declaration of pin location or the direction 1s incorrect forgotten e Performance degradation due to improper pin assignment 4 2 General Design Flow The design flow of building a Quartus II project for NEEK10 using the NEEK10 System Builder is illustrated in Figure 4 1 It gives users an overview about the steps starting from launching the System Builder to configuring the FPGA The left hand side of the chart can be done within minutes After users enter the design requirements the 10 System Builder will generate Quartus II project files Quartus II setting file top level design file Synopsis design constraint file and the pin assignment document The top level design file contains a top level Verilog HDL wrapper for users to add their own MAX 10 NEEK 43 WWW terasic com 1 4 5 August 3 2015 www terasic com JA DTE RAe design logic The Quartus II setting file contains information such as FPGA device type top level pin assignment and the I O standard for each user defined I O pin These files can be modified according to the project requirements After the compilation is successful users can download the sof file to the developmenet board via JTAG interface using the Qaurtus II programmer Launch Launch Quartus II and NEEK10 System Builder Open Project Add User Design Logic Compile to generate SOF
96. ory The Nios II processor writes the display content to the DDR3 The SG DMA reads the data and translates it to the VGA controller through the Avalon Streaming interface The I2C controller and the PIO Controller are implemented to get the touch action data of the MTL2 touch screen The Nios II processor accesses the SD card through an SD card SPI controller The Application Selector uses an SD card for storing applications hardware and software binary files The SD card must be formatted with the FAT 16 32 file system Long file names are supported The Dual Configuration IP provides an Avalon MM interface for NIOS II processor to access the MAX 10 NEEK 106 WWW terasic com Tijasic August 3 2015 www terasic com JA DTE n AV remote system upgrade circuitry the 10 FPGA device It s the critical part of this demonstration The Altera Dual Configuration IP core offers the following capabilities through Avalon MM interface Asserts RU nCONFIG to trigger reconfiguration Asserts RU nRSTIMER to reset watchdog timer if the watchdog timer 1s enabled Writes configuration setting to the input register of the remote system upgrade circuitry Reads information from the remote system upgrade circuitry The onchip flash is divided into three parts for this demonstration CMFO is used to store imageO0 which is the hardware of the application selector code and is used to store 1magel which is the hardware of the application being
97. our micro SD card root directory as well as in theSystem CD under Factory Recovery MApplication Selector folder Figure 7 1 Application Selector Main Interface shows the photograph of the application selector main interface Application Selector painter g_sensor humi_temp camera hdmi_rx Figure 7 1 Application Selector Main Interface Also you can easily convert your own applications to be loadable by the application selector For more information see Creating Your Own Loadable Applications in section 7 4 If you have lost the contained files in the SD card you could find them on the MAX 10 NEEK System CD MAX 10 NEEK 105 www terasic com Tijasic August 3 2015 www terasic com ANU S n AV under the Factory Recovery folder 7 2 Application Selector Details This section describes some details about the design of the application selector utility FPGA SOPC r 50 2 D EM __ o Dual Configuration ee Wiki 4 SD SPI 1 2 DDR3 Memory eue PIO 7 12euuooJe u uigjs S Figure 7 2 Block Diagram Of Application Selector Figure 7 2 shows the hardware block diagram of this demonstration The system requires a 50 MHz clock provided from the board The PLL generates a 100MHz clock for Nios II processor and the other controllers The DDR3 works as the system mem
98. p to 3A On Board ICs 3 3V power LDO LI CMOS Sensor 2 8V 81 88MA lt n Up to 0 25A VAA VAA PIX to 0 75A MAX10 VCCIO TV Decoder APP 1 8V 511MA CMOS Sensor VCCIO SU 2 5v 1962mMA 10 VCCA VCCADC n S 2 5V 651mA LTC3612 to AVDD VDDO LDO DDR3 VDD VDDQ 1 5V 800mA 173022 Up to 1A MAX10 VCCIO Power LDO LCD Dri 3 3V 204mA LDO LCD TP 3 3V 20mA Figure 3 35 Power tree of MAX 10 NEEK TijasiC MAX 10 NEEK 42 www terasic com August 3 2015 www terasic com Chapter 4 NEEK70 System Builder This chapter introduces the NEEK 10 System Builder to help users get started in creating their own projects in literally minutes It also describes the design flow and includes an example for users to get familiar with the tool 4 1 Introduction The NEEK10 System Builder is a Windows based utility It is created to help users build a top project for NEEK10 within minutes The generated Quartus II project files include Quartus II project file qpf Quartus II setting file qsf Top level design file v Synopsis design constraints file sdc Pin assignment document htm The above files generated by the NEEKIO System Builder can also prevent situations that are prone to compilation error when users manually edit the top level design file or place pin assignment The common mistakes that users encounter are e Board is damaged due to inc
99. please refer the details in Table 3 1 D8 JTAG TX D7 JTAG RX D6 CONF D D13 5V Power D14 2 5V Power D16 1 2V Power ANALOG EE 4a DEVICES NE MCN 2 757 i 73 TEXAS INSTRUMENTS c oa gt 3 2E 58 Figure 3 9 LED Indicators on MAX 10 Table 3 1 LED Indicators Sor luminate when 5V power isaeive 0 Dia esv Power Mmuminate when 25V powerisacive _ o h2V Power luminate when 12V power isete 0 CONF DONE illuminate when configuration data is loaded into MAX 10 device without error D7 JTAG RX Illuminate during data is uploaded from 10 device to through UB2 JTAG TX during configuration data is loaded into MAX 10 device from UB2 TxD MXD illumine during transmitting data via USB RXD RXD during receiving data via USB MAX 10 NEEK 16 www terasic com Tijasic August 3 2015 www terasic com S nV AN 3 3 Clock Circuitry Figure 3 10 shows the default frequency of all external clocks to the MAX 10 A clock generator is used to distribute clock signals with low jitter The three SOMHz clock signals connected to the FPGA are used as clock sources for user logic One 25MHz clock signal is connected to the clock input of Gigabit Ethernet Transceiver One 24MHz clock signal is connected to the clock inputs of USB microcontroller of USB Blaster II One 28 63636MHz clock signal is connected to the clock input of HDMI
100. power cycling The onchip flash memory in the FPGA provides the possibility to boot the software for the Nios II processor The demonstration my_first_niosII is designed for Nios II processor loading software after the FPGA configuration complete The section describes the detailed steps of the design e onchip flash controller ip should be added into the Qsys for storing software code The CPU data master and instruction master interface are connected to the onchip flash data bus as shown in Figure 9 external connection Conduit pio external con cpu Nios II Processor clk Clock Input clk 50 reset Reset Input clk data master Avalon Memory Mapped Master clk instruction master Avalon Memory Mapped Master elk irq Interrupt Receiver clk debug reset request Reset Output clk debug_mem_slave Avalon Memory Mapped Slave elk 0x0044 0800 custom instructi Custom Instruction Master E enchip flash Altera On Chip Flash clk Clock Input clk 50 nreset Reset Input elk data Avalon Memory Mapped Slave clk 0x0020 0000 csr Avalon Memory Mapped Slave clk 0 0044 1010 Figure 8 9 Qsys Design e And the reset vector of the CPU should be onchip flash data section The configuration mode in the onchip flash parameter setting and the Quartus device setting window should all be set as Single Uncompressed Image e In the BSP Editor Nios II SBT for Eclipse utility of the Eclipse all the check box in the hal linker table shou
101. pse 15 0 Demonstration Source Code Project directory socket server Nios II Eclipse Project workspace socket server software Demonstration Batch File Demo batch file folder Demonstrations socket server demo batch Batch file socket server bat FPGA configure file socket server sof Application file folder socket server demo_batch Application file open telnet bat Demonstration Setup Please follow the procedures below to set up the demonstration Please make sure both Quartus II and USB Blaster II driver are installed on the host PC Connect the USB cable from the USB Blaster II port 78 on the MAX 10 NEEK board to the host PC Power on the MAX 10 NEEK board Execute the demo batch file socket server bat under the folder Demonstrations socket server demo batch then the IP address and port number are assigned as shown below in Figure 6 24 Tilasic 96A ee mw terasic com www terasic com August 3 2015 Em Altera Nios II EDS 15 0 gcc4 prepped 1 interface initializing tze mac init 1 TSE MAC H found at address HxH7BWHH2HBH PHY Marvell 8E1111 found at PHY address of MAC Grouplhl PHY H H1 Automatically mapped to tze deuice Hl PHY H H Restart fluto Megotiation checking PHY link PHY H H 1 Auto Negotiation PASSED Mode changed to RGHII Modified MII to Copper mode Enable RGMII Timing Control PHY reset PHY CH 6 Checking link PHY H H 1 Link not ye
102. r feature introduces hysteresis to the input signal for improved noise immunity especially for signal with slow edge rate and act as switch debounce in Figure 3 12 for the push buttons connected VCC1P5 Aum zm TT tT TT U22 KEY3 9 222 d bl MLAX 10 21 _ oe Figure 3 11 Connections between the push buttons and the MAX 10 FPGA MAX 10 NEEK 18 www terasic com Tijasic August 3 2015 www terasic com S n AN ouem depressed o released Before o Schmitt Trigger Debounced coy Figure 3 12 Switch debouncing There are two ten switches connected to the FPGA as shown in Figure 3 13 These switches are used as level sensitive data inputs to a circuit Each switch is connected directly and individually to the FPGA When the switch is set to the DOWN position towards the edge of the board it generates a low logic level to the FPGA When the switch is set to the UP position a high logic level 1s generated to the FPGA m Jors cz gt m Logic t SW9 SW8 SW7 SW6 SW5 SW4 SW3 SW2 SW1 SWO Logic 0 Figure 3 13 Connections between the slide switches and the MAX 10 FPGA There are also ten user controllable LEDs connected to the FPGA Each LED is driven directly and individually by the MAX 10 FPGA driving its associated pin to a high logic level or low level to turn the LED on or off respectively Figure 3 14 shows the connections between L
103. sll CPU Vectors Setting e The configuration mode in Quartus device and options setting window should be set to dual compressed image mode as shown in Figure 7 5 Category General Configuration Configuration Programming Files Specify the device configuration scheme and the configuration device Unused Pins 8 Dual Purpose Pins Configuration scheme Internal Configuration z Capacitive Loading T Board Trace Model Configuration mode Dual Compressed Images 512Kbits UFM I O Timing Configuration device Voltage Pin Placement Auto Error Detection CRC Use configuration device CvP Settings Device Options Partial Re atio E Configuration device I O voltage Force VCCIO to be compatible with configuration I O voltage Figure 7 5 Setting Configuration Mode MAX 10 NEEK 108 WWW terasic com Tijasic August 3 2015 www terasic com JA DTE n A s e Create your software project in Nios II Eclipse and generate the elf file by building the software e On your host PC launch a Nios Command Shell from Start gt Progrms gt Altera gt Nios II lt version gt EDS gt Nios Command Shell e From the command shell navigate to where your ELF file is located and create your software flash file using the following command e elf2flash base qspi flash base addrss end qspi flash end address reset qspi flash base addrss input lt your software name
104. sor in this demonstration For multi touch processing the Nios II polling the associated touch information to process the touch event when touch activity occurs B Function Description Figure 6 37 shows the result of this demonstration Camera LCD Panel Or Figure 6 37 Camera demo running on MAX 10 NEEK board A Five fingers touch function is implemented in this demonstration to stop LCD from refreshing the camera image This is achieved by stopping the input of Frame Buffer VIP and the image retrieved by the Clock Video Output VIP from the Frame Buffer VIP is always the same The camera image can start refreshing again by a single finger touch to enable the input of Frame Buffer VIP The zoom in and zoom out gestures with two fingers are implemented to control the display active readout window on the image sensor Auto focus function is triggered by single finger touch MAX 10 NEEK 101 www terasic com Tijasic August 3 2015 www terasic com IAN DERYA o Figure 6 38 shows the Five fingers touch to stop the camera video Figure 6 38 Five fingers touch to stop the camera video Figure 6 39 shows the zoom in or zoom out gesture with two fingers Figure 6 39 Two fingers gesture to control zoom in or zoom out MAX 10 NEEK 102 WWW terasic com asic August 3 2015 www terasic com JA DERYA o Figure 6 40 shows the autofocus function with single finger touch Figure 6 40 Single finger touch to trigger the auto
105. t HDCP and apply for authorization For more details you can check at http www digital cp com Figure 5 18 shows the setup of the demo HDMI Player Speaker Figure 5 18 The Demo Setup MAX 10 NEEK 66 www terasic com 1 4 5 August 3 2015 www terasic com ANU S RYA o Chapter 6 NIOS Based Example Codes There are several NIOS based examples for users to get started and try them on the MAX 10 NEEK board All the NIOS based examples can be found in the system CD under the folder named Demonstrations Users are free to use or modify these example for personal use or education purpose Note The output files generated after compilation 1n Quartus II e g sof and pof files are saved the folder output files under the directory of demo project The workspace of Nios II Eclipse project 1s located in the folder software under the directory of demo project 1 Power Monitor The power monitor demo shows how to measure the power consumed through the onboard power monitor chip LTC2990 There are three LTC2990 to monitor the following power rails 3 3V VCCIO 2 5V Core 2 5V VCCIO 1 5V VCCIO 2V VCC The power monitor chip LTC2990 communicates with the FPGA via D2C protocol The OpenCore IP is used in this demonstration for the MAX 10 device to communicate with the three LTC2990 which have different I2C slave address 98h 9Ah and 9Ch B Block Diagram Figure 6 1 shows the system block diagram
106. t established restart auto negotiation PHY 6 6 Restart fluto Megotiation checking PHY link PHY H H 1 fiuto Meyotiation PASSED PHY H H 1 Link established PHY 6 6 Speed 1668 Duplex Full DK CHD GONFIG HxHBHBHBHBH MAG post initialization CMD CONFIG HxBHB4BWBHB2Hbhb tze sgdma read initl HX descriptor chain desc 1 depth created ctest init called IP address of eti 192 168 1 118 Created Inet main task Prio 227 Created clock tick task Prio 35 Acquired address via DHCP client for interface etl IP address 192 168 21 144 pubnet Mask 255 255 2554 Gateway 192 168 21 1 Simple Socket Server starting up sss_task Simple Socket Server listening on port Created simple socket server task Prio 45 Figure 6 24 Simple Socket Server e To establish connection start the telnet client session by executing open_telnet bat file and include the IP address assigned by the DHCP server provided IP along with the port number as shown below in E C Windows system32 cmd exe Microsoft Telnet Client Escape FIJ CTRL 1 Microsoft Telnet open 192 168 21 144 3H Figure 6 25 Telnet Client MAX 10 NEEK 89 1 4 51 August 3 2015 www terasic com Ie RYAN JA DTE n AV e From the Simple Socket Server Menu enter the commands in the telnet session Entering number from zero through seven followed by a return causes the corresponding LEDRs DO D7 to
107. ta valid 2 5V 0 0 PIN A10 GMII and MII receive data 0 2 5V NET RX D 1 PIN B10 GMII and MII receive data 1 2 5 0 2 PIN 11 GMII MII receive data 2 2 5V NET D 3 PIN B11 GMII and MII receive data 3 2 5 RX CLK PIN J10 GMII and MII receive clock 3 3V NET RST n PIN C14 Hardware Reset Signal 2 5 NET MDIO PIN E12 Management Data 2 5V MAX 10 NEEK Tijasic www terasic com 29 www terasSic com August 3 2015 ANU S RAe NET MDC PIN D12 Management Data Clock Reference NET RX COL PIN C9 GMII and MII collision NET RX CRS PIN 9 GMII and carrier sense NET GTX CLK PIN C11 GMII Transmit Clock PIN 7 Parallel LED output of 100BASE TX link PIN C13 Interrupt open drain output 3 4 10 HDMI RX The development board provides High Performance HDMI Receiver via the Analog Devices ADV7611 which incorporates HDMI v1 4a features including 3D video support and 165 MHz supports all video formats up to 1080 and UXGA ADV7611 is controlled via a serial I2C bus interface which is connected to pins on the MAX 10 FPGA A schematic diagram of the HDMI RX circuitry is shown in Figure 3 23 Detailed information on using the ADV7611 HDMI RX is available on the manufacturer s website or under the Datasheets HDMI folder on the Kit System CD Table 3 11 lists the HDMI Interface pin assignments and signal names relative to the MAX 10 device HDMI_RX_D 23 0 Em
108. ter any problems e Altera Corporation e 101 Innovation Drive San Jose California 95134 USA Email university altera com e Terasic Technologies e No 176 Sec 2 Gongdao 5th Rd East Dist Hsinchu City 30070 Taiwan Email support terasic com Tel 886 3 575 0880 Website max 10 neek terasic com MAX 10 NEEK 4 www terasic com 1 4 5 August 3 2015 www terasic com ATERA Chapter 2 Introduction of the MAX 10 NEEK Board 2 1 Layout and Components Figure 2 1 shows a photograph of the board It depicts the layout of the board and indicates the location of the connectors and key components Camera Light 7 Touch LCD 800x480 Module Sensor Figure 2 1 MAX 10 NEEK development board top view MAX 10 NEEK 5 www terasic com Tijasic August 3 2015 www terasic com NOS n AN 2x5 Camera JTAG Module Audio 5v pc Header USB PS2 HDMI RX Connector Codec MIC In Line In Line Out ADC Header Jack Blaster 11 gt 3 777 M t n lt un 212 9 1 4 MIC marae 7 22 tc NEAN me Potentiometer Power vt TE Bhs t 4 2 7 gt E re Y x b i H A T Spot 1 F 1x3 ADC ON OFF 3 xD S i i Eri EU Lu zer dud p Act Peripheral ERIT BS biz komme CM Selection T iis ADC IN1 pu NOG 7 M e 52 mt gt Dy P bes gt mi ndis 4 4
109. the Multi touch LCD module based on Altera Qsys tool and the Video and Image Processing VIP suite It demonstrates how to use multi touch gestures and resolution The GUI of this demonstration is controlled by the program in Nios IL B Operation Description Figure 6 27 shows the Graphical User Interface GUI of Painter demo The GUI 15 divided into 4 separate areas Painting Area Gesture Indicator Clear Button and Color Palette Users can select a color from the color palette and start painting in the paint area If a gesture is detected the associated gesture symbol will be shown in the gesture area To clear the painting area click the Clear button MAX 10 NEEK 90 www terasic com Tijasic August 3 2015 www terasic com Painting Area 4 Gesture Clear Color Palette Indicator Figure 6 27 GUI of Painter Demo Figure 6 28 shows the single finger painting of canvas area Figure 6 28 Single Finger Painting MAX 10 NEEK 9 WWW terasic com 1 4 5 August 3 2015 www terasic com ANU RYA o Figure 6 29 shows the zoom in gesture Figure 6 29 Zoom In Gesture Figure 6 30 shows the 5 Point painting of canvas area Figure 6 30 5 Point Painting MAX 10 NEEK 02 WWW terasic com 1 4 5 August 3 2015 www terasic com ANU S RYAN e B System Description For LCD display processing the reference design 1s developed based on Altera s Video and Image Processing VIP suite Th
110. the demo batch file ps2 mouse bat under the folder Demonstrations ps2_mouse demo_batch Plug in the PS 2 mouse Press KEYO to enable data transfer Press KEY 1 to clear the display data cache The 7 segment display shows X displacement when SWO is low and Y displacement when SWO is high The display should change when the PS 2 mouse moves e The LEDR 2 0 will blink according to Table 5 1 when the left button right button and or middle button 1s pressed Table 5 1 Description of 7 segment Display and LED Indicators Indicator Name Description LEDRO Left button press indicator LEDR1 Right button press indicator LEDR2 Middle button press indicator HEXO Low byte of X Y displacement HEX1 High byte of X Y displacement est a www terasic com NU S n AN 5 2 Power Monitor There are three built in power monitor LTC2990 on the NEEKIO board to observe total of six voltage and current buses Each LTC2990 can monitor two sets of voltage and current rail The six sets correspond to the core voltage current and I O voltage current of MAX 10 device and the power rails of 5V 3 3V 1 2V 1 5V of the system This demonstration uses these six buses to calculate the power consumption and display the result on the two 7 segments The voltage measured from the sense resistor will be digitized through the power monitor and feed into the MAX 10 device via I2C protocol The current is calculated based on the value of the sense resis
111. toggle on or off on the MAX 10 NEEK board as shown below in Figure 6 26 Hil Altera Nios EDS 15 0 gcc4 cB X B Telnet 192 168 21 144 PHY Link established PHVI8 01 Speed 1888 Duplex Full CMD_CONFI G 6x66666006 ios II Simple Socket Server Menu 0 2 Toggle board LEDRs AC post initialization CMD_CONFIG 6x6466626b Q Terminate session tse sgdma read initl descriptor chain desc 1 depth created ctest init called IP address of eti 192 168 1 110 reated Inet main task Prio 2 reated clock tick task Prio 3 Acquired IP address via DHCP client for interface address 192 168 21 144 Subnet Mask 255 255 255 6 ateway 192 168 21 1 Enter your choice amp press return Socket Server Command 1 2 gt Simple Socket Server Command 2 j Simple Socket Server Command 3 Socket Server Command 4 Socket Server Command 5 Simple Socket Server starting up sss_task Simple Socket Server listening on port 30 reated simple socket server task Prio 4 sss_handle_accept accepted connection request from 192 168 21 134 sss_handle_receive processing RK data for LED_PIO_BASE set for LED_PIO_BASE set for LED_PIO_BASE set for LED_PIO_BASE set for LED_PIO_BASE set Figure 6 26 Display Progress and Result Information for the Socket Server Demonstration 6 6 LCD Painter This demonstration shows how to implement a painter demo on
112. tor and the voltage measured The power consumption of each bus can be calculated accordingly and switched via SW 2 0 onboard B Function Block Diagram Figure 5 2 is the function block diagram of this demonstration The power bus monitored are SVCORE 2 5VCCIO 1 5 VCCIO 1 2VCC 5VCC 3 32VCCIO The sensing resistors connected between the source and the system are 0 01 2 0 01 2 0 01 2 0 01 2 0 01 2 0 01 2 respectively When the system is powered on there will be current floating through each bus and causing voltage drop across the sensing resistors The power monitor LTC2990 will convert the voltage drop from analog to digital and the result can be retrieved via I2C protocol The module POWER can read out the result of each power monitor and calculate the power consumption accordingly The power bus can be selected by switching SW 2 0 and the value will be displayed on the two 7 segments the NEEK 10 board The unit is in mW LH Lt Lt FPGA NU S RYA o Core 2 5v 0 10 Sensor femna MAX 70 LTC2990 I2C slave address 98h VCCIO 2 5v 0 10 Sensor fama VCCIO 1 5v 0 1 CCIO 1 5v 0 10 Sensor LTC2990 12C slave address 9ah VCC 1 2v 0 0090 Sensor fma VCC 5v 0 0090 Sensor fag 1 2990 I2C slave address 9ch Illic ae VCCIO 3 3v 0 10 Sensor fama SW2 SW1 SWO Figure 5 2 Block diagram of Power Monitor demonstration MAX 10 NEEK 53 www terasic com Tijasic August 3
113. tton x 5 LED x10 Switch x 10 lt lt Segment x2 Power Monitor lt G sensor Humidity Sensor Light Sensor Audio Codec HDMI RX microSD Card PS2 DAC QSPI Flash UART to USB DDR3 SDRAM Ethernet CS2 Camera LCD Touch Panel Uy 1122 105 lt lt A B Default Setting TMD 2x6 GPIO Header Save Setting Generate None Prefix Name Load Setting Exit Figure 4 4 List of onboard peripherals in System Configuration B Project Settings NEEK10 System Builder also provides the option to load a setting or save the current board configuration in cfg file as shown in Figure 4 5 MAX 10 NEEK 47 www terasic com Tijasic August 3 2015 www terasic com ANU S RYA o MAX 10 NEEK V1 0 0 System Confiquration NBTERYA Project Name MAX 10 NEEK FPGA Board LOO CLOCK Button x 5 LED x10 Switch x 10 lt I Segment 2 Power Monitor lt G sensor Humidity Sensor Light Sensor Audio Codec HDMI RX microSD Card PS2 DAC QSPI Flash UART to USB DDR3 SDRAM Ethernet 52 Camera LCD Touch Panel Wiha y NEEK 1055s a ia E Default Setting TMD 2x6 GPIO Header Save Setting Generate None Prefix Name Load Setting Exit Figure 4 5 Manage project settings B Project Generation When users press the Generate button as shown in Figure 4
114. und on the manufacturer s website or in the directory MAX10_NEEK_datasheets Audio CODEC of DECA System CD AUDIO MCLK AUDIO BCLK TLV320AIC3254 AUDIO WCLK AUDIO DIN MFP1 AUDIO DOUT MFP2 AUDIO SCLK MFP3 NUERA AUDIO_SCL_S_n O MAX 10 2 AUDIO MISO MFP4 AUDIO SPI SELECT AUDIO RESET n AUDIO GPIO MFP5 Audio CODEC zen Line Out Figure 3 18 Connections between the FPGA and audio CODEC Table 3 7 Pin Assignment of Audio CODEC FPGA Pin M Signal Name No Description Standard AUDIO MCLK PIN J11 Master output Clock 2 5V AUDIO BCLK PIN J12 Audio serial data bus primary bit clock 2 5V AUDIO WCLK PIN H12 Audio serial data bus primary word clock 2 5 AUDIO DIN MFP J13 Audio serial data bus data output digital microphone 2 5 output AUDIO DOUT 2 H13 Audio serial data bus data input general purpose input 2 5V AUDIO SCLK H14 SPI serial Clock headphone detect output 2 5V AUDIO SCL SS n PIN F15 2 Clock SPI interface mode chip select signal 2 5V AUDIO SDA MOSI PIN F16 12 Data SPI interface mode serial data output 2 5 AUDIO MISO MFP4 E13 Serial data input General purpose input 2 5 AUDIO SPI SELECT PIN E14 Control mode select pin 2 5V AUDIO RESET n PIN D13 Reset signal 2 5V AUDIO GPIO MFP5 D14 General Purpose digital IO CLKOUT input 2 5V 3 4 6 Two Analog
115. used gsensor lightsensor lcd sof e Nios II Eclipse project workspace gsensor lightsensor lcd software B Demonstration Batch File e Demo Batch File Folder gsensor lightsensor lcd demo batch The demo batch file includes the following files e Batch File gsensor lightsensor lcd bat gsensor lightsensor lcd sh e FPGA Configure File gsensor lightsensor lcd sof e Nios Program gsensor lightsensor lcd elf B Demonstration Setup Please follow the procedures below to set up the demonstration e Load the bit stream into the FPGA on the MAX 10 NEEK e Run the Nios II Software under the workspace gsensor_lightsensor_Icd software Note e After the Nios II program is downloaded and executed successfully a prompt message will be MAX 10 NEEK 95 www terasic com Tijasic August 3 2015 www terasic com PNOTSRYA e displayed in Nios2 terminal its ADXL345 s ID 5 e Tilt the MAX 10 NEEK to all directions and you will find that the angle of the g sensor and value of light sensor will change Figure 6 33 shows the demonstration result Figure 6 33 Digital Accelerometer demonstration Q Note Execute gsensor lightsensor lcd Memo batchWMsensor lightsensor lcd bat to download sof and elf files This demonstration illustrates steps to evaluate the performance of humidity and temperature sensor HDC1000 The HDC1000 is a fully integrated humidity and temperature sensor providing excellent measurement accuracy and long ter
116. ust 3 2015 www terasic com ANU S8 RYA e FPGA Device MAX 10 10M50DAF484C6G Device Integrated dual ADCs each ADC supports dedicated analog input and 8 dual function pins 50K programmable logic elements 1 638 Kbits embedded memory 5 888 Kbits user flash memory 4 PLLs Configuration and Debug e On board USB Blaster II mini USB type B connector e Optional JTAG direct via 10 pin header e One slide switch for dual boot image selection Memory Device e 256MB DDR3 SDRAM 64Mx16 and 128Mx8 e 512Mb QSPI Flash e Micro SD card socket Communication and Expansion Header Gigabit Ethernet PHY with RJ45 connector UART to USB USB Mini B connector 5 2 mouse keyboard connector 2x6 TMD Terasic Mini Digital Expansion Header Display e 800x480 7 0 inch Color LCD with 5 point Capacitive touch Audio 24 bit CD quality audio CODEC with line in line out jacks Video Input e HDMI RX incorporates v1 4a features including 3D video supporting e 8M pixel MIPI CS2 color camera input Analog Two MAX 10 FPGA ADC SMA inputs Potentiometer input to ADC On Board MIC input to ADC 2x10 ADC header with 16 analog inputs connected to MAX10 ADCs One DAC SMA output MAX 10 NEEK 8 www terasic com ijasic August 3 2015 www terasic com ANU S n AN Switches Buttons and Indicators Five push buttons Ten slide switches Ten red user LEDs Two 7 segment displays Sensors Ambient light sensor Humidity and te
117. www terasic com August 3 2015 www terasic com AU S RYA o Table 3 17 Pin Assignment of Ambient Light Sensor Signal Name FPGA Pin No Description Standard LSENSOR SCL PIN M1 2 Serial Clock 3 3V LSENSOR SDA PIN T3 2 Serial Data 3 3V LSENSOR INT PIN M2 Interrupt signal from Sensor 3 3V 3 4 20 Humidity and Temperature Sensor MAX 10 NEEK has a humidity and temperature sensor HDC 1000 that provides excellent measurement accuracy at very low power HDC1000 sensor is placed at board edge and away from the heat source of MAX 10 NEEK so that user can make ambient temperature measurement without heat interference from the heat source of MAX 10 NEEK Figure 3 32 shows the connection of humidity and temperature sensor to MAX 10 FPGA Table 3 18 lists the humidity and temperature sensor pin assignments VCC3P3 U50 HDC1000 2 2K AND S RYAN SCL MAX 10 SDA DRDYn Figure 3 32 shows the connections between the MAX 10 FPGA and humidity and temperature sensor Table 3 18 Pin Assignment of Humidity and Temperature Sensor Signal Name FPGA Pin No Description Standard RH TEMP 2 SCL Y18 2 Clock for HDC1000 Sensor 3 3V RH TEMP 2 SDA W18 2 Data for HDC1000 Sensor 3 3V RH TEMP DRDY n PIN Y19 Data ready input from HDC1000 Sensor 3 3V MAX 10 NEEK 39 WWW terasic com 124 51 August 3 2015 www terasic com ANU S8 RYA e 3 4 21 Accelerometer Sensor The board c
118. xel Output Port 3 3V HDMI_RX_D19 PIN AB12 Video Pixel Output Port 3 3V HDMI_RX_D20 PIN AA12 Video Pixel Output Port 3 3V HDMI_RX_D21 PIN W13 Video Pixel Output Port 3 3V HDMI 022 PIN W12 Video Pixel Output Port 3 3V HDMI RX D23 PIN V13 Video Pixel Output Port 3 3V HDMI RX CLK PIN P11 Line Locked Output Clock 3 3V HDMI RX DE PIN W10 Pals Enable Signal for Digital 3 3V Video HDMI HS PIN V12 Horizontal Synchronization 3 3V HDMI VS PIN W11 Vertical Synchronization 3 3V HDMI_RX_INT1 PIN P12 Interrupt Signal 3 3V HDMI 2 SCL PIN R13 2 Clock 3 3V HDMI_I2C SDA PIN P13 I2C Data 3 3V PIN R12 Audio Master Output Clock 3 3V HDMI_LRCLK PIN V11 Audio Left Right Clock 3 3V HDMI SCLK PIN W8 Audio Serial Output Clock 3 3V HDMI AP PIN W9 Audio Output Pin 3 3V HDMI RESET n PIN AA13 System Reset Input 3 3V 3 4 11 8M Pixel MIPI CS2 Camera The MAX 10 NEEK provides a high performance 8 megapixel RAW image sensor that delivers 3264x2488 at 30 fps Through Toshiba TC358748XBG MIPI CSI 2 to Parallel bridge device converts MIPI data from on board camera module to MAX 10 FPGA over a parallel port interface Figure 3 24 shows the connection of MIPI camera module MIPI CSI 2 to parallel bridge device and 10 FPGA The pin assignment associated to this CSI 2 to parallel interface 15 shown in Table 3 12 www terasic com MAX 10 NEEK 31 Tiasic August 3 2015 www terasic com 2 TC358 48XBG 2

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