PCI8282 User's Manual
Contents
1. Check Device Information and Press Setup Button to Load DASP 52064 Library e Step5 Perform DIO test of DASP 52064 as shown in following At first key in the digital output port value for instance writes OxFFFFFFFF to turn on all the digital output channels of it and then press the Output button to send the digital output port value to DASP 52064 Verify the digital input value presented in the DI O test panel of TooLWoRkKkSHOP for DASP 52064 Hardware Installation 45 DASP 52064 Card User s Manual Device Information N 0x041 ID amp SN oo s 0 0410 00 Offset B DLL Version 20041011 my Card Type DASP52064 DEN Enable Release White gt 10 Output Auto Test Interrupt Test Bit 0 7 NE NE Bit 8 15 eee Bit 16 23 ED Bit 24 31 p Device Information 20 5405009001 DLL Version 20041011 Card Type DASP52064 Enable Release Digital VO Test Digital O np amp _Digltal 0 Output gauto Test Interrupt Test Bit 0 NN Bit 8 15 Bit 16 23 mm m mm EE EE EM wi Bit 24 31 Perform Digital Input Output Test by Set the DO Port Value and Read Back the DI Port Value of2. 48 Cow 49 9 cow Hardware Installation 9 DASP 52064 Card User s Manual 2 3 DI DO Circuits and Wiring The optically isolated digital input and digital output wiring diagrams and functional block diagrams of DASP 52064 are depicted in 2 3 2 and 2 3 3 2 3 1 Digital Input Port Circuits and Wiring There are 32 digital input channels on DASP 52064 board The following figure demonstrates the circuit configuration of digital input port The basic layout and wiring is presented as below Ineternal Circut Photocoupler Block Diagram of Internal Circuits and Wiring of Optically Isolated Digital Input for DASP 52064 10 Hardware Installation DASP 52064 Card User s Manual 2 3 2 Digital Output Port Circuits and Wiring There are 32 digital output channels on DASP 52064 board The digital output port is sink type open collector The following figure demonstrates the circuit configuration The basic layout is presented as below QD Ineternal KP Load Circut Te a Photocopler paoe MA pourzs Load Ol GND qi Block Diagram of Internal Circuits and Wiring of Isolated Digital Output for DASP 52064 2 4 Quick setup and test To install a new DASP 52064 into an IBM PC compatible computer at first power off the PC and ope
3. Dimension of DASP 52064 and Accessories 31
4. DI 0 7 gt DO 0 7 DI 8 15 gt DO 8 15 DI 16 23 gt DO 16 23 DI 24 31 gt DO 24 31 Device Information ID amp SN oc SNOx04103001 v Offset fo DLL Version 20041011 Card DASP52064 o Enable Release owe jez Digital VO Test Digital UO Input Digital iO Outp erupt Test DIO Error Count 0 SRAM Error Count 0 160 D0 0 00000000 0 00000000 SRAM S2 W 0x 5 ROSS 161 DO OxFFFFFFFF DI OxFFFFFFFF SRAMIS2 VWOXAR ROKA 162 DO 0 55555555 DI 0 55555555 SRAMIS2 VW 0x00 R 000 163 DO OxAAAAAAAA DI OXAAAAASAA SRAM 53 VDxFF 164 DO 0 00000000 0x000001 SRAM 53 W 0x55 R 0x55 FF 0 000 FEF SRAM S3 ROWA 3555 SRAMESS W 0x0 R 0x00 Perform the DIO and SRAM Auto Test on DASP 52064 18 Hardware Installation DASP 52064 Card User s Manual e StepS8 Perform the battery backup RAM test of DASP 52064 as shown in following figure At first key in the address offset of battery backup RAM to test in the Offset field for instance writes 0x0 to test the first byte of battery backup RAM of the DASP 52064 and key in the byte value to the Write field and press the Write button to write the byte value to DASP 52064 To verify the byte value write to the specified address of battery backup RAM of DASP 52064 press the Read button of SRAM test panel of
5. Setting this register to avoid input contact bounce DBTO DBV2 Digital input bit 0 7 de bounce time DBTS DBV 10 Digital input bit 8 5 de bounce time DBT16 DBV18 Digital input bit 16 23 de bounce time DBT24 DBV26 Digital input bit 24 31 de bounce time Clock source 4MHz Registry Structure and Format 23 DASP 52064 Card User s Manual 24 Registry Structure and Format DASP 52064 Card User s Manual 3 4 Timer Value Register One programmable timer is provided by the DASP 52064 and can be served as a system interrupt source The timer resolution is 0 5 5 and the timer interval can be configured up to 2147ms To configure the timer interval of the DASP 52064 is simply achieved by writing a 32 bits timer value to its Timer Value Register as described in the following table Write Base Address Offset 0x08 32 bits timer value Timer resolution is 0 55 Timer range from 0 5us to 2147ms Registry Structure and Format 25 DASP 52064 Card User s Manual 3 5 Timer Interrupt Control Word To operate the on board timer of the DASP 52064 as an interrupt Source user can write the corresponding bit DO of its Timer Interrupt Control Register a low 0 to enable the timer interrupt the presents of a high 1 at DO of the Timer Interrupt Control Register will disable the interrupt Write Base Address Offset 0x0C wv Peo pee pee Pa Reserved EnTINT D23 022 020 pie pte
6. DASP 52064 Card User s Manual 1 1 Features 32 isolated digital inputs for source type 32 interrupt input I O digital input 32 isolated digital outputs for sink type 2K battery backup RAM for backup nonvolatile data only for DASP 52064 One programmable timer and interrupt Supports Windows 98 NT 2000 XP Labview 6 0 7 0 driver Supports VB VC BCB Delphi sample program 1 2 Specifications Isolated Digital Inputs Input channels 32 Interrupt input channel 32 Interrupt input source type I O interrupt amp timer interrupt Input type source Optical isolated 2500V Opto isolator response time 20us Over voltage protect 50V Input voltage m VIH MAX 36 Voc m VIH min 4 m VIL mox Input current m 10 2 9 6 typical m 12 3 typical 24 Voc 7 5MA typical m 36V 11 5rmA typical Introduction DASP 52064 Card User s Manual Isolated Digital Outputs Output channels 32 Output type sink open collector Optical Isolation 2500V Output voltage 10 40V Opto isolator response time 20us Battery Backup RAM DASP 52064 only m Range of base address P amp P Memory Mapped W Size 2K bytes Programmable Interval Timer Channel 1 Resolution 32 bits Time base 2MHz Timer range 0 5s 2147ms General environment Introduction I O connector type 100 pin SCSI II pin type female Power consumption Typical 5 V 300mA Max 5 V 500mA Temperat
7. 89200 2 88200 DASP 52064 CB 89200 5 Signal Connections for DASP 52064 Referring to the above figure the accessories of the DASP 52064 and their installation are depicted below and described as below e CONI The I O connector CON1 on the DASP 52064 is a 100 pin SCSI II pin type connector for digital input output signals CON1 enables you to connect to accessories the terminal block TB 88200 with the shielded 100 pin SCSI II pin type cable CB 88200 2 or CB 88200 5 6 Hardware Installation DASP 52064 Card User s Manual 2 2 2 Digital Input Output Connector of He 1 89200 88200 DIO Signal Connections for DASP 52064 The pin assignment of CON1 of DASP 52064 is listed as follows o Hardware Installation DASP 52064 Card User s Manual Desertor me en oer mo 8 Nw 2 8 Ns mo 6 se IN ma 58 ms com fe 5 icom com 16 60 icom m2 e 66 68 19 69 74 ours so ourn 8 Hardware Installation T DASP 52064 Card User s Manual Gescripion Pin Pin Description Le as 86 com Jer 87 com ours se eo oure 90 ocom 4e 99 ocom
8. DASP 52064 16 Hardware Installation DASP 52064 Card User s Manual Step 6 Perform the Interrupt Test by selecting the Interrupt Test Page in TOOLWORKSHOP At first key in the Tick value 1965535 and press Set Button to update the Timer Configuration Press the Start Button to start the timer interrupt and the ISR Count will count up The count will stop when the Stop button is pressed The Interrupt testing page is as shown below 54 IJE Yew Widow Help xl Refresh Exit Testing DASP 52084 34 f Device Information SRAM Test ID amp SN oc SN0x04103001 v Offset B DLL Version 20041011 pa Card Type DASP52064 a Enable Release Wite ozs Digital VO Test Digital WO Input Digital O Output 1O Auto Te Timer Interrupt 65535 1765535 S R 2M Tick Hz Bet Perform Interrupt Test by Set the Tick Value and Start Stop Timer Interrupt of DASP 52064 Hardware Installation 17 DASP 52064 Card User s Manual e Step7 DIO and SRAM only supported by DASP 52064 can be auto tested in this page as shown below The Error count shows the times of testing failure Press Start button to start auto testing and press Stop to stop The DIO connection must be wired as the following configuration to prevent the testing failure
9. Digital Input Registers 22 3 3 De Bounce Time Value Register 23 3 4 Timer Value Register 25 3 5 Timer Interrupt Control Word 26 3 6 I O Interrupt Edge Control Word 27 3 7 W O Interrupt Mask Control Word 28 3 8 Clear Output Control Word 29 3 9 Digital Output Register 29 3 10 O Interrupt Clear and Status Register 30 Appendix A Dimension of DASP 52064 Eu o 7 7 7 OX O 31 DASP 52064 Card User s Manual Chapter 1 Introduction The DASP 52064 is a PCl bus 32 isolated and 32 isolated D O card It offers 2K bytes on board battery backup RAM to help effectively protect important data while the system shuts down The DASP 52064 is also fitted with one programmable timer interrupt and interrupt On board Battery Backup RAM The design on board battery backup RAM supports a storage unit that data can remain stored safely without the risk of losing it and assures data security while the PC shuts down or loses power While working on it users can save important data or key parameters in advance or constantly update and save output values in RAM that lets users always obtain the latest figures or furthermore save multiple data Introduction 1
10. piz pie 5 028 027 026 025 026 Reserved EnTINT Timer Interrupt Control Bit 0 Enable e 1 Disable Default 26 Registry Structure and Format DASP 52064 Card User s Manual 3 6 I O Interrupt Edge Control Word There is an I O interrupt provided by the DASP 52064 All the 32 channels of the DASP 52064 can serve as the interrupt source signal and multiple D I channels can serve as the interrupt source signals simultaneously An OR logic is introduced to solve the interrupt status when multiple D I channels is selected to trigger the interrupt The trigger edge of I O interrupt can be assigned by writing the Interrupt Edge Control Register and the interrupt source signal can be selected by writing the mask value to the nterrupt Mask Control Register as described 3 7 To assign the interrupt edge of each channel of the DASP 52064 write the corresponding bits of the interrupt edge control register as lists in the following table A high bit 1 denotes falling edge will be detected for the D I channel otherwise the raising edge is monitoring for that channel Read Base Address Offset 0x10 br Js 4 9 pis ps 2 jw D31 030 029 028 027 26 025 024 EDGO 31 IO Interrupt Edge Control Bit I O 0 31 e 1 Falling edge e O Rising edge Default Registry Structure and Format 27 DAS
11. the Too WorkShop g Exit ol Workshop 2452 52064 Testing Refresh i Device information D 0 5 0 04103001 v DLL Version 20041011 Card DASP52064 Digital VO Test Digital VO Input Digital iO Output 0 Auto Test Interrupt Test Bit 0 7 06555555 Bit 6 15 NE SUD SUD BI 16 23 E SU SUD Bit 24 31 Perform Battery Backup RAM Test by Set the Byte Address and Byte Value to Write and Read Back the Byte Value From the Battery Backup RAM of DASP 52064 e StepO9 Before exiting Too WorkShop press Release button to release DASP 52064 library Hardware Installation 19 DASP 52064 Card User s Manual This page does not contain any information 20 Hardware Installation DASP 52064 Card User s Manual Chapter 3 Register Structure and Format 3 1 Overview DASP 52064 occupies 32 consecutive I O addresses address of each register is defined as the board s base address plus an offset The registers and their corresponding functions are listed in the followings Adres Rea J we Base 0x10 Reserved Interrupt Edge Control Base 0x14 Reserved Interrupt Mask Base 0x18 Reserved Clear Output Base 0 1 Reserved Digital Output 24 bits Base 0x20 Interrupt Clear and Status Registry Structure and For
12. 016 0023 The details of bit mapping of Digital Output Register are shown in the following Write Base Address Offset 0x1C or 52 51 pis 012 Dto pe pz2 D21 020 519 pt D17 pte Ds 629 627 p26 025 pz4 Registry Structure and Format 29 DASP 52064 Card User s Manual 310 Interrupt Clear and Status Register Read this register to read in IO interrupt status and clear interrupt Read Base Address Offset 0x20 For s oa oz ING OWNS ibiwz io ioi ws pw pra ow oro vo t pz D21 020 pss pre Fost 628 ner ozs pos pat IDINO 31 IO Interrupt Status Bit I O 0 31 e 1 Interrupt happens e 0 No Interrupt 30 Registry Structure and Format DASP 52064 Card User s Manual Appendix A Dimension of DASP 52064 and Accessories e DASP 52064 1121981905108 7 1111111111111111 Sit 1111111111111111 B XL EIC a gt F 27 Sse e 4 i BB RUM c fee uris gt UU ORS ___ S e 185 e TB 88200 50 o 87 D e M 281 I
13. Card User s Manual e Step Exit the PCI Configuration Utility and launch the ToolWorkShop for DASP 52064 Select DASP 52064 as the test target as shown below ew LTD ToolWorkshop ToolWorkshop Launch ToolWorkShop ToolWorkshop Select Board Test Hardware Installation 13 DASP 52064 Card User s Manual Device Information SRAM Test ID amp SN ID 0 SN 0x04103001 ofset 0 DLL Version 20041011 Card DASP52064 Enable Release Write Digital VO Test Digital VO Input Digital Output 10 Auto Test InterruptTest Bit 0 7 Co _ Bit8 15 16 23 Bit 24 31 Select Test Target DASP52064 14 Hardware Installation DASP 52064 Card User s Manual e Step4 Perform DIO test of DASP 52064 as shown following At first check the device information and press Enable button to load DASP 52064 library shown below TE a E Testing Refresh SRAM Test Offset fo DLL Version 20041011 vo Card DASP52064 Res Write oo Digital VO Input Digital 0 Output WO Auto Test Interrupt Test Bit 0 7 00000000 Bit8 15 EH NS Bit 16 23 EH NE Bit 24 31 EE
14. DASP 52064 Series Isolated 32 D I and 32 D O Board User s Manual Disclaimers The information in this manual has been carefully checked and is believed to be accurate Axiomtek Co Ltd assumes no responsibility for any infringements of patents or other rights of third parties which may result from its use Axiomtek assumes no responsibility for any inaccuracies that may be contained in this document Axiomtek makes no commitment to update or to keep current the information contained in this manual Axiomtek reserves the right to make improvements to this document and or product at any time and without notice No part of this document may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photocopying recording or otherwise without the prior written permission of Axiomtek Co Ltd Copyright 2004 by Axiomtek Co Ltd All rights reserved November 2004 Version A1 Printed in Taiwan ESD Precautions Integrated circuits on computer boards are sensitive to static electricity To avoid damaging chips from electrostatic discharge observe the following precautions Do not remove boards or integrated circuits from their anti static packaging until you are ready to install them Before handling a board or integrated circuit touch an unpainted portion of the system unit chassis for a few seconds This helps to discharge any static electricity on your body Wear
15. P 52064 Card User s Manual 3 7 I O Interrupt Mask Control Word All the 32 channels of the DASP 52064 can serve as the interrupt source signal and multiple D I channels can serve as the interrupt source signals simultaneously An OR logic is introduced to solve the interrupt status when multiple channels is selected to trigger the interrupt The interrupt source signal can be selected by writing the mask value to the nterrupt Mask Control Register The bit mapping of nterrupt Mask Control Register is described in the following table Read Base Address Offset 0x14 Lor os oa o2 9 pis pra prs pto vs 022 oz 020 pir 020 02 027 026 025 MSKO 31 IO Interrupt Mask Control Bit I O 0 31 e 1 Enable Unmask 0 Disable Mask Default 28 Registry Structure and Format DASP 52064 Card User s Manual 3 8 Clear Output Control Word A global clear to all of the D O channels of the DASP 52064 can be achieved by performing a write to the Clear Output Control Register Write Base Address Offset 0x18 Write Any Value to Clear All Digital Output Bits to 0 3 9 Digital Output Register The DASP 52064f I O address of them The low word DO D15 of the space latches digital output value DOO DO15 and part of the high word D16 D23 of the space latches digital output value 0
16. a wrist grounding strap available from most electronic component stores when handling boards and components Trademarks Acknowledgments AXIOMTEK is a trademark of Axiomtek Co Ltd IBM is a registered trademark of International Business Machines Corporation MS DOS and Windows 95 98 NT 2000 are trademarks of Microsoft Corporation Phoenix Award is a trademark of Phoenix Award Software Inc IBM PC AT PS 2 VGA are trademarks of International Business Machines Corporation Intel and Celeron Pentium are trademarks of Intel Corporation Other brand names and trademarks are the properties and registered brands of their respective owners Table of Contents Chapterl 1 2 1 2 Specifications issiskirti nioi 2 1 3 114 422 2 4 Chapter2 Hardware Installation 5 2 1 ce 5 2 2 Signal Connections 6 2 2 1 Signal Connection Descriptions 6 2 2 2 Digital Input Output Connector CONI 7 2 3 DI DO Circuits and Wiring 10 2 3 1 Digital Input Port Circuits and Wiring 10 2 3 2 Digital Output Port Circuits and Wiring 11 2 4 Quick setup and test 11 Chapter3 Registry Structure and Format 21 OVerVIGW 21 3 2
17. mat 21 DASP 52064 Card User s Manual 3 2 Digital Input Registers The DASP 52064 provides 32 optically isolated digital inputs A double word space is reversed start from offset 0 of I O address of them The low word DO D15 of the space latches digital input DIO DI15 the high word D16 D31 of the space latches digital input DI16 DI31 The details of bit mapping of Digital Input Register are shown in the following Read Base Address Offset 0x00 Lor os ps 52 v pis bia pts p12 pst bo Do ps D23 222 pzt 020 pts D29 nae 026 025 22 Registry Structure and Format DASP 52064 Card User s Manual 3 3 De Bounce Time Value Register Four on board anti bouncing de bounce digital filters implemented for digital input channels of the DASP 52064 8 consecutive digital input channels share an anti bouncing digital filter that can be configured independently through writing the de bounce time interval an appropriate clock divider to the De bounce Time Value Registers to count the de bounce time interval The details of bit mapping of these registers are shown in the following Write Base Address Offset 0x04 Lor os 54 pts 012 ost ps 08 528 D22 D20 bts pir pt osi ozo D28 527 pas pzs 024
18. n its chassis then plug the DASP 52064 into a PCI slot of mother board of the PC The DASP 52064 is a plug and play device for MS Windows and the OS will detect your DASP 52064 after you power on the PC The detail of driver and software installation is described in software manual of DASP 52064 After the hardware and software installation user can emulate and test DASP 52064 step by step as follows Hardware Installation 11 DASP 52064 Card User s Manual Step 1 To perform a complete test of DASP 52064 we can route the output channels to the input channels of DASP 52064 directly for read back And then by following the DASP 52064 test branch of the ToolWorkShop which will fully test all the digital I O channels of the DASP 52064 as descried in the following paragraphs Step 2 Launch the PCI Configuration Utility of DASP 52000 series to ensure that the resource of DASP 52064 is properly dispatched by the OS Press the scan button in the toolbar of the PCI Configuration Utility to find the installed DASP 52064 and then check the resource list as show below FCT Contig Vow Ute sse pep mies v Diss m ioRTR Space 0 Space 1 m ID MERLDASP S2066 0410001 02050105 000000400 000 800 04000000 08064060 Ready Dowdle Chick Highikght Module Scan DASP 52064 with PCI Configuration Utility and Check the 12 Dispatched Resource Hardware Installation DASP 52064
19. ure Operation 0 60 C Storage 20 70 C Relative humidity O to 909 o non condensing Dimensions 185mm x 122mm DASP 52064 Card User s Manual 1 3 Accessories To make the DASP 52064 functionality complete we carry a versatility of accessories for different user s requirements in the following items e Wiring Cable m CB 89200 2 100 SCSI II pin type male with 2m length m CB 89200 5 100 SCSI II pin type male with 5m length e Terminal Block m TB 88200 100 SCSI II terminal block with DIN rail mounting The terminal block is directly connected to I O connector CON1 of the DASP 52064 Introduction DASP 52064 Card User s Manual Chapter 2 Hardware Installation 2 1 Board Layout 7 1111111 safe Rafael s wu unu gran S eL 9 R3 1 23 pz lt AT Tet Se T 4 90 32 sane Soe n 2 e an 2 cb P EZ 4 Do ICE X 2 ee 2 2 REL Cae 5 e est i 12 4 gt EusdczHrzuc Men Board Layout for DASP 52064 Hardware Installation 5 DASP 52064 Card User s Manual 2 2 Signal Connections 2 2 1 Signal Connection Descriptions G cow 110 S D xac 4
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