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Z80 CPU User Manual

1. at n t n Description The low order byte in Index Register IY is loaded to memory address nn the upper order byte is loaded to memory location nn 1 The first n operand after the op code is the low order byte of nn M Cycles T States 4 MHz E T 6 20 4 4 3 3 3 3 5 00 Condition Bits Affected None Example If Index Register IY contains 4174h then upon the execution of an LD 8838h IY instruction memory location 8838h contains 74h and memory location 8839h contains 41h UMO08006 0714 Z80 Instruction Description Z80 CPU User Manual Z i Ory ILU y 110 DIXYS LD SP HL Operation SP HL Op Code LD Operands SP HL 1 1 1 r 1 0 0 1 F9 Description The contents of the register pair HL are loaded to the Stack Pointer SP M Cycles T States 4 MHz E T 1 6 1 5 Condition Bits Affected None Example If the register pair HL contains 442Eh then upon the execution of an LD SP HL instruc tion the Stack Pointer also contains 442Eh Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Z ILO U nIXYS 111 LD SP IX Operation SP IX Op Code LD Operands SP IX Description The 2 byte contents of Index Register IX are loaded to the Stack Pointer SP M Cycles T States 4 MHz E T 2 10 4 6 2 50 Condition Bits Affected None
2. Description The contents of the memory location addressed by the HL register pair is compared with the contents of the Accumulator During a compare operation a condition bit is set The HL and Byte Counter register pair BC are decremented M Cycles T States 4 MHz E T 4 16 4 4 3 5 4 00 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if A equals HL otherwise it is reset H is set if borrow from bit 4 otherwise it is reset P V is set if BC 1 x 0 otherwise it 1s reset N is set C is not affected Example If the HL register pair contains 1111h memory location 1111h contains 3Bh the Accu mulator contains 3Bh and the Byte Counter contains 0001h Upon the execution of a CPD instruction the Byte Counter contains 0000h the HL register pair contains 1110h the flag in the F Register is set and the P V flag in the F Register is reset There is no effect on the contents of the Accumulator or address 1111h UM008006 0714 Z80 Instruction Description 139 140 Z80 CPU User Manual Ar ZILOgd Operation A HL HL HL 1 BC BC 1 Op Code CPDR Operands None Description The contents of the memory location addressed by the HL register pair is compared with the contents of the Accumulator During a compare operation a condition bit is set The HL and Byte Counter BC Register
3. Description The operand n is placed on the bottom half A0 through A7 of the address bus to select the I O device at one of 256 possible ports The contents of the Accumulator also appear on the top half A8 through A15 of the address bus at this time Then one byte from the selected port is placed on the data bus and written to the Accumulator Register A in the CPU M Cycles T States 4 MHz LT 3 11 4 3 4 2 75 Condition Bits Affected None Example The Accumulator contains 23h and byte 7Bh is available at the peripheral device mapped to I O port address 01h Upon the execution of an IN A 01h instruction the Accumula tor contains 7Bh Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 293 IN r C Operation r C Op Code IN Operands r C Description The contents of Register C are placed on the bottom half A0 through A7 of the address bus to select the I O device at one of 256 possible ports The contents of Register B are placed on the top half A8 through A15 of the address bus at this time Then one byte from the selected port is placed on the data bus and written to register r in the CPU Regis ter r identifies any of the CPU registers shown in the following table which also indicates the corresponding 3 bit r field for each The flags are affected checking the input data Register r Flag 110 Undef
4. Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog BIXYS r identifies registers B C D E H L or A assembled as follows in the object code field Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description The contents of the m operand are rotated right 1 bit position The contents of bit O are copied to the Carry flag and also to bit 7 Bit O is the least significant bit Instruction M Cycles T States RRCr 2 8 4 4 RRC HL 4 15 4 4 4 3 RRC IX d 6 23 4 4 3 5 4 3 RRC IY d 6 23 4 4 3 5 4 3 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is reset P V is set if parity even otherwise it is reset N is reset C is data from bit O of source register Example Register A contains the following data 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 1 UM008006 0714 4 MHz E T 2 00 3 75 5 75 5 75 Z80 Instruction Description 223 Z80 CPU User Manual Zilog 224 BIXYS Upon the execution of an RRC A instruction Register A and the Carry flag now contain Z80 Instruction Set UM008006 07 14 RR m UM008006 0714 Operation ae Op Code RR Operand m Z80 CPU User Manual Zilog BIXYS The m operand is any of r HL IX d or 1Y d as defined for th
5. 4 n gt Description The n integer is loaded to the memory address specified by the contents of the HL register pair M Cycles T States 4 MHz E T 3 10 4 3 3 2 50 Condition Bits Affected None Example If the HL register pair contains 44 44h the instruction LD HL 28h results in the mem ory location 44 44h containing byte 28h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Z i Ory ILU y OIXYS LD IX d n Operation IX4d n Op Code LD Operands IX d n a d gt ra n Description The n operand is loaded to the memory address specified by the sum of Index Register IX and the two s complement displacement operand d M Cycles T States 4 MHz E T 5 19 4 4 3 5 3 4 75 Condition Bits Affected None Example If Index Register IX contains the number 219Ah then upon execution of an LD X4 5n 5Ah instruction byte 5Ah is contained in memory address 219Fh Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 85 LD IY d n Operation IY d n Op Code LD Operands IY d n a d gt ra n Description The n integer is loaded to the memory location specified by the contents of Index Register summed with the two s complement displacement integer d M Cycles T States 4 MHz E T 5 19 4 4 3 5 3 2 50
6. Pin Functions 6 Z80 CPU User Manual ZlIlog BIXYS RD and WR have entered their high impedance states The external circuitry can now control these lines BUSREQ Bus Request input active Low Bus Request contains a higher priority than NMI and is always recognized at the end of the current machine cycle BUSREQ forces the CPU address bus data bus and control signals MREQ IORQ RD and WR to enter a high impedance state so that other devices can control these lines BUSREQ is normally wired OR and requires an external pull up for these applications Extended BUSREQ peri ods due to extensive DMA operations can prevent the CPU from properly refreshing dynamic RAM D7 DO Data Bus input output active High tristate D7 DO constitute an 8 bit bidirec tional data bus used for data exchanges with memory and I O HALT HALT State output active Low HALT indicates that the CPU has executed a HALT instruction and is waiting for either a nonmaskable or a maskable interrupt with the mask enabled before operation can resume During HALT the CPU executes NOPs to maintain memory refreshes INT nterrupt Request input active Low An Interrupt Request is generated by I O devices The CPU honors a request at the end of the current instruction if the internal soft ware controlled interrupt enable flip flop IFF is enabled INT is normally wired OR and requires an external pull up for these applications IORQ
7. cece eee eee eee 2 Z80 CPU I O Pin Configuration 00 eee 5 Basic CPU Timing Example 0 0 0 0 cece cece eee ee 8 Instruction Op Code Fetch 0 0 0 cee cece eee 9 Memory Read or Write Cycle 10 Input or Output Cycles 0 eect eee 11 Bus Request Acknowledge Cycle 0 2c cee eee eee eee ee 12 Interrupt Request Acknowledge Cycle 0 0 0 eee ee eee 13 Nonmaskable Interrupt Request Operation 000 14 HALT Exif data teer de Sk Se ee he Dee 15 Power Down Acknowledge llle 15 Power Down Release Cycle 1 013 lessen 16 Power Down Release Cycle 2 of 3 1 eee eee eee eee 16 Power Down Release Cycle 3 of 3 2 eee eee eee 17 Interrupt Enable Flip Flops 0 0 0 0 cece eee 17 Mode 2 Interrupt Response Mode 0 00 c eee eee ee eee 20 Minimum Z80 Computer System 0 0 0 eee eee eee ee 21 ROM and RAM Implementation 0 0 00 e eee eee eee 22 RAM Memory Space Organization 0 00 cece eee eee 23 Adding One Wait State to an MI Cycle 0 0 0 0 0000 24 Adding One Wait State to Any Memory Cycle 04 24 Interfacing Dynamic RAM Memory Spaces 0 005 25 Shifting of BCD Digits Bytes eese 28 Immediate Addressing Mode 0 0 c eee cence eee 34 Immediate Extended Addressing Mode 0000 cece eee 34 Modified Page Zero Addre
8. Example If the HL register pair contains 999 9h register pair DE contains 1111h and the Carry flag is set then upon the execution of an SBC HL DE instruction HL contains 8887h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual zilog ILU hos 192 nIXYS ADD IX pp Operation IX IX pp Op Code ADD Operands IX pp Description The contents of register pair pp any of register pairs BC DE IX or SP are added to the contents of Index Register IX and the results are stored in IX In the assembled object code operand pp is specified as follows Register Pair ss BC 00 DE 01 IX 10 SP 11 M Cycles T States 4 MHz E T 4 15 4 4 4 3 3 75 Condition Bits Affected S is not affected Z is not affected H is set if carry from bit 11 otherwise it is reset P V is not affected Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 193 N is reset C is set if carry from bit 15 otherwise it is reset Example If Index Register IX contains 333h and register pair BC contains 5555h then upon the execution of an ADD IX BC instruction IX contains 8888h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Z T On ILU y 194 nIXYS ADD IY rr Operation IY IY rr Op Code ADD Operands IY rr Description The contents of register pair rr any of register
9. J M The following 8 bit arithmetic group instructions are each described in this section Sim ply click to jump to an instruction s description to learn more ADD A r see page 143 ADD A n see page 145 ADD A HL see page 146 ADD A IX d see page 147 ADD A IY d see page 148 ADC A s see page 149 SUB s see page 151 SBC A s see page 153 AND s see page 155 OR s see page 157 XOR s see page 159 CP s see page 161 INC r see page 163 INC HL see page 165 INC 1X d see page 166 INC 1Y d see page 167 DEC m see page 168 Z80 Instruction Set UM008006 0714 Z80 CPU User Manual Zilog nIXYS 143 ADDA r Operation A A r Op Code ADD Operands A r Description The contents of register r are added to the contents of the Accumulator and the result is stored in the Accumulator The r symbol identifies the registers A B C D E H or L assembled as follows in the object code Register r A 111 000 001 010 011 100 101 r Imoo o w M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is set if carry from bit 3 otherwise it is reset UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 144 BIXYS P V is set if overflow otherwise it
10. Operands None Description This instruction is used at the end of a maskable interrupt service routine to Restore the contents of the Program Counter analogous to the RET instruction e Signal an I O device that the interrupt routine is completed The RETI instruction also facilitates the nesting of interrupts allowing higher priority devices to temporarily suspend service of lower priority service routines However this instruction does not enable interrupts that were disabled when the interrupt routine was entered Before doing the RETI instruction the enable interrupt instruction EI should be executed to allow recognition of interrupts after completion of the current service routine M Cycles T States 4 MHz E T 4 14 4 4 3 3 3 50 Condition Bits Affected None Example Assume that there are two interrupting devices A and B connected in a daisy chain con figuration with A having a higher priority than B UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOg 286 DIXYS Comp A B agb Eo IEI IEO N e B generates an interrupt and is acknowledged The interrupt enable out IEO of B goes Low blocking any lower priority devices from interrupting while B is being serviced Then A generates an interrupt suspending service of B The IEO of A goes Low indicat ing that a higher priority device is being serviced The A routine is completed and a RETI is issued
11. Upon the execution of an SRL B instruction Register B and the Carry flag now contain 7 6 5 4 3 2 1 0 C o 1 o o o 1 1 1 t UM008006 0714 Z80 Instruction Description 236 Z80 CPU User Manual Z T On ILU y OIXYS RLD Operation A 7 4 3 0 7 413 0 XUL Op Code RLD Operands Description The contents of the low order four bits bits 3 2 1 and 0 of the memory location HL are copied to the high order four bits 7 6 5 and 4 of that same memory location the previous contents of those high order four bits are copied to the low order four bits of the Accumulator Register A and the previous contents of the low order four bits of the Accumulator are copied to the low order four bits of memory location HL The contents of the high order bits of the Accumulator are unaffected gt Note HL refers to the memory location specified by the contents of the HL register pair M Cycles T States 4 MHz E T 5 18 4 4 3 4 3 4 50 Condition Bits Affected S is set if the Accumulator is negative after an operation otherwise it is reset Z is set if the Accumulator is 0 after an operation otherwise it is reset H is reset Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 237 P V is set if the parity of the Accumulator is even after an operation otherwise it is reset N is r
12. 110 Sign Positive P 111 Sign Negative M If cc is true M Cycles T States 5 17 4 3 4 3 3 If cc is false M Cycles T States 3 10 4 3 3 Condition Bits Affected None Example Z80 CPU User Manual Zilog nIXYS 281 Relevant Flag Z Z C Z PN PN S S 4 MHz E T 4 25 4 MHz E T 2 50 The C Flag in the F Register is reset the Program Counter contains 1A47h the Stack Pointer contains 3002h and memory locations contain the following data Location Contents 1A47h D4h 1448h 35h 1A49h 21h If an instruction fetch sequence begins the 3 byte instruction D43521h is fetched to the CPU for execution The mnemonic equivalent of this instruction is CALL NC 2135h Upon the execution of this instruction memory address 3001h contains 1Ah address 3000h contains 4Ah the Stack Pointer contains 3000h and the Program Counter contains 2135h thereby pointing to the address of the first op code of the next subroutine to be executed UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOQd 282 nIXYS Operation pCL sp pCH sp 1 Op Code RET Operands None Description The byte at the memory location specified by the contents of the Stack Pointer SP Regis ter pair is moved to the low order eight bits of the Program Counter PC The SP is now incremented and the byte at the memory location specified by the new contents of this in
13. 9F 98 99 9A 98 90 90 9E d d 9E 9E DD FD C8 C8 C8 C8 C6 C8 C8 C8 C8 C8 A7 AO Al A2 A3 A4 A5 A6 d d A6 A6 DD FD 5 C8 C8 C8 C8 08 C8 C8 C8 C8 C8 AF A8 A9 AA AB AC AD AE d d AE AE DD FD 6 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 B7 BO B1 82 B3 B4 B5 B6 d d B6 B6 780 CPU Instructions UM008006 0714 Z80 CPU User Manual Zilog BIXYS Table 13 Bit Manipulation Group Continued Register Register Addressing Indirect Indexed Rest Bit DD DD ond i cs cs cs ca cs cs C8 C8 C8 C8 BF B8 89 8A B8 8C BD 9E d d BE BE Set Bit DD FD BET C8 C8 cs cs ca cs C8 C8 C8 C8 C7 CO C1 C2 C3 C4 C5 C6 d d C6 C6 DD FD 1 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 CF C8 C9 CA C8 CC CD CE d d CE CE DD FD 2 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 D7 DO D1 D2 D3 D4 DS D6 d d D6 D6 DD FD 3 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 DF D8 09 DA DS DC DD DE d d DE DE DD FD 4 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 E7 EO E1 E2 E3 E4 E5 E6 d d E6 E6 DD FD 5 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 EF E8 E9 EA EB EC ED EE d d EE EE DD FD 6 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 F7 FO F1 F2 F3 F4 FS F6 d d F6 F6 DD FD 7 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 FF F8 F9 FA FB FC FD FE d d FE FE UM008006 0714 Bit Manipulation 55 56 Z80 CPU User Manual ZILOg BIXYS Register addressing can
14. A Store in output buffer CP ODH Is it a CR JR Z DONE Yes finished INC HL Increment pointers INC DE DJNZ LOOP Loop back if 80 bytes have not been moved DONE E Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZItog nIXYS 277 Call and Return Group The following call and return group instructions are each described in this section Simply click to jump to an instruction s description to learn more CALL nn see page 278 CALL cc nn see page 280 RET see page 282 RET cc see page 283 RETI see page 285 RETN see page 287 RST p see page 289 UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOQd 278 nIXYS CALL nn Operation SP 1 PCH SP 2 PCL PC nn Op Code CALL Operand nn The first of the two n operands in the assembled object code above is the least significant byte of a 2 byte memory address Description The current contents of the Program Counter PC are pushed onto the top of the external memory stack The operands nn are then loaded to the PC to point to the address in mem ory at which the first op code of a subroutine is to be fetched At the end of the subroutine a RETur instruction can be used to return to the original program flow by popping the top of the stack back to the PC The push is accomplished by first decrementing the current contents of the
15. Condition Bits Affected None Example If Index Register IY contains the number A940h the instruction LD IY 10h 97h results in byte 97n in memory location A950h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Z n1 ILU hos BDIXYS LD A BC Operation A BC Op Code LD Operands A BC 0 0 0 0 1 01 0 OA Description The contents of the memory location specified by the contents of the BC register pair are loaded to the Accumulator M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Example If the BC register pair contains the number 4747h and memory address 4747h contains byte 12h then the instruction LD A BC results in byte 12h in Register A Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 87 LD A DE Operation A DE Op Code LD Operands A DE 0 0 0 1 1 0 1 0 1A Description The contents of the memory location specified by the register pair DE are loaded to the Accumulator M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Example If the DE register pair contains the number 30A2h and memory address 30A2h contains byte 22h then the instruction LD A DE results in byte 22h in Register A UM008006 0714 Z80 Instruction Description 88 Z80 CPU User Manual zilo BIXYS ry M
16. Operands cc nn The first n operand in this assembled object code is the low order byte of a 2 byte memory address Description If condition cc is true the instruction loads operand nn to register pair Program Counter PC and the program continues with the instruction beginning at address nn If condition cc is false the Program Counter is incremented as usual and the program continues with the next sequential instruction Condition cc is programmed as one of eight statuses that correspond to condition bits in the Flag Register Register F These eight statuses are defined in the following table which specifies the corresponding cc bit fields in the assembled object code Relevant cc Condition Flag 000 Non Zero NZ Z 001 Zero Z Z 010 No Carry NC C 011 Carry C C 100 Parity Odd PO PN 101 Parity Even PE P V 110 Sign Positive P S 111 Sign Negative M S Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual zilog OLXYs 261 M Cycles T States 4 MHz E T 3 10 4 3 3 2 50 Condition Bits Affected None Example If the Carry flag 1 e the C flag in F Register is set and address 1520h contains 03h then upon the execution of a JP C 1520h instruction the Program Counter contains 1520h and on the next machine cycle the CPD fetches byte 03h from address 1520h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOQd 262 nIX
17. ZIlog Table 19 Miscellaneous CPU Control NOP 00 HALT 76 Disable INT El F3 Enable INT El FB Set INT Mode 0 ED IMO 46 Set INT Mode 1 ED IM1 56 Set INT Mode 2 ED IM2 5E 8080A mode Call to address 0038h Indirect call using Register and B bits from INTER device as a pointer If Mode 0 is set the interrupting device can insert any instruction on the data bus and allow the CPU to execute it Mode 1 is a simplified mode in which the CPU automatically executes a restart RST at address 0038h so that no external hardware is required the old Program Counter content is pushed onto the stack Mode 2 is the most powerful because it allows for an indirect call to any location in memory With this mode the CPU forms a 16 bit memory address in which the upper eight bits are the contents of Register I and the lower eight bits are supplied by the interrupting device This address points to the first of two sequential bytes in a table in which the address of the service routine is located as shown in Figure 41 The CPU automatically obtains the starting address and performs a CALL instruction to this address Address of Interrupt Service Routine Z80 CPU Instructions Pointer to Interrupt Table Register is Upper Address Peripheral Supplies Lower Address Figure 41 Mode 2 Interrupt Command UM008006 0714 Z80 CPU User Manual ZzIlog nIXYS 63 Z80 Instruction Set
18. 234 nIXYS SRL m Operation 09 7 0 CY m Op Code SRL Operand n The operand m is any of r HL IX d or 1Y d as defined for the analogous RLC instructions In the assembled object code the possible op code operand combinations are specified as follows SRL r 1 1 0 0 1 0 1 1 CB SRL HL 1 1 0 0 17 0 1 41 CB SRL IX d 1 1 0 1 1 1 0 1 DD SRL IY d 1 1 1 1 1 1 0 1 FD Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZzIlog nDIXYS 235 r identifies registers B C D E H L or A Description The contents of operand m are shifted right 1 bit position The contents of bit 0 are copied to the Carry flag and bit 7 is reset Bit O is the least significant bit Instruction M Cycles T States 4 MHz E T SRL r 2 8 4 4 2 00 SRL HL 4 15 4 4 4 3 3 75 SRL IX d 6 23 4 4 3 5 4 3 5 75 SRL IY d 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected S is reset Z is set if result is 0 otherwise it is reset H is reset P V is set if parity is even otherwise it is reset N is reset C is data from bit 0 of source register Example Register B contains the following data 7 6 5 4 8 2 1 0 1 0 00 1 1 1 1
19. 4 2 00 15 4 4 4 3 3 75 23 4 4 3 5 4 3 5 75 23 4 4 3 5 4 3 5 75 Upon the execution of a RES 6 D instruction bit 6 in register 0 is reset Bit O in the D Register is the least significant bit UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 258 nIXYS Jump Group The following jump group instructions are each described in this section Simply click to jump to an instruction s description to learn more JP nn see page 259 JP cc nn see page 260 JR e see page 262 JR C e see page 264 JR NC e see page 266 JR Z e see page 268 JR NZ e see page 270 JP HL see page 272 JP IX see page 273 JP IY see page 274 DJNZ e see page 275 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog OIXYS 259 JP nn Operation PC nn Op Code JP Operand nn gt Note The first operand in this assembled object code is the low order byte of a two byte address Description Operand nn is loaded to register pair Program Counter PC The next instruction is fetched from the location designated by the new contents of the PC M Cycles T States 4 MHz E T 3 10 4 3 3 2 50 Condition Bits Affected None UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 260 nIXYS JP cc nn Operation IF cc true PC nn Op Code JP
20. 4K x 8 RAM Array Page 0 0000 to OFFFF Figure 23 Interfacing Dynamic RAM Memory Spaces UMO008006 0714 Interfacing Dynamic Memories Z80 CPU User Manual ZIlog 26 nIXYS Software Implementation Examples The Z80 instruction set provides the user with a large number of operations to control the Z80 CPU The main alternate and index registers can hold arithmetic and logical opera tions form memory addresses or act as fast access storage for frequently used data Information can be moved directly from register to register memory to memory memory to registers or from registers to memory In addition register contents and register mem ory contents can be exchanged without using temporary storage In particular the contents of main and alternate registers can be completely exchanged by executing only two instructions EX and EXX This register exchange procedure can be used to separate the set of working registers from different logical procedures or to expand the set of available registers in a single procedure Storage and retrieval of data between pairs of registers and memory can be controlled on a last in first out basis through PUSH and POP instructions that utilize a special Stack Pointer SP Register This stack register is available both to manipulate data and to auto matically store and retrieve addresses for subroutine linkage When a subroutine is called for example the address following the CALL instruction is pl
21. 4s 4 amp a ab fre PD UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 162 BIXYS Comp r identifies registers B C D E H L or A specified in the assembled object code field as follows Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description The contents of the s operand are compared with the contents of the Accumulator If there is a true compare the Z flag is set The execution of this instruction does not affect the contents of the Accumulator Instruction M Cycles T States 4 MHz E T CPr 1 4 1 00 CPn 2 7 4 3 1 75 CP HL 2 7 4 3 1 75 CP IX d 5 19 4 4 3 5 3 4 75 CP IY d 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is set if borrow from bit 4 otherwise it is reset P V is set if overflow otherwise it is reset N is set C is set if borrow otherwise it is reset Example If the Accumulator contains 63h the HL register pair contains 6000h and memory loca tion 6000h contains 60h the instruction CP HL results in the PN flag in the F Register resetting Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZzIlog nIXYS 163 INC r Operation re r 4l Op Code INC Operand r Description Register r is incremented and registe
22. As an example the AND 07h instruction is shown in Figure 38 Address A E6 Op Code A 1 07 Operand Figure 38 Example of an AND Instruction Sequence Assuming that the Accumulator contains the value F3h the result of 03h is placed in the Accumulator Accumulator before operation 1111 0011 F3h Operand 0000 0111 2 07h Result to Accumulator 0000 0011 2 03h The Add ADD instruction performs a binary add between the data in the source location and the data in the Accumulator The Subtract SUB instruction performs a binary sub traction When an Add with Carry ADC or Subtract with Carry SBC instruction is specified the Carry flag is also added or subtracted respectively The flags and the Deci mal Adjust DAA instruction in the Z80 CPU allow arithmetic operations for processing the following items e Multiprecision packed BCD numbers e Multiprecision signed or unsigned binary numbers e Multiprecision two s complement signed numbers Other instructions in this group are the Logical And AND Logical Or OR Exclusive Or XOR and Compare CP instructions Five general purpose arithmetic instructions operate on the Accumulator or Carry flag These five instructions are listed in Table 11 Table 11 General Purpose AF Operation Decimal Adjust Accumulator DAA 27 Complement Accumulator CPL 2F Negate Accumulator NEG ED two s complement 44 Complement Carry Flag CCF 3F Set Carry Fla
23. Destination A BIcipDIEI F L HL IX d IY d n DD FD m ADD 87 80 81 82 83 84 85 88 86 86 d d DD FD Add with Carry er 88 89 8A 8B 8C 8D 8E 8E 8E CE ADC n d d DD FD SUBE 97 90 91 92 93 94 95 96 96 96 pe SUB n d d DD FD Subtract with Carry oF 98 99 9A 9B 9C 9D 9E 9E 9E BE SBC n d d DD FD AND A7 AO A1 A2 A3 A4 AS A6 AG A6 d d DD FD EE XOR AF A8 A9 AA AB AC AD AE AE AE I d d DD FD ES OR B7 BO B1 B2 B3 B4 B5 B6 B6 B6 d d E DD FD EE ompare BF B8 B9 BA BB BC BD BE BE BE CP n d d Increment DD FD 3C 04 0C 14 1C 24 2C 34 34 34 INC d d Decrement 20 da 3D 05 oD 15 1D 25 2D 35 35 35 DEC A d Note Descriptions of the 8 Bit Arithmetic Group instructions begin on page 142 The result of the operation is placed in the Accumulator with the exception of the compare CP instruction which leaves the Accumulator unchanged All of these operations effect the Flag Register as a result of a specified operation 780 CPU Instructions UM008006 0714 Z80 CPU User Manual Zilog nIXYS 49 The INC and DEC instructions specify a register or a memory location as both the source and the destination of the result When the source operand is addressed using the index registers the displacement must directly follow With immediate addressing the actual operand directly follows
24. Mode 2 Interrupt Response Mode Register Seven Bits From Contents Peripheral The first byte in the table is the least significant low order portion of the address The programmer must complete the table with the correct addresses before any interrupts are accepted The programmer can change the table by storing it in read write memory which also allows individual peripherals to be serviced by different service routines When the interrupting device supplies the lower portion of the pointer the CPU automati cally pushes the program counter onto the stack obtains the starting address from the table and performs a jump to this address This mode of response requires 19 clock peri ods to complete seven to fetch the lower eight bits from the interrupting device six to save the program counter and six to obtain the jump address The Z80 peripheral devices include a daisy chain priority interrupt structure that automat ically supplies the programmed vector to the CPU during interrupt acknowledge Refer to the Z80 CPU Peripherals User Manual UM0081 for more complete information Architectural Overview UM008006 0714 Z80 CPU User Manual Z j ry ry AAA nIXYS 21 Hardware and Software Implementation This chapter is an introduction to implementing systems that use the Z80 CPU Figure 18 shows a simple Z80 system 5V Power Supply LK 5V GND Ag Ap Output Data Input Data Figure 18 Minimum Z80
25. ZIlOg nIXYS 31 The program outlined in Table 3 multiplies two unsigned 16 bit integers leaving the result in the HL register pair Table 3 Multiply Listing Object Location Code Statement Source Statement 0000 1 mult unsigned sixteen bit integer multiply 2 on entrance multiplier in de 3 i multiplicand in hl 4 5 on exit result in hl 6 7 register uses 8 9 10 h high order partial result 11 low order partial result 12 d high order multiplicand 13 e low order multiplicand 14 b counter for number of shifts 15 C high order bits of multiplier 16 a low order bits of multiplier 17 0000 0610 18 ld b 16 number of bits initialize 0002 4a 19 Id c d move multiplier 0003 7b 20 Id a 0004 eb 21 ex de hl move multiplicand 0005 210000 22 ld hl 0 clear partial result 0008 cb39 23 mloop srl C shift multiplier right 000a if 24 rra least significant bit is 25 in carry 000b 3001 26 jr nc if no carry skip the add noadd good 19 27 add hl de else add multiplicand to 28 partial result 000e eb 29 noadd ex de h shift multiplicand left goof 29 30 add hl hl by multiplying it by two 0010 eb 31 ex de hl 0011 10f5 32 djnz mloop repeat until no more bits 0013 c9 33 ret 34 end UM008006 0714 Programming Task Examples 32 Z80 CPU User Manual ZlIlog BIXYS Z80 CPU Instructions The Z80 CPU can execute 158 differen
26. address contains byte 39h the instruction results in Register B also containing 39h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg OLXYs 77 LD HL r Operation HL r Op Code LD Operands HL r Description The contents of register r are loaded to the memory location specified by the contents of the HL register pair The r symbol identifies registers A B C D E H or L assembled as follows in the object code Register r A 111 B 000 C 001 D 010 E 011 H 100 L 101 M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOg 78 nIXYS Example If the contents of register pair HL specify memory location 2146h and Register B contains byte 29h then upon the execution of an LD HL B instruction memory address 2146h also contains 29h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 79 LD IX d r Operation IX4d r Op Code LD Operands IX d r Description The contents of register r are loaded to the memory address specified by the contents of Index Register IX summed with d a two s complement displacement integer The r sym bol identifies registers A B C D E H or L assembled as follows in the object code Register r A 111 B 000 C 001 D 010
27. it is reset N is reset UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 216 DIXYS Comp C is data from bit 7 of source register Example Index Register IX contains 1000h and memory location 1022h contains the following data 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 0 Upon the execution of an RLC X 2h instruction memory location 1002h and the Carry flag now contain C 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 0 1 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZIlOg nIXYS 217 RLC IY d Operation CY x 7 lt 0 a IY d Op Code RLC Operand 1Y d Description The contents of the memory address specified by the sum of the contents of Index Register IY and the two s complement displacement integer d are rotated left 1 bit position The contents of bit 7 are copied to the Carry flag and also to bit 0 Bit O is the least significant bit M Cycles T States 4 MHz E T 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is reset P V is set if parity even otherwise it is reset N is reset UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 218 DIXYS Comp C is data from bit 7 of source re
28. stack implementation Figure 19 shows how 256 bytes of static memory are added to the example shown in Figure 18 Address Bus Data Bus Figure 19 ROM and RAM Implementation The memory space is assumed to be organized as shown in Figure 20 Hardware and Software Implementation UMO008006 0714 Z80 CPU User Manual Zilog oLxys 23 Address 0000h 1 Kbyte ROM O3FFh 0400h 256 Bytes RAM 04FFFh Figure 20 RAM Memory Space Organization In Figure 20 the address space is portrayed in hexadecimal notation Address bit A10 sep arates the ROM space from the RAM space allowing this address to be used for the chip select function For larger amounts of external ROM or RAM a simple TTL decoder is required to form the chip selects Memory Speed Control Slow memories can reduce costs for many applications The WAIT line on the CPU allows the Z80 to operate with any speed memory Memory access time requirements which are covered in the Memory Read Or Write section on page 9 are most severe during the MI cycle instruction fetch All other memory access cycles complete in an additional one half clock cycle Hence it is sometimes appropriate to add one wait state to the M1 cycle so slower memories can be used Figure 21 is an example of a simple circuit that accomplishes this objective This circuit can be changed to add a single wait state to any memory access as indicated in Figure 22 UM008006 0714 Memory Speed
29. 13 Bit Manipulation Group Register Register Addressing Indirect Indexed A 8 C D E H L HL IX d IY d Bit DD FD Test Bit C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 47 40 41 42 43 44 45 46 d d 46 46 DD FD 1 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 4F 48 49 4A 48 4C 4D 4E d d 4E 4E DD FD 2 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 57 50 51 52 53 54 55 56 d d 56 56 DD FD 3 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 5F 58 59 5A 5B 5C 5D 5E d d 46 46 DD FD 4 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 67 60 61 62 63 64 65 66 d d 66 66 DD FD 5 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 6F 68 69 6A 68 6C 6D 6E d d 6E 6E UM008006 0714 Bit Manipulation Z80 CPU User Manual ZILOg 54 BIXYS Table 13 Bit Manipulation Group Continued Register Register Addressing Indirect Indexed Test Bit DD FD jeont d R C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 77 70 71 72 73 74 75 76 d d 76 76 DD DD 7 C8 C8 C8 C8 C8 C8 CS C8 C8 C8 7F 78 79 7A 78 7C 7D 7E d d 46 46 Rest Bit DD FD RES o C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 87 80 81 82 83 84 85 86 d d 86 86 DD FD 1 C8 C8 C8 C8 C8 C8 C8 C8 C8 C8 8F 88 89 8A 88 8C 8D 8E d d 8E 8E DD FD 2 C8 C8 CS C8 C8 C8 C8 C8 C8 C8 97 90 91 92 93 94 95 96 d d 96 96 DD FD 3 C8 C8 C8 C8 CS C8 C8 C8 C8 C8
30. Control Z80 CPU User Manual Z id Mn L NN MJ 24 OLXYS WAIT 5V A gt T Te Tw Ta Ta S S CLK ALLE PAU PE 7474 7474 MAI CK c E o Mi J R R am 3 WAIT 45V 45V WAIT 5V 7400 0 CLK S S MREQ D Q D Q MREQ CLK 7474 7474 LP C Q C Q WAIT R R 5V 5V Figure 22 Adding One Wait State to Any Memory Cycle Hardware and Software Implementation UMO008006 0714 Z80 CPU User Manual ZILOg nIXYS 25 Interfacing Dynamic Memories Each individual dynamic RAM space includes its own specifications that require minor modifications to the examples provided here Figure 23 shows the logic necessary to interface 8KB of dynamic RAM using 18 pin 4K dynamic memories This logic assumes that the RAMs are the only memory in the system so that A12 is used to select between the two pages of memory During refresh time all memories in the system must be read The CPU provides the correct refresh address on lines AO through A6 When adding more memory to the system it is necessary to replace only the two gates that operate on A12 with a decoder that operates on all required address bits Address buffers and data bus buffers are generally required for larger systems RFSH MREQ A11 A0 i 4K x 8 RAM Array R W Page 1 Pir Data Bus 1000 to 1FFFF
31. DE 01 HL 10 AF 11 M Cycles T States 4 MHz E T 3 11 5 3 3 2 75 Condition Bits Affected None UM008006 0714 Z80 Instruction Description 113 Z80 CPU User Manual Zilog 114 pnixyscomo Example If the AF Register pair contains 2233h and the Stack Pointer contains 1007h then upon the execution of a PUSH AF instruction memory address 1006h contains 22h memory address 1005h contains 33h and the Stack Pointer contains 1005h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 115 PUSH IX Operation SP 2 IXL SP 1 IXH Op Code PUSH Operand IX Description The contents of Index Register IX are pushed to the external memory last in first out LIFO stack The Stack Pointer SP Register pair holds the 16 bit address of the current top of the Stack This instruction first decrements SP and loads the high order byte of IX to the memory address specified by SP then decrements SP again and loads the low order byte to the memory location corresponding to this new address in SP M Cycles T States 4 MHz E T 4 15 4 5 3 3 3 75 Condition Bits Affected None Example If Index Register IX contains 2233h and the Stack Pointer contains 1007h then upon the execution of a PUSH X instruction memory address 1006h contains 22h memory address 1005h contains 33h and the Stack Pointer contains 1005h UM008006 0714 Z80 Instruction
32. DEC DB 1B 2B 3B 2B 2B Note Descriptions of the 16 Bit Arithmetic Group instructions begin on page 185 Z80 CPU Instructions UM008006 0714 Z80 CPU User Manual fy fy Z O y BIXYS 51 Rotate and Shift UM008006 0714 A major feature of the Z80 CPU is to rotate or shift data in the Accumulator any general purpose register or any memory location All of the Rotate and Shift op codes are depicted in Figure 39 Also included in the Z80 CPU are arithmetic and logical shift oper ations These operations are useful in a wide range of applications including integer multi plication and division Two BCD digit rotate instructions RRD and RLD allow a digit in the Accumulator to be rotated with the two digits in a memory location pointed to by reg ister pair HL These instructions allow for efficient BCD arithmetic Rotate and Shift 52 Z80 CPU User Manual fry ry Z ILUO Vj BDIXYS Source Type of Rotate Shift A B C D E FJ L HL IX d IV d A DD FD CY b a bo pol CB CB CB CB CB CB CB CB CB CB RCL 07 00 01 02 03 04 106 OE d a HLCA 07 ue 06 06 RR gt Right Circular DD FD CB CB CB CB CB CB CB CB CB CB Rotate RRC oE
33. DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION DEVICES OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE The information contained within this document has been verified according to the general principles of electrical and mechanical engineering Z80 Z180 Z380 and Z80382 are trademarks or registered trademarks of Zilog Inc All other product or service names are the property of their respective owners UM008006 0714 Z80 CPU User Manual Zilog OIXYS Hi Revision History Each instance in the following revision history table reflects a change to this document from its previous version For more details refer to the corresponding pages provided in the table Revision Date Level Description Page Jul 06 Updated to Zilog style and to incorporate customer suggestions including a 63 124 2014 correction to the Z80 Status Indicator Flags table bit 4 and a correction to the EXX instruction at bit 0 Feb 05 Corrected the hex code for the RLCA instruction corrected illustration for 53 203 2005 the Rotate and Shift Group RLCA instruction Dec 04 Corrected discrepancies in the bit patterns for IM 0 IM 1 and IM 2 182 183 2004 instructions 184 UM008006 0714 Revision History Z80 CPU User Manual Zilog IV OIXYS Revision History UM008006 0714 Z80 CPU User Manual zilog DIXYS Table of Contents Revision HISlOLY ies eaters V bc le ob di a aida 111 Li
34. E 011 H 100 L 101 M Cycles T States 4 MHz E T 5 19 4 4 3 5 3 4 75 Condition Bits Affected None UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 80 BIXYS Example If the C register contains byte 1Ch and Index Register IX contains 3100h then the instruction LID IX 6h C performs the sum 3100h 6h and loads 1Ch to memory location 3106h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZIlOg nIXYS 81 LD IY d r Operation IY4d r Op Code LD Operands IY d r Description The contents of resister r are loaded to the memory address specified by the sum of the contents of Index Register IY and d a two s complement displacement integer The r sym bol is specified according to the following table Register r A 111 B 000 C 001 D 010 E 011 H 100 L 101 M Cycles T States 4 MHz E T 5 19 4 4 3 5 3 4 75 Condition Bits Affected None UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 82 nIXYS Example If the C register contains byte 48h and Index Register IY contains 2A11h then the instruction LD Y 4h C performs the sum 2A11h 4h and loads 48h to memory location 2A15 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZIlOg nIXYS 83 LD HL n Operation HL n Op Code LD Operands HL n
35. ED Destination 60 ED 68 INI input amp ED inc HL Dec B A2 INIR INP Inc HL ED Dec B repeat if B40 Register HL B2 ad npu IND input amp Inc Indir ED nds Dec HL Dec B AA INDR input Dec HL ED Dec B repeat if B40 BA Z80 CPU Instructions UM008006 0714 Table 18 8 Bit Arithmetic and Logic Z80 CPU User Manual ZILOg OIXYS Source Register Register Indirect A B C D E H L HL Immediate n 110UT ED ED ED ED ED ED ED 79 41 49 51 59 61 69 110UT output ED Block inc HL dec B A3 Output 110UT output Register ED Command dec B repeat if B40 Indirect c B3 110UT output ED dec HL and B AB 11OUTDR output dec ED HL and B repeat if BB B40 Port Destination Address gt Note Descriptions of the Input and Output Group instructions begin on page 291 CPU Control Group Table 19 shows the six general purpose CPU control instructions The HALT instruction suspends CPU operation until a subsequent interrupt is received while the DI and EI are used to lock out and enable interrupts The three interrupt mode commands set the CPU to any of the three available interrupt response modes each of these is described in the next paragraph The NOP instruction has no function UM008006 0714 CPU Control Group 61 Z80 CPU User Manual ra
36. FD CB 2E Z80 Instruction Description 231 Z80 CPU User Manual Zilog 232 DIXYS r identifies registers B C D E H L or A assembled as follows in the object code field Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description An arithmetic shift right 1 bit position is performed on the contents of operand m The contents of bit O are copied to the Carry flag and the previous contents of bit 7 remain unchanged Bit 0 is the least significant bit Instruction M Cycles T States 4 MHz E T SRAr 2 8 4 4 2 00 SRA HL 4 15 4 4 4 3 3 75 SRA IX d 6 23 4 4 3 5 4 3 5 75 SRA IY d 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is reset P V is set if parity is even otherwise it is reset N is reset C is data from bit 0 of source register Example Index Register IX contains 1000h and memory location 1003h contains the following data 7 6 5 4 3 2 1 0 1 Oj 1 1 1 0 0 0 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual zilog BIXYS Upon the execution of an SRA X 3h instruction memory location 1003h and the Carry flag now contain 7 6 5 4 3 2 1 1 1 0 1 1 1 0 UM008006 0714 Z80 Instruction Description 233 Z80 CPU User Manual ZILOg
37. IM 2 Operation Set Interrupt Mode 2 Op Code IM Operand 2 Description The IM 2 instruction sets the vectored Interrupt Mode 2 This mode allows an indirect call to any memory location by an 8 bit vector supplied from the peripheral device This vector then becomes the least significant eight bits of the indirect pointer while the I Register in the CPU provides the most significant eight bits This address points to an address in a vector table that is the starting address for the interrupt service routine M Cycles T States 4 MHz E T 2 8 4 4 2 00 Condition Bits Affected None Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 185 16 Bit Arithmetic Group The following 16 bit arithmetic group instructions are each described in this section Sim ply click to jump to an instruction s description to learn more ADD HL ss see page 186 ADC HL ss see page 188 SBC HL ss see page 190 ADD IX pp see page 192 ADD IY rr see page 194 INC ss see page 196 INC IX see page 197 INC IY see page 198 DEC ss see page 199 DEC IX see page 200 DEC IY see page 201 UM008006 0714 Z80 Instruction Description Z80 CPU User Manual zilog ILU hos 186 nIXYS ADD HL ss Operation HL HL ss Op Code ADD Operands HL ss Description The contents of register pair ss a
38. Jump instruction uses only two bytes the second byte is a signed two s com plement displacement from the existing Program Counter This displacement can be in the range of 129 to 126 and is measured from the address of the instruction op code Z80 CPU Instructions UM008006 0714 Z80 CPU User Manual ZIlog BIXYS Table 14 Jump Call and Return Group Condition Un Non Non Parity Parity Sign Sign Reg Cond Carry Carry Zero Zero Even Odd Neg Pos B 0 C3 D8 D2 CA C2 EA E2 FA F2 JUMP IMMED JP EXT nn n n n n n n i n n n n n n n n n JUMP 18 38 30 28 20 IR RELATIVE PC e e 2 e2 e2 e2 e 2 HL EB JUMP Register IX DD JP INDIR E9 FD IY E UNER B 2n po x ce a a e js EXT n n n n n n n n n Decrement B Jump If Non Zero RELATIVE PC e A DJNZ E C9 DB Do C8 co EB EO F8 FO Return From Interrupt ED RETI REGISTER SP 4D INDIR SP 1 Return From Non Maskable ED Interrupt 45 RETN y Note Descriptions of the Jump Group instructions begin on page 258 Three types of Register Indirect jumps are also included These instructions are imple mented by loading the register pair HL or one of the index registers IX or IY directly into the Program Counter This feature allows for program jumps to be a function of previous calculations A Call is a special form of a jump in which the addre
39. UM008006 0714 Z80 CPU User Manual Zilog DIXYS List of Tables Interrupt Enable Disable Flip Flops eese 18 Bubble Listing comision Eas 29 Multiply Listing i e esenea X dolar idan crac de eras 31 Hex Binary Decimal Conversion Table oooooo oooooooo o 38 8 Bit Load Group LD 0 cet ee 40 16 Bit Load Group LD PUSH and POP 20000 43 Exchanges EX and EXX 1 ene 45 Block Transfer Group 0 0 0 eee eee I 46 Block Search Group 0 eee een ees 47 8 Bit Arithmetic and Logic 0 0 eee eee 48 General Purpose AF Operation 0 0 0 c eee eee ee eee 49 16 Bit Arithmetic sins fado taeda a daa een eta ease 50 Bit Manipulation Group 1 0 0 eee n 53 Jump Call and Return Group 0 0 0 0 eee eee eee 57 Example Usage of the DJNZ Instruction o oooococoooononco oo 58 Restart Group ii A ba Ree we 59 Input Group s cireres laa rola iio cia ede Saas 60 8 Bit Arithmetic and Logic 0 0 0 eee eee eee 61 Miscellaneous CPU Control 0 0 00 eee eee 62 Flag Register Bit Positions 0 0 cee eee eee eee 63 Plas Definitions iia Oa Ae e ale RA Eade BR ye 64 Half Carry Flag Add Subtract Operations 0 005 66 List of Tables Z80 CPU User Manual Zilog XiV OIXYs List of Tables UM008006 0714 Z80 CPU User Manual ZzIlog nIXYS 1 Architectural Overview Zilog s Z80 CPU family of components are fourth g
40. UMO008006 0714 Interrupt Response Z80 CPU User Manual The state of IFF1 is used to inhibit interrupts while IFF2 is used as a temporary storage location for IFF1 A CPU reset forces both the IFF1 and IFF2 to the reset state which disables interrupts Interrupts can be enabled at any time by an El instruction from the programmer When an EI instruction is executed any pending interrupt request is not accepted until after the instruction following EI is executed This single instruction delay is necessary when the next instruction is a return instruction Interrupts are not allowed until a return is com pleted The El instruction sets both IFF1 and IFF2 to the enable state When the CPU accepts a maskable interrupt both IFF1 and IFF2 are automatically reset inhibiting fur ther interrupts until the programmer issues a new El instruction y Note For all of the previous cases IFF1 and IFF2 are always equal The purpose of IFF2 is to save the status of IFF1 when a nonmaskable interrupt occurs When a nonmaskable interrupt is accepted IFF1 resets to prevent further interrupts until reenabled by the programmer Therefore after a nonmaskable interrupt is accepted mask able interrupts are disabled but the previous state of IFF1 is saved so that the complete state of the CPU just prior to the nonmaskable interrupt can be restored at any time When a Load Register A with Register I LD A J instruction or a Load Register A with Register R
41. Upon the execution of an LD HL 5000h instruction the HL register pair contains 5000h UM008006 0714 Z80 Instruction Description 97 Z80 CPU User Manual Zilog BIXYS LD IX nn Operation IX nn Op Code LD Operands IX nn ra n ra n Description The n integer is loaded to Index Register IX The first n operand after the op code is the low order byte M Cycles T States 4 MHz E T 4 14 4 4 3 3 3 50 Condition Bits Affected None Example Upon the execution of an LD X 45A2h instruction the index register contains integer 45A2h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 99 LD IY nn Operation IY nn Op Code LD Operands IY nn at n t n Description The nn integer is loaded to Index Register IY The first n operand after the op code is the low order byte M Cycles T States 4 MHz E T 4 14 4 4 3 3 3 50 Condition Bits Affected None Example Upon the execution of a LD Y 7733h instruction Index Register IY contains the integer 7733h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Z T On BLU y 100 nIXYS LD HL nn Operation H nn 1 L nn Op Code LD Operands HL nn r n a n gt Description The
42. address and data bus enter a high imped ance state and all control output signals enter an inactive state RESET must be active for a minimum of three full clock cycles before a reset operation is complete Architectural Overview UMO008006 0714 Z80 CPU User Manual zilog nIXYS 7 RFSH Refresh output active Low RFSH together with MREQ indicates that the lower seven bits of the system s address bus can be used as a refresh address to the system s dynamic memories WAIT WAIT input active Low WAIT communicates to the CPU that the addressed memory or I O devices are not ready for a data transfer The CPU continues to enter a WAIT state as long as this signal is active Extended WAIT periods can prevent the CPU from properly refreshing dynamic memory WR Write output active Low tristate WR indicates that the CPU data bus contains valid data to be stored at the addressed memory or I O location CLK Clock input Single phase MOS level clock gt Note All signals with an overline are active Low For example B W in which word is active Low or B W in which byte is active Low Timing The Z80 CPU executes instructions by stepping through a precise set of basic operations These operations include e Memory read or write e I O device read or write e Interrupt acknowledge All instructions are a series of basic operations Each of these operations can take from three to six clock periods to comple
43. also shows the corresponding three bit r field for each that appears in the assembled object code Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 M Cycles T States 4 MHz E T 3 12 4 4 4 3 00 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 305 Condition Bits Affected None Example If Register C contains 01n and the D Register contains 5Ah then upon the execution of an OUT C D instruction byte 5Ah is written to the peripheral device mapped to I O port address 01h UM008006 0714 Z80 Instruction Description 306 Z80 CPU User Manual Ar ZILOgd Operation C HL B B 1 HL HL 1 Op Code OUTI Operands None Description The contents of the HL register pair are placed on the address bus to select a location in memory The byte contained in this memory location is temporarily stored in the CPU Then after the byte counter B is decremented the contents of Register C are placed on the bottom half AO through A7 of the address bus to select the I O device at one of 256 possible ports Register B can be used as a byte counter and its decremented value is placed on the top half A8 through A15 of the address bus The byte to be output is placed on the data bus and written to a selected peripheral device Finally the register pair HL is incremented M Cycles T States 4 MHz E T 4 16 4 5 3 4 4 00 Conditio
44. contains contents of IFF2 N is reset C is not affected If an interrupt occurs during execution of this instruction the Parity flag contains a 0 Z80 Instruction Set UM008006 0714 LD A R Operation AR Op Code LD Operands A R Description Z80 CPU User Manual ZItog DIXYS The contents of Memory Refresh Register R are loaded to the Accumulator M Cycles T States MHz E T 2 9 4 5 2 25 Condition Bits Affected S is set if R Register is negative otherwise it is reset Z is set if the R Register is 0 otherwise it is reset H is reset P V contains contents of IFF2 N is reset C is not affected If an interrupt occurs during execution of this instruction the parity flag contains a 0 UM008006 0714 Z80 Instruction Description 93 94 Z80 CPU User Manual ZIlog BIXYS LD LA Operation I A Op Code LD Operands LA Description The contents of the Accumulator are loaded to the Interrupt Control Vector Register I M Cycles T States MHz E T 2 9 4 5 2 25 Condition Bits Affected None Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 95 LD R A Operation R A Op Code LD Operands R A A 3p bob GE 351 EB Oe Oe ox ae a a ae E Description The contents of the Accumulator are loaded to the Memory Refresh register
45. contents are placed on the top half A8 through A15 of the address bus at this time Then one byte from the selected port is placed on the data bus and written to the CPU The contents of the HL register pair are placed on the address bus and the input byte is written to the corresponding location of memory Then HL and the byte counter are dec remented If decrementing causes B to go to 0 the instruction is terminated If B is not 0 the Program Counter is decremented by two and the instruction repeated Interrupts are recognized and two refresh cycles are executed after each data transfer When B is set to O prior to instruction execution 256 bytes of data are input If B Z0 M Cycles T States 4 MHz E T 5 21 4 5 3 4 5 5 25 If B 2 0 M Cycles T States 4 MHz E T 4 16 4 5 3 4 4 00 UM008006 0714 Z80 Instruction Description 301 Z80 CPU User Manual Zilog 302 BIXYS Condition Bits Affected S is unknown Z is set H is unknown P V is unknown N is set C is not affected Example Register C contains 07h Register B contains 03h the HL register pair contains 1000h and the following sequence of bytes is available at the peripheral device mapped to I O port address 07h 51h A9h 03h Upon the execution of an INDR instruction the HL register pair contains OF FDh Register B contains a 0 and the memory locations contain the following data OFFEh 03h OFFFh A9h 1000h 51h Z80 Instruction Set UM00800
46. contents of memory address nn are loaded to the low order portion of register pair HL Register L and the contents of the next highest memory address nn 1 are loaded to the high order portion of HL Register H The first n operand after the op code is the low order byte of nn M Cycles T States 4 MHz E T 5 16 4 3 3 3 3 4 00 Condition Bits Affected None Example If address 4545h contains 37h and address 4546h contains A1h then upon the execution of an LD AL 4545h instruction the HL register pair contains A137h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 101 LD dd nn Operation ddh nn 1 ddl nn Op Code LD Operands dd nn ra n ra n Description The contents of address nn are loaded to the low order portion of register pair dd and the contents of the next highest memory address nn 1 are loaded to the high order portion of dd Register pair dd defines BC DE HL or SP register pairs assembled as follows in the object code Pair dd BC DE 01 HL 10 SP 11 The first n operand after the op code is the low order byte of nn M Cycles T States 4 MHz E T 6 20 4 4 3 3 3 3 5 00 Condition Bits Affected None UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 102 BIXYS Comp Example If Address 2130h contains 65h and address 2131h contains 78h the
47. element in comparison 18 h flag to indicate exchange UM008006 0714 Programming Task Examples 30 Z80 CPU User Manual Zilog BIXYS Table 2 Bubble Listing Continued Object Location Code Statement Source Statement 19 unused 20 i ix pointer into data array 21 iy unused 22 0000 222600 23 Sort Id data hl save data address 0003 cb84 24 loop res flag h initialize exchange flag 0005 41 25 Id b c initialize length counter 0006 05 26 dec b adjust for testing 0007 dd2a260 27 ld ix data initialize array pointer 0 000b dd7e00 28 next Id a ix first element in comparison 000e 57 29 ld d a temporary storage for element goof dd5e01 30 Id e ix 1 second element in comparison 0012 93 31 sub e comparison first to second 0013 3008 32 jr pc noex _ if first gt second no jump 0015 dd7300 33 Id ix e exchange array elements 0018 dd7201 34 ld ix i d 001b cbc4 35 set flag h record exchange occurred 0010 dd23 36 noex inc ix point to next data element 001f 10ea 37 djnz next count number of comparisons 38 repeat if more data pairs 0021 cb44 39 bit flag h determine if exchange occurred 0023 20de 40 jr nz loop continue if data unsorted 0025 c9 41 ret otherwise exit 42 0026 43 flag equ 0 designation of flag bit 0026 44 data defs 2 storage for data address 45 end Hardware and Software Implementation UMO008006 0714 Z80 CPU User Manual
48. end The operation is programmed as follows LD HL ARG1 ADDRESS OF MINUEND LD DE ARG2 ADDRESS OF SUBTRAHEND LD B LENGTH LENGTH OF TWO ARGUMENTS AND A CLEAR CARRY FLAG SUBDEC LD A DE SUBTRAHEND TO ACC Hardware and Software Implementation UMO008006 0714 SBC A HL DAA LD HL A INC HL INC DE DJNZ SUBDEC Z80 CPU User Manual ZzIlog nIXYS 29 RESULT TO DECIMAL CODED VALUE SUBTRACT HL FROM ACC ADJUST STORE RESULT ADVANCE MEMORY POINTERS DECREMENT B AND GO TO SUBDEC IF B NOT ZERO OTHERWISE FALL THROUGH Seventeen bytes are required for this operation Programming Task Examples As indicated in Table 2 this example program sorts an array of numbers to ascending order using a standard exchange sorting algorithm These numbers range from 0 to 255 Table 2 Bubble Listing Object Location Code Statement Source Statement 1 A standard exchange bubble sort routine 2 i 3 atentry hl contains address of data 4 c contains number of elements to be sorted 1 c lt 256 5 6 i 7 i at exit data sorted in ascending order 8 i 9 a use of registers 10 11 i register contents 12 13 a temporary storage for calculations 14 E b counter for data array 15 C length of data array 16 d first element in comparison 17 e second
49. flag con tain the following data 7 6 5 4 8 2 1 0 C MERF2ESESERE SENI Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog oLxys 227 Upon the execution of an RR HL instruction location 434 3h and the Carry flag now contain 7 6 5 4 3 2 1 0 C 0 1 1 0 1 1 1 0 1 UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOg 228 DIXYS SLA m Operation ma oa O m Op Code SLA Operand m The m operand is any of r HL IX d or IY d as defined for the analogous RLC instructions In the assembled object code the possible op code operand combinations are specified as follows SLA r 1 1 0 0 1 0 1 1 CB SLA HL 1 1 0 0 1 0 1 1 CB SLA IX d 1 1 0 1 1 1 0 1 DD SLA IY d 1 1 1 1 1 1 0 1 FD Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZzIlog nIXYS 229 r identifies registers B C D E H L or A assembled as follows in the object code field Description Register B gt rr rm 000 001 010 011 100 101 111 r An arithmetic shift left 1 bit position is performed on the contents of operand m The con tents of bit 7 are copied to the Carry flag Bit 0 is the least significant bit In
50. in memory to be compared with Accumulator contents BC is a byte counter gt Note Descriptions of the Exchange Block Transfer and Search Group instructions begin on page 121 The CPIR instruction is merely an extension of the CPI instruction in which the compare is repeated until either a match is found or the byte counter register pair BC becomes zero As a result this single instruction can search the entire memory for any 8 bit character The Compare and Decrement CPD and Compare Decrement and Repeat CPDR instructions are similar however their only difference is that they decrement HL after every compare so that they search the memory in the opposite direction i e the search is started at the highest location in the memory block These block transfer and compare instructions are extremely powerful in string manipula tion applications Arithmetic and Logical Table 10 lists all of the 8 bit arithmetic operations that can be performed with the Accu mulator Also listed are the increment INC and decrement DEC instructions In all of these instructions with the exception of INC and DEC the specified 8 bit operation is per formed between the data in the Accumulator and the source data UM008006 0714 Arithmetic and Logical Z80 CPU User Manual ilo ry Z ILUO Vj DIXYS Table 10 8 Bit Arithmetic and Logic Source Register Register Addressing Indirect Indexed Immediate
51. in the Accumulator Instruction M Cycles T States 4 MHz E T AND r 1 4 1 00 AND n 2 7 4 3 1 75 AND HL 2 7 4 3 1 75 AND IX d 5 19 4 4 3 5 3 4 75 AND IX d 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is set P V is reset if overflow otherwise it is reset N is reset C is reset Example If Register B contains 7Bh 0111 1011 and the Accumulator contains C3h 1100 0011 then upon the execution of an AND B instruction the Accumulator contains 43h 0100 0011 780 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 157 OR s Operation A lt AVs Op Code OR Operand S The s operand is any of r n HL IX d or IY d as defined for the analogous ADD instructions These possible op code operand combinations are assembled as follows in the object code OR r 1 011 1 0 rr gt ORn 1 1 1 1 0 41 4 04 F6 OR HL 1 0 1 1 0 1 1 o B6 OR IX d 1 110 1 1 110 1 DD OR IY d 1 1 1 1 1 110 1 FD UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 158 DIXYS Comp r identifies registers B C D E H L or A specified in the assembled object code field as follows Register r B 000 C 001 D 010 E 011 H 100 L 101 A 1
52. interrupting device can place an 8 bit vector on the data bus Two wait states are automatically added to this cycle These states are added so that a ripple priority interrupt scheme can be easily implemented The two wait states allow sufficient time for the ripple signals to stabilize and identify which I O device must insert the response vector Refer to the Interrupt Response section on page 17 to learn more about how the interrupt response vector is utilized by the CPU Architectural Overview UMO008006 0714 Z80 CPU User Manual Zilog BIXYS Last M Cycle of Instruction M1 Last T State Figure 9 Interrupt Request Acknowledge Cycle Nonmaskable Interrupt Response Figure 10 shows the request acknowledge cycle for the nonmaskable interrupt This signal is sampled at the same time as the interrupt line but this line takes priority over the normal interrupt and it cannot be disabled under software control Its usual function is to provide immediate response to important signals such as an impending power failure The CPU response to a nonmaskable interrupt is similar to a normal memory read operation The only difference is that the contents of the data bus are ignored while the processor auto matically stores the Program Counter in the external stack and jumps to address 0066h The service routine for the nonmaskable interrupt must begin at this location if this inter rupt is used UMO008006 0714 Nonmaskable Inter
53. is set if result is 0 otherwise it is reset H is set if carry from bit 11 otherwise it is reset P V is set if overflow otherwise it is reset Z80 Instruction Set UM008006 07 14 UM008006 0714 Z80 CPU User Manual Zilog nIXYS 189 N is reset C is set if carry from bit 15 otherwise it is reset Example If register pair BC contains 2222h register pair HL contains 5437h and the Carry Flag is set then upon the execution of an ADC HL BC instruction HL contains 765Ah Z80 Instruction Description 190 Z80 CPU User Manual Zilo O BIXYS SBC HL ss Operation HL HI ss CY Op Code SBC Operands HL ss Description The contents of the register pair ss any of register pairs BC DE HL or SP and the Carry Flag C flag in the F Register are subtracted from the contents of register pair HL and the result is stored in HL In the assembled object code operand ss is specified as follows Register Pair ss BC 00 DE 01 HL 10 SP 11 M Cycles T States 4 MHz E T 4 15 4 4 4 3 3 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset His set if borrow from bit 12 otherwise it is reset P V is set if overflow otherwise it is reset Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog BIXyS 191 N is set C is set if borrow otherwise it is reset
54. least significant bit M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected Condition Bits Affected S is not affected Z is not affected H is reset P V is not affected N is reset C is data from bit 7 of Accumulator UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Example The Accumulator and the Carry flag contains the following data C 7 6 5 4 3 2 1 0 1 0 1 1 1 0 1 1 0 Upon the execution of an RLA instruction the Accumulator and the Carry flag contains C 7 6 5 4 3 2 1 0 0 1 1 1 0 1 1 0 1 Z80 Instruction Set UM008006 07 14 RRCA Z80 CPU User Manual ZILOg OIXYS Operation Op Code RRCA Operands None 0 0 0 0 1 1 1 fa oF Description The contents of the Accumulator Register A are rotated right 1 bit position Bit 0 is cop ied to the Carry flag and also to bit 7 Bit 0 is the least significant bit M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected S is not affected Z is not affected H is reset P V is not affected N is reset C is data from bit 0 of Accumulator Example The Accumulator contains the following data UM008006 0714 Z80 Instruction Description 207 Z80 CPU User Manual airy ZIlog Upon the execution of an RRCA instruct
55. negative after an operation otherwise it is reset Z is set if the Accumulator is 0 after an operation otherwise it is reset H is reset Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog OIXYS 239 P V is set if the parity of the Accumulator is even after an operation otherwise it is reset N is reset C is not affected Example The HL register pair contains 5000h and the Accumulator and memory location 5000h contain the following data 1 0 0 0 0 1 0 0 Accumulator 0 0 1 0 0 0 O O 5000h Upon the execution of an RRD instruction the Accumulator and memory location 5000h now contain 7 6 5 4 3 2 1 0 1 0 0 0 0 010 0 Accumulator 0 1 0 0 0 0 1 0 5000h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Z i Ory ILU y 240 nIXYS Bit Set Reset and Test Group The following bit set reset and test group instructions are each described in this section Simply click to jump to an instruction s description to learn more BIT b r see page 241 BIT b HL see page 243 BIT b IX d see page 245 BIT b LY d see page 247 SET b r see page 249 SET b HL see page 251 SET b 1X d see page 253 SET b IY d see page 254 SET b Y d see page 254 RES b m see page 256 Z80 In
56. pair HL is incremented M Cycles T States 4 MHz E T 4 16 4 5 3 4 4 00 Condition Bits Affected S is unknown Z is set if B 1 0 otherwise it is reset H is unknown P V is unknown N is set C is not affected UM008006 0714 Z80 Instruction Description 295 Z80 CPU User Manual ZILOg 296 DIXYS Comp Example Register C contains 07h Register B contains 10h the HL register pair contains 1000h and byte 7Bh is available at the peripheral device mapped to I O port address 07h Upon the execution of an INI instruction memory location 1000h contains 7Bh the HL register pair contains 1001h and Register B contains 0Fh Z80 Instruction Set UM008006 07 14 INIR Z80 CPU User Manual ZItog DIXYS Operation HL C B B 1 HL HL 1 Op Code INIR Operands None Description The contents of Register C are placed on the bottom half A0 through A7 of the address bus to select the I O device at one of 256 possible ports Register B is used as a byte coun ter and its contents are placed on the top half A8 through A15 of the address bus at this time Then one byte from the selected port is placed on the data bus and written to the CPU The contents of the HL register pair are placed on the address bus and the input byte is written to the corresponding location of memory Then register pair HL is incremented the byte counter is decremented If decreme
57. pairs BC DE IY or SP are added to the contents of Index Register IY and the result is stored in IY In the assembled object code the rr operand is specified as follows Register Pair ss BC 00 DE 01 IY 10 SP 11 M Cycles T States 4 MHz E T 4 15 4 4 4 3 3 75 Condition Bits Affected S is not affected Z is not affected H is set if carry from bit 11 otherwise it is reset P V is not affected Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 195 N is reset C is set if carry from bit 15 otherwise it is reset Example If Index Register IY contains 333h and register pair BC contains 555h then upon the exe cution of an ADD Y BC instruction IY contains 8888h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Z T On BLU y 196 DIXYS INC ss Operation ss ss 1 Op Code INC Operand SS Description The contents of register pair ss any of register pairs BC DE HL or SP are incremented In the assembled object code operand ss is specified as follows Register Pair ss BC 00 DE 01 HL 10 SP 11 M Cycles T States 4 MHz E T 1 6 1 50 Condition Bits Affected None Example If the register pair contains 1000h then upon the execution of an INC AL instruction HL contains 1001h Z80 Instruction Set UM008006 07 14 INC IX Z80 CPU User Manual ZILOg BIXYS Operation IX IX 1 Op Code IN
58. reset Z is set if result is 0 otherwise it is reset H is set if borrow from bit 4 otherwise it is reset P V is reset if overflow otherwise it is reset N is set C is set if borrow otherwise it is reset Example If the Accumulator contains 16h the carry flag is set the HL register pair contains 3433h and address 3433h contains 05h then upon the execution of an SBC A HL instruction the Accumulator contains 10h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual zilog nIXYS 155 AND s Operation AAAS Op Code AND Operand S The s operand is any of r n HL IX d or IY d as defined for the analogous ADD instructions These possible op code operand combinations are assembled as follows in the object code AND r 1 0 1 0 0 r gt ANDn 1 1 41 0 0 41 41 0 E6 AND HL 1 0 1 50 0 1441 0 A6 AND IX d 1 1 0 1 1 110 1 DD AND IY d 111114 1 1 4707 14 FD UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 156 DIXYS Comp r identifies registers B C D E H L or A specified in the assembled object code field as follows Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description A logical AND operation is performed between the byte specified by the s operand and the byte contained in the Accumulator the result is stored
59. specify the Accumulator or any general purpose register on which an operation is to be performed Register Indirect and Indexed addressing are available for operations at external memory locations Bit test operations set the Zero flag Z if the tested bit is a 0 gt Note Descriptions of the Bit Set Reset and Test Group instructions begin on page 240 Jump Call and Return Table 14 lists all of the jump call and return instructions implemented in the Z80 CPU A jump is a branch in a program in which the program counter is loaded with a 16 bit value as specified by one of the three available addressing modes Immediate Extended Rela tive or Register Indirect In Table 14 the jump group includes several conditions that can be specified before the jump is made If these conditions are not met the program merely continues with the next sequential instruction The conditions are all dependent on the data in the Flag Register The immediate extended addressing is used to jump to any location in the memory This instruction requires three bytes i e two bytes designated to specifying the 16 bit address with the low order address byte first followed by the high order address byte An example of an unconditional jump to memory location 3E32h is shown in Figure 40 Address A C3 Op Code A 1 32 low order Address A 2 SE high order Address Figure 40 Example of an Unconditional Jump Sequence The Relative
60. with minimal access time to the routine Memory Refresh R Register The Z80 CPU contains a memory refresh counter enabling dynamic memories to be used with the same ease as static memories Seven bits of this 8 bit register are automatically incremented after each instruction fetch The eighth bit remains as programmed resulting from an LD R A instruction The data in the refresh counter is sent out on the lower portion of the address bus along with a refresh control sig nal while the CPU is decoding and executing the fetched instruction This mode of refresh is transparent to the programmer and does not slow the CPU operation The programmer can load the R register for testing purposes but this register is normally not used by the programmer During refresh the contents of the I Register are placed on the upper eight bits of the address bus Accumulator and Flag Registers The CPU includes two independent 8 bit Accumula tors and associated 8 bit Flag registers The Accumulator holds the results of 8 bit arith metic or logical operations while the Flag Register indicates specific conditions for 8 bit or 16 bit operations such as indicating whether or not the result of an operation is equal to 0 The programmer selects the Accumulator and flag pair with a single exchange instruc tion so that it is possible to work with either pair General Purpose Registers Two matched sets of general purpose registers each set containing six 8 bit regi
61. 0 CPU User Manual ZIlOg nIXYS 179 HALT Operation Op Code HALT Operands None Description The HALT instruction suspends CPU operation until a subsequent interrupt or reset is received While in the HALT state the processor executes NOPs to maintain memory refresh logic M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Z id Mn LL y 180 nIXYS DI Operation IFF 0 Op Code DI 1 1 1 1 0 0 1 1 F3 Operands None Description DI disables the maskable interrupt by resetting the interrupt enable flip flops IFF1 and IFF2 Note This instruction disables the maskable interrupt during its execution M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None Example When the CPU executes the instruction DI the maskable interrupt is disabled until it is subsequently re enabled by an EI instruction The CPU does not respond to an Interrupt Request INT signal Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 181 El Operation IFF 1 Op Code EI 111 11 1jo 1 1 FB Operands None Description The enable interrupt instruction sets both interrupt enable flip flops IFFI and IFF2 to a logic 1 allowing recognition of any maskable interrupt gt Not
62. 0 language are easy to maintain In Table 5 some op codes that are available in the Z80 CPU use two bytes This feature is an efficient method of memory utilization because 8 18 24 or 32 bit instructions are implemented in the Z80 CPU Often utilized instructions such as arithmetic or logical operations are only eight bits which results in better memory utilization than is achieved with fixed instruction sizes such as 16 bits All load instructions using indexed addressing for either the source or destination location actually use three bytes of memory with the third byte being the displacement d For example a Load Register E instruction with the operand pointed to by IX with an offset of 8 is written as LID E IX 8 The instruction sequence for this value in memory is shown in Figure 32 Address A DD Op Code A 1 5E na Displacement A 2 ii EE Operand Figure 32 Example of a 3 Byte Load Indexed Instruction Sequence The two extended addressing instructions are also three byte instructions For example the instruction to load the Accumulator with the operand in memory location 6F32h is written as LID A 6F 32h The instruction sequence for this value in memory is shown in Figure 33 UMO008006 0714 Load and Exchange Z80 CPU User Manual ra ri ZILOgd Address A 3A Op Code A 1 32 low order Address A 2 6F high order Address Figure 33 Example of a 3 Byte Load Extend
63. 08 09 04 06 oC OD OE d d CA OF 3 Leit 0E 0E DD FD pr CB CB CB CB CB CB CB CB CB CB Right RL 47 10 11112 13 14 15 16 d d ae cd 16 16 Sn SERI SED CY Left Arithmetic CB CB CB CB CB CB CB CB CB CB RR HE 18 19 1A 1B 1C 4D 1E d d zs M orm 1E 1E DB FD Shift sia CB CB CB CB CB CB CB CB CB CB Panes Right Logical 27 20 21 22 23 24 235 26 d d 26 26 0 Y Rotat DD FD b3 bo b7 b4 ba bo HL Digit sra CB CB CB CB CB CB CB CB CB CB ACC A 2F 28 29 2A 2B 2C 2D 2E d d 2E 2E DD FD D CB CB CB CB CB CB CB CB CB CB acch Right 3F 38 39 3A 3B 3C 3D 3E d d 3E 3E SRL ER 6F ED 67 Figure 39 Rotates and Shifts gt Note Descriptions of the Rotate and Shift Group instructions begin on page 202 Z80 CPU Instructions UM008006 0714 Z80 CPU User Manual ZILOg nIXYS 53 Bit Manipulation The ability to set reset and test individual bits in a register or memory location is required in almost every program These bits can be flags in a general purpose software routine indications of external control conditions or data packed into memory locations making memory utilization more efficient With a single instruction the Z80 CPU can set reset or test any bit in the Accumulator in any general purpose register or in any memory location Table 13 lists the 240 instruc tions that are available for this purpose Table
64. 08006 0714 Z80 CPU User Manual Zilog OIXYS r A Sea E a a a eccL 199 DECID iii aid iaa 200 DEY ds asa ia 201 RECA 8 5 EE seid 33h 8 oa a Sa ee Se eae Cea ita 203 RLA it A ETT 205 NO Cc 207 RRA TP 209 PE outs cuui t nus iustus iuste Tuc Poeni E 211 REC EI eei hack ash he eae bo nea aks pes sud eau sui utei eA 213 RECTA eea r ecu E E 215 REC YFU a tu ede Rue Reti qoas axo 217 RIS Tfi 3 usd redd bEPLRGI BREAD ad REVO VE die iod duet ius 219 BE EPFL 222 RR ll Ie ID eT IG See Ree peer cy erp e NE dene 225 SEAM A Roe E beoe Mee A ERO AD E Dee RU obo Re AN Ted d 228 d ud MEE etad bbe Suan dhe d atadhed law daa uias aoa vitae tbe ea 231 SRE sche cae ca ce oc aos 234 RED a eres ah aden ae oa sat SAME era gee APE cre dete Sarre E se E 236 RRD iris ae Ee ade PR daa ee IU eee 238 dig c A E nee ee ee ue ve eee 241 BUT ts CIE occorre S ed oa 243 BIT DEA etc ts do ot ER e an e 245 BITO LY Ed sidad boh beige dad ida 247 SET Deis egt RIS Rec Mees WEP S Mia aes VEN ca tka ae 249 SPEA HL ia csv ach raya CO PM ARAS Eli iii LE 251 SETD DE ua ridad eh dda rnd onde eed eee id 253 SETE LY FO it o 254 INEST 256 JP DM rom 259 JECO DW iue ssid ic DET eta ce iS date dois Ae eke 260 Rie Shanes aude vibes athens Seed aha See ES LS EAS OS REO RS RAS RS 262 der Bk he fen in ets akan it PECES 264 TRING e nina da dada aka Hides Wea has hen 266 IR E ER edt ho Ra see dd A dee ES EER 268 TRIN Za A tas 270 IP HE udo ete oP bbe hd BERI dda eR aed AGG
65. 1 6 110 1 111 M Cycles T States 4 MHz E T 3 12 4 4 4 4 3 00 Condition Bits Affected S is unknown UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 244 DIXYS Z is set if specified bit is 0 otherwise it is reset H is set P V is unknown H is reset C is not affected Example If the HL register pair contains 4444h and bit 4 in the memory location 444h contains 1 then upon the execution of a BIT 4 HZ instruction the Z flag in the F Register contains 0 and bit 4 in memory location 4444h remains at 1 Bit 0 in memory location 4444h is the least significant bit Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 245 BIT b IX d Operation Z IX d b Op Code BIT Operands b IX d Description This instruction tests bit b in the memory location specified by the contents of register pair IX combined with the two s complement displacement d and sets the Z flag accordingly In the assembled object code operand b is specified as follows Bit Tested b 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 M Cycles T States 4 MHz E T 5 20 4 4 3 5 4 5 00 UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 246 OIXYS Condition Bits Affected S is unknown Z is set if specified bit is 0 otherwise it is reset H is set P V is unknown N is reset C is no
66. 11 Description A logical OR operation is performed between the byte specified by the s operand and the byte contained in the Accumulator the result is stored in the Accumulator Instruction M Cycles T States 4 MHz E T ORr 1 4 1 00 ORn 2 7 4 3 1 75 OR HL 2 7 4 3 1 75 OR IX d 5 19 4 4 3 5 3 4 75 OR IY d 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is reset P V is set if overflow otherwise it is reset N is reset C is reset Example If the H Register contains 48h 0100 0100 and the Accumulator contains 12h 0001 0010 then upon the execution of an OR H instruction the Accumulator contains 5Ah 0101 1010 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual zilog nIXYS 159 XOR s Operation ASA Os Op Code XOR Operand S The s operand is any of r n HL IX d or IY d as defined for the analogous ADD instructions These possible Op Code operand combinations are assembled as follows in the object code OR r 1 0 1 1 0 r gt ORn 1 1 1 1 0 141414 0 F6 OR HL 1 0 1 14 0 1 1 0 B6 OR IX d 1 1 0 1 1 1 0 1 DD OR IY d 1 14 4 4 144 147 0 414 4 FD UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 160 GIXY
67. 3 3 3 3 5 00 Condition Bits Affected None Example If address 6666h contains 92h and address 6667h contains DAh then upon the execution of an LD IY 6666h instruction Index Register IY contains DA92h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 105 LD nn HL Operation nn 1 H nn L Op Code LD Operands nn HL r n a n gt Description The contents of the low order portion of register pair HL Register L are loaded to mem ory address nn and the contents of the high order portion of HL Register H are loaded to the next highest memory address nn 1 The first n operand after the op code is the low order byte of nn M Cycles T States 4 MHz E T 5 16 4 3 3 3 3 4 00 Condition Bits Affected None Example If register pair HL contains 483Ah then upon the execution of an LD B229 1 HL instruction address B229h contains 3Ah and address B22Ah contains 48h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Z ilog ILU y 106 DIXYS LD nn dd Operation nn 1 ddh nn ddl Op Code LD Operands nn dd Description ED The low order byte of register pair dd is loaded to memory address nn the upper byte is loaded to memory address nn 1 Register pair dd defines either BC DE HL or SP a
68. 3 5 4 3 5 75 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog OIXYS 255 Condition Bits Affected None Example If Index Register IY contains 2000h then upon the execution of a Set 0 JY 3h instruc tion bit O in memory location 2003h is 1 Bit 0 in memory location 200 3h is the least sig nificant bit UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Z id Mn L NN MJ 256 nIXYS RES b m Operation sb 0 Op Code RES Operands b m The b operand represents any bit 7 through 0 of the contents of the m operand any of r HL IX d or IY d as defined for the analogous SET instructions These possible op code operand combinations are assembled as follows in the object code RES b rn 1 1 0 0 1 0 1 1 CB RES b HL 1 1 010 1 0 1 1 CB RES b IX d 1 1 0 1 1 1 0 1 DD RES b IY d 1 4 4 4 44 4 4 0 7 1 FD Z80 Instruction Set UM008006 07 14 w e c 000 001 010 011 100 101 110 111 Oo Of WDM o Description Bit b in operand rn is reset Instruction M Cycles RES r 4 RES HL 4 RES IX d 6 RES IY d 6 Condition Bits Affected None Example Z80 CPU User Manual ZzIlog nIXYS 257 Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 T States 4 MHz E T 8 4
69. 3 T1 T2 T3 Machine Cycle M1 M2 M3 Opcode Fetch Memory Read Memory Write Instruction Cycle Figure 4 Basic CPU Timing Example Instruction Fetch Figure 5 depicts the timing during an M1 op code fetch cycle The Program Counter is placed on the address bus at the beginning of the M1 cycle One half clock cycle later the MREQ signal goes active At this time the address to memory has had time to stabilize so that the falling edge of MREQ can be used directly as a chip enable clock to dynamic memories The RD line also goes active to indicate that the memory read data should be enabled onto the CPU data bus The CPU samples the data from the memory space on the data bus with the rising edge of the clock of state T3 and this same edge is used by the CPU to turn off the RD and MREQ signals As a result the data is sampled by the CPU before the RD signal becomes inactive Clock states T3 and T4 of a fetch cycle are used to refresh dynamic memories The CPU uses this time to decode and execute the fetched instruction so that no other concurrent operation can be performed During T3 and T4 the lower seven bits of the address bus contain a memory refresh address and the RFSH signal becomes active indicating that a refresh read of all dynamic memories must be performed To prevent data from different memory segments from being gated onto the data bus an RD signal is not generated during this refresh period The MREQ signal durin
70. 4 3 1 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is set if carry from bit 3 otherwise it is reset P V is set if overflow otherwise it is reset N is reset C is set if carry from bit 7 otherwise it is reset Example If the Accumulator contains AOh register pair HL contains 2323h and memory location 2323h contains byte 08h then upon the execution of an ADD A HL instruction the Accumulator contains A8h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 147 ADD A IX d Operation A lt A IX d Op Code ADD Operands A IX d Description The contents of the Index register pair IX Register is added to a two s complement dis placement d to point to an address in memory The contents of this address is then added to the contents of the Accumulator and the result is stored in the Accumulator M Cycles T States 4 MHz E T 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is set if carry from bit 3 otherwise it is reset P V is set if overflow otherwise it is reset N is reset C is set if carry from bit 7 otherwise it is reset Example If the Accumulator contains 11h Index Register IX contains 1000h and memory loc
71. 4h is the least significant bit Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 249 SET b r Operation rb lt 1 Op Code SET Operands b r Description Bit b in register r any of registers B C D E H L or A is set In the assembled object code operands b and r are specified as follows Bit b Register r 0 000 B 000 1 001 C 001 2 010 D 010 3 011 E 011 4 100 H 100 5 101 L 101 6 110 A 111 7 111 M Cycles T States 4 MHz E T 2 8 4 4 2 00 Condition Bits Affected None UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 250 IXYS Comp Example Upon the execution of a SET 4 A instruction bit 4 in Register A is set Bit 0 is the least significant bit Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog OLXYs 251 SET b HL Operation HL b 1 Op Code SET Operands b HL Description Bit b in the memory location addressed by the contents of register pair HL is set In the assembled object code operand b is specified as follows Bit Tested b 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 M Cycles T States 4 MHz E T 4 15 4 4 4 3 3 75 Condition Bits Affected None UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 252 nIxYs Example If the HL register pair contains 3000h then up
72. 6 07 14 Z80 CPU User Manual Zilog nIXYS 303 OUT n A Operation n A Op Code OUT Operands n A Description The operand n is placed on the bottom half A0 through A7 of the address bus to select the I O device at one of 256 possible ports The contents of the Accumulator Register A also appear on the top half A8 through A15 of the address bus at this time Then the byte contained in the Accumulator is placed on the data bus and written to the selected periph eral device M Cycles T States 4 MHz E T 3 11 4 3 4 2 75 Condition Bits Affected None Example If the Accumulator contains 23h then upon the execution of an OUT 01h instruction byte 23h is written to the peripheral device mapped to I O port address 01h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOd 304 BDIXYS OUT C r Operation C vt Op Code OUT Operands C r Description The contents of Register C are placed on the bottom half A0 through A7 of the address bus to select the I O device at one of 256 possible ports The contents of Register B are placed on the top half A8 through A15 of the address bus at this time Then the byte con tained in register r is placed on the data bus and written to the selected peripheral device Register r identifies any of the CPU registers shown in the following table which
73. 6 Bit Load Group LD PUSH and POP Source Register Imm Ext Ext Reg Indir Register AF BC DE HL SP IX IY nn nn SP AF P1 TEE BC n E C1 n n ED 11 DE n 2d D1 n n n 21 2A HL n n E1 n n DD FD 31 7B SP BY Fo F9 i n n DD DD 21 2A DD IX n n E1 n n FD FD 21 2A FD y n n El n n Extended ED ED 22 ED DD FD 43 53 73 22 22 nn n n n B n n n n n n n n Register DD FD Indirect REIN rehire HER E6 E6 POP Instructions Note The PUSH and POP instruction adjust the SP after every execution UMO008006 0714 Load and Exchange Z80 CPU User Manual ZIlog 44 BIXYS Note Descriptions of the 16 Bit Load Group instructions begin on page 96 These 16 bit load operations differ from other 16 bit loads in that the stack pointer is auto matically decremented and incremented as each byte is pushed onto or popped from the stack respectively For example the PUSH AF instruction is a single byte instruction with the op code of F5h During execution this sequence is generated as Decrement SP LD SP A Decrement SP LD SP F The external stack now appears as shown in Figure 36 SP F Top of stack SP 1 A Figure 36 Example of a 16 Bit Load Operation The POP instruction is the exact reverse of a PUSH All PUSH and POP instructions uti lize a 16 bit operand and the high order byte i
74. B can be used as a byte counter and its contents are placed on the top half A8 through A15 of the address bus at this time Then one byte from the selected port is placed on the data bus and written to the CPU The contents of the HL register pair are placed on the address bus and the input byte is written to the corresponding location of memory Finally the byte counter and register pair HL are decremented M Cycles T States 4 MHz E T 4 16 4 5 3 4 4 00 Condition Bits Affected S is unknown Zis set if B 1 2 0 otherwise it is reset H is unknown P V is unknown N is set C is not affected UM008006 0714 Z80 Instruction Description 299 Z80 CPU User Manual ZIlog 300 BIXYSconr Example Register C contains 07h Register B contains 10h the HL register pair contains 1000h and byte 7Bh is available at the peripheral device mapped to I O port address 07n Upon the execution of an IND instruction memory location 1000h contains 7Bh the HL regis ter pair contains OFFFh and Register B contains OFh Z80 Instruction Set UM008006 07 14 INDR Z80 CPU User Manual Zilog BIXYS Operation HL C B 131 HL HL1 Op Code INDR Operands None Description The contents of Register C are placed on the bottom half A0 through A7 of the address bus to select the I O device at one of 256 possible ports Register B is used as a byte coun ter and its
75. C Operand IX Description The contents of Index Register IX are incremented M Cycles T States 4 MHz E T 2 10 4 6 2 50 Condition Bits Affected None Example If Index Register IX contains the integer 3300h then upon the execution of an INC IX instruction Index Register IX contains 3301h UM008006 0714 Z80 Instruction Description 197 198 Z80 CPU User Manual zilo O BIXYS INC IY Operation IY IY 1 Op Code INC Operand IY Description The contents of Index Register IY are incremented M Cycles T States 4 MHz E T 2 10 4 6 2 50 Condition Bits Affected None Example If the index register contains 2977h then upon the execution of an INC Y instruction Index Register IY contains 2978h 780 Instruction Set UM008006 07 14 Z80 CPU User Manual ZItog nIXYS 199 DEC ss Operation ss ss 1 Op Code DEC Operand SS Description The contents of register pair ss any of the register pairs BC DE HL or SP are decre mented In the assembled object code operand ss is specified as follows Register Pair ss BC 00 DE 01 HL 10 SP 11 M Cycles T States 4 MHz E T 1 6 1 50 Condition Bits Affected None Example If register pair HL contains 1001h then upon the execution of an DEC AL instruction HL contains 1000h UM008006 0714 Z80 Instructio
76. Computer System Minimum System Hardware Any Z80 system must include the following hardware elements e 5V power supply e Oscillator Memory devices e O circuits CPU UM008006 0714 Hardware and Software Implementation 22 Z80 CPU User Manual Z Ti BLU los OLXYS Because the Z80 CPU requires only a single 5 V power supply most small systems can be implemented using only this single supply The external memory can be any mixture of standard RAM ROM or PROM In Fig ure 18 a single 8 Kb 1 KB ROM comprises the entire memory system The Z80 internal register configuration contains sufficient read write storage requiring no external RAM memory VO circuits allow computer systems to interface with the external devices In Figure 18 the output is an 8 bit control vector and the input is an 8 bit status word The input data can be gated to the data bus using any standard three state driver while the output data can be latched with any type of standard TTL latch A Z80 PIO serves as the I O circuit This single circuit attaches to the data bus as indicated and provides the required 16 bits of TTL compatible I O Refer to the Z80 CPU Peripherals User Manual UM0081 to learn more about the operation of this circuit This powerful computer is built with only three LSI circuits a simple oscillator and a single 5V power supply Adding RAM Most computer systems require some external read write memory for data storage and
77. Description Z80 CPU User Manual ZILOQd 116 nIXYS PUSH IY Operation SP 2 IYL SP 1 IYH Op Code PUSH Operand IY Description The contents of Index Register IY are pushed to the external memory last in first out LIFO stack The Stack Pointer SP Register pair holds the 16 bit address of the current top of the Stack This instruction first decrements the SP and loads the high order byte of IY to the memory address specified by SP then decrements SP again and loads the low order byte to the memory location corresponding to this new address in SP M Cycles T States 4 MHz E T 4 15 4 5 3 3 3 75 Condition Bits Affected None Example If Index Register IY contains 2233h and the Stack Pointer contains 1007h then upon the execution of a PUSH Y instruction memory address 1006h contains 22h memory address 1005h contains 33h and the Stack Pointer contains 1005h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog BIXYS POP qq Operation qqH SP 1 qqL SP Op Code POP Operand qq Description The top two bytes of the external memory last in first out LIFO stack are popped to reg ister pair qq The Stack Pointer SP Register pair holds the 16 bit address of the current top of the Stack This instruction first loads to the low order portion of qq the byte at memory location correspon
78. ELIMITER CODE LOOP CP HL COMPARE MEMORY CONTENTS WITH DELIMITER JR Z END S GO TO END IF CHARACTERS EQUAL LDI MOVE CHARACTER HL to DE INCREMENT HL AND DE DECREMENT BC JP PE LOOP GO TO LOOP IF MORE CHARACTERS END OTHERWISE FALL THROUGH NOTE P V FLAG IS USED TO INDICATE THAT REGISTER BC WAS DECREMENTED TO ZERO Nineteen bytes are required for this operation Example 3 A 16 digit decimal number is shifted as depicted in Figure 24 This shift is performed to mechanize BCD multiplication or division The 16 digit decimal number is represented in packed BCD format two BCD digits byte The operation is programmed as follows UM008006 0714 Specific Z80 Instruction Examples Z80 CPU User Manual zilo 28 nIXYS j LD HL DATA ADDRESS OF FIRST BYTE LD B COUNT SHIFT COUN XOR A CLEAR ACCUMULATOR ROTAT RLD ROTATE LEFT low order DIGIT IN ACC WITH DIGITS IN HL INC HL ADVANCE MEMORY POINTER DJNZ ROTAT DECREMENT B AND GO TO ROTAT IF B IS NOT ZERO OTHERWISE FALL THROUGH Eleven bytes are required for this operation NN ANAAN Figure 24 Shifting of BCD Digits Bytes Example 4 One number is to be subtracted from another number both of which exist in packed BCD format and are of equal but varying length The result is stored in the location of the minu
79. Example If Index Register IX contains 98DAh then upon the execution of an LD SP IX instruction the Stack Pointer also contains 98DAh UM008006 0714 Z80 Instruction Description 112 Z80 CPU User Manual zilo BIXYS ry M LD SP IY Operation SP IY Op Code LD Operands SP IY Description The 2 byte contents of Index Register IY are loaded to the Stack Pointer SP M Cycles T States 4 MHz E T 2 10 4 6 2 50 Condition Bits Affected None Example If Index Register IY contains the integer A227h then upon the execution of an LD SP IY instruction the Stack Pointer also contains A227h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZzIlog DIXYS PUSH qq Operation SP 2 qqL SP 1 qqH Op Code PUSH Operand qq Description The contents of the register pair qq are pushed to the external memory last in first out LIFO stack The Stack Pointer SP Register pair holds the 16 bit address of the current top of the Stack This instruction first decrements SP and loads the high order byte of reg ister pair qq to the memory address specified by the SP The SP is decremented again and loads the low order byte of gq to the memory location corresponding to this new address in the SP The operand qq identifies register pair BC DE HL or AF assembled as follows in the object code Pair qq BC 00
80. Example If register pair AF contains 9900h and register pair AF contains 5944h the contents of AF are 5944h and the contents of AF are 9900h upon execution of the EX AF AF instruction UMO08006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOQd 124 BIXYS Operation BC o BC DE o DE HL e HL Op Code EXX Operands None 1 1 0 1 1 0 0 1 D9 Description Each 2 byte value in register pairs BC DE and HL is exchanged with the 2 byte value in BC DE and HL respectively M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None Example If register pairs BC DE and HL contain 445Ah 3DA2h and 8859h respectively and register pairs BC DE and HL contain 0988h 9300h and 00E7h respectively then upon the execution of an EXX instruction BC contains 0988h DE contains 9300h HL contains 00E7h BC contains 445Ah DE contains 3DA2h and HL contains 8859h 780 Instruction Set UM008006 07 14 Z80 CPU User Manual ZzIlog nIXYS 125 EX SP HL Operation H gt SP 1 L gt SP Op Code EX Operands SP HL 1 1 1 0 0 0 1 1 E3 Description The low order byte contained in register pair HL is exchanged with the contents of the memory address specified by the contents of register pair SP Stack Pointer and the high order byte of HL is exchanged with the next highest me
81. Example If the Accumulator contents are 29h and the D Register contains 11h then upon the exe cution of a SUB D instruction the Accumulator contains 18h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 153 SBCA s Operation A A s CY Op Code SBC Operands A S The s operand is any of r n HL IX d or IY d as defined for the analogous ADD instructions These possible op code operand combinations are assembled as follows in the object code SBCA r 1 0 0 1 1 a r gt SBC A n 1 1 0 1 1 1 1 o DE SBC A HL 1 0 0 1 1 1 1 10 9E SBC A IX d A o oon LB od T BB SBC A IY d 1 4 4 4 44 4 0 7 1 FD UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 154 BIXYS Comp r identifies registers B C D E H L or A assembled as follows in the object code field Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description The s operand along with the Carry flag C in the F Register is subtracted from the con tents of the Accumulator and the result is stored in the Accumulator Instruction M Cycles T States 4 MHz E T SBC A r 1 4 1 00 SBC A n 2 7 4 3 1 75 SBC A HL 2 7 4 3 1 75 SBC A IX d 5 19 4 4 3 5 3 4 75 SBC A IY d 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative otherwise it is
82. Ilog nIXYS 17 T1 T2 T3 T4 T1 T2 TWA TWA HALT Figure 15 Power Down Release Cycle 3 of 3 Interrupt Response An interrupt allows peripheral devices to suspend CPU operation and force the CPU to start a peripheral service routine This service routine usually involves the exchange of data status or control information between the CPU and the peripheral When the service routine is completed the CPU returns to the operation from which it was interrupted Interrupt Enable Disable The Z80 CPU contains two interrupt inputs a software maskable interrupt INT and a nonmaskable interrupt NMI The nonmaskable interrupt cannot be disabled by the pro grammer and is accepted when a peripheral device requests it This interrupt is generally reserved for important functions that can be enabled or disabled selectively by the pro grammer This routine allows the programmer to disable the interrupt during periods when the program contains timing constraints that wont allow interrupt In the Z80 CPU there is an interrupt enable flip flop IFF that is set or reset by the programmer using the Enable Interrupt EI and Disable Interrupt DI instructions When the IFF is reset an interrupt cannot be accepted by the CPU The two enable flip flops are IFF1 and IFF2 as depicted in Figure 16 IFF1 IFF2 Disables interrupts Temporary storage from being accepted location for IFF1 Figure 16 Interrupt Enable Flip Flops
83. Input Output Request output active Low tristate IORQ indicates that the lower half of the address bus holds a valid I O address for an I O read or write operation IORQ is also generated concurrently with M1 during an interrupt acknowledge cycle to indicate that an interrupt response vector can be placed on the data bus M1 Machine Cycle One output active Low MI together with MREQ indicates that the current machine cycle is the op code fetch cycle of an instruction execution M1 when operating together with IORQ indicates an interrupt acknowledge cycle MREQ Memory Request output active Low tristate MREQ indicates that the address bus holds a valid address for a memory read or a memory write operation NMI Nonmaskable Interrupt input negative edge triggered NMI contains a higher pri ority than INT NMI is always recognized at the end of the current instruction indepen dent of the status of the interrupt enable flip flop and automatically forces the CPU to restart at location 0066h RD Read output active Low tristate RD indicates that the CPU wants to read data from memory or an I O device The addressed I O device or memory should use this signal to gate data onto the CPU data bus RESET Reset input active Low RESET initializes the CPU as follows it resets the interrupt enable flip flop clears the Program Counter and registers I and R and sets the interrupt status to Mode 0 During reset time the
84. LD A nn Operation A lt nn Op Code LD Operands A nn lt a n ra n Description The contents of the memory location specified by the operands nn are loaded to the Accu mulator The first n operand after the op code is the low order byte of a 2 byte memory address M Cycles T States 4 MHz E T 4 13 4 3 3 3 3 25 Condition Bits Affected None Example If nn contains 8832h and memory address 8832h contains byte 04h then upon the execu tion of an LD A nn instruction the 04n byte is in the Accumulator Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 89 LD BC A Operation BC A Op Code LD Operands BC A 0 0 00 0 0 1 o 02 Description The contents of the Accumulator are loaded to the memory location specified by the con tents of the register pair BC M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Example If the Accumulator contains 7Ah and the BC register pair contains 1212h the instruction LD BC A results in 7Ah in memory location 1212h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Z n1 ILU hos DIXYS LD DE A Operation DE A Op Code LD Operands DE A 0 0 0 1 0 0 1 0 12 Description The contents of the Accumulator are loaded to t
85. LD A R instruction is executed the state of IFF2 is copied to the parity flag where it can be tested or stored A second method of restoring the status of IFF1 is through the execution of a Return From Nonmaskable Interrupt RETN instruction This instruction indicates that the nonmask able interrupt service routine is complete and the contents of IFF2 are now copied back into IFF1 so that the status of IFF1 just prior to the acceptance of the nonmaskable inter rupt is restored automatically Table 1 is a summary of the effect of different instructions on the two enable flip flops Table 1 Interrupt Enable Disable Flip Flops Action IFF1 IFF2 Comments CPU Reset 0 O Maskable interrupt INT disabled DI Instruction Execution 0 O Maskable INT disabled EI Instruction Execution 1 1 Maskable INT enabled LD A I Instruction E IFF2 Parity flag Execution LD A R instruction li IFF2 Parity flag Execution Architectural Overview UM008006 0714 Z80 CPU User Manual Zilog BIXYS Table 1 Interrupt Enable Disable Flip Flops Continued Action IFF1 IFF2 Comments Accept NMI 0 T Maskable Interrupt RETN Instruction IFF2 i IFF2 Indicates completion of Execution nonmaskable interrupt service routine CPU Response The CPU always accepts a nonmaskable interrupt When this nonmaskable interrupt is accepted the CPU ignores the next instruction that it fetches and instead performs a re
86. PU Register The Z80 CPU contains 208 bits of read write memory that are available to the program mer Figure 2 shows how this memory is configured to eighteen 8 bit registers and four 16 bit registers All Z80 CPU s registers are implemented using static RAM The registers include two sets of six general purpose registers that can be used individually as 8 bit reg isters or in pairs as 16 bit registers There are also two sets of Accumulator and Flag regis ters and six special purpose registers Main Register Set Alternate Register Set NA Accumulator Flags Accumulator Flags A F A F B c B B General D E D E Purpose H L H L Register Interrupt Vector Memory Refresh R Index Register IX Special Purpose Index Register IY Registers Stack Pointer SP Program Counter PC Figure 2 CPU Register Configuration Special Purpose Registers Program Counter PC The program counter holds the 16 bit address of the current instruction being fetched from memory The Program Counter is automatically incre mented after its contents are transferred to the address lines When a program jump occurs the new value is automatically placed in the Program Counter overriding the incrementer Stack Pointer SP The stack pointer holds the 16 bit address of the current top of a stack located anywhere in external system RAM memory The external stack memory is orga nized as a l
87. R M Cycles T States MHz E T 2 9 4 5 2 25 Condition Bits Affected None UM008006 0714 Z80 Instruction Description 96 Z80 CPU User Manual ion ZILOgd BIXYS 16 Bit Load Group The following 16 bit load instructions are each described in this section Simply click to jump to an instruction s description to learn more LD dd nn see page 97 LD IX nn see page 98 LD IY nn see page 99 LD HL nn see page 100 LD dd nn see page 101 LD IX nn see page 103 LD IY nn see page 104 LD nn HL see page 105 LD mn dd see page 106 LD nn IX see page 108 LD nn IY see page 109 LD SP HL see page 110 LD SP IX see page 111 LD SP IY see page 112 PUSH qq see page 113 PUSH IX see page 115 PUSH IY see page 116 POP qq see page 117 POP IX see page 119 POP IY see page 120 Z80 Instruction Set UM008006 07 14 LD dd nn Operation dd nn Op Code LD Operands dd nn Description Z80 CPU User Manual ZIlOg DIXYS The 2 byte integer nn is loaded to the dd register pair in which dd defines the BC DE HL or SP register pairs assembled as follows in the object code Pair BC DE HL SP The first n operand after the op code is the low order byte M Cycles 2 Condition Bits Affected None Example dd 00 01 10 11 T States 10 4 3 3
88. S Comp r identifies registers B C D E H L or A specified in the assembled object code field as follows Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description The logical exclusive OR operation is performed between the byte specified by the s oper and and the byte contained in the Accumulator the result is stored in the Accumulator Instruction M Cycles T States 4 MHz E T XOR r 1 4 1 00 XOR n 2 7 4 3 1 75 XOR HL 2 7 4 3 1 75 XOR IX d 5 19 4 4 3 5 3 4 75 XOR IY d 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is reset P V is set if parity even otherwise it is reset N is reset C is reset Example If the Accumulator contains 96h 1001 0110 then upon the execution of an XOR 5Dh 5Dh 0101 1101 instruction the Accumulator contains CBh 1100 1011 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 161 CP s Operation A s Op Code CP Operand S The s operand is any of r n HL IX d or IY d as defined for the analogous ADD instructions These possible op code operand combinations are assembled as follows in the object code CP r 1 0 1 1 1 a rm gt CPn T d 4 14 110 FE CP HL 1 0 1 13 1 1 1 oO BE CP IX d 1110 11 14 44 0 14 DD CP IY d 4
89. Stack Pointer register pair SP loading the high order byte of the PC con tents to the memory address now pointed to by the SP then decrementing SP again and loading the low order byte of the PC contents to the top of stack Because this process is a 3 byte instruction the Program Counter was incremented by three before the push is executed M Cycles T States 4 MHz E T 5 17 4 3 4 3 3 4 25 Condition Bits Affected None Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nixYs 279 Example The Program Counter contains 1A47h the Stack Pointer contains 3002h and memory locations contain the following data Location Contents 1A47h CDh 1A48h 35h 1A49h 21h If an instruction fetch sequence begins the 3 byte instruction CD 3521h is fetched to the CPU for execution The mnemonic equivalent of this instruction is CALL 2135h Upon the execution of this instruction memory address 3001h contains 1Ah address 3000h contains 4Ah the Stack Pointer contains 3000h and the Program Counter contains 2135h thereby pointing to the address of the first op code of the next subroutine to be executed UMO08006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 280 GIXYS Comp CALL cc nn Operation IF cc true sp 1 PCH sp 2 PCL pc nn Op Code CALL Operands cc nn The first of the two n operands in the assembled object c
90. This chapter provides a description of the assembly language instructions available with the Z80 CPU Z80 Assembly Language Assembly language allows the user to write a program without concern for memory addresses or machine instruction formats It uses symbolic addresses to identify memory locations and mnemonic codes op codes and operands to represent the instructions Labels symbols are assigned to a particular instruction step in a source program to iden tify that step as an entry point for use in subsequent instructions Operands following each instruction represent storage locations registers or constant values The assembly lan guage also includes assembler directives that supplement the machine instruction A pseudo op for example is a statement that is not translated to a machine instruction but rather is interpreted as a directive that controls the assembly process A program written in assembly language is called a source program which consists of symbolic commands called statements Each statement is written on a single line and can consist of one to four entries A label field an operation field an operand field and a com ment field The source program is processed by the assembler to obtain a machine lan guage program object program that can be executed directly by the Z80 CPU Zilog provides several assemblers that differ in the features offered Both absolute and relocatable assemblers are available with the Develop
91. YS Operation PC PC e Op Code JR Operand e Description This instruction provides for unconditional branching to other segments of a program The value of displacement e is added to the Program Counter PC and the next instruction is fetched from the location designated by the new contents of the PC This jump is mea sured from the address of the instruction op code and contains a range of 126 to 129 bytes The assembler automatically adjusts for the twice incremented PC M Cycles T States 4 MHz E T 3 12 4 3 5 3 00 Condition Bits Affected None Example To jump forward five locations from address 480 the following assembly language state ment is used JR 5 The resulting object code and final Program Counter value is shown in the following table Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZzIlog nIXYS 263 Location Instruction 480 18 481 03 482 483 484 485 PC after jump UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZIlog 264 nDIXYS Operation If C 2 0 continue If CZ1 PC PC e Op Code JR Operands C e Description This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Carry Flag If the flag 1 the value of displace ment e is added to the Program Counter PC and the nex
92. Zilog Embedded in Life AnEITXYS Company Z80 Microprocessors Z80 CPU User Manual UM008006 0714 Copyright 2014 Zilog Inc All rights reserved www zilog com Z80 CPU User Manual J j A ry ILV UG BIXYS N Warning DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS LIFE SUPPORT POLICY ZILOG S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION As used herein Life support devices or systems are devices which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user A criti cal component is any component in a life support device or system whose failure to perform can be reason ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Document Disclaimer 2014 Zilog Inc All rights reserved Information in this publication concerning the devices applications or technology described is intended to suggest possible uses and may be superseded ZILOG INC DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION DEVICES OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT ZILOG ALSO
93. aced on the top of the push down stack pointed to by SP When a subroutine returns to the calling routine the address on the top of the stack is used to set the program counter for the address of the next instruction The stack pointer is adjusted automatically to reflect the current top stack position during PUSH POP CALL and RET instructions This stack mechanism allows pushdown data stacks and subroutine calls to be nested to any practical depth because the stack area can potentially be as large as memory space The sequence of instruction execution can be controlled by six different flags carry zero sign parity overflow add subtract half carry which reflect the results of arithmetic log ical shift and compare instructions After the execution of an instruction that sets a flag that flag can be used to control a conditional jump or return instruction These instructions provide logical control following the manipulation of single bit 8 bit byte or 18 bit data quantities A full set of logical operations including AND OR XOR exclusive OR CPL NOR and NEG two s complement are available for Boolean operations between the Accumu lator and all other 8 bit registers memory locations or immediate operands In addition a full set of arithmetic and logical shifts in both directions are available which operate on the contents of all 8 bit primary registers or directly on any memory location The carry flag can be included or
94. age 70 LD r HL see page 72 LD r X d see page 73 LD r Y d see page 75 LD HL r see page 77 LD 1X d r see page 79 LD IY 4d r see page 81 LD HL n see page 83 LD IX d n see page 84 LD 1Y d n see page 85 LD A BC see page 86 LD A DE see page 87 LD A nn see page 88 LD BC A see page 89 LD DE A see page 90 LD nn A see page 91 LD A I see page 92 LD A R see page 93 LD LA see page 94 LD R A see page 95 Z80 Instruction Set UM008006 0714 LDr r Z80 CPU User Manual ZItog DIXYS Operation rr Op Code LD Operands rr Description The contents of any register r are loaded to any other register r r r identifies any of the registers A B C D E H or L assembled as follows in the object code Register rnc A 111 000 001 010 011 100 101 r TI moosu M Cycles T States MHz E T 1 4 1 0 Condition Bits Affected None Example If the H Register contains the number 8Ah and the E register contains 10h the instruction LD H E results in both registers containing 10h UM008006 0714 Z80 Instruction Description 69 Z80 CPU User Manual zZ ILon ILL Y 70 nIXYS LD r n Operation ren Op Code LD Operands rn Description The 8 bit integer n is loaded to any register r in which r id
95. ansfer instructions These instructions operate with three registers e HL points to the source location e DE points to the destination location e BC isa byte counter UM008006 0714 Block Transfer and Search Z80 CPU User Manual ZIlog 46 IXYS Comp Table 8 Block Transfer Group Destination Source Register DE Register Indirect Indirect HL ED LDI Load DE HL AO Inc HL and DE Dec BC ED LDIR Load DE gt HL BO Inc HL and DE Dec BC repeat until BC 0 ED LDD Load DE HL A8 Inc HL and DE Dec BC ED LDDR Load DE gt HL B8 Dec HL and DE Dec BC repeat until BC 0 Note Register HL points to the source the DE Register points to the destination the BC Register is a byte counter After the programmer initializes these three registers any of these four instructions can be used The Load and Increment LDI instruction moves one byte from the location pointed to by HL to the location pointed to by DE Register pairs HL and DE are then automati cally incremented and are ready to point to the following locations The byte counter 1 e register pair BC is also decremented at this time This instruction is valuable when the blocks of data must be moved but other types of processing are required between each move The Load Increment and Repeat LDIR instruction is an extension of the LDI instruction The same load and increment operation is r
96. ast in first out LIFO file Data can be pushed onto the stack from specific CPU registers or popped off of the stack to specific CPU registers through the execution of PUSH and POP instructions The data popped from the stack is always the most recent data pushed onto it The stack allows simple implementation of multiple level interrupts unlimited subroutine nesting and simplification of many types of data manipulation Architectural Overview UM008006 0714 Z80 CPU User Manual Zilog OIXYS Two Index Registers IX and IY The two independent index registers hold a 16 bit base address that is used in indexed addressing modes In this mode an index register is used as a base to point to a region in memory from which data is to be stored or retrieved An addi tional byte is included in indexed instructions to specify a displacement from this base This displacement is specified as a two s complement signed integer This mode of addressing greatly simplifies many types of programs especially when tables of data are used Interrupt Page Address I Register The Z80 CPU can be operated in a mode in which an indirect call to any memory location can be achieved in response to an interrupt The I register is used for this purpose and stores the high order eight bits of the indirect address while the interrupting device provides the lower eight bits of the address This feature allows interrupt routines to be dynamically located anywhere in memory
97. ata OFFEh 51h OFFFh A9h 1000h 03h Upon the execution of an OTDR instruction the HL register pair contain OFFDh Register B contains a 0 and a group of bytes is written to the peripheral device mapped to I O port address 07h in the following sequence 03h A9h 51h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZIlog 314 DIXYS Customer Support To share comments get your technical questions answered or report issues you may be experiencing with oulr products please visit Zilog s Technical Support page at http support zilog com To learn more about this product find additional documentation or to discover other fac ets about Zilog product offerings please visit the Zilog Knowledge Base at http zilog com kb or consider participating in the Zilog Forum at http zilog com forum This publication is subject to replacement by a later edition To determine whether a later edition exists please visit the Zilog website at http www zilog com Customer Support UMO08006 0714
98. ation 1005h contains 22h then upon the execution of an ADD A IX 5h instruction the Accumulator contains 33h UM008006 0714 Z80 Instruction Description 148 Z80 CPU User Manual Z T On ILU y OLXYS ADD A IY d Operation A A 1Y d Op Code ADD Operands A IY d Description The contents of the Index register pair IY Register is added to a two s complement dis placement d to point to an address in memory The contents of this address is then added to the contents of the Accumulator and the result is stored in the Accumulator M Cycles T States 4 MHz E T 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is set if carry from bit 3 otherwise it is reset P V is set if overflow otherwise it is reset N is reset C is set if carry from bit 7 otherwise it is reset Example If the Accumulator contains 11h Index Register IY contains 1000h and memory location 1005h contains 22h then upon the execution of an ADD A IY 5n instruction the Accumulator contains 33h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual zilog nIXYS 149 ADC A s Operation A A c stCY Op Code ADC Operands A S This s operand is any of r n HL IX d or IY d as defined for the analogous ADD instruction These possible op
99. ation During I O operations a single wait state is automatically inserted The reason for this single wait state insertion is that during I O operations the period from when the IORQ signal goes active until the CPU must sample the WAIT line is short Without this extra state sufficient time does not exist for an I O port to decode its address and activate the WAIT line if a wait is required Addition ally without this wait state it is difficult to design MOS I O devices that can operate at full CPU speed During this wait state period the WAIT request signal is sampled During a read I O operation the RD line is used to enable the addressed port onto the data bus just as in the case of a memory read The WR line is used as a clock to the I O port for write operations Architectural Overview UM008006 0714 Z80 CPU User Manual ZIlOg nIXYS 11 CLK A15 A0 D7 DO WAIT Figure 7 Input or Output Cycles Note In Figure 7 TW is an automatically inserted WAIT state Bus Request Acknowledge Cycle Figure 8 shows the timing for a Bus Request Acknowledge cycle The BUSREQ signal is sampled by the CPU with the rising edge of the most recent clock period of any machine cycle If the BUSREQ signal is active the CPU sets its address data and tristate control signals to the high impedance state with the rising edge of the next clock pulse At that time any external device can control the buses to transfer data betw
100. ation i ia aredscntd anid sorda Dea Pee das a Shed Bila 53 Jump Call and Return 0 0 0 een enn 56 Input Output 21r A A ti Pia ede eae Hte dE eg e 59 CPU Control Group 6 0 ence m 61 Z80 Instr ction Set eas eins dnote raso eso denen deb sob reed d e bed pad 63 Z80 Assembly Language seeeeeeee I I 63 Z80 Status Indicator Flags sseeeeeeee eh 63 Carry Hae socia egit yit lea dade dibus eae da ate Sce 64 Add Subtract Flag8 o oooocoococcocococon e eens 64 Decimal Adjust Accumulator Flag 0 0 0 eee eee eee eee 65 Parity Overtlow Flag vacio tek aaa bk ERREUR e ed hee es RR dea 65 Half Carry Flag cion Acus cee ee AR RI ERE YU pee ts 66 Zeto Blag 2e od obse dado ede da ERU eso ea Dna eati oe a 66 Sign Bldg ossis exta io a meta E nter ed latas 67 Z80 Instruction Description sseeeeee ee eee 67 DEDE E oer O A s 69 LEDtf eua mese Es nee te E Ede auia ah deii abate s eos s 70 A A oath eo ERE EUER pepe doe ete 72 LED OE kos cttta st Sa eben aros tes slaw did Rec PER aO eden eee 73 LD t CX 2s eau tie ee hee ae he 75 A A das ble eon Reus e eae kes TI LD UX40 Cm 79 PA A Bae RESET EE 81 LD HL M MP 83 CD IX Fd Pm 84 Table of Contents UM008006 0714 UM008006 0714 Z80 CPU User Manual Zilog OIXYS MY NE ac ts ether ee ee We ee T 85 LD Aj BO it i5 dh Ohi eho ee edhe E ie eh ee ed 86 LD Ay DB ni e eee oda See CERES Ko Vl AG he Oe Cees 87 LDA nf a etch ed Ponc
101. block transfer and search group instructions are each described in this section Simply click to jump to an instruction s description to learn more EX DE HL see page 122 EX AF AF see page 123 EXX see page 124 EX SP HL see page 125 EX SP IX see page 126 EX SP IY see page 127 LDI see page 128 LDIR see page 130 LDD see page 132 LDDR see page 134 CPI see page 136 CPIR see page 137 CPDR see page 140 UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Z i Ory ILU y 122 DIXYS EX DE HL Operation DE HL Op Code EX Operands DE HL 1 1 1 0 1 0 1 1 EB Description The 2 byte contents of register pairs DE and HL are exchanged M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None Example If register pair DE contains 2822h and register pair HL contains 499Ah then upon the execution of an EX DE HL instruction register pair DE contains 499Ah and register pair HL contains 2822h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZItog nIXYS 123 EX AF AF Operation AF AF Op Code EX Operands AF AF 0 0 0 0 1 0 0 0 08 Description The 2 byte contents of the register pairs AF and AF are exchanged Register pair AF con sists of registers A and F M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None
102. c setting of the Flag Register making additional operations unnecessary to determine the state of the input data The parity state is one example The Z80 CPU includes single instructions that can move blocks of data up to 256 bytes automatically to or from any I O port directly to any memory location In conjunction with the dual set of general purpose registers these instructions provide fast I O block transfer rates The power of this I O instruction set is demonstrated by the Z80 CPU providing all required floppy disk formatting on double density floppy disk drives on an interrupt driven basis For example the CPU provides the preamble address data and enables the CRC codes Finally the basic CPU control instructions allow multiple options and modes This group includes instructions such as setting or resetting the interrupt enable flip flop or setting the mode of interrupt response UMO008006 0714 Instruction Types 33 Z80 CPU User Manual Z T On ILU y 34 OIXYS Addressing Modes Most of the Z80 instructions operate on data stored in internal CPU registers external memory or in the I O ports Addressing refers to how the address of this data is generated in each instruction This section is a brief summary of the types of addressing used in the Z80 CPU while subsequent sections detail the type of addressing available for each instruction group Immediate Addressing In the Immediate Addressing Mode the byte followin
103. ch as the Logical OR instruction are represented by a one operand mnemonic Instructions that contain two varying operands are represented by two operand mnemonics Load and Exchange Table 5 defines the op codes for all of the 8 bit load instructions implemented in the Z80 CPU Also described in this table is the type of addressing used for each instruction The source of the data is found on the top horizontal row and the destination is specified in the left column For example load Register C from Register B uses the op code 48h In all of the figures the op code is specified in hexadecimal notation and the 48h 0100 1000 binary code is fetched by the CPU from external memory during M1 time decoded and then the register transfer is automatically performed by the CPU The assembly language mnemonic for this entire group is LD followed by the destination followed by the source LD DEST SOURCE gt Note Several combinations of addressing modes are possible For example the source can use register addressing and the destination can be registered indirect such as load the memory location pointed to by Register HL with the contents of the D Register The op code for this operation is 72 The mnemonic for this load instruction is LD AL D UMO008006 0714 Load and Exchange Z80 CPU User Manual zilog 40 nIXYS Table 5 8 Bit Load Group LD Source Implied Register Reg Indirect Index
104. code operand combinations are assembled as follows in the object code ADC A r 1 0 0 0 1 lt r gt ADC A n 1 1 00 1 1 1 0 CE ADC A HL to 0 0 1 1 1 0 8E ADC A IX d 1 110 1 1 1 1 o DD ADC A IY d 111114 14 14 14po0 4 14 FD UMO08006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 150 IXYS Comp r identifies registers B C D E H L or A assembled as follows in the object code field Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description The s operand along with the Carry Flag C in the F Register is added to the contents of the Accumulator and the result is stored in the Accumulator Instruction M Cycle T States 4 MHz E T ADCA r 1 4 1 00 ADCA n 2 7 4 3 1 75 ADC A HL 2 7 4 3 1 75 ADC A IX d 5 19 4 4 3 5 3 4 75 ADC A IY d 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is set if carry from bit 3 otherwise it is reset P V is set if overflow otherwise it is reset N is reset C is set if carry from bit 7 otherwise it is reset Example If the Accumulator contents are 16h the Carry Flag is set the HL register pair contains 6666h and address 6666h contains 10h then upon the execution of an ADC A HL instruction the Accumulat
105. d RETURN instructions are used to transfer between multiple loca tions in the user s program This group uses several different techniques for obtaining the new program counter address from specific external memory locations A unique type of call is the RESTART instruction This instruction actually contains the new address as a part of the 8 bit op code This instruction is possible because only eight separate addresses located in Page 0 of external memory can be specified Program jumps can also be achieved by loading Register HL IX or IY directly into the Program Counter which allows the jump address to be a complex function of the routine being executed The input output group of instructions in the Z80 CPU allow for a wide range of transfers between external memory locations or the general purpose CPU registers and the external I O devices In each case the port number is provided on the lower eight bits of the address bus during any I O transaction One instruction allows this port number to be specified by the second byte of the instruction while other Z80 instructions allow it to be specified as the contents of the C Register One major advantage of using the C register as a pointer to the I O device is that it allows multiple I O ports to share common software driver routines This advantage is not possible when the address is part of the op code if the routines are stored in ROM Another feature of these input instructions is the auto mati
106. ding to the contents of SP then SP is incriminated and the con tents of the corresponding adjacent memory location are loaded to the high order portion of qq and the SP is now incriminated again The operand qq identifies register pair BC DE HL or AF assembled as follows in the object code Pair r BC 00 DE 01 HL 10 AF 11 M Cycles T States 4 MHz E T 3 10 4 3 3 2 50 Condition Bits Affected None UM008006 0714 Z80 Instruction Description 117 Z80 CPU User Manual Zilog 118 IXYS Corp Example If the Stack Pointer contains 1000h memory location 1000h contains 55h and location 1001h contains 33h the instruction POP AL results in register pair HL containing 3355h and the Stack Pointer containing 1002h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZzIlog nIXYS 119 POP IX Operation IXH SP 1 IXL SP Op Code POP Operand IX Description The top two bytes of the external memory last in first out LIFO stack are popped to Index Register IX The Stack Pointer SP Register pair holds the 16 bit address of the current top of the Stack This instruction first loads to the low order portion of IX the byte at the memory location corresponding to the contents of SP then SP is incremented and the contents of the corresponding adjacent memory location are loaded to the high order portion of IX The SP is incremented again M Cycles T States 4 MH
107. e Z80 CPU User Manual ZzIlog DIXYS e 2 Description This instruction is similar to the conditional jump instructions except that a register value is used to determine branching Register B is decremented and if a nonzero value remains the value of displacement e is added to the Program Counter PC The next instruction is fetched from the location designated by the new contents of the PC The jump is measured from the address of the instruction op code and contains a range of 126 to 129 bytes The assembler automatically adjusts for the twice incremented PC If the result of decrementing leaves B with a zero value the next instruction executed is taken from the location following this instruction if B Z0 M Cycles 3 If B 2 0 M Cycles 2 UM008006 0714 T States 13 5 3 5 T States 8 5 3 4 MHz E T 3 25 4 MHz E T 2 00 Z80 Instruction Description 275 Z80 CPU User Manual Zilog 276 DIXYS Comp Condition Bits Affected None Example A typical software routine is used to demonstrate the use of the DJNZ instruction This routine moves a line from an input buffer INBUF to an output buffer OQUTBUP It moves the bytes until it finds a CR or until it has moved 80 bytes whichever occurs first LD 8 80 Set up counter LD HL Inbuf Set up pointers LD DE Outbuf LOOP LID A HL Get next byte from input buffer LD DE
108. e During the execution of this instruction and the following instruction maskable interrupts are disabled M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None Example When the CPU executes an EI RETI instruction the maskable interrupt is enabled then upon the execution of an the RETI instruction UM008006 0714 Z80 Instruction Description 182 Z80 CPU User Manual Z i ena BLU y OIXYS IM 0 Operation Set Interrupt Mode 0 Op Code IM Operand 0 Description The IM 0 instruction sets Interrupt Mode 0 In this mode the interrupting device can insert any instruction on the data bus for execution by the CPU The first byte of a multi byte instruction is read during the interrupt acknowledge cycle Subsequent bytes are read in by a normal memory read sequence M Cycles T States 4 MHz E T 2 8 4 4 2 00 Condition Bits Affected None Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 183 IM 1 Operation Set Interrupt Mode 1 Op Code IM Operand 1 Description The IM 1 instruction sets Interrupt Mode 1 In this mode the processor responds to an interrupt by executing a restart at address 0038h M Cycles T States 4 MHz E T 2 8 4 4 2 00 Condition Bits Affected None UM008006 0714 Z80 Instruction Description 184 Z80 CPU User Manual Z i ena BLU y OLXYS
109. e Paco Poe TO A a aa da 88 LD BC Avy cere ete eee dra 89 EDADE A ete ener E M E 90 ED nt A ur RETE whee Deas ele Gs ote ad wate Gate 91 EDA ains a a Dato diee lala i 92 LDA R essa aida arado na Aa 93 EDO A i oa cio 94 EDU ad ii 95 ED dd Di isa a A eka e Seed 97 LDL UPC 98 ISD VY Bi oo eda ipe A AS A E arid A Eu eo 99 LO HL nn 12d ete e obe ds da rad dea coe 100 A 101 LDIX nii da da 103 EDEMA ERO S 104 LED nn HE eb eh Soa eu ERU edu vidus ve ddr vod 105 LD nn dd o rt te doc eno RR PRETI eee 106 ED nfi EX 4 eret baee p eoe suba a aoa cR eae 108 LED nn IY oue acces roe te ce t ERE be RR Ie te Eds 109 LD SP HL ii4ddasueiaw Mp3 dee RS Gao ep aa ie eda 110 CDSP DE oe vedere UR EMI LUE RUIN tees 111 EDSEP IY osse OE NM E use e LEES MEE 112 PUSH qq iones hee eti ti eR E hao bs Ek der de ee 113 PUSELIX ia 115 PUSH IY ei elwxbORR a Yep ren ao ds 116 POP QQ 12 eee dd wea debut De di da lee 117 POR qc 119 POP TY iki eet anh Xe qu ve iS niea qus Eas eee ae 120 BPX DESHE piores oe ne A EE E E at EHI SE 122 EX AE AF 938 3 4 cists eiaa Hes hee ee dea E ans da da 123 EXX T TT 124 EX SD HL bU at 125 EX SB IX dne ida Aa Wed E EP Edd 126 EXISPIIO 127 A Er E EE E A E E E A S 128 CDIR reires ettemme ada ia 130 LDD crisis dida dias es ridad 132 DDR a 134 Table of Contents vii viii Z80 CPU User Manual Zilog OIXYS Table of Contents O E SN E 136 A pedals sad a ede ec ee
110. e analogous RLC instructions In the assembled object code the possible op code operand combinations are specified as follows RR r 111o 0 0 0 RR HL 1 11 0 0 0 0 RR IX d 11110 Lisa ra 0 0 0 RR IY d 1 4 14 11110 ra 0 0 0 CB CB DD CB FD CB Z80 Instruction Description 225 Z80 CPU User Manual Zilog 226 nIXYS r identifies registers B C D E H L or A assembled as follows in the object code field Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description The contents of operand m are rotated right 1 bit position through the Carry flag The con tents of bit 0 are copied to the Carry flag and the previous contents of the Carry flag are copied to bit 7 Bit 0 is the least significant bit Instruction M Cycles T States 4 MHz E T RRr 2 8 4 4 2 00 RR HL 4 15 4 4 4 3 3 75 RR IX d 6 23 4 4 3 5 4 3 5 75 RR IY d 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is reset P V is set if parity even otherwise it is reset N is reset C is data from bit 0 of source register Example The HL register pair contains 4343h and memory location 4343h and the Carry
111. ea edd 272 A E AN 273 JPDY AA A cle E HE A ee 274 DD a xd 275 CALG MM xi ebcwunexeiauep aia cda 278 CALLE iii 280 Table of Contents X Z80 CPU User Manual zilog OIXYS RET iii tn deen p ORT tu tede C ga de se E 282 RET CC Em 283 RETI ui a A A 285 RETN 25e aga diodo Pee t da ae as 287 RSE Daute denen ao Lae eda das idee ea tate 289 INA D cerent ea eee eee bee eee eee ace 292 INT inicio bee ee hao ea ee eb eg e ea ced 293 INT urinaria ad E E Dites a E artes tuns 295 A E armed 297 IND A x 299 INDR sarria a dis leave oe eee 301 OUT Qi yA Em 303 OUT C T ice ck este te prete Pd toe sto poe etapa aci dae 304 OUTI oca LEE 306 OLIR Lise decidere temi ea dites Re debui edet Eod 308 QUID is i200 65 mind ra nee ibe dr UP vaa bes en EPA Cd ibd ands 310 OIDO Ru hehe bt eet eae dads i aie oda Rowe hace da 312 Customer SUpPPOMl so estou dew set kao epus qr UR e dat bee ee eee eke 314 Table of Contents UMO008006 0714 Z80 CPU User Manual Zilog OIXYS List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 UM008006 0714 Z80 CPU Block Diagram 1 0 ete eens 1 CPU Register Configuration 0
112. ed Ext Imm Destination l R A B C D E FL V HL BC DE IX d IY d Inn n Register ED ED FD DD FD FD A 7F 78 79 7A 7B 7C 7D 7E OA 1A 7E 7E 3A 2E 57 5F d d nn n DD FD DD B 47 40 41 42 43 44 45 46 46 46 D5 d d n DD FD DD C 4F 48 49 4A 4B 4C 4D 4E 4E 4E DE d d n DD FD DD D 57 50 51 52 53 54 55 56 56 56 1B d d n DD FD DD E 5F 58 59 5A 5B 5C BD 5E 5E 5E 1E d d n DD FD DD H 67 60 61 62 63 64 65 66 66 66 2B d d n DD FD DD L 6F 68 69 6A 6B 6C 6D 6E 6E 6E 36 d d n Register DD Indirect HL 77 70 71 72 73 74 75 78 D BC 02 DE 12 mgexga DD DD DD DD DD DD DD ae IX d 77 70 71 72 73 74 75 d did d d d d d n FD FD FD FD FD FD FD de IY d 77 70 71 72 73 74 75 d djd d d d dd B Ext Addr 32 nn n n Implied ED 47 ED i 4F Z80 CPU Instructions UM008006 0714 Z80 CPU User Manual Zilog nIXYS 41 Note Descriptions of the 8 Bit Load Group instructions begin on page 68 The parentheses around the HL indicate that the contents of HL are used as a pointer to a memory location In all Z80 load instruction mnemonics the destination is always listed first with the source following The Z80 assembly language is defined for ease of pro gramming Every instruction is self documenting and programs written in Z8
113. ed Instruction Sequence In this figure note that the low order portion of the address is always the first operand The load immediate instructions for the general purpose 8 bit registers are two byte instructions The instruction for loading Register H with the value 36h is written as LD H 36h The instruction sequence for this value in memory is shown in Figure 34 Address A 26 Op Code A 1 36 Operand Figure 34 Example of a 2 Byte Load Immediate Instruction Sequence Loading a memory location using indexed addressing for the destination and immediate addressing for the source requires four bytes For example LD Ix 15j 21h The instruction sequence for this value in memory is shown in Figure 35 Address A DD m gt Op Code A 1 36 A 2 F1 One or Two Bytes __ Displacement 15 in Signed A 3 21 Two s Complement Operand to Load Figure 35 Example of a 4 Byte Load Indexed Immediate Instruction Sequence Z80 CPU Instructions UM008006 0714 PUSH Instructions gt Z80 CPU User Manual ZIlOg nIXYS 43 In this figure note that with any indexed addressing the displacement always follows directly after the op code Table 6 specifies the 16 bit load operations for which the extended addressing feature covers all register pairs Register indirect operations specifying the stack pointer are the PUSH and POP instructions The mnemonic for these instructions is PUSH and POP Table 6 1
114. ed after each data transfer When the BC is set to O prior to instruction execution the instruction loops through 64 KB For BC z 0 M Cycles T States 4 MHz E T 5 21 4 4 3 5 5 5 25 For BC 0 M Cycles T States 4 MHz E T 4 16 4 4 3 5 4 00 Condition Bits Affected S is not affected Z is not affected H is reset Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 131 P V is reset N is reset C is not affected Example The HL register pair contains 11111h the DE register pair contains 2222h the BC regis ter pair contains 0003h and memory locations contain the following data 1111h contains 88h 2222h contains 66h 1112h contains 36h 2223h contains 59h 1113h contains A5h 2224h contains C5h Upon the execution of an LDIR instruction the contents of register pairs and memory locations now contain HL contains 1114h DE contains 2225h BC contains 0000h 1111h contains 88h 2222h contains 88h 1112h contains 36h 2223h contains 36h 1113h contains A5h 2224h contains A5h UMO08006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOQd 132 nIXYS Operation DE HL DE DE 1 HL HL 1 BC BC 1 Op Code LDD Operands None Description This 2 byte instruction transfers a byte of data from the memory location addressed by the contents of the HL register pair to the memory location addres
115. ed from the address of the instruction op code and contains a range of 126 to 129 bytes The assembler auto matically adjusts for the twice incremented PC If the Zero Flag 1 the next instruction executed is taken from the location following this instruction If the condition 1s met M Cycles T States 4 MHz E T 3 12 4 3 5 3 00 If the condition is not met M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 271 Example The Zero Flag is reset and it is required to jump back four locations from 480 The assem bly language statement is JR NZ 4 The resulting object code and final Program Counter value is Location Instruction 47C PC after jump 47D 47E 47F 480 20 481 FA two s complement 6 UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Z T On BLU y 272 nIXYS JP HL Operation PC HL Op Code JP Operand HL 1 1 1 0 1 0107 1 E9 Description The Program Counter PC is loaded with the contents of the HL register pair The next instruction is fetched from the location designated by the new contents of the PC M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None Example If the Program Counter contains 1000h and the HL register pair contains 4800h then upon the execution of a JP HL in
116. een memory and I O devices This operation is generally known as Direct Memory Access DMA using cycle stealing The maximum time for the CPU to respond to a bus request is the length of a machine cycle and the external controller can maintain control of the bus for as many clock cycles as is required If long DMA cycles are used and dynamic memories are used the external controller also performs the refresh function This situation only occurs if UM008006 0714 Bus Request Acknowledge Cycle Z80 CPU User Manual Z il AN ILU y 12 OIXYS large blocks of data are transferred under DMA control During a bus request cycle the CPU cannot be interrupted by either an NMI or an INT signal Any M Cycle Bus Available Status 3 8 Last T State CLK BUSREQ BUSACK A15 A0 D7 DO MREQ RD WR IORQ RFSH Figure 8 Bus Request Acknowledge Cycle Interrupt Request Acknowledge Cycle Figure 9 shows the timing associated with an interrupt cycle The CPU samples the inter rupt signal INT with the rising edge of the final clock at the end of any instruction The signal is not accepted if the internal CPU software controlled interrupt enable flip flop is not set or if the BUSREQ signal is active When the signal is accepted a special M1 cycle is generated During this special M1 cycle the IORQ signal becomes active instead of the normal MREQ to indicate that the
117. eight addresses indicated in the following table The operand p is assembled to the object code using the corresponding T state Because all addresses are stored in Page 0 of memory the high order byte of PC is loaded with 00h The number selected from the p column of the table is loaded to the low order byte of PC p t 00h 000 08h 001 10h 010 18h 011 20h 100 28h 101 30h 110 38h 111 UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 290 IXYS Comp M Cycles T States 4 MHz E T 3 11 5 3 3 2 75 Example If the Program Counter contains 1583h then upon the execution of an RST 18h object code 1101111 instruction the PC contains 0018h as the address of the next fetched op code Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZItog nIXYS 291 Input and Output Group The following input and output group instructions are each described in this section Sim ply click to jump to an instruction s description to learn more IN A n see page 292 IN r C see page 293 INI see page 295 INIR see page 297 IND see page 299 INDR see page 301 OUT n A see page 303 OUT C r see page 304 OUTI see page 306 OTIR see page 308 OUTD see page 310 OTDR see page 312 UM008006 0714 Z80 Instruction Description 292 Z80 CPU User Manual Z T On ILUV y OIXYS IN A n Operation A n Op Code IN Operands A n
118. eneration enhanced microprocessors with exceptional computational power They offer higher system throughput and more efficient memory utilization than comparable second and third generation microproces sors The speed offerings from 6 20 MHz suit a wide range of applications which migrate software The internal registers contain 208 bits of read write memory that are accessible to the programmer These registers include two sets of six general purpose registers which can be used individually as either 8 bit registers or as 16 bit register pairs In addition there are two sets of Accumulator and Flag registers The Z80 CPU also contains a Stack Pointer Program Counter two index registers a refresh register and an interrupt register The CPU is easy to incorporate into a system because it requires only a single 5V power source All output signals are fully decoded and timed to control standard memory or peripheral circuits the Z80 CPU is supported by an extensive family of peripheral controllers Figure 1 shows the internal architecture and major elements of the Z80 CPU Data Bus Control Inst Heuisier lt Internal Data Bus gt ALU lt o 13 a and CPU CPU ystem L 3 Contro Control Registers ignals Address Control 16 Bit 45V GND CLK Address Bus Figure 1 Z80 CPU Block Diagram UM008006 0714 Architectural Overview Z80 CPU User Manual C
119. entifies registers A B C D E H or L assembled as follows in the object code Register r A 111 B 000 C 001 D 010 E 011 H 100 L 101 M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Z80 Instruction Set UM008006 0714 Z80 CPU User Manual zilog BIXYS Example Upon the execution of an LD E A5h instruction Register E contains A5h UM008006 0714 Z80 Instruction Description 71 Z80 CPU User Manual Z T On ILUV y DIXYS LD r HL Operation r HL Op Code LD Operands r HL Description The 8 bit contents of memory location HL are loaded to register r in which r identifies registers A B C D E H or L assembled as follows in the object code Register r A 111 B 000 C 001 D 010 E 011 H 100 L 101 M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Example If register pair HL contains the number 75A1h and memory address 75A1h contains byte 58h the execution of LD C HL results in 58h in Register C 780 Instruction Set UM008006 07 14 Z80 CPU User Manual ZIlOg nIXYS 73 LD r IX d Operation r 1X d Op Code LD Operands r IX d Description The 1X d operand i e the contents of Index Register IX summed with two s comple ment displacement integer d is loaded to register r in which r identif
120. epeated until the byte counter reaches the count of zero As a result this single instruction can move any block of data from one location to any other Because 16 bit registers are used the size of the block can be up to 64KB long 1KB 1024 bits and can be moved from any location in memory to any other location Furthermore the blocks can be overlapping because there are no constraints on the data used in the three register pairs The LDD and LDDR instructions are similar to LDI and LDIR The only difference is that register pairs HL and DE are decremented after every move so that a block transfer starts from the highest address of the designated block rather than the lowest Table 9 specifies the op codes for the four block search instructions The first CPI Com pare and Increment compares the data in the Accumulator with the contents of the mem ory location pointed to by Register HL The result of the compare is stored in one of the flag bits and the HL register pair is then incremented and the byte counter register pair BC is decremented Z80 CPU Instructions UM008006 0714 Z80 CPU User Manual ZItog DIXYS Table 9 Block Search Group Search Location Register Indirect HL ED CPI A1 Inc HL Dec BC ED CPRI Inc HL Dec BC B1 Repeat until BC 0 or find match ED AQ WD Dec HL and BC ED CPDR Dec HL and BC B9 Repeat until BC 0 or find match Note HL points to a location
121. ese cases two types of addressing can be employed For example load can use immediate addressing to specify the source and Register Indirect or indexed addressing to specify the destination Instruction Op Codes This section describes each of the Z80 instructions and provides tables listing the op codes for every instruction In each of these tables the op codes in shaded areas are identical to those offered in the 8080A CPU Also depicted is the assembly language mnemonic that is used for each instruction All instruction op codes are listed in hexadecimal notation Sin gle byte op codes require two hex characters while double byte op codes require four hex characters For convenience the conversion from hex to binary is repeated in Table 4 Table 4 Hex Binary Decimal Conversion Table Hex Binary Decimal 0000 0 0001 0010 0011 0100 0101 0110 O11 o oc fF WD HS o ll NO oO 20 m Z80 CPU Instructions UM008006 0714 Z80 CPU User Manual ZzIlog nIXYS 39 Table 4 Hex Binary Decimal Conversion Table Continued Hex Binary Decimal 8 1000 8 9 1001 9 A 1010 10 B 1011 11 C 1100 12 D 1101 13 E 1110 14 F 1111 15 The Z80 instruction mnemonics consist of an op code and zero one or two operands Instructions in which the operand is implied contains no operand Instructions that contain only one logical operand in which one operand is invariant su
122. eset C is not affected Example The HL register pair contains 5000h and the Accumulator and memory location 5000h contain the following data 7 6 5 2 0 1 1 0 7 6 5 2 0 0 1 0 Accumulator 5000h Upon the execution of an RLD instruction the Accumulator and memory location 5000h now contain 7 6 5 2 Oo 1 1 0 7 6 5 2 0 0 0 0 UM008006 0714 Accumulator 5000h Z80 Instruction Description Z80 CPU User Manual Z i Ory ILU y 238 DIXYS RRD Operation vi y Al7 4 3 07 4 3 0 HL ha Op Code RRD Operands Description The contents of the low order four bits bits 3 2 1 and 0 of memory location HL are copied to the low order four bits of the Accumulator Register A The previous contents of the low order four bits of the Accumulator are copied to the high order four bits 7 6 5 and 4 of location HL and the previous contents of the high order four bits of HL are copied to the low order four bits of HL The contents of the high order bits of the Accu mulator are unaffected y Note HL refers to the memory location specified by the contents of the HL register pair M Cycles T States 4 MHz E T 5 18 4 4 3 4 3 4 50 Condition Bits Affected S is set if the Accumulator is
123. f the decremented B Register is not 0 the Program Counter PC is decremented by two and the instruction is repeated If B has gone to 0 the instruc tion is terminated Interrupts are recognized and two refresh cycles are executed after each data transfer Note When B is set to O prior to instruction execution the instruction outputs 256 bytes of data If B 0 M Cycles T States 4 MHz E T 5 21 4 5 3 4 5 5 25 780 Instruction Set UM008006 07 14 If B 0 M Cycles T States 4 16 4 5 3 4 Condition Bits Affected S is unknown Z is set H is unknown P V is unknown N is set C is not affected Example Z80 CPU User Manual Zilog nIXYS 309 4 MHz E T 4 00 Register C contains 07h Register B contains 03h the HL register pair contains 1000h and memory locations contain the following data 1000h contains 51h 1001h contains A9h 1002h contains O3h Upon the execution of an OTIR instruction the HL register pair contains 1003h Register B contains a 0 and a group of bytes is written to the peripheral device mapped to I O port address 07h in the following sequence 51h A9h 03h UM008006 0714 Z80 Instruction Description 310 Z80 CPU User Manual Ar ZILOgd Operation C HD B B 1 HL HL 1 Op Code OUTD Operands None Description The contents of the HL register pair are placed on the address bus to select a location in mem
124. following table indicates the operation being performed Operation UM008006 0714 ADD ADC INC SUB SBC DEC NEG C Before DAA o a O O O OO O O 9 0 0 8 0 9 A F 9 F A F 0 2 0 2 0 3 0 9 0 8 7 F 6 7 Hex Value In Upper Digit Bits 7 4 H Before DAA o O O O O 00 O Hex Value In Lower Number Digit Added To C After Bits 3 0 Byte DAA 0 9 00 0 A F 06 0 0 3 06 0 0 9 60 1 A F 66 1 0 3 66 1 0 9 60 1 A F 66 1 0 3 66 1 0 9 00 0 6 F FA 0 0 9 AO 1 6 F 9A 1 Z80 Instruction Description 171 172 Z80 CPU User Manual ZlIlog BIXYS M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected S is set if most significant bit of the Accumulator is 1 after an operation otherwise it is reset Z is set if the Accumulator is 0 after an operation otherwise it is reset H see the DAA instruction table on the previous page P V is set if the Accumulator is at even parity after an operation otherwise it is reset N is not affected C see the DAA instruction table on the previous page Example An addition operation is performed between 15 BCD and 27 BCD simple decimal arithmetic provides the following result 15 27 42 The binary representations are added in the Accumulator according to standard binary arithmetic as follows 0001 0101 0010 0111 0011 1100 3C The sum is ambiguous The DAA instruction adjusts this result so that the co
125. g SCF 37 UM008006 0714 Arithmetic and Logical Z80 CPU User Manual Z i f nri LM y 50 nIXYS Note Descriptions of the General Purpose Arithmetic and CPU Control Groups instructions begin on page 170 The decimal adjust instruction can adjust for subtraction and addition making BCD arith metic operations simple y Notes 1 To allow for this operation the N flag is used This flag is set if the most recent arithmetic operation was a Subtract The Negate Accumulator NEG instruction forms the two s complement of the number in the Accumulator 2 A Reset Carry instruction is not included in the Z80 CPU because this operation can be easily achieved through other instructions such as a logical AND of the Accumu lator with itself Table 11 lists all of the 16 bit arithmetic operations between 16 bit registers There are five groups of instructions including the Add with Carry and Subtract with Carry instruc tions ADC and SBC affect all of the flags These two groups simplify address calculation or other 16 bit arithmetic operations Table 12 16 Bit Arithmetic Source BC DE HL SP IX IY Destination HL 09 19 29 39 IX DD DD DD DD 09 19 39 29 Add ADD Y FD FD FD FD 09 19 39 29 ED ED ED ED Add with Carry and set ADC flags HL 4A 5A 6A 7A ED ED ED ED Subtract with Carry and set SBC flags HL 42 52 62 72 DD FD Increment INC 03 13 23 33 23 23 DD FD Decrement
126. g the op code in memory contains the actual operand as shown in Figure 25 Op Code One or Two Bytes Op Code D7 DO Figure 25 Immediate Addressing Mode An example of this type of instruction is to load the Accumulator with a constant in which the constant is the byte immediately following the op code Immediate Extended Addressing This mode is an extension of immediate addressing in that the two bytes following the op codes are the operand as shown in Figure 26 Op Code One or Two Bytes Op Code low order Op Code high order Figure 26 Immediate Extended Addressing Mode An example of this type of instruction is to load the HL register pair 16 bit register with 16 bits two bytes of data Z80 CPU Instructions UM008006 0714 Z80 CPU User Manual ZzIlog nIXYS 35 Modified Page Zero Addressing The Z80 contains a special single byte CALL instruction to any of eight locations in Page 0 of memory This instruction which is referred to as a restart sets the Program Counter to an effective address in Page 0 The value of this instruction is that it allows a single byte to specify a complete 16 bit address at which commonly called subroutines are located thereby saving memory space Op Code One Byte B7 BO Effective Address is B5 B4 B3 000 2 Figure 27 Modified Page Zero Addressing Mode Relative Addressing Relative addressing uses one byte of data following the op code
127. g this refresh period should be used to perform a refresh read of all memory elements The refresh signal cannot be used by itself because the refresh address is only guaranteed to be stable during the MREQ period Architectural Overview UMO008006 0714 Z80 CPU User Manual ZIlOg nIXYS 9 M1 Cycle A15 A0 MREQ Figure 5 Instruction Op Code Fetch Memory Read Or Write Figure 6 shows the timing of memory read or write cycles other than an op code fetch cycle These cycles are generally three clock periods long unless wait states are requested by memory through the WAIT signal The MREQ signal and the RD signal are used the same way as in a fetch cycle In a memory write cycle the MREQ also becomes active when the address bus is stable so that it can be used directly as a chip enable for dynamic memories The WR line is active when the data on the data bus is stable so that it can be used directly as a R W pulse to virtually any type of semiconductor memory Furthermore the WR signal goes inactive one half T state before the address and data bus contents are changed so that the overlap requirements for almost any type of semiconductor memory type is met UM008006 0714 Memory Read Or Write Z80 CPU User Manual Z i ry LL y 10 nIXYS Memory Read Cycle Memory Write Cycle WR D7 DO WAIT Figure 6 Memory Read or Write Cycle Input or Output Cycles Figure 7 shows an I O read or I O write oper
128. ge 228 SRA m see page 231 SRL m see page 234 RLD see page 236 RRD see page 238 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 203 RLCA Operation Op Code RLCA Operands None 0 0 0 0 0 1 1 1 07 Description The contents of the Accumulator Register A are rotated left 1 bit position The sign bit bit 7 is copied to the Carry flag and also to bit 0 Bit 0 is the least significant bit M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected S is not affected Z is not affected H is reset P V is not affected N is reset C is data from bit 7 of Accumulator UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ra ZIlog Example The Accumulator contains the following data 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 0 Upon the execution of an RLCA instruction the Accumulator and Carry flag contains Z80 Instruction Set UM008006 0714 Z80 CPU User Manual Zilog nIXYS 205 RLA Operation 7 30 4 CY A Op Code RLA Operands None 0 0 0 1 0 111 1 17 Description The contents of the Accumulator Register A are rotated left 1 bit position through the Carry flag The previous contents of the Carry flag are copied to bit 0 Bit O is the
129. generate a Borrow This saved Carry facil itates software routines for extended precision arithmetic Additionally the DAA instruc tion sets the Carry Flag if the conditions for making the decimal adjustment are met For the RLA RRA RLS and RRS instructions the Carry bit is used as a link between the least significant byte LSB and the most significant byte MSB for any register or mem ory location During the RLCA RLC and SLA instructions the Carry flag contains the final value shifted out of bit 7 of any register or memory location During the RRCA RRC SRA and SRL instructions the Carry flag contains the final value shifted out of bit 0 of any register or memory location For the logical instructions AND OR and XOR the Carry flag is reset The Carry flag can also be set by the Set Carry Flag SCF instruction and complemented by the Compliment Carry Flag CCF instruction Add Subtract Flag The Add Subtract Flag N is used by the Decimal Adjust Accumulator instruction DAA to distinguish between the ADD and SUB instructions For ADD instructions N is cleared to 0 For SUB instructions N is set to 1 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual zilog nIXYS 65 Decimal Adjust Accumulator Flag The Decimal Adjust Accumulator DAA instruction uses this flag to distinguish between ADD and SUBTRACT instructions For all ADD instructions N sets to 0 For all SUB TRACT instructions N sets to 1 Parit
130. gister Example Index Register IY contains 1000h and memory location 1002h contain the following data 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 0 Upon the execution of an RLC Y 2h instruction memory location 1002h and the Carry flag now contain C 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 0 4 Z80 Instruction Set UM008006 07 14 RL m Operation CY a 7 Op Code PL Operand m Z80 CPU User Manual ZIlOg DIXYS The m operand is any of r HL IX d or 1Y d as defined for the analogous PLC instructions In the assembled object code the possible op code operand combinations are specified as follows RL r 1 1 RL HL 1 1 3 RL IX d 111 RL IY d 111 UM008006 0714 CB CB DD CB FB CB 16 Z80 Instruction Description 219 Z80 CPU User Manual ra ri ZILOgd r identifies registers B C D E H L or A assembled as follows in the object code field Register r B 000 001 D 010 E 011 H 100 L 101 A iia Description The contents of the m operand are rotated left 1 bit position The contents of bit 7 are cop ied to the Carry flag and the previous contents of the Carry flag are copied to bit 0 Inst
131. gister is compared with the contents of the Accumulator With a true compare a condition bit is set Then HL is incre mented and the Byte Counter register pair BC is decremented M Cycles T States 4 MHz E T 4 16 4 4 3 5 4 00 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if A is HL otherwise it is reset H is set if borrow from bit 4 otherwise it is reset P V is set if BC 1 is not 0 otherwise it is reset N is set C is not affected Example If the HL register pair contains 1111h memory location 1111h contains 3Bh the Accu mulator contains 3Bh and the Byte Counter contains 0001h Upon the execution of a CPI instruction the Byte Counter contains 0000h the HL register pair contains 1112h the Z flag in the F register is set and the P V flag in the F Register is reset There is no effect on the contents of the Accumulator or to address 1111h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 137 CPIR Operation A HL HL HL 1 BC BC 1 Op Code CPIR Operands None Description The contents of the memory location addressed by the HL register pair is compared with the contents of the Accumulator During a compare operation a condition bit is set HL is incremented and the Byte Counter register pair BC is decremented If decrementing causes BC to go to 0 or if A HL the ins
132. he memory location specified by the con tents of the DE register pair M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Example If register pair DE contains 1128h and the Accumulator contains byte AOh then the exe cution of a LD DE A instruction results in AOh being stored in memory location 1128h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 91 LD nn A Operation nn A Op Code LD Operands nn A ra n ra n D Description The contents of the Accumulator are loaded to the memory address specified by the oper and nn The first n operand after the op code is the low order byte of nn M Cycles T States 4 MHz E T 4 13 4 3 3 3 3 25 Condition Bits Affected None Example If the Accumulator contains byte D7h then executing an LD 3141h AD7h instruction results in memory location 3141h UM008006 0714 Z80 Instruction Description 92 Z80 CPU User Manual Z T On ILUV y OIXYS LD A I Operation A lt 1 Op Code LD Operands A I Description The contents of the Interrupt Vector Register I are loaded to the Accumulator M Cycles T States MHz E T 2 9 4 5 2 25 Condition Bits Affected S is set if the I Register is negative otherwise it is reset Z is set if the I Register is 0 otherwise it is reset H is reset P V
133. ies registers A B C D E H or L assembled as follows in the object code Register r A 111 B 000 C 001 D 010 E 011 H 100 L 101 M Cycles T States 4 MHz E T 5 19 4 4 3 5 2 50 3 Condition Bits Affected None UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOg 74 BIXYS Example If Index Register IX contains the number 25AFh the instruction LD B IX 19h allows the calculation of the sum 25AFh 19h which points to memory location 25C8h If this address contains byte 39h the instruction results in Register B also containing 39h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZIlOg nIXYS 75 LD r IY d Operation r IY D Op Code LD Operands r IY d Description The operand Y d loads the contents of Index Register IY summed with two s comple ment displacement integer d to register r in which r identifies registers A B C D E H or L assembled as follows in the object code Register r A 111 B 000 C 001 D 010 E 011 H 100 L 101 M Cycles T States 4 MHz E T 5 19 4 4 3 5 3 4 75 Condition Bits Affected None UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOg 76 DIXYS Comp Example If Index Register IY contains the number 25AFh the instruction LD B IY 19h allows the calculation of the sum 25AFh 19h which points to memory location 25C8h If this
134. ined op code set the flag B 000 C 001 D 010 E 011 H 100 L 101 A 111 M Cycles T States 4 MHz E T 3 12 4 4 4 3 00 UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 294 nIXYS Condition Bits Affected S is set if input data is negative otherwise it is reset Z is set if input data is 0 otherwise it is reset H is reset P V is set if parity is even otherwise it is reset N is reset C is not affected Example Register C contains 07h Register B contains 10h and byte 7Bh is available at the periph eral device mapped to I O port address 07n Upon the execution of an IN D C com mand the D Register contains 7Bh Z80 Instruction Set UM008006 07 14 INI Z80 CPU User Manual Zilog BIXYS Operation HL C B B 1 HL HL 1 Op Code INI Operands None Description The contents of Register C are placed on the bottom half A0 through A7 of the address bus to select the I O device at one of 256 possible ports Register B can be used as a byte counter and its contents are placed on the top half A8 through A15 of the address bus at this time Then one byte from the selected port is placed on the data bus and written to the CPU The contents of the HL register pair are then placed on the address bus and the input byte is written to the corresponding location of memory Finally the byte counter is decre mented and register
135. ing the memory cycle shown in Figure 11 Power Down Acknowledge Cycle When the clock input to the Z80 CPU is stopped at either a High or Low level the Z80 CPU stops its operation and maintains all registers and control signals However ICC2 standby supply current is guaranteed only when the system clock is stopped at a Low level during T4 of the machine cycle following the execution of the HALT instruction The timing diagram for the power down function when implemented with the HALT instruction is shown in Figure 12 HALT Figure 12 Power Down Acknowledge UM008006 0714 Power Down Acknowledge Cycle Z80 CPU User Manual Z j n Di LL y 16 DIXYS Power Down Release Cycle The system clock must be supplied to the Z80 CPU to release the power down state When the system clock is supplied to the CLK input the Z80 CPU restarts operations from the point at which the power down state was implemented The timing diagrams for the release from power down mode are featured in Figures 13 through 15 When the HALT instruction is executed to enter the power down state the Z80 CPU also enters the HALT state An interrupt signal either NMI or ANT or a RESET signal must be applied to the CPU after the system clock is supplied to release the power down state Figure 13 Power Down Release Cycle 1 of 3 T1 T2 T3 T4 Figure 14 Power Down Release Cycle 2 of 3 Architectural Overview UM008006 0714 Z80 CPU User Manual Zz
136. ion the Accumulator and the Carry flag now con tain Z80 Instruction Set UM008006 07 14 RRA UM008006 0714 Z80 CPU User Manual ZItog DIXYS Operation 7 0 xir A Op Code RRA Operands None Description The contents of the Accumulator Register A are rotated right 1 bit position through the Carry flag The previous contents of the Carry flag are copied to bit 7 Bit 0 is the least significant bit M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected S is not affected Z is not affected H is reset P V is not affected N is reset C is data from bit O of Accumulator Z80 Instruction Description 209 Z80 CPU User Manual ra ZIlog Example The Accumulator and the Carry Flag contain the following data 7 6 5 4 3 2 1 0 C 1 1 1 0 0 0 0 1 0 Upon the execution of an RRA instruction the Accumulator and the Carry flag now con tain 7 6 5 4 3 2 1 0 C 0 1 1 1 0 0 0 0 1 Z80 Instruction Set UM008006 0714 RLC r Z80 CPU User Manual ZILOg OIXYS Operation CY 7 0 e Op Code RLC Operand x 1 0 1 0 1 4 CB 0 0 0 ma r po Description The contents of register r are
137. ion Set UM008006 07 14 Z80 CPU User Manual ZzIlog nIXYS 127 EX SP IY Operation IYH e SP 1 IYL gt SP Op Code EX Operands SP IY Description The low order byte in Index Register IY is exchanged with the contents of the memory address specified by the contents of register pair SP Stack Pointer and the high order byte of IY is exchanged with the next highest memory address SP 1 M Cycles T States 4 MHz E T 6 23 4 4 3 4 3 5 5 75 Condition Bits Affected None Example If Index Register IY contains 3988h the SP register pair contains 0100h memory loca tion 0100h contains byte 90h and memory location 0101h contains byte 48h then the instruction EX SP IY results in the IY register pair containing number 4890h memory location 0100h containing 88h memory location 0101h containing 39h and the Stack Pointer containing 0100h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOQd 128 DIXYS Operation DE HL DE DE 1 HL HL 1 BC BC 1 Op Code LDI Operands SP HL Description A byte of data is transferred from the memory location addressed by the contents of the HL register pair to the memory location addressed by the contents of the DE register pair Then both these register pairs are incremented and the Byte Counter BC Register pair is decremented M Cyc
138. is not 0 the program counter is decremented by two and the instruction is repeated Interrupts are recognized and two refresh cycles execute after each data transfer When the BC is set to 0 prior to instruction execution the instruction loops through 64 KB For BC z 0 M Cycles T States 4 MHz E T 5 21 4 4 3 5 5 5 25 For BC 0 M Cycles T States 4 MHz E T 4 16 4 4 3 5 4 00 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZzIlog nIXYS 135 Condition Bits Affected S is not affected Z is not affected H is reset P V is reset N is reset Example The HL register pair contains 1114h the DE register pair contains 2225h the BC register pair contains 0003h and memory locations contain the following data 1114h contains A5h 2225h contains C5h 1113h contains 36h 2224h contains 59h 1112h contains 88h 2223h contains 66h Upon the execution of an LDDR instruction the contents of the register pairs and memory locations now contain HL contains 1111h DE contains 2222h DC contains 0000h 1114h contains A5h 2225h contains A5h 1113h contains 36h 2224h contains 36h 1112h contains 88h 2223h contains 88h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual 136 nIXYS Operation A HL HL HL 1 BC BC 1 Op Code CPI Operands None Description The contents of the memory location addressed by the HL re
139. is reset N is reset C is set if carry from bit 7 otherwise it is reset Example If the Accumulator contains 44h and Register C contains 11h then upon the execution of an ADD A C instruction the Accumulator contains 55h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOG nIXYS 145 ADD A n Operation A A n Op Code ADD Operands A n a n gt Description The n integer is added to the contents of the Accumulator and the results are stored in the Accumulator M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is set if carry from bit 3 otherwise it is reset P V is set if overflow otherwise it is reset N is reset C is set if carry from bit 7 otherwise it is reset Example If the Accumulator contains 23h then upon the execution of an ADD A 33h instruction the Accumulator contains 56h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual 146 OIXYS ADD A HL Operation A A HL Op Code ADD Operands A HL 1 00 0 0 1 1 0 86 Description The byte at the memory address specified by the contents of the HL register pair is added to the contents of the Accumulator and the result is stored in the Accumulator M Cycles T States 4 MHz E T 2 7
140. it is reset Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog OLXYs 175 Example The Accumulator contains the following data UM008006 0714 Z80 Instruction Description Z80 CPU User Manual zilog ILU hos 176 nIXYS CCF Operation CY CY Op Code CCF Operands None Description The Carry flag in the F Register is inverted M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected S is not affected Z is not affected H previous carry is copied P V is not affected N is reset C is set if CY was 0 before operation otherwise it is reset Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZIlOg nIXYS 177 SCF Operation CY 1 Op Code SCF Operands None Description The Carry flag in the F Register is set M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected S is not affected Z is not affected H is reset P V is not affected N is reset C is set UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOg 178 nIXYS NOP Operation Op Code NOP Operands None Description The CPU performs no operation during this machine cycle M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected None Z80 Instruction Set UM008006 07 14 Z8
141. les T States 4 MHz E T 4 16 4 4 3 5 4 00 Condition Bits Affected S is not affected Z is not affected H is reset P V is set if BC 1 Z 0 otherwise it is reset N is reset C is not affected Example If the HL register pair contains 1111h memory location 1111h contains byte 88h the DE register pair contains 2222h the memory location 2222h contains byte 66h and the BC Z80 Instruction Set UM008006 07 14 UM008006 0714 Z80 CPU User Manual Zilog nIXYS 129 register pair contains 7h then the instruction LDI results in the following contents in reg ister pairs and memory addresses HL contains 1111h contains DE contains 2222h contains BC contains 1112h 88h 2223h 88h 6H Z80 Instruction Description 130 Z80 CPU User Manual Ar ZILOd Operation DE HL DE DE 1 HL HL 1 BCF amp BC 1 Op Code LDIR Operand B8 Description This 2 byte instruction transfers a byte of data from the memory location addressed by the contents of the HL register pair to the memory location addressed by the DE register pair Both these register pairs are incremented and the Byte Counter BC Register pair is dec remented If decrementing allows the BC to go to 0 the instruction is terminated If BC is not 0 the program counter is decremented by two and the instruction is repeated Inter rupts are recognized and two refresh cycles are execut
142. matically terminates Both the block transfer and the block search instruc tions can be interrupted during their execution so they are not occupying the CPU for long periods of time The arithmetic and logical instructions operate on data stored in the Accumulator and other general purpose CPU registers or external memory locations The results of the operations are placed in the Accumulator and the appropriate flags are set according to the result of the operation Z80 CPU Instructions UM008006 0714 Z80 CPU User Manual Zilog BIXYS An example of an arithmetic operation is adding the Accumulator to the contents of an external memory location The results of the addition are placed in the Accumulator This group also includes 16 bit addition and subtraction between 16 bit CPU registers The rotate and shift group allows any register or any memory location to be rotated right or left with or without carry and either arithmetic or logical Additionally a digit in the Accumulator can be rotated right or left with two digits in any memory location The bit manipulation instructions allow any bit in the Accumulator any general purpose register or any external memory location to be set reset or tested with a single instruc tion For example the most significant bit of Register H can be reset This group is espe cially useful in control applications and for controlling software flags in general purpose programming The JUMP CALL an
143. ment and Micro computer Systems The absolute assembler is contained in base level software operating in a 16K memory space while the relocating assembler is part of the RIO environment operating in a 32K memory space Z80 Status Indicator Flags The Flag registers F and F supply information to the user about the status of the Z80 CPU at any particular time The bit positions for each flag are listed in Table 20 and defined in Table 20 Flag Register Bit Positions Bit 7 6 5 4 3 2 1 0 Position S Z X H X P V N C UMO008006 0714 Z80 Instruction Set 64 Z80 CPU User Manual ZIlog BIXYS Table 21 Flag Definitions Symbol Field Name C Carry Flag N Add Subtract P V Parity Overflow Flag H Half Carry Flag Z Zero Flag S Sign Flag X Not Used Each of these two Flag registers contains 6 bits of status information that are set or cleared by CPU operations bits 3 and 5 are not used Four of these bits C P V Z and S can be tested for use with conditional JUMP CALL or RETURN instructions The H and N flags cannot be tested these two flags are used for BCD arithmetic Carry Flag The Carry Flag C is set or cleared depending on the operation being performed For ADD instructions that generate a Carry and for SUB instructions that generate a Borrow the Carry Flag is set The Carry Flag is reset by an ADD instruction that does not generate a Carry and by a SUB instruction that does not
144. mic Memories 0 cece cece eee 25 Software Implementation Examples 0 0 cece eee eee eee 26 Specific Z80 Instruction Examples 0 0 cece ee eee 27 Programming Task Examples 0 0c cece eee eee eee 29 Z80 CPU InsituctiOns s cien a pda chad eyed da Beatie e ado si a Gia 32 Instruction Types divisas oed deae er ee dts choad bnc MEO e ac oaa 32 Addressing Modes ceca dia dde cbe e e pP IQ redd 34 Immediate Addressing o oooooococccocooo eh 34 UM008006 0714 Table of Contents vi Z80 CPU User Manual Zilog BIXYS Immediate Extended Addressing 0 00 cece eee eens 34 Modified Page Zero Addressing 0 0 aranne 35 Relative Addressing 222 edo ee de ae ea ae Rave aca Rer hd 35 Extended Addressimg 251 2us n epe p e ra aka er dog 36 Indexed Addressing 2 22 22 A t prae tup eae dda does 36 Register Addressing comocrorencorocro cr saa eh heh 37 Implied Addressing slseeeelee e 37 Register Indirect Addressing 0 0 cee eect tenes 37 Bit Addressin cirios cias cada ie pug er cad eee ea 38 Addressing Mode Combinations 0 0 e eee eee eee eee 38 Instruction Op Codes 0 cence cece n eens 38 Load and Exchange 20 eee cece eee eens 39 Block Transfer and Search 0 0 0 cece eee eee 45 Arithmetic and Logical 0 0 0 cece e 47 Rotate and Shift 12s dade tdo geek dtd aes atlas a dated iade 51 Bit Manipul
145. mory address SP 1 M Cycles T States 4 MHz E T 5 19 4 3 4 3 5 4 75 Condition Bits Affected None Example If the HL register pair contains 7012h the SP register pair contains 885 6h the memory location 8856h contains byte 11h and memory location 8857h contains byte 22h then the instruction EX SP HL results in the HL register pair containing number 2211h memory location 8856h containing byte 12h memory location 8857h containing byte 70h and Stack Pointer containing 8856h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOQd 126 nIXYS EX SP IX Operation IXH gt SP 1 IXL gt SP Op Code EX Operands SP IX Description The low order byte in Index Register IX is exchanged with the contents of the memory address specified by the contents of register pair SP Stack Pointer and the high order byte of IX is exchanged with the next highest memory address SP 1 M Cycles T States 4 MHz E T 6 23 4 4 3 4 3 5 5 75 Condition Bits Affected None Example If Index Register IX contains 3988h the SP register pair Contains 0100h memory loca tion 0100h contains byte 90h and memory location 0101h contains byte 48h then the instruction EX SP IX results in the IX register pair containing number 4890h memory location 0100h containing 88h memory location 0101h containing 39h and the Stack Pointer containing 0100h Z80 Instruct
146. n Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is reset P V is set if parity even otherwise it is reset N is reset C is data from bit 7 of source register UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 21 4 BIXYS Example The HL register pair contains 2828h and the contents of memory location 2828h are 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 0 Upon the execution of an RLC HL instruction memory location 2828h and the Carry flag now contain C 7 6 5 4 3 2 1 0 1 0 0 0 1 0 0 0 1 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZIlOg nIXYS 215 RLC IX d Operation CY 7 0 a IX d Op Code RLC Operand IX d Description The contents of the memory address specified by the sum of the contents of Index Register IX and the two s complement displacement integer d are rotated left 1 bit position The contents of bit 7 are copied to the Carry flag and also to bit 0 Bit O is the least significant bit M Cycles T States 4 MHz E T 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is reset P V is set if parity even otherwise
147. n Bits Affected S is unknown Zis set if B 1 2 0 otherwise it is reset H is unknown P V is unknown N is set C is not affected Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual zilo C BIXYS 307 Example If Register C contains 07h Register B contains 10h the HL register pair contains 100014 and memory address 1000h contains 5914 then upon the execution of an OUTI instruc tion Register B contains 0Fh the HL register pair contains 1001h and byte 59h is writ ten to the peripheral device mapped to I O port address 07h UM008006 0714 Z80 Instruction Description 308 Z80 CPU User Manual Z i ena BLU y OIXYS OTIR Operation C HL B B 1 HL HL 1 Op Code OTIR Operands None Description The contents of the HL register pair are placed on the address bus to select a location in memory The byte contained in this memory location is temporarily stored in the CPU Then after the byte counter B is decremented the contents of Register C are placed on the bottom half AO through A7 of the address bus to select the I O device at one of 256 possible ports Register B can be used as a byte counter and its decremented value is placed on the top half A8 through A15 of the address bus at this time Next the byte to be output is placed on the data bus and written to the selected peripheral device Then reg ister pair HL is incremented I
148. n Description 200 Z80 CPU User Manual zilo O BIXYS DEC IX Operation IX IX 1 Op Code DEC Operand IX Description The contents of Index Register IX are decremented M Cycles T States 4 MHz E T 2 10 4 6 2 50 Condition Bits Affected None Example If Index Register IX contains 2006h then upon the execution of a DEC ZX instruction Index Register IX contains 2005h Z80 Instruction Set UM008006 07 14 DEC IY Z80 CPU User Manual ZILOg BIXYS Operation IY IY 1 Op Code DEC Operand IY Description The contents of Index Register IY are decremented M Cycles T States 4 MHz E T 2 10 4 6 2 50 Condition Bits Affected None Example If Index Register IY contains 7649h then upon the execution of a DEC Y instruction Index Register IY contains 7648h UM008006 0714 Z80 Instruction Description 201 Z80 CPU User Manual Z il rnt LUV uj 202 nDIXYS Rotate and Shift Group The following rotate and shift group instructions are each described in this section Simply click to jump to an instruction s description to learn more RLCA see page 203 RLA see page 205 RRCA see page 207 RRA see page 209 RLC r see page 211 RLC HL see page 213 RLC 1X d see page 215 RLC IY d see page 217 RL m see page 219 RRC m see page 222 RR m see page 225 SLA m see pa
149. n the execution of an INC AL instruction memory location 3434h contains 83h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOQg 166 nIXYS INC IX d Operation IX d IX d 1 Op Code INC Operands IX d Description The contents of Index Register IX register pair IX are added to the two s complement displacement integer d to point to an address in memory The contents of this address are then incremented M Cycles T States 4 MHz E T 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is set if carry from bit 3 otherwise it is reset P V is set if IX d was 7Fh before operation otherwise it is reset N is reset C is not affected Example If Index Register pair IX contains 2020h and memory location 2030h contains byte 34h then upon the execution of an INC X 10h instruction memory location 2030h con tains 35h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 167 INC IY d Operation 1Y 4d 1Y d 1 Op Code INC Operands IY d Description The contents of Index Register IY register pair IY are added to the two s complement displacement integer d to point to an address in memory The contents of this address are
150. n upon the execution of an LD BC 2130h instruction the BC register pair contains 78 65h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZItog nIXYS 103 LD IX nn Operation IXh nn 1 IXI nn Op Code LD Operands IX nn at n t n Description The contents of the address rn are loaded to the low order portion of Index Register IX and the contents of the next highest memory address nn 1 are loaded to the high order portion of IX The first n operand after the op code is the low order byte of nn M Cycles T States 4 MHz E T 6 20 4 4 3 3 3 3 5 00 Condition Bits Affected None Example If address 6666h contains 92h and address 6667h contains DAh then upon the execution of an LD IX 6666h instruction Index Register IX contains DA92h UM008006 0714 Z80 Instruction Description 104 Z80 CPU User Manual Z n1 ILU hos OLXYS LD IY nn Operation IYh nn 1 IYI nn Op Code LD Operands IY nn at n t n Description The contents of address nn are loaded to the low order portion of Index Register IY and the contents of the next highest memory address nn 4 1 are loaded to the high order por tion of IY The first n operand after the op code is the low order byte of nn M Cycles T States 4 MHz E T 6 20 4 4
151. nary equivalent of the magnitude of a positive number is stored in bits 0 to 6 for a total range of from 0 to 127 A negative number is represented by the twos complement of the equiva lent positive number The total range for negative numbers is from 1 to 128 When inputting a byte from an I O device to a register using an IN r C instruction the S Flag indicates either positive S 0 or negative S 1 data Z80 Instruction Description Execution time E T for each instruction is provided in microseconds for an assumed 4MHz clock Total machine cycles M are indicated with total clock periods or T states Also indicated are the number of T states for each M cycle as shown in the following example M Cycles T States E T 2 7 4 3 4 MHz 1 75 This example indicates that the instruction consists of two machine cycles The first cycle contains 4 clock periods T states The second cycle contains 3 clock periods for a total of 7 clock periods T states The instruction executes in 1 75 microseconds In the register format of each of the instructions that follow the most significant bit to the left and the least significant bit to the right UM008006 0714 Sign Flag 68 Z80 CPU User Manual ra Ti ZIlog BIXYS 8 Bit Load Group The following 8 bit load instructions are each described in this section Simply click to jump to an instruction s description to learn more LD r r see page 69 LD r n see p
152. ng is actually a form of Register Indirect addressing except that a displacement is added with indexed addressing Register indirect addressing allows for powerful but simple to implement memory accesses The block move and search commands in the Z80 CPU are extensions of this type of addressing in which automatic register incrementing decrementing and comparing is added The notation for indicating Register Indirect addressing is to put UM008006 0714 Register Addressing Z80 CPU User Manual ra ri ZILOgd parentheses around the name of the register that is to be used as the pointer For example the symbol HL specifies that the contents of the HL register are to be used as a pointer to a memory location Often Register Indirect addressing is used to specify 16 bit operands In this case the register contents point to the lower order portion of the operand while the register contents are automatically incremented to obtain the upper portion of the operand Bit Addressing The Z80 contains a large number of bit set reset and test instructions These instructions allow any memory location or CPU register to be specified for a bit operation through one of three previous addressing modes register Register Indirect and indexed while three bits in the op code specify which of the eight bits is to be manipulated Addressing Mode Combinations Many instructions include more than one operand such as arithmetic instructions or loads In th
153. ng is required for a program to jump from any location in memory to any other location or load and store data in any memory location During extended addressing use specify the source or destination address of an operand This notation nn is used to indicate the contents of memory at nn in which nn is the 16 bit address specified in the instruction The two bytes of address nn are used as a pointer to a memory location The parentheses always indicates that the value enclosed within them is used as a pointer to a memory location For example 1200 refers to the contents of memory at location 1200 Indexed Addressing In the Indexed Addressing Mode the byte of data following the op code contains a dis placement that is added to one of the two index registers the op code specifies which index register is used to form a pointer to memory The contents of the index register are not altered by this operation Op Code Op Code Two Byte Op Code Operand added to index register to form a pointer to memory Displacement Figure 30 Indexed Addressing Mode An example of an indexed instruction is to load the contents of the memory location Index Register Displacement into the Accumulator The displacement is a signed two s Z80 CPU Instructions UM008006 0714 Z80 CPU User Manual zilog nIXYS 37 complement number Indexed addressing greatly simplifies programs using tables of data because the index register can p
154. nting causes B to go to 0 the instruction is ter minated If B is not 0 the Program Counter is decremented by two and the instruction repeated Interrupts are recognized and two refresh cycles execute after each data transfer gt Note If B is set to 0 prior to instruction execution 256 bytes of data are input If B 0 M Cycles T States 4 MHz E T 5 21 4 5 3 4 5 5 25 If B 0 M Cycles T States 4 MHz E T 4 16 4 5 3 4 4 00 UM008006 0714 Z80 Instruction Description 297 Z80 CPU User Manual Zilog 298 DIXYS Comp Condition Bits Affected S is unknown Z is set H is unknown P V is unknown N is set C is not affected Example Register C contains 07h Register B contains 03h the HL register pair contains 1000h and the following sequence of bytes is available at the peripheral device mapped to I O port of address 07h 51h A9h 03h Upon the execution of an INIR instruction the HL register pair contains 1003h Register B contains a 0 and the memory locations contain the following data 1000h 51h 1001h A9h 1002h 03h Z80 Instruction Set UM008006 07 14 IND Z80 CPU User Manual Zilog BIXYS Operation HL C B B 1 HL HL 1 Op Code IND Operands None Description The contents of Register C are placed on the bottom half A0 through A7 of the address bus to select the I O device at one of 256 possible ports Register
155. ny of register pairs BC DE HL or SP are added to the contents of register pair HL and the result is stored in HL In the assembled object code operand ss is specified as follows Register Pair BC DE HL SP M Cycles 3 Condition Bits Affected S is not affected Z is not affected ss 00 01 10 11 T States 11 4 4 3 4 MHz E T 2 75 H is set if carry from bit 11 otherwise it is reset P V is not affected N is reset Z80 Instruction Set UM008006 0714 Z80 CPU User Manual Zilog nIXYS 187 C is set if carry from bit 15 otherwise it is reset Example If register pair HL contains the integer 4242n and register pair DE contains 1111h then upon the execution of an ADD HL DE instruction the HL register pair contains 5353h UM008006 0714 Z80 Instruction Description 188 Z80 CPU User Manual Zilo O BIXYS ADC HL ss Operation HL HL ss CY Op Code ADC Operands HL ss Description The contents of register pair ss any of register pairs BC DE HL or SP are added with the Carry flag C flag in the F Register to the contents of register pair HL and the result is stored in HL In the assembled object code operand ss is specified as follows Register Pair ss BC 00 DE 01 HL 10 SP 11 M Cycles T States 4 MHz E T 4 15 4 4 4 3 3 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z
156. o that of a nonmask able interrupt except that the call location is 0038h instead of 0066n The number of cycles required to complete the restart instruction is two more than normal due to the two added wait states Mode 2 Mode 2 is the most powerful interrupt response mode With a single 8 bit byte from the user an indirect call can be made to any memory location UM008006 0714 CPU Response Z80 CPU User Manual ZILO A Vj In Mode 2 the programmer maintains a table of 16 bit starting addresses for every inter rupt service routine This table can be located anywhere in memory When an interrupt is accepted a 16 bit pointer must be formed to obtain the required interrupt service routine starting address from the table The upper eight bits of this pointer is formed from the con tents of the I Register The I register must be loaded with the applicable value by the pro grammer such as LD J A A CPU reset clears the I Register so that it is initialized to 0 The lower eight bits of the pointer must be supplied by the interrupting device Only seven bits are required from the interrupting device because the least significant bit must be a 0 This process is required because the pointer must receive two adjacent bytes to form a complete 16 bit service routine starting address addresses must always start in even loca tions Starting Address Pointed to by Interrupt Routine Starting High Order Address 7 mE Figure 17
157. ode above is the least significant byte of the 2 byte memory address Description If condition cc is true this instruction pushes the current contents of the Program Counter PC onto the top of the external memory stack then loads the operands nn to PC to point to the address in memory at which the first op code of a subroutine is to be fetched At the end of the subroutine a RETurn instruction can be used to return to the original program flow by popping the top of the stack back to PC If condition cc is false the Program Counter is incremented as usual and the program continues with the next sequential instruction The stack push is accomplished by first decrementing the current contents of the Stack Pointer SP loading the high order byte of the PC contents to the memory address now pointed to by SP then decrementing SP again and loading the low order byte of the PC contents to the top of the stack Because this process is a 3 byte instruction the Program Counter was incremented by three before the push is executed Condition cc is programmed as one of eight statuses that corresponds to condition bits in the Flag Register Register F These eight statuses are defined in the following table which also specifies the corresponding cc bit fields in the assembled object code Z80 Instruction Set UM008006 07 14 cc Condition 000 Non Zero NZ 001 Zero Z 010 Non Carry NC 011 Carry C 100 Parity Odd PO 101 Parity Even PE
158. oint to the start of any table Two index registers are pro vided because often operations require two or more tables Indexed addressing also allows for relocatable code The two index registers in the Z80 CPU are referred to as IX and IY To indicate indexed addressing use the following notation IX d or IY d In this notation d is the displacement specified after the op code The parentheses indicate that this value is used as a pointer to external memory Register Addressing Many of the Z80 op codes contain bits of information that specify which CPU register is to be used for an operation An example of register addressing is to load the data in Register 6 into Register C Implied Addressing Implied addressing refers to operations in which the op code automatically implies one or more CPU registers as containing the operands An example is the set of arithmetic opera tions in which the Accumulator is always implied to be the destination of the results Register Indirect Addressing This type of addressing specifies a 16 bit CPU register pair such as HL to be used as a pointer to any location in memory This type of instruction is powerful and it is used in a wide range of applications Op Code one or Two Bytes Figure 31 Register Indirect Addressing Mode An example of this type of instruction is to load the Accumulator with the data in the memory location pointed to by the HL register contents Indexed addressi
159. on the execution of a SET 4 HL instruc tion bit 4 in memory location 3000h is 1 Bit O in memory location 3000h is the least sig nificant bit Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 253 SET b IX d Operation IX d b 1 Op Code SET Operands b IX d Description Bit b in the memory location addressed by the sum of the contents of the IX register pair and the two s complement integer d is set In the assembled object code operand b is spec ified as follows Bit Tested b 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 M Cycles T States 4 MHz E T 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected None Example If the index register contains 2000h then upon the execution of a SET 0 IX 3h instruction bit 0 in memory location 2003h is 1 Bit 0 in memory location 2003h is the least significant bit UM008006 0714 Z80 Instruction Description Z80 CPU User Manual zilog LM y 254 nIXYS SET b IY d Operation IY d b 1 Op Code SET Operands b IY d Description Bit b in the memory location addressed by the sum of the contents of the IY register pair and the two s complement displacement d is set In the assembled object code operand b is specified as follows Bit Tested b 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 M Cycles T States 4 MHz E T 6 23 4 4
160. or contains 27h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 151 SUB s Operation A A s Op Code SUB Operand S This s operand is any of r n HL IX d or IY d as defined for the analogous ADD instruction These possible op code operand combinations are assembled as follows in the object code SUB r 1 0 0 1 0 ma p SUB n 1 1 0 1 0 1 1 o D6 SUB HL 1 0 0 1 0 1 1 0 96 SUB IX d 111 0 1 1 1 0 11 DD SUB IY d 1 1 1 1 1 1 0 71 FD UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 152 BIXYS Comp r identifies registers B C D E H L or A assembled as follows in the object code field Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Description The s operand is subtracted from the contents of the Accumulator and the result is stored in the Accumulator Instruction M Cycle T States 4 MHz E T SUB r 1 4 1 00 SUB n 2 7 4 3 1 75 SUB HL 2 7 4 3 1 75 SUB IX d 5 19 4 4 3 5 3 4 75 SUB IY d 5 19 4 4 3 5 3 4 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is set if borrow from bit 4 otherwise it is reset P V is set if overflow otherwise it is reset N is set C is set if borrow otherwise it is reset
161. ory The byte contained in this memory location is temporarily stored in the CPU Then after the byte counter B is decremented the contents of Register C are placed on the bottom half AO through A7 of the address bus to select the I O device at one of 256 possible ports Register B can be used as a byte counter and its decremented value is placed on the top half A8 through A15 of the address bus at this time Next the byte to be output is placed on the data bus and written to the selected peripheral device Finally the register pair HL is decremented M Cycles T States 4 MHz E T 4 16 4 5 3 4 4 00 Condition Bits Affected S is unknown Zis set if B 1 2 0 otherwise it is reset H is unknown P V is unknown N is set C is not affected Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual zilo C BIXYS 311 Example If Register C contains 07h Register B contains 10h the HL register pair contains 1000h and memory location 1000h contains 59h then upon the execution of an OUTD instruc tion Register B contains 0Fh the HL register pair contains OFFFh and byte 59h is writ ten to the peripheral device mapped to I O port address 07h UM008006 0714 Z80 Instruction Description 312 Z80 CPU User Manual Z i ena BLU y OIXYS OTDR Operation C HL B B 1 HL HL 1 Op Code OTDR Operands None Description The contents of the HL
162. ow order first resulting in the Stack Pointer again containing 1000h The program flow continues where it left off with an op code fetch to address 1A45h order byte first and 0066h is loaded onto the Program Counter UM008006 0714 Z80 Instruction Description 287 Z80 CPU User Manual Zilog 288 BIXYS Corp That address begins an interrupt service routine that ends with a RETN instruction Upon the execution of a RETN instruction the contents of the former Program Counter are popped off the external memory stack low order first resulting in stack pointer contents of 1000h The program flow continues where it left off with an op code fetch to address 1A45h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 289 RST p Operation SP 1 PCH SP 2 PCL PCH 0 PCL P Op Code RST Operand p Description The current Program Counter PC contents are pushed onto the external memory stack and the Page 0 memory location assigned by operand p is loaded to the PC Program exe cution then begins with the op code in the address now pointed to by PC The push is per formed by first decrementing the contents of the Stack Pointer SP loading the high order byte of PC to the memory address now pointed to by SP decrementing SP again and load ing the low order byte of PC to the address now pointed to by SP The Restart instruction allows for a jump to one of
163. pairs are decremented If decrementing allows the BC to go to 0 or if A HL the instruction is terminated If BC is not 0 and A HL the program counter is decremented by two and the instruction is repeated Interrupts are rec ognized and two refresh cycles execute after each data transfer When the BC is set to 0 prior to instruction execution the instruction loops through 64KB if no match is found For BC z 0 and A HL M Cycles T States 4 MHz E T 5 21 4 4 3 5 5 5 25 For BC 0 and A HL M Cycles T States 4 MHz E T 4 16 4 4 3 5 4 00 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if A HL otherwise it is reset His set if borrow form bit 4 otherwise it is reset Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nixYs 141 P V is set if BC 1 Z 0 otherwise it is reset N is set C is not affected Example The HL register pair contains 1118h the Accumulator contains F3h the Byte Counter contains 0007h and memory locations contain the following data 1118h contains 52h 1117h contains 00h 1116h contains F3h Upon the execution of a CPDR instruction register pair HL contains 1115h the Byte Counter contains 000 4h the P V flag in the F Register is set and the Z flag in the F Reg ister is set UM008006 0714 Z80 Instruction Description 142 Z80 CPU User Manual ziloc BIXYS 8 Bit Arithmetic Group
164. r 1 4 1 00 DEC HL 3 11 4 4 3 2 75 DEC IX d 6 23 4 4 3 5 4 3 5 75 DEC IY d 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset His set if borrow from bit 4 otherwise it is reset P V is set if m was 80h before operation otherwise it is reset N is set C is not affected Example If the D Register contains byte 2Ah then upon the execution of a DEC D instruction the D Register contains 29h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOg 170 nIXYS General Purpose Arithmetic and CPU Control Groups The following general purpose arithmetic and CPU control group instructions are each described in this section Simply click to jump to an instruction s description to learn more DAA see page 171 CPL see page 173 NEG see page 174 CCF see page 176 SCF see page 177 NOP see page 178 HALT see page 179 DI see page 180 EI see page 181 IM 0 see page 182 IM 1 see page 183 IM 2 see page 184 Z80 Instruction Set UM008006 07 14 DAA Operation Op Code DAA 4 Operands None Description 27 Z80 CPU User Manual Zilog BIXYS This instruction conditionally adjusts the Accumulator for BCD addition and subtraction operations For addition ADD ADC INC or subtraction SUB SBC DEC NEG the
165. r r identifies any of the registers A B C D E H or L assembled as follows in the object code Register r A 111 000 001 010 011 100 101 r TL muoosu M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is set if carry from bit 3 otherwise it is reset P V is set if r was 7Fh before operation otherwise it is reset UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 164 oLXys N is reset C is not affected Example If the D Register contains 28h then upon the execution of an INC D instruction the D Register contains 29h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZzIlog nIXYS 165 INC HL Operation HL HL 1 Op Code INC Operand HL 0 0 1 1 0 10 0 34 Description The byte contained in the address specified by the contents of the HL register pair is incre mented M Cycles T States 4 MHz E T 3 11 4 4 3 2 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is set if carry from bit 3 otherwise it is reset P V is set if HL was 7Fh before operation otherwise it is reset N is reset C is not affected Example If the HL register pair contains 3434h and address 3434h contains 82h then upo
166. register pair are placed on the address bus to select a location in memory The byte contained in this memory location is temporarily stored in the CPU Then after the byte counter B is decremented the contents of Register C are placed on the bottom half AO through A7 of the address bus to select the I O device at one of 256 possible ports Register B can be used as a byte counter and its decremented value is placed on the top half A8 through A15 of the address bus at this time Next the byte to be output is placed on the data bus and written to the selected peripheral device Then reg ister pair HL is decremented and if the decremented B Register is not 0 the Program Counter PC is decremented by two and the instruction is repeated If B has gone to 0 the instruction is terminated Interrupts are recognized and two refresh cycles are executed after each data transfer Note When B is set to 0 prior to instruction execution the instruction outputs 256 bytes of data If B 0 M Cycles T States 4 MHz E T 5 21 4 5 3 4 5 5 25 780 Instruction Set UM008006 07 14 If B 0 M Cycles T States 4 16 4 5 3 4 Condition Bits Affected S is unknown Z is set H is unknown P V is unknown N is set C is not affected Example Z80 CPU User Manual Zilog nIXYS 313 4 MHz E T 4 00 Register C contains 07h Register B contains 03h the HL register pair contains 1000h and memory locations contain the following d
167. resetting the IEO of A allowing the B routine to continue A second RETI is issued on completion of the B routine and the IEO of B is reset High allowing lower pri ority devices interrupt access Z80 Instruction Set UM008006 07 14 RETN Z80 CPU User Manual Zilog DIXYS Operation Return from nonmaskable interrupt Op Code Operands None Description This instruction is used at the end of a nonmaskable interrupts service routine to restore the contents of the Program Counter analogous to the RET instruction The state of IFF2 is copied back to IFF1 so that maskable interrupts are enabled immediately following the RETN if they were enabled before the nonmaskable interrupt M Cycles T States 4 MHz E T 4 14 4 4 3 3 3 50 Condition Bits Affected None Example If the Stack Pointer contains 1000h and the Program Counter contains 1A45h when a Nonmaskable Interrupt NMI signal is received the CPU ignores the next instruction and instead restarts returning to memory address 0066h The current Program Counter con tains 1A45h which is pushed onto the external stack address of OF FFh and OFFER high order byte first and 0066h is loaded onto the Program Counter That address begins an interrupt service routine that ends with a RETN instruction Upon the execution of a RETN instruction the contents of the former Program Counter are popped off the external memory stack l
168. rflow has occurred This flag is also used with logical operations and rotate instructions to indicate the result ing parity is even The number of 1 bits in a byte are counted If the total is Odd ODD par ity is flagged i e P 0 If the total is even even parity is flagged i e P 1 UM008006 0714 Decimal Adjust Accumulator Flag Z80 CPU User Manual ra ri ZILOgd During the CPI CPIR CPD and CPDR search instructions and the LDI LDIR LDD and LDDR block transfer instructions the P V Flag monitors the state of the Byte Count BC Register When decrementing if the byte counter decrements to 0 the flag is cleared to 0 otherwise the flag is set tol During the LD A and LD A R instructions the P V Flag is set with the value of the inter rupt enable flip flop IFF2 for storage or testing When inputting a byte from an I O device with an IN r C instruction the P V Flag is adjusted to indicate data parity Half Carry Flag The Half Carry Flag H is set 1 or cleared 0 depending on the Carry and Borrow status between bits 3 and 4 of an 8 bit arithmetic operation This flag is used by the Decimal Adjust Accumulator DAA instruction to correct the result of a packed BCD add or sub tract operation The H Flag is set 1 or cleared 0 as shown in Table 22 Table 22 Half Carry Flag Add Subtract Operations HFlag Add Subiract 1 A Carry occurs from bit 3 to bit 4 A Borrow from bit 4 occurs 0 No Carry occurs f
169. rom bit 3 to bit 4 No Borrow from bit 4 occurs Zero Flag The Zero Flag Z is set 1 or cleared 0 if the result generated by the execution of certain instructions is 0 For 8 bit arithmetic and logical operations the Z flag is set to a 1 if the resulting byte in the Accumulator is 0 If the byte is not 0 the Z flag is reset to 0 For Compare search instructions the Z flag is set to 1 if the value in the Accumulator is equal to the value in the memory location indicated by the value of the register pair HL When testing a bit in a register or memory location the Z flag contains the complemented state of the indicated bit see Bit b rin the Bit Set Reset and Test Group section on page 240 When inputting or outputting a byte between a memory location and an INI IND OUTI or OUTD I O device if the result of decrementing Register B is 0 then the Z flag is 1 oth erwise the Z flag is 0 Additionally for byte inputs from I O devices using IN r C the Z flag is set to indicate a 0 byte input Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual zilog nIXYS 67 Sign Flag The Sign Flag S stores the state of the most significant bit of the Accumulator bit 7 When the Z80 CPU performs arithmetic operations on signed numbers the binary twos complement notation is used to represent and process numeric information A positive number is identified by a 0 in Bit 7 A negative number is identified by a 1 The bi
170. rotated left 1 bit position The contents of bit 7 are copied to the Carry flag and also to bit O In the assembled object code operand r is specified as fol lows Register M Cycles UM008006 0714 B gt r Imoo 2 000 001 010 011 100 101 111 T States 8 4 4 4 MHz E T 2 00 Z80 Instruction Description 211 Z80 CPU User Manual ra ZIlog Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is reset P V is set if parity even otherwise it is reset N is reset C is data from bit 7 of source register Example Register r contains the following data 7 6 5 4 3 2 1 0 1 010 0 1 0 0 40 Upon the execution of an RLC r instruction register r and the Carry flag now contain C 7 6 5 4 3 2 1 0 1 0 0 0 4 010 01 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZzIlog nIXYS 213 RLC HL Operation CY 4 7q 0 lt HL Op Code RLC Operand HL Description The contents of the memory address specified by the contents of register pair HL are rotated left 1 bit position The contents of bit 7 are copied to the Carry flag and also to bit 0 Bit 0 is the least significant bit M Cycles T States 4 MHz E T 4 15 4 4 4 3 3 75 Conditio
171. rrect BCD representation is obtained as follows 0011 1100 0000 0110 0100 0010 42 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 173 CPL Operation AcA Op Code CPL Operands None Description The contents of the Accumulator Register A are inverted one s complement M Cycles T States 4 MHz E T 1 4 1 00 Condition Bits Affected S is not affected Z is not affected H is set P V is not affected N is set C is not affected Example If the Accumulator contains 1011 0100 then upon the execution of a CPL instruction the Accumulator contains 0100 1011 UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Z i Ory ILU y 174 OIXYS NEG Operation A 0 A Op Code NEG Operands None Description The contents of the Accumulator are negated two s complement This method is the same as subtracting the contents of the Accumulator from zero gt Note The 80h address remains unchanged M Cycles T States 4 MHz E T 2 8 4 4 2 00 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset His set if borrow from bit 4 otherwise it is reset P V is set if Accumulator was 80h before operation otherwise it is reset N is set C is set if Accumulator was not 00h before operation otherwise
172. ruction M Cycles T States 4 MHz E T RLr 2 8 4 4 2 00 RL HL 4 15 4 4 4 3 3 75 RL IX d 6 23 4 4 3 5 4 3 5 75 RL IY d 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is reset P V is set if parity even otherwise it is reset N is reset C is data from bit 7 of source register Example The D Register and the Carry flag contain the following data C 7 6 5 4 3 2 1 0 1 0 00 1 1 1 1 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 221 Upon the execution of an RL D instruction the D Register and the Carry flag now contain UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Z id Mn L NN MJ 222 nIXYS RRC m Operation Op Code RRC Operand m The m operand is any of r HL IX d or IY d as defined for the analogous RLC instructions In the assembled object code the possible op code operand combinations are specified as follows RRC r 1 1 00 1 0 1 1 CB RRC HL 11 0 0 1 0 1 14 CB RRC IX d 1 1 0 1 1 1 0 1 DD RRC IY d 1 1 1 1 1 1 0 1 FB
173. rupt Response 13 Z80 CPU User Manual Z i ry Per y 14 OLXYS Last M Cycle CLK NMI A15 A0 Figure 10 Nonmaskable Interrupt Request Operation HALT Exit When a software HALT instruction is executed the CPU executes NOPs until an interrupt is received either a nonmaskable or a maskable interrupt while the interrupt flip flop is enabled The two interrupt lines are sampled with the rising clock edge during each T4 state as depicted in Figure 11 If a nonmaskable interrupt is received or a maskable inter rupt is received and the interrupt enable flip flop is set then the HALT state is exited on the next rising clock edge The following cycle is an interrupt acknowledge cycle corre sponding to the type of interrupt that was received If both are received at this time then the nonmaskable interrupt is acknowledged because it is the highest priority The purpose of executing NOP instructions while in the HALT state is to keep the memory refresh sig nals active Each cycle in the HALT state is a normal M1 fetch cycle except that the data received from the memory is ignored and an NOP instruction is forced internally to the CPU The HALT acknowledge signal is active during this time indicating that the proces sor is in the HALT state Architectural Overview UMO008006 0714 Z80 CPU User Manual Z j On AAA nIXYS 15 CLK HALT RD or NMI Figure 11 HALT Exit gt Note The HALT instruction is repeated dur
174. s always pushed first and popped last PUSH BC is PUSH 8 then C PUSH DE is PUSH D then E PUSH HL is PUSH H then L POP HL is POP L then H The instruction using extended immediate addressing for the source requires two bytes of data following the op code as shown in the following example LD DE 0659h The instruction sequence for this value in memory is shown in Figure 37 Z80 CPU Instructions UM008006 0714 Address A E6 A 1 07 Z80 CPU User Manual ZItog nIXYS 45 Op Code Operand Figure 37 Example of a 2 Byte Load Indexed Immediate Instruction Sequence In all extended immediate or extended addressing modes the low order byte always appears first after the op code Table 7 lists the 16 bit exchange instructions implemented in the Z80 CPU Op code 08n allows the programmer to switch between the two pairs of Accumulator flag registers while D9h allows the programmer to switch between the duplicate set of six general pur pose registers These op codes are only one byte in length to minimize the time necessary to perform the exchange so that the duplicate banks can be used to make fast interrupt response times Table 7 Exchanges EX and EXX Implied Addressing BC DE AF andHL HL IX IY Implied AF 08 BC DE D9 HL DE EB Register DD FD Indirect SP ES E3 E3 Block Transfer and Search Table 8 lists the extremely powerful block tr
175. s false the PC is simply incremented as usual and the program continues with the next sequential instruction Condition cc is programmed as one of eight status that correspond to condition bits in the Flag Register Register F These eight status are defined in the following table which also specifies the corresponding cc bit fields in the assembled object code Relevant cc Condition Flag 000 Non Zero NZ Z 001 Zero Z Z 010 Non Carry NC C 011 Carry C C 100 Parity Odd PO P V 101 Parity Even PE P V 110 Sign Positive P S 111 Sign Negative M S UM008006 0714 Z80 Instruction Description 284 Z80 CPU User Manual ZlIlog BIXYS If cc is true then the following data is returned M Cycles T States 4 MHz E T 3 11 5 3 3 2 75 If cc is false then the following data is returned M Cycles T States 4 MHz E T 1 5 1 25 Condition Bits Affected None Example The S flag in the F Register is set the Program Counter contains 3535h the Stack Pointer contains 2000h memory location 2000h contains B5h and memory location 2001h con tains 18h Upon the execution of a RET M instruction the Stack Pointer contains 2002h and the Program Counter contains 18B5h thereby pointing to the address of the next pro gram op code to be fetched Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZzIlog nIXYS 285 RETI Operation Return from Interrupt Op Code RETI
176. sed by the contents of the DE register pair Then both of these register pairs including the Byte Counter BC Regis ter pair are decremented M Cycles T States 4 MHz E T 4 16 4 4 3 5 4 00 Condition Bits Affected S is not affected Z is not affected H is reset P V is set if BC 1 Z 0 otherwise it is reset N is reset C is not affected Example If the HL register pair contains 1111h memory location 1111h contains byte 88h the DE register pair contains 2222h memory location 2222h contains byte 66h and the BC reg Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog BIXYS ister pair contains 7h then instruction LDD results in the following contents in register pairs and memory addresses HL 1111h DE 2222h BC UM008006 0714 contains contains contains contains contains 1110h 88h 2221h 88h 6h Z80 Instruction Description 133 134 Z80 CPU User Manual Ar ZILOgd Operation DE HL DE D 1 HL HL 1 BC BC 1 Op Code LDDR Operands None Description This 2 byte instruction transfers a byte of data from the memory location addressed by the contents of the HL register pair to the memory location addressed by the contents of the DE register pair Then both of these registers and the BC Byte Counter are decre mented If decrementing causes BC to go to 0 the instruction is terminated If BC
177. set by these shift instructions to provide both the testing of shift results and to link register register or register memory shift operations Hardware and Software Implementation UMO008006 0714 Z80 CPU User Manual Zilog nixYs 27 Specific Z80 Instruction Examples Example 1 When a 737 byte data string in memory location DATA must be moved to location BUF FER the operation is programmed as follows LD HL DATA START ADDRESS OF DATA STRING LD DE BUFFER START ADDRESS OF TARGET BUFFER LD BC 737 LENGTH OF DATA STRING LDIR MOVE STRING TRANSFER MEMORY POINTED TO BY HL INTO MEMORY LOCATION POINTED TO BY DE INCREMENT HL AND DE DECREMENT BC PROCESS UNTIL BC 0 Eleven bytes are required for this operation and each byte of data is moved in 21 clock cycles Example 2 A string in memory limited to a maximum length of 132 characters starting at location DATA is to be moved to another memory location starting at location BUFFER until an ASCII used as a string delimiter is found This operation is performed as follows L DATA STARTING ADDRESS OF DATA STRING LD HL LD DE BUFFER STARTING ADDRESS OF TARGET BUFFER LD BC 132 MAXIMUM STRING LENGTH LD A e STRING D
178. ss of the instruction op code and contains a range of 126 to 129 bytes The assembler auto matically adjusts for the twice incremented PC If the Zero Flag 0 the next instruction executed is taken from the location following this instruction If this condition is met the following data results M Cycles T States 4 MHz E T 3 12 4 3 5 3 00 If this condition is not met the following data results M Cycles T States 4 MHz E T 2 7 4 3 1 75 Condition Bits Affected None Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 269 Example The Zero Flag is set and it is required to jump forward five locations from address 300 The following assembly language statement is used JR Z 5 The resulting object code and final Program Counter value are Location Instruction 300 28 301 03 302 303 304 305 PC after jump UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOQd 270 nIXYS JR NZ e Operation If Z 1 continue IfZ 0 PC pc e Op Code JR Operands NZ e Description This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Zero Flag If the flag 0 the value of displace ment e is added to the Program Counter PC and the next instruction is fetched from the location designated by the new contents of the PC The jump is measur
179. ss of the byte following the call instruction is pushed onto the stack before the jump is made A return instruction is the reverse of a call because the data on the top of the stack is popped directly into the Pro UM008006 0714 Jump Call and Return 58 Z80 CPU User Manual zilc fy JU BIXYS gram Counter to form a jump address The call and return instructions allow for simple subroutine and interrupt handling Two special return instruction are included in the Z80 family of microprocessors The return from interrupt instruction RETI and the return from nonmaskable interrupt RETN are treated in the CPU as an unconditional return identical to the op code C9h The difference is that RETI can be used at the end of an interrupt routine and all Z80 peripheral chips recognize the execution of this instruction for proper control of nested priority interrupt handling This instruction coupled with the Z80 CPU s peripheral devices implementation simplifies the normal return from nested interrupt Without this feature the following software sequence is necessary to inform the interrupting device that the interrupt routine is completed Disable Interrupt Prevent interrupt before routine is exited LD A n Notify peripheral that service routine is complete OUT n A Enable Interrupt Return This seven byte sequence can be replaced with the one byte El instruction and the two byte RETI instruction in the Z80 CPU This instr
180. ssembled as follows in the object code Pair BC DE HL SP dd 00 01 10 11 The first n operand after the op code is the low order byte of a two byte memory address M Cycles 6 Condition Bits Affected None Z80 Instruction Set T States 20 4 4 3 3 3 3 4 MHz E T 5 00 UM008006 0714 Z80 CPU User Manual Zilog nIXYS 107 Example If register pair BC contains the number 4644h the instruction LD 1000h BC results in 44h in memory location 1000h and 46h in memory location 1001h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual zilog ILU hos 108 nIXYS LD nn IX Operation nn 1 IXh nn IXI Op Code LD Operands nn IX ra n ra n Description The low order byte in Index Register IX is loaded to memory address nn the upper order byte is loaded to the next highest address nn 1 The first n operand after the op code is the low order byte of nn M Cycles T States 4 MHz E T 6 20 4 4 3 3 3 3 5 00 Condition Bits Affected None Example If Index Register IX contains 5A30h then upon the execution of an LD 4392h IX instruction memory location 4392h contains number 30h and location 4393h contains 5Ah Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg nIXYS 109 LD nn IY Operation nn 1 IYh nn IYI Op Code LD Operands nn IY
181. ssing Mode 0 cee eee eee 35 Relative Addressing Mode 1 0 0 0 eee cece eee 35 List of Figures xii Z80 CPU User Manual Zilog OIXYS List of Figures Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Extended Addressing Mode 00 cece eee eee eee eee 36 Indexed Addressing Mode 0 0 0 ccc eee eee 36 Register Indirect Addressing Mode 0 ee eee eee ee 37 Example of a 3 Byte Load Indexed Instruction Sequence 41 Example of a 3 Byte Load Extended Instruction Sequence 42 Example of a 2 Byte Load Immediate Instruction Sequence 42 Example of a 4 Byte Load Indexed Immediate Instruction Sequence 42 Example of a 16 Bit Load Operation 00000000000 44 Example of a 2 Byte Load Indexed Immediate Instruction Sequence 45 Example of an AND Instruction Sequence 0200000005 49 Rotates and Shifts 0 0 ceed ede tee eee eae de RR ee 52 Example of an Unconditional Jump Sequence 0 4 56 Mode 2 Interrupt Command 0 0 cece eee eee 62 UM008006 0714 Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22
182. st Of PISUTES ota sia anabel a s ate la ata e aa xi Last ot Tables aeo ste be veau vedo ete e dog Aw e ER reda Re AUR ace xiii Architectural Overview 0 cece cent tenet eee eens 1 CPU Register sucinta ee Eae Gane eed Bh re da Mate e 2 Special Purpose Registers essel 2 General Purpose Registers llle 3 Arithmetic Logic Unit oocoocononrononc no saa hh hee 4 Instruction Register and CPU Control 0 0 cece eee 4 Pin P nctions 22 get a ea al ead alata wate 5 TIMIDE ve eee US eM eR Aine Ligh ide a aie od lees e 7 Instruction Fetch 2 cece I enna 8 Memory Read Or Write 0 ete e 9 Input or Output Cycles 0 cece een nee 10 Bus Request Acknowledge Cycle eee ees 11 Interrupt Request Acknowledge Cycle 0 0 cece eee eee 12 Nonmaskable Interrupt Response 0 0 0 0 e eee eee eee eee 13 HALT EX posteros ab eae od eee ei hah the Rd ar eet ase 14 Power Down Acknowledge Cycle 0 0 e eee eee eee 15 Power Down Release Cycle oooooccococccccccr eee 16 Interrupt Response lseeeeeeeeeeeee hrs 17 Interrupt Enable Disable sseleeeeee ce eee 17 CPU Response ios Ate eee desea hades A weeds fes a 19 Hardware and Software Implementation 20 0 cece eee eee ee 21 Minimum System Hardware ooooccccococcncc eee 21 Adding RAM tic A hee Ee a eka LRA tm 22 Memory Speed Control ooooococoocccococo eh 23 Interfacing Dyna
183. start at address 0066h The CPU functions as if it had recycled a restart instruction but to a location other than one of the eight software restart locations A restart is merely a call toa specific address in Page 0 of memory The CPU can be programmed to respond to the maskable interrupt in any one of three pos sible modes Mode 0 Mode 0 is similar to the 8080A interrupt response mode With Mode 0 the interrupting device can place any instruction on the data bus and the CPU executes it Consequently the interrupting device provides the next instruction to be executed Often this response is a restart instruction because the interrupting device is required to supply only a single byte instruction Alternatively any other instruction such as a 3 byte call to any location in memory could be executed The number of clock cycles necessary to execute this instruction is two more than the nor mal number for the instruction The addition of two clock cycles occurs because the CPU automatically adds two wait states to an Interrupt response cycle to allow sufficient time to implement an external daisy chain for priority control Figures 9 and 10 on page 13 show the timing for an interrupt response After the application of RESET the CPU automati cally enters interrupt Mode 0 Mode 1 When Mode 1 is selected by the programmer the CPU responds to an interrupt by execut ing a restart at address 0038h As a result the response is identical t
184. sters can be used individually as 8 bit registers or as 16 bit register pairs One set is called BC DE and HL while the complementary set is called BC DE and HL At any one time the pro grammer can select either set of registers to work through a single exchange command for the entire set In systems that require fast interrupt response one set of general purpose registers and an Accumulator Flag Register can be reserved for handling this fast routine One exchange command is executed to switch routines This process greatly reduces inter rupt service time by eliminating the requirement for saving and retrieving register contents in the external stack during interrupt or subroutine processing These general purpose reg UM008006 0714 General Purpose Registers Z80 CPU User Manual ra ri ZILOgd isters are used for a wide range of applications They also simplify programing specifi cally in ROM based systems in which little external read write memory is available Arithmetic Logic Unit The 8 bit arithmetic and logical instructions of the CPU are executed in the Arithmetic Logic Unit ALU Internally the ALU communicates with the registers and the external data bus by using the internal data bus Functions performed by the ALU include Add Subtract Logical AND Logical OR Logical exclusive OR Compare Left or right shifts or rotates arithmetic and logical Increment Decrement Set bit Reset bit Test bit In
185. struction SLA r SLA HL SLA IX d SLA IY d Condition Bits Affected 2 4 6 6 M Cycles T States 8 4 4 15 4 4 4 3 23 4 4 3 5 4 3 23 4 4 3 5 4 3 S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is reset P V is set if parity is even otherwise it is reset N is reset C is data from bit 7 Example Register L contains the following data 7 6 5 4 3 2 4 0 4 0 4 4 0 0 0 4 UM008006 0714 4 MHz E T 2 00 3 75 5 75 5 75 Z80 Instruction Description Z80 CPU User Manual Zilog 230 nIXYS Upon the execution of an SLA L instruction Register L and the Carry flag now contain Z80 Instruction Set UM008006 07 14 SRA m UM008006 0714 Operation 7 e CY m Op Code SRA Operand m Z80 CPU User Manual Zilog BIXYS The m operand is any of r HL X d or 1Y d as defined for the analogous PLC instructions In the assembled object code the possible op code operand combinations are specified as follows SRA r 1 1 SRA HL 1 4 SRA IX d 1 1 SRA IY d 11 CB CB 2E DD CB 2E
186. struction the Program Counter contains 4800h Z80 Instruction Set UM008006 07 14 JP IX Z80 CPU User Manual ZItog DIXYS Operation pe IX Op Code JP Operand IX Description The Program Counter PC is loaded with the contents of the IX register pair The next instruction is fetched from the location designated by the new contents of the PC M Cycles T States 4 MHz E T 2 8 4 4 2 00 Condition Bits Affected None Example If the Program Counter contains 1000h and the IX register pair contains 4800h then upon the execution of a JP IX instruction the Program Counter contains 4800h UM008006 0714 Z80 Instruction Description 273 274 Z80 CPU User Manual Z T On ILU y OIXYS JP IY Operation PC IY Op Code JP Operand IY Description The Program Counter PC is loaded with the contents of the IY register pair The next instruction is fetched from the location designated by the new contents of the PC M Cycles T States 4 MHz E T 2 8 4 4 2 00 Condition Bits Affected None Example If the Program Counter contains 1000h and the IY register pair contains 4800h then upon the execution of a JP 1Y instruction the Program Counter contains 4800h Z80 Instruction Set UM008006 07 14 DJNZ e Operation B lt B 1 If B 0 continue IfB 0 PC PC e Op Code DINZ Operand
187. struction Register and CPU Control As each instruction is fetched from memory it is placed in the Instruction Register and decoded The control sections performs this function and then generates and supplies the control signals necessary to read or write data from or to the registers control the ALU and provide required external control signals Pin Description The Z80 CPU I O pins are shown in Figure 3 The function of each pin is described in the section that follows Architectural Overview UM008006 0714 M 4 System IORQ lt 21 Control RD A wa RFSH A HALT q WAIT 24 y i a Z80 CPU NM RESET 2o Y CPU BUSRQ 2 y Bus 23 Control BUSACK lt CLK y 5V GND Figure 3 Z80 CPU I O Pin Configuration Pin Functions 30 31 32 33 34 35 36 37 38 39 40 ajA JO JM 14 15 12 10 13 AO Al A2 A3 A4 AS A6 A7 A8 AQ A10 A11 A12 A13 A14 A15 DO D1 D3 D4 D5 D6 D7 Z80 CPU User Manual ion Zi LU UU BIXYS Address Bus Data Bus A15 A0 Address Bus output active High tristate A15 A0 form a 16 bit Address Bus which provides the addresses for memory data bus exchanges up to 64 KB and for I O device exchanges BUSACK Bus Acknowledge output active Low Bus Acknowledge indicates to the requesting device that the CPU address bus data bus and control signals MREQ IORQ UM008006 0714
188. struction Set UM008006 07 14 Z80 CPU User Manual ZItog nIXYS 241 BIT b r Operation Z lt rb Op Code BIT Operands b r Description This instruction tests bit b in register r and sets the Z flag accordingly In the assembled object code operands b and r are specified as follows Bit Tested b Register r 0 000 B 000 1 001 C 001 2 010 D 010 3 011 E 011 4 100 H 100 5 101 L 101 6 110 A 111 7 111 M Cycles T States 4 MHz E T 2 8 4 4 4 50 Condition Bits Affected S is unknown Z is set if specified bit is 0 otherwise it is reset UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog DIXYS H is set P V is unknown N is reset C is not affected Example If bit 2 in Register B contains 0 then upon the execution of a BIT 2 B instruction the Z flag in the F Register contains 1 and bit 2 in Register B remains at 0 Bit 0 in Register B is the least significant bit Z80 Instruction Set UM008006 0714 Z80 CPU User Manual ZIlOg nIXYS 243 BIT b HL Operation Z HL b Op Code BIT Operands b HL Description This instruction tests bit b in the memory location specified by the contents of the HL reg ister pair and sets the Z flag accordingly In the assembled object code operand b is speci fied as follows Bit Tested b 0 000 1 001 2 010 3 011 4 100 5 10
189. struction is fetched from the location designated by the new contents of the PC The jump is measured from the address of the instruction op code and contains a range of 126 to 129 bytes The assembler automatically adjusts for the twice incremented PC If the flag 1 the next instruction executed is taken from the location following this instruction If the condition is met M Cycles T States 4 MHz E T 3 12 4 3 5 3 00 If the condition is not met M Cycles T States 4 MHz E T 7 7 4 3 1 75 Condition Bits Affected None Z80 Instruction Set UM008006 07 14 Example The Carry Flag is reset and it is required to repeat the jump instruction guage statement is JR NC The resulting object code and Program Counter after the jump are Location Instruction 480 30 PC after jump 481 00 Z80 CPU User Manual Zilog nIXYS 267 The assembly lan Z80 Instruction Description UM008006 0714 Z80 CPU User Manual ZILOQd 268 nIXYS Operation If Z 0 continue IfZ 1 PC lt PC e Op Code JR Operands Ze Description This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Zero Flag If the flag 1 the value of displace ment e is added to the Program Counter PC and the next instruction is fetched from the location designated by the new contents of the PC The jump is measured from the addre
190. struction is fetched from the memory location specified by the PC This instruction is normally used to return to the main line program at the completion of a routine entered by a CALL instruction M Cycles T States 4 MHz E T 3 10 4 8 3 2 50 Condition Bits Affected None Example The Program Counter contains 3535h the Stack Pointer contains 2000h memory loca tion 2000h contains B5h and memory location 2001h contains 18h Upon the execution of a RET instruction the Stack Pointer contains 2002h and the Program Counter contains 18B5h thereby pointing to the address of the next program op code to be fetched Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 283 RET cc Operation If cc true PCL sp pCH sp 1 Op Code RET Operand cc Description If condition cc is true the byte at the memory location specified by the contents of the Stack Pointer SP Register pair is moved to the low order eight bits of the Program Coun ter PC The SP is incremented and the byte at the memory location specified by the new contents of the SP are moved to the high order eight bits of the PC The SP is incremented again The next op code following this instruction is fetched from the memory location specified by the PC This instruction is normally used to return to the main line program at the completion of a routine entered by a CALL instruction If condition cc i
191. t ER dea eas Ede 137 CPD ta AS BN a tat eds e sd and 139 CBDR esses Sad sie o w H 5 140 ADD AT id RP ance dep aede qe 143 ADDA D A Puis iue teu EE 145 ADD As CHIL ai uev Gas dec ene s ER dea E c EE a 146 ADD A IXE dos tus dd dde 147 ADDA LY Fd iaa ata o ea e a eq 148 ADC A S a idad 149 SUBS AP debs Sia ee haa ata abs ean bd wa ea dae SS ae 151 SBC A Sia di di rad a debe Gund ates dido 153 AND M rcc 155 ORS m 157 Y A t Ee EE a E EE E EEE S E A ea 159 CP Sri fda daa ada da bra aca a laa ants aia 161 TING 455i ee a AAA deus EO A ae o 163 NA a ane ein EVE O lU NN 165 INCADCEd 2 a A A A a See 166 INCA anio 167 DEC ID ca daa e e a a a a taa 168 DAA m 171 CPL ud eirate eiaa eea sibs Glew eid ded ded tis EE E 173 NEG e eae NS 174 CCE aaee SS NN 176 DOB iu rod ditor AO 177 NOP ie BS eo a ton a aa ane tds ach RE E E E 178 HALET esa ad E ae en eae apn es E 179 Dina dai iaa di os 180 lc 181 IMO o stewie Gee d pides dedu pip ee ve e UU iV 182 E LM EE 183 IM Zara ia aia nik he eer epa a hb eU b achebe ep eia 184 ADD HESS ur Re RU iii eng 186 ADC HI SS ci eda ea RUE RERO SANE sha d eo Ce RO TER 188 SBC HL SS 000 eR Ed EE eR rior nein ad asc drea ue s 190 ADD AX DP cireni tria beber eb etae a drap t Sie S 192 ADD LDY TE uk E Er RE ten EC nc we EC RE c ac i SHORE ORE na 194 INES PO 196 ING IX sidad Shee bhai dads debe ed rr HER Hed SAR tees 197 TING DY ies o oo ias 198 UM008006 0714 UM0
192. t affected Example If Index Register IX contains 2000h and bit 6 in memory location 2004h contains 1 then upon the execution of a BIT 6 IX 4n instruction the Z flag in the F Register contains a 0 and bit 6 in memory location 2004h still contains a 1 Bit 0 in memory location 2004h is the least significant bit Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual ZILOg OLXYs 247 BIT b IY d Operation Z IY d b Op Code BIT Operands b IY d Description This instruction tests bit b in the memory location specified by the contents of register pair TY combined with the two s complement displacement d and sets the Z flag accordingly In the assembled object code operand b is specified as follows Bit Tested b 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 M Cycles T States 4 MHz E T 5 20 4 4 3 5 4 5 00 UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Zilog 248 nIXYS Condition Bits Affected S is unknown Z is set if specified bit is 0 otherwise it is reset H is set P V is unknown H is reset C is not affected Example If Index Register contains 2000h and bit 6 in memory location 2004h contains a 1 then upon the execution of a BIT 6 IY 4n instruction the Z flag and the F Register still con tains a 0 and bit 6 in memory location 2004h still contains a 1 Bit 0 in memory location 200
193. t instruction is fetched from the location designated by the new contents of the PC The jump is measured from the address of the instruction op code and contains a range of 126 to 129 bytes The assembler auto matically adjusts for the twice incremented PC If the flag 0 the next instruction executed is taken from the location following this instruction If condition is met M Cycles T States 3 12 4 3 5 If condition is not met M Cycles T States 2 7 4 3 Condition Bits Affected None Z80 Instruction Set 4 MHz E T 3 00 4 MHz E T 1 75 UM008006 0714 Z80 CPU User Manual Zilog nIXYS 265 Example The Carry flag is set and it is required to jump back four locations from 480 The assembly language statement is JR C 4 The resulting object code and final Program Counter value is shown in the following table Location Instruction 47C PC after jump 47D 47E gt 47F 480 38 481 FA two s complement 6 UM008006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOQg 266 nIXYS JR NC e Operation If C 1 continue If C20 PC PC e Op Code JR Operands NC e Description This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Carry Flag If the flag is equal to 0 the value of displacement e is added to the Program Counter PC and the next in
194. t instruction types including all 78 of the 8080A CPU The instructions fall into these major groups e Load and Exchange e Block Transfer and Search e Arithmetic and Logical e Rotate and Shift e Bit Manipulation Set Reset Test e Jump Call and Return e Input Output e Basic CPU Control Instruction Types The load instructions move data internally among CPU registers or between CPU registers and external memory All of these instructions specify a source location from which the data is to be moved and a destination location The source location is not altered by a load instruction Examples of load group instructions include moves between any of the gen eral purpose registers such as move the data to Register B from Register C This group also includes load immediate to any CPU register or to any external memory location Other types of load instructions allow transfer between CPU registers and memory loca tions The exchange instructions can trade the contents of two registers A unique set of block transfer instructions is provided in the Z80 CPU With a single instruction a block of memory of any size can be moved to any other location in memory This set of block moves is extremely valuable when processing large strings of data With a single instruction a block of external memory of any required length can be searched for any 8 bit character When the character is found or the end of the block is reached the instruction auto
195. te or they can be lengthened to synchronize the CPU to the speed of external devices These clock periods are referred to as time T cycles and the operations are referred to as machine M cycles Figure 4 shows how a typical instruc tion is a series of specific M and T cycles In Figure 4 this instruction consists of the three machine cycles M1 M2 and M3 The first machine cycle of any instruction is a fetch cycle that is four five or six T cycles long unless lengthened by the WAIT signal which is described in the next section The fetch cycle M1 is used to fetch the op code of the next instruction to be executed Subsequent machine cycles move data between the CPU and memory or I O devices and they can feature anywhere from three to five T cycles again they can be lengthened by wait states to synchronize external devices to the CPU The following paragraphs describe the timing which occurs within any of the basic machine cycles During T2 and every subsequent automatic WAIT state TW the CPU samples the WAIT line with the falling edge of the clock If the WAIT line is active at this time another UM008006 0714 Timing Z80 CPU User Manual ra ri ZILOgd WAIT state is entered during the following cycle Using this technique the read can be lengthened to match the access time of any type of memory device See the Input or Out put Cycles section on page 10 to learn more about the automatic WAIT state T Cycle CLK T1 T2 T
196. then incremented M Cycles T States 4 MHz E T 6 23 4 4 3 5 4 3 5 75 Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if result is 0 otherwise it is reset H is set if carry from bit 3 otherwise it is reset P V is set if 1Y d was 7Fh before operation otherwise it is reset N is reset C is not affected Example If Index Register IY are 2020h and memory location 2030h contains byte 34h then upon the execution of an INC JY 10h instruction memory location 2030h contains 35h UM008006 0714 Z80 Instruction Description Z80 CPU User Manual Z i Ory ILU y 168 nIXYS DEC m Operation me m 1 Op Code DEC Operand m The m operand is any of r HL IX d or IY d as defined for the analogous INC instructions These possible op code operand combinations are assembled as follows in the object code DEC r 0 0 Mw r gt 11011 DEC HL 0 0 1 1 0 110 1 35 DEC IX d 1 14 o0 14 14 4 0 14 DD DEC IY d 1 1 1 1 1 1 0 1 FD r identifies registers B C D E H L or A assembled as follows in the object code field Register r B 000 C 001 D 010 E 011 H 100 L 101 A 111 Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 169 Description The byte specified by the m operand is decremented Instruction M Cycles T States 4 MHz E T DEC
197. tions as shown in Tables 17 and 18 The addressing of the input or output device can be either absolute or Register Indirect using the C register In the Register Indirect addressing mode data can be transferred between the I O devices and any of the internal registers In addition eight block transfer instructions are implemented These instructions are similar to the memory block transfers except that they use register pair HL for a pointer to the memory source output commands or destination input commands while Register B is used as a byte counter Register C holds the address of the port for which the input or output command is required Because Register B is eight bits in length the I O block transfer command han dles up to 256 bytes In the IN A and OUT n A instructions the I O device s n address appears in the lower half of the address bus A7 A0 while the Accumulator content is transferred in the upper half of the address bus In all Register Indirect input output instructions including block I O transfers the contents of the C Register are transferred to the lower half of the address bus device address while the contents of Register B are transferred to the upper half of the address bus UM008006 0714 Input Output Z80 CPU User Manual Z lloc L NN MJ 60 nIXYS Table 17 Input Group Register Immediate Indirect n c DB ED n 7B ED 40 ED 48 Input Register ED IN Address 50 ED 58 Input
198. to specify a displacement from the existing program to which a program jump can occur This displacement is a signed two s complement number that is added to the address of the op code of the follow ing instruction Op Code Jump Relative One Byte Op Code L gt 8 bit Two s Complement Op Code Displacement Added to Address A 2 Figure 28 Relative Addressing Mode The value of relative addressing is that it allows jumps to nearby locations while only requiring two bytes of memory space For most programs relative jumps are by far the most prevalent type of jump due to the proximity of related program segments Therefore these instructions can significantly reduce memory space requirements The signed dis placement can range between 127 and 128 from A 2 This range allows for a total dis placement of 129 to 126 from the jump relative op code address Another major advantage is that it allows for relocatable code UM008006 0714 Modified Page Zero Addressing Z80 CPU User Manual ra ri ZILOgd Extended Addressing Extended Addressing provides for two bytes 16 bits of address to be included in the instruction This data can be an address to which a program can jump or it can be an address at which an operand is located One or Op Code f Two Bytes low order Address to low order Operand high order Address to low order Operand Figure 29 Extended Addressing Mode Extended addressi
199. truction is terminated If BC is not 0 and A Z HL the program counter is decremented by two and the instruction is repeated Inter rupts are recognized and two refresh cycles are executed after each data transfer If BC is set to O before instruction execution the instruction loops through 64 KB if no match is found For BC 0 and A HL M Cycles T States 4 MHz E T 5 21 4 4 3 5 5 5 25 For BC 0 and A HL M Cycles T States 4 MHz E T 4 16 4 4 3 5 4 00 UMO08006 0714 Z80 Instruction Description 138 Z80 CPU User Manual ZIlog BIXYS Condition Bits Affected S is set if result is negative otherwise it is reset Z is set if A equals HL otherwise it is reset H is set if borrow from bit 4 otherwise it is reset P V is set if BC 1 does not equal 0 otherwise it is reset N is set C is not affected Example If the HL register pair contains 1111h the Accumulator contains F3h the Byte Counter contains 0007h and memory locations contain the following data 1111h contains 52h 1112h contains 00h 1113h contains F3h Upon the execution of a CPIR instruction register pair HL contains 1114h the Byte Counter contains 000 4h the P V flag in the F Register is set and the Z flag in the F Reg ister is set Z80 Instruction Set UM008006 07 14 CPD Z80 CPU User Manual Zilog BIXYS Operation A HL HL HL 1 BC BC 1 Op Code CPD Operands None
200. uction is important because interrupt ser vice time often must be minimized The DJNZ instruction is used to facilitate program loop control This two byte relative jump instruction decrements Register B and the jump occurs if Register B is not decre mented to 0 The relative displacement is expressed as a signed two s complement num ber A simple example of its use is shown in Table 15 Table 15 Example Usage of the DJNZ Instruction Address Instruction Comments N N 1 LD B 7 Set B Register to count of 7 N 2 to N 9 Perform a sequence of instructions Loop to be performed 7 times N 10 N 11 DJNZ 8 To jump from N 12 to N 2 N 12 Next instruction Table 16 lists the eight op codes for the Restart instruction which is a single byte call to any of the eight addresses listed A simple mnemonic for each of these eight calls is also listed The Restart instruction is useful for frequently used routines due to its minimal memory consumption Z80 CPU Instructions UM008006 0714 Z80 CPU User Manual ZzIlog nIXYS 59 Table 16 Restart Group Op Code 0000h C7 RST 0 0008h CF RST 8 0010h D7 RST 16 0018h DF RST 24 CALL Address 0020h E7 RST 32 0028h EF RST 40 0030h F7 RST 48 0038h FF RST 56 Note Descriptions of the Call and Return Group instructions begin on page 277 Input Output The Z80 CPU contains an extensive set of input and output instruc
201. y Overflow Flag The Parity Overflow P V Flag is set to a specific state depending on the operation being performed For arithmetic operations this flag indicates an overflow condition when the result in the Accumulator is greater than the maximum possible number 127 or is less than the minimum possible number 128 This overflow condition is determined by examining the sign bits of the operands For addition operands with different signs never cause overflow When adding operands with similar signs and the result contains a different sign the Overflow Flag is set as shown in the following example 120 0111 1000 ADDEND 105 0110 1001 AUGEND 225 1110 0001 95 SUM The two numbers added together result in a number that exceeds 127 and the two posi tive operands result in a negative number 95 which is incorrect The Overflow Flag is therefore set For subtraction overflow can occur for operands of unalike signs Operands of alike signs never cause overflow as shown in the following example 127 0111 1111 MINUEND 64 1100 0000 SUBTRAHEND 191 1011 1111 DIFFERENCE The minuend sign has changed from a positive to a negative resulting in an incorrect dif ference the Overflow Flag is set Another method for identifying an overflow is to observe the Carry to and out of the sign bit If there is a Carry in and no Carry out or if there is no Carry in and a Carry out then an Ove
202. z E T 4 14 4 4 3 3 3 50 Condition Bits Affected None Example If the Stack Pointer contains 1000h memory location 1000h contains 55h and location 1001h contains 33h the instruction POP 1X results in Index Register IX containing 3355h and the Stack Pointer containing 1002h UMO08006 0714 Z80 Instruction Description Z80 CPU User Manual ZILOQd 120 nIXYS Operation IYH SP X1 IYL SP Op Code POP Operand IY Description The top two bytes of the external memory last in first out LIFO stack are popped to Index Register IY The Stack Pointer SP Register pair holds the 16 bit address of the cur rent top of the Stack This instruction first loads to the low order portion of IY the byte at the memory location corresponding to the contents of SP then SP is incremented and the contents of the corresponding adjacent memory location are loaded to the high order por tion of IY The SP is incremented again M Cycles T States 4 MHz E T 4 14 4 4 3 3 3 50 Condition Bits Affected None Example If the Stack Pointer Contains 1000h memory location 1000h contains 55h and location 1001h contains 33h the instruction POP Y results in Index Register IY containing 3355h and the Stack Pointer containing 1002h Z80 Instruction Set UM008006 07 14 Z80 CPU User Manual Zilog nIXYS 121 Exchange Block Transfer and Search Group The following exchange

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