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Z80380 CPU User's Manual

1. N lt 2 1 INTRODUCTION The Z380 CPU supports five address spaces correspond ing to the different types of locations that can be ad dressed and the method by which the logical addresses are formed These five address spaces are CPU Register Space This consists of all the register addresses in the CPU register file m CPU Control Register Space This consists of the Select Register SR m Memory Address Space This consists of the addresses of all locations in the main memory 2 2 CPU REGISTER SPACE The Z380 register file is illustrated in Figure 2 1 Note that this figure shows the configuration of the register on the Z380 CPU and the number ofthe register files may vary on future Superintegration devices The Z380 CPU contains abundant register resources At any given time the pro gram has immediate access to both primary and alternate registers in the selected register set Changing register sets is a simple matter of an LDCTL instruction to program the Select Register SR The CPU register file is divided into five groups of registers an apostrophe indicates a register in the auxiliary regis ters Four sets of Flag and Accumulator registers F A A gm Four sets of Primary and Working registers B C D E H L LP DC 8297 03 USER s MANUAL CHAPTER 2 ADDRESS SPACES m External I O Address Space This consists of all external I O ports addr
2. Syntax Instruction Format Time Note CPI 11101101 10100001 3 r X DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL CPIR COMPARE INCREMENT AND REPEAT BYTE CPIR Repeat until BC 0 OR match begin A HL if XM then begin HL 31 0 lt HL 31 0 1 else begin HL 15 0 lt HL 15 0 1 15 0 lt 15 0 1 end This instruction is used for searching strings of byte data The bytes of data starting at the location addressed by the HL register are compared with the contents of the accumulator until either an exact match is found or the string length is exhausted becuase the BC register has decremented to zero The Sign and Zero flags are set to reflect the result of the comparison The contents of the accumulator and the memory bytes are unaffected Two s complement subtraction is performed After each comparison the HL register is incremented by one thus moving the pointer to the next element in the string The BC register used as a counter is then decremented by one If the result of decrementing the BC register is not zero and no match has been found the process is repeated If the contents of the BC register are zero at the start of this instruction a string length of 65 536 is indicated This instruction can be interrupted after each execution of the basic operation The PC value at the start of this instruction is pushed onto the sta
3. I O Instruction A31 A24 A23 A16 A15 A8 A7 A0 IN A n 00000000 00000000 A7 A0 n IN dst C BC31 B24 BC23 B16 BC15 B8 7 0 dst mn 00000000 00000000 n DDIR IB INA W dst Imn 00000000 n DDIR IW INA W dst kimn k n Block Input BC31 B24 BC23 B16 BC15 B8 7 0 OUT n A 00000000 00000000 A7 A0 n OUT C dst BC31 B24 BC23 B16 BC15 B8 7 0 OUTA W mn dst 00000000 00000000 m n DDIR IB OUTA W Imn dst 00000000 n DDIR IW OUTA W kimn dst k n Block Output BC31 B24 BC23 B16 BC15 B8 7 0 2 6 ON CHIP I O ADDRESS SPACE The Z380 CPU has the on chip I O address space to control on chip peripheral functions of the Superintegra tion version of the devices A portion of its interrupt functions are also controlled by several on chip registers which occupy an on chip I O address space This on chip address space canbe accessed only with the following reserved on chip instructions which are identical to the 2180 original instructions to access Page 0 ad dressing area R n OTIM INO OUTO n R OTDM TSTIO n OTDMR When one of these instructions is executed the 2380 MPU outputs the register address being accessed in a pseudo transaction of two BUSCLK cycles duration with the address signals A31 A8 at zero In the pseudo trans actions all bus control signals are at their inactive state The following four registers are a
4. d d d d 00 for NZ 01 for Z 10 for NC 11 for C ote x gt x x gt x x x 2 5 81 The contents of the source are loaded into the destination 7106 LD LOAD ACCUMULATOR LD dst src Operation dst src Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Load into Accunulator Addressing Mode Syntax R LD A R RX LD A RX IM LD A n IR LD A HL LD A IR DA LD A nn X LD A XY d Load from Accunulator Addressing Mode Syntax R LD Rd A RX LD RX A IR LD HL A LD IR A DA LD nn A X LD XY d A dst src R RX IM IR DA X or dst R RX IR DA X src Instruction Format 01111 r 11y11101 0111110w 00111110 n 01111110 00041010 00111010 n low n high 11y11101 01111110 d Instruction Format 01 r 111 11y11101 0110w111 01110111 00020010 00110010 n low n high 11y11101 01110111 d Field Encodings 5 82 per convention y O for IX 1 for IY w Oforhigh byte 1 for low byte a Ofor BC 1 for DE 2380 USER S MANUAL Execute Time Note 2 2 2 2 r 2 r 3 r 4 r Time Note 2 2 3 W 3 w 4 w 5 w DC 8297 03 2380 7106 USER S MANUAL LD LOAD IMMEDIATE BYTE LD dst n dst RX IR X Operation dst n The byte of immediate data is loaded into the destinatio
5. selected flag satisfies the condition code specified in the instruction Unconditional Call always transfers control to the destination address The current contents of the Program Counter PC are pushed onto the top of the stack the PC value used is the address of the first instruction byte following the Call instruction The destination address is then loaded into the PC and points to the first instruction of the called procedure At the end procedure Return instruction RET can be used to return to the original program Each of the Zero Carry Sign and Overflow Flags can be individually tested and call performed conditionally on the setting of the flag The operand is not enclosed in parentheses with the CALL instruction Flags S Unaffected 2 Unaffected H Unaffected V Unaffected Unaffected C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note DA CALL CC addr 11 cc100 a low a high note X CALL addr 11001101 a low a high 4 w X Field Encodings cc 000 for NZ 001 for Z 010 for NC 011 for C 100 for PO or NV 101 for PE or V 110 for P or NS 111 for M or S Note 2 if CC is false 4 w if CC is true DC 8297 03 2380 USER S MANUAL CALL CALL 5 31 7106 CALR CALL RELATIVE Operation Flags Addressing Mode RA CALR cc dst dst RA if cc is true then begin dst lt SIGN EXTEND dst if XM then begin SP lt SP 4 SP
6. 11101101 00 r 000 n 3 i none INO n 11101101 00110000 n 3 i Field Encodings r per convention DC 8297 03 5 67 7106 2380 USER S MANUAL INPUT DIRECT FROM PORT ADDRESS BYTE Operation Flags Addressing Mode 5 68 INA lt The byte of data from the selected peripheral is loaded into the accumulator During the I O transaction the peripheral address from the instruction is placed on the address bus Any bytes of address not specified in the instruction are driven on the address lines as all zeros S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Execute Syntax Instruction Format Time Note INA nn 11101101 11011011 n low n high 3 1 DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 INAW HL nn HL 15 0 The word of data from the selected peripheral is loaded into the HL register During the I O transaction the peripheral address from the instruction is placed on the address bus Any bytes of address not specified in the instruction are driven on the address lines as all zeros S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Syntax INAW nn lt Instruction Format 11111101 11011011 n low n high 2380 USER S MANUAL INAW INPUT DIRECT FROM PORT ADDRESS WORD Note 5 69 2380 7106 USER S
7. Before instruction execution 1234 5678 9ABC DEFO After instruction execution 1234 DEFO 9 DEFO 2 Load register in Long Word mode DDIR LW Next instruction in Long Word mode LD BC HL Load the contents of HL into BC BCz BC HLz HL Before instruction execution 1234 5678 9ABC DEFO After instruction execution 9ABC DEFO 9 DEFO 4 2 2 Immediate IM When the Immediate addressing mode is used the data processed is in the instruction The Immediate addressing mode is the only mode that does not indicate register or memory address as the source operand 4 1 2106 4 2 2 Immediate IM Continued Instruction OPERATION OPERAND The operand value is in the instruction Immediate mode is often used to initialize registers Also this addressing mode is affected by the DDIR Immediate Data Directives to expand the immediate value to 24 bits or 32 bits Example of IM mode 1 Load immediate value into accumulator LD A 55H Load hex 55 into the accumulator A Before instruction execution 12 After instruction execution 55 2380 User s MANUAL 2 Load 24 bit immediate value into HL register DDIR IB LW next instruction is in Long Word mode with an additional immediate data sload HLz and HL with constant 123456H LD HL 123456H This case the Z380 CPU appends 00H as a MSB byte HLz HL Before instruction execution 0987 6543 After instruction execution 0012 3456 4 2 3 Indirect R
8. RX IR X Operation tmp lt dst dst 0 C lt dst 15 dst n 1 lt tmp n forn 0 to 14 The contents of the destination operand are concatenated with the Carry flag and together they are rotated left one bit position The most significant bit of the destination operand is moved to the Carry flag and the Carry flag is moved to bit 0 of the destination Flags S Setifthe most significant bit of the result is set cleared otherwise Z Setifthe result is zero cleared otherwise H Cleared P Setif parity of the result is even cleared otherwise N Cleared C Setifthe bit rotated from the most significant bit was a 1 cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R RLW 11101101 11001011 000100rr 2 RX RLW RX 11101101 11001011 0001010y 2 IR RLW HL 11101101 11001011 00010010 2 X RLW XY d 11y11101 11001011 d 00010010 4 r Field Encodings rr 00 for BC 01 for DE 11 for HL y Ofor IX 1 for IY DC 8297 03 5 145 2100 RLA ROTATE LEFT ACCUMULATOR RLA Operation tmp lt 0 lt C C lt A 7 1 lt tmp n forn 0 to 6 2380 USER S MANUAL The contents of the accumulator are concatenated with the Carry flag and together they are rotated left one bit position Bit 7 of the accumulator is moved to the Carry flag and the Carry flag is moved to bit 0 of the accumulator Flags S Unaffected Z Unaffected H Cleared P Unaffected N Cleared
9. Set if the bit rotated from bit 7 was a 1 cleared otherwise Addressing Execute Mode Syntax Instruction Format Time RLA 00010111 2 5 146 Note DC 8297 03 71106 Operation Flags Addressing Mode R IR X 2380 USER S MANUAL RLC ROTATE LEFT CIRCULAR BYTE dst dst IR X tmp lt dst C lt dst 7 dst 0 lt 7 dst n 1 lt forn 0to6 The contents of the destination operand are rotated left one bit position Bit 7 of the destination operand is moved to the bit 0 position and also replaces the Carry flag S Set if the most significant bit of the result is set cleared otherwise Z Set if the result is zero cleared otherwise H Cleared P Set if parity of the result is even cleared otherwise N Cleared C Set if the bit rotated from bit 7 was a 1 cleared otherwise Execute Syntax Instruction Format Time Note RLC R 11001011 00000 r 2 RLC HL 11001011 00000110 2 r RLC XY d 11y11101 11001011 d 00000110 4 r Field Encodings r per convention DC 8297 03 y O for IX 1 for IY 5 147 2380 7106 User s MANUAL RLCW ROTATE LEFT CIRCULAR WORD RLCW dst dst R RX IR X Operation tmp lt dst C lt dst 15 dst 0 lt 15 dst n 1 lt tmp n forn 14 The contents of the destination operand are rotated left one bit position The most significant bit of the destination operand is moved to the bit 0 position and also replaces the
10. n 2 TST HL 11101101 00110100 2 r Field Encodings r per convention DC 8297 03 5 177 7106 TSTIO TEST PORT Operation Flags Addressing Mode 5 178 TSTIO src src IM C AND src A logical AND operation is performed between the corresponding bits of the source and the contents of the I O location The contents of both the I O location and the source are unaffected only the flags are modified as a result of this instruction No external I O transaction will be generated as a result of this instruction although the I O address will appear on the adress bus while the internal read is occurring The peripheral address in the C register is placed on the low byte of the address bus and zeros are placed on all other address lines S Set if the most significant bit of the result is set cleared otherwise Z Set if all bits of the result are zero cleared otherwise H Set P Set if the parity is even cleared otherwise N Cleared C Cleared Execute Syntax Instruction Format Time Note TSTIO n 11101101 01110100 n 3 1 2380 USER S MANUAL DC 8297 03 71106 2380 USER S MANUAL XOR EXCLUSIVE OR BYTE A src RX IM IR X Operation lt AXORsrc A logical EXCLUSIVE OR operation is performed between the corresponding bits of the source operand and the accumulator and the result is stored in the accumulator A 1 bit is stored wherever the corresponding bits i
11. 34 12 34 34 12 34 34 34 34 12 12 12 Source Code SBC HL DE LD 1234H DE NEGW HL NEGW reserved IM 1 LD A I IN E C OUT GLE ADC HL DE LD DE 1234H MLT DE IM 2 LD A R IN H C OUT SBC HL HL LD 1234H HL TST 12H EXTS A EXTS RRD IN L C OUT C L ADC LD HL 1234H MLT HL RLD OUT C 12H SBC HL SP LD 1234H SP TSTIO 12H EXTSW HL EXTSW SLP IN A C OUT C A ADC HL SP LD SP 1234H MLT SP ADD lt 1234 OTIM ADDW BC ADDW HL BC ADDW DE ADDW HL DE ADDW 1234H ADDW HL 1234H ADDW HL ADDW HL HL OTDM ADCW BC ADCW HL BC ADCW DE Mode X Object Code ED 8D ED 8E 34 12 ED 8E 34 12 ED 8F ED 8F ED 92 34 12 ED 93 ED 94 ED 94 ED 95 ED 95 ED 96 34 12 ED 96 34 12 ED 97 ED 97 ED 9B ED 9C ED 9C ED 9D ED 9D ED 9E 34 12 ED 9E 34 12 ED 9F ED 9F ED 0 ED A1 ED A2 ED A3 ED A4 ED A4 ED A5 ED A5 ED A6 34 12 ED A6 34 12 ED A7 ED A7 ED A8 ED A9 ED AA ED AB ED AC ED AC ED AD ED AD ED AE 34 12 ED AE 34 12 ED AF ED AF ED BO ED B1 ED B2 ED B3 ED B4 ED B4 Source Code ADCW HL DE ADCW 1234H ADCW HL 1234H ADCW HL ADCW HL HL SUB SP 1234H OTIMR SUBW BC SUBW HL BC SUBW DE SUBW HL DE SUBW 1234H SUBW HL 1234H SUBW HL SUBW HL HL OTDMR SBCW BC SBCW HL BC SBCW DE SBCW HL DE SBCW 1234H SBCW HL 1234H SBCW HL SBCW HL HL LDI OUTI ANDW BC ANDW HL BC ANDW DE ANDW HL DE ANDW 1
12. 71006 5 5 12 Decoder Directives The Decoder Directives Table 5 17 are a special instruc tions to expand the 280 instruction set to handle the 23805 4 Gbytes of linear memory addressing space For details on this instruction refer to Chapter 3 5 6 NOTATION AND BINARY ENCODING The rest of this chapter consists of a detailed description of the Z380 CPU instructions arranged in alphabetical order by mnemonic This section describes the notational conventions used in the instruction descriptions and the binary encoding for register fields within the instruction s operation codes opcodes The description of each instruction begins on new page The instruction mnemonic and name are printed in bold letters at the top of each page to enable the reader to easily locate desired description The assembly language syntax is then given in single generic form that covers all the variants ofthe instruction along with a list of applicable addressing modes This is followed by a description of the operation performed by the instruction in pseudo Pascal fashion a detailed description a listing of allthe flags that are affected by the instruction and illustrations of the opcodes for all variants of the instruction Symbols The following symbols are used to describe the instruction set n An 8 bit constant nn A 16 bit constant d An 8 bit offset two s complement src Source of the instruction dst Destination of the ins
13. DC 8297 03 7106 4 2 4 Direct Address DA When Direct Address mode is used the data processed is at the location whose memory or I O port address is in the instruction Instruction Memory or OPERATION I O Port ADDRESS gt OPERAND The operand value is the contents of the location whose address is in the instruction 2380 USER S MANUAL Depending on the instruction the operand specified by DA modeis either in the I O address space I O instruction or memory address space all other instructions This mode is also used by Jump and Call instructions to specify the address of the next instruction to be executed The address serves as an immediate value that is loaded into the program counter Also DDIR Immediate Data Directives are used to expand the direct address to 24 or 32 bits Operand width is affected by LW bit status for the load and exchange instructions Example of DA mode 1 Load BC register from memory location 00005E22H in Word mode LD 5E22H BC with the data in address 00005 22 BC Before instruction execution 1234 After instruction execution 0301 Memory location 00005E22 01 00005E23 03 2 Load BC register from memory location 12345E22H in Word mode DDIR IW extend direct address by one word LD BC 12345E22H Load BC with the data in address 12345E22H BC Before instruction execution 1234 After instruction execution 0301 Memory location 12345E22 01 12345E23 03
14. EXX or EXALL instructions changes the register files in use Upon reset the primary register file in register set 0 is active Changing register sets is asimple matter of an LDCTL instruction to program SR The accumulator is the destination register for 8 bit arith metic and logical operations The six general purpose registers can be paired BC DE and HL and are ex tended to 32 bits by the extension to the register with suffix z BCz DEz HLz to form three 32 bit general purpose registers The HL register serves as the 16 bit or 32 bit accumulator for word operations Access to the Extended portion of the registers is possible using the SWAP instruc tion or word Load instructions in Long Word operation mode The Flag register contains eight status flags Four can be individually used for control of program branching two are used to support decimal arithmetic and two are reserved These flags are set or reset by various CPU operations For details on Flag operations refer to Section 5 2 Flag Register 2 2 2 Index Registers The four index registers IX IX IY and IY are extended to 32 bits by the extension to the register with suffix 2 IXz IYz to form 32 bit index registers To access the Extended portion of the registers use the SWAP instruction or word Load instructions in Long Word operation mode These Index registers hold a 32 bit base address that is used in the Index addressing mode
15. IX 123456H IY 123456H HL IX 123456H HL IY 123456H 0 IY 123456H 1 123456 123456 1 123456 IY 123456H 1 123456 IY 123456H 1 123456 IY 123456H 1 123456 IY 123456H 1 123456 IY 123456H 1 123456 IY 123456H IX 123456H IY 123456H A IX 123456H A IY 123456H IX 123456H IY 123456H 1 1 2 2 3 3 4 4 5 5 6 6 7 7 DD FD DD CPW HL IX 123456H HL IY 123456H IX 123456H IY 123456H IX 123456H IY 123456H HL IX 123456H HL IY 123456H A 123456H HL 123456H 1 123456 IY 123456H 12345678H A IX 123456H 56H IX 123456 IX 123456H B 123456 IX4 123456H D IX4 123456H E 123456 IX 123456H L IY 123456H 78H IY 123456H A IY 123456H B IY 123456H C IY 123456H D IY 123456H DE IY 123456H H IY 123456H L A 12345678H A IX 123456H A IY 123456H B IX 123456H B IY 123456H C IX 123456H C IY 123456H D IX 123456H D IY 123456H E IX 123456H E IY 123456H H IX 123456H H IY 123456H L IX 123456H L IY 123456H MULTUW IX 123456H MULTUW IY 123456H MULTUW HL IX 123456H MULTUW IY 123456H MULTW MULTW MULTW MULTW OR OR 1 123456 123456 HL IX 123456H 123456 1 123456 IY 123456H FE 56 34 FE 56 34 35 56 34 35 56 34 56 34 CB56 34 CB56 34
16. Load from Control Register Addressing Execute Mode Syntax Instruction Format Time Note R LDCTL A Rs 11441101 11010000 2 Field Encodings qq 01 for XSR 10 for DSR 11 for YSR DC 8297 03 5 93 7106 LDCTL LOAD FROM CONTROL REGISTER WORD LDCTL dst src dst HL src SR Operation if LW then begin dst 31 0 lt src 31 0 end else begin dst 15 0 lt src 15 0 end The contents of the Select Register SR are loaded into the HL register Flags S Unaffected Z Unaffected H Unaffected V Unaffected Unaffected C Unaffected Load from Control Register Addressing Execute Mode Syntax Instruction Format Time R LDCTL HL SR 11101101 11000000 2 5 94 2380 USER S MANUAL Note DC 8297 03 2380 2106 USER S MANUAL LDCTL LOAD INTO CONTROL REGISTER WORD LDCTL dst src dst SR src HL Operation if LW then begin dst 31 16 HL 31 16 end else begin dst 31 24 HL 15 8 dst 23 16 HL 15 8 end dst 15 8 lt dst 0 lt The contents of the HL register loaded into the Select Register SR If Long Word mode is not in effect the upper byte of the HL register is copied into the three most significant bytes of the select register This instruction does not modify the mode bits in the SR There are dedicated instructions to modify the mode bits Flags S Unaffected 7 Unaffected H Unaffected V Unaffected Unaffected Unaffected Load from Control Register Addressing
17. Only one register of each can be active at any given time although data in the inactive file can still be accessed by using EX IX IX and EX IY IY either in 16 bit or 32 bit wide depending on the LW bit status Index registers can also function as general purpose registers with the upper and lower bytes of the lower 16 bits being accessed individu ally These byte registers are called IXU IXU IXL and IXL DC 8297 03 2380 UsER s MANUAL for the IX and IX registers and IYU IYU IYL and IYL for the IY and IY registers Selection of primary or auxiliary Index registers can be made by EXXX EXXY or EXALL instructions or program ming of SR Uponreset the primary registers in register set 0 is active Changing register sets is a simple matter of an LDCTL instruction to program SR 2 2 3 Interrupt Register The Interrupt register 1 is used in interrupt modes 2 and 3 for INTO to generate a 32 bit indirect address to an interrupt service routine The I register supplies the upper 24 or 16 bits of the indirect address and the interrupting peripheral supplies the lower eight or 16 bits In Assigned Vectors mode for INT3 INT1 the upper 16 bits of the vector are supplied by the register bits 15 9 are supplied from the Assigned Vector Base register and bits 8 0 are the assigned vector unique to each of INT3 INT1 2 2 4 Program Counter The Program Counter PC is used to sequence through instruction
18. a X 280380 CPU User s MANUAL lt lt PREFACE Thank you for your interest in the 2380 Central Processing Unit CPU and its associated family of products This Technical Manual describes programming and operation of the 2380 Superintegration Core CPU which is found in the 2380 Microprocessor Unit MPU and products built around 2380 CPU core This Z380 User s Manual consists of the following Sections 1 27380 Architectural Overview Chapter 1 is an introductory section covering the key features and giving an overview of the architecture of the device 2 Address Spaces Chapter 2 explains the address spaces the 2380 CPU can handle Also this chapter includes a brief description of the on chip regis ters 3 Native Extended Mode Word Long Word Mode of Operation and Decoder Directives This chapter provides a detailed explanation on the Z380 s unique features operation modes and the Decoder Directives 4 Addressing Modes and Data Types Chapter 4 describes the Addressing mode and data types which the Z380 can handle 5 Instruction Set Chapter 5 contains an overview of the instruction set as well as detailed instruction by instruction description in alphabetical order 6 Interrupts and Traps Chapter 6 explains the interrupts and traps features of the Z380 7 Reset Chapter 7 describes the Reset function 8 7380 Appnote 9 2380 Questions amp Answers DC 8297 03 Appe
19. v nne 12 12 12 12 12 Source Code Object Code RETN ED 45 RST OOH C7 RST 08H CF RST 10H D7 RST 18H DF RST 20H E7 RST 28H EF RST 30H F7 RST 38H FF Table D 2 Instructions operates different in Long Word Modes Source Code Object Code Source Code Object Code EX SP HL E3 LD BC DE DD 02 EX IX DD E3 LD BC HL FD 02 EX FD LD BC IX DD 0B EX BC BC ED CB 30 LD FD 0B EX BC DE ED 05 LD DE BC DD 1C EX BC HL ED 00 LD DE DE DD 1D EX BC IX ED 03 LD DE HL DD 1F EX BC IY ED LD DE BC ED 12 EX DE DE ED CB 31 LD DE DE DD 12 EX DE HL EB LD DE HL FD 12 EX DE IX ED 13 LD DE IX DD 1B EX DE IY ED 1B LD DE IY FD 1B EX HL HL ED 33 LD HL BC DD 3C EX HL IX ED 33 LD HL DE DD 3D EX ED 3B LD HL HL DD EX IX IX ED 34 LD HL BC ED 32 EX 2 LD HL DE DD 32 EX ED 35 LD HL HL FD 32 EXTS A ED 65 LD HL DD 57 EXTS ED 65 LD HL IX DD 3B LD FD OC LD HL IY FD 3B LD BC DE FD 1 LD LHL DD 47 LD BO HL FD 3C LD BC DD 03 LD BO IX DD 01 LD IX DE DD 13 LD BC lY FD 01 LD IX HL DD 33 LD DE BC FD 00 LD IX BC DD 07 LD DE DE FD 1D LD IX DE DD 17 LD DE HL FD 3D LD IX HL DD 37 LD DE IX DD 11 LD IX IY DD 27 LD DE IY FD 11 LD IY BC FD 03 LD HL BC FD OF LD IY DE FD 13 LD HL DE FD 1F LD IV HL FD 33 LD FD LD FD 07 LD HL IX DD 31 LD IY DE FD 17 LD HL IY FD 31 LD IY HL FD 37 LD
20. 0 lt 1 forn 0to 6 The contents of the accumulator rotated right bit position Bit 0 of the accumulator is moved to the bit 7 position and also replaces the Carry flag Flags S Unaffected Z Unaffected H Cleared P Unaffected N Cleared Set if the bit rotated from bit 0 was a 1 cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note RRCA 00001111 2 5 156 DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL RRD ROTATE RIGHT DIGIT RRD tmp 3 0 lt A 3 0 A 3 0 lt dst 3 0 dst 3 0 dst 7 4 dst 7 4 tmp 3 0 The low digit of the accumulator is logically concatenated to the destination byte whose memory address is inthe HL register The resulting three digit quantity is rotated to the right by one BCD digit four bits The upper digit of the source is moved to the lower digit of the source the lower digit of the source is moved to the lower digit of the accumulator and the lower digit of the accumulator is moved to the upper digit of the source The upper digit of the accumulator is unaffected In multiple digit BCD arithmetic this instruction can be used to shift to the right a string of BCD digits thus dividing it by a power of ten The accumulator serves to transfer digits between successive bytes of the string This is analogous to the use of the Carry flag in multiple precision shifting using the RR instructi
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22. 2 The contents of the memory location addressed by the Stack Pointer SP into the destination in ascending byte order from ascending address memory locations The SP is then incremented by two by four in the Long Word mode Note that when not in the Long Word mode the most significant byte read from memory is also written to the two most significant bytes of the SR Also note that the XM bit is unaffected by this instruction Flags S Unaffected 2 Unaffected H Unaffected V Unaffected Unaffected Unaffected Addressing Execute Mode Syntax Instruction Format Time Note POP SR 11101101 11000001 3 r L 5 132 DC 8297 03 7106 USER S MANUAL POP POP REGISTER POP dst dst RX Operation if LW then begin dst 7 0 lt SP dst 15 8 lt SP 1 dst 23 16 SP 2 dst 31 24 SP 3 SP lt SP 4 else begin dst 7 0 lt SP dst 15 8 lt SP 1 SP SP 2 end The contents of the memory location addressed by the Stack Pointer SP are loaded into the destination in ascending byte order from ascending address memory locations The SP is then incremented by two by four in the Long Word mode Flags 5 Unaffected Z Unaffected H Unaffected V Unaffected Unaffected Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R POPR 11rr 0001 1 1 L RX POP RX 11y11101 11100001 1 r L Field Encodings rr 00 for BC 01 for DE 10 for HL y Of
23. 5 A IXL SBC 1 12 SBOW HL IX SBCW IX AND AND IXU AND A IXL AND 1 12 1 12 ANDW ANDW IX XOR Object Code DD AC DD AD DD AD DD AE 12 DD AE 12 DD AF DD AF DD B4 DD B4 DD B5 DD B5 DD B6 12 DD B6 12 DD B7 DD B7 DD BC DD BC DD BD DD BD DD BE 12 DD BE 12 DD BF DD BF DD C0 DD C1 DD C2 DD C3 DD C4 34 12 DD C6 12 DD C6 12 DD C8 DD CA 01 DD CB 12 01 DD CB 12 02 DD CB 12 03 DD CB 12 06 DD CB 12 09 DD CB 12 0A DD CB 12 0B DD CB 12 OE DD CB 12 11 DD CB 12 12 DD CB 12 13 DD CB 12 16 DD CB 12 19 DD CB 12 1A DD CB 12 1B DD CB 12 1E DD CB 12 21 DD CB 12 22 DD CB 12 23 DD CB 12 26 DD CB 12 29 DD CB 12 2A Source Code XOR XOR SRAW IXU A IXL IXL IX 12H A IX 12H HL IX IX A IXU IXU A IXL IXL IX 12H A IX 12H HL IX IX A IXU IXU A IXL IXL IX 12H A IX 12H HL IX IX W IB W IW W IB NZ 1234H IX 12H HL IX 12H SRA SR 01H BC SP 12H IX 12H BC IX 12H IX 12H SP 12H BC IX 12H IX 12H BC IX 12H DE SP 12H IX 12H DE IX 12H IX 12H IX SP 12H IX 12H IY IX 12H IX 12H SP 12H IX IX 12H Mode Object Code DD 12 2B DD 12 2 DD 12 31 DD 12 33 DD 12 39 DD 12 DD 12 DD 12 DD 12 46 DD 12 4E DD 12 56 DD 12 DD
24. 7106 5 5 2 16 Bit and 32 Bit Load Exchange SWAP and PUSH POP Group Continued 2380 USER S MANUAL Table 5 6 Supported Source and Destination Combination for 16 Bit and 32 Bit Load Instructions Source Destination BC DE SP L L L L IL DE L L L L L IL HL L L L L L IL IX L L L L IL IY L L L L IL SP L L L IL BC L L L L L ILW DE L L L L L ILW HL L L L L L ILW nn IL IL IL LIL IL IX d IL IL IL IL IY d IL IL IL IL SP d IL IL IL Note The column with the character s the allowed source destination combinations The combination with L means that the instruction is affected by Long Word nn BC DE HL IX d IY d SP d IL L L L IL IL IL IL L L L IL IL IL IL L L L IL IL IL IL L L L IL IL IL L L L IL IL IL mode I means that the instruction is can be used with DDIR Immediate instruction Also W means the instruc tion uses the mnemonic of LDW instead of LD Table 5 7 Supported Operand for PUSH POP Instructions AF BC DE HL IX PUSH NV V SR nn 4 Note These PUSH POP instructions are affected by Long Word mode of operations 5 5 3 Block Transfer and Search Group This group of instructions Table 5 8 supports block transfer and string search functions Using these instruc tions a block of up to 65536 bytes of byte Word or Long Word data can be moved in memory or a byte
25. LD C D 1B DEC DE X 4B LD 1B DECW DE X 4C LD C H 1C INC 4D LD CL 10 DEC 4 LD C HL 1E 12 LD E 12H 4F LD C A 1F RRA 50 LD 20 12 JR NZ 12H x 51 LD D C 21 34 12 LD HL 1234H L 52 LD D D 22 34 12 LD 1234H HL L 53 LD D E 23 INC HL X 54 LD D H 23 INCW HL x 55 LD Dil 24 INC H 56 LD D HL 25 DEC H 57 LD D A 26 12 LD H 12H 58 LD E B 27 DAA 59 LD E C 28 12 JR Z 12H X 5A LD ED 29 ADD HLHL X 5B LD EE 2A 34 12 LD HL 1234H L 5C LD EH 2B DEC HL X 5D LD EL 2B DECW HL X 5E LD E HL 2C INC L 5F LD EA 2D DEC L 60 LD HB 2E 12 LD L 12H 61 LD 2F CPL 62 LD H D Source Code H E H H H L H HL LB L D Object Code Source Code SBC SBC SBC SBC SBC SBC SBC AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR AE A H A HL B A D D AE E A H H L HL A HL A B A D D AE E A H H L HL A HL A B A C A D A E A H A L HL A HL Mode ween onm nne Object Code Source Code Mode Object Code Source Code Mode B7 OR A A CB 1A RR D B8 CP CB 1B RR B8 CP B CB 1C RR H B9 CP AC CB 1D RR L B9 CP CB 1E RR HL BA CP AD CB 1F RR A BA CP D CB 20 SLA BB CP AE CB 21 SA C BB CP CB 22 SA D BC CP CB 23 SA E BC CP H CB 24 SLA H BD CP OAL
26. PC 31 0 PC 31 0 dst 31 0 end else begin PC 15 0 15 0 dst 15 0 end end A conditional Jump transfers program control to the destination address if the setting of a selected flag satisfies the condition code specified in the instruction an unconditional Jump always transfers control to the destination address Either the Zero or Carry flag can be tested for the conditional Jump If the jump is taken the Program Counter PC is loaded with the destination address otherwise the instruction following the Jump Relative instruc tion is executed The destination address is calculated using relative addressing The displacement in the instruction is added to the PC value for the instruction following the JR instruction not the value of the PC for the JR instruction These instructions employ either an 8 bit 16 bit or 24 bit signed two s complement displacement from the PC to permit jumps within range of 126 to 129 bytes 32 765 to 32 770 bytes or 8 388 604 to 8 388 611 bytes from the location of this instruction Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Execute Instruction Format Time 001cc000 disp 2 00011000 disp 11011101 001cc000 d low 11011101 00011000 d low lo I Syntax JR CC addr JR addr JR CC addr JR addr JR CC addr JR addr high high mid d high mid d high 11111101 001 000 d low 11111101 00011000 d low
27. USER S MANUAL The IB decoder directive causes the decoder to fetch an additional byte immediately after the existing immediate data or direct address and in front of any trailing opcode bytes with instructions starting with DD CB or FD CB for example Likewise the IW decoder directive causes the decoder to fetch an additional word immediately after the existing immediate data or direct address and in front of any trailing opcode bytes Byte ordering within the instruction follows the usual con vention least significant byte first followed by more signifi cant bytes More significant immediate data or direct address bytes not specified in the instruction are read as all zeros by the processor The Wdecoder directive causes the instruction decoder to tag the instruction for execution in Word mode This is useful while the Long Word LW bit in the Select Register SR is set but 16 bit data manipulation is required for this instruction The LW decoder directive causes the instruction decoder to tag the instruction for execution in Long Word mode This is useful while the LW bit in the SR is cleared but 32 bit data manipulation is required for this instruction Note that regardless of Native or Extended mode a 32 bit address is always used for the data access Thus for data reference the complete 4 Gbytes of memory area may be accessed For example LD HL uses the 32 bit address value stored in HL31 HLO HLz
28. Z Setifthe specified bit is zero cleared otherwise H Set V Unaffected Cleared C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R BIT b R 11001011 01bbb r 2 IR BIT b HL 11001011 01bbb110 2 r X BIT b XY d 11y11101 11001011 d 01bbb110 4 r Field Encodings r per convention y Ofor IX 1 for IY DC 8297 03 5 29 2380 7106 USER S MANUAL BTEST BANK TEST BTEST Operation S lt SR 16 Z lt SR 24 V lt SR 0 lt SR 8 The Alternate Register bits the Select Register SR are transferred to the flags This allows the program to determine the state of the machine Flags S Set if the alternate bank IX is in use cleared otherwise 2 Set if the alternate bank IY is in use cleared otherwise H Unaffected V Set if the alternate bank AF is in use cleared otherwise N Unaffected C if the alternate bank of BC DE and HL is in use cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note BTEST 11101101 11001111 2 5 30 DC 8297 03 71106 CALL cc dst dst DA Operation if cc is TRUE then begin if XM then begin SP SP 4 SP lt 7 0 SP 1 15 8 SP 2 PC 23 16 SP 3 lt 31 24 31 0 lt dst 31 0 else begin SP SP 2 SP lt 7 0 SP 1 lt 15 8 15 0 lt dst 15 0 end end conditional Call transfers program control to the destination address if the setting
29. 101 for 28h 110 for 30h 111 for 38h 5 158 DC 8297 03 2380 71 06 USER S MANUAL SBC SUBTRACT WITH CARRY BYTE SBC A src src R RX IM IR X Operation lt A sre C The source operand together with the Carry flag is subtracted from the accumulator and the difference is stored in the accumulator The contents of the source are unaffected Two s complement subtraction is performed Flags S Set if the result is negative cleared otherwise Z Setif the result is zero cleared otherwise Setif there is a borrow from bit 4 of the result cleared otherwise V Set if arithmetic overflow occurs that is if the operands are of different signs and the result is of the same sign as the source cleared otherwise Set Set if there is a borrow from the most significant bit of the result cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R SBC A R 10011 r 2 RX SBC A RX 11y11101 1001110w 2 IM SBC A n 11011110 n 2 IR SBC A HL 10011110 2 r X SBC A XY d 11y11101 10011110 d 4 r Field Encodings r per convention y O for IX 1 for IY w Oforhigh byte 1 for low byte DC 8297 03 5 159 7106 2380 USER S MANUAL SBC SUBTRACT WITH CARRY WORD SBC HL src dst HL src BC DE HL SP Operation HL 15 0 lt HL 15 0 src 15 0 C The source operand together with the Carry flag is subtracted from the HL register and the difference is stored in the HL regis
30. 12 86 ORW FD B7 RES O IY 12H FD CB 12 86 ORW IX DD B7 RES CB 87 ORW IY FD B7 RES 0 8 CB 80 OTDM ED 8B RES OC 81 OTDMR ED 9B RES 0 D CB 82 OTDR ED BB RES CB 83 OTDRW ED FB RES CB 84 OTIM ED 83 RES OL CB 85 OTIMR ED 93 RES 1 HL CB 8E OTIR ED B3 RES 1 12 DD 12 8E OTIRW ED F3 RES 1 IY 12H FD CB 12 8E OUT 12 D3 12 RES 1 CB 8F OUT ED 71 12 RES 1B CB 88 OUT ED 79 RES 1 C CB 89 OUT C B ED 41 RES 1 0 CB 8A OUT ED 49 RES 1 CB 8B OUT ED 51 RES 1H CB 8C OUT ED 59 RES 11 CB 8D OUT ED 61 RES 2 HL CB 96 OUT ED 69 RES 2 IX 12H DD CB 12 96 OUTO 12 ED 39 12 RES 2 IY 12H FD CB 12 96 OUTO 12 ED 01 12 RES 2 CB 97 OUTO 12 ED 09 12 RES 2B CB 90 OUTO 12H D ED 11 12 RES 2 CB 91 OUTO 12 ED 19 12 RES 2 CB 92 OUTO 12H H ED 21 12 RES 2E CB 93 OUTO 12H L ED 29 12 RES 2 H CB 94 OUTA 1234 ED D3 34 12 RES 21 CB 95 OUTAW 1234H HL FD 03 34 12 RES 3 HL CB 9E OUTD ED AB RES 3 IX 12H DD CB 12 9E OUTDW ED EB RES 3 IY 12H FD CB 12 9E OUTI ED A3 RES CB 9F OUTIW ED RES 3 B CB 98 OUTW C 1234H FD 79 34 12 RES 3 C CB 99 OUTW C BC DD 41 RES 3 0 CB 9A OUTW C DE DD 51 RES CB 9B OUTW C HL DD 79 RES 3 H CB 9C POP L F1 RES 3 CB 9D POP BC L C1 RES 4 HL CB A6 POP L D1 RES 4 12 DD 12 POP HL L E1 RES 4 IY 1
31. 34 12 33 JP V 123456H EA 56 34 12 LD HL IY 1234H FD 34 12 33 JP Z 123456H CA 56 34 12 LD HL SP 1234H DD CB 34 12 31 SUB HL 123456H ED D6 56 34 12 LD IX 123456H DD 2A 56 34 12 SUB 5 123456 ED 92 56 34 12 LD IX IY 1234H FD 34 12 23 LD IX SP 1234H DD 34 12 21 LD IY 123456H FD 2A 56 34 12 LD 1 1234 DD CB 34 12 23 LD IY SP 1234H FD 34 12 21 LD SP 123456H ED 7B 56 34 12 LDW BC 123456H ED 06 56 34 12 LDW DE 123456H ED 16 56 34 12 LDW HL 123456H ED 36 56 34 12 Table E 3 Valid with DDIR IB in Long Word mode XM bit status does not affect the operation Either with DDIR IB LW or DDIR IB with LW bit set BC 123456H DE 123456H HL 123456H IX 123456H IY 123456H SP 123456H 123456H 56 56 56 21 21 56 F5 12 12 12 Table E 4 Valid with DDIR IB XM bit nor LW bit status do not affect the operation ADG ADG ADCW ADCW ADCW ADCW ADD ADD ADDW ADDW ADDW ADDW AND AND AND AND ANDW ANDW ANDW A IX 1234H A IY 1234H IX 1234H IY 1234H HL IX 1234H HL IY 1234H A IX 1234H A IY 1234H IX 1234H IY 1234H HL IX 1234H HL IY 1234H IX 1234H IY 1234H A IX 1234H A IY 1234H IX 1234H IY 1234H HL IX 1234H HL IY 1234H 0 IX 1234H 0 1Y 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H I
32. 4 w LL X 6 11y11101 11001011 d 00rr1011 5 w LL T IY d IX 11111101 11001011 d 00101011 5 w LL LD 1 4 11011101 11001011 d 00101011 5 w LL SR LD SP d R 11011101 11001011 d 00rr1001 5 w LL LD SP d XY 11y11101 11001011 d 00101001 5 w LL Field Encodings rs 01 for DE 10 for BC 11 for HL rd 00 for 01 for DE 11 for HL y Ofor IX 1 for IY rr 00 for BC 01 for DE 11 for HL ri 00 for BC 01 for DE 11 for HL ra 00 for BC 01 for DE 10 for HL 5 88 DC 8297 03 71106 LD dst src dst SP src R RX IM DA or dst DA src SP Operation if LW then begin dst 31 0 lt src 31 0 end else begin dst 15 0 lt src 15 0 end The contents of the source are loaded into the destination Flags S Unaffected 2 Unaffected Unaffected V Unaffected Unaffected Unaffected Load into Stack Pointer Addressing Mode Syntax Instruction Format R LD SP HL 11111001 RX LD SP RX 11y11101 11111001 IM LD SP nn 00110001 n low n high DA LD SP nn 11101101 01111011 n low n high Field Encodings y 0 for IX 1 for IY Load from Stack Pointer Addressing Mode Syntax Instruction Format DA LD nn SP 11101101 01110011 n low n high DC 8297 03 2380 USER S MANUAL LD LOAD STACK POINTER Execute Time 2 2 2 3 r Execute Time 4 w Note LL 5 89 2380 7106 USER S MANUAL LD LOAD FROM I OR R REGISTER BYTE LD d
33. AF Main Bank IX IY Native Mode Maskable Interrupts Disabled in Mode 0 Bus Request Lock Off A and F Registers Register Banks 3 0 F A Unaffected Register Extensions 0000 Register Bank 0 BCz DEz HLz lYz BCz DEZ HLz IYZ All non extended portions unaffected Register Bank 3 1 Unaffected I O Bus Control Register 0 00 IOCLK BUSCLK 8 Interrupt Enable Register 01 INTO Enabled Assigned Vector Base Register 00 Trap and Break Register 00 ILUU O 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc The information in this document is subject to change without notice Devices sold by Zilog Inc are covered by warranty and patent indemnification provisions appearing in Zilog Inc Terms and Conditions of Sale only ZILOG INC MAKES NO WARRANTY EXPRESS STATUTORY IMPLIED OR BY DESCRIPTION REGARDING THE INFORMA TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT ZILOG INC MAKES NO WARRANTY OF MER CHANTABILITY OR FITNESS FOR ANY PURPOSE Zilog Inc shall notbe responsible for any errors that may appear in this document Zilog Inc makes no commitment to update or keep current the information contained in this document Zilog s products are not authorized for use as critical co
34. Addressing Mode DC 8297 03 2380 USER S MANUAL CPDR COMPARE DECREMENT AND REPEAT BYTE CPDR Repeat until BC 0 OR match begin A HL if XM then begin HL 31 0 lt HL 31 0 1 else begin HL 15 0 lt HL 15 0 1 end BC 15 0 BC 15 0 1 end This instruction is used for searching strings of byte data The bytes of data starting at the location addressed by the HL register are compared with the contents of the accumulator until either an exact match is found or the string length is exhausted becuase the BC register has decremented to zero The Sign and Zero flags are set to reflect the result of the comparison The contents of the accumulator and the memory bytes are unaffected Two s complement subtraction is performed After each comparison the HL register is decremented by one thus moving the pointer to the previous element in the string The BC register used as a counter is then decremented by one Ifthe result of decrementing the BC register is not zero and no match has been found the process is repeated If the contents of the BC register are zero at the start of this instruction a string length of 65 536 is indicated This instruction can be interrupted after each execution of the basic operation The PC value at the start of this instruction is pushed onto the stack so that the instruction can be resumed S Set if the last result is negative cleared otherwise Z Setif the last resu
35. DDIR IW OUTA W kimn dst k n Block Output BC31 B24 BC23 B16 BC15 B8 7 0 2 6 ON CHIP I O ADDRESS SPACE The Z380 CPU has the on chip I O address space to control on chip peripheral functions of the Superintegra tion version of the devices A portion of its interrupt functions are also controlled by several on chip registers which occupy an on chip I O address space This on chip address space canbe accessed only with the following reserved on chip instructions which are identical to the 2180 original instructions to access Page 0 ad dressing area R n OTIM INO OUTO n R OTDM TSTIO n OTDMR When one of these instructions is executed the 2380 MPU outputs the register address being accessed in a pseudo transaction of two BUSCLK cycles duration with the address signals A31 A8 at zero In the pseudo trans actions all bus control signals are at their inactive state The following four registers are assigned to this address ing space as a part of the 7380 CPU core 2 6 Register Name Internal I O Address Interrupt Enable Register 17H Assigned Vector Base Register 18H Trap and Break Register 19H Chip Version ID Register OFFH The Chip Version ID register returns one byte data which indicates the version of the CPU or the specific implemen tation of the Z380 CPU based Superintegration device Currently the value 00H is assigned to the Z380 MPU and other valu
36. INC C 0C JR NC 1234H X DD 30 34 12 INC D 14 JR NC 12H X 30 12 INC DE x 13 JR NZ 123456H X FD 20 56 34 12 INC E 1C JR NZ 1234H X DD 20 34 12 INC H 24 JR NZ12H X 20 12 INC HL X 23 JR NZ12H X 20 12 INC IX x DD 23 JR 2 23456 X FD 28 56 34 12 INC DD 2C JR Z 1234H X DD 28 34 12 INC IXU DD 24 JR Z 12H x 28 12 INC IY X FD 23 LD 1234H A 32 34 12 INC IYL FD 2C LD 1234H BC 1 L ED 43 34 12 INC FD 24 LD 1234H DE L ED 53 34 12 INC L 2C LD 1234H HL L 22 34 12 INC SP X 33 LD 1234H HL L ED 63 34 12 INCW BC X 03 LD 1234H IX L DD 22 34 12 INCW DE X 13 LD 1234H lY L FD 22 34 12 INCW HL X 23 LD 1234H SP L ED 73 34 12 INCW IX x DD 23 LD 02 INCW IY x FD 23 LD BC BC L FD 0 INCW SP X 33 LD BC DE L FD 1C IND ED AA LD BC HL L FD 3C INDR ED BA LD L DD 01 INDRW ED FA LD BC IY L FD 01 INDW ED EA LD DE A 12 INI ED A2 LD DB BC L FD OD INIR ED B2 LD DE DE L FD 1D INIRW ED F2 LD DE HL L FD 3D INIW ED E2 LD DB X L 0011 INW BC C DD 40 LD DE IY L FD 11 INW 50 LD HL 12H 36 12 INW HL C DD 78 LD HL A 77 JP HL X E9 LD HL B 70 JP IX X DD E9 LD HL BC L FD OF JP X FD E9 LD 71 JP 1234H X C3 34 12 LD HL D 72 JP C 1234H X DA 34 12 LD HL DE L FD 1F JP Mj234H X FA 34 12 LD 73 JP NC 1234H X D2 34 12 LD 74 JP 21234 X C2 34 12 LD L FD 3F JP NS4234H X F2 34 12 LD DD 31 JP NV 1234H X E2 34 12 LD H
37. Inc are covered by warranty and patent indemnification provisions appearing in Zilog Inc Terms and Conditions of Sale only ZILOG ING MAKES NO WARRANTY EXPRESS STATUTORY IMPLIED OR BY DESCRIPTION REGARDING THE INFORMA TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT ZILOG INC MAKES NO WARRANTY OF MER CHANTABILITY OR FITNESS FOR ANY PURPOSE Zilog Inc shall not be responsible for any errors that may appear in this document Zilog Inc makes no commitment to update or keep current the information contained in this document Zilog s products are not authorized for use as critical compo nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use Life support devices or systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 Telex 910 338 7621 FAX 408 370 8056 Internet http www zilog com v The following Appendix has the Z380 instructions sorted by numeric order The column Mode indicates whether the instruction is affecte
38. SP 10000 HLz HL SPz SP Before instruction execution 1234 5678 07FF 7 00 After instruction execution EFCD AB89 07FF 7 00 Memory location 08007F00 89 08007 01 08007 02 CD 08007F03 EF Address calculation In Extended mode 010000H encod 07FF7F00 ing in the instruction is sign extended to 32 bit value 00010000 before the address calculation and calculation is done in 08007F00 modulo 232 4 8 DC 8297 03 7106 4 3 DATA TYPES The 7380 CPU can operate on bits binary coded decimal BCD digits four bits bytes eight bits words 16 bits or 32 bits byte strings and word strings Bits in registers can be set cleared and tested The basic data type is byte which is also the basic accessible elementin the register memory and I O address space The 8 bit load arithmetic logical shift and rotate instructions operate on bytes in registers or memory Bytes can be treated as logical signed numeric or unsigned numeric value Words operated on in similar manner by the word load arithmetic logical and shift and rotate instructions Operation on 2 byte words is also supported Sixteen bit load and arithmetic instructions operate on words in registers or memory words can be treated as signed or unsigned numeric values reads and writes can be 8 bit or 16 bit operations Also the Z380 CPU architecture supports operation in Long Word mode to handle 32 bit address manipulation For that pu
39. and HL as source location address However on Reset the HL31 HL16 portion HLz initializes to OOH Unless HLz is modified to other than OOH operation of this instruction is identical to the one with the Z80 CPU Modifying the extended portion of the register is done either by using a 32 bit load instruction in Long Word mode or with DDIR LW instructions or using a 16 bit load instruction with SWAP instructions DC 8297 03 71106 2380 USER S MANUAL The 7380 CPU implements one instruction to switch to Extended mode from Native mode SETC XM set Ex tended mode places the Z380 CPU in Extended mode Once in Extended mode only Reset can return it to Native mode On Reset the 2380 is in Native mode Refer to Sections 4 and 5 for more examples 3 4 WORD AND LONG WORD MODE OF OPERATION The Z380 CPU can operate in either Word or Long Word mode In Word mode the Reset configuration all word operations manipulate 16 bit quantities and are compat ible with the 780 CPU 16 bit operations In the Long Word mode all word operations can manipulate 32 bit quanti ties Note that the Native Extended and Word Long Word selections are independent of one another as Word Long Word pertains to data and operand address manipulation only The Z380 CPU implements two instructions and two decoder directives to allow switching between these two modes SETC LW Set Long Word and RESC LW Reset Long Word perform a global switch whil
40. as shown inthe encoding below Instructions which do not support decoder directives are assembled by the instruction decoder as if the decoder directive were not present The IB decoder directive causes the decoder to fetch an additional byte immediately after the existing immediate data or direct address and in front of any trailing opcode bytes with instructions starting with DD CB or FD CB for example Likewise the IW decoder directive causes the decoder to fetch an additional word immediately after the existing immediate data or direct address and in front of any trailing opcode bytes Byte ordering within the instruction follows the usual convention least significant byte first followed by more significant bytes More significant immediate data or direct address bytes not specified in the instruction are taken as all zeros by the processor The W decoder directive causes the instruction decoder to tag the instruction for execution in Word mode This is useful while the Long Word LW bit in the Select Register SR is set but 16 bit data manipulation is required for this instruction The LW decoder directive causes the instruction decoder to tag the instruction for execution in Long Word mode This is useful while the LW bit in the SR is cleared but 32 bit data manipulation is required for this instruction Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Addressing Execute Mode Syntax Instruc
41. being acknowledged If INTO is being acknowledged A3 A1 are at logic 1 and AO is at logic O For the maskable Interrupt on INTO input Interrupt Modes 0 through 3 are supported Modes 0 1 and 2 have the same schemes as those in the Z80 and Z180 MPU s Mode 3 is similar to mode 2 except that 16 bit Interrupt vectors are expected from the devices Note that 8 bit and 16 bit I O devices can be intermixed in this mode by having external pull up resistors at the data bus signals D15 D8 for example The external maskable Interrupt requests INT3 INT1 are always handled in an assigned Interrupt vectors mode regardless of the current Interrupt Mode IM3 IMO in effect As discussed in the CPU Architecture section the Z380 MPU can operate in either the Native or Extended mode In Native mode pushing and popping of the stack to save and retrieve interrupted PC values in Interrupt handling are done in 16 bit sizes and the Stack Pointer rolls over at the 64 Kbyte boundary In Extended mode the PC pushes and pops are done in 32 bit sizes and the Stack Pointer rolls over at the 4 Gbyte memory space boundary The Z380 2380 USER S MANUAL MPU provides an Interrupt Register Extension whose contents are always output as the address bus signals A31 A16 when fetching the starting addresses of service routines from memory in Interrupt Modes 2 3 and the assigned vectors mode In Native mode such fetches are automatically done in 16
42. d H JR eee FD 18 d L d M d H Table A 3 Format 3 Instruction Encoding Opcode 1 Byte Displacement Opcode RLC HL CB 06 RLC IX d DD CB d 06 Note A esc is an addressing mode escape byte and either ODDH or OFDH ED ED CB CB Table A 4 Format 4 Instruction Encoding Opcode Opcode Immediate RRCW BC ED CB 08 MULTW nn ED CB 97 n L n H 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc The information in this document is subject to change without notice Devices sold by Zilog Inc are covered by warranty and patent indemnification provisions appearing in Zilog Inc Terms and Conditions of Sale only ZILOG ING MAKES NO WARRANTY EXPRESS STATUTORY IMPLIED OR BY DESCRIPTION REGARDING THE INFORMA TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT ZILOG INC MAKES NO WARRANTY OF MER CHANTABILITY OR FITNESS FOR ANY PURPOSE Zilog Inc shall not be responsible for any errors that may appear in this document Zilog Inc makes no commitment to update or keep current the information contained in this document Zilog s products are not authorized for use as critical compo nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the
43. the instruction being executed as well as the Word Long Word mode A bit can be addressed by specifying a byte and a bit within that byte Bits are numbered from right to left with the least significant bit being 0 as illustrated in Figure 2 2 The address of a multiple byte entity is the same as the address of the byte with the lowest memory address in the entity Multiple byte entities can be stored beginning with 2 4 2380 USER S MANUAL SP holds 00010000H in Native mode and 00020000H in Extended mode In either case 5 2 can be programmed to set Stack frame This is done by the Load to Stack pointer instructions in Long Word mode upper three bytes can be loaded with the same byte value The SR may also be PUSHed POPed and is cleared to zeros on Reset For details on this register refer to Chapter 5 3 Select Register either even or odd memory addresses A word either 2 byte or 4 byte entity is aligned if its address is even otherwise it is unaligned Multiple bus transactions which may be required to access multiple byte entities can be minimized if alignment is maintained The format of multiple byte data types is also shown in Figure 2 2 Note that when word is stored in memory the least significant byte precedes the more significant byte of the word as in the Z80 CPU architecture Also the lower addressed byte is present on the upper byte of the external data bus DC 8297 03 71106
44. 03 4 5 7106 4 2 6 Program Counter Relative Mode RA Continued PCz PC Before instruction execution 0000 1000 After instruction execution 0000 Address calculation In Native mode 2 is encoded as OFEH in the instruction and it is sign extended to a 16 bit value before added to the Program Counter Calculation is done in modulo 27 and does not affect the Extended portion of the Program Counter 2 Jump relative in Extended mode 16 bit displacement SETC XM Put it in Extended mode of operation JR 5000H Jumps to the location PC value 5000H stands for current PC value This instruction jumps to itself 2 Before instruction execution 1959 0807 After instruction execution 1958 B80B Address calculation Since this is 4 byte instruction the PC value after fetch but before jump taking place is 19590807 00000004 1959080B The displacement portion 5000 is sign extended to 32 bit value before being added to the Program Counter Calculation is done in modulo 232 and affects the Extended portion of the Program Counter 1959080B FFFFB000 19588808 4 6 2380 User s MANUAL 1000 FFE FFFE DC 8297 03 2106 4 2 7 Stack Pointer Relative Mode SR For Stack Pointer Relative addressing mode the data processed is at the location whose address is the contents of the Stack Pointer offset by an 8 bit displacement in the instruction The Stack
45. 07FF 7 00 Memory location 07FF7EFC 89 07FF7EFD AB Address calculation In Native mode FCH 4 in Decimal 7F00 encoding in the instruction is sign extended to 16 bit value before the address calculation Calculation is done modulo 2 and does not take into account the Stack Pointer s extended portion DC 8297 03 4 7 7106 4 2 7 Stack Pointer Relative Mode SR Continued 2380 User s MANUAL 2 Load HL from location SP 4 in Extended mode Long Word mode SETC XM Extended mode DDIR LW LD HL SP 4 into the HL from the operate next instruction in Long Word mode contents of the memory location whose address is four less than the contents of SP HLz HL SPz SP Before instruction execution 1234 5678 07FF 7 00 After instruction execution EFCD AB89 07 7F00 Memory location 07FF7EFC 89 07FF7EFD AB 07FF7EFE CD O07FF7EFF EF Address calculation In Extended mode 4 in Deci 07FF7F00 mal encoding in the instruction is sign extended to 32 FFFFFFFC bit value before the address calculation and calculation is 07FF7EFC done in modulo 232 3 Load HL from location SP 10000H in Extended mode Long Word mode XM Extended mode DDIR IW LW operate next instruction in Long Word mode with a word immediate data Load into the HL from the contents of the memory location whose address is 10000H more than the contents of SP LD HL
46. 1 C HL HL HL 1 end This instruction is used for block output of strings of data The string of output data is loaded into the selected peripheral from memory at consecutive addresses starting with the location addressed by the HL register and increasing During the I O transaction the 32 bit BC register is placed on the address bus Note that the B register contains the loop count for this instruction so that A 15 8 are not useable as part of a fixed port address The decremented B register is used in the address First the B register used as a counter is decremented by one The byte of data from the memory location addressed by the HL register is loaded into the selected peripheral The HL register is then incremented by one thus moving the pointer to the next source for the output If the result of decrementing the B register is 0 the instruction is terminated otherwise the sequence is repeated If the B register contains 0 at the start of the execution of this instruction 256 bytes are output This instruction can be interrupted after each execution ofthe basic operation The Program Counter value atthe start of this instruction is saved before the interrupt request is accepted so that the instruction can be properly resumed S Unaffected Z Setifthe result of decrementing B is zero cleared otherwise H Unaffected V Unaffected N Set C Unaffected Execute Syntax Instruction Format Time Note OTIR 11101101 10110011
47. 1 for IY 5 24 DC 8297 03 2380 7106 USER S MANUAL ADD ADD TO STACK POINTER WORD ADD src IM Operation if XM then begin SP 31 0 lt SP 31 0 src 31 0 end else begin SP 15 0 lt SP 15 0 src 15 0 end The source operand is added to the SP register and the sum is stored in the SP register This has the effect of allocating or allocating space on the stack Two s complement addition is performed Unaffected Unaffected Set if there is a carry from bit 11 of the result cleared otherwise Unaffected Cleared Set if there is a carry from the most significant bit of the result cleared otherwise Flags Addressing Execute Mode Syntax Instruction Format Time Note IM ADD SP nn 11101101 10000010 n low n high 2 LX DC 8297 03 5 25 7106 ADDW ADD WORD 2380 USER S MANUAL ADDW HL src src X HL 15 0 lt HL 15 0 src 15 0 The source operand is added to the HL register and the sum is stored in the HL register The contents of the source are unaffected Two s complement addition is performed Flags S Set if the result is negative cleared otherwise Z Setif the result is zero cleared otherwise Setif there is a carry from bit 11 of the result cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise N Cleared Set if there is
48. 11011101 11111011 n 2 DC 8297 03 5 49 7106 2380 USER S MANUAL EXCHANGE ACCUMULATOR FLAG WITH ALTERNATE BANK Operation Flags Addressing Mode 5 50 EX AF AF SR 0 lt NOT SR 0 Bit 0 of the Select Register SR which controls the selection of primary or alternate bank for the accumulator and flag register is complemented thus effectively exchanging the accumulator and flag registers between the two banks S Value in F Z Value in F H Value in F V Value in F Value in F Value in F Execute Syntax Instruction Format Time Note EX 00001000 3 DC 8297 03 7106 Operation Flags Addressing Mode R Field Encodings 0 for IX 1 for DC 8297 03 2380 USER S MANUAL EX EXCHANGE ADDRESSING REGISTER WITH TOP OF STACK EX SP dst if LW then begin SP 3 e dst 31 24 SP 2 lt gt dst 23 16 end SP 1 SP dst HL IX lt gt dst 15 8 gt dst 7 0 The contents of the destination register are exchanged with the top of the stack In Long Word mode this exchange is two words otherwise it is one word S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected Unaffected Syntax EX SP HL EX SP XY Execute Instruction Format Time Note 11100011 3 r w L 11y11101 11100011 3 r W L 5 51 7106 EXCHANGE REGISTER WORD EX dst src dst RX src RX Operation if LW
49. 11101101 010pp110 4 Field Encodings pp 00 for Mode 0 01 for Mode 3 10 for Mode 1 11 for Mode 2 DC 8297 03 5 63 2380 2106 USER S MANUAL IN INPUT BYTE IN dst C dst R Operation dst C The byte of data from the selected peripheral is loaded into the destination register During the I O transaction the contents of the 32 bit BC register are placed on the address bus Flags S Set if the input data is negative cleared otherwise Z Set if the input data is zero cleared otherwise Cleared P Set if the input data has even parity cleared otherwise N Cleared Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R IN R C 11101101 01 r 000 2 i Field Encodings r per convention 5 64 DC 8297 03 71106 Operation Flags Addressing Mode R 2380 USER S MANUAL INW INPUT WORD INW dst C dst R dst 15 0 lt The word of data from the selected peripheral is loaded into the destination register During the I O transaction the contents of the 32 bit BC register are placed on the address bus S Set if the input data is negative cleared otherwise Z Setifthe input data is zero cleared otherwise Cleared P Set if the input data has even parity cleared otherwise N Cleared C Unaffected Execute Syntax Instruction Format Time Note INW R C 11011101 O1rrr000 2 i Field Encodings rrr 000 for 010 for DE 111 for HL DC 8297 03 5 65 2380 71
50. 11101101 101011rr 2 RX XORW HL RX 11y11101 10101111 2 IM XORW HL nn 11101101 10101110 n low n high 2 X XORW HL XY d 11y11101 11101110 d 4 r Field Encodings rr 00 for BC 01 for DE 11 for HL y for IX 1 for IY 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc The information in this document is subject to change without notice Devices sold by Zilog Inc are covered by warranty and patent indemnification provisions appearing in Zilog Inc Terms and Conditions of Sale only ZILOG INC MAKES NO WARRANTY EXPRESS STATUTORY IMPLIED OR BY DESCRIPTION REGARDING THE INFORMA TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT ZILOG ING MAKES NO WARRANTY OF MER CHANTABILITY OR FITNESS FOR ANY PURPOSE Zilog Inc shall not be responsible for any errors that may appear in this document Zilog Inc makes no commitment to update or keep current the information contained in this document Zilog s products are not authorized for use as critical compo nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use Life support devices or systems are those which are intended for surgical implantation into
51. 12 66 DD 12 6E DD 12 76 DD 12 7E DD 12 86 DD 12 8 DD 12 92 DD 12 92 DD CB 12 96 DD CB 12 9A DD 12 9A DD 12 9 DD 12 DD 12 DD 12 B6 DD CB 12 BA DD CB 12 BA DD CB 12 BE DD CB 12 C6 DD CB 12 CE DD CB 12 D6 DD CB 12 DE DD CB 12 E6 DD CB 12 EE DD CB 12 F6 DD CB 12 FE DD CC 34 12 DD CD 34 12 DD CE 12 DD CE 12 DD CF DD DO DD D4 34 12 DD D6 12 DD D6 12 DD D8 DD D9 DD DA 01 DD DC 34 12 DD DE 12 DD DE 12 DD Et Source Code DIVUW DIVUW RES SET SET SET SET SET SET SET SET CALR CALR ADCW ADCW MTEST LDCTL CALR SUBW SUBW LDCTL LDCTL CALR SBCW SBCW POP IX 12H lY IX 12H HL SP 12H HL IX 12H SP 12H HL IX 12H IX 12H HL HL IX 12H 2 IX 12H IX 12H HL IX 12H 3 IX 12H 4 IX 12H 5 IX 12H 6 IX 12H IX 12H HL IX 12H 7 1234 1234 IX 12H HL IX 12H A XSR NC 1234H IX 12H HL IX 12H XSR A XSR 01H C 1234H IX 12H HL IX 12H IX wna v nne Object Code DD E3 DD E4 34 DD E5 DD E6 12 DD E6 12 DD E9 DD EC 34 DD EE 12 DD EE 12 DD F3 1F DD F4 34 DD F6 12 DD F6 12 DD F7 DD F9 DD FB 1F DD FC 34 DD FE 12 DD FE 12 DD FF DE 12 E2 34 12 E2 34 12 E4 34 12 E4 34 12 E6 12 E6 12 12 Source Code EX CALR PUSH ANDW ANDW JP CALR XORW XORW DI CALR ORW SP IX PO 1234H IX IX 12H HL IX 12H IX PE 1234H IX 12H HL IX
52. 126 to 129 bytes 32 765 to 32 770 bytes or 8 388 604 to 8 388 611 bytes from the location of this instruction Flags 6 Unaffected 7 Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Addressing Mode Syntax Instruction Format RA DJNZ addr 00010000 disp DJNZ addr 11011101 00010000 d low d high DJNZ addr 11111101 00010000 d low d mid d high Note 3 if branch not taken 4 if branch taken 5 48 Execute Time Note note X note X note X DC 8297 03 2380 71 06 USER S MANUAL El ENABLE INTERRUPTS El n Operation if n is present then begin for i 1 to 4 begin if n i 1 then begin IER i 1 lt 1 if n O 1 then begin SR 5 1 else begin SR 5 1 end If an argument is present enable the selected interrupts by setting the appropriate enable bits in the Interrupt Enable Register and then set the Interrupt Enable Flag IEF1 in the Select Register SR if the least significant bit of the argument is set enabling maskable interrupts Bits 7 5 of the argument are ignored If no argument is present IEF1 in the SRis set to 1 enabling maskable interrupts Note that during the execution of this instruction and the following instruction maskable interrupts are not sampled Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Flags Addressing Execute Mode Syntax Instruction Format Time Note 11111011 2 El n
53. 2380 USER S MANUAL NEGW NEGATE HL REGISTER WORD NEGW HL HL 15 0 lt HL 15 0 The contents of the HL register are negated that is replaced by its two s complement value Note that 8000h is replaced by itself because in two s complement representation the negative number with the greatest magnitude has no positive counterpart for this case the Overflow flag is set to 1 S Set if the result is negative cleared otherwise Z Setif the result is zero cleared otherwise Setif there is a borrow from bit 4 of the result cleared otherwise V Setif the content of the HL register was 8000h before the operation cleared otherwise Set Setifthe content of the HL register was not 0000h before the operation cleared if the content of the HL register was 0000h Execute Syntax Instruction Format Time Note NEGW HL 11101101 01010100 2 5 109 7106 OPERATION Operation None No operation Flags S Unaffected 2 Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Addressing Mode Syntax Instruction Format NOP 00000000 5 110 Execute Time 2 Note 2380 USER S MANUAL DC 8297 03 2380 71 06 USER S MANUAL OR OR BYTE OR A src src RX IM IR X Operation lt AOR src Alogical OR operation is performed between the corresponding bits of the source operand and the accumulator and the result is stored in the accumulator A 1 bit is stored wherever
54. 7 IX 1234H 7 IV 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H A IX 1234H A IY 1234H IX 1234H IY 1234H 0 IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H SET SET SET SET SET SET SLA SLA SLAW SLAW SRA SRA SRAW SRAW SRL SRL SRLW SRLW SUB SUB SUBW SUBW XOR XOR XOR XOR XORW XORW XORW XORW 5 IX 1234H 5 IY 1234H 6 IX 1234H 6 IY 1234H 7 IX 1234H 7 IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H IX 1234H IY 1234H A IX 1234H A IY 1234H HL IX 1234H HL IY 1234H IX 1234H IY 1234H A IX 1234H A IY 1234H IX 1234H IY 1234H HL IX 1234H HL IY 1234H meu Table E 5 Valid with DDIR IW in Exteded mode LW bit status does not affect the operation ween vom nvvne Table E 6 Valid with DDIR IW XM bit status does not affect the operation Transfer size determined by LW bit ADD HL 12345678H ED C6 78 56 34 12 ADD SP 12345678H ED 82 78 56 34 12 LD 12345678H BC ED 43 78 56 34 12 CALL 12345678H CD 78 56 34 12 LD 12345678H DE ED 53 78 56 34 12 CALL C 12345678H 78 56 34 12 LD 12345678H HL 22 78 56 34 12 CALL 12345678 FC 78 56 34 12 LD 1234567
55. Bit 0 of the destination operand is moved to the Carry flag and the Carry flag is moved to bit 7 of the destination 6 Setifthe most significant bit of the result is set cleared otherwise Z Set if the result is zero cleared otherwise H Cleared P Setif parity of the result is even cleared otherwise Cleared Set if the bit rotated from bit 0 was a 1 cleared otherwise Execute Syntax Instruction Format Time Note RR R 11001011 00011 r 2 RR HL 11001011 00011110 2 r RR XY d 11y11101 11001011 d 00011110 4 r Field Encodings r per convention DC 8297 03 y O for IX 1 for IY 5 151 7106 RRW 2380 USER S MANUAL ROTATE RIGHT WORD Operation Flags Addressing Mode R RX IR RRW dst dst RX IR tmp lt dst C lt dst 0 dst 15 C dst n lt tmp n 1 for n 0 14 The contents of the destination operand are concatenated with the Carry flag and together they are rotated right one bit position Bit 0 of the destination operand is moved to the Carry flag and the Carry flag is moved to the most significant bit of the destination S Setifthe most significant bit of the result is set cleared otherwise Z Set if the result is zero cleared otherwise H Cleared P Setif parity of the result is even cleared otherwise Cleared Set if the bit rotated from bit 0 was a 1 cleared otherwise Execute Syntax Instruction Format Time Note RRW 11101101
56. CB 09 RRCW DE ED CB 99 MULTUW DE ED CB 0A RRCW HL ED CB 99 MULTUW HL DE ED CB 0B RRCW HL ED CB 9B MULTUW HL ED CB OC RRCW IX ED CB 9B MULTUW HL HL ED CB 0D RRCW IY ED CB 9C MULTUW HL IX ED CB 10 RLW BC ED 9C MULTUW IX ED CB 11 RLW DE ED CB 9D MULTUW HL IY ED 12 RLW HL ED CB 9D MULTUW IY ED CB 13 RLW HL ED CB 9F MULTUW 1234H ED CB 14 RW IX ED CB 9F MULTUW HL 1234H ED 15 RLW IY ED CB B8 DIVUW BC ED CB 18 RRW BC ED CB B8 DIVUW HL BC ED CB 19 RRW DE ED CB B9 DIVUW DE ED CB 1A RRW HL ED CB B9 DIVUW HL DE ED CB 1B RRW HL ED CB BB DIVUW HL ED CB 1C RRW IX ED CB BB DIVUW HL HL ED CB 1D RRW IY ED CB 20 SLAW BC ED CB 21 SLAW DE ED CB 22 SLAW HL ED CB 23 SLAW HL ED CB 24 SLAW IX ED CB 25 SLAW IY vom nne Object Code Source Code Mode Object Code Source Code Mode ED CB BC DIVUW HL IX FA 34 12 JP 5 1234 X ED CB BC DIVUW IX FB El ED CB BD DIVUW FC 34 12 CALL S M 1234H X ED CB BD DIVUW IY FD 01 LD BO IY L ED CB BF DIVUW 1234H FD 02 LD BG HL L BF DIVUW HL 1234H FD 03 LD IY BC L ED CC 12 CALR Z 12H X FD 07 LD IY BC L ED CD 12 CALR 12H X FD 09 ADD X ED CF BTEST FD LD BG IY L ED DO LDCTL A DSR FD OG LD L ED D3 34 12 OUTA 1234H A FD OD LD DE BC L ED D4 12 CALR NC 12H X FD OF LD HL BC L ED D6 34 12 SUB HL 1234H X FD 10 56 34 12 DJNZ 123456H X ED D8 LDCTL DSRA FD 11 LD DBLIY L ED D9 EXALL FD 12 LD DE HL L ED DA 01 LDCTL DSR 01H FD 13 LD I
57. CB 25 SA L BD CP L CB 26 SLA HL BE CP HL CB 27 SLA A BE CP A HL CB 28 SRA BF CP CB 29 SRA BF CP CB 2A SRA D CO RET NZ X CB 2B SRA C1 POP BC L CB 2C SRA H C2 34 12 JP NZ1234H X 2D SRA L C3 34 12 JP 1234H X CB 2E SRA HL C4 34 12 CALL 21234 X CB 2F SRA 5 L 30 EX B B C6 12 ADD A 12H 31 EX er C7 RST OOH X CB 32 EX D D C8 RET Z X CB 33 EX EE C9 RET x CB 34 EX H H CA 34 12 JP 2 1234 X CB 35 EX 00 RC B CB 37 EX CB 01 RC C CB 38 SRL CB 02 RC D CB 39 SRL C CB 03 RC E CB 3A SRL CB 04 RLC H CB 3B SRL E CB 05 RC L CB 3C SRL H CB 06 RLC HL CB 3D SRL L CB 07 RLC A CB 3E SRL HL CB 08 RRC B CB 3F SRL A CB 09 C CB 40 BIT 08 CB OA RRC D CB 41 BIT OG CB 0B 42 BIT CB 0C RRC H CB 43 BIT OE CB 0D RRC L CB 44 BIT CB OE RRC HL CB 45 BIT OL OF CB 46 BIT D HL 10 RL B CB 47 BIT CB 11 RL C CB 48 BIT 1B CB 12 RL D CB 49 BIT 1 13 RL E CB 4A BIT 1D CB 14 RL H CB 4B BIT E CB 15 RL L CB 4C BIT 1H CB 16 RL HL CB 4D BIT AL CB 17 RL A CB 4E BIT 1 1 CB 18 RR CB 4F BIT 1 CB 19 RR C CB 50 BIT 28 9c Object Code Source Code Mode Object Code Source Code Mode CB 51 BIT 2 C CB 87 RES 0 A CB 52 BIT 2 CB 88 RES 1B CB 53 BIT 2E CB 89 RES 1 CB 54 BIT 2H CB 8A RES 1 D CB 55 BIT 21 CB 8B RES 1E CB 56 BIT 2 HL CB 8C RES CB 57 BIT 2A CB 8D RES 11 CB 58 BIT 38 8E R
58. CB56 34 DB56 34 DB56 34 56 34 12 56 34 12 78 56 34 36 56 34 77 56 34 70 56 34 71 56 34 72 56 34 73 56 34 74 56 34 75 56 34 36 56 34 77 56 34 70 56 34 71 56 34 72 56 34 56 34 74 56 34 75 56 34 78 56 34 7E 56 34 7E 56 34 46 56 34 46 56 34 4E 56 34 4E 56 34 56 56 34 56 56 34 5E 56 34 5E 56 34 66 56 34 66 56 34 6E 56 34 6E 56 34 56 34 CB56 34 CB56 34 CB56 34 CB56 34 CB56 34 CB56 34 CB56 34 B6 56 34 B6 56 34 56 78 SBCW SBCW SET SET SET SET SET SET SET SET SET A IX 123456H 123456 1 123456 IY 123456H HL IX 123456H 123456 12345678 12345678H HL 0 IX 123456H 0 IY 123456H 1 IX 123456H 1 IY 123456H 2 IX 123456H 2 IY 123456H 3 IX 123456H 3 IY 123456H 4 IX 123456H 4 IY 123456H 5 IX 123456H 5 IY 123456H 6 IX 123456H 6 IY 123456H 7 1 123456 7 IY 123456H IX 123456H IY 123456H IX 123456H IY 123456H IX 123456H IY 123456H IX 123456H IY 123456H IX 123456H IY 123456H IX 123456H IY 123456H IX 123456H IY 123456H IX 123456H IY 123456H 123456 A IY 123456H IX 123456H IY 123456H 0 IX 123456H IY 123456H IX 123456H IY 123456H IX 123456H Q 1 1 2 2 IY 123456H 3 123456 3 IY 123456H 4 IX 123456H p DD B6 56 34 B6 56 34 F6 56 34 F6 56 34 F6 56 34 F6 56 34 D3 78 56 D3 78 56 CB 56 34 CB 56 34 C
59. Campbell CA 95008 6600 Telephone 408 370 8000 Telex 910 338 7621 FAX 408 370 8056 Internet http www zilog com DC 8297 03 4 9 N lt 5 1 INTRODUCTION Z380 CPU instruction set is a superset of the 280 CPU and the 7180 MPU the 2380 CPU is opcode compatible with the 780 CPU Z180 MPU Thus Z80 Z180 program can be executed 7380 CPU without modification The instruction set is divided into 12 groups by function 8 Bit Load Exchange Group 16 32 Bit Load Exchange SWAP and Push Pop Group m Block Transfers and Search Group 8 Bit Arithmetic and Logic Operations 16 32 Bit Arithmetic Operations 8 Bit Bit Manipulation Rotate and Shift Group B 16 Bit Rotates and Shifts 5 2 PROCESSOR FLAGS The Flag register contains six bits of status information that are set or cleared by CPU operations Figure 5 1 Four of these bits are testable C P V Z and S for use with conditional jump call or return instructions Two flags are not testable H and N and are used for binary coded decimal BCD arithmetic BRR RES 7 6 5 4 3 2 1 0 Figure 5 1 Flag Register DC 8297 03 USERS MANUAL CHAPTER 5 INSTRUCTION SET m Program Control Group B Input and Output Operations for External I O Space B Input and Output Operations for Internal I O Space B CPU Control Group W Decoder Directives This chapter describes the instruction set ofthe Z380 CPU Flags and condition c
60. Carry flag Flags S Set if the most significant bit of the result is set cleared otherwise Z Setif the result is zero cleared otherwise H Cleared P Setif parity of the result is even cleared otherwise N Cleared Setifthe bit rotated from the most significant bit was a 1 cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R RLCW R 11101101 11001011 000000rr 2 RX RLCW RX 11101101 11001011 0000010y 2 IR RLCW HL 11101101 11001011 00000010 2 r X RLCW XY d 11y11101 11001011 d 00000010 4 r Field Encodings rr 00for 01 for DE 11 for HL y Ofor IX 1 for IY 5 148 DC 8297 03 2380 7106 USER S MANUAL RLCA ROTATE LEFT CIRCULAR ACCUMULATOR RLCA Operation tmp lt C lt 7 A 0 lt tmp 7 1 lt tmp n for n 0 to 6 The contents of the accumulator are rotated left one bit position Bit 7 of the accumulator is moved to the bit O position and also replaces the Carry flag Flags S Unaffected Z Unaffected H Cleared P Unaffected N Cleared Set if the bit rotated from bit 7 was a 1 cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note RLCA 00000111 2 DC 8297 03 5 149 2380 7106 USER S MANUAL RLD ROTATE LEFT DIGIT RLD Operation tmp 3 0 lt A 3 0 A 3 0 lt dst 7 4 dst 7 4 lt dst 3 0 dst 3 0 lt 3 0 The low digit of the accumulator is logically concatenated to the destination byte whose me
61. DDIR in Extended mode LW LD 123456H SP ED 73 56 34 12 bit status does not affect the operation LD 1 1234 DD CB 34 12 0B LD IX 1234H DE DD CB 34 12 1B ADD HL 123456H ED C6 56 34 12 LD IX 1234H HL DD CB 34 12 ADD 5 123456 ED 82 56 34 12 LD 1 1234 DD 34 12 2B CALL 123456H CD 56 34 12 LD IY 1234H BC FD 34 12 OB CALL 123456 56 34 12 LD IY 1234H E FD 73 34 12 CALL M 123456H 56 34 12 LD IY 1234H HL FD CB 34 12 CALL 123456 D4 56 34 12 LD 1234 FD CB 34 12 2B CALL NZ 123456H C4 56 34 12 LD SP 1234H BC DD 34 12 09 CALL P 123456H F4 56 34 12 LD SP 1234H DE DD CB 34 12 19 CALL PE 123456H EC 56 34 12 LD SP 1234H HL DD CB 34 12 39 CALL 123456 E4 56 34 12 LD SP 1234H IX DD 34 12 29 CALL 2 123456 CC 56 34 12 LD SP 1234H IY FD 34 12 29 JP 123456H C3 56 34 12 LD BC 123456H ED 4B 56 34 12 JP C 123456H DA 56 34 12 LD BC IX 1234H DD CB 34 12 03 JP M 123456H FA 56 34 12 LD BC IY 1234H FD 34 12 03 JP NC 123456H D2 56 34 12 LD BC SP 1234H DD CB 34 12 01 JP NS 123456H F2 56 34 12 LD DE 123456H ED 5B 56 34 12 JP NV 123456H E2 56 34 12 LD DE IX 1234H DD CB 34 12 13 JP NZ 123456H C2 56 34 12 LD DE IY 1234H FD CB 34 12 13 JP 123456 F2 56 34 12 LD DE SP 1234H DD 34 12 11 JP PE 123456H EA 56 34 12 LD HL 123456H 2A 56 34 12 JP PO 123456H E2 56 34 12 LD HL 123456H ED 6B 56 34 12 JP 5 123456H FA 56 34 12 LD HL IX 1234H DD
62. E A H A IXL A IXU A IYL A IYU AL gt x gt x gt x X x x gt wna von Object Code 39 DD 09 DD 19 DD 29 DD 39 FD 09 FD 19 FD 29 FD 39 ED 82 34 DD C6 12 FD C6 12 ED 86 34 ED 84 ED 85 ED 87 DD C6 12 FD C6 12 ED 86 34 ED 84 ED 85 ED 87 DD 87 FD 87 DD 87 FD 87 A6 DD 12 FD A6 12 E6 12 A7 A6 DD A6 12 FD A6 12 E6 12 A7 0 1 2 4 DD 5 DD 4 FD 5 FD 4 5 0 1 2 4 DD 5 DD 4 FD 5 12 meu Source Code AND AND ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT IYU L IX 12H IY 12H 1234H HL IX 12H HL IY 12H HL 1234H HL BC HL DE HL HL HL IX HL IY 0 IX 12H 0 IY 12H 0 A 0 B 0 C 3 HL 3 IX 12H 3 IY 12H 3 A 3 B 3 C Mode Object Code FD 4 A5 DD E6 12 FD E6 12 ED 6 34 ED 4 ED 5 ED A7 DD E6 12 FD E6 12 ED 6 34 ED 4 ED 5 ED A7 DD A7 FD A7 DD A7 FD A7 CB 46 DD CB 12 FD CB 12 CB 47 CB 40 CB 41 CB 42 CB 43 CB 44 CB 45 CB 4E DD CB 12 FD CB 12 CB CB 48 CB 49 CB 4A CB 4B CB 4C CB 4D CB 56 DD CB 12 FD CB 12 CB 57 CB 50 CB 51 CB 52 CB 53 CB 54 CB 55 CB 5E DD CB 12 FD CB 12 CB 5 CB 58
63. Exchange SWAP and PUSH POP Group This group of load exchange and PUSH POP instructions Table 5 4 allows one or two words of data two bytes equal one word to be transferred between registers and memory The exchange instructions Table 5 5 allow for switching between the primary and alternate register files exchang ing the contents of two register files exchanging the contents of an addressing register with the top word on the stack For possible combinations of the word exchange instructions refer to Table 5 5 The 16 bit and 32 bitloads includetransferbetween registers and memory and imme diate loads of registers or memory The Push and Pop stack instructions are also included in this group None of these instructions affect the CPU flags except for EX AF Table 5 6 has the supported source destination combina tion for the 16 bit and 32 bit load instructions The transfer size 16 bit or 32 bit is determined by the status of LW bit in SR or by DDIR Decoder Directives 2380 USER S MANUAL PUSH POP instructions are used to save restore the con tents of register onto the stack It can be used to exchange data between procedures save the current register file on context switching or manipulate data on the stack such as return addresses Supported sources are listed in Table 5 7 Swap instructions allows swapping of the contents of the Word wide register BC DE HL IX or IY with its Extended portion T
64. Execute Mode Syntax Instruction Format Time Note R LDCTL SR HL 11101101 11001000 4 L DC 8297 03 5 95 2380 7106 USER S MANUAL LDD LOAD AND DECREMENT BYTE LDD Operation DE lt HL DE lt 1 HL HL 1 BC 15 0 lt 15 0 1 This instruction is used for block transfers of strings of data The byte of data at the location addressed by the HL register is loaded into the location addressed by the DE register Both the DE and HL registers are then decremented by one thus moving the pointers to the preceeding elements in the string The BC register used as a counter is then decremented by one Unaffected Unaffected Cleared Set if the result of decrementing BC is not equal to zero cleared otherwise Cleared Unaffected Flags Addressing Execute Mode Syntax Instruction Format Time Note LDD 11101101 10101000 3 r W 5 96 DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL LDDW LOAD AND DECREMENT WORD LDDW if LW then begin DE lt HL DE 1 lt HL 1 DE 2 lt HL 2 DE 3 HL 3 DE lt DE 4 HL lt HL 4 BC 15 0 lt BC 15 0 4 else begin DE lt HL DE 1 lt HL 1 DE lt DE 2 HL lt HL 2 BC 15 0 lt BC 15 0 2 end This instruction is used for block transfers of words of data The word of data at the location addressed by the HL register is loaded into the location addressed by the DE register Both the
65. HL register is then incremented by one thus moving the pointer to the next destination for the input S Unaffected Z Set if the result of decrementing is zero cleared otherwise H Unaffected V Unaffected Set Unaffected Execute Syntax Instruction Format Time Note INI 11101101 10100010 2 i W DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL INIW INPUT AND INCREMENT WORD INIW HL DB 15 0 lt 15 0 1 HL HL 2 This instruction is used for block input of strings of data During the I O transaction the 32 bit DE register is placed on the address bus First the word of data from the selected peripheral is loaded into the memory location addressed by the HL register Then the BC register used as a counter is decremented by one The HL register is then incremented by two thus moving the pointer to the next destination for the input S Unaffected Z Set if the result of decrementing BC is zero cleared otherwise H Unaffected V Unaffected N Set C Unaffected Execute Syntax Instruction Format Time Note INIW 11101101 11100010 2 i W 5 77 7106 INPUT INCREMENT AND REPEAT BYTE Operation Flags Addressing Mode 5 78 INIR repeat until B 0 begin HL lt B lt B 1 HL HL 1 end This instruction is used for block input of strings of data The string of input data from the selected periphera
66. Interrupt requests If IEF1 is at logic 0 all such Interrupts are disabled The purpose of IEF2 is to correctly manage the occurrence of NMI When NMI is acknowledged the state of IEF1 is copied to IEF2 and then IEF1 is cleared to logic 0 At the 2380 USER S MANUAL end of the NMI interrupt service routine execution of the Return From Nonmaskable Interrupt instruction RETN automatically copies the state of IEF2 back to IEF1 This is a means to restore the Interrupt enable condition existing before the occurrence of NMI Table 6 3 summarizes the states of IEF1 and IEF2 resulting from various operations Table 6 3 Operation Effects on IEF1 and IEF2 Inhibits all interrupts except Trap and NMI Disables interrupt nesting IEF1 value copied to IEF2 then IEF1 is cleared Returns from NMI service routine Disables interrupt nesting Returns from Interrupt service routine 780 I O device Returns from service routine or returns from Interrupt service routine for a non Z80 I O device Operation IEF1 IEF2 Comments RESET 0 0 0 0 0 IEF1 RETN IEF2 NC INT3 INTO 0 0 El 1 1 DI 0 0 LD or LD LD or LD HLR NC Change IEF2 value is copied to P V 6 2 2 2 I I Extend The 8 bit Interrupt Register and the 16 bit Interrupt Regis ter Extension are cleared during reset 6 2 2 3 Interrupt Enable Register D7 D4 Reserved
67. Mode Syntax Instruction Format Time Note EXTSW HL 11101101 01110101 3 5 58 DC 8297 03 2380 71 06 USER S MANUAL EXX EXCHANGE REGISTERS WITH ALTERNATE BANK EXX Operation SR 8 lt NOT SR 8 Bit 8 of the Select Register SR which controls the selection of primary or alternate bank for the DE and HL registers is complemented thus effectively exchanging the DE and HL registers between the two banks Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Flags Addressing Execute Mode Syntax Instruction Format Time Note EXX 11011001 3 DC 8297 03 5 59 7106 EXCHANGE REGISTER WITH ALTERNATE BANK EXXX Operation SR 16 NOT SR 16 Bit 16 of the Select Register SR which controls the selection of primary or alternate bank for the IX register is complemented thus effectively exchanging the IX register between the two banks Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected Unaffected Addressing Mode Syntax EXXX 5 60 Instruction Format 11011101 11011001 2380 USER S MANUAL DC 8297 03 2380 71 06 USER S MANUAL EXXY EXCHANGE IY REGISTER WITH ALTERNATE BANK EXXY Operation SR 24 lt SR 24 Bit 24 of the Select Register SR which controls the selection of primary or alternate bank for the IY register is complemented thus effectively exchanging the IY register between the two banks Flags S Unaff
68. PE 123456H IY 12H HL IY 12H P 123456H 1234H IY 12H HL IY 12H XM SP IY M 123456H IY 12H HL IY 12H 12H A 12H 38H ween v nne 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc The information in this document is subject to change without notice Devices sold by Zilog Inc are covered by warranty and patent indemnification provisions appearing in Zilog Inc Terms and Conditions of Sale only ZILOG ING MAKES NO WARRANTY EXPRESS STATUTORY IMPLIED OR BY DESCRIPTION REGARDING THE INFORMA TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT ZILOG INC MAKES NO WARRANTY OF MER CHANTABILITY OR FITNESS FOR ANY PURPOSE Zilog Inc shall not be responsible for any errors that may appear in this document Zilog Inc makes no commitment to update or keep current the information contained in this document Zilog s products are not authorized for use as critical compo nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use Life support devices or systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in a
69. Pointer Relative address is computed by adding the 8 bit two s complement signed displacement speci fied in the instruction to the contents of the SP also specified by the instruction Stack Pointer Relative ad dressing mode is used to specify data items to be found in the stack such as parameters passed to procedures Offset portion can be expanded to 16 or 24 bits by using DDIR immediate instructions DDIR IB for a 16 bit offset DDIR IW for a 24 bit offset SP ADDRESS Instruction OPERATION DISPLACEMENT 7380 USER S MANUAL Note that computation of the effective address is affected by the operation mode Native or Extended In Native mode address computation is done in modulo 21 mean ing computation is done in 16 bit and does not affect upper half of the SP portion for calculation wrap around within the 16 bit In Extended mode address computation is done in modulo 2 Also the size of the data transfer is affected by the LW mode bit In Word mode transfer is done in 16 bits and in Long Word mode transfer is done in 32 bits MEMORY OPERAND Example of SR mode 1 LD HL SP4 Load into the HL from the Load HL from location SP 4 in Native mode Word mode contents of the memory location whose address is four less than the contents of SP Assume it is in Native Word mode HLz HL SPz SP Before instruction execution 1234 5678 07 7 00 After instruction execution EFCD AB89
70. Read as 0 should write to as 0 03 00 IE3 IE0 Interrupt Request Enable Flags These flags individually indicate if INT3 INT2 INT1 or INTO is enabled Note that these flags are conditioned with the Enable and Disable Interrupt instructions with argu ments See Figure 6 1 IER 00000017H Read Only 7 0 EEE Ts 0 0 0 0 0 0 0 1 Reset Value Encoded Interrupt Requests Interrupt Requests Enable Figure 6 1 Interrupt Enable Register DC 8297 03 6 2 2 4 Assigned Vectors Base Register 07 01 AB15 AB9 Assigned Vectors Base The Interrupt Register Extension Iz together with AB15 AB9 define the base address of the assigned Interrupt vectors table in memory space See Figure 6 2 DO Reserved Read as 0 should write to as 0 AVBR 00000018H R W 7 0 AB15 AB14 AB13 AB12 JAB11 10 ago Reset Value 0 0 0 0 0 0 0 0 Reserved Program as 0 Read as 0 Assigned Vectors Base Figure 6 2 Assigned Vectors Base Register 6 3 7106 6 2 2 5 Trap Break Register D7 D2 Reserved Some of these bits are reserved for development support functions Read as 0 should write to as 0 D1 TF Trap on Instruction Fetch TF goes active to logic 1 when an undefined opcode fetched in the instruction stream is detected TF can be reset under program control by writing it with a logic 0 However it cannot be written with a logic 1 DO TV Trap on Interrupt Vector TV goes active to logic 1 when a
71. SUBW HL XY d 11 11101 11010110 d 2 Field Encodings rr 00 for BC 01 for DE 11 for HL y for IX 1 for IY DC 8297 03 5 175 7106 SWAP 2380 USER S MANUAL SWAP UPPER REGISTER WORD WITH LOWER REGISTER WORD SWAP src Operation src 31 16 lt gt src 15 0 src R RX The contents of the most significant word of the source are exchanged with the contents of the least significant word of the source Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Addressing Mode Syntax R SWAP R RX SWAP RX Field Encodings 5 176 00 for BC 01 for DE 11 for HL y for IX 1 for IY Instruction Format 11101101 OOrr1110 11y11101 00111110 Note DC 8297 03 71106 Operation Flags Addressing Mode R IM IR 2380 USER S MANUAL TST TEST BYTE TST src src IR A AND src Alogical AND operation is performed between the corresponding bits ofthe source operand and the accumulator The contents of both the accumulator and the source are unaffected only the flags are modified as a result of this instruction S Set if the most significant bit of the result is set cleared otherwise Z Setif all bits of the result are zero cleared otherwise H Set Set if the parity is even cleared otherwise Cleared C Cleared Execute Syntax Instruction Format Time Note TST 11101101 00 r 100 2 TST 11101101 01100100
72. Setifthe result is zero cleared otherwise H Cleared P Setif parity of the result is even cleared otherwise N Cleared Set if the bit shifted from the most significant bit was 1 cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R SLAW R 11101101 11001011 001000rr 2 RX SLAW RX 11101101 11001011 0010010y 2 IR SLAW HL 11101101 11001011 00100010 2 r X SLAW XY d 11y11101 11001011 d 00100010 4 r Field Encodings rr 00for BC 01 for DE 11 for HL y Ofor IX 1 for IY 5 166 DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 SLP if STBY not enabled then CPU Halts else Z380 enters Standby mode With Standby mode disabled this instruction is interpreted and executed as a HALT instruction With Standby mode enabled executing this instruction causes all device operation to stop thus minimizing power dissipation The STNBY signal is asserted to indicate this Standby mode status STNBY remains asserted until an interrupt or reset request is accepted which causes the device to exit Standby mode If the option is enabled an external bus request also causes the devcie to exit the Standby mode S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Execute Syntax Instruction Format Time Note SLP 11101101 01110110 2 2380 UsER s MANUAL SLP SLEEP 5 167 2380 7106 USER S MANUAL SRA SHIFT RIGHT ARI
73. Zero flag is cleared to 0 For block search instructions the Zero flag is set to 1 if a comparison is found between the value in the Accumulator and the memory location pointed to by the contents of the register pair HL When testing a bitin a register or memory location the Zero flag contains the complemented state of the tested bit i e the Zero flag is set to 1 if the tested bit is a 0 and vice versa For block I O instructions if the result of decrements is zero the Zero flag is set to 1 otherwise it is cleared to 0 Also for byte inputs to registers from I O devices ad dressed by the C register the Zero flag is set to 1 to indicate a zero byte input 5 2 6 Sign Flag S The Sign flag S stores the state of the most significant bit of the result When the Z380 CPU performs arithmetic operation on signed numbers binary two s complement notation is used to represent and process numeric infor mation A positive number is identified by a 0 in the most significant bit A negative number is identified by a 1 in the most significant bit When inputting a byte from an device addressed by the C register to a CPU register the Sign flag indicates either positive S 0 or negative S 1 data 5 2 DC 8297 03 2380 7106 USER S MANUAL 5 2 7 Condition Codes Table 5 1 lists the condition code mnemonic the flag setting it represents and the binary encoding for each The Carry Zero Sign and Parity O
74. also supports operations on bits BCD Binary Coded Decimal digits words 16 bits or 32 bits byte strings and word strings For details on this topic refer to Section 4 3 Data Types 1 4 2380 USER S MANUAL 1 2 4 Addressing Modes Addressing modes are used by the Z380 CPU to calculate the effective address of an operand needed for execution of an instruction Seven addressing modes are supported by the Z380 CPU Of these seven one is an addition to the Z80 CPU addressing modes Stack Pointer Relative and the remaining six modes are either existing or extensions to Z80 CPU addressing modes Register Immediate Indirect Register Direct Address Indexed Program Counter Relative Stack Pointer Relative All addressing modes are available on the 8 bit load arithmetic and logical instructions the 8 bit shift rotate and bit manipulation instructions are limited to the regis ters and Indirect register addressing modes The 16 bit loads on the addressing registers support all addressing modes except Index while other 16 bit operations are limited to the Register Immediate Indirect Register In dex Direct Address and PC Relative addressing modes For details on this subject refer to Chapter 4 Addressing Modes and Data Types 1 2 5 Instruction Set The Z380 CPU instruction set is an expansion of the Z80 instruction set the enhancements include support for additional addressing modes for the Z80 instru
75. and Long Word sized if in the Extended mode in either case even aligned least significant byte with address AO 0 mean ing 128 different vectors can be used in the Native mode and 64 different vectors can be used in Extended mode 6 5 4 Interrupt Mode 3 Response for Maskable Interrupt INTO Interrupt Mode 3 is similar to mode 2 except that a 16 bit vector is expected to be placed on the data bus D15 D0 by the I O device during the Interrupt acknowledge transac tion The interrupted PC is pushed onto the stack The size of the PC value pushed onto the stack depends on the 6 5 7106 6 5 4 Interrupt Mode 3 Response for Maskable Interrupt INTO Continued Native one word or Extended mode two words in effect IEF1 and IEF2 reset to logic 0 so as to disable further maskable Interrupt requests The starting address of the service routine is fetched and loaded into the PC to resume execution from memory location with an address com posed of the Extend contents as A31 A16 and the vector supplied by the I O device as A15 A0 Again the starting 2380 USER S MANUAL address of the service routine is word sized if the 7380 MPU is in Native mode and Long Word sized if in the Extended mode in either case even aligned meaning 32768 different vectors can be used in the Native mode and 16384 different vectors can be used in the Extended mode 6 6 ASSIGNED INTERRUPT VECTORS MODE FOR MASKABLE INTERRUPTS INT3 INT1 Re
76. appear in this document Zilog Inc makes no commitment to update or keep current the information contained in this document Zilog s products are not authorized for use as critical compo nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use Life support devices or systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 Telex 910 338 7621 FAX 408 370 8056 Internet http www zilog com DC 8297 03 3 3 N lt 4 1 INSTRUCTION An instruction is a consecutive list of one or more bytes in memory Most instructions act upon some data the term operand refers to the data to be operated upon For Z380 CPU instructions operands can reside in CPU registers memory locations or ports internal or external The method used to designate the location of the operands for 4 2 ADDRESSING MODE DESCRIPTIONS The following pages contain descriptions of the address ing modes for the Z380 CPU Each description explains how the operand s location is calculated indicates which address spaces can
77. be accessed with that particular addressing mode and gives an example of an instruction using that mode illustrating the assembly language format for the addressing modes 4 2 1 Register R RX When this addressing mode is used the instruction pro cesses data taken from one of the 8 bit registers A B C L IXU IXL IYU IYL one of the 16 bit registers BC DE HL IX lY SP or one of the special byte registers or R Storing data in a register allows shorter instructions and faster execution that occur with instructions that access memory Instruction OPERATION REGISTER gt OPERAND The operand value is the contents of the register The operand is always in the register address space The register length byte or word is specified by the instruction opcode In the case of Long Word register operation it is specified either through the SETC LW instruction or the DDIR LW decoder directive DC 8297 03 USER s MANUAL CHAPTER 4 ADDRESSING MODES AND DATA TYPES an instruction are called addressing modes The Z380 CPU supports seven addressing modes Register Imme diate Indirect Register Direct Address Indexed Program Counter Relative Address and Stack Pointer Relative A wide variety of data types can be accessed using these addressing modes Example of R mode 1 Load register in Word mode DDIR W Next instruction in Word mode LD BC HL the contents of HL into BC BCz BC HLz HL
78. bit status Since exiting from these instructions will be done when counter value gets to 0 the count value stored in the BC registers DC 8297 03 71106 has to be an even number DO 0 in Word mode transfer and multiple of four in Long Word mode D1 and DO are both 0 Also in Word or Long Word Block transfer memory pointer values are recommended to be even numbers so the number of the transactions will be mini mized Note that regardless of the Z380 s operation mode Native or Extended memory pointer increment decrement will be done in modulo 232 For example ifthe operation is LDI and HL31 HLO HLz and HL hold 0000FFFF after the opera tion the value in the HL31 HLO will be 0010000 Table 5 8 Block Transfer and Search Group Instruction Name Format Compare and Decrement CPD Compare Decrement and Repeat CPDR Compare and Increment Compare Increment and Repeat CPIR Load and Decrement LDD Load Decrement and Repeat LDDI Load and Increment LDI Load Increment and Repeat LDIR Load and Decrement in Word Long Word LDDW Load Decrement and Repeat in Word Long Word LDDRW Load and Increment in Word Long Word LDIW Load Increment and Repeat in Word Long Word LDIRW 2380 USER S MANUAL 5 5 4 8 bit Arithmetic and Logical Group This group of instructions Table 5 9 perform 8 bit arith metic and logical operations The Add Add with Carry Subtract Subtract with Carry AND OR Exclusive OR and Compare
79. customer and Zilog prior to use Life support devices or systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 Telex 910 338 7621 FAX 408 370 8056 Internet http www zilog com v This Appendix contains a quick reference guide for pro gramming It has the Z380 instructions sorted alphabeti cally The column Mode indicates whether the instruction is affected by DDIRimmediate Decoder Directives Extended mode or Native mode of operation and Word or Long Word mode of operation I means the instruction can be used USER s MANUAL APPENDIX B Z380 INSTRUCTIONS IN ALPHABETIC ORDER with DDIRIM to expand its immediate constant X means that the operation of the instruction is affected by the XM status bit and L means that the instruction is affected by LW status bit or can be used with DDIR LW or DDIR W The Native Extended modes Word Long Word modes and Decoder Directives are discussed in Chapter 3 in this manual meu Source Code ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW AD
80. decrement add subtract indexed stack relative and PC relative only operate on 16 bits and the Stack Pointer SP only increments and decrements across 16 bits The PC high order word is left at all zeros as the high order words of the SP and the I register Thus Native mode is fully compatible with the Z80 CPU s 64 Kbyte address mode It is still possible to address memory outside of 64 Kbyte address space for data storage and retrieval in Native mode however since direct addresses indirect addresses and the high order word of the SP I and the IX and IY registers may be loaded with non zero values Executed code and interrupt service routines must reside in the lowest 64 Kbytes of the address space In Extended mode however all address manipulation instructions operate on 32 bits allowing access to the entire 4 Gbyte address space of the Z380 CPU In both Native and Extended modes the Z380 drives all 32 bits of the address onto the external address bus only the width of the manipulated addresses distinguishes Native from Extended mode The Z380 CPU implements one instruc tion to allow switching from Native to Extended mode SETC XM however once in Extended mode only Reset DC 8297 03 USER S MANUAL will return the Z380 CPU to Native mode This restriction applies because of the possibility of misplacing interrupt service routines or vector tables during the transition from Extended mode back to Native mo
81. either of the corresponding bits in the two operands is 1 otherwise a 0 bit is stored The contents of the source are unaffected Flags 6 Setifthe most significant bit of the result is set cleared otherwise Z Setif all bits of the result are zero cleared otherwise H Cleared P Setif the parity is even cleared otherwise N Cleared C Cleared Addressing Execute Mode Syntax Instruction Format Time Note R OR 10110 r 2 RX OR A RX 11 11101 1011010w 2 IM OR 11110110 n 2 IR OR A HL 10110110 2 r X OR A XY d 11y11101 10110110 d 4 r Field Encodings r per convention y O for IX 1 for IY w Oforhigh byte 1 for low byte DC 8297 03 5 111 7106 ORW OR WORD ORW HL src src R RX IM X Operation HL 15 0 lt HL 15 0 OR src 15 0 2380 USER S MANUAL Alogical OR operation is performed between the corresponding bits of the source operand and the HL register and the result is stored in the HL register A 1 bit is stored wherever either of the corresponding bits in the two operands is 1 otherwise 0 bit is stored The contents of the source are unaffected Flags 6 Setif the most significant bit of the result is set cleared otherwise Z Setif all bits of the result are zero cleared otherwise H Cleared P Setif the parity is even cleared otherwise N Cleared C Cleared Addressing Execute Mode Syntax Instruction Format Time R ORW HL R 11101101 101101rr
82. explicitly in the instruction or are implied by the semantics of the instruc tion 2 1 2380 7106 USER S MANUAL 2 2 CPU REGISTER SPACE Continued 4 Sets of Registers SPz PCz Figure 2 1 Register File Organization Z380 MPU 2 2 DC 8297 03 7106 2 2 1 Primary and Working Registers The working register set is divided into two register files the primary file and the alternate file designated by prime Each file contains an 8 bit accumulator a Flag register F and six 8 bit general purpose registers C D E H and L with their Extended registers Only one file can be active at any given time although data in the inactive file can still be accessed by using EX R R instructions for the byte wide registers EX RR RR instruc tions for register pairs either in 16 bit or 32 bit wide depending on the LW status Exchange instructions allow the programmer to exchange the active file with the inac tive file The EX AF AF EXX or EXALL instructions changes the register files in use Upon reset the primary register file in register set 0 is active Changing register sets is asimple matter of an LDCTL instruction to program SR The accumulator is the destination register for 8 bit arith metic and logical operations The six general purpose registers can be paired BC DE and HL and are ex tended to 32 bits by the extension to the register with suffix z BCz DEz HLz to form thr
83. in which the interrupting peripheral device provides a vector into a table of jump address m Enhanced vectored interrupt mode Mode wherein the CPU expects 16 bit vector instead of 8 bit interrupt vectors in Mode 2 1 3 BENEFITS OF THE ARCHITECTURE The Z380 CPU architecture provides several significant benefits including increased program throughput achieved by higher bus bandwidth 16 bit wide bus reduction to two clocks basic machine cycle vs four clocks cycle on the Z80 CPU prefetch cue access to the larger linear addressing space enhanced instructions new address ing mode data address manipulation in 16 32 bits and faster context switching by utilizing multiple register banks 1 3 1 High Throughput Very high throughput rates can be achieved with the Z380 CPU due to the basic machine cycle s reduction to two clocks cycle from four clocks cycle on the Z80 CPU fine tuned four staged pipeline with prefetch cue This well designed pipeline and prefetch cue are both totally trans parent to the user thus maximizing the efficiency of the pipeline all the time The 2380 CPU implemented onto the Z380 MPU is configured with a 16 bit wide data bus which doubles the bus bandwidth These architectural features result in two clocks instructions execution minimum three clocks instruction on average The high clock rates up to 40 MHz achievable with this processor Make the overall performance of the Z380 CPU more than ten
84. is copied without destroying the overlapping area This instruction can be interrupted after each execution of the basic operation The Program Counter value of the start of this instruction is saved before the interrupt request is accepted so that the instruction can be properly resumed Unaffected Unaffected Cleared Cleared Cleared Unaffected Execute Syntax Instruction Format Time Note LDDR 11101101 10111000 n X 3 r w 2380 USER S MANUAL DC 8297 03 2380 7106 USER S MANUAL LDDRW LOAD DECREMENT AND REPEAT WORD LDDRW Operation repeat until BC 0 begin if LW then begin DE HL DE 1 HL 1 DE 2 HL 2 DE 3 HL 3 DE DE 4 HL HL 4 15 0 15 0 4 else begin DE HL DE 1 lt HL 1 DE DE 2 HL lt HL 2 15 0 15 0 2 This instruction is used for block transfers of strings of data The words of data atthe location addressed by the HL register are loaded into memory starting at the location addressed by the DE register The number of words moved is determined by the contents of the BC register If the BC register contains zero when this instruction is executed 65 536 words are transferred The effect of decrementing the pointers during the transfer is important if the source and destination strings overlap with the source string starting at a lower memory address Placing the pointers at the highest address of the strings and decreme
85. lt PC 7 0 SP 1 lt 15 8 SP 2 lt 23 16 SP 3 lt 31 24 31 0 lt 31 0 dst 31 0 else begin SP lt SP 2 SP lt PC 7 0 SP 1 lt 15 8 15 0 lt 15 0 dst 15 0 conditional Call transfers program control to the destination address if the setting selected flag satisfies the condition code specified in the instruction an unconditional call always transfers control to the destination address The current contents of the Program Counter PC are pushed onto the top of the stack the PC value used is the address of the first instruction byte following the Callinstruction The destination address is then loaded into the and points to the first instruction of the called procedure At the end of a procedure a RETurn instruction is used to return to the original program These instructions employ either an 8 bit 16 bit or 24 bit signed two s complement displacement from the PC to permit calls within the range of 126 to 129 bytes 32 765 to 32 770 bytes or 8 388 604 to 8 388 611 bytes from the location of this instruction Each of the Zero Carry Sign and Overflow flags be individually tested and call performed conditionally on the setting of the flag S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Execute Syntax Instruction Format Time CALR 11101101 11
86. of data from the memory location addressed by the HL register is loaded into the selected peripheral The HL register is then decremented by two thus moving the pointer to the next source for the output If the result of decrementing the BC register is 0 the instruction is terminated otherwise the sequence is repeated If the BC register contains 0 atthe start of the execution of this instruction 65536 bytes are output This instruction can be interrupted after each execution of the basic operation The Program Counter value atthe start of this instruction is saved before the interrupt request is accepted so that the instruction can be properly resumed 2380 User s MANUAL S Unaffected Z Set if the result of decrementing is zero cleared otherwise H Unaffected V Unaffected Set Unaffected Execute Syntax Instruction Format Time Note OTDRW 11101101 11111011 2 0 DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 OTIM 2380 USER S MANUAL OTIM OUTPUT INCREMENT MEMORY HL lt C 1 lt 1 HL 1 This instruction is used for block output of strings of data to on chip peripherals No external I O transaction will be generated as a result of this instruction although the I O address will appear on the address bus and the write data will appear on the data bus while this internal write is occurring The peripheral address is placed on the low byte of the address
87. register used as counter is decremented by one The HL register is then decremented by two thus moving the pointer to the next destination for the input If the result of decrementing the BC register is 0 the instruction is terminated otherwise the sequence is repeated Ifthe BC register contains 0 at the start of the execution of this instruction 65536 bytes are input This instruction can be interrupted after each execution of the basic operation The Program Counter value atthe start of this instruction is saved before the interrupt requestis accepted so that the instruction can be properly resumed S Unaffected Z Set if the result of decrementing BC is zero cleared otherwise H Unaffected V Unaffected Set Unaffected Execute Syntax Instruction Format Time Note INDRW 11101101 11111010 n X 2 i w 5 75 7106 2380 USER S MANUAL INPUT AND INCREMENT BYTE Operation Flags Addressing Mode 5 76 INI HL lt 8 1 HL This instruction is used for block input of strings of data During the 1 transaction the 32 bit BC register is placed onthe address bus Note that the B register contains the loop count for this instruction so that A15 A8 are not useable as part of a fixed port address First the byte of data from the selected peripheral is loaded into the memory location addressed by the HL register Then the B register used as a counter is decremented by one The
88. takes one input operand from the accumulator and the other from a register from immediate data in the instruction itself or from memory For memory addressing modes follows are supported lndirect Register Indexed and Direct Address except multiplies which returns the 16 bit result to the same register by multiplying the upper and lower bytes of one of the register pair BC DE HL or SP The Increment and Decrement instructions operate on data in register or in memory all memory addressing modes are supported These instructions operate only on the accumulator Decimal Adjust Complement and Ne gate The final instruction in this group Extend Sign sets the CPU flags according to the computed result The EXTS instruction extends the sign bit and leaves the result in the HL register If it is in Long Word mode HLz HL31 HL16 portion is also affected The TST instruction is a nondestructive AND instruction It ANDs A register and source and changes flags accord ing to the result of operation Both source and destination values will be preserved Table 5 9 Supported Source Destination for 8 Bit Arithmetic and Logic Group src Instruction Name Format dst A B C D L IXH IXL n HL IX d Add With Carry Byte se V V VV NV NV N N N 1 N NN N Add Byte ADAsc sc 4 V N N 4 NV NV NV NV 34 N N N N AND A sre sc V V 4 NV N NV NV NV NV 34 vv N N V Compare Byte se 4
89. the Indirect Register or Indexed addressing mode The RLD and RRD instructions are provided for manipulat ing strings of BCD digits these rotate 4 bit quantities in memory specified by the Indirect Register The low order four bits of the accumulator are used as a link between rotation of successive bytes Table 5 11 Bit Set Reset Test Rotate and Shift Group Instruction Name Format A B D E H L HL IX d IY d Bit Test BIT dst V V NV NV NV V N RESdst V NV NV N y Rotate Left RL dst y V NW V N Rotate Left Accumulator RLA y Rotate Left Circular RLC dst V 4 M Vv 4 4 4 Rotate Left Circular Accumulator Rotate Left Digit RLD Rotate Right RR dst j V V NV NV NV N Rotate Right Accumulator RRA y Rotate Right Circular RRCdst V NV NV N N y Rotate Right Circular Accumulator RRCA y Rotate Right Digit RRD y Set Bit V v Shift Left Arithmetic SLA dst V 4 4 1 Vv NI 4 4 Shift Right Arithmetic SRA dst A V V NI 4 4 Shift Right Logical SRL V V V V NM M N N 5 5 7 16 Bit Manipulation Rotate and Shift Group Instructions in this group Table 5 12 rotate and shift word data one bit position Rotate can optionally concatenate the Carry flag to the word to be manipulated Both left and right shifting is supported Right shifts can either shift 0 into bit 15 logical shifts or can replicate the sign in bits 14 a
90. the input If the result of decrementing the B register is 0 the instruction is terminated otherwise the sequence is repeated If the B register contains 0 at the start of the execution of this instruction 256 bytes are input This instruction can be interrupted after each execution of the basic operation The Program Counter value atthe start of this instruction is saved before the interrupt request is accepted so that the instruction can be properly resumed 2380 USER S MANUAL S Unaffected Z Setif the result of decrementing is zero cleared otherwise H Unaffected V Unaffected Set Unaffected Execute Syntax Instruction Format Time Note INDR 11101101 10111010 n X 2 i W DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL INDRW INPUT DECREMENT AND REPEAT WORD INDRW repeat until BC 0 begin HL DE 15 0 lt 15 0 1 HL lt HL 2 end This instruction is used for block input of strings of data The string of input data from the selected peripheral is loaded into memory at consecutive addresses starting with the location addressed by the HL register and decreasing During the transaction the 32 bit DE register is placed on the address bus First the BC register used as a counter is decremented by one First the word of data from the selected peripheral is loaded into the memory location addressed by the HL register Then the BC
91. the stack 3 The states of IEF1 and IEF2 are cleared 4 The Z380 MPU commences to fetch and execute instructions from address 00000000H Note that instruction execution resumes at address 0 similar to the occurrence of a reset Testing the TF and TV bits in the Assigned Vectors Base and Trap Register will distinguish the two events Even if Trap handling is not in place repeated restarts from address 0 is an indicator of possible illegal instructions at system debugging DC 8297 03 71106 6 4 NONMASKABLE INTERRUPT The Nonmaskable Interrupt Input is edge sensitive with the 2380 MPU internally latching the occurrence of its falling edge When the latched version of NMI is recog nized the following operations are performed 1 Thelnterrupted PC Program Counter value is pushed onto the stack The size of the PC value pushed onto the stack depends on Native one word or Extended mode two words in effect 2380 USER S MANUAL 2 The state of IEF1 is copied to IEF2 then IEF1 is cleared 3 7380 MPU commences to fetch and execute instructions from address 00000066H 6 5 INTERRUPT RESPONSE FOR MASKABLE INTERRUPT ON INTO The transactions caused by the Maskable Interrupt on INTO are different depends on the Interrupt Mode in effect at the time when the interrupt has been accepted as described below 6 5 1 Interrupt Mode 0 Response for Maskable Interrupt INTO This mode is similar to the 8080
92. then begin dst 31 0 src 31 0 end else begin dst 15 0 src 15 0 end The contents of the destination are exchanged with the contents of the source Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Addressing Mode Syntax R EX BC DE EX BC HL EX DE HL RX EX R RX EX IX IY Instruction Format 11101101 00000101 11101101 00001101 11101011 11101101 OOrry011 11101101 00101011 Field Encodings rr 00 for BC 01 for DE 11 for HL y for IX 1 for IY 5 52 Execute Time 2380 USER S MANUAL DC 8297 03 7106 Operation Flags Addressing Mode R 2380 USER S MANUAL EX EXCHANGE REGISTER WITH ALTERNATE REGISTER BYTE EX dst src src dst lt gt src The contents of the destination are exchanged with the contents of the source where the destination is a register in the primary bank and the source is the corresponding register in the alternate bank S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Execute Syntax Instruction Format Time Note EX RR 11001011 00110 r 3 Field Encoding r per convention DC 8297 03 5 53 2380 7106 USER S MANUAL EX EXCHANGE REGISTER WITH ALTERNATE REGISTER WORD EX dst src src RX Operation if LW then begin dst 31 0 src 31 0 end else begin dst 15 0 lt gt src 15 0 end The contents of the destination are exc
93. times that of the Z80 1 3 2 Linear Memory Address Space Z380 CPU architecture has 4 Gbytes of linear memory address space The Z80 CPU architecture allows 64 Kbytes of memory addressing space This was more than sufficient when the Z80 CPU was first developed But as DC 8297 03 USER S MANUAL The first three modes are compatible with Z80 interrupt modes the fourth mode provides more flexibility Traps are synchronous events that trigger a special CPU response when an undefined instruction is executed It can be used to increase system reliability or used as a software trap instruction Hardware resets occur when the RESET line is activated and override all other conditions A RESET causes certain CPU control registers to be initialized For details on this subject refer to Chapter 6 Interrupts and Traps the technology improved over time applications started to demand morecomplicated processing multitasking faster processing etc with the high level language needed to develop software As a result 64 Kbytes of memory ad dressing space is not enough for some Z80 CPU based applications In order to handle more than 64 Kbytes of memory the Z80 CPU requires Memory Banking scheme or MMU Memory Management Unit like the Z180 MPU or 2280 MPU These provide the overhead to access more than 64 Kbytes of memory The 2380 CPU architecture allows access to a full 4 Gbytes 2 of memory addressing s
94. 06 RETI RETURN FROM INTERRUPT Operation Flags Addressing Mode 5 142 RETI if XM then begin PC 7 0 lt SP 8 SP 1 PC 23 16 SP 2 PC 31 24 SP 3 SP SP 4 else begin PC 7 0 lt SP PC 15 8 lt SP 1 SP lt SP 2 This instruction is used to return to previously executing procedure at the end procedure entered by an interrupt The contents of the location addressed by the Stack Pointer SP are popped into the Program Counter PC thereby specifying the location of the next instruction to be executed special sequence of bus transactions is performed when this instruction is executed in order to control Z80 family peripherals see the description of the external interface for more details S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Execute Syntax Instruction Format Time Note RETI 11101101 01001101 24r X 2380 USER S MANUAL DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 RETN if XM then begin PC 7 0 RE 8 kund 16 TTTTT SP end else begin PC 7 0 PC 15 8 SP end IEF1 TT P SP 1 S SP 2 SP 3 SP 4 SP SP 1 SP 2 IEF2 2380 USER S MANUAL RETN RETURN FROM NONMASKABLE INTERRUPT This instruction is used to return to previously executing procedure at the end procedure entered by a nonmaskable interrup
95. 06 USER S MANUAL IN INPUT ACCUMULATOR IN A n Operation lt The byte of data from the selected peripheral is loaded into the accumulator During the I O transaction the 8 bit peripheral address from the instruction is placed on the low byte of the address bus the contents of the accumulator are placed on address lines A15 A8 and the high order address lines are all zeros Flags S Unaffected 7 Unaffected Unaffected V Unaffected N Unaffected Unaffected Addressing Execute Mode Syntax Instruction Format Time Note IN A n 11011011 n 3 1 5 66 DC 8297 03 2380 71 06 USER S MANUAL INO INPUT FROM PAGE 0 INO dst n dst R Operation dst n The byte of data from the selected on chip peripheral is loaded into the destination register No external I O transaction will be generated as a result of this instruction although the I O address will appear on the address bus while this internal read is occurring The peripheral address is placed on the low byte of the address bus and zeros are placed on all other address lines When the second opcode byte is 30h no data is stored in a destination only the flags are updated Flags S Set if the input data is negative cleared otherwise Z Set if the input data is zero cleared otherwise Cleared P Set if the input data has even parity cleared otherwise N Cleared Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R INO
96. 10001110 d 4 r Field Encodings r per convention y O for IX 1 for IY w Oforhigh byte 1 for low byte 5 20 DC 8297 03 71106 2380 USER S MANUAL ADC ADD WITH CARRY WORD ADC HL src dst HL src BC DE HL SP Operation 15 0 lt HL 15 0 sre 15 0 C The source operand together with the Carry flag is added to the HL register and the sum is stored in the HL register The contents of the source are unaffected Two s complement addition is performed Flags S Set if the result is negative cleared otherwise Setifthe result is zero cleared otherwise Setif there is carry from bit 11 of the result cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise Cleared C Setifthere is a carry from the most significant bit of the result cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R ADCHL R 11101101 01111010 2 Field Encodings rr 00 for BC 01 for DE 10 for HL 11 for SP DC 8297 03 5 21 2380 7106 USER S MANUAL ADCW ADD WITH CARRY WORD ADCW HL src src R IM X Operation HL 15 0 lt HL 15 0 src 15 0 C The source operand together with the Carry flag is added to the HL register and the sum is stored in the HL register The contents of the source are unaffected Two s complement addition is performed Flags S Set if t
97. 101 01000111 2 LD 11101101 01001111 2 DC 8297 03 5 91 7106 LD W LOAD I REGISTER WORD LD W dst src dst HL src OR dst src HL Operation if LW then begin dst 31 0 lt src 31 0 end else begin dst 15 0 lt src 15 0 end The contents of the source are loaded into the destination Flags S Unaffected 7 Unaffected Unaffected Unaffected Unaffected Unaffected Load from I Register Addressing Execute Mode Syntax Instruction Format Time R LD W 11011101 01010111 2 Load into I Register Addressing Execute Mode Syntax Instruction Format Time R LD W LHL 11011101 01000111 2 5 92 2380 USER S MANUAL Note Note DC 8297 03 2380 7106 USER S MANUAL LDCTL LOAD CONTROL REGISTER BYTE LDCTL dst src dst DSR XSR YSR src IM or dst A src DSR XSR YSR or dst SR src IM Operation if dst SR then begin SR 31 24 SIC SR 23 16 SIC SR 15 8 lt SIC end else begin dst lt src end The contents of the source are loaded into the destination Flags S Unaffected Z Unaffected H Unaffected V Unaffected Unaffected Unaffected Load into Control Register Addressing Execute Mode Syntax Instruction Format Time Note R LDCTL SR A 11011101 11001000 4 LDCTL Rd A 11441101 11011000 4 IM LDCTL SR n 11011101 11001010 n 4 LDCTL Rd n 11441101 11011010 n 4 Field Encodings qq 01 for XSR 10 for DSR 11 for YSR
98. 11001011 000110 2 RRW RX 11101101 11001011 0001110y 2 RRW HL 11101101 11001011 00011010 2 r RRW XY d 11y11101 11001011 d 00011010 4 r Field Encodings rr 00 for BC 01 for DE 11 for HL 5 152 y for IX 1 for IY DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL RRA ROTATE RIGHT ACCUMULATOR RRA lt A7 lt C C lt 0 A n lt 1 0 to 6 The contents of the accumulator are concatenated with the Carry flag and together they are rotated right one bit position Bit 0 of the accumulator is moved to the Carry flag and the Carry flag is moved to bit 7 of the accumulator S Unaffected Z Unaffected H Cleared P Unaffected N Cleared Set if the bit rotated from bit 0 was a 1 cleared otherwise Execute Syntax Instruction Format Time Note RRA 00011111 2 5 153 2380 7106 USER S MANUAL RRC ROTATE RIGHT CIRCULAR BYTE dst dst IR X Operation tmp lt dst C lt dst 0 dst 7 lt 0 dst n lt imp n 1 forn 0 to 6 The contents of the destination operand are rotated right one bit position Bit 0 of the destination operand is moved to the bit 7 position and also replaces the Carry flag Flags S Setif the most significant bit of the result is set cleared otherwise Z Setif the result is zero cleared otherwise H Cleared P Setif parity of the result is even cleared otherwise
99. 12H 1FH P 1234H IX 12H HL IX 12H LW SP IX 1FH M 1234H IX 12H HL IX 12H LW A 12H 18H NV 1234H PO 1234H SP HL NV 1234H PO 1234H HL 12H A 12H 20H PE V HL PE 1234H V 1234H DE HL V 1234H PE 1234H B 12H 12H B BC BC BC IX B BC DE 1234 C 12H 12H C BC HL BC Mode gt gt XXX XX gt gt gt gt Object Code 12 12 34 12 12 12 12 12 12 12 34 12 12 12 34 12 34 12 Source Code EX IN0 OUTO LD EX TST LDW EX INO OUTO EX TST SWAP EX INO OUTO TST EX INO OUTO EX TST EX INO LD EX TST LDW EX INO OUTO EX TST SWAP EX IN OUT SBC A C D 12H 12H D DE BC DE IX D DE 1234H A D E 12H 12H E DEY E DE AE H 12H 12H H H A H L 12H 12H L IX IY L 12H HL BC HL IX HL HL 1234H A HL A 12H 12H A HL IVY A HL C B HL BC 1234H BC A 0 LA C C HL BC 1234 3 R A D C C D Mode Object Code ED 52 ED 53 ED 54 ED 54 ED 55 ED 56 ED 57 ED 58 ED 59 ED ED 5B ED 5 ED 5E ED 5F ED 60 ED 61 ED 62 ED 63 ED 64 ED 65 ED 65 ED 67 ED 68 ED 69 ED 6A ED 6B ED 6C ED 6F ED 71 ED 72 ED 73 ED 74 ED 75 ED 75 ED 76 ED 78 ED 79 ED 7A ED 7B ED 7C ED 82 ED 83 ED 84 ED 84 ED 85 ED 85 ED 86 ED 86 ED 87 ED 87 ED 8B ED 8C ED 8C ED 8D 34 34
100. 2 0 5 119 7106 OTIRW OUTPUT INCREMENT AND REPEAT WORD Operation Flags Addressing Mode 5 120 OTIRW repeat until BC 0 begin 15 0 lt BC 15 0 1 DE lt HL HL lt HL 2 end This instruction is used for block output of strings of data The string of output data is loaded into the selected peripheral from memory at consecutive addresses starting with the location addressed by the HL register and increasing During the I O transaction the 32 bit DE register is placed on the address bus First the BC register used as a counter is decremented by one The word of data from the memory location addressed by the HL register is loaded into the selected peripheral The HL register is then incremented by two thus moving the pointer to the next source for the output If the result of decrementing the BC register is 0 the instruction is terminated otherwise the sequence is repeated If the BC register contains 0 atthe start of the execution of this instruction 65536 bytes are output This instruction can be interrupted after each execution of the basic operation The Program Counter value atthe start of this instruction is saved before the interrupt request is accepted so that the instruction can be properly resumed S Unaffected Z Set if the result of decrementing is zero cleared otherwise H Unaffected V Unaffected Set Unaffected Execute Syntax Instruction Format Time Note OT
101. 2 RX ORW HL RX 11y11101 10110111 2 IM ORW HL nn 11101101 10110110 n low n high 2 1 ORW 11y11101 11110110 d 4 r Field Encodings rr 00 for BC 01 for DE 11 for HL y Ofor IX 1 for IY 5 112 Note DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL OTDM OUTPUT DECREMENT MEMORY OTDM C HL lt C i lt 1 HL HL 1 This instruction is used for block output of strings of data to on chip peripherals No external I O transaction will be generated as a result of this instruction although the I O address will appear on the address bus and the write data will appear on the data bus while this internal write is occurring The peripheral address is placed on the low byte of the address bus and zeros are placed on all other address lines The byte of data from the memory location addressed by the HL register is loaded to the on chip I O port addressed by the C register The C register holding the port address is decremented by one to select the next output port The B register used as a counter is then decremented by one The HL register is then decremented by one thus moving the pointer to the next source for the output S Set if the result of decrementing B is negative cleared otherwise Z Set if the result of decrementing B is zero cleared otherwise Setif there is a borrow from bit 4 during the decrement of the B regi
102. 2 56 12 5 12 66 12 6 12 76 12 7 FD 12 86 12 8 12 92 12 92 12 96 12 9A 12 9A 12 9E 12 12 FD 12 B6 FD 12 FD 12 FD 12 FD 12 6 12 FD 12 06 12 12 12 12 F6 12 FD CC 56 34 FD CD 56 34 FD CE 12 FD CE 12 FD DO FD D3 34 12 FD D4 56 34 FD D6 12 FD D6 12 12 12 12 Source Code RRW DIVUW DIVUW RES SET SET SET SET SET SET SET SET CALR CALR ADCW ADCW LDCTL OUTAW CALR SUBW SUBW IY 12H IY 12H DE IY 12H IY SP 12H IY 12H IX IY 12H IY 12H SP 12H IY IY 12H IY 12H IX IY 12H HL IY 12H IY 12H IY 12H HL IY 12H HL IY 12H 2 IY 12H IY 12H HL IY 12H 3 IY 12H 4 IY 12H 5 IY 12H 6 IY 12H IY 12H HL IY 12H 2 123456 123456 IY 12H HL IY 12H A YSR 1234H HL 123456 IY 12H HL IY 12H Object Code FD FE 12 FD FE 12 12 12 12 12 Source Code LDCTL EXXY LDCTL INAW CALR SBCW SBCW POP EX CALR PUSH ANDW ANDW JP CALR XORW XORW CALR PUSH ORW ORW SETC LD CALR CPW YSR A YSR 01H HL 1234H C 123456H IY 12H HL IY 12H IY SP IY PO 123456H IY 12H HL IY 12H IY
103. 234H ANDW HL 1234H ANDW HL ANDW HL HL LDD CPD IND OUTD XORW BC XORW HL BC XORW DE XORW HL DE XORW 1234 XORW HL 1234H XORW HL XORW HL HL LDIR CPIR INIR OTIR ORW BC ORW HL BC ween v nne Object Code Source Code Mode Object Code Source Code Mode ED B5 ORW DE ED CB 28 SRAW BC ED B5 ORW HL DE ED CB 29 SRAW DE ED B6 34 12 ORW 1234H ED CB 2A SRAW HL ED B6 34 12 ORW HL 1234H ED CB 2B SRAW HL ED B7 ORW HL ED CB 2C SRAW IX ED B7 ORW HL HL ED CB 2D SRAW IY ED B8 LDDR ED CB 30 EX BC BC L ED B9 CPDR X ED CB 31 EX DEDE L ED BA INDR ED CB 33 EX HL HL L ED BB OTDR ED CB 34 EX IX IX ED BC CPW BC ED CB 35 EX L ED BC CPW HL BC ED CB 38 SRLW BC ED BD CPW DE ED CB 39 SRLW DE ED BD CPW HL DE ED CB 3A SRLW HL ED BE 34 12 CPW 1234H ED CB 3B SRLW HL ED BE 34 12 CPW HL 1234H ED CB 3C SRLW IX ED BF CPW HL ED CB 3D SRLW IY ED BF CPW HL HL ED CB 90 MULTW BC ED CO LDCTL HL SR L ED CB 90 MULTW HL BC ED C1 POP SR L ED CB 91 MULTW DE ED C4 12 CALR NZ 12H x ED CB 91 MULTW HL DE ED C5 PUSH SR L ED CB 93 MULTW HL ED C6 34 12 ADD HL 1234H X ED CB 93 MULTW HL HL ED C8 LDCTL SR HL L ED CB 94 MULTW HL IX ED CB 00 RLCW BC ED CB 94 MULTW IX ED CB 01 RLCW DE ED CB 95 MULTW HL IY ED CB 02 RLCW HL ED CB 95 MULTWIY ED CB 03 RLCW HL ED 97 34 12 MULTW 1234H ED CB 04 RLCW IX ED CB 97 34 12 MULTWHL 1234H ED CB 05 RLCW IY ED CB 98 MULTUW BC ED CB 08 RRCW BC ED CB 98 MULTUW HL BC ED
104. 2H FD CB 12 A6 POP IX L DD Ei RES 4 7 POP IY L FD Ei RES 4 8 0 POP SR L ED RES 4 CB 1 PUSH 1234H L FD F5 34 12 RES 4 2 Source Code Mode RES 4 E RES 4 H RES 4 L RES 5 HL RES 5 12 RES 5 IY 12H RES 5 RES 5 RES 5 RES 5 0 RES 5 RES 5 RES 541 RES 6 HL RES 6 IX 12H RES 6 IY 12H RES 6 RES 6 RES 6 RES 6 RES 6 RES 6 RES 61 RES 7 HL RES 7 1 12 RES 7 12 RES 7 RES 7 RES 7 RES 7 0 RES 7 E RES 7 H RES 71 LCK RESC LW reserved RET RET RET NC RET NS RET NV RET NZ RET PE RET PO RET V RET Z RET RETI RETN RL HL RL IX 12H RL IY 12H gt x gt gt x X X X X x X X X X gt x gt gt Object Code 12 12 12 12 12 12 12 12 AE AE B6 B6 BE BE 16 16 Source Code IX 12H IY 12H a IX 12H IY 12H DE HL IX HL IX 12H IY 12H IX 12H IY 12H oa gt Object Code 12 06 12 06 12 02 12 02 12 12 12 12 12 1E 12 1E 12 OE 12 OE meu Source Code H L RRCA RRCW HL RRCW IX 12H RRCW IY 12H RRCW BC RRCW DE RRCW HL RRCW IX RRCW IY RRD RRW HL RRW IX 12H RR
105. 3 Load BC register from memory location 12345E22H in Long Word mode DDIR IW LW extend direct address by one word operation in Long Word LD BC 12345E22H Load BC with the data in address 12345E22H BCz BC Before instruction execution 1234 5678 After instruction execution 0705 0301 Memory location 12345E22 01 12345E23 03 12345E24 05 12345E25 07 DC 8297 03 4 3 7106 4 2 5 Indexed When the Indexed addressing mode is used the data processed is at the location whose address is the contents of IX or IY in use offset by an 8 bit signed displacement in the instruction The Indexed address is computed by adding the 8 bit two s complement signed displacement specified in the instruction to the contents of the IXor IY register in use also specified by the instruction Indexed addressing allows random access to tables or other complex data structures where the address of the base of the table is known but the particular element index must be computed by the pro gram Instruction OPERATION REGISTER gt DISPLACEMENT ADDRESS 2380 USER S MANUAL The offset portion can be expanded to 16 or 24 bits instead of eight bits by using DDIR Immediate Data Direc tives DDIR IB for 16 bit offset DDIR IW for 24 bit offset Note that computation of the effective address is affected by the operation mode Native or Extended In Native mode address computation is done in modulo 215 and in Extended mode address com
106. 380 CPU This group consists of instructions for transferring a byte from to Internal I O locations and the CPU registers or memory or a blocks of bytes from the memory to the same size of Internal I O locations for initialization purposes These instructions are originally assigned as newly added instructions on the 7180 MPU to access Page 0 I O addressing space There is 256 Internal I O locations and all of them are byte wide When one of these instruc tions is executed the Z380 MPU outputs the register address being accessed in a pseudo transaction of two BUSCLK durations cycle withthe address signals A31 A8 at 0 In the pseudo transactions all bus control signals are at their inactive state The instructions for transferring a single byte INO OUTO can transfer data between any 8 bit CPU register and the Internal I O address specified in the instruction The INO instruction sets the CPU flags according to the input data however special instructions which do not have destina 2380 UsER s MANUAL tion in the instruction with Direct Address INO n do not affect the CPU register but alters flags accordingly An other variant the TSTIO instruction does a logical AND to the instruction operand with the internal location speci fied by the C register and changes the CPU flags without modifying CPU registers or memory The remaining instructions in this group form a powerful and complete complement of instr
107. 4 34 N N N N N N wN vv N N y Complement Accumulator CPL A dt N Decimal Adjust Accumulator DAA dst v Decrement Byte DEC dst dt 4 NV NV V N NV NV N N 4 N N N Extend Sign Byte EXTS A dt N Increment Byte INC dst dt V NV NV NV 34 N N NV N N N N N N y Multiply Byte MLT src Note 1 Negate Accumulator NEG A dst N OR OMA sc se V 4 wN N N N N N N N N N Subtract with Carry Byte SBCAsic se NV 14 34 4 34 o N N y Subtract Byte SUB A ec sc V VV N N N N y Nondestructive Test TST dst se N V VV N N N Exclusive OR XOR A sre se NN 4 N N N N N N N Note 1 dst DE HL or SP DC 8297 03 5 9 ZiLoG 5 5 5 16 Bit Arithmetic Operation This group of instructions Table 5 10 provide 16 bit arithmetic instructions The Add Add with Carry Subtract Subtract with Carry AND OR Exclusive OR and Com pare takes one input operand from an addressing register and the other from a 16 bit register or from the instruction itself the result is returned to the addressing register The 16 bit Increment and Decrement instructions operate on data found in a register or in memory the Indirect Register or Direct Address addressing mode can be used to specify the memory operand The remaining 16 bit instructions provide general arith metic capability using the HL register as one of the input operands The word Add Subtract Compare and signed and unsigned Multiply instructions tak
108. 5536 cleared otherwise N Unaffected Unaffected Execute Syntax Instruction Format Time Note DIVUW HL R 11101101 11001011 101110rr 20 DIVUW HL RX 11101101 11001011 1011110y 20 DIVUW HL nn 11101101 11001011 10111111 n low n high 20 DIVUW HL XY d 11y11101 11001011 d 10111010 22 r Field Encodings rr 00 for BC 01 for DE 11 for HL DC 8297 03 y OforIX 1 for IY 5 47 7106 DJNZ DECREMENT AND JUMP IF NON ZERO DJNZ dst dst lt 1 If lt gt 0 then begin dst lt SIGN EXTEND dst if XM then begin PC 31 0 end else begin PC 15 0 end end PC 31 0 dst 31 0 lt PC 15 0 dst 15 0 2380 User s MANUAL The B register is decremented by one If the result is non zero then the destination address is calculated and then loaded into the Program Counter Control then passes to the instruction whose address is pointed to by the PC When the B register reaches zero control falls through to the instruction following DJNZ This instruction provides a simple method of loop control The destination address is calculated using Relative addressing The displacement in the instruction is added to the PC the PC value used is the address of the instruction following the DJNZ instruction These instructions employ either an 8 bit 16 bit or 24 bit signed two s complement displacement from the PC to permit jumps within range of
109. 8 HL ED 63 78 56 34 12 CALL 12345678 D4 78 56 34 12 LD 12345678H IX DD 22 78 56 34 12 CALL NZ 12345678H C4 78 56 34 12 LD 12345678H IY FD 22 78 56 34 12 CALL 12345678 F4 78 56 34 12 LD 12345678H SP ED 73 78 56 34 12 CALL PE 12345678H EC 78 56 34 12 LD IX 123456H BC DD CB 56 34 12 OB CALL PO 12345678H F4 78 56 34 12 LD IX 123456H DE DD 56 34 12 1B CALL 2 12345678 CC 78 56 34 12 LD IX 123456H HL DD CB 56 34 12 3B JP 12345678H C3 78 56 34 12 LD 1 123456 IY DD 56 34 12 2B JP C 12345678H DA 78 56 34 12 LD IY 123456H BC FD CB 56 34 12 OB JP M 12345678H FA 78 56 34 12 LD 123456 73 56 34 12 JP 12345678 D2 78 56 34 12 LD IY 123456H HL FD CB 56 34 12 3B JP NS 12345678H F2 78 56 34 12 LD IY 123456H IX FD CB 56 34 12 2B JP NV 12345678H F2 78 56 34 12 LD SP 123456H BC DD CB 56 34 12 09 JP NZ 12345678H C2 78 56 34 12 LD SP 123456H DE DD CB 56 34 12 19 JP P 12345678H F2 78 56 34 12 LD SP 123456H HL DD CB 56 34 12 39 JP PE 12345678 78 56 34 12 LD SP 123456H IX DD 56 34 12 29 JP 12345678 2 78 56 34 12 LD SP 123456H 1Y FD CB 56 34 12 29 JP 5 12345678H FA 78 56 34 12 LD 12345678 ED 4B 78 56 34 12 JP V 12345678H EA 78 56 34 12 LD 1 123456 DD CB 34 12 03 JP Z 12345678H CA 78 56 34 12 LD BG IY 123456H FD 34 12 03 SUB HL 12345678H ED D6 78 56 34 12 LD BC SP 123456H DD 34 12 01 SUB SP 12345678H ED 92 78 56 34 12 LD DE 1234567
110. 8H ED 5B 78 56 34 12 LD IX 123456H DD 56 34 12 13 LD IV 123456H FD CB 56 34 12 13 LD 123456 DD 56 34 12 11 LD HL 12345678H 2A 78 56 34 12 LD HL 12345678H ED 6B 78 56 34 12 LD HL IX 123456H DD 56 34 12 33 LD HL IY 123456H FD CB 56 34 12 33 LD 123456 DD CB 56 34 12 31 LD IX 12345678H DD 2A 78 56 34 12 LD IX IY 123456H FD CB 56 34 12 23 LD IX SP 123456H DD CB 56 34 12 21 LD IY 12345678H FD 2A 78 56 34 12 LD 1 123456 DD 56 34 12 23 LD SP 123456H FD CB 56 34 12 21 LD SP 12345678H ED 7B 78 56 34 12 LDW 12345678 ED 06 78 56 34 12 LDW DE 12345678H ED 16 78 56 34 12 LDW HL 12345678H ED 36 78 56 34 12 Table E 7 Valid with DDIR IW in Long Word mode XM bit status does not affect the operation Either with DDIR IW LW or DDIR IW with LW bit set PUSH BC 12345678H DE 12345678H HL 12345678H 1 12345678 IY 12345678H 5 12345678 12345678 78 78 78 21 21 78 5 12 12 12 Table E 8 Valid with DDIR IW XM bit nor LW bit status do not affect the operation ADC ADC ADCW ADCW ADCW ADCW ADD ADD ADDW ADDW ADDW ADDW AND AND AND AND ANDW ANDW ANDW A IX 123456H A IV 123456H IX 123456H IY 123456H HL IX 123456H HL IY 123456H A IX 123456H A IY 123456H IX 123456H IY 123456H HL IX 123456H HL IY 123456H IX 123456H IY 123456H A IX 123456H A IV 123456H
111. 9 19 29 39 DD 09 DD 19 DD 29 DD 39 FD 09 FD 19 FD 29 FD 39 FD CD 56 DD CD 34 ED CD 12 FD DC 56 DD DC 34 ED DC 12 FD FC DD FC 34 ED FC 12 FD D4 56 DD D4 34 ED D4 12 FD 4 56 DD C4 34 ED 4 12 FD F4 56 DD F4 34 ED F4 12 FD EC 56 DD EC 34 ED EC 12 FD 4 56 DD E4 34 ED E4 12 FD 56 DD 34 ED 12 ED 9 ED B9 ED 1 ED Bli 0B 1B 2B DD 2B FD 2B 3B 0B 34 34 12 34 12 34 34 12 34 34 12 34 12 12 12 12 12 12 12 12 Source Code DECW DE DECW HL DECW IX DECW IY DECW SP DJNZ 123456H DJNZ 1234H DJNZ 12H INC BC INC DE INC HL INC IX INC IY INC SP INCW BC INCW DE INCW HL INCW IX INCW IY INCW SP JP HL JP IX JP JR 123456H JR 1234H JR 12H JR C 123456H JR C 1234H JR JR 123456 JR 1234 JR NZ 123456H JR 21234 JR NZ12H JR Z 123456H JR 21234 JR Z12H RET C RET M RET NC RET NS RET NV RET NZ RET P RET PE RET PO RET S RET V RET Z RET Object Code 1B 2B DD 2B FD 2B 3B FD 10 56 34 DD 10 34 12 10 12 03 13 23 DD 23 FD 23 33 03 13 23 DD 23 FD 23 33 E9 DD E9 FD E9 FD 18 DD 18 34 12 18 12 FD 38 56 34 DD 38 34 12 38 12 FD 30 56 34 DD 30 34 12 FD 20 56 34 DD 20 34 12 20 12 FD 28 56 34 DD 28 34 12 28 12 D8 F8 DO FO EO CO FO E8 F8 E8 8 9 ED 40
112. AA SUBW 1234H ED 96 34 12 XOR E AB SUBW BC ED 94 XOR H AC SUBW DE ED 95 XOR IXL DD AD SUBW HL ED 97 XOR IXU DD AC SUBW HL IX 12H DD D6 12 XOR IYL FD AD SUBW HL IY 12H FD D6 12 XOR IYU FD AC SUBW HL 1234H ED 96 34 12 XOR L AD SUBW HL BC ED 94 XORW IX 12H DD EE 12 SUBW HL DE ED 95 XORW IV 12H FD EE 12 SUBW HL HL ED 97 XORW 1234H ED AE 34 12 SUBW HL IX DD 97 XORW BC ED AC SUBW FD 97 XORW DE ED AD SUBW IX DD 97 XORW HL ED AF SUBW IY FD 97 XORW HL IX 12H DD EE 12 SWAP BC ED 0E XORW HL IY 12H FD EE 12 SWAP DE ED 1E XORW HL 1234H ED AE 34 12 SWAP HL ED 3E XORW HL BC ED AC SWAP IX DD 3E XORW HL DE ED AD SWAP IY FD 3E XORW HL HL ED AF TST HL ED 34 XORW DD AF TST 12H ED 64 12 XORW FD AF TST A ED 3C XORW IX DD AF TST ED 04 XORW IY FD AF TST C ED OC TST D ED 14 TST E ED 1C TST H ED 24 TST L ED 2 TSTIO 12H ED 74 12 XOR HL AE XOR IX 12H DD AE 12 XOR IY412H FD AE 12 XOR 12H EE 12 XOR A AF AHL AE XOR A IX 12H DD AE 12 XOR A IY 12H FD AE 12 XOR A 12H EE 12 XOR AA AF XOR A8 XOR AQ XOR AA XOR AE AB XOR AH AC XOR DD AD A IXU DD AC VU O 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc The information in this document is subject to change without notice Devices sold by Zilog
113. ALR CALR CALR CALR CALR CALR CALR 1234H 1 Z 1234H 123456 1234 12H C 123456H C 1234H C 12H M 123456H M 1234H M 12H NC 123456H NC 1234H NC 12H NZ 123456H NZ 1234H NZ 12H P 123456H P 1234H 12 123456 PE 1234H PE 12H 123456 1234 12 2 123456 Z 1234H Z 12H HL IX 12H IV 12H 12H A A HL 1 12 A IY 12H A 12H A D A E A H A IXL A IXU A IYL A IYU m g oO mn gt 2 Mode Object Code E4 34 12 DD BE 12 FD BE 12 34 12 34 12 34 12 34 12 34 12 34 12 34 12 34 12 12 12 12 12 12 12 12 12 Source Code CP DDIR DDIR DDIR DDIR DDIR DDIR DDIR DDIR DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC H HL IX IX IXU IYL IYU L HL IX 12H IV 12H 1234H HL IX 12H HL IY 12H HL 1234H HL BC HL DE HL HL HL IY IY IB IB LW IB W IW IW LW IW W LW w HL IX 12H IY 12H a EU CH Mode wv won Object Code DD FE 12 ED BE 34 DD FE 12 ED BE 34 12 12 ruwa meu DEC DEC DIVUW DIVUW DIVUW DIVUW DIVUW DIVUW DIVUW DIVUW DIVUW DIVUW DIVUW DIVUW DIVUW DIVUW DIVUW DJNZ DJNZ DJNZ El El escape escape escape escape escape escape esca
114. B 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 9E 56 34 9E 56 34 DE 56 34 DE 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 CB 56 34 SET SET SET SET SET SET SET SLA SLA SLAW SLAW SRA SRA SRAW SRAW SRL SRL SRLW SRLW SUB SUB SUBW SUBW XOR XOR XOR XOR XORW XORW XORW XORW 4 IY 123456H 5 IX 123456H 5 IY 123456H 6 IX 123456H 6 IY 123456H 7 IX 123456H 7 IY 123456H IX 123456H IY 123456H IX 123456H IY 123456H IX 123456H IY 123456H IX 123456H IY 123456H IX 123456H IY 123456H IX 123456H IY 123456H 1 123456 A IY 123456H HL IX 123456H HL IY 123456H IX 123456H IY 123456H 1 123456 A IY 123456H IX 123456H IY 123456H HL IX 123456H HL IY 123456H wv v CB 56 34 CB 56 34 CB 56 34 CB56 34 CB56 34 CB56 34 CB56 34 CB56 34 CB56 34 CB56 34 CB56 34 CB56 34 CB56 34 CB56 34 CB56 34 CB56 34 CB56 34 CB56 34 CB56 34 96 56 34 96 56 34 D6 56 34 D6 56 34 AE 56 34 AE 56 34 56 34 AE 56 34 EE 56 34 EE 56 34 EE 56 34 EE 56 34 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copi
115. BC 1234H DE 1234H HL 1234H HL LHL BC DE HL SP IX 12H IY 12H 1234H HL IX 12H HL IY 12H HL 1234H HL BC HL DE HL HL HL IX HL IY IX Fe Sale sssi xa Object Code ED 7B 34 31 34 12 ED DA 01 DD CA 01 DD DA 01 DA 01 ED 06 34 36 34 12 12 12 Source Code MULTW MULTW MULTW MULTW MULTW MULTW MULTW MULTW MULTW MULTW MULTW MULTW MULTW MULTW MULTW MULTW NEG NEG NEGW NEGW Mode IX 12H IY 12H 1234H HL IX 12H I HL IY 12H I HL 1234H HL BC HL DE HL IX HL IY IX HL HL IX 12H IY 12H 12H A A HL A IX 12H A IY 12H 1 A 12H AE A H A IXL A IXU A IYL A IYU IXL IXU IYL IYU L IX 12H 12 1234H BC Object Code DD B6 12 FD B6 12 DD B6 12 FD B6 12 DD F6 12 ED B6 34 92 92 34 12 92 34 12 12 meu ween v nne Source Code Mode Object Code Source Code Mode Object Code ORW DE ED B5 PUSH AF L F5 ORW HL ED B7 PUSH BC L 5 ORW HL IX 12H DD F6 12 PUSH DE L 05 ORW 12 FD F6 12 PUSH HL L Es ORW HL 1234H ED B6 34 12 PUSH IX L DD Es ORW HL BC ED B4 PUSH IY L FD E5 ORW HL DE ED B5 PUSH SR L ED C5 ORW ED B7 RES O HL CB 86 ORW DD B7 RES 0 IX 12H DD
116. BC BC DD OC LD IV IX FD 27 LD BC DE DD 0D LD SP HL F9 LD BC HL DD OF LD SP IX DD F9 LD BC BC ED 02 LD SP IY FD F9 ILUU Source Code Object Code LDCTL HL SR ED CO LDCTL SRHL ED C8 LDDRW ED F8 LDDW ED E8 LDIRW ED F0 LDIW ED LDW DD 57 LDW LHL DD 47 POP AF F1 POP BC C1 POP DE 01 POP HL E1 POP IX DD El POP IY FD El POP SR ED C1 PUSH AF F5 PUSH BC C5 PUSH DE D5 PUSH HL E5 PUSH IX DD E5 PUSH IY FD E5 PUSH SR ED C5 ween v 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc The information in this document is subject to change without notice Devices sold by Zilog Inc are covered by warranty and patent indemnification provisions appearing in Zilog Inc Terms and Conditions of Sale only ZILOG ING MAKES NO WARRANTY EXPRESS STATUTORY IMPLIED OR BY DESCRIPTION REGARDING THE INFORMA TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT ZILOG INC MAKES NO WARRANTY OF MER CHANTABILITY OR FITNESS FOR ANY PURPOSE Zilog Inc shall not be responsible for any errors that may appear in this document Zilog Inc makes no commitment to update or keep current the information contained in this document Zilog s products are not authorized for use as critical compo nents in life support device
117. BE RES 7 HL CB F4 SET 6H CB BF RES 7 CB F5 SET 61 CB CO SET 0B CB F6 SET 6 HL CB C1 SET OG F7 SET 6A C2 SET 0D CB F8 SET 78 CB C3 SET OE CB F9 SET 7 C4 SET CB FA SET 7 CB C5 SET OL FB SET 7 C6 SET DO HL FC SET 7H CB C7 SET FD SET 71 C8 SET 1B CB FE SET 7 HL CB C9 SET 1C CB FF SET 7 CB CA SET 1D CC 34 12 CALL 21234 X CB CB SET 1E CD 34 12 CALL 1234H X CB CC SET CE 12 ADD A 12H CB CD SET 11 CF RST 08H x CB CE SET 1 HL D0 RET NC SET 1 D1 POP DE L CB DO SET 2B D2 34 12 JP NC 1234H X CB 01 SET 2 D3 12 OUT 12H A CB D2 SET 2 D4 34 12 CALL NC 1234H X CB D3 SET 2E D5 PUSH DE L CB D4 SET 2H D6 12 SUB 12H CB D5 SET 21 D6 12 SUB A 12H CB D6 SET 2 HL D7 RST 10H X CB D7 SET 2 D8 RET 08 SET 38 D9 EXX CB D9 SET 3C DA 34 12 JP C 1234H X DA SET 30 DB 12 IN A 12H CB DB SET DC 34 12 CALL C 1234H X CB DC SET DD 01 LD L CB DD SET 3L DD 02 LD BC DE L CB DE SET 3 HL DD 03 LD IX BC L CB DF SET DD 07 LD L CB EO SET 4B DD 09 ADD IXBC X CB El SET 4 DD LD BC IX L CB E2 SET 4D DD OG LD L CB E3 SET 4E DD OD LD L E4 SET 4H DD OF LD BC HL L E5 SET 41 DD 10 34 12 DJNZ 1234H x CB E6 SET A HL DD 11 LD DE IX L E7 SET 4 DD 12 LD DE DE L CB E8 SET 58 DD 13 LD IX DE L E9 SET 5C DD 17 LD IX DE L CB EA SET 50 D
118. CB 59 12 12 46 46 4E 4E 56 56 5E 5E Source Code BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BTEST CALL CALL CALL CALL CALL CALL CALL CALL CALL 3 D 3 H 3 L 4 HL 4 IX 12H 4 IY 12H AA 4 B 4 C 4 D 4E 4H 41 5 HL 5 IX 12H 5 IV 12H 5 5 8 5 5 0 5 5 5 L 6 HL 6 IX 12H 6 IV 12H 6 A 6 B 6 C 6 D 6 E 6 H 6 L 7 HL 7 IX 12H 7 IV 12H 7 A 7 B du 7 0 7 7 H 7 L 1234H C 1234H M 1234H NC 1234H NZ 1234H P 1234H PE 1234H V 1234H PO 1234H Mode gt x gt x gt x gt x x gt x gt Object Code CB 5A 5B 5 50 CB 66 DD CB 12 FD CB 12 CB 67 CB 60 CB 61 CB 62 CB 63 CB 64 CB 65 CB 6E DD CB 12 FD CB 12 CB 6F CB 68 CB 69 6 6B 6 6D 76 DD CB 12 FD CB 12 CB 77 70 CB 71 CB 72 73 74 75 DD CB 12 FD CB 12 CB 7F CB 78 CB 79 CB 7A CB 7B CB 7 CB 7D ED CF CD 34 12 DC 34 12 FC 34 12 D4 34 12 C4 34 12 34 12 34 12 34 12 E4 34 12 66 66 6E 6E 76 76 7E 7E meu Source Code CALL CALL CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR C
119. CPU register the CPU control register the memory address on chip address and the external I O address The CPU register space is a superset of the Z80 CPU register set and consists of all of the registers in the CPU register file These CPU registers are used for data and address manipulation and are an extension ofthe Z80 CPU register set with four sets of this extended Z80 CPU register set present in the Z380 CPU Access to these registers is specified in the instruction with the active register set selected by bits in the Select Register SR in the CPU control register space 1 3 ZiLoG 1 2 2 Address Spaces Continued Each register set includes the primary registers A F B C D E H L IX and IY as well as the alternate registers A F HL IX and IY Also IX IX IY and registers are accessible astwobyte registers each named as IXU IXL IXU IXL IYU IYL IYU and IYL These byte registers can be paired B with C D with E H with L B with D with and H with L to form word registers and these word registers are extended to 32 bits with the z extension to the register This register extension is only accessible when using the register as a 32 bit register in the Long Word mode or when swapping between the most significant and least significant word of a 32 bit register using SWAP instructions Whenever an instruction refers to a word register the implici
120. CPU Interrupt response mode During the Interrupt acknowledge transaction the external I O device being acknowledged is expected to output a vector onto the upper portion of the data bus D15 D8 The Z380 MPU interprets the vector as an instruction opcode IEF1 and IEF2 are reset to logic 0 disabling all further maskable interrupt requests Note that unlike the other interrupt responses the PC is not automatically pushed onto the stack Typically a Restart instruction RST is used since the Restart opcode is only one byte long meaning that the interrupting peripheral needs to supply only one byte of information For this case itpushes the interrupted PC Program Counter value onto the stack and resumes execution at a fixed memory location Alter natively a 3 byte call to any location can be executed Note that a Trap occurs if an undefined opcode is supplied by the I O device as a vector 6 5 2 Interrupt Mode 1 Response for Maskable Interrupt INTO In Interrupt Mode 1 the Z380 CPU automatically executes a Restart to a fixed location 00000038H when an interrupt occurs An Interrupt acknowledge transaction is gener ated during which the data bus contents are ignored by the Z380 MPU The interrupted PC value is pushed onto the stack The size of the PC value pushed onto the stack is depends on Native one word or Extended mode two words in effect The IEF1 and IEF2 are reset to logic 0 so as to disable further maskable interru
121. CW ADCW ADCW ADCW ADCW ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD A HL 1 12 A IY 12H AE A H A IXL A IXU A IYL A IYU HL IX 12H HL IY 12H HL 1234H HL BC HL DE HL IX HL IY A IX 12H A IY 12H A 12H A 12H AE A H A IXL A IXU A IYL A IYU HL 1234H HL BC HL DE HL HL Mode gt x Object Code 8E DD 8E 12 FD 8E 12 8F 88 89 8A 8B 8C DD 8D DD 8 FD 8D FD 8C 8D ED 4A ED 5A ED 6A ED 7A DD CE 12 FD CE 12 ED 8E 34 ED 8C ED 8D ED 8F DD CE 12 FD 12 ED 8 34 ED 8C ED 8D ED 8F DD 8F FD 8F DD 8F FD 8F 86 DD 86 12 FD 86 12 C6 12 CE 12 87 80 81 82 83 84 DD 85 DD 84 FD 85 FD 84 85 ED 34 09 19 29 12 12 12 Source Code ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND HL SP IX BC IX DE IX SP IY DE IY SP SP 1234H IX 12H IY 12H 1234H HL IX 12H HL IY 12H HL 1234H HL BC HL DE HL IX HL IY HL IX 12H IY 12H 12H A A HL A IX 12H A IY 12H A 12H A D A
122. D 18 34 12 JR 1234H X CB EB SET 5E DD 19 ADD IXDE x CB EC SET 5H DD 1B LD DE IX L ED SET 51 DD 1C LD DE BC L EE SET 5 HL DD 1D LD DE DE L CB EF SET DD 1F LD DE HL L CB Fo SET 6B DD 20 34 12 JR NZ 1234H X CB F1 SET 6 DD 21 34 12 LD IX 1234H 1 L CB F2 SET 6 D DD 22 34 12 LD 1234H IX I 34 34 34 12 12 34 34 Source Code ING INCW ING DEG IX IX IXU IXU IXU 12H IX IY Z 1234H IX 1234H NC 1234H HL IX HL DE IX HL IX 12H IX 12H IX 12H 34H IX HL C 1234H IX SP HL IX HL BC HL DE IX HL HL C BC B IXU B IXL B IX 12H LHL LHL C IXU C IXL C IX 12H DE C C DE D IXU D IXL D IX 12H EIXL E IYL E IX 12H IXU B IXU C IXU D Mode Object Code DD A6 12 DD A6 12 Source Code Mode LD IXU E LD IXU IXU LD IXU IXL LD H IX 12H LD LD IXL B LD IXL C LD IXL D LD IXL E LD IXL IXU LD LD L IX 12H LD IXL A LD IX 12H B LD IX 12H C LD IX 12H D LD 1 12 LD IX 12H H LD IX 12H L LD 1 12 INW HL C OUTW C HL LD LD A IXL LD A IX 12H ADD ADD A IXL ADD 1 12 ADDW HL IX ADDW IX A IXU ADC A IXL ADC IX 12H ADOW ADCW SUB SUB A IXL SUB IX 12H SUBW SUBW IX SBC
123. DC 8297 03 2380 USER S MANUAL Bits within byte 16 bit word at address n Least Significant Byte Address n Most Significant Byte Address n 1 32 bit word at address n D7 0 Least Significant Byte Address n D15 8 Address n 1 D23 16 Address n 2 D31 24 Most Significant Byte Address n 3 Memory addresses Even address 0 0 Odd address 0 1 Least Significant Byte Most Significant Byte 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 2 2 Bit Byte Ordering Conventions 2 5 7106 2 5 EXTERNAL ADDRESS SPACE External I O address space is 4 Gbytes in size and External addresses are generated by instructions except those reserved for on chip address space accesses It Table 2 1 I O Addressing Options 2380 USER S MANUAL can take variety of forms as shown in Table 2 1 external I O read or write is always one transaction regard less of the bus size and the type of I O instruction Address Bus I O Instruction A31 A24 A23 A16 A15 A8 A7 A0 IN A n 00000000 00000000 A7 A0 n IN dst C BC31 B24 BC23 B16 BC15 B8 7 0 dst mn 00000000 00000000 n DDIR IB INA W dst Imn 00000000 n DDIR IW INA W dst kimn k n Block Input BC31 B24 BC23 B16 BC15 B8 7 0 OUT n A 00000000 00000000 A7 A0 n OUT C dst BC31 B24 BC23 B16 BC15 B8 7 0 OUTA W mn dst 00000000 00000000 m n DDIR IB OUTA W Imn dst 00000000 n
124. DE and HL registers are then decremented by two or four thus moving the pointers to the preceeding words in the array The BC register used as byte counter is then decremented by two or four Both DE and HL should be even to allow word transfers on the bus BC must be even transferring an even number of bytes or the operation is undefined S Unaffected 7 Unaffected H Cleared V Set if the result of decrementing BC is not equal to zero cleared otherwise N Cleared Unaffected Execute Syntax Instruction Format Time Note LDDW 11101101 11101000 3 r w L 5 97 7106 LDDR LOAD DECREMENT AND REPEAT BYTE Operation Flags Addressing Mode 5 98 LDDR repeat until BC 0 begin DE HL DE DE 1 HL HL 1 15 0 lt BC 15 0 1 end This instruction is used for block transfers of strings of data The bytes of data at the location addressed by the HL register are loaded into memory starting at the location addressed by the DEregister The number of bytes moved is determined by the contents ofthe BC register If the BC register contains zero when this instruction is executed 65 536 bytes are transferred The effect of decrementing the pointers during the transfer is important if the source and destination strings overlap with the source string starting at a lower memory address Placing the pointers at the highest address of the strings and decrementing the pointers ensures that the source string
125. ES 1 HL CB 59 BIT 3 CB 8F RES 1 A 5A BIT 90 RES 2B CB 5B BIT CB 91 RES 2 CB 5C BIT 3H CB 92 RES 2 CB 5D BIT 3L 93 RES 2E CB 5E BIT 3 HL CB 94 RES 2H CB 5F BIT CB 95 RES 21 CB 60 BIT 48 CB 96 RES gt 2 HL CB 61 BIT 4 CB 97 RES 2A CB 62 BIT 4 CB 98 RES 3B CB 63 BIT 4E CB 99 RES 3 CB 64 BIT 4H CB 9A RES 3D CB 65 BIT 41 CB 9B RES 3E CB 66 BIT 4 HL CB 9C RES 3H CB 67 BIT 4A CB 9D RES 3L CB 68 BIT 5B CB 9E RES 3 HL CB 69 BIT 5 CB 9F RES 3A CB 6A BIT 5D CB 0 RES 4B CB 6B BIT 5E CB 1 RES 4C CB 6C BIT 5H CB A2 RES 4D CB 6D BIT 51 CB A3 RES 4E CB 6E BIT 5 HL CB A4 RES 4H CB 6F BIT 5A CB A5 RES 4L CB 70 BIT 6B CB A6 RES 4 HL 71 BIT 6C CB A7 RES 4A CB 72 BIT 6D CB 8 RES 5B CB 73 BIT 6E CB A9 RES 5C CB 74 BIT 6H CB AA RES 5D CB 75 BIT 61 CB AB RES 5 CB 76 BIT 6 HL CB AC RES 5H CB 77 BIT 6A CB AD RES 51 CB 78 BIT 7B CB AE RES 5 HL CB 79 BIT 7 CB AF RES 5A CB 7A BIT 7 CB BO RES 68 CB 7B BIT 7E CB B1 RES 6 C CB 7C BIT 7H CB B2 RES 6D CB 7D BIT 7L CB B3 RES 6E CB 7E BIT 7 HL CB B4 RES CB 7F BIT 7 CB B5 RES 61 CB 80 RES 0B CB B6 RES 6 HL CB 81 RES OC CB B7 RES 6 CB 82 RES CB B8 RES 7B CB 83 RES 9 RES 7 84 RES 0H RES 7 0 85 RES OL CB BB RES 7E CB 86 RES _0 HL BC RES 7H vom nne Object Code Source Code Mode Object Code Source Code Mode CB BD RES 71 CB F3 SET 6 E
126. HL E IX 12H E IY 12H E 12H EC ED EE EH EL E IXL E IYU E IYL E IYU H HL H IX 12H H IY 12H H 12H H A HB H D HL SP 12H HL 1234H HL BC HL DE HL HL HL HL IX HL IY LA LHL IX 1234H IX SP 12H IX 1234H IX BC IX DE Ue 2 FETERE ETE EF FETERE ER TE Object Code DD 1B FD 1B DD 5E 12 FD 5E 12 1 12 DD 66 12 FD 66 12 2A 34 12 ED 6B 34 DD 2A 34 12 00 21 34 12 33 31 12 23 12 Source Code IX HL IX IY IXL 12H IXL IXL B IXL C IXL D IXL E IXL IXL IXL XU IXU A IXU B IXU C IXU D IXU E IXU IXL IXU IXU IY 1234H IY BC IY DE IY HL IY IX 12H IY SP 12H IY 1234H IY BC IY DE IY HL IYL 12H IYL B IYL C IYL D IYL IYL IYL IYU IYU 12H IYU A IYU B IYU C IYU D IYU E IYU IYL IYU IYU L HL L X 12H L IY 12H L 12H LB LC L D LE Mode wn v nne Object Code FD 2A 34 DD CB 12 FD 21 34 DD 6E 12 FD 6E 12 23 12 meu Source Code MLT MTEST MULTUW MULTUW MULTUW MULTUW MULTUW MULTUW MULTUW MULTUW MULTUW MULTUW MULTUW MULTUW MULTUW MULTUW MULTUW MULTUW LL SP 1234H SP 1234H SP HL SP IX SP IY A DSR A XSR A YSR DSR 01H DSR A HL SR SR 01H SR A SR HL XSR 01H XSR A YSR 01H YSR A
127. IM X Operation 15 0 HL 15 0 AND src 15 0 Alogical AND operation is performed between the corresponding bits ofthe source operand and the HL register and the result is stored in the HL register A 1 is stored wherever the corresponding bits in the two operands are both 1s otherwise a 0 is stored The contents of the source are unaffected Flags S Set if the most significant bit of the result is set cleared otherwise Z Setif all bits of the result are zero cleared otherwise H Set P Setifthe parity is even cleared otherwise N Cleared C Cleared Addressing Mode Syntax Instruction Format R ANDW HL R 11101101 101001rr RX ANDW HL RX 11y11101 10100111 IM ANDW HL nn 1110110110100110 n low n high X ANDW 11y11101 11100110 d Field Encodings rr 00for BC 01 for DE 11 for HL y Ofor IX 1 for IY 5 28 Execute Time 2 2 2 4 r 2380 USER S MANUAL Note DC 8297 03 2380 71 06 USER S MANUAL BIT BIT TEST BITb dst dst R IR X Operation Z lt NOT dst b The specified bit b within the destination operand is tested and the Zero flag is set to 1 if the specified bit is 0 otherwise the Zero flag is cleared to 0 The contents of the destination are unaffected The bit to be tested is specified by a 3 bit field in the instruction this field contains the binary encoding for the bit number to be tested The bit number b must be between 0 and 7 Flags S Unaffected
128. IRW 11101101 11110011 2 0 2380 User s MANUAL DC 8297 03 2380 71 06 USER S MANUAL OUT OUTPUT BYTE OUT C src src R IM Operation C src The byte of data from the source is loaded into the selected peripheral During the transaction the contents of the 32 bit BC register are placed on the address bus Flags 6 Unaffected Z Unaffected H Unaffected V Unaffected Unaffected C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R OUT C R 11101101 01 r 001 3 0 IM OUT C n 11101101 01110001 n 3 0 Field Encodings per convention DC 8297 03 5 121 2380 7106 USER S MANUAL OUTW OUTPUT WORD OUTW C src src IM Operation lt sre 15 0 The word of data from the source is loaded into the selected peripheral During the transaction the contents of the 32 bit BC register are placed on the address bus Flags S Unaffected 7 Unaffected H Unaffected V Unaffected Unaffected Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R OUTW 11011101 Otrrr 001 2 0 IM OUTW C nn 11111101 01111001 n low n high 2 0 Field Encodings rrr 000 for BC 010 for DE 111 for HL 5 122 DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL OUT OUTPUT ACCUMULATOR OUT lt The byte of data from the accumulator is loaded into the selected p
129. ITECTURE The 2380 CPU is a binary compatible extension of the Z80 CPU and the Z180 CPU architecture High throughput rates are achieved by a high clock rate high bus band width and instruction fetch execute overlap Communi cating to the external world through an 8 bit or 16 bit data bus the Z380 CPU is a full 32 bit machine internally with a 32 bit ALU and 32 bit registers 1 2 1 Modes of Operation To maintain compatibility with the 780 7180 CPU while having the capability to manipulate 4 Gbytes of memory address range the 7380 CPU has two bits in the Select Register SR to control the modes of operation One bit controls the address manipulation mode Native mode or Extended mode and the other bit controls the data ma nipulation mode Word mode or Long Word mode In result the Z380 CPU has four modes of operation On reset the Z380 CPU is in Native Word mode which is compatible to the Z80 Z180 s operation mode For details onthis subject refer to Chapter 3 Native Extended Mode Word Long Word Mode of Operation and Decoder Direc tive Instructions 1 2 1 1 Native Mode and Extended Mode The Z380 CPU can operate in either Native or Extended mode as controlled by a bit in the Select Register SR In Native mode the Reset configuration all address ma nipulations are performed modulo 65536 2 9 In this mode the Program Counter PC only increments across 16 bits all address manipulation instructions increment
130. IX registers and IYU IYU IYL and IYL for the IY and IY registers Selection of primary or auxiliary Index registers can be made by EXXX EXXY or EXALL instructions or program ming of SR Uponreset the primary registers in register set 0 is active Changing register sets is a simple matter of an LDCTL instruction to program SR 2 2 3 Interrupt Register The Interrupt register 1 is used in interrupt modes 2 and 3 for INTO to generate a 32 bit indirect address to an interrupt service routine The I register supplies the upper 24 or 16 bits of the indirect address and the interrupting peripheral supplies the lower eight or 16 bits In Assigned Vectors mode for INT3 INT1 the upper 16 bits of the vector are supplied by the register bits 15 9 are supplied from the Assigned Vector Base register and bits 8 0 are the assigned vector unique to each of INT3 INT1 2 2 4 Program Counter The Program Counter PC is used to sequence through instructions in the currently executing program and to generate relative addresses The PC contains the 32 bit address of the current instruction being fetched from memory In Native mode the PC is effectively only 16 bits long since the upper word PC31 PC16 of the PC is forced to zero and when carried from bit 15to bit 16 Lower word PC15 PCO to Upper word PC31 PC16 are inhib ited in this mode In Extended mode the PC is allowed to increment across all 32 bits 2 2 5 R Reg
131. L SETC SET CONTROL BIT SETC mode mode LCK LW XM Operation if mode LCK then begin SR 1 1 end else if mode LW then begin SR 6 lt 1 end else begin SR 7 1 end When setting Lock mode LCK the LCK bit bit 1 in the Select Register SR is set to 1 disabling external bus requests Note that bus requests are not disabled until after this instruction has been executed and that one or more of the succeeding instructions may also have been fetched for decoding before this instruction has been executed When setting Long Word mode LW the LW bit bit 6 in the SRis set to 1 selecting 32 bit words When using 32 bit words all word load instructions transfer 32 bits When setting Extended mode XM the XM bit bit 7 inthe SRis setto 1 selecting addresses modulo 4 294 967 296 32 bits as opposed to addresses modulo 65536 16 bits in Native mode In Extended mode CALL and RETurn instructions save and restore 32 bit PC values to and from the stack and the PC pushed to the stack in response to an interrupt is 32 bits In Extended mode address manipulation instructions such as INCrement DECrement ADD and Jump Relative JR employ 32 bit addresses Note that it is not possible to exit from Extended mode except via reset Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Flags Addressing Execute Mode Syntax Instruction Format Time Note SETC mode 11 1101 11110111 4 Field Encodings m
132. L IY L FD 31 JP P1234H X F2 34 12 LD HL L 75 JP PE1234H X EA 34 12 LD IX 12H 34H DD 36 12 34 JP PO 1234H X 2 34 12 LD IX 12H A 1 DD 77 12 JP S 1234H X FA 34 12 LD IX 12H B 1 DD 70 12 JP Vj1234H X E2 34 12 LD IX 12H BC L DD CB 12 JP Z1234H X CA 34 12 LD IX 12H C DD 71 12 JR 123456H X FD 18 56 34 12 LD IX 12H D 1 DD 72 12 JR 1234H X DD 18 34 12 LD IX 12H E 1 DD 73 12 JR 12H X 18 12 LD IX 12H DE L DD CB 12 1B JR C 123456H x FD 38 56 34 12 LD IX 12H H 1 DD 74 12 JR C 1234H X DD 38 34 12 LD IX 12H HL L DD CB 12 3B meu A I A IXL A IXU A IYL A IYU B HL B IX 12H B IY 12H 12 B B B C B D BH B IXL B IXU B IYL B IYU B L Object Code 5F 46 46 12 12 12 12 12 2B 0B 1B Source Code C 1234H C BC C DE C HL C IX 12H C IY 12H BC 1234H BC BC BC DE BC HL BC IX C HL C IX 12H C IY 12H C 12H GC C H C IXL C IXU C IYL C IYU C L D HL D IX 12H D IY 12H D 12H D A D B D C D D D E D H D IXL D IXU D IYL D IYU DI E 1234H E BC E DE E HL E IX 12H E IY 12H BER OH DE 1234H DE BC DE DE DE HL Mode E FET TELE AE ER Object Code 4B 34 12 12 12 12 12 34 03 01 13 11 meu Source Code DE IX DEY E
133. LOG INC MAKES NO WARRANTY OF MER CHANTABILITY OR FITNESS FOR ANY PURPOSE Zilog Inc shall not be responsible for any errors that may appear in this document Zilog Inc makes no commitment to update or keep current the information contained in this document Zilog s products are not authorized for use as critical compo nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use Life support devices or systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 Telex 910 338 7621 FAX 408 370 8056 Internet http www zilog com DC 8297 03 2 7 N lt 2 1 INTRODUCTION The Z380 CPU supports five address spaces correspond ing to the different types of locations that can be ad dressed and the method by which the logical addresses are formed These five address spaces are CPU Register Space This consists of all the register addresses in the CPU register file m CPU Control Register Space This consists of the Select Register SR m Memory Address Space This consists of the addresses
134. MANUAL INC INCREMENT BYTE INC dst dst RX IR X Operation dst dst 1 The destination operand is incremented by one and the sum is stored in the destination Two s complement addition is performed Flags S Set if the result is negative cleared otherwise Z Set if the result is zero cleared otherwise H Setifthere is a carry from bit 3 of the result cleared otherwise V Set if arithmetic overflow occurs that is if the destination was 7FH cleared otherwise N Cleared C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R INC R 00 r 100 note RX INC RX 11y11101 0010w100 2 IR INC HL 00110100 2 r W X ING XY d 11y11101 00110100 d 4 r w Field Encodings r per convention y O for IX 1 for IY w Oforhigh byte 1 for low byte Note 2 for accumulator 3 for any other register 5 70 DC 8297 03 71106 2380 USER S MANUAL INC W INCREMENT WORD dst dst R RX Operation if XM then begin dst 31 0 lt dst 31 0 1 end else begin dst 15 0 lt dst 15 0 1 end The destination operand is incremented by one and the sum is stored in the destination Two s complement addition is performed Note that the length of the operand is controlled by the Extended Native mode selection which is consistent with the manipulation of an address by the instruction Flags S Unaffected 7 Unaffected H Unaffected V Unaffected Unaffected
135. N Cleared Setifthe bit rotated from bit 0 was 1 cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R RRC R 11001011 00001 r 2 IR RRC HL 11001011 00001110 2 r X RRC XY d 11y11101 11001011 d 00001110 4 r l Field Encodings r per convention y O for IX 1 for IY 5 154 DC 8297 03 2380 7106 USER S MANUAL RRCW ROTATE RIGHT CIRCULAR WORD RRCW dst dst R RX IR X Operation tmp lt dst C lt dst 0 dst 15 0 dst n lt tmp n 1 for n 0 to 14 The contents of the destination operand are rotated right one bit position Bit 0 of the destination operand is moved to the most significant bit position and also replaces the Carry flag Flags 6 Setif the most significant bit of the result is set cleared otherwise Z Setifthe result is zero cleared otherwise H Cleared P Setif parity of the result is even cleared otherwise N Cleared Setif the bit rotated from bit 0 was a 1 cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R RRCW R 11101101 11001011 000010rr 2 RX RRCW RX 11101101 11001011 00001 10y 2 IR RRCW HL 11101101 11001011 00001010 2 r X RRCW XY d 11y11101 11001011 d 00001010 4 r Field Encodings rr 00 for BC 01 for DE 11 for HL y for IX 1 for IY DC 8297 03 5 155 2380 7106 USER S MANUAL RRCA ROTATE RIGHT CIRCULAR ACCUMULATOR RRCA Operation tmp A lt 0 A 7 lt
136. N A N A N A N A N A 2X External I O Read 9 11 9 11 N A N A N A N A N A N A 2X External Write 1 3 1 3 N A N A N A N A N A N A 4X External I O Read 17 21 17 21 N A N A N A N A N A N A External Write 1 5 1 5 N A N A N A N A N A N A 6X External I O Read 25 31 25 31 N A N A N A N A N A N A 6X External Write 1 7 1 7 N A N A N A N A N A N A 8X External I O Read 33 41 33 41 N A N A N A N A N A N A 8X External Write 1 9 1 9 N A N A N A N A N A N A Note Units are in Clocks N A is not applicable for that particular transaction DC 8297 03 5 19 2380 7106 USER S MANUAL ADC ADD WITH CARRY BYTE ADC src RX IM IR X Operation A src C The source operand together with the Carry flag is added to the accumulator and the sum is stored in the accumulator The contents of the source is unaffected Two s complement addition is performed Flags S Set if the result is negative cleared otherwise Z the result is zero cleared otherwise Setif there is a carry from bit of the result cleared otherwise V Setif arithmetic overflow occurs that is if both operands cleared otherwise Cleared C Setifthere is a carry from the most significant bit of the result cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R A R 10001 r 2 RX ADC A RX 11y11101 1000110w 2 IM ADC A n 11001110 n 2 IR ADC A HL 10001110 2 r X ADC 11y11101
137. NIRW repeat until BC 0 begin HL DE 15 0 lt BC 15 0 1 HL lt HL 2 This instruction is used for block input of strings of data The string of input data from the selected peripheral is loaded into memory at consecutive addresses starting with the location addressed by the HL register and increasing During the I O transaction the 32 bit DE register is placed on the address bus First the word of data from the selected peripheral is loaded into the memory location addressed by the HL register Then the BC register used as counter is decremented by one The HL register is then incremented by two thus moving the pointer to the next destination for the input If the result of decrementing the BC register is 0 the instruction is terminated otherwise the sequence is repeated If the BC register contains 0 at the start of the execution of this instruction 65536 bytes are input This instruction can be interrupted after each execution of the basic operation The Program Counter value atthe start of this instruction is saved before the interrupt request is accepted so that the instruction can be properly resumed S Unaffected Z Set if the result of decrementing BC is zero cleared otherwise H Unaffected V Unaffected Set Unaffected Execute Syntax Instruction Format Time Note INIRW 11101101 11110010 n X 2 i W 5 79 2380 7106 USER S MANUAL JP JUMP JP cc dst dst IR DA Operatio
138. NUAL OUTI OUTPUT AND INCREMENT BYTE OUTI lt B 1 HL HL HL 1 This instruction is used for block output of strings of data During the I O transaction the 32 bit BC register is placed on the address bus Note that the B register contains the loop count for this instruction so that A15 A8 are not useable as part of a fixed port address The decremented B register is used in the address First the B register used as a counter is decremented by one The byte of data from the memory location addressed by the HL register is loaded into the selected peripheral The HL register is then incremented by one thus moving the pointer to the next source for the output S Unaffected Z Setifthe result of decrementing B is zero cleared otherwise H Unaffected V Unaffected N Set C Unaffected Execute Syntax Instruction Format Time Note OUTI 11101101 10100011 2 1 0 5 129 7106 OUTIW 2380 USER S MANUAL OUTPUT AND INCREMENT WORD Operation Flags Addressing Mode 5 130 OUTIW BC 15 0 lt BC 15 0 1 DE HL HL HL 2 This instruction is used for block output of strings of data During the I O transaction the 32 bit DE register is placed on the address bus First the BC register used as a counter is decremented by one The word of data from the memory location addressed by the HL register is loaded into the selected peripheral The HL register is then incremented by two thus mo
139. PW HL RX 11y11101 10111111 2 CPW HL nn 11101101 10111110 n low n high 2 CPW HL XY d 11y11101 11111110 d 4 r rr 00 for BC 01 for DE 11 for HL y 0 for IX 1 for IY 5 35 7106 CPD COMPARE AND DECREMENT BYTE Operation Flags Addressing Mode 5 36 CPD A HL if XM then begin HL 31 0 lt HL 31 0 1 end else begin HL 15 0 lt HL 15 0 1 end BC 15 0 lt 15 0 1 This instruction is used for searching strings of byte data The byte of data at the location addressed by the HL register is compared with the contents of the accumulator and the Sign and Zero flags are set to reflect the result of the comparison The contents of the accumulator and the memory bytes are unaffected Two s complement subtraction is performed Next the HL register is decremented by one thus moving the pointer to the previous element in the string The BC register used as a counter is then decremented by one S Set if the result is negative cleared otherwise 2 Set ifthe result is zero indicating that the contents of the accumulator and the memory byte are equal cleared otherwise Setif there is a borrow from bit 4 of the result cleared otherwise V Set if the result of decrementing BC is not equal to zero cleared otherwise Set Unaffected Execute Syntax Instruction Format Time Note CPD 11101101 10101001 3 r X 2380 User s MANUAL DC 8297 03 71106 Operation Flags
140. SUB SUB SUBW HL HL B IYU B IYL B IY 12H C IYU C IYL C IY 12H D IYU D IYL D IY 12H E IYU EIYL E IY 12H IYU B IYU C IYU D IYU E IYU IYU IYU IYL H IY 12H IYU A IYL B IYL C IYL D IYL IYU IYL IYL L IY 12H IY 12H A C 1234H A IYU A IYL A IY 12H A IYU A IYL A IY 12H HL IY A IYU A IYL A IY 12H A IYU A IYL A IY 12H Object Code 12 6 12 6 12 12 12 B6 12 B6 12 12 12 4 56 34 12 C6 12 C6 12 CB 12 CB 12 CB 12 CB 12 CB 12 CB 12 CB 12 CB 12 CB 12 Source Code SUBW SBC SBC SBC SBCW SBCW AND AND AND AND AND AND ANDW ANDW XOR XOR XOR A IYU A IYL A IY 12H HL IY A IYU IYU A IYL IYL IY 12H A IY 12H A IYU IYU A IYL IYL IY 12H A IY 12H A IYU IYU A IYL IYL IY 12H A IY 12H A IYU IYU A IYL IYL IY 12H A IY 12H NZ 123456H IY 12H HL IY 12H IY 12H BC IY 12H IY 12H IY 12H IY 12H BC IY 12H IY 12H DE IY 12H IY 12H Mode Object Code FD CB 12 1A FD CB 12 1B 12 1 12 21 12 22 12 23 12 26 FD 12 29 FD 12 2A 12 2 FD 12 2E 12 33 12 12 12 12 46 12 4 1
141. Syntax Instruction Format Time Note R SRAW R 11101101 11001011 001010rr 2 RX SRAW RX 11101101 11001011 0010110y 2 IR SRAW HL 11101101 11001011 00101010 2 r X SRAW XY d 11 11101 11001011 d 00101010 4 r Field Encodings rr 00for BC 01 for DE 11 for HL y Ofor IX 1 for IY DC 8297 03 5 169 2380 7106 USER S MANUAL SRL SHIFT RIGHT LOGICAL BYTE SRL dst dst R IR X Operation tmp lt dst C lt dst 0 dst 7 lt 0 dst n lt tmp n 1 forn 0to6 The contents of the destination operand are shifted right one bit position Bit 0 of the destination operand is moved to the Carry flag and zero is shifted into bit 7 of the destination Flags S Cleared Z Set if the result is zero cleared otherwise Cleared P Set if parity of the result is even cleared otherwise N Cleared Setif the bit shifted from bit 0 was a 1 cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R SRL 11001011 00111 r 2 IR SRL HL 11001011 00111110 2 X SRL XY d 11y11101 11001011 d 00111110 4 r Field Encodings r per convention y OforIX 1 for IY 5 170 DC 8297 03 2380 71 06 USER S MANUAL SRLW SHIFT RIGHT LOGICAL WORD SRLW dst dst R RX IR X Operation tmp lt dst C lt dst 0 dst 15 0 dst n lt tmp n 1 for n 0 to 14 The contents of the destination operand are shifted right one bit position Bit O of the destination operand is moved to the Carr
142. T SET SET SET SET SET SET SET SET SET SET SETC SETC SETC SLA SLA SLA SLA SLA SLA SLA SLA SLA SLA SLAW SLAW SLAW SLAW SLAW 4 B 4 C 4 D 4E 4H 41 5 HL 5 IX 12H 5 IV 12H 5 5 8 5 5 0 5 5 5 L 6 HL 6 IX 12H 6 IY 12H 6 A 6 B 6 C 6 D 6 E 6 H 6 L 7 HL 7 IX 12H 7 IV 12H 7 A 7 B 7 C 7 D 7E 7 H IY 12H BC DE Mode Object Code E1 12 12 12 12 12 12 12 12 EE EE F6 F6 FE FE 26 26 22 22 Source Code SLAW SLAW SLAW SLP SRA SRA SRA SRA SRA SRA SRA SRA SRA SRA SRAW SRAW SRAW SRAW SRAW SRAW SRAW SRAW SRL SRL SRL SRL SRL SRL SRL SRL SRL SRL SRLW SRLW SRLW SRLW SRLW SRLW SRLW SRLW SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB Mode HL IX IY HL IX 12H IY 12H HL IX 12H IV 12H BC a IV 12H B C D E H L HL A IX 12H A IY 12H 12H A IXL A IXU A IYL Object Code 23 24 25 12 12 12 12 2E 2E 2 2 wn v nne Source Code Mode Object Code Source Code Mode Object Code SUB A IYU FD 94 XOR FD AD SUB AL 95 SUB XOR AJYU FD AC HL 1234H X ED D6 34 12 XOR A L AD SUB SPj234H X ED 92 34 12 XOR B A8 SUBW IX 12H DD D6 12 XOR C A9 SUBW 12 FD D6 12 XOR D
143. THMETIC BYTE SRA dst dst R IR X Operation tmp lt dst C lt dst 0 dst 7 lt tmp 7 dst n lt tmp n 1 forn 0to6 The contents of the destination operand are shifted right one bit position Bit O of the destination operand is moved to the Carry flag and bit 7 remains unchanged Flags S Set if the result is negative cleared otherwise Z Setifthe result is zero cleared otherwise H Cleared P Setif parity of the result is even cleared otherwise N Cleared Set if the bit shifted from bit 0 was 1 cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R SRA R 11001011 00101 r 2 IR SRA HL 11001011 00101110 2 r X SRA XY d 11y11101 11001011 d 00101110 4 r Field Encodings r per convention y O for IX 1 for IY 5 168 DC 8297 03 2380 71 06 USER S MANUAL SRAW SHIFT RIGHT ARITHMETIC WORD SRAW dst dst R RX IR X Operation tmp lt dst C lt dst 0 dst 15 tmp 15 dst n lt tmp n 1 for n Oto 14 The contents of the destination operand are shifted right one bit position Bit O of the destination operand is moved to the Carry flag and the most significant bit remains unchanged Flags S Set if the result is negative cleared otherwise Z Setifthe result is zero cleared otherwise H Cleared P Setif parity of the result is even cleared otherwise N Cleared Set if the bit shifted from bit 0 was 1 cleared otherwise Addressing Execute Mode
144. Table 6 4 If the Z380 CPU is in Extended mode all four bytes of the data stored in the Assigned vector location will be used as a new PC value If the 2380 CPU is in Native mode only two bytes of data from the LS Byte will be used as anew PC value Table 6 4 Assigned Interrupt Vectors Assigned Interrupt Interrupt Source Vector INT1 00H INT2 04H INT3 08H ate Interrupt under service condition clears The Z380 MPU reproduces the opcode fetch transactions on the 1 O bus when the RETI instruction is executed Note thatthe Z380 MPU outputs the RETI opcodes onto both portions of the data bus D15 D8 and D7 D0 in the transactions DC 8297 03 71106 2380 USER S MANUAL O 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc The information in this document is subject to change without notice Devices sold by Zilog Inc are covered by warranty and patent indemnification provisions appearing in Zilog Inc Terms and Conditions of Sale only ZILOG ING MAKES NO WARRANTY EXPRESS STATUTORY IMPLIED OR BY DESCRIPTION REGARDING THE INFORMA TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT ZILOG INC MAKES NO WARRANTY OF MER CHANTABILITY OR FITNESS FOR ANY PURPOSE Zilog Inc shall not be responsible for any errors that ma
145. Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R INC W 00110011 2 X RX INC W RX 11y11101 00100011 2 X Field Encodings rr 00 for BC 01 for DE 10 for HL 11 for SP y OforIX 1 for IY DC 8297 03 5 71 7106 IND 2380 USER S MANUAL INPUT AND DECREMENT BYTE Operation Flags Addressing Mode 5 72 IND HL 1 HL amp HL 1 This instruction is used for block input of strings of data During the I O transaction the 32 bit BC register is placed on the address bus Note that the B register contains the loop count for this instruction so that A15 A8 are not useable as part of a fixed port address First the byte of data from the selected peripheral is loaded into the memory location addressed by the HL register Then the B register used as a counter is decremented by one The HL register is then decremented by one thus moving the pointer to the next destination for the input S Unaffected Z Setifthe result of decrementing B is zero cleared otherwise H Unaffected V Unaffected N Set C Unaffected Execute Syntax Instruction Format Time Note IND 11101101 10101010 2 i W DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL INDW INPUT AND DECREMENT WORD INDW HL DE 15 0 15 0 1 HL lt HL 2 This instruction is used for block input of strings of data During the transa
146. W IY 12H RRW BC RRW RRW HL RRW IX RRW IY RST RST 08H RST 10H RST 18H RST 20H RST 28H RST 30H RST 38H SBC A HL SBC A IX 12H SBC A IY 12H SBC A 12H SBC SBC SBC AC SBC SBC SBC AH SBC SBC SBC AJYL SBC A IYU SBC AL SBC HL BC SBC HL DE SBC HLHL SBC HL SP SBCW 1 12 SBCW IV 12H SBCW 1234H SBCW BC SBCW DE SBCW HL SBCW HL IX 12H Mode Object Code OC CB OD DD CB 12 OA FD CB 12 OA DD CB 12 1A FD CB 12 1A DD 9 12 FD 9 12 DE 12 DD DE 12 ED 9E 34 12 DD DE 12 Source Code SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SCF SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET HL IY 12H HL 1234H HL BC HL DE HL HL HL IX HL IY IX 0 HL 0 IX 12H 0 IY 12H 0 A 0 B 0 C 3 HL 3 IX 12H 3 IY 12H 3 A 3 B 3 C 3 D 3 H 3 L 4 HL 4 IX 12H 4 IY 12H 4 A vvn v nne Object Code DD CB 12 FD CB 12 DD CB 12 FD CB 12 DD CB 12 FD CB 12 DD CB 12 FD CB 12 DD CB 12 FD CB 12 C6 C6 CE CE D6 D6 DE DE E6 E6 Source Code SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SE
147. X 11y11101 1001010w 2 IM SUB A n 11010110 n 2 IR SUB A HL 10010110 2 r X SUB A XY d 11 11101 10010110 d 4 r Field Encodings r per convention y O for IX 1 for IY w Oforhigh byte 1 for low byte 5 172 DC 8297 03 2380 7106 USER S MANUAL SUB SUBTRACT WORD SUB HL src src DA Operation if XM then begin HL 31 0 lt HL 31 0 src 31 0 end else begin HL 15 0 lt HL 15 0 src 15 0 end The source operand is subtracted from the HL register and the difference is stored in the HL register The contents of the source are unaffected Two s complement subtraction is performed Note that the length of the operand is controlled by the Extended Native mode selection which is consistent with the manipulation of an address by the instruction Flags S Unaffected 2 Unaffected Setif there is a borrow from bit 12 of the result cleared otherwise V Unaffected Set Set if there is a borrow from the most significant bit of the result cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note DA SUB HL nn 11101101 11010110 n low n high 2 r LX DC 8297 03 5 173 7106 SUB 2380 USER S MANUAL SUBTRACT FROM STACK POINTER WORD Operation Flags Addressing Mode IM 5 174 SUB SP src src IM if XM then begin SP 31 0 lt SP 31 0 src 31 0 end else begin SP 15 0 lt SP 15 0 src 15 0 end The source operand is sub
148. X 1234H IY 1234H A IX 1234H A IY 1234H DD FD DD CPW IX 1234H CPW IY 1234H CPW HL IX 1234H CPW HL IY 1234H DEC IX 1234H IY 1234H DIVUW IX 1234H DIVUW IY 1234H DIVUW HL IX 1234H DIVUW HL IY 1234H INA A 123456H INAW HL 123456H INC IX 1234H INC IY 1234H LD 123456 LD IX 1234H 56H LD IX 1234H A LD IX 1234H B LD IX 1234H C LD IX 1234H D LD IX 1234H E LD IX 1234H H LD IX 1234H L LD IY 1234H 56H LD IY 1234H A LD IY 1234H B LD IY 1234H C LD IY 1234H D LD IY 1234H DE LD IY 1234H H LD IY 1234H L LD A 1234H LD 1 1234 LD A IY 1234H LD B IX 1234H LD B IY 1234H LD C IX 1234H LD C IY 1234H LD D IX 1234H LD D IY 1234H LD E IX 1234H LD E IY 1234H LD H IX 1234H LD H IY 1234H LD L IX 1234H LD L IY 1234H MULTUW IX 1234H MULTUW IY 1234H MULTUW IX 1234H MULTUW HL IY 1234H MULTW MULTW MULTW MULTW OR IX 1234H IY 1234H HL IX 1234H HL IY 1234H IX 1234H v nne 56 56 1 SBCW SBCW SET SET SET SET SET SET SET SET SET SET IY 1234H A IX 1234H A IY 1234H IX 1234H IY 1234H HL IX 1234H HL IY 1234H 123456H A 123456H HL 0 IX 1234H 0 1Y 1234H 1 IX 1234H 1 IY 1234H 2 IX 1234H 2 IY 1234H 3 IX 1234H 3 IY 1234H 4 IX 1234H 4 IY 1234H 5 IX 1234H 5 IV 1234H 6 IX 1234H 6 IV 1234H
149. Y DE L ED DB 34 12 INA A 1234H FD 17 LD L ED DC 12 CALR C 12H X FD 18 56 34 12 JR 123456H X ED LDIW L FD 19 ADD X ED E2 INIW FD 1B LD DE IY L ED E3 OUTIW FD 1C LD BC DE L ED 4 12 CALR PO 12H X FD 1D LD DE DE L ED E8 LDDW L FD 1F LD HL DE L ED EA INDW FD 20 56 34 12 JR NZ 123456H X ED EB OUTDW FD 21 34 12 LD IY 1234H L ED EC 12 CALR PE 12H X FD 22 34 12 LD 1234 L ED FO LDIRW L FD 23 ING IY X ED F2 INIRW FD 23 INCW IY X ED F3 OTIRW FD 24 INC IYU ED F4 12 CALR 12 X FD 25 DEC IYU ED F7 SETC LCK FD 27 LD L ED F8 LDDRW L FD 28 56 34 12 JR Z 123456H X ED FA INDRW FD 29 ADD X ED FB OTDRW FD 2A 34 12 LD IY 1234H L ED FC 12 CALR M 12H X FD 2B DEC IY X ED FF RESC LCK FD 2B DECW IY X EE 12 XOR 12H FD 2C INC IYL EE 12 XOR A 12H FD 2D DEC IYL EF RST 28H X FD 2E 12 LD IYL 12H FO RET NS X FD 30 56 34 12 JR 123456 X FO RET P X FD 31 LD HL IY L F1 POP AF L FD 32 LD HL HL L F2 34 12 JP NS 1234H X FD 33 LD IV HL L F2 34 12 JP P 1234H X FD 34 12 INC IY 12H DI FD 35 12 DEC IY 12H F4 34 12 CALLNS P 1234H X FD 36 34 12 LD IY 12H 34H 1 F5 PUSH AF L FD 36 12 LD IYU 12H F6 12 OR 12H FD 37 LD IV HL L F6 12 OR A 12H FD 38 56 34 12 JR 123456 X F7 RST 30H X FD 39 ADD IY SP X F8 RET M X FD 3B LD HL IY L F8 RET 5 X FD 3C LD BC HL L F9 LD SP HL L FD 3D LD DE HL L FA 34 12 JP M 1234H X FD SWAP IY 12 Source Code ADCW ADCW SUB
150. ZILOG INC MAKES NO WARRANTY OF MER CHANTABILITY OR FITNESS FOR ANY PURPOSE Zilog Inc shall notbe responsible for any errors that may appear in this document Zilog Inc makes no commitment to update or keep current the information contained in this document Zilog s products are not authorized for use as critical compo nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use Life support devices or systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 Telex 910 338 7621 FAX 408 370 8056 Internet http www zilog com DC 8297 03 v 1 1 INTRODUCTION The Z380 CPU incorporates advanced architectural fea tures that allow fast and efficientthroughput and increased memory addressing capabilities while maintaining Z809 CPU and 2180 MPU object code compatibility The Z380 CPU core provides a continuing growth path for present Z80 or Z180 based designs and offers the following key features W Full Static CMOS Design with Low Power Standby Mode Support m DC to 18 MHz Operating Frequency 95 Vol
151. a carry from the most significant bit of the result cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R ADDW HL R 11101101 100001 rr 2 RX ADDW HL RX 11y11101 10000111 2 IM ADDW HL nn 11101101 10000110 n low n high 2 X ADDW XY d 11y11101 11000110 d 4 r Field Encodings rr y 5 26 00 for BC 01 for DE 11 for HL 0 for IX 1 for IY DC 8297 03 2380 71 06 USER S MANUAL AND AND BYTE AND A src src R RX IM IR X Operation lt AAND src Alogical AND operation is performed betweenthe corresponding bits ofthe source operand and the accumulator and the result is stored in the accumulator 1 is stored wherever the corresponding bits in the two operands are both 15 otherwise 0 is stored The contents of the source are unaffected Flags S Setifthe most significant bit of the result is set cleared otherwise Z Setif all bits of the result are zero cleared otherwise H Set P Setif the parity is even cleared otherwise N Cleared C Cleared Addressing Execute Mode Syntax Instruction Format Time Note R AND A R 10100 r 2 RX AND A RX 11y11101 1010010w 2 IM AND 11100110 n 2 IR AND A HL 10100110 2 r X AND 11 11101 10100110 d 4 r Field Encodings convention y O for IX 1 for IY w Oforhigh byte 1 for low byte DC 8297 03 5 27 7106 ANDW AND WORD ANDW HL src src RX
152. all CALL cc dst y Complement Carry Flag CCF Call Relative CALR cc dst y Decrement and Jump if Non zero DJNZ dst Jump JP cc dst dst y V Jump Relative JR cc dst Return RET cc Restart RST p y Set Carry Flag SCF 5 12 DC 8297 03 71106 5 5 9 External Input Output Instruction Group This group of instructions Table 5 14 are used for trans ferring a byte a word or string of bytes or words between peripheral devices and the CPU registers or memory Byte I O port addresses transfer bytes D7 DO only These 8 bit peripherals in a 16 bit data bus environment must be connected to data line D7 DO In an 8 bit data bus environ ment word instructions to external I O peripherals should notbe used however on chip peripherals which is external to the CPU core and assigned as word I O device can still be accessed by word instructions Theinstructions fortransferring asingle byte IN OUT can transfer data between any 8 bit CPU register or memory address specified inthe instruction and the peripheral port specified by the contents of the C register The IN instruc tion sets the CPU flags according to the input data however special instructions restricted to using the CPU accumulator and Direct Address mode and do not affect the CPU flags Another varianttests an input port specified by the contents of the C register and sets the CPU flags without modifying CPU registers or memory Theinstructions fortrans
153. and HL 23 16 specifies bit location 23 to 16 of the HL register Flags The F register contains the following flags followed by symbols S Sign Flag Z Zero Flag H Half Carry Flag P V Parity Overflow Flag N Add Subtract Flag C Carry Flag 5 17 7106 2380 User s MANUAL 5 6 NOTATION AND BINARY ENCODING Continued Condition Codes condition codes The following symbols describe the Z Zero NZ Not Zero C Carry NC No Carry 5 Sign NS No Sign NV No Overflow V Overflow PE Parity Even PO Parity Odd P Positive M Minus Abbreviated set Field Encoding For opcode binary format in the Tables use the following convention For example to get the opcode format on the instruction LD IX 12h C First find out the entry for LD XY d R That entry has a opcode format of 11 y11 101 01 110 r lt d gt 5 7 EXECUTION TIME Table 5 18 details the execution time for each instruction encoding All execution times are for instruction execution only Clock cycles required for fetch and decode are not included because most of the time the clocks required for these operations occur in parallel with execution of the previous instruction s r in the execution time column indicates a memory read operation The time required for a read operation is shown in the Table 5 18 below w in the execution time column indicates a memory write operation The time required for a write operation is shown
154. ansfer of control to a new location if the processor flags satisfy the condition specified in the in struction Jump Relative with an 8 bit offset JRe is atwo byte instruction that jumps any instructions within the range 126 to 129 bytes from the location of this instruc tion Most conditional jumps in programs are made to locations only a few bytes away the Jump Relative with an 8 bit offset exploits this fact to improve code compact ness and efficiency Jump Relative with a 16 bit offset JR cc ee is a four byte instruction that jumps any instruc tions within the range 32765 to 32770 bytes from the location of this instruction and Jump Relative with a 24 bit offset JR cc eee isa five byte instruction that jumps any instructions within the range 8388604 to 8388611 bytes from the location of this instruction By using these Jump Relative instructions with 16 bit or 24 bit offsets allows to write relocatable or location independent programs Call and Restart are used for calling subroutines the current contents of the PC are pushed onto the stack and the effective address indicated by the instruction is loaded 2380 User s MANUAL into the PC The use of a procedure address stack in this manner allows straightforward implementation of nested and recursive procedures Call Jump and Jump Relative can be unconditional or based onthe setting of a CPU flag Call Relative CALR instructions work just like ordina
155. ator NEGW A dst OR Word ORW HL src src Subtract with Carry Word SBC HL src src SBCW HL src src Subtract Word SUB HL nn src SUBW HL src src Subtract from Stack Pointer SUB SP nn src Exclusive OR XORW HL src src Note that the instructions with X at the rightmost column is affected by Extended mode These operate across all the 32 bits in Modulo 2 for address calculation 5 10 BC DE HL SP IX IY nn nn IX d IY d v V N y x N TE X y N y x N y a N V V N V NV v v N x 18 N V N v N x y N V N N N 4404 T y N T X voy N y x V V N N ree DC 8297 03 7106 5 5 6 8 Bit Manipulation Rotate and Shift Group Instructions in this group Table 5 11 test set and reset bits within bytes and rotate and shift byte data one bit position Bits to be manipulated are specified by a field within the instruction Rotate can optionally concatenate the Carry flag to the byte to be manipulated Both left and right shifting is supported Right shifts can either shift 0 into bit 7 logical shifts or can replicate the sign in bits 6 and 7 arithmetic shifts All these instructions Set Bit and Reset Bit set the CPU flags according to the calculated result the operand can be register memory location 2380 UsER s MANUAL specified by
156. bit sizes and in Extended mode in 32 bit sizes These starting addresses should be even aligned in memory locations That is their least significant bytes should have addresses with AO 0 6 2 1 Interrupt Priority Ranking The 7380 MPU assigns fixed priority ranking to handle its Interrupt sources as shown in Table 6 1 Table 6 1 Interrupt Priority Ranking Priority Interrupt Sources Highest Trap undefined opcode NMI INTO INT1 INT2 Lowest INT3 6 2 2 Interrupt Control The 7380 MPU s flags and registers associated with Inter rupt processing are listed in Table 6 2 As discussed inthe Chapter 1 CPU Architecture some of these registers reside in the on chip I O address space and can be accessed only with reserved on chip instructions Table 6 2 Interrupt Flags and Registers Names Mnemonics Access Methods Interrupt Enable Flags IEF1 IEF2 El and DI Instructions Interrupt Register LD and LD A I Instructions Interrupt Register Extension Iz LD I HL and LD Instructions Accessing both Iz and I Interrupt Enable Register IER On chip Instructions Address 17H El and DI Instruction Assigned Vectors Base and Trap Register AVBR On Chip Instructions Address 18H Trap and Break Register TRPBK On Chip Instructions Address 19H 6 2 DC 8297 03 7106 6 2 2 1 IEF1 IEF2 IEF1 controls the overall enabling and disabling of all on chip peripheral and external maskable
157. ble 2 1 DC 8297 03 5 13 7106 2380 USER S MANUAL 5 5 9 External Input Output Instruction Group Continued Table 5 14 External I O Group Instructions Instruction Name Format Input IN dst C dst A B C D H or L Input Accumulator IN A n Input to Word Wide Register INW dst C dst BC DE or HL Input Byte from Absolute Address INAW A nn Input Word from Absolute Address INAW HL nn Input and Decrement Byte IND Input and Decrement Word INDW Input Decrement and Repeat Byte INDR Input Decrement and Repeat Word INDRW Input and Increment Byte INI Input and Increment Word INIW Input Increment and Repeat Byte INIR Input Increment and Repeat Word INIRW Output OUT src H L orn Output Accumulator OUT n A Output from Word Wide Register OUTW src src BC DE HL or nn Output Byte from Absolute Address OUTAW nn A Output Word from Absolute Address OUTAW nn HL Output and Decrement Byte OUTD Output and Decrement Word OUTDW Output Decrement and Repeat Byte OTDR Output Decrement and Repeat Word OTDRW Output and Increment Byte OUTI Output and Increment Word OTIW Output Increment and Repeat Byte OTIR Output Increment and Repeat Word OTIRW 5 14 DC 8297 03 2106 5 5 10 Internal I O Instruction Group This group Table 5 15 of instructions is used to access on chip I O addressing space on the Z
158. bus and zeros are placed on all other address lines The byte of data from the memory location addressed by the HL register is loaded to the on chip I O port addressed by the C register register holding the port address is incremented by one to select the next output port The B register used as a counter is then decremented by one The HL register is then incremented by one thus moving the pointer to the next source for the output S Set if the result of decrementing B is negative cleared otherwise Z Set if the result of decrementing is zero cleared otherwise Setif there is a borrow from bit 4 during the decrement of the register cleared otherwise P Setifthe result of the decrement of the B register is even cleared otherwise Set if the most significant bit of the byte transferred was 1 cleared otherwise C Setif there is a borrow from the most significant bit during the decrement of the B register cleared otherwise Execute Syntax Instruction Format Time Note OTIM 11101101 10000011 2 0 5 117 7106 OUTPUT INCREMENT MEMORY REPEAT Operation Flags Addressing Mode 5 118 OTIMR ll repeat until B 0 begin This instruction is used for block output of strings of data to on chip peripherals No external I O transaction will be generated as a result of this instruction although the I O address will appear on the address bus and the write data will appea
159. by the DEregister The number of bytes moved is determined by the contents ofthe BC register If the BC register contains zero when this instruction is executed 65 536 bytes are transferred The effect of incrementing the pointers during the transfer is important if the source and destination strings overlap with the source string starting at a higher memory address Placing the pointers at the lowest address of the strings and incrementing the pointers ensures that the source string is copied without destroying the overlapping area This instruction can be interrupted after each execution of the basic operation The Program Counter value of the start of this instruction is saved before the interrupt request is accepted so that the instruction can be properly resumed Unaffected Unaffected Cleared Cleared Cleared Unaffected Execute Syntax Instruction Format Time Note LDIR 11101101 10110000 3 r w 2380 USER S MANUAL DC 8297 03 2380 7106 USER S MANUAL LDIRW LOAD INCREMENT AND REPEAT WORD LDIRW Operation repeat until BC 0 begin if LW then begin DE HL DE 1 HL 1 DE 2 HL 2 DE 3 HL 3 DE 4 HL 4 BC 15 0 15 0 4 else begin DE HL DE 1 lt HL 1 DE DE 2 HL lt HL 2 15 0 lt 15 0 2 This instruction is used for block transfers of strings of data The words of data atthe location addressed by the HL register ar
160. cannot be disabled masked by software Typically NMI is reserved for high priority external events that need imme diate attention such as an imminent power failure Maskable Interrupts are Interrupts that can be disabled masked through software by cleaning the appropriate bits in the Interrupt Enable Register IER and IEF1 bit in the Select Register SR All of these four maskable Interrupt inputs INT3 INTO are external input signals to the Z380 CPU core The four Interrupt enable bits in the Interrupt Enable Register deter mine IER Internal I O address 17H which of the re quested Interrupts are accepted Each Interrupt input has a fixed priority with INTO as the highest and INT3 as the lowest The Enable Interrupt El instruction is used to selectively enable the maskable Interrupts by setting the appropriate bits in the IER register and IEF1 bit in the SR register and DC 8297 03 USER s MANUAL CHAPTER 6 INTERRUPTS AND TRAPS A hardware reset overrides all other conditions including Interrupts and Traps It occurs when the RESET line is activated and causes certain CPU control registers to be initialized Resets are discussed in detail in Chapter 7 The Z380 MPU s Interrupt and Trap structure provides compatibility with the existing Z80 and Z180 MPU s with the following exception the undefined opcode Trap oc currence is with respect to the Z380 instruction set and its response is improved vs the 2180
161. cc100 disp note CALR addr 11101101 11001101 disp 4 w CALR CC addr 11011101 11 cc100 d low d high note CALR addr 11011101 11001101 d low d high 4 w CALR CC addr 11111101 11 cc100 d low d mid d high note CALR addr 11111101 11001101 d low d mid d high 4 w Field Encodings cc 000 for NZ 001 for Z 010 for NC 011 for C 100 for PO or NV 101 for PE or V 110 for Por NS 111 for M or S Note 2 if CC is false 4 w if CC is true 5 32 gt x gt x lt gt x x gt x Z 2380 USER S MANUAL ote DC 8297 03 2380 2106 USER S MANUAL CCF COMPLEMENT CARRY FLAG CCF Operation lt NOTC The Carry flag is inverted Flags S Unaffected 2 Unaffected H The previous state of the Carry flag V Unaffected N Cleared C Setifthe Carry flag was clear before the operation cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note CCF 00111111 2 DC 8297 03 5 33 2380 7106 USER S MANUAL CP COMPARE BYTE CP A src src R RX IM IR X Operation src The source operand is compared with the accumulator and the flags are set accordingly The contents of the accumulator and the source are unaffected Two s complement subtraction is performed Flags S Set if the result is negative cleared otherwise Set if the result is zero cleared otherwise Set if there is a borrow from bit 4 of the result cleared otherwise V Set if arithmetic overflow occurs that
162. ccordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 Telex 910 338 7621 FAX 408 370 8056 Internet http www zilog com This Appendix has two sets of tables Each table is subset of the Table in the Appendix B The Table D 1 has the instructions which works differently in the Native and USER s MANUAL D INSTRUCTIONS AFFECTED BY NORMAL EXTENDED MODE AND LONG WORD MODE Extended mode of operation and the Table D 2 has the instructions which works differently in Word Long Word mode of operation ILUU Table D 1 Instructions operating differently in Native or Extended mode of operation Source Code ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CALR CPD CPDR CPI CPIR DEC DEC DEC DEC DEC DEC DECW HL BC HL DE IX BC IX DE IX IX IX SP IY BC IYDE IY SP 123456H 1234H 12H 123456 C 1234H C 12H M 123456H M 1234H M 12H 123456 NC 1234H NC 12H NZ 123456H NZ 1234H NZ 12H P 123456H P 1234H P 12H PE 123456H PE 1234H PE 12H 123456 1234 12 Z 123456H Z 1234H Z 12H Object Code 0
163. ck so that the instruction can be resumed S Set if the last result is negative cleared otherwise Z Setifthe last result is zero indicating a match cleared otherwise Setifthere is a borrow from bit 4 of the last result cleared otherwise V Setifthe result of decrementing BC is not equal to zero cleared otherwise N Set C Unaffected Execute Syntax Instruction Format Time Note CPIR 11101101 10110001 8 r n X 5 39 7106 CPL COMPLEMENT ACCUMULATOR CPL A Operation lt 2380 USER S MANUAL The contents of the accumulator are complemented one s complement all 1s are changed to 0 and vice versa Flags S Unaffected Z Unaffected H Set V Unaffected Set Unaffected Addressing Mode Syntax Instruction Format CPL A 00101111 5 40 Execute Time Note 2 DC 8297 03 2380 71 06 USER S MANUAL CPLW COMPLEMENT HL REGISTER WORD CPLW HL Operation HL 15 0 NOTHL 15 0 contents of the HL register complemented ones complement all 15 changed to 0 and vice versa Unaffected Unaffected Set Unaffected Set Unaffected Flags Addressing Execute Mode Syntax Instruction Format Time Note CPLW HL 11011101 00101111 2 DC 8297 03 5 41 7106 DAA DECIMAL ADJUST ACCUMULATOR Operation Operation ADD ADC INC N 0 SUB SBC DEC NEG N 1 Flags Addressing Mode 5 42 DAA lt Decimal Adjust A The accumulat
164. ction is terminated otherwise the output sequence is repeated Note that if the B register contains 0 at the start of the execution of this instruction 256 bytes are output This instruction can be interrupted after each execution ofthe basic operation The Program Counter value atthe start of this instruction is saved before the interrupt request is accepted so that the instruction can be properly resumed S Cleared Z Set H Cleared P Set N Setif the most significant bit of the byte transferred was 1 cleared otherwise C Cleared Execute Syntax Instruction Format Time Note OTDMR 11101101 10011011 2 r 0 2380 USER S MANUAL DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL OTDR OUTPUT DECREMENT AND REPEAT BYTE OTDR repeat until B 0 begin lt 1 C HL HL HL 1 end This instruction is used for block output of strings of data The string of output data is loaded into the selected peripheral from memory at consecutive addresses starting with the location addressed by the HL register and decreasing During the transaction the 32 bit BC register is placed on the address bus Note that the B register contains the loop count for this instruction so that A 15 8 are not useable as part of a fixed port address The decremented B register is used in the address First the B register used as a counter is decremented by one The byte of data from
165. ction the 32 bit DE register is placed on the address bus First the word of data from the selected peripheral is loaded into the memory location addressed by the HL register Then the BC register used as a counter is decremented by one The HL register is then decremented by two thus moving the pointer to the next destination for the input S Unaffected Z Set if the result of decrementing BC is zero cleared otherwise H Unaffected V Unaffected Set Unaffected Execute Syntax Instruction Format Time Note INDW 11101101 11101010 2 i w 5 73 7106 INDR INPUT DECREMENT AND REPEAT BYTE Operation Flags Addressing Mode 5 74 INDR repeat until B 0 begin HL lt B B 1 HL lt HL 1 end This instruction is used for block input of strings of data The string of input data from the selected peripheral is loaded into memory at consecutive addresses starting with the location addressed by the HL register and decreasing During the I O transaction the 32 bit BC register is placed on the address bus Note that the B register contains the loop count for this instruction so that A15 A8 are not useable as part of a fixedport address First the byte of data from the selected peripheral is loaded into the memory location addressed by the HL register Then the B register used as a counter is decremented by one The HL register is then decremented by one thus moving the pointer to the next destination for
166. ctions Resetis an asynchronous event generated by outside circuits It terminates all current activities and puts the CPU into a known state Interrupts and Traps are discussed in detail in Chapter 6 and Reset is discussed in detail in Chapter 7 This section examines the relationship between instructions and the exception conditions 5 4 1 Instruction Execution and Interrupts When the CPU receives an interrupt request and it is enabled for interrupts of that class the interrupt is normally processed at the end of the current instruction However the block transfer and search instructions are designed to be interruptible so as to minimize the length of time it takes the CPU to respond to an interrupt If an interrupt request is received during a block move block search or block I O instruction the instruction is suspended after the currentiteration The address ofthe instruction itself rather than the address of the following instruction is saved on the stack so that the same instruction is executed again when the interrupt handler executes an interrupt return instruction The contents of the repetition counter and the registers that index into the block operands are such that after each iteration when the instruction is reissued upon returning from an interrupt the effect is the same as if the instruction were not interrupted This assumes of course that the interrupt handler preserves the registers 5 4 2 Instruction Executio
167. ctions as well as the addition of new instructions The Z380 CPU instruction set provides full complement of 8 bit 16 bit and 32 bit operation including multiplication and division For details on this subject refer to Chapter 5 Instruction Set 1 2 6 Exception Conditions The Z380 CPU supports three types of exceptions condi tions that alter the normal flow of program execution interrupts traps and resets Interrupts are asynchronous events typically triggered by peripherals requiring attention The Z380 CPU interrupt structure has been significantly enhanced by increasing the number of interrupt request lines and by adding an efficient means for handling nested interrupts The Z380 CPU has five interrupt lines These are Nonmaskable Interrupt line NMI and Maskable interrupt lines INTO INT1 2 and INT3 Interrupt requests on INT3 INT1 DC 8297 03 7106 handled by newly added interrupt handing mode Assigned Vectored Mode which is fixed vectored interrupt mode similar in interrupt handling to the 21805 interrupts from on chip peripherals For handling interrupt requests on the INTO line there are four modes available 8080 compatible Mode 0 in which the interrupting device provides the first instruction of the interrupt routine m Dedicated interrupts Mode 1 in which the CPU jumps to dedicated address when an interrupt occurs Vectored interrupt mode Mode 2
168. d by DDIRimmediate Decoder Directives Extended mode or Native mode of operation and Word or Long Word Mode of operation I means the instruction can be used with DDIR IM to expand its immediate constant X means USER s MANUAL APPENDIX C Z380 INSTRUCTION IN NUMERIC ORDER that the operation of the instruction is affected by the XM status bit and L means that the instruction is affected by LW status bit or can be used with DDIRLWor DDIRW The Native Extended modes Word Long Word modes and Decoder Directives are discussed in Chapter 3 in this manual vom nne Object Code Source Code Mode Object Code Source Code Mode 00 NOP 2F CPL 01 34 12 LD BC 1234H L 30 12 JR NC 12H X 02 LD 31 34 12 LD SP 1234H L 03 INC BC X 32 34 12 LD 1234H A 1 03 INCW BC X 33 INC SP X 04 INC B 33 INCW SP X 05 DEC 34 INC HL 06 12 LD B 12H 35 DEC HL 07 36 12 LD HL 12H 08 EX AFAF 37 SCF 09 ADD HL BC x 38 12 JR C 12H X 0A LD 39 ADD X 0B DEC BC X 3A 34 12 LD A 1234H 0B DECW BC X 3B DEC SP X 0C INC C 3B DECW SP X 0D DEC C 3C INC OE 12 LD C 12H 3D DEC OF RRCA 3E 12 LD A 12H 10 12 DJNZ 12H x 3F CCF 11 34 12 LD DE1234H L 40 LD B B 12 LD DE A 41 LD B C 13 INC DE X 42 LD B D 13 INCW DE X 43 LD BE 14 INC D 44 LD BH 15 DEC 45 LD B L 16 12 LD D 12H 46 LD B HL 17 RLA 47 LD 18 12 JR 12H X 48 LD 19 ADD HL DE X 49 LD EG 1 LD A DE 4
169. de 1 2 1 2 Word or Long Word Mode In addition to Native and Extended mode which are specific to memory space addressing the Z380 CPU can operate in either Word or Long Word mode specific to data load and exchange operations In Word mode the Reset configuration all word load and exchange operations manipulate 16 bit quantities For example only the low order words of the source and destination are exchanged in an exchange operation with the high order words unaffected In the Long Word mode all 32 bits of the source and destination are exchanged The Z380 CPU implements two instructions plus decoder directives to allow switching between Word and Long Word mode SETC LW Set Control Long Word and RESC LW Reset Control Long Word perform global switch while DDIR W DDIR LW and their variants are decoder directives that select particular mode only for the instruction that they precede Note that all word data arithmetic as opposed to address manipulation arithmetic rotate shift and logical opera tions are always in 16 bit quantities They are not con trolled by either the Native Extended or Word Long Word selections The exceptions to the 16 bit quantities are of course those multiply and divide operations with 32 bit products or dividends All word Input Output operations are performed on 16 bit values regardless of Word Long Word operation 1 2 2 Address Spaces Addressing spaces in the Z380 CPU include the
170. de Syntax Instruction Format Time Note R ADD A R 10000 r 2 RX ADD A RX 11y11101 1000010w 2 IM ADD A n 11000110 n 2 IR ADD A HL 10000110 2 1 ADD 11y11101 10000110 d 4 r Field Encodings r per convention y Ofor IX 1 for IY w Oforhigh byte 1 for low byte DC 8297 03 5 23 2380 7106 USER S MANUAL ADD ADD WORD ADD dst src dst HL src DE HL SP DA or dst IX src DE IX SP or dst IY src BC DE IY SP Operation If XM then begin dst 31 0 lt dst 31 0 src 31 0 end else begin dst 15 0 lt dst 15 0 src 15 0 end The source operand is added to the destination and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed Note that the length of the operand is controlled by the Extended Native mode selection which is consistent with the manipulation of an address by the instruction Flags S Unaffected 27 Unaffected Setif there is a carry from bit 11 of the result cleared otherwise V Unaffected Cleared C Setifthere is a carry from the most significant bit of the result cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R ADD HL R 00111001 2 X RX ADD XY R 11y11101 00111001 2 X DA ADD nn 11101101 11000110 n low n high 2 LX Field Encodings rr 00 for BC 01 for DE 10 for register to itself 11 for SP y OforIX
171. e Addressing mode is used by certain program control instructions to specify the address of the next instruction to be executed specifically the sum of the Program Counter value and the displace ment value is loaded into the Program Counter Relative addressing allows reference forward or backward from the current Program Counter value it is used for program control instructions such as Jumps and Calls that access constants in the memory As adisplacement an 8 bit 16 bit or 24 bit value can be used The address to be loaded into the Program Counter is computed by adding the two s complement signed displacement specified in the instruction to the current Program Counter Also in Native mode Note that computation of the effective address is affected by the mode of operation Native or Extended In Native mode address computation is done in modulo 21 and the PC Extend PC31 PC16 is forced to 0 and will not affect this portion In Extended mode address computation is done is modulo 232 and will affect the contents of PC extend if there is a carry or borrow operation Instruction PC MEMORY OPERATION ADDRESS OPERAND DISPLACEMENT Example of RA mode 1 Jump relative in Native mode 8 bit displacement JR 2 Jumps to the location PC value 2 7 represents for current PC value This instruction jumps to itself since after the execution of this instruction PC points to the next instruction DC 8297
172. e DDIR LW and DDIR W are decoder directives that select a particular mode only for the instruction that they precede Examples 1 Effect of Word mode and Long Word mode DDIR W LD BC HL Loads BC15 BCO from the location HL and HL 1 and BCz BC31 BC16 remains un changed DDIR LW LD HL Loads BC31 BC0O from the locations HL to HL 3 2 Immediate data load with DDIR instructions DDIR IW LW LD HL 12345678H Loads 12345678H into HL31 HLO DDIR IB LW LD HL 123456H Loads 00123456H into HL31 HLO 00H is appended as the Most significant byte as HL31 HL24 DDIR LW LD HL 1234H Loads 00001234H into HL31 HLO 0000H is appended as the HL31 HL16 portion O 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc The information in this document is subject to change without notice Devices sold by Zilog Inc are covered by warranty and patent indemnification provisions appearing in Zilog Inc Terms and Conditions of Sale only ZILOG INC MAKES NO WARRANTY EXPRESS STATUTORY IMPLIED OR BY DESCRIPTION REGARDING THE INFORMA TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT ZILOG INC MAKES NO WARRANTY OF MER CHANTABILITY OR FITNESS FOR ANY PURPOSE Zilog Inc shall not be responsible for any errors that may
173. e SP in ascending byte order in ascending address memory locations The contents of the source are unaffected S Unaffected 7 Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Syntax PUSH RX 00 for BG 01 for DE 10 for HL y Ofor IX 1 for IY Instruction Format 11110101 11y11101 11100101 Execute Time Note 3 W L 3 W L 5 137 2380 7106 USER S MANUAL RES RESET BIT RES dst dst R IR X Operation dst b 0 The specified bit b within the destination operand is cleared to 0 The other bits in the destination are unaffected The bit to be reset is specified by a 3 bit field in the instruction this field contains the binary encoding for the bit number to be cleared The bit number b must be between 0 and 7 Flags S Unaffected Z Unaffected H Unaffected V Unaffected Unaffected C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R RES b R 11001011 10bbb r 2 IR RES b HL 11001011 10bbb110 2 r X RES b XY d 11y11101 11001011 d 10bbb110 4 r Field Encodings r per convention y Ofor IX 1 for IY 5 138 DC 8297 03 2380 7106 USER S MANUAL RESC RESET CONTROL BIT RESC mode mode LCK LW Operation if mode LCK then begin SR 1 lt 0 end else begin SR 6 lt 0 end When reseting Lock mode LCK the LCK bit bit 1 in the Select Register SR is set to 0 enabling external bus requests Note that these re
174. e and the result is stored in the destination Two s complement subtraction is performed Note that the length of the operand is controlled by the Extended Native mode selection which is consistent with the manipulation of an address by the instruction Flags 6 Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R DEC W R 00111011 2 X RX DEC W RX 11y11101 00101011 2 X Field Encodings rr 00 for BC 01 for DE 10 for HL 11 for SP y OforIX 1 for IY DC 8297 03 5 45 7106 DI DISABLE INTERRUPTS Operation Flags Addressing Mode 5 46 DI n if n is present then begin for i 1 to 4 begin if n i 1 then begin IER i 1 lt 0 if n O 1 then begin SR 5 0 else begin SR 5 0 If an argumentis present disable the selected interrupts by clearing the appropriate enable bits in the Interrupt Enable Register and then clear the Interrupt Enable Flag IEF1 in the Select Register SR if the least significant bit of the argument is set disabling maskable interrupts Bits 7 5 of the argument are ignored If no argument is present IEF1 in the SR is set to 0 disabling maskable interrupts Note that during execution of this instruction the maskable interrupts are not sampled S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffec
175. e bytes thereby allowing more than 256 unique instructions For example the 01H opcode when alone specifies a form of a Load Register Word instruction when proceeded by OCBH escape code the opcode 01H specifies a Rotate Left Circular instruc tion Format 3 instructions with DDIR Immediate data Decoder Directives 1 to 3 bytes of displacement is between the opcode escape byte and opcode itself Format 4 instructions are proceeded by OEDH OCBH and a opcode Optionally with immediate word field follows Addressing mode escape codes are used to determine the type of encoding for the addressing mode field within an instruction s opcode and can be used in instructions with and without opcode escape value An addressing mode escape byte can have the value of ODDH or OFDH The addressing mode escape byte if present is always the first byte of the instructions machine code and is immediately followed by either the opcode Format 1 or the opcode escape byte Format 2 and 3 For example the 46H opcode when alone specifies a Load B register from memory location pointed by HL register when proceeded by the ODDH escape byte the opcode 46H specifies a Load B register from the memory location pointed by IX d m The four instruction formats are shown in Tables A 1 through A 4 Within each format several different configu rations are possible depending on whether the instruction involves addressing mode escape bytes addresse
176. e loaded into memory starting at the location addressed by the DE register The number of words moved is determined by the contents of the BC register If the BC register contains zero when this instruction is executed 65 536 words are transferred The effect of incrementing the pointers during the transfer is important if the source and destination strings overlap with the source string starting at a higher memory address Placing the pointers at the lowest address of the strings and incrementing the pointers ensures that the source string is copied without destroying the overlapping area This instruction can be interrupted after each execution of the basic operation The Program Counter value of the start of this instruction is save before the interrupt request is accepted so that the instruction can be properly resumed Unaffected Unaffected Cleared Cleared Cleared Unaffected Flags Addressing Execute Mode Syntax Instruction Format Time Note LDIRW 11101101 11110000 3 r w n L DC 8297 03 5 103 7106 2380 USER S MANUAL MULTIPLY UNSIGNED BYTE Operation Flags Addressing Mode R MLT R src R 15 0 R 7 0 x R 15 8 The contents of the upper byte of the source register are multiplied by the contents of the lower byte of the source register and the product is stored in the source register Both operands Both operands are treated as unsigned binary integers S Unaffected Z Unaffected H U
177. e one input operand from the HL register and the other from a 16 bit register from the instruction itself or from memory using Indexed 2380 USER S MANUAL or Direct Address addressing mode The 32 bit result multiply is returned to the HLz and HL HL31 HLO The unsigned divide instruction takes a 16 bit dividend from the HL register and a 16 bit divisor froma register from the instruction or memory using the Indexed mode The 16 bit quotient is returned in the HL register and the 16 bit reminder is returned to the HLz HL31 HL16 The Extend Sign instruction takes the contents of the HL register and delivers the 32 bit result to the HLz and HL registers The Negate HL instruction negates the contents of the HL register Except for Increment Decrement and Extend Sign all the instructions in this group set the CPU flags to reflect the computed result Table 5 10 16 Bit Arithmetic Operation src Instruction Name Format dst Add With Carry Word ADC HL src src ADCW HL src SIC Add Word ADD HL src src ADD 5 SIC ADD IY src SIC ADDW HL src SIC Add to Stack Pointer ADD SP nn SIC AND Word ANDW HL src SIC Complement Accumulator CPLW HL dst Compare Word CPW src Decrement Word DEC W dst dst Divide Unsigned DIVUW HL src src Extend Sign Word EXTSW HL dst Increment Word INC W dst dst Multiply Word Signed MULT HL src src Multiply Word Unsigned MULTUW HL src src Negate Accumul
178. ected 2 Unaffected H Unaffected V Unaffected Unaffected Unaffected Addressing Execute Mode Syntax Instruction Format Time Note EXXY 11111101 11011001 3 DC 8297 03 5 61 7106 HALT HALT Operation Flags Addressing Mode HALT CPU Halts The CPU operation is suspended until either an interrupt request or reset request is received This instruction is used to synchronize the CPU with external events preserving its state until an interrupt or reset request is accepted After an interrupt is serviced the instruction following HALT is executed While the CPU is halted memory refresh cycles still occur and bus requests are honored When this instruction is executed the signal HALT is asserted and remains asserted until an interrupt or reset request is accepted S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected Unaffected Syntax HALT Instruction Format 01110110 2380 USER S MANUAL 5 62 DC 8297 03 2380 71 06 USER S MANUAL IM INTERRUPT MODE SELECT IMp p 0 1 2 3 Operation SR 4 3 The interrupt mode of operation is setto one of four modes See Chapter 6 for a description of the various modes for responding to interrupts The current interrupt mode can be read from the Select Register SR Flags S Unaffected Z Unaffected H Unaffected V Unaffected Unaffected C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note IM p
179. ed internally at BUSCLK s falling edges For proper initialization of the Z380 CPU must be within operating specifications and the CLK input must be stable for more than five cycles with RESET held Low The Z380 CPU proceeds to fetch the first instruction 3 5 BUSCLK cycles after RESET is deasserted provided such deassertion meets the proper setup and hold times USER s MANUAL CHAPTER 7 with reference to the falling edge of BUSCLK On the 7380 MPU implementation withthe proper setup and hold times being met IOCLK s first rising edge is 11 5 BUSCLK cycles after the RESET deassertion preceded by mini mum of four BUSCLK cycles when IOCLK is at Low Note that if BREQ is active when RESET is deasserted the Z380 MPU would relinquish the bus instead of fetching its first instruction IOCLK synchronization would still take place as described before Requirements to reset the device and the initial state after reset might be different depending onthe particular imple mentation of the Z380 CPU onthe individual Superintegra tion version of the device For RESET effects and require ments refer to the individual product specification ILUU ween v Table 7 1 Effect of Reset 7380 CPU and Related I O Registers Register Reset Value Comments Program Counter 00000000 2 PC Stack Pointer 00000000 SPz SP 000000 2 1 00 Select Register 00000000 Register Bank 0 Selected
180. ed or reproduced in any form or by any means without the prior written consent of Zilog Inc The information in this document is subject to change without notice Devices sold by Zilog Inc are covered by warranty and patent indemnification provisions appearing in Zilog Inc Terms and Conditions of Sale only ZILOG ING MAKES NO WARRANTY EXPRESS STATUTORY IMPLIED OR BY DESCRIPTION REGARDING THE INFORMA TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT ZILOG INC MAKES NO WARRANTY OF MER CHANTABILITY OR FITNESS FOR ANY PURPOSE Zilog Inc shall not be responsible for any errors that may appear in this document Zilog Inc makes no commitment to update or keep current the information contained in this document Zilog s products are not authorized for use as critical compo nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use Life support devices or systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 Telex 910 338 7621 FAX 408 370 8056 Intern
181. ee 32 bit general purpose registers The HL register serves as the 16 bit or 32 bit accumulator for word operations Access to the Extended portion of the registers is possible using the SWAP instruc tion or word Load instructions in Long Word operation mode The Flag register contains eight status flags Four can be individually used for control of program branching two are used to support decimal arithmetic and two are reserved These flags are set or reset by various CPU operations For details on Flag operations refer to Section 5 2 Flag Register 2 2 2 Index Registers The four index registers IX IX IY and IY are extended to 32 bits by the extension to the register with suffix 2 IXz IYz to form 32 bit index registers To access the Extended portion of the registers use the SWAP instruction or word Load instructions in Long Word operation mode These Index registers hold a 32 bit base address that is used in the Index addressing mode Only one register of each can be active at any given time although data in the inactive file can still be accessed by using EX IX IX and EX IY IY either in 16 bit or 32 bit wide depending on the LW bit status Index registers can also function as general purpose registers with the upper and lower bytes of the lower 16 bits being accessed individu ally These byte registers are called IXU IXU IXL and IXL DC 8297 03 2380 UsER s MANUAL for the IX and
182. egister IR In Indirect Register addressing mode the register speci fied in the instruction holds the address of the operand Memory or Instruction OPERATION REGISTER gt The datato be processed is the location specified by the BC DE or HL register depending on the instruction for memory accesses or C register for I O I O Port OPERAND Register Address gt The operand value is the contents of the location whose address is in the register Depending on the instruction the operand specified by IR mode is located in either the I O address space I O instruction or memory address space all other instruc tions Indirect Register mode can save space and reduce ex ecution time when consecutive locations are referenced or one location is repeatedly accessed This mode can also be used to simulate more complex addressing modes since addresses can be computed before data is ac cessed The address in this mode is always treated as a 32 bit mode After reset the contents of the extend registers registers with 2 suffix are initialized as O s hence these instructions will be executed just as for the Z80 Z180 4 2 Example of IR mode 1 Load accumulator from the contents of memory pointed by HL LD A HL Load the accumulator with the data addressed by the contents of HL A HLz HL Before instruction execution OF 12345678 After instruction execution OB 12345678 Memory location 12345678 0B
183. egisters This field can be set independently of the register set selection for the other Z380 CPU registers Reset selects Bank 0 for these registers 5 3 6 BC DE HL or BC DE HL Register Select ALT This bit controls and reports whether BC DE HL or BC DE HL is the currently active bank of registers BC DE HL is selected when this bit is cleared and BC DE HL is selected when this bitis set Reset clears this bit selecting BC DE HL 5 3 7 Extended Mode XM This bit controls the Extended Native mode selection for the Z380 CPU This bit is set by the SETC XM instruction This bit can not be reset by software only by Reset When this bit is set the Z380 CPU is in Extended mode Reset clears this bit and the Z380 CPU is in Native mode DC 8297 03 2106 5 3 8 Long Word Mode LW This bit controls the Long Word Word mode selection for the 7380 CPU This bit is set by the SETC LW instruction cleared by the LW instruction When this bit is set the 2380 CPU is in Long Word mode when this bit is cleared the 2380 CPU is in Word mode Reset clears this bit Note that individual Word load and exchange instruc tions may be executed in either Word or Long Word mode using the DDIR W and DDIR LW decoder directives 5 3 9 Interrupt Enable Flag IEF This bit is the master Interrupt Enable for the Z380 CPU This bit is set by the EI instruction and cleared by the instruction or on acknowledgment
184. er For example this instruction is useful to implement the recursive program which uses the alter nate bank to save a register for the first time and saves registers into memory thereafter Mode Test instructions reports the current mode of opera tion Native Extended Word Long Word Locked or not This instruction can be used to switch procedures de pending on the mode of operation Load Accumulator from R or Register instructions are used to report current interrupt mask status Load from to register instructions are used to initialize the I register Load Control register instructions are used to read write the Status Register set reset control bit instructions and to set reset the control bits in the SR The No Operation instruction does nothing and can be used as a filler for debugging purposes or for timing adjustment Table 5 16 CPU Control Group Instruction Name Format Bank Test BTEST Disable Interrupt DI mask Enable Interrupt mask HALT HALT Interrupt Mode Select IM p Load Accumulator from I or R Register LD A src Load I or R Register from Accumulator LD dst A Load I Register from HL Register LD W Load HL Register from Register LD W Load Control LDCTL dst src Mode Test MTEST No Operation NOP Return from Interrupt Return Nonmaskable Interrupt RETN Reset Control Bit RESC dst dst LCK LW Set Control Bit SETC dst dst LCK LW XM Sleep SLP 5 16 DC 8297 03
185. eripheral During the I O transaction the 8 bit peripheral address from the instruction is placed on the low byte of the address bus the contents of the accumulator are placed on address lines A 15 8 and the high order address lines are all zeros S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Execute Syntax Instruction Format Time Note OUT n A 11010011 n 3 0 5 123 2380 7106 USER S MANUAL OUTO OUTPUT TO PAGE 0 OUTO n src src R Operation n src The byte of data from the source register is loaded into the selected on chip peripheral No external I O transaction will be generated as a result of this instruction although the I O address will appear on the address bus and the write data will appear on the data bus while this internal write is occurring The peripheral address is placed on the low byte of the address bus and zeros are placed on all other address lines Flags S Unaffected Z Unaffected H Unaffected V Unaffected Unaffected C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R OUTO n R 11101101 00 r 001 n 3 0 Field Encodings r per convention 5 124 DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 OUT nn A The byte of data from the accumulator is loaded into the selected peripheral During the I O transaction the peripheral address from the instructio
186. es are reserved For the other three registers refer to Chapter 6 Interrupts and Traps Also the Z380 MPU has registers to control chip selects refresh waits and clock divide to Internal I O address OOH to 10H For these registers refer to the Z380 MPU Product specification DC 3003 01 DC 8297 03 7106 2380 USER S MANUAL O 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc The information in this document is subject to change without notice Devices sold by Zilog Inc are covered by warranty and patent indemnification provisions appearing in Zilog Inc Terms and Conditions of Sale only ZILOG ING MAKES NO WARRANTY EXPRESS STATUTORY IMPLIED OR BY DESCRIPTION REGARDING THE INFORMA TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT ZILOG INC MAKES NO WARRANTY OF MER CHANTABILITY OR FITNESS FOR ANY PURPOSE Zilog Inc shall not be responsible for any errors that may appear in this document Zilog Inc makes no commitment to update or keep current the information contained in this document Zilog s products are not authorized for use as critical compo nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zil
187. esses through which peripheral devices are accessed m On Chip I O Address Space This consists of all internal I O port addresses through which peripheral devices are accessed Also this addressing space contains registers to control the functionality of the device giving status information m Four sets of Index registers IX IY IX m Stack Pointer SP m Program Counter Interrupt register Refresh register PC I R Register addresses are either specified explicitly in the instruction or are implied by the semantics of the instruc tion 2 1 2380 7106 USER S MANUAL 2 2 CPU REGISTER SPACE Continued 4 Sets of Registers SPz PCz Figure 2 1 Register File Organization Z380 MPU 2 2 DC 8297 03 7106 2 2 1 Primary and Working Registers The working register set is divided into two register files the primary file and the alternate file designated by prime Each file contains an 8 bit accumulator a Flag register F and six 8 bit general purpose registers C D E H and L with their Extended registers Only one file can be active at any given time although data in the inactive file can still be accessed by using EX R R instructions for the byte wide registers EX RR RR instruc tions for register pairs either in 16 bit or 32 bit wide depending on the LW status Exchange instructions allow the programmer to exchange the active file with the inac tive file The EX AF AF
188. et http www zilog com
189. ferring asingle word INW OUTW cantransfer data between the register pair and the periph eral port specified by the contents of the C register For Word the contents of B D or H appear 07 00 and 2380 USER S MANUAL the contents of C E or L appear D15 D7 These instruc tions do not affect the CPU flags Also there are instructions available which allow to specify 16 bit absolute address with DDIR decoder directives a 24 bit or 32 bit address is specified is avail able These instructions do not affect the CPU flags The remaining instructions in this group form powerful and complete complement of instructions for transferring blocks of data between I O ports and memory The tion of these instructions is very similar to that of the block move instructions described earlier with the exception that operand is always an port whose address remains unchanged while the address of the other oper a memory location is incremented or decremented In Word mode of transfer the counter i e BC register holds the number of transfers rather than number of bytes to transfer in memory to memory word block transfer Both byte and word forms of these instructions are available The automatically repeating forms of these instructions are interruptible like memory to memory transfer The addresses output on the address bus is de pendant on the instruction as listed in Ta
190. ffected 7 Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Execute Syntax Instruction Format Time Note EXALL 11101101 11011001 3 DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL EXTS EXTEND SIGN BYTE EXTS A L if A 7 0 then begin H 00 if LW then begin HL 31 16 lt 0000h end end else begin FFh if LW then begin HL 31 16 lt FFFFh end end The contents of the accumulator considered as a signed two s complement integer are sign extended to 16 bits and the result is stored in the HL register The contents of the accumulator are unaffected This instruction is useful for conversion of short signed operands into longer signed operands S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Execute Syntax Instruction Format Time Note EXTS A 11101101 01100101 3 L 5 57 2380 7106 USER S MANUAL EXTSW EXTEND SIGN WORD EXTSW HL Operation If HL 15 0 then begin HL 31 16 0000h end else begin HL 31 16 lt FFFFh end The contents of the low word of the HL register considered as a signed two s complement integer are sign extended to 32 bits in the HL register This instruction is useful for conversion of 16 bit signed operands into 32 bit signed operands Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Flags Addressing Execute
191. gardless of the Interrupt Mode in effect interrupts on INT3 INT1 is always handled by the Assigned Interrupt Mode This mode is similar to the interrupt handling on the Z180 s INT1 or INT2 line When the Z380 MPU recognizes one of the external maskable Interrupts INT3 INT1 it generates an Interrupt acknowledge transaction which is different than that for INTO The Interrupt acknowledge transaction for INT3 INT1 has the I O bus signal INTACK active with M1 IORQ IORD and IOWR inactive The interrupted PC value is pushed onto the stack The size of the PC value pushed onto the stack is depends on the Native one word or Extended mode two words in effect IEF1 and IEF2 are reset to logic 0 disabling further maskable Interrupt requests The starting address of an Interrupt service routine is fetched from a table entry and loaded into the PC to resume execution The address of the table entry is composed of the Extend contents as A31 A16 the AB bits of the Assigned Vectors Base Register as A15 A9 and 6 7 RETI INSTRUCTION 780 family devices are designed to monitor the Return from Interrupt opcodes in the instruction stream RETI EDH 4DH signifying the end of the current Interrupt service routine When detected the daisy chain within and among the device s resolves and the appropri 6 6 an assigned interrupt vector specific to the request being recognized as 8 0 The assigned vectors are defined in
192. gin 95131 0 lt src 31 0 end else begin dst 15 0 lt src 15 0 end The contents of the source are loaded into the destination 5 7 V N C Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Syntax LD Rd Rs LD R RX LD R IR LD RX IR LD HL nn LD LD R XY d LD IX IY d LD R SP d LD RX SP d LD IY IX d d Instruction Format 11rs1101 00rd0010 11y11101 OOrr1011 11011101 OOrr1 Yri 11y11101 00ri0011 00101010 n low n high 11101101 01ra1011 n low n high 11y11101 00101010 n low n high 11y11101 11001011 d OOrr001 1 11111101 11001011 d 0010001 1 11011101 11001011 d 0010001 1 11011101 11001011 d 00rr0001 11y11101 11001011 d 00100001 2380 USER S MANUAL LD W LOAD REGISTER WORD Execute Time 2 2 24r 24r 3 7 3 r 4 r 4 r 4 r 4 7 4 7 sd 2 1 22 5 87 2380 7106 USER S MANUAL LD W LOAD REGISTER WORD Load from Register Addressing Execute Mode Syntax Instruction Format Time Note RX LD RX R 11y11101 00170111 2 L LD IX IY 11011101 00100111 2 L LD IV IX 11111101 00100111 2 L IR IR RR 11111101 OOrri fri 3 w L D IR A 11y11101 00ri0001 3 w L DA D nn H 00100010 n low n high 4 w LL D nn R 11101101 01 0011 n low n high 4 w LL nn R 11y11101 00100010 n low n high
193. gister merely holds sign extension data Flags S Set if the result is negative cleared otherwise Z Setifthe result is zero cleared otherwise H Unaffected V Cleared N Unaffected C if the product is less than 32768 or greater than or equal to 32768 cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R MULTW HL R 11101101 11001011 100100rr 10 RX MULTW HL RX 11101101 11001011 1001010y 10 IM MULTW HL nn 11101101 11001011 10010111 n low n high 10 X MULTW HL XY d 11y11101 11001011 d 10010010 12 r Field Encodings rr 00 for BC 01 for DE 11 for HL y Ofor IX 1 for IY 5 106 DC 8297 03 71106 Operation Flags Addressing Mode R RX IM 7380 USER S MANUAL MULTUW MULTIPLY UNSIGNED WORD MULTUW HL src src X HL 31 0 lt HL 15 0 x src 15 0 The contents of the HL register are multiplied by the source operand and the product is stored in the HL register The contents of the source are unaffected Both operands are treated as unsigned binary integers The initial contents of the HL register are overwritten by the result The Carry flag is set to indicate that the upper word of the HL register is required to represent the result if the Carry flag is cleared the product can be correctly represented in 16 bits and the upper word of the HL register merely holds zero S Cleared Z Set if the result is zero cleared o
194. hanged with the contents of the source where the destination is a word register in the primary bank and the source is the corresponding word register in the alternate bank Flags S Unaffected 27 Unaffected H Unaffected V Unaffected Unaffected Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R EX R R 11101101 11001011 001100rr 3 L RX EX RX RX 11101101 11001011 0011010y 3 L Field Encodings rr 00 for BC 01 for DE 11 for HL y for IX 1 for IY 5 54 DC 8297 03 2380 7106 USER S MANUAL EX EXCHANGE WITH ACCUMULATOR EX A src src RIR Operation dst src The contents of the accumulator are exchanged with the contents of the source Flags S Unaffected Z Unaffected H Unaffected V Unaffected Unaffected C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R EX A R 11101101 00 r 111 3 IR EX A HL 11101101 00110111 3 r w Field Encodings r per convention DC 8297 03 5 55 7106 EXALL 2380 USER S MANUAL EXCHANGE ALL REGISTERS WITH ALTERNATE BANK Operation Flags Addressing Mode 5 56 EXALL SR 24 lt NOT SR 24 SR 16 lt NOT SR 16 SR 8 lt NOT SR 8 Bits 8 16 and 24 of the Select Register SR which control the selection of primary or alternate bank for the BC DE HL IX and IY registers are complemented thus effectively exchanging the BC DE HL IX and IY registers between the two banks S Una
195. he result is negative cleared otherwise Z Setifthe result is zero cleared otherwise Setif there is a carry from bit 11 of the result cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise Cleared C Setifthere is a carry from the most significant bit of the result cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R ADCW HL R 11101101 100011 2 RX ADCW HL JRX 11y11101 10001111 2 IM ADCW HL nn 11101101 10001110 n low n high 2 X ADCW XY d 11y11101 11001110 d 4 r Field Encodings rr 00for BC 01 for DE 11 for HL y for IX 1 for IY 5 22 DC 8297 03 2380 71 06 USER S MANUAL ADD ADD BYTE ADD A src src RX IM IR X Operation lt src The source operand is added to the accumulator and the sum is stored in the accumulator The contents of the source are unaffected Two s complement addition is performed Flags S Set if the result is negative cleared otherwise Z Setif the result is zero cleared otherwise Setifthere is a carry from bit 3 of the result cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise Cleared C Setifthere is a carry from the most significant bit of the result cleared otherwise Addressing Execute Mo
196. he upper three bytes of the SR may be accessed individually as YSR XSR and DSR In addition these 2 4 MEMORY ADDRESS SPACE The memory address space can be viewed as a String of 4 Gbytes numbered consecutively in ascending order The 8 bit byte is the basic addressable element in the 7380 MPU memory address space However there are other addressable data elements bits 2 byte words byte strings and 4 byte words The size of the data elementbeing addressed depends on the instruction being executed as well as the Word Long Word mode A bit can be addressed by specifying a byte and a bit within that byte Bits are numbered from right to left with the least significant bit being 0 as illustrated in Figure 2 2 The address of a multiple byte entity is the same as the address of the byte with the lowest memory address in the entity Multiple byte entities can be stored beginning with 2 4 2380 USER S MANUAL SP holds 00010000H in Native mode and 00020000H in Extended mode In either case 5 2 can be programmed to set Stack frame This is done by the Load to Stack pointer instructions in Long Word mode upper three bytes can be loaded with the same byte value The SR may also be PUSHed POPed and is cleared to zeros on Reset For details on this register refer to Chapter 5 3 Select Register either even or odd memory addresses A word either 2 byte or 4 byte entity is aligned if its address is even otherw
197. hen begin DE lt HL DE 1 lt HL 1 DE 2 lt HL 2 DE 3 HL 3 DE lt 4 lt 4 15 0 lt BC 15 0 4 else begin DE lt HL DE 1 HL 1 DE lt 2 HL lt HL 2 15 0 lt BC 15 0 2 This instruction is used for block transfers of words of data The word of data the location addressed by the HL register is loaded into the location addressed by the DE register Both the DE and HL registers are then incremented by two or four thus moving the pointers to the succeeding words in the array The BC register used as byte counter is then decremented by two or four Both DE and HL should be even to allow word transfers on the bus BC must be even transferring an even number of bytes or the operation is undefined S Unaffected 7 Unaffected H Cleared V Set if the result of decrementing BC is not equal to zero cleared otherwise N Cleared Unaffected Execute Syntax Instruction Format Time Note LDIW 11101101 11100000 3 r w L 5 101 7106 LDIR LOAD INCREMENT AND REPEAT BYTE Operation Flags Addressing Mode 5 102 LDIR repeat until BC 0 begin DE lt HL DE 1 lt HL 1 15 0 lt 15 0 1 end This instruction is used for block transfers of strings of data The bytes of data at the location addressed by the HL register are loaded into memory starting at the location addressed
198. hese instructions are useful to manipulate the upper word of the register to be set in Word mode For example when doing data accesses other than 00000000H 0000FFFFH address range use this instruc tion to set data frame addresses This group of instructions is affected by the status ofthe LW bit in SR Select Register and Decoder Directives which specifies the operation mode in Word or Long Word Table 5 4 16 Bit and 32 Bit Load Exchange PUSH POP Group Instructions Instruction Name Format Note Exchange Word Long Word Registers EX dst src See Table 5 5 Exchange Byte Word Registers with Alternate Bank EXX Exchange Register Pair with Alternate Bank EX AF DE or HL Exchange Index Register with Alternate Bank Exchange All Registers with Alternate Bank EXALL Load Word Long Word Registers LD dst src See Table 5 6 LDW dst src See Table 5 6 POP POP dst See Table 5 7 PUSH PUSH src See Table 5 7 Swap Contents of D31 D16 and 015 00 SWAP dst dst BC DE HL IX or lY Table 5 5 Supported Source and Destination Combination for 16 Bit and 32 Bit Exchange Instructions Source Destination BC DE HL IX IY BC V NV N N DE y y y HL SP N y y DC 8297 03 Note are supported combinations The exchange structions which designate IY register as destination are covered by the other combinations These Exchange Word instructions are affected by Long Word mode 5 7
199. in the Table 5 18 below 5 18 On the bottom of the each instruction there are the field encodings if applicable For the cases which call out per convention then use the following encoding r Reg 000 B 001 C 010 D 011 100 H 101 L 111 A To form the opcode first look for the y field value for IX register which is 0 Then find field value for the C register which is 001 Replace y and field with the value from the table replace value with the real number The results being 76 543 210 11 011 101 DD 01 110 001 71 00 010 010 21 i in the execution time column indicates an read operation The time required for a read operation is shown in the Table 5 18 below in the execution time column indicates an I O write operation The time required for a write operation is shown in the Table 5 18 below All entries in the table below assume no wait states The number of wait states per operation must be added to these numbers DC 8297 03 2380 71 06 USER S MANUAL Table 5 18 Execution Time Operation Byte Word Word Long Long Long Long Long Sequence B W B B W W W B B B W B B B W B B B B Memory Read 3 4 3 4 5 6 5 6 7 8 7 8 7 8 9 10 Memory Write 0 1 0 1 2 3 2 3 4 5 4 5 4 5 6 7 Internal I O Read 3 4 N A N A N A N A N A N A N A Internal I O Write 0 1 N A N A N A N A N A N A N A 1X External I O Read 4 5 4 5 N A N A N A N A N A N A 1X External I O Write 1 2 1 2 N A
200. is if the operands are of different signs and the result is of the same sign as the source cleared otherwise Set Set if there is a borrow from the most significant bit of the result cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R CP A R 10111 r 2 RX CP A RX 11y11101 1011110w 2 IM CP 11111110 n 2 IR CP A HL 10111110 2 r X CP A XY d 11y11101 10111110 d 4 r Field Encodings r per convention y O for IX 1 for IY w Oforhigh byte 1 for low byte 5 34 DC 8297 03 71106 Operation Flags Addressing Mode R RX IM Field Encodings DC 8297 03 2380 USER S MANUAL CPW COMPARE WORD CPW HL src src R RX IM X HL 15 0 src 15 0 The source operand is compared with the HL register and the flags are set accordingly The contents of the HL register and the source are unaffected Two s complement subtraction is performed S Set if the result is negative cleared otherwise Z Setif the result is zero cleared otherwise Set if there is a borrow from bit 12 of the result cleared otherwise V Set if arithmetic overflow occurs that is if the operands are of different signs and the result is of the same sign as the source cleared otherwise Set if there is a borrow from the most significant bit of the result cleared otherwise Execute Syntax Instruction Format Time Note CPW HL R 11101101 101111rr 2 C
201. ise it is unaligned Multiple bus transactions which may be required to access multiple byte entities can be minimized if alignment is maintained The format of multiple byte data types is also shown in Figure 2 2 Note that when word is stored in memory the least significant byte precedes the more significant byte of the word as in the Z80 CPU architecture Also the lower addressed byte is present on the upper byte of the external data bus DC 8297 03 71106 DC 8297 03 2380 USER S MANUAL Bits within byte 16 bit word at address n Least Significant Byte Address n Most Significant Byte Address n 1 32 bit word at address n D7 0 Least Significant Byte Address n D15 8 Address n 1 D23 16 Address n 2 D31 24 Most Significant Byte Address n 3 Memory addresses Even address 0 0 Odd address 0 1 Least Significant Byte Most Significant Byte 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 2 2 Bit Byte Ordering Conventions 2 5 7106 2 5 EXTERNAL ADDRESS SPACE External I O address space is 4 Gbytes in size and External addresses are generated by instructions except those reserved for on chip address space accesses It Table 2 1 I O Addressing Options 2380 USER S MANUAL can take variety of forms as shown in Table 2 1 external I O read or write is always one transaction regard less of the bus size and the type of I O instruction Address Bus
202. ister The R register can be used as general purpose 8 bit read write register The R register is not associated with the refresh controller and its contents are changed only by the user 2 2 6 Stack Pointer The Stack Pointer SP is used for saving information when an interrupt or trap occurs and for supporting subroutine calls and returns Stack Pointer relative addressing allows parameter passing using the SP The SPis 16 bits wide but is extended by the SPz register to 32 bits wide 2 3 7106 2 2 6 Stack Pointer Continued Increment decrement of the Stack Pointer is affected by modes of operation Native or Extended In Native mode the stack operates in modulo 215 and in Extended mode itoperates in modulo 2 For example SP holds 0001FFFEH and does the Word size Pop operation After the operation 2 3 CPU CONTROL REGISTER SPACE The CPU control register space consists of the 32 bit Select Register SR The SR may be accessed as a whole or the upper three bytes of the SR may be accessed individually as YSR XSR and DSR In addition these 2 4 MEMORY ADDRESS SPACE The memory address space can be viewed as a String of 4 Gbytes numbered consecutively in ascending order The 8 bit byte is the basic addressable element in the 7380 MPU memory address space However there are other addressable data elements bits 2 byte words byte strings and 4 byte words The size of the data elementbeing addressed depends on
203. l is loaded into memory at consecutive addresses starting with the location addressed by the HL register and increasing During the I O transaction the 32 bit BC register is placed on the address bus Note that the B register contains the loop count for this instruction so that A 15 8 are not useable as part of a fixedport address First the byte of data from the selected peripheral is loaded into the memory location addressed by the HL register Then the B register used as a counter is decremented by one The HL register is then incremented by one thus moving the pointer to the next destination for the input If the result of decrementing the B register is 0 the instruction is terminated otherwise the sequence is repeated If the B register contains 0 at the start of the execution of this instruction 256 bytes are input This instruction can be interrupted after each execution of the basic operation The Program Counter value atthe start of this instruction is saved before the interrupt request is accepted so that the instruction can be properly resumed S Unaffected Z Set if the result of decrementing is zero cleared otherwise H Unaffected V Unaffected Set Unaffected Execute Syntax Instruction Format Time Note INIR 11101101 10110010 n X 2 i Ww 2380 USER S MANUAL DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 UsER s MANUAL INIRW INPUT INCREMENT AND REPEAT WORD I
204. lt is zero indicating a match cleared otherwise Setif there is a borrow from bit 4 of the last result cleared otherwise V Setifthe result of decrementing BC is not equal to zero cleared otherwise Set Unaffected Execute Syntax Instruction Format Time Note CPDR 11101101 10111001 3 r n X 5 37 7106 2380 User s MANUAL COMPARE AND INCREMENT BYTE Operation Flags Addressing Mode 5 38 CPI A HL if XM then begin HL 31 0 lt HL 31 0 1 end else begin HL 15 0 lt HL 15 0 1 end BC 15 0 lt 15 0 1 This instruction is used for searching strings of byte data The byte of data at the location addressed by the HL register is compared with the contents of the accumulator and the Sign and Zero flags are set to reflect the result of the comparison The contents of the accumulator and the memory bytes are unaffected Two s complement subtraction is performed Nextthe HL register is incremented by one thus moving the pointer to the next element in the string The BC register used as a counter is then decremented by one S Set if the result is negative cleared otherwise 7 Setifthe result is zero indicating that the contents of the accumulator and the memory byte are equal cleared otherwise Set if there is a borrow from bit 4 of the result cleared otherwise Set if the result of decrementing BC is not equal to zero cleared otherwise Set Unaffected
205. m 01 for LW 10 for 11 for XM 5 164 DC 8297 03 71106 Operation Flags Addressing Mode R IR 2380 USER S MANUAL SLA SHIFT LEFT ARITHMETIC BYTE SLA dst dst IR X tmp lt dst C lt dst 7 dst 0 0 dst n 1 lt tmp n forn 0to6 The contents of the destination operand are shifted left one bit position Bit 7 of the destination operand is moved to the Carry flag and zero is shifted into bit 0 of the destination 6 Set if the most significant bit of the result is set cleared otherwise Z Setif the result is zero cleared otherwise H Cleared P Setif parity of the result is even cleared otherwise N Cleared Set if the bit shifted from bit 7 was 1 cleared otherwise Execute Syntax Instruction Format Time Note SLA R 11001011 00100 r 2 SLA HL 11001011 00100110 2 r SLA XY d 11y11101 11001011 d 00100110 4 r l Field Encodings r per convention DC 8297 03 y O for IX 1 for IY 5 165 2380 7106 USER S MANUAL SLAW SHIFT LEFT ARITHMETIC WORD SLAW dst dst R RX IR X Operation tmp lt dst dst 0 lt 0 C lt dst 15 dst n 1 lt tmp n forn 0 to 14 The contents of the destination operand are shifted left one bit position The most significant bit of the destination operand is moved to the Carry flag and zero is shifted into bit 0 of the destination Flags 6 Set if the most significant bit of the result is set cleared otherwise Z
206. mory address is in the HL register The resulting three digit quantity is rotated to the left by one BCD digit four bits The lower digit of the source is moved to the upper digit of the source the upper digit of the source is moved to the lower digit of the accumulator and the lower digit of the accumulator is moved to the lower digit of the source The upper digit of the accumulator is unaffected In multiple digit BCD arithmetic this instruction can be used to shift to the left a string of BCD digits thus multiplying it by a power of ten The accumulator serves to transfer digits between successive bytes ofthe string This is analogous to the use of the Carry flag in multiple precision shifting using the RL instruction Flags S Set if the accumulator is negative after the operation cleared otherwise Z Set if the accumulator is zero after the operation cleared otherwise H Cleared P Setif the parity of the accumulator is even after the operation cleared otherwise N Cleared Unaffected Addressing Execute Mode Syntax Instruction Format Time Note RLD 11101101 01101111 3 r 5 150 DC 8297 03 71106 Operation Flags Addressing Mode R IR 2380 USER S MANUAL RR ROTATE RIGHT BYTE RR dst dst IR X tmp lt dst dst 7 lt C lt dst 0 dst n lt tmp n 1 forn 0106 The contents of the destination operand are concatenated with the Carry flag and together they are rotated right one bit position
207. mpo nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use Life support devices or Systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 Telex 910 338 7621 FAX 408 370 8056 Internet http www zilog com v Four formats are used to generate the machine language bit encoding for the 2380 CPU instructions Also the 2380 CPU has eight Decoder Directives which work as a special escape sequence to the certain instructions to expand its capability as explained in Chapter 3 The bit encoding of the Z380 CPU instructions are parti tioned into bytes Every instructions encoding contains one byte dedicated to specifying the type of operation to be performed this byte is referred to as the instruction s operation code or opcode Besides specifying a particu lar operation opcode typically include bit encoding speci fying the operand addressing mode for the instruction and identifying any general purpose registers used by the instruction Along with the opcode instruction encoding may include bytes that contain a
208. n Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R LD R n 00 r 110 n 2 RX LD RXin 11y11101 0010w110 n 2 IR LD HL n 00110110 n 3 w X LD XY d n 11y11101 00110110 d n 5 w Field Encodings r per convention y O for IX 1 for IY w Ofor high byte 1 for low byte DC 8297 03 5 83 7106 LD LOAD IMMEDIATE WORD LD dst nn dst R RX Operation if LW then begin dst 31 0 lt nn end else begin dst 15 0 lt nn end The word of immediate data is loaded into the destination Flags S Unaffected Z Unaffected Unaffected V Unaffected Unaffected Unaffected Addressing Mode Syntax Instruction Format R LD R nn 00rr0001 n low n high RX LD RX nn 11y11101 00100001 n low n high Field Encodings rr 00 for BC 01 for DE 10 for HL y O for IX 1 for IY 5 84 2380 USER S MANUAL Execute Time Note 2 LL 2 LL DC 8297 03 71106 Operation Flags Addressing Mode IR 2380 USER S MANUAL LDW LOAD IMMEDIATE WORD LDW dst nn dst IR if LW then begin dst 31 0 lt nn end else begin dst 15 0 lt nn end The word of immediate data is loaded into the destination S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected Unaffected Execute Syntax Instruction Format Time Note LDW IR
209. n if cc is TRUE then begin if XM then begin PC 31 0 dst 31 0 end else begin PC 15 0 lt dst 15 0 end end conditional jump transfers program control to the destination address if the setting selected flag satisfies the condition code specified in the instruction an unconditional jump always transfers control to the destination address If the jump is taken the Program Counter is loaded with the destination address otherwise the instruction following the Jump instruction is executed Each of the Zero Carry Sign and Overflow flags can be individually tested and jump performed conditionally on the setting of the flag When using DA mode with the JP instruction the operand is not enclosed in parentheses Flags S Unaffected Z Unaffected H Unaffected V Unaffected Unaffected C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note IR JP HL 11101001 2 X JP XY 11y11101 11101001 2 X DA JP CC addr 11 cc010 a low a high 2 I X JP addr 11000011 a low a high 2 LX Field Encodings y 0 for IX 1 for IY cc 000 for NZ 001 for Z 010 for NC 011 for C 100 for PO NV 101 for PE V 110 for P NS 111 for M S 5 80 DC 8297 03 71106 Operation Flags Addressing Mode RA Field Encodings DC 8297 03 2380 USER S MANUAL JR JUMP RELATIVE JR cc dst dst RA if cc is TRUE then begin dst SIGN EXTEND dst if XM then begin
210. n Exchange instruction is available for swapping the contents of the accumulator with another register or with memory as well as between registers Also exchange instructions are available which swap the contents of the register in the primary register bank and auxiliary register bank The instruction in this group does not affect the flags Table 5 2 8 Bit Load Group Instructions Instruction Name Format Note Exchange with Accumulator EX A r EX A HL Exchange r and r rr D E H or L Load Accumulator LD A src See Table 5 3 LD dst A See Table 5 3 Load Immediate LD dst n See Table 5 3 LD HL n See Table 5 3 Load Register Byte LD R src See Table 5 3 LD R HL See Table 5 3 LD dst R See Table 5 3 LD HL R See Table 5 3 Table 5 3 8 Bit Load Group Allowed Source Destination Combinations Source Dis A B C D E L XL n nn BC DE HL IX d IY d A 14 N N N N N N N N N N N N N B 4 N N N N N N 4 N N N N N 4 4 N N N N N 4 N N 4 N N D 4 NV N N N N 4 4 N N N E V NV N N N N N 4 N N N N N H NV NV N N N N N N N L NV N N N N N N N XH NV N N N N N ML N N YH NV ov N N NV NV N N N N N BC DE HL V V V N y nn v N Y d V N y Note Y are supported combinations 5 6 DC 8297 03 7106 5 5 2 16 Bit and 32 Bit Load
211. n about the precision of the result Also the Decimal Adjust Accumulator DAA instruction leaves the Carry flag set to 1 if a carry occurs when adding BCD quantities For rotate instructions the Carry flag is used as a link between the least significant and most significant bits for any register or memory location During shift instructions the Carry flag contains the last value shifted out of any register or memory location For logical instructions the Carry flag is cleared The Carry flag can also be set and complemented with explicit instructions 5 2 2 Add Subtract Flag N The Add Subtract flag is used for BCD arithmetic Since the algorithm for correcting BCD operations is different for addition and subtraction this flag is used to record when an add or subtract was last executed allowing a subse quent Decimal Adjust Accumulator instruction to perform correctly See the discussion of the DAA instruction for further information 5 2 3 Parity Overflow Flag P V This flag is set to a particular state depending on the operation being performed For signed arithmetic this flag when setto 1 indicates that the result of an operation on two s complement numbers has exceeded the largest number or less than the smallest number that can be represented using two s complement notation This overflow condition can be determined by examining the sign bits of the operands and the result The P V flag is also used with logical
212. n address displacement and or immediate value used by the instruction and spe cial bytes called escape codes that determine the mean ing of the opcode itself By themselves one byte opcode would allow the encoding of only 256 unique instructions Therefore special es cape codes that precede the opcode in the instruction encoding are used to expand the number of possible instructions There are two types of escape codes ad dressing mode and opcode Escape codes for the 780 original instructions are one bytes in length and the escape codes used to expand the Z380 instructions are one or two bytes in length These instruction formats are differentiated by the opcode escape value used Format 1 is for instructions without an opcode escape byte s Format2 is for instructions with an opcode escape byte Format 3 is for instructions whose opcode escape byte has the value OCBH and Format 4 is for instructions whose escape bytes are OED followed by OCBH USER s MANUAL APPENDIX 7380 CPU INSTRUCTION FORMATS For the opcode escape byte the 7380 CPU uses ODDH and OFDH as well which on the Z80 CPU these are used only as an address escape byte In Format 2 and 4 the opcode escape byte immediately precedes the opcode byte itself In Format 3 a 1 byte displacement may be between the opcode escape byte and opcode itself Opcode escape bytes are used to distinguish between two different in structions with the same opcod
213. n and Trap The Z380 MPU generates a Trap when an undefined opcode is encountered The action ofthe CPU in response to Trap is to jump to address 00000000H with the status bit s set This response is similarto the Z180 MPU s action on execution of an undefined instruction The Trap is enabled immediately after reset and it is not maskable This feature can be used to increase software reliability or to implement extended instructions An undefined op code can be fetched from the instruction stream or it can be returned as a vector in an interrupt acknowledge transaction in Interrupt mode 0 Since it jumps to address 00000000H it is necessary to have a Trap handling routine at the beginning of the program if processing is to proceed Otherwise it behaves justlike a resetforthe CPU For adetailed description refer to Chapter 6 DC 8297 03 5 5 7106 5 5 INSTRUCTION FUNCTIONAL GROUPS This section presents an overview of the Z380 instruction set arranged by functional groups See Section 5 5 for an explanation of the notation used in Tables 5 2 through 5 11 5 5 1 8 Bit Load Exchange Group This group of instructions Table 5 2 includes load instruc tions for transferring data between byte registers transfer ring data between byte register and memory and load ing immediate data into byte register or memory For the supported source destination combinations referto Table 5 3 2380 USER S MANUAL A
214. n is placed on the address bus Any bytes of address not specified in the instruction are driven on the address lines are all zeros S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Syntax OUTA nn A Instruction Format 11101101 11010011 n low n high 2380 USER S MANUAL OUTA OUTPUT DIRECT TO PORT ADDRESS BYTE Note 5 125 7106 OUTAW 2380 USER S MANUAL OUTPUT DIRECT TO PORT ADDRESS WORD Operation Flags Addressing Mode 5 126 OUT nn HL nn HL 15 0 The word of data from the HL register is loaded into the selected peripheral During the I O transaction the peripheral address from the instruction is placed on the address bus Any bytes of address not specified in the instruction are driven on the address lines are all Zeros S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Execute Syntax Instruction Format Time Note OUTAW nn HL 11111101 11010011 n low n high 2 0 DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL OUTD OUTPUT AND DECREMENT BYTE OUTD lt B 1 HL HL HL 1 This instruction is used for block output of strings of data During the transaction the 32 bit BC register is placed on the address bus Note that the B register contains the loop count for this instruction so that A15 A8 are not useable as par
215. n the two operands are different otherwise a 0 bit is stored The contents of the source are unaffected Flags S Setifthe most significant bit of the result is set cleared otherwise Z Setif all bits of the result are zero cleared otherwise H Cleared P Setifthe parity is even cleared otherwise Cleared C Cleared Addressing Execute Mode Syntax Instruction Format Time R XOR 10101 r 2 RX XOR A RX 11y11101 1010110w 2 IM XOR A n 11101110 n 2 IR XOR A HL 10101110 2 r X XOR A XY d 11 11101 10101110 d 4 r Field Encodings DC 8297 03 per convention y O for IX 1 for IY w for high byte 1 for low byte Note 5 179 2380 7106 USER S MANUAL XORW EXCLUSIVE OR WORD XORW src X HL 15 0 lt 15 0 src 15 0 A logical EXCLUSIVE OR operation is performed between the corresponding bits of the source operand and the HL register and the result is stored in the HL register A 1 bitis stored wherever the corresponding bits in the two operands are different otherwise a 0 bitis stored The contents of the source are unaffected Flags S Set if the most significant bit of the result is set cleared otherwise Z Setif all bits of the result are zero cleared otherwise H Cleared P Setifthe parity is even cleared otherwise N Cleared C Cleared Addressing Execute Mode Syntax Instruction Format Time Note R XORW HL R
216. n undefined opcode is returned as vector in an Interrupt acknowledge transaction in mode 0 TV can be reset under program control by writing it with a logic 0 However it cannot be written with a logic 1 See Figure 6 3 6 3 TRAP INTERRUPT The Z380 MPU generates a Trap when an undefined opcode is encountered The Trap is enabled immediately after reset and itis not maskable This feature can be used to increase software reliability or to implement extended instructions An undefined opcode can be fetched from the instruction stream or it can be returned as a vector in an Interrupt acknowledge transaction in Interrupt Mode 0 When a Trap occurs the Z380 MPU operates as follows 1 The TForTVbitinthe Assigned Vectors Base and Trap Register goes active to indicate the source of the undefined opcode 2 Ifthe undefined opcode was fetched from the instruc tion stream the starting address of the Trap causing the instruction is pushed onto the stack Note that the starting address of decoder directive s preceding an instruction encoding is considered the starting ad dress of the instruction 2380 USER S MANUAL 00000019 R W 7 0 ES ER ESTEE EI E 0 0 0 0 0 0 0 O Reset Value Trap on Interrupt Vector Trap on Instruction Fetch Reserved Program as 0 Read as 0 Figure 6 3 Trap and Break Register If the undefined opcode was a returned Interrupt vector the interrupted PC value is pushed onto
217. naffected V Unaffected N Unaffected C Unaffected Execute Syntax Instruction Format Time Note MLT R 11101101 01rr1100 7 Field Encodings rr 00 for BC 01 for DE 10 for HL 11 for SP 5 104 DC 8297 03 2380 71 06 USER S MANUAL MTEST MODE TEST MTEST Operation S lt SR 7 Z lt SR 6 lt SR 1 The three mode control bits in the Select Register SR are transferred to the flags This allows the program to determine the state of the machine Flags S Setif Extended mode is in effect cleared otherwise Z Setif Long word mode is in effect cleared otherwise H Unaffected V Unaffected Unaffected C Setif Lock mode is in effect cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note MTEST 11011101 11001111 2 DC 8297 03 5 105 2380 7106 USER S MANUAL MULTW MULTIPLY WORD MULTW src RX IM X HL 31 0 lt HL 15 0 x src 15 0 The contents of the HL register are multiplied by the source operand and the product is stored in the HL register The contents of the source are unaffected Both operands are treated as signed two s complement integers The initial contents of the HL register are overwritten by the result The Carry flag is set to indicate that the upper word of the HL register is required to represent the result if the Carry flag is cleared the product can be correctly represented in 16 bits and the upper word of the HL re
218. nd 15 arithmetic shifts The operand can be aregister pair or memory location specified by the Indirect Register or Indexed addressing mode as shown below Table 5 12 16 Bit Rotate and Shift Group Instruction Name Format BC Rotate Left Word RLW dst Rotate Left Circular Word dst Rotate Right Word RRW dst Rotate Right Circular Word RRCW dst N Shift Left Arithmetic Word SLAW dst Shift Right Arithmetic Word SRAW dst Shift Right Logical Word SRLW DC 8297 03 Destination DE HL HL HL IX d IY d V NV V NV N V NV V 4 V NV V NV NV V NW N V NV V NV N V NV V NV NV V NW N V NV V NV NV V N N V NV V NV NV V N N 5 11 2100 5 5 8 Program Control Group This group of instructions Table 5 13 affect the Program Counter and thereby control program flow The CPU registers and memory are not altered except for the Stack Pointer and the Stack which play a significant role in procedures and interrupts An exception is Decrement and Jump if Non Zero DJNZ which uses register as loop counter The flags are also preserved except for the two instructions specifically designed to set and comple ment the Carry flag The Set Reset Condition flag instructions can be used with Conditional Jump conditional Jump Relative Conditional Call and Conditional Return instructions to control the program flow The Jump and Jump Relative JR instructions provide a conditional tr
219. ndix Appendix covers the Z380 s instruction format Appendix B Appendix B contains all Z380 instructions sorted in Alphabetical Order Appendix C Appendix C contains all Z380 instructions sorted in Numerical Order Appendix D The Tables in Appendix D lists all the 2380 instructions in instruction affected by Native Extended mode and Word Long Word mode Appendix E The Tables in Appendix lists all the 2380 instructions in instruction affected by DDIR IM Immediate Decoder Directives mode Index A to Z listing of Z380 User s Manual key words and phrases This manual assumes the reader has a basic knowledge of CPU based system architectures and software development systems such as the use of the text editor and invoking the assembler compiler Also knowledge of the 280 CPU architecture is desirable O 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc The information in this document is subject to change without notice Devices sold by Zilog Inc are covered by warranty and patent indemnification provisions appearing in Zilog Inc Terms and Conditions of Sale only ZILOG INC MAKES NO WARRANTY EXPRESS STATUTORY IMPLIED OR BY DESCRIPTION REGARDING THE INFORMA TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT
220. nn 11101101 00pp0110 n low n high 3 w LL Field Encodings 00 for BC 01 for DE 11 for HL DC 8297 03 5 85 7106 LD LOAD REGISTER BYTE LD dst src dst R src R RX IM IR X or dst R RX IR X src R Operation dst src The contents of the source are loaded into the destination Flags S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected Unaffected Load into Register 2380 USER S MANUAL Addressing Execute Mode Syntax Instruction Format Time Note R LD Rd Rs 01 rd rs 2 RX LD Rd RX 11y11101 01 ratOw 2 LD RXa RXb 11y11101 0110a10b 2 IM LD R n 00 r 1 10 n 2 IR LD R HL 01 r 110 5 w X LD R XY d 11y11101 01 r 110 d 74W Load from Register Addressing Execute Mode Syntax Instruction Format Time Note RX LD RX Rs 11y11101 0110w ra 2 LD RXa RXb 11y11101 0110a10b 2 IR LD HL R 01110 r 3 w X LD XY d R 11y11101 01110 r d 5 W Field Encodings r per convention rd per convention rs per convention y O for IX 1 for IY w Oforhigh byte 1 for low byte ra per convention for A B C D E only a destination 0 for high byte 1 for low byte b source 0 for high byte 1 for low byte 5 86 DC 8297 03 71106 Operation Flags Load into Register Addressing Mode R RX IR DA SR DC 8297 03 LD W dst src dst R src R RX IR DA X SR or dst R RX IR DA X SR src if LW then be
221. nting the pointers ensures that the source string is copied without destroying the overlapping area This instruction can be interrupted after each execution of the basic operation The Program Counter value of the start of this instruction is saved before the interrupt request is accepted so that the instruction can be properly resumed Unaffected Unaffected Cleared Cleared Cleared Unaffected Flags Addressing Execute Mode Syntax Instruction Format Time Note LDDRW 11101101 11111000 NX 3 r w L DC 8297 03 5 99 7106 LDI 2380 USER S MANUAL LOAD AND INCREMENT BYTE Operation Flags Addressing Mode 5 100 LDI DE HL DE DE 1 HL HL 1 BC 15 0 lt 15 0 1 This instruction is used for block transfers of strings of data The byte of data at the location addressed by the HL register is loaded into the location addressed by the DE register Both the DE and HL registers are then incremented by one thus moving the pointers to the next elements in the string The BC register used as a counter is then decremented by one S Unaffected Z Unaffected H Cleared V Set if the result of decrementing BC is not equal to zero cleared otherwise Cleared Unaffected Execute Syntax Instruction Format Time Note LDI 11101101 10100000 3 r W DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL LDIW LOAD AND INCREMENT WORD LDIW if LW t
222. odes are discussed in relation to the instruction set Then the interpretability of instructions and trap are discussed The last part of this chapter is a detailed description of each instruction listed in alphabeti cal order by mnemonic This section is intended as a reference for Z380 CPU programmers The entry for each instruction contains a complete description of the instruc tion including addressing modes assembly language mnemonics and instruction opcode formats The Flag register provides a link between sequentially executed instructions in that the result of executing one instruction may alter the flags and the resulting value ofthe flags can be used to determine the operation of a subse quent instruction The program control instructions whose operation depends on the state of the flags are the Jump Jump Relative subroutine Call Call Relative and subrou tine Return instructions these instructions are referred to as conditional instructions 5 1 ZiLoG 5 2 1 Carry Flag C The Carry flag is setorcleared depending onthe operation being performed For add instructions that generate a carry and subtract instruction generating a borrow the Carry flag is setto 1 The Carry flag is cleared to 0 by an add that does not generate a carry or a subtract that generates no borrow This saved carry facilitates software routines for extended precision arithmetic The multiply instructions use the Carry flag to signal informatio
223. of all locations in the main memory 2 2 CPU REGISTER SPACE The Z380 register file is illustrated in Figure 2 1 Note that this figure shows the configuration of the register on the Z380 CPU and the number ofthe register files may vary on future Superintegration devices The Z380 CPU contains abundant register resources At any given time the pro gram has immediate access to both primary and alternate registers in the selected register set Changing register sets is a simple matter of an LDCTL instruction to program the Select Register SR The CPU register file is divided into five groups of registers an apostrophe indicates a register in the auxiliary regis ters Four sets of Flag and Accumulator registers F A A gm Four sets of Primary and Working registers B C D E H L LP DC 8297 03 USER s MANUAL CHAPTER 2 ADDRESS SPACES m External I O Address Space This consists of all external I O ports addresses through which peripheral devices are accessed m On Chip I O Address Space This consists of all internal I O port addresses through which peripheral devices are accessed Also this addressing space contains registers to control the functionality of the device giving status information m Four sets of Index registers IX IY IX m Stack Pointer SP m Program Counter Interrupt register Refresh register PC I R Register addresses are either specified
224. of an interrupt request When this bit is set interrupts are enabled when this bit is cleared interrupts are disabled Reset clears this bit 5 3 10 Interrupt Mode IM This 2 bit field controls the interrupt mode for the INTO interrupt request These bits are controlled by the IM instructions 00 IM 0 01 IM 1 10 IM 2 11 IM 3 Reset clears both of these bits selecting Interrupt Mode 0 2380 UsER s MANUAL 5 3 11 Lock LCK This bit controls the Lock Unlock status of the Z380 CPU This bit is set by the SETC LCK instruction and cleared by the RESC LCK instruction When this bit is set no bus requests will be accepted providing exclusive access to the bus by the Z380 CPU When this bitis cleared the 2380 CPU will grant bus requests in the normal fashion Reset Clears this bit 5 3 12 AF or AF Register Select This bit controls and reports whether AF or is the currently active pair of registers AF is selected when this bitis cleared and is selected when this bitis set Reset Clears this bit selecting AF 5 4 INSTRUCTION EXECUTION AND EXCEPTIONS Three types of exception conditions interrupts trap and Reset can alter the normal flow of program execution Interrupts are asynchronous events generated by adevice external to the CPU peripheral devices use interrupts to request service from the CPU Trap is asynchronous event generated internally in the CPU by executing undefined instru
225. of the source are unaffected S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Execute Syntax Instruction Format Time Note PUSH SR 11101101 11000101 34w L 5 135 7106 PUSH 2380 USER S MANUAL PUSH IMMEDIATE Operation Flags Addressing Mode IM 5 136 PUSH src src IM if LW then begin SP lt SP 4 SP lt src 7 0 SP 1 lt src 15 8 SP 2 lt src 23 16 SP 3 lt src 31 24 end else begin SP lt SP 2 SP e src 7 0 SP 1 lt src 15 8 end The Stack Pointer SP is decremented by two by four in Long Word mode and the source is loaded into the memory locations addressed by the SP in ascending byte order in ascending address memory locations S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Execute Syntax Instruction Format Time Note PUSH nn 11111101 11110101 n low n high 3 w LL DC 8297 03 71106 Operation Flags Addressing Mode R RX Field Encodings DC 8297 03 PUSH src src R RX if LW then begin SP SP SP 1 SP 2 SP 3 lt end else begin SP SP SP 1 end SP 4 src 7 0 src 15 8 src 23 16 src 31 24 SP 2 src 7 0 src 15 8 2380 USER S MANUAL PUSH PUSH REGISTER The Stack Pointer SP is decremented by two by four in Long Word mode and the source is loaded into the memory locations addressed by th
226. og prior to use Life support devices or systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 Telex 910 338 7621 FAX 408 370 8056 Internet http www zilog com DC 8297 03 2 7 lt 3 1 INTRODUCTION Z380 CPU architecture allows access to 4 Gbytes 232 of memory addressing space and 4G locations of I O It offers 16 32 bit manipulation capability while main taining object code compatibility with the Z80 CPU In order to implement these capabilities and new instruction sets it has two modes of operation for address manipula tion Native or Extended mode two modes of operation for data manipulation Word or Long Word mode and special set of new Decoder Directives On Reset the 2380 CPU defaults in Native mode and Word mode Inthis condition it behaves exactly the same as the 280 CPU even though it has access to the entire 4 Gbytes of memory for data access and 4G locations of I O space Native Z80 Native Mode USER s MANUAL CHAPTER 3 NATIVE EXTENDED MODE WORD LONG WORD MODE OF OPERATIONS AND DECODER DIRECTIONS access to the newly added registers
227. on S Set if the accumulator is negative after the operation cleared otherwise 27 Set if the accumulator is zero after the operation cleared otherwise H Cleared P Setif the parity of the accumulator is even after the operation cleared otherwise N Cleared Unaffected Execute Syntax Instruction Format Time Note RRD 11101101 01100111 3 r 5 157 2380 7106 USER S MANUAL RST RESTART RST address Operation if XM then begin SP lt SP 4 SP lt 7 0 SP 1 lt PC 15 8 SP 2 lt 23 16 SP 3 lt 31 24 else begin SP SP 2 SP lt 7 0 SP 1 lt PC 15 8 end PC lt address The current Program Counter is pushed onto the stack and the is loaded with a constant address encoded in the instruction Execution then begins at this address The restart instruction allows for a call to one of eight fixed locations as shown in the table below The table also indicates the encoding of the address used in the instruction encoding The address is in hexadecimal the encoding in binary Address t encoding 00000000h 000 00000008h 001 00000010h 010 00000018h 011 00000020h 100 00000028h 101 00000030h 110 00000038h 111 Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Flags Addressing Execute Mode Syntax Instruction Format Time Note RST address 11 1 111 4 w X Field Encodings 000 for 00h 001 for 08h 010 for 10h 011 for 18h 100 for 20h
228. operations and rotate instructions to indicate the parity of the result The of bits setto 1 inabyte are counted If the total is odd this flag is reset indicates odd parity P 0 If the total is even this flag is set indicates even parity P 1 During block search and block transfer instructions the P V flag monitors the state of the Byte Count register BC When decrementing the byte counter results in a zero value the flag is cleared to 0 otherwise the flag is set to 1 2380 User s MANUAL During Load Accumulator with I or R register instruction the P V flag is loaded with the IEF2 flag For details on this topic refer to Chapter 6 Interrupts and Traps When a byte is inputted to a register from an device addressed by the C register the flag is adjusted to indicate the parity of the data 5 2 4 Half Carry Flag H The Half Carry flag H is setto 1 or cleared to 0 depending on the carry and borrow status between bits 3 and 4 of an 8 bit arithmetic operation and between bits 11 and 12 ofa 16 bit arithmetic operation This flag is used by the Deci mal Adjust Accumulator instruction to correct the result of an addition or subtraction operation on packed BCD data 5 2 5 Zero Flag Z The Zero flag Z is set to 1 if the result generated by the execution of certain instruction is a zero For arithmetic and logical operations the Zero flag is set to 1 if the result is zero If the result is not zero the
229. or IX 1 for IY DC 8297 03 2380 5 133 7106 PUSH PUSH ACCUMULATOR PUSH src src AF Operation if LW then begin SP lt SP 4 SP lt F SP 1 SP 2 lt 008 SP 3 lt 008 else begin SP lt 5 SP lt SP 1 The Stack Pointer SP is decremented by two by four in Long Word mode and the source is loaded into the memory locations addressed by the SP in ascending byte order in ascending address memory locations For this instruction the Flag register is the least significant byte followed by the Accumulator The other two bytes written in the Long Word mode are all zeros The Flag register and Accumulator are unaffected 2380 USER S MANUAL Flags S Unaffected Z Unaffected H Unaffected V Unaffected Unaffected C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note PUSH AF 11110101 3 w L 5 134 DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL PUSH PUSH CONTROL REGISTER PUSH src src SR if LW then begin SP lt SP 4 SP e src 7 0 SP 1 lt src 15 8 SP 2 lt src 23 16 SP 3 lt src 31 24 end else begin SP lt SP 2 SP e src 7 0 SP 1 lt src 15 8 end The Stack Pointer SP is decremented by two by four in Long Word mode and the source is loaded into the memory locations addressed by the SP in ascending byte order in ascending address memory locations The contents
230. or is adjusted to form two 4 bit BCD digits following binary two s complement addition or subtraction on two BCD encoded bytes The table below indicates the operation performed for addition ADD ADG ING or subtraction SUB SBC DEG Before DAA Syntax DAA Hex Value Upper Digit Bits 7 4 0 9 0 8 0 9 A F 9 F A F 0 2 0 2 0 3 0 9 0 8 7 6 F Instruction Format H Before DAA 00 00 00 00100111 Value Lower Digit Bits 3 0 0 9 A F 0 3 0 9 A F 0 3 0 9 A F 0 3 Number Added to Byte Execute Time 3 After DAA 000 400 Set if the most significant bit of the result is set cleared otherwise Set if the result is zero cleared otherwise See table above Set if the parity of the result is even cleared otherwise Not affected See table above H After O QO O OO O 2380 USER S MANUAL DC 8297 03 2380 7106 USER S MANUAL DDIR DECODER DIRECTIVE DDIR mode mode W or LW IB or IW Operation None decoder directive only This is not an instruction but rather a directive to the instruction decoder The instruction decoder may be directed to fetch an additional byte or word of immediate data or address with the instruction as well as tagging the instruction for execution in either Word or Long Word mode All eig ht combinations of the two options are supported
231. pace as well as 4 Gbytes of addressing area without using a Memory Banking scheme or MMU 1 3 3 Enhanced Instruction Set with 16 Bit and 32 Bit Manipulation Capability The Z380 CPU instruction set is 100 upward compatible to the Z80 CPU instruction set that is all the Z80 instruc tions have been preserved at the binary level New instruc tions added to the Z380 CPU include m Less restricted operand source destination combinations m More flexible register exchange instructions m Stack Pointer Relative addressing mode 1 5 7106 1 3 3 Enhanced Instruction Set with 16 Bit and 32 Bit Manipulation Capability Continued m DDIR Decoder Directive Instructions to enhance addressing capability to cover 4 Gbytes of memory space as well as data manipulation capability Jump relative Call relative instructions with 8 bit 16 bit or 24 bit displacement Full complements of 16 bit arithmetic instructions 32 bitmanipulate instructions for address manipulation These new instructions help to compact the code as well as shorten the program s overall execution speed For details on this subject refer to Chapter 5 Instruction Set 1 3 4 Faster Context Switching The Z380 CPU architecture allows multiple sets of register banks for AF AF BC DE HL BC DE HL 1 4 SUMMARY The Z380 CPU is a high performance 16 bit Central Pro cessing Unit Superintegration core Code compatible wi
232. pe Source Code Mode Object Code X FD 2B IYL FD 2D IYU FD 25 L 2D SP X 3B BC X 0B DE X 1B HL X 2B IX X DD 2B IY X FD 2B SP X 3B 1FH DD F3 1F F3 IX 12H 1 DD 12 IV 12H 1 FD 12 1234H ED CB BF BC ED 8 ED 9 ED BB HL IX 12H I DD 12 12 FD CB 12 HL 1234H ED CB BF HL BC ED CB B8 HL DE ED CB 9 HL HL ED CB BB HL IX ED CB BC HL IY ED CB BD IX ED CB BC IY ED CB BD 123456H X FD 10 56 1234H X DD 10 34 12H X 10 12 1FH DD FB 1F FB CB DD ED FD ED CB DD CB FD CB SP HL L SP IX L DD SP IY L FD A HL ED 37 ED 37 07 A C ED OF A D ED 17 A E ED 1F 27 ED 2F AF 08 34 12 12 Source Code 2 2 2 gt lt gt lt gt lt 205220 BC BC BC DE BC HL BC IX BC IY GE D D DEDE DE HL DE IX DE IV HL HL HL IY IXY IY Y L L gt gt ENN T N I 12131300 quor 12 A 1234H HL 1234H HL IX 12H IY 12H A Mode Object Code 31 33 34 35 12 12 meu wovon nne Source Code Mode Object Code Source Code Mode Object Code INC B 04 JR X 38 12 INC BC X 03 JR NC 123456H X FD 30 56 34 12
233. pt requests Instruc tion fetching and execution restarts at memory location 00000038H DC 8297 03 6 5 3 Interrupt Mode 2 Response for Maskable Interrupt INTO Interrupt Mode 2 is a vectored Interrupt response mode wherein the interrupting device identifies the starting loca tion of service routine using an 8 bit vector read by the CPU during the Interrupt acknowledge cycle During the Interrupt acknowledge transaction the external I O device being acknowledged is expected to output a vector onto the upper portion of the data bus D15 D8 The interrupted PC value is pushed onto the stack and and IEF2 are reset to logic 0 so as to disable further maskable interrupt requests The size of the PC value pushed onto the stack is depends on Native one word or Extended mode two words in effect The Z380 MPU then reads an entry from a table residing in memory and loads itinto the PC to resume execution The address of the table entry is composed of the Extend Iz contents as A31 A16 the Register contents as A15 A8 and the vector supplied by the I O device as 7 0 Note that the table entry is effectively the starting address of the interrupt service routine designed for the I O device being acknowledged and the table composing of starting addresses for all the Interrupt Mode 2 service routines can be referred to as the Interrupt Mode 2 vector table Each table entry should be word sized if the 7380 MPU isin the Native mode
234. putation is done in modulo 232 REGISTER OPERAND MEMORY Example of mode 1 Load accumulator from location IX 1 in Native mode LD A IX 1 Load into the accumulator the contents of the memory location whose address is one less than the contents of IX Assume it is in Native mode A IXz 0001 0001 Before instruction execution 01 After instruction execution 23 Memory location Address calculation In Native mode OFFH encoding in the instruction is sign extended to a 16 bit value before the address calculation but calculation is done in modulo 219 and does not take into account the index register s extended portion 4 4 0001FFFF 23 AX 0000 0000 0000 FFFF DC 8297 03 7106 Load accumulator from location IX 1 in Extended mode SETC XM Set Extended mode LD A IX 1 Load into the accumulator the contents of the memory location whose address is one less than 2380 USER S MANUAL the contents of IX A 2 IX Before instruction execution 01 0001 0000 After instruction execution 23 0001 0000 Memory location 0000FFFF 23 Address calculation In Extended mode OFFH encoding in 00010000 the instruction is sign extended to a 32 bit value before the FFFFFFFF address calculation but calculation is done in modulo 23 0000FFFF and takes into account the index registers extended portion 4 2 6 Program Counter Relative Mode RA The Program Counter Relativ
235. quests cannot be granted until after the instruction has been executed and that one or more of the succeeding instructions may also have been fetched for decoding before this instruction has been executed When reseting Long Word mode LW the LW bit bit 6 in the SR is set to 0 selecting 16 bit words When using 16 bit words all word load operations transfer 16 bits Flags S Unaffected 7 Unaffected H Unaffected V Unaffected Unaffected Unaffected Addressing Execute Mode Syntax Instruction Format Time Note RESC mode 11mm1101 11111111 4 Field Encodings 01 for LW 10 for LCK DC 8297 03 5 139 2380 7106 USER S MANUAL RET RETURN RET cc Operation if cc is TRUE then begin if XM then begin PC 7 0 SP PC 15 8 SP 1 PC 23 16 lt SP 2 PC 31 24 SP 3 SP SP 4 else begin PC 7 0 SP PC 15 8 SP 1 SP lt SP 2 This instruction is used to return to a previously executing procedure at the end of a procedure entered by a Call instruction Fora conditional return one of the Zero Carry Sign or Parity Overflow flags is checked to see if its setting matches the condition code cc encoded in the instruction if the condition is not satisfied the instruction following the Return instruction is executed otherwise a value is popped from the stack and loaded into the Program Counter PC thereby specifying the location of the next instruc
236. r on the data bus while this internal write is occurring The peripheral address is placed on the low byte of the address bus and zeros are placed on all other address lines The byte of data from the memory location addressed by the HL register is loaded to the on chip I O port addressed by the C register The register holding the port address is incremented by one to selectthe next output port The B register used as a counter is then decremented by one The HL register is then incremented by one thus moving the pointer to the next source for the output If the result of decrementing the B register is 0 the instruction is terminated otherwise the output sequence is repeated Note that if the B register contains 0 at the start of the execution of this instruction 256 bytes are output This instruction can be interrupted after each execution ofthe basic operation The Program Counter value atthe start of this instruction is saved before the interrupt request is accepted so that the instruction can be properly resumed S Cleared Z Set H Cleared P Set N Setif the most significant bit of the byte transferred was 1 cleared otherwsie C Cleared Execute Syntax Instruction Format Time Note OTIMR 11101101 10010011 2 r 0 2380 USER S MANUAL DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL OTIR OUTPUT INCREMENT AND REPEAT BYTE OTIR repeat until B 0 begin lt B
237. rpose 16 bit wide registers originally on the Z80 have been expanded to 32 bits wide along withthe sup port ofthe arithmetic instruction needed for 32 bit address manipulation Bits are fully supported and addressed by number within a byte see Figure 2 2 Bits within byte registers or memory locations can be tested set or cleared 2380 USER S MANUAL Operation on binary coded decimal BCD digits are sup ported by Decimal Adjust Accumulator DAA and Rotate Digit RLD and RRD instructions BCD digits are stored in byte registers or memory locations two per byte The DAA instruction is used after a binary addition or subtraction of BCD numbers Rotate Digit instructions are used to shift BCD digit strings in memory Strings of up to 65536 64K bytes of Byte data or Word data can be manipulated by the Z380 CPU s block move block search and block I O instructions The block move instructions allow strings of bytes words in memory to be moved from one location to another Block search instruc tions provide for scanning strings ofbytes words in memory to locate a particular value Block instructions allow strings of bytes or words to be transferred between memory and a peripheral device Arrays are supported by Indexed mode with 8 bit 16 bit or 24 bit displacement Stack is supported by the Indexed and the Stack Pointer Relative addressing modes and by special instructions such as Call Return Push and Pop
238. ry Call instructions but with Relative address An 8 bit 16 bit or 24 bit offset value can be used and that allows to call procedure within the range of 126 to 129 bytes 8 bit offset CALR cc e 32765 to 32770 bytes 16 bit offset CALR cc ee or 8388604 to 8388611 bytes JR cc eee are supported These instructions are really useful to program relocatable programs Jump is available with Indirect Register mode in addition to Direct Address mode It can be useful for implementing complex control structures such as dispatch tables When using Direct Address mode for a Jump or Call the operand is used as an immediate value that is loaded into the PC to specify the address of the next instruction to be executed The conditional Return instruction is a companion to the call instruction if the condition specified in the instruction is satisfied it loads the PC from the stack and pops the stack A special instruction Decrement and Jump if Non Zero DJNZ implements the control part of the basic Pascal FOR loop which can be implemented in an instruction It supports 8 bit 16 bit and 24 bit displacement Note that Jump Relative Call Relative and DJNZ instruc tions use modulo 218 in Native mode and 2 in Extended mode for address calculation So it is possible that the Z380 CPU can jump to an unexpected address Table 5 13 Program Control Group Instructions Instruction Name Format nn PC d HL IY C
239. s The SR was shown in Figure 5 2 YSR 5 gt XSR Reserved 0 31 30 29 28 27 26 25 24 IYBANK IYP Reserved 0 IXBANK IXP 23 22 21 20 19 18 17 16 Reserved 0 MAINBAN 15 14 13 12 11 10 9 Pee 111 8 7 6 5 4 3 2 1 0 Figure 5 2 Select Register 5 3 1 IY Bank Select IYBANK This 2 bit field selects the register set to be used for the IY and registers This field can be set independently of the register set selection for the other Z380 CPU registers Reset selects Bank 0 for IY and 5 3 2 IY or Register Select This bit controls and reports whether or is the currently active register IY is selected when this bit is cleared and IY is selected when this bit is set Reset clears this bit selecting IY 5 3 3 IX Bank Select This 2 bit field selects the register set to be used for the IX and IX registers This field can be set independently of the register set selection for the other Z380 CPU registers Reset selects Bank 0 for IX and IX 5 3 4 IX or IX Register Select This bit controls and reports whether IX or is the currently active register IX is selected when this bit is cleared and is selected when this bit is set Reset Clears this bit selecting IX 5 4 5 3 5 Main Bank Select MAINBANK This 2 bit field selects the register set to be used for the A BC DE HL A F BC DE and HL r
240. s dis placements or immediate data In Table A 1 through A 4 A esc A esc A esc A esc ween v nne the symbol is used to indicate the presence of an addressing mode escape byte O esc is used to indicate the presence of an opcode escape byte disp is an abbreviation for displacement and addr is an abbrevia tion for address Table A 1 Format 1 Instructions Encodings Instruction Format Opcode Opcode Opcode Opcode Opcode Opcode Opcode Opcode 2 byte Address 1 byte Displacement Immediate 2 byte Address 1 byte Displacement Immediate 1 byte Displacement Immediate Assembly Hexadecimal LD A C 79 LD A addr 3A addr L addr H DJNZ addr 10 disp LD 1 LD IX addr DD 2A addr L addr H LD A IX d DD 7E disp LD IX nn DD 21 n L n H LD IY d n FD 36 d n Note A esc is an addressing mode escape byte and either ODDH or O esc O esc O esc O esc O esc O esc Note O esc is an opcode escape byte and either ODDH OEDH or OFDH A esc Table A 2 Format 2 Instructions Encodings Instruction Format Opcode Opcode Opcode Opcode Opcode Opcode Opcode CB CB Immediate 1 byte Immediate 2 bytes Address 2 bytes Displacement 1 byte Displacement 2 bytes Displacement 3 bytes Assembly Hexadecimal LD A C 79 TST ED 64 n LD BC nn ED 06 n L n H LD BC addr ED 4B addr L addr H CALR e ED CD e JR ee DD 18 d L
241. s in the currently executing program and to generate relative addresses The PC contains the 32 bit address of the current instruction being fetched from memory In Native mode the PC is effectively only 16 bits long since the upper word PC31 PC16 of the PC is forced to zero and when carried from bit 15to bit 16 Lower word PC15 PCO to Upper word PC31 PC16 are inhib ited in this mode In Extended mode the PC is allowed to increment across all 32 bits 2 2 5 R Register The R register can be used as general purpose 8 bit read write register The R register is not associated with the refresh controller and its contents are changed only by the user 2 2 6 Stack Pointer The Stack Pointer SP is used for saving information when an interrupt or trap occurs and for supporting subroutine calls and returns Stack Pointer relative addressing allows parameter passing using the SP The SPis 16 bits wide but is extended by the SPz register to 32 bits wide 2 3 7106 2 2 6 Stack Pointer Continued Increment decrement of the Stack Pointer is affected by modes of operation Native or Extended In Native mode the stack operates in modulo 215 and in Extended mode itoperates in modulo 2 For example SP holds 0001FFFEH and does the Word size Pop operation After the operation 2 3 CPU CONTROL REGISTER SPACE The CPU control register space consists of the 32 bit Select Register SR The SR may be accessed as a whole or t
242. s or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use Life support devices or systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 Telex 910 338 7621 FAX 408 370 8056 Internet http www zilog com USER s MANUAL v APPENDIX E INSTRUCTIONS AFFECTED BY DDIR IM INSTRUCTIONS Table E 2 Valid with DDIR IB XM bit status does not affect the operation Transfer size determined by LW bit Either with DDIR IB DDIR IB LW or DDIR IB W This Appendix has instructions which can be used with the Decoder Directive s Extend Immediate There are eight tables E1 E8 which are the subset of the Table A sorted by the category of the instruction LD 123456H BC ED 43 56 34 12 Note that the instructions listed here does not have the LD 123456H DE ED 53 56 34 12 DDIR Decoder Directive in front of the instructions listed LD 123456 HL 22 56 34 12 below and notation used here may be different by the LD 123456 HL ED 63 56 34 12 assembler to be used LD 123456H IX DD 22 56 34 12 LD 123456 FD 22 56 34 12 Table 1 Valid with
243. ssigned to this address ing space as a part of the 7380 CPU core 2 6 Register Name Internal I O Address Interrupt Enable Register 17H Assigned Vector Base Register 18H Trap and Break Register 19H Chip Version ID Register OFFH The Chip Version ID register returns one byte data which indicates the version of the CPU or the specific implemen tation of the Z380 CPU based Superintegration device Currently the value 00H is assigned to the Z380 MPU and other values are reserved For the other three registers refer to Chapter 6 Interrupts and Traps Also the Z380 MPU has registers to control chip selects refresh waits and clock divide to Internal I O address OOH to 10H For these registers refer to the Z380 MPU Product specification DC 3003 01 DC 8297 03 7106 2380 USER S MANUAL O 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc The information in this document is subject to change without notice Devices sold by Zilog Inc are covered by warranty and patent indemnification provisions appearing in Zilog Inc Terms and Conditions of Sale only ZILOG ING MAKES NO WARRANTY EXPRESS STATUTORY IMPLIED OR BY DESCRIPTION REGARDING THE INFORMA TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT ZI
244. st src dst A src dst src The contents of the source are loaded into the accumulator The contents of the source are not affected The Sign and Zero flags are set according to the value of the data transferred the Overflow flag is set according to the state of the interrupt enable Note that if an interrupt occurs during execution of either of these instructions the Overflow flag reflects the prior state of the interrupt enable Also note that the R register does not contain the refresh address and is not modified by refresh transactions Flags S Setif the data loaded into the accumulator is negative cleared otherwise Z Setifthe data loaded into the accumulator is zero cleared otherwise H Cleared V Set when loading the accumulator if interrupts are enabled cleared otherwise N Cleared Unaffected Addressing Execute Mode Syntax Instruction Format Time Note LD A 11101101 01010111 2 LD A R 11101101 01011111 2 5 90 DC 8297 03 2380 7106 USER S MANUAL LD LOAD INTO I OR R REGISTER BYTE LD dst src dst src dst src The contents ofthe accumulator are loaded into the destination Note thatthe Rregister does not contain the refresh address and is not modified by refresh transactions Flags S Unaffected 2 Unaffected H Unaffected V Unaffected Unaffected Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R LD LA 11101
245. ster cleared otherwise P Setifthe result of the decrement of the B register is even cleared otherwise Set if the most significant bit of the byte transferred was 1 cleared otherwsie C Setif there is a borrow from the most significant bit during the decrement of the B register cleared otherwise Execute Syntax Instruction Format Time Note OTDM 11101101 10001011 2 0 5 113 7106 OTDMR OUTPUT DECREMENT MEMORY REPEAT Operation Flags Addressing Mode 5 114 OTDMR repeat until B 0 begin HL lt C 1 lt B 1 HL HL 1 end This instruction is used for block output of strings of data to on chip peripherals No external I O transaction will be generated as a result of this instruction although the I O address will appear on the address bus and the write data will appear on the data bus while this internal write is occurring The peripheral address is placed on the low byte of the address bus and zeros are placed on all other address lines The byte of data from the memory location addressed by the HL register is loaded to the on chip I O port addressed by the C register The C register holding the port address is decremented by one to select the next output port The B register used as a counter is then decremented by one The HL register is then decremented by one thus moving the pointer to the next source for the output If the result of decrementing the B register is 0 the instru
246. string can be searched until a given value is found All the operations can proceed through the data in either direction Further more the operations can be repeated automatically while decrementing a length counter until it reaches zero or they can operate on one storage unit per execution with the length counter decremented by one and the source and destination pointer register properly adjusted The latter form is useful for implementing more complex operations in software by adding other instructions within a loop containing the block instructions 5 8 Various Z380 CPU registers are dedicated to specific functions for these instructions the BC register for a counter the DEz DE and HLz HL registers for memory pointers and the accumulator for holding the byte value being sought The repetitive forms of these instructions are interruptible this is essential since the repetition countcan be as high as 65536 The instruction can be interrupted after any interaction in which case the address of the instruction itself rather than next one is saved on the stack The contents of the operand pointer registers as well as the repetition counter are such that the instruction can simply be reissued after returning from the interrupt without any visible difference in the instruction execution In case of Word or Long Word block transfer instructions the counter value held in the BC register is decremented by two or four depending on the LW
247. t The contents of the location addressed by the Stack Pointer SP are popped into the Program Counter PC thereby specifying the location of the next instruction to be executed The previous setting of the interrupt enable bit is restored by execution of this instruction S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Syntax Instruction Format RETN 11101101 01000101 Execute Time Note 24r X 5 143 2380 2106 USER S MANUAL RL ROTATE LEFT BYTE RL dst dst IR X Operation tmp lt dst dst 0 C lt dst 7 dst n 1 lt tmp n forn 0to6 The contents of the destination operand are concatenated with the Carry flag and together they are rotated left one bit position Bit 7 of the destination operand is moved to the Carry flag and the Carry flag is moved to bit 0 of the destination Flags 6 Setifthe most significant bit of the result is set cleared otherwise Z Setif the result is zero cleared otherwise H Cleared P Setif parity of the result is even cleared otherwise Cleared Setifthe bit rotated from bit 7 was 1 cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R RL R 11001011 00010 r 2 IR RL HL 11001011 00010110 2 r X RL XY d 11y11101 11001011 d 00010110 4 r Field Encodings r per convention y O for IX 1 for IY 5 144 DC 8297 03 2380 USER S MANUAL RLW 2106 ROTATE LEFT WORD RLW dst dst
248. t of a fixed port address The decremented B register is used in the address First the register used as counter is decremented by one The byte of data from the memory location addressed by the HL register is loaded into the selected peripheral The HL register is then decremented by one thus moving the pointer to the next source for the output S Unaffected Z Setifthe result of decrementing is zero cleared otherwise H Unaffected V Unaffected Set Unaffected Execute Syntax Instruction Format Time Note OUTD 11101101 10101011 2 1 0 5 127 2380 7106 USER S MANUAL OUTDW OUTPUT AND DECREMENT WORD OUTDW Operation BC 15 0 lt BC 15 0 1 DE HL HL lt HL 2 This instruction is used for block output of strings of data During the I O transaction the 32 bit DE register is placed on the address bus First the BC register used as a counter is decremented by one The word of data from the memory location addressed by the HL register is loaded into the selected peripheral The HL register is then decremented by two thus moving the pointer to the next source for the output Unaffected Set if the result of decrementing BC is zero cleared otherwise Unaffected Unaffected Set Unaffected Flags Addressing Execute Mode Syntax Instruction Format Time Note OUTDW 11101101 11101011 2 0 5 128 DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MA
249. t of the result cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R SBCW HL R 11101101 1001111 2 RX SBCW HL RX 11y11101 10011111 2 IM SBCW nn 11101101 10011110 n low n high 2 X SBCW HL X d 11 11101 11011110 d 4 r Field Encodings rr 00for BC 01 for DE 11 for HL y Ofor IX 1 for IY DC 8297 03 5 161 7106 SCF SET CARRY FLAG SCF Operation lt 1 Carry flag is set to 1 Flags S Unaffected 2 Unaffected H Cleared V Unaffected N Cleared C Set Addressing Mode Syntax Instruction Format SCF 00110111 5 162 2380 USER S MANUAL Execute Time Note 2 DC 8297 03 2380 7106 USER S MANUAL SET SET BIT SET b dst dst IR X Operation dst b lt 1 The specified bit b within the destination operand is set to 1 The other bits in the destination are unaffected The bit to be set is specified by a 3 bit field in the instruction this field contains the binary encoding for the bit number to be set The bit number b must be between 0 7 Flags S Unaffected Z Unaffected H Unaffected V Unaffected Unaffected Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R SET b R 11001011 11bbb r 2 IR SET b HL 11001011 11bbb110 2 r X SET b XY d 11y11101 11001011 d 11bbb110 4 r Field Encodings r per convention y 0 for IX 1 for IY DC 8297 03 5 163 2380 7106 User s MANUA
250. t size is controlled by Word or Long Word mode Also included are the R I and SP registers as well as the PC The Select Register SR determines the operation of the Z380 CPU The contents ofthis register determine the CPU operating mode which register bank will be used the interrupt mode in effect and so on The 2380 CPU s memory address spaceislinear 4 Gbytes To keep compatibility with the Za0 CPU memory address ing model it has two control bits to change its operation modes Native or Extended Word or Long Word The Z380 CPU architecture also distinguishes between the memory and addressing space and therefore requires specific instructions Furthermore ad dressing space is subdivided into the on chip address space and the external addressing space External I O addressing space in the 2380 CPU is 32 bits long and internal I O addressing space is 8 bits long There are separate sets of instructions for each I O addressing space Some of the Internal I O registers are used to control the functionality of the device such as to program read status of Trap Assigned Vector Base address enabling of inter rupts and to get Chip version ID For details on this topic refer to Chapter 2 Address Spaces 1 2 3 Data Types Many datatypes are supported by the Z380 CPU architec ture The basic data type is the 8 bit byte which is also the basic addressable memory element The architecture
251. t support decoder directives are assembled by the instruction decoder as if the decoder directive were not present DDIRW Word mode DDIR IB W Immediate byte Word mode m DDIR IW W Immediate Word Word mode m DDIR IB Immediate byte oO DDIR LW Long Word mode m DDIR IB LW Immediate byte Long Word mode El DDIR IW LW Immediate Word Long Word mode m DDIR IW Immediate Word 3 3 NATIVE MODE AND EXTENDED MODE The Z380 CPU can operate in either Native or Extended mode as a way to manipulate addresses In Native mode the Reset configuration the Program Counter only increments across 16 bits and all stack Push and Pop operations manipulate 16 bit quantities two bytes Thus Native mode is fully compatible with the Z80 CPU s 64 Kbyte address space and programming model The extended portion of the Program Counter PC31 PC15 is forced to 0 and program address location nextto 0000FFFFH is 00000000H in this mode This means in Native mode program have to reside within the first 64 Kbytes of the memory addressing space In Extended mode however the PC increments across all 32 bits and all stack Push and Pop operations manipulate 32 bit quantities Thus Extended mode allows access to the entire 4 Gbyte address space In both Native and Extended modes the Z380 CPU drives all 32 bits of the address onto the external address bus only the PC incre ments and stack operations distinguish Native from Ex tended mode 3 2 2380
252. ted Execute Syntax Instruction Format Time Note DI 11110011 2 DI n 11011101 11110011 n 2 2380 USER S MANUAL DC 8297 03 71106 Operation Flags Addressing Mode R RX IM 2380 USER S MANUAL DIVUW DIVIDE UNSIGNED WORD DIVUW HL src src X HL 15 0 HL HL 31 16 lt remainder The contents of the the HL register dividend are divided by the source operand divisor and the quotient is stored in the lower word of the HL register the remainder is stored in the upper word of the HL register The contents of the source are unaffected Both operands are treated as unsigned binary integers There are three possible outcomes of the DIVUW instruction depending on the division and the resulting quotient Case 1 If the quotient is less than 65536 then the quotient is left in the HL register the Overflow and Sign flags are cleared to 0 and the Zero flag is set according to the value of the quotient Case 2 If the divisor is zero the HL register is unchanged the Zero and Overflow flags are set to 1 and the Sign flag is cleared to 0 Case 3 If the quotient is greater than or equal to 65536 the HL register is unchanged the Overflow flag is set to 1 and the Sign and Zero flags are cleared to 0 S Cleared Z Setifthe quotient or divisor is zero cleared otherwise H Unaffected V Set if the divisor is zero or if the computed quotient is greater than or equal to 6
253. tegration device Currently the value 00H is assigned to the Z380 MPU and other values are reserved For the other three registers refer to Chapter 6 Interrupt and Trap Internal I O address Also the 7380 MPU has registers to control chip selects refresh waits and clock divide to Internal I O address OOH to 10H For these register refer to Z380 MPU Product specification DC 8297 03 5 15 ZiLoG 5 5 11 CPU Control Group The instructions in this group Table 5 16 act upon the CPU control and status registers or perform otherfunctions that do not fit into any of the other instruction groups These include two instructions used for returning from an inter rupt service routine Return from Nonmaskable Interrupt RETN and Return from Interrupt RETI are used to pop the Program Counter from the stack and manipulate the Interrupt Enable Flag IEF1 and IEF2 or to signal a reset to the Z80 peripherals family The Disable and Enable Interrupt instructions are used to set reset interrupt mask Without a mask parameters it disables enables maskable interrupt globally With mask data it enables disables interrupts selectively HALT and SLEEP instructions stop the CPU and waits for an eventto happen or puts the system into the power save mode Bank Test instructions reports which register file primary or alternate bank is in use at the time and reflect the status 2380 User s MANUAL into a flag regist
254. ter The contents of the source are unaffected Two s complement subtraction is performed Flags S Set if the result is negative cleared otherwise Set if the result is zero cleared otherwise Setifthere is a borrow from bit 12 of the result cleared otherwise V Set if arithmetic overflow occurs that is if the operands are of different signs and the result is of the same sign as the the source cleared otherwise N Set C Setifthere is a borrow from the most significant bit of the result cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R SBC HL R 11101101 01110010 2 Field Encodings rr 00for 01 for DE 10 for HL 11 for SP 5 160 DC 8297 03 2380 71 06 USER S MANUAL SBCW SUBTRACT WITH CARRY WORD SBCW HL src src R RX IM X Operation HL 15 0 HL 15 0 src 15 0 C The source operand together with the Carry flag is subtracted from the HL register and the difference is stored in the HL register The contents of the source are unaffected Two s complement subtraction is performed Flags S Set if the result is negative cleared otherwise Z Setifthe result is zero cleared otherwise Setifthere is a borrow from bit 12 of the result cleared otherwise V Setif arithmetic overflow occurs that is if the operands are of different signs and the result is of the same sign as the source cleared otherwise N Set C Setifthere is a borrow from the most significant bi
255. ter loads and exchanges plus 32 bit load and exchange and 32 bit arithmetic operation for address calculation The basic register file of the Z80 microprocessor is ex panded to include alternate register versions of the IX and IY registers There are four sets of this basic 280 micropro cessor register file present in the Z380 MPU along withthe necessary resources to manage switching between the different register sets All of the register pairs and index registers in the basic Z80 microprocessor register file are expanded to 32 bits The 2380 CPU expands the basic 64 Kbyte 780 and Z180 address space to a full 4 Gbyte 32 bit address space This address space is linear and completely accessible to the user program The external I O address space is similarly expanded to a full 4 Gbyte 32 bit range and 16 bit I O both simple and block move are included A 256 byte wide internal I O space has been added This space will be used to access on chip resources on future Superintegration implementation of this CPU core Figure 1 1 provides a detailed description of the basic register architecture of the Z380 CPU with the size of the register banks shown at four each however the Z380 CPU architecture allows future expansion of up to 128 sets of each 2380 7106 USER S MANUAL 1 1 INTRODUCTION Continued 4 Sets of Registers SPz PCz P Figure 1 1 Z380 CPU Register Architecture 1 2 DC 8297 03 7106 1 2 CPU ARCH
256. th the Z80 CPU the Z380 CPU architecture has been expanded to include features such as multiple register banks 4 Gbytes of linear memory addressing space and efficient handling of nested interrupts The benefits of this 2380 USER S MANUAL register pairs including eachregister s Extended portion When doing context switching by exceptional condition trap or interrupts or by subroutine procedure calls the CPU has to save the contents of the registers currently in use along with the current CPU status Traditionally in the Z80 CPU architecture this is done by saving the contents of the register into memory usually using push pop instructions or the auxiliary register file Register contents are then restored when the process is finished With the Z380 CPU s multiple register banks saving the contents of the working register set currently in use is just a matter of an instruction to change the field in the Select Register which allows fast context switching architecture including high throughput rates code den sity and compiler efficiency greatly enhance the power and versatility of the Z380 CPU Thus the Z380 CPU provides both growth path for existing Z80 based de signs and powerful processor for applications and the products to be developed around this CPU core O 1994 1995 1996 1997 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means witho
257. the memory location addressed by the HL register is loaded into the selected peripheral The HL register is then decremented by one thus moving the pointer to the next source for the output If the result of decrementing the B register is 0 the instruction is terminated otherwise the sequence is repeated If the B register contains 0 at the start of the execution of this instruction 256 bytes are output This instruction can be interrupted after each execution ofthe basic operation The Program Counter value atthe start of this instruction is saved before the interrupt request is accepted so that the instruction can be properly resumed S Unaffected Z Setifthe result of decrementing B is zero cleared otherwise H Unaffected V Unaffected N Set C Unaffected Execute Syntax Instruction Format Time Note OTDR 11101101 10111011 2 1 0 5 115 7106 OTDRW OUTPUT DECREMENT AND REPEAT WORD Operation Flags Addressing Mode 5 116 OTDRW repeat until BC 0 begin 15 0 lt BC 15 0 1 DE lt HL HL lt HL 2 end This instruction is used for block output of strings of data The string of output data is loaded into the selected peripheral memory at consecutive addresses starting with the location addressed by the HL register and decreasing During the I O transaction the 32 bit DE register is placed on the address bus First the BC register used as a counter is decremented by one The word
258. the body or which sustains life whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 Telex 910 338 7621 FAX 408 370 8056 Internet http www zilog com 5 180 DC 8297 03 N lt 6 1 INTRODUCTION Exceptions are conditions that can alter the normal flow of program execution Z380 CPU supports three kinds of exceptions interrupts traps and resets Interrupts are asynchronous events generated by a device external to the CPU peripheral devices use interrupts to request service from the CPU Traps are synchronous events generated internally in the CPU by a particular condition that can occur during the attempted execution of an instruction in particular when executing undefined instructions Thus the difference between Traps and Inter rupts is their origin A Trap condition is always reproduc ible by re executing the program that created the Trap whereas an Interrupt is generally independent of the currently executing task 6 2 INTERRUPTS Of the five external Interrupt inputs provided one is as signed as a Nonmaskable Interrupt NMI The remaining inputs INT3 INTO are four asynchronous maskable In terrupt requests The Nonmaskable Interrupt NMI is an Interrupt that
259. therwise H Unaffected V Cleared N Unaffected C Setifthe product is greater than or equal to 65536 cleared otherwise Execute Syntax Instruction Format Time MULTUW HL R 11101101 11001011 100110rr 11 MULTUW HL RX 11101101 11001011 1001110y 11 MULTUW HL nn 11101101 11001011 10011111 n low n high 11 MULTUW HL XY d 11y11101 11001011 d 10011010 13 r Field Encodings rr 00for BC 01 for DE 11 for HL DC 8297 03 y O for IX 1 for IY Note 5 107 2380 7106 USER S MANUAL NEG NEGATE ACCUMULATOR NEG A Operation lt A The contents of the accumulator are negated that is replaced by its two s complement value Note that 80h is replaced by itself because in two s complement representation the negative number with the greatest magnitude has no positive counterpart for this case the Overflow flag is set to 1 Flags S Set if the result is negative cleared otherwise Z Setifthe result is zero cleared otherwise Setif there is borrow from bit 4 of the result cleared otherwise V Set if the content of the accumulator was 80h before the operation cleared otherwise N Set C Setifthe content of the accumulator was not 00h before the operation cleared if the content of the accumulator was 00h Addressing Execute Mode Syntax Instruction Format Time Note NEG A 11101101 01000100 2 5 108 DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03
260. tion Format Time Note DDIR mode 11w11101 110000im 0 Field Encodings wim 000 W Word mode 001 IB W Immediate byte Word mode 010 IW W Immediate word Word mode 011 IB Immediate byte 100 LW Long Word mode 101 IB LW Immediate byte Long Word mode 110 IWLW Immediate word Long Word mode 111 IW Immediate word DC 8297 03 5 43 2380 7106 USER S MANUAL DEC DECREMENT BYTE DEC dst IR X Operation dst dst 1 The destination operand is decremented by one and the result is stored in the destination Two s complement subtraction is performed Flags S Set if the result is negative cleared otherwise Z Set if the result is zero cleared otherwise H Setifthere is a borrow from bit 4 of the result cleared otherwise V Set if arithmetic overflow occurs that is if the destination was 80H cleared otherwise Set C Unaffected Addressing Execute Mode Syntax Instruction Format Time Note R DEC R 00 r 101 note RX DEC RX 11y11101 0010w101 2 IR DEC HL 00110101 2 r w X DEC XY d 11y11101 00110101 d 4 r w Field Encodings r convention y OforIX 1 for IY w Oforhigh byte 1 for low byte Note 2 for accumulator 3 for any other register 5 44 DC 8297 03 2380 71 06 USER S MANUAL DEC W DECREMENT WORD DEC W dstdst RX Operation _ if XM then begin dst 31 0 lt dst 31 0 1 end else begin dst 15 0 lt dst 15 0 1 end The destination operand is decremented by on
261. tion to be executed For an unconditional return the return is always taken and a condition code is not specified This instruction is also used to return to a previously executing procedure at the end of a procedure entered by an interrupt in the assigned vectors mode if Z80 family peripherals are used external to the Z380 MPU Flags S Unaffected 7 Unaffected H Unaffected V Unaffected Unaffected Unaffected Addressing Execute Mode Syntax Instruction Format Time Note RET 11 cc000 note X RET 11001001 2 r X Field Encodings cc 000 for NZ 001 for Z 010 for NC 011 for C 100 for PO NV 101 for PE V 110 for P NS 111 for M S Note 2 if CC is false 2 r if CC is true 5 140 DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 2380 USER S MANUAL RETB RETURN FROM BREAKPOINT 31 0 SPC 31 0 This instruction is used to return to previously executing procedure at the end breakpoint The contents of the Shadow Program Counter SPC which holds the address of the next instruction of the previously executing procedure are loaded into the Program Counter PC Note that maskable interrupts if IEF1 is set and non maskable interrupt are enabled after the instruction following RETB is executed S Unaffected Z Unaffected H Unaffected V Unaffected N Unaffected C Unaffected Execute Syntax Instruction Format Time Note RETB 11101101 01010101 2 5 141 71
262. to make Trap handling easier The Z380 MPU also offers additional features to enhance flexibility in system design the Disable Interrupt instruction is used to selectively disable interrupts by clearing appropriate bits in the IER and or clearing IEF1 bit in the SR register When an Interrupt source has been disabled the CPU ignores any request from that source Because maskable Interrupt requests are notretained by the CPU the requestsignal on a maskable Interrupt line must be asserted until the CPU acknowledges the request When enabling Interrupts with the EI instruction all maskable Interrupts are automatically disabled whether previously enabled or not for the duration of the execution ofthe El instruction and the instruction immediately follow ing Interrupts are always accepted between instructions The block move block search and block instructions can be interrupted after any iteration The Z380 CPU has four selectable modes for handling externally generated Interrupts using the IM instruction The first three modes extend the Z80 CPU Interrupt Modes to accommodate the Z380 CPU s additional Interrupt in puts in a compatible fashion The fourth mode allows more flexibility in interrupt handling 6 1 7106 6 2 INTERRUPTS Continued In an Interrupt acknowledge transaction address outputs 1 4 are driven to logic 1 One output among A3 A0 is driven to logic 0 to indicate the maskable interrupt request
263. tracted from the SP register and the difference is stored in the SP register This has the effect of allocating or deallocating space on the stack Two s complement subtraction is performed S Unaffected 2 Unaffected Setifthere is borrow from bit 12 of the result cleared otherwise V Unaffected Set Set if there is a borrow from the most significant bit of the result cleared otherwise Execute Syntax Instruction Format Time Note SUB SP nn 11101101 10010010 n low n high 2 LX DC 8297 03 2380 7106 USER S MANUAL SUBW SUBTRACT WORD SUBW HL src src R RX IM X Operation HL 15 0 lt HL 15 0 src 15 0 The source operand is subtracted from the HL register and the difference is stored in the HL register The contents of the source are unaffected Two s complement subtraction is performed Flags S Set if the result is negative cleared otherwise Z result is zero cleared otherwise Setif there is a borrow from bit 12 of the result cleared otherwise V Setif arithmetic overflow occurs that is if the operands are of different signs and the result is of the same sign as the source cleared otherwise Set Set if there is a borrow from the most significant bit of the result cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R SUBW HL R 11101101 100101rr 2 RX SUBW HL RX 11y11101 10010111 2 IM SUBW HL nn 11101101 10010110 n low n high 2 X
264. truction SR Select Register R Any register In Word operation any register pair Any 8 bit register A B C D E H or L for Byte operation IR Indirect register RX Indexed register IX or IY in Word operation IXH IXL IYH or IYL for Byte operation SP Current Stack Pointer C I O Port pointed by C register cc Condition Code Optional field Indirect Address Pointer or Direct Address DC 8297 03 2380 USER S MANUAL Table 5 17 Decoder Directive Instructions DDIR W Word Mode DDIR IB W Immediate Byte Word Mode DDIR IW W Immediate Word Word Mode DDIR IB Immediate Byte DDIR LW Long Word Mode DDIR IB LW Immediate Byte Long Word Mode DDIRIWLW Immediate Word Long Word Mode DDIR IW Immediate Word Assignment of a value is indicated by the symbol lt For example dst dst src indicates that the source data is added to the destination data and the result is stored in the destination location The symbol lt gt indicates that the source and destination is swapping For example dst lt gt src indicates that the source data is swapped with the data in the destination after the operation data at src is in the dst location and data in dst is in the src location The notation dst b is used to refer to bit b of a given location dst m n is used to refer to bit location m to n of the destination For example HL 7 specifies bit 7 of the destination
265. ts Voc m DC to 10 MHz Operating Frequency 33 Volts m Enhanced Instruction Set that Maintains Object Code Compatibility with Z80 and Z180 Microprocessors W 16 Bit 64K or 32 Bit 4G Linear Address Space m 16 Bit Internal Data Bus Two Clock Cycle Instruction Execution Minimum m Multiple On Chip Register Files 2380 MPU has Four Banks m BC DE HL X Y Registers are Augmented by 16 Bit Extended Registers BCz DEz HLz IXz IYz PC SP I Registers are Augmented by Extended Registers PCz 5 2012 for 32 Bit Addressing Capability m Newly Added and IY Registers with Extended Registers IXz IYz m Enhanced Interrupt Capabilities Including 16 Bit Vector m Undefined Opcode Trap for Full Z380 CPU Instruction Set USER s MANUAL CHAPTER 1 2380 ARCHITECTURAL OVERVIEW The Z380 CPU an enhanced version of the Z80 CPU retains the Z80 CPU instruction set to maintain complete binary code compatiblity with presentZ80 and Z180 codes The basic addressing modes of the Z80 microprocessor have been augmented with Stack Pointer Relative loads and stores 16 bit and 24 bit Indexed offsets and in creased Indirect register addressing flexibility with all of the addressing modes allowing access to the entire 32 bit address space Significant additions have been made to the instruction set iincorporating 16 bit arithmetic and logi cal operations 16 bit I O operations multiply and divide acomplete set of register to regis
266. uctions for transferring blocks of data from memory to Internal I O locations The operation of these instructions is very similar to that of the block move instructions described earlier with the excep tion that one operand is always an Internal I O location whose address also increments or decrements by one automatically Also the address of the other operand a memory location is incremented or decremented Since Internal space is byte wide only byte forms of these instructions are available Automatically repeating forms of these instructions are interruptible like memory to memory transfer Table 5 15 Internal I O Instruction Group Instruction Name Format Input from Internal Location INO dst A D H or L Input from Internal I O Location Nondestructive INO n Test I O TSTIO n Output to Internal I O Location OUTO n src src A B D H or L Output to Internal I O and Decrement OTDM Output to Internal I O and Increment OTIM Output to Internal I O Decrement and Repeat OTDMR Output to Internal I O Increment and Repeat OTIMR Currently the Z380 CPU core has the following registers as a part of the CPU core Register Name Interrupt Enable Register 16H Assigned Vector Base Register 17H Trap Register 18H Chip Version ID Register OFFH Chip Version ID register returns one byte data which indicates the version of the CPU or the specific implemen tation of the Z380 CPU based Superin
267. ut the prior written consent of Zilog Inc The information in this document is subject to change without notice Devices sold by Zilog Inc are covered by warranty and patent indemnification provisions appearing in Zilog Inc Terms and Conditions of Sale only ZILOG INC MAKES NO WARRANTY EXPRESS STATUTORY IMPLIED OR BY DESGRIPTION REGARDING THE INFORMA TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT ZILOG INC MAKES NO WARRANTY OF MER CHANTABILITY OR FITNESS FOR ANY PURPOSE Zilog Inc shall not be responsible for any errors that may appear in this document Zilog Inc makes no commitment to update or keep current the information contained in this document Zilog s products are not authorized for use as critical compo nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use Life support devices or systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 Telex 910 338 7621 FAX 408 370 8056 Internet http www zilog com 1 6 DC 8297 03
268. verflow flags are used condition code to control the operation of the conditional instructions The operation of these instructions is a function of the state of one of the flags Special mnemonics called condition codes are used to specify the flag setting to be tested during execution of a conditional instruction the condition codes are encoded into 3 bit field in the instruction opcode itself Table 5 1 Condition codes Condition Codes for Jump Call and Return Instructions Mnemonic Meaning Flag Setting Binary Code NZ Not Zero 2 0 000 2 Zero 2 1 001 0 010 C Carry 1 011 NV No Overflow V 0 100 PO Parity Odd V 0 100 V Overflow V 1 101 PE Parity Even V 1 101 NS No Sign S 0 110 P Plus S 0 110 5 Sign S 1 111 M Minus S 1 111 Abbreviated set Condition Codes for Jump Relative and Call Relative Instructions Mnemonic Meaning Flag Setting Binary Code NZ Not Zero Z 0 100 2 Zero 2 1 101 Carry 0 110 C Carry C 1 111 DC 8297 03 5 3 7106 5 3 SELECT REGISTER The Select Register SR controls the register set selection and the operating modes of the Z380 CPU The reserved bits in the SR are for future expansion they will always read as zeros and should be written with zeros for future 2380 USER S MANUAL compatibility Access to this register is done by using the newly added LDCTL instruction Also some of the instruc tions like EXX IM p and change the bit
269. ving the pointer to the next source for the output S Unaffected Z Set if the result of decrementing BC is zero cleared otherwise H Unaffected V Unaffected N Set C Unaffected Execute Syntax Instruction Format Time Note OUTIW 11101101 11100011 2 1 0 DC 8297 03 71106 Operation Flags Addressing Mode DC 8297 03 POP dst F A SP lt SP lt SP 1 lt 5 2 if LW then begin SP lt SP 2 end dst AF 2380 USER S MANUAL POP POP ACCUMULATOR The contents of the memory location addressed by the Stack Pointer SP are loaded into the destination in ascending byte order from ascending address memory locations For this instruction the Flag register is the least significant byte followed by the Accumulator The SP is then incremented by two by four in the Long Word mode Note that in the Long Word mode only one word is read from memory although the SP is in fact incremented by four S Loaded from SP 2 Loaded from H Loaded from SP V Loaded from SP Loaded from SP C Loaded from SP Syntax POP AF Instruction Format Execute Time Note 24r L 5 131 2380 7106 USER S MANUAL POP POP CONTROL REGISTER POP dst dst SR Operation if LW then begin dst 6 0 SP dst 15 8 lt SP 1 dst 23 16 SP 2 dst 31 24 SP 3 SP SP 4 end else begin dst 6 0 SP dst 15 8 lt SP 1 dst 23 16 SP 1 dst 31 24 SP 1 SP lt SP
270. which includes Ex tended registers and register banks and the capability of executing all the Z380 instructions As described below the Z380 CPU can be switched between Word mode and Long Word mode during opera tion through the SETC LW and RESC LW instructions or Decoder Directives The Native and Extended modes are a key exception it defaults up in Native mode and can be setto Extended mode by the instruction Only Resetcan return it to Native mode Figure 3 1 illustrates the relation ship between these modes of operation 2380 Figure 3 1 2380 CPU Operation Modes For the instructions which work with the DDIR instructions refer to Appendix D and E DC 8297 03 3 1 7106 3 2 DECODER DIRECTIVES The Decoder Directive is not an instruction but rather directive to the instruction decoder The instruction de coder may be directed to fetch an additional byte or word of immediate data or address with the instruction as well as tagging the instruction for execution in either Word or Long Word mode Since the 780 CPU architecture s ad dressing convention in the memory is least significant byte first followed by more significant bytes itis possible to have such instructions to direct the instruction decoder to fetch additional byte s of address information or imme diate data to extend the instruction All eight combinations of the two options are supported as shown below Instructions which do no
271. y appear in this document Zilog Inc makes no commitment to update or keep current the information contained in this document Zilog s products are not authorized for use as critical compo nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use Life support devices or systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 Telex 910 338 7621 FAX 408 370 8056 Internet http www zilog com DC 8297 03 6 7 v 7 1 INTRODUCTION The Z380 CPU is placed in a dormant state when the RESET inputis asserted All its operations are terminated including any interrupt bus request or bus transaction that may be in progress On the Z380 MPU the IOCLK goes Low on the next BUSCLK rising edge and enters into the BUSCLK divided by eight mode The address and data buses are tri stated and the bus control signals are driven to their inactive states The effect of RESET on the 2380 CPU and related internal I O registers is depicted in Table 7 1 The RESET input may be asynchronous to BUSCLK though it is sampl
272. y flag and zero is shifted into the most significant bit of the destination Flags S Cleared Z Setifthe result is zero cleared otherwise H Cleared P Setif parity of the result is even cleared otherwise N Cleared Setifthe bit shifted from bit 0 was a 1 cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R SRLW R 11101101 11001011 001110rr 2 RX SRLW RX 11101101 11001011 0011110y 2 IR SRLW HL 11101101 11001011 00111010 2 r SRLW XY d 11 11101 11001011 d 00111010 4 r Field Encodings rr 00 for BC 01 for DE 11 for HL y Ofor IX 1 for IY DC 8297 03 5 171 2380 7106 USER S MANUAL SUB SUBTRACT BYTE SUB A src src RX IM IR X Operation lt A src The source is subtracted from the accumulator and the difference is stored in the accumulator The contents of the source are unaffected Two s complement subtraction is performed Flags S Set if the result is negative cleared otherwise Z Set if the result is zero cleared otherwise H Set if there is a borrow from bit 4 of the result cleared otherwise V Set if arithmetic overflow occurs that is if the operands are of different signs and the result is of the same sign as the source cleared otherwise N Set Set if there is a borrow from the most significant bit of the result cleared otherwise Addressing Execute Mode Syntax Instruction Format Time Note R SUB A R 10010 r 2 RX SUB A R

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