Home

Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

1. 4 4 4 20 Chapter 3 Clock Sources OVERVIEW cias lat e ie pus us b re i te dt 21 Clock Connections as es aa e tock eR ends Rr R eeu e e dues tes 22 Voltage Control eV Ze ia eb ie acd 22 50 MHz On Board Oscillator 22 Auxiliary Clock Oscillator Socket 22 Spartan 3E FPGA Starter Kit Board User Guide www xilinx com UG230 v1 1 June 20 2008 Z XILINX SMA Clock Input or Output Connector 22 UCF Constraints 22 LocatiOtis rssi eme brRIPSumco de aspa dass kje ERO a dou u qg e e p TRA shee 22 Clock Period Constraints 23 Related Resoutces uaea eee 23 Chapter 4 FPGA Configuration Options Configuration Mode Jumpers 27 PROG Push Button 28 DONE Pin LED EORR ia 28 Programming the FPGA CPLD or Platform Flash PROM via USB 29 Connecting the USB Cable 29 Programming via IMPACT 44444 eue 30 Programming Platform Flash PROM via USB 32 Generating the FPGA Configuration Bitstream File 32 Generating the PROM File
2. 142 FPGA I O Banks 0 and 1 Oscillators 144 FPGA T O Banks Zand 3 Lue saus en ep eo OR ed 0 AC EE 146 Power Supply Decoupling 148 XC2C64A CoolRunner II CPLD rails Rea 150 Linear Technology ADC and DAC 152 Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM 154 Spartan 3E FPGA Starter Kit Board User Guide www xilinx com UG230 v1 1 June 20 2008 Z XILINX Buttons Switches Rotary Encoder and Character LCD 156 DDR SDRAM Series Termination and FX2 Connector Differential Termination 158 Appendix B Example User Constraints File UCF www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Preface About This Guide This user guide provides basic information on the Spartan 3E FPGA Starter Kit board capabilities functions and design It includes general information on how to use the various peripheral functions included on the board For detailed reference designs including VHDL or Verilog source code please visit the following web link e Spartan 3E FPGA Starter Kit Board Reference Page http www xilinx com s3estarter Acknowledgements Xilinx wishes to thank the following companies for their support of the Spartan 3E FPGA Starter Kit board e Intel Corporation for th
3. 51 Read Data from CG RAM or DD RAM 52 Deeg gd geg Achs NA RA R NEH hee ee R TE nee 52 Four Bit Data Interface 52 Transferring 8 Bit Data over the 4 Bit Interface 53 Initializing the Display cari Sepa eee ette tard E dee qn 53 Power On Initialization 53 Display Conhgur tion aaa et aree ER E rt ean eee aod cen pe ded antes 53 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Z XILINX Writing Data to the Display 54 Disabling the Unused LCD 54 Related Resoutces anane eee 54 Chapter 6 VGA Display Port Signal Timing for a 60 Hz 640x480 VGA Display 56 VGA Signal Timing dd IRA AAA EG 58 UCF Location Constraints vs scr als A AAA 59 Related Resources Ges degt sono token der a iia 59 Chapter 7 RS 232 Serial Ports Chapter 8 PS 2 Mouse Keyboard Port Key DOSE L ada dait e vet E 64 MOUSE C PTT 66 Voltage BUBDLy oie dae totae e bec tede bebo b e Ae 67 UCF Location Constraints 67 Related Resources 67 Chapter 9 Digital to Analog Converter DAC SPI Communication 69 Interface Signals ad 70 Disable Other Devices on the SPI Bus to Avoid Contention
4. SF CEO SF BYTE LCD RW Operation 1 X X StrataFlash disabled Full read write access to LCD X X 0 LCD write access only Full access to StrataFlash X 0 X StrataFlash in byte wide x8 mode Upper address lines are not used Full access to both LCD and StrataFlash Notes 1 X indicates a don t care can be either 0 or 1 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX UCF Location Constraints If the StrataFlash memory is in byte wide x8 mode SF BYTE Low the FPGA application has full simultaneous read write access to both the LCD and the StrataFlash memory In byte wide mode the StrataFlash memory does not use the SF D lt 15 8 gt data lines UCF Location Constraints Figure 5 2 provides the UCF constraints for the Character LCD including the I O pin assignment and the I O standard used NET LCD E LOC M18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET LCD RS LOC L18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET LCD RW LOC L17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW The LCD four bit data interface is shared with the StrataFlash NET SF D 8 LOC R15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 9 LOC R16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D lt 10 gt LOC P17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW
5. 70 SPI Communication Details eR s 71 Communication Protocol 71 Specifying the DAC Output Voltage 72 DAC Outputs A and B isses e e ee eR sede E RR PER pn 72 DAC Outputs Cand 3 ies ied eed ctiam ana EE 72 UCF Location Constraints 73 Related Resources 73 Chapter 10 Analog Capture Circuit Digital Outputs from Analog Inputs eee 76 Programmable Pre Amplifier 77 Set 2 14 die cessera equip desea eae He aote ta eto td 77 Programmable Gaini oo sesio siis ganaq e Er ER E ER s 77 SPI Control Interface 78 UCF Location Constraints eR RR e ee 79 Analog to Digital Converter ADC 79 Interface redire A A res ED EE c dude 79 SPI Control Interface 79 UCF Location Constraints eR RR e s 80 Disable Other Devices on the SPI Bus to Avoid Contention 81 Spartan 3E FPGA Starter Kit Board User Guide www xilinx com UG230 v1 1 June 20 2008 Z XILINX Connecting Analog Inputs Related REEL gatas tee pda Chapter 11 Intel StrataFlash Parallel NOR Flash PROM StrataFlash Connections Shared Connect
6. NET LED lt 6 gt LOC E9 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 7 gt LOC F9 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 PS 2 Mouse Keyboard Port PS2 NET PS2 CLK LOC G14 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW NET PS2 DATA LOC G13 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW Rotary Pushbutton Switch ROT NET ROT A LOC K18 IOSTANDARD LVTTL PULLUP NET ROT B LOC G18 IOSTANDARD LVTTL PULLUP NET ROT CENTER LOC V16 IOSTANDARD LVTTL PULLDOWN d RS 232 Serial Ports RS232 NET RS232 DCE RXD LOC R7 IOSTANDARD LVTTL NET RS232 DCE TXD LOC M14 IOSTANDARD LVTTL DRIVE 8 SLEW SLOW NET RS232 DTE RXD LOC U8 IOSTANDARD LVTTL NET RS232 DTE TXD LOC M13 IOSTANDARD LVTTL DRIVE 8 SLEW SLOW DDR SDRAM SD I O Bank 3 VCCO 2 5V NET SD A lt 0 gt LOC TIN IOSTANDARD SSTL2 I NET SD A lt 1 gt LOC RI IOSTANDARD SSTL2 I NET SD A lt 2 gt LOC R2 IOSTANDARD SSTL2 I NET SD A lt 3 gt LOC IpI IOSTANDARD SSTL2 I NET SD A lt 4 gt LOC Fa IOSTANDARD SSTL2 I NET SD A lt 5 gt LOC HA IOSTANDARD SSTL2 I NET SD A lt 6 gt LOC H3 IOSTANDARD SSTL2 I NET SD A lt 7 gt LOC HLN IOSTANDARD SSTL2 I NET SD A lt 8 gt LOC H2 IOSTANDARD SSTL2 I NET SD A lt 9 gt LOC NA IOSTANDARD SSTL2 I NET SD
7. l CS LD i i i SPLSCK p gt SCK SPI Control Interface i i E ivcc i i 3 3V UG230_c9_02_021806 Figure 9 2 Digital to Analog Connection Schematics Interface Signals Table 9 1 lists the interface signals between the FPGA and the DAC The SPI MOSI SPI MISO and SPI SCK signals are shared with other devices on the SPI bus The DAC CS signal is the active Low slave select input to the DAC The DAC CLR signal is the active Low asynchronous reset input to the DAC Table 9 1 DAC Interface Signals Signal FPGA Pin Direction Description SPI MOSI T4 FPGA gt DAC Serial data Master Output Slave Input DAC CS N8 FPGA DDAC Active Low chip select Digital to analog conversion starts when signal returns High SPI_SCK U16 FPGA gt DAC Clock DAC_CLR P8 FPGA gt DAC Asynchronous active Low reset input SPI MISO N10 FPGA DAC Serial data Master Input Slave Output The serial data output from the DAC is primarily used to cascade multiple DACs This signal can be ignored in most applications although it does demonstrate full duplex communication over the SPI bus Disable Other Devices on the SPI Bus to Avoid Contention The SPI bus signals are shared by other devices on the board It is vital that other devices are disabled when the FPGA communicates with the DAC to avoid bus contention Table 9 2 provides the signals and logic values required to disable the other devices Although the S
8. Configuration Options Startup Options Readback Options Configuration Rate Configuration Clk Configuration Pins Configuration Pin MO Configuration Pin M1 Configuration Pin M2 Configuration Pin Program Configuration Pin Done JTAG Pin TCK v Property display level Standard v Default UG230_c4_12_022706 Figure 4 11 Set CCLK Configuration Rate under Configuration Options Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 33 UG230 v1 1 June 20 2008 34 Chapter 4 FPGA Configuration Options XILINX To regenerate the programming file double click Generate Programming File as shown in Figure 4 12 Processes User Constraints e DAD Sunthesize 57 e Implement Design E ENET ate Pro gram un ng File Programming File Generatic i ER Generate PROM ACE or JTA Configure Device iM Sc K ap Pracesses UG230 c4 13 022706 Figure 4 12 Double Click Generate Programming File Generating the PROM File After generating the program file double click Generate PROM ACE or JTAG File to launch the iMPACT software as shown in Figure 4 13 Processes User Constraints H P Sunthesize KST K R Implement Design E 9 Generate Programming File EE Programming File Generation F Generate FROM AC E or JTA SR Processes UG230 c4 14 022706 Figure 4 13 Double Click Generate PROM ACE or JTAG File
9. FX2 IP lt 40 gt FX2 CLKIN FX2 CLKOUT FX2 CLKIO D10 D9 Bank 0 Supply JP9 UG230 c12 02 022406 Figure 15 2 FPGA Connections to the Hirose 100 pin Edge Connector Three signals are reserved primarily as clock signals between the board and FX2 connector although all three connect to full I O pins Voltage Supplies to the Connector The Spartan 3E Starter Kit board provides power to the Hirose 100 pin FX connector and any attached board via two supplies see Figure 15 2 The 5 0V supply provides a voltage source for any 5V logic on the attached board or alternately provides power to any voltage regulators on the attached board A separate supply provides the same voltage at that applied to the FPGA s I O Bank 0 All FPGA I Os that interface to the Hirose connector are in Bank 0 The I O Bank 0 supply is 3 3V by default However the voltage level can be changed to 2 5V using jumper JP9 Some FPGA I O standards especially the differential standards such as RSDS and LVDS require a 2 5V output supply voltage To support high speed signals across the connector a majority of pins on the B side of the FX2 connector are tied to GND Connector Pinout and FPGA Connections Table 15 1 shows the pinout for the Hirose 100 pin FX2 connector and the associated FPGA pin connections The FX2 connect has two rows of connectors both with 50 connections each shown in the table using light yellow sha
10. Figure 5 5 Example Custom Checkerboard Character with Character Code 0x03 Command Set Table 5 3 summarizes the available LCD controller commands and bit definitions Because the display is set up for 4 bit operation each 8 bit command is sent as two 4 bit nibbles The upper nibble is transferred first followed by the lower nibble Table 5 3 LCD Character Display Command Set o z Upper Nibble Lower Nibble Function a S E dom lg Die e SE S mj TETE S Clear Display 0 0 0 0 0 0 0 0 0 1 Return Cursor Home 0 0 0 0 0 0 0 0 1 Entry Mode Set 0 0 0 0 0 0 0 1 I D S Display On Off 0 0 0 0 0 0 1 D C B Cursor and Display Shift 0 0 0 0 0 1 S C R L 48 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Z XILINX Table 5 3 LCD Character Display Command Set Continued LCD Controller Y Upper Nibble Lower Nibble Function alalnrleln eo a o 388 8 88 8 8 SS Function Set 0 0 0 0 1 0 1 0 Set CG RAM Address 0 0 0 1 A5 A4 A3 A2 A1 AO Set DD RAM Address 0 0 1 A6 A5 A4 A3 A2 A1 AO Read Busy Flag and Address 0 1 BF A6 A5 AA A3 A2 Al AO Write Data to CG RAM or DD RAM 1 0 D7 D6 D5 DA D3 D2 D1 DO Read Data from CG RAM or DD RAM 1 1 D7 D6 D5 DA D3 D2 D1 DO Disabled If the LCD_E enable signal is Low all other inputs to the LCD are ignore
11. TXD 3 0 P15 E_TX_EN R4 TX_EN TXD4 TX_ER TX_CLK RXD 3 0 RX DV E TXD 4 E TX CLK E RXD 3 0 RJ 45 Connector E RX DV E RXD lt 4 gt E RX CLK E CRS E COL E MDC RXD4 RX ER RX CLK CRS COL MDC MDIO E 25 000 MHz E MDIO UG230 c14 02 022706 Figure 14 2 FPGA Connects to Ethernet PHY via MII Table 14 1 FPGA Connections to the LAN83C185 Ethernet PHY FPGA Pin Signal Name Number Function E TXD lt 4 gt R6 Transmit Data to the PHY E TXD 4 is also the MII E TXD lt 3 gt T5 Transmit Error E_TXD lt 2 gt R5 E_TXD lt 1 gt T15 E_TXD lt 0 gt R11 E TX EN P15 Transmit Enable E_TX_CLK T7 Transmit Clock 25 MHz in 100Base TX mode and 2 5 MHz in 10Base T mode E_RXD lt 4 gt U14 Receive Data from PHY E_RXD lt 3 gt v14 E_RXD lt 2 gt U11 E_RXD lt 1 gt T11 E_RXD lt 0 gt V8 E RX DV V2 Receive Data Valid www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX MicroBlaze Ethernet IP Cores Table 14 1 FPGA Connections to the LAN83C185 Ethernet PHY Continued FPGA Pin Signal Name Number Function E RX CLK V3 Receive Clock 25 MHz in 100Base TX mode and 2 5 MHz in 10Base T mode E CRS U13 Carrier Sense E COL U6 MII Collision Detect E MDC P9 Management Clock Serial management clock E_MDIO US Management
12. 2008 Chapter 4 FPGA Configuration Options XILINX Table 4 1 Spartan 3E Configuration Mode Jumper Settings Header J30 in Figure 4 2 Configuration Mode Pins Mode M2 M1 MO FPGA Configuration Image Source Jumper Settings BPI Down 0 1 1 StrataFlash parallel Flash PROM see starting at address OxIFF FFFF and Chapter 11 decrementing through address Intel space The CPLD controls address StrataPlash lines A 24 20 during BPI Parallel NOR configuration Flash PROM JTAG 0 1 0 Downloaded from host via USB JTAG port PROG Push Button The PROG push button shown in Figure 4 2 page 26 forces the FPGA to reconfigure from the selected configuration memory source Press and release this button to restart the FPGA configuration process at any time DONE Pin LED The DONE pin LED shown in Figure 4 2 page 26 lights whenever the FPGA is successfully configured If this LED is not lit then the FPGA is not configured 28 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 3 XILINX Programming the FPGA CPLD or Platform Flash PROM via USB Programming the FPGA CPLD or Platform Flash PROM via USB As shown in Figure 4 1 page 26 the Spartan 3E Starter Kit includes embedded USB based programming logic and an USB endpoint with a Type B connector Via a USB cable connection with the host PC the iMPACT programming software directly programs the FPGA
13. 4 s 34 Programming the Platform Flash PROM 38 Related Resoutces nanea 41 Chapter 5 Character LCD Screen enka 43 Character LCD Interface Signals 44 Voltage Compatibilidad REX RE EA FERRE eanet 44 Interaction with Intel StrataFlash 44 UCF Location Constraints 45 LCD Controller 45 Memory Map 3 dee ee aee e db e Fargo n e EU HR Rede le ede oie len 45 DORA Mis is oe ee que e du RE EN e S ed NI ss ae ata 45 CG ROM smaa siera anka Exe R dde obe rona Y epp e D CEPS OPER 46 CGRAM och apri RES A d peu dee Na ee ep tA eee deed 47 Command Set gedet I ERROR MENU P d RU CERT HO aee a Ran 48 Disabled ky RR A eee ee ay teks teh d x PRICE OPE EINE 49 Clear Display so ere ptr pe ace aueh et dh A deeds decane Ra etia 49 Return Cursor Home o uae tried en ea ie bene 49 Entry Mode Set raste Ga Je di aed d ea 49 IER 50 Cursor and Display Shift ici ee aided e ee pes ee drei E ya 50 PunctonSek es uya ae uluya a Swa ut aede Re ne UR Ca trs RR paletten 51 Set CG RAM Address 51 Set DDRAM Address es eerte it e Ge teda eR e a lec dee wae ie RD 51 Read Busy Flag and Address 51 Write Data to CG RAM or DD RAM
14. LVCMOS33 SLEW SLOW DRIVE 6 NET SPI SS B LOC U3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 NET SPI ALT CS JP11 LOC R12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 Slide Switches SW NET SW lt 0 gt LOC L13 IOSTANDARD LVTTL PULLUP NET SW 1 LOC L14 IOSTANDARD LVTTL PULLUP NET SW lt 2 gt LOC H18 IOSTANDARD LVTTL PULLUP NET SW lt 3 gt LOC N17 IOSTANDARD LVTTL PULLUP VGA Port VGA NET VGA BLUE LOC G15 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA GREEN LOC H15 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA HSYNC LOC F15 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA RED LOC H14 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA VSYNC LOC F14 IOSTANDARD LVTTL DRIVE 8 SLEW FAST Xilinx CPLD XC NET XC CMD 0 LOC P18 IOSTANDARD LVTTL DRIVE 4 SLEW SLOW NET XC CMD lt 1 gt LOC N18 IOSTANDARD LVTTL DRIVE 4 SLEW SLOW NET XC CPLD EN LOC B10 IOSTANDARD LVTTL NET XC D lt 0 gt LOC G16 IOSTANDARD LVTTL DRIVE 4 SLEW SLOW NET XC D lt 1 gt LOC F18 IOSTANDARD LVTTL DRIVE 4 SLEW SLOW NET XC D lt 2 gt LOG F17 IOSTANDARD LVTTL DRIVE 4 SLEW SLOW NET XC TRIG LOC R17 IOSTANDARD LVCMOS33 NET XC GCKO LOC HI6 IOSTANDARD LVCMO
15. The most commonly used command with the board is COMMANDJ3 0 0011 which immediately updates the selected DAC output with the specified data value Following the command the FPGA selects one or all the DAC output channels via a 4 bit address field Following the address field the FPGA sends a 12 bit unsigned data value that the DAC converts to an analog value on the selected output s Finally four additional dummy or don t care bits pad the 32 bit command word Specifying the DAC Output Voltage As shown in Figure 9 2 each DAC output level is the analog equivalent of a 12 bit unsigned digital value D 11 0 written by the FPGA to the DAC via the SPI interface The voltage on a specific output is generally described in Equation 9 1 The reference voltage VREFERENCE is different between the four DAC outputs Channels A and B use a 3 3V reference voltage and Channels C and D use a 2 5V reference The reference voltages themselves have a 5 tolerance so there will be slight corresponding variances in the output voltage D 11 0 OUT 4096 VREFERENCE Equation 9 1 DAC Outputs A and B Equation 9 2 provides the output voltage equation for DAC outputs A and B The reference voltage associated with DAC outputs A and B is 3 3V 5 _ D 11 0 OUTA 4096 x 3 3V 596 Equation 9 2 DAC Outputs C and D Equation 9 3 provides the output voltage equation for DAC outputs A and B The reference voltage associated wit
16. d9TT OI DL 101 331 SH1 8 0S3 dTT OI 8 ISQ ISOW NET OI 0319978 YMAS db TT dI ISIW suo IDUN y uote anb T uo3 1041009 Yds obe 4015 332918 4edunf GE AZ Bess op 16 UNS en d U SI OW em 62 3 QT 8d 000000 000000 288 MAI JIN OND AIL oal 101 SWL 4JepeeH e2ej4eiuI 9U1f UG230 Aa 05 021806 Schematic Sheet 6 Figure A 5 143 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Appendix A Schematics A XILINX FPGA I O Banks 0 and 1 Oscillators IC10B0 represents the connections to I O Bank 0 on the FPGA The VCCO input to Bank 0 is 3 3V by default but can be set to 2 5V using jumper JP9 IC10B1 represents the connections to I O Bank 1 on the FPGA IC17 is the 50 MHz clock oscillator Chapter 3 Clock Sources for additional information IC16 is an 8 pin DIP socket to insert an alternate clock oscillator with a different frequency 144 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 FPGA I O Banks 0 and 1 Oscillators XILINX ATHEN HU 4o0uing 99 4 urbu3 280 006 4914818 JES UI SQI 32013 1 pue g S3ueg 3SEOX 133HS 90 20 20 e1ieQ 900z Geez iubr4fhdoj ju 1USTI IO p4eog 419114818 3g ue 4eds S9IP YT ZI G ueenieq huer yey SUId 40 SJL SSION X 31200895 2191 180121 NTZT OI dIZT OI NOZ 1 OI dozT OI ZWIOHH
17. the Platform Flash PROM or the on board CPLD Direct programming of the parallel or serial Flash PROMs is not presently supported Connecting the USB Cable The kit includes a standard USB Type A Type B cable similar to the one shown in Figure 4 3 The actual cable color might vary from the picture USB Type B Connector Connects to Starter Kit s USB connector USB Type A Connector Connects to computer s USB connector UG230 c4 04 030306 Figure 4 3 Standard USB Type A Type B Cable The wider and narrower Type A connector fits the USB connector at the back of the computer After installing the Xilinx software connect the square Type B connector to the Spartan 3E FPGA Starter Kit board as shown in Figure 4 4 The USB connector is on the left side of the board immediately next to the Ethernet connector When the board is powered on the Windows operating system should recognize and install the associated driver software Figure 4 4 Connect the USB Type B Connector to the Starter Kit Board Connector UG230 c4 05 030306 When the USB cable driver is successfully installed and the board is correctly connected to the PC a green LED lights up indicating a good connection Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 29 UG230 v1 1 June 20 2008 Chapter 4 FPGA Configuration Options XILINX 30 Programming via iMPACT After successfully compiling an FPGA design using the Xilinx development softw
18. 56 www Xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Z XILINX Current through the horizontal deflection coil time Signal Timing for a 60 Hz 640x480 VGA Display pixel 0 0 pixel 0 639 kang A L 640 pixels are displayed each time the beam traverses the screen VGA Display Retrace No information pixel 479 0 pixel 479 639 is displayed during this time gt Stable current ramp Information is displayed during this time Total horizontal time Horizontal display time retrace time tug A E 9 front porch L front porch s Ke L Horizontal sync signal L back porch sets the retrace frequency UG230 c6 02 021706 Figure 6 2 CRT Display Timing Example The display resolution defines the size of the beams the frequency at which the beam traces across the display and the frequency at which the electron beam is modulated Modern VGA displays support multiple display resolutions and the VGA controller dictates the resolution by producing timing signals to control the raster patterns The controller produces TTL level synchronizing pulses that set the frequency at which current flows through the deflection coils and it ensures that pixel or video data is applied to the electron guns at the correct time Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location The Spartan 3E FPG
19. B Example User Constraints File UCF provides example code from a UCE Additional Resources To find additional documentation see the Xilinx website at http www xilinx com support documentation index htm To search the Answer Database of silicon software and IP questions and answers or to create a technical support WebCase see the Xilinx website at http www xilinx com support 10 www xilinx com Spartan 3E Start Kit Board User Guide UG230 v1 1 June 20 2008 2 XILINX Chapter 1 Introduction and Overview Thank you for purchasing the Xilinx Spartan 3E FPGA Starter Kit You will find it useful in developing your Spartan 3E FPGA application Choose the Starter Kit Board for Your Needs Depending on specific requirements choose the Xilinx development board that best suits your needs Spartan 3E FPGA Features and Embedded Processing Functions The Spartan 3E Starter Kit board highlights the unique features of the Spartan 3E FPGA family and provides a convenient development board for embedded processing applications The board highlights these features e Spartan 3E FPGA specific features Parallel NOR Flash configuration MultiBoot FPGA configuration from Parallel NOR Flash PROM SPIserial Flash configuration e Embedded development MicroBlaze 32 bit embedded RISC processor PicoBlaze 8 bit embedded controller DDR memory interfaces Advanced Spartan 3 Generation Developmen
20. DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE Figure 15 7 UCF Location Constraints for Accessory Headers www xilinx com II lI o I lI FAST DRIVE FAST DRIVE FAST DRIVE FAST DRIVE f I II Wo H H H W H H H d H H WW H H H W H H H H H W W H H H H H 0 o OO O0 O0 OO O0 O0 O0 O0 00000 0 0000 0000 O0 o O0 CO OO CO CO COO CO CO I co OO OO Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Six Pin Accessory Headers Six Pin Accessory Headers The 6 pin accessory headers provide easy I O interface expansion using the various Digilent Peripheral Modules see Related Resources page 126 The location of the 6 pin headers is provided in Figure 15 1 page 115 Header J1 The J1 header shown in Figure 15 8 is the top most 6 pin connector along the right edge of the board It uses a female 6 pin 90 socket Four FPGA pins connect to the J1 header FX2 IO lt 4 1 gt These four signals are also shared with the Hirose FX2 connector The board supplies 3 3V to the accessory board mounted in the J1 socket on the bottom pin Spartan 3E FPGA Ji UG230_c12_07_022406 Figure 15 8 FPGA Connections to the J1 Accessory Header Header J2 The J2 header shown in Figure 15 9 is the bottom most 6 pin connector along the right edge of the board It uses a female 6 pin 90 s
21. DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE E PPP A A IA A PP PPP IA A A A A A A A A A SD A A HD A A A A A DDD gu ga gu ga A us AL SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 www xilinx com 165 Appendix B Example User Constraints File UCF XILINX NET SF OE LOC C18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF STS LOC B18 IOSTANDARD LVCMOS33 NET SF WE LOG D17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW H STMicro SPI serial Flash SPI H some connections shared with SPI Flash DAC ADC and AMP NET SPI MISO LOC N10 IOSTANDARD LVCMOS33 NET SPI MOSI LOC T4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 NET SPI SCK LOC U16 IOSTANDARD
22. DRIVE 8 HNET FX2 IO lt 20 gt LOC F12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 TO lt 21 gt LOC A13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 10 lt 22 gt LOC B13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 10 lt 23 gt LOC A14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 TO lt 24 gt LOC B14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 TO lt 25 gt LOC C14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 10 lt 26 gt LOC D14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Z XILINX NET FX2 10 lt 27 gt LOC A16 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 10 lt 28 gt LOC B16 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 10 lt 29 gt LOC E13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 TO lt 30 gt LOC Ca IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 TO lt 31 gt LOC B11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 10 lt 32 gt LOC A11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 TO lt 33 gt LOC A8 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 TO lt 34 gt LOC G9 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IP lt 35 gt LOC D12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IP lt 36 gt LOC C12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE
23. Display Port describes the functionality of the VGA port e Chapter 7 RS 232 Serial Ports describes the functionality of the RS 232 serial ports e Chapter 8 PS 2 Mouse Keyboard Port describes the functionality of the PS 2 mouse and keyboard port e Chapter 9 Digital to Analog Converter DAC describes the functionality of the DAC e Chapter 10 Analog Capture Circuit describes the functionality of the A D converter with a programmable gain pre amplifier e Chapter 11 Intel StrataFlash Parallel NOR Flash PROM describes the functionality of the StrataFlash PROM e Chapter 12 SPI Serial Flash describes the functionality of the SPI Serial Flash memory e Chapter 13 DDR SDRAM describes the functionality of the DDR SDRAM e Chapter 14 10 100 Ethernet Physical Layer Interface describes the functionality of the 10 100Base T Ethernet physical layer interface e Chapter 15 Expansion Connectors describes the various connectors available on the Spartan 3E FPGA Starter Kit board e Chapter 16 XC2C64A CoolRunner II CPLD describes how the CPLD is involved in FPGA configuration when using Master Serial and BPI mode e Chapter 17 DS2432 1 Wire SHA 1 EEPROM provides a brief introduction to the SHA 1 secure EEPROM for authenticating or copy protecting FPGA configuration bitstreams e Appendix A Schematics lists the schematics for the Spartan 3E FPGA Starter Kit board e Appendix
24. Figure 4 6 Right Click to Assign a Configuration File to the Spartan 3E FPGA UG230 c4 07 022406 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Programming the FPGA CPLD or Platform Flash PROM via USB If the original FPGA configuration file used the default StartUp clock source CCLK iMPACT issues the warning message shown in Figure 4 7 This message can be safely ignored When downloading via JTAG the iMPACT software must change the StartUP clock source to use the TCK JTAG clock source WARNING iMPACT 2257 Startup Clock has been changed to JtagClk in the bitstream stored in memory but the original bitstream File remains unchanged UG230 c4 08 022406 Figure 4 7 iMPACT Issues a Warning if the StartUp Clock Was Not CCLK To start programming the FPGA right click the FPGA and select Program The iMPACT software reports status during programming process Direct programming to the FPGA takes a few seconds to less than a minute depending on the speed of the PC s USB port and the iMPACT settings iMPACT C data my designs s3e starter kit s3e starter kit ipf Boundary Scan EL File Edit View Operations Options Output Debug Window Help lg El DBX axu 4 X 29 Boundary Scan L S3SlaveSeial LLL 4 EgSelectMAP t Gal Desktop Configu e LIS SystemA CE El k Parify xc3
25. Flash 7 4 Character LCD DB 7 4 The StrataFlash PROM provides various functions Stores a single FPGA configuration in the StrataFlash device aoocoocoooooooocooocccoooooocoooooocooccoooocccocooomeo UG230_c11_01_030206 Connections to Intel StrataFlash Flash Memory Stores two different FPGA configurations in the StrataFlash device and dynamically switch between the two using the Spartan 3E FPGA s MultiBoot feature Stores and executes MicroBlaze processor code directly from the StrataFlash device Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 www xilinx com 83 Chapter 11 Intel StrataFlash Parallel NOR Flash PROM XILINX e Stores MicroBlaze processor code in the StrataFlash device and shadows the code into the DDR memory before executing the code e Stores non volatile data from the FPGA StrataFlash Connections 84 Table 11 1 shows the connections between the FPGA and the StrataFlash device Although the XC3S500E FPGA only requires just slightly over 2 Mbits per configuration image the FPGA to StrataFlash interface on the board support up to a 256 Mbit StrataFlash The Spartan 3E FPGA Starter Kit board ships with a 128 Mbit device Address line SF A24 is not used In general the StrataFlash device connects to the XC3S500E to support Byte Peripheral Interface BPI configuration The upper four address bits from the FPGA A 23 19 do not connect directly to th
26. JTAG circuitry follow the steps outlined in this subsection Place the iMPACT software in the JTAG Boundary Scan mode either by choosing Boundary ScanintheiMPACT Modes pane as shown in Figure 4 22 or by clicking on the Boundary Scantab 38 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Programming the FPGA CPLD or Platform Flash PROM via USB iMPACT C data my designs s3e starter kit s3e starter kit iph EL File Edit View Operations Options Output Debug Window Help Ig H B BD SRG E Boundary Scan y al SlaveSerial i Be SelectMAP Desktop Configu i E SystemACE xc3s500e toplevel bit file E TDO iMPACT Process Operations Boundary Scan Prom File Forma UG230 c4 23 022706 Figure 4 22 Switch to Boundary Scan Mode Assign the PROM file to the XCFO4S Platform Flash PROM on the JTAG chain as shown in Figure 4 23 Right click the PROM icon then click Assign New Configuration File Select a previously generated PROM format file and click OK TDI sou P Erase Blank Check xc3s500e xcf toplevel bit file Readback Get Device ID Get Device Checksum Get Device Signature Usercode Assign New Configuration File bk Figure 4 23 Assign the PROM File to the XCF04S Platform Flash PROM UG230 c4 24 022806 To start programming the PROM right click the PROM icon and
27. JTAG header IC12 is a Maxim Dallas Semiconductor DS2432 SHA 1 EEPROM See Chapter 17 DS2432 1 Wire SHA 1 EEPROM for more information IC14 and IC15 are alternate landing pads for the STMicro SPI serial Flash IC14 accepts the 16 pin SOIC package option while IC15 accepts either the 8 pin SOIC or MLP package option See Figure 12 18 page 108 for additional informaton www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 FPGA Configurations Settings Platform Flash PROM SPI Serial Flash JTAG Connections XILINX v 1 9 119945 90 20 20 s e 280 0068 NUS 404 NY our pue LOTIBAMBTJUOD 3SE2X 133HS 99 48eutpuz sde GSN wuaojieId Pappaquy eui 40 JepesH e2ejaeiu gulf y uey 4eyie4 UoTIISOd paeoq e4eudraed e wod USATAP Bured aye STEUDIS gylf eui uaum ureu2 ue3s aui aije duo5 oi Japesy gL eui uo OGL pue IG Usamiaq pejreisur eq snw DOIG buri2ous y 9eaz Geez iubr4fdoj dul 1USTIBIA pJeog 4814818 j ue Jeds INO 30091 40 peo 38991 uo peo ON 2909 uo peo Z8U NT 4NT ANTO 829 223 929 AIS 00S 108 IdS 4ugT 39426 M 282 982 KOT Z S Hr OL 910S 9IdGzW uori3npoag 40j peo oN 6er O dYMSH NSZT OI ASna 1noGQ Z dET OI 8 LINI Z NTT OI 90 NIG Z NYTT OI a 908d ZIOT T NYTT OI 3N00 1901 1 dez OI X192 Z NYZT OI 820 1 T NEZT OI 90H T dEZ OI ZH TAT99 Z NYTT dI W Z FOI DU
28. Key Components and Features 12 Design Trade Offs Eege deer vp pa dapes d Pp Oa ORAE GE C a N K 13 Configuration Methods Galorel ee 13 Voltages for all Applications 13 Related Resources dcus ded ahi ed aad uad aule dai TER eta f di hr 13 Chapter 2 Switches Buttons and Knob Slide Switches 15 Locations and Labels ei id vu ae a qa EN etes 15 EE ee e S A ed Ua IA AAA 15 UCF Location Constraints 15 Push Button Switches 16 Locations and Labels 16 OP TAHON mm 16 UCF Location Constraints 17 Rotary Push Button Switch 17 Locations and Labels iii ree tid coat deve treed EC De Nod etie P ee Ed 17 ODperatiOni cos ee der d Pee A TEA rcd cea a 17 Push Button Switch 2 0 0 0 ccc ce eee e e e 17 Rotary ShaftEncoder ike der RI P EX pbs EE HEN EEN eda 18 UCF Location Constraints 19 Discrete LEDS xii EXER dida ia 19 Locations and Labels 2 19 Op erati fl ien Et tas iras ras 20 UCF Location Constraints 20 Related Resources
29. LOC J2 IOSTANDARD SSTL2 I NET SD LDQS LOC L6 IOSTANDARD SSTL2 I NET SD RAS LOC CIT IOSTANDARD SSTL2 I NET SD UDM LOC Ji IOSTANDARD SSTL2 I NET SD UDQS LOC 2 G3 IOSTANDARD SSTL2 I NET SD WE LOC Di IOSTANDARD SSTL2 I Path to allow connection to top DCM connection NET SD CK FB LOC B9 IOSTANDARD LVCMOS33 Prohibit VREF pins CONFIG PROHIBIT D2 CONFIG PROHIBIT G4 CONFIG PROHIBIT J6 CONFIG PROHIBIT L5 CONFIG PROHIBIT R4 Intel StrataFlash Parallel NOR Flash SF NET SF A lt 0 gt LOC BLY IOSTANDARD LVCMOS33 NET SF A lt 1 gt LOC Jis IOSTANDARD LVCMOS33 NET SF A lt 2 gt LOC JL2 IOSTANDARD LVCMOS33 NET SF A lt 3 gt LOC J14 IOSTANDARD LVCMOS33 NET SF A lt 4 gt LOC JLS IOSTANDARD LVCMOS33 NET SF A lt 5 gt LOC J16 IOSTANDARD LVCMOS33 NET SF_A lt 6 gt LOC MJIN IOSTANDARD LVCMOS33 NET SF_A lt 7 gt LOC K14 IOSTANDARD LVCMOS33 NET SF A lt 8 gt LOC K15 IOSTANDARD LVCMOS33 NET SF A lt 9 gt LOC K12 IOSTANDARD LVCMOS33 NET SF A lt 10 gt LOC K13 IOSTANDARD LVCMOS33 NET SF A lt 11 gt LOC L15 IOSTANDARD LVCMOS33 NET SF A lt 12 gt LOC L16 IOSTANDARD LVCMOS33 NET SF A lt 13 gt LOC T18 IOSTANDARD LVCMOS33 NET SF A lt 14 gt LOC R18 IOSTANDARD LVCMOS33 NET SF A lt 15 gt LOC T17 IOSTANDARD LVCMOS33 NET SF A lt 16 gt LOC U18 IOSTANDA
30. LOC U16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET SPI MISO LOC N10 IOSTANDARD LVCMOS33 Figure 10 8 UCF Location Constraints for the ADC Interface 80 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 3 XILINX Disable Other Devices on the SPI Bus to Avoid Contention Disable Other Devices on the SPI Bus to Avoid Contention The SPI bus signals are shared by other devices on the board It is vital that other devices are disabled when the FPGA communicates with the AMP or ADC to avoid bus contention Table 10 4 provides the signals and logic values required to disable the other devices Although the StrataFlash PROM is a parallel device its least significant data bit is shared with the SPI MISO signal The Platform Flash PROM is only potentially enabled if the FPGA is set up for Master Serial mode configuration Table 10 4 Disable Other Devices on SPI Bus Signal Disabled Device Disable Value SPI SS B SPI Serial Flash 1 AMP CS Programmable Pre Amplifier 1 DAC CS DAC 1 SF CEO StrataFlash Parallel Flash PROM 1 FPGA INIT B Platform Flash PROM 1 Connecting Analog Inputs Connect AC signals to VINA or VINB via a DC blocking capacitor Related Resources Amplifier and A D Converter Control for the Spartan 3E Starter Kit Reference Design http www xilinx com s3estarter Xilinx PicoBlaze Soft Processor http www xilinx
31. NET SF A lt 13 gt LOC T18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 12 gt LOC L16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 11 LOC L15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 10 gt LOC K13 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 9 LOC K12 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 8 LOC K15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 7 gt LOC K14 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 6 gt LOC J17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 5 gt LOC J16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 4 LOC J15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 3 gt LOC J14 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 2 gt LOC J12 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 1 gt LOC J13 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 0 gt LOC H17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW Figure 11 2 UCF Location Constraints for StrataFlash Address Inputs Data Figure 11 3 provides the UCF constraints for the StrataFlash data pins including the I O pin assignment and the I O standard used NET SF D 15 LOC T8 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 14 LOC R8 IOSTANDARD
32. Schematic Sheet 14 Figure A 13 159 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Appendix A Schematics XILINX 160 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 2 XILINX Appendix B Example User Constraints File UCF TRER EDD DDR DDD DDR EEEHEEHE EHE TEE THE EHE EHE EHHHHHHHHHHHHHBHBHBE SPARTAN 3E STARTER KIT BOARD CONSTRAINTS FILE TRR EDD DDR DDD DDD DR DR LHH HH HHHH HHHH EHE EHEHHHHHHHHHHHHBBHBE Analog to Digital Converter ADC some connections shared with SPI Flash DAC ADC and AMP NET AD CONV LOC PIL IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 Programmable Gain Amplifier AMP some connections shared with SPI Flash DAC ADC and AMP NET AMP CS LOC N7 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 NET AMP DOUT LOC E18 IOSTANDARD LVCMOS33 NET AMP SHDN LOC P7 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 Pushbuttons BTN NET BTN EAST LOC H13 IOSTANDARD LVTTL PULLDOWN NET BTN NORTH LOC v4 IOSTANDARD LVTTL PULLDOWN NET BTN SOUTH LOC K17 IOSTANDARD LVTTL PULLDOWN NET BTN WEST LOC D18 IOSTANDARD LVTTL PULLDOWN Clock inputs CLK NET CLK 50MHZ LOC C9 IOSTANDARD LVCMOS33 Define clock period for 50 MHz oscillator 40 60 duty cyc
33. Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 125 Chapter 15 Expansion Connectors XILINX Related Resources 126 Hirose connectors http www hirose connectors com FX2 Series Connector Data Sheet http www hirose co jp cataloge hp e57220088 pdf Digilent Inc Peripheral Modules http www digilentinc com Products Catalog cfm Nav1 Products amp Nav2 Peripheral amp Cat Peripheral Xilinx ChipScope Pro Tool http www xilinx com ise optional prod cspro htm Agilent B4655A FPGA Dynamic Probe for Logic Analyzer http cp literature agilent com litweb pdf 5989 0423EN pdf Agilent 5404A 6A Pro Series Soft Touch Connector http www home agilent com agilent product jspx cc US amp lc eng amp pageMode O V amp pid 430362 amp ct PRODUCT amp id 430362 Tektronix P69xx Probe Module s with D Max Technology http www tek com products accessories logic analyzers p6800 p6900 html www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 2 XILINX Chapter 16 XC2C64A CoolRunner II CPLD The Spartan 3E FPGA Starter Kit board includes a Xilinx XC2C64A CoolRunner II CPLD The CPLD is user programmable and available for customer applications Portions of the CPLD are reserved to coordinate behavior between the various FPGA configuration memories namely the Xilinx Platform Flash PROM and the Intel StrataFlash PROM Consequently the CPLD must provide the following
34. Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Chapter 3 Clock Sources Overview As shown in Figure 3 1 the Spartan 3E FPGA Starter Kit board supports three primary clock input sources all of which are located below the Xilinx logo near the Spartan 3E logo e The board includes an on board 50 MHz clock oscillator Clocks can be supplied off board via an SM A style connector Alternatively the FPGA can generate clock signals or other high speed signals on the SMA style connector Optionally install a separate 8 pin DIP style clock oscillator in the supplied socket Bank 0 Oscillator Voltage 8 Pin DIP Oscillator Socket Controlled by Jumper JP9 CLK AUX B8 Plathwm Flash NC P www xi com em pp a a 3SPAKTAN 3E o EN 28 On Board 50 MHz Oscillator SMA Connector CLK_50MHz C9 CLK SMA A10 UG230 c3 01 030306 Figure 3 1 Available Clock Inputs Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 21 UG230 v1 1 June 20 2008 Chapter 3 Clock Sources A XILINX Clock Connections Each of the clock inputs connect directly to a global buffer input in I O Bank 0 along the top of the FPGA As shown in Table 3 1 each of the clock inputs also optimally connects to an associated DCM Table 3 1 Clock Inputs and Associated Global Buffers and DCMs Clock Input FPGA Pin Global Buffer Associated DCM CLKS50MHZ C9 on DCMXOY CLK AUX B8 GC
35. The FPGA must read the first SPI MISO value on the first rising SPI SCK edge after DAC CS goes Low Otherwise bit 31 is missed After transmitting all 32 data bits the FPGA completes the SPI bus transaction by returning the DAC CS slave select signal High The High going edge starts the actual digital to analog conversion process within the DAC Communication Protocol Figure 9 4 shows the communications protocol required to interface with the LTC2624 DAC The DAC supports both a 24 bit and 32 bit protocol The 32 bit protocol is shown Inside the D A converter the SPI interface is formed by a 32 bit shift register Each 32 bit command word consists of a command an address followed by data value As a new command enters the DAC the previous 32 bit command word is echoed back to the master The response from the DAC can be ignored although it is a useful to confirm correct communication Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 71 UG230 v1 1 June 20 2008 Chapter 9 Digital to Analog Converter DAC XILINX SPI MISO Slave LTC2624 DAC 31 V G H G OE TT Spartan 3E SPI SCK Don t Care Don t Care 12 bit Unsigned DATA COMMAND ADDRESS ay 22 21 ao jofolofo Daca oo o 1 DACB Dono HIH I Figure 9 4 SPI Communications Protocol to LTC2624 DAC UG230_c9_04_021806 The FPGA first sends eight dummy or don t care bits followed by a 4 bit command
36. Timing Waveforms The keyboard uses open collector drivers so that either the keyboard or the host can drive the two wire bus If the host never sends data to the keyboard then the host can use simple input pins A PS 2 style keyboard uses scan codes to communicate key press data Nearly all keyboards in use today are PS 2 style Each key has a single unique scan code that is sent whenever the corresponding key is pressed The scan codes for most keys appear in Figure 8 3 If the key is pressed and held the keyboard repeatedly sends the scan code every 100 ms or so When a key is released the keyboard sends an FO key up code followed by the scan code of the released key The keyboard sends the same scan code regardless if a key has different shift and non shift characters and regardless whether the Shift key is pressed or not The host determines which character is intended Some keys called extended keys send an E0 ahead of the scan code and furthermore they might send more than one scan code When an extended key is released an E0 FO key up code is sent followed by the scan code www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Z XILINX ESC 76 EE SCH Shift e 12 Ctrl 14 Keyboard F1 F3 F4 F5 F6 F7 F8 F9 F11 F12 05 04 OC 03 08 83 0A 01 78 07 0 75 El ES Ed Ka ES ES EJ p bi m ES Back Space ch ES Ed K
37. a watchdog timer in the CPLD used during fail safe MultiBoot configurations See Chapter 16 XC2C64A CoolRunner II CPLD for more information www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XC2C64A CoolRunner Il CPLD SC XILINX v1 01 199u8S BHO oui 140uing 39 48eutpuz 90 20 20 9120 280 008 4974818 JES 371111 Q1d3 9IZIX 133HS 9eaz S z iubr4Rdoj ul 14911761 pJeog 4914815 jg ueia4edg 442p 4401 43427 JUOT 812 2812 1819 0819 1Z0I ZIZOI ZAD99 01Z01 1439 8 Z0I 95139 2820I 90201 S ZOI Z ZOI T ZOI uS9 ETIOI ZS19 TT1OI ES19 TTTOI S19 TTOI 1819 60101 TOI Z TOI 9IZIX 18701 391 DL 10L SWL N NE T A Or o d 3UZb SUBT Zx0199N Tx0199N 6219 8219 442 AUBT 2219 9219 UG230_Aa_09_021806 Schematic Sheet 10 Figure A 9 151 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Appendix A Schematics A XILINX Linear Technology ADC and DAC 152 IC19 is a Linear Technology LTC1407A 1 two channel ADC IC20 is a Linear Technology LTC6912 programmable pre amplifier AMP to condition the analog inputs to the ADC See Chapter 10 Analog Capture Circuit for additional information IC21 is a Linear Technology LTC2624 four channel DAC See Chapter 9 Digital to Analog Converter DAC for additional information www xilinx com Spartan 3E FPGA Starte
38. approximately 120 On chip differential termination is only available on I O pairs not on Input only pairs like pairs 15 and 16 in Table 15 2 Pads for 100 Differential termination g surface mount resistor 120Q LxxN 0 LxxN 0 LoNO E gt lt IM LxxP_0 Sa Rei LxxP O E 3 signal eS p a External 1000 termination resistor b On chip differential termination UG230 c12 03 022406 Figure 15 3 Differential Input Termination Options Figure 15 4 and Figure 15 5 show the locations of the differential input termination resistor landing pads on the top and bottom side of the board Table 15 2 indicates which resistor is associated with a specific differential pair LE LIS E De os Si amis o IC11 NO Jur ENTS S XILIN www xilinx con SOMHZ sILENT 55 q ICl entinc com S iht 2006 g 55 JSPARTAN 3 R295 Ee m Ser Pe Ei 4 6 Eer 5 a SMST Flash UG230 c12 04 022406 Figure 15 4 Location of Termination Resistor Pads on Top Side of Board 120 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 A XILINX Hirose 100 pin FX2 Edge Connector J3 UG230 c12 05 022406 Figure 15 5 Location of Termination Resistor Pads on Bottom Side of Board Using Differential Outputs Differential input signals do not require any special voltage LVDS and RSDS differential outputs signals on the other hand require a 2 5V supply on I
39. controls such as in the operation of nuclear facilities aircraft navigation or communications systems air traffic control life support or weapons systems High Risk Applications Xilinx specifically disclaims any express or implied warranties of fitness for such High Risk Applications You represent that use of the Design in such High Risk Applications is fully at your risk 2006 2008 Xilinx Inc All rights reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc All other trademarks are the property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 03 09 06 1 0 Initial release 06 20 08 1 1 Clarified DTE connections in Figure 7 1 Updated links Spartan 3E FPGA Starter Kit Board User Guide www xilinx com UG230 v1 1 June 20 2008 Table of Contents Preface About This Guide Acknowledgements 2 521222 irri ARA AA RR ROC KCN 9 Guide Contents 9 Additional Resources 10 Chapter 1 Introduction and Overview Choose the Starter Kit Board for Your Needs 11 Spartan 3E FPGA Features and Embedded Processing Functions 11 Advanced Spartan 3 Generation Development Boards 11
40. eee ends tennis Programming Header J12 Multi Package Layout 4 44 qatu e e eh n Related Resources Chapter 13 DDR SDRAM DDR SDRAM Connections UCF Location Constraints AUTOS cna io en ae rad act aree TRR a cles Data 3 sien io RE bx Rb ED be diem reed Na a Kaas AE Controla ii Meet ses ve cite Mal te e Reserve FPGA VREF bPms RR RR RR IRR es Related Resources Chapter 14 10 100 Ethernet Physical Layer Interface Ethernet PHY Connections www Xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Z XILINX MicroBlaze Ethernet IP Cores Re 113 UCF Location Constraints 114 Related Resources 114 Chapter 15 Expansion Connectors Hirose 100 pin FX2 Edge Connector J3 115 Voltage Supplies to the Connector 116 Connector Pinout and FPGA Connections 116 Compatible Board TTT 118 Mating Receptacle Connectors 118 Differe
41. from the CPLD if used must be configured as an open drain out i e either actively drives Low or floats to Hi Z never drives High This signal connects directly to the FPGA s PROG B programming pin The most siginficant StrataFlash PROM address bit SF A lt 24 gt is the same as the FX2 connector signal called FX2_IO lt 32 gt The 16 Mbyte StrataFlash PROM only physically uses the lower 24 bits SF A lt 23 0 gt The extra address bit SF A lt 24 gt is provided for upward density migration for the StrataFlash PROM Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 127 UG230 v1 1 June 20 2008 Chapter 16 XC2C64A CoolRunner ll CPLD XILINX 3 3V JP10 XC2C64A VQ44 WDT EN CoolRunner Il CPLD T XC WDT EN OG Y Spartan 3E FPGA XC CMD 1 XC CMD lt 0 gt XC D 2 XC_D lt 1 gt XC_D lt 0 gt FPGA_M2 FPGA M1 FPGA MO XC CPLD EN XC TRIG XC DONE Required for Master Serial Mode Enable Platform Flash PROM when M 2 0 000 XCF04S Platform Flash PROM XC PROG B XC GCKO GCLK10 SPI SCK FX2_10 lt 32 gt F_A lt 24 gt SF_A lt 23 gt SF_A lt 22 gt SF_A lt 21 gt SF_A lt 20 gt During Configuration BPI Up A 24 20 00000 BPI Down A 24 20 11111 After Configuration or Other Modes A 24 20 ZZZZ Intel StrataFlash SF A lt 19 0 gt A 23 20 Unconnected UG230 c16 01 030906 Figure 16 1 XC2
42. functions in addition to the user application e When the FPGA is in the Master Serial configuration mode FPGA_M lt 2 0 gt 000 generate an active Low enable signal for the XCF04S Platform Flash PROM The Platform Flash PROM is disabled in all other configuration modes The CPLD helps reduce the number of jumpers on the board and simplifies the interaction of all the possible FPGA configuration memory sources e When the FPGA is actively in the BPI Up configuration mode FPGA_M lt 2 0 gt 010 DONE 0 set the upper five StrataFlash PROM address lines A 24 20 to 00000 binary When the FPGA is actively in the BPI Down configuration mode FPGA_M lt 2 0 gt 011 DONE 0 set the upper five StrataFlash PROM address lines A 24 20 to 11111 binary Set the upper five address lines to ZZZZZ for all non BPI configuration modes or whenever the FPGA s DONE pin is High This behavior is identifical to the way the FPGA s upper address lines function during BPI mode So why add a CPLD to mimic this behavior A future reference design demonstrates unique configuration capabilities In a typical BPI mode application the CPLD is not required Other than the required CPLD functionality there are between 13 to 21 user I O pins and 58 remaining macrocells available to the user application Jumper JP10 WDT EN defines the state on the CPLD s XC WDT EN signal By default this jumper is empty and the signal is pulled to a logic High The XC_PROG_B output
43. gt LOC D5 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 TO lt 4 gt LOC C5 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 These four connections are shared with the J2 6 pin accessory header NET FX2 TO lt 5 gt LOC A6 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 TO lt 6 gt LOC B6 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 TO lt 7 gt LOC E7 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 TO lt 8 gt LOC F7 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 These four connections are shared with the J4 6 pin accessory header NET FX2 TO lt 9 gt LOC D7 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO lt 10 gt LOC C7 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 TO lt 11 gt LOC F8 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 TO lt 12 gt LOC E8 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 The discrete LEDs are shared with the following 8 FX2 connections HNET FX2 IO lt 13 gt LOC F9 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 HNET FX2 IO lt 14 gt LOC E9 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 HNET FX2 IO lt 15 gt LOC D11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 HNET FX2 IO 16 LOC C11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO lt 17 gt LOC F11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 HNET FX2 IO lt 18 gt LOC E11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 HNET FX2 IO lt 19 gt LOC E12 IOSTANDARD LVCMOS33 SLEW FAST
44. on a line The cursor automatically moves to the second line when it shifts beyond the 40th character location of the first line The first and second line displays shift at the same time When the displayed data is shifted repeatedly both lines move horizontally The second display line does not shift into the first display line Execution Time 40 us www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX LCD Controller Table 5 4 Shift Patterns According to S C and R L Bits DB3 DB2 S C R L Operation 0 0 Shift the cursor position to the left The address counter is decremented by one 0 1 Shift the cursor position to the right The address counter is incremented by one Shift the entire display to the left The cursor follows the display shift The address counter is unchanged Shift the entire display to the right The cursor follows the display shift The address counter is unchanged Function Set Sets interface data length number of display lines and character font The Starter Kit board supports a single function set with value 0x28 Execution Time 40 us Set CG RAM Address Set the initial CG RAM address After this command all subsequent read or write operations to the display are to or from CG RAM Execution Time 40 us Set DD RAM Address Set the initial DD RAM address After this command all subsequentsubsequent re
45. one location after each Write Data to CG RAM or DD RAM or Read Data from CG RAM or DD RAM command The cursor or blink position moves accordingly Bit DBO S Shift 0 Shifting disabled 1 During a DD RAM write operation shift the entire display value in the direction controlled by Bit DB1 I D Appears as though the cursor position remains constant and the display moves Display On Off Display is turned on or off controlling all characters cursor and cursor position character underscore blink Execution Time 40 us Bit DB2 D Display On Off 0 No characters displayed However data stored in DD RAM is retained 1 Display characters stored in DD RAM Bit DB1 C Cursor On Off The cursor uses the five dots on the bottom line of the character The cursor appears as a line under the displayed character 0 No cursor 1 Display cursor Bit DBO B Cursor Blink On Off 0 Nocursor blinking 1 Cursor blinks on and off approximately every half second Cursor and Display Shift Moves the cursor and shifts the display without changing DD RAM contents Shift cursor position or display to the right or left without writing or reading display data This function positions the cursor in order to modify an individual character or to scroll the display window left or right to reveal additional data stored in the DD RAM beyond the 16th character
46. the push buttons appear in parentheses in Figure 2 3 and the associated UCF appears in Figure 2 5 Rotary Push Button Switch ROT A K18 Requires an internal pull up BTN NORTH ROT B G18 Requires an internal pull up V4 ROT CENTER V16 Requires an internal pull down BTN WEST D18 BTN EAST H13 BTN SOUTH K17 UG230 c2 02 021206 Notes 1 All BTN push button inputs require an internal pull down resistor 2 BTN SOUTH is also used as a soft reset in some FPGA applications Figure 2 3 Four Push Button Switches Surround Rotary Push Button Switch Operation Pressing a push button connects the associated FPGA pin to 3 3V as shown in Figure 2 4 Use an internal pull down resistor within the FPGA pin to generate a logic Low when the button is not pressed Figure 2 5 shows how to specify a pull down resistor within the UCE There is no active debouncing circuitry on the push button www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Rotary Push Button Switch Push Button FPGA I O Pin 3 3V RIT BTN Signal UG230 c2 03 021206 Figure 2 4 Push Button Switches Require an Internal Pull Down Resistor in FPGA Input Pin In some applications the BTN SOUTH push button switch is also a soft reset that selectively resets functions within the FPGA UCF Location Constraints Figure 2 5 provides the UCF constraints for the four push button switches including the I O
47. then click Program Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 39 UG230 v1 1 June 20 2008 Chapter 4 FPGA Configuration Options XILINX TD verify xc3sS00e SCT taplevel bit myplat or 298 oee Blank Check Readback Get Device ID Get Device Checksum Get Device Signature Usercode Assign New Configuration File UG230 c4 25 022806 Figure 4 24 Program the XCFO4S Platform Flash PROM The programming software again prompts for the PROM type to be programmed Select xcf04s and click OK as shown in Figure 4 25 r Select PROM Part Name xcf04s v Cancel Help UG230_c4_26_022806 Figure 4 25 Select XCF04S Platform Flash PROM Before programming choose the programming options available in Figure 4 26 Checking the Erase Before Programming option erases the Platform Flash PROM completely before programming ensuring that no previous data lingers The Verify option checks that the PROM was correctly programmed and matches the downloaded configuration bitstream Both these options are recommended even though they increase overall programming time The Load FPGA option immediately forces the FPGA to reconfigure after programming the Platform Flash PROM The FPGA s configuration mode pins must be set for Master Serial mode as defined in Table 4 1 page 27 Click OK when finished 40 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1
48. 1 June 20 2008 3 XILINX Spartan 3E FPGA Starter Kit Board User Guide XXXXO0000 xxx xO00 1 E xxxx0010 xxxx001 1 3 xxxx0 100 8 XXXXO101 LKKKKOTTIO A Z xxxx0111 E sexi 1000 E xxxx 1001 7 xxxx 1010 xXxxx1011 xxxx 1100 xxxx1101 XXXX1110 Xxxx1111 O CN O mmmm anna He dEl di oe eJ Mi HE m vo GO ll CTI E Cel 3 leo U AAA e Ta M E cal D Elek APE dao LCD Controller per Data Nibble Ke D I EE x Kal 1 1 SP E E E H E Adm S L Lal 2 eee fe cm e m o EA A S UT a dE St EH a al E o Ad SH A EE E a L gt TE Pall Ef gt lt EEE un ag i oo IF HA ole Fu n eo mu A G Ub te TH 2 6 ja joo 2 T d ri pmi ep EE Dene mate ass B B E E B UG230 c5 02 030306 Figure 5 4 LCD Character Set The character ROM contains the ASCII English character set and Japanese kana characters The controller also provides for eight custom character bitmaps stored in CG RAM These eight custom characters are displayed by storing character codes 0x00 through 0x07 in a DD RAM location CG RAM The Character Generator RAM CG RAM provides space to create eight custom character bitmaps Each custom character location consists of a 5 dot by 8 line bitmap as shown in Figure 5 5 The Set CG RAM Address command initializes the address counter before reading or writing to CG RA
49. 1 the VGA connector is the left most connector along the top of the board DB15 VGA Connector front view DB15 Connector Red 2700 Av a H14 VGA RED Green d Av a o H15 VGA GREEN Blue 2700 NM f o G15 VGA BLUE 82 50 E NVV t F15 VGA HSYNC i 82 50 Vertical Sync NAA 4 o F14 VEAIS xx lt FPGA pin number UG230 c6 01 021706 Figure 6 1 VGA Connections from Spartan 3E Starter Kit Board The Spartan 3E FPGA directly drives the five VGA signals via resistors Each color line has a series resistor with one bit each for VGA_RED VGA_GREEN and VGA_BLUE The series resistor in combination with the 75Q termination built into the VGA cable ensures that the color signals remain in the VGA specified OV to 0 7V range The VGA_HSYNC and VGA VSYNC signals using LVTTL or LVCMOSS33 I O standard drive levels Drive the VGA RED VGA GREEN and VGA BLUE signals High or Low to generate the eight colors shown in Table 6 1 Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 55 UG230 v1 1 June 20 2008 Chapter 6 VGA Display Port XILINX Table 6 1 3 Bit Display Color Codes VGA_RED VGA_GREEN VGA_BLUE Resulting Color 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 White VGA signal timing is specified published copyrighted and sold by the Video Electronics Standards Association VESA The following VGA system and timing information i
50. 100 Ethernet Physical Layer Interface XILINX The hardware evaluation versions of the Ethernet MAC cores operate for approximately eight hours in silicon before timing out To order the full version of the core visit the Xilinx website at http www xilinx com products ipcenter OPB 10 100 Lite htm UCF Location Constraints Figure 14 4 provides the UCF constraints for the 10 100 Ethernet PHY interface including the I O pin assignment and the I O standard used NET E COL LOC U6 IOSTANDARD LVCMOS33 NET E CRS LOC U13 IOSTANDARD LVCMOS33 NET E MDC LOC P9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E MDIO LOC U5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E RX CLK LOC V3 IOSTANDARD LVCMOS33 NET E RX DV LOC V2 IOSTANDARD LVCMOS33 NET E RXD 0 LOC V8 IOSTANDARD LVCMOS33 NET E RXD lt 1 gt LOC T11 IOSTANDARD LVCMOS33 NET E RXD lt 2 gt LOC Ull IOSTANDARD LVCMOS33 NET E RXD lt 3 gt LOC V14 IOSTANDARD LVCMOS33 NET E RXD 4 LOC U14 IOSTANDARD LVCMOS33 NET E TX CLK LOC T7 IOSTANDARD LVCMOS33 NET E TX EN LOC P15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD lt 0 gt LOC R11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD lt 1 gt LOC T15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD lt 2 gt LOC R5 IOSTA
51. 38X3 LSUN VILIX NDITO 1NIN SUI 103 ATI XL ATI XH NA xu NI XL HOXE UI axa ecaxa Taxa eaxa OXL 437 EUX L ZOXL TOXL OXL NXU dx NX1 dXL 30H DION amp AHd X37dNA4 ZAHA ALINILIY TAHA NOYNIT AHd TOdS xu ZOd9 vauaHd TOd9 TIW 0d9 XL nisal 01S31 Z 00H T3004 93004 S8T19 E8NV Ni 838 93un Tid 3809 aan BKH Z 9G E 96 9vu MW tb t aso ON Schematic Sheet 4 Figure A 3 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Appendix A Schematics XILINX Voltage Regulators 140 IC7 is a Texas Instruments TPS75003 triple output regulator The regulator provides 1 2V to the FPGA s VCCINT supply input 2 5V to the FPGA s VCCAUX supply input and 3 3V to other components on the board and to the FPGA s VCCO supply inputs on I O Banks 0 1 and 2 Jumpers JP6 and JP7 provide a means to measure current across the FPGA s VCCAUX and VCCINT supplies respectively IC8 isa Linear Technology LT3412 regulator providing 2 5V to the on board DDRSDRAM Resistors R65 and R67 create a voltage divider to create the termination voltage required for the DDR SDRAM interface IC9 is a 1 8V supply to the Embedded USB download debug circuit and to the CPLD s VCCINT supply input www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 200
52. 5 Connects to FPGA Signals SF_D lt 11 8 gt user I O connect to character 5 110 FT LCD pins DB 74 SF D9 R16 SF D8 R15 8 SF D7 N9 Upper 7 bits of a data byte or lower 8 bits of a A SE De M9 16 bit halfword Connects to FPGA pins D 7 1 to support the BPI configuration SF_D5 R9 SF D4 U9 SF_D3 V9 SF D2 R10 SF Di P10 SPI_MISO N10 Bit 0 of data byte and 16 bit halfword Connects to FPGA pin DO DIN to support the BPI configuration Shared with other SPI peripherals and Platform Flash PROM SF CEO D16 StrataFlash Chip Enable Connects to FPGA pin LDCO to support the BPI configuration SF WE D17 StrataFlash Write Enable Connects to FPGA pin HDC to support the BPI configuration SF OE C18 StrataFlash Chip Enable Connects to FPGA e pin LDC1 to support the BPI configuration E SF BYTE C17 StrataFlash Byte Enable Connects to FPGA pin LDC2 to support the BPI configuration 0 x8 data 1 x16 data SF STS B18 StrataFlash Status signal Connects to FPGA user I O pin www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Shared Connections Shared Connections Besides the connections to the FPGA the StrataFlash memory shares some connections to other components Character LCD The character LCD uses a four bit data interface The display data connections are also shared with the SF D 11 8 signals on the StrataFlash PROM As shown in Table 11 2 the FPGA controls access to t
53. 6 d Character LCD LCD NET LCD E LOC M18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET LCD RS LOC L18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET LCD RW LOC L17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW LCD data connections are shared with StrataFlash connections SF D lt 11 8 gt HNET SF D lt 8 gt LOC R15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW HNET SF D lt 9 gt LOC R16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW HNET SF D lt 10 gt LOC P17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW HNET SF D 11 LOC M15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW H Discrete LEDs LED These are shared connections with the FX2 connector NET LED lt 0 gt LOC F12 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 1 gt LOC E12 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 2 gt LOC E11 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 3 gt LOC F11 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 4 gt LOC C11 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 5 gt LOC D11 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 I OO CO OO OO CO CO CO CO SLOW SLOW SLOW SLOW Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 www xilinx com 163 Appendix B Example User Constraints File UCF Z XILINX
54. 6 gt LOC D14 IOSTANDARD LVCMOS33 SLEW NET FX2 10 lt 27 gt LOC A16 IOSTANDARD LVCMOS33 SLEW NET FX2 10 lt 28 gt LOC B16 IOSTANDARD LVCMOS33 SLEW NET FX2 10 lt 29 gt LOC E13 IOSTANDARD LVCMOS33 SLEW NET FX2 IO 30 LOC Ca IOSTANDARD LVCMOS33 SLEW NET FX2 IO lt 31 gt LOC B11 IOSTANDARD LVCMOS33 SLEW NET FX2 10 lt 32 gt LOC A11 IOSTANDARD LVCMOS33 SLEW NET FX2 10 lt 33 gt LOC A8 IOSTANDARD LVCMOS33 SLEW NET FX2 IO 34 LOC G9 IOSTANDARD LVCMOS33 SLEW NET FX2 IP lt 35 gt LOC D12 IOSTANDARD LVCMOS33 SLEW NET FX2 IP lt 36 gt LOC C12 IOSTANDARD LVCMOS33 SLEW NET FX2 IP lt 37 gt LOC A15 IOSTANDARD LVCMOS33 SLEW NET FX2 IP lt 38 gt LOC B15 IOSTANDARD LVCMOS33 SLEW NET FX2 IO 39 LOC C3 IOSTANDARD LVCMOS33 SLEW NET FX2 IP lt 40 gt LOC C15 IOSTANDARD LVCMOS33 SLEW lI I XILINX FAST DRIVE FAST DRIVE accessory header II II FAST DRIVE FAST DRIVE FAST DRIVE FAST DRIVE accessory header lI accessory header FAST FAST DRIVE DRIVE FAST DRIVE FAST DRIVE ctions FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE
55. 8 Voltage Regulators SC XILINX ACHEN 90 20 20 e1ieQ 280 006 HUE 40uing S4oie nbes pue fitddng 49m0g 133HS 99 49901603 9e8z agaz mbri do Sul 1usTIbta p4eog 4914113 Jg ue J4eds UG230 Aa 04 021806 ANAT 699 uorionpoad 404 peo oN 220 na y UOTIINPOJd 404 er z23 peo ONST ri GS3 81917 SU WAY Hng 9 UN 10 2238c82 d HI D S UNS Ser uorionpoad 40 JnaT near 895 peo7 oN 951 s4o e nbay 400 401e Nbey inding e gdra Sjueuna4isu sexa ber uot 2npoid 40 peon on dr o o Go us ISI n y INI S su s yu 44no BOGZSdL uorionpo4d 404 peo ON Ezr uotonpoad 40 ect peo7 on 9 oz I Ter uorionpoad 40 peo7 on 9 I YING 4enog up iddns ng Schematic Sheet 5 Figure A 4 141 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Appendix A Schematics A XILINX FPGA Configurations Settings Platform Flash PROM SPI Serial Flash JTAG Connections 142 IC10MISC represents the various FPGA configuration connections IC11 is a 4 Mbit XCFO4S Platform Flash PROM Landing pads for a second XCF045 PROM is shown as IC13 although the second PROM is not mounted on the XC3S500E version of the board Resistor R100 jumpers over the JTAG chain bypassing the second XCFO4S PROM Jumper header J30 selects the FPGA s configuration mode See Table 4 1 page 27 for additional information Header J28 is an alternate
56. 96Z 48T Eh MI G GO G z30 6 6 Seals 139 039 H3M 30 q 1 4 4 4 1 a 4 a a a a a Ren YIQUZE UO UN vo e 0 LO o e 09 19 0 AUOT EK AUOT 4UZp AUOT EE 80c2 20c2 9022 S0ZI rac3 Ea 7 KL 1eeus uo G2 919149109 amp 1L SUI BZII 40 34omieu LOTIPUTWAS 310N Z 4euung oo3 XUTTIX G2Z 919 TNS 109 v LW Auzy ET 4UZp 4UZp 4UZp T ZI 1829 ZI 6619 8619 buridnossq 438 332 N32 d 3 198 gua A Ty dY 19 a o od od of od o a a1 ELA quz 4926 26139613 9619 UG230 Aa 11 021806 Schematic Sheet 12 Figure A 11 155 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Appendix A Schematics A XILINX Buttons Switches Rotary Encoder and Character LCD SWO0 SW1 SW2 and SW3 are slide switches Push button switches W E S and N are located around the ROT1 push button switch rotary encoder LDO through LD7 are discrete LEDs See Chapter 2 Switches Buttons and Knob for additional information DISP1 is a 2x16 character LCD screen See Chapter 5 Character LCD Screen for additional information 156 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Buttons Switches Rotary Encoder and Character LCD XILINX UMS 40uing SOI Ie4eueg pue 097 133HS 99 492u15u3 9eaz agaz 1ubi4fidog dul Webm p4eog 4911818 Je uei4edg 4apo2u3 Reiog
57. A Starter Kit board uses three bits per pixel producing one of the eight possible colors shown in Table 6 1 The controller indexes into the video data buffer as the beams move across the display The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 57 UG230 v1 1 June 20 2008 Chapter 6 VGA Display Port A XILINX As shown in Figure 6 2 the VGA controller generates the horizontal sync HS and vertical sync VS timings signals and coordinates the delivery of video data on each pixel clock The pixel clock defines the time available to display one pixel of information The VS signal defines the refresh frequency of the display or the frequency at which all information on the display is redrawn The minimum refresh frequency is a function of the display s phosphor and electron beam intensity with practical refresh frequencies in the 60 Hz to 120 Hz range The number of horizontal lines displayed at a given refresh frequency defines the horizontal retrace frequency VGA Signal Timing 58 The signal timings in Table 6 2 are derived for a 640 pixel by 480 row display using a 25 MHz pixel clock and 60 Hz 1 refresh Figure 6 3 shows the relation between each of the timing symbols The timing for the sync pulse width Tpw and front and back porch intervals Tgp and Tgp are based on observatio
58. A lt 10 gt LOC RRC IOSTANDARD SSTL2 I NET SD A lt 11 gt LOC N5 IOSTANDARD SSTL2 I NET SD A lt 12 gt LOC pa IOSTANDARD SSTL2 I NET SD BA lt 0 gt LOC K5 IOSTANDARD SSTL2 I NET SD BA lt 1 gt LOC ke IOSTANDARD SSTL2 I NET SD CAS LOC TG T IOSTANDARD SSTL2 I NET SD CK N LOC ga IOSTANDARD SSTL2 I NET SD CK P LOC Jas IOSTANDARD SSTL2 I NET SD CKE LOC K3 IOSTANDARD SSTL2 I NET SD CS LOC KA IOSTANDARD SSTL2 I NET SD DQ lt 0 gt LOC WEG AN IOSTANDARD SSTL2 I NET SD DQ lt 1 gt LOC ELN IOSTANDARD SSTL2 I NET SD DQ lt 2 gt LOC Hab IOSTANDARD SSTL2 I NET SD DQ lt 3 gt LOC L4 IOSTANDARD SSTL2 I NET SD DQ lt 4 gt LOC M3 IOSTANDARD SSTL2 I NET SD DQ lt 5 gt LOC M4 IOSTANDARD SSTL2 I NET SD DQ lt 6 gt LOC M5 IOSTANDARD SSTL2 I NET SD DQ lt 7 gt LOC M6 IOSTANDARD SSTL2 I NET SD DQ lt 8 gt LOC E2 IOSTANDARD SSTL2 I NET SD DQ lt 9 gt LOC El IOSTANDARD SSTL2 I NET SD DQ lt 10 gt LOC gy IOSTANDARD SSTL2 I NET SD DQ lt 11 gt LOC RS IOSTANDARD SSTL2 I NET SD DQ lt 12 gt LOC G6 IOSTANDARD SSTL2 I NET SD DQ lt 13 gt LOC kE m IOSTANDARD SSTL2 I NET SD DQ lt 14 gt LOC H6 IOSTANDARD SSTL2 I NET SD DQ lt 15 gt LOC H5 IOSTANDARD SSTL2 I 164 www Xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Z XILINX NET SD LDM
59. AM The Spartan 3E FPGA Starter Kit boards includes a 512 Mbit 32M x 16 Micron Technology DDR SDRAM MT46V32M16 with a 16 bit data interface as shown in Figure 13 1 All DDR SDRAM interface pins connect to the FPGA s I O Bank 3 on the FPGA I O Bank 3 and the DDR SDRAM are both powered by 2 5V generated by an LTC3412 regulator from the board s 5V supply input The 1 25V reference voltage common to the FPGA and DDR SDRAM is generated using a resistor voltage divider from the 2 5V rail 5 0V EM 2 5V LTC3412 1 25V Spartan 3E FPGA Micron 512 Mb DDR SDRAM SD A lt 12 0 gt See Table A 12 0 D DQ lt 15 Y VREF See Table saa DQ 15 0 VREF VCCO 3 See Table SP BA lt 1 0 gt pan BA 1 0 VDD SELARAS ANN VDDQ SD_CAS NNN SD WE AAA LE SD UDM NN UGM MT46V32M16 SL LON NW Lam 32Mx16 SD_UDOS Au uDas SD_LDSS AMN LDas SD CS NNN CS SD CKE BAN SD CK N ANN B9 GCLK9 SD OKP Aw SD CK FB NW UG230_c13_01_022406 Figure 13 1 FPGA Interface to Micron 512 Mbit DDR SDRAM Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 105 UG230 v1 1 June 20 2008 Chapter 13 DDR SDRAM All DDR SDRAM interface signals are terminated The differential clock pin SD CK P is fed back into FPGA pin B9 in I O Bank 0 to have best access to one of the FPGA s Digital Clock Managers DCMs This path is required when using the MicroBlaze
60. After iMPACT starts double click PROM File Formatter as shown in Figure 4 14 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Programming the FPGA CPLD or Platform Flash PROM via USB iMPACT C data my desi k File Edit view Operations Zr SlaveSerial EEG elect AF 8 Desktop Configu i E SystemACE ac PRO M File Form E IMPACT Modes UG230_c4_15_022706 Figure 4 14 Double Click PROM File Formatter Choose Xilinx PROMas the target PROM type as shown in Figure 4 15 Select from any of the PROM File Formats the Intel Hex format MCS is popular Enter the Location of the directory and the PROM File Name Click Next gt when finished iMPACT Prepare PROM Files Sel x want to target a Xilins PROM C Generic Parallel PROM 3rd Party SPI PROM PROM File Format MCS C TEK UEP C format C EXO C BIN SES C HEX T SwapBits Checksum Fill Value 2 Hex Digits FF PROM File Name MyPlatiormPlash Location C data my_designs s3e_starter_kit Browse UG230_c4_16_022706 Figure 4 15 Choose the PROM Target Type the Data Format and File Location Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 35 UG230 v1 1 June 20 2008 Chapter 4 FPGA Configuration Options XILINX The Spartan 3E Starter Kit board has an XCF04S Platform Flash PROM Select xc 04s from the drop list as shown in Fig
61. B Ta SPL MOSI NEN T16 VS2 A17 DIN DO N10 SPLMISO S U15 VS1 A18 CCLK U16 SPI SCK FS v15 VS0 A19 CSO B U3 SPLSS_B lz T Jumper J11 m d o m 0 9o a zo o OO tc Programming Header J12 GND B 33v SEL SDI SDO SCK UG230 c15 17 030306 Figure 12 17 Additional SPI Flash Interface Design Details Shared SPI Bus with Peripherals After configuration the SPI Flash configuration pins are available to the application On the Spartan 3E Starter Kit board the SPI bus is shared by other SPI capable peripheral devices as shown in Figure 12 17 To access the SPI Flash memory after configuration the FPGA application must disable the other devices on the shared PCI bus Table 12 3 shows the signal names and disable values for the other devices Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 101 UG230 v1 1 June 20 2008 Chapter 12 SPI Serial Flash XILINX 102 Table 12 3 Disable Other Devices on SPI Bus Signal Disabled Device Disable Value DAC CS Digital to Analog Converter DAC 1 AMP CS Programmable Pre Amplifier 1 AD CONV Analog to Digital Converter ADC 0 SF CEO StrataFlash Parallel Flash PROM 1 FPGA INIT B Platform Flash PROM 1 Other SPI Flash Control Signals The M25P16 SPI Flash has two additional control inputs The active Low write protect input W and the acti
62. C64A CoolRunner Il CPLD Controls Master Serial and BPI Configuration Modes 128 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Z XILINX UCF Location Constraints UCF Location Constraints There are two sets of constraints listed below one for the Spartan 3E FPGA and one for the XC2C64A CoolRunner II CPLD FPGA Connections to CPLD CPLD Figure 16 2 provides the UCF constraints for the FPGA connections to the CPLD including the I O pin assignment and the I O standard used NET XC CMD lt 1 gt LOC N18 NET XC CMD 0 LOC P18 NET XC D lt 2 gt LOC F17 NET XC D lt 1 gt LOC F18 NET XC D lt 0 gt LOC G16 NET FPGA M2 LOC T10 NET FPGA M1 LOC V11 NET FPGA MO LOC M10 NET XC CPLD EN LOC B10 NET XC TRIG LOC R17 NET XC GCKO LOC H16 NET GCLK10 LOC C9 NET SPI SCK LOC U16 SF_A lt 24 gt is the same as FX2 NET SF A lt 24 gt LOC A11 NET SF A lt 23 gt LOC N11 NET SF A lt 22 gt LOC V12 NET SF A lt 21 gt LOC V13 NET SF A lt 20 gt LOC T12 IOSTANDARD IOSTANDARD IOSTANDARD OSTANDARD OSTANDARD OSTANDARD OSTANDARD OSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD 10 lt 32 gt IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 L
63. DS2432 1 Wire SHA 1 EEPROM The Spartan 3E FPGA Starter Kit board includes a Maxim DS2432 serial EEPROM with an integrated SHA 1 engine As shown in Figure 17 1 the DS2432 EEPROM uses the Maxim 1 Wire interface which as the name implies cleverly uses a single wire for power and serial communication The DS2432 EEPROM offers one of many possible means to copy protect the FPGA configuration bitstream making cloning difficult Xilinx application note XAPP780 listed under Related Resources provides one possible implementation method 3 3V Maxim DS2432 Spartan 3E FPGA SHA 1 EEPROM UG230_c17_01_030906 Figure 17 1 SHA 1 EEPROM UCF Location Constraints Figure 17 2 provides the UCF constraints for the FPGA connections to the DS2432 SHA 1 EEPROM including the I O pin assignment and the I O standard used NET DS WIRE LOC U4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 Figure 17 2 UCF Location Constraints for DS2432 SHA 1 EEPROM Related Resources e Maxim DS2432 1 Wire EEPROM with SHA 1 Engine http www maxim ic com quick view2 cfm qv pk 2914 e XAPP780 FPGA IFF Copy Protection Using Dallas Semiconductor Maxim DS2432 Secure EEPROMs http www xilinx com support documentation application notes xapp780 pdf Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 131 UG230 v1 1 June 20 2008 Chapter 17 DS2432 1 Wire SHA 1 EEPROM XILINX 132 www xilinx com Spartan 3E FPGA Starter K
64. D_LDQS SD_RAS SD_UDM SD_UDQS SD_WE Path to allow NET SD CK FB Loc K5 LOC Ko LOC E2 LOC J4 LOC J5 LOC K3 LOC K4 LOC J2 LOC L6 LOC veg LOC gl LOC G3 LOC DIM connection LOC B9 IOST TOST TOST TOST TOST TOST IOST IOST IOST IOST IOST TOST TOST TOST NDARD NDARD NDARD NDARD NDARD NDARD NDARD NDARD NDARD NDARD NDARD NDARD NDARD NDARD SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I to top DCM connection LVCMOS33 H H H H H Figure 13 4 UCF Location Constraints for DDR SDRAM Control Pins Reserve FPGA VREF Pins Five pins in I O Bank 3 are dedicated as voltage reference inputs VREF These pins cannot be used for general purpose I O in a design Prohibit the software from using these pins with the constraints provided in Figure 13 5 Prohibit VREF pins CONFIG PROHIBIT CONFIG PROHIBIT CONFIG PROHIBIT CONFIG PROHIBIT CONFIG PROHIBIT Related Resources D2 G4 J6 L5 R4 Figure 13 5 UCF Location Constraints for StrataFlash Control Pins e Xilinx Embedded Design Kit EDK http www xilinx com ise embedded design prod platform studio htm e MT46V32M16 32M x 16 DDR SDRAM Data Sheet http download micron com pdf datasheets dram ddr 512MBDDRx4x8x16 pdf s MicroBlaze OPB Double Data Rate DDR SD
65. Data Input Output MicroBlaze Ethernet IP Cores The Ethernet PHY is primarily intended for use with MicroBlaze applications As such an Ethernet MAC is part of the EDK Platform Studio s Base System Builder Both the full Ethernet MAC and the Lite version are available for evaluation as shown in Figure 14 3 The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for applications that do not require support for interrupts back to back data transfers and statistics counters Base System Builder Configure Additional IO Interfaces The following external memory and 10 devices were found on your board Xilinx Spartan 3E Starter Board Revision C Please select the 10 devices which you would like to use 10 devices M DDR_SDRAM_16Mx16 Data Sheet Peripheral OPB DDR v Note v Ethernet MAC Data Sheet Peripheral DPB ETHERNET y Gi Note OPB ETHERNET DMS Preg OPB ETHERNETLITE GG No DMA UG230 c14 03 022706 Figure 14 3 Ethernet MAC IP Cores for the Spartan 3E Starter Kit Board The Ethernet MAC core requires design constraints to meet the required performance Refer to the OPB Ethernet MAC data sheet v1 02 for details The OPB bus clock frequency must be 65 MHz or higher for 100 Mbps Ethernet operations and 6 5 MHz or faster for 10 Mbps Ethernet operations Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 113 UG230 v1 1 June 20 2008 Chapter 14 10
66. ET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET SD DQ lt 15 gt SD DQ lt 14 gt SD DQ lt 13 gt SD DQ lt 12 gt SD DQ lt 11 gt SD DQ lt 10 gt SD DQ lt 9 gt SD DQ lt 8 gt SD DQ lt 7 gt SD DQ lt 6 gt SD DQ lt 5 gt SD DQ lt 4 gt SD DQ lt 3 gt SD DQ lt 2 gt SD DQ lt 1 gt SD DQ lt 0 gt Figure 13 3 LOC LOC LOC LOG LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC H5 H6 G5 G6 n F2 F1 El E2 M6 M5 M4 M3 LA L3 Ll L2 IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I SSTL2 I H UCF Location Constraints for DDR SDRAM Data l Os 108 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Z XILINX Control Related Resources Figure 13 4 provides the User Constraint File UCF constraints for the DDR SDRAM control pins including the I O pin assignment and the I O standard used NET NET NET NET NET NET NET NET NET NET NET NET NET SD BA 0 SD BA lt 1 gt SD CAS SD CK N SD CK P SD CKE SD CS SD_LDM S
67. EU NETT OI 9 TOHY bY db TT OI SX T9HH GU NETT OI NGTT OI TAQHI b T0Ht 9U dETT OI deTT OI TACA L EXTIDHA Z9 NZ TT OI N8TTOI d8T1 OI NETT OI deTT OI QU N9TT OI d9T1 OI 19 NSTT OI z dSTT OI 438N N TT OI d TT OI 1IU NG 1701 Z19 d6T OI N81701 d81701 MOT d T 01 N9T 01 d91701 438N NST OI da TOI A380 NET OI dET OI TU NZ1 OI IW d2 T 01 GIU NT1 OI 91U dT1 OI EDI TOI e ZOI e NZZ1 OI x X 10HH 8U dZTT OI TX T9HU 86U NTTT OI 9A719H4 B19 d111 OI ldl Z1dI ABYN TIdI tdI ECH 8dI 438N ZAI 9dI SdI Kd DCH TdI T ueg 40 JIN El ino ANY Z NM NODTOR SO IO v CO m NONON SO IO G N S 3 zeosos 01 ZZG6IX IX c asn N 1 40128uu05 Uno 1195 1S cT UseIjeie41S Je T Wed OS 0S 2 9IdGZW WON 1 40128uu03 ZX4 ISOMH ZX4 p 19eu429ui3 3 ID 48148 u02 Y O INO CIT 4er r Idug uteg duu ID 48148 uOj Q U QU 9191 193508 dez T OI NKZT OI dez T OI ABYN NEZT OI d Z T OI N ZT OI d dT OI 438N NSTT OI d6TT OI 3380 7N811 OI d8TT OI NATT OI d2TT OI NSTT OI dSTT OI N6T OI d67 OI N8T OI d8T OI NYT OI d9T OI ABYN NST OI dST OI NET OI db TOI 438N NET OI de TOI NTT OI dTT OI 801 201 SOI 0I ABYN EOT ZDI TX 199 NETT OI QTX199 dE TT OI amp X 199 NET T dI 8X 199 d TT dI ZW199 NZTT OI 9 199 dZTT1 OI S 199 NTTT OI PX 199 dTTT OI x NIZTOL x diZT OI x cdi NZZT dI dzZl di NYTT dI d9TT
68. GA Starter Kit Board User Guide UG230 v1 1 June 20 2008 2 XILINX Chapter 12 SPI Serial Flash The Spartan 3E FPGA Starter Kit board includes a STMicroelectronics M25P16 16 Mbit SPI serial Flash useful in a variety of applications The SPI Flash provides an alternative means to configure the FPGA a new feature of Spartan 3E FPGAs as shown in Figure 12 1 The SPI Flash is also available to the FPGA after configuration for a variety of purposes such as e Simple non volatile data storage e Storage for identifier codes serial numbers IP addresses etc e Storage of MicroBlaze processor code that can be shadowed into DDR SDRAM STMicro M25P16 Spartan 3E FPGA SPI Serial Flash MOSICSI B T4 DIN DO N10 SPI MOSI SPI MISO CCLK ue SPLSCK CSO B U3 SPI SS B UG230 c15 01 030206 Figure 12 1 Spartan 3E FPGAs Have an Optional SPI Flash Configuration Interface Table 12 1 SPI Flash Interface Signals Signal FPGA Pin Direction Description SPI MOSI T4 FPGA SPI Serial data Master Output Slave Input SPI MISO N10 FPGA SPI Serial data Master Input Slave Output SPI SCK U16 FPGA gt SPI Clock SPI SS B U3 FPGA SPI Asynchronous active Low slave select input UCF Location Constraints Figure 12 2 provides the UCF constraints for the SPI serial Flash PROM including the I O pin assignment and the I O standard used Spartan 3E FPGA Starter Kit Board User Guide www x
69. Generation Succeeded UG230 c15 13 030206 Figure 12 14 PROM File Formatter Succeeded 98 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Configuring from SPI Flash Downloading the Design to SPI Flash There are multiple methods to program the SPI Flash as listed below e Use the Xilinx iMPACT programming support e Use the PicoBlaze based SPI Flash programmer reference designs Use a terminal emulator such as Hyperlink to download SPI Flash programming data via the PC s serial port to the FPGA The embedded PicoBlaze processor then programs the attached SPI serial Flash See Related Resources page 104 e Via the FPGA s JTAG chain use a JTAG tool to program the SPI Flash connected to the FPGA See the link to the Universal Scan SPI Flash programming tutorial in Related Resources page 104 Downloading the SPI Flash The following steps describe how to download the SPI Flash PROM Attach a JTAG Parallel Programming Cable SPI programming will typicall use a JTAG parallel programming cable such as e Xilinx Parallel Cable IV with flying leads Digilent JTAG3 programming cable These cables are not provided with the Spartan 3E Starter Kit board but can be purchased separately either from the Xilinx Online Store or from Digilent Inc see Related Resources page 104 First turn off the power on the Spartan 3E Starter Kit board If the USB cable is
70. High for 12 clock cycles e Wait 40 us or longer which is 2 000 clock cycles at 50 MHz e Write SF D lt 11 8 gt 0x2 pulse LCD E High for 12 clock cycles e Wait 40 us or longer which is 2 000 clock cycles at 50 MHz Display Configuration After the power on initialization is completed the four bit interface is now established The next part of the sequence configures the display e Issue a Function Set command 0x28 to configure the display for operation on the Spartan 3E Starter Kit board e Issue an Entry Mode Set command 0x06 to set the display to automatically increment the address pointer e Issue a Display On Off command 0x0C to turn the display on and disables the cursor and blinking Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 53 UG230 v1 1 June 20 2008 Chapter 5 Character LCD Screen A XILINX e Finally issue a Clear Display command Allow at least 1 64 ms 82 000 clock cycles after issuing this command Writing Data to the Display To write data to the display specify the start address followed by one or more data values Before writing any data issue a Set DD RAM Address command to specify the initial 7 bit address in the DD RAM See Figure 5 3 for DD RAM locations Write data to the display using a Write Data to CG RAM or DD RAM command The 8 bit data value represents the look up address into the CG ROM or CG RAM shown in Figure 5 4 The stored bitmap in the CG ROM or CG RAM dri
71. June 20 2008 XILINX Related Resources IV Verify General CPLD And PROM Properties IZ Erase Before Programming Read Protect Prom CoolRunnerl Usercode 8 Hex Digits CPLD Specific Properties I write Protect Functional Test P On The Fly Program IT XPLA UES Enter up to 13 characters PROM Specific Properties UG230 c4 27 022806 Figure 4 26 PROM Programming Options The iMPACT software indicates if programming was successful or not If programming was successful and the Load FPGA option was left unchecked push the PROG B push button switch shown in Figure 4 2 page 26 to force the FPGA to reconfigure from the newly programmed Platform Flash PROM If the FPGA successfully configures the DONE LED also shown in Figure 4 2 lights up Related Resources e XAPP951 Configuring Xilinx FPGAs with SPI Serial Flash http www xilinx com support documentation application notes xapp951 pdf Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 41 UG230 v1 1 June 20 2008 Chapter 4 FPGA Configuration Options 42 www xilinx com Z XILINX Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Chapter 5 Character LCD Screen Overview The Spartan 3E FPGA Starter Kit board prominently features a 2 line by 16 character liquid crystal display LCD The FPGA controls the LCD via the 4 bit data interface shown in Figure 5 1 Although the LCD su
72. K LOC T7 IOSTANDARD LVCMOS33 NET E TX EN LOC P15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD lt 0 gt LOC R11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD lt 1 gt LOC T15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD lt 2 gt LOC R5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD lt 3 gt LOC T5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD lt 4 gt LOC R6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 FPGA Configuration Mode INIT B Pins FPGA NET FPGA MO LOC M10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET FPGA M1 LOC VIL IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET FPGA M2 LOC TLO IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET FPGA INIT B LOC T3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4 NET FPGA RDWR B LOC U10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4 NET FPGA HSWAP LOC B3 IOSTANDARD LVCMOS33 FX2 Connector FX2 NET FX2 CLKIN LOC E10 IOSTANDARD LVCMOS33 NET FX2 CLKIO LOC D9 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 CLKOUT LOC D10 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 These four connections are shared with the J1 6 pin accessory header NET FX2 IO 1 LOC B4 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 TO lt 2 gt LOC A4 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 TO lt 3
73. LKS8 DCM X0Y1 CLK SMA A10 GCLK7 DCM X1Y1 Voltage Control The voltage for all I O pins in FPGA I O Bank 0 is controlled by jumper JP9 Consequently these clock resources are also controlled by jumper JP9 By default JP9 is set for 3 3V The on board oscillator is a 3 3V device and might not perform as expected when jumper JP9 is set for 2 5V 50 MHz On Board Oscillator The board includes a 50 MHz oscillator with a 40 to 60 output duty cycle The oscillator is accurate to 2500 Hz or 50 ppm Auxiliary Clock Oscillator Socket The provided 8 pin socket accepts clock oscillators that fit the 8 pin DIP footprint Use this socket if the FPGA application requires a frequency other than 50 MHz Alternatively use the FPGA s Digital Clock Manager DCM to generate or synthesize other frequencies from the on board 50 MHz oscillator SMA Clock Input or Output Connector To provide a clock from an external source connect the input clock signal to the SMA connector The FPGA can also generate a single ended clock output or other high speed signal on the SMA clock connector for an external device UCF Constraints 22 Location The clock input sources require two different types of constraints The location constraints define the I O pin assignments and I O standards The period constraints define the clock period and consequently the clock frequency and the duty cycle of the incoming clock signal Figure 3 2 provid
74. LOC SF CEO SE OE SF STS SE WE LOC LOC LOC LOC ow H H H C17 D16 C18 B18 D17 IOSTANDARD LVCMOS33 DRIVE IOSTANDARD LVCMOS33 DRIVE IOSTANDARD LVCMOS33 DRIVE IOSTANDARD LVCMOS33 DRIVE IOSTANDARD LVCMOS33 DRIVE SLEW SLEW SLEW SLEW SLEW A AAAA Hunn D LOW LOW LOW LOW LOW Figure 11 4 UCF Location Constraints for StrataFlash Control Pins Setting the FPGA Mode Select Pins Set the FPGA configuration mode pins for either BPI Up or BPI down mode as shown in Table 11 4 See Table 11 4 Selecting BPI Up or BPI Down Configuration Modes Header J30 in Figure 4 2 Configuration Mode Pins FPGA Configuration Image in Mode M2 M1 MO StrataFlash Jumper Settings BPI Up 0 1 0 FPGA starts at address 0 and increments through address space The CPLD controls address lines A 24 20 during BPI configuration BPI Down 0 1 1 FPGA starts at address OxFF FFFF and decrements through address space The CPLD controls address lines A 24 20 during BPI configuration Related Resources e Intel J3 StrataFlash Data Sheet http www numonyx com en US MemoryProducts NOR Pages NumonyxEmbeddedFlashMomory 3vD aspx Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 www xilinx com 89 Chapter 11 Intel StrataFlash Parallel NOR Flash PROM 90 www xilinx com Z XILINX Spartan 3E FP
75. LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 13 LOC P6 OSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 12 LOC M16 OSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 11 LOC M15 OSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D lt 10 gt LOC P17 OSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 9 LOC R16 OSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 8 LOC R15 LOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 7 LOC N9 OSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D lt 6 gt LOC M9 OSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D lt 5 gt LOC R9 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 4 LOC U9 OSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 3 LOC V9 LOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 2 LOC R10 OSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF D 1 LOC P10 OSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SPI MISO LOC N10 IOSTANDARD LVCMOS33 DRIVE 6 SLEW SLOW Figure 11 3 UCF Location Constraints for StrataFlash Data I Os 88 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Z XILINX Control Setting the FPGA Mode Select Pins Figure 11 4 provides the UCF constraints for the StrataFlash control pins including the I O pin assignment and the I O standard used NET NET NET NET NET SF BYTE
76. Layout STMicroelectronics was rather clever when they defined the package layout for the M25Pxx SPI serial Flash family The Spartan 3E Starter Kit board supports all three of the package types used for the 16 Mbit device as shown in Figure 12 18 By default the board ships with the 8 lead 8x6 mm MLP package The multi package layout also supports the 8 pin SOIC package and the 16 pin SOIC package Pin 1 for the 8 pin SOIC and MLP packages is located in the top left corner However pin 1 for the 16 pin SOIC package is located in the top right corner because the package is rotated 90 The 16 pin SOIC package also have four pins on each side that do not connect on the board These pins must www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 3 XILINX Additional Design Details be left floating Why support multiple packages In a word flexibility The multi package layout provides Density migration between smaller and larger density SPI Flash PROMs Not all SPI Flash densities are available in all packages The SPI Flash migration strategy follows nicely with the pinout migration provided by Xilinx FPGAs Consistent configuration PROM layout when migrating between FPGA densities The Spartan 3E FPGA s FG320 package footprint supports the XC3S500E the XC3S1200E and the XC3S1600E FPGA devices without modification The SPI Flash multi package layout allows comparable flexibility in the associat
77. M Write CG RAM data using the Write Data to CG RAM or DD RAM command and read CG RAM using the Read Data from CG RAM or DD RAM command UG230 v1 1 June 20 2008 www xilinx com 47 Chapter 5 Character LCD Screen Z XILINX The CG RAM address counter can either remain constant after read or write operations or auto increments or auto decrements by one location as defined by the I D set by the Entry Mode Set command Figure 5 5 provides an example creating a special checkerboard character The custom character is stored in the fourth CG RAM character location which is displayed when a DD RAM location is 0x03 To write the custom character the CG RAM address is first initialized using the Set CG RAM Address command The upper three address bits point to the custom character location The lower three address bits point to the row address for the character bitmap The Write Data to CG RAM or DD RAM command is used to write each character bitmap row A 1 lights a bit on the display A 0 leaves the bit unlit Only the lower five data bits are used the upper three data bits are don t care positions The eighth row of bitmap data is usually left as all zeros to accommodate the cursor Upper Nibble Lower Nibble Write Data to CG RAM or DD RAM A5 A4 A3 A2 A1 AO D7 D6 D5 D4 D3 D2 D1 DO Character Address Row Address Don t Care Character Bitmap
78. N OO 4apeaH uoisuedx3 39091 309Z1 4012euuo2 ZSd Pueoghay CETEXEW Z9I ZNI zino INIA TLNOY DIER ZNIG una S mia e yates Jedunr sy JU L LUZ K Zo 32919 UMS 340d IdS gar 10140 UG230_Aa_02 021806 Schematic Sheet 2 Figure A 2 137 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Appendix A Schematics A XILINX Ethernet PHY Magnetics and RJ 11 Connector 138 IC6 is an SMSC 10 100 Ethernet PHY with its associated 25 MHz oscillator The PHY requires an Ethernet MAC implemented within the FPGA J19 is the RJ 11 Ethernet connector associated with the 10 100 Ethernet PHY See Chapter 14 10 100 Ethernet Physical Layer Interface for additional information www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 bI b 319908 NUS 4ouing 239 488urbu3 90 20 20 9120 280 006 4914818 FES 31111 923ej48jUu i8u48ui13 133HS 9 z geez 14brsAdog sur 1ustibtg pueog 4914815 Jg ue Jeds UG230 Aa 03 021806 139 AN k dnzv O UBT ESCH EICHER 6 3 aT 2 3 S 3 9 3 ana Doten Ethernet PHY Magnetics and RJ 11 Connector SC XILINX S 1 30Svc LIT 3H BEI BED ZED ED s4oyrsedeg ssed g 6 6r bd N AUOT omo o os as lolo ES MOSES bbI v2 ENE ANZ HNL 4401 4481 AUOT DDD SEE 000 nus 0304 19 TIYLX lo w ON IG GC GL TS
79. NDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD lt 3 gt LOC T5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E TXD lt 4 gt LOC R6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 Figure 14 4 UCF Location Constraints for 10 100 Ethernet PHY Inputs Related Resources 114 Standard Microsystems SMSC LAN83C185 10 100 Ethernet PHY http www smsc com main catalog lan83c185 html Xilinx OPB Ethernet Media Access Controller EMAC v1 02a www xilinx com support documentation ip documentation opb ethernet pdf Xilinx OPB Ethernet Lite Media Access Controller v1 01a The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for applications the do not require support for interrupts back to back data transfers and statistics counters www xilinx com support documentation ip_documentation opb_ethernetlite pdf EDK Documentation http www xilinx com ise embedded edk docs htm www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Chapter 15 Expansion Connectors The Spartan 3E FPGA Starter Kit board provides a variety of expansion connectors for easy interface flexibility to other off board components The board includes the following I O expansion headers see Figure 15 1 e A Hirose 100 pin edge connector with 43 associated FPGA user I O pins including up to 15 differential LVDS I O pairs and two Input only p
80. NET FX2 IP lt 37 gt LOC A15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IP lt 38 gt LOC B15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 TO lt 39 gt LOC C3 IOSTANDARD LVCMOS33 SLEW FAST DRIVE NET FX2 IP lt 40 gt LOC C15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 6 pin header J1 These are shared connections with the FX2 connector NET Jl lt 0 gt LOC B4 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J1 1 LOC A4 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J1 lt 2 gt LOC D5 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET Jl lt 3 gt LOC C5 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 6 pin header J2 These are shared connections with the FX2 connector NET J2 lt 0 gt LOC A6 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J2 lt 1 gt LOC B6 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J2 lt 2 gt LOC E7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J2 lt 3 gt LOC F7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 6 pin header J4 These are shared connections with the FX2 connector NET J4 lt 0 gt LOC D7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J4 lt 1 gt LOC C7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J4 lt 2 gt LOC F8 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J4 lt 3 gt LOC E8 IOSTANDARD LVTTL SLEW SLOW DRIVE
81. O Bank 0 The board provides the option to power I O Bank 0 with either 3 3V or 2 5V Figure 15 1 page 115 highlights the location of jumper JP9 If using differential outputs on the FX2 connector set jumper JP9 to 2 5V If the jumper is not set correctly the outputs switch correctly but the signal levels are out of specification PAD LxxN 0 LxxP_0 IX Signal UG230_c12_06_022406 Figure 15 6 Differential Outputs UCF Location Constraints Figure 15 7 provides the UCF constraints for the FX2 connector including the I O pin assignment and the I O standard used assuming that all connections use single ended I O standards These header connections are shared with the 6 pin accessory headers as shown in Figure 15 11 page 124 Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 121 UG230 v1 1 June 20 2008 Chapter 15 Expansion Connectors 122 FX2 Connector FX2 NET FX2 CLKIN LOC E10 IOSTANDARD LVCMOS33 NET FX2 CLKIO LOC D9 IOSTANDARD LVCMOS33 SLEW NET FX2 CLKOUT LOC D10 IOSTANDARD LVCMOS33 SLEW These four connections are shared with the J1 6 pin NET FX2 IO lt 1 gt LOC B4 IOSTANDARD LVCMOS33 SLEW NET FX2 IO lt 2 gt LOC A4 IOSTANDARD LVCMOS33 SLEW NET FX2 IO lt 3 gt LOC D5 IOSTANDARD LVCMOS33 SLEW NET FX2 IO lt 4 gt LOC C5 IOSTANDARD LVCMOS33 SLEW These four co
82. O25 C14 IO L03N 0 I O Yes 13 R206 FX2 IO26 D14 IO_L03P_0 I O Yes FX2_IO27 A16 IO_L01N_0 I O Yes 14 R207 FX2_IO28 B16 IO_L01P_0 I O Yes FX2_IP35 D12 IP L07N 0 Input 15 R208 FX2 IP36 C12 IP L07P 0 Input FX2_IP37 A15 IP LO2N 0 Input 16 R209 FX2 IP38 B15 IP Lo2P 0 Input IO_L11N_0 FX2_CLKIN E10 GCLK5 I O Yes IO L11P 0 2 FX2 CLKOUT D10 GCLKA I O Yes Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 www xilinx com 119 Chapter 15 Expansion Connectors XILINX Using Differential Inputs LVDS and RSDS differential inputs require input termination Two options are available The first option is to use external termination resistors as shown in Figure 15 3a The board provides landing pads for external 100Q termination resistors The resistors are not loaded on the board as shipped The resistor reference designators are labeled on the silkscreen as listed in Table 15 2 The landing pads are located on both the top and bottom side of the board between the FPGA and the FX2 connector The resistors are not loaded on the board as shipped External termination is always required when using differential input pairs 15 and 16 The second option shown in Figure 15 3b is a Spartan 3E FPGA feature called on chip differential termination which uses the DIFF TERM attribute available on differential I O signals Each differential I O pin includes a circuit that behaves like an internal termination resistor of
83. OC A4 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET Jl lt 2 gt LOC D5 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 HNET Jl lt 3 gt LOC C5 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 6 pin header J2 These four connections are shared with the FX2 connector HNET J2 lt 0 gt LOC A6 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 HNET J2 lt 1 gt LOC Be IOSTANDARD LVTTL SLEW SLOW DRIVE 6 HNET J2 lt 2 gt LOC E7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J2 lt 3 gt LOC F7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 6 pin header J4 These four connections are shared with the FX2 connector HNET J4 lt 0 gt LOC D7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J4 lt 1 gt LOC C7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J4 lt 2 gt LOC Fg IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J4 lt 3 gt LOC Eg IOSTANDARD LVTTL SLEW SLOW DRIVE 6 Figure 15 11 UCF Location Constraints for Accessory Headers 124 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Connectorless Debugging Port Landing Pads J6 Z XILINX Connectorless Debugging Port Landing Pads J6 Landing pads for a connectorless debugging port are provided as header J6 shown in Figure 15 1 page 115 There is no physical connector on the board Instead a connectorless probe such as those available from Agilent provides an interface to
84. OI ZAQUL HATIHT dETT OI diz1 OI ZAGUI ENTOHI NZTT 01 N ZT OI ZXT0H1 dZT1 01 d zT OI TATOHT NTTT OI N6TT OI XTIHT ATTTTOI Z82131 ds1T OI NBTT OI 218 8N d9ZT 01 3129 IQ NST1701 d8TT OI 819 1SN NGZ 1701 ZX199 2 d8T1 01 ARNA NZTT 01 619 ZSN dSZT 01 G11199 0 NE 11701 dZT1 OI ZY NbZT OI 11199 90 d 11701 N9TT OI TZU dvZ1 OI D129 90 NZT1 OI d9T1 or ZZU NZZ1 OI ZTX199 20 dZT1 01 NGTT OI EzW d2ZT 01 d amp T1 OI N TT OI Nez Tor x NIZTOI dart OI d zTor _ x diZ1 01 N amp T OI ARNN NETT 01 x 3300 N9 1701 d amp 1 01 der 01 x d9TOI NST OI N8TT OI x POI d8T 01 d811_ 01 NZT OI N TT OI deT 01 Bosch NEZT dI 438N NST 01 NET OI dEZ1 dI d9T 01 ETdI d61 01 NETT dl Ve ot DCH NAT OI d2Tl dl Basch Tdi aZ TOI ARNN NITT dI NET OI DECH NGT 01 EI dET OI 6dI d amp 1 01I N TdI A3Un NZ1 OI 8d1 NET OI d8T di de T OI dl dy TOI NZ dI NIT OI 9d1 438N 901 dz dI diT OI EEN SOI x pal ARUA EOI x 438N d1 01 x Ed dy TOI x ER S zoI ER ZOI x 10 434 101 td 101 x SI D El Sl D s 9 a H I T G D Si 9 S 9 E lt 1 1 H H T H T bi este Q uaa NG Z 3X4eg 40 JIN NE E Z 3ueg 403 220 147 UG230 Aa 07 021806 Schematic Sheet 8 www xilinx com Figure A 7 Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Appendix A Schematics A XILINX Power Supply Decoupling IC10PWR represents the various voltage supply inputs to the FPGA and shows the p
85. OPB DDR controller The MicroBlaze OPB DDR SDRAM controller IP core documentation is also available from within the EDK 8 1i development software see Related Resources DDR SDRAM Connections Table 13 1 shows the connections between the FPGA and the DDR SDRAM 106 page 109 Table 13 1 FPGA to DDR SDRAM Connections Z XILINX Address inputs DDR SDRAM FPGA Pin Category Signal Name Number SD A12 P2 SD A11 N5 SD A10 T2 SD A9 N4 SD_A8 H2 o SD A7 H1 E SD A6 H3 lt SD A5 H4 SD_A4 F4 SD_A3 P1 SD_A2 R2 SD_A1 R3 SD AO T1 Function www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Z XILINX DDR SDRAM Connections Table 13 1 FPGA to DDR SDRAM Connections Continued DDR SDRAM FPGA Pin Category Signal Name Number Function SD DQ15 H5 Data input output SD DQ14 H6 SD DQ13 G5 SD DQ12 G6 SD DQ11 F2 SD DQ10 F1 SD DQ9 El g SD_DQ8 E2 A SD_DQ7 M6 SD_DQ6 M5 SD_DQ5 M4 SD DQ4 M3 SD DO3 I4 SD DQ2 L3 SD DO L1 SD DOO I2 SD BA K6 Bank address inputs SD BAO K5 SD RAS C1 Command inputs SD CAS C2 SD_WE D1 SD_CK_N J4 Differential clock input SD_CK_P J5 SD_CKE K3 Active High clock enable input SD CS K4 Active Low chip select input SD UDM JA Data Mask Upper and Lower data masks SD LDM J2 SD_UDQS G3 Data Strobe U
86. OT_CENTER Signal UG230_c2_05_021206 Figure 2 6 Push Button Switches Require Internal Pull up Resistor in FPGA Input Pin Rotary Shaft Encoder In principal the rotary shaft encoder behaves much like a cam connected to central shaft Rotating the shaft then operates two push button switches as shown in Figure 2 7 Depending on which way the shaft is rotated one of the switches opens before the other Likewise as the rotation continues one switch closes before the other However when the shaft is stationary also called the detent position both switches are closed A pull up resistor in each input pin generates a 1 for an open switch FPGA See the UCF file for details on specifying the pull up resistor A 0 Rotary Shaft Encoder UG230_c2_06_030606 GNDW Figure 2 7 Basic example of rotary shaft encoder circuitry Closing a switch connects it to ground generating a logic Low When the switch is open a pull up resistor within the FPGA pin pulls the signal to a logic High The UCF constraints in Figure 2 9 describe how to define the pull up resistor The FPGA circuitry to decode the A and P inputs is simple but must consider the mechanical switching noise on the inputs also called chatter As shown in Figure 2 8 the chatter can falsely indicate extra rotation events or even indicate rotations in the opposite www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 Jun
87. RAM Controller v2 00b http www xilinx com support documentation ip documentation opb ddr pdf Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 www xilinx com 109 Chapter 13 DDR SDRAM 110 www xilinx com Z XILINX Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Chapter 14 10 100 Ethernet Physical Layer Interface The Spartan 3E FPGA Starter Kit board includes a Standard Microsystems LAN83C185 10 100 Bthernet physical layer PHY interface and an RJ 45 connector as shown in Figure 14 1 With an Ethernet Media Access Controller MAC implemented in the FPGA the board can optionally connect to a standard Ethernet network All timing is controlled from an on board 25 MHz crystal oscillator RJ 45 Ethernet Connector J19 SMSC LAN83C185 10 100 Ethernet PHY 25 MHz Crystal UG230 ci4 01 022706 Figure 14 1 10 100 Ethernet PHY with RJ 45 Connector Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 111 UG230 v1 1 June 20 2008 Chapter 14 10 100 Ethernet Physical Layer Interface XILINX Ethernet PHY Connections 112 The FPGA connects to the LAN83C185 Ethernet PHY using a standard Media Independent Interface MII as shown in Figure 14 2 A more detailed description of the interface signals including the FPGA pin number appears in Table 14 1 SMSC LAN83C185 Spartan 3E FPGA 10 100 Ethernet PHY E TXD 3 0 See Table
88. RD LVCMOS33 NET SF_A lt 17 gt LOC T16 IOSTANDARD LVCMOS33 NET SF A lt 18 gt LOC U15 IOSTANDARD LVCMOS33 NET SF A lt 19 gt LOC V15 IOSTANDARD LVCMOS33 NET SF A lt 20 gt LOC T12 IOSTANDARD LVCMOS33 NET SF A lt 21 gt LOC V13 IOSTANDARD LVCMOS33 NET SF A lt 22 gt LOC V12 IOSTANDARD LVCMOS33 NET SF A lt 23 gt LOC N11 IOSTANDARD LVCMOS33 NET SF A lt 24 gt LOC A11 IOSTANDARD LVCMOS33 NET SF BYTE LOC C17 IOSTANDARD LVCMOS33 NET SF CEO LOC Die IOSTANDARD LVCMOS33 NET SF D lt 1 gt LOC P10 IOSTANDARD LVCMOS33 NET SF D lt 2 gt LOC RIO IOSTANDARD LVCMOS33 NET SF D lt 3 gt LOC V9 IOSTANDARD LVCMOS33 NET SF_D lt 4 gt LOC US IOSTANDARD LVCMOS33 NET SF_D lt 5 gt LOC R9 IOSTANDARD LVCMOS33 NET SF_D lt 6 gt LOC M9 IOSTANDARD LVCMOS33 NET SF_D lt 7 gt LOC 2 N9 IOSTANDARD LVCMOS33 NET SF D lt 8 gt LOC RIS IOSTANDARD LVCMOS33 NET SF D lt 9 gt LOC 2 R16 IOSTANDARD LVCMOS33 NET SF D lt 10 gt LOC P17 IOSTANDARD LVCMOS33 NET SF D lt 11 gt LOC M15 IOSTANDARD LVCMOS33 NET SF D 12 LOC M16 IOSTANDARD LVCMOS33 NET SF D lt 13 gt LOC P6 IOSTANDARD LVCMOS33 NET SF D lt 14 gt LOC R8 IOSTANDARD LVCMOS33 NET SF D lt 15 gt LOC T8 IOSTANDARD LVCMOS33 DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE
89. RS L18 Register Select 0 Instruction register during write operations Busy Flash during read operations 1 Data for read or write operations LCD_RW L17 Read Write Control 0 WRITE LCD accepts data 1 READ LCD presents data Voltage Compatibility The character LCD is power by 5V The FPGA I O signals are powered by 3 3V However the FPGA s output levels are recognized as valid Low or High logic levels by the LCD The LCD controller accepts 5V TTL signal levels and the 3 3V LVCMOS outputs provided by the FPGA meet the 5V TTL voltage level requirements The 390Q series resistors on the data lines prevent overstressing on the FPGA and StrataFlash I O pins when the character LCD drives a High logic value The character LCD drives the data lines when LCD RW is High Most applications treat the LCD as a write only peripheral and never read from from the display Interaction with Intel StrataFlash 44 As shown in Figure 5 1 the four LCD data signals are also shared with StrataFlash data lines SF_D lt 11 8 gt As shown in Table 5 2 the LCD StrataFlash interaction depends on the application usage in the design When the StrataFlash memory is disabled SF CE0 High then the FPGA application has full read write access to the LCD Conversely when LCD read operations are disabled LCD RW Low then the FPGA application has full read write access to the StrataFlash memory Table 5 2 LCD StrataFlash Control Interaction
90. S 2 serial bus to communicate with a host device the Spartan 3E FPGA in this case The PS 2 bus includes both clock and data Both a mouse and keyboard drive the bus with identical signal timings and both use 11 bit words that include a start stop and odd parity bit However the data packets are Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 63 UG230 v1 1 June 20 2008 Chapter 8 PS 2 Mouse Keyboard Port XILINX Keyboard 64 organized differently for a mouse and keyboard Furthermore the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the keyboard The PS 2 bus timing appears in Table 8 2 and Figure 8 2 The clock and data signals are only driven when data transfers occur otherwise they are held in the idle state at logic High The timing defines signal requirements for mouse to host communications and bidirectional keyboard communications As shown in Figure 8 2 the attached keyboard or mouse writes a bit on the data line when the clock signal is High and the host reads the data line when the clock signal is Low Table 8 2 PS 2 Bus Timing Symbol Parameter Min Max Tck Clock High or Low Time 30 us 50 us Tsy Data to clock Setup Time 5 us 25 us Tip Clock to data Hold Time 5 us 25 us Tok Tok Edge 0 Edge 10 Se p aec y 9 CLK PS2C FT Tag i EE DATA PS2D pen seb TPM UG230 c8 02 021806 Figure 8 2 PS 2 Bus
91. S33 DRIVE 4 SLEW SLOW NET GCLK10 LOC C9 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW 166 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008
92. SLOW NET SF D 11 LOC M15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW Figure 5 2 UCF Location Constraints for the Character LCD LCD Controller The 2 x 16 character LCD has an internal Sitronix ST7066U graphics controller that is functionally equivalent with the following devices e Samsung 56A0069X or KS0066U e Hitachi HD44780 e SMOS SED1278 Memory Map The controller has three internal memory regions each with a specific purpose The display must be initialized before accessing any of these memory regions DD RAM The Display Data RAM DD RAM stores the character code to be displayed on the screen Most applications interact primarily with DD RAM The character code stored in a DD RAM location references a specific character bitmap stored either in the predefined CG ROM character set or in the user defined CG RAM character set Figure 5 3shows the default address for the 32 character locations on the display The upper line of characters is stored between addresses 0x00 and 0x0F The second line of characters is stored between addresses 0x40 and Ox4F Character Display Addresses de resses ae K eee ee ee SD 7 2 50 67 i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 40 Figure 5 3 DD RAM Hexadecimal Addresses No Display Shifting Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 45 UG230 v1 1 June 20 2008 Chapter 5 Character LCD Screen XILINX 46 Physically the
93. SPI SCK cycles after asserting AD CONV Sample The converted values is then presented after the next AD CONV pulse Sample point point AD CONV te SPI SCK te Channel 0 Channel 1 EDI Channel 0 SPI MISO UG230 c10 05 030306 Figure 10 6 Analog to Digital Conversion Interface Figure 10 7 shows detailed transaction timing The AD CONV signal is not a traditional SPI slave select enable Be sure to provide enough SPI SCK clock cycles so that the ADC leaves the SPI MISO signal in the high impedance state Otherwise the ADC blocks communication to the other SPI peripherals As shown in Figure 10 6 use a 34 cycle communications sequence The ADC 3 states its data output for two clock cycles before and after each 14 bit data transfer 4ns min A AD_CONV I 19 6ns min I 3ns i lal i Ei l I I SPI SCK di 2 3 4 5 Je 18ns A Channel 0 SPI_MISO High Z W 13 WW 12 ML 1 M AD_CONV i 45ns min I ra E l 30 31 32 33 34 SPI SCK ens p Channel 1 i High Z spi mso 3 M 2 M1 Mo Oo z The A D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cycles UG230 c10 06 022306 Figure 10 7 Detailed SPI Timing to ADC UCF Location Constraints Figure 10 8 provides the User Constraint File UCF constraints for the amplifier interface including the I O pin assignment and I O standard used NET AD CONV LOC P11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 NET SPI SCK
94. Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 RUE picon _ SES T i Ac FEET Ev E LM TEXAS INSTRUMENTS TIRE EF d i XILINX DIGILENT z EL 3SPARTAN 3E L A ume A Intel Wb XILINX 2 XILINX Xilinx is disclosing this Document and Intellectual Property hereinafter the Design to you for use in the development of designs to operate on or interface with Xilinx FPGAs Except as stated herein none of the Design may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of the Design may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes Xilinx does not assume any liability arising out of the application or use of the Design nor does Xilinx convey any license under its patents copyrights or any rights of others You are responsible for obtaining any rights you may require for your use or implementation of the Design Xilinx reserves the right to make changes at any time to the Design as deemed desirable in the sole discretion of Xilinx Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made Xilinx will not a
95. Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Chapter 10 Analog Capture Circuit The Spartan 3E FPGA Starter Kit board includes a two channel analog capture circuit consisting of a programmable scaling pre amplifier and an analog to digital converter ADC as shown in Figure 10 1 Analog inputs are supplied on the J7 header 6 pin ADC Header J7 Linear Tech LTC1407A 1 Dual A D SPI SCK U16 AD CONV P11 SPI MISO N10 Linear Tech LTC6912 1 Dual Amp SPI MOSI T4 AMP CS N7 SPI SCK U16 AMP SHDN P7 AMP DOUT E18 UG230 c10 01 030306 Figure 10 1 Two Channel Analog Capture Circuit The analog capture circuit consists of a Linear Technology LTC6912 1 programmable pre amplifier that scales the incoming analog signal on header J7 see Figure 10 2 The output of pre amplifier connects to a Linear Technology LTC1407A 1 ADC Both the pre amplifier and the ADC are serially programmed or controlled by the FPGA Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 75 UG230 v1 1 June 20 2008 Chapter 10 Analog Capture Circuit XILINX pe LTC 6912 1 AMP dra ge LTC 1407A 1 ADC same a REF 1 65V DIN o 1 2 3 0 1 2 3 DOUT CSD AGAIN BGAIN SCK SPI Control Interface o 210 3 sool H CHANNEL 1 CHANNEL O SCK SPI Control Int
96. Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Z XILINX Configuring from SPI Flash Formatting an SPI Flash PROM File After generating the program file double click Generate PROM ACE or JTAG File to launch the iMPACT software as shown in Figure 12 6 Processes User Constraints Eg DAD Sunthesize KST f Implement Design EL 9 Generate Programming File JO Programming File Generation F E Generate PAD IM ACE d JTA SI Processes UG230 c15 05 030206 Figure 12 6 Double Click Generate PROM ACE or JTAG File After iMPACT starts double click PROM File Formatter as shown in Figure 12 7 iMPACT C data my des Eb File Edit view Operations Zr SlaveSerial P3 GelectMAP 8 Desktop Configu F E SystemA CE o Ge PRO IM File Fo Wn IMPACT Modes UG230_c15_06_030206 Figure 12 7 Double Click PROM File Formatter Choose 3rd Party SPI PROM as the target PROM type as shown in Figure 12 8 Select from any of the PROM File Formats the Intel Hex format MCS is popular The PROM Formatter automatically swaps the bit direction as SPI Flash PROMs shift out the most significant bit MSB first Enter the Location of the directory and the PROM File Name Click Next gt when finished Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 95 UG230 v1 1 June 20 2008 Chapter 12 SPI Serial Flash XILINX iMPACT Prepare PROM Files Bei Ed want to t
97. VCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 i DRIVE DRIVE RIVE RIVE RIVE RIVE RIVE RIVE RIVE Ej Ei E E EIS DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE RRP PP a ah aS oa SAR Sog og og a SLEW SLEW LEW LEW LEW LEW LEW LEW LEW Dm uU 0 uu uu SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLOW SLOW LOW LOW LOW LOW LOW LOW LOW Dm LD n U U n n SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW Figure 16 2 UCF Location Constraints for FPGA Connections to CPLD Figure 16 3 provides the UCF constraints for the CPLD including the I O pin assignment and the I O standard used NET XC WDT EN LOC P16 IOSTANDAR NET XC CMD 1 LOC P30 IOSTANDAR NET XC CMD 0 LOC P29 IOSTANDAR NET XC D lt 2 gt LOC P36 IOSTANDAR NET XC D lt 1 gt LOC p34 IOSTANDAR NET XC D lt 0 gt LOC P33 IOSTANDAR NET FPGA M2 LOC pg IOSTANDAR NET FPGA M1 LOC pe IOSTANDAR NET FPGA MO LOC ps5 IOSTANDAR NET XC CPLD EN LOC P42 IOSTANDAR NET XC TRIG LOC P41 IOSTANDAR NET XC DONE LOC P40 IOSTANDAR NET XC PROG B LOC P39 IOSTANDAR NET XC GCKO LOC P43 IOSTANDAR NET GCLK10 LOC pi IOSTANDAR NET SPI SCK LOC p44 IOSTANDAR SF A lt 24 gt is the same as FX2 I0 lt 32 g
98. a ES bi m 66 E074 TAB a il 0D EJ E E B Ea ES Fi i Ra 54 J 51 E0 6B S EN UJ LA Lis Jas Je SPESE Med 1C B 23 2B 34 33 3B 42 48 4c 52 2072 Z X C V B N M lt 1 A Sin 1z 22 21 2a 32 31 3A 41 AA 59 Space Ctrl 29 Es E014 UG230_c8_03_021806 Figure 8 3 PS 2 Keyboard Scan Codes The host can also send commands and data to the keyboard Table 8 3 provides a short list of some often used commands Table 8 3 Common PS 2 Keyboard Commands Command ED Description Turn on off Num Lock Caps Lock and Scroll Lock LEDs The keyboard acknowledges receipt of an ED command by replying with an FA after which the host sends another byte to set LED status The bit positions for the keyboard LEDs are shown below Write a 1 to the specific bit to illuminate the associated keyboard LED 7 6 5 4 3 2 1 0 Ignored Caps Lock Num Lock Scroll Lock EE Echo Upon receiving an echo command the keyboard replies with the same scan code EE F3 Set scan code repeat rate The keyboard acknowledges receipt of an F3 by returning an FA after which the host sends a second byte to set the repeat rate FE Resend Upon receiving a resend command the keyboard resends the last scan code sent FF Reset Resets the keyboard The keyboard sends commands or data to the h
99. a logic analyzer This debugging port is intended primarily for the Xilinx ChipScope Pro software with the Agilent s FPGA Dynamic Probe It can however be used with either the Agilent or Tektronix probes without the ChipScope software using FPGA Editor s probe command Refer to Related Resources page 126 for more information on the ChipScope Pro tool probes and connectors Table 15 3 provides the connector pinout Only 18 FPGA pins attach to the connector the remaining connector pads are unconnected All 18 FPGA pins are shared with the FX2 connector J3 and the 6 pin accessory port connectors J1 J2 and J4 See Table 15 1 page 117 for more information on how these pins are shared Table 15 3 Connectorless Debugging Port Landing Pads J6 UG230 v1 1 June 20 2008 Connectorless Signal Name FPGA Pin Landing Pads FPGA Pin Signal Name FX2 IO1 B4 A1 B1 FX2 IO2 A4 A2 B2 D5 FX2 IO3 GND GND A3 B3 C5 FX2 104 FX2 105 A6 A4 B4 GND GND FX2 IO6 B6 A5 B5 E7 FX2_107 GND GND A6 B6 F7 FX2 108 FX2 IO9 D7 A7 B7 GND GND FX2 IO10 C7 A8 B8 F8 FX2_IO11 GND GND A9 B9 E8 FX2 IO12 FX2_IO13 F9 A10 B10 GND GND FX2 IO14 E9 All B11 D11 FX2 IO15 GND GND A12 B12 C11 FX2 IO16 FX2 IO17 F11 A13 B13 GND GND FX2_IO18 E11 A14 B14 A15 B15 A16 B16 A17 B17 A18 B18 A19 B19 A20 B20 A21 B21 A22 B22 A23 B23 A24 B24 A25 B25 A26 B26 A27 B27
100. ad or write operations to the display are to or from DD RAM The addresses for displayed characters appear in Figure 5 3 Execution Time 40 us Read Busy Flag and Address Read the Busy flag BF to determine if an internal operation is in progress and read the current address counter contents BF 1 indicates that an internal operation is in progress The next instruction is not accepted until BF is cleared or until the current instruction is allowed the maximum time to execute This command also returns the present value of address counter The address counter is used for both CG RAM and DD RAM addresses The specific context depends on the most recent Set CG RAM Address or Set DD RAM Address command issued Execution Time 1 us Write Data to CG RAM or DD RAM Write data into DD RAM if the command follows a previous Set DD RAM Address command or write data into CG RAM if the command follows a previous Set CG RAM Address command Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 51 UG230 v1 1 June 20 2008 Chapter 5 Character LCD Screen XILINX After the write operation the address is automatically incremented or decremented by 1 according to the Entry Mode Set command The entry mode also determines display shift Execution Time 40 us Read Data from CG RAM or DD RAM Read data from DD RAM if the command follows a previous Set DD RAM Address command or read data from CG RAM if the command follows a prev
101. airs e Three 6 pin Peripheral Module connections e Landing pads for an Agilent or Tektronix connectorless probe Jumper JP9 I O Bank 0 Voltage d Default is 3 3V set to 2 5V for differential UO Hirose 100 pin FX2 Connector J3 43 I O connections high performance J1 6 pin Accessory Header J6 Probe Landing Pads Connectorless logic analyzer probes J2 6 pin Accessory Header J4 6 pin Accessory Header UG230 c12 01 030606 Figure 15 1 Expansion Headers Hirose 100 pin FX2 Edge Connector J3 A 100 pin edge connector is located along the right edge of the board see Figure 15 1 This connector is a Hirose FX2 100P 1 27DS header with 1 27 mm pitch Throughout the documentation this connector is called the FX2 connector As shown in Figure 15 2 43 FPGA I O pins interface to the FX2 connector All but five of these pins are true bidirectional I O pins capable of driving or receiving signals Five pins FX2_IP lt 38 35 gt and FX2_IP lt 40 gt are Input only pins on the FPGA These pins are highlighted in light green in Table 15 1 and cannot drive the FX2 connector but can receive signals Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 115 UG230 v1 1 June 20 2008 Chapter 15 Expansion Connectors XILINX Hirose 100 pin Expansion Spartan 3E FPGA Connector J3 FX2 I 4 1 See Table d See Table FX2_IP lt 38 35 gt See Table C3 C15 E10 See Table FX2 10 lt 39 gt
102. and data transfers to the character display are via 8 bits transferred using two sequential 4 bit operations Each 8 bit transfer must be decomposed into two 4 bit transfers spaced apart by at least 1 us as shown in Figure 5 6 The upper nibble is transferred first followed by the lower nibble An 8 bit write operation must be spaced least 40 us before the next communication This delay must be increased to 1 64 ms following a Clear Display command Initializing the Display After power on the display must be initialized to establish the required communication protocol The initialization sequence is simple and ideally suited to the highly efficient 8 bit PicoBlaze embedded controller After initialization the PicoBlaze controller is available for more complex control or computation beyond simply driving the display Power On Initialization The initialization sequence first establishes that the FPGA application wishes to use the four bit data interface to the LCD as follows e Wait 15 ms or longer although the display is generally ready when the FPGA finishes configuration The 15 ms interval is 750 000 clock cycles at 50 MHz e Write SF_D lt 11 8 gt 0x3 pulse LCD E High for 12 clock cycles e Wait 4 1 ms or longer which is 205 000 clock cycles at 50 MHz e Write SF_D lt 11 8 gt 0x3 pulse LCD E High for 12 clock cycles e Wait 100 us or longer which is 5 000 clock cycles at 50 MHz e Write SF_D lt 11 8 gt 0x3 pulse LCD_E
103. ard User Guide www xilinx com 25 UG230 v1 1 June 20 2008 Chapter 4 FPGA Configuration Options XILINX 16 Mbit ST Micro SPI Serial Flash Serial Peripheral Interface SPI mode Configuration Options USB based Download Debug Port Uses standard USB cable PROG B button Platform Flash PROM mode pins Z NUNA k 128 Mbit Intel StrataFlash Parallel NOR Flash memory Byte Peripheral Interface BPI mode ne SPARYAN 3E UG230 c4 01 022006 Figure 4 1 Spartan 3E Starter Kit FPGA Configuration Options Configuration Mode Jumper Settings Header J30 Select between three on board configuration sources DONE Pin LED PROG B Push Button Switch Lights up when FPGA successfully configured Press and release to restart configuration GR OLF AULT ER 64 Macrocell Xilinx XC2C64A CoolRunner CPLD 4 Mbit Xilinx Platform Flash PROM Controller upper address lines in BPI mode and Configuration storage for Master Serial mode Platform Flash chip select User programmable UG230 c4 02 030906 Figure 4 2 Detailed Configuration Options 26 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 3 XILINX Configuration Mode Jumpers The configuration mode jumpers determine which configuration mode the FPGA uses when power is first applied or whenever the PROG button is pressed The DONE pin LED lights when the FPGA successfully finishes configuration Pressing the PROG button
104. are the design can be downloaded using the iMPACT programming software and the USB cable To begin programming connect the USB cable to the starter kit board and apply power to the board Then double click Configure Device iMPACT from within Project Navigator as shown in Figure 4 5 Processes Br HAO Gereete Programming File E Programming File Generation F Generate PROM ACE or JT GE Configure Device DMDAC SD wf Update Bitstream with Processo ae Processes UG230_c4_06_022406 Figure 4 5 Double Click to Invoke iMPACT If the board is connected properly the iMPACT programming software automatically recognizes the three devices in the JTAG programming file as shown in Figure 4 6 If not already prompted click the first device in the chain the Spartan 3E FPGA to highlight it Right click the FPGA and select Assign New Configuration File Select the desired FPGA configuration file and click OK iMPACT C data my designs s3e starter kit s3e starter kit ipf Boundary Scan File Edit View Operations Options Output Debug Window Help le B X Gx aex m xj e a3 Boundary Scan E i Gal SlaveSerial be mr SelectMAP tb Em wr Desktop Configu Program e B System CE Verify 355 MPACT Modes emp Get Device ID xd TDO Get Device Signature Usercode Assign New Configuration File Available Operations are Program 1
105. arget a C Xilinx PROM C Generic Parallel PROM 3rd Party SPI PROM PROM File Format Ze MCS C TEK UEP TO format C EXO C BIN C ISC C HEX JW Swap Bits Checksum Fill Value D Hex Digits FF PROM File Name MySPlFlash Location C data my_designs s3e_starter_kit Browse UG230_c15_07_030206 Figure 12 8 Choose the PROM Target Type the Data Format and File Location The Spartan 3E Starter Kit board has a 16 Mbit SPI serial Flash PROM Select 16M from the drop list as shown in Figure 12 9 Click Next iMPACT Specify SPI PROM Device Auto Select PROM Density Select SPI PROM Density bits 128K y lt Back ner Cancel UG230 c15 08 030206 Figure 12 9 Choose 16M 96 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Configuring from SPI Flash The PROM Formatter then echoes the settings as shown in Figure 12 10 Click Finish iMPACT File Generation Summary You have entered following information PROM Type SPI PROM File Format mcs Fill Value FF PROM filename MySPIFlash Number of PROMs 1 Cancel UG230 c15 09 030206 Figure 12 10 Click Finish after Entering PROM Formatter Settings The PROM Formatter then prompts for the name s of the FPGA configuration bitstream file As shown in Figure 12 11 click OK to start selecting files Select an FPGA bitstream file bit Choose No af
106. attached to the board disconnect it Simultaneously connecting both the USB cable and the parallel cable to the PC confuses the iMPACT software Connect one end of the JTAG parallel programming cable to the parallel printer port of the PC Connect the JTAG end of the cable to Header J12 as shown in Figure 12 15a The physical location of Header J12 is more clearly shown in Figure 12 3 page 93 The J12 header connects directly to the SPI Flash pins it is not connected to the JTAG chain The JTAG3 cable directly mounts to Header J12 The labels on the JTAGS cable face toward the J11 jumpers If using flying leads they must be connected as shown in Figure 12 15b and Table 12 2 Note the color coding for the leads The gray INIT lead is left unconnected Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 99 UG230 v1 1 June 20 2008 Chapter 12 SPI Serial Flash ZT XILINX a JTAG3 Parallel Connector b Parallel Cable III or Parallel Cable IV with Flying Leads UG230 c15 14 030206 Figure 12 15 Attaching a JTAG Parallel Programming Cable to the Board Table 12 2 Cable Connections to J12 Header Cable and Labels Connections J12 Header Label SEL SDI SDO SCK GND VCC JTAG3 Cable Label TMS TDI TDO TCK GND VCC Flying Leads Label TMS TDO GND VREF PROG DIN DONE GND VREF Insert Jumper on JP8 and Hold PROG B Low The JTAG parallel programming cable directly accesses the SPI Flash pins To avoid s
107. c2 01 021206 Figure 2 1 Four Slide Switches Operation When in the UP or ON position a switch connects the FPGA pin to 3 3V a logic High When DOWN or in the OFF position the switch connects the FPGA pin to ground a logic Low The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry although such circuitry could easily be added to the FPGA design programmed on the board UCF Location Constraints Figure 2 2 provides the UCF constraints for the four slide switches including the I O pin assignment and the I O standard used The PULLUP resistor is not required but it defines the input value when the switch is in the middle of a transition Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 15 UG230 v1 1 June 20 2008 Chapter 2 Switches Buttons and Knob XILINX NET SW lt 0 gt LOC L13 IOSTANDARD LVTTL PULLUP NET SW lt 1 gt LOC L14 IOSTANDARD LVTTL PULLUP NET SW lt 2 gt LOC H18 IOSTANDARD LVTTL PULLUP NET SW lt 3 gt LOC N17 IOSTANDARD LVTTL PULLUP Figure 2 2 UCF Constraints for Slide Switches Push Button Switches 16 Locations and Labels The Spartan 3E FPGA Starter Kit board has four momentary contact push button switches shown in Figure 2 3 The push buttons are located in the lower left corner of the board and are labeled BTN NORTH BIN EAST BIN SOUTH and BIN WEST The FPGA pins that connect to
108. ce File entry A Click Ok to continue UG230_c4_19_022706 Figure 4 18 Enter FPGA Configuration Bitstream File s When PROM formatting is complete the iMPACT software presents the present settings by showing the PROM the select FPGA bitstream s and the amount of PROM space consumed by the bitstream Figure 4 19 shows an example for a single XC3S500E FPGA bitstream stored in an XCF04S Platform Flash PROM xcf dz 34 13 Full xc3s500e myfpgabitstream UG230 c4 20 022706 Figure 4 19 PROM Formatting Completed Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 37 UG230 v1 1 June 20 2008 Chapter 4 FPGA Configuration Options ZT XILINX To generate the actual PROM file click Operations gt Generate File as shown in Figure 4 20 iMPACT C data my designs s3e starter kit s3e File Edit view Operations Options Output Debug J E X Sa Program ee Verify fl Erase Compact Flash Integrity Check UG230_c4_21_022706 Figure 4 20 Click Operations gt Generate File to Create the Formatted PROM File The iMPACT software indicates that the PROM file was successfully created as shown in Figure 4 21 xcf 4s 54 13 Full xc3s500e myfpgabitstream PROM File Generation Succeeded UG230 c4 22 022706 Figure 4 21 PROM File Formatter Succeeded Programming the Platform Flash PROM To program the formatted PROM file into the Platform Flash PROM via the on board USB
109. com picoblaze LTC6912 Dual Programmable Gain Amplifiers with Serial Digital Interface http www linear com pc downloadDocument do navId H0 C1 C1154 C1009 C1121 P7596 D5359 LTC1407A 1 Serial 14 bit Simultaneous Sampling ADCs with Shutdown http www linear com pc downloadDocument do navId H0 C1 C1155 C1001 C1158 P2420 D1295 Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 81 UG230 v1 1 June 20 2008 Chapter 10 Analog Capture Circuit 82 www xilinx com Z XILINX Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Chapter 1 Intel StrataFlash Parallel NOR Flash PROM l As shown in Figure 11 1 the Spartan 3E FPGA Starter Kit boards includes a 128 Mbit 16 Mbyte Intel StrataFlash parallel NOR Flash PROM As indicated some of the StrataFlash connections are shared with other components on the board Spartan 3E FPGA SF CEO SF OE SF WE SF BYTE SF STS SF D lt 15 12 gt SF D lt 11 8 gt SF D lt 7 1 gt SPI_MISO CoolRunner Il CPLD Figure 11 1 SF A lt 19 0 gt SF A lt 24 20 gt Intel StrataFlash CE2 CE1 gt CEO gt OE gt WE BYTE gt STS D 15 12 D 11 8 D 7 1 D O A 24 20 A 19 0 SPI Serial Flash L EE rr rr rr rr rr rr rr rr rr rr rr rr rr eena e c U DH D D D D D D D 8 8 8 8 8 D D D D D D D Platform
110. d Clear Display Clear the display and return the cursor to the home position the top left corner This command writes a blank space ASCII ANSI character code 0x20 into all DD RAM addresses The address counter is reset to 0 location 0x00 in DD RAM Clears all option settings The I D control bit is set to 1 increment address counter mode in the Entry Mode Set command Execution Time 82 us 1 64 ms Return Cursor Home Return the cursor to the home position the top left corner DD RAM contents are unaffected Also returns the display being shifted to the original position shown in Figure 5 3 The address counter is reset to 0 location 0x00 in DD RAM The display is returned to its original status if it was shifted The cursor or blink move to the top left character location Execution Time 40 us 1 6 ms Entry Mode Set Sets the cursor move direction and specifies whether or not to shift the display These operations are performed during data reads and writes Execution Time 40 us Bit DB1 1 D Increment Decrement 0 Auto decrement address counter Cursor blink moves to left 1 Auto increment address counter Cursor blink moves to right Spartan 3E FPGA Starter Kit Board User Guide www xilinx com UG230 v1 1 June 20 2008 49 Chapter 5 Character LCD Screen XILINX 50 This bit either auto increments or auto decrements the DD RAM and CG RAM address counter by
111. dI N TT dI d rT dl NET dI d T di NZT dI dZT dl x SdI y pal dI 101 6 19845 uo 6dr fig 185 SI g AUR 40 JON UG230 Aa 06 021806 Schematic Sheet 7 Figure A 6 145 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Appendix A Schematics XILINX FPGA I O Banks 2 and 3 146 IC10B2 represents the connections to I O Bank 2 on the FPGA Some of the I O Bank 2 connections are used for FPGA configuration and are listed as IC10MISC IC10B3 represents the connections to I O Bank 3 on the FPGA Bank 3 is dedicated to the DDR SDRAM interface and is consequently powered by 2 5V See Chapter 13 DDR SDRAM for additional information www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 FPGA I O Banks 2 and 3 XILINX v 1 8 199uS 90 20 20 e1ieQ 280 008 4200 S S BT ZZ862X OX MES 4914819 FES 37111 asn n S 1182119 I 40138UUOJ u3nol 1195 L NUS 4ouing pue z S oueg ISEDX l33HS QUO iz USRI Eea de 6 2 ON ZT ya OS 0S 39 4 urbu3 opoz soez iubi4hdog ul iuerrbiQ X 9 9IdGZW WON CT 40129uUO ZX4 9504IH ZX4 pueog 41914818 jg ue Jeds p 18040413 3 OD Dues Es 97a 290 CTT 4STFTIOWY ueg diu S3IP ST ZI G ueenieq fia yey SUId 40 9 2 SSION X TI 48149 u00 Q U QU cae Tal NrZ1 01 dbZT 01 ZX0H1 Ne T1701 NEZT OI 94 TOHT d 11701 deZT 01 SX T9H1 NET1 OI NIZT
112. data on DO FPGA MI Low FPGA M0 Low INIT B High SF CE0 Low StrataFlash outputs data SF_OE Low AD CONV High Serial data is clocked out of the A D converter SPI SCK DAC CS Low DAC outputs previous command in response to SPI SCK transitions SPI SCK Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 87 UG230 v1 1 June 20 2008 Chapter 11 Intel StrataFlash Parallel NOR Flash PROM XILINX UCF Location Constraints Address Figure 11 2 provides the UCF constraints for the StrataFlash address pins including the I O pin assignment and the I O standard used NET SF A 24 LOC A11 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 23 gt LOC N11 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 22 LOC V12 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A 21 LOC V13 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 20 gt LOC T12 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 19 gt LOC V15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 18 gt LOC U15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 17 gt LOC T16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 16 gt LOC U18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 15 gt LOC T17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF A lt 14 gt LOC R18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW
113. data sheet Select pairs have optional landing pads for external termination resistors These signals are not routed with matched differential impedance as would be required for ultimate performance However all traces have similar lengths to minimize skew 118 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 3 XILINX Table 15 2 Differential I O Pairs Hirose 100 pin FX2 Edge Connector J3 External Resistor Differential Pair Signal Name FPGA Pins FPGA Pin Name Direction DIFF_TERM Designator i FX2 IO B4 IO L24N 0 I O Yes FX2 IO2 A4 IO L24P 0 I O Yes 7 FX2 103 D5 IO L23N 0 I O Yes FX2 104 C5 IO L23P 0 I O Yes 3 FX2 105 A6 IO L20N 0 I O Yes FX2 106 B6 IO L20P 0 I O Yes x FX2 IO7 E7 IO L19N 0 I O Yes FX2 108 F7 IO L19P 0 I O Yes 5 FX2 IO9 D7 IO L18N 0 I O Yes FX2 IO10 C7 IO L18P 0 I O Yes e FX2 IO11 F8 IO L17N 0 I O Yes FX2 IO12 E8 IO L17P 0 I O Yes FX2 IO13 F9 IP L15N 0 I O Yes FX2 IO14 E9 IP L15P 0 I O Yes FX2 1015 D11 IP L09N 0 I O Yes FX2 IO16 C11 IP L09P 0 I O Yes FX2 IO17 F11 IO L08N 0 I O Yes 9 R202 FX2 1018 E11 IO L08P 0 I O Yes FX2 IO19 E12 IO L06N 0 I O Yes 10 R208 FX2 IO20 F12 IO L06P 0 I O Yes FX2 IO21 A13 IO L05P 0 I O Yes 11 R204 FX2 IO22 B13 IO L05N 0 I O Yes FX2 IO23 A14 IO LO4N 0 I O Yes 12 R205 FX2 1024 B14 IO L04P 0 I O Yes FX2 I
114. ding Table 15 1 also highlights the shared connections to the eight discrete LEDs the three 6 pin Accessory Headers J1 J2 and J4 and the connectorless debugging header J6 116 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Hirose 100 pin FX2 Edge Connector J3 Table 15 1 Hirose 100 pin FX2 Connector Pinout and FPGA Connections J3 Shared Header Connections FX2 Connector A B Signal Name FPGA Pin LED J1 J2 JP4 J6 top bottom FPGA Pin Signal Name 1 1 SHIELD 2 2 GND TMS B 3 2 TDO XC2C JTSEL 4 4 TCK_B TDO_FX2 5 5 FX2_IO1 B4 6 6 FX2_IO2 A4 7 Z FX2_IO3 D5 8 8 FX2 IO4 C5 9 9 FX2 105 A6 10 10 FX2 106 B6 11 11 FX2 IO7 E7 12 12 FX2_IO8 F7 13 13 FX2_IO9 D7 14 14 FX2 IO10 C7 9 15 15 FX2 IO11 F8 9 16 16 FX2 IO12 E8 9 17 17 FX2 IO13 F9 LD7 18 18 FX2 IO14 E9 LD6 19 19 FX2 IO15 D11 LD5 20 20 FX2_1016 C11 LD4 21 21 FX2 IO17 F11 LD3 4 22 22 FX2 IO18 Ell LD2 295 23 FX2_IO19 E12 LD1 24 24 FX2 1020 F12 LDO 29 25 FX2_1021 A13 26 26 FX2 1022 B13 25 27 FX2_IO23 A14 28 28 FX2 1024 B14 20 29 FX2_IO25 C14 30 30 FX2_IO26 D14 31 31 FX2_IO27 A16 32 32 FX2 1028 B16 33 33 FX2 1029 E13 34 34 Spartan 3E FPGA Starter Kit Board User Guide www
115. e 10 4 The amplifier captures serial data on SPI MOSI on the rising edge of the SPI SCK clock signal The amplifier presents serial data on AMP DOUT on the falling edge of SPI SCK AMP CS er 981 7 YOOX UY 5 HN mmm MN mmm amp pouT Previous MAR MAL 5 AWA 4 MAM 3 AA 2 AW All timing is minimum in nanoseconds unless otherwise noted EE Figure 10 4 SPI Timing When Communicating with Amplifier Spartan 3E FPGA Starter Kit Board User Guide 78 www xilinx com UG230 v1 1 June 20 2008 XILINX Analog to Digital Converter ADC The amplifier interface is relatively slow supporting only about a 10 MHz clock frequency UCF Location Constraints Figure 10 5 provides the User Constraint File UCF constraints for the amplifier interface including the I O pin assignment and I O standard used NET SPI MOSI LOC T4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 NET AMP CS LOC N7 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 NET SPI SCK LOC U16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET AMP SHDN LOC P7 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 NET AMP DOUT LOC E18 IOSTANDARD LVCMOS33 Figure 10 5 UCF Location Constraints for the DAC Interface Analog to Digital Converter ADC The LTC1407A 1 provides two ADCs Both analog inputs are sampled simultaneously when the AD CONV signal is applied Interface Table 10 3 lists the interface signals bet
116. e 128 Mbit StrataFlash memory e Linear Technology for the SPI compatible A D and D A converters the programmable pre amplifier and the power regulators for the non FPGA components e Micron Technology Inc for the 32M x 16 DDR SDRAM e SMSC for the 10 100 Ethernet PHY e STMicroelectronics for the 16M x 1 SPI serial Flash PROM e Texas Instruments Incorporated for the three rail TPS75003 regulator supplying most of the FPGA supply voltages e Xilinx Inc Configuration Solutions Division for the XCF04S Platform Flash PROM and their support for the embedded USB programmer e Xilinx Inc for the XC2C64A CoolRunner II CPLD Guide Contents This manual contains the following chapters e Chapter 1 Introduction and Overview provides an overview of the key features of the Spartan 3E FPGA Starter Kit board e Chapter 2 Switches Buttons and Knob defines the switches buttons and knobs present on the Spartan 3E FPGA Starter Kit board e Chapter 3 Clock Sources describes the various clock sources available on the Spartan 3E FPGA Starter Kit board e Chapter 4 FPGA Configuration Options describes the configuration options for the FPGA on the Spartan 3E FPGA Starter Kit board Spartan 3E Start Kit Board User Guide www xilinx com 9 UG230 v1 1 June 20 2008 Preface About This Guide XILINX e Chapter 5 Character LCD Screen describes the functionality of the character LCD screen e Chapter 6 VGA
117. e 20 2008 XILINX Discrete LEDs direction See the Rotary Encoder Interface reference design in Related Resources for an example Rising edge on A when B is Low indicates RIGHT clockwise rotation Switch opening chatter on A Rotating RIGHT ne co false clicks to the RIGHT a UI Nu Bu closing chatter on B injects false clicks to the LEFT B rising edge when A is Low etent DI D Detent UG230 c2 07 030606 Figure 2 8 Outputs from Rotary Shaft Encoder May Include Mechanical Chatter UCF Location Constraints Figure 2 9 provides the UCF constraints for the four push button switches including the I O pin assignment and the I O standard used and defines a pull down resistor on each input NET ROT A LOC K18 IOSTANDARD LVTTL PULLUP NET ROT B LOC G18 IOSTANDARD LVTTL PULLUP NET ROT CENTER LOC V16 IOSTANDARD LVTTL PULLDOWN Figure 2 9 UCF Constraints for Rotary Push Button Switch Discrete LEDs Locations and Labels The Spartan 3E FPGA Starter Kit board has eight individual surface mount LEDs located above the slide switches as shown in Figure 2 10 The LEDs are labeled LED7 through LEDO LED7 is the left most LED LEDO the right most LED LED1 E12 LEDS D11 LED4 C11 LED3 F11 LED2 E11 LEDO F12 oo LL H w RO D Q LI LU a J UG230 c2 04 021206 Fig
118. e StrataFlash device Instead the XC2C64 CPLD controls the pins during configuration As described in Table 11 1 and Shared Connections some of the StrataFlash connections are shared with other components on the board www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Z XILINX Table 11 1 StrataFlash Connections FPGA to StrataFlash Connections Category Address StrataFlash FPGA Pin Signal Name Number Function SF A24 All Shared with XC2C64A CPLD The CPLD EE SF A22 V12 XC2C64A CoolRunner II CPLD Also SF_A20 T12 SF_A19 V15 Connects to FPGA pins A 19 0 to support the SE AIS U15 BPI configuration SF A17 T16 SF A16 U18 SF A15 T17 SF A14 R18 SF A13 T18 SF A12 L16 SF A11 L15 SF A10 K13 SF A9 K12 SF A8 K15 SF A7 K14 SF Ap J17 SF_A5 J16 SF A4 J15 SF A3 J14 SF_A2 J12 SF_A1 J13 SF AO H17 Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 www xilinx com 85 Chapter 11 Intel StrataFlash Parallel NOR Flash PROM 86 Z XILINX Table 11 1 FPGA to StrataFlash Connections StrataFlash FPGA Pin Category Signal Name Number Function SF D15 T8 Upper 8 bits of a 16 bit halfword when SE DIE Rg StrataFlash is E SF_D13 P6 configured for x16 data SED Ie SF BYTE High SF D11 M1
119. ed configuration PROM Ship the optimally sized SPI Flash memory for the FPGA mounted on the board Supply security If a certain SPI Flash density is not available in the desired package switch to a different package style or to a different density to secure availability lt ji D o ul Pin 1 L T 16 pin SOIC Pin 1 8 pin SOIC Do not connect 8 lead MLP VCC HOLD C GN Do not connect 9 zio S o S UG230_c15_18_030606 Figure 12 18 Multi Package Layout for the STMicroelectronics M25Pxx Family Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 103 UG230 v1 1 June 20 2008 Chapter 12 SPI Serial Flash XILINX Related Resources 104 Xilinx Parallel Cable IV with Flying Leads Digilent JTAG3 Programming Cable http www digilentinc com Products Catalog cfm Nav1 Products amp Nav2 Cables amp Cat Cable STMicroelectronics M25P16 SPI Serial Flash Data Sheet http www numonyx com Documents Datasheets M25P16 pdf PicoBlaze SPI Serial Flash Programmer via RS 232 Reference Design http www xilinx com s3estarter Using Serial Flash on the Spartan 3E Starter Kit Board Reference Design http www xilinx com s3estarter Universal Scan SPI Flash Programming via JTAG Training Video http www ricreations com JTAG Software Downloads htm www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 2 XILINX Chapter 13 DDR SDR
120. eration www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 3 XILINX UCF Location Constraints UCF Location Constraints Figure 6 4 provides the UCF constraints for the VGA display port including the I O pin assignment the I O standard used the output slew rate and the output drive current NET VGA RED LOC H14 NET VGA GREEN LOC H15 NET VGA BLUE LOC G15 NET VGA HSYNC LOC F15 NET VGA VSYNC LOC F14 Figure 6 4 UCF Constraints for VGA Display Port Related Resources e VESA http www vesa org e VGA timing information IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD Wo gu H oH H LVTTI LVTTI LVTT LVTTI L L LVTTL L L DRIVE DRIVE DRIVE DRIVE DRIVE http www epanorama net documents pc vga timing html Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 www xilinx com ooo OO OO SLEW SLEW SLEW SLEW SLEW HW gw H H H FAST FAST FAST FAST FAST 59 Chapter 6 VGA Display Port 60 www xilinx com Z XILINX Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Chapter 7 RS 232 Serial Ports Overview As shown in Figure 7 1 the Spartan 3E FPGA Starter Kit board has two RS 232 serial ports a female DB9 DCE connector and a male DTE connector The DCE style port connects directly to the serial port connec
121. erface AD CONV AMP DOUT SPI MISO UG230 c10 02 022306 Figure 10 2 Detailed View of Analog Capture Circuit Digital Outputs from Analog Inputs 76 The analog capture circuit converts the analog voltage on VINA or VINB and converts it to a 14 bit digital representation D 13 0 as expressed by Equation 10 1 Vin 1 65V D 13 0 GAIN x 25V x 8192 Equation 10 1 The GAIN is the current setting loaded into the programmable pre amplifier The various allowable settings for GAIN and allowable voltages applied to the VINA and VINB inputs appear in Table 10 2 The reference voltage for the amplifier and the ADC is 1 65V generated via a voltage divider shown in Figure 10 2 Consequently 1 65V is subtracted from the input voltage on VINA or VINB The maximum range of the ADC is 1 25V centered around the reference voltage 1 65V Hence 1 25V appears in the denominator to scale the analog input accordingly www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Z XILINX Programmable Pre Amplifier Finally the ADC presents a 14 bit two s complement digital output A 14 bit two s complement number represents values between 213 and 213 1 Therefore the quantity is scaled by 8192 or 213 See Programmable Pre Amplifier to control the GAIN settings on the programmable pre amplifier The reference design files provide more i
122. es the UCF constraints for the three clock input sources including the I O pin assignment and the I O standard used The settings assume that jumper JP9 is set for 3 3V If JP9 is set for 2 5V adjust the IOSTANDARD settings accordingly www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Related Resources NET CLK 50MHZ LOC C9 IOSTANDARD LVCMOS33 NET CLK SMA LOC A10 IOSTANDARD LVCMOS33 NET CLK AUX LOC B8 IOSTANDARD LVCMOS33 Figure 3 2 UCF Location Constraints for Clock Sources Clock Period Constraints The Xilinx ISE development software uses timing driven logic placement and routing Set the clock PERIOD constraint as appropriate An example constraint appears in Figure 3 3 for the on board 50 MHz clock oscillator The CLK_50MHZ frequency is 50 MHz which equates to a 20 ns period The output duty cycle from the oscillator ranges between 40 to 60 Define clock period for 50 MHz oscillator NET CLK 50MHZ PERIOD 20 0ns HIGH 40 Figure 3 3 UCF Clock PERIOD Constraint Related Resources e Epson SG 8002JF Series Oscillator Data Sheet 50 MHz Oscillator http www eea epson com portal pls portal docs 1 793426 PDF Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 23 UG230 v1 1 June 20 2008 Chapter 3 Clock Sources 24 www xilinx com 7 XILINX Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 J
123. evice is a Linear Technology LTC2624 quad DAC with 12 bit unsigned resolution The four outputs from the DAC appear on the J5 header which uses the Digilent 6 pin Peripheral Module format The DAC and the header are located immediately above the Ethernet RJ 45 connector as shown in Figure 9 1 Linear Tech LTC2624 Quad DAC 6 pin DAC Header J5 SPI_MOSI T4 SPI MISO N10 SPI SCK U16 DAC CS N8 DAC CLR P8 UG230 c9 01 030906 Figure 9 1 Digital to Analog Converter and Associated Header SPI Communication As shown in Figure 9 2 the FPGA uses a Serial Peripheral Interface SPI to communicate digital values to each of the four DAC channels The SPI bus is a full duplex synchronous character oriented channel employing a simple four wire interface A bus master the FPGA in this example drives the bus clock signal SPI SCK and transmits serial data SPI MOSI to the selected bus slave the DAC in this example At the same time the bus slave provides serial data SPI MISO back to the bus master Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 69 UG230 v1 1 June 20 2008 Z XILINX Chapter 9 Digital to Analog Converter DAC DAC CLR lag CUT 7L TC 2624 DAC P Header J5 BEE A ET 3 3V i FI L E REF B I i i i H is REF C i i 2 5V i FI L E REF D i i Spartan 3E FPGA I sei wee JL i gt m PAD pac cs
124. fier AMP and two channel Analog to Digital Converter ADC The diagram in the lower left corner shows the JTAG chain See Chapter 15 Expansion Connectors for additional information 134 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 FX2 Expansion Header 6 pin Headers and Connectorless Probe Header SC XILINX 1 T1 199ys HU 4ouing 99 488urbu3 90 20 20 eieq 280 006 4914818 JES 31111 40128euuoj uorsuedx3j pue 9S041H 33HS seoz ggz 1brafidog Sul 1uSTIBIG p4eog 4914815 jg ueyseds fucose day 49peaH Uld 9 alno ILNO gino YLNO Japesy ScTI9Tv2 und 9IZIX IS JUSWUNJISUI sexa omg uo peo ON Sra19X Jesur Sv032X lt Od4 JES lt lt ureyg uens 9uif NO 10 W N OO peorunog asn SANO E C C N O LO NO N O O CN OO LO NO N O 9 C Q IO ND PN 00 00 2 WO XUTTIX JE NULtWUdS Dur sus Dra JE NYIUYdS NO ION N 0 UG230 Aa 01 021806 Schematic Sheet 1 Figure A 1 135 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Appendix A Schematics XILINX RS 232 Ports VGA Port and PS 2 Port 136 IC2 is the Maxim LVTTL to RS 232 level converter One of the serial channels connects to a female DB9 DCE connector J9 and the other connects to a male DB9 DTE connector J10 See Chapter 7 RS 232 Serial Ports for addi
125. file and how to download it to the board to ultimately program the FPGA Generating the FPGA Configuration Bitstream File Before generating the PROM file create the FPGA bitstream file The FPGA provides an output clock CCLK when loading itself from an external PROM The FPGA s internal CCLK oscillator always starts at its slowest setting approximately 1 5 MHz Most external PROMs support a higher frequency Increase the CCLK frequency as appropriate to reduce the FPGA s configuration time The Xilinx XCF045 Platform Flash supports a 25 MHz CCLK frequency Right click Generator Programming File in the Processes pane as shown in Figure 4 10 Left click Properties www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Programming the FPGA CPLD or Platform Flash PROM via USB Processes ER User Constraints E Pa Dy Synthesize XST H T Implement Design SB Generate Data E E Prograr 14 Bun lA Genera Rerun a Config SL Rerun all xi Stop SH Processes Oper Without Updating UG230_c4_11_022706 Figure 4 10 Set Properties for Bitstream Generator Click Configuration Options as shown in Figure 4 11 Using the Configuration Rate drop list choose 25 to increase the internal CCLK oscillator to approximately 25 MHz the fastest frequency when using an XCF04S Platform Flash PROM Click OK when finished Process Properties X Category General Options
126. forces the FPGA to restart its configuration process The 4 Mbit Xilinx Platform Flash PROM provides easy JTAG programmable configuration storage for the FPGA The FPGA configures from the Platform Flash using Master Serial mode The 64 macrocell XC2C64A CoolRunner II CPLD provides additional programming capabilities and flexibility when using the BPI Up BPI Down or MultiBoot configuration modes and loading the FPGA from the StrataFlash parallel Flash PROM The CPLD is user programmable Configuration Mode Jumpers As shown in Table 4 1 the J30 jumper block settings control the FPGA s configuration mode Inserting a jumper grounds the associated mode pin Insert or remove individual jumpers to select the FPGA s configuration mode and associated configuration memory source Table 4 1 Spartan 3E Configuration Mode Jumper Settings Header J30 in Figure 4 2 Configuration Mode Pins Mode M2 M1 MO FPGA Configuration Image Source Jumper Settings Master Serial 0 0 0 Platform Flash PROM SPI 1 1 0 SPI Serial Flash PROM starting at see address 0 Chapter 12 SPI Serial Flash BPI Up 0 1 0 StrataFlash parallel Flash PROM see starting at address 0 and Chapter 11 incrementing through address Intel space The CPLD controls address StrataFlash lines A 24 20 during BPI Parallel NOR configuration Flash PROM Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 27 UG230 v1 1 June 20
127. h DAC outputs A and B is 2 5V 5 D 11 0 Vourc 4096 2 5V 15 Equation 9 3 72 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX UCF Location Constraints UCF Location Constraints Figure 9 5 provides the UCF constraints for the DAC interface including the I O pin assignment and the I O standard used NET SPI MISO LOC N10 IOSTANDARD LVCMOS33 NET SPI MOSI LOC T4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET SPI SCK LOC U16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET DAC CS LOC N8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET DAC CLR LOC pg IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 Figure 9 5 UCF Location Constraints for the DAC Interface Related Resources e LTC2624 Quad DAC Data Sheet http www linear com pc downloadDocument do navId H0 C1 C1155 C1005 C1156 P2048 D2170 e PicoBlaze Based D A Converter Control for the Spartan 3E Starter Kit Reference Design http www xilinx com s3estarter e Xilinx PicoBlaze Soft Processor http www xilinx com picoblaze Digilent Inc Peripheral Modules http www digilentinc com Products Catalog cfm Nav1 Products amp Nav2 Peripheral amp Cat Peripheral Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 73 UG230 v1 1 June 20 2008 Chapter 9 Digital to Analog Converter DAC 74 www xilinx com Z XILINX
128. he StrataFlash PROM or the character LCD using the SF CEO and LCD RW signals Table 11 2 FPGA Control for StrataFlash and LCD SF CEO LCD RW Function 1 1 The FPGA reads from the character LCD 0 0 The FPGA accesses the StrataFlash PROM Xilinx XC2C64A CPLD The Xilinx XC2C64A CoolRunner II CPLD controls the five upper StrataFlash address lines SF A lt 24 20 gt during configuration The four upper BPI mode address lines from the FPGA A lt 23 20 gt are not connected Instead four FPGA user I O pins connect to the StrataFlash PROM upper address lines SF_A lt 23 0 gt See Chapter 16 XC2C64A CoolRunner II CPLD for more information The most significant address line SF_A lt 24 gt is not physically used on the 16 Mbyte StrataFlash PROM It is provided for upward migration to a larger StrataFlash PROM in the same package footprint Likewsie the SF_A lt 24 gt signal is also connected to the FX2 IO 32 signal on the FX2 expansion connector SPI Data Line The least significant StrataFlash data line SF D lt 0 gt is shared with data output signals from serial SPI peripherals SPI MISO and the serial output from the Platform Flash PROM as shown in Table 11 3 To avoid contention the FPGA application must ensure that only one data source is active at any time Table 11 3 Possible Contention on SPI MISO SF D lt 0 gt Data Condition Function FPGA M2 Low Platform Flash outputs
129. he clock period is 20 to 30 KHz Mouse status byte E X direction byte Y direction byte 1 ofi Rr of s psfyspavfyv 1 Lo bopapebepapspepe a Start bit Idle state 66 rer ur d Stop bit t Stop bit Stop bit Start bit Start bit Idle state UG230_c8_04_021806 Figure 8 4 PS 2 Mouse Transaction A PS 2 style mouse employs a relative coordinate system see Figure 8 5 wherein moving the mouse to the right generates a positive value in the X field and moving to the left generates a negative value Likewise moving the mouse up generates a positive value in the Y field and moving it down represents a negative value The XS and YS bits in the status byte define the sign of each value where a 1 indicates a negative value Y values YS 0 X values X values XS 1 XS 0 Y values YS 1 UG230_c8_05_021806 Figure 8 5 The Mouse Uses a Relative Coordinate System to Track Movement The magnitude of the X and Y values represent the rate of mouse movement The larger the value the faster the mouse is moving The XV and YV bits in the status byte indicate when the X or Y values exceed their maximum value an overflow condition A 1 indicates when an overflow occurs If the mouse moves continuously the 33 bit transmissions repeat every 50 ms or so The L and R fields in the status byte indicate Left and Right button presses A 1 indicates that the associated mouse button is bei
130. ignal contention with the FPGA ensure that the connecting FPGA pins are high impedance Force the FPGA s PROG B pin Low by installing a jumper on JP8 next to the PROG push button as shown in Figure 12 16 See Figure 12 3 page 93 to locate jumper JP8 and surrounding landmarks DEFAULT NO JUMPER y 3 e Gl tc Fu 30 SE L 2 wu gt ao z a No Jumper FPGA Operational default b Jumper Installed FPGA Held in Configuration State I Os in High Impedance UG230 c15 15 030206 Figure 12 16 Installing the JP8 Jumper Holds the FPGA in Configuration State Re apply power to the Spartan 3E Starter Kit board and program the SPI Flash 100 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Additional Design Details After programming the SPI Flash remove jumper JP8 as shown in Figure 12 16a If properly programmed the FPGA then configures itself from the SPI Flash PROM and the DONE LED lights The DONE LED is shown in Figure 12 3 Additional Design Details Figure 12 17 provides additional details of the SPI Flash interface used on the Spartan 3E Starter Kit board In most applications this interface is as simple as that shown in Figure 12 1 The Spartan 3E Starter Kit board however supports of variety of configuration options and demonstrates additional Spartan 3E FPGA capabilities STMicro M25P16 SE SPI Serial Flash MOSI CSI_
131. ilinx com 91 UG230 v1 1 June 20 2008 Chapter 12 SPI Serial Flash XILINX some connections shared with SPI Flash DAC ADC and AMP NET NET NET NET NET SPI MISO SPI MOSI SPI SCK SPI SS B SPI ALT CS LOC N10 IOSTANDARD LVCMOS33 LOC T4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 LOC U16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 LOC U3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 _JP11 LOC R12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 6 Figure 12 2 UCF Location Constraints for SPI Flash Connections 92 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Configuring from SPI Flash Configuring from SPI Flash To configure the FPGA from SPI Flash the FPGA mode select pins must be set appropriately and the SPI Flash must contain a valid configuration image Select SPI Mode using Jumper Settings Header J12 XSPI Programming Remove the top jumper insert the bottom two as shown Jumper J11 ST L 13 T I DONE Pin LED Lights up when FPGA successfully configured PROG_B Push Button Switch Jumper JP8 XSPI Press and release to restart configuration When programming SPI Flash using XSPI utility insert jumper to hold PROG B pin Low UG230 c15 02 030906 Figure 12 3 Configuration Options for SPI Mode Setting the FPGA Mode Select Pins Set the FPGA configuration
132. ions Character LED ada etse beso haan de senate ea erte Xilinx XC2C64A CPED uera EE nere A de eeu SPI AAA RR PER UCF Location Constraints Address Dita dd bits EG ad tt u ME M IT Ee URN Setting the FPGA Mode Select Pins Related Resources Chapter 12 SPI Serial Flash UCF Location Constraints Configuring from SPI Flash Setting the FPGA Mode Select Pins Creating an SPI Serial Flash PROM File Setting the Configuration Clock Rate Formatting an SPI Flash PROM File Downloading the Design to SPI Flash Downloading the SPI Flash Attach a JTAG Parallel Programming Cable Insert Jumper on JP8 and Hold PROG_B Low Additional Design Details Shared SPI Bus with Peripherals Other SPI Flash Control Signals Variant Select Pins VOZ Ola tnter ete de sn pen te allele eto aie Jumper Block JIT 2 2 nn
133. ious Set CG RAM Address command After the read operation the address is automatically incremented or decremented by 1 according to the Entry Mode Set command However a display shift is not executed during read operations Execution Time 40 us Operation Four Bit Data Interface The board uses a 4 bit data interface to the character LCD Figure 5 6 illustrates a write operation to the LCD showing the minimum times allowed for setup hold and enable pulse length relative to the 50 MHz clock 20 ns period provided on the board cons TIE AAA sona o LCD RW LCD E Upper Lower 4 bits 4 bits LCD R8 D SF D 11 8 D LCD RW a S ON Mo LEDE A A No 1 us 40 us L d UG230 c5 03 022006 Figure 5 6 Character LCD Interface Timing 52 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 3 XILINX Operation The data values on SF_D lt 11 8 gt and the register select LCD RS and the read write LCD RW control signals must be set up and stable at least 40 ns before the enable LCD E goes High The enable signal must remain High for 230 ns or longer the equivalent of 12 or more clock cycles at 50 MHz In many applications the LCD RW signal can be tied Low permanently because the FPGA generally has no reason to read information from the display Transferring 8 Bit Data over the 4 Bit Interface After initializing the display and establishing communication all commands
134. it Board User Guide UG230 v1 1 June 20 2008 XILINX Appendix A Schematics This appendix provides the following circuit board schematics FX2 Expansion Header 6 pin Headers and Connectorless Probe Header RS 232 Ports VGA Port and PS 2 Port Ethernet PHY Magnetics and RJ 11 Connector Voltage Regulators FPGA Configurations Settings Platform Flash PROM SPI Serial Flash JTAG Connections FPGA I O Banks 0 and 1 Oscillators FPGA I O Banks 2 and 3 Power Supply Decoupling XC2C64A CoolRunner II CPLD Linear Technology ADC and DAC Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM Buttons Switches Rotary Encoder and Character LCD DDR SDRAM Series Termination and FX2 Connector Differential Termination Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 133 UG230 v1 1 June 20 2008 Appendix A Schematics A XILINX FX2 Expansion Header 6 pin Headers and Connectorless Probe Header Headers J1 J2 and J4 are six pin connectors compatible with the Digilent Accessory board format Headers J3A and J3B are the connections to the FX2 expansion connector located along the right edge of the board Header J5 provides the four analog outputs from the Digital to Analog Converter DAC Header J6 is the landing pad for an Agilent or Tektronix connectorless probe Header J7 provides the two analog inputs to the programmable pre ampli
135. le NET CLK 50MHZ PERIOD 20 0ns HIGH 40 NET CLK AUX LOC Be IOSTANDARD LVCMOS33 NET CLK SMA LOC A10 IOSTANDARD LVCMOS33 Digital to Analog Converter DAC some connections shared with SPI Flash DAC ADC and AMP NET DAC CLR LOC P8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET DAC CS LOC N8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 d 1 Wire Secure EEPROM DS NET DS_ WIRE LOC U4 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 Ethernet PHY E NET E COL LOC U6 IOSTANDARD LVCMOS33 NET E CRS LOC U13 IOSTANDARD LVCMOS33 NET E MDC LOC P9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 161 UG230 v1 1 June 20 2008 Appendix B Example User Constraints File UCF Z XILINX 162 NET E MDIO LOC Us IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 NET E RX CLK LOC V3 IOSTANDARD LVCMOS33 NET E RX DV LOC V2 IOSTANDARD LVCMOS33 NET E RXD lt 0 gt LOC V8 IOSTANDARD LVCMOS33 NET E RXD lt 1 gt LOC T11 IOSTANDARD LVCMOS33 NET E RXD lt 2 gt LOC U11 IOSTANDARD LVCMOS33 NET E RXD lt 3 gt LOC V14 IOSTANDARD LVCMOS33 NET E RXD lt 4 gt LOC U14 IOSTANDARD LVCMOS33 NET E TX CL
136. loped by Texas Instruments the TPS75003 specifically to power Spartan 3 and Spartan 3E FPGAs This regulator is sufficient for most stand alone FPGA applications However the starter kit board includes DDR SDRAM which requires its own high current supply Similarly the USB based JTAG download solution requires a separate 1 8V supply Related Resources e Xilinx MicroBlaze Soft Processor http www xilinx com microblaze e Xilinx PicoBlaze Soft Processor http www xilinx com picoblaze e Xilinx Embedded Development Kit http www xilinx com ise embedded design prod platform studio htm e Xilinx software tutorials http www xilinx com support techsup tutorials e Texas Instruments TPS75003 http focus ti com docs prod folders print tps75003 html Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 13 UG230 v1 1 June 20 2008 Chapter 1 Introduction and Overview 14 www xilinx com Z XILINX Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 7 XILINX Chapter 2 Switches Buttons and Knob Slide Switches Locations and Labels The Spartan 3E FPGA Starter Kit board has four slide switches as shown in Figure 2 1 The slide switches are located in the lower right corner of the board and are labeled SW3 through SWO Switch SW3 is the left most switch and SWO is the right most switch HIGH LOW SW3 SW2 SW1 SWO N17 H18 L14 L13 UG230
137. ltage supply The gain of each amplifier is programmable from 1 to 100 as shown in Table 10 2 Table 10 2 Programmable Gain Settings for Pre Amplifier A3 A2 A1 A0 Input Voltage Range TM B3 B2 B1 BO Minimum Maximum 0 0 0 0 0 1 0 0 0 1 0 4 2 9 2 0 0 1 0 1 025 2 275 Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 77 UG230 v1 1 June 20 2008 Chapter 10 Analog Capture Circuit Table 10 2 Programmable Gain Settings for Pre Amplifier Continued Z XILINX A3 A2 A1 A0 Input Voltage Range one B3 B2 B1 BO Minimum Maximum 5 0 0 1 1 14 1 9 10 0 1 0 0 1 525 1 775 20 0 1 0 1 1 5875 1 7125 50 0 1 1 0 1 625 1 675 100 0 1 1 1 1 6375 1 6625 SPI Control Interface Figure 10 3 highlights the SPI based communications interface with the amplifier The gain for each amplifier is sent as an 8 bit command word consisting of two 4 bit fields The most significant bit B3 is sent first AMP_DOUT o Slave LTC2624 1 Ao A Ae As Bo Bi Be Bo I I I A Gain B Gain SPI MOSI Spartan 3E AMP CS d FPGA SPI SCK Master UG230 c10 03 030306 Figure 10 3 SPI Serial Interface to Amplifier The AMP DOUT output from the amplifier echoes the previous gain settings These values can be ignored for most applications The SPI bus transaction starts when the FPGA asserts AMP CS Low see Figur
138. mode pins for SPI mode as shown in Figure 12 4 The location of the configuration mode jumpers J30 appears in Figure 12 3 UG230 c15 03 030206 Figure 12 4 Set Mode Pins for SPI Mode Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 93 UG230 v1 1 June 20 2008 Chapter 12 SPI Serial Flash ZT XILINX Creating an SPI Serial Flash PROM File The following steps describe how to format an FPGA bitstream for an SPI Serial Flash PROM Setting the Configuration Clock Rate The FPGA supports a 12 MHz configuration clock rate when connected to an M25P16 SPI serial Flash Set the Properties for Generate Programming File so that the Configuration Rate is 12 as shown in Figure 12 5 See Generating the FPGA Configuration Bitstream File in the FPGA Configuration Options chapter fora more detailed description Regenerate the FPGA bitstream programming file with the new settings E Process Properties E Category t General Options r Configuration Options Startup Options Readback Options BH Configuration Rate 2 y Configuration Clk Configuration Pins Default 1 Configuration Pin MO 12 Configuration Pin M1 Configuration Pin M2 Configuration Pin Program Configuration Pin Done JTAG Pin TCK Property display level Standard v Default Z UG230_c15_04_030206 Figure 12 5 Set Configuration Rate to 12 MHz When Using the M25P16 SPI Flash 94 www xilinx com
139. nformation on converting the voltage applied on VINA or VINB to a digital representation see Related Resources page 81 Programmable Pre Amplifier Interface The LTC6912 1 provides two independent inverting amplifiers with programmable gain The purpose of the amplifier is to scale the incoming voltage on VINA or VINB so that it maximizes the conversion range of the DAC namely 1 65 1 25V Table 10 1 lists the interface signals between the FPGA and the amplifier The SPI MOSI SPI MISO and SPI SCK signals are shared with other devices on the SPI bus The AMP CS signal is the active Low slave select input to the amplifier Table 10 1 AMP Interface Signals Signal FPGA Pin Direction Description SPI MOSI T4 FPGA gt AD Serial data Master Output Slave Input Presents 8 bit programmable gain settings as defined in Table 10 2 AMP CS N7 FPGA gt AMP Active Low chip select The amplifier gain is set when signal returns High SPI SCK U16 FPGA gt AMP Clock AMP_SHDN P7 FPGA gt AMP Active High shutdown reset AMP_DOUT E18 FPGA AMP Serial data Echoes previous amplifier gain settings Can be ignored in most applications Programmable Gain Each analog channel has an associated programmable gain amplifier see Figure 10 2 Analog signals presented on the VINA or VINB inputs on header J7 are amplified relative to 1 65V The 1 65V reference is generated using a voltage divider of the 3 3V vo
140. ng pressed www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Voltage Supply Voltage Supply The PS 2 port on the Spartan 3E FPGA Starter Kit board is powered by 5V Although the Spartan 3E FPGA is not a 5V tolerant device it can communicate with a 5V device using series current limiting resistors as shown in Figure 8 1 UCF Location Constraints Figure 8 6 provides the UCF constraints for the PS 2 port connecting including the I O pin assignment and the I O standard used NET PS2 CLK LOC G14 IOSTANDARD NET PS2 DATA LOC G13 IOSTANDARD LVCMOS33 DRIVE LVCMOS33 DRIVE 8 SLEW 8 SLEW Figure 8 6 UCF Location Constraints for PS 2 Port Related Resources e D5 2 Mouse Keyboard Protocol http www computer engineering org ps2protocol e PS 2 Keyboard Interface http www computer engineering org ps2keyboard e PS 2 Mouse Interface http www computer engineering org ps2mouse Spartan 3E FPGA Starter Kit Board User Guide www xilinx com UG230 v1 1 June 20 2008 SLOW SLOW 67 Chapter 8 PS 2 Mouse Keyboard Port 68 www xilinx com Z XILINX Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Chapter 9 Digital to Analog Converter DAC The Spartan 3E FPGA Starter Kit board includes an SPI compatible four channel serial Digital to Analog Converter DAC The DAC d
141. nnections are shared with the J2 6 pin NET FX2 IO lt 5 gt LOC A6 IOSTANDARD LVCMOS33 SLEW NET FX2 IO 6 LOC B6 IOSTANDARD LVCMOS33 SLEW NET FX2 IO 7 LOC E7 IOSTANDARD LVCMOS33 SLEW NET FX2 IO 8 LOC F7 IOSTANDARD LVCMOS33 SLEW These four connections are shared with the J4 6 pin NET FX2 IO lt 9 gt LOC D7 IOSTANDARD LVCMOS33 SLEW NET FX2 IO 10 LOC C7 IOSTANDARD LVCMOS33 SLEW NET FX2 IO 11 LOC F8 IOSTANDARD LVCMOS33 SLEW NET FX2 IO lt 12 gt LOC E8 IOSTANDARD LVCMOS33 SLEW The discrete LEDs are shared with the following 8 FX2 conne NET FX2 IO 13 LOC F9 IOSTANDARD LVCMOS33 SLEW NET FX2 IO lt 14 gt LOC E9 IOSTANDARD LVCMOS33 SLEW NET FX2 IO lt 15 gt LOC D11 IOSTANDARD LVCMOS33 SLEW NET FX2 IO lt 16 gt LOC C11 IOSTANDARD LVCMOS33 SLEW NET FX2 IO lt 17 gt LOC F11 IOSTANDARD LVCMOS33 SLEW NET FX2 IO lt 18 gt LOC E11 IOSTANDARD LVCMOS33 SLEW HNET FX2 IO lt 19 gt LOC E12 IOSTANDARD LVCMOS33 SLEW NET FX2 IO lt 20 gt LOC F12 IOSTANDARD LVCMOS33 SLEW NET FX2 IO lt 21 gt LOC A13 IOSTANDARD LVCMOS33 SLEW NET FX2 10 lt 22 gt LOC B13 IOSTANDARD LVCMOS33 SLEW NET FX2 10 lt 23 gt LOC A14 IOSTANDARD LVCMOS33 SLEW NET FX2 IO 24 LOC B14 IOSTANDARD LVCMOS33 SLEW NET FX2 10 lt 25 gt LOC C14 IOSTANDARD LVCMOS33 SLEW NET FX2 10 lt 2
142. ns from various VGA displays The front and back porch intervals are the pre and post sync pulse times Information cannot be displayed during these times Table 6 2 640x480 Mode VGA Timing Vertical Sync Horizontal Sync Symbol Parameter Time Clocks Lines Time Clocks Ts Sync pulse time 16 7ms 416 800 521 32 us 800 Tpisp_ Display time 15 36 ms 384 000 480 25 6 us 640 Tpw Pulse width 64 us 1 600 2 3 84 us 96 Trp Front porch 320 us 8 000 10 640 ns 16 Tgp Back porch 928 us 23 200 29 1 92 us 48 gt l m 1 cx eed T isp E uii I I HT I Tow RP UG230 c6 03 021706 Figure 6 3 VGA Control Timing Generally a counter clocked by the pixel clock controls the horizontal timing Decoded counter values generate the HS signal This counter tracks the current pixel display location on a given row A separate counter tracks the vertical timing The vertical sync counter increments with each HS pulse and decoded values generate the VS signal This counter tracks the current display row These two continuously running counters form the address into a video display buffer For example the on board DDR SDRAM provides an ideal display buffer No time relationship is specified between the onset of the HS pulse and the onset of the VS pulse Consequently the counters can be arranged to easily form video RAM addresses or to minimize decoding logic for sync pulse gen
143. nsion connectors Four output SPI based Digital to Analog Converter DAC Two input SPI based Analog to Digital Converter ADC with programmable gain pre amplifier ChipScope SoftTouch debugging port Rotary encoder with push button shaft Eight discrete LEDs Four slide switches Four push button switches SMA clock input 8 pin DIP socket for auxiliary clock oscillator www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Design Trade Offs Design Trade Offs A few system level design trade offs were required in order to provide the Spartan 3E Starter Kit board with the most functionality Configuration Methods Galore A typical FPGA application uses a single non volatile memory to store configuration images To demonstrate new Spartan 3E FPGA capabilities the starter kit board has three different configuration memory sources that all need to function well together The extra configuration functions make the starter kit board more complex than typical Spartan 3E FPGA applications The starter kit board also includes an on board USB based JTAG programming interface The on chip circuitry simplifies the device programming experience In typical applications the JTAG programming hardware resides off board or in a separate programming module such as the Xilinx Platform USB cable Voltages for all Applications The Spartan 3E Starter Kit board showcases a triple output regulator deve
144. ntial OM TTT 118 Using Differential Inputs ep uk n a NEEN STEEN EEN el ei 120 Using Differential Outputs ss eese enean nn 121 UCF Location Constraints 121 Six Pin Accessory Headers 5 esassss rere re ke oe Pe ERR AUR dekken 123 Header TL 123 Hue berre sd 123 Header REM RETRO ETT 124 UCF Location Constraints 124 Connectorless Debugging Port Landing Pads J6 125 Related Resources 126 Chapter 16 XC2C64A CoolRunner ll CPLD UCF Location Constraints 129 FPGA Connections to CPLD 129 CPED POMPEII 129 Related Resources 130 Chapter 17 DS2432 1 Wire SHA 1 EEPROM UCF Location Constraints 131 Related Resources 131 Appendix A Schematics FX2 Expansion Header 6 pin Headers and Connectorless Probe Header 134 RS 232 Ports VGA Port and PS 2 Port 136 Ethernet PHY Magnetics and RJ 11 Connector eee 138 Voltage Regulators i iii ci ERE lenin bead debe dE ds 140 FPGA Configurations Settings Platform Flash PROM SPI Serial Flash JTAG on qn e
145. ocket Four FPGA pins connect to the J2 header FX2_IO lt 8 5 gt These four signals are also shared with the Hirose FX2 connector The board supplies 3 3V to the accessory board mounted in the J2 socket on the bottom pin Spartan 3E FPGA UG230_c12_08_022406 Figure 15 9 FPGA Connections to the J2 Accessory Header Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 123 UG230 v1 1 June 20 2008 Chapter 15 Expansion Connectors XILINX Header J4 The J4 header shown in Figure 15 10 is located immediately to the left of the J1 header It uses a 6 pin header consisting of 0 1 inch centered stake pins Four FPGA pins connect to the J4 header FX2_IO lt 12 9 gt These four signals are also shared with the Hirose FX2 connector The board supplies 3 3V to the accessory board mounted in the J4 socket on the bottom pin Spartan 3E FPGA UG230 c12 09 022406 Figure 15 10 FPGA Connections to the J4 Accessory Header UCF Location Constraints Figure 15 11 provides the User Constraint File UCF constraints for accessory headers including the I O pin assignment and the I O standard used These header connections are shared with the FX2 connector as shown in Figure 15 7 page 122 6 pin header Jl These four connections are shared with the FX2 connector HNET Jl lt 0 gt LOC B4 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 HNET Jl lt l gt L
146. ost only when both the data and clock lines are High the Idle state Because the host is the bus master the keyboard checks whether the host is sending data before driving the bus The clock line can be used as a clear to send signal If the host pulls the clock line Low the keyboard must not send any data until the clock is released The keyboard sends data to the host in 11 bit words that contain a 0 start bit followed by eight bits of scan code LSB first followed by an odd parity bit and terminated with a 1 stop bit When the keyboard sends data it generates 11 clock transitions at around 20 to 30 kHz and data is valid on the falling edge of the clock as shown in Figure 8 2 Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 65 UG230 v1 1 June 20 2008 Chapter 8 PS 2 Mouse Keyboard Port XILINX Mouse A mouse generates a clock and data signal when moved otherwise these signals remain High indicating the Idle state Each time the mouse is moved the mouse sends three 11 bit words to the host Each of the 11 bit words contains a 0 start bit followed by 8 data bits LSB first followed by an odd parity bit and terminated with a 1 stop bit Each data transmission contains 33 total bits where bits 0 11 and 22 are 0 start bits and bits 10 21 and 32 are 1 stop bits The three 8 bit data fields contain movement data as shown in Figure 8 4 Data is valid at the falling edge of the clock and t
147. ower decoupling network Jumper JP9 defines the voltage applied to VCCO on I O Bank 0 The default setting is 3 3V See Voltage Control page 22 and Voltage Supplies to the Connector page 116 for additional details 148 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 149 v 1 6 199us 90 20 20 e1ieQ 280 008 4200 NUS 40uing buridnossq 4emod 3SEDX 133HS 99 Lee Du 9eaz gaaz wridog 201 1U81161Q p4eog 491413 JE ue 4eds UG230 Aa 08 021806 Power Supply Decoupling uMd 191 1NI39N 1NI39N anar anal Ml aur aur aur aur aur aur aut Auer Lek Lek suizo NON DF LATA EN TTA OR Tap n TS 139913 aa TS Toles Tse er 1N1393 HEEN o 1NI39N xnvaan xnvaan lt anar anal Ml aut aur aur aur aur aur aut suzy Lek Lek suizo XNYDIN o 2ato 9619 sapane nenen nn 2 T9 P T2 8 TO T9 Z 9 XNYDIN t 6 xnu33n o XNYDIN x 3024 8 Leds uqa Z 5 o z N z 1 4724 Q lt ozi 3 D LLC O G E aN9 Md 129198 J3mod O I Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Appendix A Schematics XILINX XC2C64A CoolRunner ll CPLD 150 IC18 is a Xilinx XC2C64A CoolRunner II CPLD The CPLD primarily provides additional flexibility when configuring the FPGA from parallel NOR Flash and during MultiBoot configurations When the CPLD is loaded with the appropriate design JP10 enables
148. pin assignment and the I O standard used and defines a pull down resistor on each input NET BTN EAST LOC H13 IOSTANDARD LVTTL PULLDOWN NET BTN NORTH LOC V4 IOSTANDARD LVTTL PULLDOWN NET BTN SOUTH LOC K17 IOSTANDARD LVTTL PULLDOWN NET BTN WEST LOC D18 IOSTANDARD LVTTL PULLDOWN Figure 2 5 UCF Constraints for Push Button Switches Rotary Push Button Switch Locations and Labels The rotary push button switch is located in the center of the four individual push button switches as shown in Figure 2 3 The switch produces three outputs The two shaft encoder outputs are ROT A and ROT B The center push button switch is ROT CENTER Operation The rotary push button switch integrates two different functions The switch shaft rotates and outputs values whenever the shaft turns The shaft can also be pressed acting as a push button switch Push Button Switch Pressing the knob on the rotary push button switch connects the associated FPGA pin to 3 3V as shown in Figure 2 6 Use an internal pull down resistor within the FPGA pin to generate a logic Low Figure 2 9 shows how to specify a pull down resistor within the UCE There is no active debouncing circuitry on the push button Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 17 UG230 v1 1 June 20 2008 Chapter 2 Switches Buttons and Knob XILINX 18 Rotary Push Button 7 FPGA I O Pin 3 3V Ls R
149. pper and Lower data strobes SD_LDQS L6 SD_CK_FB B9 SDRAM clock feedback into top DCM within FPGA Used by some DDR SDRAM controller cores Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 www xilinx com 107 Chapter 13 DDR SDRAM Z XILINX UCF Location Constraints Address Data Figure 13 2 provides the User Constraint File UCF constraints for the DDR SDRAM address pins including the I O pin assignment and the I O standard used NET NET NET NET NET NET NET NET NET NET NET NET NET SD A lt 12 gt SD A lt 11 gt SD_A lt 10 gt SD_A lt 9 gt SD_A lt 8 gt SD_A lt 7 gt SD_A lt 6 gt SD_A lt 5 gt SD_A lt 4 gt SD_A lt 3 gt SD_A lt 2 gt SD_A lt 1 gt SD_A lt 0 gt LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC P2 n N5 n T2 n NA n H2 n H1 n H3 n HA n F4 n P1 n R2 n R3 n T1 n IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD SSTL2 SSTL2 SSTL2 SSTL2 SSTL2 SSTL2 SSTL2 SSTL2 SSTL2 SSTL2 SSTL2 SSTL2 SSTL2 I Hi HHH H H H H H H Figure 13 2 UCF Location Constraints for DDR SDRAM Address Inputs Figure 13 3 provides the User Constraint File UCF constraints for the DDR SDRAM data pins including the I O pin assignment and I O standard used N
150. pports an 8 bit data interface the Starter Kit board uses a 4 bit data interface to remain compatible with other Xilinx development boards and to minimize total pin count Spartan 3E FPGA Character LCD SF D lt 11 gt 3 SF D lt 10 gt SF_D lt 9 gt SF_D lt 8 gt DB7 DB6 Four bit data DBS interface DB4 His DB 3 0 Unused E Intel StrataFlash UG230 c5 01 022006 Figure 5 1 Character LCD Interface Once mastered the LCD is a practical way to display a variety of information using standard ASCII and custom characters However these displays are not fast Scrolling the display at half second intervals tests the practical limit for clarity Compared with the 50 MHz clock available on the board the display is slow A PicoBlaze processor efficiently controls display timing plus the actual content of the display Spartan 3E FPGA Starter Kit Board User Guide www xilinx com UG230 v1 1 June 20 2008 43 Chapter 5 Character LCD Screen XILINX Character LCD Interface Signals Table 5 1 shows the interface character LCD interface signals Table 5 1 Character LCD Interface Signal Name FPGA Pin Function SF_D lt 11 gt M15 Data bit DB7 Shared with StrataFlash pins SF_D lt 10 gt P17 Data bit DB6 SF_D lt 11 8 gt SF_D lt 9 gt R16 Data bit DB5 SF_D lt 8 gt R15 Data bit DB4 LCD E M18 Read Write Enable Pulse 0 Disabled 1 Read Write operation enabled LCD_
151. r Kit Board User Guide UG230 v1 1 June 20 2008 Y 1 11 118345 90 20 20 een 88 888 900 VAD 14Ouing Sj8149 u03 U Pue Dou 133HS 32 2 urbu3 9002 Geez iubi4hdoj gt u 1uSTI IO peog 4914813 JE ue 4eds Linear Technology ADC and DAC vc92211 cuTeyd jo pus ie aeld uotieutu AS ulu A ul uN ONDY lt DNOO 8NI gino UNIn uno NOHS 0 1 S3 ATI lt aS 00S 108 1dS SC XILINX 0S 00S 108 IdS 1H9 ANOD 1H2 ES OOS HJ HJ S aaan ANT 4N 7 9S ods Ids 1dS UG230_Aa_10_021806 Schematic Sheet 11 Figure A 10 153 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Appendix A Schematics A XILINX Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM 154 IC22 is a 128 Mbit 16 Mbyte Intel StrataFlash parallel NOR Flash PROM See Chapter 11 Intel StrataFlash Parallel NOR Flash PROM for additional information IC23 is a 512 Mbit 64 Mbyte Micron DDR SDRAM See Chapter 13 DDR SDRAM for additional information www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM SC XILINX 1 Z1 1989y5S VUS 40uing 99 4 urbu3 90 20 20 opt 280 006 4914818 JES UI usepjeie4is pue U990S 900 133HS seez geez iubr4fhdoj Sur 1uSTI IO p4eog 41914818 Je ue 4eds 9Gd0S1 Er
152. re are 80 total character locations in DD RAM with 40 characters available per line Locations 0x10 through 0x27 and 0x50 through 0x67 can be used to store other non display data Alternatively these locations can also store characters that can only displayed using controller s display shifting functions The Set DD RAM Address command initializes the address counter before reading or writing to DD RAM Write DD RAM data using the Write Data to CG RAM or DD RAM command and read DD RAM using the Read Data from CG RAM or DD RAM command The DD RAM address counter either remains constant after read or write operations or auto increments or auto decrements by one location as defined by the I D set by the Entry Mode Set command CG ROM The Character Generator ROM CG ROM contains the font bitmap for each of the predefined characters that the LCD screen can display shown in Figure 5 4 The character code stored in DD RAM for each character location subsequently references a position with the CG ROM For example a hexadecimal character code of 0x53 stored in a DD RAM location displays the character S The upper nibble of 0x53 equates to DB 7 4 0101 binary and the lower nibble equates to DB 3 0 0011 binary As shown in Figure 5 4 the character S appears on the screen English Roman characters are stored in CG ROM at their equivalent ASCII code address www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1
153. s provided as an example of how the FPGA might drive VGA monitor in 640 by 480 mode For more precise information or for information on higher VGA frequencies refer to documents available on the VESA website or other electronics websites see Related Resources page 59 Signal Timing for a 60 Hz 640x480 VGA Display CRT based VGA displays use amplitude modulated moving electron beams or cathode rays to display information on a phosphor coated screen LCDs use an array of switches that can impose a voltage across a small amount of liquid crystal thereby changing light permittivity through the crystal on a pixel by pixel basis Although the following description is limited to CRT displays LCDs have evolved to use the same signal timings as CRT displays Consequently the following discussion pertains to both CRTs and LCDs Within a CRT display current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a raster pattern horizontally from left to right and vertically from top to bottom As shown in Figure 6 2 information is only displayed when the beam is moving in the forward direction left to right and top to bottom and not during the time the beam returns back to the left or top edge of the display Much of the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass
154. s5t iMPACT Modes toplevel Get Device ID Xl pue Operations are my Program UG230_c4_09_022406 Figure 4 8 Right Click to Program the Spartan 3E FPGA TDO Get Device Signature Usercode Assign New Configuration File When the FPGA successfully programs the iMPACT software indicates success as shown in Figure 4 9 The FPGA application is now executing on the board and the DONE pin LED see Figure 4 2 lights up Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 31 UG230 v1 1 June 20 2008 Chapter 4 FPGA Configuration Options XILINX iMPACT C data my designs s3e starter kit s3e starter kit ipf Boundary Scan S File Edit View Operations Options Output Debug Window Help IP H 3 x eo 1 s E BA Boundary Scan B ISlaveS erial i aalSelectMAP B IDesktop Configu E SystemACE iMPACT Modes TO El xc3s500e xcf 4s xc2c64a toplevel bit file file TDO Available Operations are Program Verify gt Get Device ID Get Device Signatur Check Idcode UG230 c4 10 022406 Figure 4 9 iMPACT Programming Succeeded the FPGA s DONE Pin is High Programming Platform Flash PROM via USB The on board USB JTAG circuitry also programs the Xilinx XCF045 serial Platform Flash PROM The steps provided in this section describe how to set up the PROM
155. ssume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design THE DESIGN IS PROVIDED AS IS WITH ALL FAULTS AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE WHETHER GIVEN BY XILINX OR ITS AGENTS OR EMPLOYEES XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DESIGN INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES THE TOTAL CUMULATIVE LIABILITY OF XILINX INCONNECTION WITH YOUR USE OF THE DESIGN WHETHER IN CONTRACT OR TORT OR OTHERWISE WILL INNO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN YOU ACKNOWLEDGE THAT THE FEES IF ANY REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY The Design is not designed or intended for use in the development of on line control equipment in hazardous environments requiring fail safe
156. t NET SF A lt 24 gt LOC P23 IOSTANDAR NET SF A lt 23 gt LOC p22 IOSTANDAR NET SF A lt 22 gt LOC P21 IOSTANDAR NET SF A lt 21 gt LOC P20 IOSTANDAR NET SF A lt 20 gt LOC P19 IOSTANDAR woe we eo oe eee Oo Oo k eS LI UU M LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 i SLEN SLEN SLEN SLEN SLEN SLEN SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW Figure 16 3 UCF Location Constraints for the XC2C64A CPLD Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 www xilinx com 129 Chapter 16 XC2C64A CoolRunner Il CPLD XILINX Related Resources e CoolRunner II CPLD Family Data Sheet http www xilinx com support documentation data sheets ds090 pdf e XC2C64A CoolRunner I CPLD Data Sheet http www xilinx com support documentation data sheets ds311 pdf e Default XC2C64A CPLD Design for Spartan 3E Starter Kit Board http www xilinx com s3estarter 130 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 2 XILINX Chapter 17
157. t Boards The Spartan 3E Starter Kit board demonstrates the basic capabilities of the MicroBlaze embedded processor and the Xilinx Embedded Development Kit EDK For more advanced development consider the capable boards offered by Xilinx partners e Spartan 3 Generation Board Interactive Search http www xilinx com products devboards index htm Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 11 UG230 v1 1 June 20 2008 Chapter 1 Introduction and Overview XILINX Key Components and Features The key features of the Spartan 3E Starter Kit board are 12 Xilinx XC3S500E Spartan 3E FPGA Up to 232 user I O pins 320 pin FBGA package Over 10 000 logic cells Xilinx 4 Mbit Platform Flash configuration PROM Xilinx 64 macrocell XC2C64A CoolRunner CPLD 64 MByte 512 Mbit of DDR SDRAM x16 data interface 100 MHz 16 MByte 128 Mbit of parallel NOR Flash Intel StrataFlash FPGA configuration storage MicroBlaze code storage shadowing 16 Mbits of SPI serial Flash STMicro FPGA configuration storage MicroBlaze code shadowing 2 line 16 character LCD screen PS 2 mouse or keyboard port VGA display port 10 100 Ethernet PHY requires Ethernet MAC in FPGA Two 9 pin RS 232 ports DTE and DCE style On board USB based FPGA CPLD download debug interface 50 MHz clock oscillator SHA 1 1 wire serial EEPROM for bitstream copy protection Hirose FX2 expansion connector Three Digilent 6 pin expa
158. t together as shown in Figure 7 1 Similarly the port s RTS and CTS signals connect together UCF Location Constraints Figure 7 2 and Figure 7 3 provide the UCF constraints for the DTE and DCE RS 232 ports respectively including the I O pin assignment and the I O standard used NET RS232 DTE RXD LOC U8 IOSTANDARD LVTTL NET RS232 DTE TXD LOC M13 IOSTANDARD LVTTL DRIVE 8 SLEW SLOW Figure 7 2 UCF Location Constraints for DTE RS 232 Serial Port NET RS232 DCE RXD LOC R7 IOSTANDARD LVTTL NET RS232 DCE TXD LOC M14 IOSTANDARD LVTTL DRIVE 8 SLEW SLOW Figure 7 3 UCF Location Constraints for DCE RS 232 Serial Port 62 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Chapter 8 PS 2 MouselKeyboard Port The Spartan 3E FPGA Starter Kit board includes a PS 2 mouse keyboard port and the standard 6 pin mini DIN connector labeled J14 on the board Figure 8 1 shows the PS 2 connector and Table 8 1 shows the signals on the connector Only pins 1 and 5 of the connector attach to the FPGA 2700 PS2 DATA G13 2700 PS2 CLK G14 UG230 c8 01 021806 Figure 8 1 PS 2 Connector Location and Signals Table 8 1 PS 2 Connector Pinout PS 2 DIN Pin Signal FPGA Pin 1 DATA PS2 DATA G13 2 Reserved G13 3 4 5 CLK PS2_CLK 6 Reserved Both a PC mouse and keyboard use the two wire P
159. ter selecting the last FPGA file Finally click OK to continue Add Device d Adding device File to the SPI PROM UG230 c15 10 030206 Figure 12 11 Enter FPGA Configuration Bitstream File s When PROM formatting is complete the iMPACT software presents the present settings by showing the PROM the select FPGA bitstream s and the amount of PROM space consumed by the bitstream Figure 12 12 shows an example for a single XC3S500E FPGA bitstream stored in an XCFO4S Platform Flash PROM Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 97 UG230 v1 1 June 20 2008 Chapter 12 SPI Serial Flash ZT XILINX 15M 13 53 Full xe3s5 e mytfpgabitstream UG230 c15 11 030206 Figure 12 12 PROM Formatting Completed To generate the actual PROM file click Operations gt Generate File as shown in Figure 12 13 iMPACT C data my designs s3e starter kit s3e zb File Edit view Operations Options Output Debug 22 Program GS Verify fl Erase Compact Flash Integrity Check UG230_c15_12_030206 Figure 12 13 Click Operations gt Generate File to Create the Formatted PROM File As shown in Figure 12 14 the iMPACT software indicates that the PROM file was successfully created The PROM Formatter creates an output file based on the settings shown in Figure 12 8 In this example the output file is called MySPIFlash mcs 16M 13 53 Full xc3s5 e myfpgabitstream PROM File
160. tional information Connector J14 is a PS 2 style mouse keyboard connector powered from 5 volts See Chapter 8 PS 2 Mouse Keyboard Port for additional information Connector J15 is a VGA connector suitable for driving most VGA compatible monitors and flat screen displays See Chapter 6 VGA Display Port for additional information Header J12 provides programming support for the SPI serial Flash Jumper J11 controls how the SPI serial Flash is enabled in the application See Chapter 12 SPI Serial Flash for additional information The SMA connector allows an external clock source to drive one of the FPGA s global clock inputs Alternatively the FPGA can provide a high performance clock to another board via the SMA connector See Chapter 3 Clock Sources for additional information www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 RS 232 Ports VGA Port and PS 2 Port SC XILINX bI Z 19SYS5 90 20 20 QW 40uing 29 48eurbu3 H aN wt 0 680 110 SIEN 9002 56160 280 0085 4914818 FES 371111 NI IerIe4ed pue zsd YON ZEZSY 133HS agoz iubr4fdo5 Duy 1US TIBIO p4eog 4911819 Je ue Jeds NO 19 0 N OO 440d BON NM 19 0 N 680 2305 2Teus y 4NT 99 3NT 0 ER 0400000 wt wet wt 549018 ebea 01g 1s8 puno49 011 z011 3809 uo peo ON 38091 uo peo 06000000000000000 NO X OW
161. tor available on most personal computers and workstations via a standard straight through serial cable Null modem gender changers or crossover cables are not required Use the DTE style connector to control other RS 232 peripherals such as modems or printers or perform simple loopback testing with the DCE connector Note that Figure 7 1 shows the view looking out the DTE connector Standard Standard 9 pin serial cable 9 pin serial cable TALK DATA DB9 Serial Port Connector front view DTE Male DB9 MW RS232_DCE_TXD ANN RS232 DCE RXD RS232 DTE TXD RS232 DTE RXD R7 M14 M13 U8 Spartan 3E FPGA UG230_c7_01_062008 Figure 7 1 RS 232 Serial Ports Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 61 UG230 v1 1 June 20 2008 Chapter 7 RS 232 Serial Ports XILINX Figure 7 1 shows the connection between the FPGA and the two DB9 connectors The FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim device which in turn converts the logic value to the appropriate RS 232 voltage level Likewise the Maxim device converts the RS 232 serial input data to LVITL levels for the FPGA A series resistor between the Maxim output pin and the FPGA s RXD pin protects against accidental logic conflicts Hardware flow control is not supported on the connector The ports DCD DTR and DSR signals connec
162. trataFlash PROM is a parallel device its least significant data bit is shared with the SPI MISO signal 70 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX SPI Communication Table 9 2 Disabled Devices on the SPI Bus Signal Disabled Device Disable Value SPI SS B SPI serial Flash 1 AMP CS Programmable pre amplifier 1 AD CONV Analog to Digital Converter ADC 0 SF CEO StrataFlash Parallel Flash PROM 1 FPGA INIT B Platform Flash PROM 1 SPI Communication Details Figure 9 3 shows a detailed example of the SPI bus timing Each bit is transmitted or received relative to the SPI SCK clock signal The bus is fully static and supports clocks rate up to the maximum of 50 MHz However check all timing parameters using the LTC2624 data sheet if operating at or close to the maximum speed DAC CS N se nos CS YID NC XR SPI SCK _ J A f U7 Y SPI_MISO Previous 31 U Previous 30 MU Previous 29 UG230 c9 03 021806 Figure 9 3 SPI Communication Waveforms After driving the DAC CS slave select signal Low the FPGA transmits data on the SPI MOSI signal MSB first The LTC2624 captures input data SPI MOSI on the rising edge of SPI SCK the data must be valid for at least 4 ns relative to the rising clock edge The LTC2624 DAC transmits its data on the SPI MISO signal on the falling edge of SPI SCK The FPGA captures this data on the next rising SPI SCK edge
163. une 20 2008 2 XILINX Chapter 4 FPGA Configuration Options The Spartan 3E FPGA Starter Kit board supports a variety of FPGA configuration options e Download FPGA designs directly to the Spartan 3E FPGA via JTAG using the on board USB interface The on board USB JTAG logic also provides in system programming for the on board Platform Flash PROM and the Xilinx XC2C64A CPLD SPI serial Flash and StrataFlash programming are performed separately e Program the on board 4 Mbit Xilinx XCFO4S serial Platform Flash PROM then configure the FPGA from the image stored in the Platform Flash PROM using Master Serial mode e Program the on board 16 Mbit ST Microelectronics SPI serial Flash PROM then configure the FPGA from the image stored in the SPI serial Flash PROM using SPI mode e Program the on board 128 Mbit Intel StrataFlash parallel NOR Flash PROM then configure the FPGA from the image stored in the Flash PROM using BPI Up or BPI Down configuration modes Further an FPGA application can dynamically load two different FPGA configurations using the Spartan 3E FPGA s MultiBoot mode See the Spartan 3E data sheet DS312 for additional details on the MultiBoot feature Figure 4 1 indicates the position of the USB download programming interface and the on board non volatile memories that potentially store FPGA configuration images Figure 4 2 provides additional details on configuration options Spartan 3E FPGA Starter Kit Bo
164. uoiinqusng suoiing Aerdsig 007 ans m HA IMS m A ens os sau2iing UG230 Aa 12 021806 Figure A 12 Schematic Sheet 13 157 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 Appendix A Schematics A XILINX DDR SDRAM Series Termination and FX2 Connector Differential Termination 158 Resistors R160 through R201 represent the series termination resistors for the DDR SDRAM See Chapter 13 DDR SDRAM for additional information Resistors R202 through R210 are not loaded on the board These landing pads provide optional connections for 1009 differential termination resistors See Using Differential Inputs page 120 for additional information www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 DDR SDRAM Series Termination and FX2 Connector Differential Termination XILINX O iaa 4914818 JES 31TLIL s eubis haowey 400 133HS goaz Geez iubr4fhdoj sur iuerrbiQ p4eog 4914818 3g ue J4eds DG T LHS GE MIX ac gel BEUI cxa M ora SCH gel SEUI ZX3 MN ceur exa Er gel SZUI ZX3 M zora EG gel SZUI ZX3 Qc UT x ac par TZUI ZX3 MN EzUI zX3 caza par Zone tC par Ee caza par sorex WW zorza zac papeo 10N uoneuiw4a erius49jjIQ ZX4 u peo7 ON uorieurw49 S2149S sad UG230 Aa 13 021806
165. ure 2 10 Eight Discrete LEDs Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 19 UG230 v1 1 June 20 2008 Chapter 2 Switches Buttons and Knob XILINX Operation Each LED has one side connected to ground and the other side connected to a pin on the Spartan 3E device via a 390 current limiting resistor To light an individual LED drive the associated FPGA control signal High UCF Location Constraints Figure 2 11 provides the UCF constraints for the four push button switches including the I O pin assignment the I O standard used the output slew rate and the output drive current NET LED lt 7 gt LOC F9 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 6 gt LOC E9 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 5 gt LOC D11 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 4 gt LOC C11 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 3 gt LOC F11 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 2 gt LOC E11 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED lt 1 gt LOC E12 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET LED 0 LOC F12 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 Figure 2 11 UCF Constraints for Eight Discrete LEDs Related Resources e Rotary Encoder Interface for Spartan 3E Starter Kit Reference Design http www xilinx com s3estarter 20 www xilinx com Spartan 3E FPGA
166. ure 4 16 Click Add then click Next gt iMPACT Specify Xilinx PROM Device File Auto Select PROM Enable Revisioning Number of Revisions fi Enable Compression Select a PROM xcf y xcf04s 524288 y Add xcf01s 131072 xc 02s 262144 xc 4s 524288 xcf08p 1048575 Le xcfl6p 2097152 xcf32p 4194304 Delete All UG230 c4 17 022706 Figure 4 16 Choose the XCFO4S Platform Flash PROM The PROM Formatter then echoes the settings as shown in Figure 4 17 Click Finish Y ou have entered following information PROM Type Serial File Format mcs Fill Value FF PROM filename MyPlatformFlash Number of PROMs 1 Click Finish to start adding device files Cancel UG230_c4_18_022706 Figure 4 17 Click Finish after Entering PROM Formatter Settings The PROM Formatter then prompts for the name s of the FPGA configuration bitstream file As shown in Figure 4 18 click OK to start selecting files Select an FPGA bitstream file bit Choose No after selecting the last FPGA file Finally click OK to continue 36 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Programming the FPGA CPLD or Platform Flash PROM via USB Add Device i Start adding device File to A Data Stream O Add Device 2 Would you like to add another device file to Data Stream 0 Add Device i You have completed the devi
167. ve Low bus hold input HLD are unused and pulled High via an external pull up resistor Variant Select Pins VS 2 0 When in SPI configuration mode the FPGA samples the value on three pins labeled VS 2 0 to determine which SPI read command to issue to the SPI Flash For the M25P16 Flash VS 2 0 lt 1 1 1 gt issues the correct command sequence The VS 2 0 pins are pulled High externally via pull up resistors to 3 3V The VS 2 0 pins are also parallel NOR Flash address lines A 19 17 in the FPGA s BPI configuration mode and these signals also connect to the StrataFlash parallel Flash PROM After SPI configuration the VS 2 0 pins become user programmable I O pins allowing full access to the StrataFlash PROM despite that the FPGA configured from SPI Flash Jumper Block J1 1 In SPI configuration mode the FPGA selects the attached SPI Flash by asserting the CSO B pin Low On the Spartan 3E Starter Kit board the CSO B pin drives into the jumper J11 block This jumper block provides the option to move the on board SPI Flash to a different select line SPI ALT CS JP11 This way a different SPI Flash device can be tested by changing the JP11 jumper settings and connecting the alternate SPI Flash on Header JP12 By default both jumpers are inserted on jumper block header J11 Programming Header J12 As shown in Figure 12 15 page 100 Header J12 accepts a JTAG parallel programming cable to program the on board SPI Flash Multi Package
168. ves the 5 x 8 dot matrix to represent the associated character If the address counter is configured to auto increment as described earlier the application can sequentially write multiple character codes and each character is automatically stored and displayed in the next available location Continuing to write characters however eventually falls off the end of the first display line The additional characters do not automatically appear on the second line because the DD RAM map is not consecutive from the first line to the second Disabling the Unused LCD If the FPGA application does not use the character LCD screen drive the LCD_E pin Low to disable it Also drive the LCD_RW pin Low to prevent the LCD screen from presenting data Related Resources 54 e Initial Design for Spartan 3E Starter Kit Reference Design http www xilinx com s3estarter e PowerTip PC1602 D Character LCD Basic Electrical and Mechanical Data http www powertipusa com pdf pc1602d pdf e Sitronix ST7066U Character LCD Controller http www sitronix com tw sitronix product nsf Doc S17066U OpenDocument www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 1 June 20 2008 XILINX Chapter 6 VGA Display Port The Spartan 3E FPGA Starter Kit board includes a VGA display port via a DB15 connector Connect this port directly to most PC monitors or flat panel LCDs using a standard monitor cable As shown in Figure 6
169. ween the FPGA and the ADC The SPI MOSI SPI MISO and SPI SCK signals are shared with other devices on the SPI bus The DAC CS signal is the active Low slave select input to the DAC The DAC CLR signal is the active Low asynchronous reset input to the DAC Table 10 3 ADC Interface Signals Signal FPGA Pin Direction Description SPI SCK U16 FPGA gt ADC Clock AD_CONV P11 FPGA gt ADC Active High shutdown and reset SPI MISO N10 FPGA ADC Serial data Master Input Serial Output Presents the digital representation of the sample analog values as two 14 bit two s complement binary values SPI Control Interface Figure 10 6 provides an example SPI bus transaction to the ADC When the AD CONV signal goes High the ADC simultaneously samples both analog channels The results of this conversion are not presented until the next time AD CONV is asserted a latency of one sample The maxim sample rate is approximately 1 5 MHz The ADC presents the digital representation of the sampled analog values as a 14 bit two s complement binary value Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 79 UG230 v1 1 June 20 2008 Chapter 10 Analog Capture Circuit XILINX SPI MISO Slave LTC1407A 1 A D Converter 3E AD_CONV IZ Z Z SPI SOK Channel 1 Channel 0 Converted data is presented with a latency of one sample The sampled analog value is converted to digital data 32
170. xilinx com 117 UG230 v1 1 June 20 2008 Chapter 15 Expansion Connectors XILINX Table 15 1 Hirose 100 pin FX2 Connector Pinout and FPGA Connections J3 Continued Shared Header Connections FX2 Connector A B Signal Name FPGA Pin LED J1 J2 JP4 J6 top bottom FPGA Pin Signal Name FX2 1030 C4 35 35 FX2 IO31 B11 36 36 FX2 1032 A11 37 37 FX2 1033 A8 38 38 FX2 1034 G9 99 39 FX2_IP35 D12 40 40 FX2_IP36 C12 41 41 FX2_IP37 A15 42 42 FX2_IP38 B15 43 43 FX2 1039 C3 44 44 FX2_IP40 C15 45 45 GND 46 46 E10 FX2_CLKIN FX2_CLKOUT D10 47 47 GND 48 48 D9 FX2_CLKIO 50 50 SHIELD Compatible Board The following board is compatible with the FX2 connector on the Spartan 3E Starter Kit board e VDEC1 Video Decoder Board from Digilent Inc http www digilentinc com Products Detail cfm Prod VDEC1 Mating Receptacle Connectors The Spartan 3E Starter Kit board uses a Hirose FX2 100P 1 27DS header connector The header mates with any compatible 100 pin receptacle connector including board mounted and non locking cable connectors Differential I O The Hirose FX2 connector header J3 supports up to 15 differential I O pairs and two input only pairs using either the LVDS or RSDS I O standards as listed in Table 15 2 All I O pairs support differential input termination DIFF_TERM as described in the Spartan 3E

Xilinx UG230 Spartan-3E FPGA Starter Kit Board User Guide

Contents

Download Pdf Manuals

Related Search

Related Contents