Xilinx UG130:Spartan-3 Starter Kit Board User Guide
Contents
1. Signal FPGA Pin A1 Expansion Connector Pin 1015 R1 1014 P1 1013 L2 1012 J2 1011 H1 1010 F2 IO9 P8 108 D3 IO7 Bl 19 106 Cl 17 IO5 C2 15 IO4 R5 13 IO3 T5 11 IO2 R6 9 IO1 T8 7 IOO N7 5 CE1 chip enable IC10 P7 UB1 upper byte enable IC10 T4 LB1 lower byte enable IC10 P6 Spartan 3 Starter Kit Board User Guide www xilinx com UG130 v1 1 May 13 2005 1 800 255 7778 13 XILINX 14 Table 2 4 SRAM IC11 Connections Signal FPGA Pin 1015 N1 IO14 M1 1013 K2 IO12 C3 IO11 F5 IO10 G1 IO9 E2 108 D2 107 D1 106 El 105 G2 104 JA IO3 K1 IO2 M2 IO1 N2 100 P2 CE2 chip enable IC11 N5 UB2 upper byte enable IC11 R4 LB2 lovver byte enable 1C11 P5 www xilinx com 1 800 255 7778 Chapter 2 Fast Asynchronous SRAM Spartan 3 Starter Kit Board User Guide UG130 v1 1 May 13 2005 SC XILINX Chapter 3 Four Digit Seven Segment LED Display The Spartan 3 Starter Kit board has a four character seven segment LED display controlled by FPGA user I O pins as shown in Figure 3 1 Each digit shares eight common control signals to light individual LED segments Each individual character has a separate anode control input A detailed schematic for the display appears in Figure A 2 The pin number for each FPGA pin connected to the LED display appears in parentheses2. Vertical Sync Horizontal Sync Symbol Parameter Time Clocks Lines Time Clocks Ts Sync pulse time 16 7 ms 416 800 521 32 us 800 Tp sp Display time 15 36 ms 384 000 480 25 6 us 640 Tpw Pulse width 64 us 1 600 2 3 84 us 96 Trp Front porch 320 us 8 000 10 640 ns 16 Tgp Back porch 928 us 23 200 29 1 92 us 48 T kp TpisP bi I T r Tew Pr UG130 c5 03 051305 Figure 5 3 VGA Control Timing www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 VGA Signal Timing A XILINX Generally a counter clocked by the pixel clock controls the horizontal timing Decoded counter values generate the HS signal This counter tracks the current pixel display location on a given row A separate counter tracks the vertical timing The vertical sync counter increments with each HS pulse and decoded values generate the VS signal This counter tracks the current display row These two continuously running counters form the address into a video display buffer For example the on board fast SRAM is an ideal display buffer No time relationship is specified between the onset of the HS pulse and the onset of the VS pulse Consequently the counters can be arranged to easily form video RAM addresses or to minimize decoding logic for sync pulse generation Spartan 3 Starter Kit Board User Guide www xilinx com 25 UG130 v1 1 May 13 2005
3. The Spartan 3 Starter Kit board has a dedicated 50 MHz Epson SG 8002JF series clock oscillator source and an optional socket for another clock oscillator source Figure A 5 provides a detailed schematic for the clock sources The 50 MHz clock oscillator is mounted on the bottom side of the board indicated as 3 in Figure A 5 Use the 50 MHz clock frequeney as is or derive other frequencies using the FPGAs Digital Clock Managers DCMs e Using Digital Clock Managers DCMs in Spartan 3 FPGAs http www xilinx com bvdocs appnotes xapp462 pdf The oscillator socket indicated as in Figure 1 2 accepts oscillators in an 8 pin DIP footprint Table 8 1 Clock Oscillator Sources Oscillator Source FPGA Pin 50 MHz ICA T9 Socket IC8 D9 Spartan 3 Starter Kit Board User Guide www xilinx com 35 UG130 v1 1 May 13 2005 1 800 255 7778 XILINX Chapter 9 FPGA Configuration Modes and Functions Chapter 9 FPGA Configuration Modes and Functions FPGA Configuration Mode Settings In most applications for the Spartan 3 Starter Kit Board the FPGA automatically boots from the on board Platform Flash memory whenever power is applied or the PROG push button is pressed However the board supports all the available configuration modes via the J8 header indicated as Gei in Figure 1 2 Table 9 1 provides the available option settings for the J8 header Additionally the JP1 jumper setting is required when usi
4. 9 E Y m l 3 116 Wee UCCO e UCCO UCCO 9 UCCO UCCO o UCCO UCCO 2 ICIPHR c m S gt amp HBEELEPEBEEEEEBEE gt Nl Ja j jw N N oo IW m Tero ET ATE SE ESTER ES ESTIS alla Jost co oo Nr KO s Ko ES Ies I Ies Ies e s I Joo N mi 1 47nF C13 C14 C16 C61 C17 C18 T Ca 0 014 10 01uF C68 H Q1uF C78 T 9 Q1uF ER C7 C8 0 01uF 10 01uF 47nF 47nF QluF 47nF 12uF Cig C20 C21 C22 C23 C24 C62 47nF 47nF 0 014 47nF 47nF 47nF 1002 C71 C72 C73 C74 C75 C76 C66 9 01uF 10 01uF 10 01uF 0 01uF 10 01uF 10 01uF 10uF C85 C86 C25 C26 C41 C42 47nF 47nF C51 C52 Cs Cep 47nF 47nF C87 C88 css c90 c91 C92 T M IUF 10 01uF 10 01uF 1uF 10 01uF 10 01uF 10 01uF 10 01uF C27 C28 C29 C30 C31 C32 C33 C34 T 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF C43 C44 C45 C46 C47 C48 C49 C50 Ors 4znF 7 47nF 4znF lr 7 427nF 47nF 7 47nF 47nF C53 C54 C55 C56 C57 C58 C538 Cep T T T 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF C63 C 4 C 5 12uF 1046 1006 Digilent 53 Board Copyright 2004 Digilent Inc TITLE 3 Board Release Date 12 17 2004 Sheet 6 8 Engineer CC 3 XNITIX 811 1 482 008 4002 er ABW ELLA OF LON 09 UJOO XUI DCAAMWM p no s sn P eog Wy Jo11e1S c ueuieds pH lul 1 Al AGED JereJed 4104 2
5. Table 6 3 Common PS 2 Keyboard Commands Command ED Description Turn on off Num Lock Caps Lock and Scroll Lock LEDs The keyboard acknowledges receipt of an ED command by replying with an FA after which the host sends another byte to set LED status The bit positions for the keyboard LEDs appear in Table 6 4 Write a 1 to the specific bit to illuminate the associated keyboard LED Table 6 4 Keyboard LED Control 7 6 5 4 3 2 1 0 Caps Num Scroll Lock Lock Lock EE Echo Upon receiving an echo command the keyboard replies with the same scan code EE F3 Set scan code repeat rate The keyboard acknowledges receipt of an F3 by returning an FA after which the host sends a second byte to set the repeat rate FE Resend Upon receiving a resend command the keyboard resends the last scan code sent FF Reset Resets the keyboard The keyboard sends data to the host only when both the data and clock lines are High the Idle state Because the host is the bus master the keyboard checks whether the host is sending data before driving the bus The clock line can be used as a clear to send signal If the host pulls the clock line Low the keyboard must not send any data until the clock is released The keyboard sends data to the host in 11 bit words that contain a 0 start bit followed by eight bits of scan code LSB first followed b
6. p no s sn P eog Wy s s c ueuieds 4002 er ABW ELLA OF LON Fo I 101 L 1N_6 L LP 6 L16N 6 L16P e L17N 6 L17P 6 UREF 6 L19N 6 119 6 L2 N_6 L2 P_6 L21N_6 101 L IN_7 L 1P_7 L16N 7 L16P 7 UREF 7 L17N 7 L17P_7 L19N 7 UREF 7 Ligp 7 L20N 7 L pp 7 L21N_7 L21P_6 L21P_7 L22N_6 L22N_7 L22P_6 L22P_7 L23N_6 L23N_7 L23P_6 L23P_ L24N_6 UREF_6 L24N_7 Digilent S3 Board L24P_6 L24P_7 VIA ree L39N 6 L39N 7 Copuright 2004 Digilent Inc L39P 6 L40N 6 L40P G UREF e n9 L31N 5 D4 TS L32N 4 GCLK1 L31P 5 D5 L32P_4 GCLK to fo N8 L32N 5 GCLK3 L32P 5 GCLK2 D 2 iz D D CIE Lok WELE L L 5901 20 2 Suon uuo2 VOd3 v 2101 E m ix D oD Eok kom 6 pbb L bo o m 4 D 004 m 139 7 d TITLE S3 Board Author GMA Document Number 500 044 Spartan 3 Xilinx Release Date 12 17 2004 Sheet 5 8 906190 SO vdv 06 2 H D an Engineer CC 3 soneul vu s peog y x puaddy 4002 er Aew LEA OF LON p no s sn P eog yy JalleIg c ueueds 81 1 482 008 1 Power Supply UCCINT UCCINT UCCINT UCCINT UCCINT UCCINT UCCINT UCCINT UCCAUX UCCAUX UCCAUX UCCAUX UCCAUX AL L s l 5 ei 3 S VEEBUK S 7 gt SE Yer h wer DEED U OCCO Q Y 5 veco R ver Yom x Ge o x 9 a 2
7. 1 4 4 AAA 5 X Header pin number UG130 c11 01 042504 Figure 11 1 Spartan 3 Starter Kit Board JTAG Chain JTAG Header J7 This J7 JTAG header consists of 0 1 inch stake pins and is indicated as 2 in Figure 1 2 located toward the top edge of the board directly below the two expansion connectors The Digilent low cost parallel port to JTAG cable fits directly over the J7 header stake pins as shown in Figure 11 2 When properly fitted the cable is perpendicular to the board Make sure that the signals at the end of the JTAG cable align with the labels listed on the board The other end of the Digilent cable connects to the PC s parallel port The Digilent cable is directly compatible with the Xilinx iMPACT software The schematic for the Digilent cable appears in Figure A 9 Spartan 3 Starter Kit Board User Guide www xilinx com 41 UG130 v1 1 May 13 2005 1 800 255 7778 A XILINX Chapter 11 JTAG Programming Debugging Ports J7 we nm an s O aa 2pBaoza ro b UG130 11 02 042704 Figure 11 2 Digilent JTAG Cable Provided with Kit Connects to the J7 Header The J7 header also supports the Xilinx Parallel Cable 3 PC3 download debugging cable when using the flying leaders Again make sure that the signals at the end of the JTAG cable align with the labels listed on the board Figure A 4 provides a detailed schematic of the J7 header and the JTAG programming chain Parallel Cable IV MultiPro Desktop Tool J
8. 26 04 1 0 Initial Xilinx release 06 07 04 1 0 1 Minor modifications for printed release 07 21 04 1 0 2 Added information on auxiliary serial port connections to Chapter 7 05 13 05 14 Clarified that SRAM IC10 shares eight lower data lines with A1 connector Spartan 3 Starter Kit Board User Guide www xilinx com UG130 v1 1 May 13 2005 1 800 255 7778 Table of Contents Preface About This Guide Guide Contents i ch ee ce ew antes ee NUR senda ehren Chapter 1 Introduction Key Components and Features Component Lotalions icio re chee ee Fede by da k R Chapter 2 Fast Asynchronous SRAM Address Bus Connections EERSTEN EEN ee eh EE EEN Write Enable and Output Enable Control Signals SRAM Data Signals Chip Enables and Byte Enables Chapter 3 Four Digit Seven Segment LED Display Chapter 4 Switches and LEDs Slide Switches Push Button Switches Chapter 5 VGA Port Signal Timing for a 60Hz 640x480 VGA Display VGA Signal Timing uu eyy ei Chapter 6 PS 2 Mouse Keyboard Port Chapter 7 RS 232 Port Chapter 8 Clock Sources Chapter 9 FPGA Configuration Modes and Functions FPGA Configuration Mode Settings Program Push Button
9. 54 H d VIA 4104 5 222 5 Z V eJnDi 406190 20 vdv oeion Female DB9 DCE connector NOTE Rev E 2 and before Max3232 RXD A and TXD A are swapped on the Jl connector in the silkscreen 0 O N QN Ol Q N and schematic Used for accesory serial port No load Keyboard PS2 connector Parallel 4 JTAG Connector UREF TMS PROG TCK CCLK TDO DONE TDI DIN NC NC INIT er10 er103 FID2 FID4 1 2 3 4 5 6 4 8 9 Digilent 53 Board Copyright 2004 Digilent Inc XNHIX Z soneul vu s peog v x puaddy 4002 er Aew LEA OF LON p no s sn P eog yy JalleIg c ueueds 81 1 482 008 1 UJOO XUI DCAAMWM 19 g v ainbi4 eoepeiu INVHS snouoiuoSu sv 158 91 9 S0ELS0 80 vdv ogLon piri ob me See sheet 5 bank 6 and 7 See sheet 5 bank 5 6 and 7 R1 109 on sheet 5 Bank 5 CE1 UB1 and LB1 on Bank 5 1010 See sheet 5 bank 6 and 7 ro bo fo to pa pa fo to Io to Io B bo IO pa fo See sheet 5 bank 6 and 7 CE2 UB2 and LB2 on Bank 5 IC11 NOTE SRAM address lines and OE WE controls have shared connections with A1 connector Likewise lower eight data bits to SRAM IC10 are also shared with A1 connector 8 C82 1 80 7 C84 C c8 C C77 9 047uF 8 047uF B 047uF 0 047uF 8 047uF B 047uF 10 047uF 0 047uF GND Digilent S3 Board Copyright 2004 Digilent Inc Engineer CC 3 TITLE S3 Board Author
10. Chapter 4 Switches and LEDs Chapter 5 VGA Port Chapter 6 PS 2 Mouse Keyboard Port Chapter 7 RS 232 Port Chapter 8 Clock Sources Chapter 9 FPGA Configuration Modes and Functions Chapter 10 Platform Flash Configuration Storage Chapter 11 JTAG Programming Debugging Ports Chapter 12 Power Distribution Chapter 13 Expansion Connectors and Boards Appendix A Board Schematics Appendix B Reference Material for Major Components Spartan 3 Starter Kit Board User Guide www xilinx com 5 UG130 v1 1 May 13 2005 1 800 255 7778 XILINX Preface About This Guide 6 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 lt XILINX Chapter 1 Introduction The Xilinx Spartan 3 Starter Kit provides a low cost easy to use development and evaluation platform for Spartan 3 FPGA designs Key Components and Features Figure 1 1 shows the Spartan 3 Starter Kit board which includes the following components and features 200 000 gate Xilinx Spartan 3 XC35200 FPGA in a 256 ball thin Ball Grid Array package XC3S200FT256 3 4 320 logic cell equivalents Twelve 18K bit block RAMs 216K bits Twelve 18x18 hardware multipliers Four Digital Clock Managers DCMs Up to 173 user defined I O signals 2Mbit Xilinx XCF028 Platform Flash in system programmable configuration PROM 3 1Mbit non vola
11. DCD DTR and DSR signals connect together as shown in Figure 7 1 Similarly the port s RTS and CTS signals connect together The FPGA connections to the Maxim RS 232 translator appear in Table 7 1 Table 7 1 Accessory Port Connections to the Spartan 3 FPGA Signal FPGA Pin RXD T13 TXD R13 RXD A N10 TXD A T14 Anauxiliary RS 232 serial channel from the Maxim device is available on two 0 1 inch stake pins indicated as J1 in the schematic and in Figure 1 2 The J1 stake pins are in the lower left corner of the board to the right of the DB9 serial connector below the Maxim RS 232 voltage translator and to the left of the individual LEDs The transmitter output from the Maxim device drives the bottom stake pin while the receiver input connects to the top stake pin The FPGA auxiliary RS 232 connections to the Maxim device appear in Table 7 1 with signals RXD A and TXD A Ignore the pin numbers listed on the silkscreen markings next to the stake pins as these apply to the connections to the DB9 connector Place a jumper across the stake pins for an easy loop back test Alternately create custom serial ports by attaching the stake pins to other types of serial connectors such as male or female DB9 or DB25 cable connectors or even create null modem connections 34 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 lt XILINX Chapter 8 Clock Sources
12. DONE Indicator LED Spartan 3 Starter Kit Board User Guide www xilinx com UG130 v1 1 May 13 2005 1 800 255 7778 3 XILINX Chapter 10 Platform Flash Configuration Storage Platform Flash Jumper Options P1 38 Default Opio EE 38 Flash Read OpU002 2 sus aspa ra Ra eR e e dad ee eas 39 Pssable ePi PETI ee 40 Chapter 11 JTAG Programming Debugging Ports TRAG Header KEE 41 Parallel Cable IV MultiPro Desktop Tool JTAG Header 5 42 Chapter 12 Power Distribution AC Wall Adapter na 45 Voltage Kegilator ann ne eur 45 Chapter 13 Expansion Connectors and Boards Expansion Connectors ern er ee 47 Ad Connector Einout ee beri eie a d oe ora oen 49 AZ Connector Pinout isse sep Ba e ee x Re ea e aon es 50 Bl Connector Pinout iore sea e dere P Eee eee e 51 Expansion Boats sss u a een 52 Appendix A Board Schematics Appendix B Reference Material for Major Components 4 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 SC XILINX Preface About This Guide This user guide describes the components and operation of the Spartan 3 Starter Kit Board Guide Contents This manual contains the following chapters Chapter 1 Introduction Chapter 2 Fast Asynchronous SRAM Chapter 3 Four Digit Seven Segment LED Display
13. To light an individual signal drive the individual segment control signal Low along with the associated anode control signal for the individual character In Figure 3 1 for example the left most character displays the value 2 The digital values driving the display in this example are shown in blue The AN3 anode control signal is Low enabling the control inputs for the left most character The segment control inputs A through G and DP drive the individual segments that comprise the character A Low value lights the individual segment a High turns off the segment A Low on the A input signal lights segment a of the display The anode controls for the remaining characters AN 2 0 are all High and these characters ignore the values presented on A through G and DP AN3 E13 AN2 F14 AN1 G14 ANO D14 c N15 P16 00 00 UG130_c3_01_042704 Figure 3 1 Seven Segment LED Digit Control Table 3 1 lists the FPGA connections that drive the individual LEDs comprising a seven segment character Table 3 2 lists the connections to enable a specific character Table 3 3 shows the patterns required to display hexadecimal characters Spartan 3 Starter Kit Board User Guide www xilinx com 15 UG130 v1 1 May 13 2005 1 800 255 7778 A XILINX Chapter 3 Four Digit Seven Segment LED Display Table 3 1 FPGA Connections to Seven Segment Display Active Low Segment FPGA Pin A E1
14. through 40 include the signals required to configure the FPGA in Master or Slave Serial mode Table 13 3 Pinout for A2 Expansion Connector Schematic Name FPGA Pin Connector FPGA Pin Schematic Name GND VU 45V Veco 3 3V all banks E6 PA IO1 PA IO2 D5 C5 PA IO3 PA IO4 D6 C6 PA IO5 PA IO6 E7 C7 PA IO7 PA IO8 D7 C8 PA IO9 PA IO10 D8 C9 PA IO11 PA IO12 D10 A3 PA IO13 PA IO14 B4 A4 PA IO15 PA IO16 B5 A5 PA IO17 PA IO18 B6 B7 MA2 DB0 MA2 DB1 A7 B8 MA2 DB2 MA2 DB3 A8 A9 MA2 DB4 MA2 DB5 B10 A10 MA2 DB6 MA2 DB7 B11 B12 MA2 ASTB MA2 DSTB A12 B13 MA2 WRITE MA2 WAIT A13 B14 MA2 RESET MA2 INT GCK4 D9 B3 PROG B Oscillator socket FPGA PROG B DONE R14 N9 INIT FPGA DONE FPGA INIT B CCLK T15 M11 DIN FPGA CCLK Connects to A14 via 3900 resistor 50 www xilinx com 1 800 255 7778 Spartan 3 Starter Kit Board User Guide UG130 v1 1 May 13 2005 Expansion Connectors XILINX B1 Connector Pinout The B1 expansion connector is located on the right edge of the board as indicated by in Figure 1 2 Table 13 4 provides the pinout for the B1 connector The FPGA connections are specified in parentheses Most of the B1 expansion connector pins connect only with the FPGA and are not shared Pins 36 through 40 include
15. timing html Signal Timing for a 60Hz 640x480 VGA Display CRT based VGA displays use amplitude modulated moving electron beams or cathode rays to display information on a phosphor coated screen LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal thereby changing light permitivity through the crystal on a pixel by pixel basis Although the following description is limited to CRT displays LCD displays have evolved to use the 22 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 Signal Timing for a 60Hz 640x480 VGA Display XILINX Current through the horizontal deflection coil time same signal timings as CRT displays Consequently the following discussion pertains to both CRTs and LCD displays Within a CRT display current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a raster pattern horizontally from left to right and vertically from top to bottom As shown in Figure 5 2 information is only displayed when the beam is moving in the forward direction left to right and top to bottom and not during the time the beam returns back to the left or top edge of the display Much of the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical displa
16. 0 v1 1 May 13 2005 Connector www xilinx com 1 800 255 7778 FPGA Pin Schematic Name VU 5V N8 ADRO L5 ADR1 SRAM AO N3 ADR2 SRAM A1 M4 ADR3 SRAM A2 M3 ADR4 SRAM A3 LA ADR5 SRAM A4 G3 WE SRAM WE K4 OE SRAM OE P9 CSA FPGA DOUT BUSY M10 1 4 MA1 DB2 SRAM A5 F4 MA1 DB4 SRAM A7 E4 MA1 DB6 SRAM A9 H3 MA1 ASTB SRAM A11 04 M A1 VVRITE SRAM A13 K3 MA1 RESET SRAM A15 JTAG Isolation JTAG Isolation C14 TCK FPGA JTAG TCK Header J7 pin 3 TDO A 49 3 XILINX Chapter 13 Expansion Connectors and Boards The A1 expansion connector shares connections with the 256Kx16 SRAM devices specifically the SRAM address lines the OE and WE control signals and the eight least significant data lines to SRAM IC10 only Similarly the JTAG chain is available on pins 36 through 40 Pin 20 is the FPGA DOUT BUSY configuration signal and toggles during the FPGA configuration process A2 Connector Pinout The A2 expansion connector is located along the top edge of the board on the right as indicated by in Figure 1 2 Figure 13 3 provides the pinout for the A2 connector The FPGA connections are specified in parentheses Most of the A2 expansion connector pins connect only with the FPGA and are not shared Pin 35 connects to the auxiliary clock socket if an oscillator is installed in the socket Pins 36
17. 1 800 255 7778 A XILINX Chapter 5 VGA Port 26 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 XILINX Chapter 6 PS 2 Mouse Keyboard Port The Spartan 3 Starter Kit board includes a PS 2 mouse keyboard port and the standard 6 pin mini DIN connector labeled J3 on the board and indicated as in Figure 1 2 Figure 6 1 shows the PS 2 connector and Table 6 1 shows the signals on the connector Only pins 1 and 5 of the connector attach to the FPGA A detailed schematic appears in Figure A 7 UG130 c6 01 042404 Figure 6 1 PS 2 DIN Connector Table 6 1 PS 2 Connections to the Spartan 3 FPGA PS 2 DIN Pin Signal FPGA Pin 1 DATA PS2D M15 p Reserved 3 GND GND 4 Voltage Supply 5 CLK PS2C M16 6 Reserved Both a PC mouse and keyboard use the two wire PS 2 serial bus to communicate with a host device the Spartan 3 FPGA in this case The PS 2 bus includes both clock and data Both a mouse and keyboard drive the bus with identical signal timings and both use 11 bit words that include a start stop and odd parity bit However the data packets are organized differently for a mouse and keyboard Furthermore the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the keyboard The PS 2 bus timing appears Table 6 2 and Figure 6 2 The clock and data signals are only driven when
18. 2 The connector is a DCE style port and connects to the DB9 DTE style serial port connector available on most personal computers and workstations Use a standard straight through serial cable to connect the Spartan 3 Starter Kit board to the PC s serial port Pin 5 Pin 9 DB9 DB9 Serial Port Connector Contiector Maxim MAX3232 front view Cu RS232 Voltage Translator Spartan 3 FPGA DOUT1 DINI RIN1 ROUT1 DOUT2 DIN RIN2 ROUT2 Receiver LD7 LD6 LD5 FPGA pin number Transmitter i i eee _J1 Header Auxiliary Serial Port UG130_c7_01_072104 Figure 7 1 RS 232 Serial Port Figure 7 1 shows the connection between the FPGA and the DB9 connector including the Maxim MAX3232 RS 232 voltage converter indicated as 7 in Figure 1 2 The FPGA supplies serial output data as LVTLL or LVCMOS levels to the Maxim device which in turn converts the logic value to the appropriate RS 232 voltage level Likewise the Maxim Spartan 3 Starter Kit Board User Guide www xilinx com 33 UG130 v1 1 May 13 2005 1 800 255 7778 3 XILINX Chapter 7 RS 232 Serial Port device converts the RS 232 serial input data to LVTLL levels for the FPGA A series resistor between the Maxim output pin and the FPGA s RXD pin protects against accidental logic conflicts A detailed schematic appears in Figure A 7 Hardware flow control is not supported on the connector The port s
19. 2 Port RS 232 Serial Port Driver Auxiliary 55 e Oscillator Socket Oscillator 19 4 Character 7 LED Segment 4 Push Button 8 Slide Switches 4 8 LEDs vccof LED Regulator Regulator Regulator 5 VDC 2A Supply 100 240V AC Input 50 60 Hz AC Wall Adapter Included UG130_c1_01_042504 Figure 1 1 Xilinx Spartan 3 Starter Kit Board Block Diagram PS 2 style mouse keyboard port Four character seven segment LED display 10 Eight slide switches e Eight individual LED outputs 2 e Four momentary contact push button switches i3 8 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 Component Locations 3 XILINX 50 MHz crystal oscillator clock source bottom side of board see Figure 1 3 Socket for an auxiliary crystal oscillator clock source 12 FPGA configuration mode selected via jumper settings Push button switch to force FPGA reconfiguration FPGA configuration happens automatically at power on LED indicates when FPGA is successfully configured Three 40 pin expansion connection ports to extend and enhance the Spartan 3 Starter Kit Board 3 2 See www xilinx com s3boards for compatible expansion cards Compatible with Digilent Inc peripheral boards https digilent us Sales boards cfm Peripheral FPGA serial configuration interface signals available on the A
20. 2 and B1 connectors PROG_B DONE INIT B CCLK DONE JTAG port for low cost download cable Digilent JTAG download debugging cable connects to PC parallel port 22 JTAG download debug port compatible with the Xilinx Parallel Cable IV and MultiPRO Desktop Tool AC power adapter input for included international unregulated 5V power supply Power on indicator LED On board 3 3V 2 5V 22 and 1 2V regulators Component Locations Figure 1 2 and Figure 1 3 indicate the component locations on the top side and bottom side of the board respectively Spartan 3 Starter Kit Board User Guide www xilinx com 9 UG130 v1 1 May 13 2005 1 800 255 7778 lt XILINX Chapter 1 Introduction A1 Expansion Connector A2 Expansion Connector PEE Dan WA ES in EN EX XM WA nnm 3 2Mbit LONE 16 PlatformFlash G7 XILINX K3 XC3S200 DONE FPGA PROG POWER POWER L go e e er dl H BG H H H EIN ug130 ci 02 042704 B1 Expansion Connector m m Figure 1 2 Xilinx Spartan 3 Starter Kit Board Top Side 256Kx16 SRAM 256Kx16 SRAM ug130 c 03 042704 Figure 1 3 Xilinx Spartan 3 Starter Kit Board Bottom Side 10 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 SC XILINX Chapter 2 Fast Asynchronous SRAM The Spartan 3 Starter Kit board has a megabyte of fast asy
21. 4 B G13 d N15 D P15 E R16 F F13 G N16 DP P16 Table 3 2 Digit Enable Anode Control Signals Active Low Anode Control AN3 AN2 ANI ANO FPGA Pin E13 F14 G14 D14 Table 3 3 Display Characters and Resulting LED Segment Control Values Character a b c d e f g 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 2 0 0 1 0 0 1 0 3 0 0 0 0 1 1 0 4 1 0 0 1 1 0 0 5 0 1 0 0 1 0 0 6 0 1 0 0 0 0 0 7 0 0 0 1 1 1 1 8 0 0 0 0 0 0 0 9 0 0 0 0 1 0 0 A 0 0 0 1 0 0 0 b 1 1 0 0 0 0 0 C 0 1 1 0 0 0 1 d 1 0 0 0 0 1 0 E 0 1 1 0 0 0 0 F 0 1 1 1 0 0 0 16 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 3 XILINX The LED control signals are time multiplexed to display data on all four characters as shown in Figure 3 2 Present the value to be displayed on the segment control inputs and select the specified character by driving the associated anode control signal Low Through persistence of vision the human brain perceives that all four characters appear simultaneously similar to the way the brain perceives a TV display ANS AN2 AN1 BGDERGDP DISP3 pisP2 pisPt DISPO UG130 c3 02 042404 Figure 3 2 Drive Anode Input Low to Light an Individual Character This scanning technique reduces the number of I O pins required for the four characters If an FPGA pin were dedica
22. 5 2 The controller indexes into the video data buffer as the beams move across the display The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel As shown in Figure 5 2 the VGA controller generates the HS horizontal sync and VS vertical sync timings signals and coordinates the delivery of video data on each pixel clock The pixel clock defines the time available to display one pixel of information The VS signal defines the refresh frequency of the display or the frequency at which all information on the display is redrawn The minimum refresh frequency is a function of the display s phosphor and electron beam intensity with practical refresh frequencies in the 60 Hz to 120 Hz range The number of horizontal lines displayed at a given refresh frequency defines the horizontal retrace frequency VGA Signal Timing The signal timings in Table 5 3 are derived for a 640 pixel by 480 row display using a 25 MHz pixel clock and 60 Hz 1 refresh Figure 5 3 shows the relation between each of the timing symbols The timing for the sync pulse width Tpw and front and back porch intervals and Tgp are based on observations from various VGA displays The front and back porch intervals are the pre and post sync pulse times Information cannot be displayed during these times Table 5 3 640x480 Mode VGA Timing
23. 7 is the left most LED LEDO the right most LED Table 4 3 shows the FPGA connections to the LEDs Table 4 3 LED Connections to the Spartan 3 FPGA LED LD7 LD6 LD5 LD4 LD3 LD2 LD1 LDO FPGA Pin P11 P12 N12 P13 N14 L12 P14 K12 The cathode of each LED connects to ground via a 270Q resistor To light an individual LED drive the associated FPGA control signal High which is the opposite polarity from lighting one of the 7 segment LEDs 20 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 SC XILINX Chapter 5 VGA Port The Spartan 3 Starter Kit board includes a VGA display port and DB15 connector indicated 5 in Figure 1 2 Connect this port directly to most PC monitors or flat panel LCD displays using a standard monitor cable Pin 5 Pin 10 Pin 15 DB15 VGA Connector DB15 front view Connector 2700 AAN OR R12 d 2700 n NIN o G T12 2700 AAN o B R Horizontal Sync O HS R9 Vertical Sync ve T10 xx FPGA pin number V GND UG130_c5_01_042604 Figure 5 1 VGA Connections from Spartan 3 Starter Kit Board As shown in Figure 5 1 the Spartan 3 FPGA controls five VGA signals Red R Green G Blue B Horizontal Sync HS and Vertical Sync VS all available on the VGA connector The FPGA pins that drive the VGA port appear in Table 5 1 A detailed schematic is in Figure A 7 Sparta
24. AG pins are powered by VccAUx The FPGA configuration interface on the board is powered by 3 3V Consequently the 2 5V supply has a current shunt resistor to prevent reverse current Finally a 1 2V regulator supplies power to the FPGA s VccrNr voltage inputs which power the FPGA s core logic The board uses three discrete regulators to generate the necessary voltages However various power supply vendors are developing integrated solutions specifically for Spartan 3 FPGAs Figure A 3 provides a detailed schematic of the various voltage regulators Similarly Figure A 6 shows the power decoupling capacitors 46 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 SC XILINX Chapter 13 Expansion Connectors and Boards Expansion Connectors The Spartan 3 Starter Kit board has three 40 pin expansion connectors labeled A1 A2 and B1 The A1 and A2 connectors indicated as and Go respectively in Figure 1 2 are on the top edge of the board Connector A1 is on the top left and A2 is on the top right The B1 connector indicated as 9 in Figure 1 2 is along the right edge of the board A1 Expansion Connector A2 Expansion Connector x a O Q m 5 Al c mmm H c mm xX mum LL _ 1 m UG130_c12_01_042704 Figure 13 1 Spartan 3 Starter Kit Board Expansion Connectors Table 13 1 summarizes the capabilities of each ex
25. E u BEE provides parallel data and clock to load the FPGA SR RE I MO M1 M2 JTAG The FPGA waits for configuration via the four wire JTAG rGND J8 EEE JP1 8 lt 1 0 1 gt w interface BRE MO M1 M2 Program Push Button DONE Indicator LED The Spartan 3 Starter Kit Board includes two FPGA configuration functions located near the VGA connector and the AC power input connector as shown in Figure 9 1 The PROG push button shown as m in Figure 9 1 drives the FPGA s PROG B programming pin When pressed the PROG push button forces the FPGA to reconfigure and reload it configuration data The DONE LED shown as 18 in Figure 9 1 connects to the FPGA s DONE pin and lights up when the FPGA is successfully configured DONE PROG UG130 c9 03 042704 Figure 9 1 The PROG Button and the DONE LED Spartan 3 Starter Kit Board User Guide www xilinx com 37 UG130 v1 1 May 13 2005 1 800 255 7778 XILINX Chapter 10 Platform Flash Configuration Storage The Spartan 3 Starter Kit board has an 25 serial configuration Flash PROM to store FPGA configuration data and potentially additional non volatile data including MicroBlaze application code To configure the FPGA from Platform Flash memory all three jumpers must be installed on the J8 header indicated as Gei in Figure 1 2 Platform Flash Jumper Options JP1 The Platform Flash has three optional settings controlled by the JP1
26. GMA Document Number 500 044 Release Date 12 17 2004 Sheet 8 8 XNITIX 811 1 482 008 4002 er ABW ELLA OF LON c9 UJOO XUI DCAAMWM p no s sn P eog Wy Jones c ueuieds lqe Bngeq peojumog HYLF 1502 01 95V1f lu lIi6bid 6 v 2 6 v092r70 60 vdv ocion IC2A1 1 gt NL37WZ17 IC2A3 2 NL37W217 IC2A2 r NL37W217 NL17SZ125 its 00 c Je ICIPHR IC2PUR lur Ta ur Note PS P11 P12 are shorted at PC end of cable Jtag3 Programing Cable Copyright 2002 2003 Digilent Inc TITLE Jtag3 Document Number 500 042 Rev D Release Date 9 6 2083 Sheet 1 1 XNHIX Z soneul vu s peog v x puaddy SC XILINX Appendix B Reference Material for Major Components Table B 1 lists the major components on the Spartan 3 Starter Kit Board including full part numbers and links to complete device data sheets Table B 1 Major Components and Data Sheet Links Device Vendor Part Number Description Data Sheet Link o Xilinx Inc XC3S200 4FT256C Spartan 3 FPGA IC1 http www xilinx com bvdocs publications ds099 pdf Xilinx Inc XCF02SVO20C Platform Flash Configuration Flash PROM IC9 http www xilinx com bvdocs publications ds123 pdf Integrated Silicon IS61LV25616AL 10T 256Kx16 Fast Asynchronous SRAM IC10 IC11 Solutions Inc ISSI http www issi com pdf 61LV25616AL pdf Max
27. Interface http panda cs ndsu nodak edu achapvves PICmicro mouse mouse html Voltage Supply Most modern keyboards and mice work equally well from a 3 3V or 5V supply The voltage supply for the PS 2 port is selectable via the JP2 jumper indicated as amp in Figure 1 2 located immediately above the PS 2 connector along the right edge The 3 3V setting is preferred as the FPGA s output signals operate from the 3 3V supply The JP2 jumper should be positioned as shown in Table 6 5 by default Table 6 5 PS 2 Port Supply Voltage Options PS 2 Port Jumper JP2 Supply Voltage Setting 3 3V gt JP2 DEFAULT 5V gt JP2 Some older keyboards and mice are 5V only Consequently the JP2 jumper should be set for 5V operation as shown in Table 6 5 The Spartan 3 FPGA can tolerate 5V signals due to the 2700 series resistors on the PS 2 data and clock signals connected to the FPGA See the schematic in Figure A 7 for more details Spartan 3 Starter Kit Board User Guide www xilinx com 31 UG130 v1 1 May 13 2005 1 800 255 7778 A XILINX Chapter 6 PS 2 Mouse Keyboard Port 32 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 XILINX Chapter 7 RS 232 Serial Port The Spartan 3 Starter Kit board has an RS 232 serial port The RS 232 transmit and receive signals appear on the female DB9 connector labeled J2 indicated as in Figure 1
28. Spartan 3 Starter Kit Board User Guide UG130 v1 1 May 13 2005 XILINX XILINX Xilinx and the Xilinx logo shown above are registered trademarks of Xilinx Inc Any rights not expressly granted herein are reserved CoolRunner RocketChips Rocket IP Spartan StateBENCH StateCAD Virtex XACT XC2064 XC3090 XC4005 and XC5210 are registered trademarks of Xilinx Inc The shadow X shown above is a trademark of Xilinx Inc ACE Controller ACE Flash A K A Speed Alliance Series AllianceCORE Bencher ChipScope Configurable Logic Cell CORE Generator CoreLINX Dual Block EZTag Fast CLK Fast CONNECT Fast FLASH FastMap Fast Zero Power Foundation Gigabit Speeds and Beyond HardWire HDL Bencher IRL J Drive JBits LCA LogiBLOX Logic Cell LogiCORE LogicProfessor MicroBlaze MicroVia MultiLINX NanoBlaze PicoBlaze PLUSASM PowerGuide PowerMaze QPro Real PCI RocketlO SelectlO SelectRAM SelectRAM Silicon Xpresso Smartguide Smart IP SmartSearch SMARTswitch System ACE Testbench In A Minute TrueMap UIM VectorMaze VersaBlock VersaRing Virtex lI Pro Virtex ll EasyPath Wave Table WebFITTER WebPACK WebPOWERED XABEL XACT Floorplanner XACT Performance XACTstep Advanced XACTstep Foundry XAM XAPP X BLOX XC designated products XChecker XDM XEPLD Xilinx Foundation Series Xilinx XDTV Xinfo XSI XtremeDSP and ZERO are trademarks of Xilinx Inc The Programmable Logic Comp
29. Starter Kit Board User Guide www xilinx com 43 UG130 v1 1 May 13 2005 1 800 255 7778 SC XILINX Chapter 11 JTAG Programming Debugging Ports 44 www xilinx com 1 800 255 7778 Spartan 3 Starter Kit Board User Guide UG130 v1 1 May 13 2005 lt XILINX Power Distribution Chapter 12 AC Wall Adapter The Spartan 3 Starter Kit includes an international ready AC wall adapter that produces a 5V DC output Connect the AC wall adapter to the barrel connector along the left edge of the board indicated as Gi in Figure 1 2 There is no power switch to the board To disconnect power remove the AC adapter from the wall or disconnect the barrel connector The POWER indicator LED shown as in Figure 1 2 lights up when power is properly applied to the board If the jumpers in the J8 header and JP1 header are properly set and there is a valid configuration data file in the Platform Flash memory then the DONE indicator LED shown as in Figure 1 2 also lights up The AC wall adapter is directly compatible for North America Japan and Taiwan locales Other locations might require a socket adapter to convert from the North American standard to the local power socket standard The AC wall adapter operates from 100V to 240V AC input at 50 or 60 Hz Voltage Regulators There are multiple voltages supplied on the Spartan 3 Starter Kit Board as summarized in Table 12 1 Table 12 1 Voltage Suppl
30. TAG Header J5 The J5 header shown as in Figure 1 2 supports the Xilinx download debugging cables listed below MultiPro Desktop Tool http www xilinx com bvdocs publications ds114 pdf e Parallel Cable IV PC IV http toolbox xilinx com docsan xilinx4 data docs pac cables6 html Use the 14 pin ribbon cable supplied with both cables to connect to the J5 header DO NOT use the flying leads that are also provided with some cables Although the MultiPro Desktop Tool and the Parallel Cable IV support multiple FPGA configuration modes the Spartan 3 Starter Kit board only supports the JTAG configuration method The header is designed for a keyed socket However the Spartan 3 Starter Kit uses only stake pins The outline of the keyed connector appears around the J5 header as shown in Figure 11 3 When properly inserted the keyed header matches the outline on the board and the ribbon cable crosses over the top edge of the board The red colored lead indicates pin 1 on the cable and should be on the left side 42 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 Parallel Cable IV MultiPro Desktop Tool JTAG Header J5 XILINX Red trace i indicates pin 1 Parallel Cable IV Notch on outline JTAG matches key on header UG130_c11_03_042704 Figure 11 3 Use 14 Pin Ribbon Cable to Connect Parallel Cable IV or the MultiPro Desktop Tool to the J5 Header Spartan 3
31. V POSER SES E000 00 0 000 0000 00 000 00008 E EB E E EB ELE NZ III TICE EI EICH TTC Ve IT TTT Pin 40 77 N Pin 4 Pin 2 VU Pin 40 5V UG130 c12 02 042504 Figure 13 2 40 pin Expansion Connector The pinout information for each connector appears below The tables include the connections between the FPGA and the expansion connectors plus the signal names used in the detailed schematic in Figure A 1 48 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 Expansion Connectors A1 Connector Pinout 3 XILINX The A1 expansion connector is located along the top edge of the board on the left as indicated by FPGA connections are specified in parentheses Table 13 2 Pinout for A1 Expansion Connector in Figure 1 2 Table 13 2 provides the pinout for the A1 connector The Schematic Name FPGA Pin GND Veco 3 3V Veco all banks DBO N7 SRAM IC10 IOO DB1 T8 SRAM IC10 IO1 DB2 R6 SRAM IC10 IO2 DB3 T5 SRAM IC10 IO3 DB4 R5 SRAM IC10 104 DB5 C2 SRAM IC10 IO5 DB6 C1 SRAM IC10 IO6 DB7 B1 SRAM IC10 IO7 LSBCLK M7 MA1 DB1 F3 SRAM A6 MA1 DB3 E3 SRAM A8 MA1 DB5 G5 SRAM A10 MA1 DB7 H4 SRAM A12 MA1 DSTB J3 SRAM A14 MA1 VVATT K5 SRAM A16 MA1 INT L3 SRAM A17 TMS C13 FPGA TTAG TMS TDO ROM Platform Flash JTAG TDO Spartan 3 Starter Kit Board User Guide UG13
32. any is a service mark of Xilinx Inc All other trademarks are the property of their respective owners Xilinx Inc does not assume any liability arising out of the application or use of any product described or shown herein nor does it convey any license under its patents copyrights or maskwork rights or any rights of others Xilinx Inc reserves the right to make changes at any time in order to improve reliability function or design and to supply the best product possible Xilinx Inc will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products Xilinx provides any design code or information shown or described herein as is By providing the design code or information as one possible implementation of a feature application or standard Xilinx makes no representation that such implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation including but not limited to any warranties or representations that the implementation is free from claims of infringement as well as any implied warranties of merchantability or fitness for a particular purpose Xilinx Inc devices and products are protected under U S Patents Other U S and foreign patents pending Xilinx Inc does not represent that de
33. c ueuieds oBe1oA 110g Z Sd 40 Bum s 1eduunf Zdr suojejnbay oDeyoA e v anbig 3 UIN UOUT 12uF LM1 86CS Keyboard Power Supply Jumper PS2 4 UCCO 3 3U UCCAUX 2 5U 9 1uF LF25CDT UCCINT 1 2U for core Digilent 53 Board Copyright 2004 Digilent Inc Release Date 12 17 2004 XNHIX Z soneul vu s peog y x puaddy 4002 er Aew LEA OF LON p no s sn P eog yy JalleIg c ueueds 81 1 482 008 1 UJOO XUI DCAAMWM 258 Jeduinf suonoeuuo VL usej4 WIONEId e ejyieju voein lyuog YYdF P Y 9116 JTAG Interface Header TMS TDI TDO TCK GND UCC FPGA Control and Configuration Functions Control Functions TMS TCK Jumper Block Stor age TDO CC DO PROG L27N_4 DIN L31N 4 INIT L31P 4 DOUT BU HSWAP_ IC1MISC Note Comfirm no jumper default state FPGA Mode Select Jumpers To connectors A2 and Bi C10 C C12 11 9 Q47uF 10 047uF 0 847UF GND A shorting block must be installed between TDI and TDO on J to complete the scan chain when the JTAG signals are ic being driven from a peripheral board position rather than the Digilent S3 Board JTAG Interface Header Copyright 2004 Digilent Inc Engineer CC to bypass the the serial configuration rom 1C95 TITLE 53 Board Author CMA Shorting blocks should be installed on MODE and MODE1 of J8 Document Number 500 044 to select Slave Se
34. data transfers occur and otherwise they are held in the idle state at logic High The timings define signal requirements for mouse to host communications and Spartan 3 Starter Kit Board User Guide www xilinx com 27 UG130 v1 1 May 13 2005 1 800 255 7778 XILINX Chapter 6 PS 2 Mouse Keyboard Port Keyboard bidirectional keyboard communications As shown in Figure 6 2 the attached keyboard or mouse writes a bit on the data line when the clock signal is High and the host reads the data line when the clock signal is Low Table 6 2 PS 2 Bus Timing Symbol Parameter Min Max Tek Clock High or Lovv time 30 us 50 us Tsu Data to clock setup time 5 us 25 us THLD Clock to data hold time 5 us 25 us Tek Tek Edge 0 en 10 CLK PS2C d m l Tup Tsu ri DATA PS2D mme 0 start bit UG130 c6 02 042404 Figure 6 2 PS 2 Bus Timing Waveforms The following site contains additional information on the PS 2 bus protocol D5 2Mouse Keyboard Protocol http panda cs ndsu nodak edu achapwes PICmicro PS2 ps2 htm The keyboard uses open collector drivers so that either the keyboard or the host can drive the two wire bus If the host never sends data to the keyboard then the host can use simple input pins A PS 2 style keyboard uses scan codes to communicate key press data Nearly all keyboards in use today are PS 2 style Each key has a single unique scan code that is
35. e address signals also connect to the Al Expansion Connector see Expansion Connectors page 47 Table 2 1 External SRAM Address Bus Connections to Spartan 3 FPGA Address Bit FPGA Pin A1 Expansion Connector Pin A17 L3 35 A16 K5 33 A15 K3 34 A14 Ja 81 A13 J4 32 A12 H4 29 A11 H3 30 A10 G5 27 A9 E4 28 A8 E3 25 A7 F4 26 A6 F3 23 A5 G4 24 A4 L4 14 A3 M3 12 A2 M4 10 A1 N3 8 AO L5 6 12 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 Write Enable and Output Enable Control Signals XILINX Write Enable and Output Enable Control Signals Both 256Kx16 SRAMs share common output enable OE and write enable WE control lines as shown in Table 2 2 These control signals also connect to the A1 Expansion Connector refer to Expansion Connectors page 47 Table 2 2 External SRAM Control Signal Connections to Spartan 3 FPGA Signal FPGA Pin A1 Expansion Connector Pin OE K4 16 WE G3 18 SRAM Data Signals Chip Enables and Byte Enables The data signals chip enables and byte enables are dedicated connections between the FPGA and SRAM Table 2 3 shows the FPGA pin connections to the SRAM designated IC10 in Figure A 8 Table 2 4 shows the FPGA pin connections to SRAM IC11 To disable an SRAM drive the associated chip enable pin High Table 2 3 SRAM IC10 Connections
36. e A1 A2 or B1 connectors as listed below Spartan 3 Starter Kit Expansion Boards http www xilinx com s3boards Digilent Expansion Boards https digilent us Sales boards cfm Peripheral Digilent Breakout Probe Header TPH1 https digilent us Sales Product cfm Prod TPH1 Digilent Breadboard DBB1 https digilent us Sales Product cfm Prod DBB1 Digilent Wire wrap Board DWR1 https digilent us Sales Product cfm Prod DWR1 Digilent SPP EPP ECP Parallel Port PIO1 https digilent us Sales Product cfm Prod PIO1 52 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 SC XILINX Appendix A Board Schematics This appendix provides the schematics for the Spartan 3 Starter Kit Board Figure A 1 A1 A2 and B1 Expansion Connectors Figure A 2 Slide Switches Push Buttons LEDs and Four Character 7 Segment Display Figure A 3 Voltage Regulators JP2 Jumper Setting for PS 2 Port Voltage Figure A 4 FPGA Configuration Interface Platform Flash JTAG Connections Jumper JP1 Figure A 5 FPGA I O Connections Clock Sources Figure A 6 Power Decoupling Capacitors Figure A 7 RS 232 Serial Port VGA Port PS 2 Port Parallel Cable IV JTAG Interface Figure A 8 2x256Kx16 Fast Asynchronous SRAM Interface Figure A 9 Digilent JTAG3 Low Cost JTAG Download Debug Cable Spartan 3 Starter Kit Board User Guide www xilinx c
37. ental conflicts between the two signals Spartan 3 Starter Kit Board User Guide www xilinx com 39 UG130 v1 1 May 13 2005 1 800 255 7778 A XILINX Chapter 10 Platform Flash Configuration Storage Additional FPGA logic is required to read the Platform Flash data as described in the following application note e XAPP694 Reading User Data from Configuration PROMs http www xilinx com bvdocs appnotes xapp694 pdf Disable Option If the JP1 jumper is removed then the Platform Flash is disabled potentially allowing configuration via an expansion board connected to one of the expansion connectors 40 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 XILINX Chapter 11 JTAG Programming Debugging Ports The Spartan 3 Starter Kit board includes a JTAG programming and debugging chain Both the Spartan 3 FPGA and the Platform Flash devices are part of the JTAG chain as shown in Figure 11 1 Additionally there are two JTAG headers for driving the JTAG signals from various supported JTAG download and debugging cables A Digilent JTAG3 low cost parallel to JTAG cable is included as part of the kit and connects to the J7 header Digilent Parallel JTAG3 Cable IV Spartan 3 FPGA PlatformFlash Parallel MultiPro Cable 3 Desktop XC3S400FT256C XCF02S Tool Header Header J7 J5 2 10 NW
38. h Read Option The Spartan 3 Starter Kit Board includes a 2Mbit Platform Flash configuration PROM The XC3S200 FPGA on the board only requires slightly less than 1Mbit for configuration data The remainder of the Platform Flash is available to store other non volatile data such as revision codes serial numbers coefficients an Ethernet MAC ID or code for an embedded processor such as MicroBlaze within the FPGA To allow the FPGA to read from Platform Flash after configuration the JP1jumper must be properly positioned as shown in Figure 10 2 When the jumper is in this position the Platform Flash is always enabled After FPGA configuration completes the FPGA application drives the INIT B pin High FPGA pin N9 Consequently the Platform Flash data pointer is not reset and points to the additional data following the FPGA configuration data To read any subsequent data the FPGA application generates additional clock pulses on the RCLK signal from FPGA pin A14 After configuration the FPGA s CCLK output is three stated with a pull up resistor to VccAux 2 5V The Platform Flash presents serial data on the FPGA s DIN pin pin M11 Spartan 3 FPGA Platform Flash Nl JP1 DINDO DO Flash Read INIT_B OE RESET DONE CE CCLK USER I O xx FPGA pin number 8130 10 02 060404 Figure 10 2 Read Additional Data from Platform Flash by Setting the 1 Jumper The resistor between the CCLK output and FPGA pin A14 prevents any accid
39. ies and Sources Voltage Source Supplies 5V DC AC Wall Adapter 5V switching power supply 3 3V regulator in Figure 1 2 Optionally PS 2 port via jumper JP2 setting Pin 1 VU on Al A2 Bl expansion connectors 3 3V DC National Semiconductor LM1086C5 AD 3 3V 2 5V and 1 2V regulators regulator in Figure 1 2 Vcco supply input for all FPGA I O banks Most components on the board Pin 3 on A1 A2 B1 expansion connectors 2 5V DC STMicroelectronics LF25CDT 2 5V regulator Vccaux supply input to FPGA in Figure 1 2 1 2V DC Fairchild Semiconductor FAN1112 1 2V Vcemr Supply input to FPGA regulator in Figure 1 2 Overall the 5V DC switching power adapter that connects to AC wall power powers the board A 3 3V regulator powered by the 5V DC supply provides power to the inputs of the Spartan 3 Starter Kit Board User Guide UG130 v1 1 May 13 2005 www xilinx com 45 1 800 255 7778 3 XILINX Chapter 12 Power Distribution 2 5V and 1 2V regulators Similarly the 3 3V regulator feeds all the Veco voltage supply inputs to the FPGA s I O banks and powers most of the components on the board The 2 5V regulator supplies power to the FPGA s VccAux supply inputs The VccAux voltage input supplies power to Digital Clock Managers DCMs within the FPGA and supplies some of the I O structures In specific all of the FPGA s dedicated configuration pins such as DONE PROG B CCLK and the FPGA s JT
40. im Intersil MAX3232 ICL3232 Dual Channel RS 232 Voltage Translator IC14 http pdfserv maxim ic com en ds MAX3222 MAX3241 pdf http www intersil com data fn fn4805 pdf Epson SG 8002JF 50 MHz Crystal Oscillator IC4 http vvvvvv knap at de pdf kat o sg8002jf pdf Interex APA 101M 05 5V Switching Regulator National LM1086CS ADJ 3 3V Regulator IC5 Semiconductor http www national com pf LM LM1086 html Datasheet 2 STMicroelectronics LF25CDT 2 5V Regulator IC3 http www st com stonline books pdf docs 2574 pdf Fairchild FAN1112 1 2V Regulator IC12 Semiconductor http www fairchildsemi com ds FA FAN1112 pdf Spartan 3 Starter Kit Board User Guide UG130 v1 1 May 13 2005 www xilinx com 63 1 800 255 7778 3 XILINX SPARTAN 3 MAKE IT YOUR ASIC www xilinx com s3boards PN 0402292 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005
41. jumper which is located in the upper right hand corner of the board adjacent to the Platform Flash configuration PROM The JP1 jumper is indicated as 3 in Figure 1 2 A detailed schematic is provided in Figure A 4 Table 10 1 summarizes the available options which are described in more detail below Table 10 1 Jumper JP1 Controls the Platform Flash Options 1 2 Option Setting Description Default CN JP1 The FPGA boots from Platform Flash No additional data storage is available Flash Read The FPGA boots from Platform Flash which is permanently enabled The FPGA JP1 AM NE can read additional data from Platform Flash Disable 1 Jumper removed Platform Flash is disabled Other configuration data source PS provides FPGA boot data Default Option For most applications this is the default jumper setting As shown in Figure 10 1 the Platform Flash is enabled only during configuration when the FPGA s DONE pin is Low When the DONE pin goes High at the end of configuration the Platform Flash is disabled and placed in low power mode Spartan 3 Starter Kit Board User Guide www xilinx com 38 UG130 v1 1 May 13 2005 1 800 255 7778 Flash Read Option XILINX Spartan 3 FPGA Platform Flash Default DIN DO DO INIT_B OE RESET DONE CE CCLK 9 CLK lt USER I O 1 RCLK UG130_c10_01_060704 Figure 10 1 Default Platform Flash Option Flas
42. n 3 Starter Kit Board User Guide www xilinx com 21 UG130 v1 1 May 13 2005 1 800 255 7778 A XILINX Chapter 5 VGA Port Table 5 1 VGA Port Connections to the Spartan 3 FPGA Signal FPGA Pin Red R R12 Green G T12 Blue B R11 Horizontal Sync HS R9 Vertical Sync VS T10 Each color line has a series resistor to provide 3 bit color with one bit each for Red Green and Blue The series resistor uses the 752 VGA cable termination to ensure that the color signals remain in the VGA specified OV to 0 7V range The HS and VS signals are TTL level Drive the R G and B signals High or Low to generate the eight possible colors shown in Table 5 2 Table 5 2 3 Bit Display Color Codes Red R Green G Blue B Resulting Color 0 o O0 Bak 0 0 1 Blue 0 1 0 Green 0 1 1 Cyan 1 0 0 Red 1 0 1 Magenta 1 1 0 Yellow VGA signal timing is specified published copyrighted and sold by the Video Electronics Standards Association VESA The following VGA system and timing information is provided as an example of how the FPGA might drive VGA monitor in 640 by 480 mode For more precise information or for information on higher VGA frequencies refer to documents available on the VESA website or other electronics websites e Video Electronics Standards Association http www vesa org e VGA Timing Information http www epanorama net documents pc vga
43. nchronous SRAM surface mounted to the backside of the board The memory array includes two 256Kx16 ISSI IS61LV25616AL 10T 10 ns SRAM devices as shown in Figure 2 1 A detailed schematic appears in Figure A 8 ISSI 256Kx16 SRAM 10 ns see Table 2 3 4 gt 1 0f 15 0 A 17 0 m 1 10 UB LB WE OE Spartan 3 FPGA ISSI 256Kx16 SRAM 10 ns see Table 2 4 lt gt see Table 2 1 D xx FPGA pin number UG130_c2_01_042604 Figure 2 1 FPGA to SRAM Connections Spartan 3 Starter Kit Board User Guide www xilinx com 11 UG130 v1 1 May 13 2005 1 800 255 7778 3 XILINX Chapter 2 Fast Asynchronous SRAM The SRAM array forms either a single 256Kx32 SRAM memory or two independent 256Kx16 arrays Both SRAM devices share common write enable WE output enable OE and address A 17 0 signals However each device has a separate chip select enable CE control and individual byte enable controls to select the high or low byte in the 16 bit data word UB and LB respectively The 256Kx32 configuration is ideally suited to hold MicroBlaze instructions However it alternately provides high density data storage for a variety of applications such as digital signal processing DSP large data FIFOs and graphics buffers Address Bus Connections Both 256Kx16 SRAMs share 18 bit address control lines as shown in Table 2 1 Thes
44. ng Master Serial configuration mode as further described in Platform Flash Jumper Options JP1 The default jumper settings for the board are All jumpers in the J8 header are installed The JP1 jumper is in the Default position Table 9 1 Header J8 Controls the FPGA Configuration Mode Configuration Mode lt M0 M1 M2 gt Header J8 Jumper JP1 Deseripti n Settings Setting p Master Serial DEFAULT The FPGA automatically boots from the Platform GND J8 JP1 lt 0 0 0 gt El a ES Flash or MO M1 M2 ENS JP1 EE Jp1 he FPGA attempts to boot from a serial configuration source attached to either expansion connector A2 or B1 Slave Serial Another device connected to either the A2 or B1 expansion rGND 48 ees lt 1 1 1 gt i B B u connector provides serial data and clock to load the FPGA 2 Mo M1 M2 Master Parallel rGND J8 JP1 The FPGA attempts to boot from a parallel configuration source lt 1 1 0 gt u BEE attached to the Bl expansion connector 1 S Mo M1 M2 36 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 Program Push Button DONE Indicator LED XILINX Table 9 1 Header J8 Controls the FPGA Configuration Mode Continued Configuration Header J8 Jumper JP1 Mode Description M0 M1 M25 Settings Setting Slave Parallel GND 48 JP1 Another device connected to the B1 expansion connector 01 1 B
45. om 53 UG130 v1 1 May 13 2005 1 800 255 7778 811 1 482 008 4002 er ABW ELLA OF LON rs UJOO XUI DCAAMWM p no s sn P eog Wy Jo11e1S c ueuieds IL y eunDi4 S10199uu0 uoisuedx3 Lg pue zy LY 00 N A OI QN 0 NGO O O N MA2 INT GCK4 R61 108 R69 100 R66 188 R63 100 R56 PROG B DIN NOTE SRAM address lines and OE WE controls have shared connections with A1 connector Likewise lower eight data bits to SRAM IC10 are also shared with A1 connector Digilent Inc 906190 Lo vdv oeron AW 108 00 NO OI kr Digilent S3 Board Copyright 2004 Digilent Inc XNHIX Z soneul vu s peog v x puaddy 4002 er Aew LEA OF LON p no s sn P eog yy JalleIg c ueueds 81 1 482 008 1 UJOO XUI DCAAMWM 46 Kejdsiq lu ui5 s 2 19128e1eu2 1no Jj pue sq37 54011 4 usng 590 Z Y 2161 406190 20 vdv ogi on wal A Nje N Digilent S3 Board Copyright 2004 Digilent Inc Engineer CC TITLE S3 Board Author GMA Document Number 500 044 Rev E 3 Release Date 12 17 2004 Sheet 2 8 s XNITIX 811 1 482 008 4002 er ABW ELLA OF LON 9S UJOO XUI DCAAMWM p no s sn P eog Wy s s
46. pansion port Port Al supports a maximum of 32 user I O pins while the other ports provide up to 34 user I O pins Some pins are shared with other functions on the board which may reduce the effective I O count for specific applications For example pins on the A1 port are shared with the SRAM address signals with the SRAM OE and WE control signals and with the eight least significant data signals to SRAM IC10 only Spartan 3 Starter Kit Board User Guide www xilinx com 47 UG130 v1 1 May 13 2005 1 800 255 7778 A XILINX Chapter 13 Expansion Connectors and Boards Table 13 1 Expansion Connector Features Connector User I O SRAM JTAG Serial Configuration Parallel Configuration Al 32 Address y OE WE Data 7 0 to IC10 only A2 34 B1 34 d V Each port offers some ability to program the FPGA on the Spartan 3 Starter Kit Board For example port A1 provides additional logic to drive the FPGA and Platform Flash JTAG chain Similarly ports A2 and B1 provide connections for Master or Slave Serial mode configuration Finally port B1 also offers Master or Slave Parallel configuration mode Each 40 pin expansion header shown in Figure 13 2 uses 0 1 inch 100 mil DIP spacing Pin 1 on each connector is always GND Similarly pin 2 is always the 5V DC output from the switching power supply Pin 3 is always the output from the 3 3V DC regulator Pin 39 Pin 3 3 3V Pin 1 GND Pin 39 ma ee
47. rial Mode uhen configuring from the ROM Release Date 12 17 2004 Date 12 17 2004 Sheet 4 8 906150 O vdv oeion 86 I 0 Bank I 0 Bank 1 Solder ed 101 101 102 102 103 103 IO4 VREF_ 104 UREF 1 L 1N_ L 1N_1 L 1P_ L 1P_1 IC8 IC4 S68002DC S68002JF x L27N_ 2 L27N_1 L27P_ L27P_1 L28N_ L28N_1 L28P_ L28P_1 L29N_ L29N_1 170 Bank 2 170 Bank 3 Ee EE 101 101 L30P L3 P_1 L IN 2 LO1N 3 L31N 0 L31N_1 UREF_1 L 1P_2 L 1P_3 L31P_ UREF L31P_1 Lien 2 ES T L16N 3 L16P 2 d L16 L17N 2 L17 L17P 2 UREF 2 L17P 3 URE LION 2 L19 L19P 2 Lig L2 N 2 B 2 L20 L2 P_2 120 L21N_2 L21 L21P_2 L21 L22N 2 L22 L22P_2 L22 n PA A L32P_0 GCLK6 A 2 32N_1 6CLK5 Ha2 DB258 32N_ GCLK7 Ha D I 32P_1 6CLK4 iZ U N R 1 1 0 Bank 4 1 0 Bank 5 101 101 102 102 103 UREF 4 r 103 104 UREF 4 104 UREF 5 L23N 2 UREF 2 L23l T05 UREF 4 L 1N_5 RDWR_B L23P_2 F L23P 3 UREF _ L IN 4 L 1P_5 CS_B L24N_2 L24N_3 e L 1P_4 LI N 5 L24P_2 2 L24P_3 L25N_4 LI P 5 SVEDE UZUZ i WWWWWWWWWWWWW XNHIX Z 8 492 008 1 UJOO XUI DCAAMWM L39P_2 L40N 2 L40P 2 UREF 2 I 0 Bank 6 L39P_3 L4 N_3 UREF L4 P_3 I 0 Bank 7 L27P_4 D1 L28N_4 L28P_4 L29N 4 L29P_4 L3 N_4 D2 L3 P_4 D3 L39N 2 e L39N 3 3 125 4 L27N 5 UREF 5 L27P_5 L28N_5 D6 L28P 5 D7 L29N 5 129 5 5 L3 N 5 L30P 5
48. sent whenever the corresponding key is pressed The scan codes for most keys appear in Figure 6 3 If the key is pressed and held the keyboard repeatedly sends the scan code every 100 ms or so When a key is released the keyboard sends a FO key up code followed by the scan code of the released key The keyboard sends the same scan code regardless if a key has different shift and non shift characters and regardless whether the Shift key is pressed or not The host determines which character is intended Some keys called extended keys send an E0 ahead of the scan code and furthermore they may send more than one scan code When an extended key is released a EO FO key up code is sent followed by the scan code 28 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 Keyboard 3 XILINX Es q Es i E 7 Es ba El 7 7 EA i E 7 Es ba El 7 7 EA E 24 3 4 64 78 2 Pi K ES 7 E 24 26 25 36 3D Pi K ES 7 E Ed EH E E 2 M Md E Pi M E EH EO 6B ET ARNE re 58 1c 1B 23 2B 34 33 3B 42 4B C 52 5A 8072 8 V B N M lt A ch 8 1 E 2A 32 31 3A 41 9 4A Ctrl 14 1 oS O Space Alt Ctrl 11 29 E011 E014 UG130_c6_03_042404 Figure 6 3 PS 2 Keyboard Scan Codes The host can also send data to the keyboard Table 6 3 provides a short list of some often used commands
49. te Start bit Start bit Idle state UG130 c6 04 042404 Figure 6 4 PS 2 Mouse Transaction As shown in Figure 6 5 a PS 2 mouse employs a relative coordinate system wherein moving the mouse to the right generates a positive value in the X field and moving to the left generates a negative value Likewise moving the mouse up generates a positive value in the Y field and moving down represents a negative value The XS and YS bits in the status byte define the sign of each value where a 1 indicates a negative value Y values YS 0 X values X values XS 1 XS 0 Y values YS 1 UG130 c6 05 042404 Figure 6 5 The Mouse Uses a Relative Coordinate System to Track Movement The magnitude of the X and Y values represent the rate of mouse movement The larger the value the faster the mouse is moving The XV and YV bits in the status byte indicate when the X or Y values exceed their maximum value an overflow condition A 1 indicates 30 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 Voltage Supply A XILINX when an overflow occurs If the mouse moves continuously the 33 bit transmissions repeat every 50 ms or so The L and R fields in the status byte indicate Left and Right button presses A 1 indicates that the associated mouse button is being pressed The following site contains additional information on interfacing to a PS 2 style mouse e The PS 2 Mouse
50. ted for each individual segment then 32 pins are required to drive four 7 segment LED characters The scanning technique reduces the required I O down to 12 pins The drawback to this approach is that the FPGA logic must continuously scan data out to the displays a small price to save 20 additional I O pins Spartan 3 Starter Kit Board User Guide www xilinx com 17 UG130 v1 1 May 13 2005 1 800 255 7778 A XILINX Chapter 3 Four Digit Seven Segment LED Display 18 www xilinx com Spartan 3 Starter Kit Board User Guide 1 800 255 7778 UG130 v1 1 May 13 2005 XILINX Chapter 4 Switches and LEDs Slide Switches The Spartan 3 Starter Kit board has eight slide switches indicated as in Figure 1 2 The switches are located along the lower edge of the board toward the right edge The switches are labeled SW7 through SWO Switch SW7 is the left most switch and SWO is the right most switch The switches connect to an associated FPGA pin as shown in Table 4 1 A detailed schematic appears in Figure A 2 Table 4 1 Slider Switch Connections Switch SW7 SW6 SW5 SWA SW3 SW2 SVV1 SWO0 FPGA Pin 13 K14 J13 H4 H13 H14 G12 F12 When in the UP or ON position a switch connects the FPGA pin to Veco a logic High When DOWN or in the OFF position the switch connects the FPGA pin to ground a logic Low The switches typically exhibit about 2 ms of mechanical bounce and there is no acti
51. the signals required to configure the FPGA in Master or Slave Serial mode These same pins plus pins 5 7 9 11 13 15 17 19 and 20 provide the signals required to configure the FPGA in Master or Slave Parallel mode Table 13 4 Pinout for B1 Expansion Connector Schematic Name FPGA Pin Connector FPGA Pin Schematic Name GND VU 5V Vcco 3 3V Veco all banks C10 PB ADRO PB DBO T3 E10 PB ADRI FPGA RD VVR B config PB DB1 N11 C11 PB ADR2 FPGA D1 config PB DB2 P10 D11 PB ADR3 FPGA D2 config PB DB3 R10 C12 PB ADR4 FPGA D3 config PB DB4 T7 D12 PB ADR5 FPGA D4 config PB DB5 R7 E11 PB WE FPGA D5 config PB DB6 N6 B16 PB OE FPGA D6 config PB DB7 M6 R3 PB CS FPGA D7 config FPGA CS_B config PB CLK C15 C16 MB1 DBO MB1 DB1 D15 D16 MB1 DB2 MB1 DB3 E15 E16 MB1 DB4 1 5 15 15 1 6 MB1 DB7 G16 H15 MB1 ASTB MB1 DSTB H16 J16 MB1 WRITE MB1 WAIT K16 K15 MB1 RESET MB1 INT L15 B3 PROG B FPGA PROG_B DONE R14 N9 INIT FPGA DONE FPGA INIT_B CCLK T15 M11 DIN FPGA CCLK Connects to A14 via 390Q resistor Spartan 3 Starter Kit Board User Guide www xilinx com 51 UG130 v1 1 May 13 2005 1 800 255 7778 3 XILINX Chapter 13 Expansion Connectors and Boards Expansion Boards Various expansion boards plug into th
52. tile data or application code storage available after FPGA configuration Jumper options allow FPGA application to read PROM data or FPGA configuration from other sources 1M byte of Fast Asynchronous SRAM bottom side of board see Figure 1 3 2 Two 256Kx16 ISSI IS61LV25616AL 10T 10 ns SRAMs Configurable memory architecture Single 256Kx32 SRAM array ideal for MicroBlaze code images Two independent 256Kx16 SRAM arrays Individual chip select per device 9 9 Individual byte enables 3 bit 8 color VGA display port 9 pin RS 232 Serial Port 6 DB99 pin female connector DCE connector RS 232 transceiver level translator Uses straight through serial cable to connect to computer or workstation serial port Second RS 232 transmit and receive channel available on board test points 8 Spartan 3 Starter Kit Board User Guide www xilinx com 7 UG130 v1 1 May 13 2005 1 800 255 7778 A XILINX Chapter 1 Introduction Digilent Low Cost 23 Parallel Port to JTAG Included Cable Parallel Cable IV 64 Low Cost JTAG 22 MutliPro Desktop Tool Download Cable JTAG Connector Connector A1 Expansion Header XCFO S 2Mbit SPARTAN 3 Configuration A2 Expansion go o 2 Header B1 Expansion 9 Header 256Kx16 Configuration 18 10ns SRAM DONE LED Ons yx XILINX Push Button 8 color XC3S200 Configuration VGA Port Spartan 3 Mode Select FPGA Jumpers 6 RS 23
53. ve debouncing circuitry although such circuitry could easily be added to the FPGA design programmed on the board A 4 7KQ series resistor provides nominal input protection Push Button Switches The Spartan 3 Starter Kit board has four momentary contact push button switches indicated as in Figure 1 2 These push buttons are located along the lower edge of the board toward the right edge The switches are labeled BTN3 through BTNO Push button switch BTN3 is the left most switch BTNO the right most switch The push button switches connect to an associated FPGA pin as shown in Table 4 2 A detailed schematic appears in Figure A 2 Table 4 2 Push Button Switch Connections Push Button BTN3 User Reset BTN2 BTN1 BTNO FPGA Pin L14 L13 M14 M13 Pressing a push button generates a logic High on the associated FPGA pin Again there is no active debouncing circuitry on the push button The left most button BTN3 is also the default User Reset pin BTN3 electrically behaves identically to the other push buttons However when applicable BTN3 resets the provided reference designs Spartan 3 Starter Kit Board User Guide www xilinx com 19 UG130 v1 1 May 13 2005 1 800 255 7778 A XILINX Chapter 4 Switches and LEDs LEDs The Spartan 3 Starter Kit board has eight individual surface mount LEDs located above the push button switches indicated by in Figure 1 2 The LEDs are labeled LED7 through LEDO LED
54. vices shown or products described herein are free from patent infringement or from any other third party right Xilinx Inc assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made Xilinx Inc will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user Xilinx products are not intended for use in life support appliances devices or systems Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited The contents of this manual are owned and copyrighted by Xilinx Copyright 1994 2004 Xilinx Inc All Rights Reserved Except as stated herein none of the material may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of any material contained in this manual may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes Some portions reproduced by permission from Digilent Inc Spartan 3 Starter Kit Board User Guide UG130 v1 1 May 13 2005 The following table shows the revision history for this document Version Revision 04
55. y pass pixel 0 639 640 pixels are displayed each time the beam traverses the screen VGA Display Retrace No information pixel 479 0 pixel 479 639 is displayed during this time Stable current ramp Information is displayed during this time Total horizontal time DUC Horizontal display time retrace time Te E gt D back porch b back porch si eS Horizontal sync signal L front porch sets the retrace frequency UG130 c5 02 051305 Figure 5 2 CRT Display Timing Example The size of the beams the frequency at which the beam traces across the display and the frequency at which the electron beam is modulated determine the display resolution Spartan 3 Starter Kit Board User Guide www xilinx com 23 UG130 v1 1 May 13 2005 1 800 255 7778 Chapter 5 VGA Port Modern VGA displays support multiple display resolutions and the VGA controller dictates the resolution by producing timing signals to control the raster patterns The controller produces TTL level synchronizing pulses that set the frequency at which current flows through the deflection coils and it ensures that pixel or video data is applied to the electron guns at the correct time Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location The Spartan 3 Starter Kit board uses three bits per pixel producing one of the eight possible colors shown in Table
56. y an odd parity bit and terminated with a 1 stop bit When the keyboard sends data it generates 11 clock transitions at around 20 to 30 kHz and data is valid on the falling edge of the clock as shown in Figure 6 2 Spartan 3 Starter Kit Board User Guide www xilinx com 29 UG130 v1 1 May 13 2005 1 800 255 7778 A XILINX Chapter 6 PS 2 Mouse Keyboard Port The following site contains more information on PS 2 keyboard interfaces e The AT PS 2 Keyboard Interface http panda cs ndsu nodak edu achapwes PICmicro keyboard atkeyboard html Mouse A mouse generates a clock and data signal when moved otherwise these signals remain High indicating the Idle state Each time the mouse is moved the mouse sends three 11 bit words to the host Each of the 11 bit words contains a 0 start bit followed by 8 data bits LSB first followed by an odd parity bit and terminated with a 1 stop bit Each data transmission contains 33 total bits where bits 0 11 and 22 are 0 start bits and bits 10 21 and 32 are 1 stop bits The three 8 bit data fields contain movement data as shown in Figure 6 4 Data is valid at the falling edge of the clock and the clock period is 20 to 30 KHz Mouse status byte m X direction byte Y direction byte Lal ale i xsiysixv vvl e 1 o feolxi xe x lxd sixelxr P 1 o volvi velva val vs ve vz P NN 7 v Start bit Stop bit Stop bit Stop bit Idle sta
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