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Universe II User Manual - AGATA Experiment @ Padova

1. Integrated Device Technology Universe II User Manual www idt com May 12 2010 342 B Performance gt VME Slave Channel B 3 1 3 Write Cycles Coupled writes in the VME Slave Channel operate in a similar fashion to the coupled reads The VME slave response is directly linked to the response of the PCI target In generating the request to the PCI bus coupled write cycles require one further clock over reads Hence during single cycles or the first beat of a BLT the time from AS to REQ_ asserted is 3 4 PCI clocks while DS to REQ_ is 3 clocks for the data beat portion of a block transfer If the PCI bus is parked at the Universe II REQ_ is not asserted and the transaction begins immediately with assertion of FRAME_ As with reads the response from the PCI target s assertion of TRDY_ to DTACK assertion by the Universe II adds one clock to the transfer Figure 33 shows a typical non block coupled write cycle Because write cycles on the PCI bus require one less clock than reads due to the absence of the turn around phase between address and data phases the overall slave response during coupled writes works out to the same as coupled reads against an identical target In accessing a zero wait state PCI target the Universe II s coupled write slave response then is approximately 10 PCI clocks During subsequent data beats of a bloc
2. A B Cc D E F G H J K L M N p R Ej U V w AA AB AC AD AE 1 vd 22 vd 19 vd 9 vd 5 VDD int 7 vss Irst_ vrbr 1 ad 27 ad 58 PLL_ AVSS 1 testsel 2 vd 18 vd 14 vd 13 vd 6 vd 2 vscon_ vxbbsy ad 61 ad 59 ad 24 PLL_ VDD 2 DIR testout 3 vd 23 vd 21 vd 20 vd 12 vd 3 int 5 vbelr_ vrbr_ 2 VDD ad 57 Icik VDD vcoctl 3 4 vd 26 VDD vd 15 vd 11 vd 4 int 4 vss pwrrst_ ad 25 ad 56 perr_ ad 22 4 5 vd 30 vd 24 VDD vq 17 vd 8 VDD ad 63 ad 60 ad 26 vrbr 0 int 1 AVDD par64 5 6 vd 27 vd 25 vd 16 vd 10 vq 7 vrbbsy ad 30 vss int 3 ad 23 ad 55 vss 6 7 vrberr_ vd 28 viack_ VDD vd 0 vrbr 3 vsysclk VDD ad 28 VDD serr_ devsel_ ad 20 7 8 am DIR vwrite vd 29 VDD vd 1 int 6 par ad 29 VDD ad 21 ad 54 trdy_ 8 9 vam 5 VDD vd 31 vam 2 VDD int 2 vss ad 62 VDD ad 18 ad 53 vss VDD 9 10 vam 3 vam 1 vd DIR vam 4 vss vxsysfail ad 31 VDD ad 51 vss ad 52 ad 19 10 11 vds 1 ims vam 0 VDD vds DIR vss vss vss vss ack64_ VDD ad 50 ad 16 1 12 voe vxberr vds_ 0 ick lvas DIR vss vss cbe 6 ad 48 ad 49 ad 17 cbe 7 12 13 tdi tdo trst_ va_DIR vss vss vss vss vss cbe 3 itmode 0 rsysfail vss 13 14 vas_ va 5 va 3 va i viword_ vss vss cbe 2 cbe 1 cbe 0 vss cbe 5 14 15 va 2 vslave D VDD vdtack va 4 vss vss vss ad 15 VDD ad 14 irdy_ cbe 4 15 IR 16 va 8 va 10 va 13 va 7 vss vbgi 1 ad 0 vss vrirq 5 vss idsel ad 47 16 17 VDD va 9 va 14 va 6 VDD ad 32 vss
3. pt Universe II User Manual May 12 2010 350 B 5 B 5 1 B 5 2 B 5 2 1 B 5 2 2 B 5 2 3 B Performance gt Universe Il Specific Register Universe Il Specific Register The Universe II Specific Register U2SPEC offset OxAFC can be used to improve the performance of the Universe II by reducing the latency of key VMEbus timing elements This register is present in versions of the Universe device which have a Revision ID of Olor 02 defined in the PCI CLASS register offset 008 Overview of the U2SPEC Register Although the VMEbus is asynchronous there are a number of maximum and minimum timing parameters which must be followed These requirements are detailed in the VME64 Specification In order to qualify as compliant the master slave and location monitor devices must guarantee they meet these timing parameters independent of their surroundings They must assume zero latency between themselves and the VMEbus This in practice is never the case Buffers transceivers and the backplane itself all introduce latencies that combine to produce additional system delay The consequence of such delay is the de
4. Integrated Device Technology Universe II User Manual www idt com May 12 2010 314 12 Registers gt Register Description 12 3 4313 VMEbus Slave Image 5 Control VSI5 CTL This register provides the general VMEbus and PCI controls for this slave image Note that only transactions destined for PCI Memory space are decoupled the posted write RXFIFO generates on Memory space transactions on the PCI Bus In order for a VMEbus slave image to respond to an incoming cycle the BM bit in the PCI_CSR register must be enabled The state of PWEN and PREN are ignored if LAS is not programmed memory space Register name VSI5_CTL Register offset OXFA4 15 08 Reserved Image Enable PWR VME 0 Disable 1 Enable Posted Write Enable PWR VME 0 Disable 1 Enable R W PWR VME 0 Disable 1 Enable Program Data AM Code R W PWR VME 11 00 Reserved 01 Data 10 Program 11 Both Supervisor User AM Code PWR VME 00 Reserved Universe Il User Manual Integrated Device Technology May 12 2010 www idt com Prefetch Read Enable 01 Non Privileged 10 Supervisor 11 Both 12 Registers gt Register Description 315 VAS VMEbus Address Space R W PWR VME 000 Reserved 001 A24 010 A32 011 Reserved 100 Reserved 101 Reserved 110 User1 111 User2 LD64EN Enable 64 bit PCI Bus Transactions R W PWR VME 0 Disable 1 Enable LLRMW Enable PCI Bus Lock of VMEbus RMW R W PWR VME 0 Disable 1 Enable LAS PCI Bus Address Space R W PWR VME 0
5. Table 35 Power up Option Behavior of the VAS field in VRAI CTL Power up Option VA 28 25 Power up Option VA 28 21 Power up Option VA 28 21 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 305 12 3 105 VMEbus CSR Control Register VCSR CTL Register name VCSR_CTL Register offset OXF80 9m 24 Reserved Hd 6 Reserved 15 08 Reserved 07 00 Reserved Image Enable PWR VME The EN bit is set to a value of 1 whenever a VME64 monarch acquires the Status ID vector for the level 2 interrupt during VME64 Auto ID 0 Disable 1 Enable PCI Bus Address Space PWR VME 00 PCI Bus Address Space 01 PCI Bus I O Space Integrated Device Technology Universe II User Manual www idt com May 12 2010 306 12 Registers gt Register Description 12 3 106 VMEbus CSR Translation Offset VCSR TO For CSR s not supported in the Universe II and for CR accesses the translation offset is added to the 24 bit VMEbus address to produce a 32 bit PCI Bus address Register name VCSR TO Register offset OXF84 Reserved Reserved R W TO 31 24 Translation Offset PWR VME po TO 23 19 Translation Offset R W PWR VME Power up Option Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 307 12 3 107 VMEbus AM Code Error Log V_AMERR The Universe II VMEbus Master Interface i
6. When an external VMEbus Master begins a RMW cycle at some point a read cycle appears on the PCI bus During the time between when the read cycle occurs on the PCI bus and when the associated write cycle occurs on the PCI bus no DMA transfers occurs on the PCI bus 2 4 6 Register Accesses See Registers on page 163 for a full description of register mapping and register access Integrated Device Technology Universe Il User Manual www idt com May 12 2010 38 2 4 7 2 4 8 2 VMEbus Interface gt Universe Il as VMEbus Slave Location Monitors Universe II has four location monitors to support a VMEbus broadcast capability The location monitors image is a 4 Kbyte image in A16 A24 or A32 space on the VMEbus If enabled an access to a location monitor causes the PCI Master Interface to generate an interrupt The Location Monitor Control Register LM_CTL on page 300 controls the Universe II s location monitoring The EN field of the LM_CTL register enables the capability The PGM 1 0 field sets the Program Data AM code The SUPER 1 0 field of the LM_CTL register sets the Supervisor User AM code to which the Universe II responds The VAS 3 0 field of the LM_CTL register specifies the address space that is monitored The BS 31 12 field of the Location Monitor Base Address Register LM_BS on page 302 specifies the lowest address in the 4 Kbyte range that is decoded as a location monitor access While the Universe
7. B 4 2 1 B 4 2 2 B 4 3 B Performance gt DMA Channel and Relative FIFO Sizes When programmed for Release When Done operation the Universe II will perform an early release of BBSY when the VON counter reaches its programmed limit This gives other masters a chance to use the VMEbus and possibly access the VME Slave Channel but may decrease performance of the DMA Channel this factor may also play in favor of the DMA Channel by pausing the PCI Target Channel s use of the VMEbus Read Transfers When performing non block reads on the VMEbus the Universe II cycle time AS to next AS is approximately 209ns which translates to about 20 MB s when performing D32 transfers For block transfers the cycle time DS to next DS falls to about 156ns or 25 MB s for D32 transfers For multiplexed block transfers MBLTS the cycle time remains the same but because the data width doubles the transfer rate increases to about 5OMB s Write Transfers Non block writes to the VMEbus occur at 180ns cycle time AS to next AS or 23MB s during D32 transfers Block writes however are significantly faster with a 116ns cycle time DS to next DS or 36 MB s Multiplexed block transfers have slightly longer cycle times at about 112ns DS to next DS or 62 MB s with D64 MBLTs PCI Transfers As a master on the PCI bus the Universe II DMA follows the same general set of rules as the VME Slave channel does it never inserts any wait st
8. Posted writes are enabled for a PCI target image by setting the PWEN bit in the control register of the PCI target image see PCI Bus Target Images on page 70 to 1 and setting the LAS bit to 0 Write transactions are relayed from the PCI bus to the VMEbus through a 64 entry deep TXFIFO The TXFIFO allows each entry to contain 32 address bits with extra bits provided for command information or to a full 64 bit width For each posted write transaction received from the PCI bus the PCI Target Interface queues an address entry in the FIFO This entry contains the translated address space and mapped VMEbus attributes information relevant to the particular PCI target image that has been accessed see PCI Bus Target Images on page 70 For this reason any reprogramming of PCI bus target image attributes will only be reflected in TXFIFO entries queued after the reprogramming Transactions queued before the re programming are delivered to the VMEbus with the PCI bus target image attributes that were in use before the reprogramming Care must be taken before reprogramming target images To ensure the FIFO is empty use one of the following options e Perform a coupled read The coupled read does not complete until all posted write data has been queued Read the MISC STAT register until the TXFE bit has a value of 0 FIFO Entries Once the address phase is queued in one TXFIFO entry the PCI Target Interface may pack the subsequent data be
9. Power Up Options on page 135 this bit has have no effect If powered up on a 64 bit bus this bit can provide some performance improvements when accessing 32 bit targets on that bus Following the PCI 2 1 Specification before a 64 bit PCI initiator starts a 64 bit transaction it engages in a protocol with the intended target to determine if it is 64 bit capable This protocol typically consumes one clock period To save bandwidth the LD64EN bit can be cleared to bypass this protocol when it is known that the target is only 32 bit capable DMA Command Packet Pointer The DMA Command Packet Pointer DCPP on page 237 points to a 32 byte aligned address location in PCI Memory space that contains the next command packet to be loaded once the transfer currently programmed into the DMA registers has been successfully completed When it has been completed or the DTBC register is 0 when the GO bit is set the DMA reads the 32 byte command packet from PCI memory and executes the transfer it describes DMA Control and Status DMA General Control Status Register DGCS on page 238 contains a number of fields that control initiation and operation of the DMA as well as actions to be taken on completion DMA Initiation Once all the parameters associated with the transfer have been programmed source destination addresses transfer length and data widths and if desired linked lists enabled the DMA transfer is started by setting the GO b
10. Thermal Vias Table 41 shows the simulated Psi jt and Theta jc thermal characteristics of the Universe II package Table 41 Thermal Characteristics of Universe Il Interface Result Psi jt 0 25 C watt Theta jc junction to case 4 7 C watt These values were obtained under the following PCB and environmental conditions e PCB condtionsMaximum junction PCB standard JEDEC JESD51 9 PCB layers 4 PCB dimensions 101 6 mm x 114 3 mm PCB thickness 1 6 mm e Environmental conditions Maximum junction temperature 125 C Ambient temperature 70 C Power dissipation 3 W Thermal Vias The 313 pin plastic BGA package contains thermal vias which directly pipe heat from the die to the solder balls on the underside of the package The solder balls use the capabilities of the power and ground planes of the printed circuit board to draw heat out of the package Universe Il User Manual Integrated Device Technology May 12 2010 www idt com D 1 D 2 359 Endian Mapping Universe II has Little endian mapping Little endian refers to a method of formatting data where address 0 or the smallest address referencing the data points to the least significant byte of the data Data in a system must be consistent that is the system must be entirely big endian or little endian This chapter discusses the following topics e Little endian Mode on page 359 Overview Th
11. VMEbus Configuration and Status Registers VCSR UNIVERSE DEVICE SPECIFIC REGISTERS 4 Kbytes UCSR Space UDSR PCI CONFIGURATION SPACE PCICS 5 2 Register Access from the PCI Bus There are different mechanisms to access the UCSR space from the PCI bus Configuration space PCI Memory or I O space 5 2 1 PCI Configuration Access When the UCSR space is accessed as Configuration space it means that the access is externally decoded and the Universe II is notified through IDSEL much like a standard chip select signal Since the register location is encoded by a 6 bit register number a value used to index a 32 bit area of Configuration space only the lower 256 bytes of the UCSR can be accessed as Configuration space this corresponds to the PCICS in the UCSR space see Figure 12 on page 77 Only the PCI configuration registers are accessible through PCI Configuration cycles Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 5 Registers Overview gt Register Access from the PCI Bus 5 2 2 Figure 12 PCI Bus Access to UCSR as Memory or I O Space Accessible through PCI Configuration Cycle VMEbus Configuration and Status Registers VCSR UNIVERSE DEVICE SPECIFIC REGISTERS UDSR PCI CONFIGURATION SPACE PCICS Memory or I O Access All 4 Kbytes Accessible as Memory or I O Space PCI BS 4 Gbytes of Memory or I O Space Y 77
12. c M n P M A AS A p f DBO OOOO OOU WRITE voo PF osi LH M D DTACK eee FRAME LY LI LIT LT LI OT LT LOIT LIT LOT LIT L ONT LI LOT LN L avro a maT C BE 3 0 m OTTS IRDY TRDY DEVSEL B 2 2 B 2 2 1 Decoupled Cycles Only write transactions can be decoupled in the PCI Target Channel Effect of the PWON Counter The Posted Write On Counter PWON in the MAST_CTL register controls the maximum tenure that the PCI Slave Channel will have on the VMEbus Once this channel has gained ownership of the VMEbus for use by the TXFIFO it only relinquishes it if the FIFO becomes empty or if the number of bytes programmed in the counter expires In most situations the FIFO empties before the counter expires However if a great deal of data is being transferred by a PCI initiator to the VMEbus then this counter ensures that only a fixed amount of VME bandwidth is consumed Limiting the size of the PWON counter imposes greater arbitration overhead on data being transferred out from the FIFO This is true even when programmed for ROR mode since an internal arbitration cycle will still occur The value for the PWON counter must be weighed from the system perspective with the impact of imposing greater latency on other channels the DMA and Interrupt Channels and other VME masters in gaining ownership of the VMEbus On a Universe II equipped
13. 202 12 Registers gt Register Description 12 3 25 Special Cycle PCI Bus Address Register SCYC ADDR This register designates the special cycle address This address must appear on the PCI Bus during the address phase of a transfer for the Special Cycle Generator to perform its function Whenever the addresses match the Universe II does not respond with ACK64 Register name SCYC ADDR Register offset 0x174 9124 24 ADDR Ea ADDR 15 08 ADDR Reset Description Type Reset by value Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 203 12 3 26 Special Cycle Swap Compare Enable Register SCYC_EN The bits enabled in this register determine the bits that are involved in the compare and swap operations for VME RMW cycles Register name SCYC_EN Register offset 0x178 07 00 Reset Description Type Reset by value 31 00 EN Bit Enable R W All 0x00 0 Disable 1 Enable Integrated Device Technology Universe II User Manual www idt com May 12 2010 204 12 Registers gt Register Description 12 3 27 Special Cycle Compare Data Register SCYC_CMP The data returned from the read portion of a VMEbus RMW is compared with the contents of this register SCYC_EN is used to control which bits are compared Register name SCYC_CMP Register offset 0x17C Reset Description Type Reset by value CMP The data returned from the VMEbus is compared with R W
14. E F 4 L LL sd J N via x N E To i ur 4 00 45 4 EF 1 EF M 0 56 REF Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 335 B Performance This chapter discusses the following topics e PCI Slave Channel on page 336 e VME Slave Channel on page 340 e Decoupled Cycles on page 342 e DMA Channel and Relative FIFO Sizes on page 347 e Universe II Specific Register on page 350 e Performance Summary on page 352 B 1 Overview As a VMEbus bridge the Universe II s most important function is data transfer This function is performed by its three channels the PCI Slave Channel the VME Slave Channel and the DMA Channel Since each channel operates independently of the others and because each has its own unique characteristics the following analysis reviews the data transfer performance for each channel e PCI Slave Channel on page 336 e VME Slave Channel on page 340 e DMA Channel and Relative FIFO Sizes on page 347 e Performance Summary on page 352 Where relevant descriptions of factors affecting performance and how they might be controlled in different environments are discussed The decoupled nature of the Universe II can cause some confusion in discussing performance parameters This is because in a fully decoupled bus bridge each of the two opposing buses operates at its peak performance indepen
15. IDT Universe IID IIB User Manual May 12 2010 6024 Silver Creek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2009 Integrated Device Technology Inc GENERAL DISCLAIMER Integrated Device Technology Inc reserves the right to make changes to its products or specifications at any time without notice in order to improve design or performance and to supply the best possible product IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent patent rights or other rights of Integrated Device Technology Inc CODE DISCLAIMER Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications Any use of the code examples below is completely at your own risk IDT MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE NONINFRINGEMENT QUALITY SAFETY OR SUITABILITY OF THE CODE EITHER EXPRESS OR IMPLIED INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICU LAR PURPOSE OR NON INFRINGEMENT FURTHER IDT MAKES NO REPRESENTATIONS OR WARRANTIES AS TO THE TRUTH ACCURACY
16. Universe II as VME Master Figure 29 Coupled Write Cycle Universe I as VME Master eese Figure 30 Several Non Block Decoupled Writes Universe II as VME Master Figure 31 BLT Decoupled Write Universe II as VME Master 0000 Figure 32 Coupled Read Cycle Universe II as VME Slave 0 00 00 000005 Figure 33 Coupled Write Cycle Universe II as VME Slave bus parked at Universe II Figure 34 Non Block Decoupled Write Cycle Universe II as VME Slave Figure 35 BLT Decoupled Write Cycle Universe Il as VME Slave Figure 36 MBLT Decoupled Write Cycle Universe II as VME Slave Figure 37 BLT Pre fetched Read Cycle Universe Il as VME Slave 00 Figure 38 PCI Read Transactions During DMA Operation 0 0000000 Figure 39 Multiple PCI Read Transactions During DMA Operation Figure 40 Universe II Connections to the VMEbus Through TTL Buffers Figure 41 Universe II Connections to the VMEbus Through TTL Buffers Figure 42 Power up Configuration Using Passive Pull ups 00000 Integrated Device Technology www idt com Universe II User Manual May 12 2010 Figures 10 Figure 43 Power up Configuration Using Active Circuitry 0 0 0 ec cece 368 Figure 44 Analog Isolation Scheme ee e ea eo ses St ah eee E
17. resets the Reset VMEbus PCI Input PWRRST Power up Reset Resets the Universe ll and re configures power up options PCI Reset Input Resets the Universe II from the PCI bus VME_ VMEbus Reset Causes Universe II to assert VXSYSRST RESET_ Initiator PCI Output LRST_ PCI Bus Reset Resets PCI resources Output JTAG Input TRST JTAG Test Reset Provides asynchronous initialization of the TAP controller in the Universe ll a A more detailed account of the effects of reset signals is provided in Reset Implementation Cautions on page 133 Integrated Device Technology Universe II User Manual www idt com May 12 2010 130 9 Resets Clocks and Power up Options gt Resets The Universe II is only reset through hardware Software can make the Universe II assert its reset outputs In order to reset the Universe II through software the Universe II reset outputs must be connected to the Universe II reset inputs For example the SW_LRST bit in the MISC_CTL register which asserts the LRST_ output does not reset the Universe II itself unless LRST_ is looped back to RST_ As described in Reset Implementation Cautions on page 133 there are potential loopback configurations resulting in permanent reset Table 20 Software Reset Mechanism Master SW_LRST Control Register MAST_CTL on page 271 VMEbus CSR RESET Bit Set Register VCSR_SET on page 330 Universe Il User Manual May 12 2010 Function Softwar
18. www idt com Figure 20 shows the sources of interrupts and the interfaces from which they originate Figure 20 Sources of Internal Interrupts PCI Bus VMEbus Interface Interface VMEbus Slave Channel PCI posted writes FIFO Master prefetch read FIFO coupled path DMA Channel DMA bidirectional FIFO PCI Bus Slave Channel posted writes FIFO VME D coupled read logic Master Interrupt Channel Interrupt Handler 119 Universe Il User Manual May 12 2010 120 7 3 3 1 7 Interrupt Generation and Handling gt Interrupt Handling VMEbus and PCI Software Interrupts It is possible to interrupt the VMEbus and the PCI bus through software These interrupts may be triggered by writing a to the respective enable bits Interrupting the VMEbus Through Software The following methods trigger software interrupts on the VMEbus 1 The first method for interrupting the VMEbus through software involves writing 1 to one of the SW INTT7 1 bits in the VINT_EN register while the mask bit is 0 This causes an interrupt to be generated on the corresponding IRQ7 1 line For example setting the SW_INT1 bit triggers VXIRQI setting the SW_INT2 bit triggers VXIRQ2 etc 2 The second method for interrupting the VMEbus through software involves an extra step Writing a 1 to the SW INT bit in the VMEbus Interrupt Enable Register VINT_EN on page 248 when this bit is O triggers one interrupt on the VMEbus on
19. 2010 212 12 Registers gt Register Description 12 3 33 PCI Target Image 4 Control Register LSI4_CTL In the PCI Target Image Control register setting the VCT bit will only have effect if the VAS bits are programmed for A24 or A32 space and the VDW bits are programmed for 8 bit 16 bit or 32 bit If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64 bit the Universe II may perform MBLT transfers independent of the state of the VCT bit The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I O Space forcing all transactions through this image to be coupled Register name LSI4_CTL Register offset 0x1A0 MARA RA ese wees we ee vee ees orm ee V A 07 00 Reserved Image Enable 0 Disable 1 Enable Posted Write Enable 0 Disable 1 Enable VMEbus Maximum Datawidth 00 8 bit data width 01 16 bit data width 10 32 bit data width 11 64 bit data width VMEbus Address Space 000 A16 001 A24 010 A32 011 Reserved 100 Reserved 101 CR CSR 110 User1 111 User2 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 213 Program Data AM Code 0 Data 1 Program SUPER Supervisor User AM Code 0 Non Privileged 1 Supervisor VMEbus Cycle Type 0 no BLTs on VMEbus PCI Bus Memory Space 0 PCI Bus Memory Space 1 PCI Bus I O Space Bd 1 BLTs on VMEbus Integrated Device Technology Univ
20. 2010 www idt com 12 Registers gt Register Description 173 Description Reset by DEVSEL Device Select Timing The Universe ll is a medium speed device Master Data Parity Error R Write 1 The Universe Il PCI master interface sets this bit if to Clear the Parity Error Response bit is set if itis the master of transaction in which it asserts PERR or the addressed target asserts PERR 0 Master did not detect generate data parity error 1 Master detected generated data parity error Target Fast Back to Back Capable Universe II cannot accept Back to Back cycles from a different agent Reserved Reserved E MFBBC Master Fast Back to Back Enable The Universe II master never generates fast back to back transactions OzNo fast back to back transactions SERR EN SERR Enable Setting this and PERESP allows the Universe II PCI target interface to report address parity errors with SERR 0 Disable SERR driver 1 Enable SERR_ driver Note The Universe II only refuses PCI addresses with parity errors when both the PERESP and SERR_EN bits are programmed to a value of 1 Wait Cycle Control 0 No address data stepping PERESP Parity Error Response Controls the Universe ll response to data and address parity errors When enabled it allows the assertion of PERR to report data parity errors When this bit and SERR EN are asserted the Universe II can report address parity errors on SERR Universe Il parity generation is un
21. About this Document Scope This section discusses the following topics e Scope on page 13 e Document Conventions on page 13 e Revision History on page 15 The Universe IID IIB User Manual discusses the features capabilities and configuration requirements for the Universe II It is intended for hardware and software engineers who are designing system interconnect applications with the device Document Conventions This document uses the following conventions Signal Notation Signals are either active high or active low Active low signals are defined as true asserted when they are at a logic low Similarly active high signals are defined as true at a logic high Signals are considered asserted when active and negated when inactive irrespective of voltage levels For voltage levels the use of 0 indicates a low voltage while a indicates a high voltage For voltage levels the use of 0 indicates a low voltage while a 1 indicates a high voltage For voltage levels the use of 0 indicates a low voltage while a indicates a high voltage Each signal that assumes a logic low state when asserted is followed by an underscore sign For example SIGNAL is asserted low to indicate an active low signal Signals that are not followed by an underscore are asserted when they assume the logic high state For example SIGNAL is asserted high to indicate an active high signal The asterisk sign is used in this manua
22. Control LSIO_CTL on page 181 For example consider a 32 bit PCI transaction accessing a PCI target image with VDW set to 16 bits A data beat with all byte lanes enabled will be broken into two 16 bit cycles on the VMEbus If the PCI target image is also programmed with block transfers enabled the 32 bit PCI data beat will result in a D16 block transfer on the VMEbus Write data is unpacked to the VMEbus and read data is packed to the PCI bus data width If the data width of the PCI data beat is the same as the maximum data width of the PCI target image then the Universe II maps the data beat to an equivalent VMEbus cycle For example consider a 32 bit PCI transaction accessing a PCI target image with VDW set to 32 bits A data beat with all byte lanes enabled is translated to a single 32 bit cycle on the VMEbus If the PCI bus data width is less than the VMEbus data width then there is no packing or unpacking between the two buses The only exception to this is during 32 bit PCI multi data beat transactions to a PCI target image programmed with maximum VMEbus data width of 64 bits In this case packing unpacking occurs to make maximum use of the full bandwidth on both buses Only aligned VMEbus transactions are generated so if the requested PCI data beat has unaligned or non contiguous byte enables then it is broken into multiple aligned VMEbus transactions no wider than the programmed VMEbus data width For example consider a three byte P
23. DMA Active Status Bit 0 Not Active 1 Active DMA Stopped Status Bit R Write 1 to 0 Not Stopped Clear 1 Stopped DMA Halted Status Bit R Write 1 to 0 Not Halted Clear 1 Halted DMA Done Status Bit R Write 1 to 0 Not Complete Clear 1 Complete DMA PCI Bus Error Status Bit R Write 1 to O No Error Clear 1 Error DMA VMEbus Error Status Bit R Write 1 to O No Error Clear 1 Error DMA Programming Protocol Error Status Bit R Write 1 to Asserted if PCI master interface disabled or lower three bits of Clear PCI and VME addresses differ O No Error 1 Error Integrated Device Technology Universe Il User Manual www idt com May 12 2010 240 12 Registers gt Register Description INT_STOP Interrupt when Stopped 0 Disable 1 Enable Interrupt when Halted 0 Disable 1 Enable Interrupt when Done R W 0 Disable 1 Enable Interrupt on LERR W 0 Disable 1 Enable Interrupt on VERR 0 Disable 1 Enable Interrupt on Master Enable Error R 0 Disable 1 Enable STOP HALT DONE LERR VERR and P ERR must be cleared before the GO bit is enabled MM ibe WM d INN BE Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 241 12 3 55 DMA Linked List Update Enable Register D_LLUE The PCI Resource must read back a logic 1 in the UPDATE field before proceeding to modify the linked list After the Linked List has been modified the PCI Resource must clear the
24. DTBC register is 0 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 6 DMA Controller gt DMA Registers 87 6 2 2 6 2 2 1 6 2 2 2 Non incrementing DMA Mode The VMEbus Non Incrementing Mode Non Inc Mode enables the DMA Controller to perform transfers to or from a fixed VMEbus address This means that the specified VMEbus address is not incremented during DMA reads or writes This applies to both Direct and Linked List modes of DMA operation For more information on these two types of DMA operation refer to Direct Mode Operation on page 93 and Linked list Mode on page 96 Unlike incrementing DMA operation in Non Inc Mode the DMA Controller can only perform 8 16 or 32 bit single cycle transfers on the VMEbus This means that BLT and MBLT transfers cannot be performed when operating in Non Inc Mode Using Non Inc Mode The VMEbus Non Inc Mode is enabled by writing a 1 to the NO_VINC bit in the DMA Transfer Control Register DCTL on page 232 In order to set up and initiate DMA operation the same steps which are described in the DMA Controller Section in the Universe II User Manual must be followed for Non Inc Mode The steps in setting up and initiating DMA operation are as follows 1 Program the tenure and interrupt requirements in the DGCS register offset 0x220 2 Program the source and destination addresses in the DLA and DVA registers 3 Setthe GO bit in the DG
25. MBOX2 MBOX1 MBOX0 E E EN SW INT a pa Eu LERR LIES IACK 07 00 VIRQ7 VIRQ6 VIRQ5 VIRQ4 VIRQ3 VIRQ2 VIRQ1 VOWN Location Monitor 3 0 LM3 Interrupt Disabled 12LM3 Interrupt Enabled Location Monitor 2 0 LM2 Interrupt Disabled 1 LM2 Interrupt Enabled Location Monitor 1 0 LM1 Interrupt Disabled 1 LM1 Interrupt Enabled Location Monitor 0 O LMO Interrupt Disabled 12LMO Interrupt Enabled Mailbox 3 0 MBOX3 Interrupt Disabled 1 MBOXS3 Interrupt Enabled Mailbox 2 0 MBOXz2 Interrupt Disabled 1 MBOX2 Interrupt Enabled Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 243 MBOXO ACFAIL SYSFAIL SW INT SW IACK VERR LERR VIRQ7 VIRQ1 VOWN Mailbox 1 0 MBOX1 Interrupt Disabled 1 MBOxX1 Interrupt Enabled Mailbox 0 0 MBOXO Interrupt Disabled 12MBOXO Interrupt Enabled ACFAIL Interrupt O ACFAIL Interrupt Disabled 1 ACFAIL Interrupt Enabled SYSFAIL Interrupt 0 SYSFAIL Interrupt Disabled 1 SYSFAIL Interrupt Enabled Local Software Interrupt O PCI Software Interrupt Disabled 1 PCI Software Interrupt Enabled A zero to one transition will cause the PCI software interrupt to be asserted Subsequent zeroing of this bit will cause the interrupt to be masked but will not clear the PCI Software Interrupt Status bit VME Software IACK 0 VME Software IACK Interrupt Disabled 1 VME Software IACK Interrupt Enabled PCI
26. MBOX3 Mailbox 3 Mask 0 MBOX3 Interrupt masked 1 MBOXS3 Interrupt enabled MBOX2 Mailbox 2 Mask 0 MBOXz2 Interrupt masked 1 MBOXz2 Interrupt enabled MBOX1 Mailbox 1 Mask O MBOX1 Interrupt masked 1 MBOX1 Interrupt enabled MBOXO Mailbox 0 Mask 0 MBOXO Interrupt masked 1 MBOXO Interrupt enabled SW INT VME Software Interrupt Mask 0 VME Software Interrupt masked 1 VME Software Interrupt enabled A zero to one transition causes the VME software interrupt to be asserted Subsequent zeroing of this bit causes the interrupt to be masked and the VMEbus interrupt negated but does not clear the VME software interrupt status bit Integrated Device Technology www idt com 249 Power up Option Universe Il User Manual May 12 2010 250 12 Registers gt Register Description VERR Interrupt Mask 0 PCI VERR Interrupt masked 1 PCI VERR Interrupt enabled LERR LERR Interrupt Mask 0 PCI LERR Interrupt masked 1 PCI LERR Interrupt enabled DMA Interrupt Mask 0 PCI DMA Interrupt masked 1 PCI DMA Interrupt enabled LINT7 LINTO PCI Interrupt Mask O LINTx Interrupt masked 1 LINTx Interrupt enabled Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 251 12 3 61 VMEbus Interrupt Status Register VINT_STAT This register maps PCI Bus interrupt sources to one of the seven VMEbus interrupt pins A value of 001 maps the corresponding interrupt source to
27. Once an interrupt has been received from any of the sources the Universe II sets the corresponding status bit in the VMEbus Interrupt Status Register VINT STAT on page 251 and asserts the appropriate VMEbus interrupt output signal if enabled When a VMEbus interrupt handler receives the interrupt it will perform an IACK cycle at that interrupt level When the Universe II decodes that IACK cycle together with IACKIN asserted it provides the STATUS ID previously stored in the Interrupt STATUS ID Out Register STATID on page 255 unless it is configured as SYSCON in which case it does not monitor IACKIN See Table 17 for a list of the enable mapping and status bits for VMEbus interrupt sources Table 17 Source Enabling Mapping and Status of VMEbus Interrupt Outputs Enable Bit in the Status Bit in the VMEbus Interrupt VMEbus Interrupt Enable Register UPC Status Register VINT EN on Mapping Field in VINT STAT on Interrupt Source page 248 VINT MAPx page 251 VMEbus Software SW INT7 1 N A SW INT7 1 Interrupt VMEbus Error VERR VERR in the VME Interrupt VERR Map 1 Register VINT MAP1 on page 254 PCI Target Abort or LERR LERR in the VME Interrupt LERR Master Abort Map 1 Register VINT MAP1 on page 254 DMA Event DMA DMA in the VME Interrupt DMA Map 1 Register VINT MAP1 on page 254 Mailbox Register MBOX3 0 MBOX3 0 in the VME MBOX3 0 Interrupt Map 2 Register VINT_MAP2 on page 264 PCI bus I
28. PMC i Connection Coe PCI Bus 32 bit 64 bit Data 3 MHz Processor Bus 64 bit Data 8091142 TAO01 02 VMEbus TOOT Main Interfaces The Universe II has two main interfaces the PCI Bus Interface and the VMEbus Interface Each of the interfaces VMEbus and PCI bus there are three functionally distinct modules master module slave module and interrupt module These modules are connected to the different functional channels operating in the Universe II The device had the following channels VMEbus Slave Channel PCI Bus Target Channel DMA Channel Interrupt Channel Register Channel Figure 3 shows the Universe II in terms of the different modules and channels Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 1 Functional Overview gt Main Interfaces 21 Figure 3 Universe Il Data Flow Diagram DMA Channel DMA bidirectional FIFO VMEbus Slave Channel PCI i posted writes FIFO VME Master prefetch read FIFO Slave coupled read PCI Bus Slave Channel PCI posted writes FIFO ia VME PCI Bus Interface VMEbus Interface VMEbus BUS coupled read logic ig Master Interrupt Channel PCI VME Interrupts Register Channel Mailbox Registers Semaphores Integrated Device Technology Universe Il User Manual www idt com May 12 2010 22 1 2 1 1 2 1 1 1 2 1 2 1 2 2 1 Functional Overview gt Main Interfaces VMEbus In
29. Stops with the STOP_REQ bit in the DGCS register Halts with the HALT_REQ bit in the DGCS register Encounters an error on either the PCI bus or VMEbus Each of these conditions cause the ACT bit to clear and a corresponding status bit to be set in the DGCS register If enabled in step 1 an interrupt is generated Once the software has set the GO bit the software can monitor for DMA completion by either waiting for generation of an interrupt by polling the status bits in the DGCS register or by polling the PROCESSED bits of the command packets It is recommended that a background timer also be initiated to time out the transfer This ensures that the DMA has not been hung up by a busy VMEbus or other such system issues Linked list mode can be halted by setting the HALT REQ bit in the DMA Transfer Control Register DCTL on page 232 When the HALT REQ bit is set the DMA terminates when all transfers defined by the current command packet is complete It then loads the next command packet into its registers The HALT bit in the DGCS register is asserted and the ACT bit in the DGCS register is cleared The PROCESSED bit in the linked list is set to 1 approximately 1 us after the HALT bit is set therefore after a DMA halt the user should wait at least 1 us before checking the status of the PROCESSED bit The DMA can be restarted by clearing the HALT status bit and setting the GO bit during the same register write If the DMA is restarte
30. Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 267 12 3 76 Mailbox 2 Register MBOX2 This register is a general purpose mailbox register Register name MBOX2 Register offset 0x350 MBOX2 Mailbox R W 31 0 Integrated Device Technology Universe II User Manual www idt com May 12 2010 268 12 Registers gt Register Description 12 3 77 Mailbox 3 Register MBOX3 This register is a general purpose mailbox register Register name MBOX3 Register offset 0x354 MBOX3 Mailbox R W 31 0 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 269 12 3 78 Semaphore 0 Register SEMAO This register can only be accessed through byte wide access Register name SEMAO Register offset 0x358 wes qms 00 Tm fo me meer 00 mo e wer me pmo Fs mee 0 mo Peewee pmo 30 m mee 0 mo wer fee If a semaphore bit is a value of 0 the associated tag field can be written to If a semaphore bit is a value of 1 the associated tag field cannot be written to see Semaphores on page 83 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 270 12 Registers gt Register Description 12 3 79 Semaphore 1 Register SEMA1 This register can only be accessed through byte wide access Register name SEMA1 Register offset 0x35C Posse fer Tm fo sme eee 0 mo
31. cesse xa oa tra a Soe CRRREFPETERPOOR CERE RR bee GORE RRS oe Ras 69 4 3 JPCILBus Target Images koi ha icr e pn EROR dae OE E PR ERA NUR e ERE ais bog Ro Rr c le 70 4 3 1 PCT Bus faelds uev pRp berzert f RR A RR RON pina IN BOE kepada waked 71 4 3 2 VMEbus Fields e pRrumee EV ERE ER e Re eae be eae ped 71 4 3 3 Control Fields nite eR pp EE E EREMO ERR ped deals pee genes eens 73 4 4 Special PCI Target Image c ce pipa e e ee dee SANSA AEG AO nr ae ER RES ab Rae RR gos planes 73 5 Registers OVGIVIEW iuda EUREN e MR a oc e C NR e Ra Ru 75 5 1 CQVELVIEW MT 75 52 Register Access from the PCI BUS eris ee mene ern hcec e reed ace macer a Red rn o c ca e 76 52 1 PCI Configuration Access 2 2 e 76 5 2 2 Memory or VO ACCESS eissien deed cet Wisk Bae EEE a E RREAS LRE EEA E E E UE 77 5 2 3 Locking the Register Block from the PCI bus 1 2 0 eee cece 78 5 3 Register Access from the VMEbU S sax perire RR EREE oda eg ee EERE EE 79 5 3 1 VMEbus Register Access Image VRAI ssseesseeeeeeeee n 79 35 3 2 CR CSR ACCESSES Lea educa EEE EE eR ERRET A Bed a ADAE Ar 80 5 3 3 RMW and ADOH Register Access Cycles 0 0 eee ene 81 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com Contents 5 44 Mailbox Registers zcexecisii pinnte cyny t ree E Ud eva 5e Semaphotmes eveortbeseERERS bid Upper ee UN Ru E dob SUE hare 6 DMA Controllers iss
32. see PCI Bus Target Images on page 70 3 2 PCI Cycles The PCI Bus Interface of the Universe II operates as a PCI compliant port with a 64 bit multiplexed address data bus The Universe II PCI Bus Interface is configured as little endian using address invariant translation when mapping between the VMEbus and the PCI bus Address invariant translation preserves the byte ordering of a data structure in a little endian memory map and a big endian memory map see Endian Mapping on page 359 and the PCI 2 1 Specification The Universe II has all the PCI signals described in the PCI 2 1 Specification with the exception of SBO and SDONE These pins are exception because the Universe II does not provide cache support Universe II PCI cycles are synchronous meaning that bus and control input signals are externally synchronized to the PCI clock CLK PCI cycles are divided into the following phases Request 2 Address 3 Data transfer 4 Cycle termination 3 2 1 32 Bit Versus 64 Bit PCI The Universe II is configured with a 32 bit or 64 bit PCI data bus at power up see PCI Bus Width on page 138 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 50 3 2 2 3 2 3 3 PCI Interface gt PCI Cycles Each of the Universe II s VMEbus slave images can be programmed so that VMEbus transactions are mapped to a 64 bit data bus on the PCI Interface through the LD64EN bit in the DMA Transfer Co
33. there will be a period of time during which the DMA will pause its transfers on the bus due to the VON counter expiring An important point to consider when programming these timers is the more often the DMA relinquishes its ownership of the bus the more frequently the PCI Slave Channel will have access to the VMEbus If DMA tenure is too long the TXFIFO may fill up causing any further accesses to the bus to be retried In the same fashion all coupled accesses will be retried while the DMA has tenure on the bus This can significantly affect transfer latency and should be considered when calculating the overall system latency B 4 2 VME Transfers On the VMEbus the Universe II can perform D08 through D64 transactions in either block or non block mode The time to perform a single beat however is independent of the bus width being used Hence a DOS transaction will transfer data at 25 the rate of a D32 which in turn is half that for D64 There is a significant difference between the performance for block vs non block operations Because of the extra addressing required for each data transfer in non block operations the DMA performance is about half that compared to operating in block mode Moreover considering that most VME slaves respond less quickly in non block mode the overall performance may drop to one quarter of that achievable in block mode Integrated Device Technology Universe Il User Manual www idt com May 12 2010 348
34. 0 which signifies Memory space and the PCI_BS1 register s SPACE bit is set to 1 which signifies I O space A write must occur to this register before the Universe II Device Specific Registers can be accessed This write can be performed with a PCI configuration transaction or a VMEbus register access Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 179 12 3 6 PCI Configuration Base Address 1 Register PCI BS1 This register specifies the 4 KByte aligned base address of the 4 KByte Universe II register space in PCI Register name PCI BS1 Register offset 0x14 Reserved Reserved SPACE Reset Description Type Reset by value SPACE PCI Bus Address Space All Undefined 0 Memory 1 1 0 A power up option determines the value of the SPACE bit This determines whether the registers are mapped into Memory or I O space in relation to this base address see Power Up Options on page 135 If mapped into Memory space the user is free to locate the Universe registers anywhere in the 32 bit address space If PCI BSO is mapped to Memory space PCI_BS1 is mapped to I O space if PCI BSO is mapped to I O space then PCI BS1 is mapped to Memory space e When the VA 1 pin is sampled low at power up the PCI BSO register s SPACE bit is set to 1 which signifies I O space and the PCI BS1 register s SPACE bit is set to 0 which signifies memory space e
35. 0 0 the Universe ll is generating a SW IACK at the same level undefined as the interrupt acknowledge cycle 1 the Universe II is not generating a SW_IACK at the same level as the interrupt acknowledge cycle The reset state is designed to support the VME64 Auto ID STATUS ID value Integrated Device Technology Universe Il User Manual www idt com May 12 2010 256 12 Registers gt Register Description 12 3 65 VIRQ1 STATUS ID Register V1_STATID The Vx_STATID registers are read only registers that hold the 8 bit VMEbus STATUS ID that is acquired when the Universe II performs a IACK cycle for a given interrupt level Register name V1_STATID Register offset 0x324 Se ee ee ee eee eee 31 24 Reserved 23 16 Reserved 15 08 Reserved 07 00 STATID 7 0 Error Status Bit 0 STATUS ID was acquired without bus error 1 bus error occurred during acquisition of the STATUS ID STATID 7 0 STATUS ID acquired during IACK cycle for level 1 VMEbus el Tes interrupt The Universe II is enabled as the interrupt handler for a given interrupt level via the VIRQx bits of the LINT EN register Once a vector for a given level is acquired the Universe II does not perform a subsequent interrupt acknowledge cycle at that level until the corresponding VIRQx bit in the LINT STAT register is cleared The acquisition of a level x STATUS ID by the Universe II updates the STATUS ID field of the corresponding Vx STATID register and generation o
36. 0x0 15 11 LTIMER Latency Timer All 0x0 The latency timer has a resolution of eight clocks When the Universe II latency timer is programmed for eight clock periods and FRAME_ IRDY_ and TRDY are asserted while GNT_ is not asserted FRAME_ is negated on the next clock edge Integrated Device Technology Universe Il User Manual www idt com May 12 2010 178 12 Registers gt Register Description 12 3 5 PCI Configuration Base Address Register PCI BSO This register specifies the 4 Kbyte aligned base address of the 4 Kbyte Universe II register space on PCI Register name PCI BSO Register offset 0x10 Reserved Reserved SPACE Reset Description Type Reset by value SPACE PCI Bus Address Space All Undefined 0 Memory 14 0 A power up option determines if the registers are mapped into Memory or I O space in relation to this base address see Power Up Options on page 135 If mapped into Memory space the user is free to locate the registers anywhere in the 32 bit address space If PCI BSO is mapped to Memory space PCI BSI is mapped to I O space if PCI BSO is mapped to I O space then PCI BS1 is mapped to Memory space e When the VA 1 pin is sampled low at power up the PCI BSO register s SPACE bit is set to 1 which signifies I O space and the PCI_BS1 register s SPACE bit is set to 0 which signifies memory space e When VA 1 is sampled high at power up the PCI BSO register s SPACE register s bit is set to
37. 2 0 Mailbox 3 Interrupt destination MBOX2 2 0 Mailbox 2 Interrupt destination MBOX1 2 0 Mailbox 1 Interrupt destination MBOXO 2 0 Mailbox 0 Interrupt destination Integrated Device Technology Universe Il User Manual www idt com May 12 2010 264 12 Registers gt Register Description 12 3 73 VME Interrupt Map 2 Register VINT_MAP2 This register maps interrupt sources to one of the seven VMEbus interrupt pins A value of 001 maps the corresponding interrupt source to VIRQ 1 a value of 002 maps to VIRQ 2 etc A value of 000 effectively masks the interrupt since there is no corresponding VIRQ 0 Register name VINT_MAP2 Register offset 0x344 poopie is je 2 se Ls URN 23 16 Reserved De o o DO m ee Dwosen pwecwewgmm ow 5 Dwosem wwecmewgmm m p 9 3 Dwongs wee ea eae m p ow 3 owen wweweasmm m ow Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 265 12 3 74 Mailbox 0 Register MBOXO This register is a general purpose mailbox register Register name MBOXO Register offset 0x348 MBOXO Mailbox R W 31 0 Integrated Device Technology Universe II User Manual www idt com May 12 2010 266 12 Registers gt Register Description 12 3 75 Mailbox 1 Register MBOX1 This register is a general purpose mailbox register Register name MBOX1 Register offset 0x34C MBOX1 Mailbox R W 31 0
38. 2 Interrupt to Clear 1 Location Monitor 2 Interrupt active Location Monitor 1 Status Clear R Write 1 0 no Location Monitor 1 Interrupt to Clear 1 Location Monitor 1 Interrupt active Location Monitor 0 Status Clear R Write 1 0 no Location Monitor 0 Interrupt to Clear 1 Location Monitor 0 Interrupt active Mailbox 3 Status Clear R Write 1 0 no Mailbox 3 Interrupt to Clear 1 Mailbox 3 Interrupt active Mailbox 2 Status Clear R Write 1 0 no Mailbox 2 Interrupt to Clear 1 Mailbox 2 Interrupt active Mailbox 1 Status Clear R Write 1 0 no Mailbox 1 Interrupt to Clear 1 Mailbox 1 Interrupt active Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 245 All VIRQ7 VIRQ1 VOWN Mailbox 0 Status Clear 0 no Mailbox 0 Interrupt 1 Mailbox 0 Interrupt active ACFAIL Interrupt Status Clear 0 no ACFAIL Interrupt 1 ACFAIL Interrupt active SYSFAIL Interrupt Status Clear 0 no SYSFAIL Interrupt 1 SYSFAIL Interrupt active Local Software Interrupt Status Clear 0 no PCI Software Interrupt 1 PCI Software Interrupt active VME Software IACK Status Clear 0 no VME Software IACK Interrupt 1 VME Software IACK Interrupt active Local VERR Interrupt Status Clear O Local VERR Interrupt masked 1 Local VERR Interrupt active Local LERR Interrupt Status Clear O Local LERR Interrupt masked 1 Local LERR Interrupt active Local DMA Inter
39. 2010 354 B Performance gt Performance Summary Universe Il User Manual Integrated Device Technology May 12 2010 www idt com C C 1 C 2 355 Reliability Prediction This appendix discusses the following topics e Physical Characteristics on page 355 e Thermal Characteristics on page 356 Universe II Ambient Operating Calculations on page 357 e Thermal Vias on page 358 Overview This section is designed to help the user to estimate the inherent reliability of the Universe II The information serves as a guide only meaningful results will be obtained only through careful consideration of the device its operating environment and its application Physical Characteristics e CMOS gate array e 120 000 two input NAND gate equivalence e 0 5 um feature size e 309 mils x 309 mils scribed die size Integrated Device Technology Universe II User Manual www idt com May 12 2010 356 C 3 C Reliability Prediction Thermal Characteristics Thermal Characteristics Idle power consumption 1 50 Watts Typical power consumption 32 bit PCT 2 00 Watts e Maximum power consumption 32 bit PCI 2 70 Watts e Typical power consumption 64 bit PCI 2 20 Watts e Maximum power consumption 64 bit PCI 3 20 Watts Maximum power consumption is worst case consumption when the Universe II is performing DMA reads from the VME bus with alternating worst case data patterns SFFFF_FFFF 0000 000
40. 3 wer ws 0000 Tm mm qme 0 mo Peewee pem a om menn 0 Tm wee qe 0 e If a semaphore bit is a value of 0 the associated tag field can be written to If a semaphore bit is a value of 1 the associated tag field cannot be written to see Semaphores on page 83 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 271 12 3 80 Master Control Register MAST_CTL Writing a 1 to the VOWN bit in the MAST CTL register has the effect of asserting BBSY until a 0 is written to the VOWN bit It does not affect the transactions in the PCI Target Channel The Universe II will not do an early release of BBSY if the VMEbus was owned during a transaction by means of VOWN regardless of the value of PWON It is important to wait until VOWN ACK is a value of 0 before writing a value of 1 to the VOWN bit In the event that BERR is asserted on the VMEbus once the Universe II owns the VMEbus the user must release ownership by programming the VOWN bit to a value of 0 if the VMEbus was gained by setting the VOWN bit VMEbus masters must not write a value of 1 to the VOWN bit since this will lock up the VMEbus Once the value programmed in the PWON field is reached during de queuing of posted writes the Universe II will do an early release of BBSY If the PWON field is programmed to a value of 1111 the Universe II will do an early release of BBSY at the completion of each transactio
41. 3 2 VMEbus Interrupt Handling 0 00 7 3 3 Internal Interrupt Handling 000 7 3 4 VME64 Auto ID seien n o Eea eee ee 8 Error Handling 4256 0665 qaa qeapchiidaNs hue wee 8 1 OVELVIEW ic Seed osse UE CODE Ue e Pn vd 82 Errors on Coupled Cycles 00 0 cece cee eee eee 8 3 Errors on Decoupled Transactions lesse 8 3 1 Posted Write ioc peux CUVe ERI anh oo Se EE CN 8 3 2 Prefetched Reads 0 ccc eee eee eee 8 3 3 DMA BITOIS mr sete ae stan nee Epei tase ene 8 3 4 Parity EOTS erene pep er a samen ep ess dow SE Hue Integrated Device Technology www idt com Universe II User Manual May 12 2010 6 Contents 9 Resets Clocks and Power up Options 2 00 c eee e eee eee 129 9 1 QV ELVIE Wisse Om 129 9 2 RESES CUL 129 9 2 1 Universe II Reset Circultty 2252 ceeecee eser pb b eere e Ry E I EE A e 132 9 2 2 Reset Implementation Cautions s sussurrar rnrn eh nn 133 93 Power Up Options iiie tee isn EE AEE ov IER a req T E E p E E Ee 135 9 3 1 Power up Option Descriptions lisse n 136 9 3 2 Power up Option Implementation eeeseeeeeeeeeee n 139 9 3 3 Hardware Initialization Normal Operating Mode 0 0 00 eee eee 140 94 Test MOdES scs rx ache tenis E CERE w ahaa are nated sg ahaa aoe E E pae a C dm RR ea ag acne 141 9 4 1 Auxiliary Test Mod s s sse caseus mte rre debe ED
42. 4 4 VMEbus Lock Commands ADOH Cycles 2 4 5 VMEbus Read Modify Write Cycles RMW Cycles 2 4 6 Register ACCESSES r dd e vede eU edd d ee oe Ed s 2 4 7 Location Monitots s beciter pe eL S eas ee ERGO Ies 2 4 8 Generating PCI Configuration Cycles 0 0 2 5 VMEbus Configuration sse 2 5 1 First Slot Detector srrss riode exe rex r tanaki e ema 2 5 2 VMEbus Register Access at Power up 0 0 00 2 6 Automatic Slot Identification llle 2 6 1 Auto Slot ID VME64 Specified 00 0008 2 6 2 Auto ID A Proprietary IDT Method 00 2 6 3 System Controller Functions 0 000 000 0000 2 6 4 IACK Daisy Chain Driver Module 00 2 6 5 VMEbus Time out 0 0 e 2 6 6 Bus Isolation Mode BI Mode 0000 cece eee Integrated Device Technology www idt com Universe II User Manual May 12 2010 4 Contents ce ee ee ee CL e o ard 49 3 1 CQVELVIEW D m 49 32 POLCYCIES PL Em 49 3 2 1 32 Bit Versus 64 Bit PCL 1 4 ee nee Vo e awe hee YE oars yes bee eh ea eee 49 3 2 2 PCI Bus Request and Parking 0 0 cet eee eee 50 3 2 3 Address Phase 2 55 mie detach dex UpLOR arth RE erar tota gne ede eee dale died 50 3 2 4 Data Transtets 24 eset C UT 52 3 2 5 Termination Phase ood 39 Chad einen ER is RTI Id aum bad sure p abbas 52 3 2 6 Parity Checking 2o box eee E WE ERE P a ERE
43. 52 6 5 2 VMEbus to PCI Transfers VMEbus to PCI transfers involve the Universe II reading from the VMEbus and writing to the PCI bus With DMA transfers in this direction the DMA Channel begins to queue data in the DMAFIFO as soon as there is room for 64 bytes in the DMAFIFO When this watermark is reached the DMA requests the VMEbus through the VMEbus Master Interface and begins reading data from the VMEbus The Universe II maintains VMEbus ownership until one of the following conditions are met e DMAFIFO is full e DMA block is complete DMA is stopped alinked list is halted e DMA encounters an error e VMEbus tenure limit is reached VON in the DGCS register Integrated Device Technology Universe Il User Manual www idt com May 12 2010 104 6 6 6 DMA Controller gt DMA Interrupts The DMA can be programmed to limit its VMEbus tenure to fixed block sizes using the VON field in the DMA General Control Status Register DGCS on page 238 With VON enabled the DMA will relinquish ownership of the Master Interface at defined address boundaries see DMA VMEbus Ownership on page 91 To further control the DMA s VMEbus ownership the VOFF timer in the DGCS register can be used to program the DMA to remain off the VMEbus for a specified period when VMEbus tenure is relinquished See DMA VMEbus Ownership on page 91 Entries in the DMAFIFO are delivered to the PCI bus as PCI write transactions as soon
44. A16 address spaces Figure 10 Memory Mapping in the Special PCI Target Image BASE 400 0000 BASE 3FF 0000 3 64 Kbytes 16 Mbytes BASE 300 0000 BASE 2FF 0000 2 BASE 200 0000 BASE 1FF 0000 1 BASE 100 0000 BASE 0FF 0000 0 BASE 000 0000 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 9 5 1 75 Registers Overview The Universe II Control and Status Registers UCSR occupy 4 Kbytes of internal memory This chapter discusses the following topics Register Access from the PCI Bus on page 76 Register Access from the VMEbus on page 79 Mailbox Registers on page 83 e Semaphores on page 83 Overview The Universe II Control and Status Registers UCSR occupy 4 Kbytes of internal memory This 4 Kbytes is logically divided into the following three groups see Figure 11 e PCI Configuration Space PCICS Universe II Device Specific Registers UDSR e VMEbus Control and Status Registers VCSR The Universe II registers are little endian The access mechanisms for the UCSR are different depending upon whether the register space is accessed from the PCI bus or VMEbus Register access from the PCI bus and VMEbus is discussed in the following sections Integrated Device Technology Universe Il User Manual www idt com May 12 2010 76 5 Registers Overview gt Register Access from the PCI Bus Figure 11 Universe II Control and Status Register Space
45. BD 81 12 or BD 31 16 in LSIx BD Address space LAS in LSIx CTL Memory or I O Table 8 VMEbus Fields for the PCI Bus Target Image Translation offset TO 31 12 or TO 31 16 in Translates address supplied by PCI master LSIx TO to a specified VMEbus address Maximum data width VDW in LSIx CTL 8 16 32 or 64 bits Moe SUPER in LSIx_CTL Supervisor or non privileged PGM in LSIx_CTL Program or data VCT in LSIx_CTL single or block Address space VAS in LSIx_CTL A16 A24 A32 CR CSR User1 User2 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 4 Slave Image Programming gt PCI Bus Target Images 71 Table 9 Control Fields for PCI Bus Target Image Image enable EN in LSIx CTL Enable bit Posted write PWEN in LSIx CTL enable bit IDT recommends that the attributes in a target image not be changed while data is enqueued N in the Posted Writes FIFO To ensure data is queued from the FIFO check the TXFE status bit in the Miscellaneous Status Register MISC STAT on page 275 or perform a read from that image If the programming for an image is changed after the transaction is queued in the FIFO the transaction s attributes are not changed Only subsequent transactions are affected by the change in attributes 4 3 1 PCI Bus Fields AII decoding for VMEbus accesses are based on the address and command information produced by a PCI bus master The PCI Target Interface claims a cycle if there is an
46. Bus Error A low level signal indicates that the addressed slave has not responded or is signalling an error VRBR 3 0 Input VMEbus Receive Bus Request Lines If the Universe II is the Syscon the arbiter logic monitors these signals and generates the appropriate Bus Grant signals Also monitored by requester in ROR mode VRIRQ 7 1 Input VMEbus Receive Interrupts 7 through 1 These interrupts can be mapped to any of the Universe II s PCI interrupt outputs VRIRQ7 1_ are individually maskable but cannot be read VRSYSFAIL Input VMEbus Receive SYSFAIL Asserted by a VMEbus system to indicate some system failure VRSYSFAIL is mapped to a PCI interrupt VRSYSRST Input VMEbus Receive System Reset Causes assertion of LRST_ on the local bus and resets the Universe Il VSLAVE DIR Output VMEbus Slave Direction Control Transceiver control that allows the Universe II to drive DTACK on the VMEbus When the Universe ll is driving lines on the VMEbus this signal is driven high when the VMEbus is driving the Universe Il this signal is driven low VSYSCLK Bidirectional VMEbus System Clock Generated by the Universe II when it is the Syscon and monitored during DY4 Auto ID sequence Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 10 Signals and Pinout gt PCI Bus Signals 147 Table 26 VMEbus Signals Continued VSCON_D
47. Bus Width The PCI Interface can be used as a 32 bit bus or 64 bit bus The PCI bus width is determined during a PCI reset see the PCI 2 1 Specification The Universe II is configured as 32 bit PCI if REQ64_ is high on RST_ it is configured as 64 bit if REQ64_ is low The Universe II has an internal pull up on REQ64_ so the Universe II defaults to 32 bit PCI On a 32 bit PCI bus the Universe II drives all its 64 bit extension bi direct signals at all times these signals include C BE 7 4 _ AD 63 32 REQ64_ PAR64 and ACK64_ to unknown values If used as a 32 bit interface the 64 bit pins AD 63 32 C BE 7 4 PAR64 and ACK64_ can be left un terminated Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 9 Resets Clocks and Power up Options gt Power Up Options 139 9 3 1 10 PCI CSR Image Space There is a power up option using the VA 1 pin that determines the value of the SPACE bit of the PCI BSx registers At power up the SPACE bit of the PCI_BS1 register is the negation of the SPACE bit of the PCI_BSO register e When the VA pin is sampled low at power up the PCI_BSO register s SPACE bit is set to 1 which signifies I O space and the PCI_BS1 register s SPACE bit is set to 0 which signifies Memory space e When VA is sampled high at power up the PCI_BSO register s SPACE register s bit is set to 0 which signifies Memory space and the PCI_BS1 register s SPACE bit is set to 1 which signifie
48. DIR VD DIR VDS DIR VSLAVE DIR and VSCON DIR When the VMEbus is driving the Universe II these signals are driven low The control signals in the Universe II do not all have the same functionality Since the Universe II implements early bus release VAS DIR must be a separate control signal Contention between the Universe II and the VME buffers is handled since the Universe II tristates its outputs one 64MHz clock period before the buffer direction control is faced inwards Power up Options Power up options for the automatic configuration of slave images and other Universe II features are provided through the state of the VME address and data pins VA 31 1 and VD 31 27 All of these signals are provided with internal pull downs to bias these signals to their default conditions Should values other than the defaults be required here either pull ups or active circuitry may be applied to these signals to provide alternate configurations Power up options are described in Resets Clocks and Power up Options on page 129 Since the power up configurations lie on pins that may be driven by the Universe II or by the VME transceivers care must be taken to ensure that there is no conflict During any reset event the Universe II does not drive the VA or VD signals As well during any VMEbus reset SYSRST and for several CLK64 periods after the Universe II negates VOE to tri state the transceivers During the period that these signals are t
49. Description PCI Acknowledge 64 Bit Transfer Sad 63 0 Listed in 313 Pin PCI Address Data Pins PBGA Package on page 333 C BE 0 am PCI Command and Byte Enables C BE 1 C BE 2 C BE 3 C BE 4 C BE 5 C BE 6 C BE 7 clk64 VME Clock 64 MHz 60 40 duty 5 ns rise time enid AE21 EN CMOS aae Enable IDD Tests Integrated Device Technology Universe II User Manual www idt com May 12 2010 156 11 Electrical Characteristics gt DC Characteristics Table 30 Pin List and DC Characteristics for Universe Il Signals Continued Lm om pe NL mw m fe m ow v mo wo m 9 e ow wo LEN 9 Output Type lo Input Type mA mA Signal Description PCI Cycle Frame PCI Grant PCI Initialization Device Select PCI Interrupt TTL Co n TTL TTL TTL N TTL e M ee T5 ow e fe ew e fe Ce e fo e e BONN s Co n Co n 69 69 69 n pE HA ROG oO A For factory testing req64 AD18 m ow fe AB18 For factory testing TTL Schm Transfer PCI Stop Co n 69 n A N Co n Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 11 Electrical Characteristics gt DC Characteristics 157 Table 30 Pin List and DC Characteristics for Universe Il Signals Continued Output lot loH Type Input Type Type mA mA Signal Description bow ommo 2 Tm qm
50. Description Type Reset by value Integrated Device Technology Universe Il User Manual www idt com May 12 2010 200 12 Registers gt Register Description 12 3 23 PCI Target Image 3 Translation Offset LSI3_TO Address bits 31 16 generated on the VMEbus in response to an image decode are a two s complement addition of address bits 31 16 on the PCI Bus and bits 31 16 of the image s translation offset Register name LSI3_TO Register offset 0x148 EEUU Reset Description Type Reset by value 31 16 TO 31 16 Translation Offset Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 201 12 3 24 Special Cycle Control Register SCYC CTL The special cycle generator generates an ADOH or RMW cycle for the 32 bit PCI Bus address which matches the programmed address in SCYC_ADDR in the address space specified in the LAS field of the SCYC CTL register A Read Modify Write command is initiated by a read to the specified address Address Only cycles are initiated by either read or write cycles Register Name SCYC CTL Register offset 0x170 Reserved Reserved Reserved Reset Description Type Reset by value PCI Bus Address Space 0x00 0 PCI Bus Memory Space 1 PCI Bus I O Space For a RMW cycle only Special Cycle 0x00 00 Disable 01 RMW 10 ADOH 11 Reserved Integrated Device Technology Universe II User Manual www idt com May 12 2010
51. II is has four location monitors they all share the same LM CTL and LM_BS registers In address spaces A24 and A16 the respective upper address bits are ignored When an access to a location monitor is detected an interrupt is generated on the PCI bus VMEbus address bits 4 3 determine which Location Monitor is used and hence which of four PCI interrupts to generate see Location Monitors on page 122 The location monitors do not store write data Read data from the location monitors is undefined Location monitors do not support BLT or MBLT transfers Each Universe II on the VMEbus must be programmed to monitor the same 4 Kbytes of addresses on the VMEbus If the Universe II accesses its own enabled location monitor the same Universe II generates DTACK on the VMEbus and terminates its own cycle This removes the necessity of the system integrator ensuring that there is another card enabled to generate DTACK The generation of DTACK happens after the Universe II has decoded and responded to the cycle If the location monitor is accessed by a different master the Universe II does not respond with DTACK Generating PCI Configuration Cycles PCI Configuration cycles can be generated by accessing a VMEbus slave image whose Local Address Space field LAS is set for Configuration Space ADOH BLT and MBLT cycles must not be attempted when the LAS field of an image is programmed for PCI Configuration Space PCI Configuration
52. Interface gt PCI Cycles PCI targets must assert DEVSEL_ if they have decoded the access During a Configuration cycle the target is selected by its particular ID Select IDSEL If a target does not respond with DEVSEL_ within six clocks a Master abort is generated The role of configuration cycles is described in the PCI 2 1 Specification Data Transfer Acknowledgment of a data phase occurs on the first rising clock edge after both IRDY_ and TRDY_ are asserted by the master and target respectively REQ64_ can be driven during the address phase to indicate that the master wishes to initiate a 64 bit transaction The PCI target asserts ACK64_ if it is able to respond to the 64 bit transaction Wait cycles are introduced by either the master or the target by de asserting IRDY_ or TRDY_ For write cycles data is valid on the first rising edge after IRDY is asserted Data is acknowledged by the target on the first rising edge with TRDY asserted For read cycles data is transferred and acknowledged on first rising edge with both IRDY and TRDY asserted A single data transfer cycle is repeated every time IRDY_ and TRDY_ are both asserted The transaction only enters the termination phase when FRAME is de asserted master initiated termination or if STOP is asserted target initiated When both FRAME andIRDY are de asserted final data phase is complete the bus is defined as idle Termination Phase The PCI Bus Interface permits the follow
53. Manual Integrated Device Technology May 12 2010 www idt com 3 PCI Interface gt Universe Il as PCI Master 55 3 3 2 PCI Burst Transfers The Universe II generates aligned burst transfers of some maximum alignment according to the programmed PCI aligned burst size PABS field in the Master Control Register MAST CTL on page 271 The PCI aligned burst size can be programmed at 32 64 or 128 bytes Burst transfers do not cross the programmed boundaries For example when programmed for 32 byte boundaries a new burst begins at XXXX_XX20 XXXX XXA0 etc If necessary a new burst begins at an address with the programmed alignment To optimize PCI bus usage the Universe II always attempts to transfer data in aligned bursts at the full width of the PCI bus The Universe II can perform a 64 bit data transfer over the AD 63 0 lines if operated in a 64 bit PCI environment or against a 64 bit capable target or master The LD64EN bit must be set if the access is being made through a VMEbus slave image the LD64EN bit must be set if the access is being performed with the DMA The Universe II generates burst cycles on the PCI bus if it is performing the following tasks e Emptying the RXFIFO The TXFE bit in the Miscellaneous Status Register MISC STAT on page 275 is clear e Filling the RDFIFO receives a block read request from a VMEbus master to an appropriately programmed VMEbus slave image e Performing DMA transfers All other
54. OR COMPLETENESS OF ANY STATEMENTS INFORMATION OR MATERIALS CONCERNING CODE EXAMPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPECIAL DAMAGES HOWEVER THEY MAY ARISE AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES The code examples also may be subject to United States export control laws and may be subject to the export or import laws of other countries and it is your responsibility to comply with any applicable laws or regulations LIFE SUPPORT POLICY Integrated Device Technology s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness IDT the IDT l
55. OWEN VICA D ESS red 371 371 Figure 45 Noise Filter Scheme Universe Il User Manual Integrated Device Technology www idt com May 12 2010 11 Tables Table 1 VMEbus Address Modifier Codes sirrien eai n 28 Table 2 PCI Address Line Asserted as a Function of VA I5 1 1 0 0 0 0 00 ccc IR IIIA 39 Table 3 Command Type Encoding for Transfer Type 0 51 Table 4 VMEbus Fields for VMEbus SlaveImage 6 0 e 67 Table 5 PCI Bus Fields for VMEbus Slave Image esie ke a ahh rhe Hr het Cae RR ween eee 68 Table 6 Control Fields for VMEbus Slave Image 1 0 0 0 cee eee eee 68 Table 7 PCI Bus Fields for the PCI Bus Target Image 2 lesse e 70 Table 8 VMEbus Fields for the PCI Bus Target Image 0 0 0 cee eens 70 Table 9 Control Fields for PCI Bus Target Image 0 0 eee eee eae 71 Table 10 PCI Bus Fields for the Special PCI Target Image 0 00 73 Table 11 VMEbus Fields for the Special PCI Bus Target Image 0 eee eee eee 73 Table 12 Control Fields for the Special PCI Bus Target Image 0 00 cee eee 73 Table 13 Programming the VMEbus Register Access Image 1 0 2 ce eee eee eens 79 Table 14 VON Settings for Non Inc Mode 1 0 ce hn 88 Table 15 DMA Interrupt Sources and Enable Bits 0 0 ec ences 104 Table 16 Source Enabling Mapping and Status of PCI Interrupt Output eee 112 Table 17 Source Enabling Mapping and Status of VMEbus Interrupt Ou
56. Resuming DMA Transfers When a DMA error occurs on the source or destination bus the status bits must be read in order to determine the source of the error If it is possible to resume the transfer the transfer should be resumed at the address that was in place up to 256 bytes from the current byte count The original addresses DLA and DVA are required in order to resume the transfer at the appropriate location However the values in the DLA and the DVA registers should not be used to reprogram the DMA because they are not valid once the DMA begins In direct mode it is the user s responsibility to record the original state of the DVA and DLA registers for error recovery In Linked List mode the user can refer to the current Command Packet stored on the PCI bus whose location is specified by the DCPP register for the location of the DVA and DLA information Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 6 DMA Controller gt DMA Error Handling 107 The DTBC register contains the number of bytes remaining to transfer on the source side The Universe II does not store a count of bytes to transfer on the destination side If the error occurred on the source side then the location of the error is simply the latest source address plus the byte count If the error occurred on the destination side then one cannot infer specifically where the error occurred because the byte count only refers to the number of
57. SERR_ signal and setting the S SERR Signalled SERR bit in the PCI CS register Assertion of SERR_ can be disabled by clearing the SERR EN bit in the PCI CS register No interrupt is generated and regardless of whether assertion of SERR is enabled or not the Universe II does not respond to the access with DEVSEL_ Typically the master of the transaction times out with a Master Abort If the Universe II is accessed with REQ64_ in Memory space as a 64 bit target then it responds with ACK64_ if it is powered up as a 64 bit device 3 4 2 Data Transfer Read transactions are always coupled as opposed to VMEbus slave reads which can be pre fetched see Universe II as VMEbus Slave on page 32 Write transactions can be coupled or posted see Figure 6 and PCI Bus Target Images on page 70 To ensure sequential consistency coupled operations reads or writes are only processed once all previously posted write operations have completed the TXFIFO is empty Integrated Device Technology Universe Il User Manual www idt com May 12 2010 58 3 4 3 3 PCI Interface gt Universe II as PCI Target Figure 6 PCI Bus Target Channel Dataflow POSTED WRITE DATA PCI BUS VMEbus SLAVE COUPLED WRITE DATA MASTER INTERFACE INTERFACE COUPLED READ DATA The PCI bus and the VMEbus can have different data width capabilities The maximum VMEbus data width is programmed into the PCI target image through the VDW bit in the PCI Target Image 0
58. Signal Description 2m TTL Schm VMEbus Received BBSY Signal Baud TTL Schm VMEbus Receive Bus Error vrbr 0 TTL Schm VMEbus Receive Bus Request vrira 1 TTL Schm VMEbus Receive Interrupts vrsysfail AC13 TTL VMEbus Receive SYSFAIL Signal vrsysrst TTL Schm VMEbus Receive SYSRESET Signal vscon_dir 3S SYSCON signals direction control vslave_dir DTACK BERR direction control Signal Error BERR EN IR NINE SEE Wal al Integrated Device Technology Universe Il User Manual www idt com May 12 2010 160 11 Electrical Characteristics gt Operating Conditions Table 30 Pin List and DC Characteristics for Universe II Signals Continued Output lot loH Type Input Type Type mA mA Signal Description vxbr 0 VMEbus Transmit Bus Request NNI J19 3S 3 VMEbus Transmit Interrupts vxirq 3 K18 vxirq 5 L23 vxbr 2 vxsysfail M10 3 VMEbus Transmit SYSFAIL Signal vxsysrst A23 3S 3 3 VMEbus Transmit SYSRESET Signal 11 2 Operating Conditions The following table specifies recommended operating condition for the Universe II Table 31 Operating Conditions Frequency Symbols Parameters Operation Mhz Ta Industrial Ambient Temperature 25 33 Ta Extended Ambient Temperature 4125 C Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 11 Electrical Characteristics gt Power Dissipation 161 11 2 1 Absolute Maximum Ratings Table 32 Absolute Maximum Rat
59. Target Disconnect e When registers are accessed with FRAME asserted no bursts allowed to registers e After the first data beat of a coupled cycle with FRAME _ asserted A Target disconnect with data only occurs if FRAME_ is asserted e After the first data phase of a PCI Memory command with FRAME asserted if AD 1 0 is not equal to 00 refer to Revision 2 1 of the PCI Specification 2 Target Retry e When a new posted write is attempted and the TXFIFO does not have room for a burst of one address phase and sixteen 64 bit data phases for 64 bit PCT e When a coupled transaction is attempted and the Universe II does not own the VMEbus e When a coupled transaction is attempted while the TXFIFO has entries to process Register Channel is locked by the VME Slave Channel if a register access including a RMW access is in progress or the registers have been locked by an ADOH access If the registers are locked by the VME Slave Channel register accesses by external PCI masters are retried 3 Target Abort e When the Universe II receives BERR on the VMEbus during a coupled cycle BERR translated as Target Abort on the PCI side and the S_TA bit is set in the PCI Configuration Space Control and Status Register PCI CSR on page 172 Whether to terminate a transaction or for retry purposes the Universe II keeps STOP asserted until FRAME is de asserted independent of the logic levels of IRDY and TRDY If STOP is asserted while TRDY_
60. The Interrupt Channel always has the highest priority for access to the VMEbus Master Interface see Figure 3 on page 21 The DMA and PCI Target Channel requests are handled in a fair manner The channel awarded VMEbus mastership maintains ownership of the VMEbus until it is has completed the transaction The definition of a complete transaction for each channel is in VMEbus Release on page 27 The Interrupt Channel requests the VMEbus master when it detects an enabled VMEbus interrupt line asserted and must run an interrupt acknowledge cycle to acquire the STATUS ID Integrated Device Technology Universe II User Manual www idt com May 12 2010 26 2 2 1 2 2 2 1 3 2 2 2 2 2 2 1 2 2 2 2 2 VMEbus Interface gt VMEbus Requester PCI Target Channel The PCI Target Channel requests the VMEbus Master Interface to service the following conditions e TXFIFO contains a complete transaction e Acoupled cycle request DMA Channel The DMA Channel requests the VMEbus Master Interface in the following instances e The DMAFIFO has 64 bytes available if it is reading from the VMEbus or 64 bytes in its FIFO if it is writing to the VMEbus e The DMA block is complete see DMA Controller on page 85 In the case of the DMA Channel the DMA Channel VMEbus off timer can be used to further qualify requests from this channel The VMEbus off timer controls how long the DMA remains off the VMEbus before making another request se
61. This register maps VMEbus interrupt sources to one of the seven VMEbus interrupt pins A value of 001 maps the corresponding interrupt source to VIRQ 1 a value of 010 maps to VIRQ 2 etc A value of 000 effectively masks the interrupt since there is no corresponding VIRQ 0 SW_INT is set to 010 with the VME64AUTO power up option Register name VINT_MAP1 Register offset 0x31C sm 24 Reserved EN INT m Se Software interrupt destination Power up Option VERR O VMEbus Error VMEbus Error interrupt destination destination VMEbus Error interrupt destination RW a 9 T PCI Bus Error interrupt destination po pw foa foo Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 255 12 3 64 Interrupt STATUS ID Out Register STATID When the Universe II responds to an interrupt acknowledge cycle on VMEbus it returns an 8 bit STATUS ID STATID 7 1 can be written by software to uniquely identify the VMEbus module within the system STATID 0 is a value of 0 if the Universe II is generating a software interrupt SW_IACK at the same level as the interrupt acknowledge cycle otherwise it is a value of 1 Register name STATID Register offset 0x320 9m 24 STATID 7 0 EL Reserved 15 08 Reserved 07 00 Reserved STATID E 1 Bits NM ccs RN 1 of the STATUS ID byte are returned when the 1111111 Universe II responds to a VMEbus IACK cycle STATID
62. Two 4 Kbyte ranges of addresses in PCI Memory space and or PCI I O space can be dedicated to the Universe II registers There is one 4 Kbyte range in PCI Memory space and one 4 Kbyte range in PCI I O space The Universe II has the following two programmable registers PCI Configuration Base Address Register PCI BSO on page 178 and PCI Configuration Base Address 1 Register PCI BS1 on page 179 These register each specify the base address and address space for PCI access to the Universe II s registers The PCI BSx registers can be programmed through PCI Configuration space or through a VMEbus access to make the Universe II registers available anywhere in the 32 bit Memory space and in I O space as offsets of the BS 31 12 field in PCIBSx Integrated Device Technology www idt com Universe Il User Manual May 12 2010 78 5 2 2 1 5 2 3 5 Registers Overview Register Access from the PCI Bus The SPACE bit of the PCI BSx registers specifies whether the address lies in Memory space or I O space The SPACE bit of these two registers are read only There is a power up option that determines the value of the SPACE bit of the PCI BSx registers At power up the SPACE bit of the PCI BSI1 register is the negation of the SPACE bit of the PCI BSO register e When the VA 1 pin is sampled low at power up the PCI BSO register s SPACE bit is set to 1 which signifies I O space and the PCI BS1 register s SPACE bit is set to 0
63. UPDATE field by writing a logic 0 The Universe II does not prevent an external master from the PCI bus or the VMEbus from writing to the other DMA registers see Linked list Updating on page 100 Register name D_LLUE Register offset 0x224 ee ee ee ee ee 31 24 UPDATE Reserved 23 16 Reserved 15 08 Reserved 07 00 Reserved UPDATE DMA Linked List Update Enable R W All 0 PCI Resource not Updating Linked List 1 PCI Resource Updating Linked List Integrated Device Technology Universe II User Manual www idt com May 12 2010 242 12 Registers gt Register Description 12 3 56 PCI Interrupt Enable Register LINT_EN Bits VIRQ7 VIRQI1 enable the Universe II to respond as a VME Interrupt Handler to interrupts on the VIRQIx lines When a VIRQx interrupt is enabled and the corresponding VIRQ x pin is asserted the Universe II requests the VMEbus and performs a VME JACK cycle for that interrupt level When the interrupt acknowledge cycle completes the STATUS ID is stored in the corresponding VINT_ID register the VIRQx bit of the LINT_STAT register is set and a PCI interrupt is generated The Universe II does not acquire further interrupt STATUS ID vectors at the same interrupt level until the VIRQx bit in the LINT STAT register is cleared The other bits enable the respective internal or external sources to interrupt the PCI side Register name LINT EN Register offset 0x300 EZE 24 Reserved ES 16 MBOX3
64. User Manual www idt com May 12 2010 56 3 3 4 3 PCI Interface gt Universe ll as PCI Master If the error occurs during a posted write to the PCI bus see also Error Handling on page 125 the Universe II uses the PCI Command Error Log Register L_CMDERR on page 210 to log the command information for the transaction CMDERR 3 0 and the address of the errored transaction is latched in the PCI Address Error Log LAERR on page 211 The LL CMDERR register also records if multiple errors occur with the M ERR bit although the number of errors is not given The error log is qualified with the L STAT bit The rest of the transaction is purged from the RXFIFO if some portion of the write encounters an error An interrupt is generated on the VMEbus and or PCI bus depending upon whether the VERR and LERR interrupts are enabled see Interrupt Generation and Handling on page 109 If an error occurs on the PCI bus the Universe II does not translate the error condition into a BERR on the VMEbus the Universe II does not directly map the error By taking no action the Universe II forces the external VMEbus error timer to expire Parity The Universe II monitors PAR when it accepts data as a master during a read and drives PAR when it provides data as a master during a write The Universe II also drives PAR during the address phase of a transaction when it is a master In both address and data phases the PAR signal provides
65. VERR Interrupt 0 PCI VERR Interrupt Disabled 1 PCI VERR Interrupt Enabled PCI LERR Interrupt 0 PCI LERR Interrupt Disabled 1 PCI LERR Interrupt Enabled PCI DMA Interrupt 0 PCI DMA Interrupt Disabled 1 PCI DMA Interrupt Enabled VIRQx Interrupt 0 VIRQx Interrupt Disabled 1 VIRQx Interrupt Enabled VOWN Interrupt 0 VOWN Interrupt Disabled 1 VOWN Interrupt Enabled Integrated Device Technology www idt com Universe Il User Manual May 12 2010 244 12 Registers gt Register Description 12 3 57 PCI Interrupt Status Register LINT_STAT Status bits indicated as R Write 1 to Clear are edge sensitive the status is latched when the interrupt event occurs These status bits can be cleared independently of the state of the interrupt source by writing a 1 to the status register Clearing the status bit does not imply the source of the interrupt is cleared However ACFAIL and SYSFAIL are level sensitive Clearing ACFAIL or SYSFAIL while their respective pins are still asserted will have no effect Register name LINT STAT Register offset 0x304 EZE 24 Reserved H 16 MBOX3 MBOX2 MBOX1 MBOXO EUN a E SW INT ESSE S LERR LIES IACK oro 00 vmar vimos VIRQ5 VIRQ4 VIRQ3 VRQ vna VOWN Location Monitor 3 Status Clear R Write 1 0 no Location Monitor 3 Interrupt to Clear 1 Location Monitor 3 Interrupt active Location Monitor 2 Status Clear R Write 1 0 no Location Monitor
66. VIRQ 1 a value of 002 maps to VIRQ 2 etc A value of 000 effectively masks the interrupt since there is no corresponding VIRQ 0 Register name VINT_STAT Register offset 0x314 ae ee ee ee eee es 31 24 SW SW SW SW SW SW SW Reserved INT7 INT6 INT5 INT4 INT3 INT2 INT1 07 00 LINT7 LINT6 LINT5 LINT4 LINT3 LINT2 LINT1 LINTO Il SW_INT7 VME Software 7 Interrupt Status Clear R Write 1 A 0 no VME Software 7 Interrupt to clear 1 VME Software 7 Interrupt active SW_INT6 VME Software 6 Interrupt Status Clear R Write 1 0 no VME Software 6 Interrupt to clear 1 VME Software 6 Interrupt active SW_INT5 VME Software 5 Interrupt Status Clear R Write 1 0 no VME Software 5 Interrupt to clear 1 VME Software 5 Interrupt active SW_INT4 VME Software 4 Interrupt Status Clear R Write 1 0 no VME Software 4 Interrupt to clear 1 VME Software 4 Interrupt active SW_INT3 VME Software 3 Interrupt Status Clear R Write 1 0 no VME Software 3 Interrupt to clear 1 VME Software 3 Interrupt active SW_INT2 VME Software 2 Interrupt Status Clear R Write 1 0 no VME Software 2 Interrupt to clear 1 VME Software 2 Interrupt active SW INT1 VME Software 1 Interrupt Status Clear R Write 1 0 no VME Software 1 Interrupt to clear 1 VME Software 1 Interrupt active MBOX3 Mailbox 3 Status Clear R Write 1 0 no Mailbox 3 Interrupt to clear 1 Mailbox 3 Interrupt active Integrated Device Technology Universe Il User Manual www idt com May 12 2010 25
67. VME 00 PCI Bus Memory Space 01 PCI Bus I O Space 10 PCI Bus Configuration Space 11 Reserved Integrated Device Technology Universe II User Manual www idt com May 12 2010 326 12 Registers gt Register Description 12 3 122 VMEbus Slave Image 7 Base Address Register VSI7 BS The base address specifies the lowest address in the address range that is decoded Register name VSI7_BS Register offset OXFDO BS 31 16 Base Address PWR VME Low Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 327 12 3 123 VMEbus Slave Image 7 Bound Address Register VSI7 BD The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register If the bound register is 0 then the addresses decoded are those greater than or equal to the base address Register name VSI7_BD Register offset OxFD4 23 16 BD 31 16 Bound Address PWR VME Integrated Device Technology Universe Il User Manual www idt com May 12 2010 328 12 Registers gt Register Description 12 3 124 VMEbus Slave Image 7 Translation Offset VSI7 TO Register name VSI7_TO Register offset OXFD8 23 16 TO 31 16 Translation Offset PWR VME 09 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 329 12 3 125 VMEbus CSR Bit Clear Register VCSR CLR T
68. VMEbus Specification minimum of 200 ms SYSRST The external 64 MHz clock controls this assertion time LRST_ is asserted for 5 ms or more from all sources except VRSYSRST_ Table 21 Functions Affected by Reset Initiators Clock Services SYSCLK CLK64 enables PLL Divider VMEbus Services VMEbus Arbiter VMEbus Timer VCSR Registers General Services Most registers Power Up and Reset State Machine Power up the device Reset Registers VMEbus Reset Output VXSYSRST_ asserted for more than 200 ms PCI Bus Reset Output LRST_ asserted for at least 5 ms PWRRST_ PWRRST_ or VRSYSRST_ PWRRST_ RST or VRSYSRST PWRRST or VRSYSRST PWRRST or VME RESET or SW SYSRST bit in MISC CTL register PWRRST_ or VRSYSRST_ or SW_LRST bit in MISC_CTL register or RESET bit in VOSR SET register a On PWRRST_ options are loaded from pins On SYSRST and RST options are loaded from values that were latched at the previous PWRRST b LRST can be cleared by writing 1 to the RESET bit in the CSR CLR register Universe Il User Manual May 12 2010 Integrated Device Technology www idt com 9 Resets Clocks and Power up Options gt Resets 133 Figure 21 Reset Circuitry PWRRST_ VME Services VME Arbiter VMEbus timer VCSR registers VRSYSRST_ Clock Services SYSCLK CLK64 enables PLL divider RST General Services E Most Registers Power Up and Reset Power up reset registers asse
69. VMEbus master For this reason block read performance on the VMEbus is similar to that observed with block writes However if the RDFIFO be unable to deliver data to the VMEbus master which can happen if there is considerable traffic on the PCI bus or the PCI bus target has a slow response the VMEbus Slave Interface delays DTACK assertion until an entry is queued and is available for the VMEbus block read Integrated Device Technology Universe Il User Manual www idt com May 12 2010 36 2 4 3 2 2 4 4 2 VMEbus Interface gt Universe Il as VMEbus Slave On the PCI bus prefetching continues as long as there is room for another transaction in the RDFIFO and the initiating VMEbus block read is still active The space required in the RDFIFO for another PCI burst read transaction is determined by the setting of the PCI aligned burst size PABS in the Master Control Register MAST_CTL on page 271 If PABS is set for 32 bytes there must be four entries available in the RDFIFO for aligned burst size set to 64 bytes eight entries must be available for aligned burst size set to 128 bytes there must be 16 entries available When there is insufficient room in the RDFIFO to hold another PCI burst read the read transactions on the PCI bus are terminated and only resume if room becomes available for another aligned burst and the original VMEbus block read is still active When the VMEbus block transfer terminates any remaining data in
70. VMEbus transaction times out indicated by one of the VMEbus data strobes remaining asserted beyond the time out period The VME Bus Time out value has a 4us resolution Therefore the time out may occur up to 4us earlier than the selected VME Bus Time out period Integrated Device Technology Universe II User Manual www idt com May 12 2010 46 2 VMEbus Interface gt Automatic Slot Identification 2 6 6 Bus Isolation Mode BI Mode BI Mode is a mechanism for logically isolating the Universe II from the VMEbus This mechanism is useful for the following purposes e Implementing hot standby systems A system may have two identically configured boards one in BI Mode If the board that is not in BI Mode fails it can be put in BI Mode while the spare board is removed from BI Mode e System diagnostics for routine maintenance e Fault isolation in the event of a card failure The faulty board can be isolated While in BI Mode the Universe II data channels cannot be used to communicate between VMEbus and PCI Universe II mailboxes do provide a means of communication The only traffic permitted is to Universe II registers either through configuration cycles the PCI register image the VMEbus register image or CR CSR space No IACK cycles are generated or responded to No DMA activity occurs Any access to other PCI images result in a Target Retry Access to other VMEbus images are ignored Entering BI Mode has the following e
71. Vpp 0 3V lout 20 pA VIH_CMOS Voltage Input high Vout 0 1V or Vpp 0 1V 0 7 Vdd Vpp 0 3V lout 20 pA VIL_TTL Voltage Input low Vout 0 1V or Vpp 0 1V 0 3V 0 8V lour 20 pA VIL CMOS Voltage Input low Vout 0 1V or Vpp 0 1V 0 3V 0 3Vpp lour 20 pA 153 Tested at 0 C to 70 C VT _TTL Voltage Input high Vout 0 1V or Vpp 0 1V Schmitt trigger lout 20 pA VT _CMOS Voltage Input high Vout 0 1V or Vpp 0 1V 0 7Vpp Schmitt trigger lour 20 pA VT ttl Voltage Input low Vout 0 1V or Vpp 0 1V 0 8V Schmitt trigger lout 20 pA VT _CMOS Voltage Input low Vout 0 1V or Vpp 0 1V 0 25Vpp Schmitt trigger lout 20 pA Input leakage current With no pull up or pull down 5 0nA 5 0nA resistance Vin Vss or Vpp Integrated Device Technology www idt com Universe Il User Manual May 12 2010 154 11 Electrical Characteristics gt DC Characteristics Table 28 Non PCI Electrical Characteristics Tested at 0 C to 70 C Symbols Parameters Test conditions li Input leakage current Inputs with pull down resistance high Vin Vdd lit Input leakage current Inputs with pull up resistance 180uA 10A low Vin Vss loz loz Tristate output leakage Vout Vdd or Vss 10 0nA 10 0nA 11 1 2 PCI Characteristics Table 29 specifies the required AC and DC characteristics of all PCI Universe II signal pins Table 29 AC DC PCI Electrical Characteristics Symbols Para
72. accesses are treated as single data beat transactions on the PCI bus During PCI burst transactions the Universe II dynamically enables byte lanes on the PCI bus by changing the BE signals during each data phase 3 3 3 Termination The Universe II performs a Master Abort if the target does not respond within six clock cycles Coupled PCI transactions terminated with Target Abort or Master Abort are terminated on the VMEbus with BERR The R TA or R_MA bits in the PCI CS register are set when the Universe II receives a Target Abort or generates a Master Abort independent of whether the transaction was coupled decoupled prefetched or initiated by the DMA If the Universe II receives a retry from the PCI target then it relinquishes the PCI bus and re requests within three PCI clock cycles No other transactions are processed by the PCI Master Interface until the retry condition is cleared The Universe II can be programmed to perform a maximum number of retries using the MAXRTRY field in the Master Control Register MAST CTL on page 271 When this number of retries has been reached the Universe II responds in the same way as it does to a Target Abort on the PCI bus The Universe II can issue a BERR signal on the VMEbus All VMEbus slave coupled transactions and decoupled transactions encounter a delayed DTACK once the FIFO fills until the condition clears either due to success or a retry time out Integrated Device Technology Universe Il
73. and are not guaranteed to perform the same way when installed in customer products The information contained herein is provided without representation or warranty of any kind whether express or implied including but not limited to the suitability of IDT s products for any particular purpose an implied warranty of merchantability or non infringement of the intellectual property rights of others This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties IDT s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users Anyone using an IDT product in such a manner does so at their own risk absent an express written agreement by IDT Integrated Device Technology IDT and the IDT logo are registered trademarks of IDT Other trademarks and service marks used herein including protected names logos and designs are the property of IDT or their respective third party owners May 2010 2010 Integrated Device Technology Inc Notice The information in this document is subject to change without notice
74. and holds PERR for at least one clock for each errored data phase PLL TESTOUT Output Manufacturing Test Output No connect PLL TESTSEL Input Manufacturing Test Select Tie to ground for normal operation PWRRST Input Power up Reset All Universe II circuitry is reset by this input REQ_ Output Bus Request Used by the Universe II to indicate that it requires the use of the PCI bus REQ64_ Bidirectional 64 Bit Bus Request Used to request a 64 bit PCI transaction If the target does not respond with ACK64_ 32 bit operation is assumed RST_ Input PCI Reset Input Resets the Universe Il from the PCI bus SERR_ Output System Error Reports address parity errors or any other system error STOP_ Bidirectional Stop Used by the Universe II as PCI slave when it wishes to signal the PCI master to stop the current transaction As PCI master the Universe II terminates the transaction if it receives STOP from the PCI slave Integrated Device Technology Universe Il User Manual www idt com May 12 2010 150 10 Signals and Pinout gt PCI Bus Signals Table 27 PCI Bus Signals TCK Input JTAG Test Clock Input Used to clock the Universe II s TAP controller Tie to any logic level if JTAG is not used in the system TDI Input JTAG Test Data Input Used to serially shift test data and test instructions into the Un
75. as required e Formal Contains information about a final customer ready product and is available once the product is released to production Universe Il User Manual Integrated Device Technology May 12 2010 www idt com About this Document 15 Revision History May 12 2010 Formal This document fixed a number of minor typographical errors No technical changes were made October 2009 Formal This document was rebranded as IDT No technical changes were made June 2009 Formal There have been changes throughout the manual August 2007 Formal There have been numerous edits throughout the manual The formatting of the document has also been updated November 2002 Formal This document information applies to both the Universe IIB and the Universe IID devices The Universe ITD is recommended for all new designs For more information about the two devices see the Universe IID IIB Differences Summary The following chapter was updated for the release of this manual e Reliability Prediction on page 355 October 2002 Formal This document information applies to both the Universe IIB and the Universe IID devices The Universe IID is recommended for all new designs For more information about the two devices see the Universe IID IIB Differences Summary There was an erratum found in the 361 DBGA package drawing Integrated Device Technology Universe Il User Manual www idt com May 12 2010 16 Ab
76. bit VMEbus STATUS ID that is acquired when the Universe II performs a IACK cycle for a given interrupt level Register name V5_STATID Register offset 0x334 B GEGEN NES ee eee 31 24 Reserved 23 16 Reserved 15 08 Reserved 07 00 STATID 7 0 Error Status Bit 0 STATUS ID was acquired without bus error 1 bus error occurred during acquisition of the STATUS ID STATID 7 0 STATUS ID acquired during IACK cycle for level 5 VMEbus el Tes interrupt The Universe II is enabled as the interrupt handler for a given interrupt level via the VIRQx bits of the LINT EN register Once a vector for a given level is acquired the Universe II does not perform a subsequent interrupt acknowledge cycle at that level until the corresponding VIRQx bit in the LINT STAT register is cleared The acquisition of a level x STATUS ID by the Universe II updates the STATUS ID field of the corresponding Vx STATID register and generation of a PCI interrupt A VMEbus error during the acquisition of the STATUS ID vector sets the ERR bit which means the STATUS ID field may not contain a valid vector Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 261 12 3 70 VIRQ6 STATUS ID Register V6 STATID The Vx STATID registers are read only registers that hold the 8 bit VMEbus STATUS ID that is acquired when the Universe II performs a IACK cycle for a given interrupt level Register name V
77. cycle has sole PCI access to the Universe II registers and the VMEbus 2 program the VOWN bit in the MAST_CTL register to a value of 1 see Using the VOWN bit on page 64 Integrated Device Technology Universe II User Manual www idt com May 12 2010 64 3 4 6 3 4 6 1 3 PCI Interface gt Universe II as PCI Target wait until the VOWN_ACK bit in the MAST_CTL register is a value of 1 generate an ADOH cycle with the Special Cycle Generator perform transactions to be locked on the VMEbus release the VMEbus by programming the VOWN bit in the MAST_CTL register to a value of 0 wait until the VOWN_ACK bit in the MAST_CTL register is a value of 0 pi Qv Dec x In the event that BERR is asserted on the VMEbus once the Universe II has locked and owns the VMEbus it is the responsibility of the user to release ownership of the VMEbus by programming the VOWN bit in the MAST CTL register to a value of 0 The following restrictions apply to the use of VME Lock cycles e All byte lane information is ignored for VME Lock cycles e The Universe II generates a VME Lock cycle on the VMEbus if the PCI Target Image which includes the special cycle has posted writes disabled e The Universe II Special Cycle Generator does not generate VME Lock cycles if the address space is not one of A16 A24 or A32 it produces regular cycles instead Using the VOWN bit The Universe II provides a VMEbus ownership bit VOWN bit in the Master Control
78. eae 347 B 4 2 VMEBE Transtetsz sese t yearn TRE E Ba a R ARREST VERE dein PETERE NUR E d 347 B 4 3 IneMiTIL C PRMTPPI EETEMM 348 BS Universe M Specific Registet esses cues prr hahet EROR EAEE RUE dang RARE EUR EORR eh does 350 B 5 1 Overview of the U2SPEC Register ciis eese ht yer hohes ee EAR RE Rr E En Rs 350 B 5 2 Adjustable VME Timing Parameters llseesseeeeeeeeeeee eee eens 350 B 6 Performance SUMMA occ css eee eae a RE RR Hck De Kee e pop gus Rb od UR REC Ra RE Re 352 C Reliability Prediction i2ooas ancho ws or e o ew Fh ho ow n or ee ri Dale 355 Cel ILL T s 355 C Physical Characteristics iarciet emt e ecrire e ebd gh aec ste AE tac Ro Rae dur erates 355 C 3 Thermal Characteristics ocurreret eve were e e aren una EE DE ep RR ae E Peres o en 356 C 4 Universe II Ambient Operating Calculations sss en 357 CS VhermalVias stb 58 a UA neat ee A has rds 358 D Endian Mapping a9 9 dq ans dele n acr es obsess DR dn rn Ae ao etai pn 359 D I OVERVIEW s1 n2 244 ood ease PII AO PER EADEM SUE eg esf HR eL MUI 359 D2 ijXLittle endian Mode i occ pA Sheed ewer E RES CCeLS P Sei dp me b RR bee 359 E Typical ApplicallODs c ci xax Oh RRRECRECICOAOCRO REOR CR RC inori nidi trini Hew 363 MEE I DERE UEDEHUPIIDUMMUTU T 363 E VME Interface oiveshenro kb et Ax Hen Eun du ER ERE Re aan SOR RUE Ro eder ondes 363 E 2 1 bentes c PI r a E E a A EE E E E E E S 3
79. enabled through the MAST EN bit power up option or configured through a register access before accessing configuration ROM 9 3 1 3 Auto ID There are two Auto ID mechanisms provided by the Universe II One is the VM E64 Specification version which relies upon use of the CR CSR space for configuration of the VMEbus system and a IDT proprietary system which uses the IACK daisy chain for identifying cards in a system Either of these mechanisms can be enabled at power up see Automatic Slot Identification on page 42 Because VME64 Auto ID relies upon SYSFAIL to operate correctly this power up option overrides the SYSFAIL power up option described in SYSFAIL Assertion on page 138 9 3 1 4 BI Mode BI Mode Bus Isolation Mode is a mechanism for logically isolating the Universe II from the VMEbus for diagnostic maintenance and failure recovery purposes BI Mode can be enabled as a power up option see Bus Isolation Mode BI Mode on page 46 When the Universe II has been powered up in BI Mode then any subsequent SYSRST or RST_ restores the Universe II to BI Mode Integrated Device Technology Universe II User Manual www idt com May 12 2010 138 9 3 1 5 9 3 1 6 9 3 1 7 9 3 1 8 9 3 1 9 9 Resets Clocks and Power up Options gt Power Up Options Auto Syscon Detect The VMEbus SYSCON enabling required by the VMEbus Specification is a special power up option in that it does not return to its after power up
80. following conditions e An entire transaction no greater in length than the programmed aligned burst size is emptied from the RXFIFO e The coupled cycle is complete The DMA Channel no longer needs the PCI Master Interface when the following conditions are met e The boundary programmed into the PCI aligned burst size is emptied from the DMAFIFO during writes to the PCI bus e The boundary programmed into the PCI aligned burst size is queued to the DMAFIFO during reads from the PCI bus Access from the VMEbus can be either coupled or decoupled For a full description of the operation of these data paths see Universe II as VMEbus Slave on page 32 Command Types The PCI Master Interface can generate the following command types e O Read e I O Write Memory Read Memory Read Multiple e Memory Write e Configuration Read Type 0 and 1 e Configuration Write Type 0 and 1 The type of cycle the Universe II generates on the PCI bus depends on which VMEbus slave image is accessed and how it is programmed For example one slave image might be programmed as an I O space another as Memory space and another for Configuration space see VME Slave Image Programming on page 67 When generating a memory transaction the addressing is either 32 bit or 64 bit aligned depending upon the PCI target When generating an I O transaction the addressing is 32 bit aligned and all incoming transactions are coupled Universe Il User
81. have all been negated Because of the power up configuration the VMEbus buffers are not enabled until several CLK64 periods after release of SYSRST approximately 45 ns Allowing for worst case backplane skew of 25 ns the Universe II is not prepared to receive a slave access until 70 ns after release of SYSRST 9 3 3 Hardware Initialization Normal Operating Mode The Universe II has I O capabilities that are specific to manufacturing test functions These pins are not required in a non manufacturing test setting Table 24 shows how these pins must be terminated Table 24 Manufacturing Pin Requirements for Normal Operating Mode tmode 2 tmode 1 tmode 0 pll testsel enid pll testout VCOCTL Universe Il User Manual May 12 2010 Vss or pulled down if board tests are performed see Auxiliary Test Modes on page 141 Integrated Device Technology www idt com 9 Resets Clocks and Power up Options gt Test Modes 141 9 4 9 4 1 Test Modes The Universe II provides two types of test modes auxiliary modes NAND tree simulation and High Impedance and JTAG IEEE 1149 1 Auxiliary Test Modes Two auxiliary test modes are supported NAND tree and high impedance The Universe II has three test mode input pins TrMODE 2 0 For normal operations these inputs should be tied to ground or pulled to ground through resistors Table 25 below indicates the 3 operating modes of the Universe II At reset the TMODE 2 0 inp
82. hoe EORR RURRUR IUE ene doe eade dotate e Bond a 162 12 GOSS au du wii xad re 34H RO x cO ei t EQ o RC E ecran ul 163 IP EN uu PET C TT 163 12 2 Resister Map beet bee IER RI E Pag KORR E Me doe sack es dei e eie pane tone 164 12 3 Register Description 5 6 5 do case sei SS ERREUR EMSA LAWS REI Ac ER eee de ee t tee 171 12 3 1 PCI Configuration Space ID Register PCILID 00 0 eee eee eee 171 A Packaging Informati n iis ca cr cand e cR rh nae oa dessenat Cr wate we e 333 A 3IXPmPBGA Package ei re enaa n ahs Acer i ede bch a rid ine rc o eee DIU pon e eco ce 333 B Performance osos ak a REATO RR n TR C RO wae manne ae eee n 335 BI Overview EP EE 335 B2 PCWSlave Channel e 52e eee Sates ttle Ue Me ERES EE NVUL big Gata pa e et psa s tire 336 B 2 1 Coupled Cycles iid repere een PL Re Osee De E S Rn EEO Deoque d E ed ciea ca 336 B 2 2 Decoupled Cycles sc vrbe cese sates wince Meee esas REP ed gEEDUKe e quU E RU E 338 B3 VMESlave Channel ie ereeorR oe 2a Reese HE whe Gas Meso RR I UEDOP LEITET RE 340 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com Contents 7 B 3 1 Coupled Cyclesis lt ote eke bitin rbv ba pr Ment AS eae be Mane I ee ashe da edad 340 B 3 2 Decoupled Cycles sis soins se vetere a ii ea Nep RE eben PAIS Hell ene ees 342 B 4 DMA Channel and Relative FIFO Sizes 2 0 cece cette OETAN pE nee 347 B 4 1 VMEbus Ownership Modes 0 cet rnrn e
83. is de asserted it means that the Universe II does not transfer any more data to the master 3 4 7 1 Error During Posted Write If an error occurs during a posted write to the VMEbus the Universe II uses the AMERR field in the VMEbus AM Code Error Log V AMERR on page 307 to log the AM code of the transaction and the state of the IACK signal through the IACK bit to indicate whether the error occurred during an IACK cycle The FIFO entries for the cycle are purged The V AMERR register also records whether multiple errors have occurred with the M ERR bit although the number is not given The error log is qualified with the V STAT bit because logs are valid if the V STAT bit is set The address of the errored transaction is latched in the VMEbus Address Error Log VAERR on page 308 When the Universe II receives a VMEbus error during a posted write it generates an interrupt on the VMEbus and or PCI bus depending upon whether the VERR and VERR interrupts are enabled see Interrupt Generation and Handling on page 109 Integrated Device Technology Universe II User Manual www idt com May 12 2010 66 3 PCI Interface gt Universe II as PCI Target Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 67 4 Slave Image Programming This chapter describes the Slave Image Programming functionality of the Universe II This chapter discusses the following topics e VME Slave Image Programming o
84. not contain a valid vector Integrated Device Technology Universe II User Manual www idt com May 12 2010 258 12 Registers gt Register Description 12 3 67 VIRQ3 STATUS ID Register V3 STATID The Vx_STATID registers are read only registers that hold the 8 bit VMEbus STATUS ID that is acquired when the Universe II performs a IACK cycle for a given interrupt level Register name V3_STATID Register offset 0x32C ea ee a ee ee ee 31 24 Reserved 23 16 Reserved 15 08 Reserved 07 00 STATID 7 0 Error Status Bit 0 STATUS ID was acquired without bus error 1 bus error occurred during acquisition of the STATUS ID STATID 7 0 STATUS ID acquired during IACK cycle for level 3VMEbus Tes interrupt The Universe II is enabled as the interrupt handler for a given interrupt level via the VIRQx bits of the LINT EN register Once a vector for a given level is acquired the Universe II does not perform a subsequent interrupt acknowledge cycle at that level until the corresponding VIRQx bit in the LINT STAT register is cleared The acquisition of a level x STATUS ID by the Universe II updates the STATUS ID field of the corresponding Vx STATID register and generation of a PCI interrupt A VMEbus error during the acquisition of the STATUS ID vector sets the ERR bit which means the STATUS ID field may not contain a valid vector Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Reg
85. not clear the VME Software 5 Interrupt Status bit SW_INT4 VME Software 4 Interrupt Mask 0 VME Software 4 Interrupt masked 1 VME Software 4 Interrupt enabled A zero to one transition will cause a VME level 4 interrupt to be generated Subsequent zeroing of this bit will cause the interrupt to be masked but will not clear the VME Software 4 Interrupt Status bit Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description mame 00 nme SW INT3 VME Software 3 Interrupt Mask 0 VME Software 3 Interrupt masked 1 VME Software 3 Interrupt enabled A zero to one transition will cause a VME level 3 interrupt to be generated Subsequent zeroing of this bit will cause the interrupt to be masked but will not clear the VME Software 3 Interrupt Status bit SW_INT2 VME Software 2 Interrupt Mask 0 VME Software 2 Interrupt masked 1 VME Software 2 Interrupt enabled A zero to one transition will cause a VME level 2 interrupt to be generated Subsequent zeroing of this bit will cause the interrupt to be masked but will not clear the VME Software 2 Interrupt Status bit SW_INT1 VME Software 1 Interrupt Mask 0 VME Software 1 Interrupt masked 1 VME Software 1 Interrupt enabled A zero to one transition will cause a VME level 1 interrupt to be generated Subsequent zeroing of this bit will cause the interrupt to be masked but will not clear the VME Software 1 Interrupt Status bit
86. on the PCI bus the log only indicates that an error occurred somewhere after the latched address For a VMEbus block transfer the logged address will represent the start of the block transfer In the PCI Target Channel the Universe II generates block transfers that do not cross 256 byte boundaries the error will have occurred from the logged address up to the next 256 byte boundary In the VMEbus Slave Channel the error will have occurred anywhere from the logged address up to the next burst aligned address In the case of PCI initiated transactions all data from the errored address up to the end of the initiating transaction is flushed from the TXFIFO Since the Universe II breaks PCI transactions at 256 byte boundaries or earlier if the TXFIFO is full the data is not flushed past this point If the PCI master is generating bursts that do not cross the 256 byte boundary then again only data up to the end of that transaction is flushed Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 8 Error Handling gt Errors on Decoupled Transactions 127 In a posted write from the VMEbus all data subsequent to the error in the transaction is flushed from the RXFIFO However the length of a VMEbus transaction differs from the length of the errored PCI bus transaction For non block transfers the length always corresponds to one so only the errored data beat is flushed However if an error occurs on the PCI bus d
87. page 236 DVA 0x214 Reserved 0x218 DMA Command Packet Pointer DCPP on page 237 DCPP 0x21C Reserved 0x220 DMA General Control Status Register DGCS on page 238 DGCS 0x224 DMA Linked List Update Enable Register D_LLUE on page 241 D_LLUE 0x2280x 2FC Reserved 0x300 PCI Interrupt Enable Register LINT_EN on page 242 LINT_EN Universe Il User Manual Integrated Device Technology May 12 2010 www idt com NJ 12 Registers gt Register Map 16 Table 34 Universe II Register Map Continued Offset Register Name 0x304 PCI Interrupt Status Register LINT_STAT on page 244 LINT_STAT 0x308 PCI Interrupt Map 0 Register LINT MAPO on page 246 LINT MAPO 0x30C PCI Interrupt Map 1 Register LINT MAP1 on page 247 LINT MAP1 0x310 VMEbus Interrupt Enable Register VINT_EN on page 248 VINT_EN 0x314 VMEbus Interrupt Status Register VINT_STAT on page 251 VINT_STAT 0x318 VME Interrupt Map 0 Register VINT MAPO on page 253 VINT MAPO 0x31C VME Interrupt Map 1 Register VINT_MAP1 on page 254 VINT MAP1 0x320 Interrupt STATUS ID Out Register STATID on page 255 STATID 0x324 VIRQ1 STATUS ID Register V1 STATID on page 256 V1 STATID 0x328 VIRQ2 STATUS ID Register V2 STATID on page 257 V2 STATID 0x32C VIRQ3 STATUS ID Register V3_STATID on page 258 V3 STATID 0x330 VIRQ4 STATUS ID Register V4 STATID on page 259 V4 STATID 0x334 VIRQ5 STATUS ID Register V5 STATID
88. pre fetching slows to match the rate at which it is being read by the external VMEbus master Bandwidth consumption however remains constant only the idle time between transactions increases Figure 37 BLT Pre fetched Read Cycle Universe Il as VME Slave ICursorl 16 600 88 ns 1 Cursor2 18 345 94 ns 16 600 88 117 000 117 500 418 000 18 345 94 ns Group A Group VME Va 31 0 h zzzzzzzz FFF41000 H vam 5 0 h 3F 3z op Toros Te TT TI TT BF Vas z 4 Vd 31 0 h zzzzzzzz i Loooxxxx b i H5 H H He HE HEI vwrite 1 VdsO Vds1 Vdtack on on NON N 1 UU UU uu WU UU UU UU UU um UUU uuu ul Group PCI pclk reqnn 0 gntnn 0 BRP RRB framenn ad_low 31 0 h A5A5A5A5 A5A5A5A5 HHE 10004107C cxbenn low 3 0 h 5 5 FLO FIG irdynn 1 r s trdynn stopnn ow on RE R devselnn Universe Il User Manual Integrated Device Technology May 12 2010 www idt com B Performance gt DMA Channel and Relative FIFO Sizes 347 B 4 DMA Channel and Relative FIFO Sizes Two fixed watermarks in the DMA Channel control the Universe s II requisition of the PCI bus and VMEbus The DMAFIFO PCI Watermark is 128 bytes This me
89. register has a value of 10 and bits 1 and 0 of the DVA register are non zero e VDW field of the DCTL register has a value of 11 Single Cycle Transfers The Universe II performs 8 16 or 32 bit single cycle transfers on the VMEbus BLT and MBLT transfers cannot be performed when operating in Non Inc Mode 6 2 2 3 Non Inc Mode Performance The transfer performance of DMA in Non Inc Mode has been simulated at 14 MB s for 32 bit writes and at 8 MB s for 32 bit reads This performance was determined using ideal slave responses lower performance can be expected in actual systems Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 6 DMA Controller gt DMA Registers 89 6 2 3 Transfer Size The DMA can be programmed through the DMA Transfer Byte Count Register DTBC on page 234 to transfer any number of bytes from 1 byte to 16 MBytes There are no alignment requirements to the source or destination addresses If the width of the data turnovers 8 through 64 bit on VMEbus and 32 or 64 bit on PCI do not align to the length of the transfer or the source destination addresses the DMA inserts transfers of smaller width on the appropriate bus For example if a 15 byte transfer is programmed to start at address 0x 1000 on the VMEbus and the width is set for D32 the DMA will perform three D32 transfers followed by a DO8 transfer The Universe II does not generate unaligned transfers On a 32 bit PCI bus
90. sesso p hh RO eee iawn 6 1 OVERVIEW va us aeree E Rhbhbe Pb A EA aon dure did amore 62 DMARegisters esperanssa ria ua nena hh hh nn 6 2 1 Source and Destination Addresses 0 6 2 2 Non incrementing DMA Mode 0 6 2 3 Transfer S176 Ree ERU eR a ated ay eese 6 2 4 Transfer Data Width lees 6 2 5 DMA Command Packet Pointer 0 6 2 6 DMA Control and Status eese eess 6 3 Direct Mode Operation 0 0 cece eee eee 6 4 Linked list Mode 0 0 eee eee eens 6 4 1 Linked list Updating esses eese 6 5 FIFO Operation and Bus Ownership 0 00000 6 5 1 PCI to VMEbus Transfers 0 00 00000 6 5 2 VMEbus to PCI Transfers eese 6 6 DMA Interrupts sese eo RE LECHE RR PERS SEE 6 7 DMA Channel Interactions with Other Channels 68 DMAEBEmorHandling seeeseeeeeee eese 6 8 1 DMA Software Response to Error 0 6 8 2 DMA Hardware Response to Error 0 6 8 3 Resuming DMA Transfers 0 0 0000 7 Interrupt Generation and Handling 7 1 ONGIVIEW x ves Son rh dae heed epus e ea dees 7 2 Interrupt Generation 7 2 1 PCI Interrupt Generation 0 000000 7 2 2 VMEbus Interrupt Generation 00 7 3 Interrupt Handling 000 00 eee eee eee 7 3 1 PCI Interrupt Handling 0 000000 1
91. space and matching one of the address modifier codes specified BLTs and MBLTs are not supported VMEbus address bits 4 3 are used to set the status bit in LINT_STAT for one of the four location monitor interrupts If the Universe II VMEbus master is the owner of the VMEbus the Universe II VMEbus slave will generate DTACK to terminate the transaction The Location Monitor does not store write data and read data is undefined Register name LM CTL Register offset OXF64 EZE 24 Reserved 15 08 Reserved 07 00 Reserved Image Enable PWR VME 0 Disable 1 Enable Program Data AM Code PWR VME 00 Reserved 01 Data 10 Program 11 Both Supervisor User AM Code R W PWR VME 11 00 Reserved 01 Non Privileged 10 Supervisor 11 Both Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 301 VMEbus Address Space PWR VME 000 A16 001 A24 010 A32 011 Reserved 100 Reserved 101 Reserved 110 User1 111 User2 others Reserved Integrated Device Technology Universe II User Manual www idt com May 12 2010 302 12 Registers gt Register Description 12 3 102 Location Monitor Base Address Register LM BS The base address specifies the lowest address in the 4 Kbyte range that will be decoded as a location monitor access Register name LM_BS Register offset OxF68 LAER m BS BS 31 12 Base Address PWR VME EE Universe Il User Ma
92. the RDFIFO is removed Reading on the PCI bus does not cross a 2048 byte boundary The PCI Master Interface releases FRAME_ and the VMEbus Slave Channel relinquishes internal ownership of the PCI Master Interface when it reaches this boundary The VMEbus Slave Channel re requests internal ownership of the PCI Master Interface as soon as possible in order to continue reading from the external PCI target The PABS setting determines how much data must be available in the RDFIFO before the VMEbus Slave Channel continues reading Regardless of the read request the data width of prefetching on the PCI side is full width with all byte lanes enabled If LD64EN is set in the VMEbus Slave image the Universe II requests D64 on the PCI bus by asserting REQ64_ during the address phase If the PCI target does not respond with ACK64_ subsequent data beats are D32 Errors If an error occurs on the PCI bus the Universe II does not translate the error condition into a BERR on the VMEbus the Universe II does not directly map the error By doing nothing the Universe II forces the external VMEbus error timer to expire VMEbus Lock Commands ADOH Cycles The Universe II supports VMEbus lock commands as described in the VME64 Specification Under the specification ADOH cycles are used to execute the lock command with a special AM code see Table 1 on page 28 The purpose of the Lock command is to lock the resources on a card so a master on the card cann
93. the level programmed in the VME Interrupt Map 1 Register VINT MAPI on page 254 This method requires that the user specify in the VINT MAPI register to which line the interrupt is to be generated When the SW INT interrupt method 2 is active at the same level as one of SW INTT7 1 interrupts method 1 the SW INT interrupt method 2 takes priority While this interrupt source is active the SW INT status bit in the VINT STAT register is set This method is provided for compatibility with the original Universe device With both methods the mask bit SW INTx or SW INT in the VMEbus Interrupt Enable Register VINT EN on page 248 must be 0 in order for writing 1 to the bit to have any effect Regardless of the software interrupt method used when an IACK cycle is serviced on the VMEbus the Universe II can be programmed to generate an interrupt on the PCI bus by setting the SW IACK enable bit in the PCI Interrupt Enable Register LINT EN on page 242 see Software IACK Interrupt on page 121 Interrupting the PCI bus Through Software On the PCI bus there is only one method of directly triggering a software interrupt This method is the same as the second method described in Interrupting the VMEbus Through Software on page 120 Causing a 0 to transition in the SW INT in the LINT EN register generates an interrupt to the PCI bus While this interrupt source is active the SW INT status bit in LINT STAT is set The SW INT
94. the window defined by the base and bound addresses and the Address Modifier must match one of those specified by the address space mode and type fields The Universe II s eight VMEbus slave images images 0 to 7 are bounded by A32 space The first and fourth of these images VMEbus slave image 0 and 4 have a 4 Kbyte resolution while VMEbus slave images to 3 and 5 to 7 have 64 Kbyte resolution maximum image size of 4 Gbytes The address space of a VMEbus slave image must not overlap with the address space for the Universe II s control and status registers Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 4 Slave Image Programming gt VME Slave Image Programming 69 4 2 2 4 2 3 PCI Bus Fields The PCI bus fields specify how the VMEbus transaction is mapped to the appropriate PCI bus transaction The translation offset field allows the user to translate the VMEbus address to a different address on the PCI bus The translation of VMEbus transactions beyond 4 Gbytes results in wrap around to the low portion of the address range The LAS field controls generation of the PCI transaction command The LLRMW bit allows indivisible mapping of incoming VMEbus RMW cycles to the PCI bus via the PCI LOCK_ mechanism see VMEbus Read Modify Write Cycles RMW Cycles on page 37 When the LLRMW bit is set single cycle reads are always be mapped to single data beat locked PCI transactions Setting this bit ha
95. through the transfers in the linked list following pointers at the end of each linked list entry Linked list operation is initiated through a pointer in an internal Universe II register but the linked list itself resides in PCI bus memory Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 2 1 2 2 2 2 1 2 2 1 1 25 VMEbus Interface This chapter explains the operation of the VMEbus Interface This chapter discusses the following topics e VMEbus Requester on page 25 e Universe II as VMEbus Master on page 28 e Universe II as VMEbus Slave on page 32 e VMEbus Configuration on page 41 e Automatic Slot Identification on page 42 e System Clock Driver on page 44 Overview The VMEbus Interface incorporates all operations associated with the VMEbus This includes master and slave functions VMEbus configuration and system controller functions VMEbus Requester There are different channels in the Universe II which require the use of the VMEbus They are referred to as VMEbus requesters and are described in the following sections Internal Arbitration for VMEbus Requests Different internal channels within the Universe II require use of the VMEbus the Interrupt Channel the PCI Target Channel and the DMA Channel These three channels do not directly request the VMEbus instead they compete internally for ownership of the VMEbus Master Interface Interrupt Channel
96. use of ADOH This prevents an external PCI Master from accessing the registers of the Universe II until VMEbus BBSY is negated It also prevents other VMEbus masters from accessing the Universe II registers Integrated Device Technology Universe Il User Manual www idt com May 12 2010 82 5 Registers Overview gt Register Access from the VMEbus Figure 14 UCSR Access in VMEbus CR CSR Space VMEbus Configuration A and Status Registers VCSR UNIVERSE DEVICE SPECIFIC REGISTERS of UCSR PCI CONFIGURATION SPACE PCICS 512 Kbytes of VMEbus CR CSR Space Portion of 16 Mbyte Total for Entire VMEbus System Mapped to PCI Lo VCSR_BS Y Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 5 Registers Overview gt Mailbox Registers 83 5 4 Mailbox Registers The Universe II has four 32 bit mailbox registers which provide an additional communication path between the VMEbus and the PCI bus see Mailbox 0 Register MBOXO on page 265 to Mailbox 3 Register MBOX3 on page 268 The mailboxes support read and write accesses from either bus and may be enabled to generate interrupts on either bus when they are written to The mailboxes are accessible from the same address spaces and in the same manner as the other Universe II registers as described above Mailbox registers are useful for the communication of concise command status and parameter data The specifi
97. widths D08 EO D8BLT DIl6 DI6BIT e Da D64 D32BIT D64BLT MBLT The width of the transfer is set with the VDW field in the DCTL register The VCT bit determines whether or not the Universe II VMEbus Master will generate BLT transfers The value of this bit only has meaning if the address space is A24 or A32 and the data width is not 64 bits If the data width is 64 bits the Universe II may perform MBLT transfers independent of the state of the VCT bit Integrated Device Technology Universe Il User Manual www idt com May 12 2010 90 6 2 5 6 2 6 6 2 6 1 6 DMA Controller gt DMA Registers The Universe II can perform data transfers smaller than that programmed in the VDW field in order to bring itself into alignment with the programmed width For example if the width is set for D32 and the starting VMEbus address is 0x101 the DMA performs a D08 cycle Only once it has achieved the alignment set in the VDW field does it start D32 transfers At the end of the transfer the DMA also performs more low width transfers if the last address is not aligned to VDW Similarly if the VCT bit is set to enable block transfers the DMA can perform non block transfers to bring itself into alignment On the PCI bus the DMA provides the option of performing 32 or 64 bit PCI transactions through the LD64EN bit in the DMA Transfer Control Register DCTL on page 232 If the Universe II has powered up on a 32 bit bus see
98. 0 Figure 30 Several Non Block Decoupled Writes Universe Il as VME Master VMEbus B Performance gt VME Slave Channel A 31 1 AS T D 31 0 WRITE DTACK LI Est DS0 DS1 4 Figure 31 BLT Decoupled Write Universe Il as VME Master VMEbus A 31 1 AS D 31 0 WRITE DSO DSi DTACK B 3 B 3 1 B 3 1 1 Universe Il User Manual May 12 2010 VME Slave Channel This channel supports both coupled and decoupled transactions Each type of transaction and the performance of each are discussed in the following sections Coupled Cycles The Universe II VME Slave Channel handles both block and non block coupled accesses in similar manners Each data beat is translated to a single PCI transaction Once the transaction has been acknowledged on the PCI bus the Universe II asserts DTACK to terminate the VME data beat Block vs non Block Transfers A non block transfer and the first beat of a BLT transfer have identical timing In each the Universe II decodes the access and then provides a response to the data beat Subsequent data beats in the BLT transfer are shorter than the first due to the fact that no address decoding need be perf
99. 0 PCI Bus Memory Space 01 PCI Bus I O Space 10 PCI Bus Configuration Space 11 Reserved Integrated Device Technology Universe II User Manual www idt com May 12 2010 316 12 Registers gt Register Description 12 3 114 VMEbus Slave Image 5 Base Address Register VSI5_ BS The base address specifies the lowest address in the address range that is decoded Register name VSI5_BS Register offset OXFA8 BS 31 16 Base Address PWR VME Low Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 317 12 3 115 VMEbus Slave Image 5 Bound Address Register VSI5_BD The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register If the bound register is 0 then the addresses decoded are those greater than or equal to the base address Register name VSI5_BD Register offset OXFAC 23 16 BD 31 16 Bound Address PWR VME Integrated Device Technology Universe Il User Manual www idt com May 12 2010 318 12 Registers gt Register Description 12 3 116 VMEbus Slave Image 5 Translation Offset VSI5 TO The translation offset is added to the source address that is decoded and this new address becomes the destination address If a negative offset is desired the offset must be expressed as a two s complement Register name VSI5_TO Register offset OxFBO TO 31 16 Translation Offs
100. 0 on consecutive cycles and 100pF loading on the PCI bus In the majority of system applications the Universe II consumes typical values or less Typical power consumption numbers are based on the Universe II remaining idle 3096 5046 of the time which is significantly less than what is considered likely in most systems For this reason it is recommended that typical power consumption numbers be used for power estimation and ambient temperature calculations as described below The HTOL FIT rate is 67 FITs The HTOL test showed 67 FITs based on the calculation of 60 Confidence Level C L and Activation Energy Ea 0 7eV for 0 5um process at stress condition 1 1 x Vcc at 125 C ambient temperature This FIT rate is approximately equivalent to 90 C L 167 FITs Calculations were based on a 100 piece sample size for three lots The test conditions were at 125 C Bias 5 5 V at 1 MHz per MIL STD 883D M1015 8 FIT is the basic reliability rate expressed as failures per billion 1e 9 device hours Mean Time Between Failures MTBF is the reciprocal of FIT MTBF is the predicted number of device hours before a failure will occur Universe Il User Manual Integrated Device Technology May 12 2010 www idt com C Reliability Prediction gt Universe Il Ambient Operating Calculations 357 C 4 Universe Il Ambient Operating Calculations The maximum ambient temperature of the Universe II can be calculated as follows Ta lt Tj Oja P Where
101. 1 Location Monitors The Universe II can be programmed to generate an interrupt on the PCI bus when one of its four location monitors is accessed see Location Monitors on page 38 In order for an incoming VMEbus transaction to activate the location monitor of the Universe II the following criteria must be met e Location monitor must be enabled Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 7 Interrupt Generation and Handling gt Interrupt Handling 123 7 3 3 7 7 3 4 e Access must be within 4 kbytes of the location monitor base address see Location Monitor Base Address Register LM BS on page 302 e t must be in the specified address space When an access to a location monitor is detected an interrupt may be generated on the PCI bus if the location monitor is enabled There are four location monitors VA 4 3 00 selects Location Monitor 1 VA 4 3 2 01 selects Location Monitor 2 e VA 4 3 10 selects Location Monitor 3 and VA 4 3 11 selects Location Monitor 4 An interrupt response to the access of any location monitor can be enabled or disabled with bits in the PCI Interrupt Enable Register LINT EN on page 242 Access to each location monitor can be individually mapped to a specific interrupt on the PCI bus through the PCI Interrupt Map 2 Register LINT MAP2 on page 263 not to the VMEbus bus The status of the PCI interrupt is logged in the LM
102. 1 psi 1 DTACK PCI CLK FRAMES AD 31 0 L C BE 3 0 35 IRDY TRDY STOP DEVSEL Figure 36 MBLT Decoupled Write Cycle Universe Il as VME Slave VMEbus A 31 1 AM 5 0 4 AS 1 D 31 0 WRITE DSO g f l psi 4 L DTACK U m PCI CLK UUU O C UU UELLE LELFEFEEUEUUEUETLEU UELELFLTUEUELFLEUEEELE UL UELUT REOR GNT FRAME AD 31 0 C BE 3 0 IRDY TRDY STOP DEVSEL PCI Master Performance The Universe II supports bus parking If the Universe II requires the PCI bus it will assert REQ_ only if its GNT_ is not currently asserted When the PCI Master Module is ready to begin a transaction a
103. 1 12 PCI 11 0 Y Y Y VME 31 12 VME 11 0 Translations beyond the 4 Gbyte limit will wrap around to the low address range The Universe II provides support for user defined AM codes The User AM Codes Register USER AM on page 276 contains AM codes identified as Userl and User2 The USER AM register can only be used to generate and accept AM codes 0x10 through Ox1F These AM codes are designated as USERAM codes in the VMEbus Specification If the user selects one of these two then the corresponding AM code from the global register is generated on the VMEbus This approach results in standard single cycle transfers to A32 VMEbus address space independent of other settings in the VMEbus fields The VCT bits in the PCI Target Image 0 Control LSIO_CTL on page 181 determine whether or not the VMEbus Master Interface will generate BLT transfers The VCT bit will only be used if the VAS field is programmed for A24 or A32 space and the VDW bits are programmed for 8 16 or 32 bits If VAS bits of the control register are programmed to A24 or A32 and the VDW bits are programmed for 64 bit the Universe II may perform MBLT transfers independent of the state of the VCT bit 4 3 2 1 Transfers Transfers appear on the VMEbus as 16 bit transfers when the Universe II is programmed in the following manner e PWEN 1 e VDW 16 bit 32 bit or 64 bit e VCT 0 External PCI master begins a burst 32 bit write with A2 0 and BE_ 0011 followed by a t
104. 1 IRDY TRDY STOP DEVSEL Figure 28 Several Coupled Read Cycles Universe Il as VME Master VMEbus A 31 1 ast 3 D 31 0 WRITE DSO f DS1 I DTACK L LH Lt PCI eu JU UU UU Ue UU UU PLLA FRAMER AD 31 0 rH H H H C BE 3 0 H H H H IRDY TRDY STOP DEVSEL Integrated Device Technology Universe Il User Manual www idt com May 12 2010 338 B 2 1 3 B Performance gt PCI Slave Channel Write Cycles The performance of coupled write cycles is similar to that of coupled read cycles except that an extra wait state is inserted Figure 29 shows a coupled write cycle against an ideal VME slave Ten wait states are inserted on the PCI bus by the Universe II before it responds with TRDY_ A slower VME slave response translates directly to more wait states on the PCI bus The sustained performance when generating write cycles from a 32 bit PCI bus against an ideal VME slave is approximately 9 3 MB s Figure 29 Coupled Write Cycle Universe Il as VME Master VMEbus
105. 1 16 in Offsets VMEbus slave address to a selected VSIx TO PCI address Address space LAS in VSIx CTL Memory I O Configuration LLRMW in VSIx_CTL RMW enable bit Table 6 Control Fields for VMEbus Slave Image Image enable EN in VSIx CTL Enable bit Posted write PWEN in VSIx CTL Posted write enable bit Prefetched read PREN in VSIx CTL Prefetched read enable bit Enable PCI D64 LD64EN in VSIx CTL Enables 64 bit PCI bus transactions The Bus Master Enable BM bit of the PCI CS register must be set in order for the image to accept posted writes from an external VMEbus master If this bit is cleared while there is data in the VMEbus Slave Posted Write FIFO the data is written to the PCI bus but no further data is accepted into this FIFO until the bit is set IDT recommends that the attributes in a slave image not be changed while data is enqueued in N the Posted Writes FIFO To ensure data is queued from the FIFO check the RXFE status bit in the Miscellaneous Status Register MISC_STAT on page 275 or perform a read from that image If the programming for an image is changed after the transaction is queued in the FIFO the transaction s attributes are not changed Only subsequent transactions are affected by the change in attributes 4 2 1 VMEbus Fields Decoding for VMEbus accesses is based on the address and address modifiers produced by the VMEbus master Before responding to an external VMEbus master the address must lie in
106. 144 10 Signals and Pinout gt VMEbus Signals 10 2 VMEbus Signals Table 26 VMEbus Signals Reference Clock this 64MHz clock is used to generate fixed timing parameters It requires a 50 50 duty cycle 20 with a 5ns maximum rise time CLK64 is required to synchronize the internal state machines of the VME side of the Universe ll VA 31 1 Bidirectional VMEbus Address Lines 31 to 01 during MBLT transfers VA 31 01 serve as data bits D63 D33 VAO3 01 are used to indicate interrupt level on the VMEbus VMEbus Address Transceiver Direction Control the Universe II controls the direction of the address VA31 01 VLWORD transceivers as required for master slave and bus isolation modes When the Universe II is driving lines on the VMEbus this signal is driven high when the VMEbus is driving the Universe ll this signal is driven low VMEbus Address Modifier Codes these codes indicate the address space being accessed A16 A24 A32 the privilege level user supervisor the cycle type standard BLT MBLT and the data type program data VMEbus AM Code Direction Control controls the direction of the AM code transceivers as required for master slave and bus isolation modes When the Universe II is driving lines on the VMEbus this signal is driven high when the VMEbus is driving the Universe II this signal is driven low Bidirectional VMEbus Address Strobe the falling edge of VAS indicates a valid address o
107. 193 LSI2 BS 0x130 PCI Target Image 2 Bound Address Register LSI2 BD on page 194 LSI2 BD 0x134 PCI Target Image 2 Translation Offset LSI2 TO on page 195 LSI2 TO 0x138 Reserved 0x13C PCI Target Image 3 Control LSI3_CTL on page 196 LSI3_CTL 0x140 PCI Target Image 3 Base Address Register LSI3_BS on page 198 LSI3_BS 0x144 PCI Target Image 3 Bound Address Register LSI3 BD on page 199 LSI3_BD 0x148 PCI Target Image 3 Translation Offset LSI3_TO on page 200 LSI3 TO 0x14C 0x16C Reserved 0x170 Special Cycle Control Register SCYC_CTL on page 201 0x174 Special Cycle PCI Bus Address Register SCYC_ADDR on page 202 0x178 Special Cycle Swap Compare Enable Register SCYC_EN on page 203 0x17C Special Cycle Compare Data Register SCYC_CMP on page 204 0x180 Special Cycle Swap Data Register SCYC_SWP on page 205 0x184 PCI Miscellaneous Register LMISC on page 206 0x188 Special PCI Target Image SLSI on page 208 0x18C PCI Command Error Log Register L CMDERR on page 210 0x190 PCI Address Error Log LAERR on page 211 0x194 0x19C Reserved 0x1A0 PCI Target Image 4 Control Register LSI4_CTL on page 212 LSI4 CTL Ox1A4 PCI Target Image 4 Base Address Register LSI4 BS on page 214 LSI4 BS 0x1A8 PCI Target Image 4 Bound Address Register LSI4_BD on page 215 LSI4_BD Ox1AC PCI Target Image 4 Translation Offset LSl4 TO on page 216 LSI4 TO Ox1BO Reserved Integrated
108. 2 3 5 6 and 7 have a 64Kbyte resolution Register name LSIO_BD Register offset 0x108 Sipe eae eas eee 23 16 Reset Description Type Reset by value 31 28 BD 31 28 Bound Address Address i oe Undefined mtn Pree a Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 185 12 3 11 PCI Target Image 0 Translation Offset LSIO_TO The translation offset for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution PCI Target Images 1 2 3 5 6 and 7 have a 64Kbyte resolution Address bits 31 12 generated on the VMEbus in response to an image decode are a two s complement addition of address bits 31 12 on the PCI Bus and bits 31 12 of the image s translation offset Register name LSIO TO Register offset 0x10C Reset Description Type Reset by value 3112 TO 31312 Translation Offset CARRET Integrated Device Technology Universe II User Manual www idt com May 12 2010 186 12 Registers gt Register Description 12 3 12 PCI Target Image 1 Control LSI1_CTL In the PCI Target Image Control register setting the VCT bit will only have effect if the VAS bits are programmed for A24 or A32 space and the VDW bits are programmed for 8 bit 16 bit or 32 bit If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64 bit the Universe II may perform MBLT transfers independent of the state of the VCT bi
109. 2 12 Registers gt Register Description Mailbox 2 Status Clear R Write 1 Bl 0 no Mailbox 2 Interrupt to clear 1 Mailbox 2 Interrupt active MBOX1 Mailbox 1 Status Clear R Write 1 0 no Mailbox 1 Interrupt to clear 1 Mailbox 1 Interrupt active MBOXO Mailbox 0 Status Clear R Write 1 0 no Mailbox 0 Interrupt to clear 1 Mailbox 0 Interrupt active VERR VERR Interrupt Status Clear R Write 1 0 VME VERR Interrupt masked to Clear 1 VME VERR Interrupt enabled LERR LERR Interrupt Status Clear R Write 1 0 VME LERR Interrupt masked to Clear 1 VME LERR Interrupt enabled DM DMA Interrupt Status Clear R Write 1 0 VME DMA Interrupt masked to Clear 1 VME DMA Interrupt enabled LINT7 LINTO LINTx Interrupt Status Clear R Write 1 A O LINTx Interrupt masked to Clear 1 LINTx Interrupt enabled SW_INT VME Software Interrupt Status Clear R Write 1 All Power up 0 VME Software Interrupt inactive to Clear Option 1 VME Software Interrupt active II Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 253 12 3 62 VME Interrupt Map 0 Register VINT MAPO Register name VINT MAPO Register offset 0x318 EA ee aS eases LINT7 LINTO VMEbus destination of PCI Bus interrupt source rw o w 0 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 254 12 Registers gt Register Description 12 3 63 VME Interrupt Map 1 Register VINT MAP1
110. 5 D55 D16 D23 A8 A15 E ELI MEC D 6028 lt gt ABAIB DODA Ea E D31 LWORD A1 A7 D32 D24 D31 lt gt LWORD A1 A7 032 039 Second Transfer D0 D31 D8D15 te D15 D16 D23 SS D23 D8 D15 ELE NN D24031 e ODF D0 D7 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 362 D Endian Mapping gt Little endian Mode Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 363 E Typical Applications This chapter discusses the following topics e VME Interface on page 363 e PCI Bus Interface on page 368 e Manufacturing Test Pins on page 370 e Decoupling VDD and VSS on the Universe IT on page 371 E 1 Overview Being a bridge between standard interfaces the Universe II requires minimal external logic to interface to either the VMEbus or to the PCI bus In most applications only transceivers to buffer the Universe II from the VMEbus plus some reset logic are all that is required The following information should be used only as a guide in designing the Universe II into a PCI VME application Each application will have its own set up requirements E 2 VME Interface E 2 1 Transceivers The Universe II has been designed such that it requires full buffering from VMEbus signals Necessary drive current to the VMEbus is provided by the transceivers while at the same time isolating the Universe II from potentially noisy V
111. 6 STATID Register offset 0x338 ENERO EUR EUNT 31 24 Reserved 23 16 Reserved 15 08 Reserved 07 00 STATID 7 0 Error Status Bit 0 STATUS ID was acquired without bus error 1 bus error occurred during acquisition of the STATUS ID STATID 7 0 STATUS ID acquired during IACK cycle for level 6 VMEbus ey eT es interrupt The Universe II is enabled as the interrupt handler for a given interrupt level via the VIRQx bits of the LINT_EN register Once a vector for a given level is acquired the Universe II does not perform a subsequent interrupt acknowledge cycle at that level until the corresponding VIRQx bit in the LINT_STAT register is cleared The acquisition of a level x STATUS ID by the Universe II updates the STATUS ID field of the corresponding Vx_STATID register and generation of a PCI interrupt A VMEbus error during the acquisition of the STATUS ID vector sets the ERR bit which means the STATUS ID field may not contain a valid vector Integrated Device Technology Universe II User Manual www idt com May 12 2010 262 12 Registers gt Register Description 12 3 71 VIRQ7 STATUS ID Register V7_STATID The Vx_STATID registers are read only registers that hold the 8 bit VMEbus STATUS ID that is acquired when the Universe II performs a IACK cycle for a given interrupt level Register name V7_STATID Register offset 0x33C PEERS 31 24 Reserved 23 16 Reserved 15 08 Reserved 07 00 STATID 7 0 Error Status Bit 0 S
112. 63 E 2 2 Direc om contol ssassn EL 367 E 2 3 Power up Options soit so seed BEE Mak 5 5 Dk OS RE RARO RR CRAT X SE sabe oe e RR 367 E3 PCILBusTnterface uy txR TP EERERERRREER RAS bea RE iow aula wd EE Rp EIE PESE 368 E 3 1 ho jj P g coh sed Mea aad Cae w kee ee Lh pe seals ae eet hou E awe eee 369 E 3 2 Local Interrupts err eDLeRERC UEM PERI Rd UCERE ERR CROP E age be IUDPEES 370 E4 Manufacturing Test Pins inre Re ER RES ER hr kk ek RA e Sce rece od a RN ec ee aia a 370 E 5 Decoupling VDD and VSS on the Universe IH leslseeeeeeeeeeeeeee II 371 E Ordering Information iesse suu RR Ra Ra oo ee rawerExrtR PG das E nas 373 Fl Ordering Informations serer taad Ra oe GREER Se REF REEL EE DERI RU bee DENS ae Te ee 373 Integrated Device Technology www idt com Universe II User Manual May 12 2010 8 Contents Universe Il User Manual Integrated Device Technology May 12 2010 www idt com Figures Figure 1 Universe II Block Diagram 1 2 cece eee Figure 2 Universe II In Single Board Computer Application 000 Figure 3 Universe II Data Flow Diagram sssseeeeeee I Figure 4 VMEbus Slave Channel Dataflow 0 0 eee Figure 5 Timing for Auto ID Cycle hh hn Figure 6 PCI Bus Target Channel Dataflow ssleeesseeeeeeee esee Figure 7 Register Fields for the Special Cycle Generator 0 0 000005 Figure 8 Address Translation Me
113. AM Code R W All 0x00 0 Non Privileged 1 Supervisor wmm em L8 E VMEbus Cycle Type R W All 0x00 0 No BLTs on VMEbus 1 Single BLTs on VMEbus a m0 fa PCI Bus Memory Space R W All Undefined 0 PCI Bus Memory Space 1 PCI Bus I O Space Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 193 12 3 17 PCI Target Image 2 Base Address Register LSI2 BS The base address specifies the lowest address in the address range that will be decoded Register name LSI12_BS Register offset 0x12C BBs Ese ESAs Reset Description Type Reset by value Integrated Device Technology Universe II User Manual www idt com May 12 2010 194 12 Registers gt Register Description 12 3 18 PCI Target Image 2 Bound Address Register LSI2_BD The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register If the bound address is 0 then the addresses decoded are those greater than or equal to the base address Register name LSI2_BD Register offset 0x130 Se Ee re eee eee LONE XN E Reset Description Type Reset by value Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 195 12 3 19 PCI Target Image 2 Translation Offset LSI2_TO Address bits 31 16 generated on the VMEbus in response to an image decode are a two s complement
114. All the contents of this register Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 205 12 3 28 Special Cycle Swap Data Register SCYC SWP If enabled bits matched with the value in the compare register then the contents of the swap data register is written back to VME SCYC EN is used to control which bits are written back to VME Register name SCYC SWP Register offset 0x180 Reset Description Type Reset by value Integrated Device Technology Universe Il User Manual www idt com May 12 2010 206 12 Registers gt Register Description 12 3 29 PCI Miscellaneous Register LMISC This register can only be set at configuration or after disabling all PCI Target Images Register name LMISC Register offset 0x184 3124 24 CRT 3 0 Reserved 6 e 15 08 Reserved 07 00 Reserved CRT 3 0 This field is provided for backward compatibility with the Universe I It has no effect on the operation of the Universe II CWT 2 0 Coupled Window Timer 000 Disable release after first coupled transaction 001216 PCI Clocks 010232 PCI Clocks 011264 PCI Clocks 100 128 PCI Clocks 1012256 PCI Clocks 1102512 PCI Clocks others Reserved Reset Description Reset by value This field is provided for backward compatibility with All 0x00 the Universe I It has no effect on the operation of the Universe Il Eee em o qo pm Universe Il User Manual Integr
115. C STAT DY4AUTO MISC_CTL V64AUTO Disabled VD 28 Enabled VBGIN 3 Asserted VD 27 Disabled VA 13 S Memory VA 12 S S S A16 VA 11 10 N A S O N A S 0x0 VA 9 6 0x0 VA 5 2 See Registers on page 163 VA 1 32 bit REQ64_ A SYSFAIL Assertion SYSFAIL SYSFAIL PCI Target Image LSIO CTL E LA V PCI BS1 PCI Bus Size LCLSIZE PCI CSR Master Enable BM a All power up options are latched only at the rising edge of PWRRST They are loaded when PWRRST SYSRST and RST are negated Disabled VA 14 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 136 9 3 1 9 3 1 1 9 Resets Clocks and Power up Options gt Power Up Options b The PCI Bus Size is loaded on any RST_ event PCI 2 1 Specification The majority of the Universe II power up options are loaded from the VMEbus address and data lines after any PWRRST_ see Table 22 on page 135 The PCI bus width a power up option required by the PCI 2 1 Specification is loaded on any RST_ event from the REQ64 pin The second special power up option is VMEbus SYSCON enabling required by the VMEbus specification The SYSCON option is loaded during a SYSRST event from the BG3IN signal All power up options are latched from the state of a particular pin or group of pins on the rising edge of PWRST Each of these pins except REQ64 has a weak internal pull down to put the Universe II into a default configur
116. C register and program the DCPP register to point to the first command packet in the list When using the DMA to perform linked list transfers it is important to ensure that the DTBC register contains a value of zero before setting the GO bit of the DGCS register Otherwise the DMA cannot read the first command packet but instead performs a direct mode transfer based on the contents of the DCTL DTBC DLA DVA and DGCS registers After this direct mode transfer is completed the PROCESSED bit of the first command packet is programmed with a value of 1 even though the packet was not actually processed The DMA continues as expected with the next command packet In Step 4 to start the linked list transfer set the GO bit in the DGCS register The DMA first performs the transfers defined by the current contents of the DCTL DTBC DVA and DLA registers Once that is complete it then starts the transfers defined by the linked list pointed to in the DCPP register In Step 5 await and deal with termination of the DMA Once the DMA channel is enabled it processes the first command packet as specified by the DCPP register The DMA transfer registers are programmed by information in the command packets and the DMA transfer steps along each command packet in sequence see Figure 16 The DMA terminate when one of the following conditions are met Processes a command packet with the NULL bit set indicating the last packet of the list
117. CI data beat on a 32 bit PCI bus accessing a PCI target image with VDW set to 16 bit The three byte PCI data beat will be broken into three aligned VMEbus cycles three single byte cycles If in the above example the PCI target image has a VDW set to 8 bit then the three byte PCI data beat will be broken into three single byte VMEbus cycles Coupled Transfers The PCI Target Channel supports coupled transfers A coupled transfer through the PCI Target Channel is a transfer between PCI and VME where the Universe II maintains ownership of the VMEbus from the beginning to the end of the transfer on the PCI bus and where the termination of the cycle on the VMEbus is relayed directly to the PCI master in the normal manner Target Abort or Target Completion rather than through error logging and interrupts Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 3 PCI Interface gt Universe II as PCI Target 59 By default all PCI target images are set for coupled transfers Coupled transfers typically cause the Universe II to go through three phases the Coupled Data Transfer Phase and then the Coupled Wait Phase When an external PCI Master attempts a data transfer through a slave image programmed for coupled cycles and the Universe II currently owns the VMEbus the PCI Target Channel moves directly to the Coupled Data Transfer Phase 3 4 3 1 Coupled Data Transfer Phase At the beginning of the Coupled Data Transf
118. CK_ is negated on the PCI bus when AS is negated on the VMEbus LOCK_ is not negated when AS is negated if LOCK_ was asserted by an ADOH lock command 2 4 5 VMEbus Read Modify Write Cycles RMW Cycles A read modify write RMW cycle allows a VMEbus master to read from a VMEbus slave and then write to the same resource without relinquishing bus tenure between the two operations Each of the Universe II slave images can be programmed to map RMW transactions to PCI locked transactions If the LLRMW enable bit is set in the selected VMEbus Slave Image 1 Control VSI1_CTL on page 285 then every non block slave read is mapped to a coupled PCI locked read LOCK_ is held on the PCI bus until AS is negated on the VMEbus Every non block slave read is assumed to be a RMW since there is no possible indication from the VMEbus master that the single cycle read is just a read or the beginning of a RMW i RMW cycles are not supported with unaligned or D24 cycles If the LLRMW enable bit is not set and the Universe II receives a VMEbus RMW cycle the read and write portions of the cycle are treated as independent transactions on the PCI bus a read followed by a write The write can be coupled or decoupled depending on the state of the PWEN bit in the accessed slave image There can be an adverse performance impact for reads that are processed through a e RMW capable slave image This can be increased if LOCK_ is currently owned by another PCI master
119. CS register Issues with Non Inc Mode The VMEbus Address In Non Inc Mode the DVA register offset 0x210 does not necessarily contain the fixed VMEbus address This register must not be read during a DMA Non Inc Mode transfer Once a DMA transfer has been stopped by setting the STOP bit of the DGCS register the Non Inc Mode transfer cannot be restarted by simply writing a 1 to the GO bit of the DGCS register The DVA register must be reprogrammed with the required address before setting the DGCS GO bit The VON Counter When the VON counter in the DGCS register reaches its programmed limit the VMEbus Master Interface of the Universe II stops transferring data until the VOFF timer expires If the device is operating in Non Inc Mode the VON counter has different limits than those indicated in the DMA Controller section Integrated Device Technology Universe Il User Manual www idt com May 12 2010 88 6 DMA Controller gt DMA Registers The different settings are detailed in Table 14 Table 14 VON Settings for Non Inc Mode P_ERR Flag Behavior When the GO bit is set in Non Inc Mode the P_ERR flag of the DMA General Control Status Register DGCS on page 238 is 1 when the following conditions are true e VCT bit of the DMA Transfer Control Register DCTL on page 232 has a value of 1 e VDW field of the DCTL register has a value of 01 and bit 0 of the DVA register is a value of 0 e VDW field of the DCTL
120. DGCS ith tenure and interrupt requirements Step 2 Program source destination addresses amp transfer size attributes Step 3 Ensure status bits are clear Step 4 Set GO bit Step 5 Await termination of DMA Normal Termination More transfers required Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 6 DMA Controller gt Direct Mode Operation 95 In Step 1 the DMA General Control Status Register DGCS on page 238is set up The CHAIN bit is cleared VON and VOFF are programmed with the appropriate values for controlling DMA VMEbus tenure and the interrupt bits INT_STOP INT_HALT INT_DONE INT_LERR INT_VERR and INT_P_ERR are programmed to enable generation of interrupts based on DMA termination events DMA interrupt enable bits in the LINT_EN or VINT_EN bits should also be enabled as necessary see PCI Interrupt Generation on page 111 and VMEbus Interrupt Generation on page 113 for details on generating interrupts In Step 2 the actual transfer is programmed into the DMA Source and destination start addresses into the DLA and DVA registers transfer count into the DTBC register and transfer width direction and VMEbus address space into the DCTL register These should be reprogrammed after each transfer In Step 3 ensure that if any status bits DONE STOP HALT LERR VERR or P_ERR remain set from a previous transfer they are c
121. Data Register during a RMW cycle SCYC_CMP on page 204 32 bit swap SWP 31 0 in Special Cycle Data which is swapped with the VMEbus read data and Swap Data Register written to the original address SCYC_SWP on page 205 during a RMW cycle The following sections describe the specific properties for each of the transfer types RMW and ADOH 3 4 5 1 Read Modify Write When the SCYC field is set to RMW any PCI bus read access to the specified PCI bus address SCYC_ADDR register results ina RMW cycle on the VMEbus provided the constraints listed below are satisfied RMW cycles on the VMEbus consist of a single read followed by a single write operation The data from the read portion of the RMW on the VMEbus is returned as the read data on the PCI bus RMW cycles make use of three 32 bit registers see Table 7 The bit enable field is a bit mask which lets the user specify which bits in the read data are compared and modified in the RMW cycle This bit enable setting is completely independent of the RMW cycle data width which is determined by the data width of the initiating PCI transaction During a RMW the VMEbus read data is bitwise compared with the SCYC_CMP and SCYC_EN registers The valid compared and enabled bits are then swapped using the SCYC_SWP register Each enabled bit that compares equal is swapped with the corresponding bit in the 32 bit swap field A false comparison results in the original bit being written back In
122. Device Technology Universe Il User Manual www idt com May 12 2010 166 12 Registers gt Register Map Table 34 Universe Il Register Map Continued Offset Register Name 0x1B4 PCI Target Image 5 Control Register LSI5_CTL on page 217 LSI5_CTL 0x1B8 PCI Target Image 5 Base Address Register LSI5_BS on page 219 LSI5_BS 0x1BC PCI Target Image 5 Bound Address Register LSI5_BD on page 220 LSI5 BD 0x1C0 PCI Target Image 5 Translation Offset LSI5_TO on page 221 LSI5_TO 0x1C4 Reserved 0x1C8 PCI Target Image 6 Control Register LSI6_CTL on page 222 LSI6_CTL 0x1CC PCI Target Image 6 Base Address Register LSI6_BS on page 224 LSI6_BS 0x1D0 PCI Target Image 6 Bound Address Register LSI6_BD on page 225 LSI6 BD 0x1D4 PCI Target Image 6 Translation Offset LSI6_TO on page 226 LSI6_TO 0x1D8 Reserved 0x1DC PCI Target Image 7 Control Register LSI7_CTL on page 227 LSI7_CTL 0x1E0 PCI Target Image 7 Base Address Register LSI7_BS on page 229 LSI7_BS 0x1E4 PCI Target Image 7 Bound Address Register LSI7_BD on page 230 LSI7_BD Ox1E8 PCI Target Image 7 Translation Offset LSI7 TO on page 231 LSI7 TO 0x1EC 0x1FC Reserved 0x200 DMA Transfer Control Register DCTL on page 232 DCTL 0x204 DMA Transfer Byte Count Register DTBC on page 234 DTBC 0x208 DMA PCI Bus Address Register DLA on page 235 DLA 0x20C Reserved 0x210 DMA VMEbus Address Register DVA on
123. E LERR VERR and P_ERR and are located in the DMA General Control Status Register DGCS on page 238 These bits are all cleared by writing 1 to them either before or while setting the GO bit The GO bit always returns a 0 when read independent of the DMA s current state Clearing the bit has no impact at any time The ACT bit in the DGCS register indicates whether the DMA is currently active It is set by the DMA once the GO bit is set and cleared when the DMA is idle Generally when the ACT bit is cleared one of the other status bits in the DGCS register is set DONE STOP HALT LERR VERR or P ERR indicating why the DMA is no longer active DMA VMEbus Ownership Two fields in the DGCS register determine how the DMA shares the VMEbus with the other two potential masters in the Universe II PCI Target Channel and Interrupt Channel and with other VMEbus masters on the bus These fields are VON and VOFF VON VON affects how much data the DMA transfers before giving the opportunity to another master either the Universe II or an external master to assume ownership of the bus The VON counter is used to temporarily stop the DMA from transferring data once a programmed number of bytes have been transferred 256 bytes 512 bytes 1K 2K 4K 8K or 16K When performing MBLT transfers on the VMEbus the DMA stops performing transfers within 2048 bytes after the programmed VON limit has been reached When not performing MBLT transfer
124. E 09 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 324 12 Registers gt Register Description 12 3 121 VMEbus Slave Image 7 Control VSI7 CTL This register provides the general VMEbus and PCI controls for this slave image Note that only transactions destined for PCI Memory space are decoupled the posted write RXFIFO generates on Memory space transactions on the PCI Bus In order for a VMEbus slave image to respond to an incoming cycle the BM bit in the PCI CSR register must be enabled The state of PWEN and PREN are ignored if LAS is not programmed memory space Register name VSI7 CTL Register offset OXFCC 15 08 Reserved Image Enable PWR VME 0 Disable 1 Enable Posted Write Enable PWR VME 0 Disable 1 Enable R W PWR VME 0 Disable 1 Enable Program Data AM Code R W PWR VME 11 00 Reserved 01 Data 10 Program 11 Both Supervisor User AM Code PWR VME 00 Reserved Universe Il User Manual Integrated Device Technology May 12 2010 www idt com Prefetch Read Enable 01 Non Privileged 10 Supervisor 11 Both 12 Registers gt Register Description 325 VAS VMEbus Address Space R W PWR VME 000 Reserved 001 A24 010 A32 011 Reserved 100 Reserved 101 Reserved 110 User1 111 User2 LD64EN Enable 64 bit PCI Bus Transactions R W PWR VME 0 Disable 1 Enable LLRMW Enable PCI Bus Lock of VMEbus RMW R W PWR VME 0 Disable 1 Enable LAS PCI Bus Address Space R W PWR
125. Ebus while the Universe II is performing an IACK cycle is handled by the Universe II in two ways The first is through the error logs in the VMEbus Master Interface These logs store address and command information whenever the Universe II encounters a bus error on the VMEbus see Error Handling on page 125 If the error occurs during an IACK cycle the IACK_ bit is set in the VMEbus AM Code Error Log V AMERR on page 307 The VMEbus Master Interface also generates an internal interrupt to the Interrupt Channel indicating a VMEbus error occurred This internal interrupt can be enabled and mapped to either the VMEbus or PCI bus As well as generating an interrupt indicating an error during the IACK cycle the Universe II also generates an interrupt as though the IACK cycle completed successfully If an error occurs during the fetching of the STATUS ID the Universe II sets the ERR bit in the Interrupt STATUS ID Out Register STATID on page 255 and generates an interrupt on the appropriate LINT pin as mapped in the PCI Interrupt Map 0 Register LINT MAPO on page 246 The PCI resource upon receiving the PCI interrupt is expected to read the Interrupt STATUS ID Out Register STATID on page 255 and take appropriate actions if the ERR bit is set Note that the STATUS ID cannot be considered valid if the ERR bit is set in the STATUS ID register It is important to recognize that the IACK cycle error can generate two PCI interrupts
126. I Mode option off see BI Mode on page 137 or Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 2 VMEbus Interface gt Automatic Slot Identification 47 e Clear the BI bit in the MISC_CTL register This is effective only if the source of the BI Mode is no longer active If VRIRQ_ 1 is still being asserted while the ENGBI bit in the MISC_CTL register is set then attempting to clear the BI bit in the MISC_CTL register does not work Integrated Device Technology Universe II User Manual www idt com May 12 2010 48 Universe II User Manual May 12 2010 2 VMEbus Interface gt Automatic Slot Identification Integrated Device Technology www idt com 49 3 PCI Interface Peripheral Component Interconnect PCI is a bus protocol that defines how devices communicate on a peripheral bus and with a host processor If a device is referred to as PCI compliant it must be compliant with the PCI Local Bus Specification Revision 2 1 The Universe II PCI bus supports frequencies up to 33 MHz and 32 bit or 64 bit transfers This chapter describes the Universe II s PCI Interface This chapter discusses the following topics e PCI Cycles on page 49 Universe II as PCI Master on page 53 e Universe II as PCI Target on page 57 3 1 Overview The Universe II PCI Bus Interface is a directly connected to the PCI bus For information concerning the different types of PCI accesses available
127. IR Output Syscon Direction Control Transceiver control that allows the Universe II to drive VBCLR_ and SYSCLK When the Universe II is driving lines on the VMEbus this signal is driven high when the VMEbus is driving the Universe II this signal is driven low VWRITE__ Bidirectional VMEbus Write signal Indicates the direction of data transfer VXBBSY Output VMEbus Transmit Bus Busy Signal Generated by the Universe II when it is VMEbus master VXBERR Output VMEbus Transmit Bus Error Signal Generated by the Universe Il when PCI target generates Target Abort on coupled PCI access from VMEbus VXBR 3 0 Output VMEbus Transmit Bus Request The Universe ll requests the VMEbus when it needs to become VMEbus master VXIRQ 7 1 Output VMEbus Transmit Interrupts The VMEbus interrupt outputs are individually maskable VXSYSFAIL Output VMEbus System Failure Asserted by the Universe II during reset and plays a role in VME64 Auto ID VXSYSRST Output VMEbus System Reset The Universe Il output for SYSRST 10 3 PCI Bus Signals Table 27 PCI Bus Signals ACK64 Bidirectional Acknowledge 64 bit Transfer It indicates slave can perform a 64 bit transfer when driven by the PCI slave target AD 31 0 Bidirectional PCI Address Data Bus Address and data are multiplexed over these pins providing a 32 bit address and 32 bit
128. Independent of the setting of the LD64EN bit the Universe II will never attempt a 64 bit cycle on the PCI bus if it is powered up as 32 bit REQ64 must be pulled down with a 4 7kQ resistor at reset for 64 bit PCI see PCI Bus Width on page 138 There is an internal pull up on this pin which causes the Universe II to default to 32 bit PCI This power up option provides the necessary information to the Universe II so that these unused pins may be left unterminated Resets The Universe II provides several reset input and outputs which are asserted under various conditions These can be grouped into three types as shown in Table 46 Table 46 Reset Signals VMEbus Resets The VMEbus resets are connected to the VMEbus as indicated in Figure 40 on page 364 through external buffers PCI bus Resets Use of the PCI bus resets will be application dependent The RST input to the Universe II should typically be tied in some fashion to the PCI bus reset signal of the same name This will ensure that all Universe II PCI related functions are reset together with the PCI bus The LRST pin is a totem pole output which is asserted due to any of the following initiators e PWRRST_ e VRSYSRST e local software reset in the MISC CTL register or e VMECSR reset in the VCSR_SET register Integrated Device Technology Universe Il User Manual www idt com May 12 2010 370 E 3 1 3 E 3 1 4 E 3 2 E 4 E Typical Application
129. Integrated Device Technology www idt com 1 Functional Overview gt Overview 19 e Commercial industrial and extended temperature variants JEEE 1149 1 JTAG e Available packaging 35mm x 35mm 313 contact plastic BGA PBGA package 1 1 2 Universe II Benefits The Universe II offers the following benefits to designers e Industry proven device Reliable customer support with experience in hundreds of customer designs 1 1 3 Universe Il Typical Applications The Universe II is targeted at today s technology demands such as the following e Single board computers e Telecommunications equipment e Test equipment Command and control systems e Factory automation equipment Medical equipment Military e Aerospace 1 1 3 1 Typical Application Example Single Board Computers The Universe II is widely used on VME based Single Board Computers SBC that employ PCI as their local bus and VME as the backplane bus as shown in the accompanying diagram These SBC cards support a variety of applications including telecom datacom medical industrial and military equipment The Universe II high performance architecture seamlessly bridges the PCI and VME busses and is the VME industry s standard for single board computer interconnect device Integrated Device Technology Universe Il User Manual www idt com May 12 2010 20 1 2 1 Functional Overview gt Main Interfaces Figure 2 Universe Il In Single Board Computer Application
130. L This register provides the general VMEbus and PCI controls for this slave image Note that only transactions destined for PCI Memory space are decoupled the posted write RXFIFO generates on Memory space transactions on the PCI Bus This image has 4 Kbyte resolution In order for a VMEbus slave image to respond to an incoming cycle the BM bit in the PCI CSR register must be enabled The state of PWEN and PREN are ignored if LAS is not programmed memory space Register name VSI4_CTL Register offset OXF90 15 08 Reserved Image Enable PWR VME 0 Disable 1 Enable Posted Write Enable PWR VME 0 Disable 1 Enable R W PWR VME 0 Disable 1 Enable Program Data AM Code R W PWR VME 11 00 Reserved 01 Data 10 Program 11 Both Supervisor User AM Code PWR VME 00 Reserved Integrated Device Technology Universe II User Manual www idt com May 12 2010 Prefetch Read Enable 01 Non Privileged 10 Supervisor 11 Both 310 LD64EN LLRMW 12 Registers Register Description E i VMEbus Address Space 000 A16 001 A24 010 A32 011 Reserved 100 Reserved 101 Reserved 110 User1 111 User2 Enable 64 bit PCI Bus Transactions 0 Disable 1 Enable Enable PCI Bus Lock of VMEbus RMW 0 Disable 1 Enable PCI Bus Address Space 00zPCI Bus Memory Space 01 PCI Bus I O Space 10 PCI Bus Configuration Space 11 Reserved Universe Il User Manual May 12 2010 u p u aM B N Integrated Device Technology www
131. M bit in the PCI CSR register must be enabled The state of PWEN and PREN are ignored if LAS is not programmed memory space Register name VSI1_CTL Register offset OxF14 15 08 Reserved Image Enable PWR VME 0 Disable 1 Enable Posted Write Enable PWR VME 0 Disable 1 Enable R W PWR VME 0 Disable 1 Enable Program Data AM Code R W PWR VME 11 00 Reserved 01 Data 10 Program 11 Both Supervisor User AM Code PWR VME 00 Reserved Integrated Device Technology Universe II User Manual www idt com May 12 2010 Prefetch Read Enable 01 Non Privileged 10 Supervisor 11 Both 286 LD64EN LLRMW 12 Registers Register Description VMEbus Address Space 000 Reserved 001 A24 010 A32 011 Reserved 100 Reserved 101 Reserved 110 User1 111 User2 Enable 64 bit PCI Bus Transactions 0 Disable 1 Enable Enable PCI Bus Lock of VMEbus RMW 0 Disable 1 Enable PCI Bus Address Space 00zPCI Bus Memory Space 01 PCI Bus I O Space 10 PCI Bus Configuration Space 11 Reserved Universe Il User Manual May 12 2010 E i E u aM i M Integrated Device Technology www idt com 12 Registers gt Register Description 287 12 3 90 VMEbus Slave Image 1 Base Address Register VSI1_BS The base address specifies the lowest address in the address range that will be decoded Register name VSI1_BS Register offset OXF18 BS 31 16 Base Address PWR VME Lo 39 Integrated Device Technology Universe Il U
132. MEbus Slave Image 2 Translation Offset VSI2_TO Register name VSI2_TO Register offset OXF34 23 16 TO 31 16 Translation Offset PWR VME 09 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 295 12 3 97 VMEbus Slave Image 3 Control VSI3_CTL This register provides the general VMEbus and PCI controls for this slave image Note that only transactions destined for PCI Memory space are decoupled the posted write RXFIFO generates on Memory space transactions on the PCI Bus In order for a VMEbus slave image to respond to an incoming cycle the BM bit in the PCI CSR register must be enabled The state of PWEN and PREN are ignored if LAS is not programmed memory space Register name VSI3_CTL Register offset OxF3C 15 08 Reserved Image Enable PWR VME 0 Disable 1 Enable Posted Write Enable PWR VME 0 Disable 1 Enable R W PWR VME 0 Disable 1 Enable Program Data AM Code R W PWR VME 11 00 Reserved 01 Data 10 Program 11 Both Supervisor User AM Code PWR VME 00 Reserved Integrated Device Technology Universe II User Manual www idt com May 12 2010 Prefetch Read Enable 01 Non Privileged 10 Supervisor 11 Both 296 LD64EN LLRMW 12 Registers Register Description VMEbus Address Space 000 Reserved 001 A24 010 A32 011 Reserved 100 Reserved 101 Reserved 110 User1 111 User2 Enable 64 bit PCI Bus Transactions 0 Disab
133. MEbus backplanes In particular complete isolation of the Universe II from the VMEbus backplane allows use of ETL transceivers which provide high noise immunity as well as use in live insertion environments The VME community has recently standardized VME64 Extensions ANSI VITA 1 1 which among other new VME features facilitates live insertion environments If neither live insertion nor noise immunity are a concern those buffers that provide input only U15 and U17 in Figure 40 may be omitted The daisy chain input signals BGIN 3 0 and IACKIN have Schmitt trigger inputs which should rectify any minor noise on these signals If considerable noise is expected the designer may wish to put external filters on these signals Bear in mind that any filtering done on these signals will detrimentally affect the propagation of bus grants down the daisy chain Only extremely noisy systems or poorly designed backplanes should require these filters Figure 40 shows one example of how to connect the Universe II to the VMEbus The transceivers in this example were chosen to meet the following criteria e Provide sufficient drive strength as required by the VME specification e Meet Universe II skew requirements and Minimize part counts Integrated Device Technology Universe Il User Manual www idt com May 12 2010 364 E Typical Applications gt VME Interface U15 and U17 in Figure 40 are optional devices and provide better noise immunity for
134. May 12 2010 www idt com 109 7 Interrupt Generation and Handling An interrupt is a signal informing a program that an event for example an error has occurred When a program receives an interrupt signal it temporarily suspends normal processing and diverts the execution of instructions to a sub routine handled by an interrupt controller The controller communicates with the host processor and the device that initiated the interrupt to determine how to handle the interrupt Interrupt signals can come from a variety of sources Interrupt signals generated by devices for example a printer indicate an event has occurred and are called hardware interrupts Interrupt signals generated by programs are called software interrupts This chapter discussed the interrupt generation and handling functionality of the Universe II This chapter discusses the following topics e Interrupt Generation on page 111 e Interrupt Handling on page 116 7 1 Overview The Universe II has two types of interrupt capability it is a generator of interrupts and an interrupt handler The Interrupt Channel handles the prioritization and routing of interrupt sources to interrupt outputs on the PCI bus and VMEbus The interrupt sources are e PCILINT 7 0 e VMEbus IRQ 7 1 ACFAIL and SYSFAIL e Various internal events These sources can be routed to either the PCI LINT 7 0 lines or the VMEbus IRQ 7 1 lines Each interrupt source is indi
135. NER ge 6s sadam an REUNEA RE rae 141 9 4 2 JTAG support fick als deter tau ree ts nba ux Badal gigs FE peste dim war RURAL NR Pes 141 MECngcc c P P O MM 142 10 Signals and PINGU iiis iiaveaesvedewes aves erer rori veen nnna grenti es 143 10 1 OVeryIeW y cse sex Pacheeerey ee thcew pe X ERR EE CES RN USA RPM RS RARE FER ERE 143 10 2 VMEDbUS Signals cech cere Ree Oe RAS ROR E DAE Rer Each ROUTE RUE PRES RUE RR RO poe RES 144 10 3 PGLBusighals ct eecetse rre eee ale dtd done II TRUE a bya UTR RT E e go e de dn 147 ILU MM nri LC 151 10 4 4 313 pin Plastic BGA Package PBGA ssesseesseeeleeeee n 151 Tix Electrical CharactersH6S ass RR RE RA OC OGE bars e8 md Ret ir aii RR dcs bd 153 ILL DC Charaetenstics 645i osep hee r ieren a RR Dn HER QUee t Gare er TRU E EIER eee bi be ques 153 11 1 1 ONon PCI Characteristics 14e dendi e benm RR RIUREUH RE eIeOeRR eR tame ER QUNM ARP ERE 153 11 1 2 PCE Characteristics ceu REESE ISOPREpRRER OP D CHOPPER EUN ONCE as ote 154 11 1 3 Pin List and DC Characteristics for all Signals 155 11 2 Operating Conditions c oce REEL RU OD ERU PUER PIC Ia E ESTER IE pP GU aues 160 11 2 1 Absolute Maximum Ratings 0 eee eens 161 IES3 Power Dissipation eserse ninen eis po Stok anne Eana EE RP EROR RR eK oh ba dor odd dut ged a 161 ILA Power Sequencing oc des eraniedy hh bade RE RR
136. PP Register offset 0x218 eee ee eee eee DCPP DMA Command Packet Pointer R W All 31 5 Integrated Device Technology Universe II User Manual www idt com May 12 2010 238 12 Registers gt Register Description 12 3 54 DMA General Control Status Register DGCS Register name DGCS Register offset 0x220 ASN Oe I NON EIN CUM EUR URLPOURCOUNT 31 24 GO STOP HALT _ CHAIN REQ REQ VON 23 16 VOFF 15 08 STOP HALT DONE LERR VERR P ERR 07 00 INT INT INT INT INT INT STOP HALT DONE LERR VERR P ERR GO ll DMA Go Bit W Read 0 A 0 No effect always 1 Enable DMA Transfers STOP_ REQ DMA Stop Request W Read 0 O No effect always 1 Stop DMA transfer when all buffered data has been written HALT REQ DMA Halt Request W Read 0 O No effect always 1 Halt the DMA transfer at the completion of the current command packet CHAIN DMA Chaining 0 DMA Direct Mode 1 DMA Linked List mode VON 2 0 VMEbus On counter 000 Until done 001 256 bytes 010 512 bytes 011 1024 bytes 100 2048 bytes 10124096 bytes 11028192 bytes 111216384 bytes others Reserved Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 239 VOFF 3 0 VMEbus Off Counter 0000 0us 0001 16ys 0010 32us 0011 64us 0100 128us 0101 256us 0110 512us 0111 1024us 1000 2us 1001 4us 1010 8us others Reserved The DMA will not re request the VME Master until this timer expires
137. REQ_ is asserted and FRAME is asserted 4 clocks after AS From assertion of REQ_ the Universe II does not insert any extra wait states in its operations as an initiator on the PCI bus Upon receiving GNT_ asserted the Universe II asserts FRAME_ in the next clock and after the required turn around phase asserts IRDY_ to begin data transfer Once TRDY is sampled asserted the Universe II responds back to the VMEbus by asserting DTACK If the initiating VME transaction is 64 bit and the PCI bus or PCI bus target are 32 bit then two data transfers are required on PCI before the Universe II can respond with DTACK No wait states are inserted by the Universe II between these two data beats on PCI The assertion of DTACK from the assertion of TRDY has alatency of 1 clock Figure 32 shows a typical non block coupled read cycle When accessing a PCI target with a zero wait state response the Universe II VME response becomes approximately 10 PCI clock periods about 301ns in a 33MHz system during single cycles and the first beat of a BLT During pure data beats in both BLT and MBLTS the slave response becomes 8 clocks Figure 32 Coupled Read Cycle Universe Il as VME Slave VMEbus A 31 1 AS D 31 0 WRITE DSO DS1 DTACK PCI CLK AD 31 0 C BE 3 0 IRDY TRDY STOP
138. RR_ and take appropriate action Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 3 PCI Interface gt Universe II as PCI Target 57 3 4 Universe Il as PCI Target The Universe II becomes PCI bus target when one of its nine programmed PCI target images or one of its registers is accessed by a PCI bus master The Universe II cannot access its own images or registers and master the PCI bus Refer to Registers on page 163 for more information on register accesses When one of its PCI target images is accessed the Universe II responds with DEVSEL_ within two clocks of FRAME This makes the Universe II a medium speed device as reflected by the DEVSEL field in the PCI CS register 3 4 1 Command Types As PCI target the Universe II responds to the following command types e I O Read e O Write e Memory Read e Memory Write e Configuration Read Type 0 e Configuration Write Type 0 Memory Read Multiple aliased to Memory Read e Memory Line Read aliased to Memory Read e Memory Write and Invalidate aliased to Memory Write Type 0 Configuration accesses can only be made to the Universe II s PCI configuration registers The PCI target images do not accept Type 0 accesses Address parity errors are reported if both PERESP and SERR EN are set in the PCI Configuration Space Control and Status Register PCI CSR on page 172 Address parity errors are reported by the Universe II by asserting the
139. Register MAST CTL on page 271 to ensure that the Universe II has access to the locked VMEbus resource for an indeterminate period The Universe II can be programmed to assert an interrupt on the PCI bus when it acquires the VMEbus and the VOWN bit is set in the PCI Interrupt Enable Register LINT EN on page 242 While the VMEbus is held using the VOWN bit the Universe II sets the VOWN ACK bit in the MAST_CTL register The act of changing the VOWN_ACK bit from 0 to 1 generates and interrupt The VMEbus Master Interface maintains bus tenure while the ownership bit is set and only releases the VMEbus when the ownership bit is cleared Reasons for Using the VOWN Bit If the VMEbus Master Interface is programmed for RWD through the VREL bit in Master Control Register MAST_CTL on page 271 it may release the VMEbus when the PCI Target Channel has completed a transaction If exclusive access to the VMEbus resource is required for multiple transactions then the VMEbus ownership bit holds the bus until the exclusive access is no longer required Alternatively if the VMEbus Master Interface is programmed for ROR the VMEbus ownership bit ensures VMEbus tenure even if other VMEbus requesters require the VMEbus Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 3 PCI Interface gt Universe II as PCI Target 65 3 4 7 Terminations The Universe II performs the following terminations as PCI target 1
140. S The base address specifies the lowest address in the address range that is decoded This image has 4 Kbyte resolution Register name VSIO BS Register offset OXF04 BS 31 12 Base Address PWR VME 09 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 283 12 3 87 VMEbus Slave Image 0 Bound Address Register VSIO_BD The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register This image has 4 Kbyte resolution Register name VSIO BD Register offset OXF08 BD 31 12 Bound Address PWR VME EE Integrated Device Technology Universe Il User Manual www idt com May 12 2010 284 12 Registers gt Register Description 12 3 88 VMEbus Slave Image 0 Translation Offset VSIO TO This image has 4 Kbyte resolution Register name VSIO TO Register offset OxFOC TO 31 12 Translation Offset PWR VME ow Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 285 12 3 89 VMEbus Slave Image 1 Control VSI1_CTL This register provides the general VMEbus and PCI controls for this slave image Note that only transactions destined for PCI Memory space are decoupled the posted write RXFIFO generates on Memory space transactions on the PCI Bus In order for a VMEbus slave image to respond to an incoming cycle the B
141. S REVENUS Re TIERS grey RE s 53 33 Umversell asPCLMaster ue Ren cp RE pEi SE REA RR RR ARE ede dE RA EE ERE E 53 3 3 1 Command Types vez xatd DORIA RE EORR eR amas RC RUAUE TR UR ERA CIR RARIOR RC da 54 3 3 2 PCI Burst Iransfets sedes p Rer EE mee biel ded SUR A RURSUM inate So RR RE ep Eee dd 55 3 3 3 Termination MR c 55 3 3 4 lop 56 34 Universe IL as PCI Target severe FEDERER RE HU UE ERU pa CE No Cha E ee pig s Reus ea 57 3 4 1 Command Types re egies Late Cee ae ee Rhee Huck Ce Ru ERU RUE URS dod e pa isso ays 57 3 4 2 Data Transe oer m recte eere REFERAT Ud teehee int drei toss Em Ue ele UR Fus dod 57 3 4 3 Coupled Tramsters EM 58 3 4 4 Posted Writes P UE 60 3 4 5 Special Cycle Generato searr ianrey eb REOR ER Foes ck eR nih a nee ERR era Ce SR recie d 61 3 4 6 Using the VOWN bit eb bee d a Qe IRRORUC ERST P eae ass 64 3 4 7 Terminations 2259s pa ue RES BPO ST iun dbncedi e Debt er eie 65 4 Slave Image Programming 00 cee cece eee eee 67 4 1 OVEIVIEW a 5 5 Sted bo theca thas E Gee pe SEN Ce Rea ae eee CE mae Seba e dees 67 42 VME Slave Image Programming os choc nt Enka Gos CAE Eee E ROSAS SHOE Ee REESE AS PE SS 67 4 2 1 XVMEBEb s Fields inodo bert aoe a na a se Gna a AS Red rack nae ee Maney aie arse ur n 68 4 2 2 PCT Bus Exelds i eeu yee bs EA E E aaa amp Had MAME RN FE Gace eA SEM EE ERR 69 4 2 3 Control Fields
142. See DMA VMEbus Ownership on page 91 The DMA Channel unpacks the 64 bit data queued in the DMAFIFO to whatever the programmed transfer width is on the VMEbus D16 D32 or D64 The VMEbus Master Interface delivers the data in the DMAFIFO according to the VMEbus cycle type programmed into the DMA Transfer Control Register DCTL on page 232 The DMA provides data to the VMEbus until one of the following conditions are met e DMA FIFO empties e DMA VMEbus Tenure Byte Count expires Set in the VON in the DMA General Control Status Register DGCS on page 238 If the DMAFIFO empties transfers on the VMEbus stop and if the cycle being generated is a block transfer then the block is terminated AS negated The VMEbus ownership is relinquished by the DMA The DMA does not re request VMEbus ownership until another eight entries are queued in the DMAFIFO or the DMA Channel has completed the current Transfer Block on the PCI bus see VMEbus Release on page 27 PCI bus transactions are the full width of the PCI data bus with appropriate byte lanes enabled The maximum VMEbus data width is programmable to 8 16 32 or 64 bit Byte transfers can be only of type DO8 EO Because the PCI bus has a more flexible byte lane enabling scheme than the VMEbus the Universe II can be required to generate a variety of VMEbus transaction types to handle the byte resolution of the starting and ending addresses see Data Transfer on page
143. TATUS ID was acquired without bus error 1 bus error occurred during acquisition of the STATUS ID STATID 7 0 STATUS ID acquired during IACK cycle for level 7 VMEbus el Tes interrupt The Universe II is enabled as the interrupt handler for a given interrupt level via the VIRQx bits of the LINT EN register Once a vector for a given level is acquired the Universe II does not perform a subsequent interrupt acknowledge cycle at that level until the corresponding VIRQx bit in the LINT STAT register is cleared The acquisition of a level x STATUS ID by the Universe II updates the STATUS ID field of the corresponding Vx STATID register and generation of a PCI interrupt A VMEbus error during the acquisition of the STATUS ID vector sets the ERR bit which means the STATUS ID field may not contain a valid vector Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 263 12 3 72 PCI Interrupt Map 2 Register LINT_MAP2 This register maps interrupt sources to one of the eight PCI interrupt pins For example a value of 000 maps the corresponding interrupt source to LINT_ 0 Register name LINT_MAP2 Register offset 0x340 EGNENXESXESESSES 31 24 LM3 LM2 Description LM 2 0 Location Monitor 3 Interrupt destination LM2 2 0 Location Monitor 2 Interrupt destination LM1 2 0 Location Monitor 1 Interrupt destination LMO 2 0 Location Monitor 0 Interrupt destination MBOX3
144. Ta Ambient temperature C Tj Maximum Universe II Junction Temperature C Oja Ambient to Junction Thermal Impedance C Watt P Universe II power consumption Watts The ambient to junction thermal impedance Oja is dependent on the air flow in linear feet per minute over the Universe II The values for Oja over different values of air flow are shown in Table 39 Table 39 Ambient to Junction Thermal Impedance Air Flow m s 313 PBGA For example the maximum ambient temperature of the 313 PBGA 32 bit PCI environment with 100 LFPM blowing past the Universe II is Ta lt Tj Oja P Ta 125 13 1 2 0 Ta lt 98 8 C Therefore the maximum rated ambient temperature for the Universe II in this environment is 98 8 C Further improvements can be made by adding heat sinks to the PBGA package Tj values of Universe II are calculated as follows Tj 0ja P Ta Table 40 Maximum Universe II Junction Temperature Extended 125 C Ambient Industrial 85 C Ambient Commercial 70 C Ambient Tj 13 1 2 7 125 160 37 C Tj 13 1 2 7 85 120 37 C Tj 13 1 2 7 70 105 37 C a IDT recommends that the maximum junction temperature of the Universe Il does not exceed 150 C This temperature limit can be achieved by using heat dissipation techniques such as heat sinks and forced airflows Integrated Device Technology Universe Il User Manual www idt com May 12 2010 358 C 5 C Reliability Prediction
145. The DMA is stopped INT STOP e The DMA is halted INT HALT The DMA is done INT DONE e PCI Target Abort or Master Abort INT LERR e VMEbus errors INT VERR e A PCI protocol error or if the Universe II is not enabled as PCI master INT P ERR All of these interrupt sources are ORed to a single DMA interrupt output line When an interrupt comes from the DMA module software must read the DMA status bits in the PCI Interrupt Status Register LINT STAT on page 244 and the VMEbus Interrupt Status Register VINT STAT on page 251 to discover the originating interrupt source The DMA interrupt can be mapped to either the VMEbus or one of the PCI interrupt output lines see DMA Interrupts on page 104 Mailbox Register Access Interrupts The Universe II can be programmed to generate an interrupt on the PCI bus and or the VMEbus when any one of its mailbox registers is written to see Mailbox Registers on page 83 The user may enable or disable an interrupt response to the access of any mailbox register Each register access may be individually mapped to a specific interrupt on the PCI bus through the PCI Interrupt Map 2 Register LINT MAP2 on page 263 and or the VMEbus through the VME Interrupt Map 2 Register VINT MAP2 on page 264 The status of the PCI interrupt and the VMEbus are recorded in the PCI Interrupt Status Register LINT STAT on page 244 and VMEbus Interrupt Status Register VINT STAT on page 25
146. Universe Il as VMEbus Slave 33 2 4 2 2 4 2 1 A coupled cycle with multiple data beats such as block transfers on the VMEbus side is always mapped to single data beat transactions on the PCI bus where each data beat on the VMEbus is mapped to a single data beat transaction on the PCI bus regardless of data beat size No packing or unpacking is performed The only exception to this is when a D64 VMEbus transaction is mapped to D32 on the PCI bus The data width of the PCI bus depends on the programming of the VMEbus slave image 32 bit or 64 bit see VME Slave Image Programming on page 67 The Universe II enables the appropriate byte lanes on the PCI bus as required by the VMEbus transaction For example a VMEbus slave image programmed to generate 32 bit transactions on the PCI bus is accessed by a VMEbus D08 BLT read transaction prefetching is not enabled in this slave image The transaction is mapped to single data beat 32 bit transfers on the PCI bus with only one byte lane enabled Target Retry from a PCI target is not communicated to the VMEbus master PCI transactions terminated with Target Abort or Master Abort are terminated on the VMEbus with BERR The Universe II sets the R_TA or R MA bits in the PCI Configuration Space Control and Status Register PCI CSR on page 172 when it receives a Target Abort or Master Abort Posted Writes A posted write involves the VMEbus master writing data into the Universe II s RXFIFO inste
147. User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 217 12 3 37 PCI Target Image 5 Control Register LSI5 CTL In the PCI Target Image Control register setting the VCT bit will only have effect if the VAS bits are programmed for A24 or A32 space and the VDW bits are programmed for 8 bit 16 bit or 32 bit If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64 bit the Universe II may perform MBLT transfers independent of the state of the VCT bit The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I O Space forcing all transactions through this image to be coupled Register name LSI5_CTL Register offset 0x1B4 23 16 Reserved EN 0 Disabl 1 Enable Posted Write Enable 0 Disable 1 Enable VMEbus Maximum Datawidth 00 8 bit data width 01 16 bit data width 10 32 bit data width 11 64 bit data width 011 Reserved 100 Reserved 101 CR CSR 110 User1 111 User2 VMEbus Address Space 000 A16 001 A24 010 A32 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 218 12 Registers gt Register Description Program Data AM Code 0 Data 1 Program SUPER Supervisor User AM Code 0 Non Privileged 1 Supervisor VMEbus Cycle Type O no BLTs on VMEbus 1 BLTs on VMEbus PCI Bus Memory Space 0 PCI Bus Memory Space 1 PCI Bus I O Space Universe Il User Manual Integrated D
148. Using Active Circuitry Universe II External Register Auto Syscon and PCI Bus Width Power up Options The VME64 specification provides for automatic enabling of the system controller in a VME system through monitoring of the BGIN3 signal If at the end of SYSRST this pin is low then the system controller is enabled otherwise it is disabled The Universe II provides an internal pull down resistor for this function If it is in slot one this pin will be sampled low If not in slot one then it will be driven high by the previous board in the system and system controller functions will be disabled No external logic is required to implement this feature PCI Bus Interface The Universe II provides a fully standard PCI bus interface compliant for both 32 bit and 64 bit designs No external transceivers or glue logic is required in interfacing the Universe II to any other PCI compliant devices All signals may be routed directly to those devices Universe Il User Manual Integrated Device Technology May 12 2010 www idt com E Typical Applications gt PCI Bus Interface 369 E 3 1 E 3 1 1 E 3 1 2 The Universe II s PCI interface can be used as a 32 bit bus or 64 bit bus If used as a 32 bit interface the 64 bit pins AD 32 63 and ACK64_ are left unterminated On a 32 bit PCI bus the Universe II drives all its 64 bit extension bi direct signals C BE 7 4 _ AD 63 32 REQ64_ PAR64 and ACK64_ at all times to unknown values
149. VMEbus JACK cycle performed in response to a software interrupt Each source can be individually enabled in the PCI Interrupt Enable Register LINT_EN on page 242 and mapped to a single LINT_ signal through the PCI Interrupt Map 0 Register LINT MAPO on page 246 PCI Interrupt Map 1 Register LINT_MAP1 on page 247 and PCI Interrupt Map 2 Register LINT MAP2 on page 263 When an interrupt is received on any of the enabled sources the Universe II asserts the appropriate LINT pin and sets a matching bit in the PCI Interrupt Status Register LINT STAT on page 244 See Table 17 on page 114 for a list of the enable mapping and status bits for PCI interrupt sources Integrated Device Technology Universe Il User Manual www idt com May 12 2010 112 7 Interrupt Generation and Handling gt Interrupt Generation Table 16 Source Enabling Mapping and Status of PCI Interrupt Output Enable Bitin LINT EN Mapping Field in Status Bit in Interrupt Source Register LINT MAPx Register LINT STAT Register ACFAIL ACFAIL ACFAIL ACFAIL SYSFAIL SYSFAIL SYSFAIL SYSFAIL PCI Software SW INT SW INT SW INT Interrupt VMEbus Software SW IACK SW IACK SW IACK IACK VMEbus Error VERR VERR VERR occurred during a posted write PCI Target Abort or LERR LERR LERR Master Abort occurred during a posted write A VMEbus Interrupt VIRQ7 1 Input Location Monitor LM3 0 Mailbox Access MBOX3 0 MBOX3 0 VMEbus Ownership VOWN The PCI Int
150. When VA 1 is sampled high at power up the PCI BSO register s SPACE register s bit is set to 0 which signifies Memory space and the PCI BS1 register s SPACE bit is set to 1 which signifies I O space A write must occur to this register before the Universe II Device Specific Registers can be accessed This write can be performed with a PCI configuration transaction or a VMEbus register access The SPACE bit in this register is an inversion of the SPACE field in PCI BSO Integrated Device Technology Universe Il User Manual www idt com May 12 2010 180 12 Registers gt Register Description 12 3 7 PCI Configuration Miscellaneous 1 Register PCI MISC1 Register name PCI MISC1 Register offset OX3C 31 24 24 MAX_LAT 7 0 ee MIN_GNT 7 0 15 08 INT_PIN 7 0 07 00 00 INT LINE 7 0 Reset Description Type Reset by value pe 24 MAX LAT nnd 0 Maximum Boop ee This device has no special 0x00 nnd ee requirements haa 16 MIN_GNT 7 0 Minimum Grant 250 ns increments The MIN_GNT parameter assumes the Universe II master is transferring an aligned burst size of 64 bytes to a 32 bit target with no wait states This would require roughly 20 clocks at a clock frequency of 33 MHz this is about 600 ns MIN_GNT is set to three or 750 ns 15 08 INT_PIN 7 0 Interrupt Pin Universe Il pin INT 0 has a PCI compliant I O buffer 07 00 INT_LINE 7 0 Interrupt Line Used by some PCI systems to record interrupt rou
151. _ pins to signal a process that the interrupt started through software has been completed All VMEbus interrupts generated by the Universe II are RORA except for the software interrupts which are ROAK This means that if the interrupt source was a software interrupt then the VMEbus interrupt output is automatically negated when the Universe II receives the IACK cycle However for any other interrupt the VMEbus interrupt output remains asserted until cleared by a register access Writing to the relevant bit in the VINT_STAT register clears that interrupt source However since PCI interrupts are level sensitive if an attempt is made to clear the VMEbus interrupt while the LINT_ pin is still asserted the VMEbus interrupt remains asserted For this reason a VMEbus interrupt handler should clear the source of the PCI interrupt before clearing the VMEbus interrupt Since software interrupts are ROAK the respective bits in the VINT_STAT register are cleared automatically on completion of the IACK cycle simultaneously with the negation of the IRQ Integrated Device Technology Universe II User Manual www idt com May 12 2010 116 7 3 7 3 1 7 3 2 7 Interrupt Generation and Handling gt Interrupt Handling Interrupt Handling The Universe II can handle interrupts from both the PCI bus and the VMEbus PCI Interrupt Handling All eight PCI interrupt lines LINT 7 0 can act as interrupt inputs to the Universe II They are l
152. a eoe e ERROR srs arsine e ETE S eT e e Rech ee eae 161 lable34 Universe M Register Map recette ea E eie ace LEUR EO RO c e Rete ees 164 Table 35 Power up Option Behavior of the VAS field in VRAICTL 0 0 0 cee en 304 Table 36 PCLSlave Channel Performance Ried geese eed epRO X DC eae Hote oa aware ated ER 352 Table 37 VME Slave Channel Performance socle occ RR Obed AEERO Ga TES Coa E ER RERO we eee Ee 352 Table 387 DMA Channel Performance vdd nr eO DH RRRRR EET ESTUDIO EP pU Oe e Rd aee wee 353 Table 39 Ambient to Junction Thermal Impedance lssseseeeeeeeeeeee e 357 Table 40 Maximum Universe II Junction Temperature lsesseeeeeeeeeeee e 357 Table 41 Thermal Characteristics of Universe II 0 Re 358 Table 42 Mapping of 32 bit Little Endian PCI Bus to 32 bit VMEbus ssseeesseeeeee cee eee 360 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 12 Tables Table 43 Mapping of 32 bit Little Endian PCI Bus to 64 bit VMEbus 00 0002 cee eee eee eee 361 Table 44 VMEbus Signal Drive Strength Requirements 00 ne 366 Table 45 VMEbus Transceiver Requirements 0 0 0 ec cee eee eee eee 366 Tabler46 Reset Signals 5 eeu erre eee ce er n e eee e Rue a a ates een RH ce COBRAR See 369 Table 47 Standard Ordering Information llslseeeeeeeeeeeeee e eens 373 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 13
153. a is then delivered to the VMEbus The first data phase provided to the VMEbus master is essentially a coupled read but subsequent data phases in the VMEbus block read are delivered from the RDFIFO and are decoupled see Prefetched Reads on page 127 for the impact on bus error handling The RXFIFO is the same structure as the RDFIFO The different names are used for the FIFO s two roles In each FIFO only one role either the RXFIFO or the RDFIFO can used at one time FIFO Entries When there is a transactions from the Universe PCI Slave to the Universe VME Master the data width of the transaction on the PCI bus 32 bit or 64 bit depends on the setting of the LD64EN bit in the VMEbus Slave Image 1 Control VSI1_CTL on page 285 and the capabilities of the accessed PCI target Internally the prefetched read data is packed to 64 bit regardless of the width of the PCI bus or the data width of the original VMEbus block read no address information is stored with the data Once one entry is queued in the RDFIFO the VMEbus Slave Interface delivers the data to the VMEbus unpacking the data as necessary to fit with the data width of the original VMEbus block read D16 or D32 The VMEbus Slave Interface continuously delivers data from the RDFIFO to the VMEbus master performing the block read transaction Because PCI bus data transfer rates exceed those of the VMEbus it is unlikely that the RDFIFO will be unable to deliver data to the
154. abilities PCI and VMEbus protocols have different data transfer capabilities The maximum data width for a VMEbus data transfer is programmed with the VMEbus Maximum Datawidth VDW field in the PCI Target Image 0 Control LSIO CTL on page 181 For example consider a 32 bit PCI transaction accessing a PCI target image with VDW set to 16 bits A data beat with all byte lanes enabled will be broken into two 16 bit cycles on the VMEbus If the PCI target image is also programmed with block transfers enabled the 32 bit PCI data beat will result in a D16 block transfer on the VMEbus Write data is unpacked to the VMEbus and read data is packed to the PCI bus data width If the data width of the PCI data beat is the same as the maximum data width of the PCI target image then the Universe II maps the data beat to an equivalent VMEbus cycle For example consider a 32 bit PCI transaction accessing a PCI target image with VDW set to 32 bits A data beat with all byte lanes enabled is translated to a single 32 bit cycle on the VMEbus As the general rule if the PCI bus data width is less than the VMEbus data width then there is no packing or unpacking between the two buses The only exception to this is during 32 bit PCI multi data beat transactions to a PCI target image programmed with maximum VMEbus data width of 64 bits In this case packing unpacking occurs to make maximum use of the full bandwidth on both buses Only aligned VMEbus transactions ar
155. ace 10 PCI Bus Configuration Space 11 Reserved Universe Il User Manual May 12 2010 E i MI u MI i B Integrated Device Technology www idt com 12 Registers gt Register Description 321 12 3 118 VMEbus Slave Image 6 Base Address Register VSI6_ BS The base address specifies the lowest address in the address range that is decoded Register name VSI6_BS Register offset OXFBC BS 31 16 Base Address PWR VME a Integrated Device Technology Universe II User Manual www idt com May 12 2010 322 12 Registers gt Register Description 12 3 119 VMEbus Slave Image 6 Bound Address Register VSI6_ BD The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register If the bound register is 0 then the addresses decoded are those greater than or equal to the base address Register name VSI6_BD Register offset OxFCO 23 16 BD 31 16 Bound Address PWR VME Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 323 12 3 120 VMEbus Slave Image 6 Translation Offset VSI6_TO The translation offset is added to the source address that is decoded and this new address becomes the destination address If a negative offset is desired the offset must be expressed as a two s complement Register name VSI6_TO Register offset OxFC4 TO 31 16 Translation Offset PWR VM
156. ad data into the DMAFIFO to the full 64 bit width of the FIFO independent of the width of the PCI bus or the data width of the ensuing VMEbus transaction The PCI read transactions continue until either the DMA has completed the full programmed transfer or there is insufficient room available in the DMAFIFO for a full transaction The available space required for another burst read transaction is again 128 bytes Since the VMEbus is typically much slower than the PCI bus the DMAFIFO can fill frequently during PCI to VMEbus transfers though the depth of the FIFO helps to minimize this situation When the DMAFIFO fills the PCI bus is free for other transactions for example between other devices on the bus or possibly for use by the Universe Is VMEbus Slave Channel The DMA only resumes read transactions on the PCI bus when the DMAFIFO has space for another aligned burst size transaction The DMA can prefetch extra read data from the external PCI target This means that the N DMA must only be used with memory on the PCI bus which has no adverse side effects when prefetched The Universe II prefetches up to the aligned address boundary defined in the PABS field of the MASC CTL register On the VMEbus the actual programmed number of bytes in the DMA Transfer Byte Count Register DTBC on page 234 are written Prefetching can be avoided by programming the DMA for transfers that terminate at the PABS boundary If further data is required bey
157. ad of directly to the PCI address Write transactions from the VMEbus are processed as posted if the PWEN bit is set in the VMEbus slave image control register see VME Slave Image Programming on page 67 If the bit is cleared default setting the transaction bypasses the FIFO and is performed as a coupled transfer Incoming posted writes from the VMEbus are queued in the 64 entry deep RXFIFO Each entry in the RXFIFO can contain 32 address bits or 64 data bits Each incoming VMEbus address phase whether it is 16 bit 24 bit or 32 bit constitutes a single entry in the RXFIFO and is followed by subsequent data entries The address entry contains the translated PCI address space and command information mapping relevant to the particular VMEbus slave image that has been accessed see VME Slave Image Programming on page 67 For this reason any reprogramming of VMEbus slave image attributes are only reflected in RXFIFO entries queued after the reprogramming Transactions queued before the re programming are delivered to the PCI bus with the VMEbus slave image attributes that were in use before the reprogramming The RXFIFO is the same structure as the RDFIFO The different names are used for the FIFO s two roles In each FIFO only one role either the RXFIFO or the RDFIFO can used at one time FIFO Entries Incoming non block write transactions from the VMEbus require two entries in the RXFIFO one address entry with accompanying co
158. ad only from the PCI bus This eliminates the need to implement locking The Universe II provides semaphores which can be also be used to synchronize access to the mailboxes Semaphores are described in the next section 5 5 Semaphores The Universe II has two general purpose semaphore registers each containing four semaphores Semaphore 0 Register SEMAO on page 269 and Semaphore 1 Register SEMA1 on page 270 To gain ownership of a semaphore a process writes a logic 1 to the semaphore bit and a unique pattern to the associated tag field If a subsequent read of the tag field returns the same pattern the process can consider itself the owner of the semaphore A process writes a value of 0 to the semaphore to release it When a semaphore bit is a value of 1 the associated tag field cannot be updated Only when a semaphore is a value of 0 can the associated tag field be updated These semaphores shares resources in the system While the Universe II provides the semaphores it is up to the user to determine access to which part of the system will be controlled by semaphores and to design the system to enforce these rules Integrated Device Technology Universe Il User Manual www idt com May 12 2010 84 5 Registers Overview gt Semaphores An example of a use of the semaphore involves gating access to the Special Cycle Generator Special Cycle Generator on page 61 It may be necessary to ensure that while one process uses
159. addition of address bits 31 16 on the PCI Bus and bits 31 16 of the image s translation offset Register name LSI2_TO Register offset 0x134 Ee ee ee SES ESSE ee Reset Description Type Reset by value 31 16 TO 31 16 Translation Offset Integrated Device Technology Universe II User Manual www idt com May 12 2010 196 12 Registers gt Register Description 12 3 20 PCI Target Image 3 Control LSI3_CTL In the PCI Target Image Control register setting the VCT bit will only have effect if the VAS bits are programmed for A24 or A32 space and the VDW bits are programmed for 8 bit 16 bit or 32 bit If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64 bit the Universe II may perform MBLT transfers independent of the state of the VCT bit The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I O Space forcing all transactions through this image to be coupled Register name LSI3_CTL Register offset 0x13C Sea REN EXERTION ERE PELEAS CON penpmee qe eme erm c eee cc qexemy Reserved ous Reset Description Type Reset by value Image Enable R W All Undefined 0 Disable 1 Enable Posted Write Enable R W All 0x00 0 Disable 1 Enable 23 22 VMEbus Maximum Data width R W All 10 00 8 bit data width 01 16 bit data width 10 32 bit data width 11 64 bit data width Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Reg
160. address match and if the command matches certain criteria All of the Universe II s eight PCI target images are A32 capable only The first and fifth of them PCI target images 0 and 4 have a 4 Kbyte resolution while PCI target images to 3 and 5 to 7 have 64 Kbyte resolution Typically image 0 or image 4 would be used for an A16 image since they have the finest granularity The address space of a VMEbus slave image must not overlap with the address space for the Universe II s registers 4 3 2 VMEbus Fields The VMEbus fields map PCI transactions to a VMEbus transaction causing the Universe II to generate the appropriate VMEbus address AM code and cycle type Some invalid combinations exist within the PCI target image definition fields For example A16 and CR CSR spaces do not support block transfers and A16 space does not support 64 bit transactions Note that the Universe II does not attempt to detect or prevent these invalid programmed combinations and that use of these combinations may cause illegal activity on the VMEbus The 21 bit translation offset allows the user to translate the PCI address to a different address on the VMEbus Figure 9 illustrates the translation process Integrated Device Technology Universe Il User Manual www idt com May 12 2010 72 4 Slave Image Programming gt PCI Bus Target Images Figure 9 Address Translation Mechanism for PCI Bus to VMEbus Transfers A32 Image Offset 31 12 PCI 3
161. affected by this bit 0 Disable 1 Enable Note The Universe II only refuses PCI addresses with parity errors when both the PERESP and SERR_EN bits are programmed to a value of 1 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 174 12 Registers gt Register Description Description VGA Palette Snoop The Universe II treats palette accesses like all other accesses 0 Disable Memory Write and Invalidate Enable The Universe Il PCI master interface never generates a Memory Write and Invalidate command 0 Disable Special Cycles 0 Disable The Universe Il PCI target interface never responds to special cycles Master Enable 0 Disable 1 Enable For a VMEbus slave image to respond to an incoming cycle this bit must be set If this bit is cleared while there is data in the VMEbus Slave Posted Write FIFO the data will be written to the PCI bus but no further data will be accepted into this FIFO until the R W bit is set W Target Memory Enable R 0 Disable 1 Enable Integrated Device Technology www idt com Universe Il User Manual May 12 2010 This bit is 1 after reset if the VMEbus Address 14 equals 1 during power on reset This bit is reloaded by all This bit is 1 after reset if the VMEbus Address 13 12 equals 10 during power on reset This bit is reloaded by all 12 Registers gt Register Description 175 Reset Description Type Res
162. age 271 see VMEbus Requester on page 25 This interface is shared between several channels in the Universe II the PCI Target Channel the DMA Channel and the Interrupt Channel The Interrupt Channel has the highest priority over all other channels and if an interrupt is pending assumes ownership of the VMEbus Master Interface when the previous owner has relinquished ownership The Universe II latches the first interrupt that appears on the VMEbus and begins to process it immediately If an interrupt at a higher priority is asserted on the VMEbus before BBSY is asserted the Universe II performs an interrupt acknowledge for the first interrupt it detected Upon completion of that IACK cycle the Universe II then performs IACK cycles for the higher of any remaining active interrupts There may be some latency between reception of a VMEbus interrupt and generation of the IACK cycle This arises because of the latency involved in the Interrupt Channel gaining control of the VMEbus Master Interface and because of possible latency in gaining ownership of the VMEbus if the VMEbus Master Interface is programmed for release when done In addition the Universe II only generates an interrupt on the PCI bus once the IACK cycle has completed on the VMEbus Because of these combined latencies time to acquire VMEbus and time to run the IACK cycle systems should be designed to accommodate a certain worst case latency from VMEbus interrupt generation to it
163. al programming option set through the VMEbus Request Mode VRM bits in the Master Control Register MAST_CTL on page 271 In Fair mode the Universe II does not request the VMEbus until there are no other VMEbus requests pending at its programmed level This mode ensures that every requester on an equal level has access to the bus Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 2 VMEbus Interface gt VMEbus Requester 27 2 2 3 2 2 3 1 In the default setting of Demand mode the requester asserts its bus request regardless of the state of the BRn line By requesting the bus frequently requesters far down the daisy chain may be prevented from ever obtaining bus ownership This is referred to as starving those requesters Note that in order to achieve fairness all bus requesters in a VMEbus system must be set to fair mode VMEbus Release The Universe II VMEbus requester can be configured as either RWD release when done or ROR release on request using the VREL bit in the Master Control Register MAST CTL on page 271 The default setting is for RWD ROR means the Universe II releases BBSY only if a bus request is pending from another VMEbus master and once the channel that is the current owner of the VMEbus Master Interface is done Ownership of the bus can be assumed by another channel without re arbitration on the bus if there are no pending requests on any level on the VMEbus When set fo
164. ame level as current interrupt or Universe II is not generating an interrupt then the Universe Il propagates VIACKO VIACKO Output VMEbus Interrupt Acknowledge Out Generated by the Universe II if it receives VIACKI_ and is not currently generating an interrupt at the level being acknowledged VLWORD_ Bidirectional VMEbus Longword Data Transfer Size Indicator This signal is used in conjunction with the two data strobes VDS 1 0 _ and VA 01 to indicate the number of bytes 1 4 in the current transfer During MBLT transfers VLWORD_ serves as data bit D32 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 146 10 Signals and Pinout gt VMEbus Signals Table 26 VMEbus Signals Continued VOE_ Output VMEbus Transceiver Output Enable Used to control transceivers to isolate the Universe II from the VMEbus during a reset or Bl mode On power up VOE_ is high to disable the buffers VOE_ is negated during some VMEbus Slave Channel read operations VRACFAIL_ Input VMEbus ACFAIL Input signal Warns the VMEbus system of imminent power failure This gives the modules in the system time to shut down in an orderly fashion before power down ACFAIL is mapped to a PCI interrupt VRBBSY_ Input VMEbus Receive Bus Busy Allows the Universe II to monitor whether the VMEbus is owned by another VMEbus master VRBERR_ Input VMEbus Receive
165. andling on page 105 6 1 Overview The Universe II has a DMA controller for high performance data transfer between the PCI bus and VMEbus It is operated through a series of registers that control the source and destination for the data length of the transfer and the transfer protocol to be used There are two modes of operation for the DMA Direct Mode and Linked List Mode In direct mode the DMA registers are programmed directly by the external PCI master In linked list mode the registers are loaded from PCI memory by the Universe II and the transfer described by these registers is executed A block of DMA registers stored in PCI memory is called a command packet A command packet can be linked to another command packet so that when the DMA has completed the operations described by one command packet it automatically moves on to the next command packed in the linked list of command packets 6 2 DMA Registers The DMA registers reside in a register block starting at offset 0x200 The registers describe the following information for a single DMA transfer e Source where to transfer data from e Destination where to transfer data to Size how much data to transfer e Attributes the transfer attributes to use on the PCI bus and VMEbus Integrated Device Technology Universe Il User Manual www idt com May 12 2010 86 6 2 1 6 DMA Controller gt DMA Registers A final register contains status and control information for the
166. annel requires two available RXFIFO entries before it can acknowledge the first data phase of a BLT or MBLT transfer one entry for the address phase and one for the first data phase If the RXFIFO has no available space for subsequent data phases in the block transfer then the VMEbus Slave Interface delays assertion of DTACK until a single entry is available for the next data phase in the block transfer The PCI Master Interface uses transactions queued in the RXFIFO to generate transactions on the PCI bus No address phase deletion is performed so the length of a transaction on the PCI bus corresponds to the length of the queued VMEbus transaction Non block transfers are generated on the PCI bus as single data beat transactions Block transfers are generated as one or more burst transactions where the length of the burst transaction is programmed by the PABS field in the Master Control Register MAST CTL on page 271 The Universe II always packs or unpacks data from the VMEbus transaction to the PCI bus data width programmed into the VMEbus slave image with all PCI bus byte lanes enabled The data width for a VMEbus transaction to the PCI bus is programmed in the LD64EN bit in the VMEbus Slave Image 1 Control VSI1_CTL on page 285 The LD64EN bit enables 64 bit PCI bus transactions For example consider a VMEbus slave image programmed for posted writes and a D32 PCI bus that is accessed with a VMEbus D16 block write transaction VMEbu
167. ans that during reads from the PCI bus the Universe II will wait for 128 bytes to be free in the DMAFIFO before requesting the PCI bus For PCI writes the Universe II waits for 128 bytes of data to be in the FIFO before requesting the PCI bus The DMAFIFO VMEbus watermark is 64 bytes This means that during reads from the VMEbus the Universe II will wait for 64 bytes to be free in the DMAFIFO before requesting the Vmebus For VMEbus writes the Universe II waits for 64 bytes of data to be in the FIFO before requesting the VMEbus These watermarks have been tailored for the relative speeds of each bus and provide near optimal use of the DMA channel B 4 1 VMEbus Ownership Modes The DMA has two counters that control its access to the VMEbus the VON VMEbus On counter and the VOFF VMEbus Off timer The VON counter controls the number of bytes that are transferred by the DMA during any VMEbus tenure while the VOFF timer controls the period before the next request after a VON time out While the bus is more optimally shared between various masters in the system and average latency drops as the value programmed for the VON counter drops the sustained performance of the DMA also drops The DMA is typically limited by its performance on the VMEbus As this drops off with greater re arbitration cycles the average VMEbus throughput will drop Even if the Universe II is programmed for ROR mode and no other channels or masters are requesting the bus
168. as there are 128 bytes available in the DMAFIFO If the PCI bus responds too slowly the DMAFIFO runs the risk of filling before write transactions can begin at the PCI Master Interface Once the DMAFIFO reaches a nearly full state three entries remaining the DMA requests that the VMEbus Master Interface complete its pending operations and stop The pending read operations fill the DMAFIFO Once the pending VMEbus reads are completed or the VON timer expires the DMA relinquishes VMEbus ownership and only re requests the VMEbus Master Interface once 64 bytes again become available in the DMAFIFO If the bus was released due to encountering a VON boundary the bus is not re requested until the VOFF timer expires PCI bus transactions are the full width of the PCI data bus with appropriate byte lanes enabled The maximum VMEbus data width is programmable to 8 16 32 or 64 bits Byte transfers can be only of type DO8 EO Because the PCI bus has a more flexible byte lane enabling scheme than the VMEbus the Universe II can be required to generate a variety of VMEbus transaction types to handle the byte resolution of the starting and ending addresses see Universe II as PCI Target on page 57 DMA Interrupts The Interrupt Channel in the Universe II handles a single interrupt sourced from the DMA Channel which it routes to either the VMEbus or PCI bus through the DMA bits in the LINT_EN and VINT_EN registers There are six internal DMA sources o
169. asserted until SYSRST is negated However when SYSRST is negated the local CPU performs diagnostics and local logic sets the AUTOID bit in the Miscellaneous Control Register MISC_CTL on page 273 This asserts IRQ2 and releases SYSFAIL After SYSFAIL is released and the Universe II detects a level 2 IACK cycle it responds with the STATUS ID stored in its STATID register The default value is OxFE Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 2 VMEbus Interface gt Automatic Slot Identification 43 2 6 1 1 2 6 2 The Universe II can be programmed so that it does not release SYSFAIL until the SYSFAIL bit in the VMEbus CSR Bit Clear Register VCSR_CLR on page 329 is cleared by local logic SYSFAIL is asserted if the SYSFAIL bit in the VMEbus CSR Bit Set Register VCSR_SET on page 330 is set at power up Since the system Monarch does not service the Auto ID slave until after SYSFAIL is negated not clearing the SYSFAIL bit allows the Auto ID process to be delayed until the CPU completes local diagnostics Once local diagnostics are complete the CPU clears the SYSFAIL bit and the Auto Slot ID cycle proceeds The Monarch can perform CR CSR reads and writes at A 23 19 0x00 in CR CSR space and re locate the Universe II s CR CSR base address Universe II and the Auto Slot ID Monarch At power up an Auto Slot ID Monarch waits to run a IACK cycle until after SYSFAIL goe
170. ated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 191 12 3 16 PCI Target Image 2 Control LSI2 CTL In the PCI Target Image Control register setting the VCT bit will only have effect if the VAS bits are programmed for A24 or A32 space and the VDW bits are programmed for 8 bit 16 bit or 32 bit If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64 bit the Universe II may perform MBLT transfers independent of the state of the VCT bit The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I O Space forcing all transactions through this image to be coupled Register name LSI2 CTL Register offset 0x13C TE ERE ee DC CORE ee Sere oe eee ere we mem y Reserved BE Reset Description Type Reset by value Image Enable R W All Undefined 0 Disable 1 Enable Posted Write Enable R W All 0x00 0 Disable 1 Enable 23 22 VMEbus Maximum Data width R W All 0b10 00 8 bit data width 01 16 bit data width 10 32 bit data width 11 64 bit data width Integrated Device Technology Universe II User Manual www idt com May 12 2010 192 12 Registers gt Register Description Reset Description Type Reset by value 18 16 VMEbus Address Space R W All Undefined 000 A16 001 A24 010 A32 011 Reserved 100 Reserved 101 CR CSR 110 User1 111 User2 a fa T 9 Program Data AM Code R W All 0x00 0 Data 1 Program Tee o ee SUPER Supervisor User
171. ated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 207 Description 26 24 CWT Coupled Window Timer 000 Disable release after first coupled transaction 001 16 PCI Clocks 010 32 PCI Clocks 011264 PCI Clocks 100 2128 PCI Clocks 1012256 PCI Clocks 1102512 PCI Clocks others Reserved Reserved Reserved The Universe II uses CWT to determine how long to hold ownership of the VMEbus after processing a coupled transaction The timer is restarted each time the Universe II processes a coupled transaction If this timer expires the PCI Slave Channel releases the VMEbus Device behavior is unpredictable if CWT is changed during coupled cycle N activity Integrated Device Technology Universe Il User Manual www idt com May 12 2010 208 12 Registers gt Register Description 12 3 30 Special PCI Target Image SLSI This register fully specifies an A32 capable special PCI Target Image The base is programmable to a 64 Mbyte alignment and the size is fixed at 64 Mbytes Incoming address lines 31 26 in Memory or I O must match this field for the Universe II to decode the access This special PCI Target Image has lower priority than any other PCI Target Image The 64 Mbytes of the SLSI is partitioned into four 16 Mbyte regions numbered 0 to 3 0 is at the lowest address PCI address bits 25 24 are used to select regions The top 64 Kbyte of each region is mapped to VMEbus A16 space and the r
172. ates into the transfer i e it never negates IRDY_ until the transaction is complete and will whenever possible generate full aligned bursts as set in the PABS field of the MAST_CTL register Between transactions on the PCI bus the Universe II DMA typically sits idle for 6 clocks Hence minimizing the number of idle periods and re arbitration times by setting PABS to its maximum value of 128 bytes may increase the performance of the DMA on this bus Higher PABS values imply that the Universe II will hold on to both the PCI bus and the VMEbus for longer periods of time The reason that PABS also may impact on VMEbus tenure is that in the case of PCI writes the DMA FIFO is less likely to fill and in the case of PCI reads the DMA is less likely to go empty However given the relative speeds of the buses and the relative watermarks the effect of PABS on VMEbus utilization is not as significant as its effects on the PCI bus While higher values of PABS increase DMA throughput they may increase system latency That is there will be a longer latency for other PCI transactions including possible transactions coming through the VME Slave Channel since the DMA channel will own the PCI bus for longer periods of time Also accesses between other PCI peripherals will on average have a longer wait before being allowed to perform their transactions PCI latency must be traded off against possible DMA performance Although both read and write tra
173. ation REQ64 has an internal pull up If a non default configuration is required a pull up of approximately 10k Q is required on the signal See PCI Bus Width on page 138 and the VMEbus Specification The Universe II may be restored to the state it was in immediately following the previous power up without re asserting PWRRST_ After SYSRST or RST_ with PWRRST_ negated the values that were originally latched at the rising edge of PWRRST are reloaded into the Universe II except for PCI bus width and VMEbus SYSCON enabling which are loaded from their pins Table 22 lists the power up options of the Universe II the pins which determine the options and the register settings that are set by this option Each option is described in more detail in Power up Option Descriptions on page 136 Power up Option Descriptions This section describes each of the groups of power up options that were listed in Table 22 VMEbus Register Access Image The Universe II has several VMEbus slave images each of which can provide a different mapping of VMEbus cycles to PCI cycles All VMEbus slave images are configurable through a set of VMEbus slave image registers VSIx CTL VSIx BS VSIx BD and VSIx TO i No VMEbus to PCI transaction is possible until these registers are programmed The VMEbus Register Access Image VRAI power up option permits access from the VMEbus to the Universe II internal registers at power up The power up option allows
174. ats to a full 64 bit width before queuing the data into new entries in the TXFIFO For 32 bit PCI transfers in the Universe II the TXFIFO accepts a single burst of one address phase and 59 data phases when it is empty For 64 bit PCI the TXFIFO accepts a single burst of one address phase and 31 data phases when it is empty To improve PCI bus utilization the TXFIFO does not accept a new address phase if it does not have room for a burst of one address phase and 128 bytes of data If the TXFIFO does not have enough space for an aligned burst then the posted write transaction is terminated with a Target Retry immediately after the address phase When an external PCI Master posts writes to the PCI Target Channel of the Universe II the Universe II issues a disconnect if the address crosses a 256 byte boundary Before a transaction can be delivered to the VMEbus from the TXFIFO the PCI Target Channel must obtain ownership of the VMEbus Master Interface Ownership of the VMEbus Master Interface is granted to the different channels on a round robin basis see V MEbus Release on page 27 Once the PCI Target Channel obtains the VMEbus through the VMEbus Master Interface the manner in which the TXFIFO entries are delivered depends on the programming of the VMEbus attributes in the PCI target image see PCI Bus Target Images on page 70 For example if the VMEbus data width is programmed to 16 bit and block transfers are disabled then each data entr
175. bit of the PCI Interrupt Status Register LINT STAT on page 244 PCI and VMEbus Error Interrupts Interrupts from VMEbus errors PCI Target Aborts or Master Aborts are generated only when bus errors arise during decoupled writes The bus error interrupt from either a PCI or VMEbus error can be mapped to either a VMEbus or PCI interrupt output line VME64 Auto ID The Universe II includes a power up option for participation in the VME64 Auto ID process When this option is enabled the Universe II generates a level 2 interrupt on the VMEbus before release of SYSFAIL When the level 2 IACK cycle is run by the system Monarch the Universe II responds with the Auto ID Status ID OxFE and enables access to a CR CSR image at base address 0x00_0000 When the Monarch detects an Auto ID STATUS ID on level 2 it is expected to access the enabled CR CSR space of the interrupter From there it completes identification and configuration of the card The Monarch functionality is typically implemented in software on one card in the VMEbus system See Automatic Slot Identification on page 42 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 124 7 Interrupt Generation and Handling gt Interrupt Handling Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 8 8 1 8 2 8 3 125 Error Handling Errors occur in a system as a result of parity bus or internal problems In orde
176. by the DMAC when it loads the command packet The DMA only accesses PCI Bus Memory space The VCT bit determines whether or not the Universe II VME Master will generate BLT transfers The value of this bit only has meaning if the address space is A24 or A32 and the data width is not 64 bits If the data width is 64 bits the Universe II may perform MBLT transfers independent of the state of the VCT bit Register name DCTL Register offset 0x200 9m 24 Reserved ES 16 Beewd o O EUM 08 NNNM Reserved VINC LD amp AEN Reserved Direction O Transfer from VMEbus to PCI Bus 1 Transfer from PCI Bus to VMEbus VMEbus Maximum Datawidth 00 8 bit data width 01 216 bit data width 10 32 bit data width 11264 bit data width VMEbus Address Space 000 A16 001 A24 010 A32 011 Reserved 100 Reserved 101 Reserved 110 User1 111 User2 Program Data AM Code 00 Data 01 Program others Reserved Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 233 NO_VINC LD64EN Supervisor User AM Code 00 Non Privileged 01 Supervisor others Reserved VMEbus Non Incrementing Mode Non Inc Mode O disabled 1 enabled VMEbus Cycle Type 0 no BLTs on VMEbus 1 BLTs on VMEbus Enable 64 bit PCI Bus Transactions 0 Disable 1 Enable Integrated Device Technology Universe Il User Manual www idt com May 12 2010 234 12 Registers gt Regis
177. c uses of mailboxes depend on the application For example they can be used when a master on one bus needs to pass information a message on the other bus without knowing where the information should be stored in the other bus s address space Or they can be used to store the address of a longer message written by the processor on one bus to the address space on the other bus through the Universe II They can also be used to initiate larger transfers through the FIFO in a user defined manner Often users will enable and map mailbox interrupts so that when the processor writes to a mailbox from one bus the Universe II will interrupt the opposite bus The interrupt service routine on the opposite bus would then cause a read from this same mailbox Reading a mailbox cannot automatically trigger an interrupt However a similar effect can be achieved by reading the mailbox and then triggering an interrupt through hardware or software Or one may use a polling approach where one designates a bit in a mailbox register to indicate whether one has read from the mailbox For details on how the mailbox interrupts are enabled and mapped see Interrupt Generation and Handling on page 109 and Mailbox Register Access Interrupts on page 122 Applications will sometimes designate two mailboxes on one interface as being read write from the PCI bus and read only from the VMEbus and the two other mailboxes as read write from the VMEbus and re
178. card which is only performing system control functions the counter would be set to minimum On a card which is responsible for transferring considerable amounts of performance critical data the counter will be set much higher at the expense of system latency Universe Il User Manual Integrated Device Technology May 12 2010 www idt com B Performance gt PCI Slave Channel 339 B 2 2 2 B 2 2 3 PCI Target Response As the PCI target during decoupled write operations to the VMEbus the Universe II responds in one of two manners 1 It immediately issues a target retry because the FIFO does not have sufficient room for a burst of one address phase and 128 bytes of data There are no programmable watermarks in the PCI Target Channel The PCI Aligned Burst Size PABS does not affect the PCI Target Channel 2 It responds as a zero wait state target receiving up to 256 bytes in a transaction When the FIFO is full or a 256 byte boundary has been reached the Universe II issues a Target Disconnect In either case the Universe II will consume the minimum possible PCI bandwidth never inserting wait states VME Master Performance As a VME master the Universe II waits until a full transaction has been enqueued in the Tx FIFO before requesting the VMEbus and generating a VME cycle If the VMEbus is already owned by the decoupled path see Effect of the PWON Counter on page 338 the Universe II still waits until a full transacti
179. cess from the VMEbus There are two mechanisms to access the UCSR space from the VMEbus One method uses a VMEbus Register Access Image VRAI which can put the UCSR in an A16 A24 or A32 address space The VRAI approach is useful in systems not implementing CR CSR space as defined in the VM E64 Specification The other way to access the UCSR is as CR CSR space where each slot in the VMEbus system is assigned 512 Kbytes of CR CSR space 5 3 1 VMEbus Register Access Image VRAI The VMEbus Register Access Image occupies 4 Kbytes in A16 A24 or A32 space depending upon the programming of the address space described in Table 13 and Figure 13 All registers are accessed as address offsets from the VRAI base address programmed in the VMEbus Register Access Image Base Address Register VRAI BS on page 304 The image can be enabled or disabled using the EN bit in the VMEbus Register Access Image Control Register VRAI_CTL on page 303 The VMEbus register access image is defined by Table 13 Table 13 Programming the VMEbus Register Access Image Address space VAS in the VRAI CTL One of A16 A24 A32 Base address address BS 31 12 in the VRAI_BSi Lowest address in the 4Kbyte slave image EL in the VRAI CTL Enables VMEbus register access image enable SUPER in the VRAI CTL Supervisor and or Non Privileged PGM in the VRAI CTL Program and or Data Note that the VRAI base address can be configured as a power up option see Resets C
180. chanism for VMEbus to PCI Bus Transfers Figure9 Address Translation Mechanism for PCI Bus to VMEbus Transfers Figure 10 Memory Mapping in the Special PCI Target Image 0000 Figure 11 Universe II Control and Status Register Space 0 00 000004 Figure 12 PCI Bus Access to UCSR as Memory or I O Space 0 00 0000000 Figure 13 UCSR Access from the VMEbus Register Access Image 000 Figure 14 UCSR Access in VMEbus CR CSR Space 0 0 eee eee Figure 15 Direct Mode DMA transfers Figure 16 Command Packet Structure and Linked List Operation Figure 17 DMA Linked List Operation ssseeeeeeeeeeee eee eee Figure 18 Universe Interrupt Circuitry 0 0 0 cee eee eee Figure 19 STATUS ID Provided by Universe I Figure 20 Sources of Internal Interrupts 00 000 c cee ee eee eee es Figure 21 Reset Circuitry nob id oecetese ares Gea te bee we DUE RU bad cee pert i d arid V Figure 22 Resistor Capacitor Circuit Ensuring Power Up Reset Duration Figure 23 Power up Options Timing 0 ee Figure 24 UCSR Access Mechanisms eseleeseeeeee eee Figure 25 313 PBGA Bottom View sseeeeeeeeel eens Figure 26 313 PBGA Top and Side View 10 0 cee eee Figure 27 Coupled Read Cycle Universe II as VME Master 000000 Figure 28 Several Coupled Read Cycles
181. chnology Universe Il User Manual www idt com May 12 2010 18 1 1 1 Universe II User Manual May 12 2010 1 Functional Overview gt Overview Figure 1 Universe II Block Diagram 32 bit Address 64 bit Data 33 MHz PCI Bus 1 Four Location Monitors Fixed Priority To Support VMEbus Round Robin Broadcast Capability Single Level Modes E VMEbus Slave Channel Posted Writes Prefetched Reads Coupled Reads DMA Channel Bidirectional FIFO Direct Linked List Mode Register Channel Configuraion Registers Mailbox Registers Semaphores Interrupt Channel Interrupt Handler Interrupter 32 bit Address 64 bit Data PCI Target Channel Posted Writes Coupled Read l 8091142 BKO01 05 IEEE1149 1 Boundary Scan Universe ll Features The Universe II has the following features Industry proven high performance 64 bit VMEbus interconnect Fully compliant 32 bit or 64 bit 33 MHz PCI bus interconnect Integral FIFOs for write posting to maximize bandwidth utilization Programmable DMA controller with Linked List mode Scatter Gather support Flexible interrupt logic Sustained transfer rates up to 60 70 Mbytes s Extensive suite of VMEbus address and data transfer modes Automatic initialization for slave only applications Flexible register set programmable from both the PCI bus and VMEbus ports Full VMEbus system controller Support for RMWs ADOH PCI LOCK cycles and semaphores 33 MHz PCI Bus
182. clear this bit before re asserting it Software interrupts on the VMEbus have priority over other interrupts mapped internally to the same level on the VMEbus When a VMEbus interrupt handler generates an IACK cycle on a level mapped to both a software interrupt and another interrupt the Universe II always provides the STATUS ID for the software interrupt bit zero of the Status ID is cleared If there are no other active interrupts on that level the interrupt is automatically cleared upon completion of the IACK cycle since software interrupts are ROAK While the software interrupt STATUS ID has priority over other interrupt sources the user can give other interrupt sources priority over the software interrupt This is done by reading the PCI Interrupt Status Register LINT STAT on page 244 when handling a Universe II interrupt This register indicates all active interrupt sources Using this information the interrupt handler can then handle the interrupt sources in any system defined order Software IACK Interrupt The Universe II generates an internal interrupt when it provides the software STATUS ID to the VMEbus This interrupt can only be routed to a PCI interrupt output A PCI interrupt is generated upon completion of an IACK cycle that had been initiated by the Universe II s software interrupt if the following occurs The SW IACK bit is set in the PCI Interrupt Status Register LINT STAT on page 244 e TheSW IACK field in t
183. cycles can only be generated when the VAS field in the appropriate VSIx CTRL register is programmed for either A32 USERI or USER2 Both Type 0 and Type 1 cycles are generated and handled through the same mechanism Once a VMEbus cycle is received and mapped to a configuration cycle the Universe II compares bits 23 16 of the incoming address with the value stored in the Bus Number field BUS NO 7 0 in the Master Control Register MAST_CTL on page 271 If the bits are the same as the BUS NO field then a TYPE 0 access is generated If they are not the same a Type configuration access is generated The PCI bus generated address then becomes an unsigned addition of the incoming VMEbus address and the VMEbus slave image translation offset Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 2 VMEbus Interface gt Universe Il as VMEbus Slave 39 2 4 8 1 Generating Configuration Type 0 Cycles The Universe II asserts one of AD 31 11 on the PCI bus to select a device during a configuration Type 0 access To perform a configuration Type 0 cycle on the PCI bus the following steps must be completed 1 Program the LAS field of VSIx_CTL for Configuration Space Program the VSIx_BS VSIx_BD registers to some suitable value Program the VSIx_TO register to 0 Program the BUS_NO field of the MAST_CTL register to some value eo gm Perform a VMEbus access where e VA 7 2 identifies the PCI Register Numbe
184. d the ACT bit is set by the Universe II and execution continues as if no HALT had occurred that is the Universe II processes the current command packet see Figure 16 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 100 6 4 1 6 DMA Controller gt Linked list Mode In contrast to a halt the DMA can also be immediately terminated through the STOP_REQ bit This stops all DMA operations on the source bus immediately and set the STOP bit in the same register when the last piece of queued data in the DMA FIFO has been written to the destination bus Once stopped the DVA DLA and DTBC registers contain values indicating the next addresses to read write and the number of bytes remaining in the transfer Clearing the STOP bit and setting the GO bit causes the DMA to start up again from where it left off including continuing with subsequent command packets in the list If the DMA is being stopped to insert a high priority DMA transfer the remaining portion of the DMA transfer can be stored as a new command packet inserted at the top of the linked list A new command packet with the attributes of the high priority transfer is then placed before that one in the list Now the linked list is set up with the high priority packet first followed be the remainder of the interrupted packet followed in turn by the rest of the linked list Finally the DTBC register is cleared and the DCPP programmed with a pointer to t
185. d release conditions for the DMA Integrated Device Technology Universe Il User Manual www idt com May 12 2010 92 6 2 6 3 6 DMA Controller gt DMA Registers See DMA Channel Interactions with Other Channels on page 105 for information on other mechanisms which can delay the DMA Channel from acquiring the VMEbus or the PCI bus DMA Completion and Termination Normally the DMA continues processing its transfers and command packets until either it completes all requests or it encounters an error There are also two methods for the user to interrupt this process and cause the DMA to terminate prematurely STOP and HALT STOP causes the DMA to terminate immediately while HALT causes the DMA to terminate when it has completed processing the current command packet in a linked list STOP When the STOP_REQ bit in the DGCS register is set it tells the DMA to cease its operations on the source bus immediately Remaining data in the FIFO continues to be written to the destination bus until the FIFO is empty Once the FIFO is empty the STOP bit in the same register is set and if enabled an interrupt generated The DMA registers contain the values that the DMA stopped at the DTBC register contains the number of bytes remaining in the transfer the source and destination address registers contain the next address to be read written the DCPP register contains the next command packet in the linked list and the DCTL register conta
186. data VD 31 0 transceivers as required for master slave and bus isolation modes When the Universe II is driving lines on the VMEbus this signal is driven high when the VMEbus is driving the Universe ll this signal is driven low VDS 1 0 Bidirectional VMEbus Data Strobes the level of these signals are used to indicate active byte lanes During write cycles the falling edge indicates valid data on the bus During read cycles assertion indicates a request to a slave to provide data VDS DIR Output VMEbus Data Strobe Direction Control controls the direction of the data strobe transceivers as required for master slave and bus isolation modes When the Universe II is driving lines on the VMEbus this signal is driven high when the VMEbus is driving the Universe ll this signal is driven low VDTACK Bidirectional VMEbus Data Transfer Acknowledge VDTACK driven low indicates that the addressed slave has responded to the transfer The Universe II always rescinds DTACK It is tristated once the initiating master negates AS VIACK Bidirectional VMEbus Interrupt Acknowledge Indicates that the cycle just beginning is an interrupt acknowledge cycle VIACKI_ Input VMEbus Interrupt Acknowledge In Input for IACK daisy chain driver If interrupt acknowledge is at same level as interrupt currently generated by the Universe ll then the cycle is accepted If interrupt acknowledge is not at s
187. data bus Integrated Device Technology Universe Il User Manual www idt com May 12 2010 148 10 Signals and Pinout gt PCI Bus Signals Table 27 PCI Bus Signals AD 63 32 Bidirectional PCI Address Data Bus Address and data are multiplexed over these pins providing 64 bit address and data capability C BE_ 7 0 Bidirectional PCI Bus Command and Byte Enable Lines Command and byte enable information is multiplexed over all eight C BE lines C BE 7 4 _ are only used in a 64 bit PCI bus DEVSEL _ Bidirectional PCI Device Select This signal is driven by the Universe II when it is accessed as PCI slave ENID Input Enable IDD Tests Required for ASIC manufacturing test tie to ground for normal operation FRAME_ Bidirectional Cycle Frame This signal is driven by the Universe II when it is PCI initiator and is monitored by the Universe Il when itis PCI target GNT_ Input PCI Grant indicates to the Universe II that it has been granted ownership of the PCI bus IDSEL Input PCI Initialization Device Select This signal is used as a chip select during configuration read and write transactions LINT 7 0 _ Bidirectional Open Drain PCI Interrupt Inputs These PCI interrupt inputs can be mapped to any PCI bus or VMEbus interrupt output IRDY_ Bidirectional Initiator Ready Is used by the Universe Il as PCI master to ind
188. data queued from the source not what has been written to the destination In this case the error will have occurred up to 256 bytes before the original address plus the byte count Given this background the following procedure can be implemented to recover from errors 1 Read the value contained in the DTBC register 2 Read the record of the DVA and DLA that is stored on the PCI bus or elsewhere not the value stored in the Universe II registers of the same name 3 If the difference between the value contained in the DTBC register and the original value is less than 512 bytes the FIFO depth of the Universe II reprogram all the DMA registers with their original values 4 If the difference between the value contained in the DTBC register and the original value is greater than 512 bytes the FIFO depth of the Universe II add 512 bytes to the value contained in the DTBC register 5 Add the difference between the original value in the DTBC and the new value in the DTBC register to the original value in the DLA register 6 Add the difference between the original value in the DTBC and the new value in the DTBC register to the original value in the DVA register 7 Clear the status flags 8 Restart the DMA see DMA Initiation on page 90 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 108 6 DMA Controller gt DMA Error Handling Universe Il User Manual Integrated Device Technology
189. dently of the other The Universe II however because of the finite size of its FIFOs does not represent a 10046 decoupled bridge As the FIFOs fill or empty depending on the direction of data movement the two buses tend to migrate to matched performance where the higher performing bus is forced to slow down to match the other bus This limits the sustained performance of the device Some factors such as the PCI Aligned Burst Size and VME request release modes can limit the effect of FIFO size and enhance performance Another aspect in considering the performance of a device is bandwidth consumption The greater bandwidth consumed to transfer a given amount of data the less is available for other bus masters Decoupling significantly improves the Universe II s bandwidth consumption and on the PCI bus allows it to use the minimum permitted by the PCI specification To simplify the analysis and allow comparison with other devices Universe II performance has been calculated using the following assumptions Integrated Device Technology Universe II User Manual www idt com May 12 2010 336 B 2 B 2 1 B 2 1 1 B Performance gt PCI Slave Channel e Asa PCI master one clock bus grant latency zero wait state PCI target Asa VME master ideal VME slave response DS to DTACK 30ns Assumed as part of any calculation on VME performance is the inclusion of VME transceivers with propagation delay of 4 ns This append
190. ds on the PCI bus of length defined by the PCI Aligned Burst Size PABS in the MAST_CTL register These burst reads continue while the block transfer is still active on the VMEbus AS not negated and there is room in the RDFIFO If there is insufficient room in the RDFIFO to continue a common occurrence since the Universe II is capable of fetching data from the PCI bus at a much faster rate than a VME master is capable of receiving it then pre fetching stops and only continues once enough room exists in the RDFIFO for another full burst size The first data beat of a block transfer must wait for the first data beat to be retrieved from the PCI bus this is essentially a coupled transfer See the section on coupled transfers for details on coupled performance However once the pre fetching begins data is provided by the Universe II in subsequent data beats with a slave response of 57ns This continues while there is data in the RDFIFO If the RDFIFO empties because data is being fetched from the PCI bus too slowly wait states are inserted on the VMEbus awaiting the enqueueing of more data Integrated Device Technology Universe II User Manual www idt com May 12 2010 346 B Performance gt VME Slave Channel On the PCI bus the Universe II fetches data at 89 MB s with PABS set to 32 byte transactions 106 MB s when set to 64 byte transactions Even better performance is obtained if PABS is set for 128 byte transactions Once the RDFIFO fills
191. e PCI to VMEbus Transfers on page 101 The Universe II provides a software mechanism for VMEbus acquisition through the VMEbus ownership bit VOWN in the Master Control Register MAST CTL on page 271 When the VMEbus ownership bit is set the Universe II acquires the VMEbus and sets an acknowledgment bit VOWN ACK in the MAST CTL register and optionally generates an interrupt to the PCI bus see VME Lock Cycles Exclusive Access to VMEbus Resources on page 63 The Universe II maintains VMEbus ownership until the ownership bit is cleared During the VMEbus tenure initiated by setting the ownership bit only the PCI Target Channel and Interrupt Channel can access the VMEbus Master Interface Request Modes The Universe II has configurable request modes of operation Request Levels The Universe II is software configurable to request on any one of the four VMEbus request levels BR3 BR2 BR1 and BRO The default setting is for level 3 VMEbus request The request level is a global programming option set through the VMEbus Release Mode VRL field in the Master Control Register MAST_CTL on page 271 The programmed request level is used by the VMEbus Master Interface regardless of the channel Interrupt Channel DMA Channel or PCI Target Channel currently accessing the VMEbus Master Interface Fair and Demand Modes The Universe II requester can be programmed for either Fair or Demand mode The request mode is a glob
192. e Il as PCI Master 53 3 2 6 3 3 Parity Checking The Universe II both monitors and generates parity information using the PAR signal The Universe II monitors PAR when it accepts data as a master during a read or a target during a write The Universe II drives PAR when it provides data as a target during a read or a master during a write The Universe II also drives PAR during the address phase of a transaction when it is a master and monitors PAR during an address phase when it is the PCI target In both address and data phases the PAR signal provides even parity for C BE 3 0 and AD 31 0 The Universe II continues with a transaction independent of any parity error reported during the transaction The Universe II can also be programmed to report address parity errors It does this by asserting the SERR signal and setting a status bit in its registers No interrupt is generated and regardless of whether assertion of SERR_ is enabled the Universe II does not respond to the errored access When the Universe II is powered up in a 64 bit PCI environment it uses PAR64 in the same way as PAR except for AD 63 32 and C BE 7 4 Universe II reports parity errors during all transactions with the PERR_ signal The Universe II drives PERR high within two clocks of receiving a parity error on incoming data and holds PERR_ for at least one clock for each errored data phase Universe Il as PCI Master The Universe II requests PCI bus mastership
193. e PCI Reset OzNo effect 1 Initiate LRST_ A read always returns 0 Software VMEbus SYSRESET OzNo effect 1 Initiate SYSRST A read always returns 0 Board Reset Reads O LRST not asserted 1 LRST asserted Writes 0 no effect 1 assert LRST_ VMEbus SYSFAIL Reads 0 VXSYSFAIL not asserted 1 VXSYSFAIL asserted Writes 0 no effect 1 assert VXSYSFAIL Integrated Device Technology www idt com 9 Resets Clocks and Power up Options gt Resets 131 Table 20 Software Reset Mechanism VMEbus CSR RESET R W Board Reset Bit Clear Reads Register VCSR_CLR O LRST_ not asserted on page 329 1 LRST_ asserted Writes O no effect 1 negate LRST_ SYSFAIL R W VMEbus SYSFAIL Reads 0 VXSYSFAIL not asserted 1 VXSYSFAIL asserted Writes 0 no effect 1 negate VXSYSFAIL Integrated Device Technology Universe II User Manual www idt com May 12 2010 132 9 2 1 Universe ll Reset Circuitry 9 Resets Clocks and Power up Options gt Resets Table 21 on page 132 and Figure 21 on page 133 shows how to reset various aspects of the Universe II For example it shows that in order to reset the clock services SYSCLK CLK64 enables and PLL divider PWRRST_ must be asserted PWRRST_ resets all aspects of Universe II listed in column 1 of Table 21 Table 21 also indicates the reset effects that are extended in time For example VXSYSRST_ remains asserted for 256 ms after all initiators are removed this satisfies
194. e Test Clock Input EA Test Data Input PU tmode EE E 3 Test Mode Enable tmode 1 AA21 VA 31 1 Listed in 313 Pin PBGA Package on page 333 Mic EZ JTAG Test Mode Select e PCI Target Ready TE JTAG Test Reset VMEbus Address Pins oa 3 VMEbus Address Modifier Signals VMEbus AM Signal Direction Control TTL Schm VMEbus Address Strobe 3S VMEbus AS Direction Control 3S 12 12 VMEbus Address Direction Control Integrated Device Technology Universe Il User Manual www idt com May 12 2010 158 11 Electrical Characteristics gt DC Characteristics Table 30 Pin List and DC Characteristics for Universe II Signals Continued ETHETSESEZSEJEJES Type Input Type Type mA mA Signal Description VMEbus Bus Grant In NEN VD 81 0 Listed in 313 Pin PBGA Package on page 333 NN a 3S s 3S 12 12 VMEbus Data Direction Control m 3S VMEbus Data Strobe Direction Control TT PD TTL TTL PU TTL Schm 3S 3 3 VMEbus DTACK Signal PU TTL TTL TTL PD TTL 1 0 1 0 1 0 3S 12 12 VMEbus IACKOUT Signal lam ett tt _ 3S 24 24 VMEbus Transceiver Output Enable TTL Schm pomme VMEbus ACFAIL Signal Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 11 Electrical Characteristics gt DC Characteristics 159 Table 30 Pin List and DC Characteristics for Universe Il Signals Continued Output lo loH Type Input Type Type mA mA
195. e Universe II Neither system identifies geographical addressing only the relative position amongst the boards present in the system for example fourth board versus fourth slot Both the VME64 Auto Slot ID and the DY4 method of automatic slot identification are activated through a power up option Refer Power Up Options on page 135 for more information Auto ID prevents the need for jumpers to uniquely identify cards in a system The benefits of this feature are Increases the speed of system level repairs in the field e Reduces the possibility of incorrect configurations e Reduces the number of unique spare cards that must be stocked Auto Slot ID VME64 Specified The VME64 Auto Slot ID cycle as described in the VME64 Specification requires at power up that the Auto ID slave takes the following actions e Generate IRQ2 e Negate SYSFAIL When the Auto Slot ID slave responds to the Monarch s IACK cycle the following actions are taken 1 Enable accesses to its CR CSR space 2 Provide a Status ID to the Monarch indicating the interrupt is an Auto ID request 3 Assert DTACK 4 Release IRQ2 The Universe II participates in the VME64 Auto Slot ID cycle in either an automatic or semi automatic mode In its fully automatic mode it holds SYSFAIL asserted until SYSRST is negated When SYSRST is negated the Universe II asserts IRQ2 and releases SYSFAIL In its semi automatic mode the Universe II still holds SYSFAIL
196. e Universe II always performs Address Invariant translation between the PCI and VMEbus ports Address Invariant mapping preserves the byte ordering of a data structure in a little endian memory map and a big endian memory map Little endian Mode Table 42 shows the byte lane swapping and address translation between a 32 bit little endian PCI bus and the VMEbus for the address invariant translation scheme Integrated Device Technology Universe Il User Manual www idt com May 12 2010 360 D Endian Mapping gt Little endian Mode Table 42 Mapping of 32 bit Little Endian PCI Bus to 32 bit VMEbus PCI Bus Byte Enables Address Ea E EA pope BT e e Denm D pese E Ea DOD lt gt DMO8 D7 D24 D31 ae D15 D16 D23 D 6D23 lt gt D8D5 D23 D8 D15 D 6D23 lt gt D8Di5 D23 lt gt D8 D15 as D2409 lt gt DoD lt gt D0 D7 ae D7 lt gt D24 D31 SS D15 D16 D23 D24 D24031 lt gt D007 DO D7 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com D Endian Mapping gt Little endian Mode 361 The unpacking of multiplexed 64 bit data from the VMEbus into two 32 bit quantities on a little endian PCI bus is outlined in Table 43 below Table 43 Mapping of 32 bit Little Endian PCI Bus to 64 bit VMEbus Byte Enables Address CE DEE _ eem First Transfer D32 D63 e e ee D0 D7 A24 A31 D56 D63 D8 D15 A16 A23 D amp Di5 lt gt A16 A23 D48 D5
197. e generated so if the requested PCI data beat has unaligned or non byte enables then it is broken into multiple aligned VMEbus transactions no wider than the programmed VMEbus data width For example consider a three byte PCI data beat on a 32 bit PCI bus accessing a PCI target image with VDW set to 16 bits The three byte PCI data beat is broken into three aligned VMEbus cycles three single byte cycle the ordering of the cycles depends on the arrangement of the byte enables in the PCI data beat If in the above example the PCI target image has a VDW set to 8 bit then the three byte PCI data beat is broken into three single byte VMEbus cycles Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 2 VMEbus Interface gt Universe Il as VMEbus Master 31 2 3 3 BLT MBLT cycles are initiated on the VMEbus if the PCI target image has been programmed with this capacity see PCI Bus Target Images on page 70 The length of the BLT MBLT transactions on the VMEbus is determined by the initiating PCI transaction For example a single data beat PCI transaction queued in the TXFIFO results in a single data beat block transfer on the VMEbus With the PWON field the user can specify a transfer byte count that is queued from the TXFIFO before the VMEbus Master Interface relinquishes the VMEbus The PWON field specifies the minimum tenure of the Universe II on the VMEbus However tenure is extended if the VOWN bit in
198. e the DMA is still active and restarts the DMA for case 2 If an error has been encountered by the DMA case 3 setting the GO bit and clearing the DONE bit is not be sufficient to restart the DMA the error bits in the DGCS register also has to be cleared before operation can continue FIFO Operation and Bus Ownership The DMA uses a 256 byte 64 bit FIFO DMAFIFO This supports high performance DMA transfers In general the DMA reads data from the source and stores it as transactions in the FIFO On the destination side the DMA requests ownership of the master and once granted begins transfers Transfers stop on the source side when the FIFO fills and on the destination side when the FIFO empties 6 5 1 PCI to VMEbus Transfers PCI to VMEbus transfers involve the Universe II reading from the PCI bus and writing to the VMEbus Integrated Device Technology Universe II User Manual www idt com May 12 2010 102 6 DMA Controller gt FIFO Operation and Bus Ownership The PCI bus is requested for the current read once 128 bytes are available in the DMAFIFO The DMA Channel fills the DMAFIFO using PCI read transactions with each transaction broken at address boundaries determined by the programmed PCI aligned burst size PABS field in the Master Control Register MAST_CTL on page 271 This ensures that the DMA makes optimal use of the PCI bus by always generating bursts of 32 64 or 128 bytes with zero wait states The DMA packs re
199. ecoupling the power and ground pins on the Universe II A separate analog power and ground plane is not required to provide power to the analog portion of the Universe II However to ensure a jitter free PLL operation the analog AVpp and AVgs pins must be noise free The following are recommended solutions for noise free PLL operation The design could implement one of these solutions but not both The Analog Isolation Scheme consists of the following e a0 1uF capacitor between the AVpp and AV gg pins and corresponding inductors between the pins and the board power and ground planes See Figure 44 These inductors are not necessary but they are recommended Figure 44 Analog Isolation Scheme Board VDD 1 5 220 nH AVDD 0 1 uF AVSS 1 5 220 nH Board VSS The Noise Filter Scheme filters out the noise using two capacitors to filter high and low frequencies See Figure 45 Figure 45 Noise Filter Scheme Board VDD 10 38 AVDD 22 uF 0 01 pF Ow Freq bias AVSS Board VSS For both schemes it is recommended that the components involved be tied as close as possible to the associated analog pins Integrated Device Technology Universe Il User Manual www idt com May 12 2010 372 E Typical Applications gt Decoupling VDD and VSS on the Universe II In addition to the decoupling schemes shown above it is recommended that 0 1uF bypass capacitors should be tied between every three pairs of Vpp pins and the board ground
200. ed as coupled transactions Write transactions can be either coupled or posted depending upon the setting of the PCI bus target image see PCI Bus Target Images on page 70 With a posted write transaction write data is written to a Posted Write Transmit FIFO TXFIFO and the PCI bus master receives data acknowledgment from the Universe II with zero wait states Meanwhile the Universe II obtains the VMEbus and writes the data to the VMEbus resource independent of the initiating PCI master see Posted Writes on page 60 for a full description of this operation The Universe II has a Special Cycle Generator that enables PCI masters to perform RMW and ADOH cycles The Special Cycle Generator must be used in combination with a VMEbus ownership function to guarantee PCI masters exclusive access to VMEbus resources over several VMEbus transactions see Special Cycle Generator on page 61 and Using the VOWN bit on page 64 for a full description of this functionality 1 2 2 2 Universe II as PCI Master The Universe II becomes PCI master when the PCI Master Interface is internally requested by the VMEbus Slave Channel or the DMA Channel There are mechanisms provided which allow the user to configure the relative priority of the VMEbus Slave Channel and the DMA Channel 1 2 3 Interrupter and Interrupt Handler The Universe II has both interrupt generation and interrupt handling capability 1 2 3 1 Interrupter The Universe II Inte
201. ed for non BLT MBLT transfers Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 2 VMEbus Interface gt Universe Il as VMEbus Slave 35 2 4 3 1 Without prefetching block read transactions from a VMEbus master are handled by the VMEbus Slave Channel as coupled reads This means that each data phase of the block transfer is translated to a single data beat transaction on the PCI bus In addition only the amount of data requested during the relevant data phase is fetched from the PCI bus For example a D16 block read transaction with 32 data phases on the VMEbus maps to 32 PCI bus transactions where each PCI bus transaction has only two byte lanes enabled The VMEbus lies idle during the arbitration time required for each PCI bus transaction resulting in a performance degradation With prefetching enabled the VMEbus Slave Channel uses a 64 entry deep RDFIFO to provide read data to the VMEbus with minimum latency The RDFIFO is 64 bit with additional bits for control information If a VMEbus slave image is programmed for prefetching see VME Slave Image Programming on page 67 then a block read access to that image causes the VMEbus Slave Channel to generate aligned burst read transactions on the PCI bus the size of the burst read transactions is determined by the setting of the aligned burst size PABS in the MAST_CTL register These PCI burst read transaction are queued in the RDFIFO and the dat
202. ee fs 31 24 ACFAIL SYSFAIL m pcre ow 3 sem swmmemmmer 0 mop m p mum pennen m p 8 3 sur messes aw me wm qnmeneweawsas Tm um remeron me om qmemmnemm 0000 om m qo Integrated Device Technology Universe Il User Manual www idt com May 12 2010 248 12 Registers gt Register Description 12 3 60 VMEbus Interrupt Enable Register VINT_EN This register enables the various sources of VMEbus interrupts SW_INT can be enabled with the VME64AUTO power up option Register name VINT_EN Register offset 0x310 SW INT7 VME Software 7 Interrupt Mask 0 VME Software 7 Interrupt masked 1 VME Software 7 Interrupt enabled A zero to one transition will cause a VME level 7 interrupt to be generated Subsequent zeroing of this bit will cause the interrupt to be masked but will not clear the VME Software 7 Interrupt Status bit SW_INT6 VME Software 6 Interrupt Mask 0 VME Software 6 Interrupt masked 1 VME Software 6 Interrupt enabled A zero to one transition will cause a VME level 6 interrupt to be generated Subsequent zeroing of this bit will cause the interrupt to be masked but will not clear the VME Software 6 Interrupt Status bit SW_INT5 VME Software 5 Interrupt Mask 0 VME Software 5 Interrupt masked 1 VME Software 5 Interrupt enabled A zero to one transition will cause a VME level 5 interrupt to be generated Subsequent zeroing of this bit will cause the interrupt to be masked but will
203. egister Description 12 3 41 PCI Target Image 6 Control Register LSI6_CTL In the PCI Target Image Control register setting the VCT bit will only have effect if the VAS bits are programmed for A24 or A32 space and the VDW bits are programmed for 8 bit 16 bit or 32 bit If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64 bit the Universe II may perform MBLT transfers independent of the state of the VCT bit The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I O Space forcing all transactions through this image to be coupled Register name LSI6_CTL Register offset 0x1C8 c mqspe spes De pem me emp m Reserved Image Enable 0 Disable 1 Enable Posted Write Enable 0 Disable 1 Enable VMEbus Maximum Datawidth 00 8 bit data width 01 16 bit data width 10 32 bit data width 11 64 bit data width VMEbus Address Space 000 A16 001 A24 010 A32 011 Reserved 100 Reserved 101 CR CSR 110 User1 111 User2 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 223 Program Data AM Code 0 Data 1 Program SUPER Supervisor User AM Code 0 Non Privileged 1 Supervisor VMEbus Cycle Type 0 no BLTs on VMEbus PCI Bus Memory Space 0 PCI Bus Memory Space 1 PCI Bus I O Space Bd 1 BLTs on VMEbus Integrated Device Technology Universe II User Manual www idt com May 12 2010 224 12 Registers
204. ellaneous Control Register MISC CTL on page 273 The Universe II monitors IACK instead of IACKIN when it is configured as SYSCON This permits it to operate as SYSCON in a VMEbus chassis slot other than slot 1 provided there are only empty slots to its left The slot with SYSCON in it becomes a virtual slot 1 VMEbus Register Access at Power up The Universe II provides a VMEbus slave image that allows access to all Universe II registers The base address for the slave image is programmed through the VMEbus Register Access Image Base Address Register VRAI BS on page 304 At power up the Universe II can program the VRAI BS and VMEbus Register Access Image Control Register VRAI CTL on page 303 registers with information specifying the Universe II Control Status UCSR register slave image see Power Up Options on page 135 Register access at power up is used in systems where the Universe II s card has no CPU or where register access for that card needs to be independent of the local CPU Integrated Device Technology Universe Il User Manual www idt com May 12 2010 42 2 6 2 6 1 2 VMEbus Interface gt Automatic Slot Identification Automatic Slot Identification The Universe II supports two types of Auto ID functionality One type uses the Auto Slot ID technique as described in the VME64 Specification The other type uses a proprietary method developed by DY4 Systems and implemented in the IDT SC V64 and th
205. er Linked list Mode Unlike direct mode in which the DMA performs a single block of data at a time linked list mode allows the DMA to transfer a series of non contiguous blocks of data without software intervention Each entry in the linked list is described by a command packet which parallels the DMA register layout The data structure for each command packet is the same see Figure 16 below and contains all the necessary information to program the DMA address and control registers It could be described in software as a record of eight 32 bit data elements Four of the elements represent the four core registers required to define a DMA transfer DCTL DTBC DVA and DLA A fifth element represents the DCPP register which points to the next command packet in the list The least two significant bits of the DCPP element the PROCESSED and NULL bits provide status and control information for linked list processing The PROCESSED bit indicates whether a command packet has been processed or not When the DMA processes the command packet and has successfully completed all transfers described by this packet it sets the PROCESSED bit to 1 before reading in the next command packet in the list The PROCESSED bit must be initially set for 0 This bit when set to 1 indicates that this command packet has been disposed of by the DMA and its memory can be de allocated or reused for another transfer description Universe Il User Manual Integrated Device Tec
206. er Phase the Universe II latches the PCI command byte enable address and in the case of a write data Regardless of the state of FRAME the Universe II retries the master and then performs the transaction on the VMEbus The Universe II continues to signal Target Retry to the external PCI master until the transfer completes on the VMEbus If the transfer completes normally on the VMEbus then in the case of a read the data is transmitted to the PCI bus master If a data phase of a coupled transfer requires packing or unpacking on the VMEbus acknowledgment of the transfer is not given to the PCI bus master until all data has been packed or unpacked on the VMEbus Successful termination is signalled on the PCI bus the data beat is acknowledged with a Target Disconnect forcing all multi beat transfers into single beat At this point the Universe II enters the Coupled Wait Phase If a bus error is signalled on the VMEbus or an error occurs during packing or unpacking then the transaction is terminated on the PCI bus with Target Abort For more information refer to Data Transfer on page 57 3 4 3 2 Coupled Wait Phase The Coupled Wait Phase is entered after the successful completion of a Coupled Data Transfer phase The Coupled Wait Phase allows consecutive coupled transactions to occur without releasing the VMEbus If a new coupled transaction is attempted while the Universe II is in the Coupled Wait Phase the Universe II moves direct
207. erface 367 E 2 1 1 E 2 2 E 2 3 Should the designer wish to put any further circuitry between the Universe II and the VMEbus that circuitry must meet the same timing requirements as the transceivers in order for the combined circuit to remain compliant with the VME64 specification Pull down resistors The Universe II has internal pull down resistors which are used for its default power up option state Note that REQ64_ has an internal pull up These internal pull down resistors ranging from 25kQ 500kQ are designed to sink between 10u A 2004 A F series buffers however can source up to 650 uA of current worst case This sourced current has the ability to override the internal power up resistors on the Universe II This may cause the Universe II to incorrectly sample a logic 1 on the pins To counteract this potential problem assuming a worst case scenario of a 650 pA current IDT recommends connecting a 1 K resistor to ground in parallel with the internal pull down resistor IDT recommends that any pins controlling the power up options which are critical to the application at power up be connected to ground with a pull down resistor as described above If these options are not critical and if it is possible to reprogram these options after reset additional resistors need not be added Direction control When the Universe II is driving VMEbus lines it drives the direction control signals high i e VA DIR VAM DIR VAS
208. errupt Status Register LINT_STAT on page 244 shows the status of all sources of PCI interrupts independent of whether that source has been enabled This implies that an interrupt handling routine must mask out those bits in the register that do not correspond to enabled sources on the active LINT_ pin Except for SYSFAIL and ACFAIL all sources of PCI interrupts are edge sensitive Enabling of the ACFAIL or SYSFAIL sources ACFAIL and SYSFAIL bits in the LINT EN register causes the status bit and mapped PCI interrupt pin to assert synchronously with the assertion of the ACFAIL or SYSFAIL source The PCI interrupt is negated once the ACFAIL or SYSFAIL status bit is cleared The status bit cannot be cleared if the source is still active Therefore if SYSFAIL or ACFAIL is still asserted while the interrupt is enabled the interrupt will continue to be asserted Both of these sources are synchronized and filtered with multiple edges of the PCI clock at their inputs Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 7 Interrupt Generation and Handling gt Interrupt Generation 113 7 2 2 All other sources of PCI interrupts are edge sensitive The VMEbus source for PCI interrupts actually comes out of the VMEbus Interrupt Handler block and reflects acquisition of a VMEbus STATUS ID Therefore even though VMEbus interrupts externally are level sensitive as required by the VMEbus Specification they are internall
209. erse II User Manual www idt com May 12 2010 214 12 Registers gt Register Description 12 3 34 PCI Target Image 4 Base Address Register LSI4_BS The base address specifies the lowest address in the address range that will be decoded Register name LSI4_BS Register offset 0x1A4 Ea rages esses Es 23 16 BS Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 215 12 3 35 PCI Target Image 4 Bound Address Register LSI4_BD The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register If the bound address is 0 then the addresses decoded are those greater than or equal to the base address The bound address for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution PCI Target Images 1 2 3 5 6 and 7 have a 64Kbyte resolution Register name LSI4_BD Register offset 0x1A8 SSeS ewes NUS 23 16 Integrated Device Technology Universe II User Manual www idt com May 12 2010 216 12 Registers gt Register Description 12 3 36 PCI Target Image 4 Translation Offset LSI4_TO Address bits 31 12 generated on the VMEbus in response to an image decode are a two s complement addition of address bits 31 12 on the PCI Bus and bits 31 12 of the image s translation offset Register name LSI4_TO Register offset OX1AC Saas DNO ERREUR RC ERR POS Universe Il
210. est of each 16 Mbyte region is mapped to A24 space The user can use the PGM SUPER and VDW fields to specify the AM code and the maximum port size for each region The PGM field is ignored for the portion of each region mapped to A16 space No block transfer AM codes are generated Register name SLSI Register offset 0x188 Pea es NCC NONE EN Image Enable R W All 0 Disable 1 Enable Posted Write Enable R W All 0 Disable 1 Enable VMEbus Maximum Datawidth Each of the four bits specifies a data width for the corresponding 16 MByte region Low order bits correspond to the lower address regions 0 16 bit 1 32 bit Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt R SUPER egister Description 209 Program Data AM Code Each of the four bits specifies Program Data AM code for the corresponding 16 MByte region Low order bits correspond to the lower address regions 0 Data 1 Program Supervisor User AM Code Each of the four bits specifies Supervisor User AM code for the corresponding 16 MByte region Low order bits correspond to the lower address regions 0 Non Privileged 1 Supervisor Base Address Specifies a 64 MByte aligned base address for this 64 MByte image PCI Bus Address Space 0 PCI Bus Memory Space 1 PCI Bus I O Space Integrated Device Technology Universe II User Manual www idt com May 12 2010 210 12 Registers gt Register Descript
211. et PWR VME 09 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 319 12 3 117 VMEbus Slave Image 6 Control VSI6_CTL This register provides the general VMEbus and PCI controls for this slave image Note that only transactions destined for PCI Memory space are decoupled the posted write RXFIFO generates on Memory space transactions on the PCI Bus In order for a VMEbus slave image to respond to an incoming cycle the BM bit in the PCI CSR register must be enabled The state of PWEN and PREN are ignored if LAS is not programmed memory space Register name VSI6_CTL Register offset OxFB8 15 08 Reserved Image Enable PWR VME 0 Disable 1 Enable Posted Write Enable PWR VME 0 Disable 1 Enable R W PWR VME 0 Disable 1 Enable Program Data AM Code R W PWR VME 11 00 Reserved 01 Data 10 Program 11 Both Supervisor User AM Code PWR VME 00 Reserved Integrated Device Technology Universe II User Manual www idt com May 12 2010 Prefetch Read Enable 01 Non Privileged 10 Supervisor 11 Both 320 LD64EN LLRMW 12 Registers Register Description VMEbus Address Space 000 Reserved 001 A24 010 A32 011 Reserved 100 Reserved 101 Reserved 110 User1 111 User2 Enable 64 bit PCI Bus Transactions 0 Disable 1 Enable Enable PCI Bus Lock of VMEbus RMW 0 Disable 1 Enable PCI Bus Address Space 00zPCI Bus Memory Space 01 PCI Bus I O Sp
212. et by value Target IO Enable R W PWR VME This bitis 1 0 Disable after reset if the 1 Enable VMEbus Address 13 12 equals 10 during power on reset This bit is reloaded by all Integrated Device Technology Universe II User Manual www idt com May 12 2010 176 12 Registers gt Register Description 12 3 3 PCI Configuration Class Register PCI CLASS Register name PCI CLASS Register offset 0x08 Reset Description Type Reset by value 31 24 Base Class Code All 0x06 The Universe II is defined as a PCI bridge device 23 16 Sub Class Code All 0x80 The Universe II sub class is other bridge device 15 08 Programming Interface All 0x00 The Universe II does not have a standardized register level programming interface Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 177 12 3 4 PCI Configuration Miscellaneous 0 Register PCI MISCO The Universe II is not a multi function device Register name PCI MISCO Register offset 0x0C ZARA SSE EASA Reserved Reset Description Type Reset by value BISTC The Universe Il is not BIST Capable OR fo 30 SBIST Start BIST All 0x0 The Universe II is not BIST capable ll 0x0 27 24 CCODE Completion Code A The Universe II is not BIST capable 23 MFUNCT Multifunction Device All 0x0 The Universe II is not a multi function device 0 No 1 Yes 22 16 LAYOUT Configuration Space Layout All
213. evel sensitive and if enabled in the VMEbus Interrupt Enable Register VINT EN on page 248 immediately generate an interrupt to the VMEbus It is expected that when a VMEbus interrupt handler receives the Universe II s STATUS ID from the Universe II the interrupt handler clears the VMEbus interrupt by first clearing the source of the interrupt on the PCI bus and then clearing the VMEbus interrupt by writing a 1 to the appropriate bit in the VMEbus Interrupt Status Register VINT_STAT on page 251 Note that since PCI interrupts are level sensitive if an attempt is made to clear the VMEbus interrupt while the LINT_ pin is still asserted the VMEbus interrupt remains asserted This causes a second interrupt to be generated to the VMEbus For this reason a VMEbus interrupt handler should clear the source of the PCI interrupt before clearing the VMEbus interrupt VMEbus Interrupt Handling As a VMEbus interrupt handler the Universe II can monitor any or all of the VMEbus interrupt levels It can also monitor SYSFAIL and ACFAIL although IACK cycles are not generated for these inputs Each interrupt is enabled through the PCI Interrupt Enable Register LINT EN on page 242 Once enabled assertion of any of the VMEbus interrupt levels IRQ 7 1 causes the internal interrupt handler circuitry to request ownership of the Universe II s VMEbus Master Interface on the level programmed in the Master Control Register MAST CTL on p
214. even parity for C BE 3 0 and AD 31 0 When the Universe II is powered up in a 64 bit PCI environment it uses PAR64 in the same way as PAR except for AD 63 32 and C BE 7 4 The PERESP bit in the PCI Configuration Space Control and Status Register PCI_CSR on page 172 determines whether or not the Universe II responds to parity errors as PCI master Data parity errors are reported through the assertion of PERR_ if the PERESP bit is set Regardless of the setting of these two bits the D_PE Detected Parity Error bit in the PCI_CS register is set if the Universe II encounters a parity error as a master The DP_D Data Parity Detected bit in the same register is only set if parity checking is enabled through the PERESP bit and the Universe II detects a parity error while it is PCI master i e it asserts PERR during a read transaction or receives PERR_ during a write No interrupts are generated by the Universe II in response to parity errors reported during a transaction Parity errors are reported by the Universe II through assertion of PERR_ and by setting the appropriate bits in the PCI_CS register If PERR_ is asserted to the Universe II while it is PCI master the only action it takes is to set the DP D The Universe II continues with a transaction independent of any parity errors reported during the transaction As a master the Universe II does not monitor SERR_ It is expected that a central resource on the PCI bus monitors SE
215. evice Technology May 12 2010 www idt com 12 Registers gt Register Description 219 12 3 38 PCI Target Image 5 Base Address Register LSI5 BS The base address specifies the lowest address in the address range that will be decoded Register name LSI5 BS Register offset 0x1B8 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 220 12 Registers gt Register Description 12 3 39 PCI Target Image 5 Bound Address Register LSI5_BD The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register If the bound address is 0 then the addresses decoded are those greater than or equal to the base address Register name LSI5_BD Register offset 0x1BC The bound address for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution PCI Target Images 1 2 3 5 6 and 7 have a 64Kbyte resolution Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 221 12 3 40 PCI Target Image 5 Translation Offset LSI5 TO Address bits 31 16 generated on the VMEbus in response to an image decode are a two s complement addition of address bits 31 16 on the PCI Bus and bits 31 16 of the image s translation offset Register name LSI5 TO Register offset 0x1C0 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 222 12 Registers gt R
216. f a PCI interrupt A VMEbus error during the acquisition of the STATUS ID vector sets the ERR bit which means the STATUS ID field may not contain a valid vector Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 257 12 3 66 VIRQ2 STATUS ID Register V2_STATID The Vx_STATID registers are read only registers that hold the 8 bit VMEbus STATUS ID that is acquired when the Universe II performs a IACK cycle for a given interrupt level Register name V2_STATID Register offset 0x328 EASES ESE EAE AEA 31 24 Reserved 23 16 Reserved 15 08 Reserved 07 00 STATID 7 0 Error Status Bit 0 STATUS ID was acquired without bus error 1 bus error occurred during acquisition of the STATUS ID STATID 7 0 STATUS ID acquired during IACK cycle for level 1 VMEbus ey eT es interrupt The Universe II is enabled as the interrupt handler for a given interrupt level via the VIRQx bits of the LINT_EN register Once a vector for a given level is acquired the Universe II does not perform a subsequent interrupt acknowledge cycle at that level until the corresponding VIRQx bit in the LINT_STAT register is cleared The acquisition of a level x STATUS ID by the Universe II updates the STATUS ID field of the corresponding Vx_STATID register and generation of a PCI interrupt A VMEbus error during the acquisition of the STATUS ID vector sets the ERR bit which means the STATUS ID field may
217. f interrupts and these are all routed to this single interrupt Each of these six sources can be individually enabled and are listed in Table 15 Setting the enable bit enables the corresponding interrupt source Table 15 DMA Interrupt Sources and Enable Bits Interrupt Source Enable Bit Stop Request INT STOP Halt Request INT HALT PCI Target Abort or Master Abort Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 6 DMA Controller gt DMA Channel Interactions with Other Channels 105 6 8 6 8 1 Once an enabled DMA interrupt has occurred the corresponding DMA bit in the PCI Interrupt Status Register LINT_STAT on page 244 and VMEbus Interrupt Status Register VINT_STAT on page 251 are set regardless of whether the LINT_EN or VINT_EN enable bits have been set Each one must be cleared independently Clearing either the LINT_STAT or VINT_STAT registers does not clear the other See Interrupt Generation and Handling on page 109 DMA Channel Interactions with Other Channels This section describes the impact that the PCI Bus Target Channel and the VMEbus Slave Channel can have on the DMA Channel DMA Controller Reads and writes through the DMA Controller can occur independently of the other channels i The Universe II does not apply PCI 2 1 Specification transaction ordering requirements to the ADOH cycles and RMW cycles through the VMEbus Slave Channel do impact on t
218. ffects The VMEbus Master Interface becomes inactive PCI Target Channel coupled accesses are retried The PCI Target Channel Posted Writes FIFO continues to accept transactions but eventually fills and no further posted writes are accepted The DMA FIFO eventually empties or fills and no further DMA activity takes place on the PCI bus The Universe II VMEbus Master does not service interrupts while in BI Mode e The Universe II does not respond as a VMEbus slave Except for accesses to the register image and CR CSR image e The Universe II does not respond to any interrupt it had outstanding All VMEbus outputs from the Universe II are tri stated so that the Universe II are not driving any VMEbus signals The only exception to this is the IACK and BG daisy chains which must remain in operation as before There are four ways to cause the Universe II to enter BI Mode The Universe II is put into BI Mode for the following reasons If the BI Mode power up option is selected See Power Up Options on page 135 and Table 22 on page 135 e When SYSRST or RST is asserted any time after the Universe II has been powered up in BI Mode e When VRIRQ 1 is asserted provided that the ENGBI bit in the Miscellaneous Control Register MISC CTL on page 273 has been set e When the BI bit in the MISC CTL register is set Either of the following actions remove the Universe II from BI Mode e Power up the Universe II with the B
219. field in the PCI Interrupt Map Register LINT MAP1 on page 247 determines which interrupt line is asserted on the PCI interface 1 The term enable is more meaningful with respect to the other fields in this register i e excluding the software interrupts Writing to the software interrupt fields of this register does not enable an interrupt it triggers an interrupt Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 7 Interrupt Generation and Handling gt Interrupt Handling 121 7 3 3 2 Termination of Software Interrupts Any software interrupt can be cleared by clearing the respective bit in the VMEbus Interrupt Enable Register VINT EN on page 248 or PCI Interrupt Enable Register LINT EN on page 242 However this method is not recommend for VME bus software interrupts because it can result in a false interrupts on that bus These false interrupts are caused because the Universe II does not respond to the interrupt handler s IACK cycle and the handler is left without a STATUS ID for the interrupt Since the software interrupt is edge sensitive the software interrupt bit in the VINT EN or LINT EN register should be cleared any time between the last interrupt finishing and the generation of another interrupt It is recommended that the appropriate interrupt handler clear this bit once it has completed its operations Alternatively the process generating a software interrupt could
220. gister LM CTL on page 300 LM CTL Location Monitor Base Address Register LM BS on page 302 LM BS Reserved VMEbus Register Access Image Control Register VRAI CTL on VRAI CTL page 303 VMEbus Register Access Image Base Address Register VRAI BS on VRAI BS page 304 Reserved OxF80 VMEbus CSR Control Register VCSR_CTL on page 305 VCSR CTL OxF84 VMEbus CSR Translation Offset VCSR TO on page 306 VCSR TO OxF88 VMEbus AM Code Error Log V AMERR on page 307 V AMERR OxF8C VMEbus Address Error Log VAERR on page 308 VAERR OxF90 VMEbus Slave Image 4 Control VSI4_CTL on page 309r VSI4 CTL OxF94 VMEbus Slave Image 4 Base Address Register VSI4 BS on page 311 VSI4 BS OxF98 VMEbus Slave Image 4 Bound Address Register VS8I4 BD on VSI4 BD page 312 OxF9C VMEbus Slave Image 4 Translation Offset VSl4 TO on page 313 VSI4 TO OxFA4 VMEbus Slave Image 5 Control VSI5_ CTL on page 314 VSI5 CTL OxFA8 VMEbus Slave Image 5 Base Address Register VSI5_BS on VSI5 BS page 316 OxFAC VMEbus Slave Image 5 Bound Address Register VSI5 BD on VSI5_BD page 317 OxFBO VMEbus Slave Image 5 Translation Offset VSI5 TO on page 318 VSI5 TO OxFB8 VMEbus Slave Image 6 Control VSI6_CTL on page 319 VSI6_CTL OxFBC VMEbus Slave Image 6 Base Address Register VSl6 BS on VSI6 BS page 321 OxFCO VMEbus Slave Image 6 Bound Address Register VSIl6 BD on VSI6 BD page 322 In
221. gister name USER_AM Register offset 0x40C USER1AM 3 0 User AM Code 1 RW o oa 0000 USER2AM 3 0 User AM Code 2 RW boc 0000 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 277 12 3 84 Universe Il Specific Register U2SPEC Register name U2SPEC Register offset OXAFC 9m 24 Universe Reserved 16 Universe Reserved E 08 Universe DSO DS1 DTKFLTR Reserved MASt11 READt27 Reserved re eee ony RS Description Type Reset by value DSO DS1 Data Strobe Filtering R W This filter eliminates the noise on DS1 and DSO 0 Disable 1 Enable AS Address Strobe Filtering This filter eliminates the noise on AS 0 Disable 1 Enable DTKFLTR VME DTACK Inactive Filter 0 Slower but better filter 1 Faster but poorer filter MASt11 VME Master Parameter t11 Control DS high time during BLT s and MBLT s 0 Default 1 Faster READt27 VME Master Parameter t27 Control Delay of DS negation after read 00 Default 01 Faster 10 No Delay POSt28 VME Slave Parameter t28 Control Time of DS to DTACK for posted write 0 Default 1 Faster Integrated Device Technology Universe Il User Manual www idt com May 12 2010 278 12 Registers gt Register Description Reset Description Type Reset by value PREt28 VME Slave Parameter t28 Control Time of DS to DTACK for prefetch read 0 Default 1 Faster Universe Il User Manual Integrated Device Techno
222. gradation of overall performance The Universe II s U2SPEC register enables users to compensate for the latencies which are inherent to their VMEbus system designs Through the use of this register users can reduce the inherent delay associated with five key VMEbus timing parameters Use of the U2SPEC register may result in violation of the VME64 Specification Adjustable VME Timing Parameters VME DTACK Inactive Filter DTKFLTR In order to overcome the DTACK noise typical of most VME systems the Universe II quadruple samples this signal with the 64 MHz clock The extra sampling is a precaution that results in decreased performance Users who believe their systems to have little noise on their DTACK lines can elect to filter this signal less and therefore increase their Universe II response time VME Master Parameter t11 Control MASt11 According to the VME64 Specification a VMEbus master must not drive DSO low until both it and DS1 have been simultaneously high for a minimum of 40 ns The MASt11 parameter in the U2SPEC register however allows DSO to be driven low in less than 40 ns VME Master Parameter t27 Control READt27 During read cycles the VMEbus master must guarantee the data lines are valid within 25 ns after DTACK is asserted The master must not latch the data and terminate the cycle for a minimum of 25 ns after the falling edge of DTACK The READt27 parameter in the U2SPEC register supports faster cycle te
223. gt Register Description 12 3 42 PCI Target Image 6 Base Address Register LSI6_BS The base address specifies the lowest address in the address range that will be decoded Register name LSI6 BS Register offset 0x1CC Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 225 12 3 43 PCI Target Image 6 Bound Address Register LSI6_ BD The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register If the bound address is 0 then the addresses decoded are those greater than or equal to the base address Register name LSI6_BD Register offset Ox1DO The bound address for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution PCI Target Images 1 2 3 5 6 and 7 have a 64Kbyte resolution Integrated Device Technology Universe Il User Manual www idt com May 12 2010 226 12 Registers gt Register Description 12 3 44 PCI Target Image 6 Translation Offset LSI6_TO Address bits 31 16 generated on the VMEbus in response to an image decode are a two s complement addition of address bits 31 16 on the PCI Bus and bits 31 16 of the image s translation offset Register name LSI6_TO Register offset 0x1D4 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 227 12 3 45 PCI Target Image 7 Control Reg
224. gy Universe Il User Manual www idt com May 12 2010 163 12 Registers This appendix discusses the following topics e Overview on page 163 e Register Map on page 164 e Register Description on page 171 12 1 Overview The Universe II Control and Status Registers facilitate host system configuration and allow the user to control Universe II operational characteristics The registers are divided into three groups PCI Configuration Space e VMEbus Configuration and Status Registers e Universe II Device Specific Status Registers Universe II registers have little endian byte ordering Figure 24 below summarizes the supported register access mechanisms Figure 24 UCSR Access Mechanisms VMEbus Configuration and Status Registers VCSR UNIVERSE DEVICE SPECIFIC REGISTERS UCSR Space PCI CONFIGURATION SPACE PCICS Integrated Device Technology Universe Il User Manual www idt com May 12 2010 164 12 Registers gt Register Map Bits listed as reserved must be programmed with a value of 0 Reserved bits always read a value of zero 12 2 Register Map Table 34 lists the Universe II registers by address offset Table 34 Universe Il Register Map Offset Register Name 0x000 PCI Configuration Space ID Register PCI ID on page 171 0x004 PCI Configuration Space Control and Status Register PCI CSR on page 172 0x008 PCI Configuration Class Register PCI CLASS on page 176 0
225. h the M ERR bit although the actual number of errors is not given The error log is qualified by the value of the V STAT bit The address of the errored transaction is latched in the VMEbus Address Error Log VAERR on page 308 When the Universe II receives a VMEbus error during a posted write it generates an interrupt on the VMEbus and or PCI bus depending upon whether the VERR and LERR interrupts are enabled see Interrupt Handling on page 116 DTACK signals the successful completion of the transaction Integrated Device Technology Universe Il User Manual www idt com May 12 2010 32 2 4 2 VMEbus Interface gt Universe Il as VMEbus Slave Universe Il as VMEbus Slave This section describes the VMEbus Slave Channel and other aspects of the Universe II as VMEbus slave The Universe II becomes VMEbus slave when one of its eight programmed slave images or register images are accessed by a VMEbus master Depending upon the programming of the slave image different possible transaction types can result see VME Slave Image Programming on page 67 The Universe II cannot reflect a cycle on the VMEbus and access itself For reads the transaction can be coupled or prefetched Write transactions can be coupled or posted The type of read or write transaction allowed by the slave image depends on the programming of that particular VMEbus slave image see Figure 4 and VME Slave Image Programming on page 67 To ens
226. hat mode There are also three bits that are set in response to error conditions LERR in the case of Target Abort encountered on the PCI bus VERR in the case of a bus error encountered on the VMEbus and P_ERR in the case that the DMA has not been properly programmed the DMA was started with the BM bit in the PCI_CSR register not enabled or the DLA and DVA registers were not 64 bit aligned see Source and Destination Addresses on page 86 Before the DMA can be restarted each of these status bits must be cleared Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 6 DMA Controller gt Direct Mode Operation 93 When the DMA terminates an interrupt may be generated to VMEbus or PCI bus The user has control over which DMA termination conditions cause the interrupt through the INT_STOP INT_HALT INT_DONE INT_LERR INT_VERR and INT_P_ERR bits in the DGCS register 6 3 Direct Mode Operation When operated in direct mode the Universe II DMA is set through manual register programming Once the transfer described by the DVA DLA DTBC and DCTL registers has been completed the DMA sits idle awaiting the next manual programming of the registers Figure 15 describes the steps involved in operating the DMA in direct mode Integrated Device Technology Universe II User Manual www idt com May 12 2010 94 6 DMA Controller gt Direct Mode Operation Figure 15 Direct Mode DMA transfers Step 1 Program
227. he PCI Interrupt Map 1 Register LINT MAPI on page 247 is mapped to a corresponding PCI interrupt line This interrupt could be used by a PCI process to indicate that the software interrupt generated to the VMEbus has been received by the device and acknowledged Like other interrupt sources this interrupt source can be independently enabled through the PCI Interrupt Enable Register LINT EN on page 242 and mapped to a particular LINT pin using the LINT MAPI register A status bit in the LINT STAT register indicates when the interrupt source is active and is used to clear the interrupt once it has been serviced Integrated Device Technology Universe Il User Manual www idt com May 12 2010 122 7 3 3 3 7 3 3 4 7 3 3 5 7 3 3 6 7 Interrupt Generation and Handling gt Interrupt Handling VMEbus Ownership Interrupt The VMEbus ownership interrupt is generated when the Universe II acquires the VMEbus in response to programming of the VOWN bit in the MAST_CTL register Master Control Register MAST_CTL on page 271 This interrupt source can be used to indicate that ownership of the VMEbus is ensured during an exclusive access see VME Lock Cycles Exclusive Access to VMEbus Resources on page 63 The interrupt is cleared by writing a one to the matching bit in the PCI Interrupt Status Register LINT_STAT on page 244 DMA Interrupt The DMA module provides the following possible interrupt sources
228. he DMA Channel Once an external VMEbus master locks the PCI bus the DMA Controller does not perform transfers on the PCI bus until the Universe II is unlocked see VMEbus Lock Commands ADOH Cycles on page 36 When an external VMEbus Master begins a RMW cycle at some point a read cycle appears on the PCI bus During the time between when the read cycle occurs on the PCI bus and when the associated write cycle occurs on the PCI bus no DMA transfers occurs on the PCI bus see VMEbus Read Modify Write Cycles RMW Cycles on page 37 If the PCI Target Channel locks the VMEbus using VOWN no DMA transfers takes place on the VMEbus see Using the VOWN bit on page 64 DMA Error Handling This section describes how the Universe II responds to errors involving the DMA and how the user can recover from them The software source of a DMA error is a protocol and the hardware source of a DMA error is a VMEbus error or PCI bus Target Abort or Master Abort DMA Software Response to Error While the DMA is operating normally the ACT bit in the DMA General Control Status Register DGCS on page 238 Once the DMA has terminated it clears this bit and sets one of six status bits in the same register The DONE bit will be set if the DMA completed all its programmed operations normally If the DMA is interrupted either the STOP or HALT bits are set If an error has occurred one of the remaining three bits LERR VERR or P_ERR is set A
229. he rate at which the VME master is capable of writing it The sustained performance on the PCI bus performing single data beat write transactions to a 32 bit PCI bus is 15 MB s double this for a 64 bit bus When performing 32 byte transactions the sustained performance increases to 106 MB s 120 MB s with 64 byte transactions Again these can be doubled for a 64 bit PCI bus Bear in mind that the PCI bus can only dequeue data as fast as it is being enqueued on the VMEbus Hence as the RXFIFO empties the sustained performance on the PCI will drop down to match the lower performance on the VME side However even with the decreased sustained performance the consumed bandwidth will remain constant no extra wait states are inserted while the Universe II is master of the PCI bus These numbers assume the PCI bus is granted to the Universe II immediately and that the writes are to a zero wait state PCI target capable of accepting the full burst length Figure 27 through Figure 36 show the Universe II responding to non block BLT and MBLT write transactions to a 32 bit PCI bus Even better performance is obtained with PCI bus parking B 3 2 2 Prefetched Read Cycles To minimize its slave response the Universe II generates prefetched reads to the PCI bus in response to BLT and MBLT reads coming in from the VMEbus This option must first be enabled on a per image basis When enabled the Universe II will respond to a block read by performing burst rea
230. he role of SYSCON and sets the SYSCON status bit in the MISC_CTL register In accordance with the VME64 Specification as SYSCON the Universe II has the following functions e A system clock driver An arbitration module e AnIACK Daisy Chain Driver DCD A bus timer System Clock Driver The Universe II provides a 16 MHz SYSCLK signal derived from CLK64 when configured as SYSCON VMEbus Arbiter When the Universe II is SYSCON the Arbitration Module is enabled The Arbitration Module supports the following arbitration modes e Fixed Priority Arbitration Mode PRI e Round Robin Arbitration Mode RRS default setting Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 2 VMEbus Interface gt Automatic Slot Identification 45 2 6 3 3 2 6 3 4 2 6 3 5 2 6 4 2 6 5 These modes are selected with the VARB bit in the Miscellaneous Status Register MISC STAT on page 275 Fixed Priority Arbitration Mode PRI In this mode the order of priority is VRBR_ 3 VRBR 2 VRBR_ 1 and VRBR 0 as defined by the VME64 Specification The Arbitration Module issues a Bus Grant VBGO 3 0 to the highest requesting level If a Bus Request of higher priority than the current bus owner is asserted the Arbitration Module asserts VBCLR until the owner releases the bus VRBBSY is negated Round Robin Arbitration Mode RRS This mode arbitrates all levels in a round robin mode by scanni
231. he top of the list where the high priority command packet has been placed When the GO bit is set after clearing the STOP status bit in the DGCS register the DMA performs the transfers in the order set in the linked list For more details on updating the linked list see Linked list Updating on page 100 DMA transfers continue until the DMA encounters a command packet with the NULL bit set to 1 indicating that the last packet has been reached At this point the DMA stops the DONE bit is set and the ACT flag is cleared As it completes the transfers indicated by each command packet the DMA sets the PROCESSED bit in that command packet before reading in the next command packet and processing its contents Linked list Updating The Universe II provides a mechanism which enables the linked list to be updated with additional linked list entries without halting or stopping the DMA This takes place through the use of a semaphore in the device the UPDATE bit in the DMA Linked List Update Enable Register D_LLUE on page 241 This bit is meant to ensure that the DMA does not read a command packet into the DMA registers while the command packet outside the Universe II is being updated This semaphore does not prevent external masters from updating the DMA registers Adding to a linked list begins by writing a 1 to the UPDATE bit The DMA checks this bit before proceeding to the next command packet If the UPDATE bit is 0 then the DMA lock
232. his register implements the Bit Clear Register as defined in the VME64 Specification The RESET bit must be written to only from the VMEbus Register name VCSR_CLR Register offset OxFF4 BEER EOS ERN ee ee ee 23 16 Reserved 15 08 Reserved 07 00 Reserved Board Reset R W PWR VME Reads OZLRST not asserted 1 LRST_ asserted Writes 0 no effect 1 negate LRST_ SYSFAIL VMEbus SYSFAIL R W Power up Reads Option 0 VXSYSFAIL not asserted 1 VXSYSFAIL asserted Writes 0 no effect 1 negate VXSYSFAIL Board Fail PWR VME 0 Board has not failed Integrated Device Technology Universe II User Manual www idt com May 12 2010 330 12 Registers gt Register Description 12 3 126 VMEbus CSR Bit Set Register VCSR_SET This register implements the Bit Set Register as defined in the VME64 Specification The RESET bit must be written to only from the VMEbus Writing 1 to the RESET bit asserts LRST_ The PCI reset remains asserted until a 1 is written to the RESET bit of the VCSR CLR register Register name VCSR SET Register offset OXFF8 i See Eee NENNEN 23 16 Reserved 15 08 Reserved 07 00 Reserved Board Reset PWR VME Reads 0 LRST_ not asserted 1 LRST_ asserted Writes 0 no effect 1 assert LRST_ SYSFAIL VMEbus SYSFAIL Power up Reads Option 0 VXSYSFAIL not asserted 1 VXSYSFAIL asserted Writes O no effect 1 assert VXSYSFAIL Board Fail PWR VME 0 Board has not failed Universe Il User Manual In
233. hnology May 12 2010 www idt com 6 DMA Controller gt Linked list Mode 97 Figure 16 Command Packet Structure and Linked List Operation First Command Packet in Linked List Register information copied to DMA Control and Address Registers DcPPRegister r reserved uer cru eed proesesed bi Linked List Start Address in Command Packet Pointer Register DCPP points after command packet is processed to next command the bit is set to 1 packet Second Command Packet N null bit in Linked List in Linked List scremegser 7H N 0 for another command packet Last Command Packet in Linked List pore resister F eae ee N 1 for last command packet The NULL bit indicates the termination of the entire linked list If the NULL bit is set to 0 the DMA processes the next command packet pointed to by the command packet pointer If the NULL bit is set to then the address in the command packet pointer is considered invalid and the DMA stops at the completion of the transfer described by the current command packet Figure 17 outlines the steps in programming the DMA for linked list operation Integrated Device Technology Universe Il User Manual www idt com May 12 2010 98 6 DMA Controller gt Linked list Mode Figure 17 DMA Linked List Operation Step 1 Program DGCS with tenure and interrupt requirements Step 2 Set up linked list in PCI memory space Step 3 Clear DTBC register prog
234. icate that is ready to complete a current data phase LCLK Input PCI Clock Provides timing for all transactions on the PCI bus PCI signals are sampled on the rising edge of CLK and all timing parameters are defined relative to this signal The PCI clock frequency of the Universe Il must be between 25 and 33MHz Lower frequencies result in invalid VME timing LOCK _ Bidirectional Lock Used by the Universe II to indicate an exclusive operation with a PCI device While the Universe II drives LOCK other PCI masters are excluded from accessing that particular PCI device When the Universe Il samples LOCK it can be excluded from a particular PCI device LRST Output Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 10 Signals and Pinout gt PCI Bus Signals 149 Table 27 PCI Bus Signals PCI Reset Output Used to reset PCI resources PAR Bidirectional Parity Parity is even across AD 31 0 and C BE 3 0 the number of 1s summed across these lines and PAR equal an even number PAR64 Bidirectional Parity Upper DWORD Parity is even across AD 63 32 and C BE 7 4 the number of 1s summed across these lines and PAR equal an even number PERR Bidirectional Parity Error Reports parity errors during all transactions The Universe Il drives PERR high within two clocks of receiving a parity error on incoming data
235. idt com 12 Registers gt Register Description 311 12 3 110 VMEbus Slave Image 4 Base Address Register VSI4_BS The base address specifies the lowest address in the address range that is decoded This image has a 4 Kbyte resolution Register name VSI4_BS Register offset OXF94 07 00 Reserved BS 31 12 Base Address PWR VME row Integrated Device Technology Universe Il User Manual www idt com May 12 2010 312 12 Registers gt Register Description 12 3 111 VMEbus Slave Image 4 Bound Address Register VSI4_BD The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register If the bound register is 0 then the addresses decoded are those greater than or equal to the base address This image has 4 Kbyte resolution Register name VSI4_BD Register offset OxF98 BD 31 12 Bound Address PWR VME EE Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 313 12 3 112 VMEbus Slave Image 4 Translation Offset VSI4_TO The translation offset is added to the source address that is decoded and this new address becomes the destination address If a negative offset is desired the offset must be expressed as a two s complement This image has 4 Kbyte resolution Register name VSI4_TO Register offset OxF9C O 31 24 23 16 TO 31 12 Translation Offset PWR VME po
236. if the start address was 0x2000 the DMA would generate three data beats with all byte lanes enabled and a fourth with three byte lanes enabled The DTBC register is not updated while the DMA is active DMA is indicated as active by the ACT bit in the DGCS register At the end of a transfer it contains 0 However if stopped by the user through the STOP bit in the DGCS register or the DMA encounters an error the DTBC register contains the number of bytes remaining to transfer on the source side see DMA Error Handling on page 105 Starting the DMA while DTBC is 0 results in one of two situations If the CHAIN bit in the DMA General Control Status Register DGCS on page 238 is not set the DMA does not start it performs no action If the CHAIN bit is set then the DMA loads the DMA registers with the contents of the command packet pointed to by the DMA Command Packet Pointer DCPP on page 237 and starts the transfers described by that packet Note that the DCPP 31 5 field of the DCPP register implies that the command packets be 32 byte aligned bits 4 0 of this register must be 0 6 2 4 Transfer Data Width The VMEbus and PCI bus data widths are determined by three fields in the DMA Transfer Control Register DCTL on page 232 These fields affect the speed of the transfer They should be set for the maximum allowable width that the destination device is capable of accepting On the VMEbus the DMA supports the following data
237. ing types of PCI terminations 1 Master abort The PCI bus master negates FRAME when no target responds DEVSEL_ not asserted after six clock cycles 2 Target disconnect A termination is requested by the target STOP is asserted because it is unable to respond within the latency requirements of the PCI specification or it requires a new address phase e Target disconnect with data The transaction is terminated after data is transferred The Universe II de asserts REQ for at least two clock cycles if it receives STOP from the PCI target e Target disconnect without data The transaction is terminated before data is transferred The Universe II de asserts REQ for at least two clock cycles if it receives STOP from the PCI target 3 Target retry Termination is requested STOP is asserted by the target because it cannot currently process the transaction Retry means that the transaction is terminated after the address phase without any data transfer 4 Target abort Is a modified version of target disconnect where the target requests a termination asserts STOP of a transaction which it will never be able to respond to or during which a fatal error occurred Although there may be a fatal error for the initiating application the transaction completes gracefully ensuring normal PCI operation for other PCI resources Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 3 PCI Interface gt Univers
238. ings DC Supply Voltage VSS to VDD 0 3 to 7 0 V Storage Temperature Tstg 40 C to 125 C Stresses beyond those listed above may cause permanent damage to the devices N These are stress ratings only and functional operation of the devices at these or any other conditions beyond those indicated in the operational sections of this document is not implied Exposure to maximum rating conditions for extended periods may affect device reliability 11 3 Power Dissipation Table 33 Power Dissipation Parameter IDLE Power Dissipation 1 50W Typical Power Dissipation 32 bit PCI 2 00W Power Dissipation 64 bit PCI 2 20W Power Dissipation 32 bit PCI 2 70W Power Dissipation 64 bit PCI 3 20W Integrated Device Technology Universe Il User Manual www idt com May 12 2010 162 11 Electrical Characteristics gt Power Sequencing 11 4 Power Sequencing When designing with the Universe II device care must be taken when powering the device to ensure proper operation During power up no signals must be applied to any Universe II signal pins prior to stable power being applied to the device In a mixed 3 3V and 5V design IDT recommends that 5V power be stable prior to other devices coming out reset If other devices come out of reset before the 5V power is stable make certain that no signals are driven to the Universe II signal pins including possible signals from the VME backplane Integrated Device Technolo
239. ins the transfer attributes If read transactions are occurring on the VMEbus then setting a stop request can be affected by the VOFF timer If the STOP_REQ bit is set while the DMA is lying idle waiting for VOFF to expire before re starting reads then the request remains pending until the VOFF timer has expired and the bus has been granted HALT HALT provides a mechanism to interrupt the DMA at command packet boundaries during a linked list mode transfer In contrast a STOP requests the DMA to be interrupted immediately while halt takes effect only when the current command packet is complete A halt is requested of the DMA by setting the HALT_REQ bit in the DGCS register This causes the DMA to complete the transfers defined by the current contents of the DMA registers and if the CHAIN bit is set load in the next command packet The DMA then terminates the HALT bit in the DGCS register is set and if enabled an interrupt generated After a stop or halt the DMA can be restarted from the point it left off by setting the GO bit but before it can be re started the STOP and HALT bits must be cleared Regardless of how the DMA stops whether normal bus error or user interrupted the DMA indicates in the DGCS register why it stopped The STOP and HALT bits are set in response to a stop or halt request The DONE bit gets set when the DMA has successfully completed the DMA transfer including all entries in the linked list if operating in t
240. ion 12 3 31 PCI Command Error Log Register L CMDERR The Universe II PCI Master Interface is responsible for logging errors under the following conditions e Posted write transaction results in a target abort e Posted write transaction results in a master abort or e Maximum retry counter expires during retry of posted write transaction This register logs the command information Register name L CMDERR Register offset 0x18C Pale IS ER ENSE SS Reserved Reserved Reserved CMDERR PCI Command Error Log NN NEU 0111 M_ERR Multiple Error Occurred 0 Single error 1 At least one error has occurred since the logs were frozen L_STAT PCI Error Log Status Reads O logs invalid 1 logs are valid and error logging halted Writes 0 no effect 1 clears L_STAT and enables error logging Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 211 12 3 32 PCI Address Error Log LAERR The starting address of an errored PCI transaction is logged in this register under the following conditions e aposted write transaction results in a target abort e a posted write transaction results in a master abort or amaximum retry counter expires during retry of posted write transaction Contents are qualified by bit L STAT of the L CMDERR register Register name LAERR Register offset 0x190 Integrated Device Technology Universe Il User Manual www idt com May 12
241. is used in combination with the VOWN bit in the Master Control Register MAST_CTL on page 271 to lock resources on the VMEbus The VME Lock cycle can be used by the Universe II to inform the resource that a locked cycle is intended The VOWN bit in the MAST_CTL register can be set to ensure that when the Universe II acquires the VMEbus it is the only master given access to the bus until the VOWN bit is cleared It may also be necessary for the PCI master to have locked the Universe II using the PCI LOCK_ signal When the SCYC field is set to VME Lock any write access to the specified VMEbus address will result ina VME Lock cycle on the VMEbus A VME Lock cycle is coupled the cycle does not complete on the PCI bus until it completes on the VMEbus Reads to the specified address translate to VMEbus reads in the standard fashion The data during writes is ignored The AM code generated on the VMEbus is determined by the PCI target image definition for the specified VMEbus address see Table 8 on page 70 However after the VME Lock cycle is complete there is no guarantee that the Universe II remains VMEbus master unless it has set the VOWN bit If the Universe II loses VMEbus ownership the VMEbus resouce does not remain locked The following procedure is required to lock the VMEbus through an ADOH cycle 1 If there is more than one master on the PCI bus it may be necessary to use PCI LOCK_ to ensure that the PCI master driving the ADOH
242. ister LSI7_CTL In the PCI Target Image Control register setting the VCT bit will only have effect if the VAS bits are programmed for A24 or A32 space and the VDW bits are programmed for 8 bit 16 bit or 32 bit If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64 bit the Universe II may perform MBLT transfers independent of the state of the VCT bit The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I O Space forcing all transactions through this image to be coupled Register name LSI7_CTL Register offset 0x1DC 23316 Reserved 07 00 Reserved zs Image Enable 0 Disable 1 Enable Posted Write Enable 0 Disable 1 Enable VMEbus Maximum Datawidth 00 8 bit data width 01 16 bit data width 10 32 bit data width 11 64 bit data width VMEbus Address Space 000 A16 001 A24 010 A32 011 Reserved 100 Reserved 101 CR CSR 110 User1 111 User2 Program Data AM Code 0 Data 1 Program Supervisor User AM Code 0 Non Privileged 1 Supervisor Integrated Device Technology Universe II User Manual www idt com May 12 2010 228 12 Registers gt Register Description VMEbus Cycle Type 0 no BLTs on VMEbus 1 BLTs on VMEbus PCI Bus Memory Space 0 PCI Bus Memory Space 1 PCI Bus I O Space Universe Il User Manual May 12 2010 Integrated Device Technology www idt com 12 Registers gt Register Description 229 12 3 46 PCI Target Image 7 Base Addre
243. ister Description 197 Reset Description Reset by value 18 16 VMEbus Address Space All Undefined 000 A16 001 A24 010 A32 011 Reserved 100 Reserved 101 CR CSR 110 User1 111 User2 e mm LE 8 T 9 Program Data AM Code R W All 0x00 0 Data 1 Program a m 8 E SUPER Supervisor User AM Code R W All 0x00 0 Non Privileged 1 Supervisor wmm L8 ES VMEbus Cycle Type R W All 0x00 0 No BLTs on VMEbus 1 Single BLTs on VMEbus a m0 Ls 8 9 PCI Bus Memory Space R W All Undefined 0 PCI Bus Memory Space 1 PCI Bus I O Space Integrated Device Technology Universe Il User Manual www idt com May 12 2010 198 12 Registers gt Register Description 12 3 21 PCI Target Image 3 Base Address Register LSI3_BS The base address specifies the lowest address in the address range that will be decoded Register name LSI3_BS Register offset 0x140 Casas CRINE ese Reset Description Type Reset by value Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 199 12 3 22 PCI Target Image 3 Bound Address Register LSI3 BD The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register If the bound address is 0 then the addresses decoded are those greater than or equal to the base address Register name LSI3 BD Register offset 0x144 Sane EON RO RON REOR CRISI LONE RN E NM Reset
244. ister Description 259 12 3 68 VIRQ4 STATUS ID Register V4_STATID The Vx_STATID registers are read only registers that hold the 8 bit VMEbus STATUS ID that is acquired when the Universe II performs a IACK cycle for a given interrupt level Register name V4_STATID Register offset 0x330 EARS ESE ESE IEEE 31 24 Reserved 23 16 Reserved 15 08 Reserved 07 00 STATID 7 0 Error Status Bit 0 STATUS ID was acquired without bus error 1 bus error occurred during acquisition of the STATUS ID STATID 7 0 STATUS ID acquired during IACK cycle for level 4 VMEbus ey eT es interrupt The Universe II is enabled as the interrupt handler for a given interrupt level via the VIRQx bits of the LINT_EN register Once a vector for a given level is acquired the Universe II does not perform a subsequent interrupt acknowledge cycle at that level until the corresponding VIRQx bit in the LINT_STAT register is cleared The acquisition of a level x STATUS ID by the Universe II updates the STATUS ID field of the corresponding Vx_STATID register and generation of a PCI interrupt A VMEbus error during the acquisition of the STATUS ID vector sets the ERR bit which means the STATUS ID field may not contain a valid vector Integrated Device Technology Universe II User Manual www idt com May 12 2010 260 12 Registers gt Register Description 12 3 69 VIRQ5 STATUS ID Register V5 STATID The Vx_STATID registers are read only registers that hold the 8
245. it in the DGCS register This causes the DMA first to examine the DTBC register If it is non zero it latches the values programmed into the DCTL DTBC DLA and DVA registers and initiates the transfer programmed into those registers If DTBC 0 it checks the CHAIN bit in the DGCS register and if that bit is cleared it assumes the transfer to have completed and stops Otherwise if the CHAIN bit is set it loads into the DMA registers the command packet pointed to by the DCPP register and initiates the transfer describe there If the GO bit is set but the Universe II has not been enabled as a PCI master with the BM bus master enable bit in the PCI Configuration Space Control and Status Register PCI CSR on page 172 or if the DVA and DLA contents are not 64 bit aligned to each other the transfer does not start a protocol error is indicated by the P ERR bit in the DMA General Control Status Register DGCS on page 238 and if enabled an interrupt is generated Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 6 DMA Controller gt DMA Registers 91 6 2 6 2 If the DMA has been terminated stopped halted or error all DMA registers contain values indicating where the DMA terminated Once all status bits have been cleared the DMA may be restarted from where it left off by simply setting the GO bit The GO bit only has an effect if all status bits have been cleared These bits include STOP HALT DON
246. it is cleared in other words if the VMEbus is acquired through the use of the VOWN bit the Universe II does not release BBS Y until the VOWN bit is cleared see VME Lock Cycles Exclusive Access to VMEbus Resources on page 63 The DMA Channel is complete under the following conditions e DMAFIFO full during VMEbus to PCI bus transfers DMAFIFO empty during PCI bus to VMEbus transfers 1 This setting is overridden if the VOWN mechanism is used Integrated Device Technology Universe Il User Manual www idt com May 12 2010 28 2 3 2 3 1 2 VMEbus Interface gt Universe Il as VMEbus Master e if an error is encountered during the DMA operation the DMA VMEbus Tenure Byte Counter has expired or e DMA block is complete Refer to FIFO Operation and Bus Ownership on page 101 and DMA Error Handling on page 105 for more information Universe II ownership of the VMEbus is not affected by the assertion of BCLR because it does not monitor BCLR Universe Il as VMEbus Master The Universe II becomes VMEbus master under the following circumstances 1 PCI master accesses a Universe II PCI target image leading to VMEbus access or the DMA Channel initiates a transaction 2 Either the Universe II PCI Target Channel or the DMA Channel wins access to the VMEbus Master Interface through internal arbitration 3 Universe II Master Interface requests and obtains ownership of the VMEbus The Universe II als
247. iverse II User Manual www idt com May 12 2010 24 1 2 3 2 1 2 4 1 Functional Overview gt Main Interfaces VMEbus Interrupt Handling A VMEbus interrupt triggers the Universe II to generate a normal VMEbus IACK cycle and generate the specified interrupt output When the IACK cycle is complete the Universe II releases the VMEbus and the interrupt vector is read by the PCI resource servicing the interrupt output Software interrupts are ROAK while hardware and internal interrupts are RORA DMA Controller The Universe II has an internal DMA controller for high performance data transfer between the PCI and VMEbus DMA operations between the source and destination bus are decoupled through the use of a single bidirectional FIFO DMAFIFO Parameters for the DMA transfer are software configurable in the Universe II registers see DMA Controller on page 85 The principal mechanism for DMA transfers is the same for operations in either direction PCI to VMEbus or VMEbus to PCT only the relative identity of the source and destination bus changes In a DMA transfer the Universe II gains control of the source bus and reads data into its DMAFIFO Following specific rules of DMAFIFO operation see FIFO Operation and Bus Ownership on page 101 it then acquires the destination bus and writes data from its DMAFIFO The DMA controller can be programmed to perform multiple blocks of transfers using linked list mode The DMA works
248. iverse Il Tie to any logic level if JTAG is not used in the system TDO Output JTAG Test Data Output Used to serially shift test data and test instructions out of the Universe II TMODE 2 0 Input Test Mode Enable Used for chip testing tie to ground for normal operation TMS Input JTAG Test Mode Select Controls the state of the Test Access Port TAP controller in the Universe ll Tie to any logic level if JTAG is not used in the system TRDY Bidirectional Target Ready Used by the Universe Il as PCI slave to indicate that it is ready to complete the current data phase During a read with Universe Ill as PCI master the slave asserts TRDY to indicate to the Universe II that valid data is present on the data bus TRST Input JTAG Test Reset Provides asynchronous initialization of the TAP controller in the Universe II Tie to ground if JTAG is not used in the system VCOCTL Input Manufacturing testing Tie to ground for normal operation VME RESET Input VMEbus Reset Input Generates a VME bus system reset Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 10 Signals and Pinout gt Pin out 151 10 4 Pin out 10 4 1 313 pin Plastic BGA Package PBGA
249. ix presents sustained performance values In contrast the original Universe User Manual 9000000 MD303 01 provided peak performance numbers This explains why some of the performance numbers in this document appear to be lower than for the original Universe PCI Slave Channel This channel supports both coupled and decoupled transactions Each type of transaction and the performance of each are discussed in the following sections Coupled Cycles The Universe II has a Coupled Window Timer CWT in the LMISC register which permits the coupled channel to maintain ownership of the VMEbus for an extended period beyond the completion of a cycle This permits subsequent coupled accesses to the VMEbus to occur back to back without requirement for re arbitration Request of VMEbus The CWT should be set for the expected latency between sequential coupled accesses attempted by the CPU In calculating the latency expected here the designer needs to account for latency across their host PCI bridge as well as latency encountered in re arbitration for the PCI bus between each coupled access Care must be taken not to set the CWT greater than necessary as the Universe II blocks all decoupled write transactions with target retry while the coupled channel owns the VMEbus It is only when the CWT has expired that the PCI bus is permitted to enqueue transactions in the TXFIFO When a coupled access to the VMEbus is attempted the Universe II generates a targe
250. k transfer either BLT or MBLT the slave response DS to DTACK is 8 clocks Figure 33 Coupled Write Cycle Universe Il as VME Slave bus parked at Universe II VMEbus AD 31 0 k OST C BE 3 0 1 1 m IOS B 3 2 Decoupled Cycles B 3 2 1 Write Cycles Effect of the PCI Aligned Burst Size The PCI Aligned Burst Size PABS in the MAST_CTL register affects the maximum burst size that the Universe II generates onto the PCI bus either 32 64 or 128 bytes Note that the VME Slave Channel only generates PCI bursts in response to incoming block transfers Universe Il User Manual Integrated Device Technology May 12 2010 www idt com B Performance gt VME Slave Channel 343 The greater burst size means less arbitration and addressing overhead However incumbent in this is the greater average latency for other devices in the PCI system Hence in the VME Slave Channel the burst size is a trade off between performance and latency VME Slave Response As a VME slave the Universe II accepts data into its RXFIFO with minimum delay provided there is room in the FIFO for a further data beat Assertion of DTACK is delayed if there is insufficient room in the FIFO for the next data beat During non block transfers the Universe II must both decode the address and enqueue the data before asserting DTACK to acknowledge the transfer Because of this the slave response during non block transfers is considerably slower than block tran
251. l to show that a signal is asserted low and that is used on the on the VMEbus backplane For example SIGNAL is asserted to low to indicate an active low signal on the VMEbus backplane Integrated Device Technology Universe Il User Manual www idt com May 12 2010 About this Document Object Size Notation e A byte is an 8 bit object e lt A word is a 16 bit object A doubleword Dword is a 32 bit object e A quadword is a 64 bit 8 byte object e lt A Kword is 1024 16 bit words Numeric Notation e Hexadecimal numbers are denoted by the prefix Ox for example 0x04 e Binary numbers are denoted by the prefix Ob for example 0b010 Registers that have multiple iterations are denoted by x y in their names where x is first register and address and y is the last register and address For example REG 0 1 indicates there are two versions of the register at different addresses REGO and REGI Symbols Em This symbol indicates a basic design concept or information considered helpful AN This symbol indicates important configuration information or suggestions This symbol indicates procedures or operating levels that may result in misuse or damage to the device Document Status Information e Advance Contains information that is subject to change and is available once prototypes are released to customers e Preliminary Contains information about a product that is near production ready and is revised
252. le 1 Enable Enable PCI Bus Lock of VMEbus RMW 0 Disable 1 Enable PCI Bus Address Space 00zPCI Bus Memory Space 01 PCI Bus I O Space 10 PCI Bus Configuration Space 11 Reserved Universe Il User Manual May 12 2010 E i MI u MI i B Integrated Device Technology www idt com 12 Registers gt Register Description 297 12 3 98 VMEbus Slave Image 3 Base Address Register VSI3_BS Register name VSI3_BS Register offset OXF40 23 16 BS 31 16 Base Address PWR VME EBENEN Integrated Device Technology Universe Il User Manual www idt com May 12 2010 298 12 Registers gt Register Description 12 3 99 VMEbus Slave Image 3 Bound Address Register VSI3_BD Register name VSI3_BD Register offset OxF44 23 16 BD 31 16 Bound Address PWR VME po Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 299 12 3 100 VMEbus Slave Image 3 Translation Offset VSI3 TO Register name VSI3_TO Register offset OXF48 23 16 TO 31 16 Translation Offset PWR VME EE Integrated Device Technology Universe Il User Manual www idt com May 12 2010 300 12 Registers gt Register Description 12 3 101 Location Monitor Control Register LM CTL This register specifies the VMEbus controls for the location monitor image This image has a 4 Kbyte resolution and a 4 Kbyte size The image responds to a VME read or write within the 4 Kbyte
253. le Program Data AM Code R W PWR VME 11 00 Reserved 01 Data 10 Program 11 Both Supervisor User AM Code PWR VME 00 Reserved Universe Il User Manual Integrated Device Technology May 12 2010 www idt com Prefetch Read Enable 01 Non Privileged 10 Supervisor 11 Both 12 Registers gt Register Description 291 VAS VMEbus Address Space R W PWR VME 000 Reserved 001 A24 010 A32 011 Reserved 100 Reserved 101 Reserved 110 User1 111 User2 LD64EN Enable 64 bit PCI Bus Transactions R W PWR VME 0 Disable 1 Enable LLRMW Enable PCI Bus Lock of VMEbus RMW R W PWR VME 0 Disable 1 Enable LAS PCI Bus Address Space R W PWR VME 00 PCI Bus Memory Space 01 PCI Bus I O Space 10 PCI Bus Configuration Space 11 Reserved Integrated Device Technology Universe II User Manual www idt com May 12 2010 292 12 Registers gt Register Description 12 3 94 VMEbus Slave Image 2 Base Address Register VSI2_BS Register name VSI2_BS Register offset OXF2C 23 16 BS 31 16 Base Address PWR VME 09 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 293 12 3 95 VMEbus Slave Image 2 Bound Address Register VSI2_BD Register name VSI2_BD Register offset OXF30 23 16 BD 31 16 Bound Address PWR VME EBENEN Integrated Device Technology Universe Il User Manual www idt com May 12 2010 294 12 Registers gt Register Description 12 3 96 V
254. leared P_ERR must not be updated at the same time as Step 4 otherwise the P_ERR that may be generated by setting GO may be missed see Step 4 These bits can be cleared as part of Step 1 In Step 4 with the transfer programmed the GO bit in DGCS must be set Ifthe DMA has been improperly programmed either because the BM bit in the PCI_CSR has not been set to enable PCI bus mastership or the source and destination start addresses are not aligned then P_ERR will be asserted Otherwise the ACT bit will be set and the DMA will then start transferring data sharing ownership of the VMEbus with the PCI Target and Interrupt channels and the PCI bus with the VMEbus Slave Channel In Step 5 the DMA waits for termination of the DMA transfers The DMA continues with the transfers until it Completes all transfers Terminates early with the STOP REQ bit Encounters an error on the PCI bus or VMEbus Each of these conditions cause the ACT bit to clear and a corresponding status bit to be set in the DGCS register If enabled in Step 1 an interrupt is generated Once the software has set the GO bit the software can monitor for DMA completion by either waiting for generation of an interrupt or by polling the status bits It is recommended that a background timer also be initiated to time out the transfer This ensures the DMA has not been hung up by a busy VMEbus or other such system issues If an early termination is de
255. led If an error occurs on the PCI bus the Universe II does not translate the error condition into a BERR on the VMEbus Indeed the Universe II does not directly map the error By doing nothing the Universe II forces the external VMEbus error timer to expire 8 3 3 DMA Errors The Universe II s response to a bus error during a transfer controlled by the DMA Channel is described in DMA Error Handling on page 105 8 3 4 Parity Errors The Universe II both monitors and generates parity information using the PAR signal The Universe II monitors PAR when it accepts data as a master during a read or as a target during a write The Universe II drives PAR when it provides data as a target during a read or a master during a write The Universe II also drives PAR during the address phase of a transaction when it is a master and monitors PAR during an address phase when it is the PCI target In both address and data phases the PAR signal provides even parity for C BE 3 0 and AD 31 0 If the Universe II is powered up in a 64 bit PCI environment then PAR64 provides even parity for C BE 7 4 and AD 63 32 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 128 8 Error Handling gt Errors on Decoupled Transactions The PERESP and SERR_EN bits in the PCI Configuration Space Control and Status Register PCI_CSR on page 172 determine whether or not the Universe II responds to parity errors Data parity e
256. level see Table 21 It must be held asserted for over 100 milliseconds after power is stable Typically this can be achieved through a resistor capacitor combination see Figure 22 or under voltage sensing circuits Figure 22 Resistor Capacitor Circuit Ensuring Power Up Reset Duration 47K PWRRST_ 10uF The Universe II supports the VMEbus CSR Bit Clear and Bit Set registers The VMEbus CSR Bit Set Register VCSR SET on page 330 register allows the user to assert LRST_ or SYSFAIL by writing to the RESET or SYSFAIL bits LRST_ or SYSFAIL remains asserted until the corresponding bit is cleared in the VMEbus CSR Bit Clear Register VCSR CLR on page 329 The FAIL bit in each of these registers 1s a status bit and is set by the software to indicate board failure Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 9 Resets Clocks and Power up Options gt Power Up Options 135 9 3 Power Up Options The Universe II can be automatically configured at power up to operate in different functional modes These power up options allow the Universe II to be set in a particular mode independent of any local intelligence Table 22 Power Up Options OM Pester VMEbus Register Access Slave VRAI CTL Image VRAI BS VMEbus CR CSR Slave Image VCSR CTL L VCSR TO T Disabled E VA 31 V A16 VA 30 29 B 0x00 VA 28 21 Memory VA 20 0x00 VA 19 15 Disabled VD 30 Disabled VD 29 Auto ID MIS
257. line is asserted during the address phase in a 64 bit PCI system and is the means of determining whether the PCI target is a 64 bit port If the target asserts ACK64 with DEVSEL then the Universe II uses the 64 bit data bus If the target does not assert ACK64_ with DEVSEL then the Universe II uses a 32 bit data bus However note that use of REQ64 requires extra clocks internally If no 64 bit targets are expected on the PCI bus then performance can be improved by disabling LD64EN on the VMEbus slave images Universe II only performs 64 bit PCI transactions if the power up option LCLSIZE bit in the N Miscellaneous Status Register MISC STAT on page 275 is set to 1 If the Universe II is set for a 32 bit PCI transaction LCLSIZE bit set to 0 it does not perform 64 bit PCI transactions 4 3 PCI Bus Target Images The Universe II accepts accesses from the PCI bus with programmed PCI target images Each image opens a window to the resources of the VMEbus and allows the user to control the type of access to those resources The Table 7 Table 8 and Table 9 describe programming for the eight standard PCI bus target images numbered 0 to 7 by dividing them into VMEbus PCI bus and Control fields One special PCI target image is described in Special PCI Target Image on page 73 Table 7 PCI Bus Fields for the PCI Bus Target Image Base BS 31 12 or BS 31 16 in Multiples of 4 or 64 Kbytes base to bound LSIx BS maximum of 4 GBytes Bound
258. list the DMA controller is in one of the following conditions 1 It can be active and working its way through the linked list In this case no further steps are required 2 The DMA can be idle done because it reached the final command packet If a full set of linked command packets had already been created ahead of time then the DCPP register points to the most recently programmed command packet and the DTBC register would be zero The DMA can be started on the new packet by simply clearing the DONE bit and setting the GO bit in the DGCS register If a set of command packets have not been created ahead of time the DCPP register can not be programmed to any valid packet and needs programming to the newly programmed packet 3 The DMA has encountered an error In this circumstance see DMA Error Handling on page 105 for how to handle DMA errors Operation can be considerably simplified by ensuring that sufficient command packets have been created during system initialization probably in a circular queue In this fashion when a new entry is added to the list it is simply a matter of programming the next available entry in the list with the new transfer attributes and changing the previously last packet s NULL bit to zero The DCPP register is guaranteed to point to a valid command packet so upon updating the list both cases 1 and 2 above can be covered by clearing the DONE bit and setting the GO bit This has no effect for case 1 sinc
259. ll six forms of DMA terminations can be optionally set to generate a DMA interrupt by setting the appropriate enable bit in the DGCS register see DMA Interrupts on page 104 e LERRis set if the DMA encounters an error on the PCI bus either a Master Abort or Target Abort Bits in the PCI Configuration Space Control and Status Register PCI CSR on page 172 indicate which of these conditions caused the error Integrated Device Technology Universe II User Manual www idt com May 12 2010 106 6 8 2 6 8 2 1 6 8 3 6 DMA Controller gt DMA Error Handling e VERR is set if the DMA encounters a bus error on the VMEbus This is through a detected assertion of BERR during a DMA cycle e P ERRis set if the GO bit in the DGCS register is set to start the DMA and the DMA has been improperly programmed either because the BM bit in the PCI CSR disables PCI bus mastership or the source and destination start addresses are not aligned see Source and Destination Addresses on page 86 Whether the error occurs on the destination or source bus the DMA CTL register contains the attributes relevant to the particular DMA transaction The DTBC register provides the number of bytes remaining to transfer on the PCI side The DTBC register contains valid values after an error The DLA and DVA registers should not be used for error recovery DMA Hardware Response to Error When the error condition VMEbus Error Target Abor
260. locks and Power up Options on page 129 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 80 5 Registers Overview gt Register Access from the VMEbus Figure 13 UCSR Access from the VMEbus Register Access Image PV J VMEbus Configuration and Status Registers VCSR UNIVERSE DEVICE SPECIFIC REGISTERS UDSR PCI CONFIGURATION SPACE PCICS N 5 3 2 CR CSR Accesses 4 Kbytes of UCSR VRAI BS Total Memory in A16 A24 or A32 Address Space Y The VME64 Specification assigns a total of 16 Mbytes of CR CSR space for the VMEbus system The CR CSR image is enabled with the EN bit in the VMEbus CSR Control Register VCSR_CTL on page 305 This 16 Mbytes is broken up into 512 Kbytes per slot for a total of 32 slots The first 512 Kbyte block is reserved for use by the Auto ID mechanism The UCSR space occupies the upper 4 Kbytes of the 512 Kbytes available for its slot position see Figure 14 The base address of the CR CSR space allocated to the Universe II s slot is programmed in the VMEbus CSR Base Address Register VCSR BS on page 331 Universe Il User Manual May 12 2010 Integrated Device Technology www idt com 5 Registers Overview gt Register Access from the VMEbus 81 5 3 3 For CSRs not supported in the Universe II and for CR accesses the LAS field in the VCSR_CTL register specifies the PCI bus command that is generated when
261. logy May 12 2010 www idt com 12 Registers gt Register Description 279 12 3 85 VMEbus Slave Image 0 Control Register VSIO CTL The state of PWEN and PREN are ignored if LAS is not programmed memory space Integrated Device Technology Universe II User Manual www idt com May 12 2010 280 12 Registers gt Register Description Register name VSIO CTL Register offset 0xF00 15 08 Reserved Image Enable PWR VME 0 Disable 1 Enable Posted Write Enable PWR VME 0 Disable PWR VME 1 Enable PWR VME Prefetch Read Enable 0 Disable 1 Enable Program Data AM Code 00 Reserved 01 Data 10 Program 11 Both VMEbus Address Space 000 A16 001 A24 010 A32 011 Reserved 100 Reserved 101 Reserved 110 User1 111 User2 Supervisor User AM Code R W PWR VME 11 00 Reserved 01 Non Privileged 10 Supervisor 11 Both E PWR VME Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 281 LD64EN Enable 64 bit PCI Bus Transactions R W PWR VME 0 Disable 1 Enable Enable PCI Bus Lock of VMEbus RMW R W PWR VME 0 Disable 1 Enable PCI Bus Address Space R W PWR VME 00zPCI Bus Memory Space 01 PCI Bus I O Space 10 PCI Bus Configuration Space 11 Reserved Integrated Device Technology Universe II User Manual www idt com May 12 2010 282 12 Registers gt Register Description 12 3 86 VMEbus Slave Image 0 Base Address Register VSIO_B
262. ly to the Coupled Data Transfer Phase The Coupled Window Timer determines the maximum duration of the Coupled Wait Phase When the Universe II enters the Coupled Wait Phase the Coupled Window Timer starts The period of this timer is specified in PCI clocks and is programmable through the CWT field of the PCI Miscellaneous Register LMISC on page 206 If this field is programmed to 0000 the Universe II does an early release of BBSY during the coupled transfer on the VMEbus and will not enter the Coupled Wait Phase In this case VMEbus ownership is relinquished immediately by the PCI Target Channel after each coupled cycle Once the timer associated with the Coupled Wait Phase expires the Universe II releases the VMEbus if release mode is set for RWD or the release mode is set for ROR and there is a pending external request on the VMEbus 1 PCI latency requirements as described in revision 2 1 of the PCI Specification require that only 16 clock cycles can elapse between the first and second data beat of a transaction Since the Universe II cannot guarantee that data acknowledgment will be received from the VMEbus in time to meet these PCI latency requirements the Universe II performs a target disconnect after the first data beat of every coupled write transaction Integrated Device Technology Universe Il User Manual www idt com May 12 2010 60 3 4 4 3 4 4 1 3 PCI Interface gt Universe II as PCI Target Posted Writes
263. mation Address Phase PCI transactions are initiated by asserting FRAME and driving address and command information onto the bus In the VMEbus Slave Channel the Universe II calculates the address for the PCI transaction by adding a translation offset to the VMEbus address see Universe II as VMEbus Slave on page 32 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 3 PCI Interface gt PCI Cycles 51 The command signals on the C BE_ lines contain information about Memory space cycle type and whether the transaction is read or write Table 3 shows the PCI command type encoding implemented with the Universe II Table 3 Command Type Encoding for Transfer Type C BE_ 3 0 for PCI C BE 7 4 for non multiplexed Command Type Universe II Capability 1100 Memory Read Multiple See Memory Read Types on page 51 1110 Memory Read Line See Memory Read Types on page 51 1111 Memory Write and Invalidate See Memory Read Types on page 51 3 2 3 1 Memory Read Types Memory Read Multiple and Memory Read Line transactions are aliased to Memory Read transactions when the Universe II is accessed as a PCI target with these commands Likewise Memory Write and Invalidate is aliased to Memory Write As a PCI master the Universe II can generate Memory Read Multiple but not Memory Read Line Integrated Device Technology Universe II User Manual www idt com May 12 2010 52 3 2 4 3 2 5 3 PCI
264. meters Condition VIL VIH lin liL VOL VOH Voltage Input low Voltage Input high Input leakage current Vin 2 7V or 1 0 5V a Input leakage current low Vdd 0 5 o a To ojo a o ic e d e P Pin with pull up Voltage output low lout 3mA 6mA Voltage output high lout 2mA IOH AC Switching current high 0 lt Vout 1 4 1 4 lt Vout lt 2 4 44 Vout 1 4 0 024 Test point Vout 3 1V N P E A RK id gt F gt Equation A Equation B 95 Vout 0 023 mN e o A IOL AC Switching current high 0 lt Vout 1 4 0 6Vdd Vout lt 0 1Vdd 0 71 lt Vout 0 Test point Vout 0 71V Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 11 Electrical Characteristics gt DC Characteristics 155 Table 29 AC DC PCI Electrical Characteristics Low clamp current 5 Vin 1 25 Vin 10 mA 0 015 SLEWR Output rise slew rate 0 4V to 2 4V 5 V ns load SLEWR Output fall slew rate 2 4V to 0 4V a load a Equation A loh 11 9 Vout 5 25 Vout 2 45 for Vdd gt Vout gt 3 1V b Equation B lol 78 5 Vout 4 4 Vout for OV lt Vout lt 0 71V 11 1 3 Pin List and DC Characteristics for all Signals Table 30 specifies the required DC characteristics of all Universe II signal pins Table 30 Pin List and DC Characteristics for Universe Il Signals Output lot loH Type Input Type Type mA mA Signal
265. mmand information and one data entry The size of the data entry corresponds to the data width of the VMEbus transfer Block transfers require at least two entries one entry for address and command information and one or more data entries The VMEbus Slave Channel packs data received during block transfers to the full 64 bit width of the RXFIFO For example a ten data phase D16 BLT transfer 20 bytes in total does not require ten data entries in the RXFIFO Instead eight of the ten data phases 16 bits per data phase for a total of 128 bits are packed into two 64 bit data entries in the RXFIFO The final two data phases 32 bits combined are queued in the next RXFIFO entry When the address entry is added to the three data entries this VMEbus block write has been stored in a total of five RXFIFO entries Integrated Device Technology Universe II User Manual www idt com May 12 2010 34 2 4 2 2 2 4 3 2 VMEbus Interface gt Universe Il as VMEbus Slave Unlike the PCI Target Channel see Universe II as PCI Target the VMEbus Slave Channel does not retry the VMEbus if the RXFIFO does not have enough space to hold an incoming VMEbus write transaction Instead the DTACK response from the VMEbus Slave Interface is delayed until space becomes available in the RXFIFO Since single transfers require two entries in the RXFIFO two entries must be available before the VMEbus Slave Interface asserts DTACK Similarly the VMEbus Slave Ch
266. n Note that the VOWN setting described above overrides the POWN setting BUS NO is used by the VMEbus Slave Channel when mapping VME transactions into PCI Configuration space If the bus number of the VMEbus address bits 23 16 is equal to the BUS NO field then the Universe II generates a Type 0 configuration cycle otherwise Type 1 is generated Register name MAST CTL Register offset 0x400 BEEN EEUU sm 24 MAXRTRY PWON B RIO T i E 07 00 BUS NO MAXRTRY Maximum Number of Retries R W 1000 3 0 0000 Retry Forever Multiples of 64 0001 through 1111 Maximum Number of retries before the PCI master interface signals error condition PWON 3 0 Posted Write Transfer Count R W 0000 0000 128 bytes 0001 256 bytes 0010 512 bytes 0011 1024 bytes 0100 2048 bytes 0101 4096 bytes 0110 1110 Reserved 1111 Early release of BBSY Transfer count at which the PCI Slave Channel Posted Writes FIFO gives up the VME Master Interface Integrated Device Technology Universe Il User Manual www idt com May 12 2010 272 12 Registers gt Register Description VRL 1 0 VMEbus Request Level 00 Level 0 01 Level 1 10 Level 2 11 Level 3 VRM VMEbus Request Mode 0 Demand 1 Fair VREL VMEbus Release Mode 0 Release When Done RWD 1 Release on Request ROR VOWN VME Ownership Bit 0 Release VMEbus 1 Acquire and Hold VMEbus VOWN ACK VME Ownership Bit Acknowledge 0 VMEbus not owned 1 VMEbus acquired and held due to assertio
267. n from the PCI transaction is mapped directly to the VMEbus The general attributes of each region are programmed according to the tables below Table 10 PCI Bus Fields for the Special PCI Target Image Feia RegisterBits Bits Description a puse 0 64 C NN aligned base address for the image Address space HAS Places image in Memory or I O Table 11 VMEbus Fields for the Special PCI Bus Target Image Maximum data width data width vbw Separately sets each region for 16 or 32 bits sets each Separately sets each region for 16 or 32 bits for 16 or 32 bits EE MM Separately sets each region as supervisor or non privileged data Table 12 Control Fields for the Special PCI Bus Target Image Image enable Enable bit for the image Posted write PWEN Enable bit for posted writes for the image Integrated Device Technology Universe Il User Manual www idt com May 12 2010 74 4 Slave Image Programming gt Special PCI Target Image The special PCI target image provides access to all of A16 and most of A24 space all except the upper 64 Kbytes By using the special PCI target image for A16 and A24 transactions it is possible to free the eight standard PCI target images see PCI Bus Target Images on page 70 which are typically programmed to access A32 space Address space redundancy is provided in A16 space The VMEbus specification requires only two A16 spaces while the special PCI target image allows for four
268. n of VOWN PABS 1 0 PCI Aligned Burst Size 00 32 byte 01 64 byte 10 128 byte 11 256 byte Controls the PCI address boundary at which the Universe II breaks up a PCI transaction in the VME Slave channel see VME Slave Image Programming on page 67 and the DMA Channel see FIFO Operation and Bus Ownership on page 101 This field also determines when the PCI Master Module as part of the VME Slave Channel will request the PCI bus i e when 32 64 128 or 256 bytes are available It does not have this effect on the DMA Channel which has a fixed watermark of 128 bytes see FIFO Operation and Bus Ownership on page 101 BUS NO 7 0 PCI Bus Number pw ow 0000 0000 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 273 12 3 81 Miscellaneous Control Register MISC_CTL VMEbus masters must not write to SW_SYSRST and PCI masters must not write to SW_LRST The bits VBTO VARB and VARBTO support SYSCON functionality Universe II participation in the VME64 Auto ID mechanism is controlled by the VME64AUTO bit When this bit is detected high the Universe II uses the SW_IACK mechanism to generate VXIRQ2 on the VMEbus then releases VXSYSFAIL Access to the CR CSR image is enabled when the level 2 interrupt acknowledge cycle completes This sequence can be initiated with a power up option or by software writing a to this bit Register name MISC_CTL Register off
269. n page 67 e PCI Bus Target Images on page 70 e Special PCI Target Image on page 73 4 1 Overview The Universe II recognizes two types of accesses on its bus interfaces accesses destined for the other bus and accesses decoded for its own register space Address decoding for the Universe II s register space is described in Registers on page 163 This section describes the slave images used to map transactions between the PCI bus and VMEbus 4 2 VME Slave Image Programming The Universe II accepts accesses from the VMEbus within specific programmed slave images Each VMEbus slave image opens a window to the resources of the PCI bus and through its specific attributes allows the user to control the type of access to those resources The tables below describe programming for the VMEbus slave images by dividing them into VMEbus PCI bus and Control fields Table 4 VMEbus Fields for VMEbus Slave Image Base BS 31 12 or BS 31 16 in Multiples of 4 or 64 Kbytes base to bound VSIx_BS maximum of 4 GBytes Bound BD 81 12 or BD 31 16 in VSIx BD Address space VAS in VSIx CTL A16 A24 A32 User 1 User 2 Mode SUPER in VSIx_CTL Supervisor and or non privileged PGM in VSIx_CTL Program and or data Integrated Device Technology Universe II User Manual www idt com May 12 2010 68 4 Slave Image Programming gt VME Slave Image Programming Table 5 PCI Bus Fields for VMEbus Slave Image Translation offset TO 31 12 or TO 3
270. n the bus By continuing to assert VAS ownership of the bus is maintained during a RMW cycle VMEbus Address Strobe Direction Control controls the direction of the address strobe transceiver as required for master slave and bus isolation modes When the Universe ll is driving lines on the VMEbus this signal is driven high when the VMEbus is driving the Universe II this signal is driven low VMEbus Bus Clear requests that the current owner release the bus Asserted by the Universe Il when configured as SYSCON and the arbiter detects a higher level pending request VBGI 3 0 Input VMEbus Bus Grant Inputs The VME arbiter awards use of the data transfer bus by driving these bus grant lines low The signal propagates down the bus grant daisy chain and is either accepted by a requester if it requesting at the appropriate level or passed on as a VBGO 3 0 to the next board in the bus grant daisy chain Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 10 Signals and Pinout gt VMEbus Signals 145 Table 26 VMEbus Signals Continued VBGO 3 0 _ Output VMEbus Bus Grant Outputs Only one output is asserted at any time according to the level at which the VMEbus is being granted VD 31 0 _ Bidirectional VMEbus Data Lines 31 through 0 VD_DIR Output VMEbus Data Transceiver Direction Control the Universe II controls the direction of the
271. nd its GNT is asserted the transfer begins immediately This eliminates a possible one clock cycle delay before beginning a transaction on the PCI bus which would exist if the Universe II did not implement bus parking Bus parking is described in Section 3 4 3 of the PCI Specification Rev 2 1 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com B Performance gt VME Slave Channel 345 On the PCI bus the Universe II deliquesce data from the RXFIFO once a complete VME transaction has been enqueued or once sufficient data has been enqueued to form a PCI transaction of length defined by the PABS field Since the Universe II does not perform any address phase deletion non block transfers are decreed from the RXFIFO as single data beat transactions Only block transfers result in multi data beat PCI transactions typically 8 16 or 32 data beats In either case the Universe II does not insert any wait states as a PCI master The clock after the bus has been granted to the Universe II drives out FRAME _ to generate the address phase The data phases begin immediately on the next clock If there is more than one data phase each phase will immediately follow the acknowledgment of the previous phase In each case because of the lack of any wait states as a PCI master the Universe II is consuming the minimum possible bandwidth on the PCI bus and data will be written to the PCI bus at an average sustained rate equal to t
272. ng from levels 3 to 0 Only one grant is issued per level and one owner is never forced from the bus in favor of another requester VBCLR is never asserted Since only one grant is issued per level on each round robin cycle several scans are required to service a queue of requests at one level VMEbus Arbiter Time out The Universe Il s VMEbus arbiter can be programmed to time out if the requester does not assert BBSY within a specified period This allows BGOUT to be negated so that the arbiter can continue with other requesters The timer is programmed using the VARBTO field in the MISC CTL register and can be set to 16 us 256 us or disabled The default setting for the timer is 16 us The arbitration time out timer has a granularity of 8 us setting the timer for 16 us means the timer can timeout in as little as 8 us IACK Daisy Chain Driver Module The IACK Daisy Chain Driver module is enabled when the Universe II becomes system controller This module guarantees that IACKIN stays high for at least 30 ns as specified in rule 40 of the VME64 specification VMEbus Time out A programmable bus timer allows users to select a VMEbus time out period The time out period is programmed through the VBTO field in the Miscellaneous Control Register MISC_CTL on page 273 and can be set to 16us 32us 64us 128 us 256 us 512 us 1024 us or disabled The default setting for the timer is 64 us The VMEbus Timer module asserts VXBERR_ if a
273. ng until they receive IACKIN then count four more clocks and assert I ACKOUT to the next board Finally the last board asserts IACKOUT and the bus pauses until the data transfer time out circuit ends the bus cycle by asserting BERR Integrated Device Technology Universe II User Manual www idt com May 12 2010 44 2 6 3 2 6 3 1 2 6 3 2 2 VMEbus Interface gt Automatic Slot Identification Figure 5 Timing for Auto ID Cycle SYSCLK AS DS0 IACK IACKOUT CARD 1 IACKOUT CARD 2 IACKOUT CARD 3 ID COUNTER VALUE 0 0 1 2 3 4 5 6 TA 8 9 10 11 12 13 14 15 Because all boards are four clocks wide the value in the clock counter is divided by four to identify the slot in which the board is installed any remainder is discarded Note that since the start of the IACK cycle is not synchronized to SYSCLK a one count variation from the theoretical value of the board can occur However in all cases the ID value of a board is greater than that of a board in a lower slot number The result is placed in the DY4AUTOID 7 0 field and the DY4DONE bit is set located in the Miscellaneous Status Register MISC_STAT on page 275 System Controller Functions When located in Slot 1 of the VMEbus system see First Slot Detector on page 41 the Universe II assumes t
274. niverse II is communicated to the PCI master as a Target Abort and the S TA bit is set in the PCI CSR register No information is logged in either direction nor is an interrupt generated Errors on Decoupled Transactions During decoupled transactions there is a possibility that an error in the transaction can occur The following sections detail the decoupled transactions supported by Universe II and the types of error handling supported for these transactions Integrated Device Technology Universe Il User Manual www idt com May 12 2010 126 8 3 1 8 3 1 1 8 Error Handling gt Errors on Decoupled Transactions Posted Writes The Universe II provides the option of performing posted writes in both the PCI Target Channel and the VMEbus Slave Channel Once data is written into the RXFIFO or TXFIFO by the initiating master VMEbus or PCI bus respectively the Universe II provides immediate acknowledgment of the cycle s termination When the data in the FIFO is written to the destination slave or target by the Universe II the Universe II can receive a bus error instead of a normal termination The Universe II handles this situation by logging the errored transactions in one of two error logs and generating an interrupt Each error log one for VMEbus errors and one for PCI bus errors is comprised of two registers one for address and one for command or address space logging Error Logs If the error occurs during a posted write
275. nsactions occur on the PCI bus with zero wait states there is a period of six PCI clocks during which the Universe II remains idle before re requesting the bus for the next transaction PCI bus parking may be used to eliminate the need for re arbitration Universe Il User Manual Integrated Device Technology May 12 2010 www idt com B Performance gt DMA Channel and Relative FIFO Sizes Figure 38 PCI Read Transactions During DMA Operation PCI CLK REQ GNT FRAME AD 31 0 C BE 3 0 IRDY TRDY STOP DEVSEL Figure 39 Multiple PCI Read Transactions During DMA Operation CLK REQ GNT FRAME AD 31 0 C BE 3 0 IRDY TRDY STOP DEVSEL Integrated Device Technology www idt com 349 With PABS set for 32 byte transactions on a 32 bit PCI bus this translates to a peak transfer rate of 97 MB s for reads including pre fetching 98 MB s for writes doubling to 194 and 196 for a 64 bit PCI bus With PABS set for 64 byte transactions the peak transfer rate increases to 118 MB s for reads 125 MB s for writes on a 32 bit PCI bus 236 MB s and 250 MB s respectively for 64 bit PCI buses The numbers for writes to PCI assume that data are read from VME using BLTs
276. nterrupt LINT7 0 LINT7 0 in the VME Interrupt LINT7 0 Input Map 0 Register VINT MAPO on page 253 VMEbus Software SW INT SW INT in the VME SW_INT Interrupt Interrupt Map 1 Register mappable VINT MAP1 on page 254 a This set of software interrupts cannot be mapped That is setting the SW INTI1 bit triggers VXIRQ1 setting the SW INT2 bit triggers VXIRQ2 etc For all VMEbus interrupts the Universe II interrupter supplies a pre programmed 8 bit STATUS ID a common value for all interrupt levels The upper seven bits are programmed in the STATID register The lowest bit is cleared if the source of the interrupt was the software interrupt and is set for all other interrupt sources If a software interrupt source and another interrupt source are active and mapped to the same VMEbus interrupt level the Universe II gives priority to the software source Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 7 Interrupt Generation and Handling gt Interrupt Generation 115 Figure 19 STATUS ID Provided by Universe ll STATUS ID iii i SI if S W Int t Programmed from 0 if S W Interrupt Source VME_STATUS ID 1 if Internal or LINT Registers Interrupt Source Once the Universe II has provided the STATUS ID to an interrupt handler during a software initiated VMEbus interrupt it generates an internal interrupt SW_IACK If enabled this interrupt feeds back to the PCI bus through one of the LINT
277. ntrol Register DCTL on page 232 If the VMEbus slave image is programmed with a 64 bit PCI bus data width and Universe II is powered up in a 64 bit PCI environment the Universe II asserts REQ64 during the address phase of the PCI transaction REQ64 is asserted if LD64EN is set in a 64 bit PCI system independent of whether the N Universe II has a full 64 bit transfer This can result in a performance degradation because of the extra clocks required to assert REQ64_ and to sample ACK64 Also there can be some performance degradation when accessing 32 bit targets with LD64EN set Do not set the LD64EN bit unless there are 64 bit targets in the slave image window If the VMEbus slave images are not programmed for a 64 bit wide PCI data bus then the Universe operates transparently in a 32 bit PCI environment Independent of the setting of the LD64EN bit the Universe II never attempts a 64 bit cycle on the PCI bus if it is powered up as a 32 bit device PCI Bus Request and Parking The Universe II supports bus parking If the Universe II requires the PCI bus it asserts REQ only if its GNT_ is not currently asserted When the PCI Master Module is ready to begin a transaction and its GNT is asserted the transfer begins immediately This eliminates a possible one clock cycle delay before beginning a transaction on the PCI bus which would exist if the Universe II did not implement bus parking Refer to the PCI 2 1 Specification for more infor
278. nual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 303 12 3 103 VMEbus Register Access Image Control Register VRAI CTL The VME Register Access Image allows access to the Universe II registers with standard VMEbus cycles Only single cycle and lock AM codes are accepted When a register is accessed with a RMW it is locked for the duration of the transaction Register name VRAI CTL Register offset OXF70 9m 24 Reserved 15 08 Reserved 07 00 Reserved Image Enable PWR VME Power up 0 Disable Option 1 Enable Program Data AM Code PWR VME 00 Reserved 01 Data 10 Program 11 Both Supervisor User AM Code R W PWR VME 00 Reserved 01 Non Privileged 10 Supervisor 11 Both VMEbus Address Space Power up Option 00 A16 01 A24 10 A32 all others are reserved Integrated Device Technology Universe II User Manual www idt com May 12 2010 304 12 Registers gt Register Description 12 3 104 VMEbus Register Access Image Base Address Register VRAI BS The base address specifies the lowest address in the 4 Kbyte VMEbus Register Access Image Register name VRAI_BS Register offset OxF74 BS 31 12 The base address specifies the lowest address in the 4 Kbyte R W PWR VME Power up VMEbus Register Access Image Option The reset state is a function of the Power up Option behavior of the VAS field in VRAI_CTL Table 35 shows the behavior of the VAS field
279. o becomes VMEbus master if the VMEbus ownership bit is set see VME Lock Cycles Exclusive Access to VMEbus Resources on page 63 and in its role in VMEbus interrupt handling see VMEbus Interrupt Handling on page 116 The following sections describe the function of the Universe II as a VMEbus master in terms of the different phases of a VMEbus transaction addressing data transfer cycle termination and bus release Addressing Capabilities Depending upon the programming of the PCI target image see PCI Bus Target Images on page 70 the Universe II generates A16 A24 A32 and CR CSR address phases on the VMEbus The address mode and type supervisor non privileged and program data are also programmed through the PCI target image Address pipelining is provided except during MBLT cycles The VMEbus Specification does not permit pipelining during MBLT cycles The address and Address Modifier AM codes that are generated by the Universe II are functions of the PCI address and PCI target image programming see PCI Bus Target Images on page 70 or through DMA programming Table 1 shows the AM codes used for the VMEbus Table 1 VMEbus Address Modifier Codes Ox3F A24 supervisory block transfer BLT OxSE A24 supervisory program access 0x3D A24 supervisory data access Ox3C A24 supervisory 64 bit block transfer MBLT Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 2 VMEbus In
280. oded Register name LSI1_BS Register offset 0x118 SASSEN Reset Description Type Reset by value Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 189 12 3 14 PCI Target Image 1 Bound Address Register LSI1_BD The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register If the bound address is 0 then the addresses decoded are those greater than or equal to the base address The bound address for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution PCI Target Images 1 2 3 5 6 and 7 have a 64Kbyte resolution Register name LSI1_BD Register offset 0x11C 5 3 RE eS ea ea ee ewe LINE o e E MEME Reset Description Type Reset by value 31 16 BD 31 16 Bound Address Address ENNUN E Integrated Device Technology Universe Il User Manual www idt com May 12 2010 190 12 Registers gt Register Description 12 3 15 PCI Target Image 1 Translation Offset LSI1_TO Address bits 31 16 generated on the VMEbus in response to an image decode are a two s complement addition of address bits 31 16 on the PCI Bus and bits 31 16 of the image s translation offset Register name LSI1_TO Register offset 0x120 Dita RES ER ERE EIOS EROR ERE EROS Reset Description Type Reset by value 31 16 TO 31 16 Translation Offset Universe Il User Manual Integr
281. ogo and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology Inc Contents 1 Functional Overview o c n rh nmn 1 1 OYePVIeW 1er veo ERU EAMUS UAE ed Eu us 1 1 1 Universe II Features 0 0 0 ccc ete ences 1 1 2 Universe II Benefits 0 0 0 0 ccc ce eee 1 1 3 Universe II Typical Applications 0 005 1 2 Main Interfaces eder rat EEE E Sanne EE 1 2 1 VMEbus Interface 0 0 eee eee 1 2 2 PCI Bus nterface ssar a teenies 1 2 3 Interrupter and Interrupt Handler 002 1 2 4 DMA Controller 0 0 0 ccc ee cet I 2 VMEbus Interface 200c cece eee eee 2 1 OVETVACW sius aa i aad scito be Sadho wd doe cene deir cde dade PRA ERU 22 VMEbus Requester sesseeeeeeee eens 2 2 1 Internal Arbitration for VMEbus Requests 2 2 2 Request Modes 0 ce eee cece eet eee nee 2 2 3 VMEbus Release 0 00 cee en 2 3 Universe Il as VMEbus Master 0 cece een eee 2 3 1 Addressing Capabilities llle eee 2 3 2 Data Transfer Capabilities 0 0000000000 233 Cycle Terminations 0 0 0 0 cece eee eee eee 2 4 Universe II as VMEbus Slave 0 0 00 cc cece eee ene eee 2 4 1 Coupled Transfers 5 iret dia wid o deese ea eR RE orc 2 4 2 Posted Witte eur sees e EIE AC PHAR IHRE C 2 4 3 Prefetched Block Reads n on nunna ccc cece eee 2
282. on is enqueued in the FIFO before processing it If configured to generate non block transfers the Universe II can generate back to back VME transfers with cycle times of approximately 180ns AS to AS against an ideal VME slave 30 45 ns A greater cycle time is required between the termination of one full enqueued transaction and the start of the next This inter transaction time is approximately 210ns As such the longer the PCI transaction the greater the sustained performance on the VMEbus With 64 byte PCI transactions the sustained rate is 43 MB s With 32 byte transactions this drops to 23 MB s Each of these numbers is calculated with no initial arbitration or re arbitration for the bus Figure 30 shows the Universe II queueing a transaction with multiple non block VME transfers Block transfers significantly increase performance The inter transaction period remains at approximately 210 ns for BLTs and MBLTs but the data beat cycle time DS to DS drops to about 120ns against the same ideal slave Again the length of the burst size affects the sustained performance because of the inter transaction time For BLTs operating with a burst size of 64 bytes the sustained performance is 37 MB s dropping to 33 MB s for a burst size of 32 bytes MBLTs operating with 64 byte bursts perform at a sustained rate of 66 MB s dropping to 50 MB s for 32 bytes Integrated Device Technology Universe II User Manual www idt com May 12 2010 34
283. on page 260 V5 STATID 0x338 VIRQ6 STATUS ID Register V6 STATID on page 261 V6 STATID 0x33C VIRQ7 STATUS ID Register V7_STATID on page 262 V7 STATID 0x340 PCI Interrupt Map 2 Register LINT MAP2 on page 263 LINT MAP2 0x344 VME Interrupt Map 2 Register VINT MAP2 on page 264 VINT MAP2 0x348 Mailbox 0 Register MBOXO on page 265 MBOXO 0x34C Mailbox 1 Register MBOX1 on page 266 MBOX1 0x350 Mailbox 2 Register MBOX2 on page 267 MBOX 2 0x354 Mailbox 3 Register MBOX3 on page 268 MBOX3 0x358 Semaphore 0 Register SEMAO on page 269 SEMAO 0x35C Semaphore 1 Register SEMA1 on page 270 SEMA1 0x360 0x3FC Reserved 0x400 Master Control Register MAST_CTL on page 271 MAST_CTL 0x404 Miscellaneous Control Register MISC_CTL on page 273 MISC_CTL 0x408 Miscellaneous Status Register MISC_STAT on page 275 MISC_STAT Integrated Device Technology Universe Il User Manual www idt com May 12 2010 168 12 Registers gt Register Map Table 34 Universe Il Register Map Continued Offset Register Name 0x40C User AM Codes Register USER_AM on page 276 USER_AM 0x410 0x4F8 Reserved Ox4FC Universe ll Specific Register U2SPEC on page 277 U2SPEC 0x500 0xEFC Reserved OxF00 VMEbus Slave Image 0 Control Register VSIO CTL on page 279 VSIO CTL OxF04 VMEbus Slave Image 0 Base Address Register VSIO BS on VSIO BS page 282 OxF08 VMEbus Slave Image 0 Bound Address Regis
284. ond the boundary but before the next boundary the DTBC register may be programmed to eight byte transfers The DMA fetches the full eight bytes and nothing more Programming the DTBC to less than eight bytes still results in eight bytes fetched from PCI The DMA requests ownership of the Universe II s VMEbus Master Interface once 64 bytes of data have been queued in the DMAFIFO see VMEbus Requester on page 25 on how the VMEbus Master Interface 1s shared between the DMA the PCI Target Channel and the Interrupt Channel The Universe II maintains ownership of the Master Interface until one of the following conditions are met e DMAFIFO is empty e DMA block is complete e DMA is stopped e alinked list is halted e DMA encounters an error e DMA VMEbus tenure limit VON in the DGCS register Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 6 DMA Controller gt FIFO Operation and Bus Ownership 103 The DMA can be programmed to limit its VMEbus tenure to fixed block sizes using the VON field in the DMA General Control Status Register DGCS on page 238 With VON enabled the DMA relinquishes ownership of the Master Interface at defined address boundaries See DMA VMEbus Ownership on page 91 To further control the DMA s VMEbus ownership the VOFF timer in the DGCS register can be used to program the DMA to remain off the VMEbus for a specified period when VMEbus tenure is relinquished
285. one through the VMEbus master bus error interrupt and another through the standard PCI interrupt translation If an error occur during acquisition of a STATUS ID the PCI Interrupt Status Register LINT STAT on page 244 shows that both VIRQx and VERR are active Integrated Device Technology Universe Il User Manual www idt com May 12 2010 118 7 3 3 Internal Interrupt Handling 7 Interrupt Generation and Handling gt Interrupt Handling The Universe II s internal interrupts are routed from several processes in the device There is an interrupt from the VMEbus Master Interface to indicate a VMEbus error another from the PCI Master Interface to indicate an error on that bus another from the DMA to indicate various conditions in that channel along with several others Table 18 shows to which bus each interrupt source can be routed Some sources can be mapped to both buses but mapping interrupts to a single bus is recommended Table 18 Internal Interrupt Routing May be Routed to Interrupt Source VMEbus PCI Bus PCI s w interrupt VMEbus s w interrupt IACK cycle complete for s w interrupt Mailbox access Location monitor PCI Target Abort or y Master Abort VMEbus bus error Y VMEbus bus ownership granted Universe Il User Manual May 12 2010 y y Ni 4 Integrated Device Technology www idt com 7 Interrupt Generation and Handling gt Interrupt Handling Integrated Device Technology
286. ormed in these beats MBLT transfers behave somewhat differently The first beat of an MBLT transfer is address only and so the response is relatively fast Subsequent data beats require acknowledgment from the PCI bus With a 32 bit PCI bus the MBLT data beat 64 bits of data requires a two data beat PCI transaction Because of this extra data beat required on the PCI bus the slave response of the Universe II during coupled MBLT cycles is at least one PCI clock greater depending upon the response from the PCI target than that during BLT cycles Integrated Device Technology www idt com B Performance B 3 1 2 gt VME Slave Channel 341 Read Cycles During coupled cycles the Universe II does not acknowledge a VME transaction until it has been acknowledged on the PCI bus Because of this the VME slave response during coupled reads is directly linked to the response time for the PCI target Each clock of latency in the PCI target response translates directly to an extra clock of latency in the Universe II s VME coupled slave response The address of an incoming VME transaction is decoded and translated to an equivalent PCI transaction Typically four PCI clock periods elapse between the initial assertion of AS on the VMEbus and the assertion of REQ_ on the PCI bus During the data only portion of subsequent beats in block transfers the time from DS assertion to REQ_ is about 4 clocks If the PCI bus is parked at the Universe II no
287. ot modify the resource Any resource locked on the VMEbus cannot be accessed by any other resource during the bus tenure of the VMEbus master When the Universe II receives a VMEbus lock command it asserts LOCK_ to the addressed resource on the PCI bus The PCI Master Interface processes this as a 32 bit read transfer with all byte lanes enabled no data All subsequent slave VMEbus transactions are coupled while the Universe II owns PCI LOCK_ The Universe II holds the PCI bus lock until the VMEbus lock command is terminated by negating BBSY The VMEbus Slave Channel has dedicated access to the PCI Master Interface during the locked transaction Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 2 VMEbus Interface gt Universe Il as VMEbus Slave 37 The Universe II accepts ADOH cycles in any of the slave images when the Universe II PCI Master Interface is enabled BM bit in PCI_CSR register and the images are programmed to map transactions into PCI Memory Space 2 4 4 1 Errors If an error occurs on the PCI bus a bus error will occur on the VMEbus because they are coupled In the event a bus error occurs on the VMEbus once a LOCK_ has been established the VMEbus master which locked the VMEbus must terminate the LOCK_ by negating BBSY 2 4 4 2 DMA Access Once an external VMEbus masters locks the PCI bus the Universe II DMA does not perform transfers on the PCI bus until the bus is unlocked LO
288. out this Document Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 1 1 17 Functional Overview This chapter outlines the functionality of the Universe II This chapter discusses the following topics Overview on page 17 e VMEbus Interface on page 22 e PCI Bus Interface on page 22 e nterrupter and Interrupt Handler on page 23 e DMA Controller on page 24 Overview The IDT Universe II is the industry s leading high performance PCI to VMEbus interconnect Universe II is fully compliant with the VME64 bus standard and tailored for the next generation of advanced PCI processors and peripherals With a zero wait state implementation multi beat transactions and support for bus parking Universe II provides high performance on the PCI bus The Universe II eases development of multi master multi processor architectures on VMEbus and PCI bus systems The device is ideally suited for CPU boards functioning as both master and slave in the VMEbus system and that require access to PCI systems Bridging is accomplished through a decoupled architecture with independent FIFOs for inbound outbound and DMA traffic With this architecture throughput is maximized without sacrificing bandwidth on either bus With the Universe II you know that as your system becomes more complex you have proven silicon that continues to provide everything you need in a PCI to VME bridge Integrated Device Te
289. ower up Write O No effect 1 Initiate sequence This bit initiates Universe Il VME64 Auto ID Slave participation SYSRESET System Reset OzNo effect 1 Initiate SYSRST Universe Il asserts SYSRESET without resetting itself Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 275 12 3 82 Miscellaneous Status Register MISC_STAT Register name MISC_STAT Register offset 0x408 ESSE NEUE ee Ee BC ee ee ON 23 16 Reserved a DY4 DON TXFE RXFE E 15 08 DY4AUTOID 07 00 Reserved LCLSIZE PCI Bus Size Power up At the rising edge of RST_ the Universe Il samples REQ64_ to determine the PCI Bus size This bit reflects the result 0 32 bit 1 64 bit DY4AUTO DY4 Auto ID Enable Power up 0 Disable 1 Enable MYBBSY Universe Il BBSY O Asserted 1 Negated DY4DONE DY4 Auto ID Done 0 Not done 1 Done TXFE PCI Target Channel Posted Writes FIFO O data in the FIFO 1 no data in the FIFO RXFE VME Slave Channel Posted Writes FIFO O data in the FIFO 1 no data in the FIFO DY4 DY4 Auto ID Power up AUTOID reset and VMEbus SYS RESET Integrated Device Technology Universe Il User Manual www idt com May 12 2010 276 12 Registers gt Register Description 12 3 83 User AM Codes Register USER_AM The USER AM register can only be used to generate and accept AM codes 0x10 through Ox1F These AM codes are designated as USERAM codes in the VMEbus Specification Re
290. plane These bypass capacitors should also be tied as close as possible to the package Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 373 Ordering Information This appendix discusses Universe II s ordering information F 1 Ordering Information IDT products are designated by a product code When ordering refer to products by their full code Table 47 details the available part numbers Table 47 Standard Ordering Information CA91C142D 33CE 5V Commercial PBGA 0 to 70 C CA91C142D 33CEV 5V Commercial PBGA 0 to 70 C RoHS Green CA91C142D 383IE 5V Industrial PBGA 40 to 85 C CA91C142D 33IEV 5V Industrial PBGA 40 to 85 C RoHS Green CA91C142D 25EE 5V Extended PBGA 55 to 125 C Integrated Device Technology Universe II User Manual www idt com May 12 2010 374 F Ordering Information gt Ordering Information The IDT Tsi part numbering system is explained as follows Tsi NNN N SS S EP G Z L Ii py HUUL 3 rM 200 a 9 9 gag E g 2 s gt a S ud o0 gs N g 5 S SOS c o si a oct 5 5 z 5 agg 9 oH 208 Zz 9 E eo BS 9 5 E aa gt no A ud on o oO 6 amp s g 9 d d o pa fanl S 3 Be Ss ba A e e Indicates optional characters e Tsi IDT Tsi product identifier e NNNN Product number may be three or four digits e SS S Maximum operating frequency or data transfer rate of the fastest interface For operating frequency n
291. pliance and meet JIG Joint Industry Guide Level B requirements for Brominated Flame Retardants other than PBBs and PBDEs e Zi Prototype version status optional If a product is released as a prototype then a Z is added to the end of the part number Further revisions to the prototype prior to production release would add a sequential numeric digit For example the first prototype version of device would have a Z a second version would have Z1 and so on The prototype version code is dropped once the product reaches production status Integrated Device Technology Universe Il User Manual www idt com May 12 2010 376 F Ordering Information gt Ordering Information Universe Il User Manual Integrated Device Technology May 12 2010 www idt com CORPORATE HEADQUARTERS for SALES for Tech Support j 6024 Silver Creek Valley Road 800 345 7015 or 408 284 8200 email VMEhelpQ idt com hey l San Jose CA 95138 fax 408 284 2775 phone 408 360 1538 m www idt com Document May 12 2010 DISCLAIMER Integrated Device Technology Inc IDT and its subsidiaries reserve the right to modify the products and or specifications described herein at any time and at IDT s sole discretion All information in this document including descriptions of product features and performance is subject to change without notice Performance specifications and the operating parameters of the described products are determined in the independent state
292. programming of the VMEbus register access image address space and the upper five bits of its base address all other bits are 0 see Table 23 Once access is provided to the registers then all other Universe II features such as further VMEbus slave images can be configured from the VMEbus Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 9 Resets Clocks and Power up Options gt Power Up Options 137 Table 23 shows how the upper bits in the VRAI base address are programmed for A16 A24 and A32 VMEbus register access images Table 23 VRAI Base Address Power up Options Power up Option VA 28 25 VRAI CTL VAS A24 Power up Option VA 28 21 Power up Option VA 28 21 9 3 1 2 VMEbus CR CSR Slave Image CR CSR space is an address space introduced in the VME64 Specification The CR CSR space on any VMEbus device is 512 Kbytes in size the upper region of the 512 Kbytes dedicated to register space and the lower region is dedicated to configuration ROM The Universe II maps its internal registers to the upper region of the CR CSR space and passes all other accesses through to the PCI bus see Registers on page 163 The VMEbus CR CSR Slave Image power up option maps CR CSR accesses to the PCI bus CR CSR space can be mapped to memory or I O space with a 5 bit offset This allows mapping to any 128 Mbyte page on the PCI bus As part of this implementation ensure that the PCI Master Interface is
293. r RWD the VMEbus Master Interface releases BBSY when the channel accessing the VMEbus Master Interface is done see below Note that the MYBBSY status bit in the Miscellaneous Status Register MISC STAT on page 275 is 0 when the Universe II asserts BBSY In RWD mode the VMEbus is released when the channel for example the DMA Channel is done even if another channel has a request pending for example the PCI Target Channel A re arbitration of the VMEbus is required for any pending channel requests Each channel has a set of rules that determine when it is done with its VMEbus transaction Transaction Complete The interrupt is complete when a single interrupt acknowledge cycle is complete The PCI Target Channel is complete under the following conditions e when the TXFIFO is empty the TXFE bit is clear the TXFE bit is set by the Universe II in the MISC STAT register e when the maximum number of bytes per PCI Target Channel tenure has been reached as programmed with the PWON field in the Master Control Register MAST_CTL on page 271 L e after each posted write if the PWON is equal to 0b1111 as programmed in the MAST_CTL register e when the coupled cycle is complete and the Coupled Window Timer has expired e if the Coupled Request Timer page 58 expires before a coupled cycle is retried by a PCI master or e when VMEbus ownership is acquired with the VOWN bit in the MAST_CTL register and then the VOWN b
294. r and will be mapped directly to AD 7 2 e VA 10 8 identifies the PCI Function Number and will be mapped directly to AD 10 8 e VA 15 11 selects the device on the PCI bus and will be mapped to AD 31 12 according to Table 2 e VA 23 16 matches the BUS NO in MAST CTL register e Other address bits are not important they are not mapped to the PCI bus Table 2 PCI Address Line Asserted as a Function of VA 15 11 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 40 2 4 8 2 2 VMEbus Interface gt Universe Il as VMEbus Slave Table 2 PCI Address Line Asserted as a Function of VA 15 11 VA 15 11 PCI Address Line Asserted LM LS The other values of VA 15 11 are not defined and must not be used b Only one of AD 31 11 is asserted the other address lines in AD 31 11 are negated ADOH BLT and MBLT cycles must not be attempted when the LAS of an image is programmed to PCI Configuration space Generating Configuration Type 1 Cycles The following steps are used to generate a configuration Type 1 cycle on the VMEbus 1 Program LAS field of VSIx CTL to Configuration Space 2 Program the VSIx BS VSIx BD registers to some suitable value 3 Program the VSIx TO register to 0 4 Program the BUS NO field of the MAST CTL register to some value Perform a VMEbus access where e VMEbus Address 7 2 identifies the PCI Register Number e VMEbus Address 10 8 identifies the PCI Function N
295. r to handle errors so that they have minimum effects on an application devices have a logic module called an error handler The error handler logs data about the error then communicates the information to another device for example a host processor that is capable of resolving the error condition This chapter discusses the following topics e Errors on Coupled Cycles on page 125 e Errors on Decoupled Transactions on page 125 Overview There are different conditions under which bus errors can occur with the Universe II during coupled cycles or during decoupled cycles In a coupled transaction the completion status is returned to the transaction master which can then take some action However in a decoupled transaction the master is not involved in the data acknowledgment at the destination bus and higher level protocols are required The error handling provided by the Universe II is described for both coupled and decoupled transactions Errors on Coupled Cycles During coupled cycles the Universe II provides immediate indication of an errored cycle to the originating bus VMEbus to PCI transactions terminated with Target Abort or Master Abort are terminated on the VMEbus with BERR The R TA or R MA bits in the PCI Configuration Space Control and Status Register PCI CSR on page 172 are set when the Universe II receives a Target Abort or Master Abort For PCI to VMEbus transactions a VMEbus BERR received by the U
296. ram DCPP Step 4 Set GO bit Step 5 Await termination of DMA Normal Termination handle error In Step 1 the DGCS register is set up The CHAIN bit is set VON and VOFF are programmed with the appropriate values for controlling DMA VMEbus tenure and the interrupt bits INT STOP INT HALT INT DONE INT LERR INT VERR and INT P ERR are programmed to enable generation of interrupts based on DMA termination events DMA interrupt enable bits in the LINT EN or VINT EN bits should also be enabled as necessary PCI Interrupt Generation on page 111 and VMEbus Interrupt Generation on page 113 In Step 2 the linked list structure is programmed with the required transfers The actual structure may be set up at any time with command packet pointers pre programmed and then only the remaining DMA transfer elements need be programmed later One common way is to set up the command packets as a circular queue each packet points to the next in the list and the last points to the first This allows continuous programming of the packets without having to set up or tear down packets later Once the structure for the linked list is established the individual packets are programmed with the appropriate source and destination addresses transfer sizes and attributes Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 6 DMA Controller gt Linked list Mode 99 In Step 3 Clear the DTB
297. rammed in the VAS field of the DMA Transfer Control Register DCTL on page 232 The sub spaces are programmed in the PGM and SUPER fields of the same register Although the PCI and VMEbus addresses may be programmed to any byte aligned address they must be 8 byte aligned to each other the low three bits of each must be identical If not programmed with aligned source and destination addresses and an attempt to start the DMA is made the DMA does not start It sets the protocol error bit P_ERR in the DMA General Control Status Register DGCS on page 238 and if enabled to generates an interrupt When this occurs linked list operations cease In direct mode the user must reprogram the source and destination address registers DMA DLA before each transfer These registers are not updated in direct mode In linked list mode these registers are updated by the DMA when the DMA is stopped halted or at the completion of processing a command packet If read during DMA activity they return the number of bytes remaining to transfer on the PCI side All of the DMA registers are locked against any changes by the user while the DMA is active When stopped due to an error situation the DLA and DVA registers must not be used but the DTBC is valid see DMA Error Handling on page 105 for details At the end of a successful linked list transfer the DVA and DLA registers point to the next address at the end of the transfer block and the
298. ransfer with BE_ 1100 These criteria optimize performance of 32 bit PCI systems which regularly perform 16 bit transfers A series of 16 bit transfers is also performed if 64 bit posted write is received with BE_ 11000011 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 4 Slave Image Programming gt Special PCI Target Image 73 4 3 3 Control Fields The control fields enable a PCI target image the EN bit as well as specify how writes are processed If the PWEN bit is set then the Universe II performs posted writes when that particular PCI target image is accessed Posted write transactions are only decoded within PCI Memory space Accesses from I O spaces results in coupled cycles independent of the setting of the PWEN bit 4 4 Special PCI Target Image The Universe II provides a special PCI target image located in Memory or I O space Its base address is aligned to 64 Mbyte boundaries and its size is fixed at 64 Mbytes decoded using PCI address lines 31 26 The Special PCI Target Image SLSI on page 208 is divided into four 16 Mbyte regions numbered 0 to 3 see Figure 10 on page 74 These separate regions are selected with PCI address bits AD 25 24 For example if AD 25 24 01 then region is decoded Within each region the upper 64Kbytes map to VMEbus A16 space while the remaining portion of the 16 Mbytes maps to VMEbus A24 space Note that no offsets are provided so address informatio
299. ri stated the power up options are loaded with their values latched on the rising edge of PWRRST Configuration of power up options is most easily accomplished through passive 10k pull up resistors on the appropriate VA and VD pins The configurations may be made user configurable through jumpers or switches as shown in Figure 42 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 368 E 2 3 1 E 3 E Typical Applications gt PCI Bus Interface Figure 42 Power up Configuration Using Passive Pull ups Universe Il VDD Power up Pins Alternatively an active circuit may be designed which drives the VA and VD pins with pre set or pre programmed values This sort of circuit would be of value when power up configurations such as the register access slave image are stored in an external programmable register To implement this circuit the VOE_ output from the Universe II must be monitored When the Universe II negates this signal the appropriate VA and VD signals may be driven and upon re assertion the drive must be removed To avoid conflict with the transceivers logic must be designed such that the enabling of the transceivers does not occur until some point after the configuration options have been removed from the VD and VA signals Figure 43 shows one such implementation The delay for enabling of the VMEbus transceivers could be implemented though clocked latches Figure 43 Power up Configuration
300. rmination with one of two settings One setting allows data to be latched and the cycle terminated with an associated delay that is less than 25 ns The second setting results in no delay in latching and termination Universe Il User Manual Integrated Device Technology May 12 2010 www idt com B Performance gt Universe Il Specific Register 351 B 5 2 4 VME Slave Parameter t28 Control POSt28 According to the VME64 Specification VMEbus slaves must wait at least 30 ns after the assertion of DS before driving DTACK low When the Universe II is acting as a VME slave the POSt28 parameter in the U2SPEC register enables DTACK to be asserted in less than 30 ns when executing posted writes B 5 2 5 VME Slave Parameter t28 Control PREt28 VMEbus slaves must wait at least 30ns after the assertion of DS before driving DTACK low When the Universe II is acting as a VME slave in the transaction PREt28 parameter in the U2SPEC register enables DTACK to be asserted in less than 30 ns when executing pre fetched reads Integrated Device Technology Universe Il User Manual www idt com May 12 2010 Performance Summary Table 36 PCI Slave Channel Performance Cycle Type Coupled Read PCI target response Coupled Write PCI target response Decoupled Write Non block D32 VME cycle time sustained perf 32 byte PABS sustained perf 64 byte PABS D32 BLT VME cycle time sustained perf 32 byte PABS s
301. rrors are reported through the assertion of PERR_ if the PERESP bit is set Address parity errors reported through the SERR_ signal are reported if both PERESP and SERR_EN are set Regardless of the setting of these two bits the D_PE Detected Parity Error bit in the PCI_CS register is set if the Universe II encounters a parity error as a master or as a target The DP_D Data Parity Detected bit in the same register is only set if parity checking is enabled through the PERESP bit and the Universe II detects a parity error while it is PCI master that is it asserts PERR_ during a read transaction or receives PERR_ during a write No interrupts are generated by the Universe II either as a master or as a target in response to parity errors reported during a transaction Parity errors are reported by the Universe II through assertion of PERR_ and by setting the appropriate bits in the PCI_CSR register If PERR_ is asserted to the Universe II while it is PCI master the only action it takes is to set the DP D Regardless of whether the Universe II is the master or target of the transaction and regardless which agent asserted PERR_ the Universe II does not take any action other than to set bits in the PCI_CSR register The Universe II continues with a transaction independent of any parity errors reported during the transaction Similarly address parity errors are reported by the Universe II if the SERR EN bit and the PERESP bit are set by asserting
302. rrupt Channel provides a flexible scheme to map interrupts to the PCI bus or VMEbus Interface Interrupts are generated from hardware or software sources see Interrupt Generation on page 111 and Interrupt Handling on page 116 for a full description of hardware and software sources Interrupt sources can be mapped to any of the PCI bus or VMEbus interrupt output pins Interrupt sources mapped to VMEbus interrupts are generated on the VMEbus interrupt output pins VIRQ_ 7 1 When a software and hardware source are assigned to the same VIRQ pin the software source always has higher priority Interrupt sources mapped to PCI bus interrupts are generated on one of the INT 7 0 pins To be fully PCI compliant all interrupt sources must be routed to a single INT pin For VMEbus interrupt outputs the Universe II interrupter supplies an 8 bit STATUS ID to a VMEbus interrupt handler during the IACK cycle The interrupter also generates an internal interrupt in this situation if the SW IACK bit in the PCI Interrupt Status LINT STAT register is set to 1 see VMEbus Interrupt Generation on page 113 Interrupts mapped to PCI bus outputs are serviced by the PCI interrupt controller The CPU determines which interrupt sources are active by reading an interrupt status register in the Universe II The source negates its interrupt when it has been serviced by the CPU see PCI Interrupt Generation on page 111 Integrated Device Technology Un
303. rt VOE_ I VOE_ VME_RESET_ mS hold for 200ms gt VXSYSRST_ MISC_CTL Register SW_SYSRST SW_LRST VCSR_CLR and VCSR_SET Registers hold for RESET gt 5 ms B LRST Notes 1 On PWRRST options are loaded from pins On SYSRST and RST_ options are loaded from values that were latched at the previous PWRRST_ 2 Referto Registers on page 163 to find the effects of various reset events 9 2 2 Reset Implementation Cautions To prevent the Universe II from resetting the PCI bus the LRST output can be left unconnected Otherwise LRST_ must be grouped with other PCI reset generators to assert the RST signal so that the following conditions are met RST LRST amp reset_sourcel amp reset source2 amp If the Universe II is the only initiator of PCI reset LRST_ can be directly connected to RST Integrated Device Technology Universe II User Manual www idt com May 12 2010 134 9 Resets Clocks and Power up Options gt Resets Assertion of VME RESET causes the Universe II to assert VXSYSRST Since VME RESET causes assertion of SYSRST and since SYSRST causes N assertion of LRST_ tying both VME RESET and LRST to RST_ will put the Universe II into permanent reset If VME RESET is driven by PCI reset logic ensure that the logic is designed to break this feedback path The PWRRST input keeps the Universe II in reset until the power supply has reached a stable
304. rupt Status Clear O Local DMA Interrupt masked 1 Local DMA Interrupt active VIRQx Interrupt Status Clear 0 VIRQx Interrupt masked 1 VIRQx Interrupt active VOWN Interrupt Status Clear O0 no VOWN Interrupt masked 1 VOWN Interrupt active Integrated Device Technology www idt com R Write 1 to Clear R Write 1 to Clear R Write 1 to Clear R Write 1 to Clear R Write 1 to Clear R Write 1 to Clear R Write 1 to Clear R Write 1 to Clear R Write 1 to Clear R Write 1 to Clear Universe ll User Manual May 12 2010 246 12 Registers gt Register Description 12 3 58 PCI Interrupt Map 0 Register LINT MAPO This register maps various interrupt sources to one of the eight PCI interrupt pins For example a value of 000 maps the corresponding interrupt source to LINT 0 Register name LINT MAPO Register offset 0x308 BUS ee Be SEC UE ee ee ROTER NON VIRQ7 VIRQ1 PCI interrupt destination LINT 7 0 for VIRQx pw foal 0 VOWN VMEbus ownership bit interrupt map to PCI interrupt Rw DON 0 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 247 12 3 59 PCI Interrupt Map 1 Register LINT_MAP1 This register maps various interrupt sources to one of the eight PCI interrupt pins For example a value of 000 maps the corresponding interrupt source to LINT_ 0 Register name LINT_MAP1 Register offset 0x30C pee ee Le
305. s I O space Once set this mapping is constant until the next power up sequence See Memory or I O Access on page 77 9 3 2 Power up Option Implementation In order to implement power up requirements for the Universe II weak pull up resistors are required 9 3 2 1 Pull up Requirements The pull ups for the general power up options if other than default values are required must be placed on the VA 31 1 and VD 31 27 lines During reset the Universe II negates VOE_ putting these signals into a high impedance state While VOE_ is negated the pull ups or internal pull downs bring the option pins on A 31 1 and D 31 27 to their appropriate state The internal pull downs are very weak The leakage current on many transceivers can be sufficient to override these pull downs To ensure proper operation designers must ensure power up option pins go to the correct state Within two CLK64 periods after PVRRST is negated the Universe II latches the levels on the option pins and then negates VOE_ one clock later This enables the VMEbus transceivers inwards Figure 23 Power up Options Timing minimum 100ms CLK64 PWRRST_ VOE_ VA VD X power up options Integrated Device Technology Universe Il User Manual www idt com May 12 2010 140 9 Resets Clocks and Power up Options gt Power Up Options The power up options are subsequently loaded into their respective registers several PCI clock periods after PWRRST_ SYSRST and RST_
306. s gt Manufacturing Test Pins The designer may wish to disallow the Universe II from resetting the PCI bus in which case this output may be left unconnected Otherwise LRST_ should be grouped with other PCI reset generators to assert the RST_ signal such that RST LRST and reset_sourcel and reset source2 and If the Universe II is the only initiator of PCI reset LRST_ may be directly connected to RST_ Assertion of VME RESET causes the Universe II to assert VXSYSRST This signal must not by tied to the PCI RST_ signal unless the Universe II LRST_ N output will not generate a PCI bus reset Connecting both LRST and VME RESET to RST will cause a feedback loop on the reset circuitry forcing the entire system into a endless reset To reset the VMEbus through this signal it is recommended that it be asserted for several clock cycles until the Universe II asserts RST and then released This ensures a break is made in the feedback path Power Up Reset The PWRRST input is used to provide reset to the Universe II until the power supply has reached a stable level It should be held asserted for 100 milliseconds after power is stable Typically this can be achieved through a resistor capacitor combination although more accurate solutions using under voltage sensing circuits e g MC34064 are often implemented The power up options are latched on the rising edge of PWRRST JTAG Reset The JTAG reset TRST should be tied into the ma
307. s no effect on non block writes they can be coupled or decoupled Only accesses to PCI Memory Space are decoupled accesses to I O or Configuration Space e are always coupled Figure 8 Address Translation Mechanism for VMEbus to PCI Bus Transfers A32 Image Offset 31 12 PCI 31 12 PCI 11 0 Y Y VME 31 12 VME 11 0 Control Fields The control fields enable a VMEbus slave image using the EN bit as well as specify how reads and writes are processed At power up all images are disabled and are configured for coupled reads and writes If the PREN bit is set the Universe II prefetches for incoming VMEbus block read cycles It is the user s responsibility to ensure that prefetched reads are not destructive and that the entire image contains prefetchable resources Prefetching is only possible in PCI Memory Space If the PWEN bit is set incoming write data from the VMEbus is loaded into the RXFIFO see Posted Writes on page 33 Note that posted write transactions can only be mapped to Memory space on the PCI bus Setting the LAS bit in the PCI fields to I O or Configuration Space will force all incoming cycles to be coupled independent of this bit Integrated Device Technology Universe Il User Manual www idt com May 12 2010 70 4 Slave Image Programming gt PCI Bus Target Images If the LD64EN bit is set the Universe II generates 64 bit transactions on the PCI bus by asserting REQ64_ The REQ64_
308. s the DMA will stop performing transfers within 256 bytes once the programmed limit has been reached When programmed for Release When Done operation the Universe II performs an early release of BBSY when the VON counter reaches its programmed limit VON may be disabled by setting the field to zero When the VON bit is set to O the DMA continues transferring data as long as it is able There are other conditions under which the DMA may relinquish bus ownership See FIFO Operation and Bus Ownership on page 101 for details on the VMEbus request and release conditions for the DMA VOFF VOFF affects how long the DMA waits before re requesting the bus after the VON limit has been reached By setting VOFF to 0 the DMA immediately re requests the bus once the VON boundary has been reached Since the DMA operates in a round robin fashion with the PCI Target Channel and in a priority fashion with the Interrupt Channel if either of these channels require ownership of the VMEbus they receive it at this time VOFF is only invoked when VMEbus tenure is relinquished due to encountering the VON boundary When the VMEbus is released due to other conditions for example the DMAFIFO has become full while reading from the VMEbus it will be re requested as soon as that condition is cleared The VOFF timer can be programmed to various time intervals from Ous to 1024us See FIFO Operation and Bus Ownership on page 101 for details on the VMEbus request an
309. s translation to the PCI bus Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 7 Interrupt Generation and Handling gt Interrupt Handling 117 7 3 2 1 When the Universe II receives a STATUS ID in response to an IACK cycle it stores that value in one of seven registers These registers VIRQI STATUS ID Register V1_STATID on page 256 through VIRQ7 STATUS ID Register V7_STATID on page 262 store the STATUS ID corresponding to each IACK level in the STATID field Once an IACK cycle has been generated and the resulting STATUS ID is latched another ACK cycle is not run on that level until the level has been cleared by writing a 1 to the corresponding status bit in the PCI Interrupt Status Register LINT STAT on page 244 If other interrupts at different levels are pending while the interrupt is waiting to be cleared IACK cycles are run on those levels in order of priority and the STATUS IDs stored in their respective registers Once the IACK cycle is complete and the STATUS ID stored an interrupt is generated to the PCI bus on one of LINT 7 0 depending on the mapping for that VMEbus level in the PCI Interrupt Map 0 Register LINT MAPO on page 246 The interrupt is cleared and the VMEbus interrupt level is re armed by clearing the correct bit in the PCI Interrupt Status Register LINT STAT on page 244 register Bus Error During VMEbus IACK Cycle A bus error encountered on the VM
310. s D16 write transactions are mapped to D32 write transactions on the PCI bus with all byte lanes enabled However a single D16 transaction from the VMEbus is mapped to the PCI bus as D32 with only two byte lanes enabled During block transfers the Universe II packs data to the full negotiated width of the PCI bus This may imply that for block transfers that begin or end on addresses not aligned to the PCI bus width different byte lanes may be enabled during each data beat Errors If an error occurs during a posted write to the PCI bus the Universe II uses the PCI Command Error Log Register L_CMDERR on page 210 to log the command information for the transaction CMDERR 3 0 The L CMDERR register also records if multiple errors have occurred with the M ERR bit although the actual number of errors is not given The error log is qualified with the L STAT bit The address of the errored transaction is latched in the PCI Address Error Log LAERR on page 211 An interrupt is generated on the VMEbus and or PCI bus depending upon whether the VERR and LERR interrupts are enabled see Error Handling on page 125 and Interrupt Generation and Handling on page 109 Prefetched Block Reads Prefetching of read data occurs for VMEbus block transfers BLT MBLT in those slave images that have the Prefetch Enable PREN bit set see VME Slave Image Programming on page 67 In the VMEbus Slave Channel prefetching is not support
311. s high After the IACK cycle is performed and it has received a Status ID indicating an Auto Slot ID request the monarch software does the following 1 Masks IRQ2 It will not service other interrupters at that interrupt level until current Auto Slot ID cycle is completed 2 Performs an access at 0x00 in CR CSR space to get information about Auto Slot ID slave 3 Moves the CR CSR base address to a new location 4 Unmasks IRQ2 to allow it to service the next Auto ID slave The Universe II supports monarch activity through its capability to be a level 2 interrupt handler All other activity must be handled through software residing on the board Auto ID A Proprietary IDT Method The Universe II uses a proprietary Auto ID scheme when enabled through a power up option see Auto ID on page 137 The IDT proprietary Auto ID function identifies the relative position of each board in the system without using jumpers or on board information The ID number generated by Auto ID can then be used to determine the board s base address After any system reset assertion of SYSRST the Auto ID logic responds to the first level one IACK cycle on the VMEbus After the level one IACK signal has been asserted either through IRQ1 or with a synthesized version the Universe II in slot 1 counts five clocks from the start of the cycle and then asserts IACKOUT to the second board in the system see Figure 5 All other boards continue counti
312. s responsible for logging the parameters of a posted write transaction that results in a bus error This register holds the address modifier code and the state of the IACK signal The register contents are qualified by the V STAT bit Register name V AMERR Register offset OXF88 EZE 24 AMERR TACK MERR ERR Ta 16 V_STAT Reserved 15 08 Reserved 07 00 Reserved AMERR 5 0 VMEbus AM Code Error Log EX PWR VME ERE IACK VMEbus IACK Signal OR PWR VME za Multiple Error Occurred PWR VME 0 Single error 1 At least one error has occurred since the logs were frozen VME Error Log Status R W PWR VME Reads 0 logs invalid 1 logs are valid and error logging halted Writes 0 no effect 1 clears V STAT and enables error logging Integrated Device Technology Universe Il User Manual www idt com May 12 2010 308 12 Registers gt Register Description 12 3 108 VMEbus Address Error Log VAERR The Universe II VMEbus Master Interface is responsible for logging the parameters of a posted write transaction that results in a bus error This register holds the address The register contents are qualified by the V STAT bit of the V AMERR register Register name VAERR Register offset OXF8C pr VAERR 31 1 VMEbus address error log PWR VME Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 309 12 3 109 VMEbus Slave Image 4 Control VSI4_CT
313. s the UPDATE bit against writes and proceeds to the next command packet If the UPDATE bit is 1 then the DMA waits until the bit is cleared before proceeding to the next command packet Setting the UPDATE bit is a means of stalling the DMA at command packet boundaries while local logic updates the linked list In order to ensure that the DMA is not currently reading a command packet during updates the update logic must write a 1 to the UPDATE bit and read a value back If a 0 is read back from the UPDATE bit then the DMA is currently reading a command packet and has locked the UPDATE bit against writes If a 1 is read back from the UPDATE bit then the DMA is idle or processing a transaction and command packets can be updated If the DMA attempts to proceed to the next command packet during the update it encounters the set UPDATE bit and wait until the bit is cleared Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 6 DMA Controller gt FIFO Operation and Bus Ownership 101 6 5 If a set of linked command packets has already been created with empty packets at the end of new transfers adding to the end of the current linked list is accomplished by the following steps 1 Get UPDATE valid write 1 read back 1 2 Program attributes for new transfer in next available packet in list 3 Change null pointer on previous tail of linked list 4 Release update clear the UPDATE bit After updating the linked
314. se Il User Manual www idt com May 12 2010 142 9 Resets Clocks and Power up Options gt Clocks e boundary scan register e bypass register e anIDCODE register The following required public instructions are supported BYPASS 3 b111 SAMPLE 3 b100 and EXTEST 3 b000 The optional public instruction IDCODE 3 b011 selects the IDCODE register which returns 32 b01e201d The following external pins are not part of the boundary scan register LCLK PLL TESTOUT PLL TESTSEL TMODE 3 0 and VCOCTL 9 5 Clocks CLK64 is a 64 MHz clock that is required by the Universe II in order to synchronize internal Universe II state machines and to produce the VMEbus system clock VSYSCLK when the Universe II is system controller SYSCON This clock is specified to have a minimum 50 50 duty cycle with a maximum rise time of 5 ns Using a different clock frequency is not recommended It will alter various internal timers and change VME timing Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 10 10 1 Signals and Pinout This chapter discusses the following topics e VMEbus Signals on page 144 e PCI Bus Signals on page 147 e Pin out on page 151 Overview 143 The following detailed description of the Universe II signals is organized according to these functional groups e VMEbus Signals e PCI Signals Integrated Device Technology www idt com Universe II User Manual May 12 2010
315. se of a transfer for the Special Cycle Generator to perform its function Whenever this address on the PCI bus bits 31 2 is used to matches the address in the SCYC_ADDR register the Universe II does not respond with ACK64_ since the Special Cycle Generator only processes up to 32 bit cycles The cycle that is produced on the VMEbus uses attributes programmed into the Image Control Register of the image that contains the address programmed in the SCYC_ADDR register Integrated Device Technology Universe II User Manual www idt com May 12 2010 62 3 PCI Interface gt Universe Il as PCI Target The Special Cycle Generator is configured through the register fields shown in Table 7 Figure 7 Register Fields for the Special Cycle Generator e m 32 bit address ADDR in Special Cycle PCI Specifies PCI bus target image address Bus Address Register SCYC_ADDR on page 202 PCI Address Space LAS in Special Cycle Specifies whether the address specified in the ADDR Control Register field lies in PCI memory or I O space SCYC_CTL on page 201 Special cycle SCYC 1 0 in Special Cycle Disabled RMW or ADOH Control Register SCYC_CTL on page 201 32 bit enable EN 31 0 in Special Cycle A bit mask to select the bits to be modified in the Swap Compare Enable VMEbus read data during a RMW cycle Register SCYC EN on page 203 32 bit compare CMP 31 0 in Special Cycle Data which is compared to the VMEbus read data Compare
316. ser Manual www idt com May 12 2010 288 12 Registers gt Register Description 12 3 91 VMEbus Slave Image 1 Bound Address Register VSI1_BD The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register Register name VSI1_BD Register offset OXF1C BD 31 16 Bound Address PWR VME o9 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 289 12 3 92 VMEbus Slave Image 1 Translation Offset VSI1_TO Register name VSI1_TO Register offset OXF20 23 16 TO 31 16 Translation Offset PWR VME EE Integrated Device Technology Universe Il User Manual www idt com May 12 2010 290 12 Registers gt Register Description 12 3 93 VMEbus Slave Image 2 Control VSI2_CTL This register provides the general VMEbus and PCI controls for this slave image Note that only transactions destined for PCI Memory space are decoupled the posted write RXFIFO generates on Memory space transactions on the PCI Bus In order for a VMEbus slave image to respond to an incoming cycle the BM bit in the PCI_CSR register must be enabled The state of PWEN and PREN are ignored if LAS is not programmed memory space Register name VSI2_CTL Register offset OXF28 15 08 Reserved Image Enable PWR VME 0 Disable 1 Enable Posted Write Enable PWR VME 0 Disable 1 Enable R W PWR VME 0 Disable 1 Enab
317. set 0x404 pas es eee a ea 31 24 VBTO VARB VARBTO 23 16 SW SW Reserved ENGBI RE SYSCON V64 15 08 SYSRE SE Reserved T 07 00 Reserved VME Bus Time out 0000 Disable 0001 16 usec 0010232 usec 0011264 usec 0100 128 usec 01012256 usec 01102512 usec 011121024 usec Others Reserved Note The VBTO value has a 4us resolution The time out may occur up to 4us earlier than the selected VBTO period VMEbus Arbitration Mode O Round Robin 1 Priority Integrated Device Technology Universe II User Manual www idt com May 12 2010 274 12 Registers gt Register Description Ce ee 0 em VARBTO VMEbus Arbitration Time out R W 01 00 Disable Timer 01216 us minimum 8ps 102256 us others Reserved SW LRST Software PCI Reset OzNo effect 1 Initiate LRST_ A read always returns 0 SW Software VMEbus SYSRESET SYSRST OzNo effect 1 Initiate SYSRST A read always returns 0 Bl Mode Power up 0 Universe II is not in BI Mode Option 1 Universe II is in Bl Mode Write to this bit to change the Universe Il Bl Mode status This bit is also affected by the global BI Mode initiator VRIRQ1 if this feature is enabled ENGBI Enable Global BI Mode Initiator 0 Assertion of VIRQ1 ignored 1 Assertion of VIRQ1 puts device in Bl Mode RESCIND RESCIND is unused in the Universe II RW do 3 SYSCON SYSCON Power up O Universe Il is not VMEbus System Controller 1 Universe Il is VMEbus System Controller V64AUTO VME64 Auto ID P
318. sfers This slave response time is 127ns During BLT transfers the slave response in the first data beat being both address decode and data transfer is the same as a non block transfer i e 127ns Subsequent data beats however are much faster Response time for these is 50 to 56ns During MBLT transfers the first phase is address only and the slave response is 127ns Subsequent phases are data only and so the slave response is the same as with BLTs i e 50 to 56ns Note that the slave response is independent of the data size D16 non block transfers have a slave response identical to D32 BLT data beats have slave responses identical to MBLT data beats Figure 34 Non Block Decoupled Write Cycle Universe Il as VME Slave VMEbus A 31 1 AM 5 0 LWORD AS D 31 0 WRITE DS0 DS1 DTACK PCI CLK FRAME AD 31 0 C BE 3 0 IRDY TRDY STOP DEVSEL EXE ecu a Integrated Device Technology Universe II User Manual www idt com May 12 2010 344 B Performance gt VME Slave Channel Figure 35 BLT Decoupled Write Cycle Universe Il as VME Slave VMEbus A 31 1 4 AM 5 0 1 AS I D 31 0 WRITE DS0
319. sired perhaps because a higher priority operation is required the STOP REQ bit in the DGCS register can be set This stops all DMA operations on the source bus immediately and set the STOP bit in the same register when the last piece of queued data in the DMA FIFO has been written to the destination bus Attempting to terminate the transfer with the HALT REQ bit has no effect in direct mode operation since this bit only requests the DMA to stop between command packets in linked list mode operation Integrated Device Technology Universe Il User Manual www idt com May 12 2010 96 6 4 6 DMA Controller gt Linked list Mode When the software has detected completion it must verify the status bits in the DGCS register to see the reason for completion If one of the error bits have been set it proceeds into an error handling routine see DMA Error Handling on page 105 If the STOP bit was set the software must take whatever actions were programmed when it set the STOP_REQ bit For example if it was stopped for a higher priority transfer it might record the DLA DVA and DTBC registers and then reprogram them with the higher priority transfer When that has completed it can restore the DVA DLA and DTBC registers to complete the remaining transfers If the DONE bit was set it indicates that the DMA completed its requested transfer successfully and if more transfers are required the software can proceed to Step 2 to start a new transf
320. ss Register LSI7_BS The base address specifies the lowest address in the address range that is decoded Register name LSI7_BS Register offset 0x1E0 Integrated Device Technology Universe II User Manual www idt com May 12 2010 230 12 Registers gt Register Description 12 3 47 PCI Target Image 7 Bound Address Register LSI7_BD The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register If the bound address is 0 then the addresses decoded are those greater than or equal to the base address Register name LSI7_BD Register offset 0x1E4 The bound address for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution PCI Target Images 1 2 3 5 6 and 7 have a 64Kbyte resolution Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 231 12 3 48 PCI Target Image 7 Translation Offset LSI7_TO Address bits 31 16 generated on the VMEbus in response to an image decode are a two s complement addition of address bits 31 16 on the PCI Bus and bits 31 16 of the image s translation offset Register name LSI7_TO Register offset 0x1E8 Integrated Device Technology Universe II User Manual www idt com May 12 2010 232 12 Registers gt Register Description 12 3 49 DMA Transfer Control Register DCTL This register is programmed from either bus or is programmed
321. state following RST_ or SYSRST_ The SYSCON option is loaded during a SYSRST event from the VBG3IN signal SYSFAIL Assertion This power up option causes the Universe II to assert SYSFAIL immediately upon entry into reset The SYSFAIL pin is released through a register access Note that this power up option is over ridden if VME64 Auto ID has been enabled This option is used when extensive on board diagnostics need to be performed before release of SYSFAIL After completion of diagnostics SYSFAIL can be released through software or through initiation of the VME64 Auto ID sequence if enabled see Auto Slot ID VME64 Specified on page 42 PCI Target Image The PCI Target Image power up option provides for default enabling of a PCI target image automatically mapping PCI cycles to the VMEbus The default target image can be mapped with base and bounds at 256MB resolution in Memory or I O space and map PCI transactions to different VMEbus address spaces Beyond the settings provided for in this power up option the target image possesses its other default conditions the translation offset is 0 posted writes are disabled and only 32 bit maximum non block VMEbus cycles in the non privileged data space are generated This option is typically used to access permits the use of Boot ROM on another card in the VMEbus system PCI Register Access A power up option determines if the registers are mapped into Memory or I O space PCI
322. stead of directly from the PCI resources As VMEbus slave the Universe II does not assert RETRY as a termination of the A transaction Universe Il as VMEbus Master The Universe II becomes VMEbus master when the VMEbus Master Interface is internally requested by the PCI Bus Target Channel the DMA Channel or the Interrupt Channel The Interrupt Channel always has priority over the other two channels Several mechanisms are available to configure the relative priority that the PCI Bus Target Channel and DMA Channel have over ownership of the VMEbus Master Interface The Universe II s VMEbus Master Interface generates all of the addressing and data transfer modes documented in the VME64 Specification except A64 and those intended to augment 3U applications The Universe II is also compatible with all VMEbus modules conforming to pre VME64 specifications As VMEbus master the Universe II supports Read Modify Write RMW and Address Only with Handshake ADOH but does not accept RETRY as a termination from the VMEbus slave The ADOH cycle is used to implement the VMEbus Lock command allowing a PCI master to lock VMEbus resources PCI Bus Interface The PCI Interface is a PCI 2 1 Specification compliant interface Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 1 Functional Overview gt Main Interfaces 23 1 2 2 1 Universe Il as PCI Target Read transactions from the PCI bus are always process
323. ster system JTAG controller It resets the Universe II internal JTAG controller If JTAG is not being used this pin should be tied to ground Local Interrupts The Universe II provides eight local bus interrupts only one of which has drive strength that is fully PCI compliant If any of the other seven interrupts are to be used as interrupt outputs to the local bus all eight may be defined as either input or output an analysis must be done on the design to determine whether the 4 mA of drive that the Universe II provides on these lines is sufficient for the design If more drive is required the lines may simply be buffered All Universe II interrupts are initially defined as inputs To prevent excess power dissipation any interrupts defined as inputs should always be driven to either high or low Pull ups should be used for this purpose rather than direct drive since a mis programming of the interrupt registers may cause the local interrupts to be configured as outputs and potentially damage the device Manufacturing Test Pins The Universe II has several signals used for manufacturing test purposes They are listed in Table 24 on page 140 along with the source to which they should be tied Universe Il User Manual Integrated Device Technology May 12 2010 www idt com E Typical Applications gt Decoupling VDD and VSS on the Universe II 371 ES Decoupling Vpp and Vss on the Universe II This section is intended to be a guide for d
324. t The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I O Space forcing all transactions through this image to be coupled Register name LSI1_CTL Register offset 0x114 Sea eae ees i qwe eme erm ee c qoem Reserved ous Reset Description Type Reset by value Image Enable R W All Undefined 0 Disable 1 Enable Posted Write Enable R W All 0x00 0 Disable 1 Enable 23 22 VMEbus Maximum Data width R W All 0b10 00 8 bit data width 01 16 bit data width 10 32 bit data width 11 64 bit data width Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 187 Reset Description Reset by value 18 16 VMEbus Address Space All Undefined 000 A16 001 A24 010 A32 011 Reserved 100 Reserved 101 CR CSR 110 User1 111 User2 e mm LE 8 T 9 Program Data AM Code R W All 0x00 0 Data 1 Program a m 8 E SUPER Supervisor User AM Code R W All 0x00 0 Non Privileged 1 Supervisor wmm L8 ES VMEbus Cycle Type R W All 0x00 0 No BLTs on VMEbus 1 Single BLTs on VMEbus a m0 Ls 8 9 PCI Bus Memory Space R W All Undefined 0 PCI Bus Memory Space 1 PCI Bus I O Space Integrated Device Technology Universe Il User Manual www idt com May 12 2010 188 12 Registers gt Register Description 12 3 13 PCI Target Image 1 Base Address Register LSI1_BS The base address specifies the lowest address in the address range that will be dec
325. t or Master Abort occurs on the source bus while the DMA is reading from the source bus the DMA stops reading from the source bus Any data previously queued within the DMAFIFO is written to the destination bus Once the DMAFIFO empties the error status bit is set and the DMA generates an interrupt if enabled by INT LERR or INT VERR in the DGCS register see DMA Interrupts on page 104 When the error condition VMEbus Error Target Abort or Master Abort occurs on the destination bus while the DMA is writing data to the destination bus the DMA stops writing to the destination bus and it also stops reading from the source bus The error bit in the DGCS register is set and an interrupt asserted if enabled Interrupt Generation During Bus Errors To generate an interrupt from a DMA error there are two bits in the DGCS register and one bit each in the VINT EN and LINT EN registers In the DGCS register the INT LERR bit enables the DMA to generate an interrupt to the Interrupt Channel after encountering an error on the PCI bus The INT VERR enables the DMA to generate an interrupt to the Interrupt Channel upon encountering an error on the VMEbus Upon reaching the Interrupt Channel all DMA interrupts can be routed to either the PCI bus or VMEbus by setting the appropriate bit in the enable registers All DMA sources of interrupts Done Stopped Halted VMEbus Error and PCI Error constitute a single interrupt into the Interrupt Channel
326. t retry to the PCI initiator if the coupled path does not currently own the VMEbus This occurs if the Universe II is not currently VMEbus master or if the DMA is currently VMEbus master or if entries exist in the TXFIFO If the Universe II does not have ownership of the VMEbus when a coupled access is attempted the Universe II generates a target retry with a single wait state See Figure 27 The request for the VMEbus occurs shortly after the cycle is retried Universe Il User Manual Integrated Device Technology May 12 2010 www idt com B Performance gt PCI Slave Channel 337 B 2 1 2 Read Cycles Once the coupled channel owns the VMEbus the Universe II propagates the cycle out to the VMEbus Figure 27 shows such a coupled read cycle against an ideal VME slave There are 10 wait states inserted by the Universe II on the PCI bus before it responds with TRDY Further wait states are inserted for each extra 30ns in slave response Performing 32 bit PCI reads from VME gives a sustained performance of approximately 8 5 MB s Figure 28 shows several of these accesses occurring consecutively Figure 27 Coupled Read Cycle Universe Il as VME Master VMEbus A 31 1 AS i D 31 0 WRITE DS0 DS1 DTACK o PCI CLK FRAME AD 31 0 C BE 3 0
327. ta 1 Program Tee o ee SUPER Supervisor User AM Code R W All 0x00 0 Non Privileged 1 Supervisor wmm em L8 E VMEbus Cycle Type R W All 0x00 0 No BLTs on VMEbus 1 Single BLTs on VMEbus a m0 fa PCI Bus Memory Space R W All Undefined 0 PCI Bus Memory Space 1 PCI Bus I O Space Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 183 12 3 9 PCI Target Image 0 Base Address Register LSIO_BS The base address specifies the lowest address in the address range that will be decoded The base address for PCI Target Image 0 and PCI Target Image 4 have a 4 Kbyte resolution PCI Target Images 1 2 3 5 6 and 7 have a 64 Kbyte resolution Register name LSIO_BS Register offset 0x104 MESS eR ESEsEseseSs Reserved Reset Description Type Reset by value 31 28 BS 31 28 Base Address 27 12 BS 27 12 Base Address Undefined Integrated Device Technology Universe II User Manual www idt com May 12 2010 184 12 Registers gt Register Description 12 3 10 PCI Target Image 0 Bound Address Register LSIO_BD The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register If the bound address is 0 then the addresses decoded are those greater than or equal to the base address The bound address for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution PCI Target Images 1
328. tegrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 331 12 3 127 VMEbus CSR Base Address Register VCSR BS The base address specifies one of 31 available CR CSR windows as defined in the VME64 Specification Each window consumes 512 Kbytes of CR CSR space Register name VCSR_BS Register offset OxFFC PARSE EASES eae BS 23 19 Base Address PWR VME po VCSR_BS register is accessed with an 8 bit transfer Bits 31 27 of the register are compared with address lines 23 19 Integrated Device Technology Universe II User Manual www idt com May 12 2010 332 12 Registers gt Register Description Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 333 A Packaging Information This appendix discusses the following topics e 313 Pin PBGA Package on page 333 A 1 313 Pin PBGA Package Figure 25 313 PBGA Bottom View 22 i E i e E i E k L a 7 j E B Zz EE M _ pee 20 4 Integrated Device Technology Universe II User Manual www idt com May 12 2010 334 A Packaging Information gt 313 Pin PBGA Package Figure 26 313 PBGA Top and Side View EF Eg 4 ONER ee 3 f piles
329. tegrated Device Technology www idt com Universe Il User Manual May 12 2010 3 PCI Interface gt Universe II as PCI Target 63 Once the RMW cycle completes the VMEbus read data is returned to the waiting PCI bus master and the PCI cycle terminates RMW Constraints Certain restrictions apply to the use of RMW cycles If a write transaction is initiated to the VMEbus address when the special cycle field SCYC in Special Cycle Control Register SCYC_CTL on page 201 is set for RMW then a standard write occurs with the attributes programmed in the PCI target image in other words the special cycle generator is not used The Universe II performs no packing and unpacking of data on the VMEbus during a RMW operation The following constraints must also be met 1 The Special Cycle Generator only generates a RMW if it is accessed with an 8 bit aligned 16 bit or aligned 32 bit read cycle 2 The Special Cycle Generator only generates a RMW if the size of the request is less than or equal to the programmed VMEbus Maximum Data width 3 The destination VMEbus address space must be one of A16 A24 or A32 In the event that the Special Cycle Generator is accessed with a read cycle that does not meet the RMW criteria the Universe II generates a Target Abort The Universe II must be correctly programmed and accessed with correct byte lane information 3 4 5 2 VME Lock Cycles Exclusive Access to VMEbus Resources The VME Lock cycle
330. tegrated Device Technology Universe Il User Manual www idt com May 12 2010 170 12 Registers gt Register Map Table 34 Universe Il Register Map Continued Offset Register Name OxFC4 VMEbus Slave Image 6 Translation Offset VSI6_TO on page 323 VSI6_TO OxFC8 Reserved OxFD8 VMEbus Slave Image 7 Translation Offset VSI7 TO on page 328 VSI7 TO OxFCC VMEbus Slave Image 7 Control VSI7_CTL on page 324 VSI7_CTL OxFDO VMEbus Slave Image 7 Base Address Register VSI7 BS on VSI7 BS page 326 OxFD4 VMEbus Slave Image 7 Bound Address Register VSI7 BD on VSI7 BD page 327 OxFDC OxFEC Reserved OxFFO VME CR CSR Reserved OxFF4 VMEbus CSR Bit Clear Register VCSR CLR on page 329 VCSR CLR OxFF8 VMEbus CSR Bit Set Register VCSR SET on page 330 VCSR SET OxFFC VMEbus CSR Base Address Register VCSR BS on page 331 VCSR BS Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 171 12 3 Register Description The following tables describe the Universe II registers 12 3 1 PCI Configuration Space ID Register PCI ID Register name PCI VID Register offset 0x00 Reset Description Type Reset by value 31 16 DID 15 0 Device ID 0x10E3 IDT allocated device identifier 15 00 VID 15 0 Vendor ID 0x10E3 PCI SIG allocated vendor identifier Note IDT acquired Tundra Semiconductor Integrated Device Technology Universe II User Man
331. ter VSIO BD on VSIO BD page 283 OxFOC VMEbus Slave Image 0 Translation Offset VSIO TO on page 284 VSIO TO OxF10 Reserved OxF14 VMEbus Slave Image 1 Control VSI1_CTL on page 285 VSH_CTL OxF18 VMEbus Slave Image 1 Base Address Register VSI1_BS on VSH_BS page 287 OxF1C VMEbus Slave Image 1 Bound Address Register VSI1_BD on VSH BD page 288 OxF20 VMEbus Slave Image 1 Translation Offset VSI1 TO on page 289 vVSH TO OxF24 Reserved OxF28 VMEbus Slave Image 2 Control VSI2 CTL on page 290 VSI2 CTL OxF2C VMEbus Slave Image 2 Base Address Register VSI2 BS on VSI2 BS page 292 OxF30 VMEbus Slave Image 2 Bound Address Register VSI2 BD on VSI2 BD page 293 OxF34 VMEbus Slave Image 2 Translation Offset VSI2 TO on page 294 vSl2 TO OxF38 Reserved OxF48 VMEbus Slave Image 3 Translation Offset VSI3_TO on page 299 VSI3_TO OxF3C VMEbus Slave Image 3 Control VSI3_CTL on page 295 VSI3 CTL OxF40 VMEbus Slave Image 3 Base Address Register VSI8 BS on VSI3 BS page 297 OxF44 VMEbus Slave Image 3 Bound Address Register VSI3_BD on VSI3_BD page 298 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Map 16 Te Table 34 Universe Il Register Map Continued Offset OxF4C 0xF60 OxF64 OxF68 OxF6C OxF70 OxF74 OxF78 0xF7C Register Name Reserved Location Monitor Control Re
332. ter Description 12 3 50 DMA Transfer Byte Count Register DTBC This register specifies the number of bytes to be moved by the DMA before the start of the DMA transfer or the number of remaining bytes in the transfer while the DMA is active This register is programmed from either bus or is programmed by the DMA Controller when it loads a command packet from a linked list Register name DTBC Register offset 0x204 23 16 DTBC 15 08 DTBC 07 00 DTBC In direct mode the user must re program the DTBC register before each transfer When using the DMA to perform linked list transfers it is essential that the DTBC register contains a value of zero before setting the GO bit of the DGCS register or undefined behaviors may occur Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 235 12 3 51 DMA PCI Bus Address Register DLA This register is programmed from either bus or by the DMA Controller when it loads a command packet In direct mode the user must reprogram the DLA register before each transfer In linked list mode this register is only updated when the DMA is stopped halted or at the completion of processing a command packet Register name DLA Register offset 0x208 LA 31 3 PCI Bus Address LA 2 0 PCI Bus Address Address bits 2 0 must be programmed the same as those in the DVA After a Bus Error a Target Abort or a Master Abort the
333. terface The VME Interface is a VME64 Specification compliant interface Universe Il as VMEbus Slave The Universe II VMEbus Slave Channel accepts all of the addressing and data transfer modes documented in the VME64 Specification except A64 and those intended to augment 3U applications Incoming write transactions from the VMEbus can be treated as either coupled or posted depending upon the programming of the VMEbus slave image see VME Slave Image Programming on page 67 With posted write transactions data is written to a Posted Write Receive FIFO RXFIFO and the VMEbus master receives data acknowledgment from the Universe II Write data is transferred to the PCI resource from the RXFIFO without the involvement of the initiating VMEbus master see Posted Writes on page 33 for a full explanation of this operation With a coupled cycle the VMEbus master only receives data acknowledgment when the transaction is complete on the PCI bus This means that the VMEbus is unavailable to other masters while the PCI bus transaction is executed Read transactions may be either prefetched or coupled A prefetched read is initiated when a VMEbus master requests a block read transaction BLT or MBLT and this mode is enabled When the Universe II receives the block read request it begins to fill its Read Data FIFO RDFIFO using burst transactions from the PCI resource The initiating VMEbus master then acquires its block read data from the RDFIFO in
334. terface gt Universe Il as VMEbus Master 29 Table 1 VMEbus Address Modifier Codes 0x3B A24 non privileged block transfer BLT 0x38 A24 non privileged 64 bit block transfer MBLT 0x35 A40 lock command LCk 0x21 2eVME for 3U bus modules address size in XAM code 0x20 2eVME for 6U bus modules address size in XAM code OxF A32 supervisory block transfer BLT Ce emememeeemm O Oe NN 9s e emee O Integrated Device Technology Universe II User Manual www idt com May 12 2010 30 2 3 2 2 VMEbus Interface gt Universe II as VMEbus Master The Universe II generates Address Only with Handshake ADOH cycles in support of lock commands for A16 A24 and A32 spaces ADOH cycles can only be generated through the Special Cycle Generator see Special Cycle Generator on page 61 There are two User Defined AM codes that can be programmed through the User AM Codes Register USER AM on page 276 The USER AM register can only be used to generate and accept AM codes 0x10 through Ox1F The default USER AM code is 0x10 These AM codes are designated as USERAM codes in the VMEbus Specification After power up the two values in the USER AM register default to the same VME64 User defined AM code If USER AM code is used with the VMEbus Slave Interface the cycles must use 32 bit addressing and only single cycle accesses are used BLTs and MBLTS with USER AM codes will lead to unpredictable behavior Data Transfer Cap
335. the MAST_CTL register is set see Using the VOWN bit on page 64 During DMA operations the Universe II attempts block transfers to the maximum length permitted by the VMEbus specification 256 bytes for BLT 2 Kbytes for MBLT and is limited by the VON counter see DMA VMEbus Ownership on page 91 The Universe II provides indivisible transactions with the VMEbus lock commands and the VMEbus ownership bit see VME Lock Cycles Exclusive Access to VMEbus Resources on page 63 Cycle Terminations The Universe II accepts BERR or DTACK as cycle terminations from the VMEbus slave It does not support RETRY The assertion of BERR indicates that some type of system error occurred and the transaction did not complete properly The assertion of BERR during an IACK also causes the error to be logged A VMEbus BERR received by the Universe II during a coupled transaction is communicated to the PCI master as a Target Abort No information is logged if the Universe II receives BERR in a coupled transaction If an error occurs during a posted write to the VMEbus or during an IACK cycle the Universe II uses the VMEbus AM Code Error Log V AMERR on page 307 to log the AM code of the transaction AMERR 5 0 and the state of the IACK signal IACK bit to indicate whether the error occurred during an IACK cycle The current transaction in the FIFO is purged The V AMERR register also records if multiple errors have occurred wit
336. the SERR signal for one clock cycle and setting the S SERR Signalled SERR bit in the PCI CSR register Assertion of SERR can be disabled by clearing the SERR EN bitin the PCI CSR register No interrupt is generated and regardless of whether assertion of SERR is enabled or not the Universe II does not respond to the access with DEVSEL_ Typically the master of the transaction times out with a Master Abort As a master the Universe II does not monitor SERR It is expected that a central resource on the PCI bus monitors SERR and takes appropriate action Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 129 9 Resets Clocks and Power up Options This chapter highlights utility functions in the Universe II This chapter discusses the following topics e Resets on page 129 e Power Up Options on page 135 e Test Modes on page 141 e Clocks on page 142 9 1 Overview The Universe II has many programmable reset options and power up options that impact the functionality of the device 9 2 Resets The Universe II provides a number of pins and registers for reset support Pin support is summarized in Table 19 Table 19 Hardware Reset Mechanisms Interface and Direction Long Name VMEbus Input VRSYSRST VMEbus Reset Input Asserts LRST_ on the local bus resets the Universe Il and re configures power up options VMEbus Output VXSYSRST VMEbus System Universe ll output for SYSRST
337. the Special Cycle Generator on an address no other process accesses this address Before performing a Special Cycle a process would be required to obtain the semaphore This process would hold the semaphore until the Special Cycle completes A separate process that intends to modify the same address would need to obtain the semaphore before proceeding it need not verify the state of the SCYC 1 0 bit This mechanism requires that processes know which addresses might be accessed through the Special Cycle Generator Each of the four semaphores in a semaphore register are intended to be accessed with 8 bit transfers Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 85 6 DMA Controller Direct memory access DMA allows a transaction to occur between two devices without involving the host processor for example a read transaction between a peripheral device and host processor memory Because less time is required to complete transactions applications that contain one or more DMA channels support faster read and write transfers than applications that support only host assisted transactions This chapter discusses the following topics e DMA Registers on page 85 Direct Mode Operation on page 93 e Linked list Mode on page 96 e FIFO Operation and Bus Ownership on page 101 e DMA Interrupts on page 104 e DMA Channel Interactions with Other Channels on page 105 e DMA Error H
338. the cycle is mapped to the PCI bus There is also a translation offset added to the 24 bit VMEbus address to produce a 32 bit PCI bus address which is programmed in the VMEbus CSR Translation Offset VCSR TO on page 306 The registers in the UCSR space are located as address offsets from VCSR BS These offsets are different from those used in the VRAI mechanisms where the first register in the UCSR has address offset of zero see Table 34 on page 164 When accessing the UCSR in CR CSR space the first register has an address offset of 508 Kbytes 512 Kbytes minus 4 Kbytes A simple approach for determining the register offset when accessing the UCSR in CR CSR space is to add 508 Kbytes 0x 7F000 to the address offsets given in Table 34 on page 164 RMW and ADOH Register Access Cycles The Universe II supports RMW and ADOH accesses to its registers A read modify write RMW cycle allows a VMEbus master to read from a VMEbus slave and then write to the same resource without relinquishing VMEbus tenure between the two operations The Universe II accepts RMW cycles to any of its registers This prevents an external PCI Master from accessing the registers of the Universe II until VMEbus AS is asserted This is useful if a single RMW access to the ADOH is required If a sequence of accesses to the Universe registers must be performed without intervening PCI access to UCSR is required then the VMEbus master should lock the Universe II through the
339. the system Figure 40 Universe II Connections to the VMEbus Through TTL Buffers Universe VMEbus A 31 1 VOE_ LWORD VA_DIR VA 31 1 LWORD D 31 0 VD DIR VD 31 0 AM 5 0 VAM_DIR VAMI S5 0 VWRITE VIACK VAS VAS DIR WRITE IACK VDSO_ AS VDS1_ DS 1 0 VDS_DIR VDTACK_ DTACK VSLAVE_DIR SYSCLK_ SYSCLK VBCLR_ BCLR VSCON_DIR Universe Il User Manual Integrated Device Technology May 12 2010 www idt com E Typical Applications gt VME Interface 365 Figure 41 Universe Il Connections to the VMEbus Through TTL Buffers Universe as VMEbus VXBBSY BBSY VRBBSY VRACFAIL ACFAIL VXSYSFAIL SYSFAIL VRSYSFAIL VXSYSRST SYSRST VRSYSRST_ VXBERR BERR VRBERR VXIRQ 7 1 IRQ 7 1 VRIRQ 7 1 VXBR 3 0 BR 3 0 VRBR 3 0 VBGIN 3 0 BG 3 0 IN VBGOUT 3 0 BG 3 0 OUT VIACKIN IACKIN VIACKOUT IACKOUT 245 SN74VMEH22501 TI 241 optional U14 and U16 were originally 642 buffers but the 642 buffer is now obsolete IDT recommends any other open drain buffer as a replacement such as a F06 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 366 E Typical Applications gt VME Interface The Universe II with the addition of external transceivers is designed to meet the timing requirements of the VME specification Refer to the VME64 specification ANSI VITA 1 0 for details on the VME timing In order to meet the req
340. through its PCI Master Interface The PCI Master Interface is available to either the VMEbus Slave Channel access from a remote VMEbus master or the DMA Channel The VMEbus Slave Channel makes an internal request for the PCI Master Interface when the following conditions are met e RXFIFO contains a complete transaction e Sufficient data exists in the RXFIFO to generate a transaction of length defined by the programmable aligned burst size PABS e There is a coupled cycle request The DMA Channel makes an internal request for the PCI Master Interface when the following conditions are met e DMAFIFO has room for 128 bytes to be read from PCI e DMAFIFO has queued 128 bytes to be written to PCI e DMA block is completely queued during a write to the PCI bus Integrated Device Technology Universe Il User Manual www idt com May 12 2010 54 3 3 1 3 PCI Interface gt Universe ll as PCI Master Arbitration between the two channels for the PCI Master Interface follows a round robin protocol Each channel is given access to the PCI bus for a single transaction Once that transaction completes ownership of the PCI Master Interface is granted to the other channel if it requires the bus The VMEbus Slave Channel and the DMA Channel each have a set of rules that determine when the transaction is complete and the channels no longer need the PCI Master Interface The VMEbus Slave Channel no longer needs the PCI Master Interface under the
341. ting information Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 181 12 3 8 PCI Target Image 0 Control LSIO_CTL In the PCI Target Image Control register setting the VCT bit will only have effect if the VAS bits are programmed for A24 or A32 space and the VDW bits are programmed for 8 bit 16 bit or 32 bit If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64 bit the Universe II may perform MBLT transfers independent of the state of the VCT bit The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I O Space forcing all transactions through this image to be coupled Register name LSIO_CTL Register offset 0x100 a es eee ese eee ee Sere oe eee ere we mem y Reserved BE Reset Description Type Reset by value Image Enable R W All Undefined 0 Disable 1 Enable Posted Write Enable R W All 0x00 0 Disable 1 Enable 23 22 VMEbus Maximum Data width R W All 0b10 00 8 bit data width 01 16 bit data width 10 32 bit data width 11 64 bit data width Integrated Device Technology Universe II User Manual www idt com May 12 2010 182 12 Registers gt Register Description Reset Description Type Reset by value 18 16 VMEbus Address Space R W All Undefined 000 A16 001 A24 010 A32 011 Reserved 100 Reserved 101 CR CSR 110 User1 111 User2 a fa T 9 Program Data AM Code R W All 0x00 0 Da
342. to the VMEbus the Universe II uses the VMEbus AM Code Error Log V AMERR on page 307 to log the AM code of the transaction in the AMERR field The state of the IACK signal is logged in the IACK bit to indicate whether the error occurred during an IACK cycle The address of the errored transaction is latched in the V AERR register Table 12 3 108 An interrupt is generated on the VMEbus and or PCI bus depending upon whether the VERR interrupts are enabled see Interrupt Generation and Handling on page 109 The remaining entries of the transaction are removed from the FIFO If the error occurs during a posted write to the PCI bus the Universe II uses the PCI Command Error Log Register L_CMDERR on page 210 to log the command information for the transaction CMDERR 3 0 The address of the errored transaction is latched in the PCI Address Error Log LAERR on page 211 An interrupt is generated on the VMEbus and or PCI bus depending upon whether the VERR and LERR interrupts are enabled see Interrupt Generation and Handling on page 109 Under either of the conditions VMEbus to PCI or PCI to VMEbus the address that is stored in the log represents the most recent address the Universe II generated before the bus error was encountered For single cycle transactions the address represents the address for the actual errored transaction However for multi data beat transactions block transfers on the VMEbus or burst transactions
343. tputs 114 Table 18 Internal Interrupt ROUDE sro ieaiai ara i E E a a een a E 118 Table 19 Hardware Reset Mechanisms esse ek obese 9a R3 eek een E E RE Se shes cade 129 Table 20 Software Reset Mechanism 6 03 acid deena adios RR wed Gs Serre nea ose Rol CESSARE UP ENIRO E DICES 130 Table 21 Functions Affected by Reset Initiators 2 ee 132 Table 22 Power Up Options s sages deh iawtis he bk bh IPUCLPPPIXA Sed ees de eda doe Foe ee E deed eee 135 Table 23 VRAI Base Address Power up Options 0 0 0 0 ee eee teens 137 Table 24 Manufacturing Pin Requirements for Normal Operating Mode 0 0 0 e eee eee 140 Table 25 Test Mode Operation ss renessanse pisini as er epe fdas beg re ermine eS ocd uw ble Rec br kip dr d d ses 141 Table 26 VMEbus Signals 5s cssaea eres oat hak osea RE a Ea E dos ERR nes eee E Po ER ORO AR heed be pie d d 144 Tabl 27 PClBusSignalS i cis cen p RR dobar eee ook GE RE e eee kes pla CREDO dae UR UE PR OR bal e qna Ke 147 Table 28 Non PCI Electrical Characteristics 0 0 0 0 e 153 Table 29 AC DC PCI Electrical Characteristics leeeeeeeeeeeeeeeee eee eens 154 Table 30 Pin List and DC Characteristics for Universe II Signals leeeeeeeeeeeeeeeee eee 155 Table 31 Operating Conditions i ie deett e n mere mec ee Rennes ew e ER eh etr a Rea rere ee Rd 160 Table 32 Absolute Maximum Ratings 0 0 e heh e 161 Table33 Power Dissipation eese die iterates t t tete
344. transfer While the DMA is active the registers are locked against any changes so that any writes to the registers will have no impact In direct mode operation these registers are programmed directly In linked list operation they are repeatedly loaded by the Universe II from command packets residing in PCI memory until the end of the linked list is reached see Linked list Mode on page 96 Source and Destination Addresses The source and destination addresses for the DMA reside in two registers the DMA PCI Bus Address Register DLA on page 235 and the DMA VMEbus Address Register DVA on page 236 The determination of which is the source address and which is the destination is made by the L2V bit in the DMA Transfer Control Register DCTL on page 232 When set the DMA transfers data from the PCI to the VMEbus The DLA becomes the PCI source register and DVA becomes the VMEbus destination register When cleared the DMA transfers data from the VMEbus to PCI bus and DLA becomes the PCI destination register DVA becomes the VMEbus source register The PCI address may be programmed to any byte address in PCI Memory space It cannot transfer to or from PCI I O or Configuration spaces The VMEbus address can also be programmed to any byte address and can access any VMEbus address space from A16 to A32 in supervisory or non privileged space and data or program space The setting of address space A16 A24 or A32 is prog
345. turn asserts the local LINT if enabled Whereas the Internal Interrupt Handler implies a delay between assertion of an interrupt condition to the Universe II and the Universe s mapping of the interrupt all other interrupt sources get mapped immediately to their destination assertion of LINT_ immediately causes an IRQ assertion of ACFAIL immediately causes an LINT etc Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 7 Interrupt Generation and Handling gt Interrupt Generation 111 7 2 Interrupt Generation The Universe II has the ability to generate interrupts on both the PCI bus and VMEbus 7 2 1 PCI Interrupt Generation The Universe II expands on the basic PCI specification which permits single function devices to assert only a single interrupt line Eight PCI interrupt outputs provide maximum flexibility although if full PCI compliancy is required all interrupt sources can be routed to a single PCI interrupt output PCI interrupts may be generated from multiple sources e VMEbus sources of PCI interrupts IRQ 7 1 SYSFAIL ACFAIL internal sources of PCI interrupts DMA VMEbus bus error encountered PCI Target Abort or Master Abort encountered VMEbus ownership has been granted while the VOWN bit is set see VME Lock Cycles Exclusive Access to VMEbus Resources on page 63 Software interrupt Mailbox access Location monitor access
346. ual www idt com May 12 2010 172 12 Registers gt Register Description 12 3 2 PCI Configuration Space Control and Status Register PCI CSR Register name PCI CSR Register offset 0x004 eed ee RORIS eee 23 16 TFBBC PCI Reserved 15 08 PCI Reserved MFBBC SERR EN Detected Parity Error R Write 1 This bit is always set by the Universe Il when the PCI to Clear master interface detects a data parity error or the PCI target interface detects address or data parity errors OxNo parity error 1 Parity error Signalled SERR R Write 1 The Universe II PCI target interface sets this bit when to Clear it asserts SERR to signal an address parity error SERR EN must be set before SERR_ can be asserted O SEHRR not asserted 1 SERR_ asserted Received Target Abort R Write 1 The Universe Il PCI master interface sets this bit to Clear when a transaction it initiated was terminated with a Target Abort 0 Master did not detect Target Abort 1 Master detected Target Abort Signalled Target Abort R Write 1 0 Target did not terminate transaction with to Clear Target Abort 1 Target terminated transaction with Target Abort Received Master Abort R Write 1 The Universe Il PCI master interface sets this bit to Clear when a transaction it initiated had to be terminated with a Master Abort 0 Master did not generate Master Abort 1 Master generated Master Abort Universe Il User Manual Integrated Device Technology May 12
347. uirements outlined in this specification the external transceivers must meet certain characteristics as outlined in Table 45 Table 44 VMEbus Signal Drive Strength Requirements VME bus Signal Required Drive Strength A 81 1 D 31 0 AM 5 0 IACK LWORD WRITE DTACK IOL gt 48mA IOH 3mA AS DS 1 0 IOL gt 64mA IOH gt 3mA SYSCLK IOL gt 64mA IOH gt 3mA BR 8 0 BSY IRQ 7 0 BERR SYSFAIL SYSRESET IOL2 48mA Table 45 VMEbus Transceiver Requirements Parameter From To Timing Input Output Min Max VA VD VAM VIACK VLWORD VWRITE VAS VDSx VDTACK skew pkg to pkg A B 8 ns skew pkg to pkg B A 4 ns Prop DIR A 1 ns 5ns Prop DIR B 2ns 10ns Cin A 25 pf a There are no limits on propagation delay or skew on the remaining buffered VME signals VSYSCLK VBCLR VXBBSY VRBBSY VRACFAIL VXSYSFAIL VRSYSFAIL VXSYSRST VRSYSRST VXBERR VRBERR VXIRQ VRIRQ VXBR VRBR F Series transceivers meet the requirements specified in Table 44 and Table 45 A faster family such as ABT may also be used Care should be taken in the choice of transceivers to avoid ground bounces and also to minimize crosstalk incurred during switching To limit the effects of crosstalk the amount of routing under these transceivers must be kept to a minimum Daisy chain signals can be especially susceptible to crosstalk Universe Il User Manual Integrated Device Technology May 12 2010 www idt com E Typical Applications gt VME Int
348. umber e VMEbus Address 15 11 identifies the PCI Device Number e VMEbus Address 23 16 does not match the BUS NO in MAST CTL register and e VMEbus Address 31 24 are mapped directly through to the PCI bus Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 2 VMEbus Interface gt VMEbus Configuration 41 2 5 2 5 1 2 5 2 VMEbus Configuration The Universe II provides the following functions to assist in the initial configuration of the VMEbus system e First Slot Detector Register Access at Power up Auto Slot ID two methods First Slot Detector As specified by the VM E64 Specification the First Slot Detector module on the Universe II samples BG3IN immediately after reset to determine whether the Universe II s host board resides in slot 1 The VME64 Specification requires that BG 3 0 lines be driven high after reset This means that if a card is preceded by another card in the VMEbus system it always sample BG3IN high after reset BG3IN can only be sampled low after reset by the first card in the system there is no preceding card to drive BG3IN high If BG3IN is sampled at logic low immediately after reset due to the Universe II s internal pull down then the Universe II s host board is in slot 1 and the Universe II becomes SYSCON otherwise the SYSCON module is disabled This mechanism may be overridden by software through clearing or setting the SYSCON bit in the Misc
349. umbers M and G represent MHz and GHz For transfer rate numbers M and G represent Mbps and Gbps e E Operating environment in which the product is guaranteed This code may be one of the following characters C Commercial temperature range 0 to 70 C I Industrial temperature range 40 to 85 C E Extended temperature range 55 to 125 C e P The Package type of the product B Ceramic ball grid array CBGA E L J and K Plastic ball grid array PBGA G Ceramic pin grid array CPGA M Small outline integrated circuit SOIC Q Plastic quad flatpack QFP Universe Il User Manual Integrated Device Technology May 12 2010 www idt com F Ordering Information gt Ordering Information 375 e G IDT Tsi products fit into three RoHS compliance categories Y RoHS Compliant 60f6 These products contain none of the six restricted substances above the limits set in the EU Directive 2002 95 EC Y RoHS Compliant Flip Chip These products contain only one of the six restricted substances Lead Pb These flip chip products are RoHS compliant through the Lead exemption for Flip Chip technology Commission Decision 2005 747 EC which allows Lead in solders to complete a viable electrical connection between semiconductor die and carrier within integrated circuit Flip Chip packages V RoHS Compliant Green These products follow the above definitions for RoHS Com
350. ure sequential consistency prefetched reads coupled reads and coupled write operations are only processed once all previously posted write operations have completed the RXFIFO is empty Figure 4 VMEbus Slave Channel Dataflow PREFETCHED READ DATA PCI BUS VMEbus MASTER SLAVE INTERFACE COUPLED WRITE DATA INTERFACE POSTED WRITE DATA RXFIFO Incoming cycles from the VMEbus can have data widths of 8 bit 16 bit 32 bit and 64 bit Although the PCI bus supports only two port sizes 32 bit and 64 bit the byte lanes on the PCI bus can be individually enabled which allows each type of VMEbus transaction to be directly mapped to the PCI data bus In order for a VMEbus slave image to respond to an incoming cycle the PCI Master Interface must be enabled by setting the bit BM in the PCI Configuration Space Control and Status Register PCI CSR on page 172 If data is queued in the VMEbus Slave Channel FIFO and the BM bit is cleared the FIFO empties but no additional transfers are received 2 4 1 Coupled Transfers A coupled transfer means that no FIFO is involved in the transaction and handshakes are relayed directly through the Universe II Coupled mode is the default setting for the VMEbus slave images Coupled transfers only proceed once all posted write entries in the RXFIFO have completed see Posted Writes on page 33 Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 2 VMEbus Interface gt
351. uring a transaction initiated by a VMEbus block transfer all data subsequent to the errored data beat in the block transfer is flushed from the RXFIFO In the case of BLTs this implies that potentially all data up to the next 256 byte boundary may be flushed For MBLTs all data up to the next 2 KByte boundary may be flushed Once an error is captured in a log that set of registers is frozen against further errors until the error is acknowledged The log is acknowledged and made available to latch another error by clearing the corresponding status bit in the VINT STAT or LINT STAT registers if a second error occur before the CPU has the opportunity to acknowledge the first error another bit in the logs is set to indicate this situation M ERR bit 8 3 2 Prefetched Reads In response to a block read from the VMEbus the Universe II initiates prefetching on the PCI bus if the VMEbus slave image is programmed with this option see VME Slave Image Programming on page 67 The transaction generated on the PCI bus is an aligned memory read transaction with multiple data beats extending to the aligned burst boundary as programmed by PABS in the Master Control Register MAST_CTL on page 271 Once an acknowledgment is given for the first data beat an acknowledgment is sent to the VMEbus initiator by the assertion of DTACK Therefore the first data beat of a prefetched read is coupled while all subsequent reads in the transaction are decoup
352. ustained perf 64 byte PABS D64 MBLT VME cycle time sustained performance 32 byte PABS sustained perf 64 byte PABS B Performance Performance Summary Performance 8 PCI clocks 9 PCI clocks 180 ns 23 Mbytes s 43 Mbytes s 119 ns 32 Mbytes s 35 Mbytes s 119 ns 53 Mbytes s 59 Mbytes s Table 37 VME Slave Channel Performance Performance VME Slave Response ns Cycle Type Coupled Read non block DS2BLT D64BLT Coupled Write non block DS2BLT D64BLT Universe Il User Manual Integrated Device Technology www idt com B Performance gt Performance Summary 353 Table 37 VME Slave Channel Performance Cycle Type Pre fetched Read VME slave response 1st data beat VME slave response other data beats Decoupled Write non block slave response block slave response 1st data beat block slave response other data beats Table 38 DMA Channel Performance Cycle Type PCI Reads 32 byte PABS 64byte PABS PCI Writes 32 byte PABS 64byte PABS VME Reads non block D32 D32 BLT D64 MBLT VME Writes non block D32 D32BLT D64 MBLT a 64 bit PCI performance in brackets Integrated Device Technology www idt com Performance VME Slave VME Slave Response ns ns Performance Mbytes s 97 194 118 236 98 196 125 250 Universe II User Manual May 12
353. uts are latched by the Universe II to determine the mode of operation The Universe II remains in this mode until the TMODE 2 0 inputs have changed and a reset event has occurred PLL_TESTSEL must be high for any test mode Table 25 Test Mode Operation Operation Mode TMODE 2 0 PLL_TESTSEL Normal Mode 000 0 Accelerate 001 0 PLL Test 010 1 Scan Mode 011 1 NAND Tree Simulation 100 1 RAM Test 101 1 High Impedance 110 0 1 Reserved 111 1 For NAND Tree Simulation the values of the TMODE pins are latched during the active part of PWRRST These pins can change state during the NAND Tree tests The timers are always accelerated in this mode All outputs are tristated in this mode except for the VXSYSFAIL output pin For High Impedance mode the values of the TMODE pins are also latched during the active part of PWRRST All outputs are tristated in this mode except for the VXSYSFAIL output pin 9 4 2 JTAG support The Universe II includes dedicated user accessible test logic that is fully compatible with the IEEE 1149 1 Standard Test Access Port TAP and Boundary Scan Architecture This standard was developed by the Test Technology Technical Committee of IEEE Computer Society and the Joint Test Action Group JTAG The Universe II s JTAG support includes e five pin JTAG interface TCK TDI TDO TMS and TRST e JTAG TAP controller e three bit instruction register Integrated Device Technology Univer
354. value in the DLA register must not be used to reprogram the DMA because it has no usable information Some offset from its original value must be used Integrated Device Technology Universe Il User Manual www idt com May 12 2010 236 12 Registers gt Register Description 12 3 52 DMA VMEbus Address Register DVA This register is programmed from either bus or is programmed by the DMA Controller when it loads a command packet In direct mode the user must reprogram the DVA register before each transfer In linked list operation this register is only updated when the DMA is stopped halted or at the completion of processing a command packet Register name DVA Register offset 0x210 VMEbus Address Address bits 2 0 must be programmed the same as those in the DLA After a bus error a Target Abort or a Master Abort the value in the DVA register must not be used to reprogram the DMA because it has no usable information Some offset from its original value must be used Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 12 Registers gt Register Description 237 12 3 53 DMA Command Packet Pointer DCPP This register contains the pointer into the current command packet Initially it is programmed to the starting packet of the linked list and is updated with the address to a new command packet at the completion of a packet The packets must be aligned to a 32 byte address Register name DC
355. vidually maskable and can be mapped to various interrupt outputs Most interrupt sources can be mapped to one particular destination bus The PCI sources LINT 7 0 can only be mapped to the VMEbus interrupt outputs The VMEbus sources VIRQ 7 1 are not mapped to the PCI bus interrupts However the VIRQ 7 1 bits are status bits which indicate whether or not a STATUS ID vector has been acquired This indication can be used to generate an interrupt on the PCI bus Some internal sources for example error conditions or DMA activity can be mapped to either bus Integrated Device Technology Universe II User Manual www idt com May 12 2010 110 7 Interrupt Generation and Handling gt Overview Figure 18 Universe Interrupt Circuitry Mapping VRACFAIL_ VRSYSFAIL_ amp Internal Interrupt VRIQ 7 1 and Enabling Handler Internal LINT 7 0 Sources Mapping 974 VXIRQ 7 and Enabling Figure 18 illustrates the circuitry inside the Universe II Interrupt Channel The PCI hardware interrupts are listed on the left and the VMEbus interrupt inputs and outputs are on the right Internal interrupts are also illustrated The figure shows that the interrupt sources may be mapped and enabled The Internal Interrupt Handler is a block within the Universe II that detects assertion of the VRIRQ 7 1 pins and generates the VME IACK through the VME Master Upon completion of the IACK cycle the Internal Interrupt Handler notifies the Mapping Block which in
356. vrirq 7 VDD frame ad 13 VDD gnt 17 18 va 12 va 17 va 16 VDD vxira 3 vbgo 2 vracfail_ ad 3 VDD ad 45 stop req64_ 18 19 va va 18 va 23 VDD vxirq 1 VDD ad 33 ad 2 ad 35 VDD rst_ ad 12 ad 46 19 20 va 19 va 21 va 22 vrirq 2 int 0 vbgo 0 vrirq 6 ad 5 ad 39 ad 43 ad 11 ad 44 20 21 va 15 Ivrsysrst_ va 28 va 27 vrirq 4 viacko_ vbgi_ 0 VDD ad 38 ad 41 tmode t ad 10 enid 21 22 va 20 VDD va 29 vrirq 1 req_ vxirq 6 ad 1 ad 4 vme res ad 40 ad 8 ad 42 22 et 23 vxsysrst clk64 va 25 vxbr 3 VDD vxirq 5 vbgi 3 ad 34 ad 36 tmode 2 lock VDD viacki 23 24 VDD va 30 va 31 vxbr 1 vxirq 2 vbgo 3 vxbr 2 vss vss VDD ad 7 VDD 24 25 va 24 va 26 vrirq 3 vxbr 0 vxirg 4 vbgo 1 vbgi 2 vxirq 7 VDD ad 37 ad 6 vss ad 9 25 Integrated Device Technology Universe Il User Manual www idt com May 12 2010 152 10 Signals and Pinout gt Pin out Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 11 11 1 11 1 1 Electrical Characteristics This chapter discusses the following topics DC Characteristics on page 153 e Operating Conditions on page 160 e Power Dissipation on page 161 DC Characteristics Non PCI Characteristics Table 28 specifies the required DC characteristics of all non PCI signals pins Table 28 Non PCI Electrical Characteristics Symbols Test conditions VIH TTL Voltage Input high Vout 0 1V or Vpp 0 1V 2 2 V
357. which signifies Memory space e When VA 1 is sampled high at power up the PCI BSO register s SPACE register s bit is set to 0 which signifies Memory space and the PCI_BS1 register s SPACE bit is set to 1 which signifies I O space i Universe II registers are not prefetchable and do not accept burst writes Conditions of Target Retry Attempts to access UCSR space from the PCI bus can be retried by the Universe II under the following conditions e While UCSR space is being accessed by a VMEbus master PCI masters are retried e Ifa VMEbus master is performing a RMW access to the UCSRs then PCI attempts to access the USCR space results in a Target Retry until AS is negated e If the Universe II registers are accessed through an ADOH cycle from the VMEbus any PCI attempt to access the UCSRs is retried until BBSY is negated Locking the Register Block from the PCI bus The Universe II registers can be locked by a PCI master by using a PCI locked transaction When an external PCI master locks the register block of the Universe II an access to the register block from the VMEbus does not terminate with the assertion of DTACK until the register block is unlocked Hence a prolonged lock of the register block by a PCI resource may cause the VMEbus to timeout with a BERR Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 5 Registers Overview gt Register Access from the VMEbus 79 5 3 Register Ac
358. x00C PCI Configuration Miscellaneous 0 Register PCI MISCO on page 177 0x010 PCI Configuration Base Address Register PCI BSO on page 178 0x014 PCI Configuration Base Address 1 Register PCI BS1 on page 179 0x018 0x024 PCI Unimplemented 0x028 PCI Reserved 0x02C PCI Reserved 0x030 PCI Unimplemented 0x034 PCI Reserved 0x038 PCI Reserved 0x03C PCI Configuration Miscellaneous 1 Register PCI MISC1 on page 180 PCI MISC1 0x040 0x0FF PCI Unimplemented 0x100 PCI Target Image 0 Control LSIO_CTL on page 181 LSIO_CTL 0x104 PCI Target Image 0 Base Address Register LSIO BS on page 183 LSIO BS 0x108 PCI Target Image 0 Bound Address Register LSIO BD on page 184 LSIO BD 0x10C PCI Target Image 0 Translation Offset LSIO TO on page 185 LSIO TO 0x110 Reserved 0x114 PCI Target Image 1 Control LSI1_CTL on page 186 LSI1_CTL 0x118 PCI Target Image 1 Base Address Register LSI1_BS on page 188 LSI1_BS 0x11C PCI Target Image 1 Bound Address Register LSI1_BD on page 189 LSI1_BD Universe Il User Manual Integrated Device Technology May 12 2010 www idt com oa 12 Registers gt Register Map 16 Table 34 Universe II Register Map Continued Offset Register Name 0x120 PCI Target Image 1 Translation Offset LSI1_TO on page 190 LSH_TO 0x124 Reserved 0x128 PCI Target Image 2 Control LSI2_CTL on page 191 LSI2 CTL 0x12C PCI Target Image 2 Base Address Register LSI2_BS on page
359. y in the TXFIFO corresponds to four transactions on the VMEbus If block transfers are enabled in the PCI target image then each transaction queued in the TXFIFO independent of its length is delivered to the VMEbus as a block transfer This means that if a single data beat transaction is queued in the TXFIFO it appears on the VMEbus as a single data phase block transfer Universe Il User Manual Integrated Device Technology May 12 2010 www idt com 3 PCI Interface gt Universe II as PCI Target 61 3 4 5 Any PCI master attempting coupled transactions is retried while the TXFIFO contains data If posted writes are continually written to the PCI Target Channel by another master and the FIFO does not empty coupled transactions requested by the first PCI master in the PCI Target Channel does not proceed and are continually retried This presents a potential starvation scenario This functionality is intended to support earlier versions of PCI to PCI bridges Special Cycle Generator The Special Cycle Generator in the PCI Target Channel of the Universe II can be used in conjunction with one of the PCI Target Images to generate Read Modify Write RMW and Address Only With Handshake ADOH cycles The address programmed into the Special Cycle PCI Bus Address Register SCYC_ADDR on page 202 in the address space specified by the LAS field of the SCYC_CTL register Memory or I O must appear on the PCI bus during the address pha
360. y mapped to edge sensitive interrupts see VMEbus Interrupt Handling on page 116 The interrupt source status bit in the LINT_STAT register and the mapped LINT_ pin remain asserted with all interrupts The status bit and the PCI interrupt output pin are only released when the interrupt is cleared by writing a to the appropriate status bit VMEbus Interrupt Generation This section details the conditions under which the Universe II generates interrupts to the VMEbus Interrupts may be generated on any combination of VMEbus interrupt lines IRQ 7 1 from multiple sources e PCI sources of VMEbus interrupts LINT 7 0 Internal sources of VMEbus interrupts DMA VMEbus bus error encountered PCI Target Abort or Master Abort encountered Mailbox register access Software interrupt Each of these sources may be individually enabled through the VMEbus Interrupt Enable Register VINT_EN on page 248 and mapped to a particular VMEbus Interrupt level using the VME Interrupt Map 0 Register VINT MAPO on page 253 VME Interrupt Map 1 Register VINT_MAP1 on page 254 and VME Interrupt Map 2 Register VINT MAP2 on page 264 Multiple sources may be mapped to any VMEbus level Mapping interrupt sources to level 0 effectively disables the interrupt Integrated Device Technology Universe Il User Manual www idt com May 12 2010 114 7 Interrupt Generation and Handling gt Interrupt Generation

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