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AN121/221E04 User Manual

1. ACLK ACTIVATE wired AND LCCb device1 LCCb device2 DIN 0000 000 0 0 000000000 k device1_byteN k device2_byte0 dummy postfix dummy prefix JODIO high z k device2_byteN 1 k device2_byteN dummy postfix Figure 21 Multiple Device Serial EPROM Boot Handoff Figure 21 shows just two FPAA s in the configuration chain The common wired AND ACTIVATE signal pulls high only when the second device completes its configuration and releases it The initial sequence is the same as shown in Figure 18 During a multi device configuration the first several clocks of the configuration sequence for the second device provide the edges needed for the first device to complete its configuration The first device therefore does not require a dummy postfix byte but it is part of a standard configuration data set The clocks associated with a dummy post fix byte are however required at the end of the configuration load for the second device AnadigmDesigner 2 provides these extra for clocking only prefix and postfix dummy bytes In Figure 20 the first device generates the analog clock DCLK 16 which is used by both devices Note the different settings of the mode pins to
2. 1 IO4PA Analog O Analog multiplexer input output signals 2 IOANA Analog IO The multiplexer can accept 4 differential pairs or 4 single ended input connections 3 O1P Analog OUT 4 O1N Analog OUT 5 AVSS Analog VSS Analog Power 6 AVDD Analog VDD Analog Power 7 O2P Analog OUT 8 O2N Analog OUT 9 101P Analog 10 10 101N Analog lO 11 102P Analog 10 12 102N Analog lO 13 SHIELD Analog VDD Low noise VDD bias for capacitor array n wells 14 AVDD2 Analog VDD Analog Power 15 VREFMC Vref Attach filter capacitor for VREF 16 VREFPC Vref Attach filter capacitor for VREF 17 VMRC Vref Attach filter capacitor for VMR Voltage Main Reference 18 BVDD Analog VDD Analog Power for Bandgap Vref Generators 19 BVSS Analog VSS Analog Ground for Bandgap Vref Generators 20 CFGFLGb Digital IN In multi device systems 0 Ignore incoming data unless currently addressed 1 Pay attention to incoming data watching for address Digital OUT 0 Device is being reconfigured Open Drain Z Device is not being reconfigured 21 CS2b Digital IN 0 Chip is selected 1 Chip is not selected 22 CS1b Digital IN Prior to completion of a Primary Configuration 0 Allow configuration to proceed 1 Hold off configuration Digital IN After completion of a Primary Configuration Data input pin read back pass through port for
3. _ DIN ACTIVATE SCLK K _ ERRb MOSI PORb CFGFLGb Jr CSb CS2b EXECUTE CS1b LCCb ACLK DOUTCLK lt 16MHz FULL or 4 3DECLK MODE OUTCLK 7 An external pull up can be eliminated if the internal pull up is used Figure 13 A Typical SPI EPROM Connection Power is first applied Internal Power On Reset Asserts pr Oscillator starts within 10 mS of inernal PORb assertion Internal PORb r Internal Power On Reset Deasserts at 18 mS typical y ACLK UU UUU UU UUU UU UU UU UU UU CFGFLGb OUTCLK Sica oe f read instruction OXCO 16 bit starting address always 0x0000 DIN LSB first SPI EPROM Dout begins in high Z state y X XX X XX X X X XX X XX X a dummy_byteo k dummy_bytel C onfiguration data streams in here Figure 14 SPI EPROM Initial Timing Sequence As the system s power supply first begins to ramp up the ACLK CFGFLGb and OUTCLK signals are unknown Soon though the device s internal Power On Reset circuitry asserts and gets everything in a known state The FPAASs oscillator has a typical start up time of less then 10 mS and the POR circuitry will conclude within 30 mS Note This diagram is not to scale At an ACLK rate of 2 MHz the entire Primary Configuration occurs within 3 mS of the internal PORb de assertion Copyright O 2003 Anadigm Inc
4. Copyright 2003 Anadigm Inc All Rights Reserved 22 UM021200 U007g TM ana In each of these connection scenarios the device s ACTIVATE line is fed back to the host s general purpose input output GPIO pin to provide an indication that the configuration was successful Figure 25 also shows an optional connection from host GPIO to the FPAA s EXECUTE input More detailed discussion of EXECUTE is given in Section 3 1 14 3 4 2 Typical Microprocessor Bus Connection The configuration interface is synchronous but there is no requirement for the configuration clock to be unin terrupted It is therefore possible to clock the configuration interface using the write strobe signal typical of most microprocessor s external data buses External Bus Micro GPIO k Pr AN1 221E04 DATA O DIN ACTIVATE GPIO ERRb Add L s A 22 PORb CFGFLGb E E CS2b Add EXECUTE L CS1b Configured al LCCb ACLK DOUTCLK lt 40 MHz FULL CLK WRb 20 MHZ DCLK OUTCLK MODE Figure 26 Typical Microprocessor External Bus Connection Add X X X Le CS2DCLK gt DCLK2CS CS2b DCLKlo gt lt DCLKhi WRb DCLK lt Tsu la Tho DIN X valid X X some other Y Symbol Minimums Description CS2DCLK 2nS CS2b assertion prior to rising edge of DCLK DCLK2CS Ons CS2b
5. 0 XXXXXXXX DATA 1 Data byte to write to starting address 1 Remaining data byt es go in this region XXXXXXXX DATA n Data byte to write to starting address n 00101010 2A ERR Error check byte Figure 28 Primary Configuration Data Stream Structure Copyright 2003 Anadigm Inc All Rights Reserved 25 UM021200 U007g AN121E04 AN221E04 Device User Manual 3 5 2 Header Block SYNC BYTE The configuration logic always expects a synchronization header For the Primary Configuration and Update formats this sync header is always 11010101 D5 JTAG ID BYTE n Every Anadigm device type has a unique 32 bit JTAG ID associated with it though not all of our products have a JTAG interface port Requiring the JTAG ID to match during Primary Configuration is a way of ensuring that configuration data intended for another device does not get accidentally loaded If a Primary Configuration is attempted in which the JTAG ID is not as expected the device will assert ERRb and no data will be loaded into the array Incorrect data can cause high stress conditions to exist within the device possibly causing damage The hex JTAG ID for the AN221E04 device is 0x800022B7 The hex JTAG ID for AN121E04 device is 0x800012B7 AN121E04 pet E04 10000000000000000001001010110111 10000000000000000010001010110111 E 0x2B7 L 0x2B7 Anadigm Manufacturer s ID Anadigm Manufacturer s ID 0x001 0x002
6. All Rights Reserved 17 UM021200 U007g AN121E04 AN221E04 Device User Manual SPI data is sourced by the SPI EPROM on the falling edge of ACLK Setup time of DIN to ACLK should be greater than 2 nS Hold time is 0 nS ACLK CFGFLGb OUTCLK One of four internal analog clocks goes to OUTCLK gt DIN J00000000000000 k byte N 1 k dummy_byte 3 Figure 15 SPI EPROM Completion Sequence As the last configuration data byte a dummy byte is being clocked into the device CFGFLGb de asserts One ACLK later OUTCLK will drive out one of the four internal analog clocks or one of the four comparator outputs if the configuration data set directs it to do so If no clock is selected to be routed to OUTCLK the pin will be driven low instead 3 3 2 Single Device Boot from Serial EPROM A second readily available serial memory type is the 17 series These Serial EPROMs are typically used as configuration memories for FPGAs Unlike SPI EPROMs there is no command input path to these devices OUTCLK SPIMEM is typically left unconnected Once both CEb is asserted and RESETb released these memories simply stream serial data out with each clock As with the SPI EPROM all of this happens automat ically as the power on reset sequence concludes Mfr Part Number Xilinx XC1700E Atmel AT17 series Altera ECP1 E
7. a crystal is attached to master device s DCLK input rather than driving DCLK with a conventional clock source See Figure 23 for further details Copyright O 2003 Anadigm Inc All Rights Reserved 12 UMO21200 U007g Note that the clocks of this master device will be running about 10 ns ahead of all the slaves For this reason the clock master should be the last device in the analog chain i e Analog outputs from the clock master device should not be connected to analog inputs of clock slaves When this feature is not used DOUTCLK should be floated When this configuration data bit is not set DOUTCLK becomes a factory reserved test input with an internal pull down Setting this bit disables both the input and the pull down device 3 1 3 DCLK Data Clock The rising edge of the input on the DCLK pin is used to drive the configuration logic Until a clock is supplied the internal power up procedure cannot be completed The maximum DCLK frequency is 40MHz The supplied clock can be free running or a strobe An interesting feature of the DCLK input is that it may be driven with a standard logic signal or a series resonant crystal can be connected to DVSS The device s on chip oscillator automatically detects an attached crystal and uses it to establish a self generated internal clock that can be used by both the configu ration logic and analog portions of the device The allowable frequency range for an attached crystal is between
8. it is possible to set the length of the error pulse to be short or long in the device which generates it Short pulses are ignored by all other devices in the system and the device which generated the error resets to the point where a simple Update is required If a long ERRb pulse is generated then for both single and multiple device systems a Primary Configuration can begin immediately Long pulses are detected by all other devices in the system which reset to the point where a complete Primary Configuration is required The device which generated the error also resets to this state As an output a long ERRb pulse is asserted low for 15 DCLK clocks A short ERRb output pulse is 1 DCLK clock long As an input ERRb is recognized asserted when held low for 15 or more DCLK periods The ERRb pin may be used to force the device to do a Primary Configuration If ERRb is pulled low externally after power up completes then the device is reset and Primary Configuration will begin again once ERRb is released If used as an input for this purpose the input low period should be at least 15 DCLK periods long 3 1 8 ACTIVATE The ACTIVATE pin is an open drain input output with an internal pull up resistor selectable via configuration It asserts low during power up and remains low until Primary Configuration is complete when it is released and pulls high using only the pull up resistor It remains de asserted tri stated and pulled high thereafter Once ACTI
9. port where it presents itself as a SPI slave It can also be accessed via a microprocessor s external data bus where the microprocessor s write strobe is recognized as a SPI clk and only a single data bit of the data bus is used for the serial SPI data Reconfiguration of all or part of the device is supported in the AN221E04 device allowing multiple configurations to be loaded over time if required The configuration interface also allows multiple devices to be easily connected together to build up larger analog processing systems 1 1 Special Features of ANx21E04 The ANx21E04 devices feature an enhanced I O structure which allows up to four configurable I O and two dedicated ouputs This increases the number of possible outputs to six up from two in the ANx20E04 devices When the configurable I O cell is configured as an input cell all the active elements in the cell buffer chopper amplifier single to differential converter anti aliasing filter can be utilized However when the cell is configured as an output cell all these active elements must be bypassed Unbuffered signals signals can be routed from within the array out through any of the four Configurable Input Output Cells including the special 4 1 muxed cell Copyright O 2003 Anadigm Inc All Rights Reserved 2 UM021200 U007g The ANx21E04 devices also allow the implementation of a on chip 8 bit analog to digital converter The output of this converter can be driven off c
10. A Data Block contains data addressing information a configuration data byte count and from 1 to 256 configuration data bytes followed by error check byte Copyright O 2003 Anadigm Inc All Rights Reserved 24 UM021200 U007g TM ana Data Byte Name Description Header Block 11010101 D5 SYNC Synchronization byte always D5 10110111 B7 JTAG ID BYTE O Bits 7 0 of JTAG Device ID 0x800022B7 or 0x800012B7 00100010 22 JTAG ID BYTE 1 Bits 15 8 of JTAG Device ID 00000000 00 TAG ID BYTE 2 Bits 23 16 of JTAG Device ID 10000000 80 JTAG ID BYTE 3 Bits 31 24 of JTAG Device ID XXXXXXXX ID1 1D1 Byte XXXXXXXX CONTROL Configuration Control Byte Data Block 11XXXXXX BYTE ADDRESS Starting Byte Address DATA FOLLOWS 1 oe XXXXXXXX BANK ADDRESS Starting Bank address XXXXXXXX DATA COUNT Data byte count a value of 00 instructs 256 bytes XXXXXXXX DATA 0 Data byte to write to starting address 0 XXXXXXXX DATA 1 Data byte to write to starting address 1 Remaining data byt es go in this region XXXXXXXX DATA n Data byte to write to starting address n 00101010 2A ERR Error check byte Remaining data blocks go in this region Data Block 10XXXXXX BYTE ADDRESS Starting Byte Address DATA_FOLLOWS 0 ast XXXXXXXX BANK ADDRESS Starting Bank address XXXXXXXX DATA COUNT Data byte count a value of 00 instructs 256 bytes XXXXXXXX DATA 0 Data byte to write to starting address
11. ADC result byte and loads it into 1 or 2 specific Shadow SRAM locations For this example these locations would likely adjust the gain of an amplifier thus Copyright O 2003 Anadigm Inc All Rights Reserved 7 UM021200 U007g AN121E04 AN221E04 Device User Manual achieving the desired linearization When the SAR ADC conversion byte is routed directly back into the Configuration SRAM of its host CAB self modifying circuits can be constructed The SAR ADC may also be used to generate a serial data stream and an accompanying sync pulse These two signals can be routed to either of the two dedicated output cells configured in Digital Output mode Only on the ANx21E04 devices offer this direct access to the SAR ADC circuitry 2 7 Voltage Reference and IBIAS Generators All analog signal processing within the device is done with respect to Voltage Main Reference VMR which is nominally 2 0 V The VMR signal is derived from a high precision temperature compensated bandgap reference source In addition to VMR VREF 1 5 V above VMR and VREF 1 5 V below VMR signals are also generated for the device as shown in the figure below Pkg Pins VREF Temperature Voltage gt 5 UREEPE Compensated Reference VMRclean T Band Gap amp Reference Current gt rm VMRC Reference EL Generators E L gt S m VREFMC VREF pl Note 100nF Tantalum Capacitor
12. BYTE data tia 29 ERR BY 0 OOO O ON 29 Copyright O 2003 Anadigm Inc All Rights Reserved i UM021200 U007g Table of Contents 3 54 Update Format ANZ221E04 Only eiiis ainai A ERAAN S 30 TARGET ID Special Feature AN221E04 Only 31 3 5 5 Configuration Examples cicl n ladra 31 Primary Configuration Format Example ccccceeeeeeeeeneecceeeeeeeeeeeeeeseceaaaaeceseeeeeeseeseeseennaaeess 32 Update Format Example AN221E04 Only 33 3 5 6 Configuration Clocking Considerations ccccecceeeeeeecneeceeeeeeeeeeeeeceaaaaeaeeeeeeeeeeeeeseceancaesaeeeeeeeeess 33 4 Mechanical 34 41 Package Pin Out cin 34 4 2 Recommended PCB Design Practices sir 35 Copyright 2003 Anadigm Inc All Rights Reserved ii UM021200 U007g Table of Figures Architecture Overview Figure 1 AN121E04 and AN221E04 Chip Overview iii 1 Analog Architecture Details Figure 2 A Configurable Input Output Cell there are three oooncccnnnniccccnnnnnocccccnnncnccnnn anno ccnn rn canario 3 Figure 3 Input Output Cell with a 4 1 Input Pair Multiplexer oooooninninnnnnnccnnnnnccccnnnonnonnnccnnnnnnnnnnnnnnnnnnnnnnno 4 Figure 4 Analog Output Cell ccoo add 5 Figure 5 Overview of a Configurable Analog Block CAB 0ooonncccccnnonnocccccnnononcccnononanc cocoa no cc nana rc cnn 6 Figure 6 Voltage Reference and Bias Current Generation oooonnnnccinnnnacccccnnnconcccnnn nan c cnn nn roca cc 8 Figure 7 Cloc
13. E of the Anadigmvortex device family The new e Oo nos a i A I ajn OG a Woo ANx21E04 devices include all the advanced 1 Gel Cant Oscillator features included in the ANx20E04 devices as amp Clock oa e ETER well as a highly flexible analog I O interface omneis any CAB any Output Cel i E 1734 Instead of 4 dedicated inputs and 2 dedicated a 3 3 DVDD outputs the ANx21E04 devices offer 4 Config Bol ETT 3 es BE EL an urable Input Output cells and 2 dedicated 23 3 E CAB1 CAB2 83 o HO eco i FE f faHs al Be E 4 erre 12 outputs allowing more designs within a single z F E AL activate 1 2 FPAA SE I S kJ execute 3 EL i y de 351 L 2 et This new architecture includes resources to 30 85 lt ES S i ee 2 a g sel S Len construct 8 bit analog to digital converters The Hen e Tr e cs serial digital output of these ADC s can be 8 Ha az FT JA ae routed out of the chip via one of the dedicated output cells providing an on chip integrated lt Voltage Refences 4 Look Up Table analog to digital converter AN221E04 devices also support on the fly dynamic configuration 1 Open Drain Output o eo pura Recormendea that allows innovative analog systems with enhanced functionality and longer life to be built AVSS SVSS BVDD VREFPC VMRC VREFNC BVSS Some of the notable features of the Anadigmv
14. Output 5 lt gt or 5 Factory Test Input 2 config bit pi DCLK Chopper 3 Crystal External Clock lt 40 MHz Clock g Oscillator lt or Divider E Crystal lt 20 MHz Pre Scaler J Divide 0 By 16 ACLK SPIP 1 to SPI EPROM Clock Input or to FPGA EPROM Clock Input Configuration Config Logic Done Analog Clocks 3 0 OUTCLK SPIMEM SPI EPROM MOSI setup stream then after configuration completes Analog Clock Output sometimes SAR bit clock SPI EPROM Setup Serial Data Stream Figure 10 System Clocks when Configuration MODE 1 In MODE 1 ACLK SPIP is an output which is a divided down version of the DCLK input The intended connection is to a serial memory device s clock input Regardless of MODE setting at the beginning of configuration OUTCLK SPIMEM sources a serial data bitstream designed to set up a 25 series SPI EPROM for read The intended connection is to the MOSI Master Out Slave In pin of a SPI EPROM FPGA type serial EPROMs need no such initialization In this case the OUTCLK SPIMEM pin is typically not used Once configuration completes OUTCLK SPIMEM reverts to serving as an analog clock or comparator output port 3 1 2 DOUTCLK When enabled by configuration data the DOUTCLK output provides a buffered version of DCLK This is useful when using the oscillator feature of DCLK in the master device of a multi device system In this scenario
15. a multi device configuration serial data chain See Figure 32 for a detailed look at this configuration 3 1 10 CFGFLGb Configuration Flag The CFGFLGb pin is an open drain input output with an internal pull up resistor selectable via configuration CFGFLGb is first driven high then driven low during power up and remains low until Primary Configuration is complete when it is released and pulls high using the internal or external pull up The pin will drive low again at the beginning of reconfiguration and remain low until the end of reconfiguration when it is released and allowed to pull high once again Copyright O 2003 Anadigm Inc All Rights Reserved 14 UM021200 U007g In a multi device system the CFGFLGb pins should all be tied together Devices in a multi device system that are not being addressed for reconfiguration ignore input data until CFGFLGb pulls high The CFGFLGb pin can be monitored by the user to indicate when configurations are in progress The CFGFLGb is also used to initialize and chip select a SPI memory if used as these memories require a falling edge on their chip select input to reset This edge is provided when CFGFLGb is driven low during power up The instruction and address data subsequently output by the OUTCLK pin to initialize the SPI memory is synchronized to this falling edge The internal pull up is selectable through a control byte bit and becomes active immediately after the control byte is latched
16. achieve this Please reference Figures 9 and 10 for further detail Copyright 2003 Anadigm Inc All Rights Reserved 20 UM021200 U007g Serial EPROM OE RESETb k CEb AN1 221E04 AN1 221E04 DATAOUT 3 DIN ACTIVATE L_4 DIN ACTIVATE CLKIN kK ERRb ERRb p p PORb CFGFLGb PORb CFGFLGb 1csz2b cs2b _ EXECUTE _ EXECUTE 2 H cStb p70 Contigured L LCCb LCCb ACLK DOUTCLK ACLK DOUTCLK lt 16 MHz LT LTL l DCLK gpg OUTCLK i DCLK ope OUTCLK Figure 22 Connecting Multiple FPAAs to a Single Configuration Memory Driving DCLK In Figure 22 the cross wiring of ACLK and DCLK allows both devices to configure using the same configu ration clock input clock 16 and allows both devices to use the higher frequency input clock to the first device as the analog master clock For this to work the analogue_clk_independent configuration data bit should be set high in the second device and low in the first device Additional devices should be wired up as the second device and also have the analogue_clk_independent bit set high In order to implement a system which requires a fast analog clock and which uses the on chip crystal oscillator the connection shown in Figure 23 should be used The analogue_clk_independent bit in the second device should be set to allow the device to use the input on ACLK as the analog clock Configuration dat
17. adhere to the configuration protocol defined in this section AnadigmDesigner 2 constructs a configuration data file which adheres to this protocol so that even for the simplest case of self booting from a serial EPROM all the requisite information is contained in the serial data stream delivered to the device during configuration In dynamic applications the host processor must not only determine the appropriate configuration data but also transfer that data to the device using the protocol defined herein There are two data formats which comprise the configuration protocol Primary Configuration Format and Update Format Each is explained in detail in the following sections 3 5 1 Primary Configuration Format amp Byte Definitions The Primary Configuration format is the format of the data that is generated by AnadigmDesigner 2 and is the format that must be used exactly once to configure the device for the first time after reset Out of reset all Shadow SRAM locations are reset to zeros A Primary Configuration is therefore only required to send data to Shadow SRAM locations requiring ones The LUT SRAM is not expressly reset to zero The Primary Configuration is therefore also required to initialize the LUT SRAM if the LUT is intended to be used The Primary Configuration format is comprised of a Header Block followed by one or more Data Blocks A header block contains a Sync byte JTAG ID ID1 and Configuration Control bytes
18. by a user programmable prescaler feeding four user program mable dividers Each of these domains can be used to drive either the SAR logic of a CAB or the switched capacitor circuitry within the CAB itself The clock generation circuitry ensures that all clocks derived from a single master clock signal will synchronize their rising edges so that there is never any skew between 2 clocks of the same frequency Importantly this holds true for all clocks in a multi device system as well Copyright 2003 Anadigm Inc All Rights Reserved 9 UM021200 U007g AN121E04 AN221E04 Device User Manual 3 Configuration Interface The configuration interface provides a flexible solution for transferring configuration data into the configuration memory of the AN121E04 or AN221E04 devices The interface supports automatic standalone configuration from EPROM with both SPI and FPGA serial EPROMS supported The interface also supports configuration from an intelligent host via a standard SPI or SSI interface or via a typical microprocessor bus interface Selection between these two configuration modes is accomplished with the MODE pin Configuration speeds of up to 40MHz are supported Configuration from either a host or EPROM as above is possible with both the AN121E04 and the AN221E04 The AN221E04 however offers the additional feature of allowing reconfiguration of the device via the host This feature which is not supported by the AN121E04 allows t
19. de assertion after rising edge of DCLK DCLKlo 12 5 nS minimum low period for DCLK DCLKhi 12 5 nS minimum high period for DCLK Tsu 2nS Set up time for DIN with respect to DCLK rising edge Tho Ons Set up time for DIN with respect to DCLK falling edge Figure 27 Timing Sequence for Booting from a Host Microprocessor The timing restrictions for SPI and SSI connections are the same as given above The only significant difference in the peripheral bus connections is that DCLK is a strobe rather than a continuous clock There are several options available to drive CS2b In the example shown above some level of address decoding is accomplished with a third device typically a PAL Another option is to use a single high order address line While this may not be an efficient use of your processor s external memory address space it may be sufficient for your particular design Many microprocessors provide chip select outputs and these too are usually suitable to the task of driving the device s CS2b input Copyright 2003 Anadigm Inc All Rights Reserved 23 UM021200 U007g AN121E04 AN221E04 Device User Manual As with the SPI and SSI connections ACTIVATE or ERRb can be monitored to confirm the configuration data transfer 3 4 3 Advanced Feature ACTIVATE In multi FPAA systems it may be beneficial to prevent any of the FPAAs from going active until they have all received their configuration data ACTIVATE is an ope
20. device in the chain to begin its configuration sequence and so on down the chain Tying all the open drain ERRb bi directional pins together ensures that if any one of the devices in the config uration chain detects an error and fails to configure then all of the devices in the chain will be reset and Primary Configuration will start again Likewise all of the devices in the configuration chain have their open drain ACTIVATE bi directional pins also tied together As each device completes it s configuration it ceases to drive the ACTIVATE line low As the last device in the chain completes its configuration it too will cease to drive ACTIVATE low In this manner all the analog circuitry will become active on the next configuration clock after the ACTIVATE line pulls high Copyright O 2003 Anadigm Inc All Rights Reserved 19 UM021200 U007g AN121E04 AN221E04 Device User Manual Serial EPROM OE RESETb k CEb v AN1 221E04 AN1 221E04 DATAOUT DIN ACTIVATE DIN ACTIVATE CLKIN k ERRb ERRb PORb CFGFLGbH PORb CFGFLGbH CS2b CS2b EXECUTE I EXECUTE YZ Chain CS1b m CS1b Configured LCCb LCCb ACLK DOUTCLK ACLK DOUTCLK lt 16 MHz JDCLK mopg CUTELK DELK mope OUTCLK I l a Figure 20 Connecting Multiple FPAAs to a Single Configuration Memory Using a Crystal
21. multi device system 23 DCLK Digital IN drive with lt 40 MHz external configuration clock or attach a 12 16 20 or 24 MHz crystal 24 SVSS Digital VSS Digital Ground Substrate Tie 25 MODE Digital IN 0 select clock support for synchronous serial interface 1 select clock support for SPI amp FPGA EPROM interface 26 ACLK Digital IN MODE 0 Analog Clock Switched Capacitor Clock lt 40 MHz SPIP Digital OUT MODE 1 SPI EPROM or Serial EPROM Clock 27 OUTCLK Digital OUT During power up sources SPI EPROM initialization command string SPIMEM After power up sources selected internal analog clock or comparator output 28 DVDD Digital VDD Digital Power 29 DVSS Digital VSS Digital Ground 30 DIN Digital IN Serial Configuration Data Input 31 LCCb Digital OUT 0 Local configuration complete 1 Local configuration is not complete Once configuration is completed it is a delayed version 8 clock cycles of CS1b or if the device is addressed for read it serves as serial data read output port 32 ERRb Digital IN 0 Initiate Reset hold low for 15 DCLK s 1 No Action 10 kQ p u required Digital OUT 0 Error Condition Open Drain Z No Error Condition 33 ACTIVATE Digital IN 0 Hold off completion of configuration Rising Edge Allow completion of configuration Digital OUT 0 Device has not yet completed Primary Configuration Open Drain Z Device has completed Primary Configuration 34 DOUTCLK Digital OUT Buffered version of D
22. normally be tied low 1 Transfer Shadow SRAM into Configuration SRAM depending on configuration settings Figure 8 Pins Associated with Device Configuration Copyright O 2003 Anadigm Inc All Rights Reserved 11 UM021200 U007g AN121E04 AN221E04 Device User Manual 3 1 1 MODE MODE controls the behavior of the analog and configuration clocks portion of the device The state of the MODE pin establishes a unique configuration for the device s clock pins as shown in the Figures 9 and 10 DOUTCLK 2 Buffered DCLK Output 3 L D or F Factory Test Input 3 config bit El DCLK Chopper Crystal External Clock lt 40 MHz Clock 3 Oscillator lt Or Divider al Crystal lt 20 MHz Pre Scaler Config Logic ACLK SPIP and Clock Dividers lt Optional Analog Clock Input lt 40 MHz Done Configuration SRAM Analog Clocks 3 0 OUTCLK SPIMEM SPI EPROM MOSI setup stream then after configuration completes Analog Clock Output sometimes SAR bit clock Figure 9 System Clocks when Configuration MODE 0 SPI EPROM Setup Serial Data Stream In MODE 0 ACLK SPIP is an optional clock input that can be used to serve as the master clock for the analog clock domains within the device Clock HH Dividers pon DOUTCLK 5 Buffered DCLK
23. rra nc nannnncnn 13 3 15 0UTCGEK SPIMEM 20000020 in bi eee a 13 3 1 6 PORD Power On Reset 13 3 1 1 BERRP EMO apsiden idiota iii leas 13 31 8 ACTIVA EE EEE EEE aa 14 3 1 9 LCCb Local Configuration Complete sis 14 3 1 10 CFGFLGb Configuration Flag cuviiionian a da hadd aia 14 31 14 DIN Data luso ia E EEEE aaa 15 3 1 12 CS1b Chip Select 1 lion in inserer iaa 15 31 13 CS2b Chip Select 2 000 a it dras 15 31 14 EXECU TE niiin aai gista aaO a a a 16 SZ ROSES sise NN 16 3 9 Booting from EPROM LEEDS S gare Jediene peated 16 3 3 11 BO00tfrom SPlEPRO Mision liada ii dpi nn nl 17 3 3 2 Single Device Boot from Serial EPROM iii 18 3 3 3 Multiple Devices Boot from Serial EPROM iii 19 3 4 Booting froma Host Processor accionista rie ESSEN 22 3 4 1 Synchronous Serial Interface Connections SPI and SSI 22 3 4 2 Typical Microprocessor Bus Connection 23 3 4 3 Advanced Feature ACTIVATE siatiecsssscatccssaaiactiansinadasiaatadddecesssaadaaaderntadiedas seadacieasenaacdianranacedeegn 24 3 4 4 Advanced Feature Return Read Data Path AN221E04 Only 24 3 5 Configuration Protocol ci il its dar 24 3 5 1 Primary Configuration Format 8 Byte Definitions 24 3 5 2 Header Block A NN 26 SYNG BYTE tacita dorada ti 26 JIAGID BYTE Dina ad a da ne 26 IBD BYTE ia A aiii 26 3 9 3 Data A O A 27 BYTE ADDRESS BYTE agenter tiren anadir as idee 28 BANK ADDRESS BYTE cion tandas ordene tii 28 DATA COUNT BYTE cusco tc ai i n 29 DATA
24. through 3 1 5 for a complete explanation of these restrictions The clock going to the configuration logic is always sourced at the DCLK pin The DCLK pin may have an external clock applied to it up to 40 MHz The DCLK pin may otherwise be connected to a series resonant crystal in which case special circuitry takes over to form a crystal controlled oscillator No programming is required Connection of a crystal will result in a spon taneously oscillating DCLK Please see section 3 1 3 for complete details on this feature DOUTCLK Buffered DCLK Output gt gt or Factory Test Input DCLK Chopper Clock lt Chopper Config Crystal External Clock lt 40 MHz Clock Logic Oscillator lt or Divider Crystal lt 20 MHz lt Pre Scaler _4 Analog Clocks 3 0 an dd Dividers lt Optional Analog Clock Input lt 40 MHz Configuration OUTCLK SPIMEM Analog Clock Output sometimes SAR bit clock Figure 7 Clock Features and Clock Domains The analog clock domains are all sourced from a single master clock either ACLK or DCLK The device configuration determines which clock input will be used as the master clock This master clock is divided into 5 unique domains The first domain sources only the chopper stabilized amplifiers within the Input Output Cells The other four domains are sourced
25. 12 MHz and 24 MHz with 16 MHz being the optimal choice Mfr Frequency Part Number NDK 12 16 20 MHz NX8045GB C MAC 12 16 20 MHz 12 SMX AeL 12 16 20 24 MHz SXH Figure 11 Known Compatible Crystals 3 1 4 ACLK SPIP Analog Clock Serial PROM Clock In MODE 0 ACLK SPIP is an optional analog master clock input to drive the switched capacitor circuitry within the device In MODE 1 ACLK SPIP is a clock output which is normally used to clock data out of a Serial FPGA EPROM or provide the SPI master clock to an attached SPI EPROM See sections 3 3 1 and 3 3 2 for listing of compatible EPROMs It is a divide down by16 version of DCLK 3 1 5 OUTCLK SPIMEM During power up the OUTCLK SPIMEM pin transmits control words to the attached SPI memory device if any A SPI EPROM requires a control word to be sent followed by a 16 bit start address After configuration the OUTCLK SPIMEM pin routes out any 1 of the 4 internal analog clocks as enabled by the configuration data 3 1 6 PORb Power On Reset When PORb is asserted low the device s internal power on reset circuitry is re activated as if the device were being powered up for the first time When utilized as a control signal PORb is normally just pulsed low but it can be held low for an indefinitely long period of time Once PORb is released high the POR circuit completes a normal power on reset sequence and control is handed over to the configuration state
26. 1E04 Ly DIN ACTIVATE 3 DIN ACTIVATE 3 DIN ACTIVATE ERRb i ERRb ERRb L PORb CFGFLGb PORb CFGFLGb PORb CFGFLGb GPIO H CS2b CS2b 1cs2b m EXECUTE EXECUTE _ EXECUTE ID1 1 an En ID1 2 1D1 3 FT CS1b ID2 X 3 CS1b ID2 X 740851 ID2 Y SE LCCb LCCb LCCb 3ACLK DOUTCLK ACLK DOUTCLK 3 ACLK DOUTCLK ADCLK mope OUTCLK JDCLK ope OUTCLK ADCLK ope OUTCLK SCLK MISO k Figure 32 Configuring Multiple Devices from a Host Processor Figure 32 shows a valid connection and configuration example for multiple FPAA s being hosted from a single SPI port During Primary Configuration each device in the chain received a unique ID1 and a non unique ID2 The ID1 s were assigned via the ID1 fields of the Primary Configuration data streams The ID2 s were established within the configuration data sets downloaded into each of the devices Once Primary Configurations are complete for all of these devices each will respond to the host SPI port only if the TARGET ID field of the Update configuration data stream contains either its ID1 or ID2 identifiers or OxFF Assume that two of the devices perform identical analog functions X and the third a unique function Y Also assume that the X and Y configuration data sets contain ID2 values of X and Y respectively During the Primary Configuration the host processor assigned the first device an ID1 of 1 and filled that device with the X configuration Likewise the ID1
27. 2 device also got the X configuration The ID1 3 device got the Y configuration Once these Primary Configurations are complete and analog operations go active the host processor may alter via Update both X devices concurrently by using TARGET ID X rather than sequentially by addressing TARGET ID 1 then TARGET ID 2 If the host instead uses OxFF in the TARGET ID field then all three devices will concurrently accept the subsequent reconfigu ration data 3 5 5 Configuration Examples The following examples assume a hosted interface Data must be shifted into the FPAA most significant bit first White space and comments are included only to improve readability for these examples Copyright 2003 Anadigm Inc All Rights Reserved 31 UM021200 U007g AN121E04 AN221E04 Device User Manual Primary Configuration Format Example 00000000 00000000 00000000 00000000 00000000 11010101 10110111 00100010 00000000 10000000 00000001 00000101 11000000 00000000 00000000 datadata datadata datadata 00101010 10011110 00010111 00000010 datadata datadata 00101010 00000000 40 clocks are required to be sent to complete the power up reset sequence This is usually accomplished by sending out 5 bytes of don t care prefix data After the 40th clock the configuration logic is ready 0xD5 is the required sync header 0xB7 is Least Significant Byte of JTAG ID word AN221E04 0x22 is byte 2 of
28. AN121E04 AN221E04 Field Programmable Analog Arrays User Manual ana Anadigmvortex is the second generation field programmable analog array FPAA device family from Anadigm Four members of the Anadigmvortex family are currently shipping the low cost AN120E04 and AN121E04 devices that are geared towards high volume applications requiring consolidation of discrete analog functionality and the AN220E04 and AN221E04 devices that are further optimized to enable dynamic reconfiguration a breakthrough capability that allows analog functions to be integrated within the system and controlled by the system processor The Anadigmvortex devices consist of a 2 x 2 matrix of fully Configurable Analog Blocks CABs surrounded by a fabric of programmable interconnect resources Configuration data is stored in an on chip SRAM config uration memory Compared with the first generation FPAAs the Anadigmvortex architecture provides a signif icantly improved signal to noise ratio as well as higher bandwidth These devices also accommodate non linear functions such as sensor response linearization and arbitrary waveform synthesis The ANx20E04 devices were the first members 88d a amp a z Sa BE
29. Array Identification Array Identification 0x00 0x00 Design Center Design Center 0x8 0x8 Chip Revision Chip Revision Figure 29 The Components of the 32 Bit JTAG Identification Number ID1 BYTE The ID1 field establishes one of the two logical addresses for the device ID1 is considered the primary logical address for the device The alternate logical address ID2 is not part of the Header Block but rather it is established within the device s configuration data and is therefor delivered within a Data Block Having logical addresses for every FPAA in the system allows the connection of many FPAAs in series consuming no extra physical host connections and once configured communication only with the specifically addressed device s See section 3 5 5 for further details Copyright O 2003 Anadigm Inc All Rights Reserved 26 UM021200 U007g TM ana 3 5 3 Data Block CONTROL BYTE Bit Number 716151413 21 1110 010101010 110 Default bit values as generated by AnadigmDesigner 2 PULLUPS 1 Enable internal pull ups 0 Disable internal pull ups This bit is used to enable internal pull ups on the CFGFLGb and ACTIVATE pins PULLUPS is sticky i e Once set it stays set until a device reset If the pin is exter nally loaded then it is recommended that an external pull up resistor be used instead of the internal Note DIN pull up is controlled by configuration data only Note ERRb always r
30. CLK Inactive floats until its associated configuration bit is set If unused this pin must be left floating Digital IN Factory reserved test input Float if unused 35 PORb Digital IN 0 Chip Held in reset state Rising Edge re initiates power on reset sequence 30 mS to complete 36 EXECUTE Digital IN 0 No Action This pin should normally be tied low 1 Transfer Shadow SRAM into Configuration SRAM depending on configuration settings 37 103P Analog O 38 IO3N Analog lO 39 IO4PD Analog O Analog multiplexer input output signals 40 IO4ND Analog lO The multiplexer can accept 4 differential pairs or 4 single ended connections 41 104PC Analog 10 42 IO4NC Analog IO 43 104PB Analog 10 44 IO4NB Analog IO Copyright O 2003 Anadigm Inc All Rights Reserved 34 UM021200 U007g 4 2 Recommended PCB Design Practices The device is designed to perform with very few external components required However there is no fighting physics and some filtering capacitors are required for both the supply rails as well as the internally generated voltage references Digital Power e 2 el n 3 e a a 3 2 g Digital Ground Plane z Q 2 Analog Ground Plane Ko G ah Y Analog Power 8 2 2 D o 3 pe TD vo og EY IT Analog Power pa ry D Analog Power y 200 3 2 O 2 ei el Analog Power Figure 33 Basic Guidelines f
31. CP2 Figure 16 Known Compatible 17 Series Serial EPROM Memory Devices NAN Serial EPROM OE RESETb k CEb ke AN1 221E04 DATAOUT DIN ACTIVATE CLKIN K ERRb Y Zonfiguring PORb CFGFLGb CS2b EXECUTE CS1b Y Zonfigured ele LCCb Jack DOUTCLK lt 16 MHz FULL peik MoDE OUTCLK TI Figure 17 A Typical Serial FPGA EPROM Connection Copyright O 2003 Anadigm Inc All Rights Reserved 18 UM021200 U007g Power is first applied Internal Power On Reset Asserts r Oscillator starts within 10 mS of inernal PORb assertion Internal Power On Reset Deasserts at 18 mS typical Internal PORb SYNC byte prior to this point will not be recognized 4 4 aak o SUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUL ERRb ACTIVATE ACTIVATE goes low at Power On Reset supplying an asserted low chip enable CEb to the Serial EPROM ACTIVATE remains low until conifguration completes DIN fi EPROM Doutis Highz NODOS SKS NSSS ISSN SISSI k dummy byte0 dummy_byte1 dummy_byte2 K dummy byte3 SYNC byte 3 03 r30 Figure 18 Serial FPGA EPROM Initial Timing Sequence The start up sequence is shown in Fig 18 The only significant difference between using a
32. JTAG ID word 0x00 is byte 3 of JTAG ID word 0x80 is Most Significant Byte of JTAG ID word User assigns any Chip ID except OxFF Control Byte PULLUPS are enabled ENDEXECUTE Transfer Shadow SRAM to Configuration SRAM as soon as this download is complete Constant 1 DATA_FOLLOWS 1 start BYTE address is 0 The starting BANK address is 0 0x00 byte count field means 256 data bytes follow The first configuration data byte The second configuration data byte the 256th configuration data byte 0x2A is the Basic error checking constant expected This is the region that the other blocks of data need to be sent to completely fill the Shadow SRAM These blocks do not need to be prefaced by additional clocks nor do they require a JTAG ID ID1 or Control bytes These intermediate blocks all have the same form as the final block shown below The important point to note is that only the final block of Primary Configuration has the DATA FOLLOWS bit cleared in the BYTE ADDRESS byte DATA FOLLOWS is cleared to 0 this means that at the conclusion of the transfer of this final block Shadow SRAM will get copied into Configuration SRAM with no additional action required by the host Ox1E is the starting BYTE address 0x17 is the starting BANK address 0x02 is byte count for this particular last block Second to the last configuration data byte The Last con
33. NK ADDRESS Starting bank address of Shadow SRAM to be loaded The BYTE and BANK Address bytes taken together form the starting Shadow SRAM or LUT SRAM load address for the subsequent block of configuration data The memory within the device is organized as 18 rows banks by 32 columns bytes No special handling is required to cross bank or byte boundaries this is auto matic The address allocation of the device s Shadow and LUT SRAM is shown in the figure below BANK BYTE ADDRESS ADDRESS 11111111111111111111111111111 1lololololololololololololol ol olo FJE D C B A 918 7 61514 3 2 1 0 FJE D C B A 91817161514 3 2 1 0 00 Lower Auxiliary Shadow SRAM Bank 01 Upper Auxiliary Shadow SRAM Bank 02 CAB 1 Lower Shadow SRAM Bank 03 CAB 1 Upper Shadow SRAM Bank 04 CAB 2 Lower Shadow SRAM Bank 05 CAB 2 Upper Shadow SRAM Bank 06 CAB 3 Lower Shadow SRAM Bank 07 CAB 3 Upper Shadow SRAM Bank 08 CAB 4 Lower Shadow SRAM Bank 09 CAB 4 Upper Shadow SRAM Bank OA 0F Factory Reserved Address Range 10 Look Up Table SRAM Bank 0 11 Look Up Table SRAM Bank 1 12 Look Up Table SRAM Bank 2 13 Look Up Table SRAM Bank 3 14 Look Up Table SRAM Bank 4 15 Look Up Table SRAM Bank 5 16 Look Up Table SRAM Bank 6 17 Look Up Table SRAM Bank 7 18 FF Factory Reserved Address Range Figure 30 AN1 220E04 Memory Allocation Table Copyright 2003 Anadigm Inc All Rights Reser
34. SPI EPROM and an FPGA type Serial EPROM is that the serial command words being sourced by the unconnected OUTCLK SPIMEM pin are ignored by the FPGA EPROM Because the EPROM will start sourcing data before the FPAA is ready to accept it the configuration data should be prefixed with 4 dummy bytes prior to the SYNC byte and the meaningful configuration data AnadigmDesigner 2 design software handles this insertion of the requisite prefix data As described previously a few clocks are need at the end to complete the configuration A postfix of one dummy byte is also added to the meaningful configuration data 17 series FPGA serial EPROMs output data on the rising edge of ACLK Setup time of DIN to ACLK should be greater than 2 nS Hold time is 0 nS ACLK ACTIVATE LCCb on 100000000000 me byteN 1 byteN dummy byte Figure 19 Serial FPGA EPROM Completion Sequence 3 3 3 Multiple Devices Boot from Serial EPROM Multiple FPAAS may be configured from a single EPROM either Serial or SPI type The first FPAA in the chain has both of its chip selects pulled low and so it begins configuring immediately after power up All down stream devices are stopped from configuring because their CS1b inputs are held high As the first FPAA in the chain completes its self configuration it de asserts LCCb This flags the next
35. Single Ended Input IO4ND Differential 1 pair of 4 Single Ended 1 input of 8 Figure 3 Input Output Cell with a 4 1 Input Pair Multiplexer Copyright O 2003 Anadigm Inc All Rights Reserved 4 UM021200 U007g 2 3 Output Cell Like the analog inputs the analog Output Cells are loaded with features to ensure that your system s design can take full advantage of the fidelity and versatility that the core of the device offers The outputs can serve to deliver digital data or differential analog voltage signals Analog signal pairs sourced by CABs within the array are routed to an Output Cell via the Output Cell s input multiplexer BYPASS ia OUT PIN 3 O1P Bypass or Programmable fg DIFF2SINGLE VOUT N DIFF2SINGLE OUT PIN vour O1N 7 s 89 gy9 sAeue wo ul SJEUBIS BYPASS Figure 4 Analog Output Cell In some special circumstances it may be desirable to route the core analog signals to the outside world with no additional buffering or filtering The output cells have bypass paths which allow the core signals to come out with no further processing or buffering For special considerations governing the use of bypass mode outputs see Section 2 1 1 Each Output Cell contains a programmable filter identical to the one described for the Input Output Cells see Sect
36. Table The device contains a single 256 byte Look Up Table LUT The 8 bit address input to the LUT can come from either the a SAR ADC 8 bit output or from a special 8 bit LUT counter The functional description of the SAR ADC driving the LUT address inputs is given in the section below If the LUT counter is selected the counter continuously counts up resetting itself back to zero count each time that its programmable roll over value is met Each new count value is presented to the LUT as an address The data read back from this address is then written into 1 or 2 target locations within Shadow SRAM The target location s to be used and LUT contents are part of the device s configuration data set The clock to the LUT counter is sourced by one of the 4 internal analog clocks from one of the four clock dividers The subsequent transfer of these 1 or 2 bytes from Shadow SRAM into Configuration SRAM can occur as soon as the last configuration data byte is sent or an internal zero crossing is detected or a comparator trip point is met or an external EXECUTE signal is detected With periodic clocking of the LUT counter a LUT CAB combination can form an arbitrary waveform generator or temporally modulate a signal 2 6 SAR ADC Operation Circuitry is included within the CAB which allows the construction of an 8 bit Successive Approximation Register SAR type Analog to Digital Converter ADC The SAR ADC requires two clocks with a frequenc
37. To Array 7 I VREF VMRclean and VREF are each used as reference voltages within the analog array VMR is the node onto which all switched capacitors dump charge Figure 6 Voltage Reference and Bias Current Generation There are two versions of VMR routed to the CABs VMR is the node onto which all switched capacitor charges get dumped and can be relatively noisy VMRclean is also routed to the opamps within the CABs This quiet version of VMR is used by the opamps as the ground reference in order to improve their settling times It is required that external filtering caps be provided on VREFPC VMRC and VREFMC to ensure optimal chip performance The recommended value for each is 75 to 100 nF Higher values will have an adverse affect on settling time lower values will reduce node stability For highest possible performance capacitors with a low series inductance such as Tantalum should be used In most cases however standard ceramic capacitors will be sufficient VREF and VREF are most often used by CAMs which utilize the comparator In particular these signals bound the recommended input range of SAR conversion CAMs Copyright O 2003 Anadigm Inc All Rights Reserved 8 UM021200 U007g 2 8 System Clocks Figure 7 provides a good high level overview of the various clock features and clock domains of the device Not all of the features shown in this diagram are available in configuration MODE 1 See sections 3 1 1
38. VATE pulls high configuration is allowed to complete if the ENDEXECUTE bit is set See section 3 5 1 for further detail If there is more than one FPAA in a system all ACTIVATE signals should be tied together to ensure that all devices conclude their configuration at exactly the same time The ACTIVATE signal is also intended to be used to disable a standard FPGA Serial EPROM if used once configuration is complete See section 3 4 3 for further detail The internal pull up associated with the ACTIVATE pin is selectable through a control byte bit and becomes active immediately after the control byte is latched in 3 1 9 LCCb Local Configuration Complete During power up the LCCb output drives high So long as the Primary Configuration is incomplete the LCCb pin will continue to drive high Just before configuration completes the LCCb pin asserts low In multi device systems this output is normally connected to the CS1b input pin of the next device in the configuration chain allowing that device s configuration sequence to commence See section 3 3 3 for further details on the LCCb to CS1b connection Once configuration completes two clocks after ACTIVATE asserts high the LCCb pin becomes a data output If the device is being read from then LCCb serves as the serial data output pin for the read data If the device is not being read from then LCCb is simply a registered version of CS1b allowing serial data to pass through the device for
39. a in the first device should be set to enable a buffered version of DCLK to be output on DOUTCLK See Figure 9 for further detail For more information on how to set these configuration bits and other advanced features please contact E Anadigm technical support Serial EPROM OE RESETb _ CEb k AN1 221E04 AN1 221E04 DATAOUT 3 DIN ACTIVATE gt DIN ACTIVATE CLKIN ERRb ERRb Pa P PORb CFGFLGb PORb CFGFLGb CS2b CS2b EXECUTE EXECUTE N7 Chain CS1b m CS1b Configured L LCCb LCCb ACLK DOUTCLK gt ACLK DOUTCLKH lt 16 MHz 3 DCLK ope OUTCLK IPCLK ope OUTCLK H Figure 23 Using DOUTCLK in a Multi Device System Copyright O 2003 Anadigm Inc All Rights Reserved 21 UMO21200 U007g AN121E04 AN221E04 Device User Manual 3 4 Booting from a Host Processor In applications demanding on the fly adjustments to the analog circuitry there will be a host microprocessor available to perform the calculation of new circuit values assemble these new values into a configuration data block and transfer that data block into the FPAA The device s flexible configuration interface is designed to accept input from either serial memories or any of three major microprocessor interface types Synchronous Serial Interface SSI Serial Peripheral Interface SPI or a conventional external periphe
40. an be executed as described above In the case of the AN121E04 reconfiguration data is ignored Multiple device systems are supported through a daisy chain connection of configuration interface signals and logical addressing via the host using the reconfiguration protocol Devices can be reconfigured concur rently or singly Thus groups of devices can be updated together or devices can be updated separately using exactly the same connections to the host Copyright O 2003 Anadigm Inc All Rights Reserved 10 UM021200 U007g ana TM 3 1 Configuration and Clocks Pin List The device has many advanced configuration features and as a consequence many of the pins of the config uration interface have multiple functions Subsequent sections describe the typical connection schemes Name Type Functions DOUTCLK Output Buffered version of DCLK Inactive floats until its associated configuration bit is set If unused this pin must be left floating Input Factory reserved test input Float if unused MODE Input 0 select clock support for synchronous serial interface 1 select clock support for SPI amp FPGA EPROM interface DCLK Input drive with lt 40 MHz external configuration clock or attach a 12 16 20 or 24 MHz crystal ACLK Input MODE 0 Analog Clock Switched Capacitor Clock lt 40 MHz SPIP Output MODE 1 SPI EPROM or Serial EPROM Clock OUTCLK Output Dur
41. apacitors can take on a relative value between 0 and 255 units of capacitance The actual value of capacitance is not all that important here The CAM library elements do not depend on the absolute value of these capacitors but rather on the ratio between them which tracks to better than an 0 1 over process variations There is a second switch matrix to further establish the circuit topology and make the appropriate connections There are two opamps and a single comparator at the heart of the CAB Outputs of these active devices are Copyright O 2003 Anadigm Inc All Rights Reserved 6 UM021200 U007g routed back into the first switch matrix so feedback circuits can be constructed These outputs also go to neighboring CABs Signal processing within the CAB is usually handled with a switched capacitor circuit Switched capacitor circuits need non overlapping NOL clocks in order to function correctly The NOL Clock Generator portion of the CAB takes one of the four available analog clocks and generates all the non overlapping clocks the CAB requires There is Successive Approximation Register SAR logic that when enabled uses the comparator within the CAB to implement an 8 bit Analog to Digital Converter ADC Routing the SAR ADC s output back into its own CAB or to the Look Up Table enables the creation of non linear analog functions like voltage multiplication companding linearization and automatic gain control 2 5 Look Up
42. appropriate Anadigm software license shall prevail over the above terms to the extent of any inconsistency Copyright O 2002 Anadigm Inc All Rights Reserved Anadigm and AnadigmDesigner are registered trademarks of Anadigm Inc The Anadigm logo is a trademark of Anadigm Inc Copyright O 2003 Anadigm Inc All Rights Reserved UMO21200 U007g Table of Contents 1 Architecture Overview 1 1 1 Special Features of ANX21E04 iii 2 2 Analog Architecture Details 3 2 1 Configurable Input Output Cell sisina iaa 3 2 1 1 Special Consideration for Bypass Mode Outputs 4 2 1 2 Special Consideration for Bypass Mode Inputs 4 2 2 Muxed Analog Input Output coooooccocccccccccocononnoononcnnncnnnnnnnnnn nan n nro nn ae nn nn eee Eee nn rrnn nani 4 2 3 Output Cello a 5 2 4 Configurable Analog Block ss 6 2 5 LOOK Up TAble unna re td A Ad EA 7 VAINA AO 7 2 7 Voltage Reference and IBIAS Generators conmccccnnnnccccnnonconcccconanoncncccnno nn nn nonnnn nn cnn ran rn arrancan 8 2 8 System Clocks iii 9 3 Configuration Interface 10 3 1 Configuration a d Clocks PIN List ica inici es dis esi skadde ae de 11 311 MODE Gi A A A it 12 3 1 2 DOUTCEK iii A i tin 12 3 1 3 DOLK Data COCK iii cidad tata dene ni attente 13 3 1 4 ACLK SPIP Analog Clock Serial PROM Clock oooooonoocccononnoccccnnncccccccnonnoncccnnnnnr cc cnn
43. ces 104ND ky OO 1 Open Drain Output N un O o N o 2 A a PA 2 2 Programmable Internal Pull Up 4 a D 2 G 3 10KQ External Pull Up Recommended ec gt E gt gt Figure 1 AN121E04 and AN221E04 Chip Overview Copyright O 2003 Anadigm Inc All Rights Reserved 1 UM021200 U007g AN121E04 AN221E04 Device User Manual Analog input signals can be connected from the outside world via the four Configurable Input Output Cells The fourth Input Output Cell of the device has a special muxing feature which allows the connection of up to 4 unique signal sources or loads Each Input Output Cell can pass a differential signal pair directly into the array or process either single ended or differential input signals using combinations of a unity gain buffer a programmable gain amplifier a programmable anti alias filter and a special chopper stabilized amplifier The chopper stabilized amplifier is especially designed for use with signals requiring significant gain and hence ultra low input offset voltages Output signals can be routed from within the array out through the Input Output Cells directly bypassing any additional active circuitry Output signals can also be routed out through an Output Cell directly again bypassing any additional active circuitry or through the Output Cell s programmable reconstruction filter and a pair of differential to single ended converters In either case an output signal is always presente
44. d externally as a differential signal pair The Output Cells can also be used to route out a logic level comparator output signal The device can accept either an external clock or generate its own clock using an on chip oscillator and an external crystal Detection of the crystal is automatic The resulting internal clock frequency can be divided down into four synchronized internal switched capacitor clocks of different frequencies by programmable dividers The clock circuitry can also source any of these four clocks as a chip output The behavior of the CABs clocks signal routing Input Output Cells and Output Cells is controlled by the contents of Configuration SRAM Behind every Configuration SRAM bit is a Shadow SRAM bit The Shadow SRAM of the AN221E04 device may be updated without disturbing the currently active analog processing This allows for on the fly modification of one or more analog functions This dynamic reconfiguration is not possible with the AN121E04 device The architecture includes a simple yet highly flexible digital configuration interface The configuration interface is designed to work in stand alone mode by connecting to either a common SPI or FPGA type serial EPROM In this mode after the device powers up it will automatically load its configuration from the EPROM and begin functioning immediately thereafter The configuration interface is also designed to be connected directly to a host microprocessor s SPI master
45. equires an external pull up resistor 10KQ is the recommended value Factory Reserved 1 Factory Reserved setting 0 Normally set to 0 ENDEXECUTE 1 At the end of the current transfer cycle Shadow SRAM will be copied into Configuration SRAM 0 No action See below and section 3 1 14 further explanation SRESET 1 The device will perform a reset 0 No action This bit allows the host to initiate a soft reset The device will reset as soon this bit is latched READ 1 Sets the device in read mode Configuration SRAM and LUT only 0 Sets the device in write mode STOP READBACK 1 Stop any data read back from the device 0 Allow data read back from the device This bit can be set during Primary Configuration or Update If set an internal flag is set which prevents all further data read backs This internal flag can only be reset by re powering the device thereby destroying the SRAM contents If any attempt to do a read back is made after this bit is set then ERRb will drive low for 14 DCLK cycles and the device will be reset to a point where a Primary Configuration is required In the AN121E04 device this feature is superfluous RESET ALL 1 On an error the ERRb output will pull low for 15 DCLK cycles and the device will be reset to a point where a Primary Configuration is required 0 On an error the ERRb output will be pulsed low for a single DLCK cycle and
46. figuration data byte 0x2A is the Basic error checking constant expected 8 clocks are required by the configuration state machine to finish the transfer This is usually accomplished by sending out a single byte of don t care data Copyright O 2003 Anadigm Inc All Rights Reserved 32 UM021200 U007g ana TM Update Format Example AN221E04 Only 11010101 00000001 00000101 10011110 00000011 00000011 datadata datadata datadata 00101010 00000000 0xD5 is the required sync header TARGET ID The ID1 or ID2 value of the target device or the universal target ID of OxFF Control Byte ENDEXECUTE and PULLUPS are enabled DATA FOLLOWS is cleared to 0 so the configuration logic will expect no more data after this final block and because ENDEXECUTE is set 1 in the Control Byte Shadow SRAM will get copied into Configuration SRAM as soon as the data block is download with no additional action required by the host 0x1E decimal 30 is the starting BYTE address 0x03 is the starting BANK address 0x03 byte count field means 3 data bytes follow The 1st updated data byte goes to bank 3 byte 30 The 2nd updated data byte goes to bank 3 byte 31 The 3rd updated data byte goes to bank 4 byte 0 0x2A is the Basic error checking constant expected 8 don t care bits to provide the necessary clocks to complete the load Because the EXECUTE bit was set o
47. ght O 2003 Anadigm Inc All Rights Reserved 35 UM021200 U007g AN121E04 AN221E04 Device User Manual Copyright O 2003 Anadigm Inc All Rights Reserved 36 UM021200 U007g TM ana Copyright O 2003 Anadigm Inc All Rights Reserved 37 UM021200 U007g AN121E04 AN221E04 Device User Manual Copyright O 2003 Anadigm Inc All Rights Reserved 38 UMO21200 U007g AN121E04 AN221E04 Field Programmable Analog Array User Manual TM ana For more information logon to www anadigm com Copyright O 2003 Anadigm Inc All Rights Reserved UM021200 U007g
48. he reconfiguration of all or any part of the device repeatedly and at will using the reconfiguration protocol Thus the FPAA s behavior can be adjusted on the fly to meet the dynamic requirements of the application The configuration data is stored in SRAM based configuration memory distributed throughout the FPAA There are two SRAM memories on the chip Shadow SRAM and Configuration SRAM Configuration data is first loaded into Shadow SRAM and then on a single user controllable clock edge is loaded into Configu ration SRAM The device s analog functionality behaves according to the data in Configuration SRAM This method allows configuration data to be loaded into the device in the background and take effect instantly when required Read out of the Configuration SRAM is supported allowing users to check data integrity if required Read back applies only to the AN221E04 The AN121E04 does not support readback The device also features a Look Up Table LUT The LUT exists as part of the Configuration SRAM and can be read and written to as normal but Shadow SRAM for the LUT is not supported Thus data written to the LUT becomes effective as it is written On power up internal power on reset circuitry is activated which resets the device s Configuration SRAM and prepares the device for a first or Primary Configuration Primary Configuration then proceeds according to the protocol described later in this document Once completed reconfigurations c
49. hip via either of the dedicated output cells The dedicated output cell must be configured to be in the digital mode The output data of the ADC is presented as a serial sequence of 8 bits beginning with the MSB To implement this ADC inside the ANx21E04 device use the SAR ADC CAM that is available in the ANx21E04 Standard CAM Library ANx20E04 ANx21E04 4 dedicated input cells 4 configurable input output cells Amo Siructure 2 dedicated output cells 2 dedicated output cells available for use with CAMs such as the available for use with CAMs such as the Transfer Function CAM and can also be used Transfer Function CAM to implement an on chip 8 bit ADC for external use Integrated 8 Bit ADC 2 Analog Architecture Details The following section explains some of the architecture details of the AN221E04 and the AN121E04 devices 2 1 Configurable Input Output Cell Each Configurable Input Output Cell contains a collection of resources which allow for high fidelity connec tions to and from the outside world with no need for additional external components In order to maximize signal fidelity all signal routing and processing within the device is fully differential Accordingly each Input Output Cell accepts or sources a differential signal A single ended signal can be used as an input to the cell If a single ended source is attached an internal switch will connect the negative side of the internal differential signal pa
50. ices The remainder of the infor mation is just as described above in section 3 5 1 As with Primary Configuration it is not a requirement of the Update format to contain a complete data set for the device Partial reconfiguration of the device is supported It is most often the case that only a few Shadow SRAM or LUT SRAM addresses need new data The Update format provides a quick and compact method for moving this new data into the device Data Byte Name Description Header Block 11010101 D5 SYNC Synchronization byte always D5 XXXXXXXX TARGET ID ID1 ID2 or OxFF Logical address of the target device s XXXXXXXX CONTROL Configuration Control Byte Data Block 11XXXXXX BYTE ADDRESS Starting Byte Address DATA_FOLLOWS 1 first XXXXXXXX BANK ADDRESS Starting Bank address XXXXXXXX DATA COUNT Data byte count a value of 00 instructs 256 bytes XXXXXXXX DATA 0 Data byte to write to starting address 0 XXXXXXXX DATA 1 Data byte to write to starting address 1 Remaining data bytes if any go in this region XXXXXXXX DATA n Data byte to write to starting address n XXXXXXXX CRC MSB Most significant byte of CRC16 error code ae or or depending on Bit 5 of BYTE ADDRESS ERR Basic error check byte 00101010 2A XXXXXXXX CRC LSB Least significant byte of CRC16 error code if used Remaining data blocks if any go in this region Data Block 10XXXXXX BYTE ADDRESS Starti
51. in 3 1 11 DIN Data In DIN is the serial data input pin During power up this pin is ignored During configuration or reconfiguration DIN is the serial data input for configuration data There is a weak internal pull up on DIN which if configured ensures a valid logic state after an attached serial EPROM goes tri state 3 1 12 CS1b Chip Select 1 Prior to Primary Configuration while CS1b and CS2b are both low DCLK is used to clock the configuration state machine Once Primary Configuration is complete signals on CS1b are delayed by 8 clocks and passed to LCCb CS1b therefore behaves as an active low chip select CS1b should be synchronous to the configuration clock DCLK Note that CS1b is actually an intelligent polling I O although this function is entirely transparent to the user It operates on a cyclic basis writing a weak logic 1 out during the high period of the clock and reading the logic state on the pin during the low period of the clock On the next rising edge of the clock the logic state on the CS1b pin is latched internally See section 3 3 3 for further details on the LCCb to CS1b connection 3 1 13 CS2b Chip Select 2 CS2b is an active low chip select input pin CS2b should be synchronous to the configuration clock It is sampled at the end of the power up period and if high it stops the ERRb pin from going high Completion of power up is delayed until CS2b goes low A user can therefore delay configuration by h
52. ing power up sources SPI EPROM initialization command string SPIMEM After power up sources selected internal analog clock or comparator output PORb Input 0 Chip Held in reset state Rising Edge re initiates power on reset sequence 30 mS to complete ERRb Input 0 Initiate Reset hold low for 15 clocks 1 No Action O D Output 0 Error Condition 10 kQ p u reqd Z No Error Condition ACTIVATE Input 0 Hold off completion of configuration Rising Edge Complete configuration O D Output 0 Device has not yet completed Primary Configuration Z Device has completed Primary Configuration LCCb Output 0 Local configuration complete 1 Local configuration is not complete Once configuration is completed it is a delayed version 8 clock cycles of CS1b or if the device is addressed for read it serves as serial data read output port CFGFLGb Input In multi device systems 0 Ignore incoming data unless currently addressed 1 Pay attention to incoming data watching for address O D Output 0 Device is being reconfigured Z Device is not being reconfigured DIN Input Serial Configuration Data Input CS1b Input Prior to completion of a Primary Configuration 0 Allow configuration to proceed 1 Hold off configuration Input After completion of a Primary Configuration Data input pin serves as a serial data pass through port for a multi device chain CS2b Input 0 Chip is selected 1 Chip is not selected EXECUTE Input 0 No Action This pin should
53. ion 2 1 The filter may be bypassed or set to selected corner frequencies Whereas the filter structure served as an anti aliasing filter for the input in the Output Cell it serves as a 204 order reconstruction filter In this function it smooths out the sampling induced stairstep nature of the output waveform A differential to single converter circuit follows the programmable filter After the programmable filter and the DIFF2SINGLE conversion the system designer may elect to utilize only one of the OUT signals referencing it to Voltage Main Reference VMR or use them both OUT and OUT as a differential pair Remember that a single ended output will have half the amplitude of a differential signal Copyright O 2003 Anadigm Inc All Rights Reserved 5 UM021200 U007g AN121E04 AN221E04 Device User Manual 2 4 Configurable Analog Block Within the device there are four Configurable Analog Blocks CABs The functions available in the CAM library are mapped onto these programmable analog circuits Figure 5 shows an overview of the Configurable Analog Block CAB Control Shadow SRAM Logic Configuration SRAM Global Local SEPP EE EE NOL Clock LUT Generator Interface Logic 1234 _ Analog Clocks Ep RI Figure 5 Overview of a Configurable Analog Block Among the many analog switches within the CAB some are static and determine things like the general CAB circuit connections capacitor val
54. ir to Voltage Main Reference VMR is the reference point for all internal signal processing and is set at 2 0 V above AVSS From a Array T Programmable Gain Programmable fe PINS Amplifier gt To 101P Li gt Array IO1N 070 Ti Rp Chopper Stabilized i Amp with Gain 2 n 4 5 6 7 1 Single Ended Input Figure 2 A Configurable Input Output Cell there are three As with any sampled data system it may sometimes be necessary to low pass filter the incoming signal to prevent aliasing artifacts The input path of the cell contains a second order programmable anti aliasing filter The filter may be bypassed or set to selected corner frequencies When using the anti aliasing filter Anadigm recommends that the ratio of filter corner frequency to maximum signal frequency should be at least 30 These filters are a useful integrated feature for low frequency signals signals with frequency up to 15kHz only and if high order anti aliasing is required Where input signal frequencies are higher Anadigm does recommend the use of external anti aliasing A second unique input resource available within each Input Output Cell is an amplifier with programmable gain and optional chopper stabilizing circuitry The chopper stabilized amplifier greatly reduces the input offset Copyright 2003 Anadigm Inc All Right
55. k Features and Clock Domains issu 9 Configuration Interface Figure 8 Pins Associated with Device Configuration oooonnncccnnnnnococccnnnocccncnnonononc ennen keen ennen ren kreere kernerne 11 Figure 9 System Clocks when Configuration MODE 0 ss 12 Figure 10 System Clocks when Configuration MODE 1 mvvrennnvvrnvnnnsvvrnnenrrrvrnensrennrnnesrrnnnrreesrennrrressennnnnne 12 Figure 11 Known Compatible Crystals sise 13 Figure 12 Known Compatible 25 Series SPI Memory Devices rnnnnnsnvrnnnnnnnvvrnnnnnnnvrnnnnrennnrrenerennrrresrennnnne 17 Figure 13 A Typical SPI EPROM Connection iii 17 Figure 14 SPI EPROM Initial Timing Sequence 24 ES cnn nn rro EEN KLEE SN 17 Figure 15 SPI EPROM Completion Sequence occcccccconcncnocononccnncnncnnncnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnrnnnnnnnennns 18 Figure 16 Known Compatible 17 Series Serial EPROM Memory Devices ooocoocccccoccoccccnccconcnnncnanonancnannnnos 18 Figure 17 A Typical Serial FPGA EPROM Connection iii 18 Figure 18 Serial FPGA EPROM Initial Timing Sequence rurrnrrrnnnarnnvvrnnnnnrnnrnnnnnrnnnrnnrennnrrensrennrrresrennnnnn 19 Figure 19 Serial FPGA EPROM Completion Sequence ss 19 Figure 20 Connecting Multiple FPAAs to a Single Configuration Memory Using a Crystal 20 Figure 21 Multiple Device Serial EPROM Boot Handoff c ioocccocinccccccccococccnccnonononanannnano na nr nn ennen na nnnnnnncnr cnn 20 Fig
56. l destabilize the CAB op amps The minimum recommended external load resistance should be not less than 100 KQ and the maximum external load capacitance should be not more than 100 pF When using bypass mode outputs characterization of the final system is essential 2 1 2 Special Consideration for Bypass Mode Inputs It is not recommended to use an Input Output Cell as a bypass mode input Anadigm recommends that you use at least the unity gain buffer in the Input Output Cell when configured as an input 2 2 Muxed Analog Input Output There is a bidirectional multiplexer available in front of one of the Input Output Cells This allows the physical connection of 4 single ended or 4 differential pair input sources or 4 differential pair output loads at once though only one source or load at a time can be processed by the FPAA As with the regular Input Output Cells the optimal input connection is from a differential signal source If a single ended connection is programmed the negative side of the internal differential pair will be connected to Voltage Main Reference PINS m From I04PA kJ MN 104NA kE 104PB E ian Programmable Gain Programmable fg Amplifier gt To 104NB to SE Ls Array oo 104PC k To o IO4NCk 3 i Z i Chopper Stabilized L Out 4 Amp with Gain 2 1 n 4 5 6 7 3 104PDk i
57. machine 3 1 7 ERRb Error This is an open drain input output pin An external pull up resistor should be attached to this pin typically 10 kQ In large multi device systems this pull up may be reduced to 5K to overcome loading effects Initially during power up this pin serves as an output and is asserted low by the device As the power on reset sequence progresses the ERRb pin is released and is pulled up by the external resistor allowing the configu ration sequence to commence If there is more than one FPAA in a system then the ERRb pins should be tied together This forces power up to be delayed until ERRb has been released in all devices Different device types will take different times to power up The rising edge of ERRb is therefore used to synchronize all FPAAs in the system to the same incoming clock cycle Once ERRb goes high configuration can begin Copyright 2003 Anadigm Inc All Rights Reserved 13 UM021200 U007g AN121E04 AN221E04 Device User Manual A user can manually delay the start of configuration by externally pulling ERRb low from power up An alternative method for delaying configuration is to hold the CS2b pin high during power up ERRb will not be released until CS2b is taken low ERRb remains high during configuration and reconfiguration unless an error occurs An error condition is indicated by ERRb being asserted low by the device in which the error occurs As controlled by the configuration data set
58. most commonly used as FPGA configuration memories As system power comes up the device first completes its internal power on reset checks the state of the CS1b and CS2b pins and if set correctly will then provide the necessary signalling to read data out of either of these two common EPROM types Once the read of configuration data is complete the device will automati cally activate the analog circuitry The entire power on reset and configuration process is automatic Copyright O 2003 Anadigm Inc All Rights Reserved 16 UM021200 U007g 3 3 1 Boot from SPI EPROM A typical connection scheme for an industry standard 25 series SPI EPROM is shown in Figure 13 Once the device s internal power on reset sequence completes CFGFLGb will assert low selecting the memory device The OUTCLK SPIMEM pin sends serial command words to the SPI memory instructing it to begin delivering data starting from its internal address 0 At the appropriate time the FPAA will start paying attention to its DIN pin expecting a SYNC byte followed by configuration data If there is any error encountered during this process ERRb will assert low and the device will ignore all subsequent serial data Mfr Part Number Atmel AT25080 Xicor X5043 Microchip 25AA160 Fairchild NM25C640 Figure 12 Known Compatible 25 Series SPI Memory Devices DA SPI EPROM AN1 221E04 MISO
59. n drain bi directional pin controlling logic which achieves this function Consider Figure 20 Out of reset each FPAA drives ACTIVATE low Each device will continue to drive ACTIVATE low until its configuration is completed at which time it is released Only when the ACTIVATE net pulls high which in our example will only happen after the both devices receive their configuration will the analog circuitry be allowed to go active ACTIVATE has an optional internal pull up resistor that may be enabled via the device s configuration data set In a multi FPAA system it is recommended that a single external pull up be used 3 4 4 Advanced Feature Return Read Data Path AN221E04 Only In most applications the function of the LCCb pin is to signal that a configuration has been completed For more advanced applications a read back data path may be beneficial These applications take advantage of the fact that once a Primary Configuration is complete LCCb becomes a serial data output pin If the device is addressed for a read LCCb sources the data out If the device is not addressed for a read then LCCb registers out the state of the CS1b input pin with an 8 clock latency Read data is presented on the LCCb pin of the addressed device after a delay of 16 clocks Figure 32 shows several devices connected correctly for serial configuration and subsequent read back 3 5 Configuration Protocol Serial data no matter how it comes into the device must
60. n this block s control byte the immediate transfer from Shadow RAM to the Configuration RAM will occur here The 8 clocks at the end of each of these configurations are necessary only to complete the transfer at that time If it is not critical to complete the transfer at that particular moment then the clocking asso ciated with any subsequent Update block will be sufficient to complete the transfer With no clocks the configuration state machine simply freezes in place There are no unsafe states 3 5 6 Configuration Clocking Considerations The state machines within the device s configuration logic require a clock in order to function correctly In most of the configuration connection examples above the clock is not free running so in addition to adhering to the protocols described the host processor must also provide clocks to allow the state machines to complete their reset and data transfer sequences If the appropriate clocks are not provided the state machines will idle and the reset or configuration will not complete as expected Out of power up the configuration logic requires 40 clocks to complete its reset sequence After any configu ration or reconfiguration the configuration logic requires 8 clocks to complete the data transfer Copyright O 2003 Anadigm Inc All Rights Reserved 33 UM021200 U007g AN121E04 AN221E04 Device User Manual 4 Mechanical 4 1 Package Pin Out
61. ne key aspect The AN221E04 device is dynami cally reconfigurable This device is optimized so that it can be updated partially or completely while operating The AN121E04 device can also be reprogrammed as many times as desired however the device must first be reset before issuing another configuration data set The significant difference between the AN221E04 and AN121E04 devices is that once a Primary Configuration is complete the configuration interface of the AN121E04 device ignores all further input No further data writes are accepted unless a reset sequence is first completed Dynamic Reconfiguration available on the AN221E04 device allows the host processor to send new configu ration data to the FPAA while the old configuration is active and running Once the new data load is complete the transfer to the new analog configuration happens in a single clock cycle Dynamic Reconfiguration in the AN221E04 device allows the user to develop innovative analog systems that can be updated fully or partially in real time The Field Programmable Analog Array FPAA contains 4 Configurable Analog Blocks CABs in its core Most of the analog signal processing occurs within these CABs and is done with fully differential circuitry The four CABs have access to a single Look Up Table LUT which offers a new method of adjusting any programmable element within the device in response to a signal or time base It can be used to implement arbitrary input to
62. ng Byte Address DATA FOLLOWS 0 as XXXXXXXX BANK ADDRESS Starting Bank address XXXXXXXX DATA COUNT Data byte count a value of 00 instructs 256 bytes XXXXXXXX DATA 0 Data byte to write to starting address 0 XXXXXXXX DATA 1 Data byte to write to starting address 1 Remaining data bytes if any go in this region XXXXXXXX DATA n Data byte to write to starting address n XXXXXXXX CRC MSB Most significant byte of CRC16 error code or or or depending on Bit 5 of BYTE ADDRESS 00101010 2A ERR Basic error check byte XXXXXXXX CRC LSB Least significant byte of CRC16 error code if used Figure 31 Update Data Stream Structure Copyright O 2003 Anadigm Inc All Rights Reserved 30 UM021200 U007g TM ana 10 TARGET ID Special Feature AN221E04 Only ID1 the primary logical address is established for the device during the Primary Configuration The configuration data itself establishes ID2 the alternate logical address for the device Once the Primary Configuration is complete a device will respond to any Update format configuration data stream which contains either a matching ID1 value a matching ID2 value or OxFF in the TARGET ID byte field The hex address of OxFF serves as a global ID all devices respond to this ID A A SPI Port Micro GPIO k MOSI AN221E04 AN221E04 AN22
63. olding CS2b high from power up Once CS2b goes low ERRb goes high and configuration begins CS2b is logically NOR ed with CS1b and the output is used to gate the incoming clock to the configuration circuitry In other words when CS1b and CS2b are both low the clock is enabled To ensure that this gating always results in a clean clock to the main configuration state machine CS2b should be synchronous to the configuration clock It is important to note that when booting from either a Serial EPROM or SPI EPROM CS2b must remain low throughout configuration otherwise the data clocked out of the EPROM will not be clocked into the device This happens because CS2b does not stop data being clocked out of the EPROM but does stop it from being clocked into the device After configuration CS2b continues to act with CS1b as a clock enable for the device A user can therefore hold CS2b high after configuration to reduce power consumption in the device Copyright O 2003 Anadigm Inc All Rights Reserved 15 UM021200 U007g AN121E04 AN221E04 Device User Manual 3 1 14 EXECUTE The EXECUTE input pin should normally be tied low 3 2 Resets The available sources of reset include a hard power cycle asserting ERRb low for not less than 15 DCLK s pulsing PORb low issuing a software reset during the Primary Configuration or after an error occurs during a Primary Configuration and ERRb asserts low Assume ERRb is not actively driven and only p
64. or Optimal PCB Design Ground Planes Your PCB design should include some of the following features to ensure good separation between the digital and analog signal environments in your system Good PCB design practices dictate that the digital and analog power and ground planes be separated It is important to maintain these planes at the same basic potential but care should be exercised to prevent the usual noise of a digital plane from coupling onto the analog plane In Figure 33 the electrical connection between the two planes is made at only two points through Ferrite bead choked wire The Ferrite beads act as low pass filters As with any mixed signal board design it is good practice to keep digital signals especially digital signals with high edge rates routed only over areas where digital power and ground planes underlay Care should be exercised to never route a high edge rate digital signal perpendicular to a plane split Doing so will cause a noise wavefront to launch left and right onto both planes along the split It is recommended that the digital supply DVDD be bypassed to DVSS using ceramic capacitors A 1 uF capacitor in parallel with a 01 uF capacitor is usually sufficient The capacitor connections to the device should be made as close as practical to the package to reduce detrimental inductance This same bypassing scheme will work sufficiently for BVDD BVSS AVDD AVSS AVDD2 AVSS SHIELD AVSS pairs as well Copyri
65. ortex solution include e Analog design time reduction from months to minutes e Faster time to solution compared to discretes or ASIC e High precision operation despite system degradation and aging e Eliminating the need to source and maintain multiple inventories of product Ability to implement multiple chip configurations in a single device and to adapt functionality in the field The Anadigmvortex solution allows OEMS to deliver differentiated solutions faster and at lower overall system cost Copyright O 2003 Anadigm Inc All Rights Reserved UM021200 U007g Legal Notice Anadigm reserves the right to make any changes without further notice to any products herein Anadigm makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Anadigm assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including with out limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Anadigm does not in this manual convey any license under its patent rights nor the rights of others Anadigm software and associated products cannot be used except strictly in accordance with an Anadigm software license The terms of the
66. output transfer functions companding sensor linearization generate arbitrary signals even perform voltage dependent filtering A Voltage Reference Generator supplies reference voltages to each of the CABs within the device and has external pins for the connection of filtering capacitors ss Xx w a O ES Z w E C g F amp 2 3255 3 2 2 5 o 5 5 250 A Output Output 5 1 Cell 2 Cell 1 Oscillator T 7 TT 8 Clocks Output Only Analog Switch Fabric Analog Logic k MODE Connects any CAB to any Output Cell 1234 2 oa 101P ka a 63 s DVDD 0 loin 1339 H _ 2 3 ES 2 2 3 lels s PIN O SE Sle o 23 8 5 CAB CAB2 JE o HO Loco 3 z 2 O PE Fars dE HG EL Erro 1 3 35 2 2 ION k 8 by 2 E E LJ activate 12 gt gt 5 25 T O k EXECUTE co 3 lt a S kH PORb 1037 30 A ES e z 2 a amp Se E CFGFLGb ioan KDE KILE Sle glz 5 PU e ag a E ES O SE l capa ca a Bla gt E g 104PA KA a 3 8 2 gt 3 8 cs2b oaa Ky Sek IE AG 0 8 DVSS 104PB ky Bkz ky 104NB ka 2 Ker ma ER 104N ks VREF VMR VREF dk Volt Ref Look Up Table 104PD CH oltage Refren
67. ral bus interface 3 4 1 Synchronous Serial Interface Connections SPI and SSI As far as the device is concerned the SPI and SSI interfaces are one in the same There is a signal to indicate data is coming a serial data line and a serial data clock The only real differences between SSI and SPI connections are the names various hosts assigns these signals and the frequencies with which the host can drive them Functionally these two connection schemes are the same a4 SPI Port Micro GPIOk Y AN1 221E04 Mosi DIN ACTIVATE ERRb GPIO A PORb crcrLebl T GPIO cs2b EXECUTE CS1b Y Zonfigured L LCCb acik DOUTCLK lt 40 MHz LT LTL CLK scik 40 MHz DCLK op OUTCLK Figure 24 Typical Host SPI Port Connection Microprocessors with SPI ports are quite a bit more common than those with SSI ports The only down sides to using a SPI port is that they are considerably slower than SSI and as such are rarely supported by DMA transfer capability SSI ports on the other hand often run at or near the microprocessor s bus speed and are sometimes supported by DMA channels SSI Port Micro GPIO AN1 221E04 spo DN ACTIVATE ERRb GPIO A PORb CFGFLGb FRAME cs2b GPIO KJ EXECUTE CS1b VConfigured al LCCb acik DOUTCLK lt 40 MHz LT LTL CLK scik 40 MHz DCLK op OUTELK Figure 25 A Typical Host SSI Port Connection
68. s Reserved 3 UM021200 U007g AN121E04 AN221E04 Device User Manual voltage normally associated with op amps This can be very useful for applications where the incoming signal is very weak and requires a high gain amplifier at the input The programmable gain of the amplifier can be set to 2 where n 4 through 7 The output of the amplifier can be routed through the programmable anti aliasing input filter or directly into the interior of the array into a Configurable Analog Block CAB Single ended input signals must use either the amplifier or the anti alias filter in order to get the required single to differential conversion The programmable gain amplifier the chopper stabilized amplifier and the programmable anti aliasing filter are all resources available only on the input signal path When the Input Output Cell is used as an output the connection is a direct unbuffered connection of an internally sourced signal There are no active circuit elements available in the Input Output cell when it is configured as an output 2 1 1 Special Consideration for Bypass Mode Outputs When using either an Output Cell or an Input Output Cell in bypass output mode special care must be taken to not overload the device In bypass mode there are no amplifiers between the signal source within within the CABs and the device s output pins The CAB op amps are not designed to drive low resistive impedances Also too much load capacitance wil
69. the device will be reset to a point where only an Update is required Review section 3 1 7 for further explanation Factory Reserved 1 Factory Reserved setting 0 Normally set to 0 It is recommended that the default bit values of the Control Byte always be used For more information on Configuration SRAM and LUT read back and other advanced features please contact Anadigm technical support Data downloaded into the device is placed into Shadow SRAM In order to keep any disruption of analog processing to a minimum the transfer from Shadow SRAM to Configuration SRAM occurs in a single clock cycle Using the default control byte value in particular ENDEXECUTE 1 this transfer will happen automat ically at the completion of any configuration data download Copyright O 2003 Anadigm Inc All Rights Reserved 27 UM021200 U007g AN121E04 AN221E04 Device User Manual BYTE ADDRESS BYTE Bit Number 61514 3 210 BYTE ADDRESS Starting byte address of Shadow SRAM to be loaded Factory Reserved Factory Reserved setting Should normally be set to 0 DATA_FOLLOWS subsequent Data Block will be expected by the configuration logic This block is presumed to be the final block of configuration data CONSTANT 1 Must always be set to 1 Undefined operation oo oa BANK ADDRESS BYTE Bit Number 765432 10 BA
70. ues and which input is active Other switches are dynamic and can change under control of the analog input signal the phase of the clock selected and the SAR logic Whether static or dynamic all of the switches are controlled by the Configuration SRAM As part of the power on reset sequence SRAM is cleared to a known safe state It is the job of the configu ration logic to transfer data from the outside world into the Shadow SRAM and from there copy it into the Configuration SRAM The AN221E04 device allows reconfiguration While an AN221E04 device is operating the Shadow SRAM can be reloaded with values that will sometime later be used to update the Configuration SRAM In this fashion the FPAA can be reprogrammed on the fly accomplishing anything from minor changes in circuit characteristics to complete functional context switches instantaneously and without inter rupting the signal path The AN121E04 device must be reset between complete configuration loads and does not accept partial reconfigurations Analog signals route in from the cell s nearest neighbors using local routing resources These input signals connect up to a first bank of analog switches Feedback from the CAB s two internal opamps and single comparator also route back into this input switch matrix Next is a bank of 8 programmable capacitors Each of these 8 capacitors is actually a very large bank of very small but equally sized capacitors Each of these 8 programmable c
71. ulled high through an external pull up resistor and PORb is similarly pulled high After power is applied to the device an internally generated power on reset pulse resets the power up and configuration state machines The power on reset pulse also resets the configuration memory The power up state machine does not start until a clock becomes valid and has clocked 5 times This help protect the system from functioning until the clock is stable Thereafter the power up state machine takes control Once power up is complete the configuration state machine becomes active and configuration proceeds Assume the device is configured and operating normally Driving ERRb low for longer than 15 configuration clock cycles will cause the device to reset The device will become active and configuration can occur once again Assume the device is configured and operating normally with ERRb pulled up high If PORb is driven low the device will reset Holding PORb low keeps the device in a power on reset condition When PORb is finally released to a high state the power on reset circuitry will recognize a rising edge on PORb and be tricked into thinking that the device is powering up The normal power up sequence will repeat 3 3 Booting from EPROM The simplest method of configuring the device is to let it self boot from a non volatile serial memory The FPAA is directly compatible with both industry standard 25 series SPI EPROMs and 17 series Serial EPROMs
72. ure 22 Connecting Multiple FPAAs to a Single Configuration Memory Driving DOLK ee 21 Figure 23 Using DOUTCLK in a Multi Device System rrnnnannvnvrnnnnnnsvvrnnnnnnnnvrnnnnnernrnnnrrennnrrrnnrennrrresernnnnne 21 Figure 24 A Typical Host SPI Port Connection iii 22 Figure 25 A Typical Host SSI Port Connection sise 22 Figure 26 Typical Microprocessor External Bus Connection W Wu u u dsssesereeeeeeeeren eee ken r nc narran rca 23 Figure 27 Timing Sequence for Booting from a Host MicroprocesSor ooccccccccocccnccnccnncnonanan nana nonnnncnrnnnnnno 23 Figure 28 Primary Configuration Data Stream Structure ooocccnnnccocccnnnnocconcnnonono nana nnncnnncnn naar nana enn rra 25 Figure 29 The Components of the 32 Bit JTAG Identification Number rurnnrrrnnnnonnrnnnnnnnnnrrennnrnnrrrensrnnnnne 26 Figure 30 AN1 220E04 Memory Allocation Table oooooconnnncccnnnnnococccnnoncccncnnonnno nana nonnn een nere ker rra 28 Figure 31 Update Data Stream Structure iii 30 Figure 32 Configuring Multiple Devices from a Host Processor rarrsnrrnnnnnvnnvrnnnnnnnnrnnnnrrnnnrrenrrrnnrrresrrnnnnnn 31 Mechanical Figure 33 Basic Guidelines for Optimal PCB Design Ground Planes rurrurvrnnnnvnnrrnnnrennnrrnnnrrnnrrrrrrrnnnnnn 35 Copyright O 2003 Anadigm Inc All Rights Reserved iii UM021200 U007g TM ana 10 1 Architecture Overview The AN121E04 and the AN221E04 devices are different in o
73. ved 28 UM021200 U007g TM ana Ge DATA COUNT BYTE Setting this field to a value of 0x00 signifies that 256 data bytes follow in this data block Setting this field to any integer value between 1 and 255 signifies that exactly that many data bytes follow This byte count only represents the number of configuration data bytes that follow data bytes destined for the Shadow SRAM or LUT SRAM the count does not include the Error check byte DATA BYTE Configuration data bytes This is the data that gets loaded into the Shadow SRAM or LUT SRAM starting at the address defined in BYTE and BANK address bytes defined just above There may 1 up to 256 data bytes per block ERR BYTE The only byte expected after the DATA bytes is the ERR constant 2A If any other value is read in ERRb will assert and the configuration process will be aborted Reconfiguration will be required as described in section 3 1 7 Copyright 2003 Anadigm Inc All Rights Reserved 29 UM021200 U007g AN121E04 AN221E04 Device User Manual 3 5 4 Update Format AN221E04 Only Once a Primary Configuration has been completed there is no longer any requirement for the host to transmit out JTAG ID information or reprogram the ID1 s of the devices along the communication path A configuration data stream doing so would be considered an error and devices would assert ERRb The host now only needs to send out a sync header and a valid 1D for the target device or dev
74. y ratio of 16 to 1 The slower clock SAR clock a k a CLOCKA determines the rate at which successive conversions will occur and should not exceed 250 KHz The faster clock SC clock a k a CLOCKB is used to do the conversion itself These clocks are generated by the normal clock divider circuitry The SAR result is in the sign magnitude format 1 bit sign 7 bits magnitude The SAR inputs should be limited to VMR 1 5 V Inputs going above VREFPC VMR 1 5 V and below VREFMC VMR 1 5 V will result in the output railing to either 7F or FF as appropriate The SAR ADC result can be routed to either the LUT s address port or back into its host CAB The most common use of the SAR ADC is to serve as an address generator for the Look Up Table At the end of every conversion the 8 bit result is recognized by the LUT as a new address The configuration circuitry takes the LUT contents pointed to by this address and loads it into one or two specific locations in the Shadow SRAM A typical use scenario is where an input signal needs to be linearized and or calibrated A signal comes in from the outside world and is presented to the CAB configured to do a SAR ADC conversion The SAR ADC result is routed to the LUT where a linearization table was stored as part of the device s configuration image Using the same mechanism as described for the LUT counter in section 2 5 the configuration circuitry takes the LUT contents pointed to by this address the SAR

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