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6023E/6024E/6025E User Manual

1. National Instruments Corporation 4 5 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Table 4 1 1 0 Connector Signal Descriptions Continued Signal Name Reference Direction Description PFIS UPDATE DGND Input PFI5 Update As an input this is one of the PFIs Output As an output this is the UPDATE AO Update signal A high to low edge on UPDATE indicates that the analog output primary group is being updated for the 6024E or 6025E PFI6 WFTRIG DGND Input PFI6 Waveform Trigger As an input this is one of the PFIs Output As an output this is the WFTRIG AO Start Trigger signal In timed analog output sequences a low to high transition indicates the initiation of the waveform generation PFI7 STARTSCAN DGND Input PFI7 Start of Scan As an input this is one of the PFIs Output As an output this is the STARTSCAN AI Scan Start signal This pin pulses once at the start of each analog input scan in the interval scan A low to high transition indicates the start of the scan PFI8 GPCTRO_SOURCE DGND Input PFI8 Counter 0 Source As an input this is one of the PFIs Output As an output this is the GPCTRO_SOURCE signal This signal reflects the actual source connected to the general purpose counter 0 PFI9 GPCTRO_GATE DGND Input PFI9 Counter 0 Gate As an input this is one of the PFIs Output As an output this is the GPCTRO_GATE signal This signal reflects the act
2. National Instruments Corporation 4 31 6023E 6024E 6025E User Manual Chapter 4 Signal Connections DAQ Timing Conne 6023E 6024E 6025E User Manual detection requirements for each timing signal are listed within the section that discusses that individual signal In edge detection mode the minimum pulse width required is 10 ns This applies for both rising edge and falling edge polarity settings There is no maximum pulse width requirement in edge detect mode In level detection mode there are no minimum or maximum pulse width requirements imposed by the PFIs themselves but there may be limits imposed by the particular timing signal being controlled These requirements are listed later in this chapter ctions The DAQ timing signals are SCANCLK EXTSTROBE TRIG1 TRIG2 STARTSCAN CONVERT AIGATE and SISOURCE Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received A typical posttriggered DAQ sequence is shown in Figure 4 17 Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest in addition to data acquired after the trigger Figure 4 18 shows a typical pretriggered DAQ sequence The description for each signal shown in these figures is included later in this chapter TRIG1 i STARTSCAN CONVERT LOL UEP LP Scan Counter Figure 4 17 Typical Pos
3. 12 uV max Pregain error before calibration 28 mV max Postgain error after calibration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibration reference After calibration gain 1 0 02 of reading max Before calibration 0 00 0 2 75 of reading max Gain 1 with gain error adjusted to 0 at gain 1 0 05 of reading max Amplifier Characteristics Input impedance Normal powered on 1 0 00 eee 100 GQ in parallel with 100 pF Powered Off eee eeeeeeeeeeeeeees 4kQ min Overload a isccisccceti essed escsvessssescsees 4kQ min Input bias current eee eect eee 200 pA Input offset current eee 100 pA CMRR DC to 60 Hz Gain 0 55 10 s sinss ires 85 dB Gain 10 TOO wes desseesecsieses siseses 90 dB National Instruments Corporation A 3 6023E 6024E 6025E User Manual Appendix A Specifications Analog Output 6023E 6024E 6025E User Manual Dynamic Characteristics Bandwidth Signal Bandwidth Small 3 dB 500 kHz Large 1 THD 225 kHz Settling time for full scale step 5 us max to 1 0 LSB accuracy System noise LSBrms not including quantization Gain Dither Off Dither On 0 5 to 10 0 1 0 6 100 0 7 0 8 Crosstalk iccchss echt ohare niet 60 dB DC to 100 kHz Stability Recommended warm up time 15 min Offset temperature coefficient Pregatire niee rekes 15
4. National Instruments Corporation Chapter 4 Signal Connections Mode 1 Input Timing Timing specifications for an input transfer in mode are as follows i T1 i ____ T2 Ta a ad STB i a7 i i A IBF 4 PEER i INTR l RD i T3 T5 f me gt e gt DATA lt Name Description Minimum Maximum Tl STB Pulse Width 100 T2 STB 0 to IBF 1 150 T3 Data before STB 1 20 T4 STB 1 to INTR 1 _ 150 T5 Data after STB 1 50 T6 RD 0 to INTR 0 EE 200 T7 RD to IBF 0 150 All timing values are in nanoseconds Figure 4 13 Timing Specifications for Mode 1 Input Transfer National Instruments Corporation 4 27 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Mode 1 Output Timing Timing specifications for an output transfer in mode 1 are as follows MER WR T4 1 1 1 Ad OBF D mM gt Te L i _ INTR 1 T5 1 me gt ACK DATA p lt Name Description Minimum Maximum Tl WR 0 to INTR 0 250 T2 WR 1 to Output 200 T3 WR 1 to OBF 0 150 T4 ACK 0 to OBF 1 150 T5 ACK Pulse Width 100 T6 ACK 1 to INTR 1 150 All timing values are in nanoseconds Figure 4 14 Timing Specifications for Mode 1 Output Transfer 6023E 6024E 6025E Us
5. Clock frequency or speed Type of video board installed Operating system version Operating system mode Programming language Programming language version Other boards in system Base I O address of other boards DMA channels of other boards Interrupt level of other boards Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title 6023E 6024E 6025E User Manual Edition Date January 1999 Part Number 322072B 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address E Mail Address Phone Fax Mail to Technical Publications Faxto Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway 512 794 5678 Austin Texas 78730 5039 Glossary Prefix Meanings Value p pico 10 2 n nano 10 9 u micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 10 t tera 10 Numbers Symbols degree gt greater than lt less than negative of or minus Q ohm per percent plus or minus posi
6. Custom Cabling National Instruments offers cables and accessories for you to prototype your application or to use if you frequently change board interconnections If you want to develop your own cable however the following guidelines may be useful e For the analog input signals shielded twisted pair wires for each analog input pair yield the best results assuming that you use differential inputs Tie the shield for each signal pair to the ground reference at the source e You should route the analog lines separately from the digital lines e When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise coupling into the analog signals from transient digital signals The following list gives recommended part numbers for connectors that mate to the I O connector on your board Mating connectors and a backshell kit for making custom 68 pin cables are available from National Instruments part number 776832 01 6023E and 6024E Honda 68 position solder cup female connector part number PCS E68FS Honda backshell part number PCS E68LKPA National Instruments Corporation B 1 6023E 6024E 6025E User Manual Appendix B Custom Cabling and Optional Connectors e 6025E AMP 100 position IDC male connector part number 1 750913 9 AMP backshell 0 50 max O D cable part number 74908 1 1 AMP backshell 0 55 max O D cable part number 749854 1 Op
7. Gain Input Range Precision 0 5 10to 10V 4 88 mV 1 0 5 to 5 V 2 44 mV 10 0 500 to 500 mV 244 14 uV 100 0 50 to 50 mV 24 41 uV The value of 1 LSB of the 12 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 12 bit count Note See Appendix A Specifications for absolute maximum ratings Dither When you enable dither you add approximately 0 5 LSBrms of white Gaussian noise to the signal to be converted by the ADC This addition is useful for applications involving averaging to increase the resolution of your board as in calibration or spectral analysis In such applications noise modulation is decreased and differential linearity is improved by the addition of the dither When taking DC measurements such as when checking the board calibration you should enable dither and average about 1 000 points to take a single reading This process removes the effects of quantization and reduces measurement noise resulting in improved resolution For high speed applications not involving averaging or spectral analysis you may want to disable the dither to reduce noise Your software enables and disables the dither circuitry Figure 3 2 illustrates the effect of dither on signal acquisition Figure 3 2a shows a small 4 LSB sine wave acquired with dither off The ADC quantization is clearly visible Figure 3 2b shows what happens when 50 such acquisitions are averaged together quantization is s
8. breakdown voltage bus bus master C C CalDAC CH channel clock CMRR National Instruments Corporation G 3 Glossary the range of frequencies present in a signal or the range of frequencies to which a measuring device can respond a memory address that serves as the starting address for programmable registers All other addresses are located by adding to the base address basic input output system BIOS functions are the fundamental level of any PC or compatible computer BIOS functions embody the basic operations needed for successful use of the computer s hardware resources a signal range that includes both positive and negative values for example 5 V to 5 V the voltage high enough to cause breakdown of optical isolation semiconductors or dielectric materials See also working voltage the group of conductors that interconnect individual circuitry in a computer Typically a bus is the expansion vehicle to which I O or other devices are connected Examples of PC buses are the ISA and PCI bus a type of a plug in board or controller with the ability to read and write devices on the computer bus Celsius calibration DAC channel pin or wire lead to which you apply or from which you read the analog or digital signal Analog signals can be single ended or differential For digital signals you group channels to form ports Ports usually consist of either four or eight digital channels the clock
9. PFI lt 0 9 gt lt Sample Interval Counter TC gt GPCTRO_OUT a Figure 3 3 CONVERT Signal Routing This figure shows that CONVERT can be generated from a number of sources including the external signals RTSI lt 0 6 gt and PFI lt 0 9 gt and the internal signals Sample Interval Counter TC and GPCTRO_OUT Many of these timing signals are also available as outputs on the RTSI pins as indicated in the RTS Triggers section in this chapter and on the PFI pins as indicated in Chapter 4 Signal Connections Programmable Function Inputs Ten PFI pins are available on the board connector as PFI lt 0 9 gt and are connected to the board s internal signal routing multiplexer for each timing signal Software can select any one of the PFI pins as the external source for a given timing signal It is important to note that any of the PFI pins can be used as an input by any of the timing signals and that multiple timing signals can use the same PFI simultaneously This flexible routing scheme reduces the need to change physical connections to the I O connector for different applications National Instruments Corporation 3 7 6023E 6024E 6025E User Manual Chapter 3 Hardware Overview You can also individually enable each of the PFI pins to output a specific internal timing signal For example if you need the UPDATE signal as an output on the I O connector software can turn on the output driver fo
10. and 68 pin connectors A signal description follows the figures National Instruments Corporation 4 1 6023E 6024E 6025E User Manual Chapter 4 Signal Connections ACH8 34 68 ACHO ACH1 33 67 AIGND AIGND 32 66 ACH9 ACH10 31 65 ACH2 ACH3 30 64 AIGND AIGND 29 63 ACH11 ACH4 28 62 AISENSE AIGND 27 61 ACH12 ACH13 26 60 ACHS5 ACH6 25 59 AIGND AIGND 24 58 ACH14 ACH15 23 57 ACH7 DACOOUT 22 56 AIGND DAC1OUT 21 55 AOGND RESERVED 20 54 AOGND DIO4 19 53 DGND DGND 18 52 DIOO DIO1 17 51 DIO5 DIO6 16 50 DGND DGND 15 49 DIO2 5V 14 48 DIO7 DGND 13 47 DIOS DGND 12 46 SCANCLK PFIO TRIG1 11 45 EXTSTROBE PFI1 TRIG2 10 44 DGND DGND 9 43 PFI2 CONVERT 5 V 8 42 PFI3 GPCTR1_SOURCE DGND 7 41 PFI4 GPCTR1_GATE PFI5 UPDATE 6 40 GPCTR1_OUT PFI6 WFTRIG 5 39 DGND DGND 4 38 PFI7 STARTSCAN PFI9 GPCTRO_GATE 3 37 PFI8 GPCTRO_SOURCE GPCTRO_OUT 2 36 DGND FREQ_OUT 1 35 DGND 1 Not available on the 6023E Figure 4 1 1 0 Connector Pin Assignment for the 6023E 6024E 6023E 6024E 6025E User Manual 4 2 National Instruments Corporation Chapter 4 Signal Connections AIGND 1 51 PC7 AIGND 2 52 GND ACHO 3 53 PC6 ACH8 4 54 GND ACH1 5 55 PCS ACH9 6 56 GND ACH2 7 57 PC4 ACH1
11. guaranteed after calibration ae 1 0 mV max vets 200 mV max 6023E 6024E 6025E User Manual Appendix A Specifications 6023E 6024E 6025E User Manual Gain error relative to internal reference After calibration 0 cccccceceeeee Before calibration cccce Voltage Output Rahten disse wete avons Output coupling 0 eects Output impedance eee Current dIVE posisine essnee Protection vs scsecssecinsesteereeensdesrevwesdaeaes Power on state steady state Initial power up glitch Magnitude ceeceeeesreeeseeeeees D tati Oi ssoi reies Power reset glitch Magnitude ceeeeeeesceeeeeeerees Duration cccceceeeesccseceseseeeeees Dynamic Characteristics Settling time for full scale step Slew Tale Joinessa Midscal transition glitch Magnitude ceeeeeeeseeeseeeerees DULratiOn seses aeris eis Stability Offset temperature coefficient Gain temperature coefficient A 6 0 01 of output max 0 75 of output max 10V DC 0 1 Q max 5 mA max Short circuit to ground 200 mV Sys 1 1V 2 0 ms ae 42 2 V 4 2 us 10 us to 0 5 LSB accuracy 10 V us 200 uVrms DC to 1 MHz 12 mV 2 0 us 50 uV C 25 ppm C National Instruments Corporation Appendix A Specifications Digital 1 0 Number of channels O025E geile ai E E S 32 input output 6023E and 60
12. output timing figure 4 28 mode 2 bidirectional timing figure 4 29 signal names used in diagrams table 4 25 to 4 26 TRIGI signal 4 34 to 4 35 TRIG signal 4 35 to 4 36 trigger specifications A 9 digital trigger A 9 RTSI trigger A 9 triggers RTSI See RTSI trigger lines U UISOURCE signal 4 42 to 4 43 unpacking 6023E 6024E 6025E 1 3 UPDATE signal 4 41 to 4 42 V VCC signal table 4 7 VirtualBench software 1 4 voltage output specifications A 6 National Instruments Corporation I 9 Index W waveform generation questions about C 2 to C 3 waveform generation timing connections 4 40 to 4 43 UISOURCE signal 4 42 to 4 43 UPDATE signal 4 41 to 4 42 WFTRIG signal 4 40 to 4 41 WFTRIG signal 4 40 to 4 41 WR signal description table 4 26 mode 1 output timing figure 4 28 mode 2 bidirectional timing figure 4 29 6023E 6024E 6025E User Manual
13. 4 41 GPCTR Timing Summary eee ceeceseceeceseeeeceeeeeeeeeeeeeseseeneeeaes 4 48 Figure B 1 68 Pin E Series Connector Pin Assignment 0 0 0 0 sc ceeeeeeeeeeeeee teers B 3 Figure B 2 68 Pin Extended Digital Input Connector Pin Assignments B 4 Figure B 3 50 Pin E Series Connector Pin Assignment 00 0 0 ceceeeeeeeeeeeeeee tees B 5 Figure B 4 50 Pin Extended Digital Input Connector Pin Assignments B 6 Tables Table 3 1 Available Input Configurations 0 0 0 0 cece cseceseceeceeceseeeeseeeeseesaeaes 3 2 Table 3 2 Measurement Precision sesiunii ie e a R aae 3 3 Table 3 3 Pins Used by PXI E Series Board sseseseeeesseesseseeeseresesresrerrerererrreeees 3 10 Table 4 1 I O Connector Signal Descriptions 20 00 eee eee ceeceseeseeeeeeeeeeeseneeaee 4 4 Table 4 2 WO Si1pmall Summary eresse repos ve ceseeacsaveg ie i E E ESE i EEE 4 7 Table 4 3 Port C Signal Assignments 000 0 eee ceeceeceseeeeeeeeeeeeseesasesecsseeeeeeee 4 23 Table 4 4 Signal Names Used in Timing Diagrams 0 00 0 eee eeeeeee tetas 4 25 National Instruments Corporation ix 6023E 6024E 6025E User Manual About This Manual The 6023 6024 and 6025 E Series boards are high performance multifunction analog digital and timing I O boards for PCI PXI and CompactPCI bus computers Supported functions include analog input analog output digital I O and timing I O This manual describes the electrical and mechanical aspects of the PCI 6
14. B 3 6023E 6024E 6025E User Manual Appendix B Custom Cabling and Optional Connectors 6023E 6024E 6025E User Manual Figure B 2 shows the pin assignments for the 68 pin extended digital input connector This is the other 68 pin connector available when you use the SH1006868 cable assembly with the 6025E GND PC6 PC5 GND PC3 PC2 GND PCO PB7 GND PB5 PB4 GND GND PB1 PBO GND PA6 PA5 GND PA3 PA2 GND PAO 5 V N C N C N C N C N C N C N C N C N C wo R 68 e oe 67 a N 66 wo k 65 oo oO 64 N o 63 to 62 N NX 61 ye oO 60 Ne oa 59 ie EN 58 N ao 57 N N 56 M k 55 DS oO 54 ai o 53 at 52 N 51 i oO 50 oa 49 A 48 _ ao 47 ye 46 45 a o 44 o 43 42 41 40 39 38 37 36 N wo A OH N o 35 PC7 GND GND PC4 GND GND PC1 GND GND PB6 GND GND PB3 PB2 GND GND PA7 GND GND PA4 GND GND PAI GND GND N C N C N C N C N C N C N C N C N C Figure B 2 68 Pin Extended Digital Input Connector Pin Assignments B 4 National Instruments Corporation Appendix B Custom Cabling and Optional Connectors Figure B 3 shows the pin assignments for the 50 pi
15. Conventional LabVIEW Programming Environment LabWindows CVI or VirtualBench NI DAQ Driver Software Personal anaes r Computer or ii Workstation Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware National Instruments Corporation 1 5 6023E 6024E 6025E User Manual Chapter 1 Introduction Register Level Programming The final option for programming any National Instruments DAQ hardware is to write register level software Writing register level programming software can be very time consuming and inefficient and is not recommended for most users Even if you are an experienced register level programmer using NI DAQ or application software to program your National Instruments DAQ hardware is easier than and as flexible as register level programming and can save weeks of development time Optional Equipment 6023E 6024E 6025E User Manual National Instruments offers a variety of products to use with your board including cables connector blocks and other accessories as follows e Cables and cable assemblies shielded and ribbon e Connector blocks shielded and unshielded screw terminals e RTSI bus cables e SCXI modules and accessories for isolating amplifying exciting and multiplexing signals for relays and analog output With SCXI you can condition and acquire up to 3 072 channels e Low channel count signal conditio
16. Direction Description AIGND Analog Input Ground These pins are the reference point for single ended measurements in RSE configuration and the bias current return point for differential measurements All three ground references AIGND AOGND and DGND are connected together on your board ACH lt 0 15 gt AIGND Input Analog Input Channels 0 through 15 Each channel pair ACH lt i i 8 gt i 0 7 can be configured as either one differential input or two single ended inputs AISENSE AIGND Input Analog Input Sense This pin serves as the reference node for any of channels ACH lt 0 15 gt in NRSE configuration DACOOUT AOGND Output Analog Channel 0 Output This pin supplies the voltage output of analog output channel 0 DACIOUT AOGND Output Analog Channel 1 Output This pin supplies the voltage output of analog output channel 1 AOGND Analog Output Ground The analog output voltages are referenced to this node All three ground references AIGND AOGND and DGND are connected together on your board DGND Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply All three ground references AIGND AOGND and DGND are connected together on your board DIO lt 0 7 gt DGND Input or Output Digital I O signals DIO6 and 7 can control the up down signal of general purpose co
17. E3 A2 B2 Refer to the Timing Connections section of Chapter 4 Signal Connections for a description of the signals shown in Figures 3 4 and 3 5 National Instruments Corporation Signal Connections This chapter describes how to make input and output signal connections to your board via the I O connector The I O connector for the 6023 and 6024E has 68 pins that you can connect to 68 pin accessories with the SH6868 shielded cable or the R6868 ribbon cable You can connect your board to 50 pin signal accessories with the SH6850 shielded cable or R6850 ribbon cable The I O connector for the 6025E has 100 pins that you can connect to 100 pin accessories with the SH100100 shielded cable You can connect your board to 68 pin accessories with the SH1006868 shielded cable or to 50 pin accessories with the R1005050 ribbon cable a Caution Connections that exceed any of the maximum ratings of input or output signals on the boards can damage the board and the computer Maximum input ratings for each signal are given in the Protection column of Table 4 2 National Instruments is not liable for any damages resulting from such signal connections 1 0 Connector Figure 4 1 shows the pin assignments for the 68 pin I O connector on the 6023 and 6024E Figure 4 2 shows the pin assignments for the 100 pin I O connector on the 6025E Refer to Appendix B Custom Cabling and Optional Connectors for pin assignments of the optional 50
18. Instruments Corporation PFI PFIO TRIG1 PFI1 TRIG2 PFI2 CON VERT PFI3 GPCTRI1_ SOURCE PFI4 GPCTR1_GATE PFI5 UPDATE PFI6 WFTRIG PFI7 STARTSCAN PFI8 GPCTRO_ SOURCE PFI9 GPCTRO_GATE PGIA Plug and Play devices port posttriggering PPI ppm pretriggering pts National Instruments Corporation G 11 Glossary programmable function input PFI0 trigger 1 PFI1 trigger 2 PFI2 convert PFI3 general purpose counter source PFI4 general purpose counter 1 gate PFI5 update PFI6 waveform trigger PFI7 start of scan PFI8 general purpose counter 0 source PFI9 general purpose counter 0 gate programmable gain instrumentation amplifier devices that do not require DIP switches or jumpers to configure resources on the devices also called switchless devices 1 acommunications connection on a computer or a remote controller 2 a digital port consisting of four or eight lines of digital input and or output the technique used on a DAQ board to acquire a programmed number of samples after trigger conditions are met programmable peripheral interface parts per million the technique used on a DAQ board to keep a continuous buffer filled with data so that when the trigger conditions are met the sample includes the data leading up to the trigger condition points 6023E 6024E 6025E User Manual Glossary pu pulse trains pulsed output Q quantization error R RAM real time referenced
19. Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Under the copyright la
20. PFI You have two output options The first is an active high pulse with a pulse width of 50 to 100 ns which indicates the start of the scan The second action is an active high pulse that terminates at the start of the last conversion in the scan which indicates a scan in progress 6023E 6024E 6025E User Manual 4 36 National Instruments Corporation Chapter 4 Signal Connections STARTSCAN will be deasserted t after the last conversion in the scan is initiated This output is set to tri state at startup Figures 4 25 and 4 26 show the input and output timing requirements for the STARTSCAN signal 1 ty lt q Rising Edge Polarity i Falling Edge Polarity ty 10 ns minimum Figure 4 25 STARTSCAN Input Signal Timing ty lt gt STARTSCAN pe H tw 50 100 ns i a Start of Scan Start Puse ___ i i CONVERT a e 3 STARTSCAN lt lt _ gt tog 10 ns minimum 1 tof i b Scan in Progress Two Conversions per Scan Figure 4 26 STARTSCAN Output Signal Timing The CONVERT pulses are masked off until the board generates the STARTSCAN signal If you are using internally generated conversions the first CONVERT appears when the onboard sample interval counter reaches zero If you select an external CONVERT the first external pulse after STARTSCAN generates a conversion The STARTSCAN pulses should be separated by at least one sc
21. and symbols xi 6023E 6024E 6025E User Manual About This Manual e The Jndex contains an alphabetical list of key terms and topics in this manual including the page where you can find each one Conventions Used in This Manual lt gt bold bold italic italic monospace CompactPCI NI DAQ PC 6023E 6024E 6025E User Manual The following conventions are used in this manual Angle brackets containing numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example DBIO lt 3 0 gt The symbol indicates that the text following it applies only to a specific product a specific operating system or a specific software version This icon to the left of bold italicized text denotes a note which alerts you to important information This icon to the left of bold italicized text denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash Bold text denotes the names of menus menu items parameters dialog boxes dialog box buttons or options icons windows Windows 95 tabs or LEDs Bold italic text denotes an activity objective note caution or warning Italic text denotes variables emphasis a cross reference or an introduction to a key concept This font also denotes text from which you supply the appropriate word or value as in Windows 3 x Text in this font denotes text or characters that you should liter
22. bit ports PA PB PC Each port can be programmed as an input or output port The 82C55A has three modes of operation simple I O mode 0 strobed I O mode 1 and bidirectional I O mode 2 In modes 1 and 2 the three ports are divided into two groups group A and group B Each group has eight data bits plus control and status bits from Port C PC Modes 1 and 2 use handshaking signals from the computer to synchronize data transfers Refer to Chapter 4 Signal Connections for more detailed information Routing 6023E 6024E 6025E User Manual The DAQ STC chip provides a flexible interface for connecting timing signals to other boards or external circuitry Your board uses the RTSI bus to interconnect timing signals between boards and the Programmable Function Input PFI pins on the I O connector to connect the board to external circuitry These connections are designed to enable the board to both control and be controlled by other boards and circuits There are a total of 13 timing signals internal to the DAQ STC that can be controlled by an external source These timing signals can also be controlled by signals generated internally to the DAQ STC and these selections are fully software configurable Figure 3 3 shows an example of the signal routing multiplexer controlling the CONVERT signal 3 6 National Instruments Corporation Chapter 3 Hardware Overview RTSI Trigger lt 0 6 gt P _ gt gt CONVERT
23. connect an external TRIG1 source and an external CONVERT source to two PFI pins 6023E 6024E 6025E User Manual 4 30 National Instruments Corporation Chapter 4 Signal Connections PFIO TRIG1 PFI2 CONVERT TRIG1 Source CONVERT Source l DGND a v I O Connector Figure 4 16 Timing 1 0 Connections Programmable Function Input Connections There are a total of 13 internal timing signals that you can externally control from the PFI pins The source for each of these signals is software selectable from any of the PFIs when you want external control This flexible routing scheme reduces the need to change the physical wiring to the board I O connector for different applications requiring alternative wiring You can individually enable each of the PFI pins to output a specific internal timing signal For example if you need the CONVERT signal as an output on the I O connector software can turn on the output driver for the PFI2 CONVERT pin Be careful not to drive a PFI signal externally when it is configured as an output As an input you can individually configure each PFI pin for edge or level detection and for polarity selection as well You can use the polarity selection for any of the 13 timing signals but the edge or level detection will depend upon the particular timing signal being controlled The
24. in the Timing Connections section later in this chapter Output As an output this is the TRIG AI Start Trigger signal In posttrigger data acquisition sequences a low to high transition indicates the initiation of the acquisition sequence In pretrigger applications a low to high transition indicates the initiation of the pretrigger conversions PFI1 TRIG2 DGND Input PFI1 Trigger 2 As an input this is one of the PFIs Output As an output this is the TRIG2 AI Stop Trigger signal In pretrigger applications a low to high transition indicates the initiation of the posttrigger conversions TRIG2 is not used in posttrigger applications PFI2 CONVERT DGND Input PFI2 Convert As an input this is one of the PFIs Output As an output this is the CONVERT AI Convert signal A high to low edge on CONVERT indicates that an A D conversion is occurring PFI3 GPCTR1_SOURCE DGND Input PFI3 Counter 1 Source As an input this is one of the PFIs Output As an output this is the GPCTR1_SOURCE signal This signal reflects the actual source connected to the general purpose counter 1 PFI4 GPCTR1_GATE DGND Input PFI4 Counter 1 Gate As an input this is one of the PFIs Output As an output this is the GPCTR1_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 1 GPCTR1_OUT DGND Output Counter 1 Output This output is from the general purpose counter output
25. instrument or a specific plug in DAQ board Instrument drivers are available in several forms ranging from a function callable language to a virtual instrument VT in LabVIEW a circuit whose output voltage with respect to ground is proportional to the difference between the voltages at its two high impedance inputs a computer signal indicating that the CPU should suspend its current task to service a designated activity the relative priority at which a device can interrupt scanning method where there is a longer interval between scans than there is between individual channels comprising a scan input output the transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces current output high current output low interrupt request kilo the standard metric prefix for 1 000 or 103 used with units of measure such as volts hertz and meters G 8 National Instruments Corporation kS L LabVIEW LED library linearity LSB MIO MITE MS MSB mux NC Glossary kilo the prefix for 1 024 or 2 used with B in quantifying data or computer memory 1 000 samples laboratory virtual instrument engineering workbench light emitting diode a file containing compiled object modules each comprised of one of more functions that can be linked to other object modules that make use of these functions NIDAQMSC LIB
26. line indicates that data has been loaded into the input latch A low signal indicates the board is ready for more data This is an input acknowledge signal ACK Input Acknowledge Input A low signal on this handshaking line indicates that the data written to the port has been accepted This signal is a response from the external device indicating that it has received the data from your DIO board National Instruments Corporation 4 25 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Table 4 4 Signal Names Used in Timing Diagrams Continued Name Type Description OBF Output Output Buffer Full A low signal on this handshaking line indicates that data has been written to the port INTR Output Interrupt Request This signal becomes high when the 82C55A requests service during a data transfer The appropriate interrupt enable bits must be set to generate this signal RD Internal Read This signal is the read signal generated from the control lines of the computer I O expansion bus WR Internal Write This signal is the write signal generated from the control lines of the computer I O expansion bus DATA Bidirectional Data Lines at the Specified Port For output mode this signal indicates the availability of data on the data line For input mode this signal indicates when the data on the data lines should be valid 6023E 6024E 6025E User Manual 4 26
27. means that you can load the CalDACs with values either from the original factory calibration or from a calibration that you subsequently performed This method of calibration is not very accurate because it does not take into account the fact that the board measurement and output voltage errors can National Instruments Corporation 5 1 6023E 6024E 6025E User Manual Chapter 5 Calibration Self Calibratio vary with time and temperature It is better to self calibrate when the board is installed in the environment in which it will be used Your board can measure and correct for almost all of its calibration related errors without any external signal connections Your National Instruments software provides a self calibration method This self calibration process which generally takes less than a minute is the preferred method of assuring accuracy in your application Initiate self calibration to minimize the effects of any offset gain and linearity drifts particularly those due to warmup Immediately after self calibration the only significant residual calibration error could be gain error due to time or temperature drift of the onboard voltage reference This error is addressed by external calibration which is discussed in the following section If you are interested primarily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration 6023E 6024E 6
28. output 3 5 block diagram 3 1 digital I O 3 6 6023E 6024E 6025E User Manual timing signal routing 3 6 to 3 10 board and RTSI clocks 3 8 programmable function inputs 3 7 to 3 8 RTSI triggers 3 8 to 3 10 IBF signal description table 4 25 mode input timing figure 4 27 mode 2 bidirectional timing figure 4 29 input modes 3 2 See also analog input input range 3 2 to 3 3 exceeding common mode input ranges caution 4 10 measurement precision table 3 3 installation common questions C 2 hardware 2 1 to 2 3 software 2 1 unpacking 6023E 6024E 6025E 1 3 INTR signal description table 4 26 mode input timing figure 4 27 mode output timing figure 4 28 mode 2 bidirectional timing figure 4 29 I O connectors 4 1 to 4 8 exceeding maximum ratings warning 4 1 optional connectors B 2 to B 6 50 pin E Series connector pin assignments figure B 5 50 pin extended digital input connector pin assignments figure B 6 68 pin E Series connector pin assignments figure B 3 68 pin extended digital input connector pin assignments figure B 4 National Instruments Corporation pin assignments table 6023E 6024E 4 2 6025E 4 3 L LabVIEW and LabWindows CVI application software 1 4 manual See documentation mode input timing figure 4 27 mode 1 output timing figure 4 28 mode 2 bidirectional timing figure 4 29 multichannel scanning considerations 3 4 to 3 5 NI DAQ
29. output signal general purpose counter clock source signal general purpose counter up down General Purpose Interface bus synonymous with HP IB The standard bus used for controlling electronic instruments with a computer Also called IEEE 488 bus because it is defined by ANSI IEEE Standards 488 1978 488 1 1987 and 488 2 1987 See referenced single ended measurement system hour the frequency range over which a circuit maintains a level of at least 3 dB with respect to the maximum level a type of digital acquisition generation where a device or module accepts or transfers data after a digital pulse has been received Also called latched digital I O hexadecimal hertz the number of events per second 6023E 6024E 6025E User Manual Glossary in INL input bias current input impedance input offset current instrument driver instrumentation amplifier interrupt interrupt level interval scanning T O 6023E 6024E 6025E User Manual inches integral nonlinearity a measure in LSB of the worst case deviation from the ideal A D or D A transfer characteristic of the analog I O circuitry the current that flows into the inputs of a circuit the resistance and capacitance between the input terminals of a circuit the difference in the input bias currents of the two inputs of an instrumentation amplifier a set of high level software functions that controls a specific GPIB VXI or RS 232 programmable
30. signal sources relative accuracy resolution ribbon cable rise time rms RSE 6023E 6024E 6025E User Manual pullup multiple pulses a form of counter signal generation by which a pulse is outputted when a counter reaches a certain value the inherent uncertainty in digitizing an analog value due to the finite resolution of the conversion process random access memory a property of an event or system in which data is processed as it is acquired instead of being accumulated and processed at a later time signal sources with voltage signals that are referenced to a system ground such as the earth or a building ground Also called grounded signal sources a measure in LSB of the accuracy of an ADC It includes all non linearity and quantization errors It does not include offset and gain errors of the circuitry feeding the ADC the smallest signal increment that can be detected by a measurement system Resolution can be expressed in bits in proportions or in percent of full scale For example a system has 12 bit resolution one part in 4 096 resolution and 0 0244 of full scale a flat cable in which the conductors are side by side the difference in time between the 10 and 90 points of a system s step response root mean square the square root of the average value of the square of the instantaneous signal amplitude a measure of signal amplitude referenced single ended mode all measurements are made with re
31. signal is connected to channel 0 and a 1 mV signal is connected to channel 1 and suppose the PGIA is programmed to apply a gain of one to channel 0 and a gain of 100 to channel 1 When the multiplexer switches to channel 1 and the PGIA switches to a gain of 100 the new full scale range is 50 mV 6023E 6024E 6025E User Manual 3 4 National Instruments Corporation Chapter 3 Hardware Overview The approximately 4 V step from 4 V to 1 mV is 4 000 of the new full scale range It may take as long as 100 us for the circuitry to settle to 1 LSB after such a large transition In general this extra settling time is not needed when the PGIA is switching to a lower gain Settling times can also increase when scanning high impedance signals due to a phenomenon called charge injection where the analog input multiplexer injects a small amount of charge into each signal source when that source is selected If the impedance of the source is not low enough the effect of the charge a voltage error will not have decayed by the time the ADC samples the signal For this reason keep source impedances under 1 kQ to perform high speed scanning Due to the previously described limitations of settling times resulting from these conditions multiple channel scanning is not recommended unless sampling rates are low enough or it is necessary to sample several signals as nearly simultaneously as possible The data is much more accurate and channel to channel in
32. uV C POStEAIN nan enn 240 uV C Gain temperature coefficient 20 ppm C 6024E and 6025E only Output Characteristics Number of channels ecesseeceeeeeeees 2 voltage Resolution seis aisis 12 bits 1 in 4 096 A 4 National Instruments Corporation Max update rate Type of DAC eee ceseeeeeeteees FIFO buffer size cccececeeeeeeeeeeeee Data transfers 0 ccccccccccceeeseeeseeeee DMA mode cccececeeeeseeeeesteeeeeens Accuracy Information Appendix A Specifications 10 kHz system dependent 1 kHz system dependent Double buffered multiplying none DMA interrupts programmed TO Scatter gather Single transfer demand transfer Absolute Accuracy Temp Nominal Range V of Reading Offset Drift Positive Negative FS FS 24 Hours 90 Days 1 Year mV I C 10 10 0 0177 0 0197 0 0219 5 933 0 0005 Transfer Characteristics Relative accuracy INL After calibration cccccceeeee Before calibration 00 DNL After calibration ccccceeeeeee Before calibration 00 MOMNOtonicity ee eeeeeeeeceseeeneceneeeeees Offset error After calibration ccccceceeeee Before calibration 008 National Instruments Corporation A 5 ie 0 3 LSB typ 0 5 LSB max 4 LSB max ay 0 3 LSB typ 1 0 LSB max 3 LSB max 12 bits
33. 0 8 58 GND ACH3 9 59 PC3 ACH11 10 60 GND ACH4 11 61 PC2 ACH12 12 62 GND ACH5 13 63 PC1 ACH13 14 64 GND ACH6 15 65 PCO ACH14 16 66 GND ACH7 17 67 PB7 ACH15 18 68 GND AISENSE 19 69 PB6 DACOOUT 20 70 GND DAC1OUT 21 71 PBS RESERVED 22 72 GND AOGND 23 73 PB4 DGND 24 74 GND pioo 25 75 PB3 DIO4 26 76 GND DIO1 27 77 PB2 bios 28 78 GND DIO2 29 79 PB bios 30 80 GND DIO3 31 81 PBO DIO7 32 82 GND DGND 33 83 PA7 5V 34 84 GND 5V 35 85 PAG SCANCLK 36 86 GND EXTSTROBE 37 87 PAS PFIO TRIG1 38 88 GND PFIV TRIG2 39 89 PA4 PFI2 CONVERT 40 90 GND PFI3 GPCTR1_SOURCE 41 91 PAS PFI4 GPCTR1_GATE 42 92 GND GPCTR1_OUT 43 93 PA2 PFI5 UPDATE 44 94 GND PFI6 WFTRIG 45 95 PA PFI7 STARTSCAN 46 96 GND PFI8 GPCTRO_SOURCE 47 97 PAO PFI9 GPCTRO_GATE 48 98 GND G PcTRo_ouT 49 99 5V FREQ_OUT 50 100 GND Figure 4 2 1 0 Connector Pin Assignment for the 6025E National Instruments Corporation 4 3 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Table 4 1 shows the I O connector signal descriptions for the 6023E 6024E and 6025E Table 4 1 1 0 Connector Signal Descriptions Signal Name Reference
34. 023E PCI 6024E PCI 6025E and PXI 6025E boards from the E Series product line and contains information concerning their operation and programming Organization of This Manual The 6023E 6024E 6025E User Manual is organized as follows National Instruments Corporation Chapter 1 Introduction describes the boards lists what you need to get started gives unpacking instructions and describes the optional software and equipment Chapter 2 Installation and Configuration explains how to install and configure your board Chapter 3 Hardware Overview presents an overview of the hardware functions on your board Chapter 4 Signal Connections describes how to make input and output signal connections to your board via the I O connector Chapter 5 Calibration discusses the calibration procedures for your board Appendix A Specifications lists the specifications of each board Appendix B Custom Cabling and Optional Connectors describes the various cabling and connector options Appendix C Common Questions contains a list of commonly asked questions and their answers relating to usage and special features of your board Appendix D Customer Communication contains forms you can use to request help from National Instruments or to comment on our products and manuals The Glossary contains an alphabetical list and description of terms used in this manual including abbreviations acronyms metric prefixes mnemonics
35. 025E User Manual Your board has an onboard calibration reference to ensure the accuracy of self calibration Its specifications are listed in Appendix A Specifications The reference voltage is measured at the factory and stored in the EEPROM for subsequent self calibrations This voltage is stable enough for most applications but if you are using your board at an extreme temperature or if the onboard reference has not been measured for a year or more you may wish to externally calibrate your board An external calibration refers to calibrating your board with a known external reference rather than relying on the onboard reference Redetermining the value of the onboard reference is part of this process and the results can be saved in the EEPROM so you should not have to perform an external calibration very often You can externally calibrate your board by calling the NI DAQ calibration function To externally calibrate your board be sure to use a very accurate external reference The reference should be several times more accurate than the board itself 5 2 National Instruments Corporation Chapter 5 Calibration Other Considerations The CalDACs adjust the gain error of each analog output channel by adjusting the value of the reference voltage supplied to that channel This calibration mechanism is designed to work only with the internal 10 V reference Thus in general it is not possible to calibrate the analog output gain err
36. 24E Lees 8 input output Compatibility oseese TTL CMOS DIO lt 0 7 gt Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current Vin 0 V 320 WA Input high current Vin 5 V 10 vA Output low voltage Io 24 mA 0 4 V Output high voltage lon 13 mA 4 35 V Power on State eeecceseesteceeeeeneeeeeeees Input High Z 50 kQ pull up to 5 VDC Data transfers werir n Programmed I O PA lt 0 7 gt PB lt 0 7 gt PC lt 0 7 gt 6025E only Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2 2 V 5V Input low current Vin 0 V 100 KQ pull up 75 uA Input high current Vin 5 V 100 KQ pull up 10 uA Output low voltage Ip 2 5 mA 0 4 V Output high voltage Ion 2 5 mA 3 7 V National Instruments Corporation A 7 6023E 6024E 6025E User Manual Appendix A Specifications Timing 1 0 6023E 6024E 6025E User Manual Handshaking ceeeeeeceeseceeeeeeseceneeeee 2 wire Power on state PASO Onenn E E Input High Z 100 KQ pull up to 5 VDC PB lt O JS eek ANES Input High Z 100 kQ pull up to 5 VDC POO 67 gt a arpe oaae hear EES ET Input High Z 100 KQ pull up to 5 VDC Data transfers eeceeeseeeeeceeeeceeeeeeeeeees Interrupts programmed I O Number of channels eee 2 up down counter timers 1 frequency scaler Resolution n a e Counter time
37. 25E User Manual Chapter 4 Signal Connections Programmable Gain Instrumentation Amplifier Vins O PGIA Vm Measured Voltage Vin Vins gt Vin Gain Figure 4 3 Programmable Gain Instrumentation Amplifier PGIA In single ended mode RSE and NRSE signals connected to ACH lt 0 15 gt are routed to the positive input of the PGIA In differential mode signals connected to ACH lt 0 7 gt are routed to the positive input of the PGIA and signals connected to ACH lt 8 15 gt are routed to the negative input of the PGIA AN Caution Exceeding the differential and common mode input ranges distorts your input signals Exceeding the maximum input voltage rating can damage the board and the computer National Instruments is Nor liable for any damages resulting from such signal connections The maximum input voltage ratings are listed in the Protection column of Table 4 2 6023E 6024E 6025E User Manual In NRSE mode the AISENSE signal is connected internally to the negative input of the PGIA when their corresponding channels are selected In DIFF and RSE modes AISENSE is left unconnected AIGND is an analog input common signal that is routed directly to the ground tie point on the boards You can use this signal for a general analog ground tie point to your board if necessary The PGIA applies gain and common mode voltage rejection and presents high input impedance to the analog input signals conne
38. 4 5 6023E 6024E 6025E User Manual 4 14 National Instruments Corporation Chapter 4 Signal Connections Differential Connections for Nonreferenced or Floating Signal Sources Figure 4 6 shows how to connect a floating signal source to a channel configured in DIFF input mode ACH e TO DO Bias resistors coe Floating see text o Co Programmable Gain Signal s J Instrumentation Amplifier Source b 7 so ACH o oo Vin Measured Voltage o s o S Bias o s o ae 4 x eturn 3 Paths 3 e So Input Multiplexers o _ _ _ _ AISENSE yer AIGND O Connector Selected Channel in DIFF Configuration Figure 4 6 Differential Input Connections for Nonreferenced Signals Figure 4 6 shows two bias resistors connected in parallel with the signal leads of a floating signal source If you do not use the resistors and the source is truly floating the source is not likely to remain within the common mode signal range of the PGIA The PGIA will then saturate causing erroneous readings National Instruments Corporation 4 15 6023E 6024E 6025E User Manual Chapter 4 Signal Connections 6023E 6024E 6025E User Manual You must reference the source to AIGND The easiest way is to connect the positive side of the signal to the positive input of the PGIA and connect the negative side of the sig
39. 4 pu PB lt 0 7 gt DIO Ve 0 5 2 5 at 3 7min 2 5 at 5 100 kQ 6025E only 0 4 pu PC lt 0 7 gt DIO Yak 0 5 2 5 at 3 7min 2 5 at 5 100 kQ 6025E only 0 4 pu SCANCLK DO 3 5 at Voc 0 4 5at 0 4 1 5 50 KQ pu EXTSTROBE DO 3 5 at We 0 4 5 at0 4 1 5 50 KQ pu PFIO TRIG1 DIO Veis 0 5 3 5 at Y 0 4 5at 0 4 1 5 50 kQ pu PFI1 TRIG2 DIO Mou 0 5 3 5 at Vee 0 4 5 at0 4 1 5 50 KQ pu PFI2 CONVERT DIO Veg 0 5 3 5 at Voc 0 4 5 at0 4 1 5 50 KQ pu PFI3 GPCTR1_SOURCE DIO Mec 0 5 3 5 at Ve 0 4 5at 0 4 1 5 50 KQ pu National Instruments Corporation 4 7 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Table 4 2 1 0 Signal Summary Continued Signal Impedance Protection Sink Rise Type and Input Volts Source mA Time Signal Name Direction Output On Off mA at V at V ns Bias PFI4 GPCTR1_GATE DIO Ya 0 5 3 5 at Voc 0 4 5 at0 4 1 5 50 kQ pu GPCTR1_OUT DO 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PFIS UPDATE DIO Voa 0 5 3 5 at Voc 0 4 5at0 4 1 5 50 kQ pu PFI6 WFTRIG DIO Yao 0 5 3 5 at Voc 0 4 5 at0 4 1 5 50 kQ pu PFI7 STARTSCAN DIO Vig 0 5 3 5 at Voc 0 4 5 at0 4 1 5 50 kQ pu PFI8 GPCTRO_SOURCE DIO Voc 0 5 3 5 at Voc 0 4 5 at0 4 1 5 50 kQ pu PFI9 GPCTRO_GATE DIO Vee 0 5 3 5 at We 0 4 5at0 4 1 5 50 kQ pu GPCTRO_OUT DO 3 5 at Voc 0 4 5at0 4 1 5 50 kQ pu FR
40. 4E 6025E User Manual 4 24 National Instruments Corporation Chapter 4 Signal Connections 2 Using the following formula calculate the largest possible load to maintain a logic low level of 0 4 V and supply the maximum driving current V I1 R gt R VA where V 04V Voltage across Ry I 46uA 10uA 34 6 V across the 100 KQ pull up resistor and 10 uA maximum leakage current Therefore R 7 1kQ 0 4 V 56 pA This resistor value 7 1 kQ provides a maximum of 0 4 V on the DIO line at power up You can substitute smaller resistor values to lower the voltage or to provide a margin for V variations and other factors However smaller values will draw more current leaving less drive current for other circuitry connected to this line The 7 1 kQ resistor reduces the amount of logic high source current by 0 4 mA with a 2 8 V output Timing Specifications 6025E only This section lists the timing specifications for handshaking with your 6025E PC lt 0 7 gt lines The handshaking lines STB and IBF synchronize input transfers The handshaking lines OBF and ACK synchronize output transfers Table 4 4 describes signals appearing in the handshaking diagrams Table 4 4 Signal Names Used in Timing Diagrams Name Type Description STB Input Strobe Input A low signal on this handshaking line loads data into the input latch IBF Output Input Buffer Full A high signal on this handshaking
41. 68 pin extended digital input sampling rate C 1 connector pin assignments SCANCLK signal figure B 4 DAQ timing connections 4 33 power connections 4 30 description table 4 5 Programmable Peripheral Interface signal summary table 4 7 6025E only 4 22 to 4 23 scanning multichannel 3 4 to 3 5 mode 1 input timing figure 4 27 settling time in multichannel scanning 3 5 mode 1 output timing figure 4 28 signal connections mode 2 bidirectional timing figure 4 29 Port C pin assignments 4 23 analog input 4 8 to 4 19 common mode signal rejection considerations 4 19 power up state 4 24 to 4 25 differential connection signal names used in diagrams considerations 4 13 to 4 16 table 4 25 to 4 26 input modes 4 9 to 4 11 timing specifications 4 25 to 4 29 single ended connection timing connections 4 30 to 4 49 considerations 4 17 to 4 19 DAQ timing connections summary of input connections 4 32 to 4 40 table 4 12 general purpose timing signal types of signal sources 4 8 to 4 9 connections 4 43 to 4 49 analog output 4 20 programmable function input digital I O 4 21 connections 4 31 to 4 32 waveform generation timing connections 4 40 to 4 43 signal sources 4 8 to 4 9 floating signal sources 4 8 to 4 9 ground referenced signal sources 4 9 field wiring considerations 4 49 to 4 50 I O connectors 4 1 to 4 8 exceeding maximum ratings warning 4 1 T O connector signal descriptions table 4 4 to 4 6 s
42. DAQ 6023E 6024E 6025E User Manual Multifunction 1 0 Boards for PCI PXI and CompactPCI Bus Computers 7 NATIONAL i J 1999 Editi gt INSTRUMENTS Part suber Borean Worldwide Technical Support and Product Information http www natinst com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 7940100 Worldwide Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 011 284 5011 Canada Ontario 905 694 0085 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 09 725 725 11 France 0 1 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 India 91805275406 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico D F 5 280 7625 Mexico Monterrey 8 357 7695 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain Madrid 91 640 0085 Spain Barcelona 93 582 0251 Sweden 08 587 895 00 Switzerland 056 200 51 51 Taiwan 02 2377 1200 United Kingdom 01635 523545 For further support information see the Technical Support Resources appendix of this manual Copyright 1999 National Instruments Corporation All rights reserved Important Information Warranty Copyright Trademarks The 6023E 6024E and 6025E boards are warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National I
43. EQ_OUT DO 3 5 at Voc 04 5 at 0 4 1 5 50 kQ pu AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Output Note The tolerance on the 50 kQ pullup and pulldown resistors is very large Actual value may range between 17 KQ and 100 KQ Analog Input Signal Overview The analog input signals for these boards are ACH lt 0 15 gt ASENSE and AIGND Connection of these analog input signals to your board depends on the type of input signal source and the configuration of the analog input channels you are using This section provides an overview of the different types of signal sources and analog input configuration modes More specific signal connection information is provided in the section Analog Input Signal Connections Types of Signal Sources 6023E 6024E 6025E User Manual 4 8 When configuring the input channels and making signal connections you must first determine whether the signal sources are floating or ground referenced Floating Signal Sources A floating signal source is not connected in any way to the building ground system but rather has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples National Instruments Corporation Chapter 4 Signal Connections battery powered devices optical isolators and isolation amplifiers An instrument or device that has an isolated output is a floating signal sourc
44. FO longer latencies can be tolerated In the case of analog output a FIFO permits faster update rates because the waveform data can be stored on the FIFO ahead of time This again reduces the effect of latencies associated with getting the data from system memory to the DAQ device a type of signal conditioning that allows you to filter unwanted signals from the signal you are trying to measure signal sources with voltage signals that are not connected to an absolute reference or system ground Also called nonreferenced signal sources Some common example of floating signal sources are batteries transformers or thermocouples frequency output signal feet grams the factor by which a signal is amplified sometimes expressed in decibels a measure of deviation of the gain of an amplifier from the ideal gain gate signal an unwanted momentary deviation from a desired signal G 6 National Instruments Corporation GPCTR GPCTRO_GATE GPCTRO_OUT GPCTRO_SOURCE GPCTRO_UP_DOWN GPCTR1_GATE GPCTR1_OUT GPCTR1_SOURCE GPCTR1_UP_DOWN GPIB grounded measurement system H h half power bandwidth handshaked digital I O hex National Instruments Corporation G 7 Glossary general purpose counter general purpose counter 0 gate signal general purpose counter 0 output signal general purpose counter 0 clock source signal general purpose counter 0 up down general purpose counter gate signal general purpose counter
45. OURCE unless you select some external source GPCTR1_GATE Signal Any PFI pin can externally input the GPCTR1_GATE signal which is available as an output on the PFI4 GPCTR1_GATE pin As an input the GPCTR1_GATE signal is configured in edge detection mode You can select any PFI pin as the source for GPCTR1_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform such actions as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTR1_GATE signal monitors the actual gate signal connected to general purpose counter 1 This is true even if the gate is being externally generated by another PFI This output is set to tri state at startup 6023E 6024E 6025E User Manual 4 46 National Instruments Corporation Chapter 4 Signal Connections Figure 4 39 shows the timing requirements for the GPCTR1_GATE signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 39 GPCTR1_GATE Signal Timing in Edge Detection Mode GPCTR1_OUT Signal This signal is available only as an output on the GPCTR1_OUT pin The GPCTR1_OUT signal monitors the TC board general purpose counter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for b
46. PB4 PB3 PB2 PB1 PBO PA7 PA6 PA5 PA4 PA3 PA2 PA1 PAO 5 V OJ AJN 8 10 12 POETI 16 18 20 22 24 26 28 30 32 34 36 38 Halal aa Poe 46 48 50 QDADAADNDAADAADAADADADAAANDAADAADADAADADD D D 2 iw Z2Z22Z22Z242Z22Z222Z22 UUVUVUVOVVUDU Zz g g 2222222222222 UUTDT VVVUVUVVCVCVCVCV UD Figure B 4 50 Pin Extended Digital Input Connector Pin Assignments B 6 National Instruments Corporation Common Questions This appendix contains a list of commonly asked questions and their answers relating to usage and special features of your board General Information What is the DAQ STC The DAQ STC is the System Timing Control application specific integrated circuit ASIC designed by National Instruments and is the backbone of the E Series boards The DAQ STC contains seven 24 bit counters and three 16 bit counters The counters are divided into the following three groups e Analog input two 24 bit two 16 bit counters e Analog output three 24 bit one 16 bit counters e General purpose counter timer functions two 24 bit counters The groups can be configured independently with timing resolutions of 50 ns or 10 us With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is quite flexible and completely software configurable New capabilities such as buffered pulse generation equivalen
47. PCTRO_OUT Signal Timing GPCTRO_UP_DOWN Signal This signal can be externally input on the DIO6 pin and is not available as an output on the I O connector The general purpose counter 0 will count down when this pin is at a logic low and count up when it is at a logic high You can disable this input so that software can control the up down functionality and leave the DIO6 pin free for general use GPCTR1_SOURCE Signal Any PFI pin can externally input the GPCTR1_SOURCE signal which is available as an output on the PFI3 GPCTR1_SOURCE pin As an input the GPCTR1_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTR1_SOURCE monitors the actual clock connected to general purpose counter 1 This is true even if the source clock is being externally generated by another PFI This output is set to tri state at startup National Instruments Corporation 4 45 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Figure 4 38 shows the timing requirements for the GPCTR1_SOURCE signal tp 50 ns minimum ty 23 ns minimum Figure 4 38 GPCTR1_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTR1_S
48. R1_SOURCE GPCTR1_GATE GPCTR1_OUT GPCTR1_UP_DOWN and FREQ_OUT GPCTRO_SOURCE Signal Any PFI pin can externally input the GPCTRO_SOURCE signal which is available as an output on the PFI8 GPCTRO_SOURCE pin As an input the GPCTRO_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO_SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTRO_SOURCE signal reflects the actual clock connected to general purpose counter 0 This is true even if another PFI is externally inputting the source clock This output is set to tri state at startup Figure 4 35 shows the timing requirements for the GPCTRO_SOURCE signal National Instruments Corporation 4 43 6023E 6024E 6025E User Manual Chapter 4 Signal Connections tp 50 ns minimum ty 23 ns minimum Figure 4 35 GPCTRO_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTRO_SOURCE signal unless you select some external source GPCTRO_GATE Signal Any PFI pin can externally input the GPCTRO_GATE signal which is available as an output on the PFI9 GPCTRO_GATE pin As an input the GPCTRO_GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPC
49. TRO_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform actions such as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTRO_GATE signal reflects the actual gate signal connected to general purpose counter 0 This is true even if the gate is being externally generated by another PFI This output is set to tri state at startup Figure 4 36 shows the timing requirements for the GPCTRO_GATE signal Rising Edge Polarity 1 t i lt gt Falling Edge Polarity tw 10 ns minimum 6023E 6024E 6025E User Manual Figure 4 36 GPCTRO_GATE Signal Timing in Edge Detection Mode 4 44 National Instruments Corporation Chapter 4 Signal Connections GPCTRO_OUT Signal This signal is available only as an output on the GPCTRO_OUT pin The GPCTRO_OUT signal reflects the terminal count TC of general purpose counter 0 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at startup Figure 4 37 shows the timing of the GPCTRO_OUT signal GPCTRO_SOURCE GPCTRO_OUT Pulse on TC GPCTRO_OUT Toggle Output on TC i TC Figure 4 37 G
50. able at I O connector 4 65 to 5 25 VDC at 1 A Physical Dimensions not including connectors PCI boards eee eee s 17 5 by 10 6 cm 6 9 by 4 2 in PXT boards esenee 16 0 by 10 0 cm 6 3 by 3 9 in I O connector 6023E 6024E uo ccc ceeceecceeseesseeeee 68 pin male SCSI II type National Instruments Corporation A 9 6023E 6024E 6025E User Manual Appendix A Specifications GO25SB iiss ice heeiaiacd Aine 100 pin female 0 05D type Operating Environment Ambient temperature 0 0 0 0 0 to 55 C Relative humidity eee eeeeeeeeee 10 to 90 noncondensing PXI 6025E only Functional Shock 00 eee ee eeeeeeeeeee MIL T 28800 E Class 3 per Section 4 5 5 4 1 Half sine shock pulse 11 ms duration 30 g peak 30 shocks per face Operational random vibration 5 to 500 Hz 0 31 gims 3 axes Storage Environment Ambient temperature eee eee 20 to 70 C Relative humidity occ eee 5 to 95 noncondensing PXI 6025E only Non operational random vibration 5 to 500 Hz 2 5 gms 3 axes F Note Random vibration profiles were developed in accordance with MIL T 28800E and MIL STD 810E Method 514 Test levels exceed those recommended in MIL STD 810E for Category 1 Basic Transportation 6023E 6024E 6025E User Manual A 10 National Instruments Corporation Custom Cabling and Optional Connectors This appendix describes the various cabling and connector options for the boards
51. ally enter from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions and for statements and comments taken from programs Refers to the core specification defined by the PCI Industrial Computer Manufacturer s Group PICMG Refers to the NI DAQ driver software for PC compatible computers unless otherwise noted Refers to all PC AT series computers with PCI or PXI bus unless otherwise noted xii National Instruments Corporation About This Manual PXI Stands for PCI eXtensions for Instrumentation PXI is an open specification that builds off the CompactPCI specification by adding instrumentation specific features National Instruments Documentation The 6023E 6024E 6025E User Manual is one piece of the documentation set for your DAQ system You could have any of several types of manuals depending on the hardware and software in your system Use the manuals you have as follows National Instruments Corporation Getting Started with SCXI If you are using SCXI this is the first manual you should read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software Your SCX hardware user manuals If you are using SCXI read these manuals next for d
52. an be written to the DAC latches The board UI counter normally generates the UPDATE signal unless you select some external source The UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software command register gate UISOURCE Signal Any PFI pin can externally input the UISOURCE signal which is not available as an output on the I O connector The UI counter uses the UISOURCE signal as a clock to time the generation of the UPDATE signal You must configure the PFI pin you select as the source for the UISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low Figure 4 34 shows the timing requirements for the UISOURCE signal 4 42 National Instruments Corporation Chapter 4 Signal Connections tp 50 ns minimum ty 23 ns minimum Figure 4 34 UISOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase normally generates the UISOURCE signal unless you select some external source General Purpose Timing Signal Connections The general purpose timing signals are GPCTRO_SOURCE GPCTRO_GATE GPCTRO_OUT GPCTRO_UP_DOWN GPCT
53. an period National Instruments Corporation 4 37 6023E 6024E 6025E User Manual Chapter 4 Signal Connections A counter on your board internally generates the STARTSCAN signal unless you select some external source This counter is started by the TRIGI1 signal and is stopped either by software or by the sample counter Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence may be gated by either the hardware AIGATE signal or software command register gate CONVERT Signal Any PFI pin can externally input the CONVERT signal which is available as an output on the PFI2 CONVERT pin Refer to Figures 4 17 and 4 18 for the relationship of CONVERT to the DAQ sequence As an input the CONVERT signal is configured in the edge detection mode You can select any PFI pin as the source for CONVERT and configure the polarity selection for either rising or falling edge The selected edge of the CONVERT signal initiates an A D conversion The ADC switches to hold mode within 60 ns of the selected edge This hold mode delay time is a function of temperature and does not vary from one conversion to the next CONVERT pulses should be separated by at least 5 us 200 kHz sample rate As an output the CONVERT signal reflects the actual convert pulse that is connected to the ADC This is true even if the conversions are being e
54. ansferring data to from computer memory differential nonlinearity a measure in least significant bit of the worst case deviation of code widths from their ideal value of 1 LSB digital output software that controls a specific hardware device such as a DAQ board or a GPIB interface board electrically erasable programmable read only memory ROM that can be erased with an electrical signal and reprogrammed electrostatically coupled propagating a signal by means of a varying electric field National Instruments Corporation G 5 6023E 6024E 6025E User Manual Glossary external trigger EXTSTROBE FIFO filtering floating signal sources FREQ OUT ft G 8 gain gain accuracy GATE glitch 6023E 6024E 6025E User Manual a voltage pulse from an external source that triggers an event such as A D conversion external strobe signal first in first out memory buffer the first data stored is the first data sent to the acceptor FIFOs are often used on DAQ devices to temporarily store incoming or outgoing data until that data can be retrieved or output For example an analog input FIFO stores the results of A D conversions until the data can be retrieved into system memory a process that requires the servicing of interrupts and often the programming of the DMA controller This process can take several milliseconds in some cases During this time data accumulates in the FIFO for future retrieval With a larger FI
55. ble 4 6 signal summary table 4 8 PFI8 GPCTRO_SOURCE signal description table 4 6 signal summary table 4 8 6023E 6024E 6025E User Manual Index PFI9 GPCTRO_GATE signal description table 4 6 signal summary table 4 8 PFIs programmable function inputs common questions C 4 to C 5 signal routing 3 7 to 3 8 timing connections 4 31 to 4 32 PGIA programmable gain instrumentation amplifier analog input modes 4 10 to 4 11 differential connections ground referenced signal sources figure 4 14 nonreferenced or floating signal sources 4 15 to 4 16 single ended connections floating signal sources figure 4 18 ground referenced signal sources figure 4 19 physical specifications A 9 to A 10 pin assignments 6023E 6024E figure 4 2 6025E figure 4 3 Port C pin assignments description 4 23 signal assignments table 4 23 posttriggered acquisition figure 4 32 power connections 4 30 power requirement specifications A 9 power up state digital I O 4 24 to 4 25 PPI Programmable Peripheral Interface 6025E only 4 22 to 4 23 changing DIO power up state to pulled low 4 24 to 4 25 digital I O connections block diagram figure 4 22 mode input timing figure 4 27 mode 1 output timing figure 4 28 mode 2 bidirectional timing figure 4 29 Port C pin assignments 4 23 power up state 4 24 to 4 25 6023E 6024E 6025E User Manual l 6 signal names used in diagrams table 4 25 to 4 26 timing spe
56. board carefully Keep cabling away from noise sources The most common noise source in a computer based data acquisition system is the video monitor Separate the monitor from the analog signals as much as possible The following recommendations apply for all signal connections to your board e Separate board signal lines from high current or high voltage lines These lines can induce currents in or voltages on the board signal lines National Instruments Corporation 4 49 6023E 6024E 6025E User Manual Chapter 4 Signal Connections if they run in parallel paths at a close distance To reduce the magnetic coupling between lines separate them by a reasonable distance if they run in parallel or run the lines at right angles to each other e Do notrun signal lines through conduits that also contain power lines e Protect signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running them through special metal conduits For more information refer to the application note Field Wiring and Noise Consideration for Analog Signals available from National Instruments 6023E 6024E 6025E User Manual 4 50 National Instruments Corporation Calibration This chapter discusses the calibration procedures for your board If you are using the NI DAQ device driver that software includes calibration functions for performing all of the steps in the calibration process Calibration refers t
57. both analog output channels and the external reference signal Figure 4 9 shows how to make analog output connections to your board ie DACOOUT OF Channel 0 VOUT 0 Load VOUT 1 eae DAC10UT oad L t to lt Channel 1 Analog Output Channels I O Connector Figure 4 9 Analog Output Connections 6023E 6024E 6025E User Manual 4 20 National Instruments Corporation Chapter 4 Signal Connections Digital 1 0 Signal Connections All Boards All boards have digital I O signals DIO lt 0 7 gt and DGND DIO lt 0 7 gt are the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program all lines individually to be inputs or outputs Figure 4 10 shows signal connections for three typical digital T O applications 5 V A LED Le WW a DIO lt 4 7 gt TTL Signal o gt DIO lt 0 3 gt o 5 V VVV T gt me V DGND 1 0 Connector Figure 4 10 Digital 1 0 Connections Figure 4 10 shows DIO lt 0 3 gt configured for digital input and DIO lt 4 7 gt configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch shown in the figure Digital output applications include sending TTL signals and driving external d
58. bration 5 1 to 5 3 adjusting gain error 5 3 external calibration 5 2 loading calibration constants 5 1 to 5 2 self calibration 5 2 specifications A 9 charge injection 3 5 clocks board and RTSI 3 8 commonly asked questions See questions and answers 6023E 6024E 6025E User Manual l 2 common mode signal rejection considerations 4 19 CompactPCI products using with PXI 1 2 ComponentWorks software 1 4 configuration common questions C 2 hardware configuration 2 3 connectors See I O connectors CONVERT signal DAQ timing connections 4 38 to 4 39 signal routing figure 3 7 custom cabling B 1 to B 2 customer communication xiv D 1 to D 2 D DACOOUT signal analog output signal connections 4 20 description table 4 4 signal summary table 4 7 DACIOUT signal analog output signal connections 4 20 description table 4 4 signal summary table 4 7 DAQ timing connections 4 32 to 4 40 AIGATE signal 4 39 CONVERT signal 4 38 to 4 39 EXTSTROBE signal 4 33 to 4 34 SCANCLK signal 4 33 SISOURCE signal 4 40 STARTSCAN signal 4 36 to 4 38 TRIGI signal 4 34 to 4 35 TRIG signal 4 35 to 4 36 typical posttriggered acquisition figure 4 32 typical pretriggered acquisition figure 4 33 DAQ STC C 1 DATA signal description table 4 26 mode input timing figure 4 27 National Instruments Corporation mode 1 output timing figure 4 28 mode 2 bidirectional timing figure 4 29 DGND signal de
59. c damage to the board Electrostatic discharge can damage several components on the board To avoid such damage in handling the board take the following precautions e Ground yourself via a grounding strap or by holding a grounded object e Touch the antistatic package to a metal part of your computer chassis before removing the board from the package e Remove the board from the package and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any way Do not install a damaged board into your computer e Never touch the exposed pins of connectors Software Programming Choices You have several options to choose from when programming your National Instruments DAQ and SCXI hardware You can use National Instruments application software NI DAQ or register level programming National Instruments Corporation 1 3 6023E 6024E 6025E User Manual Chapter 1 Introduction National Instruments Application Software ComponentWorks contains tools for data acquisition and instrument control built on NI DAQ driver software ComponentWorks provides a higher level programming interface for building virtual instruments through standard OLE controls and DLLs With ComponentWorks you can use all of the configuration tools resource management utilities and interactive control utilities included with NI DAQ LabVIEW features interactive graphics a state of the art u
60. channels Table 3 1 describes the three input configurations Table 3 1 Available Input Configurations Configuration Description DIFF A channel configured in DIFF mode uses two analog input lines One line connects to the positive input of the board s programmable gain instrumentation amplifier PGIA and the other connects to the negative input of the PGIA RSE A channel configured in RSE mode uses one analog input line which connects to the positive input of the PGIA The negative input of the PGIA is internally tied to analog input ground AIGND NRSE A channel configured in NRSE mode uses one analog input line which connects to the positive input of the PGIA The negative input of the PGIA connects to analog input sense AISENSE For diagrams showing the signal paths of the three configurations refer to the Analog Input Signal Overview section in Chapter 4 Signal Connections The boards have a bipolar input range that changes with the programmed gain Each channel may be programmed with a unique gain of 0 5 1 0 10 or 100 to maximize the 12 bit analog to digital converter ADC 3 2 National Instruments Corporation Chapter 3 Hardware Overview resolution With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 2 shows the input range and precision according to the gain used Table 3 2 Measurement Precision
61. cifications 4 25 to 4 29 pretriggered acquisition figure 4 33 programmable function inputs PFIs See PFIs programmable function inputs programmable gain instrumentation amplifier See PGIA programmable gain instrumentation amplifier Programmable Peripheral Interface PPI See PPI Programmable Peripheral Interface PXI products using with CompactPCI 1 2 Q questions and answers C 1 to C 5 analog input and output C 2 to C 3 general information C 1 installation and configuration C 2 timing and digital I O C 3 to C 5 R RD signal description table 4 26 mode 1 input timing figure 4 27 mode 2 bidirectional timing figure 4 29 referenced single ended input RSE See RSE referenced single ended mode register level programming 1 6 requirements for getting started 1 2 to 1 3 RSE referenced single ended mode configuration 4 10 description table 3 2 recommended configuration figure 4 12 single ended connections for floating signal sources 4 18 RTSI clocks 3 8 RTSI trigger lines overview 3 8 National Instruments Corporation Index pins used by PXI E series board T O connectors optional B 2 to B 6 table 5 10 50 pin E Series connector pin signal connection assignments figure B 5 PCI boards figure 3 9 50 pin extended digital input PXI boards figure 3 10 connector pin assignments specifications A 9 figure B 6 68 pin E Series connector pin assignments figure B 3 S
62. controlling the time interval between individual channel sampling within a scan Boards with simultaneous sampling do not have this clock common mode rejection ratio a measure of an instrument s ability to reject interference from a common mode signal usually expressed in decibels dB 6023E 6024E 6025E User Manual Glossary cold junction compensation common mode range common mode signal conversion time CONVERT counter timer crosstalk CTR current drive capability current sinking current sourcing D A DAC DACOOUT DACIOUT 6023E 6024E 6025E User Manual a method of compensating for inaccuracies in thermocouple circuits the input range over which a circuit can handle a common mode signal the mathematical average voltage relative to the computer s ground of the signals from a differential input the time required in an analog input or output system from the moment a channel is interrogated such as with a read instruction to the moment that accurate data is available convert signal a circuit that counts external pulses or clock pulses timing an unwanted signal on one channel due to an input on a different channel counter the amount of current a digital or analog output channel is capable of sourcing or sinking while still operating within voltage range specifications the ability of a DAQ board to dissipate current for analog or digital output signals the ability of a DAQ boar
63. cted to your board Signals are routed to the positive and negative inputs of the PGIA through input multiplexers on the board The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier The amplifier output voltage is referenced to 4 10 National Instruments Corporation Chapter 4 Signal Connections the ground for the board Your board s A D converter ADC measures this output voltage when it performs A D conversions You must reference all signals to ground either at the source device or at the board If you have a floating source you should reference the signal to ground by using the RSE input mode or the DIFF input configuration with bias resistors see the Differential Connections for Nonreferenced or Floating Signal Sources section in this chapter If you have a grounded source you should not reference the signal to AIGND You can avoid this reference by using DIFF or NRSE input configurations Analog Input Signal Connections The following sections discuss the use of single ended and differential measurements and recommendations for measuring both floating and ground referenced signal sources Figure 4 4 summarizes the recommended input configuration for both types of signal sources National Instruments Corporation 4 11 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Signal Source Type Floating Signal Source G
64. d Gate Config CTR Mode Config and CTR Pulse Config advanced level VIs to indicate which function the connected signal will serve Use the Route Signal VI to enable the PFI lines to output internal signals N Caution Zf you enable a PFI line for output do not connect any external signal source to it if you do you can damage the board the computer and the connected equipment 6023E 6024E 6025E User Manual What are the power on states of the PFI and DIO lines on the I O connector At system power on and reset both the PFI and DIO lines are set to high impedance by the hardware This means that the board circuitry is not actively driving the output either high or low However these lines C 4 National Instruments Corporation Chapter C Common Questions may have pull up or pull down resistors connected to them as shown in Table 4 2 These resistors weakly pull the output to either a logic high or logic low state For example DIO 0 will be in the high impedance state after power on and Table 4 2 shows that there is a 50 kQ pull up resistor This pull up resistor will set the DIO O pin to a logic high when the output is in a high impedance state National Instruments Corporation C 5 6023E 6024E 6025E User Manual Customer Communication For your convenience this appendix contains forms to help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the p
65. d to supply current for analog or digital output signals digital to analog digital to analog converter an electronic device often an integrated circuit that converts a digital number into a corresponding analog voltage or current analog channel 0 output signal analog channel output signal G 4 National Instruments Corporation DAQ dB DC DGND DIFF differential input digital port DIO dithering DMA DNL DO drivers E EEPROM Glossary data acquisition 1 collecting and measuring electrical signals from sensors transducers and test probes or fixtures and inputting them to a computer for processing 2 collecting and measuring the same kinds of electrical signals with A D and or DIO boards plugged into a computer and possibly generating control signals with D A and or DIO boards in the same computer decibel the unit for expressing a logarithmic measure of the ratio of two signal levels dB 20log10 V1 V2 for signals in volts direct current digital ground signal differential mode an analog input consisting of two terminals both of which are isolated from computer ground whose difference is measured See port digital input output the addition of Gaussian noise to an analog input signal direct memory access a method by which data can be transferred to from computer memory from to a device or memory on the bus while the processor does something else DMA is the fastest method of tr
66. dependent if you acquire data from each channel independently for example 100 points from channel 0 then 100 points from channel 1 then 100 points from channel 2 and so on Analog Output 6025E and 6024E only These boards supply two channels of analog output voltage at the I O connector The bipolar range is fixed at 10 V Data written to the digital to analog converter DAC will be interpreted as two s complement format Analog Output Glitch In normal operation a DAC output will glitch whenever it is updated with anew value The glitch energy differs from code to code and appears as distortion in the frequency spectrum National Instruments Corporation 3 5 6023E 6024E 6025E User Manual Chapter 3 Hardware Overview Digital 1 0 Timing Signal The boards contain eight lines of digital I O DIO lt 0 7 gt for general purpose use You can individually software configure each line for either input or output At system startup and reset the digital I O ports are all high impedance The hardware up down control for general purpose counters 0 and 1 are connected onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals are input only and do not affect the operation of the DIO lines 6025E only The 6025E board uses an 82C55A Programmable Peripheral Interface to provide an additional 24 lines of digital I O that represent three 8
67. driver software 1 4 to 1 5 noise environmental 4 49 to 4 50 NRSE nonreferenced single ended mode configuration 4 10 description table 3 2 differential connections 4 15 to 4 16 recommended configuration figure 4 12 single ended connections for ground referenced signal sources 4 18 to 4 19 0 OBF signal description table 4 26 mode 1 output timing figure 4 28 mode 2 bidirectional timing figure 4 29 operating environment specifications A 10 optional equipment 1 6 National Instruments Corporation Index P PA lt 0 7 gt signal description table 4 4 digital I O specifications A 7 to A 8 signal summary table 4 7 PB lt 0 7 gt signal description table 4 4 digital I O specifications A 7 to A 8 signal summary table 4 7 PC lt 0 7 gt signal description table 4 4 digital I O specifications A 7 to A 8 signal summary table 4 7 PFIO TRIGI signal description table 4 5 signal summary table 4 7 PFI1 TRIG2 signal description table 4 5 signal summary table 4 7 PFI2 CONVERT signal description table 4 5 signal summary table 4 7 PFI3 GPCTR1_SOURCE signal description table 4 5 signal summary table 4 7 PFI4 GPCTR1_GATE signal description table 4 5 signal summary table 4 8 PFI5 UPDATE signal description table 4 6 signal summary table 4 8 PFI6 WFTRIG signal description table 4 6 signal summary table 4 8 PFI7 STARTSCAN signal description ta
68. ds without the DAQ STC If you are using the NI DAQ language interface or LabWindows CVI the answer is no the counter timer applications that you wrote previously will not work with the DAQ STC You must use the GPCTR functions ICTR and CTR functions will not work with the DAQ STC The GPCTR functions have the same capabilities as the ICTR and CTR functions plus more but you must rewrite the application with the GPCTR function calls I m using one of the general purpose counter timers on my board but I do not see the counter timer output on the I O connector What am I doing wrong If you are using the NI DAQ language interface or LabWindows CVI you must configure the output line to output the signal to the I O connector Use the Select_Signal call in NI DAQ to configure the output line By default all timing I O lines except EXTSTROBE are tri stated What are the PFIs and how do I configure these lines PFIs are Programmable Function Inputs These lines serve as connections to virtually all internal timing signals If you are using the NI DAQ language interface or LabWindows CVI use the Select_Signal function to route internal signals to the I O connector route external signals to internal timing sources or tie internal timing signals together If you are using NI DAQ with LabVIEW and you want to connect external signal sources to the PFI lines you can use AI Clock Config AI Trigger Config AO Clock Config AO Trigger an
69. e You must tie the ground reference of a floating signal to your board s analog input ground to establish a local or onboard reference for the signal Otherwise the measured input signal varies as the source floats out of the common mode input range Ground Referenced Signal Sources A ground referenced signal source is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the board assuming that the computer is plugged into the same power system Nonisolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between 1 and 100 mV but can be much higher if power distribution circuits are not properly connected If a grounded signal source is improperly measured this difference may appear as an error in the measurement The connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal Analog Input Modes You can configure your board for one of three input modes nonreferenced single ended NRSE referenced single ended RSE and differential DIFF With the different configurations you can use the PGIA in different ways Figure 4 3 shows a diagram of your board s PGIA National Instruments Corporation 4 9 6023E 6024E 60
70. ed gives unpacking instructions and describes the optional software and equipment Features of the 6023E 6024E and 6025E Thank you for buying a National Instruments 6023E 6024E or 6025E board The 6025E features 16 channels eight differential of analog input two channels of analog output a 100 pin connector and 32 lines of digital I O The 6024E features 16 channels of analog input two channels of analog output a 68 pin connector and eight lines of digital I O The 6023E is identical to the 6024E except that it does not have analog output channels These boards use the National Instruments DAQ STC system timing controller for time related functions The DAQ STC consists of three timing groups that control analog input analog output and general purpose counter timer functions These groups include a total of seven 24 bit and three 16 bit counters and a maximum timing resolution of 50 ns The DAQ STC makes possible such applications as buffered pulse generation equivalent time sampling and seamless changing of the sampling rate With other DAQ boards you cannot easily synchronize several measurement functions to a common trigger or timing event These boards have the Real Time System Integration RTSD bus to solve this problem In a PCI system the RTSI bus consists of the National Instruments RTSI bus interface and a ribbon cable to route timing and trigger signals between several functions on as many as five DAQ boards in yo
71. eeeneeees Configuration memory size DMA interrupts programmed I O Scatter gather Single transfer demand transfer A aa 512 words Accuracy Information Absolute Accuracy Relative Accuracy Noise Quantization Temp Nominal Range V of Reading Offset mV Drift Resolution mV Positive Negative FS FS 24 Hours 90 Days 1 Year mV Single Pt Averaged C Theoretical Averaged 10 10 0 0722 0 0742 0 0764 6 385 3 906 0 975 0 0010 4 883 1 284 5 5 0 0272 0 0292 0 0314 3 203 1 953 0 488 0 0005 2 441 0 642 0 5 0 5 0 0722 0 0742 0 0764 0 340 0 195 0 049 0 0010 0 244 0 064 0 05 0 05 0 0722 0 0742 0 0764 0 054 0 063 0 006 0 0010 0 024 0 008 Note Accuracies are valid for measurements following an internal E Series calibration Averaged numbers assume dithering and averaging of 100 single channel readings Measurement accuracies are listed for operational temperatures within 1 C of internal calibration temperature and 10 C of external or factory calibration temperature 6023E 6024E 6025E User Manual A 2 National Instruments Corporation Appendix A Specifications Transfer Characteristics Relative accuracy sesser 0 5 LSB typ dithered 1 5 LSB max undithered DINE oes See A 0 5 LSB typ 1 0 LSB max NO MISSING codes 0 0 eeeeeeeeeeeeeeeeceeeeeee 12 bits guaranteed Offset error Pregain error after calibration
72. er Manual 4 28 National Instruments Corporation Chapter 4 Signal Connections Mode 2 Bidirectional Timing Timing specifications for a bidirectional transfer in mode 2 are as follows CT a A WR i 1 1 i i T6 i A E a INTR age D ACK 1 73 4 A STB a I r x T10 a 174 i ooo l amiat IBF a i T2 15 T8 ag lt 4 lt lt _ gt _ _ fro N Name Description Minimum Maximum Tl WR 1 to OBF 0 150 T2 Data before STB 1 20 T3 STB Pulse Width 100 T4 STB 0 to IBF 1 _ 150 T5 Data after STB 1 50 T6 ACK 0 to OBF 1 150 T7 ACK Pulse Width 100 T8 ACK 0 to Output 150 T9 ACK 1 to Output Float 20 250 T10 RD to IBF 0 150 All timing values are in nanoseconds Figure 4 15 Timing Specifications for Mode 2 Bidirectional Transfer National Instruments Corporation 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Power Connections Two pins on the I O connector supply 5 V from the computer power supply via a self resetting fuse The fuse will reset automatically within a few seconds after the overcurrent condition is removed These pins are referenced to DGND and can be used to power external digital circuitry The power rating is 4 65 to 5 25 VDC at 1 A An Caution Under no circumstances should you connect these 5 V power pins directly to analog or digital ground or to any o
73. erface PPD ssessseseesseesseseesessseseeseesesrseeesessessrssresresseese 4 22 Port C Pin ASsignments soso scciscescssestsces sssccsanty e a as 4 23 Power Up Staterna oea a coeno n A A eva EE E as 4 24 Changing DIO Power up State to Pulled Low sssssseseeeeseeeerseeeseeee 4 24 Timing Specifications ssie esee sisse ees a Eeee EE SE iee EEEn EE NEA ES 4 25 Mode 1 Input Timi ien eo r a ea E EA Ea 4 27 Mode 1 Output Timing iiei ee eiiie eiee eieiaeo ooie soe iien 4 28 Mode 2 Bidirectional Timing eee eee ceceseeeeeeeeeeeeeseeeaecseeeaecsaesaeeneenaes 4 29 Power Connections ssni aineen aee siti ENEE de galas wie ee 4 30 Timing Connectionin renia es ors E Ers EO Epron EEr EET ESTESE E EEE EREE 4 30 Programmable Function Input Connections esessssseeseseresssrrereererrereseereseres 4 31 DAQ Timing Connections sssccccsccetsseccesnssseessecsacseesveee segue sbusesngesivessnogescbescvsqes 4 32 SCANCEK Signal si cis a oep er n eree TEE KEE wisi E 4 33 EXTSTROBE Signal nenene aei 4 33 TRIGIS otal noa SAAS a E E E E li es 4 34 TRIG Signals eeaeee sospes onae isro en Ea EErEE sige suedhsbovssdveesbees 4 35 STARTSCAN Sig alnineo nen s aeee Eee aa e r A cto eeene 4 36 6023E 6024E 6025E User Manual vi National Instruments Corporation Contents CONVERT Signals einer eara ennie Ea inca ao SEEE E 4 38 AIGATE Sign l i asiaa tiie a seh toni ate eases 4 39 SISOURCE Sign l enen eee aE Gea aioe nek 4 40 Waveform Generation Tim
74. ess you select some external source Figure 4 29 shows the timing requirements for the SISOURCE signal tp 50 ns minimum ty 23 ns minimum Figure 4 29 SISOURCE Signal Timing Waveform Generation Timing Connections 6023E 6024E 6025E User Manual The analog group defined for your board is controlled by WFTRIG UPDATE and UISOURCE WFTRIG Signal Any PFI pin can externally input the WFTRIG signal which is available as an output on the PFI6 WFTRIG pin As an input the WFTRIG signal is configured in the edge detection mode You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge The selected edge of the WFTRIG signal starts the waveform generation for the DACs The update interval UD counter is started if you select internally generated UPDATE As an output the WFTRIG signal reflects the trigger that initiates waveform generation This is true even if the waveform generation is being 4 40 National Instruments Corporation Chapter 4 Signal Connections externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 30 and 4 31 show the input and output timing requirements for the WFTRIG signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 30 WFTRIG Input Signal T
75. et E EEEE Sou ab eden E ER 4 1 Analog Input Signal Overview ciiise irnir noteer rE senao EE Ep rE TESES 4 8 Types Of Signal SOULCES nieee aneian E ara pesca tenes E Ea SKEE EErEE 4 8 Floating Signal SOUrCES sissoo ises iri naser seernes esens ene soset eisi 4 8 Ground Referenced Signal Sources seseseeeesseeeseeeerrserrerrrsrrerereee 4 9 Analog Input Modes iiser inen snena enteo renei kero Erie 4 9 Analog Input Signal ConnectionS e eeseeessereseessresesreresrsrertesesesrerrsrentesreesrsserersrerrsre 4 11 Differential Connection Considerations DIFF Input Configuration 4 13 Differential Connections for Ground Referenced Signal Sources 4 14 Differential Connections for Nonreferenced or Floating Signal SOULCES noorie eiee veh chi alec eS lees OE vides 4 15 Single Ended Connection Considerations 0 0 0 0 e cc eceeceeeeeereeeeeeeeeeeeneeeneeaee 4 17 Single Ended Connections for Floating Signal Sources RSE Configuration eesriie riie Ei E E E 4 18 Single Ended Connections for Grounded Signal Sources NRSE Configuration iane einari iaaea eE 4 18 Common Mode Signal Rejection Considerations eeesseeeeeseeeereerrerseer seee 4 19 Analog Output Signal Connections sesessseeesessssrssssterrsteetsrtersrrsrrersserrssreesreeerrenreersee 4 20 Digital I O Signal Connections 2 0 0 0 eee ce eeeeceeeeeeeeseeeeecaeecaecssesaeceeceseceeeseeeeseaeeeeeees 4 21 AI Ior iao EAE EE ETT TT 4 21 Programmable Peripheral Int
76. etailed information about signal connections and module configuration They also explain in greater detail how the module works and contain application hints SCXI Chassis Manual If you are using SCXI read this manual for maintenance information on the chassis and installation instructions Your DAQ hardware documentation This documentation has detailed information about the DAQ hardware that plugs into or is connected to your computer Use this documentation for hardware installation and configuration instructions specification information about your DAQ hardware and application hints Software documentation You may have both application software and NI DAQ software documentation National Instruments application software includes ComponentWorks LabVIEW LabWindows CVI Measure and VirtualBench After you set up your hardware system use either your application software documentation or the NI DAQ documentation to help you write your application If you have a large complicated system it is worthwhile to look through the software documentation before you configure your hardware Accessory installation guides or manuals If you are using accessory products read the terminal block and cable assembly installation guides They explain how to physically connect the relevant pieces of the system Consult these guides when you are making your connections xiii 6023E 6024E 6025E User Manual About This Manual Related Documentatio
77. evices such as the LED shown in the figure National Instruments Corporation 4 21 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Programmable Peripheral Interface PPI 6025E only The 6025E board uses an 82C55A PPI to provide an additional 24 lines of digital I O that represent three 8 bit ports PA PB and PC Each port can be programmed as an input or output port Figure 4 11 depicts signal connections for three typical digital I O applications 5 V Len Par a W O O O TTL Signal PB lt 7 4 gt 5V 4 AN Switch 1 O Connector J GND Figure 4 11 Digital 1 0 Connections Block Diagram DIO Board In Figure 4 11 port A of one PPI is configured for digital output and port B is configured for digital input Digital input applications include 6023E 6024E 6025E User Manual 4 22 National Instruments Corporation Chapter 4 Signal Connections receiving TTL signals and sensing external device states such as the state of the switch in Figure 4 11 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 4 11 Port C Pin Assignments Note e 6025 only The signals assigned to port C depend on how the 82C55A is configured In mode 0 or no handshaking configuration port C is configured as two 4 bit I O ports In modes 1 and 2 or handshaking configuration p
78. flects the posttrigger in a pretriggered acquisition sequence This is true even if the acquisition is being externally triggered by another PFI The TRIG2 signal is not used in posttriggered data acquisition The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup National Instruments Corporation 4 35 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Figures 4 23 and 4 24 show the input and output timing requirements for the TRIG2 signal Rising Edge Polarity Falling Edge Polarity tw 10ns minimum Figure 4 23 TRIG2 Input Signal Timing ty 50 100ns i Figure 4 24 TRIG2 Output Signal Timing STARTSCAN Signal Any PFI pin can externally input the STARTSCAN signal which is available as an output on the PFI7 STARTSCAN pin Refer to Figures 4 17 and 4 18 for the relationship of STARTSCAN to the DAQ sequence As an input the STARTSCAN signal is configured in the edge detection mode You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge The selected edge of the STARTSCAN signal initiates a scan The sample interval counter starts if you select internally triggered CONVERT As an output the STARTSCAN signal reflects the actual start pulse that initiates a scan This is true even if the starts are being externally triggered by another
79. gle Ended Input Connections for Ground Referenced Signals 4 19 Figure 4 9 Analog Output Connections cece ceceseeeeeeeceseeseecaeesaesececeeeeeeees 4 20 Figure 4 10 Digital I O Connections 00 eee ee eeeeeeceeceeceseeeeeeeecneesseeseeecneeeeeeeeeens 4 21 Figure 4 11 Digital I O Connections Block Diagram eee esee ce ceeenseeees 4 22 Figure 4 12 DIO Channel Configured for High DIO Power up State with FExt rnal L dde eres e aep ete aisle ch isin sini 4 24 Figure 4 13 Timing Specifications for Mode 1 Input Transfer eee 4 27 Figure 4 14 Timing Specifications for Mode 1 Output Transfer 0 4 28 Figure 4 15 Timing Specifications for Mode 2 Bidirectional Transfet 4 29 Figure 4 16 Timing I O Connections 2000 eeeecceeeceeeeeeeceeeeeeeseecaecaeeaecnaeenees 4 31 Figure 4 17 Typical Posttriggered Acquisition 0 elect ceseeeeceeeeeeceeeeeeeeeeeaeeees 4 32 Figure 4 18 Typical Pretriggered ACQUISITION el eee eeeseceeceteceeceseeeeeeeeeeeeens 4 33 Figure 4 19 SCANCLK Signal Timing ooo cece cee cnse cee ceeeseceseeecneeeeeseeeenes 4 33 Figure 4 20 EXTSTROBE Signal Timing ce ceseeeeceeceeeeeeeeeeeeeeeseeees 4 34 Figure 4 21 TRIG1 Input Signal Timing eee eeeeceeseeceesneceeeeseenseeeees 4 34 Figure 4 22 TRIG1 Output Signal Timing oo ce ceseeeeceeceeeceeeeeeeeeeeaeeeee 4 35 Figure 4 23 TRIG2 Input Signal Timing eee eseeceeeneecaeesecseeesecnaeeeees 4 36 Figure 4 24 TRIG2 Output Signal Timing o
80. he following conditions e The input signal is low level less than 1 V e The leads connecting the signal to the board are greater than 10 ft 3 m e The input signal requires a separate ground reference point or return signal e The signal leads travel through noisy environments Differential signal connections reduce picked up noise and increase common mode noise rejection Differential signal connections also allow input signals to float within the common mode limits of the PGIA National Instruments Corporation 4 13 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Differential Connections for Ground Referenced Signal Sources Figure 4 5 shows how to connect a ground referenced signal source to a channel on the board configured in DIFF input mode ACH TO 0O Ground S So Referenced o so Programmable Gain Signal Instrumentation Source Amplifier O so ACH 7 les To Measured Common Voltage Mode Q o Noise and o so Ground Potential O so Input Multiplexers AISENSE olee AIGND 1 O Connector Selected Channel in DIFF Configuration Figure 4 5 Differential Input Connections for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the board ground shown as Vem in Figure
81. ied to a product in normal use normally well under the breakdown voltage for safety margin See also breakdown voltage G 16 National Instruments Corporation Index Numbers 5 V signal description table 4 4 self resetting fuse C 1 82C55A Programmable Peripheral Interface See PPI Programmable Peripheral Interface 6023E 6024E 6025E boards See also hardware overview block diagram 3 1 features 1 1 to 1 2 optional equipment 1 6 requirements for getting started 1 2 to 1 3 software programming choices 1 3 to 1 6 National Instruments application software 1 4 NI DAQ driver software 1 4 to 1 5 register level programming 1 6 unpacking 1 3 using PXI with CompactPCI 1 2 A ACH lt 0 15 gt signal description table 4 4 signal summary table 4 7 ACK signal description table 4 25 mode 1 output timing figure 4 28 mode 2 bidirectional timing figure 4 29 acquisition timing connections See DAQ timing connections AIGATE signal 4 39 AIGND signal analog input mode 4 10 description table 4 4 signal summary table 4 7 AISENSE signal National Instruments Corporation description table 4 4 NRSE mode 4 10 signal summary table 4 7 analog input available input configurations table 3 2 common questions C 2 to C 3 dither 3 3 to 3 4 input modes 3 2 input range 3 2 to 3 3 multichannel scanning considerations 3 4 to 3 5 analog input signal connections 4 9 to 4 11 common mode s
82. ignal rejection considerations 4 19 differential connections 4 13 to 4 16 ground referenced signal sources 4 14 nonreferenced or floating signal sources 4 15 to 4 16 exceeding common mode input ranges caution 4 10 PGIA figure 4 10 recommended input connections figure 4 12 single ended connection 4 17 to 4 19 floating signal sources RSE configuration 4 18 grounded signal sources NRSE configuration 4 18 to 4 19 summary of input connections table 4 12 types of signal sources 4 8 to 4 9 floating signal sources 4 8 to 4 9 ground referenced signal sources 4 9 analog input specifications A 1 to A 4 accuracy information A 2 amplifier characteristics A 3 dynamic characteristics A 4 input characteristics A 1 to A 2 stability A 4 6023E 6024E 6025E User Manual Index transfer characteristics A 3 analog output analog output glitch 3 5 common questions C 2 to C 3 overview 3 5 signal connections 4 20 analog output specifications A 4 to A 6 accuracy information A 5 dynamic characteristics A 6 output characteristics A 4 to A 5 stability A 6 transfer characteristics A 5 to A 6 voltage output A 6 AOGND signal description table 4 4 signal summary table 4 7 B bipolar input 3 2 block diagram 3 1 board and RTSI clocks 3 8 bulletin board support D 1 C cables See also I O connectors custom cabling B 1 to B 2 field wiring considerations 4 49 to 4 50 optional equipment 1 6 cali
83. iming 1 lt aa 1 I 1 j I i ty 50 100ns l Figure 4 31 WFTRIG Output Signal Timing UPDATE Signal Any PFI pin can externally input the UPDATE signal which is available as an output on the PFIS UPDATE pin As an input the UPDATE signal is configured in the edge detection mode You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of the UPDATE signal updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode As an output the UPDATE signal reflects the actual update pulse that is connected to the DACs This is true even if the updates are being externally generated by another PFI The output is an active low pulse with a pulse width of 300 to 350 ns This output is set to tri state at startup National Instruments Corporation 4 41 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Figures 4 32 and 4 33 show the input and output timing requirements for the UPDATE signal Rising Edge Polarity Falling Edge Polarity ty 10ns minimum 6023E 6024E 6025E User Manual Figure 4 32 UPDATE Input Signal Timing t 300 350 ns Figure 4 33 UPDATE Output Signal Timing The DACs are updated within 100 ns of the leading edge Separate the UPDATE pulses with enough time that new data c
84. ing Connections ssssseseseeessresesresrrrrsrrresreereseee 4 40 WETRIG Sional i 4 2 Aico lah saan aes 4 40 UPDATE Signal Sensis A EREA TA 4 41 UISOURCE Signal ietie ire nach E a EE SE 4 42 General Purpose Timing Signal Connections ssesssseerssresreresrssrsrerrsreersreee 4 43 GPCTRO_SOURCE Signaleren aeei e eee oeiee kieneo iberan niise 4 43 GPCTRO GATE Signal ni eaa aerea Eeoae i EE i Tos 4 44 GPETRO OUT Signal ticis cc ctiiseinsieien ten en EE E resena 4 45 GPCTRO_UP_DOWN Signal seeseeseeeeeeeeseesssrrerrerersrersesreresseererse 4 45 GPCTR1_SOURCE Signal ccc ccesesseseeeceeceereessecneceeeeesaeeaeenees 4 45 GPCTRI GATE Signial 3s 02 60 ic5cesssvasosan sonesescs aa eE rapra SEa aE ein 4 46 GPGTR1 OUT Sihali e a e ea EA EENES 4 47 GPCTR1_UP_DOWN Signal 0 00 0 eeeseceeseceecneeeeeeeceecneeaeeeeeneeneee 4 47 FREQ OUT Sigtialt c ic 0 cb ae AA as 4 49 Field Wiring Considerations cece eececeeeseeeceeeeeecaeecaecasesaeceeceaeceeceseeeseeeeeeseaeeaeens 4 49 Chapter 5 Calibration Loading Calibration Constant 2 0 0 0 ce eececceeeeceseeeeecseeceecaeesaeceecaecneceseeeeseeeeeeeeaeeeaeeas 5 1 Self Caltbration sssssisescessistsiesessatdipesescesi ious ch ee eetos a rekr E E E E are EE E i 5 2 External Calibration serenon oi oath ia lela en o a e aa a Cak 5 2 Other Considerations iss sissce5cs ges soetsshssts ses de iseken decnacsanasesesceis copseoscessdescabsaddeespsesdscendevusts 5 3 Appendix A Specifications Appendix B C
85. ingle ended connections 4 17 to 4 19 I O signal summary table floating signal sources RSE 4 7 to 4 8 configuration 4 18 pin assignments figure 4 2 to 4 3 grounded signal sources NRSE configuration 4 18 to 4 19 when to use 4 17 SISOURCE signal 4 40 National Instruments Corporation l 7 6023E 6024E 6025E User Manual Index STB signal description table 4 25 software installation 2 1 software programming choices 1 3 to 1 6 ComponentWorks 1 4 LabVIEW and LabWindows CVI 1 4 National Instruments application software 1 4 NI DAQ driver software 1 4 to 1 5 register level programming 1 6 VirtualBench 1 4 specifications analog input A 1 to A 4 accuracy information A 2 amplifier characteristics A 3 dynamic characteristics A 4 input characteristics A 1 to A 2 stability A 4 transfer characteristics A 3 analog output A 4 to A 6 accuracy information A 5 dynamic characteristics A 6 output characteristics A 4 to A 5 stability A 6 transfer characteristics A 5 to A 6 voltage output A 6 calibration A 9 digital I O A 7 to A 8 DIO lt 0 7 gt A 7 PA lt 0 7 gt PB lt 0 7 gt PC lt 0 7 gt A 7 to A 8 operating environment A 10 physical A 9 to A 10 power requirement A 9 storage environment A 10 timing I O A 8 triggers A 9 digital trigger A 9 RTSI trigger A 9 STARTSCAN signal 4 36 to 4 38 6023E 6024E 6025E User Manual l 8 mode 1 input timing figure 4 27 mode 2 bid
86. irectional timing figure 4 29 storage environment specifications A 10 T technical support D 1 to D 2 telephone and fax support numbers D 2 timing connections 4 30 to 4 49 DAQ timing connections 4 32 to 4 40 AIGATE signal 4 39 CONVERT signal 4 38 to 4 39 EXTSTROBE signal 4 33 to 4 34 SCANCLK signal 4 33 SISOURCE signal 4 40 STARTSCAN signal 4 36 to 4 38 TRIGI signal 4 34 to 4 35 TRIG signal 4 35 to 4 36 typical posttriggered acquisition figure 4 32 typical pretriggered acquisition figure 4 33 general purpose timing signal connections 4 43 to 4 49 FREQ_ OUT signal 4 49 GPCTRO_GATE signal 4 44 GPCTRO_OUT signal 4 45 GPCTRO_SOURCE signal 4 43 to 4 44 GPCTRO_UP_DOWN signal 4 45 GPCTR1_GATE signal 4 46 to 4 47 GPCTR1_OUT signal 4 47 GPCTR1_SOURCE signal 4 45 to 4 46 GPCTR1_UP_DOWN signal 4 47 to 4 49 overview 4 30 programmable function input connections 4 31 to 4 32 National Instruments Corporation timing I O connections figure 4 31 waveform generation timing connections 4 40 to 4 43 UISOURCE signal 4 42 to 4 43 UPDATE signal 4 41 to 4 42 WFTRIG signal 4 40 to 4 41 timing I O common questions C 3 to C 5 specifications A 8 timing signal routing 3 6 to 3 10 board and RTSI clocks 3 8 CONVERT signal routing figure 3 7 programmable function inputs 3 7 to 3 8 RTSI triggers 3 8 to 3 10 timing specifications 4 25 to 4 29 mode input timing figure 4 27 mode
87. is a library that contains NI DAQ functions The NI DAQ function set is broken down into object modules so that only the object modules that are relevant to your application are linked in while those object modules that are not relevant are not linked the adherence of device response to the equation R KS where R response S stimulus and K a constant least significant bit multifunction I O MXI Interface to Everything a custom ASIC designed by National Instruments that implements the PCI bus interface The MITE supports bus mastering for high speed data transfers over the PCI bus million samples most significant bit multiplexer a switching device with multiple inputs that sequentially connects each of its inputs to its output typically at high speeds in order to measure several signals with a single analog input channel normally closed or not connected National Instruments Corporation G 9 6023E 6024E 6025E User Manual Glossary NI DAQ noise nonlatched digital I O nonreferenced signal sources NRSE OUT output settling time output slew rate PCI peak to peak 6023E 6024E 6025E User Manual National Instruments driver software for DAQ hardware an undesirable electrical signal Noise comes from external sources such as the AC power line motors generators transformers fluorescent lights soldering irons CRT displays computers electrical storms welders radio transmitters and in
88. ity FTP Support To access our FTP site log on to our Internet host ftp natinst com aS anonymous and use your Internet address such as joesmith anywhere com as your password The support files and documents are located in the support directories National Instruments Corporation D 1 6023E 6024E 6025E User Manual Fax on Demand Support Fax on Demand is a 24 hour information retrieval system containing a library of documents on a wide range of technical information You can access Fax on Demand from a touch tone telephone at 512 418 1111 E Mail Support Currently USA Only You can submit technical support questions to the applications engineering team through e mail at the Internet address listed below Remember to include your name address and phone number so we can contact you with solutions and suggestions support natinst com Telephone and Fax Support National Instruments has branch offices all over the world Use the list below to find the technical support number for your country If there is no National Instruments office in your country contact the source from which you purchased your software to obtain support Country Australia Austria Belgium Brazil Canada Ontario Canada Qu bec Denmark Finland France Germany Hong Kong India Israel Italy Japan Korea Mexico D F Mexico Monterrey Netherlands Norway Singapore Spain Madrid Spain Barcelona Sweden Switzerland Taiwan Uni
89. l chassis near sensors so only high level signals are sent to DAQ boards in the noisy PC environment single ended a term used to describe an analog input that is measured with respect to a common ground a property of a DAQ board that has an extremely stable onboard reference and calibrates its own A D and D A circuits without manual adjustments by the user a device that responds to a physical stimulus heat light sound pressure motion flow and so on and produces a corresponding electrical signal the amount of time required for a voltage to reach its final value within specified limits 6023E 6024E 6025E User Manual Glossary Shannon Sampling Theorem S H signal conditioning SISOURCE SNR software trigger software triggering SOURCE SS S s STARTSCAN STC synchronous TC T H 6023E 6024E 6025E User Manual a law of sampling theory stating that if a continuous bandwidth limited signal contains no frequency components higher than half the frequency at which it is sampled then the original signal can be recovered without distortion sample and hold a circuit that acquires and stores an analog voltage on a capacitor for a short period of time the manipulation of signals to prepare them for digitizing SI counter clock signal signal to noise ratio the ratio of the overall rms signal level to the rms noise level expressed in decibels a programmed event that triggers an event such as data ac
90. line for output as follows e Ifyou are using NI DAQ call Select_Signal deviceNumber ND_PFI_5 ND_OUT_UPDATE ND_HIGH_TO_LOW e Ifyou are using LabVIEW invoke Route Signal VI with signal name set to PFI5 and signal source set to AO Update 2 Set up data acquisition timing so that the timing signal for A D conversion comes from PFI5 as follows e Ifyou are using NI DAQ call Select_Signal deviceNumber ND_IN_CONVERT ND_PFI_5 ND_HIGH_TO_LOW e If you are using LabVIEW invoke AI Clock Config VI with clock source code set to PFI pin high to low and clock source string set to 5 3 Initiate analog input data acquisition which will start only when the analog output waveform generation starts 4 Initiate analog output waveform generation Timing and Digital 1 0 What types of triggering can be hardware implemented on my board Digital triggering is hardware supported on every board Will the counter timer applications that I wrote previously work with the DAQ STC If you are using NI DAQ with LabVIEW some of your applications drawn using the CTR VIs will still run However there are many differences in the counters between the E Series and other boards the counter numbers are different timebase selections are different and the DAQ STC counters are National Instruments Corporation C 3 6023E 6024E 6025E User Manual Chapter C Common Questions 24 bit counters unlike the 16 bit counters on boar
91. ling edge of the source signal FREQ_OUT Signal This signal is available only as an output on the FREQ OUT pin The board s frequency generator outputs the FREQ OUT pin The frequency generator is a 4 bit counter that can divide its input clock by the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 kHz timebases The output polarity is software selectable This output is set to tri state at startup Field Wiring Considerations Environmental noise can seriously affect the accuracy of measurements made with your board if you do not take proper care when running signal wires between signal sources and the board The following recommendations apply mainly to analog input signal routing to the board although they also apply to signal routing in general Minimize noise pickup and maximize measurement accuracy by taking the following precautions e Use differential analog input connections to reject common mode noise e Use individually shielded twisted pair wires to connect analog input signals to the board With this type of wire the signals attached to the CH and CH inputs are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference e Route signals to the
92. m assumes that the counters are programmed to count rising edges The same timing diagram but with the source signal inverted and referenced to the falling edge of the source signal would apply when the counter is programmed to count falling edges The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on your board Figure 4 41 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or low for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by t and tg in Figure 4 41 The gate signal is not required to be held after the active edge of the source signal If you use an internal timebase clock the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the 4 48 National Instruments Corporation Chapter 4 Signal Connections boards Figure 4 41 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 80 ns after the rising or fal
93. n The following documents contain information you may find helpful e DAQ STC Technical Reference Manual e National Instruments Application Note 025 Field Wiring and Noise Considerations for Analog Signals e PCI Local Bus Specification Revision 2 1 e PICMG CompactPCI 2 0 Revision 2 1 e PXI Bus Specification Revision 1 0 The following National Instruments manual contains detailed information for the register level programmer e PCIE Series Register Level Programmer Manual This manual is available from National Instruments by request You should not need the register level programmer manual if you are using National Instruments driver or application software Using NI DAQ ComponentWorks LabVIEW LabWindows CVI Measure or VirtualBench software is easier than the low level programming described in the register level programmer manual Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix D Customer Communication at the end of this manual 6023E 6024E 6025E User Manual xiv National Instruments Corporation Introduction This chapter describes the 6023E 6024E and 6025E boards lists what you need to get start
94. n E Series connector This connector is available when you use the SH6850 or R6850 cable assemblies with the 6023E and 6024E It is also one of the two 50 pin connectors available when you use the RIO05050 cable assembly with the 6025E AIGND 1 2 AIGND ACHO 3 4 ACH8 ACH1 5 6 ACH9 ACH2 7 8 ACH10 ACH3 9 10 ACH11 ACH4 11 12 ACH12 ACH5 13 14 ACH13 ACH6 15 16 ACH14 ACH7 17 18 ACH15 AISENSE 19 20 DACOOUT DAC10OUT1 21 22 RESERVED AOGND 23 24 DGND DIOO 25 26 DIO4 DIO1 27 28 DIO5 DIO2 29 30 DIO6 DIO3 31 32 DIO7 DGND 33 34 5V 5 V 35 36 SCANCLK EXTSTROBE 37 38 PFIO TRIG1 PFI1 TRIG2 39 40 PFI2 CONVERT PFI3 GPCTR1_SOURCE 41 42 PFI4 GPCTR1_GATE GPCTR1_OUT 43 44 PFI5 UPDATE PFI6 WFTRIG 45 46 PFI7 STARTSCAN PFI8 GPCTRO_SOURCE 47 48 PFI9 GPCTRO_GATE GPCTRO_OUT 49 50 FREQ_OUT 1 Not available on the 6023E Figure B 3 50 Pin E Series Connector Pin Assignments National Instruments Corporation B 5 6023E 6024E 6025E User Manual Appendix B Custom Cabling and Optional Connectors 6023E 6024E 6025E User Manual Figure B 4 shows the pin assignments for the 50 pin extended digital input connector This is the other 50 pin connector available when you use the R1005050 cable assembly with the 6025E PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO PB7 PB6 PB5
95. nal to AIGND as well as to the negative input of the PGIA without any resistors at all This connection works well for DC coupled sources with low source impedance less than 100 Q However for larger source impedances this connection leaves the differential signal path significantly out of balance Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground Hence this noise appears as a differential mode signal instead of a common mode signal and the PGIA does not reject it In this case instead of directly connecting the negative line to AIGND connect it to AIGND through a resistor that is about 100 times the equivalent source impedance The resistor puts the signal path nearly in balance so that about the same amount of noise couples onto both connections yielding better rejection of electrostatically coupled noise Also this configuration does not load down the source other than the very high input impedance of the PGIA You can fully balance the signal path by connecting another resistor of the same value between the positive input and AIGND as shown in Figure 4 6 This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination sum of the two resistors If for example the source impedance is 2 kQ and each of the two resistors is 100 KQ the resistors load down the sou
96. ning modules boards and accessories including conditioning for strain gauges and RTDs simultaneous sample and hold and relays For more information about these products refer to the National Instruments catalogue or web site or call the office nearest you 1 6 National Instruments Corporation Installation and Configuration This chapter explains how to install and configure your 6023E 6024E or 6025E board Software Installation Install your software before you install your board Refer to the appropriate release notes indicated below for specific instructions on the software installation sequence If you are using NI DAQ refer to your NI DAQ release notes Find the installation section for your operating system and follow the instructions given there If you are using LabVIEW LabWindows CVI or other National Instruments application software packages refer to the appropriate release notes After you have installed your application software refer to your NI DAQ release notes and follow the instructions given there for your operating system and application software package If you are a register level programmer refer to the PCI E Series Register Level Programmer Manual and the DAQ STC Technical Reference Manual for software configuration information Hardware Installation CF Note Install your software before you install your board After installing your software you are ready to install your hardware Yo
97. ns i l Figure 4 22 TRIG1 Output Signal Timing The board also uses the TRIGI signal to initiate pretriggered DAQ operations In most pretriggered applications the TRIG1 signal is generated by a software trigger Refer to the TRIG2 signal description for a complete description of the use of TRIG and TRIG2 in a pretriggered DAQ operation TRIG2 Signal Any PFI pin can externally input the TRIG2 signal which is available as an output on the PFI1 TRIG2 pin Refer to Figure 4 18 for the relationship of TRIG2 to the DAQ sequence As an input the TRIG2 signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG signal initiates the posttriggered phase of a pretriggered acquisition sequence In pretriggered mode the TRIG1 signal initiates the data acquisition The scan counter indicates the minimum number of scans before TRIG2 can be recognized After the scan counter decrements to zero it is loaded with the number of posttrigger scans to acquire while the acquisition continues The board ignores the TRIG2 signal if it is asserted prior to the scan counter decrementing to zero After the selected edge of TRIG2 is received the board will acquire a fixed number of scans and the acquisition will stop This mode acquires data both before and after receiving TRIG2 As an output the TRIG2 signal re
98. nstruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National
99. o eee ceseeseceeeeseceeeeeeeeeeeneeees 4 36 Figure 4 25 STARTSCAN Input Signal Timing eee ceeeceeeeseceeeeseeeeees 4 37 Figure 4 26 STARTSCAN Output Signal Timing 0000000 ceeeeeeeeeeeeees 4 37 6023E 6024E 6025E User Manual viii National Instruments Corporation Contents Figure 4 27 CONVERT Input Signal Timing eee ceeeceeeeseeeeeeeeeeeees 4 38 Figure 4 28 CONVERT Output Signal Timing 0 0 ee e eeeeeceeeeeeeeeeeeaee 4 39 Figure 4 29 SISOURCE Signal Timing cece ceseeeeceeceeeceeeeeeseeeeneeeneeaes 4 40 Figure 4 30 WFTRIG Input Signal Timing ssssseeeesseeesseresesreesressrsrsrerresrerreserreseerse 4 4 Figure 4 31 WFTRIG Output Signal Timing eee creesee ce cneecnseeneeneens 4 4 Figure 4 32 UPDATE Input Signal Timing eee eneeneecneeeaecnseeneeneens 4 42 Figure 4 33 UPDATE Output Signal Timing 0000 cee cee ceteeeeeeseeeeees 4 42 Figure 4 34 UISOURCE Signal Timing 0 ce ceseeeeceeceeeceeeeeeeeeseneseneeaes 4 43 Figure 4 35 GPCTRO SOURCE Signal Timing 0 0 eee ce eee ceeeeeeeeeeeeeeneeaee 4 44 Figure 4 36 GPCTRO_GATE Signal Timing in Edge Detection Mode 4 44 Figure 4 37 GPCTRO_OUT Signal Timing eee cee ceeeceeeeeeeeeeeseeeneeaee 4 45 Figure 4 38 GPCTR1_ SOURCE Signal Timing 00 eee eeeeceeeeeeeeeeeeeeneenes 4 46 Figure 4 39 GPCTR1_GATE Signal Timing in Edge Detection Mode 4 47 Figure 4 40 GPCTR1_OUT Signal Timing cece cess ceeeeneeeeeeeeeeeeeaes 4 47 Figure
100. o the process of minimizing measurement and output voltage errors by making small circuit adjustments For these boards these adjustments take the form of writing values to onboard calibration DACs CalDACs Some form of board calibration is required for all but the most forgiving applications If you do not calibrate your board your signals and measurements could have very large offset gain and linearity errors Three levels of calibration are available to you and described in this chapter The first level is the fastest easiest and least accurate whereas the last level is the slowest most difficult and most accurate Loading Calibration Constants Your board is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored in the onboard nonvolatile memory EEPROM Because the CalDACs have no memory capability they do not retain calibration information when the board is unpowered Loading calibration constants refers to the process of loading the CalDACs with the values stored in the EEPROM NI DAQ software determines when this is necessary and does it automatically If you are not using NI DAQ you must load these values yourself In the EEPROM there is a user modifiable calibration area in addition to the permanent factory calibration area This
101. on Considerations ACH TO O O Ground o coe Referenced 7 o S o Signal n V e Source s 4 7 O so ACH e TO O Common Mode n o co Noise and V o s o Ground cm Potential TIF a Input Multiplexers AISENSE AIGND Programmable Gain Instrumentation Amplifier Measured Voltage Selected Channel in DIFF Configuration Figure 4 8 Single Ended Input Connections for Ground Referenced Signals Figures 4 5 and 4 8 show connections for signal sources that are already referenced to some ground point with respect to the board In these cases the PGIA can reject any voltage caused by ground potential differences between the signal source and the board In addition with differential input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the board The PGIA can reject common mode signals as long as V and V input signals are both within 11 V of AIGND National Instruments Corporation 4 19 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Analog Output Signal Connections 6024E and 6025E The analog output signals are DACOOUT DACIOUT and AOGND DACOOUT and DACIOUT are not available on the 6023E DACOOUT is the voltage output signal for analog output channel 0 DACIOUT is the voltage output signal for analog output channel 1 AOGND is the ground reference signal for
102. on or edge detection mode You can configure the polarity selection for the PFI pin for either active high or active low In the level detection mode if AIGATE is active the STARTSCAN signal is masked off and no scans can occur In the edge detection mode the first active edge disables the STARTSCAN signal and the second active edge enables STARTSCAN The AIGATE signal can neither stop a scan in progress nor continue a previously gated off scan in other words once a scan has started AIGATE does not gate off conversions until the beginning of the next scan and conversely if conversions are being gated off AIGATE does not gate them back on until the beginning of the next scan National Instruments Corporation 4 39 6023E 6024E 6025E User Manual Chapter 4 Signal Connections SISOURCE Signal Any PFI pin can externally input the SISOURCE signal which is not available as an output on the I O connector The onboard scan interval counter uses the SISOURCE signal as a clock to time the generation of the STARTSCAN signal You must configure the PFI pin you select as the source for the SISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE signal unl
103. or when using an external reference In this case it is advisable to account for the nominal gain error of the analog output channel either in software or with external hardware See Appendix A Specifications for analog output gain error information National Instruments Corporation 5 3 6023E 6024E 6025E User Manual Specifications This appendix lists the specifications of 6023E 6024E and 6025E boards These specifications are typical at 25 C unless otherwise noted Analog Input Input Characteristics Number of channels 000 0 eee 16 single ended or 8 differential software selectable per channel Type of ADC nni en a ie Successive approximation Resolution 056 66 Selb n a a tac 12 bits 1 in 4 096 Sampling rate oo cece ceeeeee etree 200 kS s guaranteed Input signal ranges 00 0 eeeeeeeeesseceeeee Bipolar only Board Gain Software Selectable Range 0 5 10 V 1 5 V 10 500 mV 100 50 mV Input coupling ee eee ceeeeeeeeereeeees DC Max working voltage signal common mode eeeeee Each input should remain within 11 V of ground National Instruments Corporation A 1 6023E 6024E 6025E User Manual Appendix A Specifications Overvoltage protection Powered On Powered Off ACH lt 0 15 gt 42 35 AISENSE 40 25 FIFO buffer size ceeeeeeeeeeeeees 512 S Data transfer Sinsnrnninosnim DMA modes cceceeececeeeeceseseses
104. ort C is used for status and handshaking signals with any leftover lines available for general purpose I O Table 4 3 summarizes the port C signal assignments for each configuration You can also use ports A and B in different modes the table does not show every possible combination Table 4 3 shows both the port C signal assignments and the terminology correlation between different documentation sources The 82C55A terminology refers to the different 82C55A configurations as modes whereas NI DAQ ComponentWorks LabWindows CVI and LabVIEW documentation refers to them as handshaking and no handshaking Table 4 3 Port C Signal Assignments Configuration Terminology Signal Assignments 6023E National 6024E 6025E Instruments User Manual Software PC7 PC6 PCS PC4 PC3 PC2 PC1 PCO Mode 0 No vo vO VO vo vo VO 1 0 T O Basic I O Handshaking Mode 1 Handshaking T O T O IBF STB INTR STBpg IBFBg INTRg Strobed Input Mode 1 Handshaking OBF ACKa 1 0 vo INTR ACKg OBFg INTRg Strobed Output Mode 2 Handshaking OBF ACK IBF STB INTR VO 1 0 VO Bidirectional Bus Indicates that the signal is active low Subscripts A and B denote port A or port B handshaking signals National Instruments Corporation 4 23 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Power up State 6025E only The 6025E contains bias resistors that control the state of
105. oth options This output is set to tri state at startup Figure 4 40 shows the timing requirements for the GPCTR1_OUT signal GPCTR1_SOURCE GPCTR1_OUT Pulse on TC GPCTR1_OUT Toggle Output on TC Figure 4 40 GPCTR1_OUT Signal Timing GPCTR1_UP_DOWN Signal This signal can be externally input on the DIO7 pin and is not available as an output on the I O connector General purpose counter 1 counts down when this pin is at a logic low and counts up at a logic high This input can be disabled so that software can control the up down functionality and leave the DIO7 pin free for general use Figure 4 41 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of your board National Instruments Corporation 4 47 6023E 6024E 6025E User Manual Chapter 4 Signal Connections V i i e SOURCE H NSO NOY NSL V GATE IH X IL q tow It tout V i OUT ON i V L OL Source Clock Period tise 50 ns minimum Source Pulse Width tsp 23 ns minimum Gate Setup Time tgsu 10 ns minimum Gate Hold Time tgh Ons minimum Gate Pulse Width tow 10 ns minimum Output Delay Time tout 80 ns maximum 6023E 6024E 6025E User Manual Figure 4 41 GPCTR Timing Summary The GATE and OUT signal transitions shown in Figure 4 41 are referenced to the rising edge of the SOURCE signal This timing diagra
106. our PXI E Series board will work in any standard CompactPCI chassis adhering to PICMG CompactPCI 2 0 R2 1 core specification PXI specific features are implemented on the J2 connector of the CompactPCI bus Table 3 3 lists the J2 pins used by your PXI E Series board Your PXI board is compatible with any Compact PCI chassis with a sub bus that does not drive these lines Even if the sub bus is capable of driving these lines the PXI board is still compatible as long as those pins on the sub bus are disabled by default and not ever enabled Damage may result if these lines are driven by the sub bus What You Need to Get Started To set up and use your board you will need the following 0 One of the following boards e PCI 6023E e PCI 6024E e PCI 6025E e PXI 6025E LL 6023E 6024E 6025E User Manual 6023E 6024E 6025E User Manual 1 2 National Instruments Corporation Chapter 1 Introduction Q One of the following software packages and documentation ComponentWorks LabVIEW for Windows LabWindows CVI for Windows Measure NI DAQ for PC Compatibles VirtualBench J Your computer equipped with one of the following PCI bus for a PCI board PXI or CompactPCI chassis and controller for a PXI board t Note Read Chapter 2 Installation and Configuration before installing your board Always install your software before installing your board Unpacking Your board is shipped in an antistatic package to prevent electrostati
107. quipment sitein rera eeo oe rie rE EEEE EEEE ESTEE ioo rn aE TES 1 6 Chapter 2 Installation and Configuration Software Installation sad ccocceweissecssucodsoesust evteessthcoeseeskerbores sevegseeedisvesosettloucooentlemmorsten ties 2 1 Hardware Installation ccccccccccccccccccececeseseesesesessccseeususcesssecseseeceseseseeeesesesssesererenanees 2 1 Hardware Configuration csere cece eeeceeceseeeeecseeesecseesaecsecsaecsecseeseseeeeeseeeeeeseaseaeeeaes 2 3 Chapter 3 Hardware Overview Analog Inputs coh See heh ail Se eins ae etc ee ee 3 2 Input Modenie a e estas caucasian EEEREN NS 3 2 InputRange cata see ai Ba ei eta Ra Ss 3 2 DHS eE E OT EEE EE E SEENE dae ededtesh uote atyanceste stv 3 3 Multichannel Scanning Considerations 0 cess ceecesecsseeseceeeseceseeseeeseees 3 4 ANALOGS OUUTE E E E E RE 3 5 Analog Output Glitch sssseseeseseseseesseseesrsrestsresrsressrrssrereseeresresertenrerrnreeresenree 3 5 Dipital UL O ENE EEEE ENEE EET EAEE EE E E E EEE ANE 3 6 Timing Signal Routing eee eeeeeseeceeeeeecseeesecsaesaecsecsaecnecsaeeeeeeseeeseaeeeesenseaeeeaes 3 6 Programmable Function Inputs 20 0 0 eee ee ceesecseceseceeceeeseceeeeeeceeeeeeseaeeaeeeaes 3 7 National Instruments Corporation v 6023E 6024E 6025E User Manual Contents Board and RTS Cloke e nea reae cedatdecteceteveossescussinscuodvecodseeodese 3 8 RISE Trig S60 oso E E ETTET 3 8 Chapter 4 Signal Connections TO Comme ctr iet sasoe eae Taa E p
108. quisition a method of triggering in which you simulate an analog trigger using software Also called conditional retrieval source signal simultaneous sampling a property of a system in which each input or output channel is digitized or updated at the same instant samples per second used to express the rate at which a DAQ board samples an analog signal start scan signal system timing controller 1 hardware a property of an event that is synchronized to a reference clock 2 software a property of a function that begins an operation and returns only when the operation is complete terminal count the highest value of a counter track and hold a circuit that tracks an analog voltage and holds the value on command G 14 National Instruments Corporation THD THD N throughput rate transducer transfer rate TRIG trigger TTL U UI unipolar UISOURCE update update rate V Vy Vcc National Instruments Corporation G 15 Glossary total harmonic distortion the ratio of the total rms signal due to harmonic distortion to the overall rms signal in decibel or a percentage signal to THD plus noise the ratio in decibels of the overall rms signal to the rms signal of harmonic distortion plus noise introduced the data measured in bytes s for a given continuous operation calculated to include software overhead See sensor the rate measured in bytes s at which data is moved from
109. r the PFI5 UPDATE pin Board and RTSI Clocks RTSI Triggers 6023E 6024E 6025E User Manual Many board functions require a frequency timebase to generate the necessary timing signals for controlling A D conversions DAC updates or general purpose signals at the I O connector These boards can use either its internal 20 MHz timebase or a timebase received over the RTSI bus In addition if you configure the board to use the internal timebase you can also program the board to drive its internal timebase over the RTSI bus to another board that is programmed to receive this timebase signal This clock source whether local or from the RTSI bus is used directly by the board as the primary frequency source The default configuration at startup is to use the internal timebase without driving the RTSI bus timebase signal This timebase is software selectable PXI 6025E The RTSI clock connects to other boards through the PXI trigger bus on the PXI backplane The RTSI clock signal uses the PXI trigger lt 7 gt line for this connection The seven RTSI trigger lines on the RTSI bus provide a very flexible interconnection scheme for any board sharing the RTSI bus These bidirectional lines can drive any of eight timing signals onto the RTSI bus and can receive any of these timing signals This signal connection scheme is shown in Figure 3 4 for PCI boards and Figure 3 5 for PXI boards 3 8 National Instruments Corporation Chapter 3 Hardwa
110. rce with 200 kQ and produce a 1 gain error Both inputs of the PGIA require a DC path to ground in order for the PGIA to work If the source is AC coupled capacitively coupled the PGIA needs a resistor between the positive input and AIGND If the source has low impedance choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current typically 100 KQ to 1 MQ In this case you can tie the negative input directly to AIGND If the source has high output impedance you should balance the signal path as previously described using the same value resistor on both the positive and negative inputs you should be aware that there is some gain error from loading down the source 4 16 National Instruments Corporation Chapter 4 Signal Connections Single Ended Connection Considerations A single ended connection is one in which the board analog input signal is referenced to a ground that can be shared with other input signals The input signal is tied to the positive input of the PGIA and the ground is tied to the negative input of the PGIA When every channel is configured for single ended input up to 16 analog input channels are available You can use single ended input connections for any input signal that meets the following conditions e The input signal is high level greater than 1 V e The leads connecting the signal
111. re Overview DAQ STC lt TRIG lt _ TRIG2 lt _ CONVERT lt lt UPDATE lt h WFTRIG lt gt GPCTRO_SOURCE lt _ GPCTRO_GATE lt GPCTRO_OUT STARTSCAN AIGATE gt SISOURCE UISOURCE GPCTR1_SOURCE gt GPCTR1_GATE lt gt RTSI_OSC 20 MHz Trigger RTSI Bus Connector RTSI Switch Figure 3 4 PCI RTSI Bus Signal Connection National Instruments Corporation 3 9 6023E 6024E 6025E User Manual Chapter 3 6023E 6024E 6025E User Manual Hardware Overview PXI Bus Connector ae A PXI Star 6 PXI Trigger 0 5 lt gt PXI Trigger 7 RTSI Switch switch lt ___ gt DAQ STC TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCTRO_SOURCE GPCTRO_GATE GPCTRO_OUT STARTSCAN AIGATE SISOURCE UISOURCE GPCTR1_SOURCE GPCTR1_GATE RTSI_OSC 20 MHz Figure 3 5 PXI RTSI Bus Signal Connection Table 3 3 lists the name and number of pins used by the PXI 6025E Table 3 3 Pins Used by PXI E Series Board PXIE Series Signal PXI Pin Name PXI J2 Pin Number RTSI lt 0 5 gt PXI Trigger lt 0 5 gt B16 A16 A17 A18 B18 C18 RTSI 6 PXI Star D17 RTSI Clock PXI Trigger 7 E16 Reserved LBL lt 0 3 gt C20 E20 A19 C19 Reserved LBR lt 0 12 gt A21 C21 D21 E21 A20 B20 E15 A3 C3 D3
112. roduct documentation When you contact us we need the information on the Technical Support Form and the configuration form if your manual contains one about your system configuration to answer your questions as quickly as possible National Instruments has technical assistance through electronic fax and telephone systems to quickly provide the information you need Our electronic services include a bulletin board service an FTP site a fax on demand system and e mail support If you have a hardware or software problem first try the electronic support systems If the information available on these systems does not answer your questions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest instrument drivers updates and example programs For recorded instructions on how to use the bulletin board and FTP services and for BBS automated information call 512 795 6990 You can access these services at United States 512 794 5422 Up to 14 400 baud 8 data bits 1 stop bit no parity United Kingdom 01635 551422 Up to 9 600 baud 8 data bits 1 stop bit no parity France 01 48 65 15 59 Up to 9 600 baud 8 data bits 1 stop bit no par
113. rounded Signal Source Not Connected to Building Ground Examples Examples Ungrounded Thermocouples Plug in instruments with e Signal conditioning with isolated outputs nonisolated outputs e Battery devices Differential DIFF See text for information on bias resistors NOT RECOMMENDED Ground Single Ended G Vi Referenced RSE Q Ground loop losses Vg are added to measured signal Single Ended Nonreferenced NRSE AIGND See text for information on bias resistors Figure 4 4 Summary of Analog Input Connections 6023E 6024E 6025E User Manual 4 12 National Instruments Corporation Chapter 4 Signal Connections Differential Connection Considerations DIFF Input Configuration A differential connection is one in which the analog input signal has its own reference signal or signal return path These connections are available when the selected channel is configured in DIFF input mode The input signal is tied to the positive input of the PGIA and its reference signal or return is tied to the negative input of the PGIA When you configure a channel for differential input each signal uses two multiplexer inputs one for the signal and one for its reference signal Therefore with a differential configuration for every channel up to eight analog input channels are available You should use differential input connections for any channel that meets any of t
114. rs ccccccccccceeeseeeeeeeee 24 bits Frequency scaler cccceeeeseeeeees 4 bits Compatibility 0 cee eeeeesseeeeeceteeeneeenees TTL CMOS Base clocks available Counter timers 0 cccccccceeesseeeeeees 20 MHz 100 kHz Frequency scalers ote eeeeeees 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency eee 20 MHz Min source pulse duration 0 ee 10 ns in edge detect mode Min gate pulse duration 10 ns in edge detect mode Data transfers eeeeeeseeeneeceteeeneeeenees DMA interrupts programmed T O DMA modes ieira Scatter gather Single transfer demand transfer A 8 National Instruments Corporation Appendix A Specifications Triggers Digital Trigger Compatibility 000 ee eeeeeeeeeeee TTL RESPONSE sce eovsives ase nics aiiai Nis Rising or falling edge PUlSO WAGED is pecscsccospestesarscecstesadtheeteestyes 10 ns min RTSI THe ger Hnesisin iii tae 7 Calibration Recommended warm up time 15 minutes Interval eo a elie E 1 year External Calibration reference gt 6and lt 10V Onboard calibration reference Level co cc chiens ae neces 5 000 V 3 5 mV actual value stored in EEPROM Temperature coefficient 0 5 ppm C max Long term stability oe eee 15 ppm 1 000 h Power Requirement 5 VDC 45 cecceescesceeseesceseeeeeneeeeenees 0 7A t Note Excludes power consumed through V available at the I O connector Power avail
115. s 4 15 to 4 16 single ended connections RSE configuration 4 18 FREQ_OUT signal description table 4 6 general purpose timing signal connections 4 49 signal summary table 4 8 frequently asked questions See questions and answers FTP support D 1 fuse self resetting C 1 G gain error adjusting 5 3 general purpose timing signal connections 4 43 to 4 49 FREQ_OUT signal 4 49 GPCTRO_GATE signal 4 44 GPCTRO_OUT signal 4 45 GPCTRO_SOURCE signal 4 43 to 4 44 GPCTRO_UP_DOWN signal 4 45 6023E 6024E 6025E User Manual Index GPCTR1_GATE signal 4 46 to 4 47 GPCTR1_OUT signal 4 47 GPCTR1_SOURCE signal 4 45 to 4 46 GPCTR1_UP_DOWN signal 4 47 to 4 49 glitch analog output 3 5 GPCTRO_GATE signal 4 44 GPCTRO_OUT signal description table 4 6 general purpose timing signal connections 4 45 signal summary table 4 8 GPCTRO_SOURCE signal 4 43 to 4 44 GPCTRO_UP_DOWN signal 4 45 GPCTR1_GATE signal 4 46 to 4 47 GPCTR1_OUT signal description table 4 5 general purpose timing signal connections 4 47 signal summary table 4 8 GPCTR1_SOURCE signal 4 45 to 4 46 GPCTR1_UP_DOWN signal 4 47 to 4 49 ground referenced signal sources description 4 9 differential connections 4 14 single ended connections NRSE configuration 4 18 to 4 19 H hardware configuration 2 3 installation 2 1 to 2 3 hardware overview analog input 3 2 to 3 5 dither 3 3 to 3 4 input mode 3 2 input range 3 2 to 3 3 analog
116. s related and data acquisition related configuration The PCI boards are fully compatible with the industry standard PCI Local Bus Specification Revision 2 1 The PXI board is fully compatible with the PXI Specification Revision 1 0 These specifications let your computer automatically set the board base memory address and interrupt channel with no user interaction You can modify data acquisition related configuration settings such as analog input range and mode through application level software Refer to Chapter 3 Hardware Overview for more information about the various settings available for your board These settings are changed and configured through software after you install your board Refer to your software documentation for configuration instructions National Instruments Corporation 2 3 6023E 6024E 6025E User Manual Hardware Overview This chapter presents an overview of the hardware functions on your board Figure 3 1 shows a block diagram for the 6023E 6024E and 6025E Voltage Multiplexer Calibration Mux REF z Dither Generator Analog Mode Calibration DACs T A D Converter Configuration Memory al ADC FIFO Data IRQ DMA Generic Bus Bus Interface Interface Address Data oO 8 Trigger Cc PFI Trigger Interface a ee O Counter oO Timing Timing I O O Digital O gt Digital 1 0 AO Con
117. scription table 4 4 signal summary table 4 7 DIFF mode description table 3 2 recommended configuration figure 4 12 differential connections 4 13 to 4 16 ground referenced signal sources 4 14 nonreferenced or floating signal sources 4 15 to 4 16 when to use 4 13 digital I O See also PPI Programmable Peripheral Interface common questions C 3 to C 5 overview 3 6 signal connections 4 21 digital I O specifications A 7 to A 8 DIO lt 0 7 gt A 7 PA lt 0 7 gt PB lt 0 7 gt PC lt 0 7 gt A 7 to A 8 digital trigger specifications A 9 DIO power up state changing to pulled low 4 24 to 4 25 DIO lt 0 7 gt signal description table 4 4 digital I O signal connections 4 21 digital I O specifications A 7 signal summary table 4 7 dither 3 3 to 3 4 documentation conventions used in manual xii xiii National Instruments documentation xiii organization of manual xi xii related documentation xiv National Instruments Corporation l 3 Index E EEPROM storage of calibration constants 5 1 electronic support services D 1 to D 2 e mail support D 2 environmental noise 4 49 to 4 50 equipment optional 1 6 EXTSTROBE signal DAQ timing connections 4 33 to 4 34 description table 4 5 signal summary table 4 7 F fax and telephone support numbers D 2 Fax on Demand support D 2 field wiring considerations 4 49 to 4 50 floating signal sources description 4 8 to 4 9 differential connection
118. ser interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of VIs for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW The LabVIEW Data Acquisition VI Library is functionally equivalent to NI DAQ software LabWindows CVI features interactive graphics state of the art user interface and uses the ANSI standard C programming language The LabWindows CVI Data Acquisition Library a series of functions for using LabWindows CVI with National Instruments DAQ hardware is included with the NI DAQ software kit The LabWindows CVI Data Acquisition Library is functionally equivalent to the NI DAQ software VirtualBench features virtual instruments that combine DAQ products software and your computer to create a stand alone instrument with the added benefit of the processing display and storage capabilities of your computer VirtualBench instruments load and save waveform data to disk in the same forms that can be used in popular spreadsheet programs and word processors Using ComponentWorks LabVIEW LabWindows CVI or VirtualBench software will greatly reduce the development time for your data acquisition and control application NI DAQ Driver Software The NI DAQ driver software is included at no charge with all National Instruments DAQ hardware NI DAQ is not packaged with SCXI or accessory products except for the SCXI 1200 NI DAQ has an extensive library of f
119. source to destination after software initialization and set up operations the maximum rate at which the hardware can operate trigger signal any event that causes or starts some form of data capture transistor transistor logic update interval a signal range that is always positive for example 0 to 10 V update interval counter clock signal the output equivalent of a scan One or more analog or digital output samples Typically the number of output samples in an update is equal to the number of channels in the output group For example one pulse from the update clock produces one update which sends one new sample to every analog output channel in the group the number of output updates per second volts positive supply voltage 6023E 6024E 6025E User Manual Glossary VDC VI waveform WFTRIG working voltage 6023E 6024E 6025E User Manual volts direct current virtual instrument 1 a combination of hardware and or software elements typically used with a PC that has the functionality of a classic stand alone instrument 2 a LabVIEW software module VI which consists of a front panel user interface and a block diagram program volts input high volts input low volts in measured voltage volts output high volts output low reference voltage volts root mean square multiple voltage readings taken at a specific sampling rate waveform generation trigger signal the highest voltage that should be appl
120. spect to acommon reference measurement system or a ground Also called a grounded measurement system G 12 National Instruments Corporation RTSI bus S sample counter scan scan clock scan rate SCXI SE self calibrating sensor settling time National Instruments Corporation G 13 Glossary real time system integration bus the National Instruments timing bus that connects DAQ boards directly for precise synchronization of functions For PCI boards the connection is made by means of connectors on top of the board For PXI boards the connection is made across the PXI trigger bus seconds samples the clock that counts the output of the channel clock in other words the number of samples taken On boards with simultaneous sampling this counter counts the output of the scan clock and hence the number of scans one or more analog or digital input samples Typically the number of input samples in a scan is equal to the number of channels in the input group For example one pulse from the scan clock produces one scan which acquires one new sample from every analog input channel in the group the clock controlling the time interval between scans the number of scans per second For example a scan rate of 10 Hz means sampling each channel 10 times per second Signal Conditioning eXtensions for Instrumentation the National Instruments product line for conditioning low level signals within an externa
121. t time sampling and seamless changing of the sampling rate are possible What does sampling rate mean to me It means that this is the fastest you can acquire data on your board and still achieve accurate results For example these boards have a sampling rate of 200 kS s This sampling rate is aggregate one channel at 200 kS s or two channels at 100 kS s per channel illustrates the relationship What type of 5 V protection do the boards have The boards have 5 V lines equipped with a self resetting 1 A fuse National Instruments Corporation C 1 6023E 6024E 6025E User Manual Chapter C Common Questions Installation and Configuration How do I set the base address for a my board The base address of your board is assigned automatically through the PCI PXI bus protocol This assignment is completely transparent to you What jumpers should I be aware of when configuring my E Series board The E Series boards are jumperless and switchless Which National Instruments document should I read first to get started using DAQ software Your NI DAQ or application software release notes documentation is always the best starting place What version of NI DAQ must I have to use my 6023E 6024E 6025E You must have NI DAQ for PC Compatibles version 6 5 or higher Analog Input and Output I m using my board in differential analog input mode and I have connected a differential input signal but my readings are random and drift rapidl
122. tation Amplifier Floating x 4 Signal Source o so Input Multiplexers M d o AISENSE v oe Voltage o o 1 O Connector Pai AIGND 7 Selected Channel in RSE Configuration Figure 4 7 Single Ended Input Connections for Nonreferenced or Floating Signals Single Ended Connections for Grounded Signal Sources NRSE Configuration To measure a grounded signal source with a single ended configuration you must configure your board in the NRSE input configuration The signal is then connected to the positive input of the PGIA and the signal local ground reference is connected to the negative input of the PGIA The ground point of the signal should therefore be connected to the AISENSE pin Any potential difference between the board ground and the signal ground appears as acommon mode signal at both the positive and negative inputs of the PGIA and this difference is rejected by the amplifier If the input circuitry of a board were referenced to ground in this situation as in the RSE input configuration this difference in ground potentials would appear as an error in the measured voltage 6023E 6024E 6025E User Manual 4 18 National Instruments Corporation Chapter 4 Signal Connections Figure 4 8 shows how to connect a grounded signal source to a channel configured for NRSE mode I O Connector Common Mode Signal Rejecti
123. ted Kingdom United States 6023E 6024E 6025E User Manual Telephone 03 9879 5166 0662 45 79 90 0 02 757 00 20 011 284 5011 905 694 0085 514 694 8521 45 76 26 00 09 725 725 11 O 148 14 24 24 089 741 31 30 2645 3186 91805275406 03 6120092 02 413091 03 5472 2970 02 596 7456 5 280 7625 8 357 7695 0348 433466 32 84 84 00 2265886 91 640 0085 93 582 0251 08 587 895 00 056 200 51 51 02 2377 1200 01635 523545 512 795 8248 D 2 Fax 03 9879 6277 0662 45 79 90 19 02 757 03 11 O11 288 8528 905 785 0086 514 694 4399 45 76 26 02 09 725 725 55 O 1 48 14 24 14 089 714 60 35 2686 8505 91805275410 03 6120095 02 4139215 03 5472 2977 02 596 7455 5 520 3282 8 365 8543 0348 430673 32 84 86 00 2265887 91 640 0533 93 582 4370 08 730 43 70 056 200 51 55 02 2737 4644 01635 523154 512 794 5678 National Instruments Corporation Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Compan
124. ternal sources such as semiconductors resistors and capacitors Noise corrupts signals you are trying to send or receive a type of digital acquisition generation where LabVIEW updates the digital lines or port states immediately or returns the digital value of an input line Also called immediate digital I O or non handshaking signal sources with voltage signals that are not connected to an absolute reference or system ground Also called floating signal sources Some common example of nonreferenced signal sources are batteries transformers or thermocouples nonreferenced single ended mode all measurements are made with respect to a common NRSE measurement system reference but the voltage at this reference can vary with respect to the measurement system ground output pin a counter output pin where the counter can generate various TTL pulse waveforms the amount of time required for the analog output voltage to reach its final value within specified limits the maximum rate of change of analog output voltage from one level to another Peripheral Component Interconnect a high performance expansion bus architecture originally developed by Intel to replace ISA and EISA It is achieving widespread acceptance as a standard for PCs and work stations it offers a theoretical maximum transfer rate of 132 Mbytes s a measure of signal amplitude the difference between the highest and lowest excursions of the signal G 10 National
125. the digital I O lines PA lt 0 7 gt PB lt 0 7 gt PC lt 0 7 gt at power up Each digital I O line is configured as an input pulled high by a 100 KQ bias resistor You can change individual lines from pulled up to pulled down by adding your own external resistors This section describes the procedure Changing DIO Power up State to Pulled Low Each DIO line is pulled to V approximately 5 VDC with a 100 kQ resistor To pull a specific line low connect between that line and ground a pull down resistor R whose value will give you a maximum of 0 4 VDC The DIO lines provide a maximum of 2 5 mA at 3 7 V in the high state Using the largest possible resistor ensures that you do not use more current than necessary to perform the pull down task However make sure the resistor s value is not so large that leakage current from the DIO line along with the current from the 100 KQ pull up resistor drives the voltage at the resistor above a TTL low level of 0 4 VDC Figure 4 12 shows the DIO configuration for high DIO power up state 82C55 Digital I O Line RL Figure 4 12 DIO Channel Configured for High DIO Power up State with External Load Example A given DIO line is pulled high at power up To pull it low on power up with an external resistor follow these steps 1 Install a load R1 Remember that the smaller the resistance the greater the current consumption and the lower the voltage 6023E 602
126. ther voltage source on the board or any other device Doing so can damage the board and the computer National Instruments is NoT liable for damages resulting from such a connection Timing Connections A Caution Exceeding the maximum input voltage ratings which are listed in Table 4 2 can damage the board and the computer National Instruments is nor liable for any damages resulting from such signal connections All external control over the timing of your board is routed through the 10 programmable function inputs labeled PFI lt 0 9 gt These signals are explained in detail in the section Programmable Function Input Connections These PFIs are bidirectional as outputs they are not programmable and reflect the state of many DAQ waveform generation and general purpose timing signals There are five other dedicated outputs for the remainder of the timing signals As inputs the PFI signals are programmable and can control any DAQ waveform generation and general purpose timing signals The DAQ signals are explained in the DAQ Timing Connections section later in this chapter The waveform generation signals are explained in the Waveform Generation Timing Connections section later in this chapter The general purpose timing signals are explained in the General Purpose Timing Signal Connections section in this chapter All digital timing connections are referenced to DGND This reference is demonstrated in Figure 4 16 which shows how to
127. till plainly visible In Figure 3 2c the sine wave is acquired with dither on There is a considerable amount of visible noise but averaging about 50 such acquisitions as shown in Figure 3 2d eliminates both the added noise and the effects of quantization Dither has the effect of forcing quantization noise to become a zero mean random variable rather than a deterministic function of the input signal National Instruments Corporation 3 3 6023E 6024E 6025E User Manual Chapter 3 Hardware Overview a Dither disabled no averaging b Dither disabled average of 50 acquisitions c Dither enabled no averaging d Dither enabled average of 50 acquisitions Figure 3 2 Dither Multichannel Scanning Considerations The boards can scan multiple channels at the same maximum rate as their single channel rate however pay careful attention to the settling times for each of the boards No extra settling time is necessary between channels as long as the gain is constant and source impedances are low Refer to Appendix A Specifications for a complete listing of settling times for each of the boards When scanning among channels at various gains the settling times may increase When the PGIA switches to a higher gain the signal on the previous channel may be well outside the new smaller range For instance suppose a 4 V
128. tional Connectors Figure B 1 shows the pin assignments for the 68 pin E Series connector This connector is available when you use the SH6868 or R6868 cable assemblies with the 6023E and 6024E It is also the MIO 16 68 pin connector available when you use the SH1006868 cable assembly with the 6025E 6023E 6024E 6025E User Manual B 2 National Instruments Corporation Appendix B Custom Cabling and Optional Connectors ACH8 34 68 ACHO ACH1 33 67 AIGND AIGND 32 66 ACH9 ACH10 31 65 ACH2 ACH3 30 64 AIGND AIGND 29 63 ACH11 ACH4 28 62 AISENSE AIGND 27 61 ACH12 ACH13 26 60 ACHS5 ACH6 25 59 AIGND AIGND 24 58 ACH14 ACH15 23 57 ACH7 DACOOUT 22 56 AIGND DAC1OUT 21 55 AOGND RESERVED 20 54 AOGND DIO4 19 53 DGND DGND 18 52 DIOO DIO1 17 51 DIO5 DIO6 16 50 DGND DGND 15 49 DIO2 5V 14 48 DIO7 DGND 13 47 DIOS DGND 12 46 SCANCLK PFIO TRIG1 11 45 EXTSTROBE PFI1 TRIG2 10 44 DGND DGND 9 43 PFI2 CONVERT 5 V 8 42 PFI3 GPCTR1_SOURCE DGND 7 41 PFl4 GPCTR1_GATE PFI5 UPDATE 6 40 GPCTR1_OUT PFI6 WFTRIG 5 39 DGND DGND 4 38 PFI7 STARTSCAN PFI9 GPCTRO_GATE 3 37 PFI8 GPCTRO_SOURCE GPCTRO_OUT 2 36 DGND FREQ_OUT 1 35 DGND 1 Not available on the 6023E Figure B 1 68 Pin E Series Connector Pin Assignments National Instruments Corporation
129. tive of or plus a square root of 5 V 5 VDC source signal National Instruments Corporation G 1 6023E 6024E 6025E User Manual Glossary A A AC ACH A D ADC ADC resolution Al AIGATE AIGND AISENSE alias ANSI AO AOGND ASIC asynchronous 6023E 6024E 6025E User Manual amperes alternating current analog input channel signal analog to digital analog to digital converter an electronic device often an integrated circuit that converts an analog voltage to a digital number the resolution of the ADC which is measured in bits An ADC with 16 bits has a higher resolution and thus a higher degree of accuracy than a 12 bit ADC analog input analog input gate signal analog input ground signal analog input sense signal a false lower frequency component that appears in sampled data acquired at too low a sampling rate American National Standards Institute analog output analog output ground signal Application Specific Integrated Circuit a proprietary semiconductor component designed and manufactured to perform a set of specific functions for a specific customer 1 hardware a property of an event that occurs at an arbitrary time without synchronization to a reference clock 2 software a property of a function that begins an operation and returns prior to the completion or termination of the operation G 2 National Instruments Corporation bandwidth base address BIOS bipolar
130. to the board are less than 10 ft 3 m e The input signal can share a common reference point with other signals DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions Using your software you can configure the channels for two different types of single ended connections RSE configuration and NRSE configuration The RSE configuration is used for floating signal sources in this case the board provides the reference ground point for the external signal The NRSE input configuration is used for ground referenced signal sources in this case the external signal supplies its own reference ground point and the board should not supply one In single ended configurations more electrostatic and magnetic noise couples into the signal connections than in differential configurations The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electrical coupling is a function of how much the electric field differs between the two conductors National Instruments Corporation 4 17 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Single Ended Connections for Floating Signal Sources RSE Configuration Figure 4 7 shows how to connect a floating signal source to a channel configured for RSE mode ACH oO OO O So h Soy Programmable Gain Instrumen
131. tomer Communication of this manual Turn off and unplug your computer Choose an unused PXI slot in your system For maximum performance the board has an onboard DMA controller that can only be used if the board is installed in a slot that supports bus arbitration or bus master cards National Instruments recommends installing the board in such a slot The PXI specification requires all slots to support bus master cards but the CompactPCI specification does not If you install in a CompactPCI non master slot you must disable the board s onboard DMA controller using software Remove the filler panel for the slot you have chosen Touch any metal part of your computer chassis to discharge any static electricity that might be on your clothes or body Insert the board into a 5 V PXI slot Use the injector ejector handle to fully insert the board into the chassis Screw the front panel of the board to the front panel mounting rail of the system 2 2 National Instruments Corporation Chapter 2 Installation and Configuration 8 Visually verify the installation 9 Plug in and turn on your computer The board is installed You are now ready to configure your hardware and software Hardware Configuration Due to the National Instruments standard architecture for data acquisition and standard bus specifications these boards are completely software configurable You must perform two types of configuration on the boards bu
132. trol Analog Input Timing Control DMA Interrupt Request DAQ STC Bus Interface 1 Analog Output Timing Control RTS Bus Interface A l Control DAQ Interface APE Play Analog Output Control Address nalog 1 H EEPROM DMA input 1 Control Interface f 1 Bus 1 82C55 1 Interface pip lt DACO lt lt DAC1 Calibration DACs Analog Output Not on 6023E RTSI Connector DIO Control 6025E Only PCI Connector for PCI 602X PXI Connector for PXI 6025E National Instruments Corporation Figure 3 1 6023E 6024E and 6025E Block Diagram 3 1 6023E 6024E 6025E User Manual Chapter 3 Hardware Overview Analog Input Input Mode Input Range 6023E 6024E 6025E User Manual The analog input section of each board is software configurable The following sections describe in detail each of the analog input settings The boards have three different input modes nonreferenced single ended NRSE input referenced single ended RSE input and differential DIFF input The single ended input configurations provide up to 16 channels The DIFF input configuration provides up to eight channels Input modes are programmed on a per channel basis for multimode scanning For example you can configure the circuitry to scan 12 channels four differentially configured channels and eight single ended
133. ttriggered Acquisition 4 32 National Instruments Corporation Chapter 4 Signal Connections TRIG1 TRIG2 STARTSCAN CONVERT Scan Counter Don t Care 0 cu 2 I i 2 i 1 2 0 Figure 4 18 Typical Pretriggered Acquisition SCANCLK Signal SCANCLEK is an output only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A D conversion begins The polarity of this output is software selectable but is typically configured so that a low to high leading edge can clock external analog input multiplexers indicating when the input signal has been sampled and can be removed This signal has a 400 to 500 ns pulse width and is software enabled Figure 4 19 shows the timing for the SCANCLK signal CONVERT i ta SCANCLK he l tw tg 50 to 100 ns tw 400 to 500 ns Figure 4 19 SCANCLK Signal Timing EXTSTROBE Signal EXTSTROBE is an output only signal that generates either a single pulse or a sequence of eight pulses in the hardware strobe mode An external device can use this signal to latch signals or to trigger events In the single pulse mode software controls the level of the EXTSTROBE signal A 10 us and a 1 2 us clock are available for generating a sequence of eight pulses in the hardware strobe mode Figure 4 20 shows the timing for the hard
134. ual gate signal connected to the general purpose counter 0 GPCTRO_OUT DGND Output Counter 0 Output This output is from the general purpose counter 0 output FREQ_OUT DGND Output Frequency Output This output is from the frequency generator output Not available on the 6023E 2 Not available on the 6023E or Indicates that the signal is active low 6024E 6023E 6024E 6025E User Manual 4 6 National Instruments Corporation Chapter 4 Signal Connections Table 4 2 shows the I O signal summary for the 6023E 6024E and 6025E Table 4 2 1 0 Signal Summary Signal Impedance Protection Sink Rise Type and Input Volts Source mA Time Signal Name Direction Output On Off mA at V at V ns Bias ACH lt 0 15 gt AI 100 GQ 42 35 200 pA in parallel with 100 pF AISENSE AI 100 GQ 40 25 200 pA in parallel with 100 pF AIGND AO DACOOUT AO 0 1 2 Short circuit 5 at 10 5 at 10 10 6024E and 6025E only to ground V us DACIOUT AO 0 1 Q Short circuit 5 at 10 5 at 10 10 6024E and 6025E only to ground V us AOGND AO DGND DO VCC DO 0 1 Q Short circuit 1A fused to ground DIO lt 0 7 gt DIO View 0 5 13 at Veg 0 4 24 at 1 1 50 kQ pu 0 4 PA lt 0 7 gt DIO Vise 0 5 2 5 at 3 7min 2 5 at 5 100 kQ 6025E only 0
135. ucts are NOT intended to be a substitute for any form of established process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment Contents About This Manual Organization of This Manual 00 0 eee eeeseeeeecseecsecseeeaeceeceaeceeceseeseceeesseseeeeeeseaseseeeaes xi Conventions Used in This Manual cccccessscccsssecesseceseseceseeceecseecseaeecseseeesseeeenenees xii National Instruments Documentation ccccccceessceeessecesesceeceececesaeecseeececeseeceseeeensaes xiii Related Doc MENIA OT r aee a a aa aa a E a a a iE et xiv Customer COMMUNICATION eer r e enr e Ea E R TE E E xiv Chapter 1 Introduction Features of the 6023E 6024E and 6025E ccccccsssccccecesssceececessececeeceessaeceeceesenseeees 1 1 Using PXI with CompactPCl cic eceecsessecssesseceeceseeseceseeseceseeeeseneseaecaeesaecaseaeenees 1 2 What You Need to Get Started ceccccescesssceessseceseeeeceseeceeeeecsenececeseeeesneeecesaeeeseneees 1 2 Wnipackim g e a ere rea E tech EE EEE tie Helene EEE R ha RE E whee E 1 3 Software Programming Choices sesesseseseesssreseseeresresrertssrreseetesrsresresesresrerrsreeresrsteses 1 3 National Instruments Application Software ssessssesesseersererrsesrrrrrrrrrseeereseee 1 4 NI DAQ Driver SO WA E a aa a a a a ea aE a ini 1 4 Register Level Programming sseesssssressssesrsreereerssrrrssrerrsrersreserrenrerrsreeresent 1 6 Optional E
136. unctions that you can call from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation timed D A conversion digital I O counter timer operations SCXI RTSI self calibration messaging and acquiring data to extended memory 6023E 6024E 6025E User Manual 1 4 National Instruments Corporation Chapter 1 Introduction NI DAQ has both high level DAQ I O functions for maximum ease of use and low level DAQ I O functions for maximum flexibility and performance Examples of high level functions are streaming data to disk or acquiring a certain number of data points An example of a low level function is writing directly to registers on the DAQ device NI DAQ does not sacrifice the performance of National Instruments DAQ devices because it lets multiple devices operate at their peak NI DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to your code Whether you are using conventional programming languages or National Instruments application software your application uses the NI DAQ driver software as illustrated in Figure 1 1 ComponentWorks
137. unters 0 and 1 respectively PA lt 0 7 gt 2 DGND Input or Output Port A bidirectional digital data lines for the 82C55A programmable peripheral interface on the 6025E PA7 is the MSB PAO is the LSB PB lt 0 7 gt 2 DGND Input or Output Port B bidirectional digital data lines for the 82C55A programmable peripheral interface on the 6025E PB7 is the MSB PBO is the LSB PC lt 0 7 gt 2 DGND Input or Output Port C bidirectional digital data lines for the 82C55A programmable peripheral interface on the 6025E PC7 is the MSB PCO is the LSB 5 V DGND Output 5 VDC Source These pins are fused for up to 1 A of 5 V supply The fuse is self resetting 6023E 6024E 6025E User Manual 4 4 National Instruments Corporation Chapter 4 Signal Connections Table 4 1 1 0 Connector Signal Descriptions Continued Signal Name Reference Direction Description SCANCLK DGND Output Scan Clock This pin pulses once for each A D conversion in scanning mode when enabled The low to high edge indicates when the input signal can be removed from the input or switched to another signal EXTSTROBE DGND Output External Strobe This output can be toggled under software control to latch signals or trigger events on external devices PFIO TRIG1 DGND Input PFI0 Trigger 1 As an input this is one of the Programmable Function Inputs PFIs PFI signals are explained
138. ur board will fit in any 5 V expansion slot in your computer However to achieve best noise performance leave as much room as possible between your board and other devices The following are general installation instructions Consult your computer user manual or technical reference manual for specific instructions and warnings National Instruments Corporation 2 1 6023E 6024E 6025E User Manual Chapter 2 Installation and Configuration PCI Board Installation 6023E 6024E 6025E User Manual 1 icky gt ok 8 9 Write down your board s serial number in the 6023E 6024E 6025E Hardware and Software Configuration Form in Appendix D Customer Communication of this manual Turn off and unplug your computer Remove the top cover of your computer Remove the expansion slot cover on the back panel of the computer Touch any metal part of your computer chassis to discharge any static electricity that might be on your clothes or body Insert the board into a 5 V PCI slot Gently rock the board to ease it into place It may be a tight fit but do not force the board into place Screw the mounting bracket of the board to the back panel rail of the computer Visually verify the installation Replace the top cover of your computer 10 Plug in and turn on your computer PXI Board Installation 1 Write down your board s serial number in the 6023E 6024E 6025E Hardware and Software Configuration Form in Appendix D Cus
139. ur computer In a PXI system the RTSI bus consists of the National Instruments RTSI bus interface and the PXI trigger signals on the PXI backplane to route timing and trigger signals between several functions on as many as seven DAQ boards in your system National Instruments Corporation 1 1 6023E 6024E 6025E User Manual Chapter 1 Introduction These boards can interface to an SCXI system the instrumentation front end for plug in DAQ boards so that you can acquire analog signals from thermocouples RTDs strain gauges voltage sources and current sources You can also acquire or generate digital signals for communication and control Using PXI with CompactPCI Using PXI compatible products with standard CompactPCI products is an important feature provided by PXI Specification Revision 1 0 If you use a PXI compatible plug in card in a standard CompactPCI chassis you will be unable to use PXI specific functions but you can still use the basic plug in card functions For example the RTSI bus on your PXI E Series board is available in a PXI chassis but not in a CompactPCI chassis The CompactPCI specification permits vendors to develop sub buses that coexist with the basic PCI interface on the CompactPCI bus Compatible operation is not guaranteed between CompactPCI boards with different sub buses nor between CompactPCI boards with sub buses and PXI The standard implementation for CompactPCI does not include these sub buses Y
140. ustom Cabling and Optional Connectors Appendix C Common Questions Appendix D Customer Communication National Instruments Corporation vil 6023E 6024E 6025E User Manual Contents Glossary Index Figures Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware ccccsccccsecesssceeesecesesceesseeecseeesseeeenaes 1 5 Figure 3 1 6023E 6024E and 6025E Block Diagram eee eee eee eneeeeeeeee 3 1 Bigure 322 Dither n ni eene ae Actes Sects See A e icone aces 3 4 Figure 3 3 CONVERT Signal Routing eee csecsseeeceeceseceeeeseeeeeeseeeeeees 3 7 Figure 3 4 PCI RTSI Bus Signal Connection eee ee eee eseeeneeseecsecneeeneesaeenees 3 9 Figure 3 5 PXI RTSI Bus Signal Connection eee eeeseecseensecseeeseesseesees 3 10 Figure 4 1 I O Connector Pin Assignment for the 6023E 6024E ee 4 2 Figure 4 2 I O Connector Pin Assignment for the 6025E ooo eee eeeeeeeeeee 4 3 Figure 4 3 Programmable Gain Instrumentation Amplifier PGIA 4 10 Figure 4 4 Summary of Analog Input Connections 2 0 0 0 cece eee eeseeseceeeeseeeeees 4 12 Figure 4 5 Differential Input Connections for Ground Referenced Signals 4 14 Figure 4 6 Differential Input Connections for Nonreferenced Signals 4 15 Figure 4 7 Single Ended Input Connections for Nonreferenced Or Floating Sigmals s ci cc c s cb coceccsteecacecuscnecocaeees sovca osnov ero erie a EASi 4 18 Figure 4 8 Sin
141. ware strobe mode EXTSTROBE signal National Instruments Corporation 4 33 6023E 6024E 6025E User Manual Chapter 4 Signal Connections vee i L L tw 600 ns or 5 us Figure 4 20 EXTSTROBE Signal Timing TRIG1 Signal Any PFI pin can externally input the TRIG1 signal which is available as an output on the PFIO TRIG1 pin Refer to Figures 4 17 and 4 18 for the relationship of TRIG1 to the DAQ sequence As an input the TRIG1 signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG1 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG 1 signal starts the data acquisition sequence for both posttriggered and pretriggered acquisitions As an output the TRIG1 signal reflects the action that initiates a DAQ sequence This is true even if the acquisition is being externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 21 and 4 22 show the input and output timing requirements for the TRIGI signal Rising Edge Polarity Falling Edge Polarity tw 10 ns minimum 6023E 6024E 6025E User Manual Figure 4 21 TRIG1 Input Signal Timing 4 34 National Instruments Corporation Chapter 4 Signal Connections 1 I I i i lt gt I 1 I 2 I 1 f ty 50 100
142. ws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation ComponentWorks CVI DAQ STC LabVIEW Measure MITE natinst com NI DAQ RTSI SCXI and VirtualBench are trademarks of National Instruments Corporation Product and company names mentioned herein are trademarks or trade names of their respective companies WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments prod
143. xternally generated by another PFI The output is an active low pulse with a pulse width of 50 to 150 ns This output is set to tri state at startup Figures 4 27 and 4 28 show the input and output timing requirements for the CONVERT signal Rising Edge Polarity 1 t 1 lt gt Falling Edge Polarity tw 10ns minimum 6023E 6024E 6025E User Manual Figure 4 27 CONVERT Input Signal Timing 4 38 National Instruments Corporation Chapter 4 Signal Connections tw 50 150 ns Figure 4 28 CONVERT Output Signal Timing The sample interval counter on the board normally generates the CONVERT signal unless you select some external source The counter is started by the STARTSCAN signal and continues to count down and reload itself until the scan is finished It then reloads itself in preparation for the next STARTSCAN pulse A D conversions generated by either an internal or external CONVERT signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence may be gated by either the hardware AIGATE signal or software command register gate AIGATE Signal Any PFI pin can externally input the AIGATE signal which is not available as an output on the I O connector The AIGATE signal can mask off scans in a DAQ sequence You can configure the PFI pin you select as the source for the AIGATE signal in either the level detecti
144. y Address Fax Phone Computer brand Model Processor Operating system include version number Clock speed MHz RAM MB Display adapter Mouse ___ yes ___no___ Other adapters installed Hard disk capacity MB Brand Instruments used National Instruments hardware product model Revision Configuration National Instruments software product Version Configuration The problem is List any error messages The following steps reproduce the problem 6023E 6024E 6025E Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently National Instruments Products Board Serial Number Hardware revision Interrupt level of hardware DMA channels of hardware Base I O address of hardware Programming choice National Instruments software Other boards in system Base I O address of other boards DMA channels of other boards Interrupt level of other boards Other Products Computer make and model Microprocessor
145. y What s wrong Check your ground reference connections Your signal may be referenced to a level that is considered floating with reference to the board ground reference Even if you are in differential mode the signal must still be referenced to the same ground level as the board reference There are various methods of achieving this while maintaining a high common mode rejection ratio CMRR These methods are outlined in Chapter 4 Signal Connections I m using the DACs to generate a waveform but I discovered with a digital oscilloscope that there are glitches on the output signal Is this normal When it switches from one voltage to another any DAC produces glitches due to released charges The largest glitches occur when the most significant bit MSB of the D A code switches You can build a lowpass deglitching filter to remove some of these glitches depending on the frequency and nature of your output signal 6023E 6024E 6025E User Manual C 2 National Instruments Corporation Chapter C Common Questions Can I synchronize a one channel analog input data acquisition with a one channel analog output waveform generation on my PCI E Series board Yes One way to accomplish this is to use the waveform generation timing pulses to control the analog input data acquisition To do this follow steps 1 through 4 below in addition to the usual steps for data acquisition and waveform generation configuration 1 Enable the PFIS5

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