Service Manual - R6 RU4 Montesecchieta
Contents
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12. p d d 20149 DP0105 2 Front View 2 0001 7 N 0 O O 9 5 00114 00727 01 802 16 AF0020 6 01 86Z 3 Rear View AF0020 TS0102A 5 0008 FP0093AY 6 A Sa 0094 Lay SDA UE0029A 0012 17 81 2894 6coodH 69002 2114007999 86 05 220000 2 690 10001 0105 0 906484 SILA AELC ASDEDHH 0 05 0 506 9 A 89fASDEDNH 3 dnb O90EAY AZOSCASDEMAA 3dno LOCI AFLC ASDEDHH adm 9061 10 ASOIfASDEDHH AFCC ASDEDHH 3dno 9906n1 ACIG ASDEDHH 3 dno 68022 AZ89MASDEMAA Ad Vs6codn d8E000ZENXV 02090 IOLNO do 60059 61 2 do 60050 120 _ Odmo 109 Odmo scono do 960059 _ 110 Odmo 0109 do 6fr00SD 60 2 do 750082 6012 Odmo ezoenmo 6012 _ Odmo 200 Odmo 100 187 149 duo y os ____ 12995 zooz 06 91 AESOOLS AAA MAMA MEA cora rana 881004
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14. 162MHz for TA2 Version Caution lll Do not press the or key while channel 20 is selected in the adjustment mode Otherwise the VCO switch frequency will change causing a malfunction 22 23 Reference Frequency Adjustment High Power Adjustment Low Power Adjustment Minimum Frequency Sensitivity Adjustment Medium Frequency Sensitivity Adjustment Maximum Frequency Sensitivity Adjustment 1 In the adjustment mode select channel 1 by rotating the main tuning dial Press the key to start transmission 3 Rotate TC101 on the RF circuit board until the value on the frequency counter matches the one displayed on the LCD 4 On 145 05MHz measure TP near the VCO and adjust L301 to obtain 1 1V 0 1V If the second decimal point is flashing the PLL is unlocked N 1 In the adjustment mode select channel 2 by rotating the main tunin dial 2 Hold down the key and press the key to enter the high power mode L at the lower left of the display disappears 3 Hold down the key to start transmission 4 While watching the reading of the TX power meter set the output power to the value closest to 5 W by using the or keys 5 When the key is released the output power at that time will be stored as the high power setting 1 In the adjustment mode select channel 3 by rotating the main tuning dial 2 Hold down the key and press the key to enter the low power mode L appears at the lower left of the
15. has stabilized When the external power drops to 3 2 V or below the output signal from the backup IC IC3 which has been input to pin 34 of the CPU changes from H to L level The CPU will then be in the backup state The DC potential of pin 13 of IC104 18 input to pin 3 of the CPU IC5 converted from an analog to a digital signal and displayed as the S meter signal on the LCD The CPU IC5 is equipped with an internal tone encoder The tone signal 67 0 to 254 1 Hz is output from pin 11 of the CPU to the varicap of the VCO for modulation Page 5 5 CPU Terminal Functions M38267M8L 413 035 10 5 5 714 12 93S ld 5 D3SFld 5 O3S Ld 8 OISPId 8 916 04 5 D3SP0d 8 53SPSd 5 53S O0d 2 O53S O0d 5 53S 0d 5 4935 04 8 D3SP0d 5 503S d 8 t 3SP d DISPEd 5 53SP d 8 DISFEd 8 O3Sf d 095 8 El D3SPE d N 1035 KI 035 N DIST O3S RI DIS 2035 Ri DIST DIS 50 149 1 48 2 47 o 46 P2 45 P2 44 43 o P2 42 41 P2 Vss 39 38 37 136 35 RESET 134 33 7 32 P7 31 lt P7 40 8 714 Of Ld ale a gt INI Fd IN INOW 9
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17. ev BP3 TICD ev 1 1 7 8 9 1 5 4 5 gt a 5 100 4V L2 E x a dM set e 561 1 R64 849 6 8 EERE 85 R79 R99 gt 1 MONI 867 4 7 012 3 55 m 4 E 2 58V 0 2 7 DOWN NA mih 11 1 1 suoni 5 5 D 4 UNS210 Y b C45 0 061 R57 C29 220p 1 2K 5 an uf 2052 02545988 453589 CN7 004200 33 38 Cav 5 8 amp 01 03 C3V A 1101 Cav A 01 LAMP ON CMT si Ev Cav lt Cv A is T is x oc D on 2 9 2 0 o ly C40 lo UK Pot 9 1 240687 1 42 amp gt 2 EY HT Vee 5 DIL IC2 E 25 RHSVL25AA RHSVL32AA gt 4 19 Li R 33P 556 5 9 1 35 ua Ll R56 220K R68 82K 106 NS 2 4 S No os 5 5 777 oR das no JA TX B 2 0v E OV C 0V 38 R72 33K C24 Q7 0 022 0 022 DTIC144EK C25 R73 CN3 CN4 P2 B 128G02M RE1 5 1 Sao S R 3 um SL R75 LS 8 47K AFP a BEEN 2 Fe lol 2 4 13 14 81006 K 17
18. SEMICONDUCTOR DATA 1 24LC16BT 1 SN 0351 EEPROM Pin Assignment 24LC01B 24LC02B 24LC04B 24LC08B 24LC16B Block Diagram WP HV generator Memo SCION EEPROM array circuit XDEC Page latch YDEC Sense amplifier R W control 1 control circuit 2 5222 600 XA0385 Electronic Volume RI 26 8 e 207 d NE 49 48 rr 9 99 mem IN RI Voltage to ampere Vi to i converting circuit i Vi Ri TdT TT xj f OUT Q105 0 Q107 RO 10 3 M64076GP 0352 PLL Pin Assignment 20 GND 19 Xin 18 Xout 17 2 16 1 15 Fin2 14 Lock2 13 PD2 12 VT2 11 GND 11 Block Diagram 2 modular Pre scaler 1 64 65 2 modular Pre scaler 4 RH5VL25AA T1 XA0309 C MOS Voltage Detector Data latch 17 bits 1 64 65 Programmable divider for local 2 Data latch 16 bits 1 Programmable for local 1 Data latch 17 bits Data latch 6 bits 21 bit shift re
19. tester Press the key The transceiver beeps indicating the new setting has been stored successfully In the adjustment mode select channel 9 by rotating the main tuning dial Input 50 mVrms 1 2 signal with your transceiver tester through the external microphone jack With the tester put the transceiver in the transmission mode Using the or key set the deviation to the value closest to 4 5kHz deviation has three levels namely O to 2 which is displayed in the uper right corner of the LCD This function is only for checking the tone encoder not adjusting it 1 In the adjustment mode select channel 12 by rotating the main tuning dial Press the key A 67 Hz tone is automatically sent Check the deviation with the transceiver tester In the adjustment mode select channel 13 by rotating the main tuning dial Press the key An 88 5 Hz tone is automatically sent Check the deviation with the transceiver tester 24 25 Tone 250 3 Hz Test Tone Burst Test Aging Note on Adjusting Sensitivity 1 In the adjustment mode select channel 14 by rotating the main tuning dial 2 Press the key A 250 3 Hz tone is automatically sent 3 Checkthe deviation with the transceiver tester This function is only for checking the tone burst not adjusting it 1 In the adjustment mode select channel 15 by rotating the main tuning dial 2 Pressthe key A 1750 Hz tone burst is automatically sent 3 C
20. 11 88001 1110 AEICIVSC 21015180011 88001 0110 W90LLISOPOSC 6001 6010 N90LL660rOSc 96001 8010 1015180011 6101 1010 5 184 60004 9010 TLADIO9 EMSZ 184 000 0 9010 N90OIL660 OSZ 96001 lt 010 XI TOSIAX PTAIIL OSELISZ 10 SISUPA ITNAIL ISECOST 01818461 IT XOIXG809IHTN 109 L MO0IYG9IZEXTA TOD __ 0 1109 __ 0 1109 __ 0 1109 __ 0 1109 9 ToD VSLVAO 1109 1 01 09091 1109 1301 09091 110 10 LCE STAN ToD FO LSE STAN 1109 LCE STAX ToD 110 TLXO OZX N TA XAZLEEON 2009 4 501 01 II OLI OI 05702 60002 TLOOV 1400 11 00 1100 0600 0570 0570 OVM OVM 91000 COV E 4 lt nO oo 5 2 eo d E Ct Q a Q lt TT an dia 0 013 013 CN lt 212012 AIAIAIAIAIAIOIAI lt I lt lt lt lt lt TX 7
21. 13001111 9190912 seoeno 209 VLOOSONIHOS0910 900 2 909 71111 91909122 __ 160602 soga 13 01111 91909122 roco 13 0111199091 7210 00 ALWILFDOSWONLL 90 209 13001111 9190912 __ 109 2 1 4 260040 PISIUSINd AIOIOSL 12004 ____ 004 ZHWSCIc MSMO 9 000 101 AVOIZLO 10012 10121 AC OlfASDEfHH ATU scocxW AIOLASDENNE ococxW Occ AE LV ASDEfHH edi scocxW 6108 di coocxwW CA 9 di SICA A OlfASDETNH 4 2 OSOCNW 013 4 2 080 AO00NOASDETNH 4 2 100634 0103 4 440 29020 AO0NOASDETNH 4 2 100634 1013 4 2 COE AEISIASDENNE 4 0 arzzrasoerda AIUD OOH poza azorrasoerda dual COTA azzrasoerda ACID croc soral arcrrasoerda 9614 areerasoerda 4 440 soral azorrasoerda dual SEES cola Aoorrasoerda AIUD VIOEAN Toral __ eorerasoerda AIUD OOH 1613 asorrasoerda AIUD OOH 6814 AIUD OOH 88
22. 14 NELVEASDEINA AIUD SOA 814 azprasoerda AIUD ove 9814 aporrasoerda AIUD COOEAN SST NELCEASDEINA pera azzzrasoerda esta aelprasoerda AIUD azprasoerda AS 9 IST azzzrasoerda duo croc OSTA aAreerasoerda 4 440 ACSIFASDERIA duo 8213 AVLVEASDEINA AIUD OLOEAN LLIN ACLPfASDEDHH AIUD OVOEAN 9 1 arzzrasoerda AIUD VSOEAN GL TH aposrasoerda AIUD 1002 PLT azeerasoerda AIUD proca ELIA arzzrasoerda AIUD VSOEAN CLIN AIUD SOA LI azorrasoerda 0213 NICEFASDEINA 4 440 CEOEAN 69TH azazrasoerda SOLON 8914 ACOMASDEPDNH Lora Azprasoerda aS 9914 dual POT AICCfASDEPNH 4 440 AESIFASDERIA Adol ZIA AESIFASDERIA 4 440 1914 arzzrasoerda 4 440 VSOEAN ooral azosrasoerda zroesa asocrasoerda 4 440 650634 esta azerrasoerda duo Troe sia ACSIFASDERIA 9914 J A LPfASDEDHH azzzrasoerda dual croc pela aezzrasoerda AIUD VSOEAN esta __ ALFfASDEPHH aS VEOEAN OSTA asorrasoerda a dS Loew asgorasoerda AIUD asorrasoerda AIUD Loew Lora asorrasoerda asorrasoer
23. 4 azosrasoerga ado Lroexal J AFCC ASOtfWHH dd 990694 AESIfASDEPMHH Ada ESOC ACOIfASOEfWHH 860694 A OIFASDE SIA AMI 0S0ENA AESI ASDELHA 0 A OIFASDE SIA 0S0ENA 40 1 AM 0 ATOILASDELHA 9Z05XX ASOIASDEMJA AZONASDEMNA _ CVl AczirAsoerga adoj 16024 HVIVITL OSOENA ado agorrAsoerga ddu osoexal J AIOIfASDEfWH Udo 90 J AEOIfASDEfWHH HCO 0504 CVl AECIfASOtPWHH adoj 16024 HVIVITL A OIfASOEDNH AMO OSOENA AIOUXAS9graH AIOUXAS9grag AdO NAM Adol _ 970 A amp O0IfASDEfWH adoj 050634 ATLISASDESSA PEON AJOMASOEMJA adoj adyo 9700 AIs raspersal _ adyo SCOEAM 1014 1 29000 000 xXurizenn ssw 8600 6110 9OLLWOHbbIVLO 2035180811 SZIONMX 8110 ISSHL O S90SOST JOISISUBIL IOLX 72110 XI 10SIdX 1osrsue L 210 00 9110 W90LLISOPOSC 60020 AEICIVSC 21015180011 88001 1110 0 9 0 2 100 SVLLVLVINA 2000 10151800
24. 86 R177 C179 C183 C191 and C194 and the internal noise amplifier in IC104 The desired noise of the signal 15 output through pin 11 of IC104 to be further amplified by the noise amplifier Q115 The amplified noise signal is rectified by voltage doublers D109 and input to pin 4 of CPU 105 Page 3 2 Transmitter System 1 Modulator Circuit 2 Power Amplifier Circuit 3 APC Circuit The audio signal 15 converted to an electric signal in either the internal external microphone and input to the microphone amplifier 1 6 IC6 consists of two operational amplifiers one amplifier pins 1 2 and 3 1s composed of pre emphasis and IDC circuits and the other pins 3 6 and 7 15 composed of a splatter filter The maximum frequency deviation 15 determined to its optimal value by switch circuits consisting of Q9 and and input to the cathode of the varicap of the to change the electric capacity in the oscillation circuit This produces the frequency modulation The transmitted signal 15 oscillated by the VCO amplified by the pre drive amplifier Q102 and drive amplifier Q101 and input to the power module 1101 The signal is then amplified by the power module IC101 and led to the antenna switch D101 and low pass filter L102 L103 L104 C113 C107 C116 and C114 where unwanted high harmonic waves are reduced as needed and the resulting signal is supplied to the antenna Part of the transmission power
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27. O 2 2K le R316 504 teuH 820 854494068480940960444848 08 462990 SHON 268 MOD 1 5 0 9 314 1305 1800 5 RX 130 09 161 7 2 551 TX 130 00 140 00MHz GND Ne 75 151 17 174 00 2 96 TX 140 00 174 00MHz ne 4 3 US gt 999e9909090090098699494590909900000 95 29 04949 90 00 P9 99 94 VO 9900900 OF CO 0600 4 HE 0049 4694 b4 000400 OO PO OV OV V9 99 0000 10409099 0400 89 5900 00 PO HE TA Pa 245 UG P9 NEES EE O00440 99 2 9d 1 DE R208 0116 NC NC To CPU Unit 41 LINSNYY1 3913934 3 14234 gt LINSNVYL 5 dmn 021 AvdSIq rer 927 mn m as 021 JndNI A34 MS B ndo so 131 XY WAS lt 4 Ed 13938 8 MS 565 AS ACI WSZ SHY L2 qnx ZII AYA noud33 LIZBEN CIZIYSZ 521 1110 189127 2 121 3300930 3NOL 83002N3 AYVLOY viZZNN BOLZIAON LZSNN EA 91 60 DIN D ZHWSZ 1Z 310 DIA DIN 1919 A30 49920990 Td 33113 4001 5 669952 5905252 590 lt 252 03911210 wo lt coro VIVO 114 34408 831308 ODA MS XU Xl N 2 CIZIYSZ SE 809252 966252 9854956 125 nid 7812
28. Service Manual CONTENTS SPECIFICATIONS 2 CIRCUIT DESCRIPTION 3 SEMICONDUCTOR DATA 9 EXPLODED VIEW 15 PARTS LIST 18 ADJUSTMENT 21 PCBOARD VIEW 26 CIRCUIT DIAGRAM 36 BLOCK DIAGRAM 43 ALINCO INCORPORATED TWIN 21 TOWER BUILDING 23F 1 61 2 SHIROMI CHUO KU OSAKA 540 8580 JAPAN Tel 81 6 6946 8150 fax 81 6 6946 8175 e mail export alinco co jp SPECIFICATIONS Frequency Coverage DJ 190T u s Amateur version DJ 190E European Amateur version DJ 190TA1 commercial version DJ 190TA2 commercial version VHFH Channel Step Memory Channels Antenna Impedance Frequency Stability Microphone Input Impedance S gnal Type Offset Range Deviation TX Output supply voltage RX Sensitivity RX Selectivity ILF Power Supply Requirements Current Consumption at 13 8V DC Operating Temperature Dimensions with EBP 37N without projections Weight Subaudible Tones CTCSS TX RX 144 000 147 995MHz 135 000 173 995MHz 144 000 145 995MHz 144 000 145 995MHz 135 000 155 000MHz 135 000 173 995MHz 150 000 173 995MHz 135 000 173 995MHz 5 10 12 5 15 20 25 30kHzsteps 40 Channels 50ohm unbalanced 5 ppm 2kohm nominal F3E FM 0 99 995 7 15 max 1 5W 4 8V 3 5W 7 2V SW 9 6 13 8V 124 SINAD better than 16dBu 6dB 12kHz 1st 21 25MHz 2nd 450kHz 4 8 13 8V DC 4 8V DC standard Transmitting Approx 1 2 Amp
29. TPOOIN 0617 121 OIW 4948 290004 061 1291 Lid A68I0D4 O6rradeo er 81004 06 eqqny f Jaqny 981004 06IfdIeqnx eid AISIODH 9 0 A081094 dj 9905 01044 sodp qgvod 014524 40 mas 000XV WIS SL OXLN LON 7295 100 5 0 7 7 XOd __ MOIS 1000 maws 00001 sodZ ad 9 ZN S Hd MOS z ooav Sued PUY __ 98 002 260051 AzzZrASOE a YU Nea 8 5 760634 orea 5 6064 AzzZrASOE a NUO 8064 sdno LOE APOHASDEDHIH 29004 9064 APOHMASDEDIH socal APOHASDEDHIH adyo 90634 A 0HASDEPHIH YU coca aArzzrAsoera YU zoca AIOHASDEPHIH YU 1064 E E NEN E E EA EA p pio moeods ewedsizarioosa SW IrterHimosooro 9cognD rreo mm En E ES A E E EA Ea EA EA VIMCOIHIgf800102 190 VINZOIHIAISO9IO __ 2440 TIED VINZOIHIAIS09IO TIED 71111 91909122 16060 2 oreo VID0Z0DIHD809ID 900 6091 VI20S0DIHO80912 9000 9091
30. charge pump output pin 8 of IC102 generates a pulse signal which is converted to DC voltage by the PLL loop filter and input to the varicap of the VCO unit for oscillation frequency control Page 4 5 VCO Circuit A Colpitts oscillation circuit driven by Q301 directly oscillates the desired frequency The frequency control voltage determined in the CPU 1 5 and PLL circuit 1s input to the varicaps D301 and D304 This changes the oscillation frequency which is amplified by the VCO buffer Q302 and output from the VCO unit Note The oscillation frequency 1s determined by turning Q301 ON and OFF Displayed frequencies Q301 TX 130 00 139 995 MHz RX 130 00 161 695 MHz TX 140 00 173 995 MHz RX 161 70 173 995 MHz 4 CPU and Peripheral Cir The CPU turns ON the LCD segment and common terminals with 1 3 1 LCD Display Circuit 2 Display Lamp Circuit 3 Reset and Backup Circuits 4 S Signal Meter Circuit 5 Tone Encoder the duty and 1 3 the bias at the frame frequency is 85 Hz When the LAMP key is pressed H is output from pin 45 of CPU 1 5 to the bases of Q1 then turn ON and the LEDs DI D3 Bight When the power from the DC jack or external battery increases from 0 V to 2 5 or more H level reset signal is output from the reset IC IC2 to pin 35 of the CPU IC5 causing the CPU to reset The reset signal however waits at C6 and R98 and does not enter the CPU until the CPU clock X1
31. da AIUD VLOEAN SPIN A OIEASDEDHH Admofosocma veral Se MN TS ON yu 199 0 0 OOAAUN AA ADJUSTMENT 1 Required Test Equipment 1 Regulated power supply 2 Digital multi meter 3 Oscilloscope 4 Audio dummy load 2 SSG 6 Spectrum Analyzer 7 Power meter 8 Audio voltmeter 9 Audio generator 10 Distortion meter SINAD meter 11 Frequency counter 12 Linear detector Note Standard modulation Reference sensitivity The following items are required to adjust radio parameters Supply voltage 5 14 VDC Current 3 A or more Voltage range FS Approx 20 V Current 10A or more Input resistance High impedance Measurable frequency Audio frequency Impedance 8 ohm Dissipation 1 W or more Jack 3 5 mm D Output frequency 200 MHz or more Output level 20 dB 0 1 a V 120dB 1V Modulation AM FM Measuring range Up to 2 GHz or more Measurable frequency Up to 200 MHz Impedance 50 ohm unbalanced Measuring range 10 W Measurable frequency Up to 100 KHz Sensitivity mV to 10 V Output frequency 67 Hz to 10 kHz Output impedance 600 ohm unbalanced Measurable frequency 1 kHz Input level Up to 40 dB Distortion level 1 100 Measurable frequency Up to 200 MHz Measurable stability Approx 0 1 ppm Measurable frequency Up to 200 MHz Cha
32. display 3 Hold down the key to start transmission 4 While watching the reading of the TX power meter set the output power to the value closest to 0 8 W by using the or keys 5 When the key is released the output power at that time will be stored as the low power setting See Note on Adjusting the Sensitivity later in this section 1 In the adjustment mode select channel 4 by rotating the main tuning dial 2 Using the or key set the minimum frequency sensitivity See Note on Adjusting the Sensitivity later in this section 1 In the adjustment mode select channel 5 by rotating the main tuning dial 2 Using the or key set the medium frequency sensitivity See Note on Adjusting the Sensitivity later in this section 1 In the adjustment mode select channel 6 by rotating the main tuning dial 2 Using the or key set the maximum frequency sensitivity S meter 1 Adjustment S meter FULL Adjustment Deviation Tone 67 Hz Test Tone 88 5 Hz Test In the adjustment mode select channel 7 by rotating the main tuning dial The S meter will show a single star Enter 0 dB y with the transceiver tester Press the key The transceiver beeps indicating the new setting has been stored successfully In the adjustment mode select channel 8 by rotating the main tuning dial The S meter will show all six stars X 9 Enter 20 dB with the transceiver
33. enD 9210 VID0OIOHIHD809ID 200600 VIMCOIHIgf800 1O 2 do VIf0CCHIHOS09IO 2442 EZIO VII070HIHO8091D 00819 VID050HIHD809ID DTD vooenol 2210 VID0ZOHIHD809ID 00819 VID050HIHD809ID ___ 20 d 00819 1210 01 18 80913 2 40 6605 610 VIMCOIHIgf800 1O 2 40 sEOENO STIO ALWSOIIIVSOWL dio 670050 112 0011111909 106 2 910 VIf0LFHIHOS09IO 61 06 9119 VIf0SIHIHOS09IO 4 eroenal VIIOSIHIHD809ID 8sIogsnD YIID VLf0LFHIHOS09IO 6106 VIIOSIHIHD809ID 2492 VLIOEEHIHDSO9IO LIOENO VLI00IHIHO809I9 110 01 ZITO 01119091 442 LIOENO 0102 VID09 0HIHD809ID 2492 2000 90121 VID090HIHD809ID 2000 20121 VID060HIHD809ID 010 01 20121 01119091 442 LIOENO 9019 13301111 9190912 442 sorol 13001111 9190912 ss0gnD roro 13001111 9190912 ___ 2 40 sg0gnD 6012 lt coto VIMCOIHIgf800 1O p cre l A CRA uonduoseq oN sred PN qu send ini ei _ E E iu _ p E pz HVL VIAL HVL VL HL HVLVLTL 01 09 EXS IXYLAS
34. from the low pass filter is detected by D103 converted to DC and then amplified by a differential amplifier The output voltage controls the bias voltage from pin 2 of the power module IC101 to maintain the transmission power constant 3 PLL Synthesizer Circuit The dividing ratio is obtained by sending data from the CPU 105 to pin 2 I PLL 2 Reference Frequency Circuit 3 Phase Comparator Circuit and sending clock pulses to pin 3 of the PLL IC IC102 The oscillated signal from the VCO 15 amplified by the buffer Q117 and input to pin 6 of IC102 Each programmable divider in IC102 divides the frequency of the input signal by N according to the frequency data to generate a comparison frequency of 5 or 6 25 kHz The reference frequency appropriate for the channel steps is obtained by dividing the 21 25 MHz reference oscillation X101 by 4250 or 3400 according to the data from the CPU IC5 When the resulting frequency is 5 kHz channel stepsof5 10 15 20 25 and 30 kHz are used When it is 6 25 kHz the 12 5 kHz channel step is used The PLL IC102 uses the reference frequency 5 or 6 25 kHz The phase comparator in the IC102 compares the phase of the frequency from the VCO with that of the comparison frequency 5 or 6 25 kHz which is obtained by the internal divider in IC102 4 PLL Loop Fitter Circuit If a phase difference 15 found in the phase comparison between the reference frequency and VCO output frequency the
35. gister Tu 21 pulse counter Latch selection Data latch 16 bits Programmable divider for 4 reference frequency 2 m Lock detection c s 55 va 28 58 22 a Tr circuit for high pressure proof LPF Charge eS pump Tr ES Charge PS pressure proof LPF 4 circuit for V V 5 5 2 1 XA0198 C MOS Voltage Detector Block Diagram 6 MC3372VM EL 0343 Narrow Band IC Block Diagram 7 2070 T1 XA0210 Audio Power Amplifier TOP View 12 8 NJM2100M 1 XA0209 Operational Amplifier Pin Assignment Block Diagram A OUTPUT 1 8j jv A INPUT 2 7 JB OUTPUT INPUT 68 INPUT v 14 5 JB INPUT TOP VIEW INPUT INPUT 9 Transistor Diode and LED Ontline Drawings Top View DA204U T106 FMA7XT 148 MA716 TW MA741WA TX se XD0130 er PASTA I a 2 MA742 TX UN211H TX UN2214 TX UN9111 TX XU0040 XU0038 XU0062 AA re lt lt lt lt lt iii alal 13 OUTPUT 10 P A Module 101 XA0381 T XA0439 0421 1 2 GND GND 11 LCD Connection 14 EXPLODED VIEW 1 Front View 1 FGO179Z T
36. heckthe deviation with the transceiver tester Perform this aging test only when necessary 1 In the adjustment mode select channel 16 by rotating the main tuning dial The transceiver automatically repeats transmission for a minute and reception for another minute Sensitivity is adjusted by applying the optimum voltage from the CPU to the varicap of the tuning circuit The coil manipulation for L109 L110 L111 and L112 is not required If any of the coils is accidentally rotated return it to the default position as described below before adjusting the sensitivity 1 Program any frequency within 145MHz 1 MHz on memory channel 5 2 Holding down both the and key press the POWER switch to turn the power ON chEc will appears on the LCD for two seconds and C appears 3 Select channel 5 by rotating the main tuning dial 4 Using the or keys set the adjustment data to 7F 7F appears in the channel number area on the LCD 5 Turnthe power OFF 6 Holding down both the and key turn the power ON When the C no longer appears the transceiver is in the normal status 7 Set the reception frequency to 145 MHz 1MHz Rotate the coil to maximize the sensitivity PC BOARD VIEW CPU Unit Side A VALUE 26 CPU Unit Side A REFERENCE VAL CPU Unit Side B VALUE 28 Unit Side If is replaced clone data must be transfered to the repaired radio from a brand new radio For cl
37. in High Power Setting Receiving Squelched Approx 24mA BS on 10 60 C 14 140 F 57 W x 151 H x 27 D mm 2 1 4 W x 6 x 1 1 16 D inches Approx 300g Encoder installed 50 tones Page 2 CIRCUIT DESCRIPTION 1 Receiver System 1 Front End 2 IF Circuit 3 Demodulator Circuit A Audio Circuit 5 Squelch Circuit The receiver system is a double superheterodyne system with a 21 7 MHz first IF and a450 kHz second IF The received signal at any frequency in the 130 00 to 173 995 MHz range 15 passed through the low pass filter L102 L103 L104 C113 C107 C116 and C114 and tuning circuit 1 112 and D107 and amplified by the RF amplifier Q107 The signal from Q107 1s then passed through the tuning circuit L109 L110 L111 and varicapsi D104 D105 and D106 and converted into 21 7 MHz by the mixer Q106 The tuning circuit which consists of L112 L109 varicaps D107 and D104 11110 L111 varicaps D105 and D106 is controlled by the tracking voltage from the CPU so that it is optimized for the reception frequency The local signal from the VCO is passed through the buffer Q108 and supplied to the source of the mixer Q106 The radio uses the lower side of the superheterodyne system The mixer mixes the received signal with the local signal to obtain the sum of and difference between them The crystal filter XF101 XF102 selects 21 7 MHz frequency from the results and eliminates the signals of the unwa
38. nit Side VALUE REFERENCE 35 CIRCUIT DIAGRAM PTT UNIT FEY PTT 5 LAMP m M MONI PET MON 4 KO 1 GND VCO UNIT R301 100 MT 890 1901 SOY 021070 ar 9059 YAN Av Lv coca C305 470P 1000 LOCI al 0301 2505065 020 COSY 100 1990 0 OUT 0303 _DTC114EU 95555 YSIVHO sos MOL 60t 4 9051 MOD VCO 36 CHARGE UNIT 2781 010020 0801 0 U2FWJ44N Mn 13 07V 0802 U2FWJ44N TO RF Neca 15 07 5 B 5 284 SS GND E 8 az 0801 12 3V E 12 98V 12 98V TSQ UNIT 1 R707 100P 9 270K R710 02265 5 6K 4 7u 16V 1u 16V 2 o 2 48 555 8 5558 RER VAL 8718 WA BIAS DENNATU 1C761NO DOUSADENNATU WO KETTUTEI 37 DC IN 13 8V CPU UNIT n 0 15K C3V 101 No er 1 1 5 E 0 53V 2 0 3 55 xi x ae AN CIV A i 215 KO R7 1x r ni VOL LEVEL 16 3 27 sa VOL LEVEL 16 BV VOL LEVEL 16 VOL LEVEL 16 av VOL LEVEL 16 cc Vdd i Im 105 vd L9 Vdd scum NE ro 3 53V OV PIT ON 3 54 3 544 TX on 2 02 1 4V 3 29V
39. nted frequencies The first IF amplifier Q105 then amplifies the signal of the selected frequency After the signal is amplified by the first IF amplifier Q105 it is input to pin 16 of the demodulator 1 104 The second local signal of 21 25 MHz shared with PLL IC reference oscillation which is oscillated by the internal oscillation circuit in C102 and crystal X101 is input through pin 1 of IC104 Then these two signals are mixed by the internal mixer in IC104 and the result is converted into the second IF signal with a frequency of 450 kHz The second IF signal is output from pin 3 of C104to the ceramic filter FL101 where the unwanted frequency band of that signal is eliminated and the resulting signal is sent back to the IC104 through pins 5 and 7 The second IF signal input via pin 7 is demodulated by the internal limiter amplifier and quadrature detection circuit in 1 104 and output as an audio signal through pin 9 The audio signal from pin 9 of IC104 15 compensated to the audio frequency characteristics in the de emphasis circuit R162 R161 C172 C173 and amplified by the AF amplifier Q109 The signal is then input to pin 2 of the electronic volume 1C103 for volume adjustment and output from pin 1 The adjusted signal is sent to the audio power amplifier 1C105 through pin 2 to drive the speaker Part of the audio signal from pin 9 of IC104 is amplified by the noise filter amplifier consisting of R176 R1
40. o0emo 185 _ OdMmo ceoemo 960 OdMmo ceoemo SEDI OdMmo ceoemo DdmoplssosnD zed digo 5900 9 IED OdMmol6s0EmO 060 Po diy 200 _ diy seoenoj zo OdMo zO0EMO 920 1 0 ST OdMo ISO0EMO _ Idmo ceoemo ezo diy seoeno _ 100 VILXZOIHIgr809ID odmo seoeno 000 VII 089HIHD809ID ICON 610 ALNSOIIIVSOWL 670052 810 XILINSZZIOVSDINIL du 150050 910 VIZIOLATASS09 IO ___ 0 440 6606 2 ULMWL0IDOCINONI 902052 ALWILYIIAWOIWL duo 16050 YLINLOIDOGADIAL do 902052 60 VIMCOIHIgf800 1O ___ 2 40 80 VILXCZOIHIgr809ID 2 40 12 ULWSLICOVINOMI 103461 440 800050 90 SW LI0 HIHO809IO ___ 2 440 10200 SWV LIO0 HIHO809IO 442 106 2 ALMNLOIDOAWINL diy 900052 1 01 18 800123 Odmo ceoemo 12 nnd LSTI SLIVA 61 9384 ACCCLASDE SIA AMI ATCCLASDE SIA AMI 0 0 NA AESILASOELAH a dyo 0 cra Orla sel YU Lela SETA tel Y Tela Ocla SCI 921 VOT ICT 614 8113 8113 Lila 9113 SITA pila ella ella TIT 0114 8014 LOTA 9014 SOLA 2014 cora p E ACOIfASOtfWHH 86069
41. one procedures see page 24 of the Inst ruction Manual REFERENCE RF Unit Side A VALUE REFERENCE 30 31 RF Unit Side B VALUE RF Unit Side REFERENCE Ege 0107 m 157 E Sed Em 4 n 41C LO Pa o 0185 Riaz 4 d omen Brise j 14 De n vo pe Po Ths E 010 22 E Tih d ds re 2 20 alr T misil ET iG PETOA ces i RIG ET RAN ta2 cE TOREO 3 EM 75 ene f H 4 sj E ER fos der EU T eios MA 09 Wee PTT Unit Side A VALUE REFERENCE ide 1 VALUE REFERENCE SW403 SWAOI SW404 SW402 33 VCO Unit Side A VALUE us pao sr 0 919050 070050 a 3 gt m G VCO Unit Side B VALUE x E p urease REFERENCE As ses R peor REFERENCE 34 10821 717882 TPOB3 TP866 8 CHARGE Unit Side A VALUE REFERENCE CHARGE Unit Side B VALUE REFERENCE TSQ Unit Side A VALUE REFERENCE Aer 6K _ 1 18 TSQ U
42. racteristics Flat CN 60 dB or more 1 kHz 3 5 kHz DEV 12dBSINAD Specified audio output level 200 mW at 8 ohm Standard audio output level 50 mW at 8 ohm Use an RF cable 3D2W 1 m for test equipment Attach a fuse to the RF test equipment AI SSG outputs are indicated by EMF Supply voltage for the transceiver 13 8 VDC Page 21 2 Adjustment Mode The DJ 190 does not require a serviceperson to manipulate the compo nents on the printed circuit board except the trimmer and coil when adjusting frequency Most of the adjustments for the transceiver are made by using the keys on it while the unit is in the adjustment mode Because the adjustment mode temporarily uses the channels frequency must be set on each channel before adjustments can be made For instructions on how to program the channels see the DJ 190 INSTRUCTION MANUAL which came with the product In consideration of the radio environment the frequency on each channel must be near the value 1 MHz listed in the table below To enter the adjustment mode turn the power off hold down both the UP and DOWN keys and press the POWER key appears on the LCD for about two seconds and C appears indicating the unit is in the adjustment mode Channel frequencies used in the adjustment mode Maximum frequency sensitivity adjustment 173 MHz S meter 1 adjustment 5 145 MHz S meter FULL adjustment 145 MHZ
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