"TRF6900 Evaluation Board User's Guide"
Contents
1. Chip Layout Screen for Receiver Testing Measured Data With 50 dBm Input Signal at AMP_OUT and RXDATA POMS once a Measured Data With 90 dBm Input Signal at AMP_OUT and RXDATA Test PONS aa a quies ead ate glatte gat Leos Chapter 1 Overview This chapter provides an overview of the TRF6900 evaluation module EVM Topic Page 1 2 1 2 1 2 1 3 Purpose 1 1 Purpose 1 2 EVM Setup The TRF6900 evaluation module EVM provides a platform for lab prototype evaluation of the Texas Instruments TRF6900 The TRF6900 EVM board is used to evaluate the RF performance of the TRF6900 It contains a PC parallel port interface and operates from 850 MHz to 950 MHz from 2 2 V to 3 6 V The TRF6900 EVM contains seven SMA connectors that allow the user to observe transmitted data LNA output mixer output IF output RSSI output to test the VCO tuning range or to feed in an external RF input or mixer signal The transmitted data can be viewed on a spectrum analyzer as either a single output frequency or in FSK mode at data rates up to 30 kbps Although higher data rates are achievable with the TRF6900 the TRF6900 EVM is designed to operate at data rates up to 30 kbps at room temperature The 3 5 inch diskette supplied with the TRF6900 contains the softwa2. ARMM d 1 2 1 3 Block Diagram be ED UE get ee dr oe oet 1 3 Evaluation Board ee eee e nnn 2 1 2 1 ertet tete agen eee nerf ee eee 2 2 2 1 4 Top Side Silkscreen and Drawing 2 4 2 1 2 Bottom Side Silkscreen and Drawing 2 5 2 2 at ed a ceu ERR RUE 2 6 2 9 EVM DC Voltage Setup sse sure bene SEU 2 9 2 4 Serial Interface and PC Port Pin Out 2 10 2 5 Standard PC Parallel Port 2 11 2 6 Jumper Connections 2 12 2 6 1 Jumper Connections 2 13 2 6 2 Jumper 2 13 2 7 Connectors and Test Points sn 2 15 227251 COMMECIOLS sso 5 63 eate ned pane tit Sia ve Piles 2 15 2 f 2 Test Pointe CLP a td erue Be ELE I teats 2 15 2 03 Adjustments 22555245 tet ar Ok suat 2 16 ZLA bED lndICators 5 oou boxe eere ee ee 2 16 Software User s Guide nn nnn 3 1 3 1
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4. Vo 8 aD Fie Edt Go Help Low Pass Piker 0 OFF L 6n valid in Made and Mode 1 Pur T um fin ske jon IF fon Words fem n Tx A foo 1000110101001 100000000 Moda 0 47 za E zl ejf 10001 10101001 100000000 Mode i Enable lon gt 11011110011401100110111111 Mode 10111111111111000000000 Mode 01 Clock width 345 Strobe width 75 Operation Made Mode 1 TXData DIT Chip On When Word Bits are Displayed in Red the Send Words Now F12 Button Must Be Pressed for __ Changes to Be Updated Note The receiver frequency of the TRF6900 is 915 000 MHz The TRF6900 15 us ing a 10 7 MHz IF frequency Therefore the local oscillator LO is set to a frequency of 904 30 MHz LO frequency RF frequency IF Frequency 904 30 915 000 10 7 The desired frequency block of the TRF6900 software control program is used to set the internal VCO frequency of the TRF6900 See block diagram Software User s Guide 3 19 Testing of the Receiver Figure 3 17 Chip Layout Screen for Receiver Testing High Gain BEI A IF Amp UM 55 ON a y LFF FSK 100 E Pul q Daa Sicer Press to Program
5. eC arrears ae nee at da art ee eet ee 3 2 3 2 Main Program Screen 3 3 3 21 Syntheslzer c nones Pere eis aie Rui GNE Cr Eos 3 3 3 2 2 ORE RERO EE REDE 3 4 3 23 Output Parameters dee ss cel OR bue mall pr Ie eet 3 4 3 24 PLL and MM Options n 3 4 3 25 t eC TEE 3 4 23 2 6 Help x a ni ERE RE ERES 3 5 MOIS coiere eim em Ue ee reet IEEE EE I M 3 5 3 2 8 Operation Mode ose rere kg 3 5 3 2 9 Changing Values on the Main Program Screen 3 5 3 3 Chip Layout Screenm c irene dee nrg tare Phe damm dare sere cals 3 7 3 4 PLL Modulation Options Screen 0 3 8 3 5 Testing of Transmitter 1 3 9 3 6 Testing of the Receiver 3 18 3 6 1 Test Equipment Setup 0 3 18 3 6 2 Software Programming for Receiver Testing 3 6 3 Learning and Hold Modes 3 6 4 Measured Receive Figures d d d d 1 T vi TRF6
6. Smp Alaria i cose 1 Dts Smich TxDaOFF Enable Test 100 Hz Dura 536 OFF Run Time Select This Button to Start the FSK Modulation Test Send words Select This Button With Mouse to Set FSK Frequency veo j as Select to Program the TRF6900 Setthe DVx bits as shown in Figure 3 11 by double clicking inside each DVx box to set the value to either a 1 or 0 For this example only DV6 is set to a 1 Li Press the Send Bits button located on the PLL Modulations Options Screen to obtain the results shown in Figure 3 11 Li Press the Close button located on the PLL Modulations Options screen 3 14 Testing of Transmitter Figure 3 11 PLL Modulation Options Screen DV6 Display Set to 1 SE Frequency Fegato Dv4 DWI DWI DVO k d fo 00 gi 7 80 1007 12069 14D f4 Frequency pied mu 915 MHz Fout T4 Dala Low MHz fo Frequency 915 10 MHz FSK Deviation of 100 kHz 944755 54275 Delia Foul KHz Send Bits Button Pressthe Send Words button on the chip layout screen or the Send Words Now F12 on the main program screen Press the FSK Test button on the chip layout screen as shown in Figure 3 10 to start the FS
7. 1 Daa Sech FSK Test send wodr Lo PAF Hz OFF vco vco n Run Time Miri After setup is complete press the Send Words button on the chip layout screen or the Send Words Now F12 button on the main program screen to send the programming words to the TRF6900 Software User s Guide 3 11 Testing of Transmitter Step 3 Spectrum Analyzer Setup and Clock Offset Procedure Set up the spectrum analyzer to observe the following Figure 3 7 Spectrum Analyzer Delta 4 1 RBW 300 Hz RF Att 40 dB Ref Lvl 41 62 dB VBW 30 Hz 10 dBm 20 24048096 kHz SWT 28 s Unit dBm Wee Teal 4 9 14 999698940 MHz 0 40 ag 4 00801 3 kHz a2 1 11 47 390 dB Center 9815 MHz 10 kHzz Span 100 kHz Date 21 JAN 00 16 17 06 Clock Offset Procedure 1 Use the test setup as seen in Figure 3 4 and transmitter software setup as shown in Figure 3 6 2 Observe the frequency reading on the frequency counter 3 Subtract 915 000000 MHz from the frequency counter reading 4 Enter the difference value in the Freq Error box in the main program screen as shown in Figure 3 8 5 If difference value is negative enter sign followed by the difference value Example Frequency Counter reading is 914 996000 MHz Subtracting 915 000 MHz from 914 996 MHz yields a difference of 4000 Hz This difference is entered in the Freq Error block as 0 004 MHz
8. the LPF amplifier enabled ane the a En DM 2 data patch ls get bo pecan for gn pr Press Enber on Ans bo Send ALL Pur SE TN FE Words pro gt Words GE s Im LPT_ Ji 0 Made 1 cr Mode 10 1 Made 0 Eus LEOLELEELELELEECODOLIODOD Operation Mode Moden Chip On Computer Printer Port Press to Program the TRF6900 LPT1 or LPT2 NOTE When word bits are displayed in RED the Send Words Now F12 button on the main program screen must be pressed for changes to be updated The main program screen is divided into eight main sections as follows 3 2 1 Synthesizer This section is used to set the crystal clock CLK frequency the Desired Freq and the PreScaler value of the divided by N of the PLL From these inputs the actual frequency and bit values of Words A and B are calculated Software User s Guide Main Program Screen 3 2 2 Mode Options This section allows the user to control various features of the TRF6900 The following is a brief summary of the 12 controls 1 PLL Turns the phase locked loop on or off 2 VCO Turns the voltage controlled oscillator on or off 3 Pwr Amp Allows the power amp to be set to off 20 dB attenuation 10 dB attenuation or 0 9 attenuation states 4 Slicer Turns the data slicer on or
9. TRF6900 EVM uses pins 2 7 for signals from the PC to the EVM Pins 11 and 12 are used for signals from the EVM to the PC Evaluation Board 2 11 Jumper Connections 2 6 Jumper Connections Figure 2 3 shows the default position of the jumpers on the TRF6900 EVM Figure 2 3 EVM Jumper Locations and Default Configuration of the EVM J1 MIX OUT 1 J3 IF Out FN 1 e ft e e e MIX_OUT 2 22 JP 2 2 IF1 OUT BPF1 Input 1 Ber 9 BPF2 Input 17 JP1 default is NO Connection P BPF1 Output BPF2 MIX_IN IF2 IN BPF2 Output JP2 J2 LNA OUT MIX OUT LNA OUT E 5 8 5 2j 9 1 z lt n 5 c 5 5 a gt RX IN gt 2nd LNA_GND RF Buffer IF Amplifier DEM VCC Amplifier Limiter LNA IN RF Mixer 1st IF DEM TANK Amplifier FM FSK LNA GND Demodulator DEM TANK LO Buffer Amplifi J5 Out PA mplifier RSSI OUT ey AMP_IN LPF Amplifier Post Detection Amplifier 1 AMP CAP _ RSSI RXDATA Out FON 2 es 4 J6 AMP OUT q S amp H CA TRF6900 Top View DATA OUT Direct Digital Synthesizer Serial DATA and Interface Power Down Logic CLOCK 9 STROBE Default connection S a Q Q a a CE 6 z 2 9 B 9 e 9 5 90 8 Q
10. a 8 x 9 On 38 a a gt gt 2 12 Jumper Connections 2 6 1 Jumper Connections JP1 To IC1 44 MIX OUT JP9 1 To 1 1 47 1 OUT 1 Input 1 1 46 MIX IN JP3 JP4 To IC1 41 IF1 OUT To J6 RSSI RXDATA OUT To BPF2 Input To 1 1 28 RXDATA To R11 and C29 Loop Filter To Voce To R19 and R21 VCO Tank To Mode Test Point To Ground JP6 Default is no connection JP8 Voce VR1 output VCC1 To STDBY Test Point To LED3 anode Power on LED To Ground JP7 Default is no connection BPF1 Bypass Capacitor To IC1 44 MIX OUT gt 4 Denotes Default Connection To IC1 42 IF1 IN 8 Default is a 0 1 2 6 2 Jumper Description The jumpers on the TRF6900 EVM as shown in Figure 2 3 are used for the following purposes JP1 Jumper JP1 is used for testing of the mixer circuit of the TRF6900 Testing of the mixer stage by itself is accomplished by connecting JP1 1 to 1 2 connecting JP2 1 to JP2 3 and removing the 0 1 uF capacitor connecting terminal 44 MIX OUT and terminal 42 IF1 IN If the BPF1 filter were installed jumpers JP1 2 and JP1 3 would be connected The default state for jumper JP1 is no connection Evaluation Board 2 43 Jumper Connections 2 14 JP2 Jumper JP2 is used for testing of the mixer circuit of the TRF6900 Testing of the mixer stage by itself is
11. and the Run Time Min which can be set in minutes For example if you want the test to run for five minutes set Run Time Min to 5 The PLL Modulation Options button brings up the PLL Modulation Options screen as shown in Figure 3 3 This button is activated only when the PLL is on 3 4 PLL Modulation Options Screen The PLL Modulation Options screen is accessed by pressing the PLL Modulation Option button located on the chip layout screen and is displayed as shown in Figure 3 3 Figure 3 3 PLL Modulation Options Screen DV6 Display Set to 1 by Double Clicking im PLL Modulation Options co C2 40 C 60 80 C 100 C 120 140 quency Register Dv Dv6 Dv4 Dv2 DV1 DVO b Pb P Modulation Mode 256 FSK 915 Fout TX Data Low MHz T 315 099975585938 99 9755859375 f4 Frequency 915 MHz fo Frequency 915 10 MHz Fout TX Data High FSK Deviation of 100 kHz lt basFo Clear Send Bits Button The PLL Modulations Options screen is divided into four sections Controls the acceleration factor for the PLL The values 0 20 40 60 80 100 120 and 140 Any changes are automatically updated in the PLL and MM Options section of the main program screen after pressing the Send Bits button located on the PLL screen g NPLL Controls the N Divider of the PLL The
12. see Figure 3 8 6 Press the Update CLK button on the main program screen 7 Observe that clock frequency is updated as shown in Figure 3 9 8 Pressing the Update CLK button twice causes the frequency offset to be cleared 3 12 Figure 8 8 Input of Frequency Error 900 2 8 File Edit Go Help Main Program Testing of Transmitter ES Synthesizer CLK 25 6 zm Desired Freq 515 0000 Actual Freq 915 000000 MHz Freq Error 0 004 MHz Update PLL and MM Options Clock Width 345 PLL APLL 140 RSSI NPLL ps Pwr Ampfo dB LIM MM Slicer IF Off EPT Bor Learn MIX LPT_x 1 Off LNA Output Parameters Enable TXData Off Mode Strobe Width 675 Operation Mode Mode 0 TXData Off Chip On Help TRF6900 Control Software Double Click HERE For a Chip layout Note demodulator is automatically enabled if the limiter and the LPF amplifier are enabled and the data switch is set to FSK reception Press Enter on Any Input to Send ALL Words Words ffporonori1011111000000000 Mode 0 B fori000 1101 111000000000 Mode 1 C fiortsioor00r111000000000 Mode 1 Difirorsiri1111111000000000_ Mode 0 Figure 3 9 Main Panel Display After Clock Offset Is Applied 6900 2 8 File Edit Go Help Main P
13. Manufacturing 1 CQ1_A DNP CX 1 SM Surface mount quartz CMAC Frequency crystal Products Distributor Part No CQ1 B ATS SM series Crystal CTS Reeves i Digi Key 4 CR1 CR2 CR4 MELF3 MINIMELF Fast switching diode Diode Inc LL4148 Digi Key LL4148BCT ND 1 CR5 SMB Rectifier Diode Inc S1JBT Digi Key S1HBDUCT ND TQFP48 Single chip transceiver Texas Instruments TRF6900A 1817 Sueg pieog 1 0 SO20WB Octal Buffers and line Instruments SN74LVT244BDW Digi Key drivers with 3 state outputs 296 1707 5 ND J1 J2 J3 J5 J6 SMA_H SMA brass connector Johnson Components 142 0701 801 Newark 90F2624 J7 horizontal PC mount E T E E he C een Bresawaynesders nue 51092390 Nowak 90F725 fa oes puse Murata h e wo Surace mountinductor 0000 tow 2 fee es Sulace mountinguctor h qu es Surace mountinductor hu 000 Surace mountinauctor 1 LED1 LDET LED S type Surface mount LED gull Panasonic LN1371SG TR Digi Key wing S type green P516CT ND 1 LED2 ENABLE LED S type Surface mount LED gull Panasonic LN1471SY TR Digi Key wing S type amber P517CT1 ND LED3 LED S type Surface mount LED gull Panasonic LN1271SR TR Digi Key wing S type red P490CT ND 5 __ D connector 7
14. NPLL can be set to either 256 or 512 Any changes are automatically updated in the NPLL box on the main program screen after pressing the Send Bits button located on the PLL screen 3 8 Testing of Transmitter Modulation Mode Allows the user to select FSK modulation Any changes are automatically updated in the MM box on the main program screen after pressing the Send Bits button located on the PLL screen FSK Frequency Register This section acts as a calculator and sets bits 20 13 of Word D to the user defined bits The bits of the FSK deviation register 0 7 0 0 can be set individually by double clicking inside each DVx box After setting all bits press the Send Bits button located on the PLL screen The bits of the frequency register will be mapped to Word D on the main program screen and highlighted in green Furthermore Fout TX Data High MHz Fout TX Data Low MHz frequencies and their difference Delta Fout kHz are calculated and displayed Press the Send Bits button located on the PLL Modulation Options screen to program the TRF6900 Press the Close button to return to the chip layout Screen 3 5 Testing of Transmitter To perform tests of the transmitter section of the TRF6900 perform the following steps Step 1 Test Setup Set up the test bench as shown in Figure 3 4 Figure 3 4 Block Diagram for Testing of the TRF6900 EVM Transmitter Section PC with TRF6900 software installed Frequenc
15. V Software User s Guide 3 21 3 22
16. accomplished by connecting JP1 1 to JP1 2 2 1 to 2 3 and removing the 0 1 capacitor connecting terminal 44 MIX_OUT and terminal 42 IF1_IN The IF mixer and LNA stages may be tested together by connecting JP1 1 to JP1 2 connecting JP2 2 to JP2 3 default and removing the 0 1 uF capacitor connecting terminal 44 MIX OUT and terminal 42 IF1 IN The LNA stage is tested by itself by connecting JP2 1 to JP2 2 The default state for jumper JP2 is JP2 2 to JP2 3 JP3 Jumper is used to observe the output of IF 1 the first IF amplifier by connecting JP3 1 to 2 The default configuration of JP3 2 to JP3 3 connects the output of the first IF amplifier to the input of the second IF amplifier JP4 Jumper JP4 is used to monitor RXDATA OUT when connected as JP4 2 to JP4 3 Jumper JP4 is used to monitor RSSI OUT when connected as JP4 1 to JP4 2 The default state for jumper JP4 is JP4 2 to JP4 3 JP5 Jumper JP5 is used to connect the VCO tank circuit to the loop filter of the PLL circuit The only reason to remove jumper JP5 is to test the tuning range of the VCO tank circuit with an external power supply The default state for jumper JP5 is JP5 1 to JP5 2 JP6 Jumper JP6 can be used to pull the MODE line up to VCC JP6 1 to 4 6 2 or pull down to ground JP6 2 to 6 3 if a computer connection is not installed The primary purpose for JP6 is as a test point to monitor th
17. box to turn the PLL on or off Turn on for transmit or receive VCO The VCO is always on Clicking has no effect Pwr Amp Use the arrow at the side of the box to select the desired power amplifier attenuation Software User s Guide 3 5 Main Program Screen Slicer SLCTL LPF DSW RSSI LIM IF MIX LNA Click inside the box to turn the data slicer on or off Click inside the box to select between Learn and Hold modes This will only work when the data slicer is on Click inside the box to turn LPF on or off Click inside the box to select between LIM and RSSI This changes the position of the data switch inside the TRF6900 The data switch selects between the output of RSSI and FM FSK demodulator LIM as the input to the LPF amplifier See block diagram in Figure 1 1 Click inside the box to turn RSSI on or off Click inside the box to turn LIM second IF amp limiter on or off Click inside the box to turn the first IF amplifier on or off Click inside the box to turn the RF mixer on or off Click the arrow beside the box to turn LNA off set to High Gain mode or set to Low Gain mode Output Parameters Enable TXData Mode Clock Width Strobe Width Click inside the box to turn the TRF6900 on or off Click inside the box to switch the TXData line between high or low Click inside the box to switch the mode line between 0 and 1 Type inside the box to increase or decrease the clock pulse
18. off 5 SLCTL If the data slicer is on this selects either the Learn or Hold mode for the data slicer 6 LPF Turns the low pass filter LPF on or off 7 DSW Data switch Selecting LIM sets LPF input to the demodulator Selecting RSSI sets the LPF inputto the RSSI 8 RSSI Turns the radio strength signal indicator RSSI on or off 9 LIM Turns the limiter LIM on or off 10 IF Turns the intermediate frequency IF amplifier on or off 11 MIX Turns the mixer on or off 12 LNA Allows the low noise amplifier LNA to be set to off low gain or high gain modes 3 2 3 Output Parameters This section allows the user to turn the TRF6900 Enable TXData and Mode control lines on and off When the mode control line is off Mode 0 is defaulted When the mode control line is on Mode 1 is defaulted Mode 0 initializes using Words A and D Mode 1 initializes using Words B and C Clock Width and Strobe Width allow the clock and strobe pulse widths to be increased or decreased 3 2 4 PLL and MM Options Allows the change of the APLL value 0 20 40 140 the NPLL value 256 512 and the modulation mode FSK 3 2 5 LPT Port Allows the user to change between the LPT1 and LPT2 ports of the controlling computer 3 4 3 2 6 Help 3 2 7 Words Main Program Screen Gives a brief description of each control box For example when the PLL box in the Mode Options section on the main program screen is clicked the Help box reads Phase
19. width this should not be changed during normal use Type inside the box to increase or decrease the strobe pulse width this should not be changed during normal use PLL and MM Options APLL NPLL MM LPT Port LPT_x 3 6 Use arrows on side of box to select between values of 0 20 40 60 80 100 120 and 140 Click inside of the box to change the divide by N value between 256 and 512 The value of PreScaler under Synthesizer changes when the NPLL value changes Modulation mode is fixed to FSK modulation mode Click inside the box to chose between PC parallel ports LPT 1 or LPT 2 Chip Layout Screen Help Help When any box on the main program screen is selected clicked inside of box with mouse the Help screen displays the valid selections for that box Double clicking inside the Help box causes the chip layout screen to be displayed as shown if Figure 3 2 3 3 Chip Layout Screen The chip layout screen can be accessed by double clicking on the left mouse button in the Help section of the main program screen The chip layout screen appears as a simplified internal schematic of the TRF6900 as shown in Figure 3 2 Figure 8 2 Chip Layout Screen Clicking Here Turns LNA On or Off or Select High Gain or Low Gain Mode Selecting Icon Turns Function On or Off Enable or Standby IC is Disabled in Standby nag Mode LHA High Gam Modi Dee i Clicking Here Sets F
20. 2 9 2 4 Serial Interface and PC Port Input 2 10 2 5 StandardiPC Parallel 2 11 2 67 Jumper Connections 2 12 27 Connectors and Test 2 15 2 1 Schematics 2 1 Schematics i X3 1 4 X3 ANN ar vey Gel Ud _ 92d We 0255 a a eed B 3901 91 e rd L0 LVZ LAWS Sf AON3nO3uJ 859 WE 104100 15 2 l W 0L 02 ANN 92 9 506 930 98 OL 07 c ANA Wdd0z dW3l avis 159 50 7HINS96 SV8 06 1603 5 Wdd 2 3ONVH3TOL Goors 928 2390007 20 ONINAL TWOIdAL UL SS wena WVINIWYANN eiu NINNL HOS 750 103138 4 H31N39 804 81193135 01 1301 As SEO 2 1031 T VAVZZZZAWNA 0 v 130001 A80 T T 10 ES _ dd 00 49 094 2 A ayo 5 SF oor L__ L ey 14 pus S o 4 x Q Sc e
21. 2 to test the mixer and LNA circuits of the TRF6900 J3 IF OUT IF OUT is an SMA female connector used with jumper JP3 to monitor the IF output circuit of the TRF6900 J4 RX IN RX IN is an SMA female connector which is connected to the input of the LNA The LNA is the input to the receiver section of the TRF6900 J5 TX OUT TX OUTis an SMA female connector which is connected to the transmit ter output of the TRF6900 J6 RSSI RXDATA OUT RSSI RXDATA OUT is an SMA female connector used with jumper JP4 to monitor the RXDATA output or RSSI output of the TRF6900 J7 VCO TANK VCO TANK is an SMA female connector used with resistors R22 R24 R25 R26 and capacitor C31 to directly feed in an external VCO signal Resistors R22 R24 R25 and R26 are used to form a 7 attenuator The components for this option are not installed on the EVM TP1 Test point TP1 is used to monitor the tuning voltage applied to the VCO circuit by the PLL circuit AMP OUT TP The AMP OUT test point is used to monitor the output of the LPF amplifier post detection amplifier LDET TP The LDET test point is used to monitor the lock detect line of the TRF6900 Evaluation Board 2 15 Connectors and Test Points 2 7 3 Adjustments RSSI TP The RSSI test point is used to monitor the RSSI level from IC1 33 RSSI OUT RXDATA TP RXDATA test point is used to monitor the RXDATA from IC1 28 DATA OUT This is the demodulated signal MODE TP The M
22. 45783 4 EC RN EC RN MN Q2 NPN silicon planar Zetex FMMT2222A switching transistor 330 mW 87 815 R19 R21 10 S R30 R32 R35 R36 R39 R41 2 o3 R18 R27 R28 R29 100 0603 R38 R34 R43 R45 0603 R47 1817 8 pieog P1S Panasonic oe mount trimmer EMEN potentiometer V2 80 E ea tuning Alpha Industries Inc SMV1247 079 poe 0 CADES369A 13 Three terminal adjustable ON Semiconductor LM317MDT 06F9320 output positive voltage regulator SO6NB Three terminal adjustable ON Semiconductor LM317LBD Newark 06F9304 output positive voltage regulator SMBK BI Transient voltage Vishay Liteon SMBJ8 5CA Digi Ec suppressor Ec ND _ CLOCK PC test point Color coded PC test point Components Corp Newark DATA F_TXDATA any color LDET MODE RSSI RXDATA STDY STROBE TXDATA Color coded PC test point Components Corp TP 105 01 00 Newark 97B3259 black Color coded PC test point Components Corp TP 105 01 02 Newark 97B3257 red TP2 TP6 itl SMD test point Surface mount test point Components Corp TP 107 01 Newark 97B2647 1817 EVM DC Voltage Setup 2 3 EVM DC Voltage Setup The evaluation board should be used with a dc power supply voltage of 8 V nominal Figure 2 1 details the dc voltage supply setup for the TRF6900 EVM Figure 2 1 TRF6900 EVM DC Voltage Setup Vout
23. 48 5 INSTRUMENTS TRF6900 Evaluation Board User s Guide May 2001 Mixed Signal RF Products SWRUOO1C EVALUATION BOARD DISCLAIMER The enclosed evaluation boards are experimental printed circuit boards and are therefore only intended for device evaluation We would like to draw your attention to the fact that these boards have been processed through one or more of Texas Instruments external subcontractors which have not been pro duction qualified Device parameters measured using these boards are not representative of any final data sheet or of a final production version Texas Instruments does not represent or guarantee that a final version will be made available after device evaluation THE EVALUATION BOARDS ARE SUPPLIED WITHOUT WARRANTY OF ANY KIND EX PRESSED IMPLIED OR STATUTORY INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE TEXAS INSTRUMENTS ACCEPTS NO LIABILITY WHATSOEVER ARISING AS A RESULT OF THE USE OF THESE BOARDS The fee associated with the evaluation modules EVM is a partial nonrecurring engineering fee NRE to partially defray the engineering costs associated with the EVM development and applications support for the RF integrated semiconductor product The EVM is a tool for evaluating the RF semiconductors supplied by Texas Instruments The EVM is supplied to prospective component customers to provide services and software allowing t
24. 8132 1 2154 1A8 1Y3H B 1A4 1Y4 TX DATA FILTER e 8 20 TXDATA 15 20113 TXDATA gt 18 2 2 2 217 lt 834 19243 2 3 5 lt 2200 RSSI OUT lt 10 STDBY lt R35 SN74LVT244BDW gt R36 7 NY lt o ioko Ny FMMT2222ATA RSSI 5 1202 ENABLE RXD MODE LN1471SY TR lt R37 51000 8 6 8 2 gt oly STDBY Y lt R38 gt 100 2 Lf 8 JP7 8 1 5 2 4 DATA 114148 lt S10k2 gt 10ka INO pue 5 2 5 Standard PC Parallel Port Standard PC Parallel Port A standard PC parallel port is configured as follows 1 13 14 25 Pin Description 1 Strobe 2 Data 0 3 Data 1 4 Data 2 5 Data 3 6 Data 4 7 Data 5 8 Data 6 9 Data 7 10 ACK 11 Busy 12 Paper Empty 13 Select 14 Auto Feed 15 Error 16 Initialize Printer 17 Select Input View Is Looking at Connector Side of DB 25 Male Connector PC Output PC Output PC Output PC Output PC Output PC Output PC Output PC Output PC Output PC Input PC Input PC Input PC Input PC Output PC Input PC Output PC Output Pin Assignments Note 8 Data Outputs 4 Misc Other Outputs 5 Data Inputs Note Pins 18 25 Are Ground Note
25. 900 Block Diagram ia 1 TRF6900 EVM DC Voltage Setup cee eee eee ees TRF6900 EVM Serial Interface eee en EVM Jumper Locations and Default Configuration of the EVM Main ise Chip Layout Screen ened eens PLL Modulation Options 5 Block Diagram for Testing of the TRF6900 EVM Transmitter Section Main Program Screen eph URS Chip Layout Screen hn Spectrum Analyzer 2 helped ai genie Input of Frequency Error cece 0 Main Panel Display After Clock Offset Is Applied PLL Modulation Options View ssssssssssseee II PLL Modulation Options 5 FSK Output From Transmitter ete eens Block Diagram for Testing of the TRF6900 EVM Transmitter Section With an External Pulse Generator 0 FSK Output From Transmitter With an External Modulation Test Setup for TRF6900 Receiver Testing Main Program Screen
26. K test Setup the spectrum analyzer to observe the spectrum analyzer display as shown in Figure 3 12 Software User s Guide 3 15 Testing of Transmitter Figure 3 12 FSK Output From Transmitter Marker 1 1 RBW 30 kHz RF Att 40 dB Ref Lvl 4 15 dBm VBW 300 Hz 10 dBm 915 00000000 MHz SWT 2 8 Unit dBm 1SA 114 Center 915 MHz 100 kHz Span 1 MHz Date 21 JAN 00 17 04 57 Note This is FSK modulation with f4 equal to 915 0 MHz fo equal to 915 10 MHz and 100 Hz data rate The f4 frequency is the 0 frequency The fo frequency is the 1 frequency Figure 3 13 Block Diagram for Testing of the TRF6900 EVM Transmitter Section With an External Pulse Generator PC With TRF6900 Software Installed PC Printer LPT1 or LPT2 Cable DB25M to DB25F TRF6900 Evaluation Spectrum Analyzer Board 2 TXDATA TP gt GND TP Coaxial Cable With Clip Lead Ends Pulse Generator Output Waveform 3 16 Testing of Transmitter To use an external pulse generator to supply transmit data set up the test bench as shown in Figure 3 13 Perform the FSK modulation output test as described in the previous section In this new setup an external pulse generator provides the modulation The FSK Testbutton on the chip layout screen does not need to be pressed to start the FSK test Figure 3 14 FSK Output From Transmitter With an External Modulation Delta 1 T1 RBW 30 kH
27. Lock Loop 0 Off 1 On Valid in Mode 0 or 1 Most of the other control boxes follow this format The first line indicates what portion of the TRF6900 is being controlled The next two lines indicate the bit value If the PLL is off bit 12 of Words C and D are equal to 0 If itis on bit 12 is equal to 1 The last line indicates this control works in both Mode 0 and Mode 1 Double clicking in the Help box on the main program screen activates the chip layout screen This section updates the binary words after changes are made to the control options Clicking on the box next to the word individually sends each word Clicking on the Send Words Now F12 button on the main program screen or pressing F12 on the keyboard sends all the words to the TRF6900 3 2 8 Operation Mode Operation Mode shows whether the TRF6900 is enabled which mode 0 or 1 is selected and whether the transmit TX data line is on or off 3 2 9 Changing Values on the Main Program Screen Synthesizer Section CLK Type the desired clock frequency inside the box or use the arrows located at the right side of the box Desired Freq the desired transmit or LO receive frequency inside the box or use the arrows located at the right side of the box PreScaler Click inside the box to change divide by N value between 256 and 512 The value of NPLL under PLL and MM Options changes when the PreScaler value changes Mode Options PLL Click inside the
28. ODE test point is used to monitor the MODE line STDBY TP The STDBY test point is used to monitor the STDBY line CLOCK TP The CLOCK test point is used to monitor the CLOCK signal from the PC DATA TP The DATA test point is used to monitor the DATA signal from the PC STROBE TP The STROBE test point is used to monitor the STROBE signal from the PC TXDATA TP The TXDATA test point is used to monitor the transmitted data Transmit data from an external source can also be applied at this point Resistor R44 is varied to adjust the VCC1 voltage applied to IC1 TRF6900 2 7 4 LED Indicators 2 16 VCC LED If JP8 is installed the VCC LED is illuminated when voltage is applied to IC1 LDET LED The LDET LED is illuminated when the lock detect line IC1 11 TRF6900 is high indicating that the PLL circuit is locked ENABLE LED The ENABLE LED is illuminated when the STDBY line from computer is in the high state 3 Software User s Guide This chapter describes the Windows based software application that accompanies the EVM Topic Page 1 E Ie 3 2 3 2 Main ProgramiScreen EE cies epee lees eee 3 3 eee Screen 3 7 3 4 PLL Modulation Options 3 8 3 9 3 6 Testing of the Receiver 3 18 3 1 Introduct
29. The TRF6900 Press to Select Learning or Hold Modes 3 6 3 Learning and Hold Modes 3 20 During the Learning Mode the data slicer is constantly integrating the incoming signal and charging capacitor C25 see schematic diagram to a dc voltage level that is proportional to the average demodulation dc level Capacitor C25 is connected to terminal 29 of the TRF6900 S amp H CA terminal During the Hold Mode the data slicer stops integrating and uses the dc voltage level stored on capacitor C25 as the decision threshold between a logic 1 and logic 0 as measured on terminal 28 DATA OUT For receiver measurements the output of terminal 28 DATA OUT is measured at the RXDATA test point Testing of the Receiver 3 6 4 Measured Receive Data The data plots in Figure 3 18 and Figure 3 19 show the measured receive data at the AMP_OUT and RXDATA test points for input signals at 50 dBm and 90 dBm respectively Figure 3 18 Measured Data With 50 dBm Input Signal at OUT and RXDATA Test Points AMP OUT Test Point RXDATA v MC RE Test Point C2 Freq 10 000 2 Low signal plitude Figure 3 19 Measured Data With 90 dBm Input Signal at OUT and RXDATA Test Points AMP OUT _ Test Point s Low signal EA Law signal RXDATA qu Test Point 4 2 10 039 2 Low signal plitude 60V WE 1 00v 2 00V M20 0gs Chi i 64
30. ame Power Amp Select Icon to Change Attenuation 0 dB 9 Position of Data Switch Posing 0 36 10 dB 20 dB or Turn the Power zu Between RSSI FSK DEMOD Amp Off Selecting Icon Turns phon LEF OM CHI T LPF Video Amp PLL Tepe OFF On or Off 1 F3K Selecting Icon Turns ae Data Slicer On or Off ome gt si ae M Dea Data Slicer Must be 8 V Run Tire More to Select Between wen OM Learning and Hold Modes Mode Select 0 or 1 SES Press to Select Learning or Hold Mode Turn TX Data On or Off Press to Program the TRF6900 Press to Select PLL Modulation Options Screen Note PLL Must be On Press to Start FSK Test The 12 Mode Options e g the PLL VCO LNA etc are controlled from the chip layout screen as well as the main program screen Changes made in either the main program screen or the chip layout screen simultaneously update both screens The user can also control the chip enable TXData and mode control lines from the chip layout screen Software User s Guide 3 7 PLL Modulation Options Screen Theusercan select FSK Modulation The FSK Test button located on the chip layout screen allows the user to transmit data using the TRF6900 Options for use with the FSK Test button are the pulse repetition frequency PRF which is defaulted to 100 Hz
31. e state of the MODE line The default state for jumper JP6 is not con nected JP7 Jumper JP7 can be used to pull the STDBY line up to VCC JP7 1 to 4 7 2 or pull down to ground JP7 2 to JP7 3 if a computer connection is not installed The primary purpose for JP7 is as a test point to monitor the state of the STDBY line The default state for jumper JP7 is not con nected JP8 Jumper JP8 is used to connect the Power On LED to the output of the IC1 voltage regulator The default state for jumper is JP8 1 to JP8 2 BPF1 Bypass Capacitor A 0 1 uF capacitor is used to bypass BPF1 and connect the mixer output directly to the first IF amplifier BPF1 is notinstalled on the TRF6900 evaluation board If the user requires BPF1 to be installed then remove the capacitor C3 connecting terminal 44 MIX OUT and terminal 42 IF1 IN and connect JP1 2 to 1 3 Connectors and Test Points 2 7 Connectors and Test Points The following are descriptions of the TRF6900 EVM connectors and test points 271 Connectors 2 7 2 Test Points TP 1 P1 is the PC parallel port interface and is a male DB25 connector 1 is connected to the LPT1 or LPT2 port of the computer on which the TRF6900 software is running J1 MIX OUT MIX OUT is an SMA female connector used with jumpers JP1 and JP2 to test the mixer circuit of the TRF6900 J2 LNA OUT MIX IN LNA OUT MIX IN is an SMA female connector used with jumpers JP1 and JP
32. for LM317 voltage regulator is equal to Vout 1 25 1 R44 R43 V at terminal 3 of LM317 should be 2 V to 3 V higher than Vout With V jnequal to 8 V Mee Connect JP8 For Power POWER ON LED 8 0V VRI RED 5 LM317MDT 2 2 3 6V 3 0V TYP T 1 t t t S1JB 791 041 c42 2 c45 M 8 8 5 1087 1 1 2200 JotuF 0 01 F 9 B 1 EI LEDs W vec 2 lt Rag LN1271R TR 2 5000 R45 Vin is equal to 8 V vl min to 10 V max VVV 2200 A Vagj Used to Change Vout From 2 2 V to 3 6 V ifv 8 33V vo vol VCC2 2 ADJ NC lt i 2200 C46 C47 C48 LM317LBD 1 0 0 011 F R48 3600 Evaluation Board 2 9 01 0 pieog 2 4 Serial Interface and PC Port Pin Out Figure 2 2 details the serial interface portion of the TRF6900 EVM Figure 2 2 TRF6900 EVM Serial Interface 1 2 Clock Input from PC P1 3 Data Input from PC P1 4 Strobe Input from PC P1 5 TX Data from PC 1 6 Enable from PC P1 7 Mode from PC 11 RSSI Out to PC P1 12 RX Data to PC AMP OUT Y m AMP OUT 5 CLOCK c39 T DATA STROBE IC2 20 t 1 lt R30 lt R31 10E S10kQ lt 18 lt lt lt 2 1 1H
33. he prospect customers to evaluate the RF semiconductors in products they would build The EVM may be operated only for product evaluation purposes and then only in nonresiden tial areas Tl s understanding is that the customers products using the RF parts listed shall be designed to comply with all applicable FCC and appropriate regulatory agency requirements and will upon testing comply with these requirements Operation of this device is subject to the conditions that it not cause harmful interference and that it must accept any interference IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its products to the specifications applicable at the time of sale in accordance with standard warranty Testing and other quality control techniques are utilized to the extent Tl deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requiremen
34. ide Silkscreen and Drawing 2 1 1 E WA 0069441 SINANNYLSNI SVX3L E a ilg 1 1 an 2 4 Top Side Silkscreen and Drawing 2 1 2 Bottom Side Silkscreen and Drawing Evaluation Board 2 5 9 2 pieog 2 2 Parts List C3 C4 10 13 C19 C25 C27 C35 C39 C42 C44 C47 ice C43 C46 1208 tantalum Tantalum capacitor Newark 95F9901 C9 pem L ho es rater eso ___ ____ _____ _______ asse ow SSCS SSCS fee aree S 3 fora cre mom uos os __ ______ oss 3 fes Res ous 3 s ow 1 C15 DNP 0603 Surface mount ceramic Temex AT0300 trimmer capacitor 1 CQ1 26 MHz HC45 U gull wing Resistance weld miniature International Crystal 865850 crystal
35. ion 3 1 3 2 Introduction A Windows based software application accompanies the evaluation board The software is intended for use in either a Windows 95 98 or Windows NT environment If the Windows NT environment is used the Windows NT driver software must accompany the software However if the operating system is Windows 95 98 the software application can run on its own Both the Windows NT Driver and the TRF6900 software are provided on diskette Your system administrator must install the Windows NT Driver if you do not have administrative privileges on your computer The TRF6900 software can run from the floppy disk by following these steps 1 Click on the Start button on the desktop 2 Click on the Run button 3 AA TRF6900 exe and press Main Program Screen 3 2 Main Program Screen The screen shown in Figure 3 1 appears on your monitor Figure 3 1 Main Program Screen Transmit Frequency for Transmit Mode or LO Frequency for Receive Mode Crystal or Clock Double Click Here With the Frequency Left Mouse Button to Obtain Chip Layout View Hain Program 1 1 Edi Gp Synthesizer Desired 205 000000 Mir 3 Actual Fre 15 000000 MHz Conia Software Double Chek FERE For Chip Presei at Error Ha m Norge FAFE demodulator is Pode natans PUL and Options automatically enabled the miter and
36. n unfair and deceptive business practice and TI is not responsible nor liable for any such use Also see Standard Terms and Conditions of Sale for Semiconductor Products www ti com sc docs stdterms htm Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2001 Texas Instruments Incorporated Preface Read This First About This Manual This document is intended to introduce the TRF6900 evaluation module EVM and familiarize the reader with setting up and testing the TRF6900 EVM using the evaluation software in a typical laboratory environment How to Use This Manual This document contains the following chapters Chapter 1 Overview Chapter 2 Evaluation Board Chapter3 Software User s Guide Information About Cautions and Warnings This user s guide may contain cautions and warnings This is an example of a caution statement A caution statement describes a situation that could potentially damage your software or equipment This is an example of a warning statement A warning statement describes a situation that could potentially cause harm to you The information in a caution or a warning is provided for your protection Please read each caution and warning carefully 1 Contents Ove ivi Wii a a cg cea cae S ceed ei ata LE mete Ed 1 1 1 1 CE 1 2 122 sete cetus tetra
37. oftware _______ 1 3 Block Diagram Block Diagram Figure 1 1 shows the block diagram for the TRF6900 Figure 1 1 TRF6900 Block Diagram 529 z 5 5 x x 2 25 gt gt gt 46 45 44 RF Buffer Amplifier RE Mixer 22 LNA_GND 4 LO Buffer PA_VCC Amplifier 5 PA_OUT 6 Power Amplifier PA I PLL A PD_SET PD_OUT2 PD_OUT1 LOCKDET DDS_GND VCO_TANK1 MODE a a z 5 2 2 x 40 58 E E w 6 SE 42 44 aoj 39 36 Second DEM IF Amplifier 5 Limiter DEM TANK irs Amplifier RSSI FM FSK Demodulator DEM TANK 33 RSSI OUT Data Switch 4 Buffer d Amplifier 32 AMP IN LPF Amplifier 31 Postdetection TRF6900 Amplifier 30 AMP_OUT 29 Data Slicer S amp H CA 28 DATA OUT DATA Direct Digital Synthesizer Power Down ldg ower Down Logic j CLOCK STROBE O lt a 2 2 gt a gt 9 id oO K Overview 1 3 1 4 Chapter 2 Evaluation Board This chapter describes the EVM and its operation Topic Page 21 Schematics eerie enm eie 2 2 2 2 51 10 02115010 01051051 1 01 10 10 01 08 05 2 6 23 EVM DC Voltage Setup cee een See neve
38. re re quired to demonstrate the TRF6900 Complete the following steps to set up the TRF6900 for evaluation Step 1 Place the 3 5 inch diskette into the floppy disk drive of the computer being used to evaluate the TRF6900 Step 2 Copy the TRF6900 exe file to the hard drive Step 3 Connect a DB25 female to DB25 male cable between the TRF6900 evaluation board and the PC parallel port The DB25 female end of the cable is connected to the TRF6900 The DB25 male end of the cable is connected to the desired LPT port of the PC LPT1 or LPT2 Step 4 Connect a dc power supply capable of 10 V 200 mA between the red power supply pin and ground on the TRF6900 evaluation board Step 5 Verify that the power supply output is set to 8 V Step 6 Turn the power supply on Step 7 Ifjumperat JP8 is installed verify that LED3 the red power on LED is illuminated Step 8 Run the TRF6900 exe file on the PC Step 9 Press the Send Words Now F12 button on the program screen Step 10 Verify that LED1 the green lock detect LED is illuminated When the lock detect LED is illuminated the PLL is locked on frequency Note The actual icons windows on the computer screen may differ from those shown in this user s guide due to software version upgrades The schematics shown in this user s guide may not match the current revi sion due to PCB and component upgrades Always check the TI website for the latest schematics and s
39. rogram Synthesizer j CLK 25 599888 PreScaler 256 Desired 915 000 Actual Freq 914 999878 MHz Freq Error MHz 2 Clock Width 345 Mode Options jrPLL and MM Options PLL on DSW APLL 140 RSSI NPLL ps Pwr dB Fx Slicer off IF Off LPT Port SLCTL MIX LPT_x 1 LPF OFF v Output Parameters 9 Enable TXData JOFF Mode Strobe Width 675 Operation Mode Mode 0 _ TXData Off Chip On Help TRF6900 Control Software Double Click HERE for Chip layout Note demodulator is automatically enabled if the limiter and the LPF amplifier are enabled and the data switch is set to FSK reception Press Enter on Any Input to Send ALL _ 601000111011111000001010 Mode 0 ffo11000111011111000000000 Mode 1 1 101111001001111000000000 Mode 1 1111111111000000000 Mode 0 Software User s Guide 3 13 Testing of Transmitter Step 4 FSK Modulation Output Test On the chip layout screen press the PLL Modulation Options button The PLL Modulation Options View Is Set Up as Shown in Figure 3 10 Figure 3 10 PLL Modulation Options View OFF 4 gt mM PAKEMON E E 1 Amp OFF
40. t ely OX 6 819 HLON31 T lt 9c PER AAA NOISSIASNVH L US 12 OF Zi ug IR you S20 vio 5 REE c1no XL wivaxwissy Z 2 3800 82 6 VAF Ades Y A e 100 VlVOXH SSH var 229 62 Sr doce 0 0068481 Dd Qu at end 9P L NMOHS SV 420 985 101 5 v 24000 820 39000 HLGIMQNVS 135 220 120 6d 5 619 7 2 1no 18858 Y d p I pn 91 5 4000 T CoNEXH aNd L 00 L 401s HW 910 or 19 95482 _ WOIdAL be be be by bv Ev 001 199A 9u ASZ 1 E O1 V HWZL 0LAO33S 2 HOS i 09 vd 2 051 i c SPINZ 0LADSSS doi 1 69 HZZ T Jdozi 1 440001 o 1 ANdNI alz 1nO 3l O LANI 412100 4901 er 82 29 EN J T9NO ari ro Hues E 99 A d et NI XIIN LRO YNI C NI XIW LnO vo 5 50 0S LEME SPINL OLND34S 1399 T 7 1 XIN ONANI XIN 2 2 Schematics 11111 vos lt Sru gt vdi 241 31100 anro gt 870 170 go 9082 avd 2 ray 4 4 i H
41. ts Customers are responsible for their applications using Tl components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such products or services might be or are used TI s publication of information regarding any third party s products or services does not constitute approval license warranty or endorsement thereof Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service is an unfair and deceptive business practice and TI is not responsible nor liable for any such use Resale of products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service is a
42. y Counter Spectrum Analyzer PC Printer port LPT1 or LPT2 Coupled Port 4 Cable DB25M to DB25F Directional TRF6900 Coupler Evaluation Board Software User s Guide 3 9 Testing of Transmitter Step 2 Software Programming For testing the TRF6900 transmitter section set the main program screen and the chip layout screen as shown in Figure 3 5 and Figure 3 6 Figure 3 5 Main Program Screen Double Clicking Here With Left Mouse Transmit Frequency Button to Obtain Chip Layout View Main M Bel fie Go Synthesiar Desred Freq TRF SOD Contfol Software PreScaler 755 22 Double Click MERE For s Chip laur More FRIRE demodulator is PLL and Options automaticaly enasied the miter snd the are enabled Gui 40 data patch is set ba Pres Enbar Any Deut ke Send ALL TN E p 3 10 Testing of Transmitter Chip Layout Screen of TRF6900 Software for Transmitter Testing Figure 3 6 Chip Layout Screen OFF ao OFF 1 amp Clicking Here Sets OFF o Ae FSKDEMOD Power Amp Attenuation F Amp OFF m 0 dB 10 dB 20 dB or Boo OFF Turn the Power Amp Off Pue 008 Allanaalicn 18 Dpr Enabw ON
43. z RF Att 30 dB Ref Lvl 0 03 dB VBW 300 kHz Mixer 20 dBm 10 dBm 100 20040080 kHz SWT 2s Unit dBm Span 1 MHz Center 915 MHz 100 kHzv Date 27 JAN 00 13 11 00 Note This is FSK modulation with f4 equal to 915 0 MHz fo equal to 915 10 MHz and 1000 Hz data rate The f4 frequency is the 0 frequency The fo frequency is the 1 frequency Software User s Guide 3 17 Testing of the Receiver 3 6 Testing of the Receiver Figure 3 15 Test Setup for TRF6900 Receiver Testing Pulse External Modulation Input Generator Signal Generator Pulse Generator Output Waveform 10 kHz Power Supply Voltage 8 V Cable DB25M to DB25F _ RSSI TP PC With TRFe900 PX IN TRF6900 Software Evaluation Installed Board PC Printer Port LPT1 or LPT2 AMP_OUT TP RXDATA TP CIN Channel 1 Channel 2 Oscilloscope 3 6 1 Test Equipment Setup Set the external signal generator and oscilloscope according to the following Signal Generator Oscilloscope Center frequency 915 000 MHz Channel Volts Division Time Division FM frequency deviation from carrier 50 kHz 1 1 20 us External modulation input 10 kHz 2 2 20 us 3 18 Testing of the Receiver 3 6 2 Software Programming for Receiver Testing Set up the main program screen and the chip layout screen as shown in Figure 3 16 and Figure 3 17 Figure 3 16 Main Program Screen Transmit Frequency for Transmit Mode or LO Frequency for Receive Mode imi
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