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Xilinx PlanAhead User Guide

1. BUFIODQS_XO BUFIODQS_X1 BUFIODQS_X2 GTXE1_XOYS BUFIODQS_X0 BUFIODQS_X1 BUFGCTRL_XO 29 BUFIODQS_X2 BUFIODQS_X0 BUFIODQS_X1 BUFGCTRL_XO 28 BUFIODQS_X2 BUFIODQS_X1 BUFGCTRL_XO 27 BUFIODQS_X2 Wi azo sr BUFGCTRL_XOY26 TREAT 4 BUFGCTRL_XOY25 SaR All ia BUFGCTRL_X0Y24 AI SiS BUFGCTRL_XOY23 AAIR oi BUFGCTRL_XOY22 AD MR E19 MR BUFGCTRL_XOY21 AE7 MR REFCLKIP A21 5R BUFGCTRL_XOY20 AF11 5R REFCLK BUFGCTRL_XOY19 E BUFGCTRL_X0Y18 E BUFGCTRL_XOY17 BUFGCTRL_XOY16 A22 SR AG11 5R AF10 GC AE10 GC AH11 GC AG12 GC N3 RXP2 E T REFCLKOP E TS REFCLK E T2 TXN1 E R4 RXN1 E T1 TXP1 E R3 RXP1 E 2 TXNO E U4 RXNO E 1 TXPO E U3 RXPO Bottom Half Clock Region xOVO GT Bank 114 BUFGCTRL_xO 15 Site Instance n E BUFGCTRL_xov14 E BUFR _X2Y1 GTXE1_XOY3 BUFR_XOYO E BUFGCTRL_xOv13 E BUFR_x2Y0 E GTXE1_x0Y2 BUFIODQS_X0 E BUFGCTRL_X0Y12 E BUFIODQS_X2 E GTXE1_x0Y1 BUFIODQS_X0 E BUFGCTRL_xOv11 E BUFIODQS_X2 E GTxE1_xovo BUFIODQS_X0 E BUFGCTRL_X0Y10 E BUFIODQS_X2 E Y2 TXN3 BUFIODQS_X0 E BUFGCTRL_X0Y9 E BUFIODQS_X2 E AC4 RXN3 BUFGCTRL_xOv8 E Y1 TXP3 BUFGCTRL_XOY7 E AC3 RXP3 i BUFGCTRL_XO
2. i BEIEIEIEIEIEIEIEIEIEIEIEIKR JAHANARA JAK E3 ok ju Figure 4 47 Package View Layers The available layers are listed hierarchically in a tree view which can be expanded or collapsed In the Package view the three primary categories of layers are I O Ports Pins and I O Banks The 7 series FPGAs offer both high performance HP and high range HR I O banks HP and HR I O banks of Virtex 7 Kintex 7 and Artix 7 devices are highlighted in the Package view I O Ports shows the ports in the design that are currently placed in either a fixed or unfixed state The design might have currently unplaced ports that are not displayed in the Package view Pins includes the available package pins grouped into specific categories such as multifunction pins power pins and unconnected pins Multifunction pins display with symbols representing their available functions For example e Clock capable pins display as blue hexagrams e Vref pins display with a small power icon The Layers Slideout provides a legend of the icons used for multifunction pins PlanAhead User Guide www xilinx com 135 UG632 v13 4 January 18 2012 136 Chapter 4 Using the Viewing Environment XILINX e I O Banks show the sites of the pins for each of the I O banks on the device as well as the sites of the GTX pins Each I O bank and GT bank is color coded to allow you to easily differentiate the
3. Ee ee EE Ee ee Ee Clit ict LL iL je es EE EE EE 333 w or Schematic view You can also select multiple instances and drag and drop them to new locations at the same time www xilinx com Figure 10 24 Dual Zoomed Device Views The primitive instance is assigned to the new site You can display net flight lines from Select Tools gt Options and select the Themes from the menu on the left then select the the instance to connected placed logic or Pblocks Device tab The Device tab displays various configurable elements of the Device view Select a placed instance in the Device view Netlist vie You can use the Device view Layers control to display or hide the location constraints See Color columns Setting Visible Device View Layers page 131 for more information 2 Change settings in the Select column or adjust the colors in the Frame Color and Fill Fixed and unfixed placement instances have individual color and selection controls To adjust other display characteristics for the LOC and BEL constraints 2 Drag and drop the selected instance or instances to another legal site To move placed instances 1 Moving Placed Instances gt Project Summary X wb_conmax_pri_dec v_X Device 2 x Fle te Cl DSi HA Mee 4 VA UG632 v13 4 January 18 2012 PlanAhead User Guide Chapter 10 Floorplanning the Design g XILINX Moving a combinati
4. Figure 11 18 Metric Results View Configuring the Metric Ranges Within the Metric Properties view you can configure the bin ranges for each metric map Colors and the range display are adjustable You can add or delete new bins to define ranges To do so select Apply changes in the Metric Properties view or select Apply Changes from the popup menu To insert a new range bin select the bin you want to split and select Insert Bin from the right click popup menu Figure 11 19 allows the definition of the range and color Insert Bin Enter bin range between 0 and co From lo New bin color 255 255 0 v Cancel Figure 11 19 Insert Bin Dialog Box The ranges of existing bins are adjusted to accommodate the newly defined range 360 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Performing Timing Simulation Performing Timing Simulation To perform timing simulation on the implemented FPGA design the PlanAhead tool first invokes the NetGen utility to convert the internal database to a Verilog or VHDL netlist NetGen is a command line executable that reads Xilinx design files as input and generates a Verilog or VHDL netlist that can be used with third party simulators and timing analysis tools For more information on running NetGen see the Command Line Tools User Guide UG628 as cited in Appendix E Additional Resources The PlanAhead tool is integrat
5. Rule Name Rule Abbrev Rule Intent Severity Bank I O BIVC IOSTANDARD based VOUT voltage compatibility check for IOs in Error Standard Vcc that bank Bank I O BIVB Checks that the I O Standard is supported in the I O bank Error Standard Support Bank I O BIVT IOSTANDARD based DCI Termination voltage compatibility check Error standard for IOs in that bank Termination Bank I O BIVR IOSTANDARD based VREF voltage compatibility check for I Os in Error Standard VREF that bank Bank I O BIVRU Checks for an available VREF site in I O banks which implement Warning Standard VREF I O Standards requiring a VREF Utilization Bank I O BIIVRC Checks for a conflict between the I O standards of a Bank and an Warning Standard INTERNAL_VREF constraint on the bank Standards in a bank cannot require a VREF voltage that differs from that specified by an INTERNAL_VREF constraint for the bank 428 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX I O Port and Clock Logic and Placement DRC Rule Descriptions Table B 18 Bank I O Standard DRCs Cont d UG632 v13 4 January 18 2012 Rule Name Rule Abbrev Rule Intent Severity Bank I O BISLIM Checks the I O placed within an I O bank against Simultaneous Error Simultaneous Switching Noise SSN Output Switching Output Limits Bank I O DCIP There are dedicated VRP and VRN I O sites in I O banks which
6. 15S_RECONFIGURABLE lines General Pins Attributes Connectivity Se e e a a 6 Project Status Bar l TA Main Viewing Area Figure 4 2 The Main Viewing Area Shows project status and the actively running commands You can cancel Synthesis Implementation and Generate Bitstream commands from this area PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 93 Chapter 4 Using the Viewing Environment XILINX 7 Tcl Console and Messages Area Shows Tcl command status application messages compilation results reports and access to design runs See Using the Tcl Console and Messages Area page 97 for more information 8 Information Bar Displays information about the open project and any objects currently beneath the cursor Using the Main Viewing Area Each window or view has a set of banner controls to minimize or maximize the window float the window as separate from other views or close the window altogether These controls are located in the upper right corner of the window as in Figure 4 3 Float Close Maximize Minimize iming Score Unrouted Description Based on Area Rec Figure 4 3 Window Controls The following subsections describe these commands in greater detail Using View Banner Controls You can expand a view to use the all of the viewing environment by clicking Maximize in the upper right of the view The PlanAhead tool minimizes all other open
7. but the actual last element of the list is still correct in the Tcl variable Object Relationships PlanAhead User Guide Related objects can be queried using the of option to the relevant get__ command For example to get a list of pins connected to a cell object do the following get_pins of get_cells inst_1 Figure 14 2 is a diagram of the object types in the PlanAhead tool and their relationship where an arrow from one object to another object indicates that you can use the of option to the get__ command to traverse logical connectivity and get Tcl references to any connected object www xilinx com 399 UG632 v13 4 January 18 2012 Chapter 14 Tcl and Batch Scripting XILINX Figure 14 2 PlanAhead Object Relationships Errors Warnings Critical Warnings and Info Messages Messages that result from individual commands appear in the log file as well as in the GUI console if it is active These messages are generally numbered to identify specific issues and are prefixed in the log file with INFO WARNING CRITICAL_WARNING ERROR followed by a subsystem identifier and a unique number The following is an example of an INFO message that appears after reading the timing library INFO HD LIB 1 Done reading timing library These messages make it easier to search for specific issues in the log file to help to understand the context of operations during command execution
8. fi Run Noise Analysis Properties S Report Timing cing Slack Histogram 2 Set up ChipScope gt 55 5 Al Violations 224 a S DSP48 224 Implement Be 5 DSP output pipelining DPOF a DPOP 1 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul Implemented Design DPOP 2 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul DPOP 3 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul DPOP 4 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul DPOP 5 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul Program and Debug DPOP 6 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul DPOP 7 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul DPOP 8 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul DPOP 9 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul DPOP 10 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul DPOP 11 Warning DSP
9. s UP 5 nunm Figure 8 21 Placing I O Ports in I O Banks 1 2 3 Wish REFS Place 8 of 8 ports w Lums 30 4 If more I O ports are selected than fit in the I O bank the PlanAhead tool places as many as possible in the selected I O bank then lets you select another I O bank into which to place the remaining ports The cursor drags the remaining I O ports to the next selected I O bank and so on until all of the I O ports are placed or you press Esc e Moving the cursor within the Package view actively displays the I O pin coordinates on the top and left sides of the view e Additional I O pin and bank information displays in the Status Bar located at the bottom of the environment e The active object being reported is highlighted in the Package view e Holding the cursor over the Package view invokes a tool tip that displays the pin information Ports are assigned in the order they appear in the I O Ports view The assignment order can be adjusted by applying sorting techniques in the I O Ports view prior to assignment Port assignment to device resources is also driven from the initial selection from the I O bank Selecting a pin at one end of an I O Bank results in a continuous bus assignment across the I O bank PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 271 272 Chapter 8 O Pin Planning g XILINX The PlanAhead tool also keeps track of PCB routing concerns for bu
10. 3 Run the Power Estimation command using one of the following methods e Tools gt Power Estimation e Flow Navigator gt Power Estimation for an open RTL design The Power Estimation dialog box opens as shown in Figure 5 6 G Power Estimation i Estimate power consumption based on the RTL design and part xc6vix7StfF484 2 Note that the settings will be modified accordingly based on a vectorless analysis of the design Logic Settings Logic Toggle Rate IOB Settings Input Toggle Rate Output Toggle Rate Bidir Toggle Rate Output Enable Rate Bidir Enable Rate Output Load DSP48 Settings DSP48 Toggle Rate BRAM Settings BRAM Toggle Rate BRAM Write Rate BRAM Enable Rate Figure 5 6 RTL Power Estimation Dialog Box 4 Adjust the default toggle rate information as required for your design and click OK The PlanAhead tool runs power estimation and opens the Power Estimation view in the workspace To calculate power the PlanAhead tool uses the RTL resource estimation and user constraints and performs a vectorless power estimation for the netlist nodes The Power Estimation view displays a Power Summary along with an expandable power consumption graph based on the resource types and the design hierarchy You can expand the logic tree using the view widgets to allow visibility into the hierarchy Figure 5 7 page 184 shows the Power Estimation view Note Default activity rates are used as seeds for
11. Limitations on Launching Runs on Remote Linux Hosts The limitations on launching Runs on remote Linux hosts are e Host execution is performed with SSH a service provided by Linux operating system and not PlanAhead For this to work you must configure SSH so that you are not prompted for a password each time you log in to a remote machine If you have not configured key agent forwarding for password less SSH or if you have configured SSH and you are prompted for a password see Appendix D Configuring SSH Without Password Prompting e Linux to Linux hosting is the only supported platform because of security and lack of remote shell capabilities on windows systems e ISE tool installation is assumed to be available from any login shell which means that XILINX and PATH are configured correctly in your cshrc bashrc setup scripts If you can log into a remote machine and enter map help without sourcing any other scripts this flow works If you do not have ISE set up upon login CSHRC or BASHRC you can use the Run pre launch script option to pass an environment setup script to be run prior to all jobs e PlanAhead installation must be visible from the mounted file systems on remote machines If the PlanAhead installation is stored on a local disk on your own machine itis not be visible from remote machines e PlanAhead project files ppr and directories data and runs must be visible from the mounted file systems on remote
12. Then the compiled object codes are linked into a simulation executable named after the top level module specified in the ISim Launch dialog When the ISim executable is complete the PlanAhead tool launches the simulator INFO Runs 8 Fuse completed INFO Runs 10 Launching ISim INFO Runs 11 Running C project_cpu_hdl project_cpu_hd1l sim sim_1 top exe intstyle pa gui tclbatch ISim cmd wdb wdb_testl wdb view wcfg_test1l wcfg The simulation executable is run with the various options specified in the Launch Options form The PlanAhead tool launches ISim with the gui option This opens the ISim GUI so you can interactively simulate the design For information about running Sim through the GUI see the Sim User Guide UG660 as cited in Appendix E Additional Resources Figure 11 24 shows the ISim GUI SS isim 0 76 Default wcfe a File Edit View Simulation Window Layout Help De st CO Oo Mis w Instances and Processes 0 xXx Objects Ogx gl alal l glr gal Simulation Objects for top Wea cam UA UB US fe Instance and Process Name D a i a gt 5 F top ol Object Name Value F gbl gll cpuclk 3 std_logic_1164 st wbclk 9 std_logic_arith st usbClk std_logic_signed st FFECIk 3 bftpackage bf reset vl_types vl TILEO_REFCLK TILEO_REFCLK TILE1_REFCLK TILE1_REFCLK TILE2_REFCLK TILE2_REFCLK TILE3_REFCLK TILES_REFCLK GTPRESET_IN TILEO_PLLLKD
13. Using Non Rectangular Pblocks PlanAhead supports creating modifying and deleting non rectangular Pblock shapes with multiple rectangles per Pblock It is recommended that you use this approach sparingly and only when necessary because non rectangular Pblock shapes can increase the possibility of error in downstream tools www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Configuring Pblocks Creating Non Rectangular Pblocks To add additional rectangles to existing Pblocks with rectangles use Add Pblock Rectangle i Pblocks with multiple rectangles appear as separate rectangles with a dashed line connecting them as shown in Figure 10 5 page 314 Modifying Non Rectangular Pblocks When you select a Pblock with multiple rectangles defined all of its rectangles are selected They can be moved individually or together as a group To reshape one of the rectangles of a multiple rectangle Pblock select a rectangle and use the Set Pblock Size command or resize it manually To select or resize a rectangle individually use one of the following methods e Fora single Pblock rectangle click Select in the popup command e To select the rectangle then select the Pblock Properties Rectangles tab Defined Pblocks that span PowerPC 405 and 440 processors serial transceiver sites or configuration blocks might receive multiple rectangle regions automatically This is done to enable the correct rect
14. Figure 3 21 Add Constraints Dialog Box To create constraints sets 1 Inthe Add Constraints dialog box use the Specify Constraint Set field select the Create Constraint Set command and enter a name as shown in Figure 3 21 When you select Create Constraint Set the PlanAhead tool prompts you to enter a name for the new constraint set and provides a checkbox to make it the active constraint set 2 Click Add Files to select UCFs NCFs or XCFs to add to the constraint set or use the Create File command to select a location and name for a new UCF Using the Save Design As Command You can also create a new constraint set by saving changes made to constraints during the design and analysis process Save Design As lets you enter a new constraint set name into which to save all constraints Figure 3 22 shows the Save Design As dialog box G Save Design As i Save design as a new Constraint Set Specify Constraint Set New Constraint Set name constrs_4 Make active Figure 3 22 Save Design As Dialog Box PlanAhead User Guide www xilinx com 59 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects g XILINX With multiple places to make constraint changes it is convenient to save changes to a new constraint set to manage changes or support what if analysis The Save Design As dialog box e Creates a new constraint set e Copies the active constraint files into the new constraint
15. Select a command from the results list of the command search to execute that command Using the Information Banner The information banner at the bottom of the main window displays useful information such as the item currently under the mouse cursor the currently selected object the coordinates of the cursor and the current design mode Figure 4 24 shows both the left hand end and the right hand end of the information banner separated to provide a closer look BEL Pin SLICE _ 66Y88 CARRY4_BMUX 50 CARRY4_BMUX SLICE_X66188 SLICEL RTL Flow Figure 4 24 Information Banner The information banner displays e Information Message The first field in the Information Banner displays context sensitive information For example when the cursor is in the device view or the schematic view this field contains the name of the instance or site directly under the cursor The information message field also contains detailed description of commands when the mouse is over its corresponding toolbar button or menu item e Coordinates To the right of the Information Message field is the Coordinates field As the cursor moves over block RAM DSP48 and other parts in the Device view this field displays the name and coordinates as shown in Figure 4 24 If the cursor is over a pin in the Package view this field displays pin information such as coordinates type and name e Mode Indicates the type of project such as RTL Flow or Post Synthes
16. e Create File Invokes the Create Source File dialog box where you can create new VHDL Verilog or Verilog header files See Defining New Modules page 39 for more information e Delete Removes the selected source files from the list of files to be added e Move Selected File Up Moves the file or directory up in the list order The order of the files affects the order of elaboration and compilation during downstream processes such as synthesis and simulation See Controlling File Compilation Order in Chapter 6 for more information e Move Selected File Down Moves the file or directory down in the list order e Scan and Add RTL Include Files into Project Scans all RTL source files and imports any referenced Verilog include files into the local project directory structure e Copy Sources into Project Copies the original source files into the project and uses the local copied version of the file in the project If you added directories of source files using Add Directories the directory structure is maintained when the files are copied locally into the project For a complete discussion of this topic refer to Using Remote Sources or Copying Sources into Project page 55 e Add Sources from Subdirectories Adds source files from the subdirectories of directories specified with Add Directories Creating RTL Sources To create a new source file select the Add or Create Design Sources option from the Add Sourc
17. e Input and High Drive outputs only go to capable pins Spartan 3 devices only e Differential I O ports are set to the proper sense pin e No output pins are placed on input only pins It is recommended that you begin your I O port placement with DRCs enabled I O Port and Clock Logic and Placement DRC Rule Descriptions page 426 lists the I O related DRCs PlanAhead User Guide www xilinx com 269 UG632 v13 4 January 18 2012 Chapter 8 VO Pin Plann Placing I O Por ing XILINX ts The I O Planning view layout provides a variety of ways to assign I O Ports to package pins You can select individual I O ports groups of I O ports or interfaces in the I O Ports view and assign them to package pins in the Package view or I O pads in the Device view You can toggle the online DRCs on or off during interactive placement The following subsections describe each placement mode option Placing I O Ports Sequentially To place I O ports sequentially 1 2 In the I O Ports view select an individual I O port a group of I O ports or interfaces Use one of the following commands e IntheI O Ports view from the popup menu select Place I O Ports Sequentially e Ineither the Package view or the Device view click the Place I O Ports af Sequentially button The first I O port in the group is attached to the cursor when you move it over a package pin or I O pad A tool tip displays the I O port and package pin names
18. All clients pointing to this network location have this option disabled by default Client users have the option of enabling this option Tools gt Options gt General gt Miscellaneous gt Automatically check xilinx com for software updates on startup and also running manual checks Figure C 1 page 432 shows the option PlanAhead User Guide www xilinx com 431 UG632 v13 4 January 18 2012 Appendix C Installing Releases with XilinxNotify XILINX G PlanAhead Options Selection Rules Jiri Shortcuts Look and Feel Style Office 2003 w Theme Default Warning Dialogs Show warning dialog before closing a floorplan Show warning dialog before closing a project C Show warning dialog before upgrading an old project Show warning dialog before exiting Plandhead C Show warning dialog when accessing unavailable features 1 0 Placement Automatically enforce legal I O placement Miscellaneous Automatically check xilinx com For software updates on startup Number of recent projects to list 3 Figure C 1 i Cancel Automatically Check xilinx com for Software Updates Apply Note To perform a software update installation you must have write permissions for the XILINX installation directory Quarterly releases for all platforms are regularly made available on the Download Center at http www xilinx com support download index htm 432 w
19. Automatically Scrolling to Selected Objects Some views in the workspace such as the Clock Resources view have an option to automatically scroll to a selected object This allows the displayed view to be updated to focus on an object that is cross selected from a different view To enable this mode use the Automatically scroll to selected objects toolbar button t in the views where it is available the Sources view the Netlist view and the Clock Resources view Enable or disable this command as needed Moving Selected Objects You can move selected objects in graphical workspace views e To move objects e Hold the left mouse down to select an object e Drag the object to move it e Release the object to drop it on a new location The cursor changes to a hand symbol when the move mode is activated e To move multiple instances at the same time e Press and hold the Ctrl key to enable multiple selections e Left click multiple times to select multiple objects e Hold down the left mouse button and drag and drop the selected objects to a new location Highlighting Selected Objects The PlanAhead tool has a highlight mechanism that lets you selectively highlight objects Highlighting lets you display multiple placement groups at the same time using different colors Highlighted objects remain highlighted even when you unselect them They are highlighted in all applicable views including the Schematic You can highlight any
20. Figure 4 6 Layout Pulldown Menu The predefined view layouts are e Project Management The Project Management view layout is the default view layout when you first open a project in the PlanAhead tool The Project Management view layout enables creating importing and managing source files IP cores and constraint sets e Design Analysis After a design is opened and elaborated into memory the design data displays in the Design Analysis view layout You can analyze RTL and netlist designs apply timing and physical constraints e I O Planning Define I O placement constraints place ports e Clock Planning Cross select between the Clock Resources view and the Device view and I O Port view to plan and place clock resources in the design e Floorplanning Define Pblocks manage partitions and perform hierarchical floorplanning e ChipScope Insert ChipScope analyzer tool debug cores You can also create custom view layouts that meet your specific requirements Creating and Removing View Layouts The PlanAhead tool provides predefined view layout configurations to complete specific design tasks such as the I O Planning view layout or the Design Analysis view layout These view layouts predefine the location and size of views commonly used for a specific design task The PlanAhead tool also lets you create store remove and reset user defined view layouts after moving and resizing views to suit your ow
21. Pblocks Without Assigned Instances Pblocks with no instances and with rectangles defined assigned appear as blue three dimensional cubes with a blue P in the center as shown in the following snippet ep pblock_viterbi Pblocks with no instances assigned with no rectangles defined appear as blue two dimensional squares with a blue P in the center as shown in the following snippet pblock_1 Partially Reconfigurable PBlocks Partially reconfigurable partition Pblocks appear as yellow diamonds as shown in the following snippet pblock_usbEngine1 Working with Relatively Placed Macro RPMs Relatively Placed Macros RPMs folders list the RPMs that exist in a Design RPMs can be assigned to Pblocks If RPMs are assigned to Pblocks they appear in an RPM folder under the Pblock Each instantiation of an RPM displays in the Physical Constraints View as shown in Figure 7 31 a a 5 netlist _1 S E ROOT gt RPMs 9 core_Ojenable_genO txspeedis100gen core_O enable_genO_txspeedis100gen core_O enable_genO txspeedis10100gen core_O enable_genO_txspeedis10100gen core_O enable_gen1 txspeedis100gen core_O enable_gen1_txspeedis100gen core_Ofenable_gen1 txspeedis10100gen core_O enable_gen1_txspeedis10100gen core_Oj rxspeedis10100gen0 core_O_rxspeedis10100gen0 core_Ojrxspeedis10100gen1 core_0_rxspeedis10100gen1 ios_O rx_ramii_reset_gen_Ofios_O_rx_ramii_reset_gen_0 ios_Ojrx_rgmii_reset_gen_1fios_O_rx_rgmii_reset_gen_1
22. UG632 v13 4 January 18 2012 XILINX Exporting IBIS Models i ccssovrgernenses ease ea ansad nadaes sore reeeeess 281 Using Noise Analysis Predictors 0 c cece cece eee eee ee 283 Chapter 9 Implementing the Design Running Implementation 0 66 65 ciennk ce sa eter eer ennodee cease enes cuss 291 Monitoring the Implementation Run 0 0 0c cee eee 295 Determining the Project Status 0 0 00 296 Analyzing Implementation Run Results 0 0 00 0 eee ee 297 Selecting the Step After Implementation 0 0000005 300 Creating and Managing New Runs 0 000 c cece eee eee 300 Using the Design Runs View 0 000 c cence eee es 302 Launching Runs on Remote Linux Hosts 00 00 e eee ee 306 Chapter 10 Floorplanning the Design Working with Pblocks s sjicasda oxyde orate ted Pie ee Re 309 Configuring POON S oii 6 02 3 0odh 6 Pend ge cickwh duke eee Ral mn Kl Gaetan ybicias 319 Working with Placement LOC and BEL Constraints 329 Interfacing with ISE Outside of PlanAhead 00008 338 Chapter 11 Analyzing Implementation Results Opening the Implemented Design 0 0 00 e cece eee eee 341 Analyzing Timing Results Lannau nuaran Pea inaiiuseniere cies 345 Exploring Logic Connectivity s u ussuinusrnirerrrru rr rrnr e
23. e Enable Timing Pessimism Removal Removes the skew delay generated by the common clock path between source and destination registers when modeling on chip delay variation Analyzing Timing Histogram Results After the histogram is generated you can use the results to obtain an indication of the type of timing problems associated with the design The Histogram view contains a graph of the delays and lists each of the path endpoints in a table beneath the histogram Figure 7 24 page 238 is an example of the slack histogram results You can sort the endpoints by selecting the column headers of the table or display only the paths within a specified bin by selecting that bin in the graph PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 237 Chapter 7 Netlist Analysis and Constraint Definition XILINX E Project Summary X Device X E Clock Interaction results_1 x Number of Endpoints 26561 items from 11 528 ns to 25 382 ns Id Name 1 cpuEngine cpu_dbg_dat_o buffer_fifo Mram_fifo_ram DIADI 25 2 cpuEngine cpu_dbg_dat_o buffer_fifo Mram_fifo_ram DIADI 28 3 cpuEngine cpu_dbg_dat_o buffer_fifo Mram_fifo_ramsDIADI O 4 cpuEngine cpu_dbg_dat_o buffer_fifo Mram_fifo_ram DIADI 1 5 cpuEngine cpu_dbg_dat_o buffer_fifo Mram_fifo_ram DIADI 2 6 cpuEngine cpu_dbg_dat_o buffer_fifo Mram_fifo_ram DIADI 3 i VURVVN9U9 7 cpuEngine cpu_dbg_dat_o buffer_fifo Mram_fifo_ram DIADI 4 Endpoint Setu
24. g XILINX If you are satisfied with the results click Finish to instantiate and connect the ILA cores in the design Using the ChipScope Window to Add and Customize Debug Cores The main ChipScope view provides more fine grained control over ILA core insertion than what is available in the ChipScope wizard The controls available in this window allow core creation core deletion debug net connection and core parameter changes The main ChipScope view e Shows the list of debug cores that are connected to the ICON controller core e Maintains the list of unassigned nets at the bottom of the window You can manipulate debug cores and ports from the popup menu or the toolbar buttons on the top of the view Creating and Removing Debug Cores To create ChipScope debug cores in the ChipScope view click Create Debug Core Using this interface you can change the parent instance debug core name and set parameters for the core To remove an existing debug core in the ChipScope view select the core and select Delete Adding Removing and Customizing Debug Core Ports In addition to adding and removing debug cores you can add remove and customize ports of each debug core to suit your debugging needs To add a new port 1 Select the core 2 Click Create Debug Port The Create Debug Port dialog box opens as shown in Figure 12 7 Create Debug Port Debug Core Type Port width Options co
25. www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Performing Behavioral Simulation rangecheck Switch to specify that fuse linker and compiler should perform a value range check on VHDL assignments during compilation This option applies to VHDL code only Note This does not affect index range checking for arrays which ISim always checks wdb Specify a filename to save the simulation waveform data The simulation results of the signals being traced are saved to the specified filename in the working directory The PlanAhead tool creates a lt top_module_name gt wdb file by default wcfg Specify a waveform configuration filename to use when opening the waveform data in the ISim GUI The wave configuration file specifies settings such as the signal order name style radix and color Load glbl Switch to specify that the g1b1 module should be loaded during compilation If the design uses a Verilog UniSim or a SimPrim library you must enable this switch More Fuse Options Specify additional command line options for fuse These commands should be typed in a single string with the command value pair For instance maxdelay init file lt filename gt notimingcheck You can also add the fuse options into a command file and reference this file in the More Fuse Options field with the command as follows lt command_file gt More Simulator Options Specify additional com
26. Generally when an error occurs in a Tcl command sourced from a Tel script further execution of subsequent commands is halted This is to prevent unrecoverable error conditions There are Tcl built ins that allow users to intercept these error conditions and to choose to continue Consult any Tcl reference for the catch command for a description of how to handle errors using general Tcl mechanisms Tcl References The following subsections provide recommended Tcl references 400 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Tcl References Tcl Developer Xchange Tcl reference material is available on the Internet Xilinx recommends the Tcl Developer Xchange which maintains the open source code base for Tcl and is located at http www tcl tk An introductory tutorial is available at http www tcl tk man tcl tutorial tcltutorial html About SDC Synopsys Design Constraints SDC is an accepted industry standard for communicating design intent to tools particularly for timing analysis A reference copy of the SDC specification is available from Synopsys by registering for the TAP in program at http www synopsys com Community Interoperability Pages TapinSDC aspx Available Tcl Documents Tcl reference documents are available in book stores or online retailers PlanAhead User Guide www xilinx com 401 UG632 v13 4 January 18 2012 Chapter 14 Tcl and Batch Scripting
27. Hierarchy Libraries Compile Order E E E E p p 0 p pO rEg Figure 4 39 Sources View The Sources view has three tabs to display the source files in different ways The Hierarchy tab displays the hierarchical view of the design sources starting with the top module The top module defines the hierarchy of the design for compilation synthesis and implementation It is identified with a special icon in the Sources view as shown in Figure 4 39 The PlanAhead tool automatically detects the top module but you can also manually define the top module using the Set as Top command see Sources View Popup Menu page 124 The Libraries tab displays the sources sorted into the various libraries A green dot next to the source file name indicates that the source file is copied into the local project directory When source files display in red the software could not find the required files The Compile Order tab displays source files in the order in which they will be compiled first to last In this case the top module is usually the last You can allow the PlanAhead tool to automatically determine the compile order based on the defined top module and the elaborated design You can also manually control the compile order of the design by setting the Hierarchy Update command and reordering the source files see Sources View Popup Menu page 124 Using the Sources View Commands The Sources view has a toolbar menu and a popup m
28. Selects the speed grade of the device used in the timing analysis This field allows the estimation of design timing using different device speed grades e Multi corner analysis Multi corner analysis simultaneously uses different process and operating condition corners to perform a worst case setup and hold analysis This results in a more accurate but pessimistic analysis than minimum or maximum delays alone e Slow corner Selects the delay types used for the slow corner analysis The available values are 236 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using Slack Histograms None Specifies that no delays are used Max Specifies that maximum delays are used for the clock and data paths during setup and hold analysis Min Specifies that minimum delays are used for the clock and data paths during setup and hold analysis Min_Max Uses a combination of minimum and maximum delays for the clock and data paths during setup and hold analysis Fast Corner Selects the delay types used for the fast corner analysis The values are None Specifies to use no delays Max Uses maximum delays for the clock and data paths during setup and hold analysis Min Uses minimum delays for the clock and data paths during setup and hold analysis Min_Max Uses a combination of minimum and maximum delays for the clock and data paths during setup and hold analysis
29. e The Schematic view allows selective logic expansion and hierarchical display e The Device view provides a graphical view of the device placed logic objects and connectivity All views cross select and present the most useful information e The Implemented Design contains additional logic analysis capabilities The capabilities are more powerful after placement and timing results are imported Refer to Chapter 11 Analyzing Implementation Results for more information The following subsections describe the available logic exploration methods Exploring the Logic Hierarchy The Netlist view displays the logic hierarchy of the RTL You can expand and select any logic instance or net within the netlist As you select logic objects in other views the Netlist view expands automatically to display the selected logic objects For more information refer to Using the Netlist View page 148 Information about instances or nets displays in the Instance or Net Properties views The Hierarchy view displays a graphical representation of the RTL logic hierarchy Each module is sized in relative proportion to the others so you can determine the size and location of any selected module For more information refer to Using the Hierarchy View page 151 Exploring the Logical Schematic The Schematic view allows selective expansion and exploration of the logical design You must select at least one logic object before the Schematic view is available
30. modify different elements of views General Device I Os and Bundle Nets General Tab Define colors for the PlanAhead tool to use when displaying different elements of the viewing environment such as background and highlight colors The color values for specific elements can be changed by e Clicking on a color box to expose a pulldown menu and select from a list of available colors e Choosing More Colors to Name Graphical Editors Background Foreground Selection 4 Highlight 4 Hierarchy View 4 Schematic Viewer 4 Histogram Chart Console Background Foreground Command text Error text Warning text Windows mele display even more colors to choose from Color 240 240 240 EE 0 0 0 E 255 102 0 P55 255 0 None BO ae More Colors MA arr arre are Description Color for selecte Color for Tcl com Color for error m Color for warning PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 163 Chapter 4 Using the Viewing Environment g XILINX e Entering a specific RGB value directly in the text field for the color Device Tab Object Type Select Frame Color Fill Color Adjust the default color and acc Ts E 255 15 Bed a A Pblock 2nd Level MMH 153 51 E 170 1 selectability for objects in the Device Polock 3rd Levels TET v v
31. 1 Oo O 1 E 128 bundl 2 20 2 Mal 148 undle nets 21 60 4 E 255 i 61 200 6 EE 255 e Use the From To columns to adjust the a mag E 102 signal count ranges for bundles Each 501 1 000 10 ai column represents a bundle net range 1 001 12 EE 153 which can be independently configured e Use the Width column to define the line width for the bundle in the Device view e Inthe Display column toggle the check boxes off to hide the bundle e In the Select column toggle the check boxes off to make the object types unselectable Saving a Custom Theme After you have configured the various color settings in the Theme Options dialog you can save your own custom view settings for use in future sessions Click the Save Theme As button next to the Theme pulldown menu as shown in Figure 4 71 page 165 164 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Configuring PlanAhead PlanAhead Options PlanAhead Light Theme x Save As Delete es FD Save Theme As x Description Colors for the Floorplar a y Selection Rules Theme name My_Theme P7 ANF i Available Themes Color to use for selecte Shortcuts Highlight colors Instance Hierarchy Viev World View colors Schematic View colors _ Colors for the comman Color for Tcl command Color for error messag Color for warning mess Colors for all other win v gt General Device 1
32. 16 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Launching the PlanAhead Tool To open or download the PlanAhead tool documentation click the documentation links to launch a PDF viewer or website download location Note The PlanAhead tool installs with a placeholder PDF file for the User Guide In that file you are guided to a web URL to download the latest document There are simple installation instructions to enable the link to then invoke the full local copy of the User Guide when selected e Release Note Guide A web link to the Release Notes for a given release e User Guide A link to this manual e Methodology Guides A web link to Xilinx methodology guides e PlanAhead Tutorials A web link to Xilinx tutorials and supporting design data Command Line Options The PlanAhead tool has several command line options To view the PlanAhead tool command line options type the following command at the command prompt planAhead help A help menu displays in the shell window Using a Startup Tcl Script create projec set_property import files set_property import files set_property set_property set_property set_property launch runs launch runs close_project Use the Tools gt Run Tel Script command to run a script You can copy the PlanAhead tool Tcl commands from the planAhead jou file or from the Tcl console to create startup scripts Figure 1 2 shows a
33. 2012 Chapter 12 Programming and Debugging the Design XILINX 380 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Chapter 13 Using Hierarchical Design Techniques The PlanAhead tool supports hierarchical design Xilinx strongly recommends that you decide whether or not to use hierarchical design before you begin your project e The decision to use hierarchical design requires some forethought about design partitioning and Register Transfer Logic RTL coding decisions e Your results could be less than optimal if you try to adapt a design to this methodology late in the design cycle in an attempt to close timing or reduce runtime For more information see the following documents cited in Appendix E Additional Resources e Hierarchical Design Methodology Guide UG748 e Partial Reconfiguration User Guide UG702 Using Partitions PlanAhead User Guide The hierarchical capabilities that are central to setting and managing hierarchical boundaries in the design are called partitions These boundaries prevent the Synthesis and Implementation tools from optimizing the logic across the boundaries making it possible to isolate the logic for reuse Effective partitioning relies on good logic design practices and knowledge of the design The PlanAhead tool supports the following partitioning capabilities e An incremental Xilinx Synthesis Technology XST flow using RTL projects
34. After you import the ISE placement you can use Highlight Primitives to highlight the underlying primitive logic elements selectively for Pblocks and logic modules then select a color to highlight their associated placement When you select multiple instances you can select the same color for all or use Cycle Colors to use different highlight colors for each of the selected modules PlanAhead marks modules and primitives in the Netlist view with the matching highlight color in the Device Schematic and Package views as shown in Figure 11 14 B Primitives 1 I cpuEngine If O_top E matEngine matT oy E usbengined usbe E usbEngine1 usbe f wbarbengine wb_co H 6 Nets 892 h Primitives 64 J mo b_conmax H H Ee Ge id r b_conmax_rF so wb_co Hs wb 2 wb ss WwD_co HBR s4 wb D fftenaine fftEngine fftTop ngine0 usbf toj linel usbr_ tor Hm b_conmax_maste ef s15 wb_conmax_slave OS e be fr x agp es web TT ey Netlist El Physical Constraints amp Timing Constraints E Project Summary X Figure 11 14 Matching Highlighting Color in the Netlist and Device Views 356 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Locking Placement for Future Implementation Runs Unhighlighting Objects To un highlight objects use one of the following commands e View gt Unhighlight All to unhighlight al
35. Analyze Implemented Design Results Use the PlanAhead tool to analyze implementation results generated outside of the PlanAhead tool such as in Xilinx ISE Design Suite You can examine placement and timing results to explore design changes timing adjustments or floorplanning to achieve timing closure Partial Reconfiguration The PlanAhead tool provides an environment to set up and manage partial reconfiguration projects These designs require special features and project structure to manage reconfigurable modules For more information see the Partial Reconfiguration User Guide UG702 cited in Appendix E Additional Resources 1 Partial Reconfiguration is only available under special licensing PlanAhead User Guide www xilinx com 19 UG632 v13 4 January 18 2012 Chapter 2 The PlanAhead Tool Flow XILINX Design Flow The PlanAhead design flow depends on the type of input file that you start with This section describes the design flow and design tasks Figure 2 1 shows the common design flows and the input and outputs of the PlanAhead tool Project Creation Create Add Sources RTL Analysis 1 0 Planning Behavioral Simulation RTL Design RTL Flow Mol LY MO 3 SIRON ae _ Netlist Analysis Aguet Constraint Entry I O Planning Mold SIREN Synthesis ATL Flow MOl 4 LH Timing Simulation Results Analysis Floorplannin
36. Bin Display Number of bins Significant digits C Plot on log10 scale Command create_slack_histogram delay_type max num_bins 10 significant_digits Figure 7 20 Generate Slack Histogram for Endpoints Dialog Box Options Tab The options are e Endpoint Scope Specifies the endpoints and delay types to be used in the slack histogram generation By filtering the endpoints based on clock name and group name a histogram can be generated to focus on specific paths of interest The fields in this area are e Delay Type Specifies the delay values used in the generation of the slack histogram Min Uses minimum delays for the clock and data paths for the slack histogram Max Uses maximum delays for the clock and data paths for the slack histogram Min_Max Uses a combination of minimum and maximum delays for the clock and data paths for the slack histogram e Clock Name Filters the endpoints by the associated clock name The value for this field can be entered directly or by using the Choose Endpoint Destination Clocks dialog box e Group Name Filters the endpoints by the associated group name The value for this field can be entered directly or by using the Choose Endpoint Path Groups dialog box 232 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Using Slack Histograms e Slack Range Filters the endpoints based on the slack value By filt
37. Checks DCI Cascade DCICPC Warns the user to load the UCF into other compatible parts and to Warning with part run DRC manually to ensure the DCI cascades are valid compatibility DCI check for DCICIOSTD Ensures that there are no conflicts related to Vec and DCI Error I O standard termination of I O standards used within the DCI Cascade legality Table B 5 Delay Control DRC Rule Name Rule Abbrev Rule Intent Severity IDelayCtrl IDLYCTRL Checks that Delay placement is consistent with IDlyController Error Checks LOCs For a full list of Bank IO standard rules see I O Port and Clock Logic and Placement DRC Rule Descriptions page 426 PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 423 Appendix B PlanAhead DRCs XILINX ClkBuf DRC Table B 6 ClikBuf DRC Rule Name Rule Abbrev Rule Intent Severity BufR amp BuflO BUFRIOC Checks that BUFR and BUFIO driven by the same regional clock Error Locations terminal are placed at mutually route able locations See Global Clock DRCs page 426 for a full list of global clock rules DSP48 DRCs Table B 7 DSP48 DRCs Rule Name Rule Abbrev Rule Intent Severity DSP48 output DPOR DSP48 has a register on the output side to use this register the Information registers register should be synchronously controlled Virtex 4 only DSP48 input DPIR DSP48 has a register on the
38. D Strategy ISE Defaults ISE 13 Synthesis Description ISE Defaults including packing registers in IOs off NL Translate ngdbuild Map map gt 7 Place amp Route par i i Static Timing Report trce IP Catalog This option causes the timing report to be a verbose report instead of a default summary report The value supplied For this switch is an integer limit on the number of items reported For each timing constraint in the report file The value of limit must be Figure 3 44 Implementation Project Settings The Implementation Project Settings dialog box contains the following information e Default Constraint Set Select the constraint set to be used for the implementation run e Strategy Select the strategy to use for the implementation run There is a set of pre defined strategies to select from or you can create your own For more information see Defining Strategies for Synthesis and Implementation in Chapter 4 When you select a strategy the command line options for the ISE implementation tools NGDBuild MAP PAR and TRCE display in the lower part of the dialog box as shown in Figure 3 44 You can override implementation strategy options by changing the command line options e Description Displays a textual description of the selected implementation strategy 88 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Configuring Project Settings
39. DRCs e Debug core insertion and implementation with the ChipScope debugging tool e Perform device configuration and file generation using the iMPACT tool e Analyze implementation results e Launch programming and design verification tools Project Creation and Management The PlanAhead tool provides a variety of options for creating and managing FPGA design projects and creating different constraint sets to explore design variations See Chapter 3 Working with Projects RTL and IP Design The PlanAhead tool RTL Design environment lets you create and manage RTL design files You can customize and implement IP through integration with the CORE Generator tool In addition to creating and managing design source files the PlanAhead tool provides RTL design elaboration enabling RTL logic exploration an RTL Schematic Viewer a set of RTL DRCs and RTL based resource and power estimation For more information see Chapter 5 RTL Design Design Simulation The PlanAhead tool also lets you launch Xilinx ISim to perform behavioral simulation of HDL designs and full timing simulation of implemented designs The PlanAhead tool prepares the required simulation executables and launches the Sim Graphical User Interface GUI to allow you to simulate the design add and view signals www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Using the PlanAhead Tool in the waveform viewer and examine and debug the
40. Decreases the zoom level e Zoom Fit Views the entire histogram in the display e Zoom Area Fits a selected area in the entire display e Options Invokes the main PlanAhead Options menu Analyzing Clock Interactions 240 In large complex FPGA designs data is frequently transferred from one clock domain to another To identify potential problems such a metastability or data loss or incoherency some visibility into the paths that cross clock domains is beneficial The Clock Interaction Report in PlanAhead offers insight into clock interactions and signals that cross clock domains The path between a flip flop in one clock domain to logic in a second clock domain is not automatically analyzed by the ISE or PlanAhead timing tools unless there is a constraint that specifies that the two clock domains are related Therefore unconstrained paths might go unanalyzed The purpose of the Clock Interaction Report is to look at the circuit topology and the design constraints and inform you of any paths that cross clock domains whether they have defined constraints or not In this way you can identify paths that are properly constrained unconstrained or are false paths that should simply be ignored The Clock Interaction Report can also help you find signals that are implied in the RTL code and inadvertently cross clock domains and so might lack required constraints Reporting Clock Interactions With a synthesized netlist design open i
41. Flop 0 0 0 0 0 0 3912 3912 Flop RTL Hierarchy Resources LUT BRAM 503 0 65 0 613 0 658 0 2707 0 261 0 51 30 4858 30 LUT BRAM 82 52 82 52 82 52 82 52 82 52 R 5 DSP48 1 1 1 1 1 1 kRoooc to0 DSP48 210 0 0 00O a v Figure 5 5 Viewing RTL Resource Estimates General Statistics Pins Children Attributes Connectivity To save the resource estimation report to a text file an XML file or a CSV file e Select Export Statistics from the popup menu of the Resource Estimation view or e Click the Export Statistics toolbar button in the Instance Properties view re Analyzing the RTL Logic Hierarchy Ll The PlanAhead tool provides the following views into the logical design hierarchy e The RTL Netlist view provides an expandable logic tree e The Hierarchy view provides a graphical representation of the logic hierarchy e The Schematic view provides a view in which to explore the logic and hierarchy in a schematic representation All views cross select offering a unique set of capabilities to explore and analyze the logical design For more information see Using the Netlist View and Using the Hierarchy View in Chapter 4 Exploring the RTL Design Schematic You can select any level of logic hierarchy in the RTL Netlist view and display it in the RTL Schematic view To invoke the RTL Schematic view for any selected logic select one of the following e
42. IP Catalog Settings Figure 3 45 shows the IP Catalog Settings dialog box G Project Settings IP Catalog IP Repository Search Path IP Catalog Location C Documents and Settings randyh Application Data xilinx PlanAhead 13 1 pa_cg_catalog xml HDL Type Auto o o o uto Verilog HDL OK Cancel Figure 3 45 IP Catalog Project Settings The IP Catalog settings are e IP Catalog Location Displays the path to the local IP Catalog You can change the path using Update IP Catalog to generate a new local version of the IP Catalog See Updating the IP Catalog page 69 e HDL Type Defines the language to use when creating the IP e Auto Derives the preferred language automatically based upon the language of the top level HDL file e Verilog Specifies that the IP core generated by the CORE Generator tool is output in the Verilog language for inclusion into the project e VHDL Specifies that the IP core generated by the CORE Generator tool is output for inclusion into the project as VHDL code PlanAhead User Guide www xilinx com 89 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects 90 www xilinx com XILINX PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Chapter 4 Using the Viewing Environment The PlanAhead tool has a dynamic viewing environment comprised of view layouts that display the design and device information for the design current task I
43. Package Pin Properties You can select pins or I O banks in the Package view and see the corresponding details in the Properties view as shown in the Figure 8 2 gt Gali D T6 Name me Type GCLK Bank a I O Bank 34 Site Type IO_L1P_GC_34 Trace Length um 8983 IOB Alias 10B_x2Y37 Figure 8 2 Package Pin Properties 254 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Viewing Device Resources Clock Region Resources and Statistics The Clock Regions view allows easy selection of the clock regions Selecting a clock region highlights the related I O banks and regional clock resources as shown in Figure 8 3 F Package X E Project Summary x Device x Od x f Package 2 x Od x Id Name Row Column 1 xOvO 0 0 2 xOv1 1 0 0 12345 6 7 8 9101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ERITA tl p Secaunuzir xt rormsoo0ey Po EE Ee O 2a L i m z a a a E Ss A a Ss amp So H Net Tim G Pr Figure 8 3 O Planning Clock Region Sources The Properties view displays the properties for the selected clock region Selecting the Statistics tab in the Clock Region Properties view displays the resource statistics available within the clock region as well as the logic content of the selected clock region Click the Resources tab to locate device clock resources to for logic a
44. Pro debug software The ChipScope Pro integration provides simplified post Synthesis insertion and connection of the ChipScope Pro Integrated Logic Analyzer ILA debug cores in the PlanAhead tool Overview of ChipScope Integration in PlanAhead PlanAhead provides a GUI wizard for quick and easy design debug for most situations A non wizard GUI and Tcl command flow are available for precision debug core and net connection control This flow provides a robust ILA core connection solution without leaving the PlanAhead tool Figure 12 3 page 371 illustrates the debug core integration 370 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Debugging the Design with ChipScope User s Design Logic Q ChipScope ILA Debug Cores Figure 12 3 Block Diagram of PlanAhead ChipScope Integration User s Design Logic PlanAhead Chipscope Core Insertion Requirements and Limitations When Using Core Insertion Flow To use the ChipScope integration features in PlanAhead you must have Xilinx ISE Design Suite 13x tools including ChipScope Pro and PlanAhead installed To perform run time design debugging you must also have the Xilinx platform USB cable and board For more information about ChipScope Pro see http www xilinx com support documentation dt_chipscopepro htm The ChipScope integration in the PlanAhead tool has the following limitations The same software versions of
45. Severity I O Crosstalk to MGT IOCTMGT Check for possible crosstalk problems between I Os and serial transceivers Warning I O Bus SLR Crossings IOBUSSLRC The following message occurs when bits of the same bus are placed on different Super Logic Regions Bus port lt BUSPORT LO HI gt spans more than one Super Logic Region SLR Bits placed in SLR lt SLR1 gt 0 3 Bits placed in SLR lt SLR2 gt 4 7 This is not recommended as it makes routing and timing closure more difficult Eliminate the warning by moving all related bus ports into the same SLR Warning Part compatibility IOPCSLR Check for part compatibility between monolithic and multi die devices Information IOB clock sharing IOCS TOB sites are divided into pairs for the purpose of sharing clock routing resources These pairs are normally LVDS pairs as well In some cases there could be routing issues based on how the flops are packed inside the IOB To resolve this issue flops need to be assigned to specific BEL Warning IOB set reset sharing IOSR IOB site has input output and tri state registers all of these registers share same set reset signal Cannnot pack registers with different reset signals Error Bank I O Standard DRCs Table B 18 lists the Bank I O standard DRCs abbreviation intent and severity Table B 18 Bank I O Standard DRCs
46. Sources View page 122 Editing RTL Source Files The PlanAhead RTL environment provides an Text Editor in which to create or modify RTL sources The Text Editor uses color coding to distinguish the various types of RTL constructs You can open multiple files simultaneously and each open file displays a view tab in the workspace with access to all open files When you modify a file PlanAhead appends an asterisk to the file name in the view tab until the file is saved To save the file use one of the following methods e Right click in the Text Editor and select Save File e Use the Save File toolbar button in the Text Editor or 4 e Select File gt Save File PlanAhead User Guide www xilinx com 175 UG632 v13 4 January 18 2012 Chapter 5 RTL Design XILINX If you attempt to close a file with unsaved changes the PlanAhead tool prompts you to save the changes Using the Text Editor The RTL Design environment enables cross probing to and from the Text Editor with other views such as the Schematic Messages RTL Netlist and Hierarchy views For more information on the Text Editor see Using the Text Editor page 157 Using Find Commands to Search Source Files You can use Find or Find in Files to search for any given text string in an open source file or a selected set of source files You can perform the following actions e Enter any text string including wildcards as search criteria e Use the filtering
47. TILE1_PLLLKD TILE2_PLLLKD TILE3_PLLLKD a RXN_IN 0 ZZZZZZZZ 2 RXP_IN 7 0 ZZZZZZZZ BG TXN_OUT 7 0 11111111 t TXP_OUT 0 11111111 o OpMode_pad_1_o_temp st_pad_1_o_temp endM_pad_1_o_temr See EN ee A EEn ee ee ee ee s phy_clk_pad Oi z DataOut_pad xxxxxxxx TxValid_pad_0 x TxReady_pad z DataIn_pad_0 zzzzzzzz r a oe att ae 1 RxActive_pad l w 0 x p P vControl_pad_0_o 3 0 ar RxError_pad_ xcvSelect_pad TermSel_pad_ z z x x la phy_rst_pad_1_o Figure 11 24 Sim User Interface PlanAhead User Guide www xilinx com 367 UG632 v13 4 January 18 2012 Chapter 11 Analyzing Implementation Results XILINX Analyzing Power Distribution with XPower Analyzer You can launch the XPower Analyzer tool directly from PlanAhead to perform power analysis on any implemented design To invoke XPower Analyzer in the Flow Navigator open Implemented Design gt XPower Analyzer from the Implemented Design task list as shown in Figure 11 25 Implemented Design w E Resource Estimation Run DRC Run TRCE g Report Clock Networks FPGA Editor i XPower Analyzer iq Timing Simulation Figure 11 25 Launch XPower Analyzer The routed NCD file and timing constraints PCF file are passed automatically to the XPower Analyzer when it is launched from the PlanAhead tool For more information on using XPower Analyzer see the ISE Help Launchi
48. The Preview window shows the text that will be inserted into the Text Editor window The text cannot be edited in the Preview window prior to inserting it into the Text Editor 3 In the Text Editor place the cursor at the location in the file where the Xilinx language template should be inserted The cursor should be placed at the location where you want to insert the start of the template text Note The PlanAhead tool does not overwrite existing text in the Text Editor when inserting the template If a block of text is selected in the Text Editor window the template text is inserted at the end of the block of text 4 Insert the selected template into the text file by using the Insert Template i command from the Text Editor toolbar or popup menu to add the template text at the cursor location 5 Modify the inserted template text as needed to suit your design Configuring PlanAhead 160 The PlanAhead tool configuration options include selection rule options shortcut keys general settings options and window settings options The following subsections describe the configuration options Setting General PlanAhead Options To set the PlanAhead tool options select Tools gt Options The PlanAhead Options dialog box opens for you to set options of how PlanAhead operates as an application Some of these options overlap with the Project Settings that can be specified for a specific project within PlanAhead rather than for the t
49. To assign an I O port click a pin or a pad Figure 8 20 shows a sequential I O port placement If more I O ports are selected the command is continued The cursor drags the next I O ports and so on until all of the I O ports are placed or until you press Esc E Project Summary x 2 RTL Schematic x eos p Place GTPRESET_IN at F7 P Site Type IO_L9P_MRCC_36 Bank 36 1 of 44 Press ESC to quit oes ome wl i om Teal ons whith yd Lee orra orma orma TN ae in Figure 8 20 Placing I O Ports Sequentially The PlanAhead tool assigns ports in the order that they appear in the I O Ports view You can adjust the assignment order by applying sorting techniques in the I O Ports view prior to assignment 270 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Placing I O Ports Placing I O Ports into I O Banks To place I O ports into I O banks In the I O Ports view select an individual I O port a group of I O ports or Interfaces In the I O Ports view the Package view or the Device view click the Place I O Ports in an I O Bank button The group of I O ports is attached to the cursor when it is dragged over a package pin or I O pad A tool tip displays how many pins can be placed in the selected I O bank Click on a pin or pad to assign the selected I O ports Figure 8 21 shows an I O pad E Project Summary X 2 RTL Schematic x ff P oar nima GHD
50. UCF and RTL output files for use later in the design flow when RTL sources or netlists are available The output files can also be used to create schematic symbols for use in the Printed Circuit Board PCB design Note Use an RTL Source project to perform I O pin planning on a design using RTL header or source files Project Navigator Created Projects You can import project data from ISE Project Navigator to migrate a design The PlanAhead tool uses the various project settings from Project Navigator when creating this new project You can also launch the PlanAhead tool launched from within Project Navigator for use in I O Pin Planning and Floorplanning For information about using PlanAhead tools from the ISE Project Navigator environment refer to Chapter 15 Using PlanAhead With Project Navigator www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Creating a New Project Creating a New Project The following subsections describe how to create a project and the project options available within the wizard Using the New Project Wizard The New Project wizard takes you through the individual steps to define a project name and location add source files and constraint files to the project and select a target device To create a new project 1 Select one of the following e On the Getting Started page click Create a New Project e Select File gt New Project or the New Project toolbar button
51. XilinxNotify Network Installations 0 0 cece eee eee 431 Appendix D Configuring SSH Without Password Prompting Setting Up SSH Key Agent Forward 0 ccc cece eee 433 Appendix E Additional Resources Xilinx Resources 00 0 ccc eee e tenn nee ens 435 Hardware Documentation 0 00 00 000 cece ccc cect eee rraren 435 ChipScope Documentation os 442 1 05 cevsearreerigayenseeeeead essen rreren 436 EDK Documentation 0 0 00 00 00 cence rererere 436 EDK Additional Resources ooann nuen 00 cece ccc cece teen ee eees 436 ISE Documentation 0 0 0 00 000 nee cnc cence SS 436 Partial Reconfiguration Documentation 0 cee eee eee 438 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Application NoteSce sis cn 2ccyeu snes ecavad reseni Dy Esad e napa naie npa EE PlanAhead Documentation 0 0 aeaaaee eea IP DVO CU CPt issn escoe etic ces Wis acetate ded aac geese Be ooo aad bee eee heel eo Ae PlanAhead User Guide www xilinx com UG632 v13 4 January 18 2012 10 www xilinx com XILINX PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Chapter 1 About the PlanAhead Tool The Xilinx PlanAhead tool is a design tool for the entire FPGA device design and implementation cycle For information about Xilinx tool installation and new features see the following d
52. You can view and select any logic in the Schematic view You can display groups of timing paths to show all of the instances on the paths This aids floorplanning because it helps you visualize where the timing critical modules are in the design To open the Schematic view 1 Select one or more instances nets or timing paths 2 Select Schematic from the view toolbar or the popup menu or press the F4 key The view opens with the selected logic displayed 3 You can then select and expand the logic for any pin instance or hierarchical module For more information see Using the Schematic View page 136 Analyzing Hierarchical Connectivity Sometimes it is helpful to create a top level floorplan to help visualize the connectivity flow of the design as shown in Figure 7 8 page 215 214 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Inserting ChipScope Debug Cores x Package x E Project Summary x Figure 7 8 Viewing Top level Design Connectivity You can create a top level floorplan by creating Pblocks for key levels of the design hierarchy See Chapter 10 Floorplanning the Design for more information The Net bundles indicate the heaviest connectivity requirements between the modules When you select a Net bundle information about the net content displays in the Net Bundle Properties view The color and line thickness of the Net bundles can be configured depending on the number o
53. consist of logic from anywhere in the logic hierarchy Exporting a Pblock creates an EDIF netlist and a UCF physical constraints file for each Pblock selected for export To export Pblocks to EDIF and UCF 1 Select one or more Pblocks 2 Select File gt Export gt Export Pblocks The Export Pblocks wizard opens as shown in Figure 10 30 page 340 www xilinx com 339 UG632 v13 4 January 18 2012 340 5 Chapter 10 Floorplanning the Design XILINX qd Export Pblocks Select file types to generate and Pblocks to export Floorplan orig_fp Directory name C HDI project_1 lgj File types to generate Netlist EDIF Constraints UCF Export only fixed placement Export all placement Pblocks 2 Id Name Primitives Pins 1 pblock_1 w 2 pblock_LED Caj Figure 10 30 Export Pblocks Wizard Edit the options Directory name Enter the directory name or use the file browser to select a directory to export the files for the specified Pblocks The PlanAhead tool creates a subdirectory called pblockname_cCV for each exported Pblock To keep track of EDIF and UCFs associated with each Pblock it is a good practice to specify a unique directory name for each ISE run The exported Pblock directory is used to seed the Import Placement and Import TRACE Results command file browsers File types to generate Netlist EDIF Export the netli
54. e cece eee eee Using the Main Viewing Area 00000 e cece Using the Tcl Console and Messages Area Working with Views 00 00 00 cece cece eee eee Selecting Marking and Moving Objects Using the Find Commands 0 000 e cece Using Common Views s 0ic s sitio vs hiwsddewe bined bdeasiivs PlanAhead User Guide www xilinx com UG632 v13 4 January 18 2012 Using the Text Bq osc oo1 20ehorsceuad seereteaeeenarnetaess Configuring Plan Ahead vei unnn ti nag de teare hee dwnnawvalens Chapter 5 RTL Design Managing Design Source Files 000 0 c eee Editing RTL Source Files 0 00 0 cece eee Elaborating and Analyzing the RTL Design Estimating Power 355 85 lt tsssiaeieaceiacie Seeds pec ePecer secs Performing Behavioral Simulation 6 Running RTL DRC S 652 0 ve apeeade thin h in ven eheeg anand cewek Chapter 6 Synthesizing the Design Synthesis Methodology ii i410 cw vleid own a wvn gee neee Cia ier neon Running Synthesis lt 2iiscs3 5 cra s0ceupecteeeceveciesecereay Creating and Managing New Runs 06 Monitoring the Synthesis Run 000 0020 0 aoe Selecting The Step After Synthesis 000 Analyzing Synthesis Results 0 000 cece eee Chapter 7 Netlist Analys
55. f The first dialog box of the New Project wizard gives an overview of the wizard 2 Click Next to continue The Project Name page opens as shown in Figure 3 1 page 35 G New Project Project Name Enter a name for your project and specify a directory where the project data files will be stored Project name project_1 Project location C Data Project will be created at C Datalproject_1 Figure 3 1 Create Project 3 Inthe Project Name page specify a project name and disk storage location then click Next e Project name Enter a name to identify the project directory for example project_3 e Project location Enter a location to create the new project directory e Create Project Subdirectory Use this checkbox to indicate whether the PlanAhead tool should add a subdirectory of the same name as the project within the specified project location If you enable this checkbox which is the default the project file ppr is created at lt project_location gt lt project_name gt and all folders and data files created for the project are stored in that subdirectory PlanAhead User Guide www xilinx com 35 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects g XILINX If you disable this checkbox the project file ppr is created at lt project_location gt and all folders and data files created for the project are stored in that project location Selecting the Design Sou
56. ios_Ojtx_rgmii_reset_genfios_O_tx_rgmii_reset_gen o m set B E RPMs 34 core_O client_side_FIFOO rx_fifo_ifresync_wr_store_frame_tog core_Ojclient_side_FIFO core_O client_side_FIFOO rx_fifo_i sync_rd_addr 0 sync_rd_addr_gray core_Ojclient_sic core_Ojclient_side_FIFOO rx_fifo_i sync_rd_addr 10 sync_rd_addr_gray core_Ojclient_s core_O client_side_FIFOO rx_fifo_i sync_rd_addr 11 sync_rd_addr_gray core_O client_s core_Ojclient_side_FIFOO rx_fifo_i syne_rd_addr 1 sync_rd_addr_gray core_Ojclient_sic v m gt amp Sources B Netlist amp Timing Constraints Figure 7 31 Displaying Relatively Placed Macros RPMs RPM properties and statistics display in the RPM Properties view When RPMs are assigned to Pblocks the Pblock Properties view displays RPM size and utilization statistics information as shown in Figure 7 32 page 248 PlanAhead User Guide www xilinx com 247 UG632 v13 4 January 18 2012 Chapter 7 Netlist Analysis and Constraint Definition RINE MEN lt gtx_cik io_logic Global RPM Statistics Type Dim Avail Reqd o Util Set Name SLICE Max Width 22 1 SLICE Max Height 49 1 Clock Region Statistics General Statistics Instances Rectangles Attributes 4 core_O client_side_FIFOO r 2 core_Ojclient_side_FIFOO r XILINX eA Figure 7 32 RPM Utilization Statistics for Pbloc
57. lt version gt themes directory contains patheme files that are created when you customize color and fill pattern themes for displaying layers in the PlanAhead GUI You can select a theme file to use during the active session from a pull down selection menu For more information see Configuring the Viewing Environment in Chapter 4 View Layout Files lt layout_name gt layout The PlanAhead lt version gt layouts directory contains layout files that define the layout configuration of the PlanAhead tool views in the GUI You can create custom view layouts using the Layout gt Save Layout As command See Using View Layouts in Chapter 4 for more information Keyboard Shortcuts shortcuts xml The PlanAhead lt version gt shortcuts directory containsa shortcuts xml file that maps keyboard shortcuts to tool commands You can define and configure multiple keyboard shortcuts which are stored in the shortcuts file Refer to Configuring Shortcut Keys in Chapter 4 for more information Custom Commands commands paini The PlanAhead lt version gt commands directory contains the commands paini file which stores custom TCL commands added to the PlanAhead tool GUI Refer to Adding Custom Menu Commands in Chapter 4 for more information 414 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Outputs for Project Data Outputs for Project Data Figure A 2 is a diagra
58. no termination is assumed However for LVTTL at 12mA 16mA and 24mA a far end parallel termination of 50 Ohms to Vyr is assumed As a result of this termination the available noise margin is less for signals with drive strength of 12mA or more when compared to 2mA to 8mA Virtex 4 Virtex 5 Virtex 6 Spartan 6 and all Xilinx 7 series FPGA devices use this assumption Displays either None or a short description of the expected or defined off chip termination style for example FP_VTT_50 describes a Far end Parallel 50 Q termination to Vrr termination style The full list of termination styles is available in the device specific SelectIO Resources User Guide cited in Appendix E Additional Resources To change the settings use either e The CSV file import feature described in Importing a CSV Format File or e The pulldown selection in the I O Ports table OUT_TERM Spartan 6 only OUT_TERM Spartan 6 Devices Only displays the OUT_TERM attribute setting for the port if defined NONE is most common For more information about OUT_TERM see the Spartan 6 FPGA SelectIO Resources User Guide UG381 cited in Appendix E Additional Resources Margin V e Available Virtex 6 only Defines the allowable noise margin for that particular I O standard on the high side of the signal as it switches to a 1 It is strictly based on the DC logic levels implicit in the I O standard no quantity information is taken into acc
59. or select Delete from the popup menu in the Timing Results view Note You cannot undo a delete command to restore paths to the timing report You must rerun Timing Analysis PlanAhead User Guide www xilinx com 229 UG632 v13 4 January 18 2012 Chapter 7 Netlist Analysis and Constraint Definition g XILINX Displaying Path Details When you select a path from the list the Path Properties view populates with information about the path Logic elements are listed with detailed delay information shown in Figure 7 19 Summary U Name Slack Source Destination Requirement Delay Source Clock Destination Clock P Path 0 161 lt usbEngine0 usb_dma_wb_in BU2 UO gen_fifo18_36 fgfifo018_36 fblk inst_few k1 1 inst_fed one_prim inst_fifoprim gfifo36 sngfifo36 fifo36_wrap_inst DOP 1 usbEngineO usbEngineSRAM BU2 U0 blk_mem_generator valid cstr ramloop 0 ram r v5 ram SP WIDE_PRIM18 5P 3 800 3 961 usbClk rising at 0 000ns usbClk rising at 3 800ns Source Clock Path Delay Type net fo 0 IBUFG net Fo 1 BUFG net fo 407 Total Delay Cumulative Location Logical Resource 0 000 0 000 E AB19 D usbclk 0 000 0 000 E AB19 D usbClk_ibuffibufg T 0 818 0 818 E AB19 lt usbClk_ibuf ibufg O 0 000 0 818 E BUFGCTRL_XOY9 D usbCik_ibuf bufg I 0 250 1 068 5 BUFGCTRL_X0Y9 usbCik_ibuf bufg O 2 033 3 101 E RAMB36_X2 1 pblock_usbEngineO D usbEngineO usb_dma_wb_in BU2 UO g
60. 1 143 usbEngine usbEngi 2 134 66 0 4 usbClk_BUFGP usbClk_BUFGP TRCE impl_1 244 paths Td Console alo e Post Synthesis Flow _ Figure 11 10 Highlighted Timing Paths in the Device View Viewing Timing Paths in Schematic View When you select Schematic from the Timing Results toolbar or popup menu the PlanAhead tool generates a Schematic view that displays the instances found in the selected paths The Schematic view displays the instances clearly along with the hierarchical modules as shown in Figure 11 11 usb Engine1 MJECTOBITERR DOPADOR MJECTSBIFERR ECCPARITY FifoBuffer_usb_dma_wb_in usbEngine 1fusbf_top Figure 11 11 Timing Paths Displayed in Schematic View PlanAhead User Guide www xilinx com 353 UG632 v13 4 January 18 2012 XILINX perform one of the following page 136 ew Select one or more primitives from the Netlist view or the Schematic view a placed logic element in the Device view or a Pblock instance from the Device view or the Physical Properties view You can also select these objects in some combination 1 popup commands in the Schematic view let you make direct assignment to Pblocks in the device view For more information about Schematic expansion and traversal commands see Using the Schematic Vi For example if you select an instance or Pblock in the Schematic view all of the nets The Show Connectivity com
61. 11640 62 10 104 360 29 Bonded IPAD 16 38 42 Bonded OPAD 16 24 67 RAMB36E1 108 312 35 FIFO36E1 1 312 1 RAMB18E1 18 312 6 ILOGICE1 40 360 11 OLOGICE1 18 360 5 DSP48E1 100 288 35 GTXE1 8 12 67 MMCM_ADY 4 6 67 Global Clock Buffer 16 32 50 Figure 3 38 Tabular Resource Estimates In some cases links display in the Resources panel to guide you through the commands required for populating the Resources chart For Netlist Estimation a Netlist Design must be open For Implemented Utilization an Implemented Design must be open Implemented Timing Implemented Timing summarizes the overall timing results for an implementation run as shown in Figure 3 39 The Timing Score Minimum Period Maximum Frequency and worst Failing Constraint for the active Implementation run display as well as a link to open the Implemented Design and the Timing Results view For more information about Timing Analysis see Chapter 11 Analyzing Implementation Results Implemented Timing 4 constraints Failed Timing Score 59581 Setup 59415 Hold 166 Component Switching Limit 0 Minimum Period 12 785 ns Maximum Frequency 78 217 MHz Go To Implemented Design Failing Constraints Constraint Worst Slack 1 Endpoint Errors TS_FFtClk PERIOD TIMEGRP fftClk 7 5 ns HIGH 50 1 098 65 TS_wbClk PERIOD TIMEGRP wbCIk 9 ns HIGH 50 0 222 1 amp T5_phy_clk_pad_1_i PERIOD TIMEGRP phy_clk_pad_1_i 11 ns HIGH
62. 15_BLACKBOX 15_LOC_FIXED 15_PARTITION amp _INPUT Attribute Type String Read only No Description Selects the input to the 4 port between parallel input DIRECT or the cascaded input From the previous slice CASCADE NO_RESET DIRECT lo DSP48E1 DSP48E1 o 30 INPUT A429 0 gt lo 1 General Pins Attributes Connectivity Using Common Views Figure 4 57 Properties View Properties View Commands The Properties view toolbar contains a variety of commands depending on the selected object and the specific tabs displayed Some of the common commands are Previous object Displays the properties of the previously selected object as s opposed to the currently selected object You can use this command iteratively to P scroll backward through the selected objects Next object Scrolls forward through the selected objects to display the object gt properties This command is only available after using the Previous object command Automatically update the view when new objects are selected By default the Properties view is updated to display the properties of the latest object as new objects Bg are selected This command toggles the Properties view to auto update as new objects are selected or to remain static displaying the properties of the currently selected object Select Unselect object Select or de select the object reported in the Properti
63. 2 LUT E Slice P 10 TO RAMB36E1 PHE 5 1 1 OLOGICE1 P 9 BSCAN D 250 DSP4SE1 M 332 0 Global Clock Buffer _ 9 d G Implemented Timing WV All constraints were met Minimum Period 7 51 ns PlanAhead User Guide 25 sb Utilization Maximum Frequency 133 156 MHz Go To Implemented Design Figure 3 37 Graphical Resource Estimates The PlanAhead tool populates the Project Summary Resources at each stage of the design process The types of displayed logic objects varies as the design progresses through the design stages As the information becomes available the tabs at the top of the view panel become selectable e RTL Estimation Provides estimates from the RTL Design after the Estimate Resources command has run e Synthesis Estimates Extracts resource estimates from the XST Synthesis report e Netlist Estimation Provides estimates from the Netlist Design after the Estimate Resources command has run e Implemented Utilization Extracts actual resource utilization from the ISE MAP report This requires that an Implemented Design is open www xilinx com 81 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects g XILINX g Resources Show Graph A RTL Estimation Synthesis Estimation Netlist Estimation Implemented Utilization Part xc6vlx7Stff784 3 Resource Utilization Available Utilization Register 15287 93120 16 LUT 19491 46560 42 Slice 7217
64. 2 Use the Select Area command from the side toolbar menu to select multiple sites See Using the Select Area Command in Chapter 4 for more information 3 Select the Set Prohibit command from the right click pop up menu The prohibited sites display a red warning as shown in Figure 10 29 E Project Summary X Device x RTL Schematic x Figure 10 29 Prohibited Sites in the Device View PlanAhead User Guide www xilinx com 337 UG632 v13 4 January 18 2012 Chapter 10 Floorplanning the Design XILINX Interfacing with ISE Outside of PlanAhead The PlanAhead tool lets you selectively export files required for external ISE software implementation If you are using the PlanAhead tool for design implementation you do not need to export files because implementation is done within the tool The PlanAhead tool also enables the creation of a project that is based on existing command line implementation results For more information see Building an Implemented Design with Imported Placement page 344 Exporting Constraints Exporting constraints to ISE consists of exporting a UCF constraints file for the entire design or for individual Pblocks To export the constraints 1 Inthe Sources view select the constraint set to export and click Make Active to set it as the active constraint set 2 Select File gt Export gt Export Constraints The Export Constraints dialog box opens 338 www xilinx com PlanAhead Use
65. 313 UG632 v13 4 January 18 2012 Chapter 10 Floorplanning the Design g XILINX E Project Summary x Figure 10 5 Creating Pblocks with Non Rectangular Shapes 314 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Working with Pblocks Creating Clock Region Pblocks You can define a Pblock to include all resources within a specific clock region or regions To define a Pblock as a clock region in the Device view 1 Draw a Pblock with a rectangle that encompasses the boundary of the clock region The PlanAhead tool displays the clock region boundaries To change the color or display characteristics of the clock region boundaries refer to the Customizing Display Themes in Chapter 4 Figure 10 6 shows a clock region Pblock ees eerrir wry H eee SiS SiSS Si si s0 S Figure 10 6 Creating Clock Region Pblocks The tool tip changes to indicate the Pblock range is a Clock Region 2 In the Set Pblock dialog box select OK to define the Pblock range as the clock region CLOCKREGION_X as shown in Figure 10 7 G Set Pblock Description Which resources do you wish pblock_cpuEngine to constrain Grids CLOCKREGION_X1 4 Figure 10 7 Set Pblock Dialog Box to Confirm Pblock as Clock Region PlanAhead User Guide www xilinx com 315 UG632 v13 4 January 18 2012 316 Chapter 10 Floorplanning the Design g XILINX Note
66. 4 74 Command Options and Description 168 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Configuring PlanAhead 8 Click Apply and OK to save the new strategy The new strategy is listed under User Defined Strategy and can be used for synthesis or implementation as shown in Figure 4 75 O Synthesis Settings i Change synthesis options and launch the run Options Top Module Name bft Part xc6vix75tfF784 3 active Ls Constraint Set faq constrs_1 active z Options amp AreaReduction XST 13 v S User Defined Strategies a S X5ST 13 J my_default_synthesis 2 EEEE Plandhead Strategies XST 13 Ja Plandhead Defaults Aig TimingWithIOBPacking Sig TimingWithoutIOBPacking J AreaReduction ig PowerOptimization A XST Defaults Figure 4 75 Selecting User Defined Strategies Launch Options Language Options Design teams that want to create and share strategies can copy any user defined strategy to the lt InstallDir gt strategies directory where lt Instal1Dir gt is the installation directory Setting Fonts for Text Editor You can define the fonts and colors used by the Text Editor You can specify a different font size and color for different elements of a text file such as comments and keywords Figure 4 76 page 170 shows the effect of changing the comment font to green text PlanAhead User Guide
67. 763 phy_clk_pad_0_i_BUFGP top Global 3748 phy_clk_pad_1_i_BUFGP top Global 3748 rst_GND_307_o_AND_448_of or1200_genpc Local 1 usbClk_BUFGP top Global 1494 wbClk_BUFGP top Global 1432 Carry Statistics Number of carry chains Longest chain 464 cpuEngine cpu_dbg_dat_i buffer_fifo Mcount_rd_addr_tmp_cy lt 0 gt Figure 7 4 Netlist Resource Statistics Viewing Resource Statistics for Pblocks The PlanAhead tool provides logic utilization statistics for Pblocks that can help determine if enough device resources are contained in the Pblock area to satisfy the assigned logic Also the ROOT Pblock is considered the top of the design and can provide utilization statistics for the entire design To display utilization statistics for a Pblock 1 Select either the ROOT Pblock or any Pblock in the Physical Constraints view Figure 7 5 shows a selected ROOT Pblock a e 5 netlist_1 2 9 B pblock_usbEngined E pblock_usbEngine1 amp Sources DI Netlist Timing Constraints Figure 7 5 Physical Constraints View with ROOT Selected The Pblock Properties display in the Properties view 2 If the Pblock Properties do not display right click ROOT or Pblock and select Pblock Properties from the popup menu For more information refer to Viewing Pblock Properties in Chapter 10 PlanAhead User Guide www xilinx com 211 UG632 v13 4 January 18 2012 Chapter 7 Netlist Analysis and
68. 892 usbEngineO usbEngine0 5 949 2 563 3 386 43 1 56 9 6 usbClk BUFGP usbClk E G TRCE impl_1 420 paths a TRCE results_1 420 paths x E Tcl Console Messages E Compilation 3 Reports Design Runs D I O Ports Timing Figure 11 6 ISE TRACE Timing Results Timing results from the TRACE software are different from the results of the Report Timing command available for use with Netlist Designs as described in Analyzing Timing Results page 228 The TRACE results report the exact timing information of the placed and routed design The PlanAhead tool only estimates the routing delays in its timing analysis When you read in the TRACE timing report the nets and primitives from the timing report are correlated to the netlist database in PlanAhead for cross probing and analysis If primitives BELs from the timing report cannot be directly correlated to primitives in the netlist they are not displayed in the timing report and the delays are associated with primitives that PlanAhead does find The timing delays from TRACE are preserved in the accumulated delay of the timing report in PlanAhead Note SE can optimize and change logic to optimize and improve placement and routing results When this happens logic in the original netlist might be removed or replaced This causes a mismatch between the pre Ilmplementation netlist opened in the PlanAhead tool and the timing results returned by TRACE These discrepancies do n
69. Constraint Definition XILINX Using the Statistics Tab The Statistics tab displays design information that includes overall device utilization for the various device resources carry chain count and max length RPM count maximum sizes clock names and clocked instance count I O utilization signal and primitive instance counts Figure 7 6 provides an example of the Statistics tab Physical Resource Estimates Site Type LUT FD_LD SLICEL SLICEM BSCAN BUFGCTRL BUFHCE BUFIODQS BUFR CAPTURE CFG_IO_ACCESS DCI DCIRESET DNA_PORT DSP48E1 EFUSE_USR FRAME_ECC GTXE1 IBUFDS_GTXE1 ICAP IDELAYCTRL ILOGICE1 IODELAYE1 MMCM_ADY OLOGICE1 PCIE_2_0 PMVBRAM PMVIOB RAMBFIFO36E1 STARTUP SYSMON TEMAC_SINGLE USR_ACCESS lt Mi General Statistics Instances Rectangles Attributes Available 46560 93120 7460 4180 4 32 72 36 18 Required 2087 1374 335 188 an oooo ccc cc 0c 0c 0c COC 4B oO oO oO oO oO oO oO ON o a oo Oo oO oO oO oo ls ol aan a N Q m ooocorov co cc cc cc coco Co oO 0 gt v Figure 7 6 Pblock Properties Statistics Tab 212 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Viewing and Reporting Resource Statistics Exporting Resource Statistics Reports You can save displayed resource statistic data to a spreadsheet file The PlanAhead tool generates a hierarchical style report in which you can de
70. Constraint Set E constrs_1 active Options ISE Defaults ISE 13 v e Launch Options Launch with 2 jobs on local host X5JRANDYH O e Specify Partitions wbArbEngine Implement usbEngine0 Implement usbEngine1 Implement e Figure 9 3 Implementation Run Settings Dialog Box The Implementation Settings dialog box options are e Constraint Set Select or accept the constraint set See Managing Constraints in Chapter 3 for more information Options Select the implementation strategy to use for the run Click the file browser button to open the Design Run Settings dialog box to modify ISE command line options Figure 9 4 page 294 shows the Design Run Settings dialog box For more information about setting specific ISE command line options see the Command Line Tools User Guide UG628 cited in Appendix E Additional Resources e Launch Options Specifies how to launch the implementation run See Configuring Implementation Launch Options for more on this form e Specify Partitions This field only appears when partitions are defined in the design See Chapter 13 Using Hierarchical Design Techniques for more information on using partitions e Run Click Run to launch the run with the current settings PlanAhead User Guide www xilinx com 293 UG632 v13 4 January 18 2012 Chapter 9 Implementing the Design g XILINX e Save Click Save to save the settings without starting the run e C
71. Device and Package view as shown in Figure 4 17 or the Device and Clock Resources view to permit better interaction between the two views B Goch Remurcer x Oevee x Wrakee x Ero iarewy x Figure 4 17 Splitting the Workspace to Display Device and Package Views You can split the workspace by either of the two following methods e Use the New Horizontal Group or New Vertical Group commands from the popup menu These commands are available in the workspace views only e Select the tab of an open view and drag it to the very far right scroll banner of the workspace A grey rectangle displays where the view can be placed Position the cursor so that the workspace view arrangement is as desired and release the mouse to move the view and split the workspace This same technique works with many of the views PlanAhead User Guide www xilinx com 105 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment g XILINX Merging Split Views If you split the workspace views you might need to merge the views to better utilize the available viewing area To collapse the views back into one tabbed area do one of the following e Select Move to Previous Tag Group or Move to Next Tag Group from the popup menu in a workspace view e Select any view and drag it onto the view tab of another The dragged grey rectangle displays around the entire view showing how the windows will merge Using Tree Table Style Views The Pl
72. Error Standard VRN can be used as regular IOs also If a DCI I O standard is used in VRP Occupied that bank these IOs should be left unoccupied Inconsistent Diff DIFFISTD Checks that the terminals of a differential pair have the same I O Error pair I O standard Standards Inconsistent Diff DIFFISTDDrv Checks that the terminals of a differential pair have the same drive Error pair I O Standards Inconsistent Diff DIFFISTDSlew Checks that the terminals of a differential pair have the same slew Error pair I O Standards Vccaux Voltage VCCAUX1 Warns of any requirements on for LYCMOS25 Warning requirement Vccaux Voltage VCCAUX2 Warns of any requirements on LVPECL_33 and TMDS_33 Error requirement ChipScope DRCs Table B 19 lists the ChipScope DRCs abbreviation intent and severity Table B 19 ChipScope DRCs Rule Name Rule Abbrev Rule Intent Severity Unconnected CSUC Checks for unconnected channels Error channel Clocked by CSCL Checks for non clock net connected to debug clock port Warning non clock net Device block CSBR Checks if device has sufficient block RAM resources to implement Warning RAM ChipScope debug cores PlanAhead User Guide www xilinx com 429 Appendix B PlanAhead DRCs XILINX 430 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Appendix C Installing Releases with XilinxNotify PlanAhead Release Strategy The PlanAhead application is targeted to introduce new
73. From the Following two ports Positive End gt QDRO_DIN O Negative End gt QDRO_DIN 1 EA Swap i Cancel Figure 8 14 Make I O Diff Pair The two I O Ports display in the dialog box with initial Positive End and Negative End definitions e To reverse the Positive End and Negative End signals click Swap e To remove the differential pair definition on any differential pin pair select Split Diff Pair Configuring DCI_CASCADE Constraints You can configure the DCI_CASCADE constraint for the following devices e 6Virtex 5 e Virtex 6 e Virtex 7 e Kintex 7 e Artix 7 About the DCI_CASCADE Constraint The DCI_CASCADE constraint links two or more adjacent I O Banks together for DCI reference voltage purposes The I O bank with the DCI reference voltage is the master All other I O banks are slaves All banks in a cascade must be in the same column of the device To set the constraint e Pre select the I O banks before running the command or e Select the I O banks in the command dialog box For more information about the DCI_CASCADE constraint see the Constraints Guide UG625 cited in Appendix E Additional Resources Creating a DCI_CASCADE Constraint To create a DCI CASCADE constraint 1 Select the I O banks to configure 2 Select Create a DCI Cascade from the popup menu The DCI Cascade Editor opens www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILI
74. Instances in the Find field and define the criteria as needed to locate the specific logic instance or instances of interest 3 Use the Find Results view to drag logic instances onto the Clock Resources or the Device view to assign to the appropriate device resource Refer to Using the Find Results View in Chapter 4 for more information on using Find You can also locate physical resources on the device such as Global Clock Buffers BUFGCTRL for placing logic instances Specify Sites in the Find field and define the criteria as needed Use the results in the Find Results field to highlight the physical device resource in the Clock Resources view or the Device view Using the Clock Resources View PlanAhead User Guide The Clock Resources view supports the Virtex 6 Virtex 7 Kintex 7 and Artix 7 devices showing the relationship and interactions between regional and global clocking resources BUFRs BUFIOs BUFGs MMCMs and G s The spreadsheet like interface of the Clock Resources view lets the PlanAhead tool display a simplified view of the device resources while maintaining proper relative positioning between these resources Most of the details of the FPGA device shown in the Device view are not shown in the Clock Resources view Figure 8 25 page 277 displays the Clock Resources view for a Virtex 6 LX75 device The Clock Resources view interface shows that e The device has six clock regions arranged in a 2x3 matrix
75. Interface always posedge wb_clk or posedge wh_reset begin if wb_reset 1 begin wh_ack_o 1 0 wb_dat_o 1 0 control_reg 1 32 h0 data_reg 1 127 h0 data_o 1 127 h0 end else begin if ready_i begin control _reg 1 lt 1 1 b1 data_reg lt 1 data_i end Q Search command Implementation Failed Compiler 1127 Line 534 Assignment to data_o ig ine HDLCompiler 413 Line 619 Result of 2 bit expression is truncated to fit in 1 bit target Figure 9 14 Error Navigation to RTL Sources Select any message and use the Search for Answer Record popup menu command to search the Xilinx Customer Support database for related answer records PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 299 Chapter 9 Implementing the Design g XILINX Selecting the Step After Implementation After the run is complete a dialog box opens that prompts you to take the next step shown in Figure 9 15 Implementation Completed e l1 Implementation successfully completed Promote Partitions Generate Bitstream View Reports C Don t show this dialog again Figure 9 15 Implementation Completed Successfully Dialog Box In the Implementation Completed dialog box select the option then click OK e Open Implemented Design Imports the netlist active constraint set ISE placement and timing result
76. LVCMOS18 Output 1 8 14 High Performance Multi Function L4P DataOut_pad_0_o 7 LVCMO518 Output 1 8 14 High Performance Multi Function L4N DataOut_pad_0_o 4 LVCMOS518 Output 1 8 14 High Performance Multi Function LSP DataOut_pad_0_o 5 LYCMOS18 Output 1 8 14 High Performance Multi Function LSN DataOut_pad_0_o 2 LVCMOS18 Output 1 8 14 High Performance Multi Function L6P DataOut_pad_0_o 3 LYCMOS18 Output 1 8 14 High Performance Multi Function L6N DataOut_pad_0_o 0 LVCMOS18 Output 1 8 14 High Performance Multi Function L7P DataOut_pad_0_o 1 LVCMOS18 Output 1 8 14 High Performance Multi Function L7N DataIn_pad_1_i 3 LYCMOS18 Input 1 8 14 High Performance Multi Function L amp P DataIn_pad_1_i 4 LVCMO518 Input 1 8 14 High Performance Multi function LEN DataIn_pad_1_i 1 LYCMOS18 Input 1 8 14 High Performance User IO L9P DataIn_pad_1_i 2 LVCMO518 Input 1 8 14 High Performance Multi Function LON Figure 4 66 Package Pins View Device pin information such as I O Bank number Bank Type Differential pair partners Site Types and Min Max package delay are listed for each package pin The Bank Type column identifies the HP HR banks of the Virtex 7 Kintex 7 and Artix 7 devices Table values appear as follows e Gray for default values e Black for non default values e Red for illegal values Note The unit of measurement for the Min Max package trace delay in the Package Pins view is in picoseconds ps You can sort the information in the Packag
77. Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul Severity Details Q results_1 224 violations x Tel Console Messages Cal Compilation DRC Results Design Runs RTL Flow Figure 7 34 DRC Results You can also toggle the Hide warnings and informational messages button in the toolbar menu to turn off warnings and informational messages to see only the errors reported You can also click on the header of the Severity column of the DRC Results view to sort violations by severity e Click once on the column header to sort in an increasing order e Click twice to sort in a decreasing order See Using Tree Table Style Views page 106 for more information When you select a violation message in the DRC Results view you can select Violations Properties in the popup menu to open the Violations Properties view This view shows both a general review of the DRC rule violation and specific details of the design elements that violate the rule The Details tab of the Violations Properties can have links to specific design objects that violate the DRC These links can be clicked to view the design object in the Netlist view the Device view the Schematic or the source RTL file Appendix B PlanAhead DRCs lists the PlanAhead DRCs 250 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Chapter 8 I O Pin Planning The I O Planning view
78. Mode Suppresses messages in the timing report regarding errors in command options Understanding the Timer Settings Tab The Timer Settings tab of the Report Timing dialog box contains fields that allow the designer to specify the delays parameters used by the timing engine in generating the timing report Figure 7 16 page 227 shows the Timer Settings tab 226 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX PlanAhead User Guide Running Timing Analysis G Report Timing Results Name results _1 Targets Options Advanced Interconnect estimated Y Speed Grade 3 default v Multi Corner Configuration Corner Name Delay Type Slow min_max Y Fast minimax Y Enable timing pessimism removal Command report_timing from get_pins SuspendM_pad_1_o C Control_pa Open in a new tab Figure 7 16 Report Timing Timer Settings Tab The options are Interconnect Selects the type of delay values used for the interconnect delay The different delay values are as follows e Estimated Uses estimated delays for the interconnect values e None Sets the interconnect delays to 0 Speed Grade Selects the speed grade of the device used in the timing analysis This field allows the estimation of design timing using different device speed grades Multi corner analysis Multi corner analysis simultaneously uses different process and operating condition corner
79. Os Bundle Nets gt a Figure 4 71 PlanAhead Options Save Theme As Dialog Box If you create your own theme it is prudent to back up the initialization file that contains the custom settings For detailed information about the default and custom initialization files for the PlanAhead tool see Outputs for Environment Defaults in Appendix A Setting Selection Rule Options Selection rule options control the object selection settings for all views When you select an object other objects can become selected also for example selecting a Pblock also selects the assigned netlist instances For more information on setting selection rules see Setting Selection Rules page 111 Configuring Shortcut Keys Most commonly used commands have pre defined shortcuts using keyboard key combinations The shortcuts defined display next to the command in the popup menu For example press F9 to access the Fit Selection command You can modify the default shortcut values by using the Shortcuts option of the PlanAhead Shortcut Options dialog box which is shown in Figure 4 72 page 166 PlanAhead User Guide www xilinx com 165 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment g XILINX G PlanAhead Options Shortcuts Plan head Default Filter Q Name Shortcut Description gja All Actions Main Menu Main Menu Shortcuts Code Editor Code Editor Shortcuts Selection Rules Device V
80. PM File folde d blockdiagram 1 29 2010 11 29 AM File folde d data 10 1 2010 1 23 PM File folde d etc 10 1 2010 1 24 PM File folde hdl 10 1 2010 1 25 PM File folde d implementation 10 1 2010 1 56 PM File folde d pcores 29 2010 11 27 AM File folde d synthesis 10 1 2010 1 36 PM File fold system bsb i XpsGuiSessionLock system make 10 1 2010 2 14 F system_inclmake 10 1 2010 2 14 PM system mhs system mss platgen opt _ clock_generator_0 log platgen log system log 10 1 2010 2 14 PM systemxmp 10 1 2010 1 25 PM nx Platform Studio Project temp_spi_lowlevel_design xml 10 1 101 PM MLC Figure 3 32 Example Directory Structure The four directories you need to be familiar with are the data etc hd1 and implementation directories These directories contain the files needed to include your design into PlanAhead Note If these directories do not exist you need to run Hardware gt Generate Netlist in XPS This synthesizes the embedded processor system components and creates the needed files The files that are important to understand in each of the four directories are 72 data system ucf Ifthe embedded system was originally created using the Base System Builder this UCF file includes the PIN and I O Standard assignments as well as timing constraints etc fast_runtime opt This file contains the implementation options used to implement the embedded processor system hdl system_stub vhd or system_
81. PlanAhead ISE and ChipScope Pro must be used with this flow Mixing and matching versions is not supported This flow is not available with the Project Navigator or the ChipScope Pro Core Inserter flow However you can import ChipScope Debug Cores CDC into PlanAhead This flow is not available when PlanAhead is launched from ISE Project Navigator You can view but not change pre existing debug cores connected to a ChipScope Pro Integrated CONtroller ICON core This flow is not compatible with a pre existing ICON core that was generated without a BSCAN primitive and that requires connection to a BSCAN primitive instantiated outside of the core Because the PlanAhead tool adds debug cores to the post synthesis design netlist some nets might be unavailable for debugging due to trimming or other optimization that takes place during the synthesis process Only ChipScope Pro ILA cores can be created and connected using this flow Using the Core Insertion Flow Insertion of ChipScope debug core in the PlanAhead tool is presented in a layered approach to address different needs of the diverse group of PlanAhead users PlanAhead User Guide The highest level is a simple GUI wizard that creates and configures ILA cores automatically based on the selected set of nets to debug The next level is the main ChipScope view allowing control over individual cores ports and their parameters The ChipScope view can be displayed by selecting t
82. Planning Post Synthesis PlanAhead User Guide Note Whenever possible I O pin planning should be performed after logic synthesis The presence of a netlist ensures that the clocks clock logic differential pairs GTs and so forth are recognized and considered automatically during pin assignment in PlanAhead There are also many Design Rule Checks DRCs that are performed based on logic connectivity and clocks to ensure a legal placement prior to Implementation To perform I O pin planning in Project Navigator after running logic Synthesis e Inthe Processes pane expand User Constraints and double click IO Planning PlanAhead Post Synthesis or e Select the Tools gt PlanAhead gt Post Synthesis IO Pin Planning command When you invoke the PlanAhead tool Project Navigator passes the synthesized NGC or EDIF format netlist and the UCF s to the project The PlanAhead tool opens with a display of the default I O Planning view layout and the I O ports display in the I O Ports view When you save or close the PlanAhead tool project it updates the original Project Navigator source UCF s and this resets the Project Navigator design process state if appropriate Refer to Passing Logic and Constraints page 404 for more information about the integration mechanics and process Refer to Chapter 8 I O Pin Planning for more information about using the I O pin planning environment www xilinx com 405 UG632 v13 4 January 18 2
83. Power q Child Power mw Logic BRAM DSP48 Haraip dma_out 5 1 5 0 0 ud 2 2 0 0 0 ul 5 5 0 0 0 u2 1 1 0 0 0 u4 3 3 0 0 0 u5 1 1 0 0 0 usbEngineSRAM 83 1 83 0 0 usb_dma_wb_in 5 1 5 0 0 usb_in 2 1 2 0 0 usb_out 5 1 5 0 0 Primitives 1 1 0 0 0 Total 110 11 99 0 0 4 gt 0 General Statistics Pins Children Attributes Connectivity Partition Figure 5 9 Instance Properties with Power Table To document your project or share information with other member of the team use the Export Statistics icon in the Netlist Properties toolbar or for tabular information select Export to Spreadsheet from the right mouse menu to export the data for use in other tools for further analysis or reports You can also specify output text or XML files from the Power Estimation command when you run it from the Tcl Console as the report_power command For more information about the options for this command see the PlanAhead Tcl Command Reference Guide UG789 cited in Appendix E Additional Resources When you click Export Statistics the Export RTL Instance Statistics dialog box displays where you can select a format Text XML or CSV Performing Behavioral Simulation The PlanAhead tool is integrated with the ISE Simulation tool ISim Xilinx Sim is a Hardware Description Language HDL simulator that lets you perform behavioral and timing simulations for VHDL Verilog and mixed VHDL Verilog designs You can launch ISim by se
84. Refer to Managing Project Sources page 50 for more information Note Module level Netlist Constraints File NCF show as design sources adjacent to their associated cores and are read only To open the Sources view e Select Windows gt Sources or e Click the Sources button on the toolbar menu amp Figure 4 39 page 123 shows an example of the Sources view 122 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using Common Views a mw ote 3 5 Design Sources 10 9 Verilog Header 4 JAR top top v 6 H S mgtEngine mgtTop matTop 21 B fftEngine FftTop FFtTop v 1 E D FFtInst bft aBFT bit v hdl 6 GS 8 arndi round_1 aR1 round_1 vhdl 1 i ct coreTransform aCT core_transform y arnd2 round_2 aR2 round_2 vhdl 8 g arnd3 round_3 aR3 round_3 vhdl 2 S arnd4 round_4 aR4 round_4 vhdl 1 inagressFifo FifoBuffer FifoBuffer v 1 egressFifo FifoBuffer FifoBuffer v 1 iF buffer_Fifo async_fifo as cpuEngine or1200_top ori 200_top 8 cpu_iwb_dat_i FifoBuffer F cpu_iwb_dat_o FifoBuffer Fif 88 cpu_dwb_dat_i FifoBuffer FiF 6 cpu_dwb_dat_o FifoBuffer FifoBuffer cpu_iwb_adr_o FifoBuffer Fif cpu_dbg_dat_o FifoBuffer Fif 6 cpu_dbg_dat_i FifoBuffer FifoBuffer v 1 iwb_biu or1200_iwb_biu or1200 _wb_biu G dwh hin ort 200th hin fort 200 wih hin s
85. Results Name results_1 Targets Advanced Timer Settings Report Path delay type LEEA EEES Path report format full_clock_expanded_ v C Do not report unconstrained paths Path Limits Number of paths per group Number of paths per endpoint Limit paths to group Path Display Display paths with slack greater than Display paths with slack less than Significant digits Sort paths by slack v Command report_timing delay_type max path_type full_clock_expanded J Figure 7 14 Report Timing Options tab The fields available in the Report Timing Options tab are Path Delay Type Specifies the type of delays that are used in the timing report path analysis Accepted values are min min_rise min_fall max max_rise max_fall and min_max A rising or falling path delay refers to the transition at the timing path endpoint Path Report Format Specifies the type of timing report to be generated In many cases the format of the GUI timing report and written timing report are different based on the selected option This field contains the following values End Specifies an endpoint report that contains only slack and endpoint information for each path in the written timing report Full Specifies a timing report that contains full path details for the datapath and hides the details of the clock path s Full_Clock Specifies a timing report that con
86. SDK select Xilinx Tools gt Program FPGA to open the Program FPGA dialog box shown in Figure 3 35 page 79 This lets you select both the bitstream and BMM file 78 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using the Project Summary view Program FPGA Program FPGA Specify the bitstream and the ELF files that reside in BRAM memory Hardware Configuration Hardware Specification C Data Xilinx Documents XAPPs PlanAhead XPS_App_Note test_design Embedded_Design SDK SOK_Workspace_35 hw_plationn_O systemam Bitstrear C Data Glin _Documents XAPPs PlanAhead_ XPS App Note test_design PlanAhesd_ Design project_I peopect_1 runs impl_1_4 system_stub bit Browse BMM File C Data Xilira_Docurnents XAPPs PlanAhesd XPS App Note test_design Embedded _Designumplementatonisystem_stub_bd bmm Software Configuration Processor ELF File to Initialize in Block RAM microblare 0 bootloop Program Cancei Figure 3 35 SDK Program FPGA By default the SDK project points to the SDK_Workspace directory You must locate the files generated by the PlanAhead tool when creating the bitstream The PlanAhead tool bitstream is found in the following directory lt project_name gt project_1 runs lt impl_run_name gt Where project_name is the name of the PlanAhead project and imp1_run_name is the name of the specific implementation run used to implement the design and generate the bitstream When the bitstr
87. See Running WASSO Analysis page 289 for more information Enter a name in the Results Name field to identify the results in the SSN Results view Click the Export to File checkbox and enter an output file name in the Output File field or browse and select a location to write an external CSV format report file then click OK A Noise v Margin v sa Name Port IO Std Ycco Slew Drive Strength Phase Ps Contributed Bank Total Available Rer v 1 0 Bank 0 Dedic wey IJO Bank 14 5 0 v 1 0 Bank 15 Standard 5 LYCMOS25 2 5 SLOW 12 default 0 104 0 35 I l Group 1 5 LYCMOS25 2 5 SLOW 12 default 0 1036817 0 104 0 35 P N24 OpMode_pad_1_o 1 L CMOS25 2 5 SLOW 12 default P N25 or1200_pm_out 0 LYCMOS25 2 5 SLOW 12 default P N23 or1200_pm_out 1 LYCMOS25 2 5 SLOW 12 default P N21 or1200_pm_out 2 LYCMOS25 2 5 SLOW 12 default P P23 or1200_pm_out 3 LYCMOS25 2 5 SLOW 12 default aV IJO Bank 16 Standard 0 V I O Bank 24 Standard 7 LYCMOS25 2 5 SLOW 12 default 0 124 0 35 E results_1 11 of 11 Banks Passed x B Tel Console O Messages al Compilation Reports Design Runs gt I O Ports G Timing Results id SSN Results Figure 8 32 SSN Results View Viewing the SSN Results After the analysis is complete the SSN Results view opens as shown in Figure 8 32 displaying the following information e Name Displays the I O Banks available in the device Each I O bank
88. Table A 5 lists the created directories and files for behavioral and timing simulation Runs Table A 5 Behavioral and Timing Simulation Files and Directories File Directory Name Description Simulation Type fuse log Fuse execution log file Both fuse xmsgs Fuse execution log file in XML format Both fuseRelaunch cmd Batch commands for ISim passed under the banner Both and ISim cmd of tclbatch when tclbatch is NOT specified ISim log ISim execution log file Both top exe ISim simulation executable created by fuse from the Both top level module specified on the Simulation Launch dialog box name varies based on the name of the top module top prj PlanAhead project file containing the top level Both design top wdb Waveform database file created by ISim Both top_timing_sim nlf NetGen execution log file Timing top_timing_sim sdf DF delay file output from netgen for use in timing Timing simulation top_timing_sim v Verilog netlist output by Netgen used in Timing Timing simulation could be a VHDL file based on the specified ofmt option xilinxsim ini File containing logical to physical mappings of Both libraries ISim Directory containing the Both isim_usage_statistics htn file ISim work Directory containing the g1b1 sdb and top sdb Both files ISim top exe sim Directory generated by fuse to store object code and Both data files for each design unit comprising the design Co
89. The Pblock rectangle must encompass the clock region boundary to enable the CLOCKREGION option in the Set Pblock dialog box When you de select CLOCKREGION_X you can define the Pblock using traditional logic based ranges Note You can toggle the two types of Pblocks by selecting or deselecting CLOCKREGION in the Set Pblock dialog box or in the Pblock General Properties view The Pblock clock region coordinates display in the Pblock General Properties view Understanding Pblock Graphics The default display options show the Pblock and the instances assigned to the Pblock e The outer rectangle is the Pblock border e The rectangles contained inside the Pblock are the assigned netlist instances You can place multiple instances into a Pblock and instance rectangles displayed inside the Pblock are sized based on the amount of logic they contain relative to the other instances in the same Pblock If many instances are assigned to a Pblock they might appear as lines instead of rectangles as shown in Figure 10 8 TIMP LIITES ILILLIT IIT LLI IIIT ET LI LLT LELI LLIE TE L LLLE D Figure 10 8 Pblocks With Assigned Instances Displayed Graphically Using the default selection rules selecting the Pblock rectangle selects all of the netlist instances contained in it also You can drag and assign Instances into other Pblocks To modify Selection Rules for the tool select Tools gt Options then choose Selection Rule
90. The PlanAhead Metrics view displays a list of design metrics that you can display using a colored graph of the potentially troublesome areas in the design The metrics include utilization routing congestion and timing checks at the Pblock and implemented design level To open the Metrics view select Window gt Metrics Figure 11 15 shows the Metrics view a amp ay Primitive Metrics 1 amp Min Slack per placed BEL CLB Metrics 4 w LUT Utilization per CLB FF Utilization per CLB gt i vertical routing congestion per CLB i a Horizontal routing congestion per CLB Pblock Metrics 6 gt LUT Utilization per Pblock a FF Utilization per Pblock a Estimated Slice Utilization per Pblock w Min Slack per Pblock i Total Negative Slack per Pblock i a Pblock boundary crossing net count Netlist Physical Constraint amp Timing Constraints Figure 11 15 Metrics View The Metric Properties view provides a description of the selected Metric function along with the bins defined to highlight potential problems as shown in Figure 11 16 page 359 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Displaying Design Metrics RAA NEEE a FF Utilization per CLB Summary of FF resources consumed by LOC Constraints Details Helps to visualize FF densities of your placed design Bins Id From To Show Color a o mm 255 255 255 2 70 85 M C0 255 255 153 3 85 100 M E 25
91. The constraints display in two different ways by type or as a list As shown in Figure 7 10 constraints are sorted by type allowing expansion and collapsing of the constraint types Notice that the number of defined constraints of each type displays in parenthesis PlanAhead User Guide www xilinx com UG632 v13 4 January 18 2012 217 Chapter 7 Netlist Analysis and Constraint Definition g XILINX 218 To view all currently defined timing constraints as a list disable the Group by type button in the Timing Constraints view E You can modify the values of defined constraints by selecting a constraint in the upper half of the Timing Constraints view and editing the values of the constraint in the lower half of the view as shown in Figure 7 10 page 217 The attributes of the constraint that can be changed are displayed in editable fields Click Apply to save changes to modified constraints values Adding New Timing Constraints 1 Open the New Timing Constraints dialog box using one of the following methods e From the main menu click Tools gt Timing gt New Timing Constraint e Inthe Timing Constraints view click the New Timing Constraint button G The New Timing Constraint dialog box opens as shown in Figure 7 11 G New Timing Constraint Constraint Types Basic period Timespec period Clock net iphy_clk _pad_0_i Derived period amp Input pad to clk offset 3 amp Clk
92. This analysis provides less detail than the SSN analysis offered for the Spartan 6 Virtex 6 Virtex 7 Kintex 7 and Artix 7devices but provides some understanding of the switching noise for Spartan 3 Virtex 4 and Virtex 5 devices 1 To run a WASSO analysis select Run Noise Analysis from either the Flow Navigator or from the Tools menu The Run WASSO Analysis dialog box opens as shown in Figure 8 35 Note Run Noise Analysis runs either SSN or SSO analysis based on the target Xilinx device The dialog box that opens depends on the type of analysis the PlanAhead tool performs See Using Noise Analysis Predictors page 283 for more information Use the Output File field to specify a report file name and a location to write to disk 3 Tool tips appear when you drag the cursor over each of the entry fields that indicate what values to enter You can modify the device and board parameter values to reflect your specific design G Run WASSO Analysis Results Name lresults_1 i Output File Device Parameters Maximum ground bounce fm Capacitance per output driver pF Board Parameters Board Thickness mils Finished via diameter mils Pad to via breakout length mils Breakout width mils Other PCB parasitic inductance nH Socket inductance nH ij Cancel Figure 8 35 Run WASSO Analysis Dialog Box PlanAhead User Guide www xilinx com 289 UG632 v13 4 January 18 2012 Chapter
93. Up Down Sort Arrows To add a second sort criteria from a second column press Ctrl and click the header of a second column In the example in Figure 4 21 the Voltage column is the primary sort criteria and the Clock column is the secondary sort criteria Add additional columns as needed to refine the sort Press Ctrl and click the column header again to remove a sort from a column from the sort criteria Organizing Columns You can move hide and restore columns e To move a column select it and drag it into a new location e To hide a column select it and use the popup menu in the column header to select Hide This Column The popup menu also enables quick view configuration for each column PlanAhead User Guide www xilinx com 107 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX e Adjust the width of the columns per the displayed data using the Auto Resize Column command e Restore the defaults using the Reset to Default command Using View Specific Toolbar Commands Most views provide toolbar buttons within the view to operate commands specific to that view as shown in Figure 4 22 Figure 4 22 Device view Toolbar Menu These buttons become enabled only when certain data is selected or commands are active The PlanAhead tool features are made available through these view specific toolbar buttons so it is beneficial to become familiar with them These view specific commands are c
94. User Guide UG632 v13 4 January 18 2012 g XILINX Configuring Pblocks Using Resource Utilization Statistics to Shape Pblocks You can use the utilization estimates in the Pblock Properties view to size and place Pblocks The tool estimates resources required by the logic assigned to the Pblock and compares that against available device resources to compute utilization estimates To display the utilization estimates for a Pblock 1 Select the Pblock and view the Pblock Properties 2 Click the Statistics tab shown in Figure 10 14 e Balt pblock_usbEngine1 Physical Resource Estimates Site Type Available Required o Util LUT 7040 6120 FD_LD 14080 4701 SLICEL 1080 939 SLICEM 680 592 RAMBFIFO36E1 24 36 lt General Statistics Instances Rectangles Attributes Figure 10 14 Pblock Properties View Statistics Tab 3 Inthe Statistics tab view the utilization estimates columns e Available Displays the number of available sites in the Pblock e Required Displays the number of sites required by the assigned logic e Utilization Displays the estimated utilization percentage for each logic type The appropriate utilization can be met by resizing the Pblock If utilization for logic objects is over 100 the text appears in red as shown in Figure 10 14 4 Scroll down to view the required RAM sites for the Pblock The Pblock Properties view is dynamic and updates each time you modify the Pb
95. User Guide www xilinx com 201 UG632 v13 4 January 18 2012 202 Chapter 6 Synthesizing the Design XILINX The Synthesis Settings dialog box options are Top Module Name Enter or accept the top level RTL module name for the design Constraint Set Select or accept the constraint set See Managing Constraints in Chapter 3 for more information Options Select the strategy to use for the synthesis run Click the file browser button to open the Design Run Settings dialog box to modify XST command line options for the run Figure 6 4 shows the Design Run Settings dialog box Launch Options Specifies how to launch the synthesis run See Synthesis Launch Options for more on this form Language Options Specifies the Verilog or VHDL language options See General Project Settings in Chapter 3 for more information on setting language options Specify Partitions This field only appears when partitions are defined in the design See Chapter 13 Using Hierarchical Design Techniques for more information on using partitions Click Run to launch the run with the current settings Click Save to save the settings without starting the run Click Cancel to close the form without saving G Design Run Settings Strategy fast_area_reduction XST 13 Description Based on Area Reduction opt_mode speed gt opt_level 2 register_balancing Forward Fsm_encoding auto Ic auto au
96. Utilization on All Pblocks Figure 10 20 Place Pblocks Dialog Box e Set Utilization on all Pblocks Specifies a new SLICE utilization target for listed Pblocks Setting this option overrides any individual utilization values you might have modified previously Use this option to specify the preferred value for all Pblocks then modify the Utilization of any specific Pblock as needed 3 Click OK to place Pblocks in the design A Place Pblocks progress meter displays while the Place Pblocks command is running The Pblocks are sized and placed automatically based on SLICE utilization only For instructions on creating top level floorplans using Create Pblocks and Place Pblocks see the PlanAhead Tutorial Design Analysis and Floorplanning UG676 cited in Appendix E Additional Resources Working with Placement LOC and BEL Constraints You can assign primitive logic elements to specific logic sites using either Create Site Constraint Mode or Create BEL Constraint Mode PlanAhead uses LOC constraints to assign logic elements to a specific SLICE and to restrict placement to the available resources within the SLICE and uses BEL constraints to place a logic instance on a specific site in the SLICE LOC applies generally to a SLICE while BEL targets a specific site Understanding Fixed and Unfixed Placement Constraints PlanAhead User Guide The PlanAhead tool differentiates between logic placement assigned interactively by the user
97. Views page 106 Filtering and Grouping Compilation Messages You can use select to display Errors Critical Warnings Warnings and Informational Messages in the Messages view by selecting the appropriate checkbox in the banner as shown in Figure 9 13 page 299 298 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Analyzing Implementation Run Results A a S V 2 errors M 1 critical warning 10 547 warnings V 150 info messages o ir Tr ArchReader 3 To clock buffers from C IPlanAhead TInstall planAhead parts xilinx v ArchReader 9 Loading clock placement rules from C Plan4head_Install plan4head part ArchReader 10 Loading clock capable ios from C Plan4head_Install plandhead parts xi ArchReader 13 Loading package pin Functions from C Plan4head_Install plandhead pa Mh Aoh 511 nadine amabam Come M Mlan Ab ned Tob allatam Abn ode ecb a Jilin ke leben Figure 9 13 Messages View Banner The Group duplicate messages button flattens the list and groups similar messages together Selecting any of the messages in the Messages view that have a referenced line number automatically opens the RTL file and highlights that line of source code Figure 9 14 shows an example of the error navigation process G project_cpu_hdl C PlanAhead_Install planAhead testcases PlanAhead_Tutorial Projects project_cpu_hdl project_cpu_hdl ppr PlanAhead 1
98. With Project Navigator for information about ISE Integration mode Input and Output Files The PlanAhead tool accepts a variety of input files and creates a variety of output file types and formats See Appendix A PlanAhead Input and Output Files for descriptions of the input and output files 14 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Launching the PlanAhead Tool Design Rule Checks The PlanAhead tool Design Rule Checks DRCs are listed in Appendix B PlanAhead DRCs PlanAhead Software Terminology For definitions of the terminology used in this Guide see Xilinx Glossary cited in Appendix E Additional Resources Accessing Updates Xilinx uses a XilinxNotify utility that notifies you when there are updates available See Appendix C Installing Releases with XilinxNotify for more information Configuring Multiple Linux Hosts The multiple host capabilities for executing PlanAhead synthesis and implementation runs use the Linux Secure Shell SSH Before configuring multiple hosts in the PlanAhead tool configure SSH so you are not prompted for a password each time you log in toa remote computer For more information see Appendix D Configuring SSH Without Password Prompting Additional Resources Appendix E Additional Resources contains links to all documents referenced in this guide If you are using at a printed copy of this guide the full URL to the referenced document i
99. You can remove previously promoted directories to clean up the Project directories The entire promoted directory is removed including all promoted partitions from the run To delete promoted directories select the promoted directory in the Promoted Partitions view and click the Delete popup menu command 386 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Importing Partitions Importing Partitions After you have promoted partitions you can import those partitions for subsequent runs e For Synthesis importing partitions results in the imported NGC file being copied into the current results directory This ensures the identical synthesis results are used for implementation e For Implementation importing partitions results in the placement and routing being copied out of the promoted partitions run and imported into the new run prior to implementing the rest of the design ensuring identical results Updating Sources Updating RTL Sources When changes are made to RTL sources the RTL and Netlist views as well as any completed Synthesis or Implementation Runs go out of date You can open or reload the RTL and Netlist view to apply the logic changes Updating Netlist Sources As design modifications occur the updated netlists are either picked up automatically if you are using remote sources or updated in the project to update the existing netlists After source files are updated you can open
100. a Top Level Netlist and Module Search Path page 44 Define a default part as discussed under Selecting a Default Part page 42 Figure 3 11 page 47 shows the dialog box that prompts for the ISE implementation results You can import the placement and routing results and timing files generated in ISE The PlanAhead tool then uses these files to create an implemented design for viewing and analysis in the PlanAhead tool www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Creating a New Project G New Project Import ISE Implementation Results Specify placement results NCD and optionally timing results TW From a completed ISE place and route run Placement File NCD Data FPGA_design ise_designs drp_des drp_demo_routed ncd Import Timing TWX C Data FPGA_design ise_designs drp_des drp_demo twx Figure 3 11 New Project Wizard ISE Implementation Results 5 Inthe Import ISE Implementation Results page edit the options e Placement File NCD Select an implemented NCD file to import and the PlanAhead tool automatically converts the file to read the placement information NCD is the output file from the ISE software place and route application PAR e Import Timing TWX Check this option then locate and select a TRACE command output file from the ISE Implementation such as a TWX format file The New Project Summary page displays the various options selected to define t
101. and Constraint Definition e Chapter 11 Analyzing Implementation Results Pin Planning The PlanAhead tool provides an I O Planning view to define and analyze the device I O requirements It supports creating and assigning I O ports to physical package pins This lets you define an I O pinout configuration that satisfies the requirements of both the Printed Circuit Board PCB and the Field Programmable Gate Array FPGA designers Chapter 8 I O Pin Planning contains more information about I O pin planning Floorplanning PlanAhead User Guide The PlanAhead tool supports a floorplanning methodology that lets you group and constrain related logic to ensure shorter interconnect lengths with less delay and to ensure more predictable implementation results You can floorplan a design by creating physical block Pblock locations to constrain logic placement or by locking individual logic objects to specific device sites See Chapter 10 Floorplanning the Design and Floorplanning Methodology Guide UG633 cited in Appendix E Additional Resources for more information about floorplanning www xilinx com 13 UG632 v13 4 January 18 2012 Chapter 1 About the PlanAhead Tool XILINX Programming and Debugging Designs and ChipScope Integration The PlanAhead tool is integrated with the Xilinx ChipScope debugging tool which lets you add debugging cores to your design After implementation you can access the ISE tools to generate bitstream
102. as described in the following sections Analyzing Timing Results Timing analysis of the implemented design being placed and routed includes the actual routed path delays between logic elements or device resources To complete timing analysis of the implemented design you can e Run the Tools gt Timing gt Run TRCE command to access the Xilinx Timing Reporter And Circuit Evaluator TRACE tool for sign off timing analysis See Running TRACE on an Implemented Design for more information e Click the Run TRCE command on the Flow Navigator e Run the Tools gt Timing gt Run Timing command to access the internal timing engine of the PlanAhead tool See Running Timing Analysis in Chapter 7 for more information Running TRACE on an Implemented Design PlanAhead User Guide The TRACE tool provides static timing analysis of an FPGA design based on input timing constraints The TRACE software verifies that the design meets timing constraints and generates a report file that lists compliance of the design against the input constraints As a standalone ISE application TRACE can be run on unplaced designs or placed designs partially routed design and completely placed and routed designs In the PlanAhead tool TRACE can be run on an Implemented Design When an Implemented Design is open in PlanAhead you can launch the TRACE software by e Run the Tools gt Timing gt Run TRCE command e Click the Run TRCE command on the Flow Naviga
103. be passed to the subsequent implementation runs Fixing Specific Types of Logic A method for improving the consistency of implementation results is to lock some or all of the block macro logic such as block RAMs and DSPs You can do this manually in the PlanAhead tool using your own knowledge of the design or by leveraging successful ISE implementation results If your design has many block RAMs or DSPs this method can help produce more consistent results and improve run time PlanAhead User Guide www xilinx com 357 UG632 v13 4 January 18 2012 Chapter 11 Analyzing Implementation Results g XILINX Refer to Working with Placement LOC and BEL Constraints page 329 for information about manually assigning LOC constraints To Fix place specific types of logic use Find to select specific types of logic such as block RAMs and DSPs Then select them in the Find Results view and use Fix Instances Fixing Logic Modules A method for improving consistency of implementation result is to lock critical logic in place This can involve locking specific logic timing paths or entire logic modules To fix place all logic in a particular module select the module or modules and use Select Primitives to select the primitive logic instances associated with the logic module To lock the logic use Fix Instances Displaying Design Metrics 358 The following subsections describe the design metrics options Using the Metrics View
104. changes to indicate either a successful or failed attempt Failures are displayed with red text If source files change the project can be marked Out of Date if Synthesis or Implementation is complete as shown in Figure 9 9 The Status Bar indicates an Out of Date Status You can select the more link to display the reason Synthesis Out of Date more LS Out of Date Details sources_1 modified Figure 9 9 Information on why Project is Out of Date Design State in the Flow Navigator The Flow Navigator helps visualize the design state by providing access to only the commands applicable to the design state For example if Implementation is not run the Implemented Design button is greyed out The Flow Navigator visually guides you to click the next step in the design process Design Data Out of Date Banner As source files netlists constraints or implementation results update a banner appears in the top of the open design indicating that a newer version of the design is available than what is loaded in memory You are prompted to reload what is loaded in memory as shown in Figure 9 10 RTL Design rtl_1 xc6vlx75tff784 3 active RTL Design is out of date Design sources modified Reload Figure 9 10 Out of Date Banner and Reload button 296 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Analyzing Implementation Run Results Analyzing Implementation Run Results After Synt
105. com ise embedded edk_ip htm ISE Documentation 436 Libraries Guides http www xilinx com support documentation dt_ise13 4_librariesguides htm www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX ISE Documentation CPLD Libraries Guide UG606 Spartan 3 Libraries Guide for HDL Designs UG608 Spartan 3 Libraries Guide for Schematic Designs UG607 Spartan 3A and Spartan 3ADSP Libraries Guide for HDL Designs UG613 Spartan 3A and Spartan 3ADSP Libraries Guide for Schematic Designs UG614 Spartan 3E Libraries Guide for HDL Designs UG617 Spartan 3E Libraries Guide for Schematic Designs UG618 Spartan 6 Libraries Guide for HDL Designs UG615 Spartan 6 Libraries Guide for Schematic Designs UG616 Virtex 4 FGPA Libraries for HDL Designs UG619 Virtex 4 FGPA Libraries for Schematic Designs UG620 Virtex 5 FGPA Libraries for HDL Designs UG621 Virtex 5 FGPA Libraries for Schematic Designs UG622 Virtex 6 FGPA Libraries for Schematic Designs UG624 Virtex 6 FGPA Libraries for HDL Designs UG623 7 Series FPGA Libraries Guide for HDL Designs UG768 7 Series FPGA Libraries Guide for Schematic Designs UG767 e ISE Design Suite Documentation http www xilinx com support documentation dt_ise13 4 htm PlanAhead User Guide UG632 v13 4 January 18 2012 Command Line Tools User Guide UG628 http www xilinx com support documentation sw_manuals xilinx13_4 devref pdf Constr
106. coming into the I O from the board level design The following CSV Entries Can Appear in Spartan Devices BUFIO2_REGION Defines the BUFIO2 clocking region to which a port could be related IN_TERM OUT_TERM Defines the optional IN_TERM or OUT_TERM driver impedance attributes for Spartan 6 This is most commonly left blank and is not yet supported for production devices Using this terminal definition overrides the SLEW and DRIVE STRENGTH attributes and is not supported in SSN calculations OFFCHIP_TERM Specifies the external board level termination of the I O This is used for SSN calculations If the field is left blank PlanAhead uses the expected terminations in the SSN calculations and shows this expected termination by default in the SSN report and I O Ports table The expected terminations as well as the corresponding shortened names that display in PlanAhead can be found in the Spartan 6 FPGA SelectIO Resources User Guide UG381 as cited in Appendix E Additional Resources Any column values that are not defined are retained by the PlanAhead tool when reading the CSV and reported as user defined columns in the I O Ports view Outputs for Reports Figure A 1 shows a the directory structure used for reporting output on a Windows OS When the file location is not user specified the PlanAhead tool places report output files based on the OS 412 On Linux the directory is the PlanAhead invocation direc
107. configure launch and monitor implementation runs using the ISE Design Suite You can experiment with different implementation options and create reusable strategies for implementation runs As an example you can create strategies for quick runtimes performance or area optimization The implementation run results display interactively and report files are accessible Also you can launch multiple implementation runs either simultaneously or serially when using the Linux platform you can use remote servers You can create Constraint Sets so you can experiment with various logical constraints physical constraints or alternate devices Results Analysis and Floorplanning Load the various run results interactively for analysis and floorplanning The capabilities in the Implemented Design are described in e Chapter 7 Netlist Analysis and Constraint Definition e Chapter 11 Analyzing Implementation Results You can import results from any run that is launched from the PlanAhead tool When you open an Implemented Design the original netlist constraints and implementation results are loaded into the Results Viewer You can open multiple designs www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX User Models simultaneously You can also launch the ISE Simulator ISim for timing simulation XPower Analyzer and FPGA Editor tools directly from the PlanAhead tool for further design analysis Devic
108. design as needed For more information see e Chapter 5 RTL Design for information about Behavioral simulation e Chapter 11 Analyzing Implementation Results for Timing simulation Synthesis and Implementation The PlanAhead tool includes a synthesis and implementation environment supporting multiple synthesis and implementation runs using different physical or timing constraints and different tool options to help complete routing and achieve timing closure The synthesis and implementation runs can be queued to launch sequentially or simultaneously with multi processor machines using the Xilinx ISE synthesis and implementation software e Chapter 6 Synthesizing the Design describes how to use synthesis e Chapter 9 Implementing the Design describes how to use implementation Design Analysis and Constraints Definition The PlanAhead tool enables analyzing the design at each stage of the design process Resource timing and power estimations along with DRCs let you experiment with various devices constraints and synthesis and implementation options to achieve desired results After implementation you can launch the FPGA Editor and XPower Analyzer tools directly from the PlanAhead tool for a detailed look at the implemented FPGA These features are available both before and after implementation by analyzing the synthesized netlist design or the implemented design results For more information see e Chapter 7 Netlist Analysis
109. design using the Add Sources command and specifying Add or Create Design Sources to load the files Adding Existing IP Cores PlanAhead User Guide To add existing IP cores xco to a project 1 Select File gt Add Sources from the main menu or Add Sources from the popup menu or from the Flow Navigator The Add Sources wizard opens as shown in Figure 3 14 page 50 2 Select the Add Existing IP option and click Next The Add Existing IP dialog box opens as shown in Figure 3 25 page 64 www xilinx com 63 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects g XILINX CB Add Sources Add Existing IP Specdily an exikting configurable 1P file to add to your project Enter the IP name to be used in tha project inthe IP Nome column id IF Nams Frie i CiD FPGA _designiproct_Siprosct 5 sresisouross I ap HFt samll 0 Mren vI 0 c_shft_ram_v11_0_0 C a FPGA desinipmojert Siproject 5 srcs sources Tupe set rem vil O he diit ram Figure 3 25 Add Existing IP The Add Existing IP options are e Add Files Invokes a file browser so you can select XCO files to add existing IP cores to the project e Remove Removes the selected source files from the list of files to be added When you have specified the existing IP core files to add to the project click Finish to add the cores The added IP cores display in the Sources view in the IP folder You can select these cores in the Sources view to se
110. different banks of pins The display of a specific pin in the Package view can depend on a combination of layers that represent the pin The visibility of the layers and the pins can be controlled through the use of the Layers Slideout for the Package view Figure 4 47 page 135 shows an example of e HP HR banks are displayed as a feature of the I O banks e Multifunction pins display as part of the I O bank in which they are contained e Power pins display separately from the I O banks If the I O banks are not displayed then power pins display but the multifunction pins do not display even though both are selected under the Pins heading of the Layers Slideout Click the sign to expand or the sign to collapse the levels of the tree view to see the layer of interest Click in the box to enable or disable the layer for display in the Package view A check mark indicates the currently displayed layer You can display or hide e Groups of objects or layers by clicking the category of the layers e Individual layers or objects by selecting the item directly Note If a specific pin is not visible in the Package view check that both the pin and the I O block it is contained in are selected for display in the Package View Layers command Use the Layer Slideout toolbar menu for e Searching for specific layers to display with the Show Search command e Expanding and collapsing layer with the Expand all Collapse all commands Click the Pac
111. e Destination Clock Displays the destination clock name Note In PlanAhead Timing Analysis carry chain interconnect is counted as individual stages of logic Sorting the Timing Report You can sort the Timing Results by clicking any of the column headers For example click on the Stages column header to sort the list by stages of logic Click the column header a second time to reverse the sort order You can sort by a second column by pressing the Ctrl key and clicking a second column header You can sort by as many columns as necessary to refine the sort results Press Ctrl and click the column header again to remove a sort from a column Refer to the Using Tree Table Style Views page 106 for information regarding working with tree table style views Figure 11 7 shows a timing result sorted by stages of logic Name Type Constrained Paths 10 P Pathi Setup P Path2 Setup P Path3 Setup Setup Setup Setup Setup Setup Slack From To Total Delay Logic Delay Net Stages Source Clock Destination Clock 1 059 usbEngineOsusb_dma_ usbEngineO ut dout_14 D 4 191 1 771 57 7 6 TS_usbclk TS_usbClk 1 059 usbEngine1 usb_dma_ usbEngine1 ut dout_14 D 4 191 1 771 57 7 6 TS_usbClk TS_usbClk 1 163 usbEngineO usb_dma_ usbEngineO ut Funct_adr_O CE 4 087 1 891 53 7 5 TS_usbclk TS_usbClk 1 163 usbEngineO usb_dma_ usbEngineO u Funct_adr_1 CE 4 087 1 891 53 7 5 TS_usbclk TS_usbClk usbEngineO u4 funct_adr_2 CE 4 087 1
112. e Importing a partition into a different hierarchy than in which a partition was created e AREA_GROUPS within partitions e Black Box support in Synthesis and Implementation e Boundary optimization for constants and unconnected inputs and outputs on partition ports Note Nested partitions which are available in the ISE command line flow are not support in PlanAhead After you have implemented designs with partitions you can export the results for use in future runs The partition definition and behavior is defined in an XML file called xpartitions pxml The ISE Design Suite tools search the run directory for that file and act accordingly Partitions are defined as well as the specified partition action such as Implement or Import See the Hierarchical design documentation for a description of the xpartitions pxml file usage and syntax www xilinx com 381 UG632 v13 4 January 18 2012 Chapter 13 Using Hierarchical Design Techniques XILINX Setting Partitions You can set partitions on any hierarchical design instance in a Design The hierarchical design flows require that each partition be synthesized separately resulting in individual netlists per partition This ensures that partition netlists can be isolated and reused To set a partition 1 Inthe Netlist view select the module instances on which to set partitions 2 Select the Set Partition popup menu command 3 The icon associated with the instance in the
113. e Updated selecting objects See Selecting Marking and Moving Objects Chapter 4 Using the Viewing Environment e Described customizing GUI with custom Tcl Commands See Adding Custom Menu Commands in Chapter 4 Using the Viewing Environment e Added cross selecting across designs See Chapter 4 Using the Viewing Environment e Documented Find and Replace in Files See Using the Find Commands in Chapter 4 Using the Viewing Environment e Described changing target parts for specific synthesis or implementation runs See Using the Run Properties View in Chapter 4 Using the Viewing Environment e Described resizing and repositioing the World View See Using Graphical Workspace Views in Chapter 4 Using the Viewing Environment e Added SSN support for Artix 7 devices See Using Noise Analysis Predictors in Chapter 8 e Changed Create Multiple Runs command to Create New Runs command See Creating and Managing New Runs in Chapter 9 Implementing the Design e Documented IOBUSSLRC and IOPCBT design rule checks See Appendix B IOB DRCs 1 18 12 13 4 e Documented Exporting IBIS Models in Chapter 8 Updated paths to planAhead ini file See Outputs for Environment Defaults in Appendix A Added reference to running NetGen for simulation See Performing Timing Simulation in Chapter 11 Added details on grouping search criteria in Find command See Using the Find Commands in Chapter 4 PlanAhead User Guide www xilinx com UG632
114. file order shown in the Compile Order tab will be automatically updated or can be manually defined depending on the setting of the Hierarchy Update command as discussed below Note The Move commands are not available from the Hierarchy tab of the Sources view e Move Up Moves the currently selected source file up in the source file list e Move Down Moves the currently selected source file down in the source file list e Move to Bottom Relocates the currently selected source file to the bottom of the source file list Hierarchy Update Determines how the PlanAhead tool responds to changes of the source files such as redefined top module added or removed files or changed file order The three possible settings for this command are vw Automatic Update and Compile Order Automatic Update Manual Compile Order No Update Manual Compile Order e Automatic Update and Compile Order Specifies that the hierarchy view of the design and the compilation order should be automatically updated as source files are changed e Automatic Update Manual Compile Order Specifies that the hierarchy view of the design should be automatically updated as source files are changed but that the compilation order is determined manually The compilation order can be manually defined by ordering the files as desired using the Move to Top Move Up Move Down and Move to Bottom commands from the Compile Order tab e No Update
115. files and launch the iMPACT and ChipScope Analyzer tools directly from within the PlanAhead tool See Chapter 12 Programming and Debugging the Design Hierarchical Design Design Preservation and Partial Configuration The PlanAhead tool provides some advanced hierarchical design features to support team design design preservation and partial reconfiguration methodologies See Chapter 13 Using Hierarchical Design Techniques The Hierarchical Design Methodology Guide UG748 cited in Appendix E Additional Resources more completely describes the hierarchical design process Tcl Commands and Batch Scripting For information about the syntax of Tool Command Language Tcl commands and batch options in the PlanAhead tool see Chapter 14 Tcl and Batch Scripting For a reference to the Tcl commands supported by the PlanAhead tool see PlanAhead Tel Commands Reference Guide UG789 cited in Appendix E Additional Resources Using PlanAhead Software with the ISE Project Navigator Environment The PlanAhead tool is integrated with the Project Navigator software tool to provide an environment for improving your design results throughout the design flow Project Navigator automatically launches the PlanAhead tool at the following design steps e Pre Synthesis e I O pin planning e Post Synthesis e I O pin planning e Floorplan Area IO logic e Post Implementation e Analyze Timing and Floorplan design See Chapter 15 Using PlanAhead
116. first object then press and hold the Ctrl key and click to select multiple additional objects You can select a range of objects from a list of objects for instance Click on and select the primary object then press and hold the Shift key and select the last object in a range of elements from a tree or table view You can select all the objects in an area of a graphical view See Using the Select Area Command page 111 for more information When objects overlap a priority scheme is used where the smaller size objects are selected If objects become difficult to select in the Device view use the Physical Constraints or Netlist views You can select objects from either of these two views regardless of the Selection Rule in the Options dialog box see Setting Selection Rule Options page 165 If you experience difficulty selecting the desired object use the Select command in the right click popup menu as shown in Figure 4 25 to select a specific object from a list of objects at the location of the currently selected item 110 BEL Properties Ctrl E Create a DCI Cascade Highlight Schematic Show Hierarchy Select BEL H20 OUTBUF View s Site H20 Metric Tile LIOB33_X0Y77 I O Bank 14 High Range Clock Region XO 1 Figure 4 25 Select gt Objects www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Selecting Marking and Moving Objects Using the Select Area Command You can draw a
117. global include files The Global Include switch forces the selected file to be compiled at the start of the compile order for elaboration and synthesis See Defining Global Include Files in Chapter 6 for more information e Deselect the Enabled checkbox to disable a specific source file from the design Disable files are still listed in the source files but are not considered part of the design for elaboration or compilation e Use the Read only checkbox to ensure that changes are not written to the selected source file 2 Click Apply or Cancel to implement or discard any changes to the Source File Properties 128 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Using Common Views Using the Device View PlanAhead User Guide The Device view is the main graphical interface used for multiple purposes related to design analysis and floorplanning For more information see e Chapter 7 Netlist Analysis and Constraint Definition e Chapter 8 I O Pin Planning e Chapter 11 Analyzing Implementation Results e Chapter 10 Floorplanning the Design The Device view displays the FPGA device resources including the FPGA logic clock regions I O pads BUFGs DCMs Pblocks instance locations and net connectivity The locations on the device where specific logic can be assigned are called Sites Figure 4 43 shows a Device view E Project Summary X Device x E Figure 4 43 Device View The
118. in Figure 3 30 page 70 PlanAhead User Guide www xilinx com 69 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects g XILINX Update IP Catalog i Update your IP Catalog with new user IP Please specify the location of IP repositories and the location where your IP catalog will get saved IP Repository Search Paths d Add Directories Save IP Catalog To Documents and Settings randyh Application Data xilinx Planahead 13 1 Figure 3 30 Update IP Catalog Edit the Save IP Catalog To field to define the output directory of the IP Catalog to be created by the update process The PlanAhead tool creates an IP Catalog file called pa_cg_catlog xml and places it in the specified location Importing XPS Embedded Processor Designs 70 EDK provides an environment for you to integrate your hardware and software system components You can use the Xilinx Platform Studio XPS to design the hardware portion of your embedded processor system Specification of the microprocessor peripherals and the interconnection of these components along with their respective detailed configuration takes place in XPS XPS uses XST for design synthesis The synthesis netlists generated by XST are in NGC format The top level file is named system ngc and any other NGC files have the nomenclature module_name ngc The system ucf contains the design constraints You can add these files to the project as sources either as top le
119. indicates that the value is currently set to a non default value Note Modifications to these options are not preserved if you do not run Synthesis prior to exiting the PlanAhead tool If Synthesis results exist in the project the Project Settings inherit the settings of the active Synthesis run If no Synthesis run exists in the project the PlanAhead restores the defaults For more information about specific XST options see the following documents cited in Appendix E Additional Resources e XST User Guide for Virtex 4 Virtex 5 Spartan 3 and Newer CPLD Devices UG627 e XST User Guide for Virtex 6 Spartan 6 and 7 Series Devices UG687 PlanAhead User Guide www xilinx com 199 UG632 v13 4 January 18 2012 200 Chapter 6 Synthesizing the Design XILINX Creating a Hierarchical Netlist All Synthesis strategies in the PlanAhead tool except the XST default strategy are defined using the netlist_hierarchy rebuilt option This option instructs XST to flatten the netlist to perform logic optimization but then rebuild the netlist hierarchy in the Netlist Design based upon logic names This facilitates design analysis and floorplanning within the PlanAhead tool If you encounter problems with this option in XST set the net list_hierarchy option to as_optimized in the Synthesis Settings dialog box as shown in Figure 6 1 page 199 Controlling File Compilation Order RTL source files are compiled by the synthesis engine
120. information about device pins and pinout See I O Port Lists CSV page 409 for details about the CSV file format The PlanAhead tool requires a specific CSV file format for importing I O pin related data as described in I O Port Lists CSV page 409 CSV files can also contain additional information not recognized by the PlanAhead tool If unrecognized information is found in the imported CSV file it displays that information in columns of the Package Pins view for your review and use To modify or define values in the customer CSV fields select the Set User Column Values from the popup menu in the Package Pins view Use the File gt Export gt Export I O Ports to export a CSV file Added columns and user defined values are preserved and exported to the output file Importing a UCF Format File You can import UCF format files as a way to populate the I O Ports view To import I O port definitions from a UCF select File gt Import gt Import I O Ports and select the UCF option to browse to a UCF as shown in Figure 8 10 page 260 Because the UCF format does not define port direction the direction is undefined To define the I O port direction select Set Direction from the I O Ports view You can also directly modify the direction of a specific I O port in the I O Ports view See Setting I O Port Direction page 263 for more information Note f the imported UCF defines ports uses wildcard syntax the PlanAhead tool does no
121. legal Tel command supported by the PlanAhead tool You can also source another Tcl script file from within the init tcl file by adding the following statement source lt path_to_file gt lt file_name gt tcl General Tcl Syntax Guidelines Tcl uses the Linux file separator convention regardless of the OS on which you are operating PlanAhead User Guide www xilinx com 393 UG632 v13 4 January 18 2012 Chapter 14 Tcl and Batch Scripting XILINX The following subsections describe the general syntax guidelines for using Tcl in the PlanAhead tool Sourcing a Tcl Script You can source a Tcl script from a command line option source file_name Within the PlanAhead GUI you can source a Tel script from Tools gt Run Tel Script General Syntax Structure The general structure of the PlanAhead tool Tcl commands is command optional_parameters required_parameters Command syntax is of the verb noun and verb adjective noun structure separated by the underscore _ character Commands are grouped together with common prefixes when they are related e Commands that query things are generally prefixed with get_ e Commands that set a value or a parameter are prefixed with set_ e Commands that generate reports are prefixed with report_ The commands are exposed in the global namespace Commands are flattened meaning there are no sub commands for a command Example Syntax The following is an exa
122. location The PlanAhead tool prompts you to overwrite any previously promoted partitions in an effort to enforce this methodology Refer to the Hierarchical Design Methodology Guide UG748 as cited in Appendix E Additional Resources 4 Select the partitions to promote By default all partitions in the design are selected to promote except for the top level partition 5 Optionally enter a Description for the partition then click OK The Promoted Partitions view opens to report the results After you promote a partition the default action for that partition in the Specify Partitions dialog box is set to Import for subsequent synthesis or implementation runs Using the Promoted Partitions View The Promoted Partitions view displays each time you select Promote Partitions To open the Promoted Partitions view select Window gt Promoted Partitions Figure 13 6 shows the Promoted Partitions view Promoted Directory Run Promoted on Description SH 5 promote ximpl_1 3 impl_t 3 14 10 5 31 PM My Initial Run O top U1_RP_Bram U2_RP_Count 5 promote ximpl_2 2 impl_t 3 14 10 5 36 PM My Second Run U1i_RP_Bram U2_RP_Count amp Sources Netlist 7 amp Timing Constraints Figure 13 6 Promoted Partitions View Each promotion displays in a tree table detailing the partitions promoted the source run the promote date and time and the description Deleting Promoted Partitions
123. machines If the design data is saved to a local disk it is not visible from remote machines Configuring Remote Hosts Linux Only After you have configured SSH as described in Setting Up SSH Key Agent Forward in Appendix D the PlanAhead tool enables launching Runs using remote servers To do so they must first be configured 1 To configure a remote host select one of the following commands e Tools gt Options gt Remote Hosts e Synthesis gt Launch Runs gt Configure Hosts e Implementation gt Launch Runs gt Configure Hosts e Configure Hosts in the Launch Selected Runs options dialog box The Remote Hosts dialog box displays as shown in Figure 9 21 page 307 306 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX PlanAhead User Guide 10 Launching Runs on Remote Linux Hosts y Ey PlanAhead Options x Remote Hosts H Hosts hemes Name Jobs Enabled Re E xsind colin TE 7 Selection Rules x nux2 36H m Schematic a3 Strategies Ee Remote Hosts W Launch jobs with Add Remove Test ssh 0 BatchMode yes G al m r le Ll Run pre launch script i IE C Run post completion script Text Editor 7 7 C Send email to After all jobs OK J Cancel Apply Figure 9 21 Configuring Remote Hosts Click Add to enter the names of
124. main toolbar menu with Tools gt Custom Commands gt Customize Commands from the main menu This allows you to add frequently used Tcl commands to the GUI for use within the graphical environment The Customize Commands dialog box is opened when you run Customize Commands as shown in Figure 4 78 page 172 PlanAhead User Guide www xilinx com 171 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX G Customize Commands i Configure custom Tcl menu and toolbar entries Current Commands Ra Modules loads Edit Command Menu name loads Shortcut S Ctrl Alt G Run command loads i p Source Tel file Toolbar Options Add to the toolbar Tooltip Report the Loads in the Design Icon file path Data show_loads png Figure 4 78 Customizing Menu Commands The options of the Customize Commands dialog box are e Current Commands Displays the list of currently defined custom commands e Adda New Command Displayed as a icon the Add command lets you specify new commands to add to the custom menu Click Add a New Command type the command name and press Enter to add the command to the list of custom commands e Remove Selected Commands Displayed as an X icon the Remove command lets you select one or more commands and remove them from the custom menu e Edit Command Lets you specify the attributes of the selected comm
125. multiple projects in a single session use any of the methods previously described to open a second project while another project is already open The PlanAhead tool asks if you want to close the current project If you do not close the first project both projects are opened Each open project has a separate main window Note System memory requirements can hinder performance when opening multiple projects Saving a Project To save projects select File gt Save Project or File gt Save Project As When you save a project the PlanAhead tool prompts you to save unsaved changes to designs and source files Save Project As copies the entire project directory structure to a new specified location and maintains the status of the existing runs Archiving Projects PlanAhead User Guide To create a project archive to store as backup or to encapsulate the design to send to a remote site click File gt Archive Project The PlanAhead tool e Parses the hierarchy of the design e Copies the required source files include files and remote files from the library directories e Copies the constraints e Copies the results of the various synthesis simulation and implementation runs e Creates a ZIP file of the project Figure 3 13 shows the Archive Project dialog box G Archive Project i Create a compressed zip file that contains all the sources settings and other files associated with this project Name and Location Archive n
126. number of selected objects as follows e Select objects in a graphical view such as the Device view and use the View gt Highlight gt Highlight Color command from the main menu e Select objects in a graphical view such as the Device view and use the Highlight gt Highlight Color command from the popup menu e Select a Pblock in the Device view and use the Highlight gt Highlight Color command from the popup menu www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using the Find Commands e Select a module or primitives in the Netlist view and use the Highlight gt Highlight Color command from the popup menu For more information see Using Select Primitives and Highlight Primitives Commands page 356 Marking and Unmarking Selected Objects The PlanAhead tool lets you place a Mark symbol and remove the Mark in all applicable views for selected objects Marking Objects Marking a selected object is helpful when displaying small objects that you want to see in the Device view To mark selected objects select the object and then use the View gt Mark command from the main menu the Mark command from the popup menu or use the Ctrl M keyboard shortcut The Mark command is also available in other views including the Netlist view Physical Hierarchy view and Timing Report view Figure 4 30 shows a timing path marked from the Timing Report view The start point of the timing path is marked i
127. of unrouted nets on the run in progress or after completion e Description Displays the description associated with the run This description is set initially to a strategy description when that strategy is applied to the run however the description can be modified later The table is updated dynamically as the run commands progress Runs that are launched outside of the PlanAhead tool using generated scripts cause the table to update upon invoking the software Using the Design Runs View Popup Menu Commands The Design Runs view popup menu contains the Implementation Run Properties Ctrl E following commands Copy Text Ctrl C e Synthesis or Implementation Run Properties X Pelete posta Displays the Run Properties view Make active e Copy Text Copies the selected text Save As Strategy e Delete Deletes the selected runs You are prompted to confirm prior to removing any nee runs Ki Reset Runs e Make Active Sets the selected run as the i N i Generate Bitstream active run This run launches automatically n 5 2 opy Run when the Implement command is used The i f Create New Runs results for the active run display in the E i u Open Run Directory Messages Compilation Reports and Project Summary views e Change Run Settings Lets you change the S strategy and command line options for the S selected synthesis or implementation run See Launching a Synthesis Run in Ch
128. of window layouts and themes to configuration and initialization files that are loaded when the tool is launched You can also save custom themes window layouts and run strategies to be loaded when you need them The files defining these themes and layouts are written to the PlanAhead tool environment folders in the following locations On Windows the PlanAhead tool environment settings are stored in files located under the user s Document and Settings folder e C Documents and Settings lt user_name gt Application Data Xilinx PlanAhead lt version gt On Linux the PlanAhead tool environment settings are stored in files located under the user s Home directory e 6 Xilinx PlanAhead lt version gt Table A 3 lists the files locations and descriptions for the PlanAhead environment configuration files Table A 3 PlanAhead Environment Default Outputs File Name View Display Options File planAhead ini Description The PlanAhead lt version gt planAhead ini file captures the settings in Tools gt Options that include display color and other viewing options for the environment For more information see Configuring PlanAhead in Chapter 4 The PlanAhead tool saves your settings to the planAhead ini file when you exit the tool Upon invocation it imports the file automatically and applies the settings to initialize the tool PlanAhead Themes lt theme_name gt patheme The PlanAhead
129. options to search source files constraint files and report files For more information see Using the Find Commands page 115 Elaborating and Analyzing the RTL Design The PlanAhead tool lets you elaborate and analyze the RTL design without running synthesis When the RTL sources are elaborated the RTL Netlist view opens You can open the RTL Design at any time in the design process to review and re analyze the design or to make any necessary changes Elaborating the RTL Design Enabled RTL source files in the project are elaborated regardless of whether they are compiled as a part of the design or during synthesis The Messages view shows the messages from elaboration and compilation You can select the HDL language options used during elaboration in the PlanAhead Project Settings See General Project Settings page 84 Elaboration results are not saved with the RTL design You can run and re run elaboration on the RTL Design After you synthesis the RTL Design the PlanAhead tool saves it as a Netlist Design 1 After design source files are imported into the project you can elaborate the design using one of the following commands e Elaborate command from the Project Manager menu of the Flow Navigator e Tools gt Elaborate command from the main menu e Flow gt RTL Design or RTL Design command in the Flow Navigator If needed the Specify Top Module dialog box opens However the PlanAhead tool automatically identifies the
130. or reload the Netlist Design to apply the logic changes Refer to Managing Design Source Files page 175 for more information Setting Partition Actions Based on Logic Updates You must set the Partition action for each run as described in Configuring Synthesis and Implementation Runs with Partitions page 382 e Partitions with updated netlists must be set to Implement to ensure that the logic is re implemented with the changes e Unchanged partitions must be set to Import for results to be preserved The PlanAhead tool sets the Partition actions automatically to Import for any promoted partitions and selects the most recent promoted directory from which to import The PlanAhead tool does not track logic updates or set the appropriate partitions to Implement Figure 13 7 page 388 shows the Specify Partitions dialog box PlanAhead User Guide www xilinx com 387 UG632 v13 4 January 18 2012 Chapter 13 Using Hierarchical Design Techniques g XILINX G Specify Partitions i Specify whether partitions will be imported or implemented Implementation i Action Import from Preservation Implement v NJA V usbEngine0 Implement v NjA v iect DP RTL importediproiect DP RTL imported promatelxsynth 1 Routing Placement Synthesis Figure 13 7 Importing Partitions The ISE NGDBuild report provides information about the Partition actions for each run To access the report select the Reports view tab and open the NGDBuild repo
131. ouput wil Pipelining DSP48 ouput wil improve performance improve performance improve performance improve performance improve performance improve performance improve performance improve performance improve performance Both mul Both mul Both mul Both mul Both mul Both mul Both mul Both mul Both mul results_1 224 violations x A Td Console Messages al Compilation Figure 8 28 Highlighting DRC Violations s Design Runs A violation can be e Informational only to make you aware of a possible issue shown in yellow e A warning to suggest an issue that might need some resolution shown in orange e A critical warning to highlight an issue that you must resolve shown in orange e An error to highlight issues that would prevent proper implementation of your design Errors show with a red marker You can toggle the Hide warnings and informational messages button in the toolbar menu to turn off warnings and informational messages to see only the errors reported You can also click on the header of the Severity column of the DRC Results view to sort violations by severity e Click once on the column header to sort in an increasing order e Click twice to sort in a decreasing order See Using Tree Table Style Views in Chapter 4 for more information Select a violation message in the DRC Results view then select Violations Properties to open the Viol
132. pa w top ngd Using target part 6vlx7 5Stff784 3 Mapping design into LUTs WARNING MapLib 701 Signal TILE3 REFCLK_PAD_P_IN connected to top level port TILE3 REFCLK PAD P IN has been removed lt B Tel Console Messages Reports Design Runs D I O Ports Figure 9 7 Compilation view The Pause button lets you pause the output to the Compilation view so that you can scroll and read the log while a command continues running PlanAhead User Guide www xilinx com 295 UG632 v13 4 January 18 2012 Chapter 9 Implementing the Design XILINX Determining the Project Status The PlanAhead tool provides several visual indicators about the overall status of a project as well as methods to take in the next step of the process Only the results of the major design tasks in the design process are reported in the project status The overall project status displays in the Project Summary and in the Status Bar so you can quickly visualize the status of a project upon opening the project or while you are running the design flow commands These include RTL Elaboration Synthesis Implementation and Bitstream Generation Project Status Bar The overall project status displays in the upper right corner of the viewing environment as shown in Figure 9 8 Status Implemented Figure 9 8 Project Status Bar As you run the Elaborate Synthesize Implement and Generate Bitstream commands the Project Status Bar
133. page 311 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Working with Pblocks lt M Package x E Project Summary x 1B Figure 10 2 Pblock Connectivity Analysis in the Device View See Analyzing Hierarchical Connectivity page 214 and Using the Show Connectivity Command page 354 for more information about this view Using the New Pblock Command The New Pblock command creates a new Pblock in the Physical Constraints view but does not create a rectangle in the Device view You must pre select logic for assignment to the new Pblock If no logic is pre selected the command creates an empty Pblock To create new Pblocks with or without pre selected logic select New Pblock Creating Multiple Pblocks with the Create Pblocks Command You can create multiple Pblocks in a semi automated way by using the Create Pblocks wizard The wizard creates a separate unplaced Pblock for each selected netlist instance To use the wizard pre select a set of instances for inclusion into individual Pblocks To create multiple Pblocks for specific netlist instances 1 Select the instances to include in the Pblocks 2 Select Tools gt Floorplanning gt Create Pblocks The Create Pblocks wizard opens with a list of the selected instances as shown in Figure 10 3 page 312 PlanAhead User Guide www xilinx com 311 UG632 v13 4 January 18 2012 Chapter 10 Floorplanning the Design g XILINX 312 G C
134. phase For more information see Defining I O Port Switching Phase Groups in SSN page 288 Note The Phase option applies to Virtex 6 devices only and is not available for other device families Refer to Xilinx device documentation for information regarding voltage capabilities of the device Configuring I O Ports You can configure I O ports to support specific IOSTANDARDs define specific voltage characteristics and delay characteristics To configure a port or a group of ports 1 Inthe I O Ports view select the ports 2 From the popup menu select Configure I O Ports www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Defining and Configuring I O Ports The Configure Ports dialog box opens as shown in Figure 8 13 G Configure Ports I O Standard LVCMOS25 default Drive Strength 12 default Slew Type SLOW default Pull Type NONE default Phase default Figure 8 13 Configure Ports Dialog Box 3 Edit the options e I O Standard Select the I O Standard constraint You can set all I O Standards on any I O regardless of whether the tool has awareness of differential pairs this could result in DRC errors e Drive Strength Select the drive strength value e Slew Type Select the Slew Type value e Pull Type Select the Pull Type value e Phase Enter a phase group or select an existing phase group For more information
135. places as many of the I O Ports as is possible This functionality is available for certain device architectures only and you must have a synthesized netlist for the available rules to be applied See Automatically Placing I O Ports page 273 The PlanAhead tool attempts to maintain correct assignment rules by e Placing differential pair ports into proper pin pairs e Grouping and placing GTXs together with their I O buffers to ensure proper resource assignment on the device The PlanAhead tool uses interactive and batch DRCs to ensure legal I O placement See Validating I O and Clock Logic Placement page 278 tel project_pin_plan C Data FPGA_design project_pin_plan project_pin_plan ppr PlanAhead 13 2 x File Edit Flow Tools Window Layout view Help Pek Seah aan amp 2B oe X HO XK E a Eo planning Oe OG Project Manager VO Design io_1 xc6v 84 3 HB WODesign aaa oOx f Package x Oax bevice x TEE Z E F Import 1 0 Ports D empty Run prc fe Run Noise Analysis Export 1 0 Ports amp Sources i Netlist Timing Constraints UCF Properties 00x ev O Properties Clock Regions 1O Ports A Name Dir Neg Diff Pair Ste Bank YOStd Veco Vref Drive Strength Slew Type Pull Type Phase E E Al ports 144 Al Dataln_pad_oj e Input 14 Lvcmos25 25 12 SLOW default a amp Dataln_pad_1i 8 Input 1elvemos25 25 12 SLOW default P 1G Datadut_pa
136. project_bft_core_hdl project_bft_core_hdl srcs sources_1 imports hdl async_fifo 20 67 The Following is paramatizable RTL code for an asynchronous FIFO 3 59 1 This code is provided as a reference for a possible FIFO implementation and 40 14 40 43 FIFO_WIDTH 144 l Set the FIFO data width number of bits FIFO_WIDTH 144 l Set the FIFO data width number of bits FIFO_DEPTH 12 j Express FIFO depth by power of 2 or number of address bits for the FIFO RAM FIFO_DEPTH 12 j Express FIFO depth by power of 2 or number of address bits for the FIFO RAM FIFO_DEPTH 12 Express FIFO depth by power of 2 or number of address bits for the FIFO RAM FIFO_RAM_TYPE BLOCK_RAM AUTO HARDFIFO BLOCKRAM or DISTRIBUTED_RAM FIFO_RAM_TYPE BLOCK_RAM AUTO HARDFIFO BLOCKRAM or DISTRIBUTED_RAM Occurrences of FIFO in all project files 162 x E Tcl Console O Messages G Compilation Design Runs G Timing Results Figure 4 36 Find Results View Use the Replace in Files command to search for any given text string in a selected set of source files and replace it with a different text string Select the Replace in Files command from the Text Editor popup menu or select Edit gt Replace in Files from the main menu Figure 4 37 page 121 shows the Replace in Files dialog box 120 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using the Find Comman
137. provided for proper power estimation Table 5 1 lists the Confident level description and score by category Table 5 1 Confidence Levels Confidence a Category Laval Description Score Low At least one black box was found in the design 0 Design State Medium N A 0 High No black boxes were found in the design 1 Low At least one unconstrained clock found 0 Clock Nodes Medium N A 0 High All clocks properly constrained 2 gt 10 of IOBs have enable derived from toggle Low i 0 rate of driver logic I O Medium lt 10 derived enable rates for IOBs at least one 1 Nodes I O activity rate using default value lt 10 derived enable rates for IOBs all I O High os 2 activity rates set by user Low lt 50 of instances matched by toggle rate 0 templates Internal 3 gt 50 matched instances at least one internal Medium 1 Nodes rate using default value High gt 90 matched instances or all internal activity 2 rates set by user Low Advance characterization data 0 laa a Medium Preliminary characterization data 0 High Production characterization data 1 Low Sum of Score for all categories is less than 4 Overall er gt Medium Sum of Score for all categories is 4 5 or 6 Design High Sum of Score for all categories is greater than 6 e Table 5 2 page 186 lists the Color Legend for Total on chip power Junction temperature and Thermal margin PlanAhead User Guide w
138. provides dynamic connectivity feedback to help guide placement of Pblocks Figure 10 5 shows an example of a connectivity display The combined connectivity between Pblocks show as bundled nets PlanAhead sizes and colors each bundle based upon the number of connections between Pblocks so that the heavily connected Pblocks are easy to identify A reasonable strategy is to define the Pblocks with the largest net bundles close together Typically the Pblocks are placed to achieve the shortest net lengths and to avoid routing conflicts or congestion Displaying Bundle Net Properties You can view connectivity information by displaying properties for net bundles or for individual nets To view connectivity information 1 Select the net or bundle net 2 View the Net Properties or Bundle Net Properties view The Nets tab in the Bundle Net Properties view displays the nets contained in the bundle as shown in Figure 10 15 T 3E Bundle Net 118 Id Name Pins Flat Pins 1 usbEngine1 wb_ack_o 2 usbEngine1 susp_o 3 usbEngine1 udfinta 4 wbArbEngine s1 s1_we_o 5 wbArbEngine s1 si_cyc_o 6 wbArbEngine s1 si_stb_o 7 usbEngine1 wb_data_o 31 amp D amp D amp amp lt Figure 10 15 Bundle Net Properties Nets Tab Adjusting Bundle Net Defaults You can define the color line width and signal count range in the view specific settings of the Themes dialog box Tools gt Options gt Themes gt Bundle Nets
139. rectangle in any of the workspace views to select objects 1 Use one of the following e View gt Select Area from the main menu or e Click the Select Area toolbar button Objects that the rectangle surrounds or touches are listed in the Select Area dialog box with which you can filter selection by type shown in Figure 4 26 qd Select Area Objects to select 10 Pblocks 5 O Rectangles 6 Figure 4 26 Select Area Dialog Box 2 Turn off the check box to filter Object types from selection 3 Click OK to select all of the checked objects Selecting Primitive Parent Modules The Select Primitive Parents command lets you select the parent modules for selected primitive logic To access the command select Select Primitive Parents from the popup menu available in most views Floorplans are easier to maintain when logic modules are assigned to Pblocks rather than primitive logic instances Select a group of timing paths to select the primitive logic instances contained on the paths The Select Primitive Parents command selects the parent modules automatically for selected primitive logic The originally selected primitive logic is no longer selected The command interpolates what is selected and returns with only modules selected unless ROOT level logic was originally selected If you select modules the command does not select parent modules the pre selected modules remain selected Setting Selection Ru
140. region statistics Printing the Device View You can print the Device view using the File gt Print command which prints the current viewable area To print the entire Device view zoom to fit and then print Opening Multiple Device Views You can open multiple Device views for the same floorplan This enables you to work on different areas of the device To open a second Device view display select Window gt Device A separate tab opens for the second Device view Device 2 You can then split the view using the dragging technique described in the Splitting the Workspace page 105 to view different design aspects Figure 4 45 shows an example of a split view 0000000 mene Vu G fh A 2 zd v REEE NE ee SS eS a G a amp g fo gO g amp amp Gop G go Ja atal 2 t d aii ez at dtz so at gt to Ja a Mi Seel 70 1 gt E Device 2 x 1 gt e Figure 4 45 Displaying Multiple Device Views Using the Package View PlanAhead User Guide The Package view displays the physical characteristics of the design device and is used primarily during the I O pin planning process For information about using the Package view for I O pin planning refer to Chapter 8 I O Pin Planning Pin types display in different colors and shapes for better visualization To open the Package view
141. related to the supported Tcl commands e help Returns a list of Tcl command categories help www xilinx com 391 UG632 v13 4 January 18 2012 Tcl Console Chapter 14 Tcl and Batch Scripting g XILINX Command categories are groups of commands performing a specific function like File I O for instance help category lt category gt Returns a list of commands found in the specified category help category object This example returns the list of Tcl commands for handling objects help lt pattern gt Returns a list of commands that match the specified search pattern This form can be used to quickly locate a specific command from a group of commands help get_ This example returns the list of Tcl commands beginning with get_ help lt command gt Provides detailed information related to the specified command help get_cells This example returns specific information of the get_cells command help short lt command gt Provides an abbreviated help text for the specified command help short get_cells The PlanAhead tool GUI environment contains an area that echoes the Tcl commands as operations are performed and provides information warnings and error messages that result from tasks performed The Tcl console is located along the bottom of the PlanAhead environment and fixed to the width of the GUI Along the right side of the Tcl console just to the right of the scrollbar is an area with color
142. remote hosts See Launching Runs on Remote Linux Hosts page 306 for more information on configuring PlanAhead to run on remote hosts Generate scripts only Select this option to export and create the run directory and run script but not to launch the run from PlanAhead The script can be run at a later time outside of the PlanAhead environment 3 Click OK to create the run with the selected launch options If the selected Runs are in a state other than Not Started you are prompted to first reset the Runs prior to launching them Resetting Runs To re set a run select Reset Runs The PlanAhead tool removes the results of the selected Runs then prompts you to remove the run data from disk which is advisable run Status is set back to Not Started To reset Runs 1 Select one or more Runs in the Design Runs view 2 Press www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using the Design Runs View e Shift click or e Ctrl click for multiple selections 3 Select the Reset Runs popup command The Reset Runs dialog box prompts you to remove all implementation data from disk for the selected Runs 4 Inthe confirming dialog box click Reset If any ISE processes are currently running or queued you are prompted to stop them 5 Click Yes to proceed The status for the selected Runs is reset Deleting Runs The Delete command removes selected Runs from the Design Runs view and re
143. required steps for running I O Port and clock related DRCs See I O Port and Clock Logic and Placement DRC Rule Descriptions page 426 for information on running netlist and floorplan related DRCs Running I O Port and Clock Logic Related DRCs To select and run individual rules 1 Select e Tools gt Run DRC from the main menu or e Run DRC from the Flow Navigator The Run DRC dialog box opens as shown in Figure 8 27 page 279 278 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Validating I O and Clock Logic Placement G Run DRC Results Name results_1 Output File a Rules to Check 52 of 52 m a A t SFM OORT x Mi Global 4 M IBUFG to DCM connectivity IDCM M DCM to BUFG connectivity DC M Number of BUFGs allowed i DCM DCMN iM DCM and BUFG connectivity DC SM Bank 16 S M DCI 1 iM DCI Cascade Checks DCIC Z a IDLY 1 iM IDelayCtri Checks IDLYCTRL E a 10 Standard 13 W Bank IO standard Vcc BIVC gt Bank IO standard Support BIVB gt Bank IO standard Termination BIVT W Bank IO standard Vref BIVR iM Bank IO standard Vref utilization BI VRU M Bank IO standard internal vref conflict BIIYVRC Bank IO standard limits BISLIM iM Bank IO standard YRN VRP Occupied DCIP M Inconsistent Diff pair IOStandards DIFFISTD M Inconsistent Diff pair IOStandards DIFFISTDDry iM Inconsistent Diff pair IOStandards DIFFISTDSlew i
144. runs synth_1_7 bft srp 1 Release 13 1 xst 0 40b nt 2 Copyright c 1995 2011 Xilinx Inc All rights reserved 3 gt Reading design bft prj 4 STABLE OF CONTENTS 6 1 Synthesis Options Summary 7 2 HDL Parsing 8 3 HDL Elaboration 9 4 HDL Synthesis 10 4 1 HDL Synthesis Report 11 5 Advanced HDL Synthesis 12 5 1 Advanced HDL Synthesis Report 13 6 Low Level Synthesis 14 7 Partition Report 15 8 Design Summary 16 8 1 Primitive and Black Box Usage 1 8 2 Device utilization summary 18 8 3 Partition Resource Summary 19 8 4 Timing Report 20 8 4 1 Clock Information 2L 8 4 2 Asynchronous Control Signals Information 22 8 4 3 Timing Summary 23 8 4 4 Timing Details 24 8 4 5 Cross Clock Domains Report 25 26 27 5522222 28 Synthesis Options Summary s ee 30 Source Parameters 31 Tnnut File Name hft nra I Figure 6 8 XST Synthesis Report The Table of Contents for this report shows the type of information that can be found in the synthesis report For more information see Using the Project Summary view in Chapter 3 Using the Netlist Design Environment in Chapter 7 Analyzing Implementation Run Results in Chapter 9 PlanAhead User Guide www xilinx com 205 UG632 v13 4 January 18 2012 Chapter 6 Synthesizing the Design XILINX 206 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Chapter 7 Netlist Analysis and Constraint Defin
145. searches for design objects such as nets or instances in open designs you can use the Find Find in Files and Replace in Files commands to search for text strings in source files Use the Find command to search within a single open source file Select the Find mw command from within the Text Editor popup menu or from the toolbar icon The Find toolbar opens at the bottom of the Text Editor Enter a text string to find in the source file You can also optionally choose to highlight all occurrences of the string in the open file Figure 4 34 page 119 shows an example of the Find command toolbar www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using the Find Commands 4l 42 entity round_4 is 43 generic 44 DATA WIDTH integer 16 45 Ve 46 port 47 clk im std_logic 48 x in xType 49 xOut out xType 50 i v lt gt E Find Pata_wIDTH Find Next Find Previous Highlight 7 Match Case E Project Summary X Figure 4 34 Using Find Feature in an Open Source File You can also use Find in Files to search for a given text string in an open source file or a specified set of source files Select the Find in Files command from the Text g Editor popup menu or from the toolbar icon or select Edit gt Find in Files from the main menu You can e Enter any text string including wildcards as search criteria e Use the filtering options to search sour
146. set in the local project directory e Writes any modifications to the constraints to the copied constraint files leaving the original UCF files unchanged e Saves the design partition information and changes to ChipScope cores with the new design e Provides an option to make the new constraint set active in the project Defining the Active Constraint Set If more than one constraint set exists you must designate an active constraint set The PlanAhead tool uses the active constraint set by default when you launch the next implementation run or when you open an RTL or Netlist Design To set the active constraint set select the constraint set and click Make active from the popup menu The active constraint set appears bold and has the active designation in the Sources view as shown in Figure 3 23 a S a ot E ve Frame_gen y work E o Frame_check work Gd bft vhdl work Do wb_conmax_top work o usbf_top work o or1200_top work e magtTop work o fftTop v work i o top work Constraints 3 fj constrs_1 active J top ucf J o rjh_top ucf target 3 6 constrs_2 J top_full ucf target a constrs_3 top_fipn ucf target 3 Simulation Only Sources 1 E sim_i 1 8 o bft_tb v work E RTL Netlist Timing Constraints Figure 3 23 Setting the Active Constraint Set Using Module level Constraint Files The PlanAhead too
147. set is one or more constraint files that are maintained independently and concatenated into a single UCF for analysis and implementation A constraint set defines the constraint files to be used at specific moments or under specific conditions in the design process By defining multiple constraints sets you can for example specify different active constraints to resolve floorplanning and timing problems A constraint set must include at least one UCF in order to save any design constraints If the constraint set does not include a UCF the PlanAhead tool reports an error when attempting to save the design Creating Constraint Sets In the PlanAhead tool you can define constraints at various stages of the design flow including RTL Design Netlist Design Implementation and Analysis Figure 3 21 page 59 shows the Create Constraint Set Name dialog box in the Add Sources command www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Managing Constraints G Add Sources Add or Create Constraints Specify or create constraint files for physical and timing constraint to add to your project If there are multiple files then please choose the target which is where all of the constraints created by PlanAhead will be saved Specify Constraint Set G Create Constraint Set C Make active Create Constraint Set Name amp Enter Constraint Set Name Add Files Create File
148. shows the Choose Endpoint Path Groups dialog box G Choose Endpoint Path Groups Find names of type path groups Options With pattern Regular expression Ignore case Ignore command errors Find results 15 Selected names 6 i TS_cpuclk A TS_FFtClk 15 _phy_clk_pad_0_i Bg _phy_clk_pad_1_i T5 _usbck T5_wbClk v synthetic_master_1 Command get_path_groups TS_cpuClk TS_FFtClk T5_phy_clk_pad_0_i T5_phy_clk_pad_1_i TS_usbClk TS_wb Concatenate commands of all the types Figure 7 22 Choose Endpoint Path Groups The options are PlanAhead User Guide Find Names of Type Filters the points based on path groups With Pattern Defines the pattern expression used to filter the design elements This field is modified with the following options e Regular Expression Specifies the search string uses regular expression syntax e Ignore Case Specifies that the search string is case insensitive Ignore Command Errors Suppresses warning messages generated during Tcl command processing of the timing report Find Command button for launching a search based on the defined expression Find Results Contains the results of the object search e Move Item to the Right Moves the currently selected object from the Find Results column to the Selected Names column e Move Item to the Left Moves the currently selected object from the Selected Names column to
149. specified paths By adding values to the various fields you can generate a report focusing on the paths of interest The available fields are e Start Points Lets you choose the synchronous elements to begin the paths for analysis The Start Point fields are e From Contains an expression used to filter the starting points Enter text in this field to manually create the filter or view the filter text created by the Choose Start Points dialog box e Choose Start Points Opens a dialog box used to build expressions that filter the starting points This dialog box is described in further detail in Understanding the Choose Points Dialog Box e Transition Further filters the paths according to the active clock edge of the starting point synchronous elements This field contains the following values Rise Filters starting point synchronous elements to those triggered by a rising positive clock edge Fall Filters starting point synchronous elements to those triggered by a falling negative clock edge Rise Fall Includes both rising and or falling clock edges e Through Point Groups Enter paths that travel through a set of points for analysis The following fields are available www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Running Timing Analysis Through Contains an expression used to filter the paths based on the points the path travels through Ch
150. the Find Results column e Move All Items to the Right Moves items from the Find Results column to the Selected Names column www xilinx com 235 UG632 v13 4 January 18 2012 Chapter 7 Netlist Analysis and Constraint Definition g XILINX e Move All Items to the Left Moves items from the Selected Names column back to the Find Results column e Selected Names Contains the currently selected path groups e Command Contains the Tcl command used to represent the selected objects Using Slack Histogram Timer Settings You can specify the delays parameters used by the slack histogram timing engine in the Timer Settings tab of the Generate Slack Histogram dialog box The Timer Settings tab is shown in Figure 7 23 G Generate Slack Histogram for Endpoints Histogram name results_1 Interconnect estimated v Speed Grade 3 default v Multi Corner Configuration Corner Name Delay Type Slow min max 7 Fast min_max Enable timing pessimism removal Command create_slack_histogram delay_type min num_bins 10 s Open in a new tab Figure 7 23 Generate Slack Histogram for Endpoints Dialog Box Timer Settings Tab The Slack Histogram Timer Settings options are e Interconnect Selects the type of delay values used for the interconnect delay The delay values are e Estimated Uses estimated delays for the interconnect values e None Sets interconnect delays to 0 e Speed Grade
151. the Generate Bitstream command Figure 2 4 shows the Program and Debug button Refer to Chapter 12 Programming and Debugging the Design for more information Working with Designs PlanAhead User Guide The PlanAhead tool lets you open designs at various stages of the design process A design is defined as a netlist elaborated RTL or synthesized a constraint set and a target device The PlanAhead tool loads the design into memory for analysis constraint definition or ChipScope debug core insertion The Flow Navigator has buttons for RTL Design Netlist Design and Implemented Design The Implemented Design loads the specific design data used to launch the run You can open the RTL and Netlist Designs with different target devices and or constraint sets allowing experimentation and constraints version control You can analyze the design at various stages of completion including elaborated RTL synthesized netlist or the implemented results You can perform constraint modifications such as timing or floorplanning at any phase by opening the corresponding design Constraint change management is made possible by the ability to create and manage multiple constraints sets The available design levels of abstraction that you can open as designs in the PlanAhead tool environment are e RTL Design Elaborated RTL design constraint set and target device e Netlist Design Synthesized netlist constraint set and target device e Implemen
152. the Netlist Design button from the Flow Navigator e Click Flow gt Open Netlist Design and specify the name to use for the Netlist Ei Design the constraint set and the target part The PlanAhead tool creates a new Netlist Design as specified With the design open the PlanAhead tool opens the Design Analysis view layout to for you to examine design logic and hierarchy view the resource utilization and timing estimates run DRCs and apply timing and physical constraints www xilinx com 207 UG632 v13 4 January 18 2012 Chapter 7 Netlist Analysis and Constraint Definition XILINX G project_cpu_hdl C PlanAhead_Install planAhead testcases PlanAhead_Tutorial Projects project_cpu_hdl project_cpu_hdl ppr PlanAhead 13 3 0RO The default views presented in the Design Analysis view layout include the Project Summary Device Netlist Sources Timing Constraints and Physical Constraints views as shown in Figure 7 1 Fie Edit Flow Tools Window Layout View Help Hem CEPR HOSGOSKZEG Project Manager RTL Design Synthesize Netlist Design F Resource Estimation J Power Estimation Run pre E Report Clock Networks Q Report Timing MY Slack Histogram Set up ChipScope Implement Implemented Design x Program and Debug Netlist Design netlist_1 cc Netlist es AE top 4 Nets 1025 Primitives 155 E cpuEngine E FFtEngine FftTop il matEngine mat Toy H usb
153. the number of instances for which to create Pblocks e Preview Displays the number and names of Pblocks to create based upon the defined parameters Click OK to create the specified Pblocks The PlanAhead tool creates the Pblocks and adds them to the list of defined Pblocks in the Physical Constraints view You can select a Pblock to examine its contents and attributes in the Pblocks Properties view The Auto Create Pblocks command does not add Pblocks to the Device view It creates the Pblock constraint and assigns logic elements to the Pblock After creating the Pblocks you must place them onto the device Running the Automatic Pblock Placer When you create Pblocks in an open Netlist Design or an Implemented Design you can place the Pblocks onto the FPGA logic in the Device view using Tools gt Floorplanning gt Place Pblocks The Pblock placer automatically sizes and places Pblocks based on SLICE content only Other logic elements are ignored by the Place Pblocks command while the PlanAhead tool sizes and places Pblocks The command provides a quick placement of the specified Pblocks to let you view the data flow through the design modules Note The resulting Pblocks from the Place Pblocks command might not be suitable for implementation You might need to resize the Pblocks manually to account for non SLICE based logic elements To run the Pblock placer 1 Select Tools gt Floorplanning gt Place Pblocks The
154. the power analysis The actual activity for each individual element are calculated based on the seed plus any value from user input files user overrides and results from the vectorless estimation engine PlanAhead User Guide www xilinx com 183 UG632 v13 4 January 18 2012 Chapter 5 RTL Design XILINX E Project Summary Device x Power Estimation x Power Summary Estimated power consumption is shown for xc6vix 5tff784 3 Avectorless RTL analysis is used with applied constraints with the resources taken from the RTL resource estimation Note that this is an early estimation and can change after implementation Total On Chip Power 2 536 W E Transceiver 452 MW 18 Junction Temperature 53 6 C 1 0 124 mW 5 Thermal Margin 31 4 C 14 2 W O Core Dynamic less 911 mW 36 Effective SJA 2 2 C W E Clock 198 mW 22 Confidence Level High O Logic 107 MW 12 Temp Grade Commercial E Block Memory 353 MW 29 Process Typical E Block Arithmetic 122 mW 13 Characterization Advance E Clock Manager 131 mW 1499 v1 1 2010 02 22 1049 mW 41 E Device Static Em Setti Default Activity Rates Power Supply Currents Power Utilization Clock Utilization 9 Go O38 mW 2 of total usbClk 190 5 MHz 37 mW 1 of total fftClk 142 9 MHz 033 mW 1 of total amp phy_clk_pad_O_i 90 9 MHz 033 mW 1 of total amp phy_clk_pad_1_i 90 9 MHz 030 mW 1 of total amp cpuClk
155. the related BUFR are placed at mutually Error route able locations e IOBUFIO which checks that a regional clock terminal and the related BUFIO are placed at mutually route able locations Design lock PLDL Checks for invalid LOC constraints Error 426 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Table B 16 Placer DRCs I O Port and Clock Logic and Placement DRC Rule Descriptions Rule Name Rule Abbrev Rule Intent Severity Valid placement PLVP Checks for constraints that would lead to an infeasible Ertot placement Valid placement PLIO Checks for valid placement of I O Error IOB DRCs Table B 17 lists the IOB DRCs abbreviation intent and severity Table B 17 IOB DRCs Rule Name Rule Abbrev Rule Intent Severity Port Properties PORTPROP Check for inconsistencies within the properties of a port Error Differential I O pads IODI Differential I O P and N signals should be LOCed in Error dedicated differential pair I O Standard Type IOSTDTYPE Ensures that a Diff pair I O Standard has been applied to Warning diff pair pins only Number of IOs IOCNT Indicates whether more I O Ports are defined than there Warning are pins in the target device I Os placement IOPL I Os placement on disallowed site Included in the IOPL Error are e IOPR which checks that a port is not placed on a prohibited pin e IOLVDSCC which checks that differential output s
156. to output pad offset Period 0 amp Path delay FROM TO amp Basic group TNM C Duty Cycle amp Multi group TIMEGRP amp Object false path C Input jitter amp Group false path amp Feedback Period Specification Cancel Figure 7 11 Create New Timing Constraint Dialog Box 2 On the left select the type of constraint you want to create The appropriate fields display on the right 3 Define the constraint values 4 Click OK For more information about timing constraints and timing constraints syntax see the Constraints Guide UG625 cited in Appendix E Additional Resources Removing Timing Constraints To remove the constraint from the design select a constraint or group of constraints in the Timing Constraints view and select Delete from the popup menu You are prompted to remove the selected constraint s prior to the removal of the constraint Note Due to the interdependence between timing constraints removing one constraint could result in the removal of several other related constraints Adding editing and deleting timing constraints cannot be undone www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Running Timing Analysis Running Timing Analysis Timing analysis of the Netlist Design is useful for ensuring that paths are covered by needed constraints to help ensure effective implementation As more physical constraints such as Pbloc
157. ug789_pa_tcl_commands pdf e PlanAhead Tutorials http www xilinx com support documentation dt_planahead_planahead13 4_tutorials htm IP Documents Quick Front to Back Flow Overview UG673 I O Pin Planning UG674 RTL Design and IP Generation UG675 Design Analysis and Floorplanning UG676 Debugging with ChipScope UG677 Tcl and SDC UG760 Team Design UG839 Design Preservation UG747 Partial Reconfiguration UG743 Reconfiguration with Processor Peripheral UG744 This document references documentation available from the following page of the Xilinx website http www xilinx com support documentation axi_ip_documentation htm PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 439 Appendix E Additional Resources XILINX 440 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012
158. unregistered outputs You can improve the Warning pipeline register multiplier clock to out performance by adding a level of registers In addition for best results avoid using asynchronous control signals on these registers Found RAM ROM with unregistered outputs You can improve the RAM ROM clock to out performance by adding a level of registers In addition for best results avoid using asynchronous control signals on these registers Inefficient RPIP Found register_name file_name 1ine_number register with Warning pipeline register asynchronous control signals on input or output of multiply function Dedicated DSP hardware resources do not have asynchronous control signals such as preset or clear The registers cannot be mapped into the dedicated hardware resources resulting in suboptimal use of the device Found Black RPBX Component Module component module_name description Warning Box instance not unavailable during Synthesis i1e_name line Paths to and from belonging to this black box cannot be optimized Synthesis tool utilization estimates UniSim library and mapping decisions could be negatively affected Found latch in RPLD Found latch description for signal signal_name Warning design file_name 1ine_num Latches creates difficult to analyze timing paths which require post Implementation simulations to ensure implemented design match expected behavior Found RPCL Found combinatorial loop for signal signal_name Warning co
159. views except the Flow Navigator and expands the selected view to fill all available screen area When one view is maximized all other open views are minimized and placed temporarily at the side or at the bottom of the maximized view You can also minimize a specific view at any time by selecting Minimize in the upper right corner of the view In Figure 4 4 the Properties Netlist and Sources views are minimized at the side of the maximized Device view Clicking on any of these minimized views restores it to its original location 94 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using the Main Viewing Area O V E Project Summary X a Properties B Netlist Sources 2 60 Figure 4 4 Minimized views make room for Maximized views Floating Views You can un dock views including the workspace from the display docking area so that it floats and can be moved and sized independently To float a window e Click Float Frame or fm e Select Float from the popup menu When you activate the floating option the view appears in a separate floating window In the case where windows overlap you can move it by dragging the view banner after you float the window You can move a floating window outside of the main window The PlanAhead tool stores the default locations and sizes in which to display floating views Closing Views You close the views by clicking on the X ic
160. warning or error message in the Messages view and the PlanAhead tool opens the selected file in the Text Editor You can also open the PlanAhead tool Journal and Log files in the Text Editor by using the File gt Open Log File and File gt Open Journal File as appropriate www xilinx com 157 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX Creating a New Text File You can use the File gt New File command from the main menu to create a new file and open it for editing in the Text Editor This is useful for creating text files that capture portions of the Tcl Console Compilation logs or errors or warnings from the Messages view This command opens a file browser for you to navigate to the desired folder and to specify the name of a new file to be created Text Editor Commands The Text Editor commands are available from the B save File Ctrl 5 popup menu or from the view specific toolbar buttons Save File s The commands are wal Undo Ctrl4z e Save File Saves the individually displayed file e Save File As Lets you rename and save a file q pate 2 Copy Text Ctrl C e Undo Redo Reverses changes in sequential Eh Paste Ctrl order Duplicate Selection Ctrl D e Cut Copy Paste Delete Cuts or copies selected Find Ctrl F text to the clipboard pastes the contents of the Replace Ctrl R clipboard to the current location or remove the PTENT EFA A nagent select
161. ways to launch the I O Planning view layout e Select the I O Planning layout in the Layout menu or from the Layout selector e Create anew Pin Planning project using the New Project wizard The following references in Chapter 4 Using the Viewing Environment apply to the I O Planning environment e Using the Device View page 129 e Using the Package View page 133 e Using the I O Ports View page 153 e Using the Package Pins View page 154 e Using the Design Runs View page 155 Figure 8 1 page 253 shows the I O Planning environment Viewing Device Resources The Device and Package views display a graphical representation of the device and placed logic resources When any logic object or device site is selected in any view information displays in the Properties view The Properties view often has tabbed panes to display various types of information as shown in Figure 8 2 page 254 To view properties for a selected object display the Properties view If the Properties view is not visible select the Obj ect_Type Properties popup menu command on the object or select Window gt Properties You can search for specific objects or device sites by using the Find command There are a variety of searchable object types and robust filtering capabilities to search the device or design for specific objects You can select objects directly from the Find Results view for more information refer to Using the Find Results View in Chapter 4
162. 012 Chapter 15 Using PlanAhead With Project Navigator XILINX Floorplan Area IO Logic Post Synthesis You can use the PlanAhead tool design analysis and floorplanning environment prior to or after Implementation To analyze the design or to perform floorplanning from Project Navigator after running logic Synthesis and prior to Implementation e Inthe Processes pane expand User Constraints and select Floorplan Area IO Logic PlanAhead Post Synthesis or e Select the Tools gt PlanAhead gt Post Synthesis Floorplan Area IO Logic command When PlanAhead is invoked Project Navigator passes the synthesized NGC or EDIF format netlist and the UCF s to the PlanAhead tool It opens with the default design analysis and floorplanning environment displaying Note In Project Navigator set the Translate process property Macro Search Path sd to the appropriate directory if lower level NGC format core files are used in the design and are not added as sources When you save or close the PlanAhead tool project it updates the original Project Navigator source UCF s and resets the Project Navigator design process state if appropriate Refer to Passing Logic and Constraints page 404 for more information about the integration mechanics and process Refer to Chapter 5 RTL Design for more information about using the PlanAhead tool environment prior to Implementation For more information about using it after Implementation see Cha
163. 1 VJ RAMB16 output registers RBOR lvl RAMB 1 Ma FIFO 1 Open in a new tab Figure 7 33 Run DRC Dialog Box 5 Click OK to invoke the selected DRC checks The DRC Results view displays the rule violations found grouped under the various rule categories defined in the Run DRC dialog box shown in Figure 7 33 The rule violations are also categorized by severity and color code A violation can be e Informational only to make you aware of a possible issue shown with a yellow marker e A warning or a critical warning to suggest an issue that might need some resolution shown with an orange marker e Anerror to highlight issues that prevent proper implementation of your design shown with a red marker PlanAhead User Guide www xilinx com 249 UG632 v13 4 January 18 2012 Chapter 7 Netlist Analysis and Constraint Definition XILINX Viewing DRC Violations After the DRCs are completed the DRC Results view opens as shown in Figure 7 34 C3 project_1 C PA_Project ChipScope_Project bft_core project_1 project_1 ppr PlanAhead 13 1 Ox File Edit Flow Tools Window Layout View Help Search 4 Fee oe xX Dd 0 MAS OG AX E G Desig analysis RQOG Fe amp Netlist Design netlist_1 xc Project Manager RTL Design Netist E Project Summary x Device x gt Synthesize Netlist Design E Resource Estimation a arnd4 round 4 Runorc amp Sources Netlist Timing Constraints
164. 13 48 54 2010 IZ 13 Mapping design into LUTs l4Running directed packing 15 Running delay based LUT packing 16 Updating timing models 17 INFO Map 215 The Interim Design Summary has been generated in the 18 mrp 19 Running timing driven placement 20 Total REAL time at the beginning of Placer 45 secs 21Total CPU time at the beginning of Placer 41 secs 22 23 Phase 1 1 Initial Placement Analysis 24Phase 1 1 Initial Placement Analysis Checksum lcc64 REAL time 51 25 lt E Project Summary X s Mi Figure 9 12 Viewing Report Files When viewing reports you can e Browse the report file using the scroll bar e Select the Find or Find in Files buttons to search for specific text e Use the Go to the beginning or Go to the End toolbar buttons to scroll to the beginning or end of the file Viewing Messages The Messages view provides a filtered list of the Compilation log that includes only the main messages warnings and errors The view has further filtering capabilities using view toolbar buttons to show only errors or warnings Figure 4 7 page 97 shows an example Messages view The implementation messages are organized by ISE command and severity Click the expand and collapse tree widgets to view the individual messages The command buttons on the left provide searching and filtering capabilities The Show Search Collapse All and Expand All options are described in Using Tree Table Style
165. 19 GusbClk_ibuffibufg o net fo 1 0 000 0 818 E BUFGCTRL_xOv9 D usbClk_ibuf bufg T BUFG 0 250 1 068 E BUFGCTRL_X0Y9 lt usbClk_ibuf bufg O net fo 407 2 033 3 101 E RAMB36_X1Y1 pblock_usbEngine0 D usbEngineD usbEngineSRAM BU2 UI0 blk_mem_generator valid cstr ramloop O ran Total 3 101 3 101 gt General Report Instances Options fe Selection Figure 11 9 Path Properties View Report Tab The report has a similar format to the TRACE report e By default selecting a path also selects all instances contained within the path e Selecting any of the objects in the report cross selects the object in other open views such as the Netlist and Device views e Select multiple paths using the Shift and Ctrl keys e All instances contained in the selected paths are selected but the Path Properties displays information only about the first path selected You can also view the Path Properties in the larger workspace area by selecting a path in the Timing Results view and using the View Path Report command in the right mouse popup menu You can also open the Path Report by double clicking on the selected path in the Timing Results view Viewing Timing Paths in the Device View You can view timing paths in the Device view when you select a path row or rows in the Timing Results view The path is highlighted in the Device view You can select multiple paths and all instances found in the path are selected and highl
166. 2 egressFifo FifoBuffe EegressLoop 3 egressFifo FifoBuffe ElegressLoop 4 egressFifo Fifo8 EegressLoop 5 egressFifo Fi egressLoopl egressFifo FifoBuffe EegressLoop 7 egressFifo FifoBuffe ingressLoop 0 ingressFifo F ingressLoop 1 ingressFifo Fifo8 e MlingressLoop 2 ingressFifo FifoBuffer N lingressLoop 3 ingressFifo Fife ii ingressLoop 4 ingressFifo Fifoe ii ingressLoop 5 ingressFifo FifoBuffer N ii ingressLoop 6 ingressFifo FifoBui silable i ingressLoop 7 ingressFifo FifoBuffer_NO1_ingre Block Memory Available Estimation Device x E Project Summary x E Res 1b E Figure 7 2 Hierarchical Resource Estimation PlanAhead User Guide www xilinx com 209 UG632 v13 4 January 18 2012 210 Chapter 7 Netlist Analysis and Constraint Definition g XILINX Viewing Resource Statistics for Logic Instances The PlanAhead tool provides estimates of the number of device resources contained in the design You can display resource statistics for any logic instance including the top level in the Instance Properties view To display design resource statistics select a top level module or any instance module in the Netlist view Figure 7 3 shows the Netlist view with a top module selected Sj Nets 1002 3 Primitives 153 cpuEngine or1200_top FftEngine fftEngine fftTop matEngine matTop usbEngineO usbEngineO usbf_top usbEngine1 usbEngine1 usbf
167. 20 156 288 ixc6vix7SthF484 2 484 240 11640 46560 93120 156 288 xc6vlx75StfF484 3 484 240 11640 46560 93120 156 288 xcovix75tfF784 1 784 360 11640 46560 93120 156 288 xc6vlx7StrF784 2 784 360 11640 46560 93120 156 288 xc6vlx75tff784 3 784 360 11640 46560 93120 156 288 xc vlx130tff484 1 484 240 20000 80000 160000 264 480 xc6vlx130tfF484 2 484 240 20000 80000 160000 264 480 xc6vlx1 30tFF484 3 484 240 20000 80000 160000 264 480 xc6vlx130tff784 1 784 400 20000 80000 160000 264 480 xc vlx130tff784 2 784 400 20000 980000 160000 264 480 is i E Figure 3 8 Specifying the Default Part Available devices display in a scrollable list Information about the device resources displays in a table view You can filter the list to help you select a target device using the Product Family Sub Family Package Speed Grade and Temp Grade filters at the top of the dialog box You can also use the Search command to limit the listed devices to those matching the search criteria you specify 1 Select a device in the device list and click Next Note You can change the Default Part when opening an RTL or Netlist Design and during synthesis and implementation The New Project Summary page opens 2 To initiate the project in the Summary page click Finish The project environment then displays with the Project Manager related views available PlanAhead User Guide www xilinx com 43 UG632 v13 4 January 18 2012 Cha
168. 2012 Chapter 9 Implementing the Design XILINX 308 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Chapter 10 Floorplanning the Design The PlanAhead tool supports a floorplanning methodology that allows you to constrain critical logic to ensure shorter interconnect lengths with less delay This methodology requires user interaction with the physical design It is not a push button design flow You can use the analysis capabilities in the PlanAhead tool coupled with your own knowledge of the design to define constraints and set tool options for improving performance Floorplanning can be accomplished by e Creating physical block Pblock locations to constrain logic placement or e Locking individual logic objects to specific device sites The Floorplanning View shows the more common views used during floorplanning To open the Floorplanning View select e Layout gt Floorplanning or e Select Floorplanning from the Layout Selector on the toolbar menu The complexities of floorplanning require more explanation than is practical to provide in this user guide For detailed information see the Floorplanning Methodology Guide UG633 cited in Appendix E Additional Resources Working with Pblocks The process of floorplanning begins by dividing some or all of the logic in the design into groups and constraining that logic The PlanAhead tool provides the ability to hierarchical
169. 3 1 File Edit Flow Tools Window Layout View Help Netlist Design netlist_1 Hea max a gt dw E a s yes Project Manager RTL Design T Physical Constraints 00x Netlist 00 q OS ee A E netlist _1 a 520 S E ROOT EE Nets 1024 521 anne E pblock_phy_rst_pad_0_o_OBUF ee eA oe cpuEngine 1_top 4 E Netlist Design H fftEngine S s23 E mgtEngine mot Ee E Resource Estimation E usbEngined u i id rinore E usbEngine a 525 zi il wbArbEngine X 526 ER Run Noise Analysis g 527 Report Timing a IM Slack Histogram i 530 5 Set up ChipScope F 531 B 532 gt TRS Erat tng Coe q 7 gt 534 Implement Source File Properties yeti 535 emented De 4 gt Blk 536 mattop v 537 j 538 NEAD Location C PlanAhead _InstalliplanAheadtestcas 539 A Type Verilog z 540 Library ork z 541 542 Size 167 8 Kb 543 Modified 6 15 10 10 33 10 AM 544 CopiedTo project_cpu_hdl srcs sources_t imports 545 Copied From C Plandhead_Installplanahead testc 546 Copied On 6 15 10 8 33 10 AM 547 Read only 548 549 lt 20 550 G Properties Clock Regions Selection eee Device x mgtTop v x assign tied to_ ground vec i 64 20000000000000000 assign tied_to_vec_i 1 bi assign tied_to_vee_vec_i 8 hff always posedge wb_clk begin if wh_sel_i 4 hc ready i lt 1 bl else ready i lt 1 bO Re ee ed Wishbone
170. 3 4 January 18 2012 g XILINX Analyzing Clock Interactions Fast are Corner Selects the delay types used for the fast corner analysis The values None Specifies that no delays are used Max Uses maximum delays for the clock and data paths during setup and hold analysis Min Uses minimum delays for the clock and data paths during setup and hold analysis Min_Max Uses a combination of minimum and maximum delays for the clock and data paths during setup and hold analysis Enable timing pessimism removal Removes the skew delay generated by the common clock path between source and destination registers when modeling on chip delay variation Viewing the Clock Interactions Matrix E Project Summary X Device x Ts TS_cpuclk TS_fFtClk TS_phy_clk_pad_0_i TS_phy_clk_pad_1_i Launching Clocks TS_usbClk TS_wbClk Launching Clock 1 TS_cpuclk TS_cpuclk TS_fFtClk TS_fFtClk TS_fFtClk TS_phy_clk_pad_0_i TS_phy_clk_pad_O_i TS_phy_clk_pad_O_i TS_phy_clk_pad_0_i TS nhy clk nad 1i H Clock Interaction results_1 x Ducy Receiving Clocks TS phy cik oag Y clk 7 7 TS fo Wad oy Lt a oe 1 L 1 N No Paths 1 Receiving Clock TS_cpuclk TS_wbclk TS_cpuclk TS_fFtClk TS_wbclk TS_cpuclk TS_phy_clk_pad_t TS_usbClk TS_wbCclk TS_cnuck U Unconstrained P Partially Constrained F Fully Constrained 2 WNS Asynchronous Pat
171. 391 Tel Console ois istic te bit cee hei be eee ee 392 Invoking the PlanAhead Software 0 00 0 c eee ees 392 General Tcl Syntax Guidelines 0 0000s 393 First Class Tcl Objects and Relationships 0 0 00008 396 Errors Warnings Critical Warnings and Info Messages 400 Wel Referent s 5 4iie bib die tba Lhe bid Ohad eee eee ed 400 Chapter 15 Using PlanAhead With Project Navigator PlanAhead Processes within Project Navigator 0005 403 Appendix A PlanAhead Input and Output Files Input Files sess creio Meda teenie tsa OV i a UIT ENO Re eee IWS 409 I O Port Lists CSV Pile Paral cu cc secs einwdr wager enn nurnerr errre 410 Outputs for Reports 024405 4 c os pele acres ere dee eee eee 412 Outputs for Environment Defaults 0000s 414 Outputs for Project Data oo ci6i ivr d esa pen ranctannenda adnan reine ene nn Ka kinn 415 Outputs for ISE Implementation 0 0 60 c cece eee eee ees 417 Appendix B PlanAhead DRCs RTL DRCs Power and Performance 0 00 e cece eee eee 421 Floorplannin DRES cesis ikers yeah aie ve Le ed ee LG 4 423 I O Port and Clock Logic and Placement DRC Rule Descriptions 426 Appendix C Installing Releases with XilinxNotify PlanAhead Release Strategy 00 00 coc cece eee eee 431 Running XNMxX NOY visas espi capers ete vad es Cad nepi Ep ei kp ey i 431
172. 3_4 ug750 pdf EDK Documentation You can also access the entire documentation set online at http www xilinx com support documentation dt_edk_edk13 4 htm Individual documents are listed below EDK Concepts Tools and Techniques UG683 http www xilinx com support documentation sw_manuals xilinx13_4 edk_ctt pdf EDK Profiling Guide UG448 http www xilinx com support documentation xilinx13_4 edk_prof pdf Embedded System Tools Reference Manual UG111 http www xilinx com support documentation xilinx13_4 est_rm pdf MicroBlaze Processor User Guide UG081 http www xilinx com support documentation sw_manuals xilinx13_4 mb_ref_guide pdf Platform Specification Format Reference Manual UG642 http www xilinx com support documentation xilinx13_4 psf_rm pdf PowerPC 405 Processor Block Reference Guide UG018 http www xilinx com support documentation user_guides ug018 pdf PowerPC 405 Processor Reference Guide UGO11 http www xilinx com support documentation user_guides ug011 pdf PowerPC 440 Embedded Processor Block in Virtex 5 FPGAs UG200 http www xilinx com support documentation user_guides ug200 pdf EDK Additional Resources EDK Tutorials website http www xilinx com support documentation dt_edk_edk13 4_tutorials htm Platform Studio and EDK website http www xilinx com ise embedded_design_prod platform_studio htm XPS EDK Supported IP website http www xilinx
173. 5 153 0 4 100 o M E 252 63 63 Figure 11 16 Properties View Set Metric Range Values Displaying the Metric Maps in the Device View To display a Metric map in the Device view select the desired metric s in the Metrics view and from the popup menu select Show The PlanAhead tool displays a color based metric map Figure 11 17 is an example Om wy z Primitive Metrics 1 i Min Slack per placed BEL CLB Metrics 4 a FF Utilization per CLB amp Vertical routing congestion per CLB a Horizontal routing congestion per CLB Pblock Metrics 6 e LUT Utilization per Pblock a FF Utilization per Pblock amp Estimated Slice Utilization per Pblock a Min Slack per Pblock a Total Negative Slack per Pblock QO Netlist Bl Physical Con Timing Constr GS H q H H H H H H 3 en Metric Properties f Og X o Riz S a x 1a LUT Utilization per CLB RR de st Y Summary of LUT resources consumed by LOC Constraints Details Helps to visualize LUT densities of your placed gt design a4 i z s gt m 4 lt Mil i tA Device x E Project Summary x duit f Figure 11 17 Metric Map in the Device View You can display multiple metric maps simultaneously e To display any of the slack related metrics run timing estimation first using Report Timing e To display any of the CLB or BEL constraints type metrics import the placement results from ISE implement
174. 50 0 135 7 TS_usbClk PERIOD TIMEGRP usbCik 5 25 ns HIGH 50 0 094 4 Figure 3 39 Timing Results in Project Summary View Partition Summary For Implemented Designs that have partitions defined the Project Summary view also provides a Partition Summary to allow you to quickly view the status of all partitions The Partition Summary provides a post implementation report of the attributes of each partition and values such as State Preservation Level and BoundaryOpt Refer to Chapter 13 Using Hierarchical Design Techniques and Partial Reconfiguration User Guide UG702 cited in Appendix E Additional Resources for more information on defining and using partitions www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Configuring Project Settings Configuring Project Settings Each project has specific settings that can be configured to meet specific needs These project settings include general settings related to the top module definition and language options simulation settings synthesis settings implementation settings and IP Catalog settings The PlanAhead tool provides access to the project settings from a variety of views and menus Based upon how you invoke the project settings the dialog box displays the settings Select IP Catalog Settings from the IP Catalog view to open the Project Settings dialog box with the IP Catalog settings displayed To open the Project Settings dialog bo
175. 63 usbEngineOsusb_dma_ usbEngineO u4 Funct_adr_O CE 4 087 1 891 53 7 5 TS_usbclk TS_usbClk 1 163 usbEngineOsusb_dma_ usbEngineO u4 Funct_adr_1 CE 4 087 1 891 53 7 5 TS_usbclk TS_usbClk 1 163 usbEngineO usb_dma_ usbEngineO ut Funct_adr_2 CE 4 087 1 891 53 7 5 TS_usbclk TS_usbClk 1 163 usbEngineO usb_dma_ usbEngineO u4 Funct_adr_3 CE 4 087 1 891 53 7 5 TS_usbclk TS_usbClk 1 163 usbEngineO usb_dma_ usbEngineO u4 Funct_adr_4 CE 4 087 1 891 53 7 5 TS_usbclk TS_usbclk 1 163 usbEngineO usb_dma_ usbEngineO u4 Funct_adr_5 CE 4 087 1 891 53 7 5 TS_usbclk TS_usbClk 1 163 usbEngineO usb dma usbEnaineO u4 funct adr 6 CE 4 087 1 891 53 7 5 T5 usbCik T5 _usbClk Report Timing results_1 10 paths x Group by Constraint Figure 7 18 Sorted Timing Results and Group by Constraint Flattening the List of Paths By default the paths are categorized by constraint You can flatten the list and view all paths by clicking Group by Constraint button in the Timing Results view toolbar as shown in Figure 7 18 The Group by Constraint toolbar button toggles between a list of paths grouped by constraint and a flattened list of paths Removing Paths from the Timing Report You can remove paths from the timing report to make for easier sorting and viewing of critical paths 1 Select the paths to remove paths from the timing report To select multiple paths press the Shift or Ctrl keys and select the paths 2 Press the Delete key
176. 8 O Pin Planning XILINX Viewing the WASSO Analysis Results The analysis is performed across the entire device first and then within each I O bank as they relate to their neighboring I O banks The WASSO Results view displays in the workspace as shown in Figure 8 36 Device Parameters Board Parameters Board Thickness Finished via diameter Pad to via breakout length Breakout width Allowed Utilization Status Maximum ground bounce Socket inductance Capacitance per output driver Other PCB parasitic inductance Package 100 22 3 OK Banks Bank 0 100 42 7 OK Bank 1 100 20 OK Bank 2 100 1 3 OK Bank 3 100 9 3 OK Bank 4 100 14 7 0K Bank 5 100 42 7 OK Bank 6 100 24 OK Bank 7 100 24 OK Heighbors Bank 0 1 100 31 3 OK Bank 1 2 100 10 7 OK Rosle 2 2 LANH L LN AIZ 600 0 n 15 0 pF 62 0 mils 12 0 mils 33 0 mils 12 0 mils 0 0 nH 0 0 nH Hil Package Device FH WASSO results_1 x 10E Figure 8 36 WASSO Results Notice that the report lists allowable loading utilization and status for I O banks and neighboring pairs 290 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Chapter 9 Implementing the Design The PlanAhead tool features a push button flow with single synthesis and implementation attempts or runs Run data is managed automatically allowing repeated run attempts with varying e Regist
177. 8 39 2009 ERREGRERE aalala Build PlanAhead v11 1 LRO by ECloudinternalUser4 on Thu Feb 5 20 04 57 PST 2009 10 Bank Pin Number IOB Alias Site Type Min Trace Max Trace Prohibit Interface Signal Name Direction DiffPair Type DiffPair SignilO Standard Drive mA Slew Rate P2 OPAD_XDYS MGTTXPO_114 34878 40691 TXP_OUT 4 OUT P TXN_OUT 4 LVDS_25 W2 OPAD_XOY MGTTXP1_114 41406 49307 TXP_OUT 5 OUT P TXN_OUT 5 LVDS_25 B2 OPAD _X0Y13 MGTTXPO_116 63540 74130 TXP_OUT 6 OUT P TXN_OUT 6 LVDS_25 G2 OPAD _X0Y15 MGTTXP1_116 55620 64890 TXP_OUT 7 OUT P TXN_OUT 7 LYDS5_25 17 AD16 OB_XOY8 O_L1I5N_17 80604 94038 DataOut_USB_ OUT LYCMOS25 17 AE15 OB_XOY6 O_LI6N_17 89010 103845 DataOut_USB_ OUT LYCMOS25 17 AC21 OB_XOY17 I0_L11P_CC_17 47370 55265 DataOut_USB_OUT LYCMOS25 17 AE16 OB_xOYS O_L15P_17 78702 91819 DataOut_USB OUT LYCMOS25 17 AE21 OB_XO 22 IO_L8N_CC_17 63150 73675 DataOut_USB_ OUT LYCMOS25 17 AD20 OB_xOY18 IO_L10N_CC_17 62046 72387 DataOut_USB_ OUT LYCMOS25 17 AC23 OB_XO 26 IO_LBN_17 58710 68495 DataOut_USB_OUT LYCMOS25 1 AFI7 OB_XOY1O 10_L14N_VREF_17 80994 94493 DataOut_USB_ OUT LYCMOS25 17 AD24 OB_XOY36 IO_LIN_17 64386 75117 Dataln_USB_OIN LVCMOS25 Figure 8 11 WO Port List CSV Format 260 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Defining and Configuring I O Ports CSV is a standard file format used by FPGA and board designers to exchange
178. 8 ouput will improve performance Both mul DPOP 11 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul Q results_1 224 violations x E Tel Console Messages E Compilation 2 DRC Results Design Runs RTL Flow Figure 5 15 RTL Design with Objects that Violate DRCs When you select a violation message in the DRC Results view you can use the Violations Properties command in the popup menu to open the Violations Properties view This view lets you see both a general review of the DRC rule violation and specific details of the design elements that violate the rule The Details tab of the Violations Properties can have links to specific design objects that violate the DRC Click the links to view the design object in the RTL Netlist view the Device view the Schematic or the source RTL file PlanAhead User Guide www xilinx com 195 UG632 v13 4 January 18 2012 Chapter 5 RTL Design XILINX 196 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Chapter 6 Synthesizing the Design The PlanAhead application includes a Synthesis and Implementation environment that facilitates a push button flow with single synthesis and implementation attempts or runs The PlanAhead tool manages the run data automatically allowing repeated run attempts with varying Register Transfer Level RTL source version
179. 83 3 MHz 027 mW 1 of total amp wbClk 111 1 MHz lo Utilization E124 mW 5 of total top Logic Utilization Q B62 mW 2 of total fftEngine 1988 Flops 1975 LUTs 014 mW 1 of total 8 whArbEngine 880 Flops 3165 LUTs 011 mW lt 1 of total usbEnginel 4638 Flaps 6418 LUTs 111 mW lt 1 of total BJ usbEngineo 4638 Flops 6419 LUTs 19 mW lt 1 of total couEngine 3913 Flops 5387 LUTs 1 lt 0 1 mW lt 1 of total i mgtEngine 715 Flops 710 LUTs O O O O O Block Memory Utilization m 353 mW 14 of total top Block Arithmetic Utilization E122 mW 5 of total top Clock Manager Utilization E13 1 mW 5 of total top Gigabit 10 Figure 5 7 Power Estimation View Utilization 22 mM EK of tota top 184 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Estimating Power Analyzing Power Distribution The Power Estimation view as displayed in Figure 5 7 page 184 features a Power Summary and a Power Utilization e Power Summary Summarizes the power distribution and provides a summary of the device environment used in power calculations e Click the links to view or hide details To modify any parameter return to step 2 and 3 under Estimating Power page 182 e Confidence Level Review the confidence level to ensure sufficient input data was
180. 891 53 7 5 TS_usbclk TS_usbClk usbEngineO u4 Funct_adr_3 CE 4 087 1 891 Sanh 5 TS_usbclk TS_usbClk usbEngineO u4 Funct_adr_4 CE 4 087 1 891 53 7 5 TS_usbclk TS_usbClk 1 163 usbEngineO usb_dma_ 1 163 usbEngineO usb_dma_ 1 163 usbEngineO usb_dma_ 1 163 usbEngineO usb_dma_ usbEngineO u4 Funct_adr_5 CE 4 087 1 891 53 7 5 TS_usbclk TS_usbClk Setup 1 163 usbEnaineO usb dma usbEnaineO udsFumct adr 6 Ce 4 087 __1 891 _53 7 5 TS _usbClk __TS_usbClk Group by Constraint PlanAhead User Guide Figure 11 7 Sorted Timing Results and Group by Constraint www xilinx com 349 UG632 v13 4 January 18 2012 Chapter 11 Analyzing Implementation Results XILINX Flattening the List of Paths By default the paths are categorized by constraint You can flatten the list and view all paths by clicking Group by Constraint button in the Timing Results view toolbar as shown in Figure 11 7 The Group by Constraint toolbar button toggles between a list of paths grouped by constraint and a flattened list of paths Removing Paths from the Timing Report You can remove paths from the timing report to make for easier sorting and viewing of critical paths 1 Select the paths to remove paths from the timing report To select multiple paths press the Shift or Ctrl keys and select the paths 2 Press the Delete key or select Delete from the popup menu in the Timing Results view Note You cannot undo a delete command to re
181. Analysis command from the main menu Depending on the Xilinx device targeted by the design the PlanAhead tool performs either a Simultaneous Switching Noise SSN or a Simultaneous Switching Output SSO analysis e For Spartan 6 Virtex 6 Virtex 7 Kintex 7 and Artix 7 devices the PlanAhead tool performs SSN analysis See Running SSN Analysis for more information on this type of analysis e For Spartan 3 Virtex 4 and Virtex 5 devices the PlanAhead tool performs SSO analysis See Running WASSO Analysis page 289 for more information Running SSN Analysis PlanAhead User Guide The PlanAhead tool uses the SSN predictor to provide detailed analysis of simultaneous switching output noise in Spartan 6 Virtex 6 Virtex 7 Kintex 7 and Artix 7 devices SSN analysis provides estimates of the disruption that simultaneously switching outputs can cause on other output ports in the I O bank as well as input ports in the case of Spartan 6 devices The SSN predictor incorporates I O bank specific electrical characteristics into the prediction to better model package effects on SSN I Os are grouped into separate isolated I O banks each with its own unique power distribution networks and each with unique responses to switching activity Because power distribution networks within a packaged FPGA have different responses to noise it is important to understand not only the I O standards and number of I O in a design but also the response of the devic
182. Area and draw a rectangle around multiple instances ports and nets When you select instances in the Schematic view they are also selected in all other views as shown in Figure 4 51 The cross selection works also when you select or highlight objects in other views so that they are highlighted in the Schematic view Netlist ox E Project Summary X Device X Schematic x Pe gt i 79 Instances SOPorts 89 Nets idle_cnt_clr_GND_365_o0_AND_2216_o_r A i B idle_cnt_clr_idle_cnt1 7 _AND_2213_o_r D m ty sa me cne cirit i B idle_long_glue_set i idle_long_idle_cnt_clr_OR_880_o i idle_long_ps_cnt_clr_OR_878_o i b opt suw PSU Fihn f lopt_621 AR 5 i lopt_622 a lale long e a i lopt_623 i m opt_624 FOR ee ee s_idle E i gt pey 4 ae Fraz n stare FSW Faz i sr 3 Er EE l x EH Zz eae FEU FOTOS ry rau reese i sare fau Phin Eem t i i e H s i Is_k_r_rstpot 5 os a j R eee i la la re ls_se0y x P x08 A OON FoR e lt i gt LUTE p E amp Sources P Netlist Timing Constra F H SEN F e FOR saw PSU Fii state FSW Fatt stare PGW FRI it jet Properties E HE BD z T4 amp idle_long T Fratt n4 Os Id Name Pin Cell Pins G1 usbEngine0 u0 u0 state_me 14 LUT6 Zz BE A 2 usbEngine0 u0 u0 state_su I1 LUT4 F 3 usbEngine0 u0 u0 state FS 10 LUTS G 4 usbEngineO uO uO state_FS IS LUT6 F 5
183. BEL Constraint Mode www xilinx com 331 UG632 v13 4 January 18 2012 Chapter 10 Floorplanning the Design XILINX D ION Oe J a A cool J foo 2 gt r A E A c 1 Figure 10 23 Create BEL Constraint SLICEM The dynamic cursor does not allow instance placement to an illegal or occupied gate site PlanAhead indicates a legal placement site when the dynamic cursor changes from a slashed circle to an arrow After location constraint assignment is complete return to the default Assign Bid instance to Pblock mode by clicking Assign Instance Mode u To view location constraint properties select the placement constraint and view the Instance Property view Adjusting the Visibility of Placement Constraints To change how assigned placement constraints display adjust the zoom level e From a zoomed out view the LOCs and BELs display as a filled in rectangle inside the assigned site e When the zoom level increases the logic displays as being assigned to specific logic gates within the site Figure 10 24 page 333 shows the Device view zoomed out and zoomed in and the different details displayed at different zoom factors 332 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 Working with Placement LOC and BEL Constraints XILINX hd A g Em l l ee TTT TT TTT E TUTTE EET TTT To
184. Bank 2 Id Name Prohibit Port I O Std Dir Veco Bank Type Diff Pair Clock Voltage Min Trace Dly Max Trace Dly Input VYVVYVYVVYVVYVVVYVVYVVVVVVVVVVVY 2 5 2 User IO L N 35 32 41 21 IC 2 5 2 User IO L8P 13 69 15 97 IC 25 2 User IO L8N 6 86 8 01 I 2 5 2 User IO LOP 25 72 30 01 IC 2 5 2UserIO LON 24 71 28 83 IC 25 2 CCO 2 9 2 CCO General Package Pins I O Ports Clock Regions Figure 8 33 WO Bank Properties Package Pins PlanAhead User Guide www xilinx com 287 UG632 v13 4 January 18 2012 Chapter 8 VO Pin Planning g XILINX Defining I O Port Switching Phase Groups in SSN Sometimes different groups of I O within a bank have a synchronous phase offset from one another meaning it is not possible for them to switch simultaneously This is true of data and strobe signals in many memory interfaces In this case proper SSN accounting must be informed by phase information A phase group is a logical grouping of ports that are all in phase with each other from a timing perspective their clocks have the same frequency and phase When you create a grouping phase not only the group created but I Os with a different phase are separated Note Phase groups are supported in Virtex 6 devices only The noise produced by the groups within a bank is summed to get the total noise for that bank and if all outputs are either in phase with each other or do not have a synchronous relationship th
185. C Table B 11 lists the Netlist DRC Table B 11 Netlist DRC Rule Name Rule Abbrev Rule Intent Severity Driverless Nets NDRV Checks that each net has a proper driver pin Warning Instance DRC Table B 12 lists the Instance DRCs Table B 12 Instance DRCs Rule Name Rule Abbrev Rule Intent Severity Black Box INBB Checks that there is no blackbox undefined logics in the netlist Warning Instances Attribute DRCs Table B 13 lists the Attribute DRCs Table B 13 Attribute DRCs Rule Name Rule Abbrev Rule Intent Severity Invalid attribute AVAL Checks for invalid attribute values Warning Undefined ADEF Checks for undefined attribute values Warning attribute Required Pin DRC Table B 14 lists the Required Pin DRC Table B 14 Required Pin DRCs Rule Name Rule Abbrev Rule Intent Severity Unconnected REQP Required pin not connected Warning pin 425 PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com Appendix B PlanAhead DRCs XILINX I O Port and Clock Logic and Placement DRC Rule Descriptions The I O Port and Clock Logic DRCs available in PlanAhead is not an exhaustive list of I O related DRCs Consult the device documentation for more information about I O ports and clock region specifications In some cases the Severity level issued by PlanAhead might differ from the severity level of the same condition reported by ISE Implementation tools Selecting DRC Rules page 194 provides other DRC rule descriptions Gl
186. CF is then passed to the PlanAhead tool The PlanAhead tool supports Project Navigator projects with more than one UCF source file Before the PlanAhead tool is invoked a dialog box prompts you to select one of the UCF files e New constraints defined in the PlanAhead tool are written to the selected UCF e Any physical constraints that exist in a non chosen UCF remain in that file even if the value of that constraint is modified The Project Navigator design flow does not pass core level NCF files to the PlanAhead tool To use or view any physical constraints in these files you must merge them manually into a top level UCF prior to invoking the PlanAhead tool Project Navigator creates a temporary PlanAhead design project in the ISE project directory and removes and replaces this project every time you invoke the PlanAhead tool from Project Navigator I O Pin Planning Pre Synthesis You can elect to perform early I O pin planning prior to having a synthesized netlist either by using the stand alone PlanAhead application or by selecting this process step in Project Navigator 404 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX PlanAhead Processes within Project Navigator Note At this stage of the design process logic Synthesis has not been run The tool has no concept of clock ports clock related logic differential pairs or GTs You must ensure these types of ports are placed appropriately
187. CLOCKREGION M suce X0Y0 X43Y39 DSP48 RAMB18 7 RAMB36 xOvO x2V7 v General Statistics Instances Rect 4 gt E Project Summary x Figure 10 11 Pblock Shading Reflects Logic Contained in Pblock PlanAhead User Guide www xilinx com 319 UG632 v13 4 January 18 2012 Chapter 10 Floorplanning the Design g XILINX 320 Assigning Logic to Pblocks After you create a Pblock you can assign netlist instances by either dragging and dropping logic or by using the Assign popup command To use the drag and drop method 1 Click and drag logic instances from the Netlist Schematic Hierarchy or Find Results views 2 Drop the instances into the Pblock rectangle area To use the Assign command method to assign logic to existing Pblocks 1 Select logic instances in the Netlist view 2 Select Assign The Select Pblock dialog box displays the allowable selections of the Pblock assignment as shown in Figure 10 12 G Select Pblock Assign selected instances to jp ROOT E pblock_cpuEngine E pblock_fftEngine E pblock_matEngine I pblock_usbEngine1 E pblock_usbEngine1_1 E pblock_wbArbEngine_1 i Cancel Figure 10 12 Select Pblock Dialog Box Unassigning Logic from Pblocks To remove instances from Pblocks 1 Select the instances 2 Select the Unassign popup command A confirmation dialog box opens asking you to confirm the removal of instances from the Pblock Movi
188. D_6_0_GND_6_o0_mux_40_OUT52 UT6 Tas 76 Total Logic 2 085 Net 2 846 General Report Instances Options Figure 11 8 Timing Path Property View Selecting any object in the Logical Resource column cross selects that object in all other views The PlanAhead tool provides links under the Delay Type column which invokes a PDF viewer opens the FPGA device data sheet and searches the PDF file for the selected logic site object automatically For more information about analyzing timing results using the Timing Results and Path Properties views see Chapter 7 Netlist Analysis and Constraint Definition When you select a path from the list the Path Properties view populates with information about the path Logic elements are listed with detailed delay information shown in Figure 11 9 page 352 PlanAhead User Guide www xilinx com 351 UG632 v13 4 January 18 2012 Chapter 11 Analyzing Implementation Results g XILINX Summary Name P Path Slack 0 161 Source lt usbEngine0 usb_dma_wb_in BU2 UO gen_fifo18_36 fgfifo18_36 fblk inst_few ki 1 inst_fed one_prim inst_fifoprim gfifo36 sngfifo36 fifo36_wrap_inst DOP 1 Destination usbEngineO usbEngineSRAM BU2 U0 blk_mem_generator valid cstr ramloop 0 ram r v5 ram SP WIDE_PRIM18 5P Requirement 3 800 Delay 3 961 Source Clock usbClk rising at 0 000ns Destination Clock usbClk rising at 3 800ns 5 Source Clock Path De
189. Design Runs view select one or more Runs Use Shift click or Ctrl click for multiple selections 2 Select one of the following commands e Launch Runs popup menu command PlanAhead User Guide www xilinx com 303 UG632 v13 4 January 18 2012 Chapter 9 Implementing the Design g XILINX 304 The Launch selected Runs toolbar button The Launch Selected Runs dialog box opens as shown in Figure 9 20 G Launch Selected Runs Launch Directory lea lt Default Launch Directory gt Options Launch Runs on Local Host Number of Jobs it zj Generate scripts only C Copy RTL Sources into Launch Directory Runs to Launch 1 gt impl_i i Cancel Figure 9 20 Launching Existing Runs The options are Launch Directory Specify a location to create and store the Implementation run data Note Defining any non default location outside of the project directory structure makes the project non portable because absolute paths are written into the project files Launch Runs on Local Host Launches the run on the local machine processor Number of Jobs Define the number of local processors to use for Runs This option is only used when launching multiple Runs simultaneously Individual runs are launched on each processor No multi threaded processors are used with this option Launch Runs on Remote Hosts Linux only Use remote hosts to launch a job or jobs Configure Hosts Configure
190. E pblock_matEngine E pblock_usbEngineO E pblock_usbEngine1 Figure 10 4 Pblocks in Physical Constraints To create rectangles for the newly created Pblocks 1 Select each of the new Pblocks one at a time in the Physical Constraints view 2 Inthe Device view toolbar click Set Pblock Size a P 3 Draw a rectangle in the Device view Creating Nested Pblocks You can create Pblocks within Pblocks nested Pblocks to provide further control for constraining logic This can be helpful when trying to improve performance of critical modules The top level Pblock contains all the lower level Pblocks during utilization estimates Note The ISE implementation software does not support extensive use of this feature Occasionally map and placement errors result when creating nested Pblocks Creating Pblocks with Multiple Rectangles You can also create Pblocks with multiple rectangles to create non rectangular Pblocks or to cover distant device resources without creating a single monolithic Pblock With an existing Pblock selected select Add Pblock Rectangle from the Device view toolbar menu to add a rectangle to an existing Pblock Pblocks consisting of multiple rectangles display with dashed lines connecting the rectangles to indicate that they are part of the same Pblock The assigned instance rectangles and connectivity display in the largest rectangle as shown in Figure 10 5 page 314 PlanAhead User Guide www xilinx com
191. Engine E usbEngine0 i usbEngine1 usb S E wbArbEngine 29 Design Analysis Run orc E Report Clock Networks Q Report Timing WE Slack Histogram S Set up ChipScope gt Implement Sources i Netlist Implemented Design Properties py gt G Program and Debug Design Runs ets e A Name Part Constraints Strategy Status Progress Start Elapsed Util I V synth_1 xc k7OtFbg676 2 constrs_1 Plandhead Defaults X5T 13 XST Complete a 100 8 18 11 7 31 AM 00 04 54 53 Sv impli xc7k70tfbg676 2 constrs_1 Rodin Implementation Defaults RDI 13 route_design Complete i 100 8 18 11 3 26PM 00 25 29 lt E Td Console Messages E Compilation Design Runs RTL Flow Figure 2 5 Open Netlist Design e For more information on using the Design Analysis view layout to analyze and constrain the design refer to Chapter 7 Netlist Analysis and Constraint Definition e See Chapter 8 I O Pin Planning for more information about using the I O Planning view layout for I O pin planning Setting the Active Netlist If multiple synthesis runs exist the PlanAhead tool displays information about and reacts to the active run The active run displays in bold text in the Design Runs view The Project Summary Compilation and Messages views display information about the active run only Select the Synthesis Run in the Design Runs view then use the Make active popup menu command to set the acti
192. Engined u u usbEngine1 u wbArbEngine Sources P Netlist Properties z Design Runs a Ps aa S Name Part 5v synth_1 xc7k70tfbg676 2 Sv impl_1 xc7k70tFbg676 2 lt I Tel Console Messages G Compilation Design Runs Figure 7 1 Netlist Design Analysis View Layout Constraints Strategy constrs_1 Planahead Defaults XST 13 00x Start Elapsed Util 100 8 18 11 7 31 AM 00 04 54 53 constrs_1 Rodin Implementation Defaults RDI 13 route_design Complete I 100 8 18 11 3 26PM 00 25 29 RTL Flow The PlanAhead tool provides default configurations of many of the design views and presents them as View Layouts You can open other views if needed including the Package view For more information about using specific views see Using Common Views page 122 You can save the arrangement of any opened views under a user defined view layout so you can restore frequently used view configurations See Using View Layouts in Chapter 4 for more information 208 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Viewing and Reporting Resource Statistics Viewing and Reporting Resource Statistics In an opened Netlist Design statistical information about the design logical content and device utilization is available in the Project Summary view This includes a e Resources pane with resource utilization estimates for the elabor
193. File no_coe_file_Inacded Browse Number of Coeficient Sets 1 Number of Coefficients per set 21 Filter Specification Filter Type Single Rate Rate Change Type Integer Interpolation Rate Vakie p Ranga 1 41 Decimation Rate value ange 1 1 Interleaved Channel Configuration Channel Sequence Fixed Incement Number of Channels 1 Range 1 64 Selact Patter All Pattem List P4 0 P4 1 P4 2 P Hardware Oversameling Specification Select format Frequency Specification v Input Sampling Frequency 0 001 Range 0 000001 950 0 MHz Clock Freguency 300 0 Range 0 001 550 0 MRE Input Sample Pariad r Clock cycles 7 a aera P ppup peee anaiai ire 9 isi YPM q Freq Resp 4 Implementation Da q Coefficient Rel patasteot ea Pag 1of4 Agde paman canei _ Hep Figure 3 27 CORE Generator Interface The interface fields define the parameters of the IP that allow you to customize the IP for use in your design The CORE Generator interface varies depending on the type of core you have selected and can include one or more pages of parameters to define The CORE Generator interface also includes the IP symbol the Frequency Response graph and Implementation Details related to resource consumption You can toggle through these different view by selecting the appropriate tab the bottom left of the interface When you have completed defining the various parameters of the interface click Genera
194. Further assistance adopting Planahead Flows PlanAhead Tutorials RY a m Invaluable for first time users or to try new features Figure 1 1 PlanAhead Software Getting Started Page XILINX The PlanAhead tool Getting Started page assists you with creating or opening projects as well as viewing the documentation To display the Getting Started page close all open projects Using the Getting Started Page The Getting Started page displays when you invoke the PlanAhead tool Click the command links to run specific commands or to view documentation The Getting Started options are e Create New Project Invokes the New Project wizard which lets you create any type of PlanAhead design project e Open Project Invokes a browser enabling you to open any PlanAhead design project ppr file e Open Recent Design Displays the last 10 previously opened projects Ten is the default to change this number use Tools gt Options gt General The PlanAhead tool checks to ensure the project data is available before displaying the projects e Open Example Project Provides four sample design projects e A small RTL project BFT Core bft ppr e A larger RTL project CPU HDL e Anetlist based project CPU synthesized e An IP example with three embedded IP cores from CORE Generator Wave HDL You can use this design as a reference project to see how you can use IP cores with PlanAhead design projects
195. General Project Manager RTL Design TE ChipScope st I Device x Schematic x Schematic 2 x 4 gt E Ar EOE ET 2 AE a D aei gt rz Name BA bft amp I Gl gt Nets 1957 Synthesize u_jcon chipscope_icon_v a f CONTROL _cs_ila_0 36 S cs_ila_O chipscope_ila_vi amp GND_6_0_GND_6_0_mux_39_OUT 32 I tae CLK amp egressFifoEmpty 1 Cho wb amp fifoSelect a Netlist Design F Resource Estimation ppe Hb TRIGO amp fifoSelect 6 _fifoSelect 7 _mux_40_OUT Run prc a TRIG 8 amp loadingressFifo 8 Unassigned nets 65 va MMW fi Run Noise Analysis Hf n0114 amp n0115 are amp n0116 3 amp Report Timing fn amp n0117 amp n0118 Jili Slack Histogram amp n0119 32 amp n0120 32 Set up ChipScope gt Bus Net Properties v amp Es amp whInputData 32 amp whOutputData 3 Sil GND_6_o_fifoSelect 7 _equal_27_o lt 7 gt 1 Implement gt ale e GND_6_of _equal_27_ Ee E GND_6_0_fifoSelect 7 _equal_27_o0 lt 7 gt 2 29 o kanon a amp validForEgressFifo Name validForEgressFifo Z Ss gt General Scalar Nets Program and Debug Tcl Console Ogd nl sSet_property mark debug true get_nets match_style ucf n0114 31 n0114 30 n0114 29 n0114 28 n0114 27 n0114 26 n0l1l4 25 4 set_property mark debug true get_nets match_style ucf n0115 0 nO115 1 nO0115 2
196. I O Ports To better manage Gigabit Transceivers GTXs the I O Planning views group the two related I O diff pairs and the GTX logic object automatically during selection placement and moving The GTX objects are selected as one object and move together which prohibits illegal assignment of the GTX resources If the online DRCs are enabled the noise sensitive I O pins surrounding the GTXs are prohibited automatically during port placement Refer to Disabling or Enabling Interactive Design Rule Checking page 268 Removing I O Placement Constraints You can remove placement constraints by selecting placed logic and then selecting the Unplace command from the right mouse popup menu Refer to Working with Placement LOC and BEL Constraints in Chapter 10 for information on selectively removing placement constraints www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Placing Clock Logic Placing Clock Logic You can manually place global and regional clock related logic such as Global Clock Buffers BUFGs DCMs or MMCMs BUFRs and IDELAYCTRLSs using the Clock Resources view as discussed in Using the Clock Resources View page 275 You can also manually place clock logic in the Device view Appropriate logic sites are displayed in the Device view for all device specific resources To locate logic instances for placing onto the device such as BUFGs 1 Select Edit gt Find 2 Specify
197. ISim Specifying Simulation Options When you select the Options button the PlanAhead tool opens the Simulation Options form This form includes the previously specified top level module and three option tabs PlanAhead User Guide www xilinx com 361 UG632 v13 4 January 18 2012 362 Chapter 11 Analyzing Implementation Results g XILINX Launch Options Specify command line options for the fuse compiler and the ISim tool Language Options Specify details of the Verilog or VHDL language used by the simulation netlist Netlist Options Define options for the NetGen program to create the Verilog or VHDL netlist from the implemented FPGA design The following subsections describe these simulation options Launch Options Click the Launch Options tab of the Simulation Options dialog box shown in Figure 11 21 to control the execution of fuse and ISim tools G Simulation Options i Specify Options For timing simulation Top Module Design Under Test bt Launch Options Language Options Netlist Options Simulation Run Time 1000ns Unit Under Test incremental nodebug tclbatch rangecheck wdb lt Default WDB Filename gt weFg Load glbl SAIF Filename SDF Delay sdfmax More Fuse Options More Simulator Options Select an option above to see description of it i Cancel Figure 11 21 Timing Simulation Launch Options The options are e Simulation Run Time Specify length of s
198. In this case there is no clock interaction and nothing to report e A green cell indicates properly constrained paths cross from the launching clock to the receiving clock All the paths have been constrained with the use of the FROM TO constraint Note The diagonal line in which the launching clock and the receiving clock are the same is always green e An orange or yellow cell indicates partially constrained clock domain crossing Some of the paths through the logic are properly constrained but some paths are not constrained This could be due to paths that are implied in the RTL and so are not properly constrained in the netlist design e A red cell indicates an unconstrained clock interaction None of the paths crossing between clock domains have the required FROM TO constraint Green or Black is the desired result in this matrix A red or yellow cell highlights a potential timing problem Note that the color of a cell in the matrix reflects the state of the constraints between clock domains not the state of timing of the paths between the domains A green cell does not indicate that the timing is good only that timing paths are constrained across clock domains The table below the matrix shows the state of the timing The table below the matrix displays the path with the worst case negative slack for each clock interaction This provides details not initially displayed in the matrix above The table does not include paths from cells i
199. LK e SCLKBWRCLK DIADI 01BDI DIPADIP O0IPBDIP SENARDEN RAD INJECTDBITERR DOPBDOP SINJECTSBITERR ECCPARITY aaah aa arecadi IREGCEB SBITERR usbf_wb RIX Pi ee STRAM IRSTRAMB RSTREGARSTREG RSTREGB Sven RAMB36E1 async_fifo_1_buffer_fifo FifoBuffer_usb_dma_wb_in ERIRE Vv j gt E Project Summary X 1 gt B Schematic x 1 Figure 11 13 Logic Expanded in the Schematic View PlanAhead User Guide www xilinx com 355 UG632 v13 4 January 18 2012 Chapter 11 Analyzing XILINX Implementation Results Also you can expand and display instance and module connectivity and content interactively For more information about exploring logic in the schematic see Using the Schematic View page 136 Searching for Objects using the Find Command After the placement displays in the Device view you can use Find to search for and locate any type of logic The Edit gt Find dialog box provides flexibility for filtering the search criteria in many different ways For more information about searching for logic objects see Searching and Replacing in Source Files page 118 Using Select Primitives and Highlight Primitives Commands Netlist After you import the ISE placement you can use Select Primitives to select the underlying primitive logic elements for Pblocks and logic modules This command is often used in conjunction with Show Connectivity Fix Instances or Clear Placement
200. LOST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION Copyright 2011 2012 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries PCI PCle and PCI Express are trademarks of PCI SIG and used under license All other trademarks Synopsis AXI Mentor Graphics are the property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 03 01 11 13 1 e Added integration with ISim for timing and behavioral simulation e New GUI that facilitates the push button flow e Ability to create a project from Project Navigator files e New clocking reSources View e New Main Menu Search e New Pin Planning and Banking Rules e New sort capabilities e Ability to export IBIS models N ew message management that consolidates error critical warning warning and information messages e Ability to customize text editor including the ability to add a third party text editor e New Archive Project feature e Ability to tag nets for debug in ChipScope e Ability to add a legend in Device View Schematic legend PlanAhead User Guide www xilinx com UG632 v13 4 January 18 2012 Date 07 06 11 Version 13 2 Revision Clock Domain Interaction Report See Analyzing Clock Interactions in Chapter 7 Open TRACE
201. M Vecaux voltage requirement for LYCMOS25 VC AL iM ecaux voltage requirement for LYPECL_33 and TMS lt o W Configuration Mode CFGM SM DCI 2 M DCI Cascade with part compatibility OCICPC Mi DCI Cascade IO standard DCICIOSTD SM ClkBuf 1 Mi BufR amp BufIO Locations BUFRIOC SM IOB 10 Mi Inconsistent port properties PORTPROP 108 clock sharing 10C5 ol lt Select All Clear All Figure 8 27 Run DRC Dialog Box I O Pin and Clock DRC Rules 2 View or edit the Results Name field Enter a name for the results for a particular run for easier identification during debug in the DRC Violations browser The output file name matches the entered name 3 Inthe Rules to Check group box use the check boxes to select the design rules to check for each design object For information about each rule see I O Port and Clock Logic and Placement DRC Rule Descriptions page 426 e Expand the hierarchy using the Expand All toolbar button orclickthe p next to each category or design object e Click the check box next to design object to run all DRCs e Select individual DRCs or click All Rules to run a complete DRC all rules for all design objects 4 Click OK to invoke the selected DRC checks PlanAhead User Guide www xilinx com 279 UG632 v13 4 January 18 2012 Chapter 8 O Pin Planning XILINX Viewing DRC Violations If violations are found the DRC Results view open
202. Manual Compile Order Specifies that the hierarchy view should not be automatically updated and that the compilation order is determined manually To update the design hierarchy in this mode use the Refresh Hierarchy command Refresh Hierarchy Updates the design hierarchy to reflect the latest source file changes and top module definition Use this command to manually refresh the hierarchy as needed Set as Top Specifies the Top Module to define the starting point for elaboration of the design hierarchy for synthesis and simulation purposes See Specifying the Top Module and Reordering Source Files in Chapter 3 www xilinx com 125 UG632 v13 4 January 18 2012 126 Chapter 4 Using the Viewing Environment g XILINX The top level module is identified by a special icon in the Hierarchy tab of the Sources view ae Set Global Include Defines the specified file as a global include file This command is only available for use with Verilog source files See Defining Global Include Files in Chapter 6 for more information Note The Global Include attribute can also be set from within the Source File Properties view see Viewing Source File Properties page 127 e Clear Global Include Clears the Global Include attribute from the selected Verilog source file Make active Makes the selected Constraint Set the active constraint set for synthesis or implementation Set as Target Constraint File For Constr
203. NET fftClk 20 21 Multi cycle paths for ALU 22NET cpuEngine or1200_cpu or1200 alu TPTHRU GRP_ALU DATAOUT 23 TIMESPEC TS_ALU_MCP FROM cpuClk THRU GRP_ALU DATAOUT TO cpuClk TS_cpuClk 2 24 Multi cycle paths for LSU 25 NET cpuEngine or1200_cpu or1200 lsu TPTHRU GRP_LSU 26 TIMESPEC TS_LSU_MCP FROM cpuClk THRU GRP_LSU TO cpuClk TS_cpuClk 2 Qed WPaAX BLS 29 1 0 and GT Constraints 30 INST cpuEngine pm_clksd_o 0 I0B TRUE 31 INST cpuEngine pm _clksd_o_ 1 I0B TRUE 32 INST cpuEngine pm_clksd_o 2 I0B TRUE 33 INST cpuEngine pm_clksd_o 3 I0B TRUE 34 lt Figure 7 9 Text Editor For more information about the commands and features available in the Text Editor see Using the Text Editor page 157 Using Constraint Templates Common UCF templates are available for use in the Text Editor to assist with defining new constraints The PlanAhead tool also provides standard Verilog and VHDL language templates as well as predefined UCF templates Selected templates can be instantiated into any file that is open in the Text Editor See Instantiating Language or Constraint Templates page 159 216 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Defining Timing Constraints Using the Timing Constraints View You can use the Timing Constraints view to display edit and create timing constraints for the design PlanAhead provides a view o
204. NX Defining and Configuring I O Ports DCI Cascade Editor Name Master Sites Side gt EE EA a faa iO Bank 25 ef Figure 8 15 Creating a DCI Cascade 3 To include additional I O banks click Add Preselected I O banks appear in the dialog box Select I O banks from the same column on the device The software does not check this interactively when you create the DCI_CASCADE constraint but checks later when you run DRC 4 Select an I O bank to be the Master 5 Click OK As I O banks are selected they are highlighted in the other views The DCI Cascades are displayed in the Physical Constraints View See Figure 8 16 page 266 When you select a cascaded I O bank in the Physical Constraints View all I O banks from that group are selected View and edit details in the Properties View PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 265 Chapter 8 O Pin Planning 266 5 constrs_1 EI ROOT B DCI Cascade 1 O Bank 25 amp Sources E mm Clock Re Timing C QI Netlist DCI_CASCADE Properties fea ee abn gt Balt x DCI Cascade 24 Name Master Sites Side SESS a oo TEE S ES Package Pins A Name Prohibit Port I O Std A Ham I O Bank 15 45 lt 9 LTO Ham IO Bank 34 45 D 1 0 Ports 9 Package Pins Figure 8 16 Viewing DCI Cascades XILINX As you select DCI cascades in the Physical Constrai
205. Netlist view changes to highlight that the module is defined as a partition and a Partition tab appears in the Instance Properties view as shown in Figure 13 1 The Partition tab reports the locations and dates of each time the Partition was promoted Netlist Og g x x P top W Nets 1002 W Primitives 153 w 8 cpuEngine or1200_top ia fftEngine fftEngine fftTop w 2 mgtEngine matTop w Gj usbEngineO usbEngine0 usbf_top esa mAsbEnginel usbEngine1 usbf_top it WibArbEngine wb _conmax_top amp Sources I Netlist E Physical Constraints amp Timing Constraints Slk usbEngine1 Type Partition Partition Status Not Promoted General Statistics Pins Children Attributes Connectivity Partition Figure 13 1 Setting Partitions in the Netlist View After a partition is set in the project the top level of the design automatically becomes a partition as well You can treat this top level partition like any other partition implement or import it as needed during design iterations Configuring Synthesis and Implementation Runs with Partitions Defining partitions in a design automatically enables the XST incremental flow This incremental flow implements individual netlist files NGC for each partition including the top level partition and results are then imported into the Netlist Design For more information on synthesis see Chapter 6 Synthesizi
206. O36E1 This attribut Figure 4 8 Wrap Messages Critical Warnings and Frrors are also displayed in a popup dialog when loading a Netlist Design and at the start of any Implementation Runs as shown in Figure 4 9 This is to ensure that you are aware of any issues that might require your attention These messages can also be found in the main Messages view G Open Design Critical Messages A There were 4 critical warning messages while opening this design Messages fo ALGAI O Incorrect value VIRTEX6 specified For property SIM_DEVICE file toy ALGAI 0 Incorrect value VIRTEX6 specified for property SIM_DEVICE file to ALGAI 0 Incorrect value VIRTEX6 specified for property SIM_DEVICE file to ALGAI 0 Incorrect value VIRTEX6 specified for property SIM_DEVICE file to m Open Messages View Figure 4 9 Critical Messages Window Using the Compilation view The Compilation view displays the active output status of commands that compile the design such as ngc2edif Xilinx Synthesis Technology XST MAP and Place and Route PAR 98 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Using the Tcl Console and Messages Area Figure 4 10 shows the Compilation view that displays the standard output from the compilation commands It opens automatically when you launch a command on an active run To open the Compilation view select the e Compi
207. ON Ia My 3 F tiol 3 Rules Show dialog before switching to a different design SOO Si z Show warning dialog before closing a project Show warning dialog before upgrading an old project Show warning dialog before exiting Plandhead Ask before overwriting synthesis or implementation results Warn before viewing SSN results oO T Notifications e Show warning dialog when synthesis Fails a 3 a Ed a Show warning dialog when implementation Fails a Show information dialog when synthesis completes successfully Show information dialog when implementation completes successfully Show information dialog when bitstream completes successfully Show information dialog when bitstream Fails Show information dialog for empty TRCE results when opening Implemented Design Show dialog before adding net for ChipScope debugging Alerts Alert when non active synthesis or implementation completes successfully Alert when non active synthesis or implementation Fails cores ae Figure 4 77 Window Behavior Options Dialog Box e Warnings amp Confirmation Sets how the PlanAhead tool shows warning dialog boxes e Notifications Provides checkboxes that let you set if and how notifications display e Alerts Provides checkboxes that let you set alerts on or off upon success or failure Adding Custom Menu Commands You can add system or user defined Tcl commands to the main menu and to the
208. Place Pblocks dialog box opens as shown in Figure 10 20 page 329 2 Edit the options as follows e Parent Pblock Select the level of hierarchy to place Pblocks You can place Pblocks at The top level module ROOT Any partitioned Pblock level of hierarchy e Pblocks to place Displays the list of Pblocks that exist under the specified parent Pblock or ROOT Place Checkbox to specify the Pblocks to be placed Deselecting the checkbox causes the PlanAhead tool to ignore that Pblock and preserve existing Pblock locations Pblocks in the list that have been previously sized and placed are reset by PlanAhead and resized and replaced unless the Place checkbox is deselected Pblock Lists the name of the Pblocks within the specified level of the hierarchy Utilization Lets you set specific SLICE utilization targets for each Pblock PlanAhead sizes and places the Pblock according to the specified Utilization percentage www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Working with Placement LOC and BEL Constraints G Place Pblocks Parent Pblock pblock_cpuEngine Pblocks to place Place Pblock Utilization pblock_cpu_dbg_dat_i 87 pblock_cpu_dwb_dat_o 87 pblock_iwb_biu 87 pblock_or1200_cpu 87 pblock_or1200_dc_top 87 pblock_or1200_du 87 pblock_or1200_ic_top 87 pblock_or1200_immu_top 87 pblock_or1200_qmem_top 87 pblock_or1200_tt 87 M M M M M Set
209. PlanAhead Timing Analysis completes Figure 7 17 shows an example of timing results The Timing Results view is also available when you open an Implemented Design and run TRACE for sign off timing analysis See Analyzing Timing Results page 345 for more information Either the PlanAhead Timing Analysis or the ISE TRACE tool must be run to populate the Timing Results view with paths The Timing Results view contains the paths that meet the criteria defined in the Run Timing Analysis dialog box as described in Running Timing Analysis page 219 Name P Pathi P Path2 P Paths P Path4 Paths 2 Pathe Path 2 Paths P Paho Type S Constrained Paths 10 Setup Setup Setup Setup Setup Setup Setup Setup Setup 1 059 usbEngine0 usb_dma_ usbEngine0 u4 dout_14 D 4 191 1 771 S77 6 T5_usbCl 1 059 usbEngine1 usb_dma_ 1 163 usbEngine0 usb_dma_ 1 163 usbEngineO usb_dma_ 1 163 usbEngine0 usb_dma_ 1 163 usbEngineO usb_dma_ 1 163 usbEngineO usb_dma_ 1 163 usbEngine0 usb_dma_ A 1 163 usbEngineO usb dma usbEngineO udifunct adr 6 CE 4 087 o 8 CER Pr 5 TS_usbClk Report Timing results_1 10 paths x Slaclke From To Total Delay Logic Delay Net Stages Source Clock Destination Clock a T5_usbClk T5_usbClk TS_usbclk TS_usbclk TS_usbClk TS_usbclk TS_usbclk TS_usbClk _TS_usbClk usbEngine1 u dout_14 D 4 191 1 771 57 7 6 T5_usbCl usbEngineO u4 Funct_adr_O CE 4 087 1 891 53 7 5 T
210. PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX amp XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOSS OF DATA OR
211. PlanAhead User Guide www xilinx com 73 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects XILINX LEDs_4Bits_TRI_O Push_Buttons_4Bits_TRI_I out std_logic_vector 0 to 3 in std_logic_vector 0 to 3 RS232_Uart_1_sout out std_logic RS232_Uart_1l_sin in std_logic SPI_FLASH_SCLK inout std_logic SPI_FLASH_MOSI inout std_logic SPI_FLASH_ MISO inout std_logic SPI_FLASH_SS inout std_logic end component Ly Following the component declaration several attributes are defined that must be included in the top level HDL file Design functionality and resource utilizations are negatively affected without the inclusion of these attributes in the top level attribute BUFFER_TYPE STRING attribute BOX_TYPE STRING attribute BUFFER_TYPE of Ethernet_Lite_TX_CLK signal is IBUF attribute BUFFER_TYPE of Ethernet_Lite_RX_CLK signal is IBUF attribute BOX_TYPE of system component is user_black_box Note If the embedded processor system is instantiated lower in the design hierarchy and NOT in the top level module these attributes must still be added to the top level module and the signal names must be changed to reflect the top level ports used to connect to the appropriate component ports The component instantiation follows the attribute definitions The component instantiation should be made at the top level and the instantiation name should not be changed This simplifies constr
212. RAM Mram_snoopyRam30 usbEngineO usbEngineSRAM Mram_snoopyRam30 usbEngine1 usbEngineSRAM Mram_snoopyRam31 usbEngineO usbEngineSRAM Mram_snoopyRam31 usbEngine1 usbEngineSRAM Mram_snoopyRam32 usbEngineO usbEngineSRAM Mram_snoopyRam32 usbEngine1 u1 u0 Mshreg_d2_0 usbEngineO u1 u0 Mshreg_d2_0 usbEngine1 u1 u0 Mshreg_d2_1 usbEngineO u1 u0 Mshreg_d2_1 usbEngine1 u1 u0 Mshreg_d2_2 Cell RAMB36E1 RAMB36E1 RAMB36E1 RAMB36E1 RAMB36E1 RAMB36E1 RAMB36E1 SRLC16E SRLC16E SRLC16E SRLC16E SRLC16E Pins 223 223 223 223 223 223 223 9 Partition Top Top Top Top Top Top Top Top Top Top Top Top E Instances Type is Block Memory Type is Distributed Memory amp Name matches 94 X Figure 4 33 Find Results View The PlanAhead tool creates a new Find Results tab each time you run the Find command which is named according to the Search criteria and number of objects found You can select objects directly from the Find Results dialog box and those objects are selected in other views as well You can select multiple elements by using the Shift or Ctrl keys Additional commands are available from the popup menu To sort columns e Click any of the column headers e Press the Ctrl key and clicking a second column header To close the Find Results views click the X icon in a Find Results tab Searching and Replacing in Source Files 118 While the Find command
213. RAM is being used as a FIFO in which case the crossover point becomes a depth of 32 bits or less When building interfaces less than 18 bits wide the LUT based SelectRAM could be a better choice for depths up to 128 bits however generally past that the dedicated block RAM is a better choice for power Inefficient RPDS Small multipliers mapped to DSP or to other hard multipliers IP such as Warning mapping of MULT18X18 should be pushed to MSBs The rest of the LSBs should be small multiplier mapped to ground In this way the carry propagation is reduced to its in DSP block minimum Usual Implementation especially when inferring the multiplier uses LSBs and sign extensions to map the MSBs PlanAhead User Guide www xilinx com 421 UG632 v13 4 January 18 2012 Appendix B PlanAhead DRCs RTL DRCs Performance Table B 2 Performance Rules XILINX Rule Name Rule Abbrev Rule Intent Severity Inefficient RPWL Found instance name of type library_component_name that Warning library element belongs to another FPGA family This might result in suboptimal instantiation performance The ISE software might remap this element automatically onto a similar element in the selected family However modifying the source code to infer or instantiate native elements takes advantage of any added or expanded functionality in the element This could improve area utilization and performance Missing RPPR Found multiplier with
214. SE Placement and Timing Results page 46 344 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Analyzing Timing Results Importing Placement Results into an Existing Project You can also import placement results generated outside the PlanAhead tool into an existing project Placement constraints are assigned for all placed logic objects You can select an implemented Native Circuit Description NCD file to import and the PlanAhead tool converts the file to an Xilinx Definition List XDL format file to import the placement information NCD is the output file from PAR the ISE software place and route application To import placement results 1 Select File gt Import gt Import Placement The Import Placement dialog box opens You must have an open RTL Netlist or Implemented Design for the Import Placement command to be available See Working with Designs page 27 for more information 2 Select an NCD file in the Import Placement dialog box The PlanAhead tool automatically runs the XDL utility to convert the NCD file to XDL format and imports the results Note You can also import an XDL file directly if one exists 3 Click OK to import the placement results The PlanAhead tool imports the placement file and build an Implemented Design with the file With the Implemented Design open you can analyze the FPGA placement results performing timing analysis power analysis and timing simulation
215. S_cpuclk TS_wbClk rising TS_cpucClk rising D gt 3 cpuEngine cpu_dbg_dat_o buffer_fifo Mram_fifo_ram DIADI 0 11 284 Pin TS_cpuclk TS_wbClk rising TS_cpucClk rising p 4 cpuEngine cpu_dbg_dat_o buffer_fifo Mram_fifo_ram DIADI 1 11 284 Pin TS_cpuclk TS_wbClk rising TS_cpucClk rising p 5 cpuEngine cpu_dbg_dat_o buffer_fifo Mram_fifo_ram DIADI 2 11 284 Pin TS_cpuclk TS_wbclk rising TS_cpuclk rising p 6 cpuEngine cpu_dbg_dat_o buffer_fifo Mram_fifo_ram DIADI 3 11 284 Pin TS_cpuclk TS_wbClk rising TS_cpucClk rising p 7 cpuEngine cpu_dbg_dat_o buffer_fifo Mram_fifo_ram DIADI 4 11 284 Pin TS_cpuclk TS_wbClk rising TS_cpucClk rising Figure 7 25 Slack Histogram Log10 scale Selecting Endpoints for Analysis The Histogram provides selection and filtering of endpoints for analysis The selected endpoints display in the histogram table the bars of the histogram are not changed by the filter The selection and filter options include e Select one or more bins Click a bin in the histogram display to select it and list the endpoints of that bin To select multiple bins press Ctrl and click the bin The table updates to display endpoints from all selected bins e Filter Bars The Filter Bars command on the histogram toolbar lets you select one or more bins by dragging a selection rectangle in the histogram If you select only a portion of a bin the entire bin is selected and all of the endpoints contained in the se
216. S_usbc usbEngineO u4 Funct_adr_1 CE 4 087 1 891 537 5 T5_usbCl usbEngineO u4 Funct_adr_2 CE 4 087 1 891 53 7 5 TS_usbcl usbEngineO u4 Funct_adr_3 CE 4 087 1 891 53 7 5 TS_usbc usbEngineO u4 Funct_adr_4 CE 4 087 1 891 S37 5 TS_usbc usbEngineO u4 Funct_adr_5 CE 4 087 1 891 53 7 5 TS_usbc RAR KRRRR KR KR Figure 7 17 Timing Results You can examine sort and select specific paths and instances in the Timing Results interface In the Timing Results view the following information displays for each path Constraint Name Displays the constraint name for the paths listed Name Shows a sequential number with which to sort back to the original order Type Displays whether the path is Setup or Hold related Slack Displays the total positive or negative slack on the path e From Displays the path source pin e To Displays the paths destination pin Total Delay Lists the total estimated delay on the path Logic Delay Lists the delay attributed to logic elements on the path Net Delay Lists the delay attributed to the interconnect of the path Logic Displays the percentage of the delay attributed to logic elements Net Displays the percentage of the delay attributed to interconnect www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Running Timing Analysis e Stages Displays the total number of instances on the path including the source and destina
217. Simulation Project Settings dialog box G Project Settings QQ EE General Simulation Set E sim_1 mg Simulation Top Module Name bft_tb Lod paS E Top Module Design Under Test D Language Options Netlist options Advanced Option Simulation Run Time Unit Under Test incremental nodebug tclbatch rangecheck Implementation 1p wdb lt Default WDB Filename gt wefg IP Catalog Load glbl SAIF Filename SDF Delay sdfmax More Fuse Options More Simulator Options Simulation Run Time Specify simulation run time Figure 3 42 Simulation Project Settings Refer to Performing Timing Simulation page 361 for a description of the simulation project settings Synthesis Settings Figure 3 43 page 87 shows the Synthesis Project Settings dialog box 86 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Configuring Project Settings G Project Settings Synthesis Constraints Default Constraint Set E constrs_1 active Options Strategy lz Fast_area_reduction XST 13 Description Based on 4rea Reduction auto_bram_packing yes Implementation P use_dsp48 auto th resaurce_sharing yes iob true netlist_hierarchy rebuilt power as_optimized ram_style bufg IP Catalog equivalent_register_removal lyes mux _extract yes More Options netlist _
218. Table 10 1 Pblock Properties Tabs and Options Tab General Options e Name Displays the Pblock name e Parent Displays the Parent Pblock This field is a non editable field for some Pblocks If a Pblock has multiple potential parent Pblocks the field becomes active allowing definition of the Parent Pblock e Grid Range Enables the Pblocks to be specified with specific AREA_GROUP RANGE properties Selecting specific ranges constrains only the selected logic types within the Pblock area The grid range coordinates display for each logic type after the Pblock is created e CLOCKREGION Defines the Pblock range to be an entire clock region The Pblock rectangle is drawn to match the clock region boundary e Apply Cancel Saves or discards changes Statistics e Physical Resources Estimates A chart of each resource type in the device e Site Type The site types defined within the Pblock rectangle e Available The number of sites contained in the Pblock e Required The number of sites required for the logic assigned to the Pblock e Utilization The estimated percentage of the sites populated in the Pblock e Carry Statistics The number of vertical carry chain logic objects assigned to the Pblock It also displays the tallest carry chain assigned to the Pblock and the percentage of its height in relation to the Pblock height Carry height utilization values over 100 can cause PlanAhead DRC
219. The Project Settings displays the Project Name Device Family Default Part and Top Module Name Selecting the Edit link invokes the Project Settings dialog box Refer to Configuring Project Settings page 83 Device x frol Project Settings Project Name project_cpu_hdl Product Family Virtex6 Default Part xc6vlx7StF784 3 Top Module Name top fal Project State Status Implemented Messages O errors O critical warnings 0 warnings Messages Compilation Reports Next Step Generate Bitstream D gt Compilation Synthesis Implementation Part xc6vix7SthF784 3 Part Strategy Plandhead Defaults Strategy xc6vlx7StFF784 3 ISE Defaults Constraints constrs 1 Constraints constrs 2 Util 46 0 Util 41 0 FMax 113 968 MHz Timing Score 0 Unrouted 0 El Resources Show Table RTL Estimation Synthesis Estimation Netlist Estimation Implemented Utilization Part xc vlx75tff784 3 Register M 160 Or E 12 Sice a 62 1O E 29 Bonded IPAD pa 42 Bonded OPAD E RAMB36E1 Figure 3 36 Project Summary Project State The Project State panel contains the following information e Status Displays the project status or the status of the actively running command e Messages Summarizes the number of errors and warnings encountered during compilation commands There is also a link to open the Messages view that is filtered to show the warnings or errors e Go To Provides links to open the Me
220. The options are e Implement Launches Implementation with the current Implementation Project Settings For more information on the Implementation process see Chapter 9 Implementing the Design 204 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Analyzing Synthesis Results e Open Netlist Design Imports the netlist active constraint set and target part into the Design Analysis and Floorplanning environment so you can perform I O pin planning design analysis and floorplanning See Netlist Analysis and Constraint Definition in Chapter 7 for more information e View Reports Opens the Reports view so you can select and view the XST Report file For more information see Viewing Report Files page 297 2 Click OK or Cancel Analyzing Synthesis Results After Synthesis completes you can view the reports and open analyze and use the synthesized netlist design to apply constraints to the design before Implementation The Reports view contains a list of reports provided by the various synthesis and implementation tools in the PlanAhead tool Open the Reports view and select a report for a specific run to see details of the run Figure 6 8 shows an example report from a Synthesis run E Project Summary X 4 XST Report synth_1 x gt qa BOX Fe le A C Planahead_Install plandheaditestcases Plandhead_Tutorial Projects project_bFt_core_hdl project_bft_core_hdl
221. Tools gt Schematic from the main menu e Schematic from the popup menu in the RTL Netlist view PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 181 Chapter 5 RTL Design XILINX For more information on traversing expanding and exploring the RTL Schematic refer to Using the Schematic View in Chapter 4 After you have elaborated the RTL design you can use the Find command to search for logic objects using a range of filtering techniques Refer to Using Find Commands to Search Source Files page 176 Exploring the RTL Source Files You can also select any logic element in the RTL Netlist view and open the instantiation of that object in the RTL source file it is instantiated in or open the definition of the logic in the RTL file it is defined in To open the instantiation or definition of any selected logic in the RTL source file select the object and use the Go To Instantiation command The PlanAhead tool opens the appropriate source file with the specific instance highlighted Estimating Power The PlanAhead tool can perform power estimation to provide an early view of the power distribution of your design at the RTL level You can specify the device operating environment the I O properties and the default activity rates for the design using constraints or within the GUI The PlanAhead tool estimates the design resources needed from the HDL code and reports the estimated power from a statistical
222. Verilog code Although the entity or module name defaults to the file name it does not have to match file name e Architecture name Specify the Architecture for the RTL source file By default the name is Behavioral PlanAhead User Guide www xilinx com 53 UG632 v13 4 January 18 2012 54 Chapter 3 Working with Projects XILINX Note This field only applies to VHDL code and does not appear when defining Verilog modules e I O Port Definitions Define the ports to be added to the module definition Port Name Define the name of the port to appear in the RTL code Direction Specify if the port is an Input Output or Bidirectional port Bus Specify if this is a bus port Define the width of the bus using the MSB and LSB fields as described below MSB Define the number of the most significant bit This combines with the LSB field to determine the width of the bus being defined LSB Define the number of the least significant bit Note MSB and LSB are ignored if the port is not a bus port 4 When you have finished defining the details of each of the new modules listed under New Source Files you can click OK to create the RTL source files and add the modules to your project You will see the newly defined modules listed in the Sources view 5 Open the new source files in the Text Editor to edit as needed Double click the file or select Open File from the popup menu to open the file in the t
223. X Outputs for ISE Implementation Table A 6 Outputs For ISE Implementation Cont d Output Exported IP Description Exporting IP writes the EDIFs and UCF s for specified netlist modules for use when creating reusable IP blocks When you run the Export IP command on a selected module instance in the design it exports the Pblock logical hierarchy and placement constraints The exported files include the EDIF netlist and UCF physical constraints in the original logical netlist format This allows for easier implementation in the next design by keeping the interface identical You can use the exported UCF to re create the Pblock placement constraints You can duplicate identical placement for multiple modules by moving the modules after they are imported Figure 10 20 page 329 is an example of how Export Pblock and Export IP can be used to export different parts of the design based on either logical Export IP or physical Export Pblock hierarchy ISE Launch Scripts jobx bat sh amp runme bat sh amp ISE_command rst When you launch a run the PlanAhead tool creates ISE launch scripts automatically These scripts contain commands and command line options specified in the PlanAhead Strategy The jobx bat sh scripts are located under the project run directory ina jobs subdirectory These scripts sequentially launch each selected run The script calls each run specific runme bat sh script You can launch t
224. XILINX 402 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Chapter 15 Using PlanAhead With Project Navigator The PlanAhead application is integrated with the ISE software to let you perform specific design tasks When you invoke the PlanAhead tool from the ISE Project Navigator environment the PlanAhead tool is in ISE Integration mode In this mode the available PlanAhead features apply only to specific design tasks including I O pin planning floorplanning and timing analysis The Project Navigator environment creates and manages the PlanAhead tool project automatically The four processes in the Project Navigator Processes pane from which you can invoke the PlanAhead tool are e Pre Synthesis e I O Pin Planning e Post Synthesis e I O Pin Planning e Floorplan Area IO Logic e Post Implementation e Analyze Timing Floorplan Design The data passed between the two tools and the view layout presented in the PlanAhead tool depends upon which step you invoke Refer to the PlanAhead Processes within Project Navigator page 403 for more information on the mechanics of the integration including data passing and processes The PlanAhead tool has two default view layouts for the many design tasks e The I O pin planning environment called the I O Planning view layout which contains views pertinent to I O pin planning and assignment e The Design Analysis environment which contains views
225. XILINX Using the Design Runs View Select Window gt Design Runs to open the Design Runs view as shown in Figure 9 19 Name arl onstraints rategy atus rogress ar laps AJN Part Constraint Strat Stat Pi Start El E v synth_ xc vlx 3 constrs_ landhead Defaults omplete fo I ie gt th_1 6vlx75tff784 3 trs_1 Plandhead Defaults XST 13 XST Complete I 100 2 2 11 2 27 PM 00 V impl_ xcbvlx 3 constrs_ efaults omplete fo Hy v impl_1 6vlx75tff784 3 trs_2 ISE Defaults ISE 13 PAR Ci lete LT 100 2 8 116 524M 00 a gt impl4 xc6vix75tff784 3 constrs_2 MapTiming ISE 13 Not started CJ 0 D Sy synth_2 active xc6 ix75tff784 3 constrs_1 fast_area_reduction XST 13 XST Complete EE 100 2 8 11 8 09 4M 00 i4 gt impl_2 active xc6vlx75tfF784 3 constrs_1 ISE Defaults ISE 13 Not started 0 j synth xc6vix constrs_ imingwithoul acking lot starter fo gt th_3 6vlx75tff784 3 trs_1 Ti WithoutIOBPacking XST 13 Not started ox gt impl_3 xc6vix75tfF784 3 constrs_1 ISE Defaults ISE 13 Not started C7 0 Figure 9 19 Design Runs View Each implementation run appears indented beneath the synthesis run it is a child of You can expand and collapse synthesis runs using the tree widgets in the view Details of the runs display in table form Refer to Using Tree Table Style Views page 106 for more information on working with the columns to sort the data in this view When you select a run in the Design R
226. Y6 E AB2 TXN2 E BUFGCTRL_xovs E AE4 RXNZ E BUFGCTRL_xov4 E AB1 TXP2 E BUFGCTRL_XOYS E W4 REFC E BUFGCTRL_xov2 E W3 REFC E BUFGCTRL_xov1 E AE3 RXP2 E BUFGCTRL_XOYO E AG14 MR E AA4 REFC E MMCM_ADV_XOY1 E AF15 MR E AAS REFC E mmcm_ADy_xovo E AD15 S5R E AD2 TXN1 E AC15 5R E AG4 RXN1 E AD1 TXP1 AG3 RXP1 E AF2 TXNO E AH2 RXNO E AF1 TXPO Figure 8 25 Clock Resources View PlanAhead User Guide www xilinx com 277 UG632 v13 4 January 18 2012 Chapter 8 VO Pin Planning XILINX Placing Clock Logic in the Device View To place clock logic manually 1 Inthe Device view zoom to locate the appropriate device site to place the logic 2 Select Create Site Constraint Mode 3 Select the logic instance to place from the Find Results Schematic Netlist or I O Ports views and drag it onto the appropriate device resource in the Device view Figure 8 26 shows an example of manual clock placement i E B Ee i E E B 6 i E Ee B e Ss i i B B E E e B E B i 6 Device lt x E Project Summary x M Package x Figure 8 26 Manually Placing Clock Logic Validating I O and Clock Logic Placement This section describes the
227. You can disable source files to prevent them from being elaborated synthesized or used in simulation You can load different versions of a source file then enable or disable the appropriate source file in the Sources view to control the current configuration of the design e To disable source files select the files in the Sources view then select the Disable File popup command e To enable disabled files select the files in the Sources view then select the Enable File popup command www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Managing RTL Source Files Using Remote Sources or Copying Sources into Project To provide project management flexibility you can reference source files from a remote location or copy the source files into the project directory Copy the files into the project if you plan to move or archive the project because the files are contained within the project When you add remote files the PlanAhead tool automatically detects the latest file version then prompts you to Refresh your open Designs or to Synthesize with the latest updates made to the file Note When you copy files into a project the project is easier to port to another system however the PlanAhead tool does not automatically recognize external file changes When remote files change you must remove and re add or update the files using commands in the Sources view When you add sources to the project using
228. _1 active Simulation Options fe Strategy fast_area_reduction XST 13 Description Based on Area Reduction auto _bi king f Implementation auto_bram_packing yes use_dsp48 auto t resource_sharing yes iob true IP Catalog netlist _hierarchy rebuilt r ram_style rebuilt o bufg equivalent_register_removal yes v v mux _extract yes More Options netlist_hierarchy Netlist Hierarchy Specifies the format of the final netlist generated by synthesis Use rebuilt to generate a hierarchical netlist after the narmal synthesis optimizations have occurred Use as_optimized to generate an optimized Flat netlist Hierarchical OK Cancel Apply Figure 6 1 Synthesis Project Settings The Synthesis Settings dialog box lets you set XST options to use during synthesis The options are e Default Constraint Set Select the active constraint set The synthesis application uses an XCF constraint set format e Strategy Select an existing strategy to use for the synthesis run For more information on strategies see Defining Strategies for Synthesis and Implementation in Chapter 4 e Description Displays the strategy description This field is editable for user defined strategies only e XST options Configure any XST command line option You can find a brief description of each option and its use in the lower dialog box pane An asterisk next to an option name
229. _TDP_MACRO Preview 1 2 FIFO DUALCLOCK_MACRO In order to incorporate this function into the design VHDL the following instance declaration needs to be placed instance in the architecture body of the design code The declaration FIFO_DUALCLOCK_MACRO_inst and or the port declarations code after the gt assignment maybe changed to properiy reference and connect this function to the design All inputs and outputs must be connected Library In addition to adding the instance declaration a use declaration statement for the UNITSIM vcomponents library needs to be for added before the entity declaration This library Xilinx contains the component declarations for aii Xilinx primitives primitives and points to the models that will be used for simulation Sources 4 DI Netlist La Timing Constraints UCF G Properties Figure 4 68 Xilinx Language Templates To instantiate a language or constraint template 1 Use the Language Templates command to open the Template view to browse the available language templates Xilinx language templates are provided for Ka Verilog VHDL and Constraints files 2 Browse and select a template from the VHDL Verilog or UCF hierarchy in the Template view Figure 4 68 shows an example of a Xilinx supplied templates PlanAhead User Guide www xilinx com 159 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX
230. _i 14 207 25 define USBF_MEM_SEL wb_addr_i 14 B A C Plan4head_Projects Plan4head_Tutorial_13 3 Projects project_cpu_hdl project_cpu_hdl srcs sources_1 imports hdl wb_conmax wb_conmax_rf v 2 99 31 i_wb_data_i i_wb_data_o i_wb_addr_i i_wb_sel_i i_wb_we_i i_wb_cyc_i 18 input aw 1 0 i_wb_addr_i 207 46 assign rF_sel i_wb_cyc_i amp i_wb_stb_i amp i_wb_addr_ifaw 5 aw 8 rF_addr 16 iFerF_we amp i_wb_addr_i 5 2 4 d0 jconfO lt 1 i_wb_data_i 15 0 9 16 if rF_we amp i_wb_addr_i 5 2 4 d1 jconfi lt 1 i_wb_data_i 15 0 16 iF rF_we amp i_wb_addr_i 5 2 4 d2 jconf2 lt 1 i_wb_data_i 15 0 PUI PAN TA eee Ft wee ET CLP a ee oe oe Se ee Parni Mi Replace All Replace Selected 66 occurrences of wb_addr_i in 7 of 91 project files x Figure 4 38 Replace in Files Results Using Common Views The following subsections describe the common views Using the Sources View When design sources constraint files simulation sources and IP cores are added to a project they appear in the Sources view of the project You can use the Sources view to manage project source files adding removing and reordering the sources to meet specific design requirements The Design Sources folder contains source file types which include Verilog VHDL NGC NGO EDIF and IP cores Constraint files are assigned to constraint sets and are displayed under the Constraints folder
231. _timing ucf 44 45 INST_TAG END End INSTANTIATION Template 46 47 You must compile the wrapper file char_fifo v when simulating 4A 77 the rnre char fifo When ecomniline the wranner file he sure tin E Project Summary X 4 char_fifo veo Read Only x Figure 3 28 instantiated IP RTL Code 1 Open both the VEO or VHO template file for the IP core and the RTL design file in the Text Editor by double clicking on each source file in the Sources view or by selecting the files and using Open Files 2 Select the Instantiation Template in the VEO or VHO template file and copy it to the open RTL design at the appropriate location 3 Edit the RTL to integrate the IP template into your design as needed With the IP core properly instantiated into your design you are ready to synthesize the IP core along with the rest of your design 68 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Managing IP Cores You can synthesize IP cores in a project along with the overall design by running the Synthesize You can also synthesize a specific IP core at any time by selecting the IP in the Sources view and running Generate IP from the popup menu When you generate IP the Xilinx Synthesis Tool XST runs on the core and creates the logic content based on the customization settings After the IP is generated a check mark appears on the IP source icon in the Sources view and the PlanAhead tool adds the synt
232. _top wbArbEngine wb _conmax_top E Physical Constr Timing Constraints Figure 7 3 Netlist View with Top Module Selected The Netlist or Instance properties open in the Properties view If the Netlist or Instance Properties do not display right click on the module and select Netlist Properties or Instance Properties from the popup menu The Netlist Properties view contains five tabs The Instance Properties dialog box contains seven tabs In the Netlist or Instance Properties view click the Statistics tab The Statistics tab displays valuable design information including Primitive Instance Counts Interface Signal Counts Clock Names and Clocked Instance Count Carry Chain Count and Max Length Figure 7 4 page 211 shows an example of the Netlist Resource Statistics www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Viewing and Reporting Resource Statistics Primitive Statistics Primitive type Count LUT 22511 FD_LD 14973 MUXFX 782 CARRY 8116 BMEM 135 68 18 141 178 336 Net Boundary Statistics Boundary crossing Nets 146 Clock Report Domain Module Resource Instances DIV2_OUT MGT_USRCLK_SOURCE Global 82 DI 2_OUT MGT_USRCLK_SOURCE_NO1_txoutclk_dem1_i Global 226 DIV2_OUT MGT_USRCLK_SOURCE_NO2_txoutclk_dcm2_i Global 90 DIV2_OUT MGT_USRCLK_SOURCE_txoutclk_dem0_i Global 82 cpuClk_BUFGP top Global 3411 FFtClk_BUFGP top Global
233. ading clock buffers from C PlanAhead_Install planAhead parts xilinx virtex6 virtex6lxt xc6vlx75t ClockBuffers xml INFO ArchReader 9 Loading clock placement rules from C PlanAhead_Install planAhead parts xilinx virtex6 ClockPlacerRules xml a INF ArchReader 10 Loading clock capable ios from C PlanAhead_Install planAhead parts xilinx virtex6 ClockCapableIOBs xml INF ArchReader 13 Loading package pin functions from C PlanAhead_Install planAhead parts xilinx virtex6 PinFunctions xml INFO ArchReader 3 Loading package from C PlanAhead_Install planAhead parts xilinx virtex6 virtex6lxt xc6vlx75t f 784 Package xml X Imro archReader 4 Loading io standards from C PlanAhead_Install planAhead parts xilinx virtex6 1ostandards xml INFO GDRC 0 Loading list of dres for the architecture PlanAhead_Install planAhead parts xilinx virtex6 dre xml Parsing UCF File C PlanAhead_Install planAhead testcases PlanAhead_Tutorial Projects project_cpu_hdl project_cpu_hdl sres constrs_1 imports Sources top ucf Finished Parsing UCF File C PlanAhead_Install planAhead testcases PlanAhead_Tutorial Projects project_cpu_hdl project_cpu_hdl sres constrs_1 imports Sources top ucf lt E Tel Console Messages GI Compilation Design Runs Figure 5 2 RTL Design Analysis view The PlanAhead tool provides device resource estimations based on the compiled RTL design To populate the Resource Estimation view select e Tools gt Res
234. aint Sets with multiple constraint files this command lets you specify the constraint file that the PlanAhead tool targets to write newly created constraints See Managing Constraints in Chapter 3 Set Library Lets you specify a library for the selected RTL source file s You can choose from a list of libraries that are currently defined in the project or type a new library in the text entry field Entering a new library adds it to the list of currently defined libraries Note The Library attribute can also be set from within the Source File Properties view see Viewing Source File Properties page 127 Set Type Define the type of the currently selected file or files The PlanAhead tool will automatically recognize the type of a file as it is added to the project based on appropriate file extensions However you can use the Set Type command to redefine the file type in cases of non standard file extensions Note The Type attribute can also be set from within the Source File Properties view see Viewing Source File Properties page 127 G Set Type i Set the type of the selected sources Choose Type VHDL Figure 4 40 Set Type Set Used In Specify what tools the file is used for You can specify a source file to be used or not used during synthesis simulation or implementation Disabling a source file for a particular tool will prevent that file from being used by that tool For example if you set a sou
235. aint entry and eliminates the need for changes to the BMM file Any changes to the component instantiation name or hierarchy must be reflected in the BMM and UCF files as well system_i system port map RESET gt RESET CLK_P gt CLK_P CLK_N gt CLK_N DIP _ Switches _4Bits_TRI_I gt DIP_Switches_4Bits_TRI I Ethernet_Lite_MDIO gt Ethernet_Lite_MDIO Ethernet_Lite MDC gt Ethernet_Lite_ MDC Ethernet_Lite_TX_ER gt Ethernet_Lite_TX_ER Ethernet_Lite_TXD gt Ethernet_Lite_TXD Ethernet_Lite_TX_EN gt Ethernet_Lite_TX_EN Ethernet_Lite_TX_CLK gt Ethernet_Lite_TX_CLK Ethernet_Lite_COL gt Ethernet_Lite_COL Ethernet_Lite RXD gt Ethernet_Lite _RXD Ethernet_Lite_RX_ER gt Ethernet_Lite_RX_ER Ethernet_Lite_RX_CLK gt Ethernet_Lite_RX_CLK Ethernet_Lite_CRS gt Ethernet_Lite_CRS Ethernet_Lite_RX_DV gt Ethernet_Lite_RX_DV Ethernet_Lite_PHY_RST_N gt Ethernet_Lite_PHY_RST_N LEDs 4Bits TRI_O gt LEDs 4Bits TRI_O Push Buttons_4Bits_TRI_I gt Push_Buttons_4Bits_TRI_I RS232_Uart_l_sout gt RS232_Uart_1_sout RS232_Uart_1_sin gt RS232 Uart_1_sin SPI_FLASH_SCLK gt SPI_FLASH_SCLK SPI_FLASH_MOSI gt SPI_FLASH_MOSI SPI_FLASH_MISO gt SPI_FLASH_MISO SPI_FLASH_SS gt SPI_FLASH_SS PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com XILINX Importing XPS Embedded Processor Desig
236. aints Guide UG625 http www xilinx com support documentation sw_manuals xilinx13_4 cgd pdf Data2MEM User Guide UG658 http www xilinx com support documentation sw_manuals xilinx13_4 data2mem pdf ISim User Guide UG660 http www xilinx com support documentation sw_manuals xilinx13_4 plugin_ism pdf Power Methodology Guide UG786 http www xilinx com support documentation sw_manuals xilinx13_4 ug786_PowerMethodology pdf Synthesis and Simulation Design Guide UG626 http www xilinx com support documentation sw_manuals xilinx13_4 sim pdf Timing Closure User Guide UG612 http www xilinx com support documentation sw_manuals xilinx13_4 ug612 pdf Xilinx Cadence PCB Guide UG629 http www xilinx com support documentation sw_manuals xilinx13_4 cadence_pcb pdf Xilinx Mentor Graphics PCB Guide UG630 http www xilinx com support documentation sw_manuals xilinx13_4 mentor_pcb pdf XPower Estimator User Guide UG440 http www xilinx com support documentation sw_manuals xilinx13_4 ug440 pdf www xilinx com 437 Appendix E Additional Resources XILINX e XST User Guide for Virtex 4 Virtex 5 Spartan 3 and Newer CPLD Devices UG627 http www xilinx com support documentation sw_manuals xilinx13_4 xst pdf e XST User Guide for Virtex 6 Spartan 6 and 7 Series Devices UG687 http www xilinx com support documentation sw_manuals xilinx13_4 xst_v6s6 pdf ISE Tutori
237. als e ISE In Depth Tutorial UG695 http www xilinx com support documentation sw_manuals xilinx13_4 ise_tutorial_ug695 pdf e ISE RTL Technology Viewer Tutorial UG685 http www xilinx com support documentation sw_manuals xilinx13_4 ug685 pdf e Sim In Depth Tutorial UG682 http www xilinx com support documentation sw_manuals xilinx13_4 ug682 pdf e Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications UG750 http www xilinx com support documentation sw_manuals xilinx13_4 ug750 pdf e Xilinx Power Tools Tutorial UG733 http www xilinx com support documentation sw_manuals xilinx13_4 ug733 pdf Partial Reconfiguration Documentation Partial Reconfiguration website www xilinx com tools partial reconfiguration htm Partial Reconfiguration User Guide UG702 http www xilinx com support documentation sw_manuals xilinx13_4 ug702 pdf Tutorials Design Preservation Tutorial UG747 http www xilinx com support documentation sw_manuals xilinx13_4 PlanAhead_Tutorial_Design_Preservation pdf e Partial Reconfiguration Tutorial UG743 http www xilinx com support documentation sw_manuals xilinx13_4 PlanAhead_Tutorial_Partial_Reconfiguration pdf e Partial Reconfiguration of a Processor Peripheral Tutorial UG744 http www xilinx com support documentation sw_manuals xilinx13_4 PlanAhead_Tutorial_Reconfigurable_Processor pdf White Papers e Repeatable Resul
238. also categorized by severity A violation can be informational only to make you aware of a possible issue can be a warning to suggest an issue that might need some resolution can be an error to highlight issues that prevent proper implementation of your design The DRC Results view also color codes violations for quick review of errors warnings and informational messages 194 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Running RTL DRCs e Errors have a red marker e Warnings have an orange marker e Informational messages have a yellow marker You can toggle the Hide warnings and informational messages button in the Q toolbar menu to turn off warnings and informational messages and see only the errors reported You can also click the header of the Severity column of the DRC Results view to sort violations by severity e Click once on the column header to sort in an increasing order e Click twice to sort in a decreasing order See Using Tree Table Style Views in Chapter 4 for more information Gi project_1 C PA_Project ChipScope_Project bft_core project_1 project_1 ppr PlanAhead 13 4 File Edit Flow Tools Window Layout View Help SAB NAX HD DAAK E G Boesmans KRSM SHY Project Manager Netlist Design netlist_1 x RTL Design Netlist Ag gt Hit H Nets 1957 Synthesize Ss Netlist Design El Resource Estimation 0 Run DRC Tim
239. ame ise_imp4 Archive location C Datalpractice_designs Archive file will be created at C Data practice_designs ise_imp4 pa zip Include Run Results Figure 3 13 Archive Project To archive a project 1 Select File gt Archive Project 2 Specify a file name for the archive 3 Specify a directory location to write the archive file 4 Enable or disable Include Run Results to include the settings and results of the runs performed on the project then click OK to create the archive www xilinx com 49 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects XILINX The PlanAhead tool creates a ZIP file archive of the project containing the required source and include files and the run files if specified and creates an archive 1log file of the archival process that is included in the archive ZIP file You can review the creation of the archive in the archive log file Closing a Project To close projects select File gt Close Project When you close a project you are prompted to save any unsaved changes to the design or source files Managing Project Sources 50 The PlanAhead tool can create new source files and manage existing source files that are either local to the current project or remotely referenced from a library You can add Verilog and VHDL source files to an existing project at any time in the design flow You can also create and add constraint files add a simulation test benc
240. amount of logic object detail displayed is determined by the selected zoom level the more you increase the zoom level the more logic object detail displays The Device view popup and toolbar menus contain self explanatory zoom level commands The Device view has scroll bars and dynamic pan capabilities to pan the viewable area of the device also When you drag the cursor over an object in the Device view a tool tip identifies the object The Properties view displays object properties for selected sites or logic objects Use Edit gt Find to search for specific device resource sites The Device view uses a dynamic cursor that changes appearance based on the activity being performed www xilinx com 129 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX For example if you attempt a logic resource assignment that is illegal the dynamic cursor changes so you can make adjustments For more information see Understanding the Context Sensitive Cursor page 109 Using Device View Commands Toolbar buttons on the left side of the Device view are view specific commands which are described in Using View Specific Toolbar Commands page 108 The following commands are available in the Device view toolbar e To create e Anew Pblock rectangle use Draw Pblock e Non rectangular Pblocks use Add Pblock Rectangle to create a non rectangular space using multiple rectangles e To add or change the shape of a
241. an specify time in units of fs ps ns us ms and sec The default unit is ps You can also specify all as a keyword to indicate that ISim should run until there are no more events to simulate incremental Switch to indicate that fuse linker and compiler should compile only the files that have changed from the last compilation nodebug Switch to indicate that fuse should create a simulation executable exe that has no information for debugging your HDL code during simulation resulting in faster simulation run times tclbatch Specify filename of Tcl commands listed in a batch file for execution by the simulator at run time Commands in the specified batch file are executed sequentially until completion ISim ignores any commands entered from the command prompt until batch file execution has completed PlanAhead uses a tclbatch command to pass three required commands to Sim ina file called isim cmd The contents of this file are onerror resume wave add run lt value gt If you create a Tcl command to control the execution of the simulator at launch time you must include these three commands in your tclbatch file It is recommended that onerror be the first command listed and that wave add and run be the last commands listed You can add any other ISim command line commands between onerror and wave add Note The tclbatch command file must have a file extension of either TCL or CMD to be properly handled by ISim
242. anAhead tool contains views that display as expandable spreadsheet tables These views all share some common characteristics and features described in the following subsections and illustrated in Figure 4 18 Name Dir Neg Diff Pair Location Bank J OStd Drive Strength SlewType Pull Type B E All ports 146 H B RXP_IN 8 Input RXN_IN LvDS_25 Dataln_pad_0_i 8 Input LYCMOS25 12 SLOW LineState_pad_0_i 2 Input LYCMOS25 12 SLOW HD Status_pad_0 Input L CMOS25 12 SLOW HD Dataln_pad_1_i Input L CMOS25 12 SLOW ID LineState_pad_1_i 2 Input LYCMOS25 12 SLOW D LineState_pad_1_i 1 Input LYCMOS25 12 SLOW D LineState_pad_1_i 0 Input LY CMOS25 12 SLOW D J Package Pins Figure 4 18 Tree Table Style View Expanding and Collapsing the Table Toggle the expand and collapse widgets in the Name column to expand or collapse mA the tree independently r g The Expand all and Collapse all buttons expand or collapse the entire tree Display Entries in a Flat List or in a Group Most of these style views have a Group by Type button or equivalent which either display the entries grouped by an expandable type or as a single flat list of entries Flattening the list is helpful to search and filter the overall list of entries as shown in Figure 4 19 Name D 1 RXP_IN 7 ei 2 RXP_IN 6 iD 3 RXP_IN S D 4 RXP_IN 4 D 5 RXP_IN 3 8 RXP_IN O N NakstTa mad N fF J Package Pins Figure 4 19 Gro
243. analysis of the activity of each resource in the design The Power Estimation view is similar to the summary sheet provided by XPower Estimator so you can compare results The power by resource and by hierarchy is added to the properties to provide a complete view of the power distribution for the design This enables further analysis and supports decisions on how to best achieve your power requirements Note The RTL power estimation features are only available for the Virtex 5 Virtex 6 and Spartan 6 device families To run the Power Estimation 1 Ensure all clock domains are constrained You can enter timing constraints e Manually see Defining Timing Constraints page 216 e Using the create_clock command in the Tcl Console or e Importing a UCF see Configuring Project Settings page 83 2 Specify the FPGA environment settings using the set_operating_conditions command in the Tcl console window FPGA environment conditions have a significant influence on the device total power consumption Use the set_operating conditions command to match process voltages cooling or any other environment settings to the actual operating environment of your system For more information about Tool Command Language Tcl commands see the PlanAhead Tcl Command Reference Guide UG789 cited in Appendix E Additional Resources 182 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Estimating Power
244. ancel Click Cancel to close the form without saving G Design Run Settings Strategy amp ISE Defaults ISE 13 Description ISE Defaults including packing registers in IOs off Translate ngdbuild More Options Map map pr lt none gt smartquide ir off Select an option above to see description of it Cancel Figure 9 4 Design Run Settings for an Implementation Run Configuring Implementation Launch Options G Specify Launch Options Launch Directory E lt Default Launch Directory gt Options Launch Runs on Local Host Number of Jobs 2 v Generate scripts only i Cancel Figure 9 5 Implementation Launch Options The Specify Launch Options dialog box options are e Launch Directory Specify a location to create and store the implementation run data Note Defining any non default location outside of the project directory structure makes the project non portable because absolute paths are written into the project files e Launch Runs on Local Host Launch the run on the local machine processor e Number of Jobs Define the number of local processors to use for runs This option is used only when you are launching multiple runs simultaneously Individual runs are launched on each processor No multi threaded processors are used with this option 294 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Monitoring the Implementation Run e Lau
245. and Power Estimation Assign I Os using RTL Ports a ee Load Synthesized Netlist Design Netitat Design e Analyze Logic Hierarchy and Connectivity View Resource Estimates gt Define Constraints I O Timing Implement Placement Configure and Run Timing Analysis Implemented Design DRC and SSN Analysis i a Load Implemented Design Program and Debug e Analyze Timing and Placement Results e View Connectivity e Launch Sim Timing Simulation Refine Constraints Timing Placement PlanAhead Software Flow Navigator RTL Project www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Understanding the Flow Navigator Using the Flow Navigator with a Synthesized Netlist Project Figure 2 3 illustrates the design flow for synthesized netlist based projects Configure Project Sources Project Manager e Create and Manage Source Files Project Settings e Create and Manage Constraint Sets B7 Add Sources e Manage Project Settings Project Si 2 ar Load Synthesized Netlist Design Run ISE Implementation Metitet Dewar Analyze Logic Hierarchy and Connectivity View Resource Estimates e Configure and Launch Runs gt Define Constraints I O Timing Placement e Assign Run Strategies Implement Configure and Run Timing Analysis e Analyze Results DRC and SSN Analysis Insert ChipScope Debug Cores 3 Implemented Design Launch Programming and Debug ap Load Implemented Design e Ru
246. and assigns Prohibit constraints to pins that are not common to all devices The number of pins available for placement might be reduced as you select additional alternate parts The PlanAhead tool automatically prohibits signals from being assigned to any unbonded pins in the selected alternate devices A dialog box displays the number of prohibited package pins You can view prohibits in the Package Package Pins and Device views Note If you are defining an alternate compatible part for a Spartan 6 LX25 or LX25T device pins that are bonded are prohibited because of differences in the clocking topology between this device and alternate compatible parts in the same package Refer to AR 34885 for more information Setting Device Configuration Modes The PlanAhead tool provides information about device configuration modes and you can set any number of them as shown in Figure 8 8 page 259 258 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Setting Device Configuration Modes G Set Configuration Modes SPI JTAG Boundary Scan Master Serial The JTAG configuration mode allows the device to be configured through the JTAG port This is often used with board testers for debug and for indirectly programming SPI flash or parallel NOR flash connected to the FPGA configuration port The Xilinx download cables and the ChipScope Pro tool use the JTAG configuration mode Supporting this mode f
247. and automatically by the tool User assigned placement is either defined within an imported constraint file or assigned by interactive placement within the PlanAhead tool e User assigned placement constraints are considered fixed and display in one color www xilinx com 329 UG632 v13 4 January 18 2012 330 Chapter 10 Floorplanning the Design XILINX e Placement constraints defined by PlanAhead or ISE during implementation are considered unfixed and display in a different color To fix placement constraints for unfixed instances use the Fix Instances or Fix Ports command in the Device Package or Schematic view The PlanAhead tool exports fixed constraints by default to the ISE implementation tools to lock the placement The File gt Export gt Export Constraints and File gt Export gt Export Pblocks dialog boxes have a switch that enables exporting both fixed and unfixed placement constraints Figure 10 21 shows an example of how Export Pblock and Export IP can be used to export different parts of the design based on either logical Export IP or physical Export Pblock hierarchy A edn A ucf AD edn Export Pblock AD ucf Figure 10 21 Example of Export Pblock and Export IP Understanding Site and BEL Level Constraints Site constraints result in a LOC constraint being assigned to the instance The logic element is assigned to the CLB SLICE only and not to any specific site or resource The following
248. and in the Current Commands list e Menu Name Defines the name of the command bi se as G Add Shortcut as it is displayed on the Custom Command menu z Press new shortcut e Shortcut Defines a keyboard shortcut to use to Se ctrl G run the Tcl command Click Add to open the Add Shortcut dialog Then you can enter a keystroke Shortcuts currently used by combination to run the selected command The Goto Line Ctr G dialog box reports any commands that already use the specified shortcut e Run Command This radio button causes the specified Tcl command or procedure to be run from the custom menu 172 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Configuring PlanAhead e Source Tcl File This radio button causes the specified Tcl script file to be sourced rather than a single Tcl command or procedure to be run from the custom menu e Toolbar Options Specifies whether an icon for the command should be added to the main toolbar menu Add to the toolbar Checkbox to enable the toolbar icon When this checkbox is disabled the command will not appear on the main toolbar menu Tooltip Specifies the text to display as a tooltip when the mouse hovers over the command icon Icon file path Specify the file path to the toolbar icon Note An icon file should be a PNG JPG or GIF file of approximately 20x20 pixels The PlanAhead tool will resize larger ima
249. angle ranges to be defined for implementation Figure 10 16 shows an example of an individually selected Pblock Pblock Properties Og x a pblock_fftEngine Id x Lo Y Lo Hi Y Hi 1 109 1 171 125 O ME E E E EE eneral Statistics Instances Rectangles 4 gt E Figure 10 16 Selecting the Pblock Rectangles Individually Note The tools are not optimized to handle too many ranges per the AREA_GROUP constraint It is best to use simple shape configurations such as L or T shapes Removing a Pblock Rectangle To remove the Pblock rectangle select the Pblock and click Clear Rectangle You can clear e Individual Pblock rectangles one at a time e Multiple rectangles and Pblocks simultaneously Clearing Pblock rectangles does not delete the Pblock from the physical constraints PlanAhead User Guide www xilinx com 325 UG632 v13 4 January 18 2012 Chapter 10 Floorplanning the Design XILINX Setting Attributes for Pblocks You can assign attributes to Pblocks in the Attributes tab of the Pblock Properties view as shown in Figure 10 17 Pblock attributes define options for ISE which can affect the implementation results and cause failures o Bir ETE J pblock_usbEngine1_1 ss abd aridtypes SLICE DSP48 RAMB16 R name pblock_usbEngine1_1 class Attribute Type String Read only Yes istics Instances Rectangles Attributes 4 p E Figure 10 17 Pblock P
250. apter 6 or Launching an Implementation Run in Chapter 9 for more information Launch FPGA Editor Launch XPower Analyzer Export to Spreadsheet e Save as Strategy Lets you save any modifications made to the applied strategy to a new strategy file for future use 156 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Using the Text Editor e Launch Runs Invokes the Launch Selected Runs dialog box to launch the selected runs e Reset Runs Invokes the Reset Runs dialog box to remove previous run results and to set the run status back to Not Started for the selected runs e Open Implemented Design Loads the resulting netlist from the Synthesis run or Implementation results from ISE in to the analysis environment The active loaded run appears in bold text in the Design Runs view e Generate Bitstream Invokes the Generate Bitstream dialog box to create a bitstream This command is available for completed Implementation runs only e Copy Run Creates a new run using the same Strategy as the selected run e Create New Runs Invokes the Create New Runs wizard to create and configure new Synthesis or Implementation runs e Open Run Directory Opens a file browser in the selected run directory on disk e Launch ChipScope Analyzer Invokes ChipScope analyzer with the current BIT file e Launch iMPACT Invokes iMPACT with the current BIT file e Launch FPGA E
251. artition from the Physical Constraints view Creating Pblocks Automatically PlanAhead User Guide To use automatic Pblock creation select Tools gt Floorplanning gt Auto create Pblocks Use this command to create top level Pblocks to view the data flow of the design and to understand the relative size and relationship between the various logic modules in the design Figure 10 19 shows the Auto create Pblocks dialog box G Auto create Pblocks Pblock to partition ROOT Maximum number of Pblocks to generate Process instances with primitive count of at least Preview 6 Pblocks are going to be generated For the Following instances wbArbEngine usbEngineO usbEngine1 cpuEngine FFtEngine matEngine Figure 10 19 Auto Create Pblocks Specify the following options Pblock to partition Enter the name of an existing Pblock to partition or specify ROOT to partition the top level of the design Maximum number of Pblocks to generate Specify the number of Pblocks to generate based on the hierarchy of the design or selected Pblock Use this to increase or decrease the number of Pblocks created www xilinx com 327 UG632 v13 4 January 18 2012 328 Chapter 10 Floorplanning the Design XILINX e Process instances with primitive count of at least Limits the examination of instances within the design hierarchy to modules with more than the specified number of primitives Use this to reduce
252. ated RTL and synthesized netlists and Compilation pane with summary information from synthesis and implementation reports You can select any netlist instance or Pblock and examine the resource statistics in the Instance or Pblock Properties view including selecting the top level design The information includes logic object type counts percentage of device resources utilized carry chain information and clock reports You can export the information into an Excel spreadsheet Generating Hierarchical Resource Estimates You can display resource estimates graphically as an expandable hierarchical tree As each Resources type displays you can expand it to view each level of logic hierarchy To display a graphical view of device resource estimates 1 Open a Netlist Design 2 Click either e Flow Navigator gt Resource Estimation e Tools gt Resource Estimation A Hierarchical Resource Utilization summary opens as shown in Figure 7 2 Resource Utilization Estimated resources are compared with xc6vix7Stff484 2 Register Available 93120 Estimation 01373 available bft LUT Available SSS 46560 Estimation 2056 Ec rransformLoop O ct E transformLoopf1 ct e E transformLoop 2 ct e E transformLoop 3 ct E transformLoop 4 ct E transformLoop 5 ct E transformLoop 6 ct E transformLoop 7 ct ElegressLoop 0 egressFifo Fifo8 legressLoop 1 egressFifo FifoB H egressLoop
253. ation PlanAhead User Guide www xilinx com 359 UG632 v13 4 January 18 2012 Chapter 11 Analyzing Implementation Results g XILINX For more information see Opening the Implemented Design page 341 and Building an Implemented Design with Imported Placement page 344 Removing the Metric Map Display To hide a metric map in the Device view select the metric and from the popup menu select Hide or Hide All Metrics Using the Metric Results View After you select Show the metric results display in the bottom view In the Metric Results view you can e Sort the information by clicking any of the column headers e Sort by a second column by pressing Ctrl and clicking a second column header e Add as many sort criteria as necessary to refine the list order The Pblock metric results update automatically as you modify the Pblocks The different types of metrics such as for Pblocks CLBs and primitives display in different charts Each type has a tab along the bottom of the Metric Results view as shown in Figure 11 18 Id Name Type Sites Instances LUTUtI Vert route cong Hori route cong 13 CLBLM_X18 102 CLBLM 100 00 14 CLBLM_X26 57 CLBLM 100 00 15 CLBLM_X37 63 CLBLM 100 00 42 16 C 30 88 J 61 01 L 81 30 16 CLBLM_X28Y57 CLBLM 100 00 17 CLBLL_X38 63 CLBLL 100 00 18 CLBLL_X27 4 CLBLL 100 00 19 CIBU 9YS7 CIBULI 100 on E CLBs 5820 x Pblocks 2
254. ation in the Source File Properties view To view source file properties In the Sources view select a source file and select the Source File Properties view Figure 4 42 page 128 shows the Source File Properties view for a selected Verilog file www xilinx com 127 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment g XILINX E e async_fifo v Location C Plan4head_InstalliplanShead testcases Plan4head_Tutorial Projects project_bft_core_hd Type Verilog v Library work Size 17 3 Kb Modified 1 18 11 1 25 58 PM Copied To project_bft_core_hdl srcs sources_1 imports hdl Copied From C Plan4head_Install plandheaditestcases Plan4head_Tutorial Sources hdl async_Fifo v Copied On 1 18 11 1 25 57 PM Global Include Enabled Read onl Apply Cancel Figure 4 42 Viewing Source File Properties The file information includes location type library size modified timestamp date location copied from copy date and parent module e You can change the file type using the Type option This is useful in cases where files could have non standard extensions and the file type is not properly detected e Select a new target library for a source file by clicking the pulldown Library menu to select from the list of defined libraries or simply type a new name in the Library name field e Use the Global Include checkbox to enable or disable Verilog source files as
255. ations Properties view This view provides a general review of the DRC rule violation and specific details of the design elements that violate the rule The Details tab of the Violations Properties might have links to specific design objects that violate the DRC Click these links to view the design object in the RTL Netlist view the Device view the Schematic view or the source RTL file 280 PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com XILINX Exporting I O Pin and Package Data Exporting I O Pin and Package Data You can export I O pin and pin package information as described in the following subsections Exporting Package Pin Information You can export the device package pin information to a CSV format file The exported information includes information about all of the package pins in the device as well as design specific I O Port assignments and their configuration The package pin section of the exported list is a good starting point for defining I O port definitions in a spreadsheet format Refer to Defining and Configuring I O Ports page 260 for information on the exported CSV file format Exporting an I O Port List 1 You can export the I O port list to an HDL UCF or CSV format file for use with RTL coding or PCB schematic symbol creation 1 To export the I O Ports list information select File gt Export gt Export I O Ports as shown in Figure 8 29 G Export 1 0 Ports Speci
256. aunch the Implementation run you can open the results by clicking Implemented Design from the Flow Navigator The Implemented Design command is available only when a successfully Implemented design exists in a project see Figure 11 1 page 342 PlanAhead User Guide www xilinx com 341 UG632 v13 4 January 18 2012 Chapter 11 Analyzing Implementation Results Figure 11 1 XILINX a Implement Implemented Design w E Resource Estimation Run DRC Run TRCE g Report Clock Networks FPGA Editor igs XPower Analyzer iq Timing Simulation a v Program and Debug Flow Navigator Implemented Design The Implemented Design menu shows available analysis tools in the Flow Navigator menu when an Implemented Design is opened Figure 11 2 page 343 shows the default view layout for an Implemented Design 342 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Opening the Implemented Design G project_cpu_hdl C PlanAhead_Install planAhead testcases PlanAhead_Tutorial Projects project_cpu_hdl project_cpu_hdl ppr PlanAhead 13 3 0R0 File Edit Flow Tools Window Layout View Help See mMaxg od ByARGOSKEZ Project Manager Implemented Design impl_1 Netlist alg gt top Nets 1016 Synthesize Ee Primitives E epuEngine or120 c E fftEngine f ia mgtEngine rat Te Fs a RTL Design Netlist Design gt Implement Implemented De
257. b The report has a similar format to the TRACE report e By default selecting a path also selects all instances contained within the path e Selecting any of the objects in the report cross selects the object in other open views such as the Netlist and Device views e Select multiple paths using the Shift and Ctrl keys e All instances contained in the selected paths are selected but the Path Properties displays information only about the first path selected Displaying Timing Path Reports in the Workspace An individual Timing Path Report can also be displayed in the workspace for easier viewing Also multiple path reports can be opened in separate views in the workspace To view the report 1 Select the timing path 2 Select the View Path Report popup menu command 230 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using Slack Histograms Using Slack Histograms PlanAhead User Guide The Slack Histogram provides a visual indication of the timing delays in the design This view can assist the designer in determining the next course of action if the design is not meeting performance requirements Slack Histogram shows the timing slack calculated at the endpoint It does not show the complete timing path The Schematic command shows the endpoint of the path You must use the Report Timing command to see the timing of a complete path 1 Select one of the following methods t
258. bEngine1 8 41 0 54 7 866 6 4 93 6 0 wbClk phy_clk_pad P Path2 Slow SETUP 0 23 reset_rea Q usbEnginel 8 48 0 57 7 913 6 7 93 3 0 wbclk phy_clk_pad P Paths Slow SETUP 0 23 reset_reg Q usbEngine1 8 48 0 57 7 913 6 7 93 3 0 wbCik phy_clk_pad P Path Slow SETUP 0 23 reset_reg Q usbEngine1 8 42 0 57 7 848 67 93 3 0 wbclk phy_ck pad P Paths Slow SETUP 0 23 reset_reg Q usbEngine1 8 48 0 57 7 911 6 7 93 3 0 wbclk phy_clk_pad P Pathe Slow SETUP 0 24 reset_rea Q usbEngine1 8 4 0 57 7 829 6 8 33 2 0 wbclk phy_clk_pad Path Slow SETUD 024 racat reciO uchEmainett fat naz 72 937 EA Oa a NAmhllk uehfik Report Timing results_1 10 paths x E Td Console Messages E Compilation Design Runs RTL Flow Figure 2 6 Open Implemented Design The Implemented Design imports the netlist constraints placement and timing results from the implementation run directory The PlanAhead tool loads the design into memory where you can analyze it in the Design Analysis view layout AEEA To open an Implemented Design select one of the following e The Implemented Design button in the Flow Navigator to open the active synthesized netlist constraint set and the target device for a project e Open Implemented Design from the Implemented Design pulldown menu in the Flow Navigator then select any listed implementation run e Select any completed implementation run in the Design Runs view and use the Open I
259. box is opened select the Implementation icon as shown in Figure 9 1 G Project Settings Implementation Constraints Default Constraint Set E constrs_1 active Options D Strategy ISE Defaults ISE 13 Synthesis Description ISE Defaults including packing registers in IOs off Translate ngdbuild Map map ae Place amp Route par Static Timing Report trce IP Catalog This option causes the timing report to be a verbose report instead of a default summary report The value supplied for this switch is an integer limit on the number of items reported for each timing constraint in the report file The value of limit must be OK Cancel Apply Figure 9 1 Implementation Project Settings The Implementation Project Settings dialog box contains the following options Default Constraint Set Select the constraint set to use for the Synthesis run Strategy Select an existing strategy to use for the implementation run For more information on strategies see Defining Strategies for Synthesis and Implementation in Chapter 4 Description Displays the description for the selected strategy This field is editable for user defined strategies only ISE command line options Configure command line options for the ISE implementation tools NGDBuild MAP PAR and TRCE Use the More Options field to specify options that are not listed You can find a brief description of each o
260. can run Design Rule Checks DRCs after RTL design elaboration The available rules focus on power reduction and performance improvement opportunities 1 Torun the DRC checks after elaborating the design select one of the following commands e Tools gt Run DRC from the main menu e From the RTL Design menu of the Flow Navigator select Run DRC The Run DRC dialog box opens as shown in Figure 5 14 to enable rule selection G Run DRC Results Name results_1 Output File e Rules to Check 10 of 10 tag a JA naa SM All Rules 10 Mi RTL 10 SM Power 4 LM Constantly enabled synchronous RAM RPRC Mi Inefficient dangling BRAM port RPRM M Shallow RAM implemented in Block RAM RPRS iM Inefficient mapping of small multiplier in DSP block RPDS SM Performance 6 iM Inefficient library element instantiation RPL M Inefficient pipeline register RPIP iM Found Black Box instance not belonging to UNISIM library RPX W Found latch in design RPLD Figure 5 14 Run Design Rule Checker Dialog Box 2 Inthe Run DRC dialog box select the required rules and click OK For rule descriptions see Appendix B PlanAhead DRCs Analyzing DRC Violations If violations are found the DRC Results view opens as shown in Figure 5 15 page 195 The DRC Results view displays the rule violations found grouped under the various rule categories defined in the Run DRC dialog The rule violations are
261. cated after the move Dropping one view onto an existing view places the two tabs in the same region To move a view to share the space in a viewing area 1 Click a tab for example the Constraints tab 2 Drag the tab to a location The gray outline serves as a guide 3 Release the tab at the location you want Using Graphical Workspace Views PlanAhead User Guide The views with a graphical interface and those that require more screen space like the Text Editor or the Report Viewer display in an area called the workspace These views are different than other views because more than one can be opened simultaneously to view or compare different information These workspace views can be made full size floated or split by using the popup menu commands on the view tab The PlanAhead tool workspace is the graphic viewing area that displays the graphical views and some report and log information The views that display in the workspace are e Project Summary e Text Editor e Device view e Package view e Clock Resource Planner e Schematic view e Hierarchy view To open a new Device or Package view select Window gt Device or Window gt Package You can open multiple views of the same view type within the workspace area For example two Device views can display different areas of the device While most graphical views can be opened from the Window menu the Schematic and Hierarchy views must be opened after selecting a logic el
262. ce files constraint files and report files Figure 4 35 shows the Find in Files dialog box G Find in Files Find what FIFO Options C Match case Enabled design sources 91 C Constraints 3 Reports 1 Open in a new tab Figure 4 35 Find in Files Dialog Box Use the Find in Files command to search for a specified text string as follows 1 Enter the text string to locate in the Find What field 2 Enable options as needed e Match case makes the search case sensitive PlanAhead User Guide www xilinx com 119 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment g XILINX it Bi A e Match whole word do not search for substrings e Use Regular expressions or Wildcard based search e Scope search enabled design sources constraint files open reports e Open in anew tab open the results in a new view or replace an existing view 3 Click Find The search results display in the Find in Files Results view as a list of files that contain the search string and the number of occurrences in each file Double click a file name in the Results view to load the source file into the Text Editor and highlight the string Figure 4 36 shows the Results view of a sample search 7 SO 52 14 3 41 101 SO 14 59 L1A inout FIFO WIDTH 1 01 din Found usages 162 usages 8 C Planahead_Installiplandhead testcases Plan4head_Tutorial Projects
263. ce_sharing iob netlist_hierarchy power ram_style bufg equivalent_register_removal mux_extract More Options Figure 4 73 Strategies Options Description Plandhead Defaults XST defaults with hierarchy speed 1 forward auto off no auto yes auto rebuilt no auto yes yes Select an option above to see description of it m The PlanAhead tool provides several commonly used strategies that are tested against internal benchmarks The command line settings for predefined PlanAhead synthesis and implementation strategies cannot be changed However you can copy and modify supplied strategies to create your own PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 167 Chapter 4 Using the Viewing Environment XILINX The PlanAhead tool writes the copied strategies to C Documents and Settings username Application Data Xilinx PlanAhead strategies on Windows at the time you create them To review copy and modify strategies 1 Select Tools gt Options from the main menu 2 Select Strategies in the left side panel The Strategies dialog box shown in Figure 4 73 page 167 contains a list of pre defined strategies for each ISE and Xilinx Synthesis Technology XST version 3 Inthe Flow pulldown select the appropriate XST version for synthesis or ISE version for implementation A list of provided strategies and their various command line options displays Fo
264. ceed to manually specify source files and settings 3 Click Next Adding Source Files or Directories The Add Sources page in the New Project wizard lets you add RTL source files and add directories that contain RTL source files Use the Add Files and Add Directories commands as shown in Figure 3 3 You can create new RTL source files using the Create File command G New Project Add Sources Specify HDL and netlist files or directories containing HDL and netlist files to add to your project Create a new source File on disk and add it to your project You can also add and create sources later async_Fifo v work bFt vhdl work bft_tb v work FFtTop work FifoBuffer v work Frame_check y work frame_gen work bFtLib work 100000600 OID HARYNE EA Id Name Library HDL Source for Synthesis amp Simulation Synthesis amp Simulation Synthesis amp Simulation Synthesis amp Simulation Synthesis amp Simulation Synthesis amp Simulation Synthesis amp Simulation Synthesis amp Simulation Location v C iPlanahead_Projects Planahead_Tutorial_13 3 Sour v C Plan head_Projects PlanAhead_Tutorial_13 3450ur v C Plan4head_Projects PlanShead_Tutorial_13 3 Sour C Plandhead_Projects PlanShead_Tutorial_13 3 Sour v C Plandhead_Projects Plandhead_Tutorial_13 3 Sour v C Plandhead_Projects Plan4head_Tutorial_13 3 Sour v C Plan4head_Projects Plandhead_Tutorial_13 3 Sour v C Plandhead_Projects Plandhea
265. ces See Understanding Fixed and Unfixed Placement Constraints page 329 for more information If you chose to unplace ports you might also be presented the choice of preserving fixed ports or unplacing all ports as shown 336 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Working with Placement LOC and BEL Constraints 7 Click Next to continue The Clear Placement Summary opens to show a summary of the instances to be unplaced 8 Verify the contents of the Clear Placement Summary and click Finish e The specified I O ports and instances are unplaced from the device e Previously assigned ports are not cleared until a new UCF is read into the PlanAhead tool e New port assignments write over previous assignments Note A best practice is to first clear all port assignments prior to importing new port assignment constraints Setting Placement Prohibit Constraints PROHIBIT constraints allow you to mark resources on the device as prohibited for placement purposes That is you cannot place and the software cannot place instances or ports on prohibited resources The PROHIBIT constraint can be used to ensure device compatibility between multiple parts By prohibiting resources not common to compatible parts you can ensure the design easily maps from one device to another You can create a PROHIBIT constraint for any logic site on the device To do so 1 Select the sites in the Device view
266. cific object in the Clock Resources view on the device on the package or in the netlist Use Automatically Scroll to Selected Object on the toolbar menu to scroll the Clock Resources view to display an object that is cross selected when you have selected an instance or resource in another view Use this to quickly locate a specific resource on the device in the Clock Resources view You can toggle the automatic scroll off to prevent the PlanAhead tool from changing the displayed resources every time an object is selected ina different view Placing Design Instances The Clock Resources view displays two columns Site and Instance under each I O bank CMT or GTX bank to report both the device resource and the design instance to which it is assigned You can select logic instances from the design to place into the device resources from the Find Results Schematic Netlist or I O Ports views Select logic instances and drag them onto the instance column of the appropriate device resource in the Clock Resources view As you drag the instance around in the Clock Resources view the PlanAhead tool indicates sites where the instance cannot be placed with a NO symbol and sites where the instance can be placed with a rectangle The PlanAhead tool enforces specific rules and limitations regarding global and regional clock tree structures while you are placing instances from the design For specific information on these rules and limitations refe
267. code snippet from a Tcl script t project 1 C Data Plandhead_Designs Plandhead_Tutorial Tutorial Created Data project_ 1 design mode RTL get_property sreset current_run force norecurse C Data Planadhead Designs 12 demo Sources Therm library work get_files of_objects get_property sreset current _run C Data Plandhea fileset get property constrset current run force norecurse C Data Plandhead Desig top therm get_property sreset Current_run verilog 2001 true get_property sreset current_run verilog uppercase false get_property sreset current_run loop_count 1000 get_property sreset Ccurrent_run runs synth 1 jobs 1 runs impl_ 1 jobs 1 Figure 1 2 Example Tcl Script For more information about the PlanAhead tool journal file see Journal File planAhead jou and planAhead jou backup page 413 For more information about scripting and using the PlanAhead tool with Tcl see Chapter 14 Tcl and Batch Scripting PlanAhead User Guide www xilinx com 17 UG632 v13 4 January 18 2012 Chapter 1 About the PlanAhead Tool 18 www xilinx com XILINX PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Chapter 2 The PlanAhead Tool Flow You can use the PlanAhead tool at many places in the design flow The flows described in this chapter correspond to the project types that can be created Project types are described in more detail in Chapter 3 Working with Pro
268. coded indicators for warnings and errors Any warnings issued to the console are colored yellow and errors are red This is a useful feature to scroll back through message history and navigate to view warnings and errors in the context of the command that was performed Figure 14 1 shows the Tcl console within the environment E INFO HD LIB 0 Reading timing library C pal2 plandhead parts xilinx virtex virtex lib INFO HD LIB 1 Done reading timing library C pal2 plan head parts xilinx virtex6 virtex6 lib get_cells cpuEngine cpuEngine PWR_295 cpuEngine cpu_iwb_dat_i cpuEngine cpu_iwb_dat_o cpuEngine cpu_dwb_dat_i cpuEngine cpu_dwb_dat_o Console Elaboration Messages Reports Figure 14 1 Tcl Console Invoking the PlanAhead Software The PlanAhead tool provides three primary modes of operation 392 The GUI mode default Invocation of the PlanAhead tool executable by a Tcl command line option Batch mode Tcl shell mode www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX General Tcl Syntax Guidelines The following subsections describe Batch and Tcl shell modes Batch Mode Batch mode executes a script and then shuts down the tool To invoke the PlanAhead tool in batch mode planAhead mode batch source script_name tcl Tcl Shell Mode Tcl mode invokes a shell similar to windows command shell or a linux shell This is an interactive shell session
269. compliance status of the IP and license requirements When you select a specific IP core a description displays in the lower pane of the view Figure 3 26 shows an example of the IP Catalog view You can select an IP core from the catalog and view a variety of information regarding that core To bring up a PDF datasheet for a selected IP you can e Click Data Sheet from the popup menu e Click the View Information button on the IP Catalog toolbar and select the Data Sheet command from that popup menu Q Search 24 Name 1 Version 2 AxI4 Status License H Telecommunications H Wireless Debug amp Verification Digital Signal Processing Building Blocks gt B B Filters dX F CIC Compiler A Production Included 4 RK IF DUC DDC Compiler kere iia a Ww TF FIR Compiler ere Pe ey H Modulation H Transforms W o Trig Functions v El H Waveform Synthesis Detalls Name FIR Compiler Version 6 0 Interfaces AXI4 Stream Description The Xilinx FIR Compiler LogiCORE is a module for generation of high speed compact Filter implementations that can be configured to implement many different filtering Functions The core is fully synchronous using a single clock and is highly parameterizable allowing designers to control the filter type data E Project Summary X FIP Catalog x EAE Figure 3 26 Xilinx IP Catalog Command options available in th
270. cond to show Unclocked Register Pins to help you identify unclocked pins and resolve timing constraint problems e Select an unclocked pin in the report and use the Schematic command on the right mouse button to open the schematic instance containing the pin e Select the Expand Cone command from the Schematic view to expand the path to the pin These tools can help you better understand the problems in a large design Defining Physical Constraints The PlanAhead tool provides a variety of ways to apply physical constraints Physical constraints consist of LOC BEL instance placement constraints AREA_GROUP placement constraints DCI_CASCADE constraints and Device Configuration Mode constraints For more information on assigning physical constraints refer to Chapter 8 I O Pin Planning and Chapter 10 Floorplanning the Design The following subsections describe the Physical Constraints view and the available options Using the Physical Constraints View PlanAhead User Guide The Physical Constraints view is used to display and interact with a variety of physical constraint types The Physical Constraint view is opened when you switch to the Floorplanning view layout using Layout gt Floorplanning or by selecting the Floorplanning layout in the Layout Selector on the toolbar You can also open the Physical Constraints view at any time by selecting Window gt Physical Constraints The Physical Constraints view displays the hi
271. created by NetGen You can specify Verilog or VHDL insert_pp_buffers Switch to control whether path pulse buffers are inserted into the output netlist to eliminate pulse swallowing Pulse swallowing is seen in timing simulations when the pulse width is shorter than the delay on the input port of the component fn Switch to output a flattened netlist versus a hierarchical netlist a Switch to generate only architectures in the VHDL output This option suppresses generation of VHDL entities in the output sdf_anno Specify whether the sdf_annotate statement should be added to the netlist output by Netgen for delay annotation tm Specify a new name for the top module to be used in the output from NetGen extid Switch to output extended identifiers in VHDL output sdf_path Specify the path to output the SDF file created by NetGen By default the SDF file is output to the simulation run directory ism Switch to include SimPrim modules from the SimPrim library in the output Verilog file This option lets you avoid specifying the library path during simulation but increases compile time and the size of the output netlist More NetGen Options Specify additional command line options for NetGen These commands must be typed in a single string with the command value pair For example aka gp lt port_name gt s 3 www xilinx com 365 UG632 v13 4 January 18 2012 366 Chapter 11 Analyzing I
272. cts While executing get_ports of objects Spin procedure my_report line 6 invoked from within procs tcl You can add the puts errorInfo into catch clauses in your Tcl script files to report the details of an error when it is caught or use the command interactively in the Tcl console immediately after an error is encountered to get the specific details of the error In the example code above typing the puts errorInfo command in line 6 reports detailed information about the command and its failure in line 7 PlanAhead User Guide www xilinx com 395 UG632 v13 4 January 18 2012 Chapter 14 Tcl and Batch Scripting XILINX Sourcing a Tcl Script A Tel script can be sourced from either one of the command line options or from the GUI using File gt pulldown When you invoke a Tcl script from the GUI a progress bar is displayed and all operations in the GUI are blocked until the scripts completes There is no way to interrupt script execution during run time consequently standard OS methods of killing a process must be used to force interruption of the tool If the process is killed you lose any work done since your last save First Class Tcl Objects and Relationships 396 The Tcl commands in the PlanAhead tool provide direct access to the object models for netlist devices and projects These objects are first class which means they are more than just a string representation and they can be operated on and querie
273. currently Note Phase groups are only supported in the software and SSN calculations for Virtex 6 devices While phase shifting improves the Spartan 6 device performance on SSN the improved performance cannot be seen in the software calculations For Virtex 6 see Defining I O Port Switching Phase Groups in SSN page 288 Phase shift the offending group by 90 degrees if at a DDR rate or by 180 degrees if at an SDR rate This puts half the aggressive output switching out of phase with the other half and instead of interfering constructively it interferes destructively If a Spartan 6 design fails SSN certain failures can be ignored See AR 36141 for details For more information see Pin Planning to Mitigate SSO Sensitivity in the Spartan 6 FPGA SelectIO Resources User Guide UG381 cited in Appendix E Additional Resources Viewing I O Bank Properties in SSN Results You can select an I O bank in the SSN Results view to display information about the I O ports pins and groups assigned to the I O bank in the I O Bank Properties view Select the General tab to view information about the number and types of Ports assigned to the I O Bank Select the Package Pins or I O Ports tab to view the detailed information about the Pins or Ports within the bank as shown in Figure 8 33 page 287 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Using Noise Analysis Predictors gt fit aa I O
274. d There are a few exceptions to this rule but generally things can be queried as objects and these objects have properties that can be queried and they have relationships that allow you to get to other objects Object Types and Definitions There are many object types in the PlanAhead tool this chapter provides definitions and explanations of the basic types The most basic and important object types are associated with entities in a design netlist and these types are listed in the following subsections Cell A cell is an instance either primitive or hierarchical inside a netlist Examples of cells include flip flops LUTs I O buffers RAM and DSPs as well as hierarchical instances which are wrappers for other collections of cells Pin A pin is a point of logical connectivity on a cell A pin allows the internals of a cell to be abstracted away and simplified for easier use and can either be on hierarchical or primitive cells Examples of pins include clock data reset and output pins of a flop Port A port is a special type of hierarchical pin a pin on the top level netlist object module or entity Ports are normally attached to I O pads and connect externally to the FPGA device Net A net is a wire or collection of wires that eventually be physically connected directly together Nets can be hierarchical or flat but always sorts a collection of pins together Clock A clock is a periodic signal that propagates to sequential lo
275. d peripherals An example is shown in Figure 3 31 CA Se 4 x MM TeS u SS D o _ u Ji f C aea 5 Bus Interfaces Ports Addresses Name 3 8 4 2 GOSS OOO ee Figure 3 31 axi_interconnect_memory_mapped_lite_O microblaze_0_dimb microblaze_0_ilmb microblaze_O microblaze_O_bram_block microblaze_0_d_bram_ctri microbloze_O_ _bram_ctri debug_module microblaze_O_inte Ethernet_Lite DIP_Switches_4Bits LEDs_4Bits Push_Buttons_4Bits SPI_Fiash ax_timer_O RS232 Uart_1 clock_generator_0 reset 0 Embedded Processor System IP Type XE axi_interco wr imb_v10 tr Imb_v10 r microblaze wy bram_bloci r Imb_bram_ ty imb_bram_ r mdm x axi_intc XS axi_etherne XE ax_gpio 2k ai_gpio XE axi_gpio XE ax_spi XE axi_timer XE ai_uartlite tr clock_gene vy proc_sys_re This example system includes MicroBlaze Block Memory Ethernetlite UARTLite SPI_Flash Controller GPIO Clock and Reset modules This system also utilizes the AXI interconnect for communication as shown under the IP Type column of Figure 3 31 To properly integrate the embedded processor system into the PlanAhead tool it is important to understand the files and directory structure produced by XPS Figure 3 32 page 72 shows the directory structure of the example embedded processor system UG632 v13 4 January 18 2012 www xilinx com 71 Chapter 3 Working with Projects XILINX E _xps 10 1 2010 2 14
276. d_Tutorial_13 3 Sour Add Files 4dd Directories Create File Scan and Add RTL Include Files into Project Copy Sources into Project Add Sources From Subdirectories Figure 3 3 New Project Wizard Add Sources Page PlanAhead User Guide www xilinx com UG632 v13 4 January 18 2012 37 Chapter 3 Working with Projects XILINX Note If you imported an XST or Synplify project file the PlanAhead tool detects the source files in the specified project file and adds the files automatically to the Add Source table You can add or remove files from this list as needed The available commands and options of the Add Sources dialog box are e Add Files Invokes a file browser so you can select RTL files to add to the project e Add Directories Invokes a directory browser to add all RTL source files from the selected directories Files in the specified directory with valid source file extensions are added to the project e Library Specify the RTL library for a file or directory by selecting one from the currently defined library names or specify a new library name by typing in the Library text field The work library is the default library into which all HDL source files are placed You can create or reference additional user VHDL libraries as needed e HDL Source for Specify if the source being loaded is an RTL design source for synthesis and simulation or an RTL test bench for simulation only
277. d_o_o Output 14LvCMos25 25 12 SLOW default D DataOut_pad_t_o 8 Output 16 LVCMOS25 25 12 SLOW default 3 H Linestate_pad_O_i 2 Input 14 Lvcmos25 25 12 SLOW default GB eB LineState_pad_1_i 2 Input 16 LyCMOS25 25 12 SLOW default E Opmode_pad_0_0 2 Output 14 LvcMmos25 2 5 12 SLOW default Sd GG OpMode_pad_1_o 2 Output 16 LYCMOS25 2 5 12 SLOW default g Package Pins 00x A Name Prohibit Port Yostd Dir Veco Bank BankType Type Diff Pair Clock Voltage Config System Monitor Gigabit E AllPins 784 a a a IO Banko Dedicated Sa 10 Bank 14 25 Standard eam IO Bank 15 25 Standard ial H a I O Bank 16 25 Standard 1 0 Bank 23 Dedicated a I O Bank 24 25 Standard a I O Bank 25 25 Standard Heim I O Bank 26 25 Standard I O Bank 34 2 5 Standard a 1 0 Bank 35 Standa 25 Standard x si EJE E Tel Console Messages 9 Package Pins I O Planning Flow Figure 8 1 WO Planning Environment Using the I O Planning view layout You can use the I O Planning view layout in the RTL Design Netlist Design and Implemented Design environments The view layout uses both Device and Package views Other views provide additional I O information the Clock Resources and Clock Regions view the Package Pins view the I O Ports view and the Properties view PlanAhead User Guide www xilinx com 253 UG632 v13 4 January 18 2012 Chapter 8 VO Pin Planning XILINX There are two
278. dd to your project IF there are multiple files then please choose the target which is where all of the constraints created by Plandhead will be saved Specify Constraint Set jaa constrs_1 active Constraint File Target optional Location top ucf O C Data FPGA_design AddFiles Create File Copy Constraints into Project lt Back J Einish Cancel Figure 3 20 Adding Constraint Files using Add Sources The Add or Create Constraints dialog box has the following options PlanAhead User Guide Specify Constraint Set Defines the constraint set into which the constraint files are placed By default the currently active constraint set is selected but you can specify a different constraint set or define a new constraint set using the drop down menu Add Files Browse to and select the UCF NCF or XCF files to add to the project Create File Create a new top level UCF for the project Remove Remove the selected UCF from the Constraint files list Up Down Move a constraint file up or down in the listed order of UCF files Constraints are order dependent with the last read definition of a constraint www xilinx com 57 UG632 v13 4 January 18 2012 58 Chapter 3 Working with Projects XILINX over writing earlier definitions If there are multiple files in a constraint set the order in which they appear in the Sources view corresponds to the order that the PlanAhead tool
279. default value is 3 Sort Paths By Selects that parameter that are used to sort the timing report This field contains the following values e Group Sorts the timing report based on group name e Slack Sorts the timing report based on path slack Understanding the Advanced Tab PlanAhead User Guide The Advanced Options tab of the Report Timing dialog box contains fields that let you specify pin and net details report output locations and command error processing The Advanced Options tab is shown in Figure 7 15 page 226 www xilinx com 225 UG632 v13 4 January 18 2012 Chapter 7 Netlist Analysis and Constraint Definition XILINX G Report Timing Results Name results_1 Targets Options Timer Settings Pins amp Nets Show input pins in path List net names Output i Overwite Append Miscellaneous C Quiet mode Ignore command errors Command report_timing from get _pins Suspend pad_1_o C Control_pa Open in a new tab Figure 7 15 Report Timing Advanced Tab The Advanced tab options are e Show input pins in path Shows the input pins that start each path e List net names Lists the name of the net connection for each path element e Write results to file Write the results of the timing report to a file e Overwrite Overwrites a file with the same name as the specified file e Append Appends the timing report details to the specified file e Quiet
280. design flow To accommodate this you can create the following types of projects Register Transfer Level RTL source based Synthesized netlist based Implemented design results based I O pin planning projects Comma Separated Values CSV User Constraint File UCF based Projects created in ISE Project Navigator Partial Reconfiguration projects with an enabled license These projects are differentiated by the input source types used to create the project You can select the type of project during the Create New Project process After you select a particular project type it cannot be later migrated to a different type Note The PlanAhead tool uses a derivative type of project to support Partial Reconfiguration designs This capability is available only through special licensing and is covered in the Partial Reconfiguration User Guide UG702 cited in Appendix E Additional Resources PlanAhead User Guide www xilinx com 33 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects XILINX 34 RTL Source Based Projects You can use the PlanAhead tool to manage the entire FPGA design flow from RTL creation through bitstream generation You can add RTL source files as well as IP generated by the CORE Generator tool and precompiled NGC NGO format IP netlists to the project You can elaborate and analyze the RTL to ensure proper constructs launch and manage various synthesis and implementation runs and ana
281. directories to search for lower level modules and cores By default both the launch directory and the directory from which the top level netlist was selected are included in the search path To arrange the order of the directories select them and use the up or down arrows buttons To remove directories from the list use Remove Remove Selected Files and Directories The X icon removes the selected source files and directories from the list www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Creating a New Project e Move Selected Files and Directories Up The upward pointing arrow icon moves the file or directory up in the list order e Move Selected Files and Directories Down The downward pointing arrow icon moves the file or directory down in the list order e Copy Sources into Project Copies the original source files into the project and uses the local copied version of the file in the project If you added directories of source files using Add Directories the directory structure is maintained when the files are copied locally into the project For a complete discussion of this topic refer to Using Remote Sources or Copying Sources into Project page 55 e Add Sources from Subdirectories Look for netlist files in the subdirectories of directories specified with Add Directories Click Next Add constraints as described in Adding and Creating Constraint Files page 57 Defin
282. ditor Invokes FPGA Editor with the current implemented design e Launch XPower Analyzer Invokes XPower Analyzer with the current implemented design e Export to Spreadsheet Export information in the Design Runs view into a spreadsheet file e Promote Partitions Invokes the Promote Partitions dialog box to promote implemented partitions This option is only available when partitions are defined in the design See Chapter 13 Using Hierarchical Design Techniques for more information Using the Text Editor The Text Editor in PlanAhead provides the ability to edit a variety of text files in a context sensitive editor PlanAhead supports a variety of formats Verilog and Verilog header files VHDL files Constraint files PlanAhead Journal and Log files and simple text files Some of these files are supported with context sensitive editing to make it easy to identify keywords and comment lines within the file Refer to Setting Fonts for Text Editor page 169 for more information on configuring the Text Editor Opening a Text File PlanAhead User Guide You can open a file for editing in the Text Editor by selecting the file in the Sources view and selecting the Open File command from the right mouse popup menu You can also open a file using the File gt Open File command from the main menu This command opens a file browser for you to navigate to the file and open it for editing You can double click the file name from a
283. ds G Replace in Files Find what whb_addr_i Replace with wb_Addr_in Options Match case Match whole word C Use Scope Enabled design sources 91 C Constraints 3 Figure 4 37 Replace in Files Dialog Box Use the Replace in Files command to search and replace a specified text string as follows 1 Enter the text string to locate in the Find What field 2 Enter replacement text in the Replace with field 3 Enable options as needed e Match case makes the search case sensitive e Match whole word do not search for substrings e Use Regular expressions or Wildcard based search e Scope search enabled design sources constraint files open reports e Open in a new tab open the results in a new view or replace an existing view 4 Click Find The search results display in the Find in Files Results view as a list of files that contain the search string and the number of occurrences in each file You can select any occurrence of the text in the list to replace with the new text or you can choose to replace all occurrences of the specified text Double clicking on an occurrence of the text in the Results view will highlight that occurrence in the Text Editor Figure 4 38 page 122 shows the results of an example search PlanAhead User Guide www xilinx com 121 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment g XILINX it HA 15 25 define USBF_RF_SEL wb_addr
284. duces verification time and reduces design closure time See Leveraging Design Preservation for Predictable Results UG747 as cited in Appendix E Additional Resources Partial Reconfiguration The PlanAhead tool provides an environment to configure implement and manage Partial Reconfiguration projects The PlanAhead tool uses the partitions and Partial Reconfiguration capabilities that are built into the ISE Design Suite implementation tools See Overview of Partial Reconfiguration Flow UG743 as cited in Appendix E Additional Resources PlanAhead User Guide www xilinx com 389 UG632 v13 4 January 18 2012 Chapter 13 Using Hierarchical Design Techniques XILINX 390 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Chapter 14 Tcl and Batch Scripting This chapter is not a comprehensive reference to Tcl commands but does provide references to Tcl resources and describes the general capabilities of Tcl in the PlanAhead environment The Tool Command Language Tcl is the scripting language integrated in the PlanAhead application environment Tcl is a standard language in the semiconductor industry for design constraints and Synopsys Design Constraints SDC SDC is the mechanism for communicating timing constraints for FPGA synthesis tools from Synopsys Synplify as well as other vendors and is a timing constraint industry standard consequently the Tcl infrastructure is a B
285. e lt inputdir gt lt design gt pcf Physical constraints file END Program map The three important options to consider are e pr b pack the internal flops into input i output o or both b types of IOBs e ol high overall effort level is set to high e timing perform a timing driven packing Set these options in the Implementation Settings for the implementation run especially the pr b option Without this option several of the Processor IP cores will not function correctly Refer to Setting Implementation Options in Chapter 9 or Configuring Implementation Run Settings in Chapter 9 for more information on setting these options The following PAR options are set in the fast_runtime opt Program par w Overwrite existing placed and routed ncd ol high Overall effort level lt inputdir gt lt design gt _map ncd Input mapped NCD file lt design gt ncd Output placed and routed NCD lt inputdir gt lt design gt pcf Input physical constraints file END Program par You only need to be concerned with the 01 high option which sets the Place and Route overall effort level to high Set the PAR options as outlined above for the MAP options After all of the Implementation Options are set launch the run Creating the Bitstream File PlanAhead User Guide The final step is to create a bitstream file in BitGen containing the software application targeted for the block RAM For this step to be success
286. e I O planning environment PlanAhead User Guide www xilinx com 153 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX e Display the ports according to category by interface or alphabetically by clicking the Group by Interface and Bus button in the I O Ports view e Define the direction of the port by directly editing the Dir column to specify Input Output or In Out as the port direction e Open the Schematic viewer for selected I O ports by selecting the Schematic toolbar button y el ie Ba P You can select ports and interfaces from the I O Ports view and assign them using the I O Planning environment See Using Tree Table Style Views page 106 for more information about using the tree table style views Using the Package Pins View The Package Pins view displays I O related package information You can sort and filter the table to analyze the I O pins and I O ports information Opening the Package Pins View To invoke the Package Pins view select Window gt Package Pins Figure 4 66 shows the Package Pins view all J BB27 fs P BB28 Sal P BB30 P Bc30 P Bc28 P BC29 P Baza P BA30 D aw29 P AY29 D AW27 P ave P AY31 J BA31 Prohibit Port Yo Std Dir Yeco Bank Bank Type Type Diff Pair DataIn_pad_1_i 5 LVCMO518 Input 1 8 14 High Performance Multi function L3P DataIn_pad_1_i 6 LVCMO518 Input 1 8 14 High Performance Multi Function L3N DataOut_pad_0_o 6
287. e IP Catalog toolbar and or popup menu include e Show Search Displays a Search field to search the catalog for any text string e Collapse Expand All Collapses or Expands the IP Catalog tree e Hide Superseded and Discontinued IPs Filters the list to show current IP only e Hide incompatible IP Filters the list to show only the IP that is compatible with the selected device family e Group by Category Groups or flattens the list for better sorting and searching e Customize IP Opens the customization GUI for the selected IP See Customizing IP for the Project page 66 for more information PlanAhead User Guide www xilinx com 65 UG632 v13 4 January 18 2012 66 Chapter 3 Working with Projects XILINX e License Status Displays license requirements and status for the selected IP e Compatible Families Displays a list of all device families that are compatible with the selected IP e View Data Sheet Version Information Webpage and Answer Records Displays specified documentation for the selected IP e IP Catalog Settings Opens Project Settings for the IP Catalog e Update IP Catalog Regenerates the IP Catalog at the specified location This lets you check for any updates to the Xilinx IP Catalog See Updating the IP Catalog page 69 for more information e Automatically Scroll to Selected Objects Toggles the display to jump to the selected object in the open view e Expor
288. e Net Properties View See Using the Schematic View in Chapter 4 Using the Viewing Environment Document Tool Command Language Tcl error errorInfo variable See Errors Warnings Critical Warnings and Info Messages in Chapter 14 Removed File gt Export IBIS command UG632 v13 4 January 18 2012 www xilinx com PlanAhead User Guide Date Version Revision 10 19 11 13 3 e Documented file based design entry for netlist projects See Creating a Project with a Synthesized Netlist in Chapter 3 Working with Projects e Added Define Modules when creating new RTL source files See Defining New Modules in Chapter 3 Working with Projects e Documented project part for synthesis and implementation See Configuring Project Settings in in Chapter 3 Working with Projects e Documented project wide default language See Configuring Project Settings in Chapter 3 Working with Projects e Described the project subdirectory checkbox in New Project wizard See Creating a New Project in Chapter 3 Working with Projects e Documented automatic command completion in the Tcl Console See Using the Tel Console and Messages Area in Chapter 4 Using the Viewing Environment e Updated Properties View and Run Properties View See Using the Properties View in Chapter 4 Using the Viewing Environment e Documented Hierarchies Libraries Compile Order tabs of the Sources View See Using Common Views in Chapter 4 Using the Viewing Environment
289. e Pins view by clicking any of the column headers Clicking again reverses the sort order To sort by a second column press the Ctrl key and click another column You can add as many sort criteria as necessary to refine the list order Sorted results might be more readable if you flatten the list of Package Pins using the Bl Group by I O Bank toolbar button 154 PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com g XILINX Using Common Views Refer to the Using Tree Table Style Views page 106 for more information Cells with editable values can be directly edited in the Package Pins view either by entering text or by selecting from drop down menus Using Package Pins View Commands Refer to the Using View Specific Toolbar Commands page 108 for more information on toolbar commands You can toggle to display pins according to category by I O bank or display the pins alphabetically by clicking the Group by I O Bank button in the Package Pins view Using the Design Runs View You can use the Design Runs view to view configure launch and analyze Synthesis and Implementation runs The Design Runs view offers commands to manage runs such as Copy Run Reset Run Launch Runs Use the right mouse popup menu for a complete review of the available commands As runs are created launched or imported the status shows in the Design Runs view The Design Runs view is used extensively in the Partial Reconfigu
290. e Programming You can create programming bitstream files for any completed implementation run Bit file generation options are configurable Launch the iMPACT tool to configure and program the part Design Verification and Debug User Models You can configure and implement ChipScope Pro Analyzer tools and IP cores such as the Integrated Logic Analyzer ILA and Integrated Controller ICON in the Netlist Design and select and configure the required probe signals into the cores You can launch the ChipScope Analyzer tool on any run that has a completed bitstream file You can launch the ChipScope Analyzer tool directly from the PlanAhead tool for further analysis of the routing or device resources The PlanAhead tool provides a Graphical User Interface GUI with layered complexity It provides an intuitive environment for new or casual users and also provides access to the more advanced features By default the PlanAhead tool opens with a push button flow suitable for users who do not require more advanced analysis and floorplanning features The flow is controlled by a view called the Flow Navigator described in Understanding the Flow Navigator page 24 Basic User Flow The PlanAhead tool lets you execute the entire development cycle using the run buttons in the PlanAhead tool Flow Navigator You can traverse the FPGA development process front to back beginning with importing source files synthesizing design logic impleme
291. e a default part as discussed under Selecting a Default Part page 42 The New Project Summary page displays the selected options that define the project Click Finish to create and open the project Creating an I O Planning Project Another project type is an I O Pin Planning project used specifically for planning the device pinout for an in progress system level design You can create such a project prior completing the HDL or the synthesized EDIF This allows you for example to exchange design information with the system level or PCB designer For more information about I O pin planning refer to Chapter 8 I O Pin Planning In the Design Source page select the Create an I O Planning Project option Importing I O Ports PlanAhead User Guide The next page in the New Project wizard shown in Figure 3 10 prompts you to select a file for importing I O Port definitions and constraints G New Project Import Ports optional You may specify a CS file or a UCF File to define and configure your ports IF you skip this step now you can import ports later and or create ports manually Import CSV C Plandhead_Installiplan4head testcases Plan4head_Tutorial Sources IO_Ports_import csy Import UCF iz Do not import IJO ports at this time Figure 3 10 New Project Wizard IO Pin Planning www xilinx com 45 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects XILINX 46 1 Set the following o
292. e a new source file 1 2 Select the Add or Create Design Sources option from the Add Sources command Click Create File The Create Source File dialog box opens in which you can define the type name and location of the new source file you are creating as shown in Figure 3 16 G Create Source File i Create a new source file and add it to your project File type name amp location File type Verilog File name File location 6 lt Local to Project gt Figure 3 16 Create New Source File You can define the following information in the Create Source File dialog box e File type Select one of the following file types Verilog Create a Verilog format file v Verilog Header Create a Verilog Header format file vh VHDL Create a VHDL format file vhd1 e File name Enter a name for the new HDL source file e File location Designate a location to create the file www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Managing RTL Source Files 4 Click OK A placeholder for the file is added to the list of sources the file is created when you click Finish 5 You can repeat the Create File command multiple times to define a number of new modules to add to the project 6 Inthe Add Sources dialog box specify the appropriate Library for the source file By default sources are added to the work library 7 Click Finish to add the speci
293. e effect after you modify options and click OK or Apply There are default view settings for both light and dark background themes To use either select the PlanAhead Light Theme or PlanAhead Dark Theme options in the Theme pulldown menu www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Configuring PlanAhead These default options are defined in the planahead ini file For more information see Outputs for Environment Defaults in Appendix A G PlanAhead Options Plandhead Light Theme 7 Save As Name Color Graphical Editors Background Foreground Selection Markers Highlight Hierarchy view 4 Schematic Viewer Histogram Chart Console Background Foreground Command text Error text Warning text Windows Background Foreground 240 240 240 EE o o o EE 255 102 0 9 255 255 0 255 255 255 EE o o o E 0 0 255 EE 153 0 0 E 204 102 0 255 255 255 EE o o o Window Behavior lt Description Color for selected objects Color For Tcl commands Color for error messages Color for warning messages General Device I Os Bundle Nets Figure 4 70 Theme Options Customizing Display Themes You can adjust the options that control the appearance of the PlanAhead viewing environment in the Themes options The tabs at the bottom of the Themes options let you
294. e files from the list of files to be added e Move Selected File Up Moves the file up in the list order e Move Selected File Down Moves the file down in the list order e Scan and Add RTL Include Files into Project Scans the added RTL file and adds any referenced include files e Copy Sources into Project Copies the original source files into the project and uses the local copied version of the file in the project If you selected to add directories of source files using the Add Directories command the directory structure is maintained when the files are copied locally into the project e Add Sources from Subdirectories Adds source files from the subdirectories of directories specified in the Add Directories option Managing IP Cores The PlanAhead tool lets you add IP cores to a project from the Xilinx IP Catalog and from third party IP providers Existing IP cores refers to existing XCO core files created outside of the PlanAhead tool by the CORE Generator tool You can add XCO core files to RTL projects only Also you can load parameterized cores by running the CORE Generator software from within the PlanAhead tool by using the IP Catalog command IP cores are available in the Embedded Development Kit EDK or DSP tools also and you can load existing XCO core files from these sources as well Note In some cases third party providers offer IP as synthesized NGC or EDIF netlists You can load these files into a
295. e layers and objects are listed hierarchically in a tree view that can be expanded or collapsed PlanAhead User Guide www xilinx com 131 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX E Project Summary X Device x ff Package Bottom x Haze x e EE Design a v E Instances Nets P Layers R Q Ports E Pblocks Slideout my J Bundle Nets Button Gak Device A H Tiles E Sites Bels I O Banks Om yo Banko BB 1 0 Bank 13 BB 1 0 Bank 14 D Yo Bank 15 E 1 0 Bank 16 E 1 0 Bank 33 E 1 0 Bank 34 4 D D p p pM p pppE mNNO oooo agp EOS P Dedicated Clock Regions 0000009 5 RK R RRP Figure 4 44 Device View Layers The two primary branches are Design objects and Device objects e Design objects are elements from the design sources such as instances nets and ports that are placed on the device e Device objects are resources on the device such as I O blocks clock regions and tiles on which design objects can be placed Click the sign to expand or the sign to collapse the levels of the tree view so you can see the layer or object Click the checkbox to enable or disable the layer or object for display in the Device view A green check mark indicates the currently displayed layer You can display or hide groups of objects or layers by clicking the category of the layers select individual layers or objects directory t
296. e library The 20 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Design Flow PlanAhead tool contains a Find in Files feature that lets you search these libraries using a variety of search criteria Opening an RTL Design elaborates the RTL source files and loads the RTL netlist automatically The open RTL Design lets you check RTL structure syntax and logic definitions Analysis and reporting capabilities include e RTL compilation validation and syntax checking e Netlist and schematic exploration e Design Rule Checks DRCs e Behavioral simulation e Resource utilization and power consumption estimation e Early I O pin planning is enabled using an RTL port list With a design open selecting an object in one view will cross select the object in other views including instantiations and logic definitions within the RTL source files Refer to Chapter 5 RTL Design for more information IP Customization and Implementation Run the integrated CORE Generator tool to browse customize instantiate implement and automatically update IP Logic Synthesis The PlanAhead tool lets you configure launch and monitor synthesis runs using the Xilinx Synthesis Technology XST tool Refer to Chapter 6 Synthesizing the Design for more information You can experiment with different synthesis options and create reusable strategies for Synthesis runs For example you could create strategies fo
297. e output can be expected to switch change values at the same time If a bank is failing in the SSN analysis phase groups can be used to group ports that are at separate synchronous phases thus lowering the total noise for that bank when the SSN predictor is run again To set the switching phase for a single or a set of I O ports 1 In any of the I O Planning views select one or more I O port s 2 Inthe I O Ports view Package Pins view or SSN view select Configure I O Ports as shown in Figure 8 34 G Configure Ports I O Standard multiple TENEN Drive Strength multiple Slew Type multiple Pull Type INONE default Phase 180 Figure 8 34 Configure Ports Dialog Box In the Configure Ports dialog box ensure the I O Standard is correct If the port s are in phase leave the Phase as default or enter a unique phase such as 180 and click OK 5 After the appropriate phase groups are assigned rerun the SSN analysis Note Asynchronous groups should not be treated as separate synchronous phases as it is possible for them to switch simultaneously 288 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using Noise Analysis Predictors Running WASSO Analysis The PlanAhead tool contains a set of Weighted Average Simultaneous Switching Output WASSO checks to validate signal integrity of the device based on the I O pin and bank assignments made in the design
298. e power system to this switching Xilinx characterizes all banks through three dimensional extraction and simulation This information is incorporated into the SSN predictor such that it can take the expected switching profile of a device and predict how the switching affects the power network of the system and in turn how other outputs in the I O bank are affected The SSN predictor is the most accurate method available for predicting how output switching affects interface noise margins The calculation and results are based on a range of variables These estimates are intended to identify potential noise related issues in your design and should not be used as final design sign off criteria 1 For Virtex 7 Kintex 7 and Artix 7 devices the PlanAhead tool performs a preliminary SSN analysis www xilinx com 283 UG632 v13 4 January 18 2012 Chapter 8 VO Pin Planning g XILINX To run the SSN predictor 1 Inthe Flow Navigator or from the Tools menu select Run Noise Analysis The Run SSN Analysis dialog box opens as shown in Figure 8 31 G Run SSN Analysis e J Runssn analysis on the current package and pinout Results Name fesults_1 C Export to File Open in a new tab Figure 8 31 Run SSN Analysis Dialog Box Note The Run Noise Analysis command runs either SSN or SSO analysis based on the target Xilinx device The dialog box that opens depends on the type of analysis the PlanAhead tool performs
299. e preserved providing consistent results and in some cases reduced runtimes With appropriate licensing the PlanAhead tool also provides access to the Partial Reconfiguration design application See Chapter 13 Using Hierarchical Design Techniques for an overview of these advanced design techniques www xilinx com 11 UG632 v13 4 January 18 2012 Chapter 1 About the PlanAhead Tool XILINX You can use the PlanAhead tool as a stand alone application or launch it for specific purposes from the ISE software A subset of features is available when launched from Project Navigator this subset is called ISE Integration Mode Refer to Chapter 15 Using PlanAhead With Project Navigator for more information about integration with Project Navigator Using the PlanAhead Tool 12 Use the PlanAhead tool to e Manage the design data flow with a push button run process from RTL development through bitstream generation e Perform RTL design and analysis using an elaborated RTL netlist e Perform behavioral and timing simulation using the integrated Xilinx ISim tool e Export I O Buffer Information Specification IBIS models e Customize and implement IP using the integrated CORE Generator tool e Configure and launch multiple synthesis and implementation runs e Perform I O pin planning e Manage constraints and perform floorplanning e Estimate the resource utilization timing and power consumption e Perform Design Rule Checks
300. e report indicates why a device resource is not displayed You can e Expand the logic tree under a specific resource using the view widgets to look into the resources of the hierarchy e Select design objects from the expanded Resource Estimation view to get more details of the selected object Selecting an object in the Resource Estimation view cross selects the object in the RTL Netlist allowing you a more complete understanding of the hardware requirements of the hierarchy The PlanAhead tool determines the estimation of the hardware resources required for an RTL design from pre synthesis design data These statistics are an early estimation and can change after synthesis or implementation The resource estimation is a quick estimation with an average accuracy of or 15 The Confidence Level value displayed in the Resource Estimation view provides insight into how accurate the resource estimation is likely to be based on design characteristics such as the number of black boxes in the design bus widths and macro types PlanAhead User Guide www xilinx com 179 UG632 v13 4 January 18 2012 Chapter 5 RTL Design XILINX Click the Confidence Level value link for details about the determining characteristics for the design being analyzed as shown in Figure 5 4 Resource Utilization Estimated resources are compared with xc6vlx7StfF784 3 Confidence Level High Show More Details Confidence Level Details n
301. e source location for the partition being imported This is useful for specifying which results to import when there are multiple implementations of a specific partition The Preservation level lets you import the Synthesis results for the partition and re implement the block or preserve the Placement but not the routing or preserve the Routing and timing of the implemented partition e If you are implementing a partition for the first time or re implementing a partition due to changes made in a design iteration select Implement as the action e Select OK or Cancel to close the form When you launch synthesis or implementation you can view the results in the Reports view The actions taken for the partitions in the run display in the report Figure 13 4 page 385 shows the NGDBuild report for an implementation with partitions 384 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Promoting Partitions R Projects project_DP_import project_DP_import runs impl_1 top bld pg 72 Partition Implementation Status n 35 Preserved Partitions Partition top usbEngine0 Partition top usbEnginel Implemented Partitions Partition top 65 Attribute STATE set to IMPLEMENT It Pl S e X i iii of Figure 13 4 Viewing Partition Actions in NGDBuild Report Promoting Partitions When synthesis or implementation have completed to your satisfaction you can c
302. e the files that make up the core and to view the properties in the Source File Properties view You can select existing IP cores in the Sources view and use the Re customize IP command from the popup menu to reopen the core in the CORE Generator tool interface and change any of the parameters associated with the core for this project With IP cores added to your project when you run the Synthesize command the PlanAhead tool automatically synthesizes the IP cores in the project first and then synthesizes the top level design For netlist based projects add the generated NGC or EDIF netlist for an IP core using the Add Sources command and specifying Add or Create Design Sources to load the files Using the Xilinx IP Catalog In RTL based projects you can browse the Xilinx IP Catalog to locate and add IP cores to your project The steps involved in using the Xilinx IP Catalog are as follows e Opening the IP Catalog e Customizing IP for the Project e Instantiating IP into the Design Each step is described in the following sections 64 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Managing IP Cores Opening the IP Catalog To open the IP Catalog select Window gt IP Catalog or IP Catalog under the Project Manager or the RTL Design menus in Flow Navigator The IP cores display by category in an expandable tree table that provides the IP version Advanced eXtensible Interface AXI protocol
303. e toned Design State High Available No black boxes were found Estimation Bit Widths High 29 7 of primitives in RTL netlist represent 1 bit logic LUT Macro Types High Available 30 4 of primitives in RTL netlist are bitwise logic and 11 4 are multiplexers Estimation Figure 5 4 Resource Estimation Confidence Level Analyzing Resource Statistics in the Instance Properties view When you select an object in the Resource Estimation view or the RTL Netlist view the Instance Properties view opens for the selected object The Statistics tab of the Instance Properties view displays the estimated device resource requirements for the selected object or the top level module in the RTL view Logic resources are categorized as Arithmetic Comparators Multiplexers Storage and so forth Memory and primitive tables list memories their depth bit width number of ports and macros or primitives by bit width in the chosen level of the hierarchy Figure 5 5 page 181 shows an example of resource estimates for a selected object 180 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX E cpuEngine gt i Elaborating and Analyzing the RTL Design Macro type Bitwise Logic Unary Logic Arithmetic Comparators Multiplexers Shifters Storage Total Child cpu_dbg_dat_i cpu_dbg_dat_o cpu_dwb_dat_i cpu_dwb_dat_o cpu_iwb_adr_o cou imh dat i lt RTL Macro Resources
304. e0 E pblock_usbEngine1 amp Sources DI Netlist Timing Constraints Figure 7 30 Physical Constraints View Selecting a Pblock selects all of the assigned logic for that Pblock Understanding the Physical Constraints View Icons The Physical hierarchy Pblock tree uses several icons that can help you identify the state of the various objects This display updates automatically as you manipulate the physical hierarchy As you create Pblocks they appear in a hierarchical fashion in the Physical Constraints view Each folder type in the Physical Constraints view displays a number in parenthesis that details the number of objects in that folder Each instantiation of an RPM displays in the Physical Constraints view If RPMs are assigned to Pblocks they appear in an RPM folder under the Pblock Selecting an RPM in the Physical Constraints view selects all of the logic contained in the RPM Pblocks With Assigned Instances Pblocks with instances assigned and with rectangles defined in the Device view appear as blue three dimensional cubes with a yellow center as shown in the following snippet H E pblock_RCCInst www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Defining Physical Constraints Pblocks with instances assigned and with no rectangles defined in the Device view appear as blue two dimensional squares with a yellow center as shown in the following snippet pblock_channel
305. eam file is created by the PlanAhead tool a new BMM file is also created called system_stub_bd bmm The PlanAhead tool writes the new BMM file to the same directory as the original BMM file This file can be found in the implementation subdirectory of the embedded processor project These file paths are shown in Figure 3 35 When the correct files are selected click Program to configure the FPGA Using the Project Summary view The PlanAhead tool provides an interactive Project Summary view that details information about the design and the project The Project Summary view updates dynamically as design commands are run and as the design progresses through the design flow The Project Summary displays design information like default part project status state of synthesis and implementation resource estimates and timing results The Project Summary view also provides links to launch commands and to display more detailed information You can use the scroll bar or the Collapse and Expand buttons to view or hide the different data categories You can open the Project Summary using one of these methods e Select Project Summary from the Project Manager menu e Select the Project Summary toolbar button e Select Windows gt Project Summary Figure 3 36 page 80 shows the Project Summary view PlanAhead User Guide www xilinx com 79 UG632 v13 4 January 18 2012 XILINX Chapter 3 Working with Projects Project Settings
306. ect Specify Smdaton Set imam Wd Nae library Location dp_dema_tb tming amy work y CDa PEA _desgnitse implemertedise imolemerted cm sr 2 Nork dp demo twing smy wok Y CaF dgmi _impiementehjse implemented amisi bee dd Fies j AddDrectores Create Fie v Scan and Add ATL Inchade Fies nto Progect lv Copy Sources into Project Figure 3 24 Add Simulation Sources The options are e Specify Simulation Set Specifies the simulation set to which to add files and directories Select the Create Simulation Set command from the pulldown menu to specify a new simulation set e Add Files Invokes a file browser so you can select simulation source files to add to the project e Add Directories Invokes directory browser to add all simulation source files from the selected directories Files in the specified directory with valid source file extensions are added to the project e Library Specify the library for an added file or directory by selecting one from the currently defined library names or specify a new library name by typing in the Library text field Note The Verilog library is the work directory e Create File Invokes the Create Source File dialog box where you can create new simulation source files See Creating RTL Sources page 52 62 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Managing IP Cores e Remove Removes the selected sourc
307. ected to selected top level port Instance TO Port Select top level port connected to selected pad instance D 1 0 Port Package Pin Select top level port assigned to selected package pin P Package Pin TO Port Select package pin to which selected top level port is assigned D 1 0 Port Bus D 1 0 Port Select scalar ports belonging to the selected port bus and vice versa LO Port Interface D I O Port Select all scalar ports and port buses that are assigned to the selected por Clock Region a I O Bank Select all 1 O banks associated with the selected clock region Debug Core Instance Select instance corresponding to the ChipScope debug core D Debug Port Debug Channel Select debug channels that belongs to the ChipScope debug port Debug Channel Net Select net connected to ChipScope debug channel i Instance Debug Core Select ChipScope debug core corresponding to Instance Shortcuts Ph Schematic 38 Strategies A KS ES KS KS ES ES ES ES S KS SYS SS ES ES KS Figure 4 27 PlanAhead Options Selection Rules The default selection rules enable the PlanAhead tool to operate in the most efficient manner You can change these selection rules when you are having trouble selecting a specific object To enable or disable automatic selections click the Set column heading e Enabling a selection rule causes the PlanAhead tool to select the secondary To object types that are associated with
308. ecting Nets to Debug Cores in Chapter 12 Understanding the Netlist View Icons Various icons are used to represent the state of netlist logic as shown in Figure 4 62 and described in the following subsections E Hierarchical instance logic E Hierarchical instance black box Hierarchical instance black box Pblock Z Hierarchical instance Pblock E Partitioned instance logic Partitioned instance black box Partitioned instance Pblock Partitioned instance black box Pblock amp Bus Net Primitive instance Primitive instance fixed with LOC Figure 4 62 Netlist View Icons Hierarchical Instances Hierarchical netlist modules or instances are displayed with a yellow I icons as shown in the following figure 2 LED decode SegDispCk_49_123 j B receiver RCY_802_11 Hierarchical Instances Assigned to Pblocks Hierarchical netlist modules or instances are assigned to Pblocks are displayed with blue checkmark icons as shown in the following figure E busMuxwrapInst busMuxwrap Black Box Modules Hierarchical instances that do not have netlists or logic content are viewed by the PlanAhead tool as black boxes These are identified with a hierarchical instance icon with a dark background as shown in the following figure A hierarchical instance may be a black box by design or may be the result of bad a search path or missing files E CONVDECOD vit
309. ed Block RAM and DSP components e Criteria For each object type a different set of search parameters are available in the dialog box Inthe first field select the attribute to use to search for objects For example Name Status Type Parent Pblock Module or Primitive count The values in this field depend on the object type in the Find field Inthe second field you can define search criteria such as matches does not match contains and does not contain Use the third field to define the value of the attribute based on the search criteria You can use the asterisk as wildcards in search strings Optionally click the button to define additional search criteria A new row of search criteria fields display in the Find dialog box An AND OR field displays where you can define the additional search criteria as shown in Figure 4 32 page 117 New search criteria are added parenthetically with prior search criteria to define the Find query The first two search criteria are grouped together and nested as each new search criteria is added Adding multiple search criteria results in grouping them as follows eritl OP crit2 OP crit3 OP critN Where www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX 7 Using the Find Commands e critt1 is the first search criteria e critN is the last search criteria e OP is the boolean AND or OR operation defining the relationship betw
310. ed with the ISE Simulation tool ISim Xilinx Sim is a Hardware Description Language HDL simulator that lets you perform behavioral and timing simulations for VHDL Verilog and mixed VHDL Verilog designs To launch ISim select e Tools gt Simulation gt Timing Simulation on an Implemented Design or e Timing Simulation from the Flow Navigator The PlanAhead tool opens the Launch Timing Simulation dialog box as shown in Figure 11 20 G Launch Timing Simulation i Launch Sim Simulator using an existing simulation source set or a new simulation set Settings Simulation Set E sim4 Simulation Top Module Name Hrp_demo_tb Figure 11 20 Launch Timing Simulation The fields are e Simulation Set Specify the name of the simulation run This lets you create different simulation runs with different design hierarchies and different options e Simulation Top Module Name Specify the top level of the design The PlanAhead tool automatically populates this field with the defined top module but you can specify a different top module simulate from different levels of the hierarchy or to elaborate different variations of the design e Options Opens the Simulation Options dialog to define runtime options for the ISim tool See Specifying Simulation Options for more information e Launch Runs the ISim compile and elaboration steps and launches ISim in GUI mode e Cancel Closes the dialog box without launching
311. een the search criteria Find Instances Criteria Type li v Block Memory v Type is v Distributed Memory Name matches X usbEngine C Match Case Open in a new tab Figure 4 32 Searching for Objects with Additional Search Criteria The query defined in Figure 4 32 should be read as Find Instances where Type is Block Memory OR Type is Distributed Memory AND Name matches usbEngine This query finds all block memories and distributed memories in the design and then filters the list to return only those named usbEngine Click the or X button to add or remove search criteria rows Click the Match Case checkbox to make all search criteria case sensitive Enable or disable the Open in a new tab checkbox to have the results open a new tab in the Find Results view or replace existing results Click OK to perform the search The combined search results are discussed in Using the Find Results View Using the Find Results View The objects matching the search criteria defined in the Find dialog box display in the Find Results view after you click OK Figure 4 33 page 118 shows the Find Results view PlanAhead User Guide www xilinx com 117 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX Id 66 67 bala G 69 70 1G 71 72 G 73 G 74 G 75 G 76 G 77 Name usbEngineO usbEngineSRAM Mram_snoopyRam29 usbEngine 1 usbEngineS
312. els from the design and per pin package data through the Export IBIS Model command The www xilinx com 281 UG632 v13 4 January 18 2012 282 Chapter 8 O Pin Planning XILINX PlanAhead tool uses the netlist and implementation details from the design and combines that information with the available per pin parasitic package information to create a custom IBIS model for the design With an RTL Design Netlist Design or Implemented Design open you can export an IBIS file for use in analyzing the design Select File gt Export gt Export IBIS Model The Export IBIS Model dialog box opens as shown in Figure 8 30 G Export IBIS Model i Export a model to use with IBIS aware simulation tools Output File project_cpu_hdl xc 20010 ibs Options C Disable per pin modeling Maximum length of signal names 40 Updated generic IBIS models File e Updated parasitic package data file e Figure 8 30 Export IBIS Model Dialog Box The Export IBIS Model options are Output File Specify the filename and path for the output IBIS file e Include all models Checkbox to include all available I O buffer models for this device By default only buffer models used in the design are included e Disable per pin modeling Checkbox to disable inclusion of the per pin modeling of the package This is the path from the die pad of the device to the pin of the package With per pin modeling disabled the package
313. ement from another view To open a Schematic view 1 Select at least one object to display in schematic format in the Netlist view for instance 2 Select the Schematic command from the popup menu e Press F4 or e Click the Schematic toolbar button Dei The Schematic displays in the workspace You can open multiple Schematic views in the workspace www xilinx com 103 UG632 v13 4 January 18 2012 104 Chapter 4 Using the Viewing Environment XILINX Using the World View When zoomed in on a graphical workspace view such as the Device view you can open the World view to navigate around the overall design area The World view displays a less detailed overview of the active graphical workspace to enable a quick pan of the viewed area This capability is available in the Device view Schematic view Package view and Hierarchy view when you are zoomed into a small region of the device or design To invoke the World view click the World view icon in the lower right hand corner of a graphical workspace view such as the Device view as shown in Figure 4 15 Show World View Figure 4 15 World View The World view reflects the zoom area and the selected objects for the active view In Figure 4 16 the world view shows the overall Device view which is currently zoomed into the area identified by the navigation rectangle in the World view You can select and drag the navigation rectangle to reposition the displayed area
314. ementation Run Properties view for a selected run impl_1 Part xc vix7StfF784 3 active Description jse Defaults including packing re Status PAR Complete Synthesis Run gt Y synth_1 Constraints constrs_1 Run Directory C Plan4head_Projects Plan4head_Tutorial_13 3 Projects project_bft_core_hdl project_bFt_core_hdl runs impl_1 General Options Monitor Reports Messages Partitions Figure 4 58 Implementation Run Properties View As you select runs in the Design Runs view the properties of the run appear in the Run Properties view under one of the tabs The General tab reports the configuration of the run including the target part the constraint set the parent run the run strategy and the run directory where output files for the run are or will be written Table 4 1 page 147 provides details of each of the tabs of the Run Properties view The properties reported in the Run Properties view can be changed directly in the view if the run has not been launched However once a run has been synthesized or implemented the run properties are locked to the currently selected properties and cannot be changed unless the run is reset To reset a run use the Reset Runs command from the Design Runs view popup menu See Using the Design Runs View in Chapter 9 for more information www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using Common Views Table 4 1 Tabs of the Run Pr
315. en_fifo18_36 fofifo18_36 Fblkfinst_few k1 3 101 3 101 Data Path Delay Type FIFO36_EXP net fo 40 LUT6 net fo 42 LUT6 net fo 4 RAMB1S Total Cumulative Location PBlock Logical Resource 0 818 0 818 E RAMB36_X2 1 pblock_usbEngineO lt usbEngineO usb_dma_wb_in BU2 U0 gen_fifo18_36 fafifo18_36 Fblkjinst_few k1 1 1 520 2 338 E SLICE_X19 8 pblock_usbEngine0 D usbEngineO u2 wsel 10 0 094 2 432 E SLICE_X19 8 pblock_usbEngine0 lt usbEngineO u2 wsel o 0 381 2 813 E SLICE_X18 9 pblock_usbEngineO D usbEngineOju2 sram_we I4 0 094 2 907 E SLICE_X18Y9 pblock_usbEngineO J usbEngineO u2 sram_we O 0 430 3 337 E RAMB36_X1Y1 pblock_usbEngine0 D usbEngine0 usbEngineSRAM BU2 UO blk_mem_generator valid cstr ramloop 0 ram 3 961 E RAMB36_X1 1 pblock_usbEngine0 G usbEngineO usbEngineSRAM BU2 U0 blk_mem_generator valid cstr ramloop O ram 3 961 Destination Clock Path Delay Type net fo 0 IBUFG net fo 1 BUFG net Fo 407 Total Delay Cumulative Location Logical Resource 0 000 E 4B19 D usbClk 0 000 E AB19 D usbClk_ibuf ibufg T 0 818 E AB19 GusbClk_ibuffibufg o 0 818 E BUFGCTRL_X0Y9 D usbClk_ibuF buFg T 1 068 E BUFGCTRL_X0Y9 usbCik_ibuf bufg O 3 101 E RAMB36_x1Y1 pblock_usbEngine0 D usbEngineO usbEngineSRAM BU2 U0 blk_mem_generator valid cstr ramloop 0 ran 3 101 lt gt General Report Instances Options Figure 7 19 Path Properties View Report Ta
316. enu that displays when you press and hold the right mouse button You can add view or modify source files using the Sources view toolbar and popup menu commands Sources View Toolbar Menu The toolbar menu as shown in Figure 4 39 contains the following commands PlanAhead User Guide www xilinx com 123 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX Show Search Opens the Search bar to allow you to quickly locate objects in the Sources view This command is also accessed through the Alt keyboard shortcut Expand all Expands all hierarchical tree objects to see all elements of the Sources view Collapse all Collapses the hierarchical tree objects to display only the top level objects ie H Open Selected Source Files Opens the selected files in the text editor For information on using the features in the Text Editor refer to Using the Text Editor in Chapter 5 Add Sources Lets you add or create RTL source files simulation source files Constraint files or add existing IP to the project Group Sources by Library and File Type Displays the source files grouped by type or displays the source file in sequential order Automatically Scroll to Selected Object Causes the Sources view to update to focus on the currently selected object This can be useful on large designs with many source files This feature is on by default Sources View Popup Menu The So
317. er Transfer Level RTL source versions e Synthesis options e Implementation options e Constraints The PlanAhead tool also allows multiple synthesis and implementation runs using varied e Software command options e Timing constraints e Physical constraints You can queue the synthesis and implementation runs to launch sequentially or simultaneously with multi processor computers Synthesis runs use Xilinx Synthesis Technology XST You can create and save strategies which are sets of option configurations for each implementation command The strategies are then applied to runs for synthesis or implementation using Xilinx ISE Design Suite tools For more information see Defining Strategies for Synthesis and Implementation in Chapter 4 Using the Viewing Environment Running Implementation When you run implementation in the PlanAhead tool you can e Set implementation options e Run implementation e View the results of the run Setting Implementation Options There are several locations in the environment in which to configure implementation settings e Select the Project Settings command in the Flow Navigator Project Manager Menu e Select the Project Settings button in the main toolbar es e Select the Implementation link in the Project Summary view PlanAhead User Guide www xilinx com 291 UG632 v13 4 January 18 2012 Chapter 9 Implementing the Design g XILINX 292 When the Project Settings dialog
318. erarchical structure of the design relative to the created Pblocks The physical hierarchy is dynamic expanding and changing automatically as you manipulate the physical hierarchy As objects are selected in other views the appropriate elements are highlighted in the Physical Constraints view www xilinx com 245 UG632 v13 4 January 18 2012 246 Chapter 7 Netlist Analysis and Constraint Definition XILINX The objects that display in the Physical Constraints view are Relatively Placed Macros RPMs and Physical Block Pblocks and DCI Cascade Constraints You can select these objects in the Physical Constraints view for manipulation in other views Any physical constraints that you add to the design are saved when you select e File gt Save Design or e File gt Save Design As You are prompted to save any unsaved design changes if you close the project without saving If you have a design with multiple constraint sets or multiple constraint files be aware that any added constraints are written to the active constraint set and the target constraint file Using the ROOT Design Pblock The physical hierarchy begins with the design name followed by the top level Pblock called ROOT As you create lower level Pblocks they display in a hierarchical fashion under the Pblock folder with Child Pblocks nested under their parent Pblock shown in Figure 7 30 page 246 5 netlist_1 E ROOT 5 pblock_usbEngin
319. erarchy up from the selected instance e This command has no effect if the selected instance is at the top level of the design hierarchy e Use Collapse Outside to hide the expanded hierarchy outside the selected instance Double click a pin of an instance to expand to the next primitive logic elements on a net e Double click the pin inside a symbol to expand the net into the hierarchy e Double click the pin outside a symbol to expand the net outward Expand buses to include all bits of the bus Buses show as thick wires www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using Common Views e Use the Expand Cone command from the popup menu to expand the cone of logic from a selected pin or instance or between two selected instances The available Expand Cone options as shown in Figure 4 50 are e To Flops Appends the view to display the entire cone of logic to the first flops or to any sequential element such as block RAMs FIFOs and embedded processors e To Primitives Appends the view to display the entire cone of output logic to the first primitives This is also the default behavior when you double click a pin e To I Os Appends the view to display the entire cone of output logic to the I Os This can involve a large amount of logic The PlanAhead tool sends a warning and lets you cancel the command if more than 10 levels of logic are to be appended e Between selected insta
320. erbi 150 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using Common Views Partition Modules Modules that have been set as Partitions using the Set Partition popup menu command See Chapter 13 Using Hierarchical Design Techniques for more information on using design partitions W E wbArbEngine wb_conmax_top Partial Reconfiguration Partition Modules Modules that have been set as Reconfigurable Partitions using the Set Partition menu command in a Partial Reconfiguration project D usbEngine1 usbEngine1 usbf_top Primitive Logic Instances Primitive logic instances display as follows e Without placement constraints assigned display as an i inside a yellow rectangle e With placement constraints assigned display a yellow rectangle with a blue stripe e Assigned to a Pblock display a blue checkmark inside a yellow rectangle e Placed and assigned to a Pblock display a checkmark and blue stripe in a yellow rectangle Notice the logic types display also as shown in the following figure dataOut_h 0 FDE dataOut_h 1 FDE dataOut_h 2 FDE dataOut_h 3 FDRE Using the Hierarchy View PlanAhead User Guide The Hierarchy view lets you visualize the logic hierarchy You can see the relationship between selected modules as well as their relative sizes This view is used primarily during design analysis and floorplanning It lets you see how a timing path traver
321. ering the endpoints based on a specific slack value a histogram can be generated to focus on the problematic paths The fields in this area are as follows Greater Than Specifies the minimum slack value that a path can have to be included in the histogram Less Than Specifies the maximum slack value that a path can have to be included in the histogram e Bin Display Allows further customization of the histogram This field contains the following values Number of Bins Specifies the number of bins to display in the histogram The range of slack values PlanAhead finds is divided into the number of bins specified By selecting a smaller number of bins the histogram provides a general view of the timing performance of the design A larger number of bins is best used within a slack range to better enable focus on the performance of a specific range of delays Significant Digits Specifies the number of significant digits to use in reporting slack values By default this value is set to 3 Plot on Log10 scale Specifies whether to draw the resulting slack histogram with the Y axis on a logarithmic or linear scale Log scale is useful when there are delay bins that are very small relative to other larger bins and consequently difficult to see clearly with a linear scale This setting can be also controlled through the Plot Histogram on Log10 Scale command in the toolbar after the histogram has been drawn e Command C
322. errors and ISE map errors e Clock Report Clock signals Local Global and Resource contained in the Pblock as well as the number of clocked instances on each clock e RPM Statistics The number of Relatively Placed Macros RPM objects assigned to the Pblock It also displays the tallest and widest RPM assigned to the Pblock and the percentage of its size in relation to the Pblock size Note RPM utilization values over 100 causes PlanAhead DRC errors and ISE map errors PlanAhead does not indicate whether multiple RPMs can fit inside the Pblock rectangle e Clock Region Statistics The utilization percentage of each clock region that the Pblock overlaps e Primitive Statistics The number of each type of logical resource assigned to the Pblock Note You can save the contents to a text file by clicking on the Export Statistics icon Instances Displays information about the instances contained in the Pblock You can select the instance fields and use them to seed many popup menu commands Rectangles Displays information about the various rectangles created for the Pblock The Rectangle tab is used for selecting rectangles of a Pblock Refer to the Using Non Rectangular Pblocks page 324 Attributes Lets you define Attribute properties to a Pblock See Setting Attributes for Pblocks page 326 318 Note To accept changes click Apply to cancel changes click Cancel Selecting another item or clos
323. es For more information see Setting Device Configuration Modes page 258 www xilinx com 257 UG632 v13 4 January 18 2012 Chapter 8 VO Pin Planning g XILINX When you set the device configuration mode the pin definition of the multifunction pin displays in the Config column of the Package Pins view Defining Alternate Compatible Parts The PlanAhead tool lets you select compatible devices for the design to allow you to retarget the design to alternate Xilinx FPGAs if necessary Set Part Compatibility checks that I O pin assignments are defined to work across selected alternate devices Compatible Xilinx devices are selected in the same package as the current target part to preserve as much of the I O assignment as possible To define an alternate compatible part 1 Select Tools gt IO Planning gt Set Part Compatibility The command locates alternate parts available in the same package as the current default part Compatible devices available in the same package display in a list as shown in Figure 8 7 G Set Part Compatibility i Add and or remove PROHIBIT constraints to package pins such that device is compatible with all selected parts Compatible Parts C xc6vlx130tff784 C xc6vix195tFf784 C xc vix240tff784 i Cancel Figure 8 7 Select Alternate Compatible Parts 2 Select the alternate parts The PlanAhead tool identifies the pins that are common to all selected alternate parts
324. es command and click Create File The Create Source File dialog opens in which you can define the type name and location of the new source file you are creating as shown in Figure 3 4 page 39 38 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Creating a New Project G Create Source File e J Create a new source file and add it to your project File type name amp location File type Verilog File name File location 6 lt Local to Project gt Figure 3 4 Create Source File Dialog Box 1 You can define the following information in the Create Source File dialog box e File type Select one of the following file types Verilog Create a Verilog format file v Verilog Header Create a Verilog Header format file vh VHDL Create a VHDL format file vhd1 e File name Enter a name for the new HDL source file e File location Designate a location to create the file 2 Click OK A placeholder for the file is added to the list of sources The file itself is created when you click Finish 3 You can repeat the Create File command multiple times to define a number of new modules to add to the project 4 Inthe Add Sources dialog box specify the appropriate Library for the source file By default sources are added to the work library 5 Click Finish to add the specified sources to the project e If you have used Create Files the Define Modules dia
325. es view Expand all Expands all hierarchical tree objects to see all elements of the Sources ma view PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 2 r g EE 145 146 Chapter 4 Using the Viewing Environment g XILINX Collapse all Collapses the hierarchical tree objects to display only the top level objects Group by type Groups the selected items by type By Delete Deletes an attribute or object from within one of the tabs of the Properties x view This command is only available for certain object types and in specific view panes Export statistics to file Saves data to the specified file for later use Available from the Statistics tab of the Pblock Clock Region and Instance Properties view only LJ Show unsaved attributes only Displays only the unsaved attributes on the m Attributes tab of the Properties view These are the attributes that have been updated and will be saved when the Apply command is used Add pre defined attributes Adds a new attribute to the selected object This dh command is only available for certain object types and in specific view panes Using the Run Properties View The Run Properties view which is one form of the Properties view displays information about a selected synthesis or implementation run Accordingly it is labelled the Synthesis Run Properties view or the Implementation Run Properties view Figure 4 58 shows the Impl
326. esign source for synthesis and simulation or an RTL test bench for simulation only PlanAhead User Guide www xilinx com 51 UG632 v13 4 January 18 2012 52 Chapter 3 Working with Projects XILINX Create File Invokes the Create Source File dialog box where you can create new VHDL Verilog or Verilog Header files See Creating RTL Sources page 52 for more information Delete Removes the selected source files from the list of files to be added Move Selected File Up Moves the file or directory up in the list order The order of the files affects the order of elaboration and compilation during downstream processes such as synthesis and simulation Move Selected File Down Moves the file or directory down in the list order Scan and Add RTL Include Files into Project Scans the added RTL files and adds any referenced Verilog include files Copy Sources into Project Copies the original source files into the project and uses the local copied version of the file in the project If you added directories or source files with Add Directories the directory structure is maintained when the files are copied locally into the project For a complete discussion of this topic refer to Using Remote Sources or Copying Sources into Project page 55 Add Sources from Subdirectories Adds source files from the subdirectories of directories specified using the Add Directories option Creating RTL Sources To creat
327. est Practice for scripting language Tcl lets you perform interactive queries to design tools in addition to executing automated scripts Tcl offers the ability to ask questions interactively of design databases particularly around tool and design settings and state Examples are querying specific timing analysis reporting commands live applying incremental constraints and performing queries immediately after to verify expected behavior without re running any tool steps The following sections describe some of the basic capabilities of Tcl with PlanAhead For specific information about each command consult the online help for the individual command The Tcl Command Reference Guide UG789 as cited in Appendix E Additional Resources lists and describes the PlanAhead Tcl commands Tcl Journal Files Tcl Help PlanAhead User Guide When you invoke the PlanAhead tool it writes the PlanAhead 1og file to record the various command and operations performed during the design session The PlanAhead tool also writes a file called PlanAhead jou which is a journal of just the Tcl commands run during the session that can be used as a source to create new Tcl scripts Note One backup version of this file called planahead jou_backup is written to save the details of the previous run Refer to Appendix A PlanAhead Input and Output Files for information regarding the location of these files The Tcl help command provides information
328. ew Banner The view banner reflects the design name constraint set and target part as shown in Figure 2 8 RTL Design rtl_1 xc6vix75tff784 3 active RTL Netlist E Project Summary X Device x a peg PE 8 as Project Settings Bbft r a H Nets 1891 a Project Name project bft_core_hdl SLL INdtie Uem uM Lure iui Figure 2 8 Design View Banner As source files are updated a banner appears at the top of the open RTL Designs indicating that a newer version of the design data is available You are prompted to reload what is loaded in memory Using the Design is Out of Date and Reload Banner In the course of any design process source files often require modification The PlanAhead tool manages the dependencies of these files and indicates when the displayed design data is out of date Changing project settings can also trigger an out of date status on a project As source files netlists or implementation results update a banner opens at the top of any open designs indicating that a newer version of the data is available than the data currently loaded in memory The software prompts you to reload the in memory view of the design To refresh the in memory data click Reload Figure 2 9 shows the out of date banner D Netlist Design is out of date Constraints were modified more Reload Close Design Out of date Details oo ll Q Files New H a egressLoop 6 eqressFifo FifoBurfer_NO _ear
329. expressions Filter Matching Name with Expression An SDC syntax option that specifies the filter command e Ignore Command Errors Suppresses warning messages generated during Tcl command processing of the timing report e Find Command button for launching a search based on the defined expression e Find Results Contains the results of the object search Move Item to the Right Moves the currently selected object from the Find Results column to the Selected Names column Move Item to the Left Moves the currently selected object from the Selected Names column to the Find Results column Move All Items to the Right Moves items from the Find Results column to the Selected Names column Move All Items to the Left Moves items from the Selected Names column back to the Find Results column e Selected Name Contains the subset of the search result objects that are chosen for Start Points Through Points or End Points e Command Contains the Tcl command used to represent the selected objects Understanding the Options Tab The Options tab of the Report Timing dialog box contains fields to specify the type of timing report to be generated as well as the number of paths reported The Options tab is shown in Figure 7 14 page 224 PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 223 Chapter 7 Netlist Analysis and Constraint Definition g XILINX 224 G Report Timing
330. ext editor for editing See Using the Text Editor in Chapter 4 for information on editing the newly created file Specifying the Top Module and Reordering Source Files The PlanAhead tool automatically determines the top level of the design hierarchy and the order of elaboration synthesis and simulation for source files added to the project The hierarchy of the design is displayed in the Hierarchy tab of the Source view The file order is displayed in the Compile Order tab of the Sources view See Using the Sources View in Chapter 4 for more information With a group of RTL files added to the project you can also manually specify the top level of the design hierarchy To define the top module from within the Sources view you can use the Set as Top popup menu command The PlanAhead tool automatically reorders files according to the requirements of the new top module You can also manually order files according to your own requirements Use the Update Hierarchy setting in the Sources view to automatically reorder files based on updates to the source files To manually re order source files from within the Sources view select a file and drag it up or down in the file list order Alternatively after selecting the file execute Move Up Move Down Move to Top or Move to Bottom from the Sources view popup menu Enabling or Disabling Source Files When you add or create source files those files are enabled in the Sources view by default
331. f signals they contain The Tools gt Options gt General dialog box contains connectivity display options One option is to display the Net Bundles as a Mesh or ina Tree pattern You can also traverse the hierarchy and create submodules for the larger top level instances to gain more detailed granularity This top level floorplan can be an indicator of the I O pinout configuration quality and can help identify potential routing congestion issues Also examining resource statistics and clock requirements for each module can aid in understanding potential placement issues For more information see the Floorplanning Methodology Guide UG633 cited in Appendix E Additional Resources Inserting ChipScope Debug Cores PlanAhead User Guide The PlanAhead tool lets you insert and configure ChipScope Integrated Logic Analyzer ILA and Integrated ChipScope Onboard Netlist ICON debug cores into the Netlist Design You can select debug nets and configure cores using the Set Up ChipScope wizard The added ChipScope cores are preserved though through netlist iterations The ChipScope netlist overlay reconnects with the selected debug nets after you add a new netlist and open it in a project The PlanAhead tool sends a warning if it finds any www xilinx com 215 UG632 v13 4 January 18 2012 Chapter 7 Netlist Analysis and Constraint Definition g XILINX discrepancies For more information on inserting debug logic and debugging wi
332. f the timing constraints defined in the design Constraints are constraint set specific and can vary between open designs within the same project You can experiment with different constraints devices I O pins and so forth You can modify defined values and create new constraints in the Timing Constraints view To view the timing constraints defined in the design click the Timing Constraints tab or select Window gt Timing Constraints The Timing Constraints view opens as shown in Figure 7 10 All Constraints Clk period PERIOD 6 Basic period 0 Timespec period 6 amp TIMESPEC TS_cpuClk PERIOD cpuClk 13 ns A IMESPEC TS_wbClk PERIOD wbClk 9 ns amp TIMESPEC TS_usbClk PERIOD usbClk 5 25 ns amp TIMESPEC TS_phy_clk_pad_0_i PERIOD phy_clk_pad_0_i 11 ns amp TIMESPEC TS_phy_clk_pad_1_i PERIOD phy_clk_pad_1_i 11 ns amp TIMESPEC TS_fftCik PERIOD FftClk 7 5 ns Derived period 0 H Pad clk offset OFFSET 0 __ Path delay FROM TO 2 UCF TIMESPEC TS_wbClk PERIOD wbCIk 9 ns x db BP Br x Timespec name T5_wbClk Period Specification Period 15 C Duty Cycle Group wbcik C Input jitter a a C Priority fi oo Source C Plan4head_Install plandheaditestcases Plan4head_Tutorial Projects project_cpu_hdl project_cpu_hdl srcs constrs_1 imports Soure j E Figure 7 10 Timing Constraints view
333. fied sources to the project If you have used Create Files the Define Modules dialog box opens as discussed in Defining New Modules page 53 Defining New Modules If you have specified new RTL source files to add to the project you will need to write the Verilog or VHDL code to define the module The PlanAhead tool provides the Define Modules dialog box to facilitate creating new RTL code as shown in Figure 3 17 G Define Modules e 1 Specify I O Ports to add to your source files For each port specified MSB and LSB values will be ignored unless its Bus column is checked Ports with blank names will not be written New Source Files Module Definition gpu vhd Entity name gpu mimo vhd divGen v Architecture name Behavioral I O Port Definitions Port Name Direction Bus id_Clk_In Vid_Clk_Out H_sync _sync AWADDR ARADDR lt JHOOOO Figure 3 17 Define Modules Dialog Box 1 The Define Modules dialog is populated with the new source files that were defined by the Create File command as described under Creating RTL Sources page 52 Both Verilog and VHDL modules can be defined in this form Start by selecting a specific module to define from the list of New Source Files The following information can be provided in the Define Modules dialog box to speed RTL coding e Entity name Module name Specify the name for the entity construct in the VHDL code or the module name in the
334. file that instantiates the embedded system There are two ways to use this file 1 Add this file to your PlanAhead project as the top level HDL file 2 Use this file as a template to copy the embedded systems instantiation from this file and include it in your own top level HDL file As mentioned previously system_stub vhd or system_stub v is the file containing the instantiation template This file contains the component declaration and instantiation template The following is a VHDL example of the component declaration component system is port RESET in std_logic CLK_P in std_logic CLK_N in std_logic DIP_Switches_4Bits_TRI_TI in std_logic_vector 0 to 3 thernet_Lite_MDIO inout std_logic thernet_Lite_MDC out std_logic thernet_Lite_TX_ER out std_logic thernet_Lite_TXD out std_logic_vector 3 downto 0 thernet_Lite_TX_EN out std_logic thernet_Lite_TX_CLK in std_logic thernet_Lite_COL in std_logic hernet_Lite_RXD in std_logic_vector 3 downto 0 hernet_Lite_RX_ER in std_logic hernet_Lite_RX_CLK in std_logic hernet_Lite_CRS in std_logic hernet_Lite_RX_DV in std_logic hernet_Lite_PHY_RST_N out std_logic HEA ARPA d a a d d a a 2 1 It is recommended to add the embedded processor system into the top level of the HDL design However it is possible to instantiate the component lower in the hierarchy with some changes to the following steps
335. fine how many levels of hierarchy to report with estimates listed for each module at each level To export a resource statistics report 1 Select the Export Statistics button to export the data to a spreadsheet file The Export Netlist Statistics dialog box opens as shown in Figure 7 7 O Export Netlist Statistics Netlist DI top File Name ts Plandhead_XDC Projectstproject_cpu_hdlttop_stats txt Format Text OXML Oc Levels Lie Reports to Generate Primitive Statistics Clock Report Carry Statistics Net Boundary Statistics Set All Clear All Figure 7 7 Export Netlist Resource Statistics The Export Netlist Statistics dialog box options are e File Name Enter the name and location of the spreadsheet file to be created e Format Select the format of the output file Text XML or CSV e Levels Indicate the number of levels of hierarchy to traverse and include in the report as separated modules e Reports to Generate Define the types of netlist statistics to include in the output report file 2 Select the options for the exported file and click OK PlanAhead User Guide www xilinx com 213 UG632 v13 4 January 18 2012 Chapter 7 Netlist Analysis and Constraint Definition XILINX Exploring the Logic The PlanAhead tool provides several perspectives in which to analyze design logic e The Netlist and Hierarchy views contain a navigable hierarchical tree style view
336. fix the placement of any unfixed instances to prevent reassignment during subsequent implementation runs by using the Fix Instances or Fix Ports command in the Device Package or Schematic view Refer to Working with Placement LOC and BEL Constraints page 329 for more information Note ISE can optimize and change logic to improve placement and routing results When this happens logic in the original netlist is removed or replaced This results in a mismatch between the pre Implementation netlist opened in the PlanAhead tool and the Implementation results The Tcl console reports these discrepancies as the Implemented Design is opened It does not pose any problems other than the logic in the netlist does not match the viewed results exactly PlanAhead User Guide www xilinx com 343 UG632 v13 4 January 18 2012 Chapter 11 Analyzing Implementation Results g XILINX Opening Multiple Implemented Designs You can open any implementation run by one of the following options e Select an implementation run in the Design Runs view and use Open Implemented Design or double click the implementation run e Set the run as the active run then click Flow Navigator gt Implemented Design Refer to Setting the Active Run page 303 e Open multiple implementation runs if they were launched from the PlanAhead tool Tabs display in the upper left corner of the viewing environment to enable switching between open implemented designs as shown in Fi
337. for selecting a synthesis strategy and for setting synthesis command line options The command line options are defined by the selected synthesis strategy but you can override these with your own selections A description of the selected command line option displays at the bottom of the dialog box Implementation Shows the Default Part and Default Constraints Set and provides an Options area for selecting an implementation strategy and for setting command line options for the translate MAP PAR and timing analysis steps that occur during Implementation The command line options are defined by the selected implementation strategy You can override the setting with your own selections A description of the selected command line option displays at the bottom of the dialog box IP Catalog Shows the IP Catalog location and the HDL type This dialog box is described in detail in Adding Existing IP Cores page 63 General Project Settings Figure 3 40 page 83 shows the General Project Settings with the Language options dialog box 84 Name Displays the project name Project Part Defines the target part to be used as a default for both synthesis and implementation Select the browser button to invoke the Part Selector dialog box to choose another part See Selecting a Default Part page 42 for more information on setting the target part The Project Part allows you to quickly define or change the target device for the whole p
338. fter Implementation page 300 e For more information on customizing IP see Managing IP Cores page 63 PlanAhead User Guide www xilinx com 25 UG632 v13 4 January 18 2012 Chapter 2 The PlanAhead Tool Flow XILINX The Project Manager Flow Navigator menu contains the following commands e Project Settings Opens the Project Settings dialog box Refer to Setting Command Options page 26 for more information e Add Sources Invokes the Add Sources dialog box Refer to Managing Project Sources page 50 e IP Catalog Opens the IP Catalog view Refer to Using the Xilinx IP Catalog page 64 e Elaborate Elaborates the RTL design and displays messages in the Elaboration Messages view Refer to Elaborating and Analyzing the RTL Design page 176 e Behavioral Simulation Launches ISim to perform a behavioral simulation on the RTL design Refer to Performing Behavioral Simulation page 188 e Project Summary Displays the Project Summary view For more information on the Project Summary view refer to Selecting the Step After Implementation page 300 Setting Command Options To set synthesis and implementation options click Project Settings in the Project Manager or from the main toolbar fat These options are also available from pulldown menus by clicking Synthesis and Implementation in the Flow Navigator For more information see e Chapter 6 Synthesizing the Design e Chapter 9 Implementing the Desig
339. ful it is critical for you to setup the linker script associated with the C C project to locate the application code in the block RAM 1 Inthe PlanAhead tool select Program and Debug from the Flow Navigator and then select Generate Bitstream The Generate Bitstream dialog box opens allowing you to specify BitGen options as shown in Figure 3 34 page 78 www xilinx com 77 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects XILINX fe Generate Bitstream os Create a programming bit file for the design Use IMPACT to program the FPGA device or generate a PROM programming file from the generated bitstream l More Options g ql bd Update BlockRAM contents with data from file lt memfile gt Ca ioe Figure 3 34 Generate Bitstream 2 Select the pulldown arrow next to the bd option The bd option updates the bitstream with the block Ram content from the specified ELF or MEM file Selecting this option in the options dialog opens a file browser to select the executable file to include in the block RAM 3 Select OK The bit file created by PlanAhead now has the block RAM initialized with the selected executable code The Software Development Kit SDK enables the download and configuration of the FPGA However care must be taken to ensure that the correct bitstream and BMM files are being used in this process Note SDK also provides this functionality to debug and or load your code In
340. fy Types to Generate csy Cc Data Plandhead_Designs Plandhead_Tutorialilabs projects project_7ifloorplan_1 csv i UCF C Data Plandhead_Designs PlanAhead_Tutorialilabs projects project_7ifloorplan_1 suc V Verilog C DatalPlandhead_Designs Plandhead_Tutorialilabs projects project_7 netlist_1_EMPTY vf ia C Data Planahead_Designs PlanAhead_Tutorialilabs projects project_7 netlist_1 EMPTY vhdl les Figure 8 29 Exporting I O Port Lists You can specify the type of I O port to generate and the path The I O port type options are CSV UCF Verilog and VHDL When you output a I O port list to a UCF the IOSTANDARD constraints for the ports are also output to the file This includes both any user defined IOSTANDARD constraints and the default assigned IOSTANDARD Exporting IBIS Models PlanAhead User Guide To better understand the signal integrity at the system level PCB designers often need to simulate the design with I O Buffer Information Specification IBIS models Designers must consider signal integrity issues such cross talk ground bounce and Simultaneous Switching Noise SSN IBIS models help characterize I V curves and parasitic information of the packaged device Xilinx provides generic IBIS models for complete device families that can be downloaded from the website http www xilinx com support download For Xilinx 7 series FPGAs the PlanAhead software can generate IBIS mod
341. g Implementation Implemented Design RTL Flow Netlist Flow Programming Debug Figure 2 1 PlanAhead Design Flows X12117 Project Creation and Management of Project Sources The PlanAhead tool provides a wizard flow to facilitate project creation and the creation or addition of source files to the project You can Create projects specific to the type of flow and sources you are using Create new source files or add existing source files to the project Reference remote write protected files or copy files into the local project folder Disable or enable source files within a project Create constraint sets to experiment with various constraints options or devices Create simulation source sets for behavioral and timing simulation Archive projects to create a backup or make a portable copy of the design The PlanAhead tool project environment lets you create and store multiple variations of the design constraints within a single project This allows for the creation of multiple RTL source versions constraints sets target devices synthesized netlists and implementation run results using various implementation strategies As you modify the source files or launch design tools the software monitors and displays design flow status RTL Development and Analysis The PlanAhead tool includes an integrated text editor to create or modify source files You can copy example logic constructs directly from the supplied Xilinx templat
342. g ISim When you select the Options button the PlanAhead tool opens the Simulation Options dialog box which includes two option tabs Launch Options and Language Options The following subsections describe these options Specifying Simulation Options When you select the Options button the PlanAhead tool opens the Simulation Options form This form includes the previously specified top level module and two option tabs Launch Options Specify command line options for the fuse compiler and the ISim tool Language Options Specify details of the Verilog or VHDL language used by the simulation netlist The following subsections describe these simulation options Launch Options The Launch Option tab of the Simulation Options dialog box contains the options to control the execution of fuse and ISim as shown in Figure 5 11 page 190 PlanAhead User Guide www xilinx com 189 UG632 v13 4 January 18 2012 Chapter 5 RTL Design 190 XILINX G Simulation Options i Specify Options for behavioral simulation Launch Options Language Options Simulation Run Time 1000ns incremental nodebug o tclbatch rangecheck o wdb lt Default WDB Filename gt wefg Load glbl More Fuse Options More Simulator Options Select an option above to see description of it Figure 5 11 Simulation Options Dialog Box The Launch Options are Simulation Run Time Specify length of simulation time with time unit You c
343. g XCO core files from these sources as well In some cases third party providers offer IP as synthesized NGC or EDIF netlists To load these files into a design use the Add Sources command and specify Add or Create Design Sources Refer to Adding Existing IP Cores page 63 for a complete explanation of this process Adding Constraints The New Project wizard prompts you with the optional Add Constraints dialog box shown in Figure 3 7 page 42 to add top level UCF files or module level Netlist Constraint Files NCF files www xilinx com 41 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects g XILINX G New Project Add Constraints optional Specify or create UCF constraint files For physical and timing constraints If there are multiple Files then please choose the target which is where all of the constraints created by Plandhead will be saved Constraint File Target optional Location top uc C Plan4head_Install plandhead testcases PlanShead_Tutorial Sources top_flpn ucf C Plan4head_Install plandhead testcases Plan4head_Tutorial Sources top_Full ucF O C Plan head_Installiplan headitestcasesiPlan head_Tutorial Sources Add Files Create File Copy Constraints into Project Figure 3 7 Add Constraints Dialog Box You can add or create constraint files as needed for your project Refer to Managing Constraints page 56 for a complete description of this process Any UCF NCF o
344. g dialog box opens as shown in Figure 7 12 page 219 and lets you customize the timing report The Report Timing dialog box options are listed as follows e Results Name Specifies the name of the timing report e Targets tab Allows the filtering of reported paths based on Start Points Through Points and Endpoints e Options tab Specify the options used in generating the report e Advanced tab Contains advanced options used for generating and storing the timing report e Timer Settings tab Specify timing engine and delay options used to generate the timing report e Command Contains the text of the Tcl command generated by the Report Timing options Note This field can be edited and modifies the Tcl command being executed but does not change the options specified in the dialog box e Open in New Tab Specifies that the timing analysis results open a new tab in the Timing Results view or replace an existing tab e Click OK to run the timing report The following subsections describe the various tabs of the Report Timing dialog box Understanding the Targets Tab The Targets tab of the Report Timing dialog box shown in Figure 7 12 page 219 contains fields where you can specify the starting points through points and end points of the paths to include in the timing report By default the dialog box opens with blank fields indicating all points included in the report up to the maximum number of
345. g various Flows and strategies Create Implementation Runs Name Strategy Make Active optional impl_2 fla ISE Defaults ISE 13 impl_3 l MapTiming ISE 13 impl_4 i MapGlobalOptParHigh ISE 13 impl _5 fb MapLogicOptParHighExtra ISE 13 Runs to create 4 Cancel Figure 9 18 Choose Synthesis Strategies Enter a Name or accept the default name and select a strategy for the new run 5 Click the More button to define additional new runs Enter names and choose strategies for additional runs as shown above 6 Click Next to invoke the Launch Options dialog box Refer to Defining Synthesis Run Options page 198 or Setting Implementation Options page 291 for more information on setting launch options Click Next and review the Create New Runs Summary Click Finish to create the defined runs and execute the specified launch options Using the Design Runs View The PlanAhead tool provides the capability to create multiple synthesis and implementation runs The Design Runs view displays all of the synthesis and implementation runs created in a project and provides commands to configure manage and launch the runs The PlanAhead tool issues messages for out of date design data when source files constraints or project settings are modified You can reset runs and delete stale run data using various commands of the Design Runs view 302 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g
346. ges to fit onto the toolbar Currently defined custom commands are available from the Tools gt Custom Commands menu item with each command listed on the submenu The Custom Command menu is persistent with the PlanAhead tool and is restored each time the tool is launched Custom commands are saved to the commands paini file output by the PlanAhead tool Refer to Outputs for Environment Defaults in Appendix A for more information PlanAhead User Guide www xilinx com 173 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX 174 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Chapter 5 RTL Design The Project Manager in the PlanAhead tool lets you create and manage individual Register Transfer Level RTL files and elaborate and analyze them in the context of an overall FPGA design The PlanAhead tool includes e Source file management e Context sensitive text editor for Verilog and VHDL files e RTL schematic viewer e RTL design rule checks DRCs e Behavioral simulator e RTL power estimator Managing Design Source Files You can add and manage the following design source file types in a project e Verilog and VHDL RTL source files e NGC EDIF and Xilinx CORE Generator XCO files e UCF constraint files e Simulation test benches e Block Memory Map BMM files Most of the interaction with source files is from within the Sources view See Using the
347. gic element is placed into the center of the SLICE and is only assigned to a specific device resource when you click to assign the element to the SLICE col Create Site con coo CYINIT CIN SLICEM Figure 10 22 Create Site Constraint The dynamic cursor does not allow instances to be placed if the SLICE would be over packed with logic Certain logic groups such as carry chain logic move as a single object which requires open placement sites for all logic on the carry chain After location constraint assignment is complete return to the default Assign Aid instance to Pblock mode by clicking the Assign Instance Mode toolbar button a To view location constraint properties select the placement constraint and view the Instance Property view Assigning BEL Placement Constraints BELs PlanAhead User Guide You can place a leaf level primitive instance into a specific device resource site by dragging it from the netlist tree and dropping it onto a specific device resource using Create BEL Constraint Mode The BEL constraint assigns a logic element to both a SLICE and a specific device resource within that SLICE The logic elements are assigned as fixed placed and are locked during subsequent ISE placement iterations To create a BEL constraint click Create BEL Constraint Mode Figure 10 23 page 332 shows a logic element placed into a specific device resource in a SLICE using Create
348. gic within a design Clocks can be primary clock domains or generated by clock primitives such as a DCM PLL or MMCM A clock is the rough equivalent toa TIMESPEC PERIOD constraint in UCF and forms the basis of static timing analysis algorithms www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX First Class Tcl Objects and Relationships Querying Objects All first class objects can be queried by a get_ Tcl command that generally has the following syntax get_object_type pattern Where pattern is a search pattern which includes if applicable a hierarchy separator to get a fully qualified name Objects are generally queried by a string pattern match applied at each level of the hierarchy and the search pattern also supports wildcard style search patterns to make it easier to find objects for example get_cells inst_1 This command searches for a cell named inst_1 within the first level of hierarchy under the top level of hierarchy To recursively search for a pattern at every level of hierarchy use the following syntax get_cells hierarchical inst_1 This command searches every level of hierarchy for any instances that match inst_1 For complete coverage of syntax see the specific online help for the individual command help get_cells get_cells help Object Properties PlanAhead User Guide Objects have properties that can be queried Property names are unique for any give
349. gnal Specifies the name of the other pin in the differential pair Values are the name of the user I O or blank when unused I O Standard I O standard for a specific user I O When this field is blank for a user I O the software uses the appropriate device defaults Values are a legal I O standard for the user I O in the device or blank Drive Drive strength of the I O standard for a specific user I O Not all I O standards accept a drive strength If this field is blank the tools use the default Values are a number or blank Slew Rate Slew rate of the I O standard for a specific user I O Not all I O standards accept a slew rate If this field is blank the tools use the default Values are FAST and SLOW Pull Type Specifies the pull type for the selected port When using 3 state output OBUFT or bidirectional IOBUF buffers the output can have a weak pull up resistor a weak pull down resistor or a weak keeper circuit For input IBUF buffers the input can have either a weak pull up resistor or a weak pull down resistor Phase Specifies the phase of an I O relative to the phase of other I O in the bank in cases of a synchronous phase offset Board Signal The name of the signal coming into the I O from the board level design www xilinx com 411 UG632 v13 4 January 18 2012 Appendix A PlanAhead Input and Output Files XILINX Board Voltage Specifies the voltage level of the signal
350. gular Expression Specifies that the search string use regular expression syntax e Ignore Case Specifies the search string is case insensitive e Filter Matching Name with Expression An SDC syntax option that specifies the filter command Note This field is only available when matching style is set to SDC Ignore Command Errors Suppresses warning messages generated during Tcl command processing of the timing report Find Command button for launching a search based on the defined expression Find Results Contains the results of the object search e Move Item to the Right Moves the currently selected object from the Find Results column to the Selected Names column e Move Item to the Left Moves the currently selected object from the Selected Names column to the Find Results column e Move All Items to the Right Moves items from the Find Results column to the Selected Names column www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using Slack Histograms e Move All Items to the Left Moves items from the Selected Names column back to the Find Results column Selected Name Contains the currently selected destination clocks Command Specifies the Tcl command expressions used to identify the selected clocks Choosing Endpoint Path Groups The Choose Endpoint Path Groups dialog box lets you filter the endpoints by the specified group name Figure 7 22
351. gure 11 3 Implemented Design impl_2 constrs xcb lx 5tff764 3 active E S impl_1 constrs_1 xc vlx75tff784 3 Xx SB impl_2 constrs_1 xc6vIx75tff784 3 X Figure 11 3 Multiple Implemented Designs Open Tabs You can open and close available Implemented designs using the pulldown menu in the Flow Navigator Each Implementation run shows under the Open Implemented Design menu enabling any completed run to be opened as shown in Figure 11 4 El Implemented Design Run DRC OE Run Noise Analysis impl_1 constrs_1 xc6vlx75tff784 3 active impl_2 constrs_2 xc6vix75StfF784 3 E Report Timing Close Jili Slack Histogram 2 Launch FPGA Editor ff Launch XPower Analyzer Figure 11 4 Opening and Closing Implemented Designs When multiple implemented designs are open the Implemented Design button displays with multiple icons Building an Implemented Design with Imported Placement You can import existing ISE results using the New Project wizard or by import timing results The following subsections describe the options for importing ISE results Using the New Project Wizard to Import Placement You can create a new project and populate the project with a netlist and placement and timing results from an ISE software implementation run For more information about creating a new project that imports ISE implementation results see Creating a Project with I
352. h and add existing IP cores to your design To create new source files or add existing source files to your project select File gt Add Sources from the main menu or Add Sources from the popup menu or from the Flow Navigator The Add Sources wizard opens as shown in Figure 3 14 page 50 G Add Sources Add Sources This wizard will guide you through the process of adding and creating sources for your project What type of sources you want to add Add or Create Design Sources Add or Create Constraints Add or Create Simulation Sources Add Existing IP Pla nAhead To continue click Next i Cancel Figure 3 14 Add Sources Wizard Refer to the following sections for discussion on adding the various types of source files e Managing RTL Source Files page 51 e Managing Constraints page 56 e Managing Simulation Sources page 61 e Managing IP Cores page 63 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Managing RTL Source Files Managing RTL Source Files The following subsections describe how to manage RTL source files Adding and Creating RTL Source Files To add Verilog or VHDL source files select the Add or Create Design Sources option from the Add Sources command and click Next Figure 3 15 shows the Add Sources dialog box G Add Sources Add or Create Design Sources Specify HDL and netlist files or directories containing HDL and netlist Files to add to you
353. has pin icons indicating how full the bank is and puts a check mark for a passing predictor or a red circle indicating failure e Group Virtex 6 only Displays the pin groups with like I O standards assigned within the bank and displays their status Groups are determined automatically based on the I O standards drive strength slew rate and phase assigned e T O Std Vcco Slew Drive Strength Displays the appropriate values for the port or bank 284 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX PlanAhead User Guide Using Noise Analysis Predictors Noise V e Contributed Virtex 6 only Contains the SSN aggregate of each group generated by the I O standard drive strength and slew type of that group e Bank Total Virtex 6 only Defines aggregate SSN predicted for a bank or group If multiple phases are specified for the groups of a given bank the SSN contributions of groups with different phases are accumulated separately and the maximum of these is reported Because the SSN calculation is isolated to the output of that bank one SSN bank total does not affect another bank total This column identifies which I O groups are creating the most SSN and how much margin they use Off Chip Termination The Off Chip Termination field automatically populates with the default terminations for each I O standard if one exists For example for LVTTL at 2mA 4mA 6mA and 8mA
354. hasdht1 UWnlanthasdthackeseacthlan the i gt oO si Figure 3 18 Remote and Copied Source Files Updating Local Source Files PlanAhead User Guide When referencing remote sources the PlanAhead tool automatically detects the updated source file changes However with source files that are copied to the local project any changes to the original source file are not recognized You must manually update local source files if necessary You can update source files that are copied into the local project directory using the following options 1 Select the source file in the Sources view and select the Update File command from the popup menu A file browser opens with the original source file referenced Click OK to reload the original source file www xilinx com 55 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects g XILINX You can also specify a different file to use as the referenced source at this time and the PlanAhead tool copies the new source file into the local project directory 2 Click Add Sources from the popup menu to add the newly updated sources to the project The PlanAhead tool then imports the added file into the project However because there is already a local source with the same name the Import Source Conflicts dialog box shown in Figure 3 19 prompts you to resolve the conflict by overwriting the existing file or by not loading the newly added file 3 Select the preferred
355. he ChipScope view layout from the Layout Selector or the Layers menu or can be opened directly using Windows gt ChipScope www xilinx com 371 UG632 v13 4 January 18 2012 Chapter 12 Programming and Debugging the Design XILINX e The lowest level is the set of Tcl debug commands that you can enter manually or replay as a script You can use a combination of the modes to insert and customize debug cores also Deciding Which Debug Core Insertion Mode to Use The following table summarizes how to decide what insertion mode s to use based on the debugging goal Table 12 1 Debugging Goals and Core Insertion Modes Debugging Goal Core Insertion Mode Quickly create ILA debug core s with default settings for the ChipScope Wizard selected nets Change parameters on existing debug cores ChipScope Window Manually create or delete existing debug cores ChipScope Window Manually create delete or configure trigger or data portsonan ChipScope Window ILA core Manually assign nets to the trigger data clock channels ChipScope Window Play back a recorded script of debug commands later Tcl Commands Marking Nets for Debug The first step in the debug flow is to identify the set of nets to debug ChipScope debug core insertion and configuration operations must be performed in the Netlist Design because you must add the cores to the netlist prior to Implementation See Using the Netlist Design Env
356. he Show Instance Connections toolbar button on and off The Show Instance Connections mode remains active which lets you select additional logic objects for viewing connectivity Toggle the toolbar button to turn off that mode Expanding and Selecting a Logic Fanout You can run Show Connectivity sequentially to continue to select and expand a logic fanout 1 Select a Netlist a Pblock instance or a combination thereof 2 From the popup menu select Show Connectivity The command highlights all nets connected to the selected element 3 From the popup menu select Show Connectivity a second time The command selects the set of connected instances to those nets You can use the Ctrl T shortcut key also 4 From the popup menu select Show Connectivity a third time The command highlights the next level of nets connected to the selected instances and so on This is an easy way to select a logic fanout starting at a particular instance or I O port Expanding Logic in the Schematic View You can trace logic throughout the design hierarchy using the Schematic view Anything selected in the Schematic view is highlighted in the Device view also You can expand signals interactively by double clicking on the pins of the instance to be traced Figure 11 13 shows an example of expanded logic in the Schematic view pe E usb_dma_wb_in R butfer_fifo R Mram_fifo_ram RA A ADDRBWRADDR CASCADEINA CASCADEINB CLKARDC
357. he project 6 Click Finish to create and open the project When the implemented design is complete the PlanAhead tool prompts you to Open Implemented Design Generate Bitstream or View Reports The PlanAhead tool opens the Implemented design environment with design placement and timing results loaded and related views available Importing an ISE Project The ISE project type lets you import an existing RTL level ISE project to migrate the design from Project Navigator in ISE to Project Manager in the PlanAhead tool 1 Follow the steps described in Creating a New Project page 35 2 Inthe Design Source page shown in Figure 3 2 page 36 select Import ISE Project The Import Setting from an ISE Project dialog box opens as shown in Figure 3 12 page 48 PlanAhead User Guide www xilinx com 47 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects XILINX G New Project Import Settings From an ISE Project Specify an ISE project file ISE project file C Data FPGA_design ise_designs drp_des first_pass xise Figure 3 12 Import ISE Project 3 Specify the ISE project file to import Locate the XISE file stored under the ISE project directory you want to import 4 Select Import Source to the Project Directory to have the design sources from the ISE project copied locally into the PlanAhead tool project instead of being referenced from their current location 5 The New Project Summary page displays the opt
358. he command e If you have not yet launched a run you can modify the values of the command options Select a command option to edit and click the checkbox to enable or disable the option enter a value or select the value from the pulldown menu and click Apply e Modified values show an asterisk next to the option to indicate that default Strategy values have changed e With the right mouse popup menu e Save Strategy As to save the new option settings as a strategy for later use in other runs e Refresh or restore the command options to their preset values e After you launch the run which is described in Launching an Implementation Run in Chapter 9 you can no longer modify the Strategy option you must reset the run and then edit the option to change the run See Resetting Runs in Chapter 9 Monitor Displays the same STDOUT command status logs that display in the Compilation view Figure 4 10 page 99 shows an example of the Compilation log The Monitor view continues to update as commands run You can use the scroll bar to browse through the command log reports Click Automatically update the contents of this view to stop the active reporting This lets you scroll easier and read results while the command is running PlanAhead User Guide www xilinx com 147 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment g XILINX 148 Table 4 1 Tabs of the Run Properties View Tab Optio
359. he embedded processor system was originally created using the Base System Builder BSB the UCF has placement and timing constraints specific to the targeted reference board These constraints must be added to the PlanAhead project You can add the constraints by adding the system ucf to the active constraints fileset in PlanAhead or by copying the constraints from system ucf into the active PlanAhead UCF file When adding the system ucf file to the PlanAhead project constraint fileset you should be aware of the order of precedence between multiple UCF files to ensure that required embedded processor system constraints are not overwritten Constraints are order dependent with the last read definition of a constraint over writing earlier definitions See Adding and Creating Constraint Files page 57 for more information To copy the constraints from the system ucf file into the active UCF file 1 Open the system ucf file located in the data directory of the embedded processor project in a text editor Open the target constraint file in the PlanAhead project in a text editor Select and copy all of the constraints in system ucf into the PlanAhead UCF file Note If the embedded processor system was instantiated in the top level HDL file no changes are required to the constraints If the embedded processor system was NOT instantiated in the top level HDL file the net names used in the system ucf constraints must be changed as appropriate
360. he new interface 4 USB_1 44 Figure 8 18 Create I O Ports Interface 3 Enter a name for the interface and adjust assignment selection then click OK The interfaces appear as expandable folders in the I O Ports view To add additional I O ports to the interface select them in the I O Ports view and drag them into the Interface folder as shown in Figure 8 19 Neg Diff Pair Location Bank J OStd Drive Strength Slew Type Pull Type S All ports 138 Gl USB_O 30 H 8 LineState _pad_0_i 2 17 LYCMOS25 12 SLOW H 8 Dataln_pad_O_i 8 LYCMOS25 12 SLOW DataOut_pad_O_o 8 17 LYCMOS25 12 SLOW H 5 Scalar ports 12 H USB_1 44 B LYDS_25 Scalar ports 0 Figure 8 19 Manage I O Port Interfaces To include additional I O ports in an interface 1 Select a port or bus 2 From the popup menu select Assign to Interface 3 Select the target interface to which to add the I O ports To remove I O ports and interfaces 1 Select a port or interface 2 From the popup menu click Unassign from Interface To delete interfaces select an interface and select Delete from the popup menu or press the Delete key Disabling or Enabling Interactive Design Rule Checking The PlanAhead tool checks to ensure a legal pin out however only ISE implementation tools provide complete signoff DRCs Therefore you need to run your design through the ISE pinning process to ensure final legal pinouts 268 www
361. hen you hover the cursor over a logic site See Viewing and Reporting Resource Statistics page 209 for more information about viewing device resources You must zoom the view to see the CLBs SLICEs and BELs You can e Assign primitive logic instances to the appropriate displayed sites e Import ISE placement results to display the logic assignments At the zoom level the placed instances appear as rectangles within a SLICE When you increase the zoom level the logic symbols display You can assign logic to specific sites that generate LOC placement constraints Using BEL constraints you can assign sites to specific gates or toa SLICE Logic imported from ISE displays as BEL level constraints For more information about placement constraints see Working with Placement LOC and BEL Constraints page 329 Setting Visible Device View Layers For Virtex 6 Virtex 7 Kintex 7 and Artix 7 device families the Device view toolbar includes the Device View Layers command that lets you define what layers and objects are visible in the Device view This command accesses the Layers Slideout and allows you to control the level of detail displayed in the Device view and is especially useful when the display seems over crowded with information Figure 4 44 page 132 shows the Device View Layers toolbar button and the Layers Slideout with layers and objects that you can display or hide The availabl
362. hese scripts independently also PlanAhead User Guide www xilinx com 419 UG632 v13 4 January 18 2012 Appendix A PlanAhead Input and Output Files XILINX 420 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Appendix B PlanAhead DRCs RTL DRCs Power and Performance Table B 1 and Table B 2 page 422 list the RTL Power and the RTL Performance DRCs RTL DRCs Power Table B 1 Power Rules Rule Name Rule Abbrev Rule Intent Severity Constantly RPRC A described RAM either inferred or instantiated which is constantly Warning enabled enabled was found in one or both ports If it can be determined that this synchronous RAM is not constantly accessed Significant power reduction might be RAM seen by describing the logic to disable the RAM unless it is being accessed Inefficient RPRM A RAM in which there is an unconnected output port has been detected Warning dangling block and the WRITE_MODE is set to a value other than NO_CHANGE Modifying RAM port the description of the RAM to set unconnected output port WRITE_MODE set to NO_CHANGE could save up to 10 of the dissipated block RAM power Shallow RAM RPRS Virtex 5 and Virtex 6 devices For wide over 18 bits and shallow Warning implemented in 64 bits or less RAM it is generally advantageous to choose block RAM SelectRAM LUT based RAM referred to as distributed RAM whenever possible unless the
363. hesis or Implementation completes you can view the ISE reports and open the Netlist or Implemented design to apply timing or physical constraints analyze the design and re implement the run as needed See Chapter 11 Analyzing Implementation Results for details Viewing Report Files You can view report files generated by the ISE tools from within the Reports view The view is usually opened automatically after commands are run if it is not available select the Reports link in the Project Summary The Reports view opens as shown in Figure 9 11 A Name Modified Size Synthesis xst E A XST Report 2 2 11 2 32 PM 686 KB a 5 Translate nadbuild A NGDBuild Report 2 3 11 10 08 AM 5 KB Map map 3 MRP Report 2 3 11 10 10 AM 199 KB 2 MAP Report 2 3 11 10 10 AM 2KB Place amp Route par E Tel Console Messages Lal Compilation Design Runs D Figure 9 11 Selecting Report Files to View Select and view any available report files in the workspace shown in Figure 9 12 page 298 PlanAhead User Guide www xilinx com 297 UG632 v13 4 January 18 2012 Chapter 9 Implementing the Design g XILINX lRelease 12 0 Map M 46 nt 2Xilinx Map Application Log File for Design therm 3 4Design Information 6 Command Line map intstyle ise therm ngd 7 Target Device xc6vlx75t 8 Target Package ff484 9 Target Speed l1 10 Mapper Version virtex6 Revision 1 52 11 Mapped Date Sat Feb 27
364. hesized netlist files NGC to the core in the Sources view In Figure 3 29 there is no check mark by the char_fifo IP because it has not yet been synthesized while the clk_core and samp_ram IPs are synthesized and have check marks wb ot at B Design Sources 24 H Verilog 21 G IP 3 H LF char_fifo 4 4 44 e clk_core 5 io samp_ram 7 JF e samp_ram xco Sg SAaMp_ram veo Seg Samp_ram_xmdf tcl Ee blk_mem_gen_ds512 pdf gt e samp_ram nge samp_ram A coregen log Constraints 1 S E constrs_1 J wave_gen_timing ucf target Figure 3 29 IP Displayed in Sources View For cores that are synthesized or generated you can select the IP cores in the Sources view and select Reset IP from the popup menu to reset the IP This restores the core to an un generated state eliminating the NGC files associated with the synthesized core This allows you recustomize the core in the project if needed and then synthesize the reset core Updating the IP Catalog The PlanAhead tool creates a local version of the Xilinx IP Catalog when the tool is invoked for the first time after installation Periodically Xilinx or an authorized third party partner updates the IP Catalog consequently you must update the local version of the IP Catalog to ensure it is up to date Use Update IP Catalog from the popup menu in the IP Catalog view to update the catalog The Update IP Catalog dialog box displays as shown
365. hich to operate Other commands perform an action but do not necessarily return a value that can be used directly by the user Some tools that integrate Tcl interfaces return a 0 or a 1 to indicate success or error conditions when the command is run To properly handle errors in Tcl commands or scripts you should use the Tel built in command catch Generally the catch command and the presence of numbered info warning or error messages should be relied upon to assess issues in Tcl scripted flows All PlanAhead application commands return either TCL_OK or TCL_ERROR upon completion In addition the PlanAhead tool sets the global variable ERRORINFO through standard Tcl mechanisms To take advantage of the SERRORINFO variable use the following line to report the variable after an error occurs in the Tcl console puts SERRORINFO This reports specific information to the standard display about the error For example the following code example shows a Tcl script procs tc1 being sourced and a user defined procedure loads being run There are a few transcript messages and then an error is encountered at line 5 Line 1 PlanAhead source procs tcl Line 2 PlanAhead loads Line 3 Found 180 driving FFs Line 4 Processing pin a_reg_reg 1 Q Line 5 ERROR HD Tcl 53 Cannot specify patterns with of_objects Line 6 PlanAhead puts SerrorInfo Line 7 ERROR HD Tcl 53 Cannot specify patterns with of_obje
366. hierarchy Netlist Hierarchy Specifies the Format of the final netlist generated by synthesis Use rebuilt to generate a hierarchical netlist after the normal synthesis optimizations have occurred Use as_optimized to generate an optimized flat netlist Hierarchical OK Cancel Apply Figure 3 43 Synthesis Project Settings The Synthesis Project Settings dialog box contains the following information e Default Constraint Set Select the active constraint set See Managing Constraints page 56 for more information on constraint sets e Strategy Select the strategy to use for the synthesis run The PlanAhead tool includes a set of pre defined synthesis strategies or you can define your own For more information see Defining Strategies for Synthesis and Implementation in Chapter 4 When you select a synthesis strategy the command line options for XST display in the lower part of the dialog box as shown in Figure 3 43 You can override synthesis strategy settings by changing the values of command line options e Description Displays a text description of the selected strategy PlanAhead User Guide www xilinx com 87 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects g XILINX Implementation Settings Figure 3 44 shows the Implementation Project Settings dialog box G Project Settings Implementation Constraints Default Constraint Set aa constrs_1 active Simulation Options
367. hierarchy using the Expand All toolbar buttons or click the next to each category or design object e Click the check box next to the design object to run all DRCs e Click individual DRCs to run individual ones e Click Select All to run a complete DRC 248 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Running the Design Rule Checker DRC G Run DRC Results Name results_1 Output File Rules to Check 59 of 59 rag A A pa SM All Rules 59 SMI Netlist 5 SM Net 1 W Driverless Nets NDRY Mi Instance 4 iW Black Box Instances INBB i Attribute 2 Mi Invalid attribute value AVAL Mi Attribute not defined ADEF W Required Pin not connected REQP MI Clock 4 SM Bank 18 a w pcr 3 DCI Cascade Checks DCIC M DCI Cascade with part compatibility OCICPC W DCI Cascade IO standard DCICIOSTD MI 10 Standard 13 W Configuration Mode CFGM Mi IDLY 1 Mi IDelayCtrl Checks IDLYCTRL vd IOB 11 w wa Placer 5 Floorplan 5 M4 PBlock 5 W Longest carry chain height LCCH Mi Pblock overlap FLBO M Pblock partition FLBP MI Resource utilization UITLZ W Area group tile alignment FLEA w wa CIkBuf 1 GM DSP48 7 DSP output registers DPOR MI DSP input registers DPIR VJ DSP output pipelining DPOP DSP multiplier output pipelining DMOP MI DSP input pipelining DPIP W DSP48 Cascade DPCA WM DSP48 asynchronous feedback DPREG RAMB16
368. hing rates The default filename is xpower saif SDF Delay Specify the type of delays for ISim to use Values are e sdfmin to annotate minimum delays e sdfmax to annotate maximum delays Xilinx recommends running separate simulations to check for setup violations by specifying sdfmax and for hold violations by specifying sdfmin More Fuse Options Specify additional command line options for fuse These commands should be typed in a single string with the command value pair For instance maxdelay init file lt filename gt notimingcheck You can also add the fuse options into a command file and reference this file in the More Fuse Options field with the command as follows www xilinx com 363 UG632 v13 4 January 18 2012 Chapter 11 Analyzing Implementation Results g XILINX lt command_file gt e More Simulator Options Specify additional command line options for ISim The commands must be in a single string with the command value pair For example log lt filename gt transport_int_delays You can also add the ISim options into a command file and reference this file in the More Simulator Options field with the command as follows lt command_file gt Language Options Figure 11 22 shows the Language Options tab of the Simulation Options dialog box G Simulation Options i Specify Options For timing simulation Top Module Design Under Test top Launch Options Netlist Opt
369. hs 2 82 Fully Constrained a 0 Vv Unconstrained 0 V Unconstrained 1 94 Fully Constrained 0 v Unconstrained 0 v Unconstrained oi 6 15 Fully Constrained Unconstrained Unconstrained LUncanstrained lt lt Clock Interactions Unclocked Register Pins Figure 7 28 Clock Interaction Report After running the Report Clock Interaction command the results open in the Clock Interaction view The Clock Interaction Report displays as a matrix of clock domains with the launching clocks in the vertical axis and the receiving clocks in the horizontal axis A table showing the worst case slack calculated for each cross clock domain is displayed below the matrix Figure 7 28 shows an example of the Clock Interaction Report and its table In Figure 7 28 there are six separate clock domains found by the PlanAhead tool so each clock is analyzed against all the other clock domains to determine if there are timing paths that cross those domains The state of constraints across any two clock domains is reported PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 243 244 Chapter 7 Netlist Analysis and Constraint Definition XILINX in the Clock Interaction Report The results display in a six by six matrix which uses the following color scheme to display the state of cross domain signals e A white or black cell indicates that no paths were found crossing between the two clock domains
370. ialog box to speed RTL coding e Entity name Module name Specify the name for the entity construct in the VHDL code or the module name in the Verilog code Although the entity or module name defaults to the file name it does not have to match file name e Architecture name Specify the Architecture for the RTL source file By default the name is Behavioral Note This field only applies to VHDL code and does not appear when defining Verilog modules e I O Port Definitions Define the ports to be added to the module definition Port Name Define the name of the port to appear in the RTL code Direction Specify if the port is an Input Output or Bidirectional port Bus Specify if this is a bus port Define the width of the bus using the MSB and LSB fields as described below MSB Define the number of the most significant bit This combines with the LSB field to determine the width of the bus being defined LSB Define the number of the least significant bit Note MSB and LSB are ignored if the port is not a bus port 4 When you have finished defining the details of each of the new modules listed under New Source Files click OK to create the RTL source files and add the modules to your project The Sources view lists the newly defined modules 40 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX PlanAhead User Guide Creating a New Project 5 Open the new
371. ic lower level modules are imported automatically You can define a search path to locate the design modules The advantage to this process is more flexibility when updating the design The PlanAhead tool has an incremental netlist import capability that allows netlist updates at any level of the design hierarchy PlanAhead User Guide www xilinx com 409 UG632 v13 4 January 18 2012 Appendix A PlanAhead Input and Output Files XILINX Table A 1 Input Files Cont d File Name NGC Top Level Netlists EDIF Description The PlanAhead tool supports importing EDIF or NGC netlists The netlist should be synthesized for a Virtex 4 Virtex 5 Virtex 6 Virtex 7 Kintex 7 Artix 7 Spartan 3 or Spartan 6 device The PlanAhead tool can construct the design using multiple netlists supporting a Hierarchical Design methodology When you select the top level logic lower level modules are imported automatically Incremental netlist import capabilities allow netlist updates at any level of design hierarchy In process floorplanning constraints are maintained through iterations Constraint Files UCF The PlanAhead tool supports importing UCF NCF and XCF format files for timing and NCF XCF physical constraints The PlanAhead tool can import multiple UCF files which allows for separation of physical constraints I Os and timing constraints NCF files are module level constraints that are spec
372. icators to display the messages in a tool tip e Double click the color indicator to auto scroll to the associated message in the Tcl Console Entering Tcl Commands You can use Tcl format commands on the command line entry box at the bottom of the Tel Console view shown in Figure 4 11 page 99 To enter commands click on the command line and type Tcl commands The Tcl Console auto complete feature attempts to complete the name of the command or command parameters as you type on the command line In Figure 4 12 page 101 the Tel Console provides a list of commands that match create_ Click on a command from the list to select it You can continue to type until the auto complete feature has narrowed the command to one choice and press the Tab key to select it After a command is selected the Tcl Console attempts to auto complete any arguments of the command You can also select from a list of parameters or press the Tab key when the list is narrowed to one choice www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using the Tcl Console and Messages Area AF 2 create_clock create_debug_core x create_debug_port create_fileset create_generated_clock create_interface create_ip create_ip_catalog create_ ted Consol create _ ssages J q Compilation Reports I Figure 4 12 Auto Complete Tcl Commands The PlanAhead tool writes a Tcl command equivale
373. ids SLICE 352 DS5P48 16 RAMB36 8 Assign selected instance i Cancel Figure 10 1 New Pblock Dialog Box 5 Edit the options and click OK when done Options are e Name Enter a name for the Pblock If no name is entered a default name of pblock_nor Pbhlock_instancename is used e Grids Select the device resource ranges to be constrained by the Pblock e Assign selected instances Assign the selected instances to the new Pblock Note Occasionally logic is inadvertently selected which is not intended for assignment Take care to avoid this error The Pblock displays and then you can select it in the Device view and the Physical Constraints view The Physical Constraints view opens in the Floorplanning view layout or you can open it using Window gt Physical Constraints The initial Pblock size and location are not critical during manual creation Pblocks can be appropriately sized by viewing the Physical Resource Estimates in the Statistics tab of the Pblock Properties view The location of a Pblock s rectangles is displayed under the Rectangles tab of the Pblock Properties view You can also determine how to reposition Pblocks relative to other Pblocks by viewing the connectivity in the Device view Sometimes it is helpful to initially create all of the Pblocks with small rectangles to visualize the logic connectivity flow between the Pblocks prior to attempting sizing as shown in Figure 10 2
374. ies and the interconnect wires shown in Figure 4 56 RChainTopIinst equaCalAinst bitREV_ EQUAL xMULT_BREi ESEC mult12b_RE1_RE2 3 EU gt E a iglesia E eR v aS lt i Sein awa dpram_24b_64w_wa_rb_HD33 equalMEM equacalAFFT Ge FENA Y mult12b_HD25 POE oxMULT_12_12_10_RChainTop bitRev_Equal_12 RChainTop RCV_802_11 Figure 4 56 Logic Hierarchy in Schematic View For more information about setting the timing path logic see Chapter 7 Netlist Analysis and Constraint Definition and Chapter 11 Analyzing Implementation Results Note Occasionally paths displayed from the Timing Reporter and Circuit Evaluation TRACE TWX an XML file or TWR a Text file format timing reports are missing interconnect wires This is because the logic was optimized out of the path during ISE Implementation The objects that display in the Schematic view are all of the actual objects contained in the selected paths however the PlanAhead tool cannot interpolate the connectivity after objects have been optimized away and no longer exist You can use the Schematic view in conjunction with the Path Properties to trace the path connectivity Usually the schematic is drawn is such a way that it is easy to see the path direction For more information see Analyzing Timing Results page 228 Using the Properties View The Properties view displays information about any selected logic ob
375. iew 2 Select Set Prohibit from the popup menu The PlanAhead tool places an X symbol on the prohibited pins in the Package view and places a checkmark in the Prohibit column of the Package Pins view as shown in Figure 8 17 E Project Summary x 29 RTL Schematic x M Package x re RH nies Outan Puish uP Den Figure 8 17 Setting Prohibits on Package Pins Creating I O Port Interfaces To group multiple ports or buses together you can create an interface This aids in pin assignment by treating all of the interface ports as one group Assigning all of the pins simultaneously helps condense and isolate the interface for clock region or PCB routing Also it is easier to visualize and manage the signals associated with a particular logic interface To create an interface 1 Inthe I O Ports view select the signals to group together 2 From the popup menu select Create I O Port Interface as shown in Figure 8 18 page 268 PlanAhead User Guide www xilinx com 267 UG632 v13 4 January 18 2012 Chapter 8 VO Pin Planning g XILINX Neg Diff Pair ation Ran JO Sid Drive Stranoth Clas Te Pull Type Create I O Port Interface po Create a new I O Port interface for project project_cpu_r Name EEE w8 LineState_pad_0_i 2 E8 Dataln_pad_O_ v Assign 5 selected I O port buses to the new interface DataOut_pad_0_o 8 9 op 5 Scalar ports 12 Assign 18 selected I O ports to t
376. iew Assigned Instance I O Net e Inthe Select column toggle the Placed Port check boxes off to make the object Fixed Port types unselectable Placed Instance Fixed Instance e The display of items in the Device Path view is controlled through the layer Tile Outline a a n z il j 1 ore Colors slideout in the Device view menu 5t Tri mode Ethernet i i Site System Monitor V Gg 59 Ib page 129 for more information ae Note Some elements of the Device view are specific to a target device and so changes to the display color or selectability will not have effect except on that device I Os Tab Object Type Frame Color Fill Color Adjust the default color for each object type in the VOPn Eo 0 255 128 1 k Input Pin B o o 255 M128 1 Package view Global Clock Pin E 255 0 0 miss 1 r i i Clock Capable Pin EE 255 0 0 iiss ran e The display of elements in the Package view ccc Ph 192 19 M181 2 can be controlled through the layer slideout GND Pin 192 19 N40 12 in the Package view menu bar See Using the Special Pin Eoo ioa 1 Package View page 133 for more fazali Eo o 0 255 1 informati n JTAG Pin Eo oo mess 1 j Power Management Pin MO 0 0 EE 255 1 Temp Sensor Pin E o o o EE 255 1 5Y5MON Pin Eo oo B255 1 GT Pin E 255 0 247 2 Bundle Nets Tab From To Display Select Width Color Configure the characteristics of displayed
377. iew Device View Shortcuts aed Package View Package View Shortcuts au Design Runs Sources Netlist 4 Properties I O Ports 1 Schematic Metrics Find View 4 Chipscope Configurations Simulation Other General Shortcuts Shortcuts for selected command Window Behavior Figure 4 72 Shortcuts Options Dialog Box The Shortcuts dialog box lets you create new custom shortcut settings At the top the available shortcut schemas lets you manage Shortcut schemas You cannot modify the default shortcuts You must create a new shortcut schema to customize Click Copy to create a new schema from the Default schema You can activate any schema in the list by selecting it from the pulldown menu of available schemas The bottom portion of the Shortcuts dialog box has an area where you can make modifications to shortcuts in the copied schema You can search through the list of views and select commands to enter new shortcuts as follows 1 Select Add Shortcut type in the new shortcut in the dialog box then click OK to Amy accept the new shortcut aan You can filter the commands listed for shortcut assignment using the Filter field Enter any text string to filter the list of available commands Also you can use different shortcuts for the same command in different views User specific shortcuts are saved to the shortcuts xml file in the PlanAhead tool configuration directories Refer to Outputs for E
378. ific to blocks of design or IP cores XCF files or XST Constraint Files can also be imported into projects The PlanAhead tool supports all of the UCF constraints supported by Xilinx Refer to the Constraints Guide UG625 as cited in Appendix E Additional Resources for more information about UCF constraints and the supported syntax ISE Placement Results The PlanAhead tool can import ISE placement results using XDL format data XDL data NCD XDL is created automatically when Implementation runs are launched After ISE commands complete you can create an XDL format file from the placed_design_name ncd file You can create XDL files and import placement for individual blocks or for the entire design The PlanAhead tool runs the XDL command automatically when you select a placed_design_name ncd file in the Import Placement dialog box TRCE Timing Results The PlanAhead tool can import the timing report generated by the Xilinx TRACE TWX TWR command including TWX and TWR files After the files are imported signal tracing and selection is available through the Timing Results View If both files exist TWX is the preferred format to use to import timing results I O Port Lists CSV File Format You can import a Comma Separated Values CSV format file to populate the I O Ports view within the I O Planning views This functionality is available in an Empty I O pin planning project only 410 You can then assign these I O ports to ph
379. ighted Figure 11 10 page 353 shows a highlighted timing path in the device view 352 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Analyzing Timing Results G project_DP_flat Implemented Design C Documents and Settings brianj My Documents PlanAhead_Designs PlanAhead_Tutorial_TSC Projects ee EJE Fie Edit View Flow Tools Window Select Layout Help Setepiweaxaes SRILA SI A p E Implementation Out of Date more Implemented Design impl_1 xc6v active am_fifo_ram Requirement Delay Source Clock usbClk_BUFGP rising at 0 000ns Destination Clock usbClk_BUFGP rising at 5 250ns Skew 0 105 1 194 1 299 Uncertainty 0 035 T5J 2 TIJ 2 1 2 DJ j 2 PE Total System Jitter T5J 0 070 Total Input Jitter TIJ 0 000 Discrete Jitter DJ 0 000 Phase Error PE 0 000 lt General Report Instances Options Device x E Project Summary x Timing Results A Name T Slaski From To Total Delay Logic Delay Net Stages Source Clock Destination Clock Z Constrained Paths 244 al j amp TS_usbClk PERIOD TIMEGRP usbCik 5 25 ns HIGH 50 30 Be P Path2 Setup 1 150 usbEngine usbEngi 2 134 65 9 4 usbClk_BUFGP usbCik_BUFGP gt P Paths Setup 1 145 usbEngine usbEngi 2 134 65 9 4 usbClk_BUFGP usbClk_BUFGP P Path Setup 1 143 usbEngine usbEngi 2 134 66 0 4 usbClk_BUFGP usbClk_BUFGP P PathS Setup
380. ile only They are not expected in the input file Trace Length um Specifies the length of the internal trace between the package pin and the die pad Prohibit Certain sites can be prohibited for many reasons to prevent user I O from being added to the site Prohibits ease board layout issues reduce cross talk between signals and ensure that a pinout works between multiple FPGAs in the same package In the UCF this is represented by a CONFIG PROHIBIT constraint Values are TRUE or a blank field leave this field blank when the Pin Number is left blank Interface An optional user specified grouping for an arbitrary set of user I O As an example this field provides a means to specify a relationship for the data address and enable signals for a memory interface Values are a text string or blank Signal Name The name of the User I O in the FPGA design Values are a string or blank for an unassigned Package Pin Direction The direction of the signal Values are IN OUT INOUT or blank when a user I O is not assigned to the site DiffPair Type Instructs the software about which pin is the N side of a differential pair and which pin is the P side This is used for differential signals only The software uses this column instead of a naming convention to determine which pin is the N side of the pair and which pin is the P side Values are P N or blank when a user I O is not assigned to the site DiffPair Si
381. iles Keep this in mind if you want to save these files for future reference When you launch the software it saves a backup copy of your last set of files to j ou_backup and 1log_backup Table A 1 lists the input file names and descriptions Table A 1 Input Files File Name Design Text Files Verilog VHDL Description You can import and elaborate Verilog and or VHDL files to analyze the logic or modify the source The original source files can be referenced and left in place or they can be copied into the project for portability You can specify the search directories when importing RTL source files All recognized files and file types contained in the directories are imported into the project I O Port Lists CSV You can import a Comma Separated Values CSV format file to populate the I O Ports view within the I O Planning view layout This functionality is available in an Empty I O pin planning project only You can then assign these I O ports to physical package pins to define the device pin configuration CSV is a standard file format used by FPGA and board designers to exchange information about device pins and pinout The CSV columns are listed in I O Port Lists CSV File Format page 410 Module Level Netlists and Cores EDIF NGC NGO BMM The PlanAhead tool can construct a design using multiple EDIF or NGC netlists supporting a Hierarchical Design methodology When you select the top level log
382. ilinx com 259 UG632 v13 4 January 18 2012 Chapter 8 O Pin Planning XILINX Defining and Configuring I O Ports To create and configure I O ports in an empty Pin Planning project use the I O Planning environment Importing I O Ports The PlanAhead tool supports importing UCF or CSV format files into an empty Pin Planning project Import the CSV file or a UCF into the project at the time you create the project or later by using the file import capability Use RTL files or headers to create an RTL source project for I O pin planning then add more complete RTL source files to the project later as the design progresses When you create an RTL based or synthesized Netlist based project the I O Ports view populates automatically with the I O ports defined in the design Importing a CSV Format File To import an I O ports list from a CSV 1 Select File gt Import gt Import I O Ports The Import I O Ports dialog box opens as shown in Figure 8 10 G Import 1 0 Ports i Import I O ports definitions and configurations from a UCF or CS file Import From csvFie Ji QUCF File Figure 8 10 Import I O Ports Dialog Box 2 Select the CSV File option and browse to select the CSV file to import The CSV file format is shown in Figure 8 11 a a e oo e e e e NO Top top Floorplan floorplan_1 Part xc5ysx35tff665 1 _2 Generated by brianj on Fri Feb 06 17 2
383. imulation time with time unit You can specify time in units of fs ps ns us ms and sec The default unit is ps You can also specify all as a keyword to indicate that ISim should run until there are no more events to simulate e Unit Under Test Specify the name of a unit to test Typically this is the same name as the top module however in cases where a test bench contains multiple possibilities for the top module the software prompts you to select the unit to test e incremental Switch to indicate that fuse linker and compiler should compile only the files that have changed from the last compilation www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX PlanAhead User Guide Performing Timing Simulation nodebug Switch to indicate that fuse should create a simulation executable exe that has no information for debugging your HDL code during simulation resulting in faster simulation run times tclbatch Specify filename of Tcl commands listed in a batch file for execution by the simulator at run time Commands in the specified batch file are executed sequentially until completion ISim ignores any commands entered from the command prompt until batch file execution has completed PlanAhead uses a tclbatch command to pass three required commands to Sim ina file called isim cmd The contents of this file are onerror resume wave add run lt value gt If you create a Tcl c
384. in the graphical workspace view Figure 4 16 World View The World view opens to a default size To resize the World view to make it larger or smaller left click and hold and drag any of the drag handles on the edge of the World view as shown in the figure above To reposition the World view left click and hold and drag anywhere on the perimeter of the view except on the drag handles Use this feature to reposition the World view anywhere within the limits of the graphical workspace view www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Working with Views To close the World view click on the downward pointing arrow icon in the view When you resize or reposition the World view it remains at the size and position you have established whenever you close and reopen the view Printing the Workspace View You can print the view that is active in the workspace Device view Package view Schematic view and Instance Hierarchy view Select File gt Print to print the current viewable area Splitting the Workspace You can split the workspace viewing area horizontally or vertically to enable multiple simultaneously displayed views Each panel acts independently allowing multiple views to be docked for viewing You can open two views of the same type such as two Device views for viewing different areas of the device or at different zoom levels You can also open two different views such as the
385. in the order they are displayed in the Compile Order tab of the Sources view The file at the top of the list is compiled first and the file at the bottom of the list is compiled last A specific compile order is necessary in cases where declarations are made in files that must be compiled before those entities can be used in other files To modify the compile order before synthesis e Drag and drop files in the Sources view or e Use the Move Up or Move Down commands in the Sources view popup menu See Using the Sources View in Chapter 4 for more information In addition when you specify a Top Module in the Sources view you can have the PlanAhead tool reorder the source files automatically based upon the design hierarchy of the new top module Defining Global Include Files In the case of Verilog and Verilog header files you can also define the files as Global Include files The PlanAhead tool supports designating one of more Verilog or Verilog Header source files as Global Include files Files that are marked as global include are processed first before any other sources for the following operations specify top module scan for include files auto re order source RTL elaboration synthesis and simulation Because the global include files are always processed before any other files in the design this lets you more easily specify common Verilog header files that are used by other sources in the design Verilog typically requires an i
386. in the project UCF Evaluate Implementation Options Evaluate the options for NGDBUILD MAP and PAR used for implementation of the embedded processor system It is important to recognize the effect positive or negative that various options can have on the implemented design Open the fast_runtime opt file located in the etc directory in a text editor The following NGDBuild options are set inthe fast_runtime opt file This information is for your reference here None of these options need to be changed from within PlanAhead Program ngdbuild p lt partname gt Partname determined by xflow command line nt timestamp NGO File generation Regenerate only when source netlist is newer than existing NGO file default bm lt design gt bmm Block RAM memory map file lt userdesign gt Userdesign determined by xflow command line uc lt design gt ucf User constraints file lt design gt ngd Name of NGD file same as design filebase End Program ngdbuild The following MAP options are set in the fast_runtime opt Program map o lt design gt _map ncd Output Mapped ncd file w Overwrite output files pr b Pack internal FF latches into IOBs fp lt design gt mfp Floorplan file www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Importing XPS Embedded Processor Designs ol high timing detail lt inputdir gt lt design gt ngd Input NGD fil
387. ine a name for the results reported in the Timing Results view 3 Click OK to import the timing results The timing results display within the PlanAhead environment Using the Timing Results View Timing Results A Name 5 5 Constrained 8 SI TS_usbClk PERIOD TIMEGRP usbCik 5 25 ns HIGH 50 2 Setup 30 P Pathi 2 Path2 2 Paths 2 Path 2 Paths 2 Pathe 2 Path Type SETUP SETUP SETUP SETUP SETUP SETUP SETUP PlanAhead imports the timing results from the ISE TRACE program and displays the results in the Timing Results view The Timing Results view displays the TRACE timing path information sorted by clock constraint Timing paths can be expanded and collapsed using the tree widgets in the view Slack numbers for failing paths are displayed in red Figure 11 6 shows the TRACE results Slack 1 Net From To Total Delay Logic Delay Net Delay Logic Net Stages Source Clock Destine 1 368 usbEngine1 usbEngine1 6 41 2 239 4 171 34 9 65 1 5 usbClk_BUFGP usbClk_ 1 235 usbEngine1 usbEngine1 6 277 2 239 4 038 35 7 64 3 5 usbClk_BUFGP usbClk_E 1 093 usbEngine0 usbEngineD 6 15 2 563 3 587 41 7 58 3 6 usbClk_BUFGP usbCik_E 1 045 usbEngine1 usbEngine1 6 083 2 169 3 914 35 7 64 3 4 usbClk_BUFGP usbClk_E 1 042 usbEngine1 usbEngine1 6 08 2 171 3 909 35 7 64 3 4 usbClk_BUFGP usbClk_E 1 002 usbEngineQ usbEngineO 6 059 2 279 3 78 37 6 62 4 5 usbClk_BUFGP usbClk_ 0
388. ing Constraints fd Run Noise Analysis Properties aP t Report Timing lill Slack Histogram DRC H Set up ChipScope Tr A Name Severi Details gt lg All Violations 224 SE DSP48 224 Implement to amp DSP output pipelining DPOP DPOP 1 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul Implemented Design DPOP 2 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul DPOP 3 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul p DPOP 4 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul DPOP 5 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul Program and Debug DPOP 6 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul DPOP 7 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul DPOP 8 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul DPOP 9 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput will improve performance Both mul DPOP 10 Warning DSP Mmult_n0027 output is not pipelined Pipelining DSP4
389. ing the Properties view does not initiate any changes unless you click Apply www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Configuring Pblocks Configuring Pblocks The following subsections describe configuring Pblocks Setting Pblock Logic Type Ranges To set Pblock AREA_GROUP range types in the Pblock Properties view modify the Grid Range options in the General tab Adjusting these options controls which type of logic is constrained within the Pblock rectangle as shown in Figure 10 10 G Set Pblock 2 Which resources do you wish pblock_usbEngine1 to constrain Grids SLICE DSP48 RAMB18 RAMB36 Figure 10 10 Setting AREA_GROUP Range Types If you resize a Pblock or move it to a location that includes new device logic types such as block RAM and DSP a dialog box displays prompting you to add the new range types to the Pblock definition The contents of this dialog box varies based upon the location of the Pblock Toggling the ranges off results in the Pblock showing differently in the Device view As you select the Pblock the shading affects only the logic types for the ranges set on the Pblock as shown in Figure 10 11 Physical Constraints rO x ET E netlist _1 B ROOT lock_usi amp Sources B Netlist E Phys Timing Pblock Properties rO X gt B I pblock_usbEngine1 Name pblock_usbEngine1 Parent ROOT Grid Range C
390. ings xst 2677 Node lt validForEgressFifo_10 gt of sequential type is unconnected in block lt bft gt xst 2677 Node lt validForEgressFifo_11 gt of sequential type is unconnected in black lt bft gt xst 2677 Node lt validForEgressFifo_12 gt of sequential type is unconnected in block lt bft gt xst 2677 Node lt infer_fifo rd_addr_tmp_10 gt of sequential type is unconnected in block lt async_fifo gt xst 2677 Node lt infer_fifo wr_addr_tmp_10 gt of sequential type is unconnected in block lt async_fifo gt xst 2677 Node lt ingressLoop 0 ingressFifo buffer_fifo wr_ack gt of sequential type is unconnected in block lt bft gt xst 2677 Node lt inqressLoopf1 inaressFifo buffer fifo wr ack gt of sequential type is unconnected in block lt bft gt i Bens E Tel Console L E Compilation Find in Files 2 Package Pins Design Runs D HO Ports Figure 6 6 Synthesis Message and RTL Source File Selecting The Step After Synthesis After the run is complete the Synthesis Completed dialog box shown in Figure 6 7 opens and prompts you to take the next step Synthesis Completed LD Project project_bft_core_hdl Synthesis successfully completed Next Implement Open Netlist Design View Reports C Don t show this dialog again Figure 6 7 Synthesis Completed Dialog Box 1 Inthe Synthesis Completed dialog box select the option that matches how you want to proceed
391. inimized tabs to restore the Messages view to its original size and location Figure 4 13 page 102 shows the Minimize button in the upper right of the window as well as the minimized Messages tabs displayed in the lower left of the viewing environment www xilinx com 101 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX Messages Al is iG Figure 4 13 Minimize View command with Minimized Message View tabs Working with Views The PlanAhead tool has different types of views for displaying different types of information You can independently control views with respect to size visibility and location Opening Views To open most view types use the Window menu from the main menu Select a window that is already open to make it the active window As commands run new views open in the interface with which to interact or to display results e The Schematic view requires at least one design object to be selected in another view such as in the Sources view Use the popup menu Schematic command or the Schematic toolbar button to open the Schematic view See Using the Sources View page 122 e The Properties view requires at least one object to be selected in another view such as in the Netlist view Use the popup menu Object_type Properties command to open the Properties view See Using the Properties View page 144 Navigating Views Each opened view in the viewing environment has a
392. input side to use this register the Information registers register should be synchronously controlled Virtex 4 only DSP48 output DPOP DSP48 has a register on the output side using this pipeline Information pipelining mechanism improves performance Virtex 4 only DSP48 DMOP DSP48 output is not pipelined Pipelined output improves Warning multiplier performance output pipelining DSP48 input DPIP DSP48 has a register on the input side using this pipeline Information pipelining mechanism improves performance Virtex 4 only DSP48 cascade DPCA DSP48 cascade check Warning DSP48 DPREG DSP48 asynchronous feedback Warning asynchronous RAMB16 DRC Table B 8 RAMB16 DRC Rule Name Rule Abbrev Rule Intent Severity RAMB16 output RBOR RAMB16 has a register on the output side to use this register the Information registers register should be synchronously controlled Virtex 4 only RAMB DRC Table B 9 RAMB16 DRC Rule Name Rule Abbrev Rule Intent Severity RAMB RBRF Clock restrictions for READ_FIRST mode Warning Read first mode 424 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX FIFO DRC Table B 10 lists the FIFO DRC Table B 10 FIFO DRC Floorplanning DRCs Rule Name Rule Abbrev Rule Intent Severity FIFO FSYN Check for synchronous FIFO Warning Synchronous Netlist DR
393. ion Simulation sources are used for behavioral and timing simulation in ISim See Performing Behavioral Simulation page 188 and Performing Timing Simulation page 361 for more information The PlanAhead tool stores simulation source files in simulation file sets that display in folders in the Sources view and remotely referenced or stored in the local project directory The simulation set lets you define different sources for different stages of the design For example one simulation source to provide stimulus for behavioral simulation of the RTL design or a module of the design and a different test bench to provide stimulus for timing simulation of the implemented design www xilinx com 61 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects g XILINX When adding simulation sources to the project you can specify which simulation source set into which to add files Adding and Creating Simulation Source Files To add simulation sources to a project 1 Select either e File gt Add Sources e Add Sources from the popup menu or from the Flow Navigator The Add Sources wizard opens 2 Select Add or Create Simulation Sources and click Next The Add or Create Simulation Sources dialog box opens as shown in Figure 3 24 a Add Sources Add or Create Simulation Sources Specify dinulation spectic HOL flas or directories contains HOL flac to add to your project Crosta anew source file on f dsk and addit to your proj
394. ion al selected text from the Text Editor Unindent Selection Shift Tab e Duplicate Selection Copies the current selected yy toggle Line Comments ore text and inserts it at the cursor location Toa Block Comments Sones e Find Replace Invokes the Find field to enter a Select All Ctrl a text string to search or replace individual or all the Tabs OCCUTTENCES Find in Files Ctrl Shift F e Indent Selection Unindent Selection Inserts or Change editor style Ctrl Shift T removes a tab space on the selected line or lines E insert Template 158 Toggle Line Comments Lets you select a line or group of lines and insert a line comment symbol at the start of the line This command removes the line comment symbol if the selected lines are already commented Note The comment symbol inserted is dependent on the type of file being edited Toggle Block Comments Adds or removes a block comment at the start and end of a selected block of text This command is useful for commenting out a section of text in a single command Select All Selects all the text in the Text Editor Tabs Specifies that the Text Editor should use the tab character t or use a specified number of spaces when a tab is inserted This allows the text file to be portable to third party applications that might not properly handle tab characters Find in Files Invokes the Find in Files dialog box for you to enter text strings fo
395. ions Verilog Options verilog_version Verilog 2001 Generics Parameters Options j Top Library work Figure 11 22 Timing Simulation Language Options The Timing Simulation Language Options tab contains three language options e Verilog Options Specify Verilog Search Paths Macro definitions Uppercase identifiers and Verilog2001 language standard e VHDL Options Specify VHDL Generic values e Top Library Specify the top level module library name The PlanAhead tool automatically determines this library but you can specify a different library to locate the top module Netlist Options The Netlist Options tab as shown in Figure 11 23 page 365 provides options to control the NetGen program for generating a Verilog or VHDL netlist from the implemented FPGA design 364 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Performing Timing Simulation G Simulation Options i Specify Options For timing simulation Top Module Design Under Test top Launch Options Language Options of mt insert_pp_buffers fn a sdf_anno tm extid sdf _path ism More Netgen Options Select an option above to see description of it Figure 11 23 Timing Simulation Netlist Options The commands and options on this tab specify how NetGen writes the simulation netlist PlanAhead User Guide ofmt Specify the output format for the simulation netlist
396. ions that are selected to define the project Click Finish to create and open the project The PlanAhead tool imports the RTL source files constraint files and run settings from the ISE project and creates a project file in the specified directory The PlanAhead tool writes a summary of the import process to the import_ise_summary txt log file in the new project directory You can review the steps used in creating the project in this summary file Managing Projects 48 Opening Existing Projects You can open existing projects in the PlanAhead tool As a project is opened the PlanAhead tool restores the state of the project from the time the project was closed The project state includes the current source file order disabled and enabled source files active and target constraint files and the state of synthesis simulation and implementation runs To open a project use one of the following methods e Inthe Getting Started page click Open Recent Project or Open Project e Select File gt Open Project 2 e Click Open Project toolbar The Open Project dialog box lets you select a project file ppr The File Preview window in the Open Project dialog box displays information about the currently selected file To open a project from within Windows Explorer double click a project file www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Managing Projects Opening Multiple Projects To open
397. iple Netlist Designs using combinations of these inputs The design is loaded into memory and can be analyzed in either the I O Planning view layout or the Design Analysis view layout Opening a Netlist Design To open a Netlist Design select either e Open Netlist Design button EF e The Open Netlist Design command in the Netlist Design pulldown menu of the Flow Navigator You can open the active synthesized netlist with the active constraint set and the target device or specify an alternative constraint set and target device to be loaded with the design You can enter e Design Name Enter a name to display in the view banner The design is stored in memory during the session only e Constraint Set Select an existing constraint set to be opened against the netlist e Part Select a target part Figure 2 5 page 29 shows the open Netlist Design view 28 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Working with Designs G project_cpu_hdl C PlanAhead_Install planAhead testcases P lanAhead_Tutorial Projects project_cpu_hdl project_cpu_hdl ppr PlanAhead 13 3 0R0 File Edit Flow Tools Window Layout view Help feo XO Or HADGOSRKEZ Project Manager RTL Design gt Synthesize Netlist Design F Resource Estimation E Power Estimation Netlist Design netlist_1 c Netlist AE GA top E5 Nets E Primitives H E cpuEngine or E fftEngine f m mgt
398. ironment page 207 for more information The PlanAhead tool lets you make debug net selection by picking a set of nets or buses in the Netlist view or the Schematic view and either selecting Add to ChipScope Unassigned Nets or dragging and dropping the net from the Netlist view in the Unassigned nets folder You can perform net selection by selecting nets or buses in any view including the Schematic view The ChipScope view is shown in Figure 12 4 ChipScope Og x a 2 6 a E a E a Name S E u_icon chipscope_icon_v1 S cs_ila_O chipscope_ila_v1 ae CLK 1 HG TRIGO 9 Hf TRIIGI 8 c Unassigned nets 1 amp validForEgressFifo 1 validForEgressFifo 9 lt gt Figure 12 4 Unassigned Nets List in ChipScope Window There is also a net selector built into the Setup ChipScope wizard 372 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Debugging the Design with ChipScope You can also identify the nets to debug prior to Synthesis Nets marked for debug in HDL or constraint files are automatically listed in the ChipScope view under the Unassigned nets folder and in the Set up ChipScope wizard The procedure for marking nets for debug depends on whether you are working with an RTL source based project or a synthesized netlist based project For an RTL netlist based project e Using Xilinx Synthesis Technology XST you can optionally mark nets for debug using the ma
399. is an example code snippet INST receiver uartInst G_98_1 LOC SLICE_X49Y69 BEL constraints result in a LOC constraint and a BEL constraint being assigned to the instance in the saved and exported UCF files BEL constraints assign a logic element to a specific site within the CLB SLICE as shown in the following example code snippets INST channel receiveRE 8 BEL FFX INST channel receiveRE 8 LOC SLICE_X59Y2 Assigning Site Location Placement Constraints LOCs You can place a leaf level primitive instance such as a LUT block RAM or flip flop into a specific device resource site by dragging it from the netlist tree and dropping it into a specific site When you place instances into sites the PlanAhead tool adds Instance LOCs to the exported UCF files for ISE The locations are assigned as fixed and locked during subsequent ISE attempts To place a primitive instance into a device site click Create Site Constraint Mode The dynamic cursor does not allow instance placement to an illegal site or to a site that is already occupied A legal placement site is indicated when the dynamic cursor changes from a slashed circle to an arrow or diamond www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Working with Placement LOC and BEL Constraints Figure 10 22 shows the placement of a logic element into a specific SLICE when you use Create Site Constraint Mode The lo
400. is Flow When you invoke the PlanAhead tool from ISE Project Navigator the ISE Integration mode displays Understanding the Context Sensitive Cursor PlanAhead User Guide The cursor changes based on the available command mode When the cursor changes to a e Horizontal vertical or diagonal stretch bar symbol you can stretch Pblock edges and Windows view borders e Hand symbol you can move Pblocks or instances e Cross symbol you can draw rectangles for zooming in defining pin assignment areas or drawing Pblock rectangles e Slashed circle symbol you are dragging objects are over illegal placement sites e Move point to point symbol you are dragging objects over legal placement sites www xilinx com 109 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX Selecting Marking and Moving Objects The PlanAhead tool provides a few methods for selecting objects You can select a single object Click the primary object to select it in the current view When selected in any view objects also become cross selected as appropriate in other open views and in other open designs of the same project When you have selected a primary object the PlanAhead tool can also select any connected or associated secondary objects This feature can be configured through selection rules See Setting Selection Rule Options page 165 for more information You can select multiple objects Click to select the
401. is and Constraint Definition Using the Netlist Design Environment Viewing and Reporting Resource Statistics Exploring the LOGIC is isi cs resse dvemyaryuaeete rikal cregenaeerew Inserting ChipScope Debug Cores 0 00005 Defining Timing Constraints 0 0 2 e eee Running Timing Analysis 0 00 c cece eee eee Using Slack Histograms 0 00 00 c cece cece eee eee Analyzing Clock Interactions 0 00 cece eee Defining Physical Constraints 00 eee Running the Design Rule Checker DRC Chapter 8 I O Pin Planning I O Pin Planning Methodology 0 00008 Using the I O Planning view layout Viewing Device Resources 49oksd irene vende ieee ner ecanes nee Defining Alternate Compatible Parts Setting Device Configuration Modes 002 Defining and Configuring I O Ports Disabling or Enabling Interactive Design Rule Checking Placing VO Ports oeiee eiieeii Minune canes ned eunu lke nies Placing Clock Logie vas iircecissicersaseasseeapepeenecr shea Validating I O and Clock Logic Placement Exporting I O Pin and Package Data 06 www xilinx com XILINX PlanAhead User Guide
402. is reduced to a single RLC transmission line model applied to all pins and defined in the Package section of the IBIS file e Maximum length of signal names Truncate signal names to the specified limit e 40 Truncate signal names to 40 characters supported by IBIS version 4 2 as the default e 20 Truncate signal names to 20 characters e Unlimited Do not truncate signal names e Updated generic IBIS model file Optionally provide an IBIS model file for the device This is used to override the IBIS models found in the installation under the parts directory Note The IBIS model file is required for devices that do not have IBIS models included with software installation www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using Noise Analysis Predictors e Updated parasitic package data file Optionally provide a parasitic package file pkg file to use for per pin extractions This is used to override the parasitic package file found in the installation hierarchy under the parts directory Note The parasitic package file is required for devices that do not have IBIS models included with software installation Using Noise Analysis Predictors The PlanAhead tool provides analysis of the switching noise levels associated with the I O of different devices This analysis can be accessed by clicking the Run Noise Analysis command from Flow Navigator or from the Tools gt Run Noise
403. isplay until after timing analysis Annotating Slack Fanout and Values onto Schematic Pins To access the PlanAhead Options dialog box 1 Select Tools gt Options and select the Schematic options 2 To annotate these values you must first set the Attribute type field to Pin 3 Select from the Available Attributes to annotate on the left of the following dialog box and use the arrow indicators to move them to the right side which is labeled Displayed Attributes and click OK www xilinx com 141 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment g XILINX Figure 4 52 shows the PlanAhead Options dialog box G PlanAhead Options Schematic Attribute Types Pin ai Available Attributes Displayed Attributes Selection Rules Slack Shortcuts Strategies Window Behavior Cancel Apply Figure 4 52 PlanAhead Options Schematic Pin Annotation Figure 4 53 shows an example of the resulting pin annotation e SL 74 82 FO 2 S SPECIAL_SVGA_TI OSL 73 60 FO 2 SL 73 60 FO 2 Cl SL N P D x Ce Me RA it RA Ri we A AR ee CR MUXCY BS fl Package Device l Schematic x 1 Figure 4 53 Annotated Pins in the Schematic View v Annotating Cell References and Instance Equations onto Instances The PlanAhead Options dialog box Schematic options let you tag instances with Cell References and Instance Equation values 142 www xilinx com PlanAhead User G
404. isplay Percentage of Logic Selected in Module When you double click on a module in the Hierarchy view a sub hierarchy for any sub modules displays also To select logic parent modules for Pblock assignment in this view use the Select Primitive Parents command 152 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Using Common Views Using the I O Ports View The I O Ports view is used to create configure and place I O ports onto I O sites in either the Package view or Device view The I O Ports view shows the I O signal ports defined in the design Creating I O Ports In an I O Planning project you can create ports manually or import a port list from a CSV file or a UCF Creating projects with an RTL Header RTL sources or synthesized netlists populates the I O Ports view with the I O ports defined in the design To open the I O Ports view select Window gt I O Ports Figure 4 65 shows the display Name Dir Neg Diff Pair Site Bank I O Std Yeco Vref Drive Strength SlewType PullType Phase 5 5 All ports 144 tH Dataln_pad_0_i 8 Input LYCMOS25 2 5 12 SLOW PULLUP default Bs Dataln_pad_1_i Input LYCMOS25 25 12 SLOW PULLUP default H A DataOut_pad_0_o Output LYCMOS25 2 5 12 SLOW PULLDOWN default H LineState_pad_0 i 2 Input LYCMOS25 2 5 12 SLOW default Qe LineState_pad_1_i 2 Input LYCMOS25 2 5 12 SLOW default t A OpMode_pad_O_o 2 Output LYCMOS25 25 12 SLOW default fH OpMode_
405. isplay and compare the various multifunction pins You can edit cells which have editable values directly by entering text or selecting a value from drop down menus Figure 8 6 shows an example of the Package Pins view PlanAhead User Guide Prohibit Port NO Std Dir Ycco Bank Type al Diff Pair Clock Voltage Config System Monitor Gigabit 1 0 Low Cap Min Trace Dly ps Max T Contig 161 66 Config 157 16 Config 159 71 Config 168 88 Config 159 30 Config 167 15 Gigabit MGTTXNS 77 24 Gigabit MGTRXNS 89 00 Gigabit MGTTXP3 77 03 Gigabit MGTRXP3 88 81 Figure 8 6 Package Pin Tab The Type column identifies multifunction pin types Other columns contain information about logic or configuration modes involving multifunction type pins The Package view identifies multifunction pins using specific symbols representing their available function e Global clock pins are grey hexagrams e Vref pins display with a small power icon The Package View Layers command provides a legend of the icons used for multifunction pins See Setting Visible Package View Layers page 135 for more information Designs that contain Gigabit Transceivers GTs memory controllers or PCI logic have information in the Package Pin table that identifies conflicting multifunction pins Many device configuration modes use multifunction pins Select Tools gt I O Planning gt Set Configuration Modes to set the required device configuration mod
406. it gt Generates a verbose report The optional limit is used to limit the number of items reported for each timing constraint in the report file The value of limit must be an integer from 1 to 32 000 inclusive If a limit is not specified the default value is 3 e 1 lt limit gt Limits the number of items reported for each timing constraint in the report file lt limit gt must be an integer from zero to 2 billion inclusive The default value is 3 346 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Analyzing Timing Results u lt limit gt Reports delays for unconstrained paths lt Jimit gt is an integer from one to 2 billion inclusive The u option adds a constraint to all unconstrained paths in the design to include them in the timing analysis This constraint performs a default path enumeration on any paths for which no other constraints apply The default path enumeration includes circuit paths to data and clock pins on sequential components and data pins on primary outputs stamp lt filename gt Generates a pair of STAMP timing model files lt filename gt mod and lt filename gt data that characterize the timing of a design tsi lt filename tsi gt Generates a Timing Specification Interaction TSI report also known as the Constraint Interaction report The TSI report can be used to understand which timing constraints take precedence when multiple timing constrain
407. ition The design analysis and constraint definition features available in the PlanAhead tool are typically performed by opening a Netlist Design before running Implementation However many of the analysis and constraints features described in this chapter are available for implemented designs as well In the Netlist Design environment you can e Perform I O Planning e Analyze aspects of the design e Validate resource and timing estimates e Run Design Rule Checks DRCs listed in Appendix B PlanAhead DRCs e Define physical and timing constraints for the Xilinx ISE Design Suite The PlanAhead tool design tasks performed in the Netlist Design environment are e Inserting ChipScope Pro Analyzer debug cores see Debugging the Design with ChipScope page 370 e Defining partitions for Design Preservation and Partial Reconfiguration on netlist based projects see Using Hierarchical Design Techniques in Chapter 13 Using the Netlist Design Environment PlanAhead User Guide The PlanAhead tool provides an environment to analyze the design from several different perspectives and to apply constraints to the design prior to implementation When you open a Netlist Design the software loads the synthesized netlist the active constraint set and the target device See Using the Netlist View page 148 for more information Create or open a Netlist Design using one of the following e Select Flow gt Netlist Design e Click
408. ject or device resource The Properties view is dynamic by default as you select an object its properties are automatically displayed in the Properties view The displayed name of the Properties view changes to reflect the selected object For instance the view will be called BEL Properties view when a BEL is selected or Clock Region Properties view when a clock region is selected Note When selecting multiple objects the Properties view will display the properties of the last object selected To open the Properties view e Use the Windows gt Properties command from the main menu e Click the Properties toolbar icon e Select an object and use the Object Properties command in the popup menu The Properties view displays the various properties associated with a selected object using tabs to organize information under different categories The specific tabs that are available and the information they display is dependant on the type of object currently selected Figure 4 57 page 145 for instance shows the various tabs of the Instance Properties view currently displaying the Attributes tab of the selected instance www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX e ZSE Msub_xReg 15 _uReg 15 _sub_7_OUT lt 31 0 gt 1 ACASCREG ADREG ALUMODEREG AREG AUTORESET_PATDET B_INPUT BCASCREG BEL BREG BUS_INFO CARRYINREG CARRYINSELREG CLASS CREG DREG INMODEREG 15_BEL_FIXED
409. jects You have access to design analysis and constraint definition capabilities at each stage of the design flow including elaborated Register Transfer Level RTL design synthesized netlist design and any of the implemented design runs Design flows supported by the PlanAhead tool include RTL to Bitstream Use the PlanAhead tool to manage the entire FPGA design process from RTL development IP customization synthesis and implementation through to programming the device You can add Verilog and VHDL sources previously defined and configured intellectual property IP cores and physical and timing constraints to a project You can experiment with synthesis simulation and implementation options and constraints to help meet your design objectives Synthesized Netlist to Bitstream The PlanAhead tool manages netlist designs from implementation to device programming You can add synthesized netlists netlist based IP cores and constraints to a project You can experiment with implementation options and constraints to help meet your design objectives Device Exploration and I O Pin Planning The PlanAhead tool provides an I O Planning environment to analyze the device resources and visualize the relationship between the FPGA and system level designs Proper clocking and I O planning can improve device performance and routability Early I O planning can also improve PCB routing signal integrity and the performance of the overall system
410. jects handling without the need for special iteration commands like the foreach_in_collection which is handled with the Tcl built in foreach There are a few nuances with respect to large lists particularly in the log files and the GUI Tcl console Typically when you set a Tcl variable to the result of a get__ command the www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX First Class Tcl Objects and Relationships entire list is echoed to the console and to the log file For large lists this is truncated when printed to the console and log to prevent memory overloading of the buffers in the tool What is echoed is the list printed to the log and console is truncated and the last element appears to be in the log and console however the actual list in the variable assignment is still correct and the last element is not an error An example of this is querying a single cell versus every cell in the design which can be large get_cells inst_1 inst_1 get_cells hierarchical XST_VCC XST_GND error readIngressFifo wbDataForInputReg fifoSelect_0 fifoSelect_1 fifoSelect_2 fifoSelect_3 Sset x get_cells hierarchical XST_VCC XST_GND error readIngressFifo wbDataForInputReg fifoSelect_0 fifoSelect_1 fifoSelect_2 fifoSelect_3 Slindex x end bf tClk_BUFGP bufg Sllength x 4454 In this example all four thousand cells were not printed to the console and the list was truncated with a
411. kage View Layers command in the toolbar to hide the Layer Slideout when you have finished hiding or displaying specific layers Opening Multiple Package Views You can open Multiple Package views simultaneously Moving the cursor within the Package view shows the I O pin coordinates actively on the top and left sides of the view Additional I O pin and bank information displays in the Information bar located at the bottom of the environment The Package view highlights the active object Printing the Package View You can print the Package view using the File gt Print command that prints the current viewable area To print the entire Package view zoom to fit and then print Using the Schematic View You can generate a Schematic view for any level of the logical or physical hierarchy view You can select a logic element in an open view such as a primitive or net in the Sources view and use the Schematic command in the popup menu to open the schematic view for the selected object In the Schematic view you can view design interconnect hierarchy structure or trace signal paths for either the elaborated RTL Design synthesized Netlist Design or Implemented Design www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX PlanAhead User Guide Using Common Views e See Analyzing Synthesis Results in Chapter 6 for more information about analyzing RTL netlist e For more information about synthesized netlist a
412. ks Running the Design Rule Checker DRC The PlanAhead tool contains a set of batch DRC commands that can help verify design integrity prior to running the ISE software The rules are categorized by type of logic checks being performed Many different types of checks are available These checks are designed to provide an early indication about potential design implementation issues The final validation step to ensure the design is DRCs compliant is to run the design through the ISE implementation tools Running I O Port and Clock Logic DRCs Many of the DRC rules are related to I O pin assignment and clock logic For information on running I O Port and lock logic related DRCs see Chapter 8 I O Pin Planning and Appendix B PlanAhead DRCs Running Netlist and Constraint DRCs To run DRCs on the Netlist Design to validate netlist and constraint condition 1 From the Flow Navigator or Tools menu select the Run DRC command The Run DRC dialog box opens as shown in Figure 7 33 page 249 2 View or edit the Results Name field Enter a name for the results for a particular run for easier identification during debug in the DRC Violations browser Enter an Output File name to create a report text file This is an optional field In the Rules to Check group box use the check boxes to select the design rules to check for each design object For a description of each rule see Appendix B PlanAhead DRCs e Expand the
413. ks and LOC constraints are assigned in the design the results of the timing analysis becomes more accurate although still containing some estimation of path delay As the implementation of the design is completed the timing analysis includes the actual routed path delays from the implemented design The static timing analysis engine in PlanAhead is intended for timing estimation only and should not be used for timing sign off For sign off timing you can run TRACE on an Implemented Design incorporating both the circuit delays and the path delays of the placed and routed design See Running TRACE on an Implemented Design page 345 for more information Using the Report Timing Command PlanAhead User Guide G Report Timing Results Name results_1 Options Advanced Timer Settings Start Points From Through Point Groups 1 Through 2 Through 3 Through 14 Through Fewer End Points To Command report _timing delay _type max path_type full_clock_expanded rr Open in a new tab Figure 7 12 Report Timing Dialog Box Perform a timing analysis using one of the following methods e From the main menu click Tools gt Timing gt Report Timing e From the Flow Navigator click Report Timing from the Netlist Design menu www xilinx com 219 UG632 v13 4 January 18 2012 220 Chapter 7 Netlist Analysis and Constraint Definition XILINX The Report Timin
414. l objects e View gt Unhighlight Color to unhighlight based on color e Unhighlight All toolbar button mf Setting Object Selections in the Workspace Views Object selection is set in the PlanAhead Options dialog box available when you go to Tools gt Options For more information about setting object selections see Customizing Display Themes page 163 Highlighting Selected Objects You can highlight objects with color for display purposes Highlighting remains until you clear all highlights for the floorplan For more information on highlighting see Highlighting Selected Objects page 114 Marking and UnMarking Selected Objects You can place a Mark symbol for all selected objects Select the objects to mark and click either e View gt Mark e Mark in the popup menu Select the UnMark All toolbar button to remove all marks Locking Placement for Future Implementation Runs When you import placement results from ISE placed instances display as unfixed in PlanAhead Placed instances that were constrained with LOC constraints prior to Implementation are referred to as fixed and display with a different color Using the Fix Instances Command To lock placement in place for subsequent runs select the logic then select Fix Instances You can use this capability to help ensure consistent implementation results After you have saved the implemented design the fixed logic receives LOC and BEL constraints in the UCF and can
415. l supports adding module level NCF files into a project These files are typically associated with an IP core The module constraint file must have the same name as the module to which it applies to be recognized and applied For example xyz ngc must have a netlist constraint file named xyz ncf When you add the NCF to the project the PlanAhead tool automatically makes the association to the proper netlist module 60 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Managing Simulation Sources Note NCFs are processed only if the name matches the name of the module level netlist In projects that have constraints defined in both top level UCF files and module level NCF files the following rules apply 1 Ifthe constraints overlap UCF overrides NCF and any embedded netlist constraints 2 The NCF overrides any embedded constraints You can add NCF files to the project in the New Project wizard or use the Add Sources option An NCF that is in the same directory as an RTL source file loaded into a project is automatically added to the Add Constraints dialog box The PlanAhead tool also loads constraints automatically when an NGC format core has embedded timing constraints as is often the case with EDK and some CORE Generator software cores The ngc2edif command extracts timing constraints before passing the EDIF netlist to the PlanAhead tool This allows the PlanAhead tool to recognize the constraint
416. lO pdf Spartan 6 FPGA Configuration User Guide UG380 http www xilinx com support documentation sw_manuals xilinx13_4 ug380 pdf Spartan 6 FPGA SelectIO Resources User Guide UG381 http www xilinx com support documentation sw_manuals xilinx13_4 ug381 pdf Spartan 6 PCB Design Guide UG393 http www xilinx com support documentation sw_manuals xilinx13_4 ug393 pdf Virtex 4 FPGA Configuration User Guide UGO71 http www xilinx com support documentation user_guides ug071 pdf Virtex 5 FPGA Configuration User Guide UG191 http www xilinx com support documentation user_guides ug191 pdf Virtex 6 FPGA Configuration User Guide UG360 http www xilinx com support documentation user_guides ug360 pdf Virtex 6 FPGA SelectIO Resources User Guide UG361 http www xilinx com support documentation sw_manuals xilinx13_4 ug361 pdf www xilinx com 435 UG632 v13 4 January 18 2012 Appendix E Additional Resources XILINX ChipScope Documentation ChipScope Pro Software and Cores User Guide UGO029 http www xilinx com support documentation sw_manuals xilinx13_4 chipscope_pro_sw_cores_ug029 pdf Debugging with ChipScope UG677 http www xilinx com support documentation sw_manuals xilinx13_4 PlanAhead_Tutorial_Debugging_w_ChipScope pdf Using Xilinx ChipScope Pro ILA Core with Project Navigator to Debug FPGA Applications UG750 http www xilinx com support documentation sw_manuals xilinx1
417. lanAhead_Tutorial Projects project_bft_core _hdl project_bft_core_hdl ppr PlanAhead 13 1 BEE Fil Edit Flow fools Layout View Help Q Search commands Pu8KIEC Gls Me S Implemented Project Manager Project Manager Lb he x Project Settings pours x E Project Summary x om x a t oe i ae ol F B Add Sources arg a Project Settings Edt 2 E Project State N 3 Design Sources 9 AF Ip Catalog GB Verilog 2 Project Name project_Hft_core_hdl Status Implemented p Elaborate S work 2 Product Family Virtex6 Messages errors e async_fifo v Default Part xc6vlx75 f784 3 2 critical warnings T Behavioral Simulation Dion bye FifoBuffer v Top Module Name bt Z1 warnings Project Summary S bFtLib 6 Go To Messages n see E e core_transform vhdl oral ery elise o bft_package vhdl penats B Eep Next Step Generate Bitstream Synthesize round_2 vhd De Compilation az round_1 vhdl Netlist Design work 1 Synthesis Implementation o bft vhdi al Part xc vlx7Stff784 3 Part xc6vix7Stff784 3 gt F gt er S E Strategy AreaReduction Strategy ISE Defaults eTa A Sources KJ Templates Util 4 0 Util 4 0 ee sare FMax 211 833 MHz FMax 133 156 MHz x P roperties _ Implemented Design pi a Timing Score 0 k x Unrouted 0 ap Program and Debug E Resources Show Table 2 RTL Estimation Synthesis Estimation Netlist Estima
418. lation tab or e Window gt Compilation e Running xst with args ifn bft xst ofn bft srp intstyle ise eading design bft prj ing alyzing Verilog file C Plandhead Projects PlanAhead Tutorial Tutorial_C Parsing module lt async_fifo gt Analerine Varilor fila Cs sDlianihasA Draianto Dlanihaad Tutarial TMuitarial F Tel Console Messages Design Runs gt 1 0 Ports Figure 4 10 Compilation View The output displays in a continuous scroll able format and is overwritten when new commands are run Use the Pause output button to scroll back or read reports while commands are running Using the Tcl Console The Tcl Console view displays messages from previously executed Tcl commands The PlanAhead tool writes messages to the planAhead 1og file Command errors warnings and successful completion echo to this window also The status of design netlists and constraints that open in the Netlist Planner and Results Viewer display also To invoke the Tcl Console view select Window gt Tcl Console Figure 4 11 shows the Tel Console add files scan_for_includes C PlanAhead_Install planAhead testcases PlanAhead_Tutorial Sources hdl asyne_fifo add files fileset sim 1 scan_for_includes C PlanAhead_Install planAhead testcases PlanAhead_Tutorial Sources h add files scan_for_includes C PlanAhead_Install planAhead testcases PlanAhead_Tutorial Sources hdl bftLib _set_property librar
419. lay Type Delay Cumulative Location Logical Resource 0 000 0 000 E AB19 D gt usbclk net fo 0 0 000 0 000 E A819 D usbCik_ibuf ibufg I IBUFG 0 818 0 818 E AB19 GusbClk_ibuffibufg o net fo 1 0 000 0 818 E BUFGCTRL_X0Y9 D usbCik_ibuf bufg I BUFG 0 250 1 068 E BUFGCTRL_X0Y9 GQ usbClk_ibuf bufg o net fo 407 2 033 3 101 E RAMB36_X2 1 pblock_usbEngine0 D usbEngineO usb_dma_wb_in BU2 U0 gen_fifo18_36 fafifo18_36 Fblkjinst_few k1 Total 3 101 3 101 Data Path Delay Type Cumulative Location PBlock Logical Resource FIFO36_EXP 0 818 0 818 E RAMB36_X2Y1 pblock_usbEngine0 lt usbEngine0 usb_dma_wb_in BU2 UO gen_fifo18_36 fgfif018_36 fblk inst_Ffew k1 1 net fo 40 1 520 2 338 E SLICE_X19Y8 pblock_usbEngine0 usbEngine0 u2 wsel I10 LUT6 0 094 2 432 E SLICE_X19 8 pblock_usbEngineO lt usbEngineDju2 wsel O net fo 42 0 381 2 813 E SLICE_X18Y9 pblock_usbEngine0 D usbEngineO u2 sram_we I4 LUT 0 094 2 907 E SLICE_X18Y9 pblock_usbEngine0 lt usbEngineO u2 sram_we O net fo 4 0 430 3 337 E RAMB36_X1 1 pblock_usbEngine0 gt usbEngine0 usbEngineSRAM BUZ UO blk_mem_generator valid cstr ramloop 0 ram RAMB18 0 624 3 961 E RAMB36_X1Y1 pblock_usbEngine0 G usbEngine0 usbEngineSRAM BUZ UO blk_mem_generator valid cstr ramloop 0 ram Total 3 961 3 961 Destination Clock Path Delay Type Delay Cumulative Location Logical Resource 0 000 0 000 E AB19 D usbclk net fo 0 0 000 0 000 E A819 D usbCik_ibuf ibufg I IBUFG 0 818 0 818 E AB
420. layout provides an interface to analyze the design and device I O requirements and to define an I O pinout configuration or pinout that satisfies the requirements of both the PCB and the FPGA designers The PlanAhead application lets you create I O port signals I O Planning project only and import I O port lists from Comma Separated Value CSV files User Constraint Files UCF or Register Transfer Level RTL files This allows for early pinout definition to eliminate pinout related changes that typically happen late in the design cycle Often designers are hindered by a non optimal pinout that causes further delays when trying to meet timing and signal integrity requirements By considering the data flow from Printed Circuit Board PCB to FPGA die you can achieve optimal pinout configurations quickly thus reducing internal and external trace lengths as well as routing congestion I O Pin Planning Methodology I O pin planning is a complex process involving design groups that include PCB designers FPGA designers and the System designer each with their own specific set of concerns and requirements This chapter focuses on using the PlanAhead tool environment to perform device exploration and I O pin planning and related tasks For more information about I O pin planning methodology see the Pin Planning Methodology Guide UG792 cited in Appendix E Additional Resources I O Planning Stages PlanAhead User Guide The PlanAhead
421. lected bin are reported in the histogram table e Unfilter All The Unfilter All command on the histogram toolbar deselects all selected bins and restores the table to display the endpoints Ld Histogram Popup Menu Commands The right mouse button opens a popup menu that features several command for manipulating the histogram and endpoints display The following commands can be found on the popup menu e Report Timing Generates a new timing report on the endpoints in selected bins using the Report Timing command This opens the Report Timing command for the currently selected path endpoints but PlanAhead User Guide www xilinx com 239 UG632 v13 4 January 18 2012 Chapter 7 Netlist Analysis and Constraint Definition XILINX runs a full path timing analysis based upon the options in the Report Timing dialog box Note The Report Timing command is only available on the histogram popup menu when one or more bins have been selected PlanAhead issues a warning that it might take some time to run when a large number of path endpoints are included in the selected bins e Refresh Histogram Opens the Generate Slack Histogram dialog box for you to specify new options and re run the Generate Slack Histogram command e View Provides access to a submenu of commands which allow you to change the display of the histogram This submenu contains the following options e Zoom In Increases the zoom level e Zoom Out
422. lecting e Tools gt Simulation gt Behavioral Simulation from either from the main menu bar on an RTL design or e Flow Navigator gt Behavioral Simulation The PlanAhead tool opens the Launch Behavioral Simulation dialog box as shown in Figure 5 10 page 189 188 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Performing Behavioral Simulation G Launch Behavioral Simulation e 1 Launch Sim Simulator using an existing simulation source set or a new simulation set Settings Simulation Set Figure 5 10 Launch Behavioral Simulation The Launch Behavioral Simulation dialog box contains the following fields Simulation Set Specify the name of the simulation run This lets you create different simulation runs with different design hierarchies and different options Simulation Top Module Name Specify the top level of the design This field is automatically populated with the defined Simulation Top Module Name but you can specify a different top module to allow simulation from different levels of the hierarchy or to elaborate different variations of the design Click the file browse button to view top modules found in the design Options Opens the Simulation Options dialog box as shown in Figure 5 11 page 190 and Figure 5 12 page 192 Launch Runs the ISim compile and elaboration steps and launches Sim in GUI mode Cancel Closes the dialog without launchin
423. les PlanAhead User Guide When selecting an object associated or connected objects might also become selected For example selecting a Pblock can also select the netlist instances assigned to the Pblock Selecting a Port object may also select the Pin object of the port Use the Tools gt Options gt Selection Rules command to control what secondary elements are selected when you select a primary object Figure 4 27 page 112 shows the Selection Rules dialog box www xilinx com 111 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment g XILINX G PlanAhead Options Selection Rules From To Description Instance Phloc elect the Pblock that contains the selected instance a Pblock Instance Select all instances contained by selected Pblock E Pblock A Rectangle Select all rectangles comprising the selected Pblock Site Package Pin Select the package pin with which the selected I O site is associated P Package Pin Site Select the I O site with which the selected package pin is associated E RPM E Instance Select all instances belonging to the selected RPM D Pin E Instance Select the instance to which the selected pin belongs am IJO Bank D I O Port Select all top level ports assigned to the selected I O bank amp Bus Net Net Select all scalar nets belonging to the selected bus net P Path E Instance Select all instances belonging to the selected path TO Port Instance Select all pad instances conn
424. leting placement constraints from the current floorplan You can clear instance placement I O port placement or both What type of placement do you want to clear Instance placement Yo port placement Both PlanAhead To continue click Next Figure 10 25 Clear Placement Constraints 334 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX PlanAhead User Guide Working with Placement LOC and BEL Constraints From the Clear Placement Constraints wizard specify the type of placement constraints to remove Instance placement I O port placement or Both Click Next to continue The Unplace Instances dialog is opened as shown in Figure 10 26 G Clear Placement Constraints Unplace Instances Specify the primitive instances to be unplaced Instances to Unplace Unplace 54 selected instance Unplace all except for 54 selected instances Unplace all instances Do not unplace any instances Figure 10 26 Unplace Instances If you have selected instances prior to using the Clear Placement command you are prompted to specify which instances to unplace e Unplace the selected instances e Unplace all but the selected instances e Unplace all instances regardless of the selected objects e Do not unplace any instances if you no longer want to unplace instances Note If you have not previously selected instances step 2 is skipped and you are presented with a list of in
425. line of code highlighted e Expand or collapse the messages by toggling the tree widgets in the view or by clicking the Expand all or Collapse all icons on the sidebar menu e Use the checkboxes in the banner of the Messages view to hide or display the Errors Critical Warnings Warnings and Info Messages PlanAhead User Guide www xilinx com 97 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX e Use the Show Search icon in the sidebar menu to search for and display specific A messages This command is also available through the Alt keyboard shortcut e Consolidate the list by clicking Group duplicate messages in the sidebar menu By default messages written to the Messages view are line wrapped to allow the display of the whole message within the message window When line wrap is enabled the lines adjust to fit the width of the Messages view If the Messages view is resized line wrapping is adjusted accordingly If line wrap is disabled the messages are written to a single line regardless of the width of the Messages view You can enable or disable the line wrap function using the right mouse popup menu Wrap Messages command as shown in Figure 4 8 176 info messages Search For Answer Record 360 1 warning clock signals were not automatically buffered by info messages v Wrap Messages 3 Copy Message _DEYICE is not allowed on symbol fifo_36_bl_1 fifo_36_bl_1 of type FIF
426. linked into a simulation executable named after the top level module specified in the ISim Launch dialog box When the ISim executable is complete the PlanAhead tool launches the simulator The following code snippet is an example of the command execution INFO Runs 8 Fuse completed INFO Runs 10 Launching ISim INFO Runs 11 Running C project_cpu_hdl project_cpu_hdl sim sim_1 top exe intstyle pa gui tclbatch ISim cmd wdb wdb_testl wdb view wcfg_test1l wcfg The simulation executable runs with options specified in the Launch Options tab The PlanAhead tool launches ISim with the gui option which opens the ISim user interface for you to interactively simulate the design For more information about running ISim through the GUI see the Sim User Guide UG660 cited in Appendix E Additional Resources Figure 5 13 page 193 shows the ISim GUI www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Performing Behavioral Simulation B isim 0 76 Default wcfe ea File Edit View Simulation Window Layout Help 8x De st Hoo Mim ORAM a kA E Aies iaa DD Lous 6 l Reun Instances and Processes 0 8X Objects Oex al Ae anpe Simulation Objects for top LU Wal ipl ia Instance and Process Name Di l I ua 16 1b se F top to Object Name Value A p obl all cpuclk z B std_logic_1164 st wbclk z std_logic_arith st 5 usbClk std_logic_signed s
427. local to the project Remove File from Project Deletes the selected source files from the project It also removes the files from the project disk location if the files were initially copied into the project www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX PlanAhead User Guide Using Common Views Enable File Sets the source file status to active for elaboration and synthesis You can toggle source files between enabled and disabled to define different design configurations Note The Enabled attribute can also be set from within the Source File Properties view see Viewing Source File Properties page 127 e Disable File Sets the source file status to inactive for elaboration and synthesis You can toggle source files between enabled and disabled to define different design configurations Disabled source files appear in a shaded grey color in the Sources view Move to Simulation Sources Relocates currently selected source files into the simulation set If there are more than one simulation sets the application prompts you to select the simulation set to use Move to Top Relocates the currently selected source file to the top of the source file list in the Compile Order tab The compilation and synthesis of source files is handled in the order listed in Compile Order tab from top to bottom so the order of files will affect the elaboration synthesis and simulation results The
428. location constraints of the pblock This unplaces all instances both fixed and unfixed and allows the greatest flexibility in moving Pblocks www xilinx com 321 UG632 v13 4 January 18 2012 Chapter 10 Floorplanning the Design XILINX This mode is useful for moving all of the logic assigned to a Pblock to a new region of the device and placing instances into the available sites To cancel an active move operation press Esc and the active command is terminated Note If you have difficulty moving Pblocks click Set Pblock Size to redraw the rectangle elsewhere You might need to remove placement constraints prior to moving Pblocks Resizing a Pblock To stretch the edges of a Pblock select the Pblock then move the cursor near one of its edges or corners When the cursor changes to a drag symbol click and drag to reshape the Pblock To cancel an active stretch operation press Esc Using the Set Pblock Size Command To size or resize existing Pblocks with a new rectangle use Set Pblock Size To create a new rectangle for an already existing Pblock 1 2 3 In the Physical Constraints view or Device view select the Pblock Click Set Pblock Size The cursor changes to enable you to draw a new rectangle in the desired location in the Device view fs Use the cursor to draw a new rectangle Also you can use this command to draw a rectangle for an existing Pblock with no rectangle yet defined such as
429. lock If the Pblock does not contain a site for a specific logic device element the dialog box shows the following values e Available 0 e Required The required number e Utilization Percentage of available resources used by the logic in the Pblock A value of Disabled means that the Site Type is disabled on the General tab and is not available for use If there are sites of this type required by the Pblock it is an error condition A value of No Sites means that the Pblock range on the device does not include any sites of that type Note The Pblock SLICE utilization calculation assumes maximum site utilization Realistically the maximum site utilization is rarely achieved in placement and routing tools Designers should optimize for a target utilization of approximately 80 or higher This number is a function of the device used and the characteristics of the design and its constraints PlanAhead User Guide www xilinx com 323 UG632 v13 4 January 18 2012 324 Chapter 10 Floorplanning the Design XILINX Note Pblock utilization is affected by carry chains RPM macros and the geometry of the Pblock rectangle These statistics are estimates to help guide you to a successful ISE implementation All Pblock Statistics must be taken into account when sizing Pblocks Occasionally Pblocks must be enlarged for design tools to place them successfully Placing Pblocks Based on Connectivity The PlanAhead tool
430. lock name e Pins Choose design elements based on pin name e Ports Design elements based on port name e Nets Specify nets for Through Points Matching Style Select the type of pattern matching used for filtering the design elements The field contains the following options e UCF Choose UCF based syntax for pattern matching e SDC Choose an SDC based syntax for pattern matching With Pattern The pattern expression used to filter the design elements This field is modified with the following options e Regular Expression Specifies that the search string uses regular expression syntax e Ignore Case Specifies the search string is case insensitive e Search Hierarchically This option is available for SDC pattern matching and specifies that the SDC based search pattern is applied to every level of hierarchy Of These Objects Select objects based on dialog box selection The following options are available Note This field is only available when matching style is set to SDC www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Running Timing Analysis Include Leaf Pins An SDC syntax option that specifies that the search string should only match pins components and not match pins across hierarchical boundaries Select Object Dialog Box An SDC syntax option that launches an additional object selection dialog box where you can generate recursive search
431. log opens as discussed in Defining New Modules page 39 e If you have not defined new modules the process continues with Adding IP page 41 Defining New Modules If you have specified new RTL source files to add to the project you will need to defined the Verilog or VHDL code to define the module The PlanAhead tool provides the Define Modules dialog box to facilitate creating new RTL code as shown in Figure 3 5 page 40 PlanAhead User Guide www xilinx com 39 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects g XILINX G Define Modules i Specify I O Ports to add to your source files For each port specified MSB and LSB values will be ignored unless its Bus column is checked Ports with blank names will not be written New Source Files Module Definition gpu vhd Entity name gpu mimo vhd divGen v Architecture name Behavioral I O Port Definitions Port Name Direction Bus id_Clk_In Vid_Clk_Out H_sync _sync AWADDR ARADDR lt YJHOOOO i Figure 3 5 Define Modules Dialog Box 1 The Define Modules dialog box is populated with the new source files that were defined by the Create File command as described under Creating RTL Sources page 38 Both Verilog and VHDL modules can be defined in this form 2 Start by selecting a specific module to define from the list of New Source Files 3 The following information can be provided in the Define Modules d
432. lt 0 gt 1 LUT4 E Mxor_n1835_x0 lt 0 gt 1 LUTS E Mxor_n1836_xo lt O0 gt 1 LUTS E Mxor_n1837_xo lt 0 gt 1 LUT2 El Physical Constr 4 Timing Constrai Figure 4 60 Primitives Folder in the Netlist View You can assign all the primitive logic of a module to a Pblock by assigning the Primitives folder directly to the Pblock Note Netlist updates might require reassignment of the Primitives folder to the Pblock because logic names might have changed during re Synthesis Nets or wires are placed ina Nets folder for each level of the hierarchy All of the bits of a bus are collapsed under the bus by default but you can expand buses to show each individual bit as shown in Figure 4 61 W Primitives 153 ig cpuEngine or1200_top B amp Nets 2178 H gt Mmux_wp 1 H branch_op 3 E clmode_i 1 B ff dbg_adr_i 32 dbg_adr_i 0 dbg_adr_i 1 D dbg_adr_i 2 dbg_adr_i 3 A Physical Constr A Timing Constrai Figure 4 61 Nets Folder in Netlist View www xilinx com 149 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX When you select nets they highlight in the Device view Selecting a bus highlights all nets contained within that bus You can also view nets in the Schematic view You can select nets for ChipScope tool debug testing by using Add to ChipScope Unassigned Nets See Connecting and Disconn
433. ly divide the design into smaller more manageable physical blocks Pblocks These Pblocks can include logic modules and primitive logic from anywhere in the logic hierarchy You can group critical or associated logic together into a single Pblock which prevents logic migration limits interconnect lengths and reduces delays The following subsections describe how to work with Pblocks Creating Pblocks PlanAhead User Guide Creating a Pblock results in an AREA_GROUP constraint that is written into the exported UCF constraint file The constraints in PlanAhead reflect the assigned logic specified ranges and defined attributes www xilinx com 309 UG632 v13 4 January 18 2012 310 Chapter 10 Floorplanning the Design g XILINX Using the Draw Pblock Command The Draw Pblock commands assigns pre selected logic to a new Pblock in the Device view You can select the logic to assign to the Pblock before you invoke the command To create a Pblock 1 Select the logic in any view such as the Netlist view to assign to the Pblock 2 Click Draw Pblock in either the Device view popup menu or toolbar a 3 Move your cursor to the location in the Device view to draw a Pblock 4 Press and hold the left mouse button move the mouse cursor to the opposite corner of the Pblock and release the mouse button The New Pblock dialog box opens as shown in Figure 10 1 G New Pblock Name sblock_cpuEngine_cpu_dbg_dat_i Gr
434. lyze the design and run results You can also experiment with different constraints or implementation strategies Synthesized Netlist Based Projects You can create projects from designs that were synthesized outside of the PlanAhead tool using the Xilinx Synthesis Technology XST tool or any supported third party synthesis tool The PlanAhead tool can import EDIF and NGC NGO format netlists The netlist can be all inclusive in a single file or hierarchical in nature consisting of multiple module level netlists You can analyze the logic netlist launch and manage various Implementation runs and analyze the design and run results You can also experiment with different constraints or implementation strategies Implemented Design Results Based Projects You can create projects to allow analysis of implementation results created outside of the PlanAhead tool using the Xilinx command line tools You can import a design netlist implementation and timing results to explore timing or placement related issues I O Pin Planning Projects You can perform I O pin planning early in the design cycle by creating an empty I O Pin Planning project You can create I O ports within the PlanAhead tool or import them with either CSV or User Constraint Files UCF input files You can also create pin planning projects to explore the logic resources available in the different device architectures After I O pin assignment the PlanAhead tool can create CSV
435. m of PlanAhead Project data directory structure c User_Specified project_ Name DB project _ data O project_ runs B project_ srcs E archive log iE project_ ppr O project_ sim Figure A 2 Project Data Directory Structure Table A 4 lists the PlanAhead Project Data outputs and descriptions Table A 4 PlanAhead Project Data Outputs Output Project Directory Description When you create a new project the PlanAhead tool creates a project directory in which to projectname ppr projectname store the project file the project data directory and the ISE Implementation results The project directory has the same name as the project name entered in the New Project wizard Project File When you create a new project the PlanAhead tool creates a project file The project file has the same name as the project name entered in the New Project wizard Project Data Directory projectname data When you create a new project the PlanAhead tool creates a project data directory in which to put project data The project data directory has the same name as the project name entered in the New Project wizard Project Data Netlist Subdirectory netlist A netlist subdirectory contains a copy of the netlist files for the design For RTL based projects the PlanAhead tool creates a Synthesis subdirectory for each run for the produced netlist which refreshes each time the run is reset For Netli
436. mand highlights all of the nets connected to the selected identify what modules should be grouped together for floorplanning Pblock creation elements To use this command When the PlanAhead tool generates the Schematic view for a timing path it displays all of the objects When you select a Schematic view for individual logic instances to be generated only the selected instances display You can display the instances from a group of paths in this manner making it easy to The following sections describe logic connectivity options in the PlanAhead tool Using the Show Connectivity Command 2 From the popup menu select Show Connectivity Chapter 11 Analyzing Implementation Results Exploring Logic Connectivity FETA Il EE EEE vumm noon EENT RET TABU TT TST TT FY EIT TT T falelefeTaTe als ele Teles HARAMA AA els oI Tafel ISBT PSUS ale elatal lslelel lalelalels aera IRTE TE IRTEE ele ole lls els ole els els olsleLal a EEEE connecting to that element are highlighted in the Device view as shown in Figure 11 12 PlanAhead User Guide UG632 v13 4 January 18 2012 Figure 11 12 Net Connectivity in the Device View www xilinx com 354 g XILINX Exploring Logic Connectivity Viewing Logic Connectivity using Show Connectivity Mode You can run Show Connectivity continuously on newly selected objects by toggling t
437. mand line options for ISim The commands must be in a single string with the command value pair For example log lt filename gt transport_int_delays You can also add the ISim options into a command file and reference this file in the More Simulator Options field with the command as follows lt command_file gt Language Options Figure 5 12 page 192 shows the Language Options tab of the Simulation Language Options dialog box The language options are PlanAhead User Guide UG632 v13 4 January 18 2012 Verilog Options Specify Verilog Search Paths Macro definitions Uppercase identifiers and Verilog2001 language standard Generics Parameters Options Define values for VHDL generics or Verilog parameters Top Library Specify the top level module library name This is automatically determined but you can specify a different library to locate the top module www xilinx com 191 Chapter 5 RTL Design XILINX G Simulation Options i Specify Options for behavioral simulation Launch Options Verilog Options verilog_version erilog 2001 Generics Parameters Options Top Library work Figure 5 12 Behavioral Simulation Language Options Launching the Simulator To invoke ISim for behavioral simulation click Launch The PlanAhead tool runs fuse the ISim object compiler and linker to compile and elaborate the Verilog and VHDL code The compiled object codes are then
438. mbinatorial file_name 1ine_number Combinatorial loops are generated when loop in design a cone of combinatorial logic uses its outputs to feedback as partial input to the same cone of logic The total combinatorial delay from source to destination should be increased by the feedback path delay This type of structure could be required from the design expected behavior or might be unintentional 422 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Floorplanning DRCs Floorplanning DRCs Floorplan Pblock DRCs Table B 3 Floorplan Pblock DRCs Rule Name Rule Abbrev Rule Intent Severity Longest Carry LCCH Checks that the Pblock height can accommodate longest carry Warning Chain Height chain assigned to Pblock Pblock overlap FLBO Checks for overlapping Pblock rectangles Information Pblock Partition FLBP Checks that the LUT to MUXCY and MUXFx connection is not Error broken by a Pblock partition Resource UTLZ Checks that Pblocks have enough resources for logic assigned to Warning for Utilization them SLICE logic Error for non SLICE logic Area Group Tile FLBA Checks that the site ranges in AREA_GROUP constraints are aligned Warning Alignment with the CLB grid Bank DCI DRCs Table B 4 DCI Cascade DRC Rule Name Rule Abbrev Rule Intent Severity DCI Cascade DCIC Checks that DCI cascade constraint is legal Error
439. me in the Export Netlist dialog box ChipScope Core Netlists ngc The PlanAhead tool is integrated with ChipScope Pro Analyzer which lets you insert and configure Integrated Logic Analyzer ILA cores An NGC format netlist for the core is compiled when the core is implemented The PlanAhead tool places the core in the project netlist directory and copies it to each Implementation run directory as Runs are launched Refer to Chapter 12 Programming and Debugging the Design for more information PlanAhead User Guide www xilinx com 417 UG632 v13 4 January 18 2012 Appendix A PlanAhead Input and Output Files XILINX Table A 6 Outputs For ISE Implementation Cont d Output Constraint Files ucf Description The PlanAhead tool writes UCF ASCII files containing timing and physical constraints that are used for ISE These files are created during the following commands e Implement and Launch Runs PlanAhead e File gt Export gt Export Constraints e File gt Export gt Export Pblocks e File gt Export gt Export IP Run Implementation and Launch PlanAhead Runs When you launch runs the PlanAhead tool exports the EDIF and UCF data automatically When you launch a run the PlanAhead tool creates a run directory that contains the original logic hierarchy in the output netlist The exported files for the run consist of a single EDIF format netlist file and a UCF format constrai
440. moves their associated data from disk You are prompted to confirm the deletion of the selected Runs Note You cannot delete the currently active runs 1 Select one or more Runs in the Design Runs view Use Shift click or Ctrl click for multiple selections 2 Select one of the following e The Delete toolbar button e The Delete popup menu command in the Design Runs view x e Edit gt Delete e The Delete key Copying Runs To create a new run based on an existing run use Copy Run in the Design Runs view This command creates a new run using the same strategy and inputs as the selected run from which you are copying The run status is reset to Not Started in the newly created copied run Opening a File Browser in a Run Directory You can open a file browser directly from the Runs view to browse files in the run directory on your system To do this select a run in the Design Runs view then right click and select Open Run Directory PlanAhead User Guide www xilinx com 305 UG632 v13 4 January 18 2012 Chapter 9 Implementing the Design XILINX Launching Runs on Remote Linux Hosts The PlanAhead tool ships functionality to allow parallel execution of Runs on multiple Linux hosts This is accomplished with simplified versions of more robust load sharing software such as Grid Engine by Oracle and LSF Job submission algorithms are implemented using a greedy round robin style with Tcl pipes within Secure Shell SSH
441. mp LD string XSTLIB 1 bool Filtering Based on Properties The object query get_ commands have a common option to filter the query based on any property value attached to the object This is a powerful capability for the object query commands For example to query all cells of primitive type FD do the following get_cells hierarchical filter lib_cell FD To do more elaborate string filtering utilize the operator to do string pattern matching For example to query all flip flop types in the design do the following get_cells hierarchical filter lib_cell FD Multiple filter properties can be combined with other property filters with logical OR and AND amp amp operators to make very powerful searches To query every cell in the design that if of any flop type and has a placed location constraint get_cells hierarchical filter lib cell FD amp amp loc W Note In the example the filter option value was wrapped with curly braces instead of double quotes This is normal Tcl syntax that prevents command substitution by the interpreter and allows users to pass the empty string to the loc property Large Lists of Objects Collections Commands that return more than one object generally return a container that looks and behaves like a native Tcl list This is a feature of the PlanAhead tool in that it allows dramatic optimization of large collections of Tcl ob
442. mple of the return format on the get_cells help command get_cells help Description Get a list of cells in the current design Syntax get_cells hierarchical regexp nocase filter arg of_objects args quiet patterns Returns list of cell objects Usage Name Optional Default Description hierarchical yes false Search level by level in current instance regexp yes false Patterns are full regular expressions nocase yes false Perform case insensitive matching filter yes Filter list with expression of_objects yes Get cells of these pins or nets 394 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX General Tcl Syntax Guidelines Name Optional Default Description quiet yes false Ignore command errors patterns yes Match cell names against patterns Unknown Commands Tcl contains a list of built in commands that are generally supported by the language PlanAhead specific commands which are exposed to the Tcl interpreter and user defined procedures Commands that do not match any of these known commands are sent to the OS for execution in the shell from the exec command This lets users execute shell commands that might be OS specific If there is no shell command then an error message is issued to indicate that no command was found Return Codes Some Tcl commands are expected to provide a return value such as a list or collection of objects on w
443. mplementation Results XILINX You can also add all of the NetGen options into a command file and reference this file in the More Netgen Options field with the command as follows lt command_file gt The ISim Tool Click the Launch button on the Launch Timing Simulation dialog box to invoke ISim shown in Figure 11 20 page 361 The PlanAhead tool runs NetGen which reads the NCD file from MAP or PAR and creates a partial or full timing Standard Delay Format SDF netlist based on the results Before launching a timing simulation a timing simulation model and delay file for back annotation are required PlanAhead uses the NetGen tool to generate these files For more information on running NetGen see the Command Line Tools User Guide UG628 as cited in Appendix E Additional Resources NetGen creates the flattened timing delays in the output SDF file and creates a verilog or VHDL netlist for simulation purposes top_timing_sim v Note The output Verilog or VHDL file is for simulation purposes only and cannot be synthesized The Verilog or VHDL netlist created by NetGen references the Xilinx simulation primitive library SimPrim and so must be used with SimPrim during simulation When NetGen completes The ISim object compiler and linker fuse is run to compile and elaborate the Verilog and VHDL code www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Performing Timing Simulation
444. mplemented Design popup menu command or double click the run The Design Analysis view opens Typically you do placement and timing analysis and floorplanning in this view Figure 2 6 shows an open Implemented Design 30 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Working with Designs You can open multiple Implemented Design views simultaneously to display results from multiple runs Tabs at the top of the view layout indicate which run results are open and which are displayed For information on creating and managing multiple implementation runs see Creating and Managing New Runs in Chapter 9 Note Some capabilities that involve manipulation of the netlist such as altering design partitions or Partial Reconfiguration control might be restricted in the Implemented Design You might need to open the RTL or Netlist Design for these operations to ensure that you are operating on the proper data Managing Open Designs As you open Designs and the PlanAhead tool loads the design into memory an icon displays within the appropriate button in the Flow Navigator This provides a visual reference of the data in memory and can help manage the software session Figure 2 7 shows an design indicator icon RTL Design v Figure 2 7 Open Design Indicator Icon When multiple designs are open simultaneously multiple icons display Saving Designs To save the changes you have made t
445. n Corner Name Delay Type Slow min_max Y Fast min_max v Enable timing pessimism removal Command report_clock interaction delay_type minn Open in a new tab Figure 7 27 Report Clock Interaction Timer Settings Tab e Interconnect Selects the type of delay values used for the interconnect delay The different delay values are as follows e Estimated Uses estimated delays for the interconnect values e None Sets the interconnect delays to 0 e Speed Grade Selects the speed grade of the device used in the timing analysis This field allows the estimation of design timing using different device speed grades e Miulti corner analysis Multi corner analysis simultaneously uses different process and operating condition corners to perform a worst case setup and hold analysis This results in a more accurate but pessimistic analysis than minimum or maximum delays alone e Slow corner Selects the delay types used for the slow corner analysis The available values are None Specifies that no delays are used Max Specifies that maximum delays are used for the clock and data paths during setup and hold analysis Min Specifies that minimum delays are used for the clock and data paths during setup and hold analysis Min_Max Uses a combination of minimum and maximum delays for the clock and data paths during setup and hold analysis 242 www xilinx com PlanAhead User Guide UG632 v1
446. n Running Synthesis After you add Sources to a project open the Synthesis option to launch the XST Synthesis tool See Chapter 6 Synthesizing the Design for more information Synthesize Running Implementation After Synthesis has completed you can run the ISE implementation tools in the Flow Navigator by clicking Implement gt If you have not yet run synthesis you can still click Implement and the Implement PlanAhead tool completes a synthesis run as a prerequisite to performing implementation See Chapter 9 Implementing the Design for more information Generating Bitstream Files After Implementation has completed in Flow Navigator click Program and Debug to generate bitstream files and launch the debugging and programming tools from the menu of available commands Figure 2 4 page 27 shows the Program and Debug button 26 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Working with Designs gt Implement Implemented Design w ta v Program and Debug v Generate Bitstream Pad Figure 2 4 Flow Navigator Program and Debug Button Refer to Generating Bitstream Files page 369 for more information Launching Programming and Debug tools The PlanAhead tool can automatically launch the ISE debugging and programming tools including iMPACT and the ChipScope analyzer The ChipScope analyzer and iMPACT require a BIT file and are available only after you run
447. n This constraint set can have the same name as the active constraint set in the open project When opening an Implemented Design the constraint set loaded from the implementation run could be older than the constraint set currently in the project memory This would cause the loss of newly defined constraints when you save the design Generally the PlanAhead tool manages these revision issues and prompts you to take the appropriate action as needed However you should keep in mind the potential conflict between the www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Managing Constraints current constraint set in memory and any existing constraints associated with an Implemented Design Adding and Creating Constraint Files The PlanAhead tool supports a variety of constraint file formats This lets you add top level constraints in UCF or XCF or module level constraints in NCF Constraints can include placement timing and I O restrictions To add constraint files to the project 1 Select File gt Add Sources from the main menu or Add Sources from the popup menu or from the Flow Navigator The Add Sources wizard opens as shown in Figure 3 14 page 50 Select Add or Create Constraints and click Next The Add or Create Constraints dialog box opens as shown in Figure 3 20 G Add Sources Add or Create Constraints Specify or create constraint files for physical and timing constraint to a
448. n except for the XST default strategy which specifies netlist_hierarchy as_optimized to produce a flattened netlist For more information about optimizing synthesis results see the following documents cited in Appendix E Additional Resources Xilinx Synthesis and Simulation Design Guide UG626 XST User Guide for Virtex 4 Virtex 5 Spartan 3 and Newer CPLD Devices UG627 XST User Guide for Virtex 6 Spartan 6 and 7 Series Devices UG687 Running Synthesis When you run synthesis in the PlanAhead tool you can configure the synthesis run launch the run and view the results of the run 198 Defining Synthesis Run Options A synthesis run defines and configures aspects of the design which are used during synthesis A synthesis run defines the Xilinx device to target during synthesis the constraint set to apply and command line options to control the results of the synthesis engine A synthesis run can be defined from Tools gt Project Settings and click the Synthesis icon on the left hand side of the Project Settings dialog box as shown in Figure 6 1 page 199 In the Flow Navigator select Project Settings from the Project Manager menu and click the Synthesis icon Click the Project Settings command icon from the main toolbar B www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Running Synthesis G Project Settings Synthesis Constraints Default Constraint Set constrs
449. n object type To query a specific property for an object the following command is provided get_property lt property_name gt lt object gt An example would be the 1ib_ce11 property on cell objects which tells you what UniSim component a given instance is mapped to get_property lib cell get_cell inst_1 To discover all of the available properties for a given object type use the report_property command report_property get_cells inst_1 Table 14 1 shows the properties returned for a specific object Some properties are read only and some are user definable Properties that map to attributes that can be annotated in UCF or in HDL are generally user definable through Tel with the set_property command set_property loc OLOGIC_X1Y 27 get_cell inst_1 Table 14 1 Reported Properties for Specified Object Key Value Type bel OLOGICE1 OUTFF string class cell string iob TRUE string is_blackbox 0 bool www xilinx com 397 UG632 v13 4 January 18 2012 398 Chapter 14 Tcl and Batch Scripting XILINX Table 14 1 Reported Properties for Specified Object Key Value Type is_fixed 0 bool is_partition 0 bool is_primitive 1 bool is_reconfigurable 0 bool is_sequential 1 bool lib_cell FD string loc OLOGIC_X1Y27 string name error string primitive_group FD_LD string primitive_subgroup flop string site OLOGIC_X1Y27 string type FD a
450. n BitGen CS e Launch ChipScope Analyzer Program and Debug Analyze Timing and Placement Results e Launch Impact View Connectivity Launch Sim Timing Simulation Refine Constraints Timing Placement Launch FPGA Editor Launch XPower Analyzer Figure 2 3 PlanAhead Software Flow Navigator Synthesized Netlist Project Launching Commands from the Flow Navigator The Flow Navigator facilitates a push button flow by enabling synthesis and implementation to be run immediately after you add source files to a project There is no need to open any of the Design environments to complete the design The following subsections describe how to implement a design with the Flow Navigator Using the Project Manager When you open a project the Project Manager opens by default To open the Project Manager click Project Manager in the Flow Navigator When you open the Project Manager no design compilation is performed and no design data is loaded into memory This environment enables creating importing and managing source files and constraint sets You can also use the Project Manager to browse customize and create IP from the Xilinx IP Catalog The Project Manager displays the sources source properties and a Project Summary view by default e For more information on using the Sources view to configure Project Sources refer to Using the Sources View page 122 e For more information on the Project Summary view refer to Selecting the Step A
451. n PlanAhead select the Tools gt Timing gt Report Clock Interaction command from the main menu This brings up the Report Clock Interaction form as shown in Figure 7 26 page 241 The Report Clock Interaction form has a number of fields and switches on it Results Name Specifies the output results set Options Tab Allows the customization of the Clock Interaction report The detailed options of this tab are discussed in Setting the Clock Interaction Options Timer Settings Tab Specifies timing engine and delay options used to generate the timing report The detailed options of this tab are discussed in Using the Timer Settings tab page 242 Command Contains the text of the Tcl command generated by the Report Clock Interaction options www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Analyzing Clock Interactions Note This field can be edited to modify the Tcl command being executed but does not change the options specified in the dialog box Open in a new tab When enabled this switch opens the results of the Report Clock Interaction command in a new window without closing any older open windows However when not selected the older window is closed before the new results are displayed Setting the Clock Interaction Options PlanAhead User Guide The Options tab has three fields or switches as shown in Figure 7 26 G Report Clock Interaction Results Name results 1 O
452. n constraints outside new site ranges Delete all location constraints of the pblock Figure 10 13 Setting Behavior for Modifying Pblocks with LOCs The available actions are Leave all location constraints in their current position This leaves all placed logic instances in their current location removing the logic from the Pblock and moving the Pblock and all remaining logic to the newly selected site range This mode is useful when many instances have been placed and the Pblock is being relocated to a new region of the device Delete location constraints outside new site ranges This removes the LOC and BEL constraints from placed logic that falls outside of the new Pblock location The placement constraints of any instances still placed within the area of the new Pblock location are preserved This mode is useful when moving a Pblock slightly so that only a few placed instances fall outside the new Pblock location Delete unfixed location constraints outside new site ranges This removes the LOC and BEL constraints of any unfixed instances that fall outside of the new Pblock location while preserving the placement of fixed instances that fall outside the new Pblock location See Understanding Fixed and Unfixed Placement Constraints page 329 for more information This mode is useful to preserve user assigned placement of possibly critical instances while allowing flexibility in replacing unfixed instances Delete all
453. n existing Pblock rectangle use Set Pblock Size e To toggle the display of I O connectivity to place LOCs or Pblocks use the Show Hide I O Nets command e To change the selection behavior click the Show Instance Connections button i With this mode on connectivity displays automatically for newly selected objects This button toggles the mode on and off e To assign e A LOC and BEL placement constraint to the object being placed use Create BEL Constraint Mode e ALOC placement constraint to the objects being placed use Create Site Constraint Mode e Logic instances to Pblocks use Assign Instance to Pblock Mode This is the af default mode use this mode whenever possible to ensure proper command a behavior e I O Ports to I O Banks use Place I O Ports in an I O Bank e I O Ports in a rectangular area use Place I O Ports in Area e I O Ports sequentially use Place I O Ports Sequentially e To toggle Automatic enforcement of interactive I O placement DRCs use h Autocheck I O Placement A Understanding the Device Resource Display The PlanAhead tool displays the various resources contained in a selected device in the Device view Graphical sites display and are available for all of the device specific FPGA resources The level of detail for displaying the device resources depends on the zoom level within the Device view Some resources such as specific slice resources are not visible until zoomed in quite close on
454. n green the end point in red and the through points are marked in yellow E Project Summary X Figure 4 30 Marked Timing Path Symbols in Device View Unmarking Objects You can remove marks on selected object or all objects using one of the following methods e Choose Unmark to unmark the selected instance e Click Unmark All to unmark all instance amp Using the Find Commands The PlanAhead tool lets you selectively search for design objects such as instances or nets in open designs using the Find command To invoke the Find command you must open an RTL Netlist or Implemented Design 1 Select one of the following e Edit gt Find from the main menu PlanAhead User Guide www xilinx com 115 UG632 v13 4 January 18 2012 116 2 Chapter 4 Using the Viewing Environment g XILINX e Ctrl F keyboard shortcut a e The Find toolbar button The Find dialog box opens as shown in Figure 4 31 Find Instances v Crit Instances is Gigabtio v x matches v _ Match Case Open in a new tab Figure 4 31 Find Dialog Box Edit the search fields e Find Select the object type Instances Nets Pins Pblocks Sites and so forth for which you want to search Note Most object types in the Find field refer to logical objects in the design netlist but the Sites object type refers to physical objects in the device such as physical I O Pads slices global buffers dedicat
455. n needs 96 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using the Tcl Console and Messages Area e Save a view layout that you defined using the Layout gt Save Layout As command The user defined view is available in your installation for use in all your design projects User defined layouts are listed in the Layout pulldown menu from the main menu and are saved to a layout file by the PlanAhead tool see Outputs for Environment Defaults in Appendix A e Remove user defined view layouts using the Layout gt Remove Layout command This command has a submenu of any user defined view layouts that can be removed e Reset to the original layout view if you have resized or moved views using the Layout gt Reset Layout command e Undo any view manipulation commands by selecting Layout gt Undo To repeat a command use the Layout gt Redo Using the Tcl Console and Messages Area aly S nal i The status and results of the commands that run from within the PlanAhead tool display in a set of views grouped at the bottom of the viewing environment As messages are generated they appear in the appropriate view within this area The views in this area include the Tcl Console the Messages view the Compilation view Reports view and Design runs In addition some of the other views such as the Find Results view Package Pins view and Timing Results display in this area when opened Using
456. n which there are no cross clock interactions the cells displayed in black on the matrix Therefore a six by six matrix might result in a table with only a few results The data in the table can be sorted by selecting one of the column headers as a key for sorting in increasing or decreasing amounts Select once for up once for down and once again turns it off restoring the table to its original state Use the CTRL key to select additional columns to add secondary sorting criteria See Using Tree Table Style Views in Chapter 4 for more information on working with tables Selecting a cell in the matrix cross selects a specific row of the table below and selecting a row from the table highlights a cell in the matrix above The specific columns from the table are e ID Indicates a numeric ID for the path being displayed e Launching Clock Defines the clock domain from which the path originates e Receiving Clock Defines the clock domain within which the path terminates e WNS Worst Negative Slack Displays the worst slack calculated for various paths crossing the specified clock domains The slack associated with each connection is the difference between the required time and the arrival time A negative slack indicates a problem in which the path violates a required setup or hold time e Asynchronous Displays a check mark on cross domain interactions that are asynchronous in nature Note that if you have selected the O
457. n0115 3 m0115 4 n0115 5 n0115 6 n0l y lt gt b A Tcl Console Messages sj Compilation Design Runs RTL Flow Figure 12 8 Dragging and Dropping Nets onto Debug Core Ports Customizing Debug Core and Port Parameters ChipScope Debug cores have parameters that can be customized To access these core parameters 1 Inthe ChipScope view select one of the ChipScope debug cores 2 Inthe Debug Core Properties tab select Options to configure the core parameters as shown in Figure 12 9 page 378 PlanAhead User Guide www xilinx com 377 UG632 v13 4 January 18 2012 Chapter 12 Programming and Debugging the Design XILINX e gt Mh SE cs_ila_0 enable_storage_qualifica max_sequence_levels 1 sample_data_depth sample_on use_rpms Select an option above to see description of it General Options Port Figure 12 9 Debug Core Parameters Implementing Debug Cores The PlanAhead tool creates ChipScope Pro ICON and ILA cores initially as black boxes These cores must be implemented prior to running through MAP and PAR ChipScope debug core implementation is automatic when running the implementation flow using Implement in the Flow Navigator or Tools menu however you can force debug core implementation manually for floorplanning or timing analysis by clicking the Implement toolbar button on the left side of the ChipScope view The Xilinx CORE Generator tool invokes in ba
458. nalysis see Chapter 7 Netlist Analysis and Constraint Definition Selecting Logic in the Schematic View You can select logic directly from the Schematic view for use in analysis and floorplanning in the Device view To create a Schematic view 1 Select one or more logic elements in an open view 2 Right click and select Schematic from the popup menu or select the Schematic gt toolbar button The Schematic view displays the selected logic instances or nets If only one instance is selected the module shows with all pins displayed as shown in Figure 4 48 e rx Sa DUIS KI kai x Device x Package x E Project Summary x 2 Figure 4 48 Schematic View When you select objects in the Schematic view those objects display in all other views If you have opened an implemented design the logic and paths display in the Device view Viewing Logic Hierarchy in the Schematic View Higher levels of hierarchy display as concentric rectangles when a Schematic view is generated as shown in Figure 4 49 page 138 Notice that no pins display for the upper levels of hierarchy In most cases the lack of pins makes the Schematic view more readable To expand module pins for a selected module select e Toggle Autohide Pins or e The Toggle Autohide Pins for selected instance toolbar button in the oA Schematic view www xilinx com 137 UG632 v13 4 January 18 2012 138 Chapter 4 Using the Viewing E
459. nalyzer command from the main menu e Inthe ChipScope view right click and select Launch ChipScope Analyzer from the popup menu The PlanAhead tool passes the BIT bitstream and CDC netlist name files automatically to the ChipScope Pro Analyzer For more information about ChipScope Pro Analyzer see the Xilinx website http www xilinx com support documentation dt_chipscopepro htm Launching iMPACT PlanAhead User Guide The iMPACT tool lets you perform device configuration and file generation e Device Configuration lets you directly configure Xilinx FPGAs and PROMs with the Xilinx cables Parallel Cable IV Platform Cable USB or Platform Cable USB II e Operating in Boundary Scan mode iMPACT can configure or program Xilinx FPGAs CPLDs and PROMs e File generation enables you to create the following programming file types System ACE interface files CF PROM SVF STAPL and XSVF files iMPACT also lets you e Readback and verify design configuration data e Debug configuration problems e Execute SVF and XSVF files You can launch the iMPACT software tool directly from the PlanAhead tool on any implemented design on which the Generate Bitstream command has been run To invoke iMPACT in the Flow Navigator select iMPACT The BIT bitstream file is passed automatically to iMPACT when launched from the PlanAhead tool For more information on using iMPACT see the iMPACT Help www xilinx com 379 UG632 v13 4 January 18
460. nces Appends the view to display the entire cone of logic between two selected instances Expansion of logic can go beyond hierarchical boundaries Draw Pblock New Pblock Import Partition Settings Set Partition Select Primitives Highlight Primitives gt g Highlight Mark Ctrl M Show Connectivity Ctrl T Ro Show Hierarchy F6 Expand Cone m To Flops Toggle Autohide Pins To Primitives To IOs alee ees Between selected Instances Expand Inside Figure 4 50 Expand Logic Cone Traversing the Schematic Hierarchy You can double click on a hierarchical instance to collapse the displayed logic and expand the logic within the selected module To go up a level of hierarchy use the Expand Outside command in conjunction with the Collapse Inside command PlanAhead User Guide www xilinx com 139 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX Regenerating a Schematic View Occasionally after several expand and collapse commands the Schematic view needs to be refreshed You can force a Schematic view regeneration by selecting the Regenerate schematic toolbar button This command redraws the active Schematic view a Selecting Objects in the Schematic View The following are object selection options for the Schematic view e Left click an object in the Schematic view e Use the Ctrl key to select multiple objects e Click Select
461. nch Runs on Remote Hosts Linux only Use remote hosts to launch one or more jobs See Launching Runs on Remote Linux Hosts e Configure Hosts Select this option to configure remote hosts e Generate scripts only Export and create the run directory and run script but do not launch the run at this time The script can be run at a later time outside of the PlanAhead tool Monitoring the Implementation Run You can monitor the status of a Synthesis or Implementation run by reading the Compilation view viewing the compilation information warnings and errors in the Messages view viewing the Project Summary or opening the Design Runs view The following subsections describe the run status monitoring options Using the Project Status Display The Project Status indicator in the upper right corner of the PlanAhead tool environment shown in Figure 9 6 serves functions that include e Displaying the overall status of the project and the progress of running commands e Providing a Cancel command to stop any running commands Synthesizing XS5T on Figure 9 6 Project Status Display Cancelling a Run To stop a run click the Cancel button in the Project Status Display shown in Figure 9 6 Viewing the Compilation Log The Compilation view opens after you launch a run and shows the standard output messages Figure 9 7 is an example of a compilation log il INGDBUILD done Running map with args intstyle
462. nclude statement to be placed at the top of any Verilog source file that references content from a another Verilog file or header file Designs that use common header files might require multiple include statements to be repeated across multiple Verilog sources used in the design Marking the header files as global include files can eliminate the need for these repeated include statements since the global include files are processed before any other source files To designate a Verilog or Verilog header file as a global include file e Select the file in the Sources view and use the right mouse popup menu Set Global Include command or e Use the Global Include checkbox in the Source File Properties view See Using the Sources View and Viewing Source File Properties in Chapter 4 for more information www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Running Synthesis When a file is designated as a global include it displays with a different icon and is placed at the top of the source tree in the Sources view Multiple files can be designated as global include files and are evaluated in the order listed in the Sources view In this case all global include files are processed before the other source files in the project Because the content of all global include files is visible to all the other source files in the project any Verilog header files that should be specifically applied to a single Verilog so
463. nese and Japanese e WebTalk Controls whether WebTalk is able to send Xilinx usage information e CoreGen Specifies the amount of memory allocated to Java when generating an IP core You might need to increase the memory allocated to Java when generating very large IP cores Conversely you might need to reduce the allocated memory if you encounter an Initialization Failed error e Miscellaneous Controls whether the software automatically searches the Xilinx website for new software updates and defines how many previously opened projects and directories to list in the Getting Started page Configuring the Viewing Environment The PlanAhead tool has numerous user configurable viewing options The tool ships with default settings that you can customize and save for use in subsequent sessions The PlanAhead tool e Separately saves each available view layout e Creates a layout file to restore the overall window size and location e Stores the saved view configurations in your home directory upon exiting the software see Outputs for Environment Defaults in Appendix A Selecting a Theme You can adjust view display options to control the appearance and behavior of the environment To view or edit the display options available in the PlanAhead Options dialog box select Tools gt Options and select Themes in the PlanAhead Options dialog box as shown in Figure 4 70 page 163 Changes to the various settings only tak
464. ng FPGA Editor You can launch the FPGA Editor directly from PlanAhead on any implemented design To invoke the FPGA Editor in the Flow Navigator open the implemented design then select FPGA Editor from the Implemented Design task list Alternatively to launch FPGA Editor without first loading the implemented design you can select Tools gt Analysis gt FPGA Editor The routed NCD file passes automatically to the FPGA Editor when launched from the PlanAhead tool For more information on using FPGA Editor see the ISE Help Cross Probing Timing Paths to FPGA Editor To cross probe from a timing path in PlanAhead to FPGA Editor select a timing path from the Timing Results view or the Device view and select Cross probe to FPGA Editor You can also select individual logic instances to cross probe to FPGA Editor FPGA Editor opens with the selected path or instance highlighted If FPGA Editor is not open you are prompted to open the tool 368 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Chapter 12 Programming and Debugging the Design This chapter discusses programming and debugging the design and includes e Generating Bitstream Files e Debugging the Design with ChipScope e Launching ChipScope Pro Analyzer e Launching iMPACT Generating Bitstream Files After Implementation is successful you can run the ISE bitgen command on the results to create the bitstream data 1 Inthe Fl
465. ng and Resizing Pblocks The following subsections describe how to move resize and set Pblocks Moving a Pblock To move a Pblock select and drag the Pblock within the Device view and drop it in the new location The dynamic hand shaped cursor indicates that the Pblock is selected for moving Ensure that you have selected the outer Pblock rectangle and not one of the assigned instances If you move the Pblock to a location that includes new device logic types such as a block RAM or a DSP a dialog box displays prompting you to add the new range types to the Pblock definition www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX PlanAhead User Guide Configuring Pblocks Pblocks behave differently when assigned logic has a BEL or LOC placement constraint inside the Pblock borders The target location must contain adequate resources to accommodate the placement constraints As you move the Pblock the cursor indicates which sites are legal for a move based upon placement requirements If you attempt to move a Pblock to an inadequate location the Choose LOC mode dialog box displays as shown in Figure 10 13 prompting you to either remove the location constraints or leave them intact G Choose LOC mode Description Some location constraints are on sites being removed from the PBlock What should happen to them Action Leave all location constraints in their current position Delete locatio
466. ng clock edges Understanding the Choose Points Dialog Box The Choose Points dialog box lets you choose the design elements for which you require timing analysis based on element type and a pattern matching string and lets you enter filter strings for the Start Points Through Points and End Point Figure 7 13 page 222 shows the Choose Start Points dialog box PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 221 Chapter 7 Netlist Analysis and Constraint Definition g XILINX 222 G Choose Start Points Find names of type pins using UCF matching style Options With pattern Clk Regular expression Ignore command errors Find results 701 Selected names 2 FFtEngine Mshreg_wb_adr_i_reg_29 CLK Z lcpuEngine cpu_dbg_dat_i wb_clk FFtEngine Mshreg_wb_adr_i_reg_30 CLK FFtEngine Mshreg_wb_adr_i_reg_31 CLK FFtEngine clk FFtEngine fftInst arnd1 clk FFtEngine fftInst arnd1 transformLoop O ct Madc FFtEngine fftInst arnd1 transformLoop 0 ct Mmu lt pa Command get_pins cpuEngine cpu_dbg_dat_i wb_clk FftEngine clk C Concatenate commands of all the types Figure 7 13 Choose Start Points Dialog Box The options are Find Names of Type Filters the points based on the type of design element The field contains the following options e Cells Choose design elements based on cell name e Clocks Choose design elements based on c
467. ng the Design 382 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using Partitions On subsequent design iterations you can configure the action the PlanAhead tool takes for each partition during synthesis and implementation Partitions can either be resynthesized and re implemented if changed or imported from the specified location if unchanged To set a partition action for synthesis or implementation 1 Inthe Flow Navigator select the drop down menu on the right side of the Synthesize or Implement button and select Specify Partitions as shown in Figure 13 2 Project Manager Netlist Design netlist_1 xc6vIx75 ce Netlist RTL Design Pile QQ top H O Nets 1024 Synthesize H E Primitives 153 Netlist Design Synthesis Settings P re Create New Synthesis Runs EJ Resource Estimation top Specify Partitions top S Power Estimation wb rbEngine wb_conmax_top Run DRC Run Noise Analysis Report Timing it Slack Histogram Set up ChipScope B Implementation Settings o Create New Implementation Runs E Promote Partitions usbEngineO a Figure 13 2 Synthesis and Implementation Settings The Specify Partition dialog box lets you specify the actions for each partition in the design for the active synthesis and implementation runs You can set the action for each partition to either Implement or Import If
468. nly report timing paths 1 The color of the cell is determined by the background color of the Graphical Editors as defined under the Tools gt Options command See Configuring the Viewing Environment in Chapter 4 for more information www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Defining Physical Constraints between asynchronous clocks when running Report Clock Interaction this column is completely populated with check marks e Paths Indicates whether the specified paths are fully or partially constrained or unconstrained The matrix at the top of the Clock Interaction Report shows clock domains that are either constrained unconstrained inadvertently or partially or that have no relationship to each other A popup menu available from the right mouse button from within the table holds the Export to Spreadsheet command This command exports the table to an XLS file for use in a spreadsheet application Note The cursor must be located in the field of the table and not in the headers of the column to see the Export to Spreadsheet command 8 TS_phy_clk_ TS_phy_clk_pad_0_i 9 TS_phy_clk_ TS_usbClk 10 TS_phy_clk_ TS_wbClk Clock Interactions Unclocked Register Pins Figure 7 29 Clock Interactions and Unclocked Register Pins At the bottom of the Clock Interaction Report view are two tabs as shown in Figure 7 29 one to display the Clock Interactions as described above a se
469. ns Adding the Embedded Processor System Netlist The next step is to include the embedded processor system netlist created in XPS In the PlanAhead tool add the system ngc file 1 Select Add Sources in the Flow Navigator or from the File gt Add Sources command on the main menu This opens the Add Sources wizard to select from various types of source files to add to the project 2 Select the Add or Create Design Sources option and click Next The Add Sources dialog box opens allowing you to add the source files as shown in Figure 3 33 Add Sources a lll li Add or Create Design Sources Specify HOL and netiist files or directories containing HDL and netist files to add to your project Create a new source de file on disk and add it to your project library Location Id Name 1 ax4_0_wrapper ngc N A C Pata Xilinx_Documents KAPPs PlanAhead_XPS_Ar a G2 axidite_0_wrapper ngc N A C Pata Kilinx_Documents KAPPs PlanAhead_XPS_Ar 3 dock_generator_0_wrapper ngc N A C Pata Xilinx_Documents KAPPs PlanAhead_XPS_Ag G4 dde3_sdram_wrapper nge N A C Data Xlinx_Documents XAPPs PlanAhead_ XPS_Ag gt s debug_module_wrapper ngc N A C Pata Xilinx_Documents KAPPs PlanAhead_XPS_Ag 6 dip_switches_Sbits_wrapper ngc N A C Pata Xilinx_Documents XAPPs PlanAhead_XPS_Ag 7 ethernetite_wrapper ngc N A C Data Xilinx_Documents KAPPs PlanAhead_XPS_Ar s _ ethernet_ite_wrapper_fifo_generator_v8_1 nge N A C Pata Kilinx_Documen
470. ns Reports View report files generated by the ISE tool from within the PlanAhead tool In the Implementation Run Properties view select the run and then select the Reports tab to display the list of available report files and to open a report in the workspace Messages View run messages An example of the Messages view is shown in Figure 4 7 page 97 Using the Netlist View The Netlist view provides a hierarchical view of the elaborated or synthesized logic design including the nets logic primitives and hierarchical modules of the design starting with the currently defined top module Figure 4 59 shows the Netlist view GH Nets 1002 W G Primitives 153 8 cpuEngine or1200_top CH ia FFtEngine FFtEngine fFtTop w R matEngine matTop 6 R usbEngineO usbEngineO usbF_top 6 R usbEngine1 usbEnaine p a fe h R m0 i onmax_master_if_m0 2 onmax_master_if H z 2 a a 08 H Primitives 103 msel wb_conmax_msel_2 Figure 4 59 Netlist View The Netlist view displays the logic instances and nets contained in the design The netlist can be navigated by expanding and collapsing the logic tree The default fal netlist tree setting is to expand and scroll the netlist object dynamically when they are selected in other views To disable this feature select the Au
471. nt file for the entire top level design The file names correspond to the original top level netlist name of the imported EDIF file Exported Constraints When you export constraints the PlanAhead tool attempts to preserve the original UCF content and structure including comments You can specify the output constraints file in the Export Constraints dialog box Exported Pblocks Exporting a Pblock writes the EDIF and UCF files for the specified Pblocks to use for ISE Implementation outside of the PlanAhead environment When you export a Pblock the PlanAhead tool derives the netlist hierarchy based on the Pblock assignments The resulting UCF references the PlanAhead physical hierarchy structure to match the exported EDIF netlist names and provides flexibility when using a block based Implementation strategy The exported Pblock files consist of a single netlist file and constraint file The PlanAhead tool automatically creates and maintains a block level directory structure When you export selected Pblocks the PlanAhead tool creates pblockname_Cv subdirectories containing pblockname_CV edn and pblockname_CV ucf files Export Pblocks is typically used for a complex IP that contains the physical hierarchy on which you can close timing and then use those instances in other designs without restructuring your code to obtain a netlist 418 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILIN
472. nt to the Tcl Console and the planAhead jou file for all actions performed using a menu command or through direct manipulation such as drag and drop The planahead jou file is written each time the PlanAhead tool is launched Note One backup version of this file called planahead jou_backup is written to save the details of the previous run Use the history command to access the command history in the Tcl Console Press the Up or Down arrow keys to scroll through the command history one command at a time Using Tcl Help Command line help is available for commands by using the following syntax at the command line Command gt help You can retrieve more detailed information about the commands by extending the help query with the following command Command gt help get_cells The Tcl Console displays the list of available commands or command options based on the help topic that you enter For explicit command syntax perform the command once then view the planAhead jou file in the invocation directory See Chapter 14 Tcl and Batch Scripting for more information about the Tcl command formats and help Hiding the Tcl Console and Messages view PlanAhead User Guide To hide the entire set of Tcl Console and Messages views click Minimize in the banner of any of the Messages views When the Tcl Console and Messages views are minimized they temporarily display as tabs at the bottom of the viewing environment Click any of the m
473. ntains top exe the simulation executable created by fuse to run Sim on the design top exe sim Directory containing design data and object code Both secureip compiled by fuse top exe sim Directory containing design data files and object Both simprims_ver code compiled by fuse top exe sim work Directory containing design data files and object Both code compiled by fuse top exe_main c and top exe_main os_type obj 416 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Outputs for ISE Implementation Outputs for ISE Implementation Table A 6 provides a brief description of the files PlanAhead creates during ISE Implementation design operations These files are maintained by PlanAhead and must not be modified manually Table A 6 Outputs For ISE Implementation Output Run Directory projectname runs Description The PlanAhead tool lets you launch and queue multiple ISE Implementation attempts or runs You are prompted to enter a location to create the run directory The default location is in the project directory Each run directory contains a complete EDIF netlist and UCF constraint file for that run The PlanAhead tool creates a run script to launch the ISE commands with your specified options in each run directory Each run directory contains the implementation design data including the netlist and the constraints files When a satisfactory implementation result i
474. nting synthesized netlists analyzing the results generating bitstreams and launching programming and verification tools Advanced User Features PlanAhead User Guide The PlanAhead tool provides a series of analysis environments at each stage of the design flow for advanced design configuration and analysis You can load the elaborated RTL design synthesized netlist design and implementation results for analysis and constraint definition These environments are described in Working with Designs page 27 The PlanAhead tool lets you create and store multiple variations of the design within a single project This allows for the creation of multiple RTL source versions constraints sets target devices synthesized netlists and implementation run results using various implementation strategies As you modify the source files or launch design tools the software provides a design status You can configure launch and monitor multiple synthesis and implementation runs locally or on remote Linux servers You can experiment with different command options constraints and devices www xilinx com 23 UG632 v13 4 January 18 2012 Chapter 2 The PlanAhead Tool Flow XILINX Understanding the Flow Navigator The Flow Navigator provides control over the major design process tasks such as project configuration synthesis implementation and bitstream creation As these tasks are completed you can open the resulting designs to analyze
475. nts view the PlanAhead tool also selects the associated I O banks Modifying or Removing DCI Cascade Constraints You can modify DCI Cascades by selecting the DCI Cascade in the Physical Constraints view and using the DCI_CASCADE Properties view The actions are To save all changes in the DCI_CASCADE Properties view click Apply To change the Master select a different I O Bank and assign it as the Master To remove I O banks from the DCI Cascade select the I O banks in the DCI_CASCADE Properties view then click Delete I O Banks To include additional I O banks in the DCI Cascade select them in the DCI_CASCAI Properties view and click Add I O Banks The Add I O Banks dialog box displays and you can select new I O banks The newly selected I O banks also highlight in the other views To remove DCI Cascade constraints in the Physical Constraints view select the constraint then click Delete DE www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Defining and Configuring I O Ports Prohibiting I O Pins and I O Banks The I O Planning view layout provides an interface to selectively prohibit port placement onto individual I O pins groups of I O pins or I O banks You can select and prohibit pins in the Device Package and Package Pins views To prohibit I O pins or I O banks 1 Select the I O pins or I O banks in the Device Package or Package Pins v
476. numbered from XOY0 in the lower left of the device to X1Y2 in the upper right e Each of these clock regions also has I O banks containing clock capable pins CCIOs BUF 10s and BUFRs that display in the Clock Resources view for each clock region e The device itself is divided into a top half containing four clock regions and a bottom half containing two clock regions e Inthe center column of the device as displayed in the Clock Resources view are the Clock Management Tiles CMTs with MMCMs and BUFGs for managing global clocks on the device e The clock regions on the left side of the device contain both an outer I O bank IOOL and a center I O bank IOCL while the clock regions on the right side of the device have only a center I O bank IOCR with a column of Gigabit Transfers GTs located on the right hand edge of the device You can expand or collapse the Clock Resources view levels to display only the information of interest e Click Collapse All or Expand All to hide or view levels of the Clock Resources view e Click the or sign on the label of a specific level to expand or collapse that level www xilinx com 275 UG632 v13 4 January 18 2012 276 Chapter 8 O Pin Planning XILINX To cross select the object in other views such as the Device view in the Clock Resources view click the name of a specific clock region or I O bank Use this to quickly locate a spe
477. nvironment XILINX det_block_ det_unit_1 E Hiei clk dei_cos_table 3260 det_cos_table_ 8260 dei_cos_tanle 8260 det_cos_table S260 det_cos_itable 5280 RIX ERK eos table 8260 dct_cos_table 3260 dei_cos_table_8280 9 detu_11s_85_7_1 dctub_11s_8s_7 Figure 4 49 Viewing Hierarchy in the Schematic Expanding Logic from Selected Instances and Pins With a selected schematic instance or a selected pin on a schematic instance you can Individually expand or collapse module pins and logic Selectively expand the logic either from individual pins instances or the entire logic content inside or outside the module You can expand or collapse logic contained either inside a selected module or outside in the next level of hierarchy You can expand a single module or multiple selected modules The commands to expand schematic logic are Use the Expand Inside from the popup menu to display the schematic hierarchy of a selected instance The PlanAhead tool regenerates the Schematic view to expand the contents of the selected instance e This command is not available if the selected instance is a primitve within the design hierarchy e Use Collapse Inside to hide the expanded contents of a selected instance Use the Expand Outside from the popup menu to display the hierarchy upward from a selected instance The PlanAhead tool regenerates the Schematic view to expand the hi
478. nvironment Defaults in Appendix A for more information 2 To delete shortcuts click the Remove button 166 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Configuring PlanAhead Schematic Attributes The Schematic options enables you to tag source pins with Fanout values and destination pins with Slack values See Annotating Schematic Design Information page 141 for more information Defining Strategies for Synthesis and Implementation G PlanAhead Options A strategy is a defined approach for resolving the synthesis or place and route challenges of the design The strategy is defined in a preconfigured set of command line options for the synthesis application or the various utilities and programs run during implementation Strategies are tool and version specific Each major release has version specific command line options See Synthesis Settings page 86 and Implementation Settings page 88 for more information on setting strategies Strategies Flow SaxsT 13 co fe te GX Name large_area_impl User Defined Strategies fast_area_reduction ca i my_default_synthesis Plan4head Strategies Sg Plandhead Defaults gt He Timing WithIOBPacking Se Timing WithoutlOBPacking Sg SreaReduction PowerOptimization Fg XST Defaults Options opt_mode opt_level register_balancing Fsm_encoding ic auto_bram_packing use_dsp48 resour
479. o display or hide them Note If you cannot see a specific object or layer of the Device view check the configuration of the Device View Layers command to see if the design object or device resource is currently hidden The Layer Slideout has a toolbar menu featuring a Show Search command to search for specific layers to display and Expand all Collapse all commands Click the Device View Layers to hide the Layer Slideout when you have finished hiding or displaying specific layers The PlanAhead tool stores settings for the Device view by user Selecting Clock Regions The clock regions display as large rectangles indicating the periphery of the various device clock regions These outlines can help guide floorplanning for critical circuitry In the Device view you can e Select the clock regions in the Clock Regions view e Select and specify that Clock regions display their resource statistical properties e View the clock placement statistics after importing the Implementation results e Change the display color of Clock Regions in the Device view using the Tools gt Options gt Themes gt Device dialog box 132 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using Common Views When you select the clock region the PlanAhead tool also selects the associated I O banks and clock related logic sites See Clock Region Resources and Statistics page 255 for more information about displaying Clock
480. o generate a Slack histogram e Tools gt Timing gt Slack Histogram In the Flow Navigator e Netlist Design gt Slack Histogram e Implemented Design gt Slack Histogram The Generate Slack Histogram dialog box opens as shown in Figure 7 20 page 232 and you can customize the slack histogram The options are e Histogram Name Specifies the name of the generated histogram report e Options tab Allows the customization of the histogram report Setting Slack Histogram Options page 232 further describes the tab selections e Timer Settings tab Specifies timing engine and delay options used to generate the timing report Using Slack Histogram Timer Settings page 236 further describes the detailed table options e Command Contains the text of the Tcl command generated by the Generate Slack Histogram options Selecting OK displays a slack histogram with specified values www xilinx com 231 UG632 v13 4 January 18 2012 Chapter 7 Netlist Analysis and Constraint Definition g XILINX Setting Slack Histogram Options You can specify the options used to generate the histogram using the Options tab of the Generate Slack Histogram dialog box Figure 7 20 shows the Options tab G Generate Slack Histogram for Endpoints Histogram name results_1 Options Timer Settings Endpoint Scope Delay type max Clock name Group name Slack Range Greater than Use default Less than Use default
481. o individual modules Defining partitions invokes the XST incremental flow which generates individual NGC files for each partition See Chapter 13 Using Hierarchical Design Techniques for more information Note Critical paths that span large numbers of hierarchical modules can be difficult to floorplan or partition e If you expect to change the design often consider an incremental approach to synthesis Most synthesis tools enable a top down approach for incremental synthesis and implementation This capability coupled with Xilinx partitions can preserve unchanged modules of the implemented design Refer to Chapter 13 Using Hierarchical Design Techniques for more information www xilinx com 197 UG632 v13 4 January 18 2012 Chapter 6 Synthesizing the Design XILINX Design Preservation helps create an incremental flow but can hurt performance because global optimizations across the hierarchy are disabled Consider this trade off before you embark on an incremental methodology Constrain the synthesis engine to rebuild or to otherwise preserve the hierarchy in the synthesized netlist Flattened netlists could be optimal from a synthesis perspective but make it difficult to floorplan and constrain placement reliably Consider using synthesis options that rebuild the logic hierarchy after synthesis such as the XST command line option netlist_hierarchy rebuilt Note Allof the synthesis strategies in PlanAhead specify this optio
482. o your project click File gt Save Design The Save Design command saves any changes to the constraint files design partitions and project settings a When an Implemented Design is open Save Design saves changed constraints to the constraint file used during design implementation rather than the currently active constraint file This ensures that the changes to the Implemented Design are saved with the proper constraint files However this can cause unintended changes to the constraint files used for a specific implementation run and might not be the desired result The PlanAhead tool warns of this circumstance and lets you choose the correct constraint file to which to save changes before committing a save action Closing Designs PlanAhead User Guide You can close designs to reduce the number of designs in memory and to prevent multiple locations where sources could be edited In some cases you are prompted to close a design prior to changing to another design representation In some cases such as for a Partial Reconfiguration design you must close the design when leaving the design You can close e Individual designs by clicking Close in the banner of the main viewing area x e All designs by selecting the Close Design command from the pulldown menu on any Design button in the Flow Navigator www xilinx com 31 UG632 v13 4 January 18 2012 Chapter 2 The PlanAhead Tool Flow XILINX Understanding the Design Vi
483. oToo ooo N mil gt tRNA aAa el eS D oo gt 0 an AAD AAS Aan AAD AAS Aas AK Device x x oreraray b LICEL 3 3 3 SLICEL 3 3 3 SLICEL a A aaee e E E Od A AA ALA AA AA AA AA AA ao Aa p dad aaga adda aaqa Eii AA AA AA AQA AA AA A adad aada aadd qd oooo poo ma foon oop foon Gono foon oooo 0000 Oooo 0000 0000 000 LICEL SLICEL LICEL pgpEgcggJmgaagnazJjouunaaJ ccann ouan ETTE ETTE oc ao og a ad of fo a dd da aada d ddd Fd Ce Eee SIE o a ee Poo ma oo 0000 ae 0000 0000 iz 0000 jooo00 0000 00000000 000 o Hdd a o oa a ad adadad aadd oA Ap qd dd oc Ga Regnard o F fpooo ma joooo J 0000 T 0000 0000 fe 0000 joooo 0000 oooo 0000 ooo LICEL SLICEL LICEL c f gag mM m gogg gogg bo o oo A qaa ao oa a a o A Ao a CCE Rat aid laa aa laa aa a dda aa agaga aa aq bs of ao agaa JCEM
484. obal Clock DRCs Table B 15 provides the Global Clock DRCs abbreviation intent and severity Table B 15 Global Clock Rules Rule Rule Name Abbrev Rule Intent Severity IBUFG to DCM IDCM IBUFGs have dedicated routing only to all DCMs on the same edge top Warning connectivity bottom left right of the device DCM to BUFG DCMB DCM can connect to a maximum of four BUFGs There are pairs of buffers Error connectivity with shared dedicated routing resources such that if both are driven by the same DCM one of the two is driven using non dedicated routing resources this causes the design to fail If the buffers are numbered 1 through 8 from left to right there are four pairs of exclusives 1 5 2 6 3 7 4 8 If a buffer is placed in Site 1 another driven by the same DCM should not be placed in Site 5 Number of BUFGs DCMN DCM can connect only up to 4 BUFGs This is related to DCMB Error allowed for DCM DCM and BUFG DCME BUFGs have dedicated routing only to all DCMs on the same edge top Warning connectivity bottom left right of the device Placer DRCs Table B 16 lists the Placer DRCs Table B 16 Placer DRCs Rule Name Rule Abbrev Rule Intent Severity Placement constraint PLCR Placement constraint check for clock regions Error Clock placer Checks the clock placement for valid locations Included in PLCK are e IOBUFR which checks that a regional clock terminal PLCK and
485. ocuments cited in Appendix E Additional Resources e ISE Design Suite Installation and Licensing Guide UG798 e ISE Design Suite Release Notes Guide UG631 e Known Issues for PlanAhead AR40512 About PlanAhead Software PlanAhead User Guide The PlanAhead tool is a design and analysis product that provides an environment for the entire FPGA design and implementation process The PlanAhead tool is integrated with e Xilinx ISE Design Suite synthesis tools e Xilinx ISE Design Suite implementation tools e Xilinx Synthesis Technology XST tool e CORE Generator tool e ChipScope Pro debugging tool e ISE Simulator ISim tool e XPower Analyzer tool e FPGA Editor tool e iMPACT device programming tool The PlanAhead tool lets you improve circuit performance by defining and analyzing the Register Transfer Level RTL sources in the design synthesized netlists and implementation results You can experiment with different implementation options refine timing constraints and apply physical constraints with floorplanning techniques to help improve design results Early estimates of resource utilization interconnect delay power consumption and routing connectivity can assist with appropriate logic design device selection and floorplanning The PlanAhead tool includes a hierarchical data model that enables an incremental design capability referred to as Design Preservation By partitioning the design unchanged modules can b
486. ommand to control the execution of the simulator at launch time you must include these three commands in your tclbatch file It is recommended that onerror be the first command listed and that wave add and run be the last commands listed You can add any other ISim command line commands between onerror and wave add Note The tclbatch command file must have a file extension of either TCL or CMD to be properly handled by ISim rangecheck Switch to specify that fuse linker and compiler should perform a value range check on VHDL assignments during compilation This option applies to VHDL code only Note This does not affect index range checking for arrays which ISim always checks wdb Specify a filename to save the simulation waveform data The simulation results of the signals being traced are saved to the specified filename in the working directory The PlanAhead tool creates a lt top_module_name gt wadb file by default wcfg Specify a waveform configuration filename to use when opening the waveform data in the ISim GUI The wave configuration file specifies settings such as the signal order name style radix and color Load glbl Switch to specify that the g1b1 module should be loaded during compilation If the design uses a Verilog UniSim or a SimPrim library you must enable this switch SAIF Filename Specify a filename to write a Switching Activity Interchange Format SAIF file and record port and signal switc
487. on In the Flow Navigator invoke the Set Up ChipScope wizard from the Netlist Design menu or click Tools gt Set Up ChipScope Figure 12 5 shows where to launch the wizard Netlist Design E Resource Estimation Run DRC fe Run Noise Analysis E Report Timing Jili Slack Histogram S Set up ChipScope yO Implement Figure 12 5 Launching the Set up ChipScope Wizard 3 Follow the instructions screen by screen to connect and configure the debug cores Importing a ChipScope CDC File The Set Up ChipScope wizard lets you add an existing ChipScope Debug Core CDC file to the project When you click the Set up ChipScope box a wizard pane prompts you to select the CDC file www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Debugging the Design with ChipScope Select the CDC file and click Next Note Not all ChipScope cores are importable CDC files originating from the ChipScope Core Inserter or PlanAhead contain the required core information required for import Selecting or Confirming Debug Nets If you have added nets to the Unassigned Nets list you are prompted to use them or to select new nets The PlanAhead tool invokes an Add Remove Nets dialog box to search for and select nets to debug Add or remove nets as needed and click Next Specifying Debug Nets and Clock Domains The ChipScope wizard attempts to detect the correct clock automatically for each selected net or b
488. on Implemented Design for timing analysis See Analyzing Timing Results in Chapter 11 Importing Embedded Processor Designs in PlanAhead Projects See Importing XPS Embedded Processor Designs in Chapter 3 Global Include files in RTL Elaboration and Synthesis See Controlling File Compilation Order in Chapter 6 New Critical Warning dialog box to highlight potential problems in Messages View See Using the Messages view in Chapter 4 Using the Viewing Environment Wrap message lines in Messages View See Using the Messages view in Chapter 4 Using the Viewing Environment Schematic View now default for opened RTL Design See Resource Estimation of the RTL Design in Chapter 5 Preliminary SSN support added for some Virtex 7 and Kintex 7 devices See Using Noise Analysis Predictors in Chapter 8 7 Series HP HR Bank Support in Device and Package View See Using the Device View and Using the Package View in Chapter 4 Using the Viewing Environment Specify Partitions for Synthesis and implementation combined See Using Partitions in Chapter 13 Automatically sort package pins view after setting config mode See Setting Device Configuration Modes in Chapter 8 Corrected Unfixed Unplaced terminology See Working with Placement LOC and BEL Constraints in Chapter 10 Board Signal and Board Voltage are exported to Comma Separated Value CSV See I O Port Lists CSV File Format in Appendix A Added discussion of Connectivity and Pins tab of th
489. on in a view tab Hiding and Showing the Flow Navigator To make more screen space available for other views you can hide the Flow Navigator by e Clicking Hide Navigator on the left side of the Flow Navigator or e Selecting View gt Hide Navigator command in the main menu To re display the Flow Navigator e Click Show Navigator e Select View gt Show Navigator Figure 4 5 shows the Hide Navigator and Show Navigator buttons Hide Navigator Show Navigator Figure 4 5 Hide and Show Navigator Buttons PlanAhead User Guide www xilinx com 95 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment g XILINX Using View Layouts The PlanAhead tool provides predefined view layouts as shown in Figure 4 6 to facilitate various tasks in the design process The layout of the views generally supports the required tasks for the selected design process After you open a design you can switch the view layout between available preconfigured layouts using e Layout menu on the main menu or e Layout Selector on the toolbar menu Tools Window Layout View Help ox A Design Analysis gt o 25 Design Analysis A Q I O Planning t Manager o o xc6vix75tfi484 1 active Clock Planning Design Floorplanning gt resize ChipScope Project Management 20 06 06 06 06 io D Save Layout As Estimation imation Reset Layout F5 lym vhdl wde AFF nackane vhell
490. on using phase group see Defining I O Port Switching Phase Groups in SSN page 288 Note The Phase option applies to Virtex 6 devices only and is not available for other device families Refer to Xilinx device documentation for information regarding voltage capabilities of the device Setting I O Port Direction To set the I O port direction select the I O ports buses or interfaces to be configured and select Set Direction in the I O Ports view You can use this command to define a port direction of Input Output or In Out This command is only available in I O Pin Planning projects In RTL source projects you define the port direction in the RTL source You can also edit the I O Ports view table to change the direction of a selected port Click in the Dir column on the selected port and change the direction to one of the available selections from the drop down menu Defining Differential Pairs To define a differential pin pair in an I O Planning project select any two I O ports then select Make Diff Pair in the I O Ports view as shown in Figure 8 14 page 264 Note The Make Diff Pair option is not applicable in RTL based projects In RTL based projects differential ports must be defined in the source code using appropriate I O buffer instantiations PlanAhead User Guide www xilinx com 263 UG632 v13 4 January 18 2012 Chapter 8 VO Pin Planning g XILINX 264 G Make 1 0 Diff Pair Create a Differential I O Pair
491. onal logic object such as a MUX or a carry chain results in the selection of the entire group of instances to move together The cursor indicates legal placement sites for the entire group and PlanAhead moves all objects to new relative locations You can examine location constraint properties in the Instance Property view for selected instances Swapping Placement Locations You can select two placed components and swap their locations To swap locations 1 Select two component instances from any of the available views Hold the Ctrl key while clicking to select multiple ports 2 Right click and select Swap Locations Swapping unfixed instances causes them to become fixed Clearing Placement Constraints and Unplacing Instances Placed instances can be unplaced by selecting one or more instances and using one of the following methods e Click the Unplace command in the popup menu of the Device view or another view This will simply unplace the selected objects from sites on the FPGA device clearing LOC and BEL constraints in the process e Select Tools gt Floorplanning gt Clear Placement The Clear Placement command opens the Clear Placement Constraints wizard as shown in Figure 10 25 allowing you to unplace objects removing LOC and BEL constraints from instances I O ports or both instances and ports G Clear Placement Constraints Clear Placement Constraints This wizard will quide you through the process of de
492. one created with the New Pblock s commands For more information see Creating Multiple Pblocks with the Create Pblocks Command page 311 When working with Pblocks be aware that 322 If a Pblock has multiple rectangles this command regenerates the Pblock with a single rectangle Often this is useful when a Pblock gets fragmented into multiple rectangles If you resize the Pblock to a location that includes new device logic types such as a block RAM or a DSP a dialog box displays prompting you to add the new range types to the Pblock definition Pblocks behave differently when assigned logic has a placement constraint inside the Pblock borders The target size should contain adequate resources to accommodate the placement constraints If you attempt to resize a Pblock to an inadequate size a dialog box displays prompting you to either remove or leave the location constraints intact Pblocks also behave differently when there are location placement constraints assigned inside of them If location constraints are assigned to the Pblock a dialog box displays prompting you to either remove or leave the location constraints intact Fixed and unfixed location constraints are listed separately in the dialog box allowing you to handle them differently See Understanding Fixed and Unfixed Placement Constraints page 329 for more information To cancel an active resize operation press the Esc key on the keyboard www xilinx com PlanAhead
493. one of the following e Group I Os together into interfaces to easily identify or select them for placement See Creating I O Port Interfaces page 267 e Drag groups of I O ports and assign them to placement sites in either the Package view or Device view using one of three I O placement modes e Placing I O Ports into I O Banks Places selected I O ports within a selected I O bank e Placing I O Ports in a Defined Area Define a rectangle in the Device or Package view into which the PlanAhead tool places selected I O ports e Placing I O Ports Sequentially Interactively place selected I O ports onto available and legal placement sites The selected I O placement mode remains active until the selected I O ports are placed or until you press the Esc key Each I O placement mode offers a different assignment method for the I O ports to be assigned to pins The cursor tool tip provides information about the number of ports being placed and whether the placement site under the cursor is a legal site for the port See Disabling or Enabling Interactive Design Rule Checking page 268 for more information www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using the I O Planning view layout To place unplaced I Os or any selected group of I Os automatically select Tools gt I O Planning gt Autoplace I O Ports The command obeys I O bank rules differential pair rules and global clock pins and
494. ontains the Tcl command used to run the Slack Histogram command Choosing Endpoint Destination Clocks The Choose Endpoint Destination Clocks dialog box lets you choose the clock domains for the endpoints of interest PlanAhead filters the endpoints by the associated clock name Figure 7 21 page 234 shows the Choose Endpoint Destination Clocks dialog box PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 233 Chapter 7 Netlist Analysis and Constraint Definition XILINX G Choose Endpoint Destination Clocks Find names of type clocks v using ucF v matching style Options With pattern i C Regular expression Ignore command errors Find results 6 Selected names 2 a Its cpuCik Ts EE o G TS phy clk pad Di ITS_phy_clk_pad_1_i gt T5_usbClk TS_wbClk Command get_clocks TS_cpuClk TS_FFtClk Concatenate commands of all the types Figure 7 21 Choose Endpoint Destination Clocks The options are 234 Find Names of Type Filters the points based on associated clock domains Matching Style Select the type of pattern matching used for filtering the design elements The field contains the following options e UCF Choose UCF based syntax for pattern matching e SDC Choose a SDC based syntax for pattern matching With Pattern The pattern expression used to filter the design elements This field is modified with the following options e Re
495. ool in general See Configuring Project Settings page 83 for more information Figure 4 69 page 161 shows the General options in the PlanAhead Options dialog box www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Configuring PlanAhead General a Default Project Directory oO Current Working Directory Last Project s Created or Saved Directory Home Directory C Documents and Settings randyh Specify Project Directory E Data I Source Files Oj Copy sources into project Recurse all subdirectories and add found sources to project Show file path in text editor 1 0 Placement Automatically enforce legal I O placement Connectivity Display Draw Nets As Mesh Tree Show connections while dragging instances Show Hide connections for selected instances High Fanout Net Limit 200 nets File Saving Prompt to Save Files Automatically Save Files Text Editor PlanAhead Text Editor default gt Tabs Use tab character Insert 3 spaces Language amp ToolTips Language tooltips amp help English X ToolTips v Tooltip initial delay 750 _2 ms Cancel __ Apply Figure 4 69 General Options Dialog Box The General options are e Default Project Directory Specifies where PlanAhead searches for existing projects and where it writes newly created projects PlanAhead User Guide
496. oose Through Points Opens a dialog box to build the expression that filters the paths based on the through points Transition Further filters the paths according to the active clock edge of the through point synchronous elements This field contains the following values Rise Filters through point synchronous elements to those triggered by a rising positive clock edge Fall Filters through point synchronous elements to those triggered by a falling negative clock edge Rise Fall Includes both rising and or falling clock edges More Adds additional through point filter expressions Fewer Removes existing through point filter expressions e End Points Enter paths that end in a set of synchronous elements This section contains the following fields To Contains an expression used to filter the paths based on the points the path travels to or end points Choose End Points Opens a dialog box used to build the expression that filters the paths based on the end points Transition Further filters the paths according to the active clock edge of the starting point synchronous elements This field contains the following values Rise Filters ending point synchronous elements to those triggered by a rising positive clock edge Fall Filters ending point synchronous elements to those triggered by a falling negative clock edge Rise Fall Includes both rising and or falli
497. op_6 BA sinegen_demo_sp601 ucF C P4_Project ChipScope_tutorial src Bl enrecel nnnl71 enreccFifin FifoRiifFer MOIS enreccl n Figure 2 9 Design Out of Date and Reload Banner If a design step needs to be run again to update the data the Status Bar and Project Summary indicate an out of date status The PlanAhead tool provides a link to run the next required step such as Synthesize or Implement Toggling Multiple Open Designs If multiple Designs are open tabs display that allow you to toggle between the open designs You can use the make active link in the view banner to set the constraint set associated with the design as the active constraint set as shown in Figure 2 10 Netlist Design netlist_2 xc6vcx75tff784 1 a netlist_1 xc6vex7StfF784 1 netlist_3 xc6vcex7StfF784 1 netlist_2 xc6vcx75thh784 1 X Figure 2 10 Multiple Open Design Tabs 32 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Chapter 3 Working with Projects This chapter discusses working with projects including Project Types Project Types Creating a New Project Managing Projects Managing Project Sources Managing RTL Source Files Managing Constraints Managing Simulation Sources Managing IP Cores Importing XPS Embedded Processor Designs Using the Project Summary view Configuring Project Settings You can use the PlanAhead application at different points in the FGPA
498. operties View Tab Options General e Name Defines the run name e Part Displays the target part for the current run and allows you to change the default part for the run The target part is defined under Project Settings but can be changed in the Run Properties form See Configuring Project Settings in Chapter 3 for information on setting the target part for the entire project To change the target part for a specific synthesis or implementation run the run must not be active This means that you must have more than one synthesis or implementation run defined in order to make the run inactive by making another run active See Creating and Managing New Runs in Chapter 9 for more information When the run is not the active run the browser button in the Run Properties view will allow you to change the target part See Selecting a Default Part in Chapter 3 for more information on setting the target part e Description Provides a brief description of the current run strategy e Status Displays the status of the run e Synthesis Run Displays the parent synthesis run of a selected implementation run Note This field does not appear in the Synthesis Run Properties view e Constraints Accept or change the constraint set for the run e Run Directory Displays the location of the run data Options Displays the command line options and their currently set values Select a command option to see a description of t
499. opriately Note The Auto place I Os function is only available for Virtex 6 Virtex 7 Kintex 7 and Artix 7 device families Autoplace 1 0 Ports Autoplace I O ports A This wizard will guide you through the process of E automatically placing I O ports The automatic placer will honor I O bank constraints if any Which ports do you want to place All 703 10 ports 92 selected ports PlanAhead To continue click Next Cancel Figure 8 23 Autoplace I O Ports Wizard www xilinx com 273 UG632 v13 4 January 18 2012 Chapter 8 VO Pin Planning g XILINX 274 To automatically assign I O ports 1 Inthe I O Ports view choose the I O ports to place 2 Select e Tools gt I O Planning gt Auto place I O Ports or e Inthe I O Ports view Auto place I O Ports The Autoplace I O Ports wizard opens as shown in Figure 8 23 page 273 3 Select the group of I O ports to place and click Next If you select I O ports that have already been assigned to package pins the dialog box opens as shown in Figure 8 24 5 Select the I O ports to place click Next and then Finish in the Summary page Autoplace I O Ports Placed 1 0 Ports 3 of the 92 ports you are about to place already are assigned to package pins How do you want to treat these ports Keep these 3 ports in their current locations Find new locations for these 3 ports Figure 8 24 Autoplace I O Ports Wizard Placing Gigabit Transceiver
500. option then click OK G Import Source Conflicts Description One or more source files or Folders that you are attempting to copy to your project directory will conflict with existing sources in your project Would you like to overwrite these existing Files i View Conflicts What do you want to do Overwrite existing files Don t overwrite existing files Figure 3 19 Import Source Conflicts Managing Constraints 56 The PlanAhead tool provides flexibility for defining and using constraints in a project You can use a single UCF to add and maintain the design constraints or you can use multiple UCF files to organize the constraints into separate files Add the UCF while creating the project or later using Add Sources You can create multiple constraint sets to experiment with various types of constraints or store multiple versions of constraints Each constraint set can contain one or more constraint files You can open multiple designs referencing a single constraint set However you must be careful to manage changes made to multiple designs that reference the same constraint set If the PlanAhead tool detects unsaved changes in multiple designs it prompts you to select which design to save to the referenced constraint file Note This could overwrite unsaved constraint definitions in an unsaved design An Implemented Design contains a snapshot of the state of the constraint set used during the implementation ru
501. opy the results to a directory or repository to preserve the results to import the partition into future design iterations Preserving the partition results is called promoting the partition You can only promote partitions from successfully completed synthesis or implementation runs To promote partitions 1 Inthe Flow Navigator select Promote Partitions You can also use the Flow gt Promote Partitions command 2 The Promote Partition dialog box opens as shown in Figure 13 5 G Promote Partitions i Please select entire runs or specific partitions to be promoted This copies the partitions in implemented run to the specified promote directory After promoting runs you can import the partitions into runs Select Partitions to promote SS t tay ga Run Directory Description L top W usbEngined M usbEngine1 Select Implemented j Clear All Automatically manage Partition action and import location Figure 13 5 Promoting Partitions PlanAhead User Guide www xilinx com 385 UG632 v13 4 January 18 2012 Chapter 13 Using Hierarchical Design Techniques XILINX 3 Specify the directory to store the promoted partition The directory or data repository is where the partition and all of its required files are stored You will reference this location when importing partitions rather than re implementing them in future design iterations Note You should promote all partitions to a single
502. or debug is recommended even if another mode will be zaj used by the production design Bl Slave Serial BPI Up x8 BPI Up x16 BPI Down x8 BPI Down x16 Master SelectMap x8 Master SelectMap x16 Master SelectMap x32 Slave SelectMap x8 Slave SelectMap x16 Slave SelectMap x32 JTAG Header Virtex 6 FPGA TDO TDO TDI TMS TCK Select all Clear all Figure 8 8 Set Configuration Modes Dialog Box To set the device configuration modes 1 Select Tools gt IO Planning gt Set Configuration Modes e Click any configuration mode to view information including the schematic e Click Print to print a copy of the configuration diagram 2 Select the configuration modes you want and click OK When you set the configuration modes the associated I O pins display in the Config column of the Package Pins view The PlanAhead tool prompts you to automatically sort the Package Pins view using the Config column header to sort the pins as shown in Figure 8 9 Changes Found 3 The pins unique to the configuration mode s selected are shown in the Config column of the Package Pins view C Don t show this dialog again Figure 8 9 Sort Config Pins For more information about analyzing how the configuration modes might conflict with other multi function pins refer to Multifunction Pins page 257 PlanAhead User Guide www x
503. ore information 5 Main Viewing Area Displays the Project Summary and graphical views of the design Figure 4 2 shows that the main viewing area is split between data views and graphical views e Data views present tree and text views of design data such as the Sources Netlist and Property views e Graphical views such as the Schematic Device and Package views are displayed in the workspace area and are for interacting with the design and device resources See Working with Views page 102 for information on using these different views Netlist Design netlist_1 xc7k160tfbg676 Netlist zag ar Er ESSA S FORE 2 validForEgressFifo_9 FDRE G wbClk_BUFGP E E wbDataForInputReg FDRE i wbDataForInput_IBUF IBUI E wbDataForInput_IN _75_o1_INV_O LUT i wbDataForOutput FDRE l whbDataForOutput_OBUF T E wbInputData_O_IBUF IBUF l G wbInputData_1_IBUF IBUF E wbInputData_3_IBUF IBUF l E wbInputData_4_IBUF E wbInputData_5_IBUF IBUF E wbInputData_6_IBUF IBUF E wbInputData_ _IBUF IBUF G wbInputData_8_IBUF IBUF E wbInputData_9_IBUF IBUF E wbInputData_10_IBUF BUF i wbInputData_11_IBUF TE l wbInputData_12_IBUF IB E wbInputData_13_IBUF BUF E wbInputData_14_IBUF IBLF amp Sources Netlist amp Timing Constraints UCF Instance Properties le gt 6R E wbInputData_2_IBUF TFU_DECAT VACC ROTO IOSTANDARD DEFAULT IS_BEL_FIXED 1S_BLACKBOX 1S_LOC_FIXED
504. ormation on using the MIG Memory Generator MIG refer to http www xilinx com support documentation ipmeminterfacestorelement_meminterfacecontrol_mig htm e For information on specific IP refer to http www xilinx com ipcenter or the IP Catalog Refer to http www xilinx com ipcenter axi4 htm for information on AXI IP Instantiating IP into the Design After you customize the IP and add it to your project the IP displays in the Sources view under the IP folder Expanding the IP core in the Sources view displays the CORE Generator XCO file and the VHO VEO file containing the instantiation template that you can copy and paste into your design RTL Figure 3 28 shows instantiated IP RTL code ae i a a Pe corial Projects project_wave_gen_hdliproject_wave_gen_hdl srcs sources_1 ip fifo_generator_v6_1_ gt es B g g yA 3177 in parentheses to your om signal names lee Design Sources 24 an ve H Verilog 21 S f Begin Cut here for INSTANTIATION Template INST_T GB IP 3 34char_fifo YourInstanceName iF char_Ffifo 4 ia 35 rst rst dF o char_fifo xco i 36 wr_clk wr_clk Be Sa rd_clk rd_clk B e char_fifo_xmdf tcl X 38 din din Bus 0 coregen log l 39 ur_en wr_en 8 2 clk_core 4 Py 40 rd_en rd_en Hi samp_ram 4l dout dout Bus 7 0 B Constraints 1 a 42 full full Stag constrs_1 B43 empty empty J e wave_gen
505. ot pose any problems in the FPGA implementation but are reported by the Tcl console when the Implemented Design is opened www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Analyzing Timing Results You can examine sort and select specific paths and instances in the Timing Results view Selected paths are displayed in the Device view and view properties of the path displayed in the Path Properties view In the Timing Results view the following information displays for each path e Name Shows a sequential number with which to sort back to the original order e Type Displays whether the path is Setup or Hold related e Slack Displays the total positive or negative slack on the path e From Displays the path source pin e To Displays the paths destination pin e Total Delay Lists the total estimated delay on the path e Logic Delay Lists the delay attributed to logic elements on the path e Net Delay Lists the delay attributed to the interconnect of the path e Logic Displays the percentage of the delay attributed to logic elements e Net Displays the percentage of the delay attributed to interconnect e Stages Displays the total number of instances on the path including the source and destination which contribute to the overall delay e The stages reported might be different than levels of logic reported in ISE e Source Clock Displays the source clock name
506. ou captures the Tcl commands froma session You can replay the journal file to reproduce the commands of the previous session You can create Tcl scripts by copying commands from the journal file for later replay It might be necessary to edit this file to remove any erroneous commands or commands from multiple sessions prior to replay Note Not every action logs a Tcl command into the journal file Error Log Files planAhead_pidxxxx debug amp hs_err_pidxxxx log The error files can provide valuable information for debugging the PlanAhead tool in the event of an unexpected interrupt If the PlanAhead tool issues a dialog box that warns of an internal exception error the error files are stored When you open a case with Xilinx Technical Support include any generated error log files the journal file p lanAhead jou and the log file 1anAhead 10g These files contain no design data DRC Results results_x_dre txt Results from the Design Rule Checks DRC are reported in the results_x_drc txt files Each time DRC is run a new file is produced with the same name as specified in the Results Name field of the Run DRC dialog box unless a different file name is specified in the Output File field Timing Analysis Results Excel file The results from timing analysis can be exported into a text file To export the data select Export Statistics in the Timing Results view Netlist Module Pblock and Clock Region Sta
507. ount and represents the margin that the weakest drive of a high signal is above the JEDEC input thresholds These margin values assume the weakest drive conditions JEDEC specification termination and standard receiver requirements for the standard This is one place where conservative assumptions are made in the analysis providing some guard band e Remaining Displays the amount of noise margin that is left over after accounting for all SSN in the bank Result Displays a Pass or Fail condition with failures in red Notes Displays information about the I O bank or groups The SSN results are relative to the state of the design when the SSN Analysis is run It is not a dynamic report www xilinx com 285 UG632 v13 4 January 18 2012 Chapter 8 VO Pin Planning XILINX 286 Improving SSN Results To improve SSN results when a violation occurs Use I O standards that have a lower SSN impact for the failing group Changing to a lower drive strength a parallel terminated DCI I O standard or a lower class of driver can improve SSN for example changing the SSTL Class II to an SSTL Class I Spread the failing pins across multiple banks This reduces the number of aggressive outputs on the power system of one bank Spread the failing group s across multiple synchronous phases See the following note regarding phase groups If the Result is a Fail condition assign phase groups to ports that are switching con
508. ource Estimation or e Resource Estimation from the RTL Design menu in the Flow Navigator The Resource Estimation view displays in the workspace Figure 5 3 page 179 shows an example of the Resource Estimation view www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Elaborating and Analyzing the RTL Design Resource Utilization Estimated resources are compared with xc6vlx 5tff784 3 Confidence Level High Register Available ees 93120 Estimation G S 17757 19 of available top LUT Available a 46560 Estimation 7 S 25154 54 of available top Block Memory Available Le 156 Estimation gt i 134 85 of available top of available R usbEngineO usbf_top T usbEngine1 usbf_top ble cpuEngine or1200_top E FFtEngine fftTop HE 16 10 of available R mgtEngine mgtTop Block Arithmetic Available ees 268 Estimation 36 12 of available top Clock Manager Available Estimation 56 of available top Figure 5 3 Resource Estimation View for the RTL Design The Resource Estimation view shows the resource utilization of device resources such as registers LUTs and block memory The resources displayed in the Resource Estimation view is based on the logic hierarchy of the design If a specific type of device resource is not used by the RTL design it is not displayed A note at the bottom of th
509. outside of the PlanAhead tool G Specify Launch Options Launch Directory lt Default Launch Directory gt Options Launch Runs on Local Host Number of Jobs 2 v O Generate scripts only i Cancel Figure 6 5 Synthesis Launch Options Creating and Managing New Runs You can create and launch new synthesis and implementation runs to explore design alternatives and find the best results See Creating and Managing New Runs in Chapter 9 for a detailed discussion of these tasks Monitoring the Synthesis Run PlanAhead User Guide You can monitor the status of a Synthesis run by reading the compilation log in the Compilation view or viewing the synthesis information warnings and errors in the Messages view See Monitoring the Implementation Run page 295 for more information Selecting any message in the Messages view opens the associated RTL source file and cross selects the appropriate line of code Figure 6 6 page 204 shows this interaction between the Messages view and the Text Editor This lets you find and resolve issues that occur during Synthesis www xilinx com 203 UG632 v13 4 January 18 2012 Chapter 6 Synthesizing the Design XILINX E Mmux_GND_6_0_GND_6_o_mux_40_OUT36 LUT6 48 output 31 0J dout i Mmux_GND_6_0_GND_6_o_mux_40_OUT42 LUT6 49 output empty G Mmux_GND_6_0_GND_6_o0_mux_40_OUT43 LUTS G Mmux_GND_6_0_GND_6_o0_mux_40_OUT44 LUTS 50 output full C Mmux_GND_6_0_GND_6_o_m
510. overed in more detail in the specific view sections of this document Using the Main Menu Command Search The PlanAhead tool provides a Command Search field on the main menu bar at the top right corner of the viewing environment to quickly locate and execute a command from the main menu Enter a few letters of a command name and a list of commands that match your search criteria displays The search mechanism employs a wildcard search of the form value where value is the string of characters you typed in the search field For example in Figure 4 23 typing the letters c1 in the Command Search field found the following commands Clear List Clock Regions Clock Resources Close Project Run Tel Script Tcl Console Clear Prohibit and Clear Placement These last two are inactive due to the current state of the example project ad Clear List ma Clock Regions Clock Resources Close Project EL Run Tel Script A Tcl Console Figure 4 23 Main Menu Command Search 108 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Working with Views The list of commands presented is based on the current design context in the project An open RTL design offers a different set of commands than an open implemented design In addition to commands the command search field reports project names and files that are listed under the Open Recent Project and Open Example Project commands on the main menu
511. ow Navigator click Program and Debug Flow gt Generate Bitstream Figure 12 1 shows the command e a I Program and Debug F Generate Bitstream Configure and launch bitstream Figure 12 1 Running the Generate Bitstream Command The Generate Bitstream dialog box opens as shown in Figure 12 2 page 370 PlanAhead User Guide www xilinx com 369 UG632 v13 4 January 18 2012 Chapter 12 Programming and Debugging the Design g XILINX G Generate Bitstream i Create a programming bit file For the design Use iMPACT to program the FPGA device or generate a PROM programming file From the generated bitstream Options a OOOOOooOooH J b 4 m t n u a f 4 bd More Options Select an option above to see description of it Figure 12 2 Generate Bitstream Dialog Box You can set ISE BitGen options prior to running the command When you select an option a description of the option displays in the dialog box For more information about BitGen options see the Command Line Tools User Guide UG628 cited in Appendix E Additional Resources 2 Click OK to start BitGen You can view the command status in the Compilation view and Messages view and the BitGen report file in the Reports view after it completes PlanAhead generated the resulting bit file in the project Run directory Debugging the Design with ChipScope The PlanAhead application is integrated with the ChipScope
512. ower Netlist Properties Og x e gt alk E top RTL Hierarchy Power Child Power mW Logic BRAM DSP48 Hard IP cpuEngine 65 3 56 l fftEngine 239 62 55 122 mgtEngine 626 1 44 0 583 usbEngined 110 ala 33 0 usbEnginel 110 11 99 0 wbArbEngine 14 14 0 0 Total 1165 107 353 122 583 RTL Macro Resources Macro type Flop LUT BRAM DSP48 Bitwise Logic 0 3503 0 0 Unary Logic 0 220 0 0 Arithmetic 0 3963 0 68 Comparators 0 4862 0 0 Multiplexers 0 11000 0 0 Shifters 0 261 0 0 Storage 16772 265 134 0 Total 16772 24074 134 68 RTL Hierarchy Resources Child Flop LUT BRAM DSP48 cpuEngine 3913 5387 30 4 fftEngine 1988 1975 16 64 mgtEngine 715 710 16 0 usbEngine 4638 6419 36 0 usbEnginel 4638 6418 36 0 whbArbEngine 880 3165 0 0 Statistics Partition Figure 5 8 Netlist Properties with Power Table Note The Hard IP column includes all the other resources such as clock managers gigabit I Os PCle and EMAC When you select a hierarchical instance from the RTL Netlist view the Instance Properties view opens also The Statistics tab of the Instance Properties view displays the RTL Hierarchy Power table presenting the power distribution by resource type for each module instantiated from this level shown in Figure 5 9 page 188 PlanAhead User Guide www xilinx com 187 UG632 v13 4 January 18 2012 Chapter 5 RTL Design XILINX Instance Properties Op x B E usbEngine1 RTL Hierarchy
513. p Slacks ns 5 Slack Type 11 527 Pin 11 527 Pin 11 284 Pin 11 284 Pin 11 284 Pin 11 284 Pin 11 284 Pin 10 Group TS_cpuclk TS_cpuclk TS_cpuclk TS_cpuclk TS_cpuclk TS_cpuclk TS_cpuclk Corner Figure 7 24 Slack Histogram Source Clock Destination Clock TS_wbClk rising TS_cpuclk rising TS_wbclk rising TS_cpuclk rising TS_wbClk rising TS_cpucClk rising TS_wbClk rising TS_cpucClk rising TS_wbClk rising TS_cpucClk rising TS_wbClk rising TS_cpucClk rising TS_wbClk rising TS_cpucClk rising To change the scale of the Y axis to be either logarithmic or linear click Plot Z histogram on log10 scale Figure 7 25 page 239 displays an example of the slack histogram graph view using a logarithmic scale 238 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using Slack Histograms E Project Summary X Device X 8 Clock Interaction results_1 gt l Histogram results x EFE Endpoint Setup Slacks ns 5 10 E S a 2 1 fal 2 amp 3 b uJ e 3 i 2 E 5 z 26561 items from 11 528 ns to 25 382 ns Id Name Slack Type Group Corner Source Clock Destination Clock D gt 1 cpuEngine cpu_dbg_dat_o buffer_fifo Mram_Ffifo_ram DIADI 25 11 527 Pin TS_cpuclk TS_wbClk rising TS_cpucClk rising D gt 2 cpuEngine cpu_dbg_dat_o buffer_fifo Mram_fifo_ram DIADI 28 11 527 Pin T
514. pad_1_o 2 Output LYCMOS25 2 5 12 SLOW default H D RXP_IN 8 Input RXN_IN LYDS_25 default S F TXP_OUT 8 Output TXN_OUT LYDS_25 2 5 default HQ Control_pad_0_o 4 Output LYCMOS25 2 5 12 SLOW default S A V Control_pad_1_o 4 Output LYCMOS25 2 5 12 SLOW default tH De Status_pad_0_i 8 Input LYCMOS25 2 5 12 SLOW default _ H B vStatus_pad_1_i 8 Input LYCMOS25 25 12 SLOW default H or1200_pm_out 4 Output LYCMOS25 2 5 12 SLOW default lt o Figure 4 65 O Ports View Li 9 MPa Hi PIB The Port view e Lists the port signal names direction package pin bank I O Standard Drive strength Diff pair partner Slew type voltage requirements and other signal information for each I O port e Shows table values as follows e Blank if they are default values e Anasterisk for non default values e Red when they are illegal or undefined values e Shows cells with editable values in the I O Ports view either enter text or select text from drop down menus e Buses are in expandable folders that can be selected as one object for analysis configuration and assignment Using I O Ports View Commands In the I O Ports view you can e Create I O Ports manually in I O Planning projects using Create I O Port e Select and group ports together into interfaces using the Create I O Port Interface toolbar button or popup menu command You can select and place these interfaces as one object within th
515. pecify RTL source files to create a project This can be used for RTL code development and analysis purposes as well as synthesis and implementation See Chapter 5 RTL Design for more information on RTL development and analysis 1 Follow the project creation steps previously described in Creating a New Project page 35 36 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Creating a New Project 2 In the Design Source page shown in Figure 3 2 page 36 select the Specify RTL Sources option Importing Settings from XST or Synplify Projects You can import an existing project file created for either XST or Synplify synthesis tools This lets you add the source files from those projects to the new project Settings such as top module target device and VHDL library assignment can also be imported from these existing project files To import an existing XST or Synplify project file 1 Inthe Design Source page click the checkbox for Import settings from XST or Synplify project beneath the Specify RTL Sources option 2 Select one of the following options from Import Settings in either the XST or Synplify Project dialog box e Import XST Browse to specify an existing XST project file xst e Import Synplify Browse to specify an existing Synplify project file prj e Do not import settings at this time Do not specify an existing project file at this time and instead pro
516. pertinent to design analysis and floorplanning It is important to ensure the proper view layout is loaded for the desired design task For more information about using the PlanAhead tool viewing environment see Chapter 4 Using the Viewing Environment For more information about configuring and loading view layouts refer to Using View Layouts in Chapter 4 PlanAhead Processes within Project Navigator Project Navigator and the PlanAhead tool are two independent environments operating under a separate system process The two processes are integrated to ensure that data is PlanAhead User Guide www xilinx com 403 UG632 v13 4 January 18 2012 Chapter 15 Using PlanAhead With Project Navigator XILINX passed effectively between the two tools Changes to design data in one tool are not recognized automatically in the other in real time and you should not to edit logic or constraints simultaneously in both tools Invoke PlanAhead for the intended purpose and close it before updating the Project Navigator design data The Project Navigator process steps are synchronized to recognize edits to the User Constraint File UCF made in the PlanAhead tool after saving the data The following sections describe the steps involved and the data transactions that enable the integration Passing Logic and Constraints The PlanAhead tool in ISE Integration mode enables only physical constraint modification for I O pins logic LOC and AREA_GROUP cons
517. play updated to focus on the selected object Various workspace views offer different methods for doing this as described in the following sections Automatically Displaying Selected Objects PlanAhead User Guide When selecting objects in the Sources view or Netlist view the objects become cross selected in the graphical workspace view such as the Device view or the Schematic view However these objects can be small and difficult to see because of the volume of information that may be displayed or the current zoom level of the view The PlanAhead tool provides a Auto Fit selection command on the toolbar menu of graphical workspace views to help display selected objects Enable this command so that the workspace view is always redrawn to display the selected object Disable the command so the view is not redrawn every time an object is selected V The PlanAhead tool automatically corrects the zoom factor to allow multiple objects to be displayed when more than one object is selected www xilinx com 113 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX 114 Fit Selection Views in the workspace also have an interactive zoom command Fit Selection to fit all selected objects Use this command when the Auto Fit Selection mode is disabled To zoom fit the selected objects use one of the following methods e Select View gt Fit Selection e Press F9 e Click the Fit Selection toolbar button
518. port timing results from the TWR or TWX format timing report files generated by the TRACE command run outside of the PlanAhead tool The TRACE software outputs the following timing reports based on options specified on the command line TWR default timing report The e error report and v verbose report options can be used to specify the type of timing report you want to produce a summary report the default an error only report or a verbose report TWX an XML timing report output by using the xml option This report is viewable with the Timing Analyzer GUI tool The e error report and v verbose report options apply to the TWX file as well as the TWR file See the xm1 XML Output File Name section for details To import TRACE timing results into the PlanAhead tool www xilinx com 347 UG632 v13 4 January 18 2012 Chapter 11 Analyzing Implementation Results g XILINX Fab ba 348 1 Select File gt Import gt Import Timing from the main menu You must have an open RTL Netlist or Implemented Design for the Import Timing command to be available See Working with Designs page 27 for more information 2 Edit the dialog box fields e File Name Select a TWX file from which to import results Note You can alternatively select to import a TWR format file if the TWX file does not exist If both files exist TWX is the preferred format to use to import timing results e Results Name Def
519. processes the files The first file in the list is the first file processed If the same constraint appears in more than one constraint file the last file read has precedence in defining the constraint e Copy Constraints into Project Mark the checkbox to copy constraint files into the local project directory instead of referencing the original files Setting the Target UCF When you add multiple UCF files to a project you must define the target UCF The PlanAhead tool writes newly created constraints to the target UCF Existing constraints that are modified during design are written back to the UCF from which they originated not the target UCF You can change the target UCF at any time using the Set Target UCF command from the Sources view Note NCF and XCF files cannot act as a target for new constraints New constraints must be written to a UCF Referencing Original UCF Files or Copying Files As with other source files you can add UCF files to reference from a remote location or copy the files locally into the project directory when they are added When you add remote files the PlanAhead tool automatically detects the latest file version and prompts you to Reload the design with the latest files To copy files into a project select Copy Constraints into Project from the Add Constraints dialog box See Using Remote Sources or Copying Sources into Project page 55 for more information Using Constraint Sets A constraint
520. pter 11 Analyzing Implementation Results and Chapter 10 Floorplanning the Design Analyze Timing Floorplan Design Post Implementation You can use the PlanAhead tool design analysis and floorplanning environment after Implementation When you analyze the design after Implementation you can view the placement and timing results to catch potential design issues Often physical LOC or AREA_GROUP floorplanning constraints can help drive the Implementation tools toward better and more consistent results and reduce Implementation runtimes To analyze the design or to perform floorplanning from Project Navigator after Implementation e Inthe Process pane expand Implement Design expand Place amp Route and double click Analyze Timing Floorplan Design PlanAhead Post Synthesis or e Select Tools gt PlanAhead gt Post Implementation gt Analyze Timing Floorplan Design 406 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX PlanAhead User Guide PlanAhead Processes within Project Navigator Project Navigator passes the following files to the PlanAhead tool when it opens e Synthesized NGC or EDIF format netlist e UCF s e ISE placement data e Timing results e Block RAM Memory Map BMM files The PlanAhead tool is invoked with the default design analysis and floorplanning environment displayed For the PlanAhead tool to extract the ISE placement data it must convert the Native Circui
521. pter 3 Working with Projects g XILINX 44 Creating a Project with a Synthesized Netlist A second project type of begins with a synthesized netlist and corresponding constraints You can then analyze floorplan and implement the design using the Floorplanning and Implementation environment 1 Follow the project creation steps described in Using the New Project Wizard page 35 2 Select the Specify synthesized EDIF or NGC netlist option in the Design Source page Selecting a Top Level Netlist and Module Search Path The next page in the New Project wizard shown in Figure 3 9 lets you specify netlist files to read identify the file containing the top level module and define directories to search for lower level module netlist files G New Project Add Netlist Sources Specify netlist Files to add to your project Use the Add Files button to select the file that contains the design Top module and part i bft_test edF C Data FPGA_design Ga 2 FPGA_design C Data Copy Sources into Project Add Sources from Subdirectories Id Name Top Location Add Files Add Directories Cancel Figure 3 9 New Project Wizard Specify Netlist Files Edit the definable options Add Files Invokes a file browser so you can select netlist files NGC or EDIF to add to the project Top Enable the radio button for the file containing the top level netlist Add Directories Select
522. pter 8 I O Pin Planning for more information You can e Examine the internal I O connectivity to ensure proper data flow through the device as well as optimal access to internal device resources e Improve system performance by examining both the external and internal connectivity requirements and then making informed decisions e Use DRCs and Simultaneous Switching Noise SSN analysis to ensure compliance to connectivity requirements e Use a variety of source input formats to begin I O pin planning including CSV UCF RTL or synthesized netlists When you use a synthesized netlist as the source the DRC coverage improves substantially because often the clock logic dictates proper I O assignment The final I O verification step is to run the complete design through the implementation tools Netlist Analysis and Constraints Definition The PlanAhead tool has design analysis and constraints assignment capabilities The design data is presented in different forms using cross selecting and coordinating views The PlanAhead tool provides interactive graphical views of the internal die and external package with which you can analyze device resources and apply constraints You can also apply and analyze timing and physical constraints Early timing analysis including timing simulation resource estimation connectivity analysis and DRCs help identify design issues prior to Implementation Implementation The PlanAhead tool lets you
523. ption and what it is used for in the lower dialog pane An asterisk next to an option name indicates that the value is currently set to a non default value For more information about specific ISE software options see the Command Line Tools User Guide UG628 cited in Appendix E Additional Resources Note If you exit the PlanAhead tool before running the modified Implementation run the options are not preserved If Implementation results exist in the project the project settings are inherited when you open the project If no Implementation run exists in the project the PlanAhead tool uses the default options www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Running Implementation Launching an Implementation Run To launch an Implementation run click the Implement button from the Flow Navigator or main toolbar gt The current Implementation project settings are used to launch the run ath Configuring Implementation Run Settings To set the Implementation run options use the Implementation Settings in the Flow Navigator Implementation button pulldown menu as shown in Figure 9 2 D _ Implementation Setting amp Create New Implementation Runs AN a inal Figure 9 2 Configuring Implementation Run Settings The Implementation Settings dialog box displays as shown in Figure 9 3 G Implementation Settings i Change implementation options and launch the run Options
524. ptions then click Next e Import CSV Select a CSV format file with I O Ports definitions in the defined PlanAhead file format See I O Port Lists CSV File Format page 410 for a specification of this file e Import UCF Select a UCF with I O Port related constraints only e Donot import I O ports at this time Create an empty project You can create or import I Os later Note Use an RTL Source project to perform I O pin planning on a design using RTL header or source files Define a default part as discussed under Selecting a Default Part page 42 The New Project Summary page displays the options you selected to define the project Click Finish to create and open the project Creating a Project with ISE Placement and Timing Results Another type of project lets you import netlists with ISE Placement and Routing PAR results along with corresponding constraints and project settings This is used to analyze the PAR results using the implementation and analysis environment in the PlanAhead tool 1 2 4 Follow the project creation steps described in Using the New Project Wizard page 35 Select the Import ISE Place amp Route results option in the Design Source page The steps for creating this project type are the same as creating a synthesized netlist project except this project type asks for the ISE placement and timing files Specify the top level netlist and search directories as described in Selecting
525. ptions Timer Settings Delay type max Significant digits 2 C Only report timing paths between asynchronous clocks Command report_clock_interaction delay_type max sigil C Open in a new tab Figure 7 26 Report Clock Interaction Options Tab e Path Delay Type Specifies the type of delays that are used in the Clock Interaction analysis This field contains the following options e Max Uses maximum delays for the clock and data paths during setup and hold analysis e Min Uses minimum delays for the clock and data paths during setup and hold analysis e Min_Max Uses a combination of minimum and maximum delays for the clock and data paths during setup and hold analysis e Significant Digits Determines the significant digits reported in the Clock Interaction report Specified values from 0 to 13 e Only report timing paths between asynchronous clocks A switch limiting the Clock Interaction Report to analyzing asynchronous clock domains This lets you focus on the endpoints of specific paths that might present special challenges www xilinx com 241 UG632 v13 4 January 18 2012 Chapter 7 Netlist Analysis and Constraint Definition g XILINX Using the Timer Settings tab The Timer Settings tab has three fields or switches as shown in Figure 7 27 G Report Clock Interaction Results Name results 1 Interconnect estimated Speed Grade 3 default Multi Corner Configuratio
526. r searching the selected files The Find in Files view displays at the bottom of the PlanAhead environment with the results of the search Change Editor Style Lets you edit the fonts and colors associated with the Text Editor See Setting Fonts for Text Editor page 169 for more information Language Templates Opens the Templates view for you to use the Xilinx Language Templates to insert into your text file See Instantiating Language or Constraint Templates page 159 for more information www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Using the Text Editor e Insert Template Inserts the currently selected Language Template into your text file at the location of your cursor e Go To Beginning End Moves the cursor to the start or end of the open file Instantiating Language or Constraint Templates The PlanAhead tool provides standard Verilog and VHDL language templates and UCF constraint templates for use with the Text Editor to quickly define certain logic constructs or design constraints Selected templates can be instantiated into any file that is open in the Text Editor Figure 4 68 shows the Template view with a selected language template H 5 Spartan 3 H 5 Spartan 6 4 Virtex 4 H Virtex 5 A Virtex 6 9 irtex 7 Device Macro Instantiation B Kintex 7 i gt RAM A Single Port RAM BRAM_SINGLE_MACRO Simple Dual Port RAM BRAM_SDP_MACRO B True Dual Port RAM BRAM
527. r Guide UG632 v13 4 January 18 2012 g XILINX Interfacing with ISE Outside of PlanAhead 3 Edit the options in the Export Constraints dialog box e File name Enter the file name and location to create the UCF e Export fixed location constraints only Select this option to export only user assigned fixed placement LOC constraints or uncheck it to export the fixed and unfixed placement constraints imported from ISE then click OK to export the constraints The PlanAhead tool creates the designated top level UCF format constraint file in the export directory You can use this file as input for custom ISE implementation scripts For more information about the exported files see Appendix A Outputs for Reports Exporting Netlist Exporting the PlanAhead Netlist to ISE consists of exporting a single EDIF format netlist file for the entire design or for individual Pblocks This requires an open Netlist Design To export the netlist from an open Netlist Design 1 Select File gt Export gt Export Netlist The Export Netlist dialog box opens 2 Edit the File name and location to create the EDIF format netlist file in the Export Netlist dialog box then click OK to export the netlist For more information about the exported files see Appendix A Outputs for Reports Exporting Pblocks for ISE Implementation PlanAhead User Guide The PlanAhead tool can export Pblock level files for Implementation These Pblocks
528. r XST Constraint File XCF found in the same directories as the RTL or Netlist source files you have already added to the project are listed automatically as constraint files to be added to the project The Add Constraints dialog box has the following options e Add Files Browse and select a UCF NCF or XCF to add to the project e Create File Create a new top level UCF for the project e Remove Remove the selected UCF from the constraint files list e Up Down Move a constraint file up or down in the listed order of the UCF Constraints are order dependent the last read definition of a constraint over writes earlier definitions e Copy Constraints into Project Check box copies constraint files into the local project directory instead of referencing the original files After adding the constraint files and setting the target UCF click Next Selecting a Default Part The New Project wizard prompts you to select a default part as shown in Figure 3 8 page 43 42 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Creating a New Project G New Project Default Part Choose a default Xilinx part for your project This can be changed later Filter Product All Package Family virtex6 Speed Grade Sub Family virtex6 LXT Temp Grade rm Search Device I O Pin Count Available IOBs Slices LUT Elements FlipFlops BlockRAMs DSPs xcvlx75tff484 1 484 240 11640 46560 931
529. r more information about specific XST and ISE software options see the Command Line Tools User Guide UG628 cited in Appendix E Additional Resources 4 To create a new strategy copy a provided strategy by using the Create a copy of this strategy toolbar button or from the popup menu 5 The PlanAhead tool creates a copy of the strategy in the User Defined Strategies list and displays the command line options on the right side of the dialog box for you to modify 5 Provide a name and description for the new strategy as follows e Name Enter a strategy name to assign to a run e Description Enter the strategy description which is displayed in the Design Run results table Click a command option to view the option description at the bottom of the dialog box Modify command options by clicking in the command option area to the right and selecting an option from the pulldown menu or typing a new value Available command option settings display in the popup menu as shown in Figure 4 74 Notice that you cannot change the default options for predefined PlanAhead tool strategies Name My_New_Strategy Description ISE Defaults including packim Options Translate ngdbuild a ur 3 a aul u f bm More Options Map map lt none gt v smartquide 000d ir o b v acn lt none gt pr Pack internal flops latches into input i output o or both b types of IOBs Figure
530. r power performance or area optimization The Synthesis run results display interactively and the PlanAhead tool creates report files that you can access Select synthesis Warnings and Errors from the Compilation Messages view to highlight the logic in the source files e You can launch multiple Synthesis runs simultaneously or serially e Ona Linux system you can launch runs locally or on remote servers When you have multiple Synthesis runs those runs create multiple netlists that are stored within the PlanAhead tool project The PlanAhead tool then lets you load the various versions of the netlist into the environment for analysis After the netlist import you can perform device and design analysis and create constraints for I O pin planning floorplanning and implementation The most comprehensive list of Design Rule Checks DRCs is available after a synthesized netlist is produced when clock and clock logic are available for analysis and placement I O Pin Planning PlanAhead User Guide The PlanAhead tool provides an I O pin planning environment that enables correct by construction I O port assignment either onto specific device package pins or onto internal die pads The PlanAhead tool offers a variety of display views and tables in which www xilinx com 21 UG632 v13 4 January 18 2012 22 Chapter 2 The PlanAhead Tool Flow XILINX to analyze and design package and design I O related data Refer to Cha
531. r project Create a new source file on disk and add it to your project Id Name Library Location async_fifo y work C xilinx 13 1 ISE_DS Plan4headitestcases Plan4head_Tutorial Sources hdl bft vhdl work C xilinx 13 1 ISE_DS Plan4head testcases Plan4head_Tutorial Sources hdl bft_tb work C xilinx 13 1 ISE_DS Plan4head testcases Plan4head_Tutorial Sources hdl FftTop work C xilinx 13 1 ISE_DS Plan4head testcases Plan4head_Tutorial Sources hdl FifoBuffer y work C xilinx 13 1 ISE_DS Plandheaditestcases Plan4head_Tutorial Sources hdl bFtLib bftLib vw C xilinx 13 1 ISE_DS Plan4head testcases Plan4head_Tutorial Sources hdl Add Files Add Directories Create File Scan and Add RTL Include Files into Project Copy Sources into Project Add Sources From Subdirectories Figure 3 15 Add Sources Dialog Box Adding RTL Sources The available commands and options of the Add Sources dialog box are e Add Files Opens a file browser so you can select RTL files to add to the project e Add Directories Opens a directory browser to add RTL source files from the selected directories Files in the specified directory with valid source file extensions are added to the project e Library Specify the RTL library for a file or directory by selecting one from the currently defined library names or specify a new library name by typing in the Library text field e HDL Source for Specify if the source being loaded is an RTL d
532. r to the device specific clocking resources guide www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Placing Clock Logic E Project Summary x Device x Package x Clock Resources x A 5 xc6vix75tff784 3 Top Half amp CMT y 2 Site Instance E MMcM_ADY_xovS Clock Region I O Bank 16 Clock Region I O Bank 26 Site Instance E BUFR_xOYS E BUFR_X0Y4 E BUFIODQS_XOY E BUFIODQS_XO0Y E BUFIODQS_XOY E BUFIODQS_XO0Y E 321 S5R E 322 5R E B27 MR E B28 MR E E25 MR E F24 MR E D27 5R E C28 5R 5 GT Bank 116 Site Instance E GTXE1_xov11 E GTxe1_xov10 GTXE1_xOv9 GTXE1_x0Y8 D2 TXNS A4d RXNS 5 m Clock Region I O Bank 36 Site Instance BUFR_X2Y5 5 BUFR_X2Y4 E BUFIODQS_x2y BUFIODQS_X2 BUFIODQS_X2 BUFIODQS_X2 D10 5R c10 5R F7 MR G7 MR H11 MR H10 MR W2 5R K13 5R FA TXP2 E G4 REFCLK1P G3 REFCLKIN cen T E J4 REFCLKOP E J3 REFCLKON E H2 TXN1 E C4 RXN1 E H1 TXP1 E C3 RXP1 E K2 TXNO E E4 RXNO E K1 TXPO E E3 RXPO Clock Region X1 1 Clock Region I O Bank 25 a Clock Region I O Bank 35 GT Bank 115 Site Instance MMCM_ADV_XOY3 Site Instance Site Instance E MMcm_ADV_xOv2 BUFGCTRL_X0Y31 BUFGCTRL_X0Y30 BUFR_X1Y3 BUFR_X1Y2 BUFR_X2Y3 GTXE1_X0Y7 BUFR_X2Y2 GTXE1_XOY6
533. r_fifo_dout mark_debug true END Synplify Syntax Examples PlanAhead User Guide The following are examples of Synplify syntax for VHDL Verilog and SDC VHDL Syntax Example attribute syn_keep boolean attribute mark_debug string attribute syn_keep of char_fifo_dout signal is true attribute mark_debug of char_fifo_dout signal is true Verilog Syntax Example www xilinx com 373 UG632 v13 4 January 18 2012 374 Chapter 12 Programming and Debugging the Design XILINX syn_keep true mark_debug true wire 7 0 char_fifo_dout SDC Syntax Example define_attribute n char_fifo_din mark_debug true Note Net names in an SDC source must be prefixed with the n qualifier See About SDC page 401 for more information Precision Syntax Examples The following are examples of VHDL and Verilog syntax when using Precision VHDL Syntax Example attribute mark_debug string attribute mark_debug of char_fifo_dout signal is true Verilog Syntax Example mark_debug true wire 7 0 char_fifo_dout Using the ChipScope Wizard for Debug Core Insertion The Set up ChipScope debug wizard is the easiest and fastest way to add debug cores in the PlanAhead tool To use the Set Up ChipScope wizard to insert debug cores 1 Optionally select a set of nets for debug either using the unassigned nets list or direct net selecti
534. ration flow to create and manage various design configurations Opening the Design Runs View Select Window gt Design Runs to invoke the Design Runs view Figure 4 67 shows the Design Runs view Name v synth_1 vy impl_1 active impl_2 impl_3 impl_4 impl_5 EE R Tcl Console EJ Compilation Log PlanAhead User Guide Part Constraints Strategy Status Progress Start Elapsed 6vlx75t constrs_1 Plandhead Defaults XST 12 XST Complete E 100 2 27 10 1 42PM 00 00 1 6 lx75t constrs_1 ISE Defaults ISE 12 Bitgen Complete EEE 100 2 27 10 1 48 PM_ 00 03 11 6vlx75t constrs_1 ISE Defaults ISE 12 Not started Co 0 6vlx75t constrs_1 MapTiming ISE 12 Not started EA fi 6vlx75t constrs_1 MapGlobalOptParHigh ISE 12 Not started 0 6vlx75t constrs_1 MapLogicOptParHighExtra ISE 12 Not started RUMEN phy Compilation Messages Reports Figure 4 67 Design Runs View The view displays the status and results of the design runs defined and provides commands to modify import launch and manage the design runs Also this view is used to manage and report Synthesis and Implementation runs The view indicates the runs as follows e Currently running with a green arrow icon e Completed runs have a blue check mark icon Run information displays as the commands are being run You can close the PlanAhead tool without affecting in progress runs When you re open a project the PlanAhead tool updates the run
535. rce Data Type Designate the Design Source input format by selecting one of the options shown in Figure 3 2 page 36 G New Project Design Source Specify the type of sources for your design You can start with RTL or a synthesized EDIF O Specify RTL Sources You will be able to run RTL analysis synthesis post synthesis design analysis planning and implementation Specify synthesized EDIF or NGC netlist You will be able to run post synthesis design analysis planning and implementation Enable Partial Reconfiguration Create an I O Planning Project Do not specify design sources You will be able to do port assignment and verification Import ISE Place amp Route results You will be able to do post implementation analysis of your design O Import ISE Project Create a Plandhead project from an ISE project file Cancel Figure 3 2 New Project Wizard Design Source Page Select the design source and click Next Depending upon the design input continue with the instructions in one of the following sections e Creating a Project with RTL Sources e Creating a Project with a Synthesized Netlist e Creating an I O Planning Project e Creating a Project with ISE Placement and Timing Results e Importing an ISE Project The next pages of the wizard guide you through adding appropriate sources to the project based on the project type you selected in the previous steps Creating a Project with RTL Sources You can s
536. rce file as not used in Synthesis and then open the RTL design you will see a black box for that source file Disabling an EDIF or NGC source file from implementation will prevent it from being used during implementation www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using Common Views However a Verilog or VHDL source file enabled for synthesis but disabled for implementation will cause the source to be synthesized into the output netlist and thus used during implementation To prevent RTL source files from being used during implementation you must disable the source file from synthesis Note The Used In attribute can also be set from within the Source File Properties view see Viewing Source File Properties G Set Library i Set the USED_IN_ properties for selected sources Used In Implementation Simulation Figure 4 41 Set Used In Add Sources Lets you add or create RTL source files simulation source files Constraint files or add existing IP to the project See Managing Project Sources in Chapter 3 Find in Files Invokes the Find in Files dialog box to enter text strings to search in the selected files The Find in Files Results view displays with the results of the search See Searching and Replacing in Source Files page 118 for more information Viewing Source File Properties PlanAhead User Guide Selecting an RTL source file in the Sources view displays inform
537. rea rectangles can provide useful pinout configurations from a PCB routing perspective www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Placing I O Ports Swapping and Moving Previously Placed I O Ports Working interactively you find occasions where you need to move or swap I O ports that have already been assigned You can select two placed I O ports and swap their locations with each other as follows 1 Select two I O ports from any of the available views Hold down the Ctrl key while clicking to select multiple ports 2 Right click and select Swap Locations If you swap two ports which are not yet fixed if you are viewing the implemented placement in the Implemented Design the act of swapping them also causes them to be fixed and the resultant LOC constraint are written to the design constraint file You can also move a port or groups of ports by selecting them and dragging them from one location to another When you move a group of ports from one I O bank to another the PlanAhead tool automatically finds suitable locations for the selected ports This is similar to using the Place I O Ports in an I O Bank command Automatically Placing I O Ports PlanAhead User Guide The Auto place I O Ports command can automatically assign all I O ports to package pins or any unplaced or selected I O ports The autoplacer obeys I O standard and differential pair rules and places global clock pins appr
538. reate Pblocks Create Pblock s from the following instances Instances 5 Id Name Cell Primitives E7 1 cpuEngine cpu_dwb_dat_i FifoBuffer a 2 cpuEngine cpu_dwb_dat_o FifoBuffer E7 3 cpuEngine cpu_dbg_dat_i FifoBuffer fi 4 cpuEngine cpu_dbg_dat_o FifoBuffer EF 5 cpuEngine cpu_iwb_adr_o FifoBuffer Ci eoe Cee Figure 10 3 Create Pblocks Wizard Create Pblocks from Instances e To add additional netlist instances to this list click Add which invokes a browser in which you can select other instances e To remove any netlist instances from the list click Remove e To clear netlist instances from the list click Clear Click Next The Create Pblocks wizard lets you specify a naming scheme In the Create Pblocks wizard edit the naming scheme fields e Prefix Defines a name prefix to be used for the Pblock names Enter a new prefix or allow the default instance name or number to be used e Suffix Select Instance name to append the instance name onto the prefix or select Numeric to append a number starting with 1 to the prefix Click Next Verify the contents in the Summary page Click Finish to create the Pblocks with these settings The Pblocks show in the Physical Constraints view as represented in Figure 10 4 page 313 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Working with Pblocks map block_cpuEngine E pblock_fftEngine
539. remote servers Toggle the Jobs option to specify how many processors on the remote machine to use Individual Runs are launched on each processor No multi threading of processors is used Toggle the Enable option to specify whether to use the server You can use this field when launching Runs to specify which servers to use for the selected Runs to be launched Optionally modify the launch jobs in the field to change the remote access command The default is ssh Note Be careful when modifying this field For example removing BatchMode yes could cause the process to hang because the shell incorrectly prompts for an interactive password Optionally click the Run pre launch script button and define a script to run prior to launching the Runs Use this option to pass an environment setup script if you do not have ISE set up upon login CSHRC or BASHRC Optionally click the Run post completion script button and define a custom script to run after the run completes Optionally click Send email to and enter an email address to send a notification when the run completes Select one or more hosts and click Test to verify that the server is available and the configuration is properly set Note It is strongly recommended that you test each host to ensure proper set up Click Remove to delete selected remote hosts or click OK to accept the Remote Host configuration settings www xilinx com 307 UG632 v13 4 January 18
540. results and apply constraints by clicking RTL Design Netlist Design or Implemented Design in the Flow Navigator Each of these Designs displays a set of commonly used sub tasks for the applicable phase of the flow Available options depend on the status of the design Inapplicable steps are greyed out until the appropriate design tasks are completed Figure 2 2 and Figure 2 3 page 25 illustrate how the Flow Navigator view is used to perform design tasks and to open the analysis environments at various stages of the design process Using the Flow Navigator with an RTL Project Figure 2 2 illustrates the design flow using RTL sources as input to the PlanAhead tool Run XST Synthesis e Configure and Launch Runs e Assign Run Strategies e View Results Run ISE Implementation e Configure and Launch Runs e Assign Run Strategies e Analyze Results Launch Programming and Debug e Run BitGen e Launch ChipScope Analyzer e Launch Impact e Launch FPGA Editor Figure 2 2 24 Project Manager Configure Project Sources Project Settings e Create and Manage Source Files e Browse Customize and Implement IP e Create and Manage Constraint Sets LF IP Catalog e Manage Project Settings ar Add Sources Fo Elaborate Load Elaborated RTL Designs m Behavioral Simulation fad ale Se View Compilation issues L Project Summary Analyze Logic Hierarchy and Connectivity JU ere Behavioral Simulation Early Resource
541. rk_debug constraint in VHDL and Verilog sources or in a Xilinx Constraint File XCF source For more information about the Mark Debug constraint see the Constraints Guide UG625 cited in Appendix E Additional Resources In addition to the boolean string values of true or false a value of soft allows the software to optimize the specified net if possible Note XST automatically supports this constraint for Spartan 6 Virtex 6 and newer devices For a synthesized netlist based project e Using the Synopsis Synplify synthesis tool you can optionally mark nets for debug using the mark_debug and syn_keep constraints in VHDL or Verilog or using the mark_debug constraint alone in the Synopsys Design Constraints SDC file Synplify does not support the soft value as this behavior is controlled by the syn_keep attribute e Using the Mentor Graphics Precision synthesis tool you can optionally mark nets for debug using the mark_debug constraint in VHDL or Verilog The following subsections provide syntactical examples for XST Synplify and Precision source files XST Syntax Examples The following are examples of VHDL Verilog and XCF syntax when using XST VHDL Syntax Example attribute mark_debug string attribute mark_debug of char_fifo_dout signal is true Verilog Syntax Example mark_debug true wire 7 0 char_fifo_dout XCF Syntax Example BEGIN MODEL wave_gen NET cha
542. roject However when there are multiple synthesis or implementation runs you can also change the part used for a specific run by changing the run settings from the Run Properties view See Using the Run Properties View in Chapter 4 for more information on setting design run attributes Target Language Specifies the target output language for the design as either Verilog or VHDL RTL output will be generated from the design in the specified target language Specific examples of output controlled by the target language are synthesis simulation top level wrappers test benches and instantiation templates Top Module Name Enter the top RTL module name of the design You can enter a lower level module name to experiment with synthesis on a specific module also www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX PlanAhead User Guide Configuring Project Settings G Verilog Options VYerilog Search Paths Add Directories Defines C Uppercase all identifiers Verilog Version Verilog 2001 Verilog 95 Verilog 2001 stem Verilog Figure 3 41 Verilog Options Language Options Enter specific Verilog and VHDL options e Verilog Options Specify Verilog search paths Macro definitions Uppercase identifiers and Verilog2001 language standard These fields are shown in Figure 3 41 Verilog Search Paths Specify the paths to search for files referenced by include statement
543. roperties View Attributes Tab To define new attributes for the Pblock 1 Inthe Attributes tab of the Pblock Properties View select Add pre defined dh attributes from the popup menu or the toolbar button The Add Pre defined Attributes dialog box opens as shown in Figure 10 18 G Add Pre defined Attributes Search PARENT WEIGHT GROUP IMPLEMENT PLACE Name Description Figure 10 18 Add Predefined Attributes 2 Select the attribute to assign then click OK The specified attribute type is added into the Attributes tab 3 You can then specify an attribute value and click Apply to accept the changes www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Configuring Pblocks Renaming a Pblock You can rename Pblocks using the General tab of the Pblock Properties view Enter the new Pblock name in the Name field and click Apply Alternatively you can modify the Name attribute on the Attributes tab of the Pblock Properties view Deleting a Pblock You can delete selected Pblocks as follows 1 2 3 In the Physical Constraints view select one or more Pblocks Press Delete In the Confirm Delete dialog box select the Remove Pblock children option to remove any nested Pblocks along with their partitions Otherwise when left unselected you delete the selected Pblock only and move any nested Pblocks up one layer of hierarchy Click OK to remove the Pblock p
544. rrn 354 Locking Placement for Future Implementation Runs 357 Displaying Design Metrics 00 00 o eens 358 Performing Timing Simulation 0 0 c cece eee 361 Analyzing Power Distribution with XPower Analyzer 368 Launching FPGA Editor iio ccac ceviwiwe ins nde needed desis cawrakaueien vies 368 Cross Probing Timing Paths to FPGA Editor 0 0005 368 Chapter 12 Programming and Debugging the Design Generating Bitstream Files 4407s hian ak cee deneeceiapawiedGdahe doe errre 369 Debugging the Design with ChipScope 0 0 00 c cece eee 370 Launching ChipScope Pro Analyzer 0 0 0 0 ccc cece cece eee 378 Leach IMPACT i circ oak Rea A ns Send ee itu un E s Belson heey Syl a a 379 Chapter 13 Using Hierarchical Design Techniques Using Partitions eeii paaria nia e iE EEE EEEE EEEE K 381 Promoting Partitions lt cic2i3 ia 6 Hehe eee LER Ahh rnr rreren 385 Importing Partitions 0s sce2senddstgveersysstteiadeeenebaieegusxeganes 387 Updating SOUTCES ase dyctas kicsire r beet wind EEEE E a aw Ei 387 Related Methodologies unnnnunnnnnurrinunrrnnrrrrunarrrru rernu 388 PlanAhead User Guide www xilinx com UG632 v13 4 January 18 2012 XILINX Chapter 14 Tcl and Batch Scripting Tel Jo rnal Piles p930y 9 ceva ksh ee kas eee ee eee ee ee 391 TelHelp rrene pri E bho dnd ia ee Kd kG lenges Ree A
545. rst time you access a new machine it prompts you for a password upon subsequent access it does not prompt If you are always prompted for a password contact your System Administrator to have your Linux account set up for passwordless SSH After a passwordless SSH is set up you can continue configuring the remote host Linux only PlanAhead User Guide www xilinx com 433 UG632 v13 4 January 18 2012 Appendix D Configuring SSH Without Password Prompting XILINX 434 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Appendix E Additional Resources The following are links to additional resources available for your use Xilinx Resources Device User Guides http www xilinx com support documentation user_guides htm Glossary of Terms http www xilinx com company terms htm ISE Design Suite Installation and Licensing Guide UG798 http www xilinx com support documentation sw_manuals xilinx13_4 iil pdf ISE Design Suite Release Notes Guide UG631 http www xilinx com support documentation sw_manuals xilinx13_4 im pdf Product Support and Documentation http www xilinx com support Hardware Documentation PlanAhead User Guide 7 Series Device Documentation http www xilinx com support documentation 7_series htm 7 Series FPGAs SelectIO Resources User Guide UG471 http www xilinx com support documentation sw_manuals xilinx13_4 ug471_7Series_Select
546. rt Figure 13 8 shows the Partition activity in an NGDBuild report Projects project_DP_import project_DP_import runs impl_1 top bld 72 Partition Implementation Status Preserved Partitions Partition top usbEngined Partition top usbEnginel 80 81 82 Implemented Partitions 83 64 Partition top 85 Attribute STATE set to IMPLEMENT e aa 5j ial x Ci E 2 EOE SOME x ie Figure 13 8 Partition Import Activity in the NGDBuild Report The PlanAhead tool copies successfully preserved partitions from the promoted area and pastes the partitions into a new run providing identical results for imported partitions Related Methodologies Team Design The PlanAhead tool provides an environment to create and manage multiple projects for independent and parallel development This Team Design flow supports Xilinx Synthesis Technology XST incremental synthesis and black box support throughout Implementation See Increased Productivity Using Team Design WP388 as cited in Appendix E Additional Resources 388 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Related Methodologies Design Preservation The Design Preservation methodology coupled with the partition features lets you lock and preserve the placement and routing of a partition from one run and use it in subsequent runs This incremental design approach produces more consistent results re
547. s and the target part into the design analysis and floorplanning environment so you can perform design analysis and floorplanning See Chapter 11 Analyzing Implementation Results for more information e Promote Partitions This option is only available when the design has defined partitions This lets you choose partitions from the design to promote for use in future design iterations See Chapter 13 Using Hierarchical Design Techniques for more information e Generate Bitstream Launches the Generate Bitstream dialog box See Chapter 12 Generating Bitstream Files for more information e View Reports Opens the Reports view for you to select and view ISE Report files See Chapter 9 Viewing Report Files for more information Creating and Managing New Runs You can create and launch new synthesis and implementation runs to explore design alternatives and find the best results You can queue and launch the runs serially or in parallel using multiple local CPUs On Linux systems you can use remote servers See Launching Runs on Remote Linux Hosts page 306 300 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Creating and Managing New Runs The steps to create new synthesis or implementation runs are 1 Select one of the following e Flow gt Create New Runs e Inthe Flow Navigator click Create New Synthesis Runs from the Synthesize pulldown menu or Create New Implementation Runs from
548. s as shown in Figure 8 28 The DRC Results view displays the rule violations found grouped under the various rule categories defined in the Run DRC dialog box The rule violations are also categorized by severity and display color codes for quick review of errors warnings and informational messages Severity Details A Name All violations 224 B DsP48 224 DSP output pipelining DPOP DPOP 1 Warning DPOP 2 Warning i a DSP Mmult_n0027 output is not pipelined DSP Mmult_n0027 output is not pipelined Both mul Both mul improve performance improve performance Pipelining DSP48 ouput wil Pipelining DSP48 ouput will DPOP 3 Warning DPOP 4 Warning DPOP 5 Warning DPOP 6 Warning DPOP 7 Warning DPOP 8 Warning DPOP 9 Warning DPOP 10 Warning DPOP 11 Warning DSP Mmult_n0027 output is not pipelined DSP Mmult_n0027 output is not pipelined DSP Mmult_n0027 output is not pipelined DSP Mmult_n0027 output is not pipelined DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput wil Pipelining DSP48 ouput wil Pipelining DSP48 ouput will DSP Mmult_n0027 output is not pipelined DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput wil Pipelining DSP48 ouput wil Pipelining DSP48 ouput will DSP Mmult_n0027 output is not pipelined DSP Mmult_n0027 output is not pipelined Pipelining DSP48 ouput wil Pipelining DSP48
549. s from the menu on the left of the Options dialog box Note Be careful when manipulating Pblocks to ensure the Pblock rectangle is selected and not the smaller rectangles indicating the assigned instances It is helpful when manipulating Pblocks to turn off the selection ability for instances This ensures Pblocks are selected in the Device view and not the instances assigned to them PlanAhead draws the I O nets connected to the center of the instance inside the Pblock rather than in the Pblock center as shown in Figure 10 9 page 317 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Working with Pblocks we BETS i Package x E Project Summary x Figure 10 9 WO Connectivity Displays to Center of Instance Rectangles Child Pblocks appear in a different color to differentiate the rectangles You can configure the color configuration of objects like Pblocks and children Pblocks using e Tools gt Options e Themes from the Options dialog box e The Device tab of the Themes and defining the settings for Pblocks Viewing Pblock Properties You can display various types of information with the Pblock Properties view To display or edit Pblock properties select the Pblock and view the Pblock Properties view Table 10 1 page 318 lists the Pblock Properties view tabs and options PlanAhead User Guide www xilinx com 317 UG632 v13 4 January 18 2012 Chapter 10 Floorplanning the Design XILINX
550. s synthesis or implementation options or constraints Also the PlanAhead tool allows multiple Synthesis and Implementation runs using different command options target devices timing constraints and physical constraints You can queue the Synthesis and Implementation runs to launch sequentially or simultaneously with multi processor machines Synthesis runs use Xilinx Synthesis Technology XST You can create and save Strategies which are sets of option configurations for each implementation command that are then applied to runs for Synthesis or Implementation using Xilinx ISE Design Suite tools See Defining Strategies for Synthesis and Implementation in Chapter 4 You can monitor progress view log reports cancel runs and manage run data to identify and import the best Synthesis and Implementation results Synthesis Methodology PlanAhead User Guide The following are suggestions for the logic synthesis methodology to use the PlanAhead tool optimally for design analysis floorplanning and hierarchical design e Register the module outputs to limit the number of modules involved in a critical path Note Long paths in single large hierarchical blocks can make floorplanning a difficult task Consider dividing large hierarchical blocks in the RTL e The PlanAhead tool lets you define block level partitions in the elaborated RTL Design You might want to partition the design at the RTL level to confine critical timing paths t
551. s achieved you can copy and archive the entire run directory because it is self contained EDIF Netlists ed PlanAhead exports EDIF format ASCII netlist files that are created during the following commands e Implement and Launch Runs PlanAhead e File gt Export gt Export Netlist e File gt Export gt Export Pblocks e File gt Export gt Export IP Run Implementation and Launch Runs Launching PlanAhead implementation runs automatically exports the files required to implement the Runs and to launch the ISE commands with the options specified in the Strategy When you launch a run the PlanAhead tool exports the EDIF and UCF data automatically When you launch a run the PlanAhead tool creates a run directory containing a single EDIF format netlist file and a UCF format constraint file for the entire top level design The file names correspond to the original top level netlist name contained in the originally imported EDIF file If NGC NGO format module netlist files are used they are copied to each run directory The Synthesis Run Properties view and the Implementation Run Properties view indicate where the actual run directory resides on disk Exported Netlists Exporting a Netlist supplies the design EDIF file for ISE Implementation outside of the PlanAhead environment When a Netlist is exported the original logical netlist hierarchy is maintained in the output netlist You can specify an output file na
552. s and to expose them during design analysis These files are treated as read only and does not enable modification to them directly however you can define new values for module level constraints New constraint values are written into the target UCF Because the PlanAhead tool passes the top level UCF to implementation after the module level NCF the new constraint values are given higher precedence and are used during implementation You cannot remove constraints from the NCF because it is read only Note When modifying module level constraints it is a best practice to edit the files in the original source using the IP creation method Exporting Constraints Designers often use the PlanAhead tool to create constraint files for use in scripting command line design flows To export constraints for a command line flow select File gt Export gt Export Constraints You can export the I O STANDARD constraints for I O Ports and Banks both user specified and the default values assigned by the PlanAhead tool to a UCF by selecting File gt Export gt Export I O Ports and generating the UCF output Managing Simulation Sources PlanAhead User Guide The PlanAhead tool lets you add simulation sources to the project for behavioral simulation of an RTL design project or timing simulation of an implemented design Simulation source files include Hardware Definition Language HDL based test bench files to use as a stimulus for simulat
553. s in the source Verilog files Defines Specify Verilog macro definitions for the project Uppercase all identifiers Specify that all Verilog identifiers should be uppercase Verilog Version Specify the format of the input source files PlanAhead supports Verilog 95 Verilog 2001 and System Verilog Note Some of the reserved keywords of SystemVerilog could have been used as design constructs in an earlier version of Verilog and could result in compilation errors if the source is incorrectly identified as SystemVerilog e Generics Parameters VHDL supports generics while Verilog supports defining parameters Both these techniques allow parameterized designs that can be re used in different situations This option allows you to define generic and parameter values to override defaults defined in the source files e Top Library Specify the top level module library name e Loop Count Specify the maximum loop iteration value The default is 1000 The Loop Count option is used during RTL elaboration but does not apply to synthesis For synthesis you must specify the loop_iteration_limit switch in the More Options field of the Synthesis Settings dialog box www xilinx com 85 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects XILINX For more information on setting Synthesis options see Chapter 6 Synthesizing the Design Simulation Settings Figure 3 42 shows the Launch Options for the
554. s provided Launching the PlanAhead Tool Linux Windows PlanAhead User Guide You can invoke the PlanAhead tool from any directory however running it from a project directory is advantageous because the PlanAhead log and journal files are written to the launch directory making project log files easily located To invoke the PlanAhead tool in Linux type the following command at the command prompt planAhead To invoke the PlanAhead tool in Windows double click the Xilinx PlanAhead y shortcut icon To specify the Start in folder modify the desktop icon properties to define where to write the log files The PlanAhead tool opens to the Getting Started Page as shown in Figure 1 1 page 16 www xilinx com 15 UG632 v13 4 January 18 2012 Chapter 1 About the PlanAhead Tool Gi PlanAhead 13 4 File Tools Window Help XILINX Ahead 13 4 Getting Started New Project Wizard will quide you through the process of selecting design sources and a target device for a new project A Create New Project Open Project AE Open any previously created project he Open Recent Project Open one of the most recently used projects Open Example Project Open one of the tutorial projects Documentation Release Notes Guide Information about installation and new IDS features in this release User Guide More detailed info on Plandhead commands dialogs and buttons Methodology Guides
555. s the current viewable area To print the entire Schematic view zoom to fit and then print Schematic View Specific Popup Menu Commands You can select instances and nets within the Schematic view for manipulation The Schematic view command are e Expand Cone Appends the view to display the entire cone of input logic either to the first primitives flip flops or to the I Os e Toggle Autohide Pins Toggles the display of module pins for selected modules e Remove Selected Elements From Schematic Removes the selected objects from the schematic e Expand Inside Expands logic contained inside of selected modules e Expand Outside Expands logic contained outside of selected modules The expansion only occurs on the parent module logic e Collapse Inside Collapses logic contained inside of selected modules e Collapse Outside Collapses logic contained outside of selected modules The collapsing only occurs on the parent module logic e Select All Primitive in Schematic Selects displayed primitive logic in the active schematic fit view e Select Primitive Parents Selects all of the parent logic modules of the selected logic available only when instances are selected Annotating Schematic Design Information PlanAhead User Guide The Schematic option selection in the PlanAhead Options dialog box lets you tag source pins with Fanout values and destination pins with Slack values Slack values do not d
556. s to perform a worst case setup and hold analysis This results in a more accurate but pessimistic analysis than minimum or maximum delays alone e Slow corner Selects the delay types used for the slow corner analysis The available values are None Specifies that no delays are used Max Specifies that maximum delays are used for the clock and data paths during setup and hold analysis Min Specifies that minimum delays are used for the clock and data paths during setup and hold analysis Min_Max Uses a combination of minimum and maximum delays for the clock and data paths during setup and hold analysis e Fast Corner Selects the delay types used for the fast corner analysis The values are www xilinx com 227 UG632 v13 4 January 18 2012 Chapter 7 Netlist Analysis and Constraint Definition g XILINX 228 None Specifies to use no delays Max Use maximum delays for the clock and data paths during setup and hold analysis Min Use minimum delays for the clock and data paths during setup and hold analysis Min_Max Use a combination of minimum and maximum delays for the clock and data paths during setup and hold analysis e Enable timing pessimism removal Removes the skew delay generated by the common clock path between source and destination registers when modeling on chip delay variation Analyzing Timing Results The Timing Results view opens when the
557. select Window gt Package When you hold the cursor over the Package view it invokes a tool tip that displays the pin information as shown in Figure 4 46 page 134 www xilinx com 133 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX You can e Drag ports and I O buffer instances into the Package view for assignment and reassign instances to other I O pins within the Package view e View pins and I O banks as follows e VCC and GND pins show as red and green square pins e Clock capable pins display as hexagon pins e The colored areas between the pins display the I O banks e Click the pins or bank to select them e Select I O pins or banks to highlight them in the Device view Pins or I O banks that you select in the Device view also highlight in the Package view e Display the differential pair pins in the Package view by toggling on the Show A Differential I O Pairs toolbar button You can set the Package view to display the package from the top or the bottom by clicking the Show Top View or Show Bottom View toolbar button The Package view toolbar buttons show on the left ee a e SC I O Ports G E A Pins H V Dedicated Configuration Pins H m O 1 0 and Multi Function Pins V5 Power Supplies S RocketIO Serial Transceiver Pins MB System Monitor Pins H V Unconnected Pins fil Other Pak SCE AEE A in a E AE4 Gigabit x Site Type MGTRXNZ_114 Ci
558. ses Pin ordering during assignment attempts to keep the bus bits vectored within the assignment area You can customize assignment patterns to address other bus routing concerns Placing I O Ports in a Defined Area To place I O Ports into a defined area 1 Inthe I O Ports view select individual I O ports groups of I O ports or interfaces 2 Inthe I O Ports view the Device view or the Package view click the iw Place I O Ports in Area button He The cursor turns into a cross symbol which indicates that you can define a rectangle for port placement 3 Ineither the Package view or the Device view draw a rectangle to define the assignment area as shown in Figure 8 22 4 If you select more I O Ports than fit in the defined area the command is continued The cursor continues to display as a cross to draw another area to place the remaining I O ports until all of the I O ports are placed or until you press Esc een yeent ib scent REFS our seas moma ede d at Place 13 of 44 ports COI Figure 8 22 Placing I O Ports in an Area Ports are assigned in the order that they appear in the I O Ports view You can adjust the assignment order by applying sorting techniques in the I O Ports view prior to assignment The direction in which you draw the rectangle dictates the I O ports assignment order I O ports are assigned from the inside pin of the first rectangle coordinate selected Creative definition of the a
559. ses the logic hierarchy or gauge how big a module is before you floorplan the module The Hierarchy view displays a graphical view of the logic hierarchy for both the elaborated RTL design or the synthesized netlist design Viewing the design from top to bottom you can identify module sizes and location within the design In the popup menu select the Show Hierarchy command to invoke the Hierarchy view shown in Figure 4 63 page 152 www xilinx com 151 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment g XILINX IU LLL TEE UT LETTE TTL TT LU LAU Ul i Device x E Project Summary X Figure 4 63 Hierarchy View Only hierarchical instances display in the Hierarchy view Primitive logic is grouped into folders that are represented as sub modules Refer to Using the Netlist View page 148 for more information about primitive logic folders The widths of the blocks in the Hierarchy view are based on the relative FPGA resources within the block When you select logic it is highlighted so you can see where critical logic resides in the design The module highlights proportionally to the amount of logic selected as shown in Figure 4 64 det_unit_1 dctu_11s_8s_1_ a T det_unit_2 detu_1 E det_unit_3 detu_11s_8s W Nets 349 eB Bea E gt amp Constraints Package Device 7 Schematic Sj Hierarchy X 4 gt Figure 4 64 D
560. sign w E Resource Estimation E usbEngined usb E usbEnginet usbf_top_usbEngin E wbArbEngine Sy Power Analysis Run prc E Report Clock Networks Report Timing IM Slack Histogram E FPGA Editor amp Sources i Netlist f XPower Analyzer Properties GE Timing Simulation i a Program and Debug A Name Type Total Delay Logic Delay Net Delay Logic Net Stages Source Clock Destinatio ESET ES Setup 10 P Pathi Slow SETUP 0 23 reset_reg Q usbEnginet 6 0 wbclk phy_clk_pad P Path2 Slow SETUP 0 23 reset_reg Q usbEngine1 i 0 wbclk phy_clk_pad P Paths Slow SETUP 0 23 reset_reg Q usbEnginel A 0 wbCik phy_clk_pad P Path Slow SETUP 0 23 reset_reg Q usbEngine1 i 0 wbClk phy_clk_pad P Paths Slow SETUP 0 23 reset_regiQ usbEnginet i 0 wbclk phy_clk_pad P Paths Slow SETUP 0 24 reset_regiQ usbEngine1 R i 0 wbClk phy_clk_pad Path Slow SETO NPA racat rentO uehEmainett DLsaibCle uchlik Report Timing results_1 10 paths x E Tel Console Messages E Compilation Design Runs iming Results RTL Flow Figure 11 2 Implemented Design Environment The placed design shows in the Device view with fixed and unfixed instances displaying in different colors Fixed instances are logic instances that were interactively placed by a user Unfixed instances are logic instances that were automatically placed by the software You can
561. source files in the Text Editor to edit as needed Double click the file or select Open File from the popup menu to open the file in the Text Editor for editing See Using the Text Editor in Chapter 4 for information on editing the newly created file Adding IP After specifying RTL source files for your project you can add existing IP cores using existing CORE Generator core files XCO created outside of the PlanAhead tool An XCO file is a log file that records all the customization parameters used to create the core and the project options in effect when the core was generated The XCO file is used by the PlanAhead tool to recreate the core in the new project Figure 3 6 shows an IP core being added to the project G New Project Add Existing IP optional Specify an existing configurable IP file to add to your project IPName IP File char_fifo C Data FPGA_design Plan4head_Tutorial Projects project_wave_gen_verilog char_fifo xco clk_core C Data FPGA_design Plan4head_Tutorial Projects project_wayve_gen_verilog clk_core xco Figure 3 6 Add Existing IP Dialog Box Note XCO core files can be added to RTL projects only Parameterized cores can also be loaded by running the CORE Generator software from within the PlanAhead tool by using the IP Catalog command See Managing IP Cores page 63 for more information IP cores are also available in the Embedded Development Kit EDK and DSP tools You can load existin
562. sources I O Bank Resources You can select I O resources in any of the I O Planning views and their corresponding data is highlighted in all other views as shown in Figure 8 3 page 255 This provides a visual indication of the relationship between the physical package and the internal die Use the following steps to access information about a specific I O bank 1 Inthe Package Pins view select one of the I O banks The I O Bank Properties view will be opened 2 IntheI O Bank Properties view click the various tabs at the bottom to see the different types of information available Figure 8 5 page 257 shows the I O bank Properties view 256 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Viewing Device Resources e gt Bilki am I O Bank 13 High Range Id Name Prohibit Bank Type Port I O Std 1719 High Range 2721 High Range 3 U21 High Range 4 U22 High Range 5 v22 High Range 6 T18 High Range 7 U18 High Range 8 w21 High Range 9 W22 High Range 10 U17 High Range 11 v18 High Range yo General Port Summary Package Pins I O Ports Resc q4 gt E ooog AVVVYVVYVVYVVVVY Clock Regions Selection Figure 8 5 Displaying I O Bank Properties Multifunction Pins The Package Pins view contains a variety of data types that display in spreadsheet like columns The view can be flattened filtered and sorted You can move hide and configure columns to d
563. ssages Compilation or Reports views Refer to Using the Tcl Console and Messages Area in Chapter 4 for more information e Next Step Provides a link to show the next step in the flow to be completed Click the link to run the step Compilation Compilation shows the results for both the synthesis and implementation runs when available Compilation shows the target part the strategy applied in the summarized run the resource utilization and the max frequency Fmax observed on the device PlanAhead User Guide UG632 v13 4 January 18 2012 80 www xilinx com g XILINX Using the Project Summary view Compilation also shows the timing score and unrouted paths reported from the implementation run Click the target part or strategy links to open the Project Settings dialog box for either synthesis or implementation See Configuring Project Settings page 83 for more information Resources The resource utilization for the target device displays in either a graphical form as shown in Figure 3 37 or tabular form as shown in Figure 3 38 page 82 Click the link in the upper right of the Resources section of the Project Summary to toggle between the graph and table views Erol Project Settings be Compilation E Resources Part xc vlx75tff784 3 Register p RAMB18E1 ILOGICE1 Device x Edit E Project State RTL Estimation Synthesis Estimation Netlist Estimation Implemented Utilization
564. ssignment as shown in Figure 8 4 page 256 When you selecting an object in the Clock Regions Properties view that object is cross selected in another open view such as the Device view The Clock Resources view also provides a view of available clock resources to aid in planning and placing elements of global and regional clock trees see Using the Clock Resources View page 275 PlanAhead User Guide www xilinx com 255 UG632 v13 4 January 18 2012 Chapter 8 O Pin Planning XILINX Netlist Design netlist_1 cor Netlist Od AE G XST_GND GND E XcvSelect_pad_0_o_OBUF OBU E XcvSelect_pad_1_o_OBUF OBUF E cpuClk_BUFGP BUFGP FFtClk_BUFGP E sF C or 1200_clmode_IBUF C or 1200_pic_ints_IBUF IBUF C of 1200_pm_out_0_OBUF OB G or 1200_pm_out_1_OBUF OF G or 1200_pm_out_2_OBUF OBUF C 0 1200_pm_out_3_OBUF OBUF J J E phy_clk_pad_0_i_BUFGP BUFG phy_rst_pad i phy_rst_pad_t E phy_rst_pad_1_o G phy_rst_pad_1_o_OBUF i reset_IBUF IBUF reset_reg F Gil usbClk_BUFGP BUFGP E usb_vbus_pad_0O_i_IBUF IBU C usb_vbus_pad_1_i_IBUF IBUF EE wbCIk_BUFGP EUFGP amp Sources Netlist Timing Constraints Clock Region Properties Od e gt Bk ic aa ole a m X1 1 Name Type IOB Alias Instances a a Ooo erx or IDELAYCTRL KZVI IDELAYCTR General Statistics Resources I O Banks Tiles Properties Clock Reaions Figure 8 4 Viewing Clock Region Re
565. st Constraints UCF Export all or only fixed placement constraints Pblocks Lists the Pblocks selected for export Click Add and Clear to select and remove Pblocks from the export list respectively and click Next or Finish to continue When you chose Next the Export Pblocks Summary dialog box displays Pblock export selections Click Finish to perform the export The PlanAhead tool creates separate EDIF and UCF files for each of the exported Pblocks named pblockname_CV edn and pblockname_CV uc f A pblockname_cv directory is also created for each exported Pblock containing the Pblock specific files www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Chapter 11 Analyzing Implementation Results The PlanAhead tool has many features to help analyze the placement and routing results of an implemented design The design can be implemented in the PlanAhead tool or you can import implementation results from the Xilinx ISE Design Suite of tools The PlanAhead tool can perform the following on placed and routed designs Design Rules Check DRC SSN analysis SSO analysis Timing analysis Power analysis In addition the PlanAhead tool allows you to Open the FPGA Editor to view and modify routing resources in the implemented design Launch the Xilinx ISim tool for timing simulation of the implemented design Opening the Implemented Design If you used PlanAhead to l
566. st based projects the PlanAhead tool creates a single netlist directory that contains the imported netlist including copies of all NGC core files used in the design Project Data Constraint Set Subdirectories and Files constraint_set_name As you create constraint sets the PlanAhead tool creates matching subdirectories under the projectname data directory The files in the constraint set directories are e ucf Imported UCF names might differ from input files e iseloc xml Used to differentiate fixed placement constraints from the unfixed placement constraints imported from ISE e pfi xml Contains target device for the design e pfp xml Contains current experiment information for the design e expXx subdirectories Contains experiment information about each run Project RTL Directory projectname srcs The project sources directory stores the HDL source files that are imported into a project These folders are maintained by the PlanAhead tool and do not require your attention Caution Modifying any of these files could result in project data corruption PlanAhead User Guide www xilinx com 415 UG632 v13 4 January 18 2012 Appendix A PlanAhead Input and Output Files Project Data Simulation projectname sim XILINX The project simulation directory structure for both behavioral and timing simulation Runs is the same project_name project_name sim sim_run_name sim_
567. stance types in the design to unplace as described in step 4 and shown in Figure 10 27 page 336 Click Next to continue You are presented with a list of instance types to unplace as shown in Figure 10 27 page 336 This lets you selected from the various types of instances within the group of instances specified in Step 2 www xilinx com 335 UG632 v13 4 January 18 2012 Chapter 10 Floorplanning the Design g XILINX G Clear Placement Constraints Instance Types to Unplace Below is a list of types of the 6210 specified instances Only instances of the selected types will be unplaced Primitive Types to Unplace FD amp LD 2500 LUT 3500 MuxFx 7 CarryLogic 48 C 10 129 Figure 10 27 Unplace Instance Types 5 Choose the types of instances to unplace and click Next If some of the instances or ports you have selected to unplace are fixed the Fixed Placement dialog box opens as shown in Figure 10 28 G Clear Placement Constraints Fixed Placement Some of the instances and ports you are about to unplace are marked as Fixed Do you want to unplace these fixed objects Fixed Instances Keep 6 fixed instances Unplace all 6069 placed instances Fixed Ports Keep 1 fixed port Unplace all 135 placed ports Figure 10 28 Unplace Fixed Instances and Ports 6 Specify whether you want to preserve the current placement of fixed instances or you want to unplace all instan
568. status to reflect the latest status which displays in the Design Runs chart The columns used for tracking information are e Name Displays run name e Part Indicates the target part selected for the run www xilinx com 155 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX e Constraint Displays the constraint set used for the run e Strategy Displays the strategy assigned to the run Strategies appearing with an asterisk indicate that the command option values in the strategy have been overridden in the Run Properties Options tab e Status Indicates run status or the command that is currently running e Progress Indicates overall progress of the entire ISE command sequence from ngdbuild through XDL The progress bar is non linear in that some steps can take considerably longer then others e Start Indicates the time ISE started working on the design e Elapsed Indicates the total elapsed time for all ISE commands run on the design e Device Utilization for synthesis runs only Indicates the resulting LUT utilization for the run e Fmax for synthesis runs only Indicates the expected clock frequency for the run from the XST Synthesis report e Timing Score for Implementation runs only Indicates the current timing score on the run in progress or after completion e Unrouted Nets for Implementation runs only Indicates the current number
569. store paths to the timing report You must rerun Timing Analysis Using the Path Properties View To display information about the logic and delay on that path in the Path Properties view select a Path in the Timing Results view The timing results from TRACE are different from the timing results of the PlanAhead tool Report Timing command described in Analyzing Timing Results page 228 The TRACE results report additional information such as Clock Skew and Jitter as shown in Figure 11 8 page 351 350 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Analyzing Timing Results TS_wbClk PERIOD TIMEGRP wbClk 9 ns HIGH 50 3 840ns op 4 eqressFifo buffer_fifo Mram_Ffifo_ram FE whOutputData_13 9 000ns 4 931ns 5 wbClk_BUFGP rising at 0 000ns wbClk_BUFGP rising at 9 000ns 0 194ns 0 999ns 1 193ns 0 035ns T5142 TIJ 2 1 2 DI 2 PE Total System Jitter T5J 0 070ns Total Input Jitter TIJ 0 000ns Discrete Jitter DJ 0 000ns 0 000ns Data Path Delay l Cumulative Location Logical Resource v c 2B E Site RAMB36_x1Y21 egressLoop 4 eqressFifo buffer_fifo Mram_fifo_ram net Fanout 1 r 0 972 2 943 D demux lt 4 gt lt 13 gt r 0 045 Site SLICE _X44Y104 EE Mmux_GND_6_0_GND_6_o_mux_40_OUT52 net Fanout 1 r 0 984 3 976 Mmux_GND_6_0_GND_6_o0_mux_40_OUTS1 E Site SLICE _X44Y88 FE Mmux_GND_6_0 GND_6 0 mux_40_OUT53 net Fanout 1 r 0 890 4 915 Mmux_GN
570. stub v These files contain the instantiation template that you can use to instantiate the embedded processor system into your PlanAhead project implementation e system ngc This is the synthesized netlist representing your embedded processor system e system_stub bmm This file contains the Block RAM Memory Map BMM www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Importing XPS Embedded Processor Designs Adding Embedded Processor Systems To add an embedded processor system into the PlanAhead tool project create a new PlanAhead RTL project Refer to Creating a New Project page 35 for more information The embedded processor HDL can also be instantiated into an existing PlanAhead RTL project Note Because the embedded processor system was synthesized for a specific Xilinx device the part and package specified in the PlanAhead Project must be the same as is specified in the embedded processor system After the PlanAhead project is created there are four steps that need to be completed e Instantiate the embedded processor system HDL e Add the embedded processor system netlist e Import the embedded processor system constraints e Evaluate implementation options Instantiate the Embedded Processor System HDL When the embedded processor system is created a VHDL or Verilog file called system_stub vhd or system_stub v is also created based upon project settings to provide an example
571. t expand the wildcards and does not import those ports Creating New I O Ports You can define new ports manually when working in an I O Planning project in which you have imported a CSV file or UCF to define I O ports To create I O ports 1 Inthe I O Ports view select Create I O Ports The Create I O Ports dialog box opens as shown in Figure 8 12 page 262 PlanAhead User Guide www xilinx com 261 UG632 v13 4 January 18 2012 Chapter 8 VO Pin Planning 262 XILINX G Create 1 0 Ports Name port_1 Direction Input v Diff Pair port_1_P port_1_N a 5 ok Configure I O Standard LVD5_25 default v Drive Strength Slew Type Pull Type NONE default w Phase deFault v Figure 8 12 Create I O Ports Dialog Box 2 Edit the options e Name Enter the port or bus name to create e Direction Select the port direction e Diff Pair Define differential pair signals or buses e Create Bus Enter bus range for bus creation e Configure I O Standard Select the I O Standard constraint Drive Strength Select the Drive Strength value Slew Type Select the Slew Type value Pull Type Select the Pull Type value Phase Enter a phase group or select an existing phase group A phase group is a logical grouping of ports used in Simultaneous Switching Noise SSN calculations to indicate that the set of ports share the same frequency and
572. t Description NCD file from ISE to a Xilinx Definition List XDL format file A progress bar displays in the PlanAhead tool while this command is running To expedite re invoking the PlanAhead tool the interface first checks for the existence of the XDL file and does not regenerate the file if it is still current When you select Tools gt PlanAhead gt Post Implementation Analyze Timing Floorplan Design with the Implementation process out of date you are prompted to either re implement the design or launch the PlanAhead tool on the existing result data without rerunning the Implementation tools When you save or exit the PlanAhead tool updates the original Project Navigator source UCF s and this resets the Project Navigator design process state also if appropriate www xilinx com 407 UG632 v13 4 January 18 2012 Chapter 15 Using PlanAhead With Project Navigator XILINX 408 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Appendix A PlanAhead Input and Output Files Input Files While reading the input files the PlanAhead application writes out any information errors warnings critical warnings and messages in to the planAhead 1og file These messages display in the PlanAhead Console view also The PlanAhead tool lets you specify the location of files used as input Note Be aware that upon invocation the PlanAhead tool overwrites any existing journal and log f
573. t FFtclk z C9 bftpackage bf reset z vl_types vl TILEO_REFCLK z TILEO_REFCLK z TILE1_REFCLK z TILE1_REFCLK z TILE2_REFCLK z TILE2_REFCLK z TILES_REFCLK z TILE3_REFCLK z GTPRESET_IN z J TILEQ_PLLLKD z TILE1_PLLLKD z TILE2_PLLLKD z TILES_PLLLKD z Bj RXN_IN 7 0 zzzzzzzz IQ RXP_IN 7 0 zzzzzzzz BG TXN_OUT 7 0 11111111 35 TXP_OUT 7 0 11111111 U phy_clk_pad_Oi z DataOut_pad xxxxxxxx TxValid_pad_0 x TxReady_pad z Dataln_pad_0 zzzzzzzz RxValid_pad_Oi z Rx ctive_pad z RxError_pad_ z XcevSelect_pad x TermSel_pad_ x LineState_pad zz usb_ybus_pad z ig Control_Load x VStatus_pad_ zzzzzz2z lt gt Uy phy_clk_pad_1i z a lt IK gt lt ha Sa Instanc Memory IE source lt a gt Default wefg xf Console Oex INFO USB Function core instantiated top usbEngine1 amp Supported Endpoints 16 0 through 15 WISHBONE Address bus size 414 0 SSRAM Address bus size 414 0 Buffer Memory Size 131072 bytes Finished circuit initialization process ISim gt v HM Console B Compilation Log Breakpoints PA Find in Files Results Search Results Sim Time 100 000 ps Figure 5 13 ISim User Interface PlanAhead User Guide www xilinx com 193 UG632 v13 4 January 18 2012 Chapter 5 RTL Design g XILINX Running RTL DRCs The following subsections describe selecting DRC rules and analyzing DRC violations in the PlanAhead tool Selecting DRC Rules You
574. t provides unique capabilities and viewing perspectives for design information Most views cross select Information selected in one view is also selected in other open views enabling efficient methods to examine the design and device information Select a port in the I O Ports View then see the highlighted port in the Device View or Package View for example Cross selection also applies to other open designs in a single project Selecting an object in an implemented design of a project also cross selects the object in an open Register Transfer Level RTL design The type of project determines the initial appearance of the viewing environment See Chapter 3 Working with Projects The PlanAhead tool lets you control each major step of the FPGA design process including RTL development and analysis logic synthesis constraints definition physical design analysis floorplanning and implementation control with the Xilinx ISE Design Suite software The Viewing Environment The main elements of the viewing environment are shown by number in Figure 4 1 page 92 1 Main Menu 2 Main Toolbar 3 Flow Navigator 4 View Layout Selector 5 Main Viewing Area 6 Project Status Bar 7 Tcl Console and Messages Area 8 Information Bar PlanAhead User Guide www xilinx com 91 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment g XILINX G prose ct_bft_ccre_hdl PlanAhead_Install planAhead testc ses P
575. t to Spreadsheet Lets you output the IP Catalog to an XLS file for use in a spreadsheet Customizing IP for the Project You can select a core from the IP Catalog and customize the IP for use in your design by specifying values for the various parameters associated with the IP core The PlanAhead tool customizes IP using the integrated CORE Generator tool 1 Select the IP to customize from the IP Catalog 2 Select the Customize IP command from the toolbar or popup menu or double click the selected IP The PlanAhead tool invokes the CORE Generator tool interface to enable core generation The IP type you select determines what type of interface displays The interfaces are e Memory Integration Generator MIG wizard e CORE Generator software wizard Figure 3 27 page 67 shows the CORE Generator wizard www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX FIR Compiler View Freg Response Frequency Response Magnitude ke 3 a S 3 i G i Normalized Frequency PI rad sample S tto Display 1 Range dd Filter Analysis Passbarnd Stop band Range 0 0 ios fos Min 18 061800 dB Maz 43 525674 cB 21 563525 cB Ripple 25 463974 cB Managing IP Cores sagiCXPe FIR Compiler Component Name fir_cormpiler_ 5_0_9 Filter Coefficients Select Source Vector v Coefficient Yactor 6 0 4 3 5 6 6 13 7 44 54 44 7 13 6 6 5 3 4 0 6 Coefficients
576. t wlth Figure 4 46 Package View 134 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using Common Views Setting Visible Package View Layers The Package view toolbar includes a Package View Layers command that lets you define what layers and objects are visible in the Package view This command accesses the Layers Slideout allowing you to control the level of detail available to see in the Package view Layers Slideout icon Figure 4 47 shows the Package View Layers command on the toolbar and the Layers Slideout with various layers you can display or hide E Project Summary X Device x f Package x J opp x F VCCAUXIO_G2 Eh qe CCAUX_IO_G3 qe CCBRAM CCINT CCO Transceiver Pins B Unclassified B Unconnected Pins IO Banks E 1 0 Banko E 1 0 Bank 14 E yo Bank 15 E 1 0 Bank 16 E 1 0 Bank 17 E 1 0 Bank 18 E 1 0 Bank 19 E 1 0 Bank 34 E 1 0 Bank 35 O 0 Bank 36 E 1 0 Bank 37 O 1 0 Bank 38 E 1 0 Bank 39 HB 1 0 Bank 114 G 1 0 Bank 115 I O Bank 116 E 1 0 Bank 117 E 1 0 Bank 118 Gi 1 0 Bank 119 O Yo Bank 214 E 1 0 Bank 215 E 1 0 Bank 216 E 1 0 Bank 217 E 1 0 Bank 218 E 1 0 Bank 219 Z N High Range K Dedicated Other E 4 KUIKSKSIKS KS Sa RR TSY Ft
577. tab to select and make that view active Some views have a tab at the bottom of the view window such as the Tcl Console and Messages view Some views have a tab at the top of the view window such as the Project Management and Device views You can activate a view by selecting the appropriate tab In views the following actions are available e Double click the view tab to display the view on the full screen e Restore workspace views by double clicking the view tab again e Stretch the overall size of these viewing areas by sliding the view borders The cursor changes to a slider symbol you can use to stretch the view borders e Move the views by selecting a view tab and dragging it to a new location See Configuring the Viewing Environment page 162 for more information Some view types allow multiple tabs For instance Figure 4 14 page 103 shows the SSN Results view with two different result sets displayed 102 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Working with Views wey I O Bank 34 Standard 0 aav IJO Bank 35 Standard 0 A results_1 7 of 7 Banks Passed results_2 7 of 7 Banks Passed x E Tel Console Messages Lal Compilation JP Package Pins Design Runs Figure 4 14 SSN Results Tab Moving Views To move a view from its current location to another select the tab and drag the view This produces a rectangular box which indicates where the view is lo
578. tains full path details for the datapath and summary details for the clock path s Full_Clock_Expanded Specifies a timing report that contains full path details for the datapath and full details for the clock path s Short Specifies a timing report that contains summary details for the datapath and hides the details of the clock path s Summary Specifies a written timing report that only contains summary information on the timing performance of the design www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Running Timing Analysis Do Not Report Unconstrained Path Specifies that the report contain details for constrained paths only Number of Paths Per Group Specifies the number of timing paths reported per group Number of Paths Per Endpoint Specifies the maximum number of timing paths reported per endpoint Limit Paths Per Group Limits the paths to a group or set of groups The group identifier can be entered directly or by using the Choose Path Groups dialog box Display Paths With Slack Greater Than Filters the displayed paths based on a minimum slack value Only paths with slack greater than this value are shown Display Paths With Slack Less Than Filters the displayed paths based on a maximum slack value Only paths with slack less than this value are shown Significant Digits Specifies the significant digits of the timing report delay values The
579. tandards are not used on low capacitance sites that cannot support them IO Part Compatibility IOPCBT This message occurs in 7 series designs with multiple Warning for Bank Type compatible parts when the use of an I O standard is legal in the bank it is placed in on one part but not in legal in the corresponding bank of one of the compatible parts This can occur when the bank on one part is a high performance HP I O bank but the corresponding bank ona compatible part is a high range HR I O bank The set of legal I O standards is not the same for these two bank types To resolve this issue e Place the ports on an I O bank that supports the I O standard on all the compatible parts e Change to an I O standard that is legal in both HP and HR banks e Change to different compatible parts Prohibit not specified IOPCPR For designs that use part compatibility checks that if any Error for part compatibility package pin does not exist on at least one compatible part it is marked as prohibit and nothing is placed on it MGT not allowed for IOPCMGT Indicates whether part compatibility is used with two parts Warning part compatibility that have different serial transceiver supply voltages thereby disallowing the use of serial transceivers PlanAhead User Guide www xilinx com 427 UG632 v13 4 January 18 2012 Appendix B PlanAhead DRCs Table B 17 IOB DRCs Cont d XILINX Rule Name Rule Abbrev Rule Intent
580. tch mode for each black box debug core This operation can take some time A progress indicator shows that the operation is running When the debug core implementation is complete the debug core black boxes are resolved and you can access the generated instances Exporting Net Connections CDC File for ChipScope Analyzer Tool A ChipScope Analyzer CDC file is generated automatically when design Implementation is complete Also you can export a CDC file manually from Export Debug Net Names in the ChipScope view You can import this CDC file into the ChipScope Analyzer to automatically set up the net names on the ILA core data and trigger ports Implementing the Design with the Debug Cores After ChipScope debug cores are created and connected you can run the standard PlanAhead design implementation flow to create a bitstream for the device Start the Implementation flow by selecting the Implement in the Flow Navigator or the Tools menu Launching ChipScope Pro Analyzer 378 When the ChipScope Pro Analyzer software is installed you can launch it directly from the PlanAhead tool on any implemented design on which Generate Bitstream has been run To launch ChipScope Pro Analyzer do one of the following e Inthe Flow Navigator select ChipScope Analyzer from the Program and Debug menu www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Launching iMPACT e Use the Tools gt Analysis gt ChipScope A
581. te to create the customized IP core and add it as a source into the project The core is not synthesized at this time Note The Generate button has a different effect in the stand alone CORE Generator tool With IP cores added to your project when you run the Synthesize command the PlanAhead tool automatically synthesizes the IP cores in the project first then synthesizes the top level design This lets you instantiate multiple IP cores without having to synthesize each one as it is added to the project and also bundles synthesis to save time IP cores display in the Sources view when they have been added to your project after customization You can select these cores in the Sources view to see the various files that make up the core and to view the properties in the Source File Properties view PlanAhead User Guide www xilinx com 67 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects g XILINX To select the IP cores in the Sources view use Re customize IP to reopen the core in the CORE Generator interface and change any of the parameters associated with the core for this project You can select the IP cores in the Sources view and use Upgrade IP to update the customized IP to the latest version from the Xilinx IP Catalog and reapply any customizations from the current project e For information on using the CORE Generator tool to generate IP refer to http www xilinx com tools coregen htm e For inf
582. technology and respond to customer requests New releases are periodically introduced The version number reflects the release for example 13 1 or 13 2 The Help gt About PlanAhead command displays the currently installed PlanAhead application version To check for new releases run the Help gt Check for Updates command as described in the following subsections Refer to the Appendix E Additional Resources for more information about Xilinx tool installation Running XilinxNotify The XilinxNotify tool is the preferred method of obtaining software updates It performs the following activities e Compares the latest version of Xilinx software updates available on http www xilinx com support with what you have installed and notifies you if a newer version is available e Provides a Download button that launches a browser allowing you to login to the Xilinx Download Center When you login the download of your selected product starts XilinxNotify can be run in any of the following ways e Automatic periodic checks upon software invocation e Select Help gt Check for Updates e Type xilinxnotify in a Linux shell Note The Edit gt Preferences menu selection lets you control the frequency of automatic checks at start up XilinxNotify Network Installations By default the Automatically check for software updates option at start up is enabled on the machine used to install the PlanAhead tool to the network location
583. ted Design Netlist constraints and results from any implemented run For all design views the Design Analysis view layout displays by default Select the I O Planning view layout in the menu toolbar to toggle between view layout See Using View Layouts page 96 www xilinx com 27 UG632 v13 4 January 18 2012 Chapter 2 The PlanAhead Tool Flow XILINX Opening an RTL Design When you click RTL Design in the Flow Navigator the PlanAhead tool automatically elaborates the RTL design and loads it into memory along with the active constraint set and the target device Elaboration messages display in the Messages view To open a RTL Design select either e RTL Design in the Flow Navigator to load the elaborated netlist the active constraint set and the target device e The Open RTL Design command in the RTL Design pulldown menu of the Flow Navigator where you can specify an alternative constraint set and target device to load into the design The RTL Netlist view displays the compiled logic hierarchy See Chapter 5 RTL Design for more information on analyzing the RTL logic design See Chapter 8 I O Pin Planning for more information about using the I O Planning view layout for I O pin planning Using a Netlist Design The Netlist Design consists of combination of a synthesized netlist a constraint set and a target device The PlanAhead tool allows for multiple Synthesis runs and provides support for analysis of mult
584. th ChipScope Debugging the Design with ChipScope in Chapter 12 Defining Timing Constraints PlanAhead provides the ability to define and modify timing constraints for the design however you must ensure that constraints are written to the correct constraints set and target UCF so that constraints are applied as expected Editing Constraints You can view and modify constraints in the UCF in which they are defined This makes it easy to cut and paste constraints and to modify values of existing constraints To open a UCF in the Text Editor double click the appropriate constraints file name in the Sources view Figure 7 9 shows an open UCF You can open multiple files at one time E Project Summary X Device x 3 C Planahead_Install plan4head testcases PlanAhead_Tutorial Projects project_cpu_netlist project_cpu_netlist srcs constrs_1 imports top_full ucf aA 2 Timing Constraints STIMESPEC TS_cpuClk PERIOD cpuClk 13 ns 4NET cpuClk TNM_NET cpuClk 5 6TIMESPEC TS_wbClk PERIOD whClk 9 ns 7NET whClk TNM_NET whClk 8 STIMESPEC TS_usbClk PERIOD usbClk 5 25 ns 10 NET usbClk TNM_NET usbClk 11 12 TIME PEC T3_phy_clk_pad_0_i PERIOD phy clk pad 0 i 11 ns 13NET phy clk pad 0 i TNM NET phy clk pad 0 i 14 15TIME PEC TS_phy_clk_pad_l_i PERIOD phy clk pad 1 i 11 ns 16NET phy clk pad 1 i TNM NET phy clk pad 1 i 17 18 TIMESPEC TS_fftClk PERIOD fftClk 7 ns 19 NET fftClk TNM_
585. that does not invoke the GUI Optionally you can pass a script with the source switch which executes the script and then passes the control to the interactive shell where you can manually enter Tcl commands To launch PlanAhead in Tel shell mode planAhead mode tcl source script_name tcl Tcl Init File When the PlanAhead tool is launched it looks for the existence of a Tcl initialization script in two different locations 1 lt installdir gt planAhead scripts init tcl 2 lt userdir gt Xilinx PlanAhead init tcl Where e lt installdir gt is the installation directory where the PlanAhead tool is installed and e lt userdir gt is your home directory e For Windows 3APPDATA Xilinx PlanAhead init tcl e For Linux SHOME Xilinx PlanAhead init tcl If the init tcl script exists in one or both of those locations the PlanAhead tool sources this file first from the installation directory and second from your home directory The init tcl file in the installation directory allows a company or design group to support a common initialization script for all users Anyone invoking the PlanAhead tool from that software installation sources that init tcl script The init tcl in the home directory allows each user to specify additional commands or to overwrite commands from the software installation to meet their specific design requirements The init tcl script is a standard Tcl command file that can contain any
586. the From object that is the primary selection e Disabling the selection rule allows the PlanAhead tool to only select the primary From object when it is selected Using the Selection View The Selection view as shown in Figure 4 28 page 113 displays the list of objects currently selected You can sort de select or mark objects from this view The list is updated dynamically as you manipulate objects To invoke the Selection view select Window gt Selection 112 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Selecting Marking and Moving Objects Type 2 ASIC_BIF_ADDR_O_hNib 3 1 0 Port 3 H2 Package Pin 1 0 site amp Properties Figure 4 28 Selection View e To sort elements click the column header to use as alpha numeric sort criteria e To sort objects by Name ID or Type click the banner of the sort column e To remove selected items from the list use the Unselect Unselect All or Unselect All Except commands from the popup menu Select groups of objects using the Ctrl and Shift keys The total number of objects selected displays in the view banner as shown in Figure 4 29 Unselect R Unselect All Unselect All Except Figure 4 29 Selection View Popup Menu Commands Fitting the Display to Show Selected Objects When selecting objects directly in the workspace view or indirectly by cross selecting from other views you might want to have the dis
587. the Add Sources command you can copy the sources to the local project directory by selecting the Copy Sources into Project option If you initially add the sources as remote sources but later wish to copy them into the project directory use Copy into Project or Copy All Files into Project in the popup menu in the Sources view to copy some or all individual remote source files into the project directory e Local files that you copy into the project directory have a green dot next to the file name in the Sources view e The absence of a green dot indicates that the file is a remote source e A red dot indicates an RTL file that could not be located either local or remote Figure 3 18 shows an example of how these sources display in the Sources view Sources 00 x eE H Name Library Location Design Sources 2 kad D 5 Verilog 2 B async _fifo v work C planahead 12 2 plan4headitestcases Plandhe SA FifoBuffer v work C planahead 12 2 plan4headitestcases Plandhe o VHDL 7 Ga bft vhdl work C planahead 12 2 plan4headitestcases Plandhe fh round_4 vhdl bftLib C planahead 12 2 plan4headitestcases PlanAhe Wf round_3 vhdl bftLib C planahead 12 2 plandhead testcases Planahe GH round_2 vhdl bftLib C planahead 12 2 plandhead testcases PlanAhe amp round_1 vhdl bftLib C planahead 12 2 plandhead testcases PlanAhe amp core_transform vhdl bftLib C planahead 12 2 plandhead testcases PlanAhe OR hfk nachna hal Keb ih Chalana
588. the Implement pulldown menu as shown in Figure 9 16 Properties E Implementation Settings Make active E Create New Implementation Runs H Specify Partitions Part is Promote Partitions Figure 9 16 Create New Runs Command The Create New Runs wizard opens The first page of the wizard is a summary of the command 2 Click Next to proceed The Set Up Implementation Runs page opens as shown in Figure 9 17 G Create New Runs Set Up Implementation Runs Define the Part and Constraints for the implementation runs to be created Synthesized Netlist E synth_1 active Constraints Set E constrs_1 active Part xqSvix85ef676 2 Figure 9 17 Create New Runs Set Up Implementation Runs PlanAhead User Guide www xilinx com 301 UG632 v13 4 January 18 2012 Chapter 9 Implementing the Design g XILINX e Select for use in the runs For synthesis runs select a constraint set and a target part For implementation runs select a synthesis run a constraints set and a target part Note The default values of the Set Up Runs dialog box are defined by the active synthesis or implementation run at the time the Create New Runs command is run 3 Click Next to bring up the Choose Synthesis Strategies or Choose Implementation Strategies as shown in Figure 9 18 G Create New Runs Choose Implementation Strategies Create and configure one or more implementation runs usin
589. the Messages view Messages are grouped under specific headings to enable quick location of messages from different tools or processes For instance when you open the RTL design the PlanAhead tool displays the design and reports messages in the Message view as shown in Figure 4 7 58 warnings V 61 info messages how Al Oc eee e a a Tutorial Tutorial Created Datalproject 1 project 1 sres sources 1 imports hdl asyne fifo v 1 info message RTL Design 2 info messages open_rtl Peedi name rtl EKN info message Plandhead 58 Using Verific elaboration open_netlist_design name netlist_1 1 info message Project 5 Unisim Transformation Summary 4 total of 35 instances were transformed BUFGP gt BUFGP IBUFG BUFG 2 instances INV gt LUT1 33 instances Synthesis 26 warnings 30 info messages H C Plandhead Installiplandheaditestcases Plandhead Tutorial Tutorial Created Datalproject 1 project_1 srcs sources 1 imports hdl bft vhdl 3 warnings 23 info C Plandhead Installiplandhead testcases Plandhead Tutorial Tutorial Created Datalproject 1 project 1 srcs sources 1 importsthdl FifoBuffer v 2 warnings 3 info me E Tcl Console C a EJ Compilation 5 Package Pins Design Runs Figure 4 7 Messages View To open the Messages view select Windows gt Messages e Double click any of the messages to open the RTL source file in the Text Editor The source file opens with the appropriate
590. there are multiple synthesis and implementation runs defined in the project you should specify the active run prior to using the Specify Partitions command You can also access the Specify Partitions dialog box directly from the Synthesis Settings dialog box and Implementation Settings dialog box for each run See Configuring Synthesis Run Settings in Chapter 6 or Configuring Implementation Run Settings in Chapter 9 for more information 1 This figure shows both the Synthesize menu and the Implement menu open at the same time for illustration purposes only PlanAhead User Guide www xilinx com 383 UG632 v13 4 January 18 2012 Chapter 13 Using Hierarchical Design Techniques g XILINX G Specify Partitions i Specify whether partitions will be imported or implemented Implementation Action Import from Preservation Implement v NJA Ev usbEngine0 Implement v Nj e usbEngnei imot Q ject DP RTL importediproject DP RTL imported promote Xsynth 1 J Routing Routing Placement Synthesis Figure 13 3 Specify Partitions 2 The first time a design is implemented all partitions must be set to Implement because there are no promoted locations to import the implemented partitions 3 Set the partition action as follows e If you are importing a partition select Import as the action specify the Import from directory and specify the Preservation level for the partition The Import from directory lets you specify th
591. tion Implemented Utilization Part xc6vix75tfF784 3 Register 2 LUT 5 x v 2 critical warnings 71 warnings 118 info messages Show all RTL Design 2 critical report_resources 2 critical warnings C Plandhead Installiplandhead testcases Plandhead TutorialiProjects project bft core hdliproject bft core hdl srcs constrs 1 imports Sources bft ucf 2 critical warnings Td onsole E Compilation Reports Design Runs RTL Flow Figure 4 1 PlanAhead Tool Viewing Environment 1 Main Menu Contains the available commands Certain commands in the menu might not be available or might be greyed out if the command is not effective for the current state of the design or for the specific selected object 2 Main Toolbar Contains commonly used commands and extends to include Design specific commands 3 Flow Navigator Enables workflow like control over the design process The defined flow lets you manage project data view and edit RTL source and constraint files launch synthesis and implementation and generate bitstream files These commands are also located under the Flow menu of the main menu 92 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX The Viewing Environment 4 View Layout Selector Provides access to predefined and user defined view layout configurations See Using View Layouts page 96 for m
592. tion which contribute to the overall delay Note In the PlanAhead tool carry chain interconnect is counted as individual stages of logic so the stages reported might be different than levels of logic reported in ISE e Source Clock Displays the source clock name e Destination Clock Displays the destination clock name Sorting the Timing Report You can sort the Timing Results by clicking any of the column headers For example click on the Stages column header to sort the list by stages of logic Click the column header a second time to reverse the sort order You can sort by a second column by pressing the Ctrl key and clicking a second column header You can sort by as many columns as necessary to refine the sort results Press Ctrl and click the column header again to remove a sort from a column Refer to the Using Tree Table Style Views page 106 for information regarding working with tree table style views Figure 7 18 shows a timing result sorted by stages of logic Name Type Constrained Paths 10 P Pathi Setup P Path2 Setup P Path3 Setup P Path4 Setup P PathS Setup Setup Setup P Paks Setup Path Setup A a E Q a a Slack From Total Delay Logic Delay Net Stages Source Clock Destination Clock 1 059 usbEngineO usb_dma_ usbEngineO ut dout_14 D 4 191 1 771 57 7 6 TS_usbClk TS_usbClk 1 059 usbEngine1 usb_dma_ usbEngine1 u dout_14 D 4 191 1 771 SA 6 T5_usbCik TS_usbclk 1 1
593. tistics Reports Resource statistics displayed in the Instance Properties Clock Region and Pblock Properties View can be exported to an Microsoft Excel format file Information includes resource utilization RPM and carry chain sizes clocks and clocked instances and other relevant resource data To export the data from the Statistics tab of the Instance Clock Region or Pblock Properties View select Export Statistics The dialog box lets you define the information to include in the report as well as how many levels of hierarchy to report SSN Analysis Report The results from Simultaneous Switching Noise SSN analysis can be exported to a CSV report file by specifying a file name and location in the Run SSN Analysis dialog box WASSO Analysis Reports The results from the Weighted Average Simultaneous Switching Output WASSO analysis can be exported to a text report file by specifying a file name and location in the Run WASSO Analysis dialog box Strategy Files The Strategy directory contains files with your specified default command line options for ISE implementation commands You can apply a strategy to any given ISE attempt You can either create strategies or copy a supplied strategy PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 413 Appendix A PlanAhead Input and Output Files XILINX Outputs for Environment Defaults The PlanAhead tool saves the current configuration
594. to avoid Implementation errors Whenever possible you should perform the I O pin planning after logic Synthesis The presence of a netlist ensures that the clocks clock logic differential pairs GTs and so forth are recognized and considered automatically during pin assignment in PlanAhead Also there are many Design Rule Checks DRCs that are performed based on logic connectivity and clocks to ensure a legal placement prior to Implementation To perform I O pin planning in Project Navigator prior to running Synthesis e Inthe Processes pane expand User Constraints and double click IO Pin Planning PlanAhead Pre Synthesis or e Select the Tools gt PlanAhead gt Pre Synthesis IO Pin Planning command When you invoke the PlanAhead tool Project Navigator passes all of the RTL source files the top level module name and the UCF s to PlanAhead The PlanAhead tool opens with a display of the default I O Planning view layout The PlanAhead tool performs an RTL elaboration to extract and display the top level I O ports in the I O Ports view When you save or close the PlanAhead project it updates the original Project Navigator source UCF s This resets the Project Navigator design process state if appropriate Refer to Passing Logic and Constraints page 404 for more information about the integration mechanics and process Refer to Chapter 8 I O Pin Planning for more information about using the I O Planning view layout I O Pin
595. to the FPGA logic Some resources such as Clock Regions and I O Banks are displayed even when viewing the whole device In addition the Device View Layers slideout lets you turn on or off the display of specific objects or resources in the Device view For more information see Setting Visible Device View Layers page 131 130 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Using Common Views The PlanAhead tool Device view resource placement process is e The I O pads and clock objects display around the periphery and or down the center of the device e I O banks display as thin color shaded rectangles just outside the row of I O pads e The 7 series FPGAs offer both high performance HP and high range HR I O banks which display in the Device view as right or left angled lines e Available I O bank sites display as color filled I O bank rectangles e Some devices have unbonded I O banks that display with empty I O bank rectangles e The I O clock pads display as filled in rectangles e All clock resources such as BUFGs BUFRS and BUFGPs show in the Device view When you select an I O bank or clock region the available device resources display in the Properties view e The interior of the device is broken up into smaller rectangles called Tiles Tiles are placement sites for the different types of logic primitives for the architecture A tool tip identifies each site in the Device view w
596. to_bram_packing yes use_dsp48 auto resource_sharing yes iob true netlist_hierarchy rebuilt ZIIRIIRIRIRIRIRIRIERIRIR power no lt Select an option aboye to see description of it Figure 6 4 Design Run Settings for a Synthesis Run Synthesis Launch Options The Specify Launch Options dialog box options as shown in Figure 6 5 page 203 are Launch Directory Specify a location to create and store the Synthesis run data Note Defining any non default location outside of the project directory structure makes the project non portable because absolute paths are written into the project files Launch Runs on Local Host Launch the run on the local machine processor www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Creating and Managing New Runs Number of Jobs Define the number of local processors to use for runs This option is used only when you are launching multiple runs simultaneously Individual runs are launched on each processor No multi threaded processors are used with this option Launch Runs on Remote Hosts Linux only Use remote hosts to launch one or more jobs See Launching Runs on Remote Linux Hosts in Chapter 9 e Configure Hosts Select this option to configure remote hosts Generate scripts only Export and create the run directory and run script but do not launch the run at this time The script can be run at a later time
597. tomatically scroll to selected objects toolbar button in the Netlist view The entire netlist tree can be collapsed by selecting the Collapse All toolbar buttonin mga the Netlist view For more information see Using View Specific Toolbar Commands mi page 108 The Netlist tree collapses to display only the top level logic modules You can select instances and apply commands using the main menu the toolbar or the popup menu www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX PlanAhead User Guide Using Common Views Use the Shift key or the Ctrl key to select multiple elements in the Netlist view for use with most commands Selected logic is highlighted in the Netlist view Logic selected in a different view such as the Schematic or Device views is cross selected in the Netlist view The Netlist tree expands automatically to display all selected logic You might need to scroll the tree to view all selected logic Collapsing the Netlist tree does not unselect logic Primitive logic is placed ina Primitives folder for each level of the hierarchy This condenses the display of logic content and hierarchical modules in the Netlist view as shown in Figure 4 60 gt Primitives 153 c 8 cpuEngine or1200_top Nets 2178 B Primitives 12 E Mxor_n0164_3_xo lt 0 gt 1_F MUXF E Mxor_n0164_3_xo lt 0 gt 11 LUT3 E Mxor_n0164_3_xo lt 0 gt 12 LUTS i Mxor_n1834_xo
598. tool facilitates I O planning at different stages of the design process As the design progresses more information becomes available enabling more complex rule checking as the design is synthesized and implemented Proper I O assignment can depend on how the clocks are configured assigning I Os and clock logic often go together For the I O placement DRCs to account for clocks you must have a synthesized Netlist Design Whenever possible it is optimal to perform I O assignment with a Netlist Design The final validation of an I O pin and clock configuration is to implement the design Proper clock resource validation can require full implementation of all clocks The PlanAhead tool lets you do I O Planning starting with an empty project moving to RTL source files synthesized netlist and finally working in an Implemented Design The kinds of work you can do in each step of the design process varies because early in the process some data is missing consequently analysis is an estimate only and later in the process some data is decide consequently design changes can be restricted www xilinx com 251 UG632 v13 4 January 18 2012 Chapter 8 VO Pin Planning XILINX 252 The following briefly describes the design stages 1 Creating Pin Planning Projects You can create an empty project to enable early device exploration and I O port configuration Create I O ports manually or import them from CSV or UCF inputs Export de
599. top level module for the design in most cases 2 Inthe Specify Top Module dialog box shown in Figure 5 1 page 177 enter the top level module and click OK 176 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Elaborating and Analyzing the RTL Design e Specify Top Module i Specify the top module name of your design Initialize RTL file list based on selected top module Options Top Module Name bft C Scan and Add RTL Include Files C Auto Re order Source Files Figure 5 1 Specify Top Module Dialog Box The Messages view displays the results of the compilation and flags irregularities in the RTL source files under the heading of Analysis You can filter the Messages view to display errors or warnings or informational messages from the results of RTL elaboration To enable or disable the display of Errors Critical Warnings Warnings or Informational messages select a checkbox in the banner of the Messages view You can select any of the warning or error messages in the Messages view to load the appropriate RTL source file with the selected source code highlighted in the Text Editor Resource Estimation of the RTL Design PlanAhead User Guide When you select RTL Design the PlanAhead tool automatically elaborates the RTL design generates the top level schematic view and displays the design in the Design Analysis view layout Figure 5 2 page 178 shows the RTL Design Analysis
600. tor www xilinx com 345 UG632 v13 4 January 18 2012 Chapter 11 Analyzing Implementation Results g XILINX The PlanAhead tool opens the Run TRCE dialog box as shown in Figure 11 5 G Run TRCE x i Specify settings for TRCE static timing analysis Results Name results_1 TRCE Options e 30 4 30 u 0 stamp tsi nodatasheet Fastpaths oO More Options e This option causes the timing report to be an error report instead of a default A summary report The value supplied for this switch is an integer limit on the number of items reported for each timing constraint in the report file The iM Open in a new tab Figure 11 5 Run TRCE Dialog Box e Results Name Specifies the name of the results for the output timing results As a default the results are written to a file in the implementation directory with the name of the top module and the specified Results Name combined The output file name can also be changed by specifying the o option in the More Options field The results are posted to the Timing Results view under the specified results name See Using the Timing Results View page 348 TRCE Options e e lt limit gt Causes the timing report to be an error report instead of the default summary report lt limit gt is an integer from 0 to 32 000 inclusive that restricts the number of items reported for the different violations of each timing constraint e y lt lim
601. tory The location shown in Figure A 1 or C Documents and Settings user_name Application Data Xilinx PlanAhead project_name O C Documents and Settings user_name 4pplicaion Data Planahead Name DB version mn strategies la plan4head jou e plandhead jou_backup planahead log la plan4head log_backup plandhead nac2edif log 3 plandhead _pid4032 debug results_1_drc txt Figure A 1 PlanAhead Directories for Reporting Output Table A 2 page 413 lists the PlanAhead output files and a description www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Table A 2 Reporting Outputs Outputs for Reports Verilog VHDL File Name Description I O Pin Assignment CSV I O pin assignments are stored in a CSV format file that contains the I O port assignment and relative package pin information This file used for RTL port header definition and PCB schematic symbol generation I O Pin Assignment RTL Verilog or VHDL format file contains the I O port assignments defined as ports in the file header in a legal language format This file is used for RTL port header definition Log File planAhead log planAhead log backup The log file planAhead 1og captures the contents of the messages created from running PlanAhead commands View the file by selecting Window gt View Log File Journal File planAhead jou and planAhead jou backup The journal file planAhead j
602. traints Logic connectivity in the form of Register Transfer Level RTL sources or synthesized netlists are passed into the PlanAhead tool for analysis purposes only and not passed back to Project Navigator The PlanAhead tool features that enable logic or timing constraint modification are disabled in ISE Integration mode You must perform logic modifications in Project Navigator an external RTL or in synthesis tools The PlanAhead tool passes only the UCF constraint files to Project Navigator The PlanAhead tool maintains the original content and format of the UCF files including comments incomplete constraints and so forth The legality of constraints in the design is not checked upon opening or closing the PlanAhead tool The Translate Process step in Project Navigator does the constraint checking When you invoke the PlanAhead tool the UCF source files in the Project Navigator project are passed to the PlanAhead tool project where you can add or modify physical constraints When you use the Save Project command in the PlanAhead tool the software writes the modified UCF files back to the original Project Navigator source location If you make constraint changes in the PlanAhead tool and select the Exit command you are prompted to save changes back to the Project Navigator project before the tool closes If the PlanAhead tool is invoked and no UCF exists in the Project Navigator project you are prompted to create one This empty U
603. ts KAPPs PlanAhead_XPS_Ar 9 leds_Sbits_wrapper ngc N A C Data Xilinx_Documents KAPPs PlanAhead_XPS_Ar 10 leds_positions_wrapper ngc N A C Pata Xilinx_Documents XAPPs PlanAhead_XPS_Ar 11 imear_flash_invertor_wrapper ngc N A C Pata Xilinx_Documents KAPPs PlanAhead_XPS_Ar G12 inear_flash_wrapper ngc N A C Pata Kilinx_Documents KAPPs PianAhead_xPS_Ar _ Scan and Add RTL Indude Files into Project m i F Copy Sources into Project Add Sources from Subdirectories PlanAhead User Guide Figure 3 33 Add Sources Select Add Files to browse for and select the NGC files as well as the system_stub bmm file found in the implementation subdirectory of the embedded processor design Disable the Scan and Add RTL Include Files into Project and Copy Sources in Project options If you copy the embedded processor system files into the local project directories the PlanAhead project files could become out of sync with the XPS project See Using Remote Sources or Copying Sources into Project page 55 for more information Select OK and Finish The system ngc file has been added to PlanAhead project www xilinx com 75 UG632 v13 4 January 18 2012 76 Chapter 3 Working with Projects XILINX Adding the Embedded Processor System Constraints After the design files are added to the project you must add the embedded processor system placement and timing constraints into the PlanAhead project If t
604. ts cover the same paths nodatasheet Excludes the datasheet section of the standard timing report fastpaths Reports the fastest paths of a design More Options Applies the specified TRACE options For more information about specific TRACE commands see the Command Line Tools User Guide UG628 as cited in Appendix E Additional Resources Two examples of additional commands are e o lt file_name gt Specifies the name of the output timing report The twr extension is optional e s lt speed_grade gt Overrides the device speed contained in the design and instead performs an analysis for the device speed specified The option lets you see if faster or slower speed grades might meet your timing requirements lt speed_grade gt can be specified as values of 1 2 or 3 entered with or without the leading dash Open in a New Tab Specifies that the timing report as a result of the run should be opened in a new tab in the Timing Results view If this option is not specified the last timing results are closed when the new report is opened The PlanAhead tool displays the results from TRACE timing analysis by extracting information from the TWX timing report files After the TWX files are imported the timing results display in the Timing Results view If no timing constraints are returned then no timing results display Importing ISE TRCE Timing Results into an Existing Project PlanAhead User Guide You can im
605. ts with Design Preservation WP362 http www xilinx com support documentation white_papers wp362 pdf Application Notes 438 AXI Multi Ported Memory Controller XAPP739 http www xilinx com support documentation application_notes xapp739_axi_mpmce pdf Fast Configuration of PCI Express Technology through Partial Reconfiguration XAPP883 http www xilinx com support documentation application_notes xapp883_Fast_Config_PCle pdf www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX PlanAhead Documentation e PRC EPRC Data Integrity and Security Controller for Partial Reconfiguration XAPP887 http www xilinx com support documentation application_notes xapp887_PRC_EPRC pdf PlanAhead Documentation e PlanAhead User Guides http www xilinx com support documentation dt_planahead_planahead13 4_userguides htm Floorplanning Methodology Guide UG633 http www xilinx com support documentation sw_manuals xilinx13_4 Floorplanning_Methodolgy_Guide pdf Hierarchical Design Methodology Guide UG748 http www xilinx com support documentation sw_manuals xilinx13_4 Hierarchical_Design_Methodolgy_Guide pdf Pin Planning Methodology Guide UG792 http www xilinx com support documentation sw_manuals xilinx13_4 ug792_pinplan pdf PlanAhead Tcl Command Reference Guide UG789 http www xilinx com support documentation sw_manuals xilinx13_4
606. uide UG632 v13 4 January 18 2012 XILINX Using Common Views The PlanAhead Options dialog box is available by selecting Tools gt Options gt Schematic Figure 4 54 shows the Schematic options in the PlanAhead Options dialog box G PlanAhead Options Schematic Attribute Types Instance nd Available Attributes Displayed Attributes Cell Ref Inst Equation Ly J Window Behavior OK Cancel Apply Figure 4 54 PlanAhead Options Schematic Instance Annotation Set the Attribute type field to Instance 2 Select from the Available Attributes to annotate on the left side of the dialog box shown in Figure 4 54 and use arrows to move them to the right side labeled Displayed Attributes and click OK Figure 4 55 is an example of the resulting instance annotation gt ae as ot we amp x a f SPECIAL_SVGA_TIMING_GENERATION pixel_count_inst_cy_16 o DI CR MUXCY lt gt Hi Package Device Schematic x 1 D Figure 4 55 Annotated Instances in the Schematic View PlanAhead User Guide www xilinx com 143 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment XILINX 144 Viewing Timing Path Logic in the Schematic View You can select Timing paths from the PlanAhead Timing Results view and the paths then display in the Schematic view All of the objects on the selected path or group of paths display with the logic hierarchy boundar
607. uns view the Synthesis Run Properties or Implementation Run Properties view displays the current configuration of the selected run In the Run Properties view you can view or modify run properties for each run See Using the Run Properties View in Chapter 4 for more information In the Design RUns view you can use the Show Search Collapse All and Expand All buttons to filter the Runs displayed in the table The options are e Launch Selected Runs Launches the active run e Reset Selected Runs Resets a run to a Not Started status and remove the data e Create New Runs Invokes the Create Multiple Runs wizard e Import Run Results Opens the Implemented Design environment with the run results loaded Setting the Active Run Only one synthesis run and one implementation run can be active in the PlanAhead tool at any time The Compilation and Messages views Status Bar and Project Summary display the information for the active run The Project Summary view only displays compilation resource and summary information for the active run To make a run active select the run in the Design Runs view and use the Make Active command from the popup menu to set it as the active run Launching Selected Runs The Launch Runs command launches existing Runs in the Design Runs view You can launch Runs in any state including completed Runs The Launch Selected Runs dialog box displays first so you can set launch options 1 Inthe
608. unter_width Disabled exclude_from_data_storage match_type basic match_units 1 Select an option above to see description of it OK Cancel Figure 12 7 Customizing Ports and Options of Debug Cores 3 Select the port type in the drop down www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Debugging the Design with ChipScope Any configurable options for the port display in the Options area The port width starts as a default but expands or contracts as you add or remove nets from the port 4 Click OK To remove a debug port in the ChipScope tab select the port and select Delete Connecting and Disconnecting Nets to Debug Cores You can select and then drag and drop nets and buses vectors of nets from the Schematic view or the Netlist view onto the debug core ports shown in the following figure This expands the port as needed to accommodate the net selection Also you can right click on any net or bus and select Assign to ChipScope Debug Port To disconnect nets from the debug core port select the nets that are connected to the debug core port and click Disconnect Net Figure 12 8 illustrates these activities GS project_1 C PA_Project ChipScope_Project bft_core project_1 project_1 ppr PlanAhead 13 1 File Edit Flow Tools Window Layout View Help Q Search cor ni Gg BeB aex a gt gt X izi e X x 2S chipScope N Q ia y aN Bitstream
609. up by Type or Flat List Toggle Button 106 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Working with Views Using the Show Search Capability to Filter the List Click the Show Search button to display a search field in the banner of the view a enabling any text string to be entered to filter the list displayed in the table view Use the keyboard shortcut Alt to quickly access this command For best results flatten the list first by using the Group by Type toggle button described in the previous section Any column in the table can be used as search filter criteria Select the pulldown menu in the Search field to select a column header to search Figure 4 20 shows the search pulldown menu Interface Neg Diff Pair Location Figure 4 20 Search Pull down Menu Enter any text string and the list adjusts dynamically to list only those entries that contain the string Select the Show Search button again to remove the Search field and sorting Sorting Columns Sort any table by clicking in a column header This sorts the data in the table in an increasing order according to the sort criteria of the selected column Click the column header again to sort the data in the table in a decreasing order according to the sort criteria of the selected column A visual indication of the sort order and direction displays in the column header as shown in Figure 4 21 Clock 2 voltage 1 Figure 4 21
610. urce for example a particular define macro should be referenced by an include statement rather than marked as a global include file Launching a Synthesis Run To launch Synthesis click the Synthesize button The PlanAhead tool uses the current Synthesis Project Settings to launch the run Synthesize The Status Bar indicates that Synthesis is running and the Compilation view begins to display the active command status Configuring Synthesis Run Settings You can set the Synthesis run options using the Synthesis Settings command Figure 6 2 shows the Flow Navigator Synthesize button pulldown menu mydiv8 v RTL Design v mymults v testbench y gt therm amp Constraints 1 Synthesize aj constrs_1 LNB Synthesis SottiNgS of Create Multiple Runs Configure and launch synthesis Figure 6 2 Configuring Synthesis Run Settings The Synthesis Settings dialog box opens as shown in Figure 6 3 G Synthesis Settings i Change synthesis options and launch the run Options Top Module Name fop Constraint Set constrs_1 active Options 2 fast_area_reduction XST 13 Launch Options Launch with 2 jobs on local host XSIRANDYH Language Options loop_count 1000 yerilog_version Verilog 2001 Specify Partitions wbArbEngine Implement usbEngine0 Implement usbEngine1 Implement Figure 6 3 Synthesis Settings Dialog Box PlanAhead
611. urces view popup menu commands are 124 Source File Properties Ctrl E Source File Properties Invokes the Source Hat Copy Text Ctri c File Properties view See Viewing Source File GR Open File AO Properties page 127 Update File Alt U Note This command is called Source Node Properties in the Hierarchy tab Copy Text Lets you copy the selected text to Remove File from Project Delete paste into another location Use this command to select a filename for instance and copy it Dizabie Fie AR Minas into the Tcl Console Move to Simulation Sources Open File Opens the selected file s in the Move to Top Text Editor view For information on using the Move Up features in the Text Editor refer to Using the Move Down Text Editor page 157 Move to Bottom Update File Replaces Source files with the Hierarchy Update gt newly selected files See Updating Local Source Set Global Include Files in Chapter 3 Copy File into Project Copies selected Set Library Alt L source files and directories into the project Set Type directory This command is only enabled when Set Used In the selected source file is not currently localto RENAE ER the project See Using Remote Sources or g Copying Sources into Project in Chapter 3 Bie rri Copy All Files Into Project Copies remotely referenced source files into the local project directory This command is only available when the source files are not
612. us as shown in Figure 12 6 G Set up ChipScope Specify Nets to Debug Specify Nets for debugging using ChipScope Name ClockDomain TRIG DATA E MULTIPLIER inb_latched 14 clk_scaler 9 Vv Vv GH MULTIPLIER mult_counter 3 clk_scaler 9 Vv Vv Select Clock Domain Oe ae Set TRIG only Set DATA only Set TRIG and DATA Export to Spreadsheet Add Remove Nets Nets to debug 32 Figure 12 6 Specifying Debug Nets and Clock Domains If multiple clocks are detected for a given net a drop down list allows the selection of different clocks for the net or bus 1 To modify the debug net selection further click Add Remove Nets 2 Configure each net or bus for use as a trigger data storage or both 3 When the net and clock configuration is correct click Next to proceed to the summary screen If ILA cores exist in the design you are prompted to remove them and regenerate based on the new information or to keep them intact and generate new cores Inserting ILA Cores The ChipScope wizard inserts one ILA core per clock domain The nets that were selected for debug are assigned automatically to the trigger and data ports of the instantiated ILA cores The last wizard screen shows the core creation summary displaying the number of clocks found and ILA cores to be created and or removed PlanAhead User Guide www xilinx com 375 UG632 v13 4 January 18 2012 376 Chapter 12 Programming and Debugging the Design
613. usbEngineO u uO state_FS I2 LUT6 G 6 usbEngine0 u0 u0 idle long I3 LUT4 E 7 usbEngine0 u0 u0 idle long I3 LUT4 F 8 usbEngineO uO uOjfidle_long I1 LUTS E 9 usbEngine0 u0 u0 ide_long Q FDR LUT saw PSU FF 12hgs1 Luts state_suspena ser SWO LUT y Ft ouanrnnte ons se a lt M wabe_wawl_Is General Pins Aliases Attributes Connectivity lt j Figure 4 51 Select Net in Schematic view When you select objects in the Schematic view the Properties view for the selected object opens as well Notice in Figure 4 51 that the Net Properties view has opened for the selected net In this case the Connectivity tab of the Net Properties view is displayed 140 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Using Common Views The Connectivity tab traverses the hierarchy to report all primitive instances connected to the net This is different from the Pins tab which reports the pins of all instances connected to the net reporting both primitive and hierarchical instances Select a net that is connected to a hierarchical instance to see the difference between these tabs Removing Objects From the Schematic View You can remove selected objects and their associated connectivity using the Remove X selected elements from schematic toolbar button in the Schematic view Printing the Schematic View You can print the Schematic view using the File gt Print command which print
614. ux_40_OUT45 LUTS 51 C Mmux_GND_6_0_GND_6_0_mux_40_OUT46 LUT6 C Mmux_GND_6_0_GND_6_0_mux_40_OUTS2 LUTS ggetize full wire wr_ack wire C Mmux_GND_6_o0_GND_6_0_mux_40_OUTS3 LUTS 53 E ee LUT6 54async_fifo buffer_fifo din din rd_clk rd_clk rd_en Mmux_GND_6_0_GND_6_o_mux_40_OUTSS LUTS 7 s C Mmux_GND_6_0_GND_6_0_mux_40_OUTS6 LUTE 55 defparam buffer_fifo FIFO_WIDTH 32 i Mmux_GND_6_0_GND_6_0_mux_40_OUT62 LUTE 56 defparam buffer_fifo FIFO_DEPTH 10 Peleg ae oles LUT6 57 defparam buffer _fifo DEVICE VIRTEX6 G Mmux_GND_6_o_GND_6_o_mux_40_OUTS64 LUTS a aia n C Mmux_GND_6_0_GND_6_0_mux_40_OUTES LUTS 58 defparam buffer_fifo FIFO_RAM TYPE BLOCKRAM C Mmux_GND_6_0_GND_6_o0_mux_40_OUT66 LUTS 59 defparam buffer _fifo OPTIMIZE POWER C Mmux_GND_6_0_GND_6_o0_mux_40_OUT 72 LUT6 60 LUTE E Mmmux_GND_6_9_GND_6_o_mux_40_OUT73 LUTE Gil fl asain full full wire amp Sources s A Netlist Timing Constraints 2 critical warnings 84 warnings 98 info messages how Al i xst 3210 line 54 Output port lt prog_empty gt of the instance lt buffer_fifo gt is unconnected or connected to loadless signal xst 3210 line 54 Output port lt prog_full gt of the instance lt buffer_fifo gt is unconnected or connected to loadless signal xst 0 The RAM lt Mram_fifo_ram gt will be implemented as a BLOCK RAM absorbing the Following register s S O xst 2677 21 warn
615. v13 4 January 18 2012 Table of Contents Revision History i 4 cece cr diarctuaesdiewe hater edi wi bee areien Chapter 1 About the PlanAhead Tool About PlanAhead Software 0 0 0c c eee cece eee Using the PlanAhead Toei 05441n2406s dawg en nde sd eweeseunaie Launching the PlanAhead Tool 0 005 Chapter 2 The PlanAhead Tool Flow Design FIOW sini saceterpaeeteniieg ide ieee eee ieee User Models 3 0 sisjoevrgeuetdveraodetauestderehereeeaaoaenens Understanding the Flow Navigator 04 Working with Designs 0 0 000 c cece eee eee Chapter 3 Working with Projects Project Fy Pes 2ie4 ci iis cae etunimeksi imik e unir eS rE ie Creating a New Project 0 00 c02s se0sbaednege estes snagucue eens Managing Projects lt 06 dcstiscatidessacesdaciaseccadeisices Managing Project Sources 600 ccc cece eee eee Managing RTL Source Files 0 0 0 cece eee eee Managing Constraints 6 ccc cece eee eee Managing Simulation Sources 0 0 000 e eee eee Managing IP Cores cic sos cvicsetst advances daecdnsaceebece secs Importing XPS Embedded Processor Designs Using the Project Summary view 0 0020000 Configuring Project Settings 0 0c eee Chapter 4 Using the Viewing Environment The Viewing Environment 0 000
616. ve netlist The software uses that netlist by default when opening designs or launching runs For more information on creating and managing multiple synthesis runs see Chapter 6 Synthesizing the Design PlanAhead User Guide UG632 v13 4 January 18 2012 www xilinx com 29 Chapter 2 The PlanAhead Tool Flow XILINX Opening an Implemented Design An Implemented Design consists of a completed implementation run Because the PlanAhead tool allows for multiple implementation runs you can select any completed implementation run to open in the Implemented Design G project_cpu_hdl C PlanAhead_Install planAhead testcases PlanAhead_Tutorial Projects project_cpu_hdl project_cpu_hdl ppr PlanAhead 13 3 0R0 File Edit Flow Tools Window Layout View Help Tee wax dd BH AHS OS RZ B besig analysis Project Manager RTL Design Synthesize Primitives T cpuEngine o Netlist Design E FFtEngine fft E matEngine matTo E usbEngined us gt evtarisenses E wbArbEngine wb _con Implement E Resource Estimation Sp Power Analysis Run pre E Report Clock Networks G Report Timing IW Slack Histogram 2 FPGA Editor Sources BI Netlist S XPower Analyzer Properties GE Timing Simulation SB Program and Debug Slack 1 From To Total Delay Logic Delay Net Delay Logic Net Stages Source Clack Destinatio eg esr ie 0 Setup P Path i Slow SETUP 0 23 reset_reg Q us
617. vel modules or instantiated into a system level design during project creation or when using Add Sources The files are under the Cores folder in the Sources view In XPS the synthesis and implementation subdirectories are automatically created when you use either the Hardware gt Generate Netlist or Hardware gt Generate Bitstream commands e The synthesis subdirectory contains all the XST synthesis scripts scr project files prj and report srp files that create the netlists used for implementation e The implementation subdirectory contains a copy of the User Constraints file UCF Block RAM Memory Map BMM files for configuring the block RAMs on the device and the implementation results including the BIT file You can import an embedded system core into a PlanAhead project after running synthesis on the embedded system The following material briefly addresses how to create an embedded processor system in XPS and import it into the PlanAhead tool For complete details on the use of XPS and EDK refer to EDK Documentation in Appendix E www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Importing XPS Embedded Processor Designs Creating an Embedded Processor System PlanAhead User Guide The first step is to create your embedded processor system using the Xilinx Platform Studio XPS design environment Your embedded processor system might include the MicroBlaze processor and embedde
618. vice and I O port assignment in any of these formats for use later in the design process for example in an RTL design project 2 Elaborating and Checking RTL Designs You can perform I O planning in a PlanAhead application RTL based project When an RTL Design is elaborated the software provides basic DRC checks To check clock logic validation with a synthesized netlist is recommended 3 Synthesizing Netlist Designs You can perform I O planning after synthesis in the Netlist Design Because all clocks are determined the PlanAhead tool performs a more thorough validation because the tool has visibility into all clocks Whenever possible perform I O assignment using a Netlist Design 4 Implementing the Design and Final I O Validation The Design must be fully implemented to ensure a legal I O pinout Examine the NGDBuild and MAP reports for I O and clock related messages Only ISE Implementation tools have sign off DRCs Configuring and Placing I O Ports To select and configure ports or interfaces use Configure I O Ports You can set I O standard drive strength and slew type The I O Planning view layout lets you output to a CSV format file for use in PCB schematic symbol creation or the HDL port list See Configuring I O Ports page 262 You can place a prohibit property on individual I O pins or I O banks to prevent I O assignment to them See Prohibiting I O Pins and I O Banks page 267 To perform I O port placement use
619. view layout The PlanAhead tool also applies the active constraint set to the elaborated design when it opens the RTL Design This enables e I O pin planning based on the RTL port list and e Module level floorplanning from the RTL logic hierarchy For information on creating and managing constraint sets see Managing Constraints page 56 www xilinx com 177 UG632 v13 4 January 18 2012 Chapter 5 RTL Design XILINX O project_cpu_hdl C PlanAhead_Install planAhead testcases PlanAhead_Tutorial Projects project_cpu_hdl project_cpu_hdl ppr PlanAhead 13 2 File Edit Layout View Help feo X BD e NAO G KE IG E Desn Anass z Project Manager Flow Tools Window RTL Netlist DE Run Noise Analysis Q Behavioral Simulation Synthesize Implement Program and Debug 178 gt Netlist Design X lee 8 Implemented Design w ri 4 Properties e B 00x E Project Summary x t RTL Schemat RTL Design LE IP Catal om AE 1Sinstances 1441 0 Ports 922 Nets lo atalog CE Elaborate H B Nets x G Primitives 11 R E Resource Estimation amp H cpuEngine top a S E fftEngine fft E Power Estimation E I ngtenaine motor z a E usbEngined rRunorc i usbEngine t E i wbArbEngine wb_conmax_top dw 32 aw 32 rf_addr 4 b11 1 1 p amp Sources RTL Netlist Timing Constraints UCF 00x Tel Console INFO ArchReader 8 Lo
620. ww xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Appendix D Configuring SSH Without Password Prompting The PlanAhead application allows you to run synthesis and implementation runs on remote hosts or multiple hosts simultaneously The multiple host capabilities for executing the PlanAhead tool runs uses Secure Shell SSH a service provided by Linux operating system Prior to configuring multiple hosts in the PlanAhead tool you should configure SSH so that you are not prompted for a password each time you log in to a remote machine Setting Up SSH Key Agent Forward SSH configuration is accomplished with the following commands at a Linux terminal or shell Note This is a one time step and when successfully set up does not need to be repeated 1 Run the following command at a Linux terminal or shell to generate a public key on your primary machine Though not required it is a good practice to enter and remember a private key phrase when prompted for maximum security ssh keygen t rsa 2 Append the contents of your publish key to an authorized_keys file on the remote machine Change remote_server to a valid host name cat ssh id_rsa pub ssh remote_server cat gt gt ssh authorized_keys 3 Run the following command to prompt for your private key pass phrase and enable key forwarding ssh add You should now be able to ssh to any machine without typing a password The fi
621. ww xilinx com 185 UG632 v13 4 January 18 2012 Chapter 5 RTL Design XILINX Table 5 2 Color Legend Text Color Description black Default value as determined by the tool blue User override This field is normally calculated by the tool Warning Indicates the resource configuration is not supported or the orange 8 value exceeds the device normal operating range Error The resource configuration or count is invalid or the value exceeds red i the device maximum operating range e Power Utilization Shows the power distribution by resource type e Expand the power utilization bars to see power based on the design hierarchy e Selecting any object highlights the object in the Netlist view and opens the properties window Holding the mouse over an object also provides more details and the right mouse menu provides access to specific commands Viewing Netlist and Instance Power Properties When you select the top level of the design hierarchy in the RTL Netlist view the Netlist Properties view opens also After running Power Estimation the Netlist Properties view includes various power properties such as the RTL Hierarchy Power table as shown in Figure 5 8 page 187 The RTL Hierarchy Power table reports the power distribution by resource type for each module instantiated from the top level 186 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Estimating P
622. www xilinx com 161 UG632 v13 4 January 18 2012 162 Chapter 4 Using the Viewing Environment XILINX e Source Files Contains checkboxes to copy sources recurse through the subdirectories to locate source files and to show the file path in the Text Editor e I O Placement Toggles ON or OFF the interactive I O placement DRCs e Connectivity Display Controls how connectivity displays in the Device view e File Saving Defines whether PlanAhead should save project files automatically when closing or prompt to save any changes e Text Editor Defines the preferred text editor to use when opening source RTL or UCF files for modification There are a number of preconfigured Text Editors to choose from or you can specify the command line to launch a third party text editor The native text editor is the default selection which opens if the PlanAhead tool detects issues with the specified text editor e Tabs Specifies that the Text Editor should use the Tab character t or use a specified number of spaces when a tab is inserted This allows the text file to be portable to third party applications that might not properly handle tab characters Note Some features of PlanAhead are not supported in third party text editors e Language amp Tooltips Specify the language and behavior of the tooltips that appear when you move your mouse over a command in the PlanAhead tool The supported languages are English Chi
623. www xilinx com 169 UG632 v13 4 January 18 2012 Chapter 4 Using the Viewing Environment g XILINX XILI document co KOMATO ected by copyr rs to original ther work distr e of derivitive Change Style Iq m e a 2 o final author s 1 Name Monospaced final license ag Text Style dified form immd Themes as nx Inc Re Normal Font C Bold Italic sage NX IS PROVIDING Selection Rules CA Background TESY TO YOU B D Keywords1 e Foreground 153 204 0 POSSIBLE IMPLH aa Keywords2 a E 153 204 DARD XILINX IS Shortcuts Keywords3 Effect None Literal1 Literal2 Effect Color E Label Operator Stripe Color REE FROM ANY CLA OBTAINING ANY R NX EXPRESSLY DI ADEQUACY OF THE WARRANTIES OR Ri T CLAIMS OF INFR Reset to Defaults FITNESS FOR A PA LY Pa VIMILLELLLLLL LF a Window Behavior FifoBuffer clk Figure 4 76 Font Options for PlanAhead Text Editor Use the Reset to Defaults command to reset the default font definitions 170 www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX Configuring PlanAhead Setting General Window Behavior Options To set the window behavior options select Tools gt Options gt Window Behavior Figure 4 77 shows the Window Behavior dialog box G PlanAhead Options Window Behavior
624. x use the one of the following methods e Project Settings toolbar button 25 e Project Settings from the Project Manager menu in the Flow Navigator e Click the Edit link in the Project Summary view The Project Settings dialog box opens as shown in Figure 3 40 G Project Settings General Name project_cpu_hdl Project Part xc6vix75tff784 3 active Simulation Target Language Verilog D Top Module Name top Synthesis Language Options loop_count 1000 verilog_version Verilog 2001 Implementation t G Language Options IP Catalog Verilog Options verilog_version Verilog 2001 e IG Top Library Generics Parameters Loop Count E 1 000 4 Figure 3 40 General Project Settings and Language Options The Project Settings dialog box shows the following menu on the left hand side e General Displays a dialog box where you can view the project Name specify the Top Module Name and set language options PlanAhead User Guide www xilinx com 83 UG632 v13 4 January 18 2012 Chapter 3 Working with Projects XILINX Simulation Displays the Simulation Set the Simulation Top Module Name Top Module Design Under Test Simulation Runtime and a tabbed listing of Launch Options Language Options and Netlist Options The currently selected options have a green check mark Synthesis Shows the Default Part and Default Constraints Set and provides an Options area
625. xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 g XILINX Disabling or Enabling Interactive Design Rule Checking The interactive I O placement routines check common error cases You can toggle this capability on and off using e Inthe Device or Package view toolbar menu click Autocheck I O Placement button or PI e Use the Tools gt Options command from the main menu and click the General button on the left hand side of the dialog box This allows you to set the option under I O Placement When you enable automatic checking the tool does not allow placement of I O ports on pins that cause a design issue In Place I O Ports Sequentially mode if you attempt to place an I O Port on a problematic pin a tool tip display that describes why the I O Port is not able to be placed The interactive DRC checks are enabled by default Note Many of these checks can run only when a synthesized netlist of the full design is loaded The interactive I O placement rules include e Prohibiting e Placement on noise sensitive pins associated with Gigabit Transceivers GTs I O package pins that are potentially noise sensitive e I O standard violations e Ensuring e I O standards are not used in banks that do not support them e Banks do not have incompatible VCC ports assigned e Banks that need VREF ports have free VREF pins e Proper assignment of global clocks and regional clocks only with an imported EDIF NGC netlist and UCF
626. y bftLib get files of_objects sources_1 C PlanAhead_Install planAhead testcases PlanAhead_ import_files force norecurse X iii amp a ba INFO Designutils 348 Importing the appropriate files for fileset sources_1 INFO Designutils 348 Importing the appropriate files for fileset sim 1 _import files fileset constrs_1 force norecurse C PlanAhead_Install planAhead testcases PlanAhead_ Tutorial sou _set_property target_constrs file PlanAhead_Install planAhead testcases PlanAhead_Tutorial Tutorial Created _Dati lt is E le Messages E Compilation 5 Package Pins Design Runs Figure 4 11 Tcl Console In the Tel Console view you can PlanAhead User Guide www xilinx com 99 UG632 v13 4 January 18 2012 100 Chapter 4 Using the Viewing Environment XILINX e Expand or collapse the messages reported by each Tcl command in the Tcl Console view by toggling the tree widgets or by clicking the Expand all or Collapse all icons on the sidebar menu e Filter the displayed messages using the Show Find icon e Use Copy to cut and paste commands within the Tcl Console e Use Clear all output or Clear All Output popup menu command to clear the Tcl console report Locating Warnings and Errors in the Tcl Console Warnings or Errors show with a yellow or red indicators on the right side of the Tcl Console as shown in the figure a e Hold the mouse over one of the yellow or red ind
627. ysical package pins to define the device pin configuration CSV is a standard file format used by FPGA and board designers to exchange information about device pins and pinout You can also export a CSV file from an RTL Design a Netlist Design or an Implemented Design by using the File gt Export gt Export I O Ports command The CSV columns are I O Bank The I O Bank in which the pin is located The software fills in this field for all pins in the device Values are a number or blank This is not required in the input CSV file Pin Number The name or location of the package pin The software writes this out for all pins in the device This is not required in the input file If used for input it is used to define placement Values are legal pins in the device www xilinx com PlanAhead User Guide UG632 v13 4 January 18 2012 XILINX PlanAhead User Guide I O Port Lists CSV File Format IOB Alias An alternate part name for the package pin This field is specified by the software and is unused if specified in the input CSV file Site Type The pin name from the device data sheet This field is specified by the software and is unused if specified in the input CSV file Min Max Trace Delay ps The distance between the pad site of the die and the ball on the package in picoseconds This is specified by the tool to help the board engineer match trace delays The Trace Delay fields are in the output f

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