Home

TMS320C3x GENERAL-PURPOSE APPLICATIONS USER'S GUIDE

1. Logical address A23 Memory Bank 1 Ag Physical address 20000h Oh 9 0 OW W O 1 27FFFh 7FFFh Y Y 40000h Oh 0 o i oo OW H p 4FFFFh 7FFFh 80000h g g gt p Joya Oh o ojo fort p 9FFFFh 32 bits wide 7FFFh 32 bits wide Memory Bank 2 40000h Oh gt p 70 0 TO ri 43FFFh 7FFFh 80000h Oh oip To BU 119 p 87FFFh 7FFFh 100000h Y Y h 0 1 0 T H p 10FFFFh 32 bits wide ZPPER 16 bits wide Memory Bank 3 Oh 60000h FS CHEN RENNES gt 61FFFh 7FFFh C0000h Oh gt E B C3FFFh 180000h 0 L HBETI Oh leto Lis p 187FFFh ie 32 bits wide A23
2. TN 32 8 Data A14 A14 Data t A14 Data A14 Data A13 A13 A13 13 e zp c e Je gt e e o e o e o TMS320C32 e e 5 Ue 5 tje 5 A2 A2 0 A2 DA2 Al A1 Tt A1 Al AO AO cs A0 cs 1 A0 cs STRBO_B3 A 1 STRBO B2 A 2 STRBO B1 STRBO BO T 16 bit data bus Memory bank 32 bits wide 16 bye Data A14 A14 Data A13 A13 e e e e E TMS320C32 e e D A2 A2 A1 A1 AO AO Gs O dani Memory bank 16 bits wide STRBO B3 A 1 STRBO B2 A 2 STRBO B1 STRBO BO 8 bit data bus be Data A14 A13 o TMS320C32 e A2 A1 AO STRBO B3 A 1 STRBO B2 A 2 STRBO B1 STRBO BO
3. E gt TMS320C32 9 On chip DSP Po EMU emulation 00 i scan chain oo MPSD emulation CRU connector Emulati bl The CPU executes the C Boot mu a daad code to copy initialized variables from cinit to bss spaces The emulator uses CPU write cycles to load the initialized data The emulator uses directly into SRAM2 CPU write cycles to load the aaa c intOO isthe execution code into SRAM1 entry point file out SRAM1 SRAM2 C boot C boot File1 text section text section data boot asm boot asm bss section LL a E File1 File1 L File2 text section gt text section data b bss section File2 gt File2 E text section text section The debugger s loader program I uses the on chip emulation logic I File1 to load the out file to the target E cinit section The program data is transferred over the emulation cablefromthe meaa bs PC to the target system File2 Es cinit section COFF format 32 bits wide 32 bits wide binary file uauiuoJIAUu3 2 e ui uiejs
4. The C3x quickly executes FFT lengths up to 1024 points complex or 2048 real covering most applications It performs this task almost entirely in on chip memory See Table 6 2 on page 6 79 for the number of CPU clock cycles and the execution time required for FFT lengths between 64 and1024 points for the four algorithms DSP Algorithms 6 77 TMS320C3x Benchmarks 6 7 TMS320C3x Benchmarks Table 6 1 provides benchmarks for common DSP operations Table 6 2 sum marizes the FFT execution time required for FFT lengths between 64 and 1024 points for the algorithms in Example 6 13 Example 6 15 Example 6 16 and Example 6 17 beginning on page 6 31 The benchmarks are given in clock cycles the H1 internal processor cycle To get the benchmark time multiply the number of cycles by the processor s internal clock period For example for a 60 MHz C3x multiply by 33 ns Table 6 1 TMS320C3x Application Benchmarks 6 78 Application Inverse of a floating point number 32 bit precision Square root Double precision integer add subtract Double precision integer multiply IEEE to C3x format conversion fast IEEE to C3x form
5. 9pIM shq8 INOHd3 19 8 ue epoo 10sseooJd em OSV 1soH jyeuuo xeu lelul J041u02 Ionuoo ei eulq 9pIM SYA ZE Japeolio0g Jepeopnoog yewo 4402 elep elep uollo9s liulo eel cells cell eje bid ij 1009 HUI Uollo9s UID Helld balla 100q 1xel jad SuoloeS X UTOR lonuoo Japeolloog Jepeolloog9 i Spo Jewweiboid Uolges xe opoo z l I WOHd3 p z l z l d coils Uoloes 1xer gt opoo ES opoo E Hell bells Lell ESI NA use4ooq E EA 090 S Bm uise 1009 apoo use1009 Wse 100q uonoes 1xer Jooq 9 apoo apoo jooq 5 1000 9 HNVHS EID ino epy ulod Aqua ec ede uonnooxe PS Ed INVHS ol way edlsl00luro WOHd3 Iden peo ol Mou ureJ6oJd iepeol epeo 1ooq diuo uo y lonnsul Jooq eui 40 sSuononi su oj suonoes esoui ol splom 13S3H Jojuoo jeieds snld elep jonuoo eiixe sppe pue pejooq jo uonisuen ubiu orwo Duunp uid pezyeniu sepoodo wei6oid aq ol suogoes y seynuepi 7 XLNI 8U0 uo Mo pue dW 182IN UO UBiu Jo sisisuoo slqel 100q eui ui pueisJepun ueo Ag pala661 si uonroaxe Jepeol zoog 991 ep NOHd3 19 8 94 sung JeuuwueJ6oid NOHd3 ue ey v Jeuur4Dold WOHd3 uL yoye uq 8 uod jejereg OI OS V EWO plepuels e 0 i l
6. DMA INITIALIZATION LDI DMA ARO POINT TO DMA GLOBAL CONTROL REGISTER LDI SPORT AR1 LDI RESET RO STI RO AR1 4 RESET SPORT TIMER STI RO ARO RESET DMA STI RO AR1 RESET SPOR LDI SOURCE RO INITIALIZE DMA SOURCE ADDRESS REGISTER STI RO ARO 4 LDI DESTIN RO INITIALIZE DMA DESTINATION ADDRESS REGISTER STI RO ARO 6 LDI COUNT RO INITIALIZE DMA TRANSFER COUNTER REGISTER STI RO ARO 8 OR IEVAL IE ENABLE INTERRUPT FROM DMA TO CPU OR 2000H ST ENABLE CPU INTERRUPTS GLOBALLY LDI CONTROL RO INITIALIZE DMA GLOBAL CONTROL REGISTER STI RO ARO START DMA TRANSFER SERIAL PORT INITIALIZATION LDI SXCTRL RO SERIAL PORT TX CONTROL REG INITIALIZATION STI RO AR1 2 LDI STPERIOD RO SERIAL POR IMER PERIOD INITIALIZATION STI RO AR1 6 LDI STCTRL RO SERIAL POR IMER CONTROL REG INITIALIZATION STI RO AR1 4 LDI SGCCTRL RO SERIAL PORT GLOBAL CONTROL REG INITIALIZATION STI RO AR1 CPU WRIT THE FIRST WORD TRIGGERING EVENT XINT IS GENERATED LDI G SOURCE ARO LDI ARO 1 R0 STI RO AR1 8 BU END Other examples of DMA initialization include
7. TITLE COMPLEX RADIX 2 DIF FFT bad GENERIC PROGRAM FOR LOOPEDICODE RADIXt2 FFT COMPUTATION IN TMS320C3x THE PROGRAM IS TAKEN FROM THE BURRUS AND PARKS BOOK P 111 THE COMPLEX DATA RESIDE IN INTERNAL MEMORY THE COMPUTATION IS DONE IN PLACE BUT THE RESULT IS MOVED TO ANOTHER MEMORY SECTION TO DEMONSTRATE THE BITHREVERSED ADDRESSING THE TWIDDLE FACTORS ARE SUPPLIED IN A TABLE THAT IS PUT IN A DATA SECTION THIS DATA IS INCLUDED IN A SEPARATE FILE O PRESERVE THE GENERIC NATURE OF THE PROGRAM FOR THE SAME PURPOSE THE SIZE OE THE FFTN AND LOG2 N ARE DEFINED IN A GLOBL DIRECTIVE AND SPECIFIED DURING LINKING globl FFT Entry point for execution globl N P FFT size globl M LOG2 N globl SINE Address of sine table INP usect IN 1024 Memory with input data BSS OUTP 1024 Memory with output data text INITIALIZE FFTSIZ word N LOGFFT word M SINTAB word SINE INPUT word INP OUTPUT word OUTP FFT LDP FFTSIZ Command to load data page pointer LDI FFTSIZ IR1 LSH 2 IR1 IRL N 4 pointer for SIN COS table LDI 0 AR6 AR6 holds the current stage number LDI FFTSIZ IRO LSH 1 IRO gt TRO 2 N1 because of real imag LDI QFF
8. REGISTERS USED RO R1 R2 R3 R4 R5 R6 R7 ARO AR1 AR2 AR3 ARA AR5 AR6 ART IRO IRL RC RS RE DP MEMORY REQUIREMENTS Program 322 words approximately Data 7 words Stack 12 words BENCHMARKS Assumptions Program in RAMO Reserved data in RAMO Stack on primary expansion bus RAM Sine cosine tables in RAMO 2i Processing and data destination in RAM1 Primary expansion bus RAM 0 wait state ei FFT Size Bit Reversing Data Source Cycles C30 st 1024 OFF RAM1 25892 approx i Note This number does not include the C callable overheads Add 57 cycles for these overheads FP Set AR3 global ifft ri Entr
9. reversing is performed if enabled mor processor intensive 2 FFT_SIZE must be gt 64 this is not checked SYNOPSIS int ifft_rl FFT SIZE LOG SIZE SOURCE ADDR DEST ADDR SINE TABLE BIT REVERSE int FFT SIZE 64 128 256 512 1024 int LOG SIZE 6 Vy 8 9 10 float SOURCE ADDR Points to where data is originated and operated on float DEST_ADDR Points to where data will be stored float SINE_TABLE Points to the SIN COS table int BIT_REVERSE 0 bit reversing is disabled lt gt 0 bit reversing is enabled NOTE 1 If SOURCE ADDR DEST ADDR then in place bit DSP Algorithms 6 61 Fast Fourier Transforms FFTs Example 6 17 Real Inverse Radix 2 FFT Continued c ESCRIPTION Generic function to do an inverse radix 2 FFT computation on the C30 The data array is FFT SIZE long with real and imaginary points R and I as follows SOURCE ADDR 0 gt R FFT_SIZE 2 I _SIZE 2 1 I 2 SOURCE ADDR FFT SIZE 1 gt I 1 The output data array will contain only real values Bit reversal is optionally implemented at the end of the function The sine cosine table for the twiddle factors is expected to be supplied in the following format
10. STF R7 AR1 IRO X I1 R3tR5 ADDF R3 RZ2 R5 i R5 R2 R3 SUBF R2 R3 R2 R2 tR2 R3 SUBF R1 R4 R3 R3 R4tR1 ADDF R1 R4 R4 R44 R1 SUBF R5 R3 R1 Rl R3tR5 PYF ARA R1 F R1 R1 CO21 ADDF R5 R3 R3 R3 R5 PYF AR4 R3 H R3 R3 CO21 STF R1 AR2 Y I2 R3tR5 CO21 SUBF R4 R2 R1 R1 R2tRA PYF ARA R1 H R1 R1 CO21 STF R3 AR2 IRO X I2 R3 R5 CO21 ADDF R4 R2 R2 R2 R4 PYF AR4 R2 E R2 R2 CO21 BLK3 STF R1 AR3 Y I3 R44R2 CO21 STF R2 AR3 IRO X I3 R4 R2 CO21 CMPI LPCNT RO BPD INLOP E Loop back to the inner loop CONT LDI RPTCNT AR7 LDI IEINDX AR6 LSH 2 AR7 Increment repeat counter for next time STI AR7 RPTCNT LSH 2 AR6 IE 4 IF STI AR6 QIEINDX LDI RO IRO Nl N2 LSH 3 R0 ADDI 2 R0 STI RO JT JT N2 2 2 SUBI 2 R0 LSH 1 R0 f N2 N2 4 BR LOOP Next FFT stage A STORE RESULT USING BITXREVERSED ADDRESSING END DI FFTSIZ RC RC N SUBI 1 RC RC should be one less than desired 4 LDI FFTSIZ IRO j IRO size of FFT N LDI 2 IR1 LDI INPUT ARO LDP STORE LDI STORE AR1 RPTB BITRV LDF ARO 1 RO LDF ARO IRO B R1 BITRV STF RO AR1 1 STF R1 AR1 IR1 SELF BR SELF Branch to itself at the end end DSP Algorithms 6 41 Fast Fourier Transforms FFTs
11. f typedef volatile int VI typedef volatile float VF typedef VF volatile VPVF typedef VI volatile VPVI BK KK HK kk Ck kk Ck kk kk kk kk kk kk kk kk kk kk kk kk kk kk kk kk ke kk kk kc ke kc ke kc kc kc k kc k kc k kc kk kk ke ke ke ke e ek A FUNCTION PROTOTYPES RK IK IK IK kk kk kk kk kk I kk kk kk kk kkk kk kkk kkk ko kk kk I kc kc kc ko kc ko kc ko kc ko ko kkk kkk kk ke ke ke ke e e kx f void c int99 void void heap overflow void void init c30 void void error in real time void BK KK HK IKK kk kk kk kk kk kk kk kk kk kk kk kk ck kk Ck kk kk kk kk kk kk ke kc ke kc ke kc ke kk kc ke kc ke ke ke kk e ke e ke e e k f MACROS d BK AK HK kk kk ke kk kk ko kk kk kk kk ke kk kk Ck kk kk kk kk kk ke kk kk kc kk ke kc ko kk kc ko kc kc k kc k kc k kk kk ke ke e ke e eG k define BLOCK SIZE 64 BUFFER SIZE define GEN OSC OFF GENERATE OSCILLATOR define GEN CC O GENERATE CONVERT COMMAND define SER NU SERIAL PORT ONE define OSC TIMER NUM TIMER ZERO define CC TIMER NUM TIMER ONE define XF NUM 1 define ERROR CHECK ON define WAIT BUFFERS while buffer rcvd buffer xmtd define RESET FLAGS buffer rcvd
12. commdrvr c staff 01 15 92 C Texas Instruments Inc 1992 Refer to the file license txt included with this this package for usage and license information OKCKCKCKCkCKCkCKCkCKCkCkCkCkCk kCkCkCkCkCkCkCk kCkCkCkCk Ck kCkCk Ck kCk kc k kk k ck k ck ck ckckckck ckok ee i COMMDRVR C xy TMS320C3x COMMOM DRIVER ROUTINES TMS320C3x CODE Compile and archive into aic lib C 1991 TEXAS INSTRUMENTS HOUSTON include lt commdrvr h gt
13. UPON ENTERING THE ROUTINE AR1 POINTS TO THE FOLLOWING TABLE P FF Xo Ro F FH OxFF800000 lt ARL OxFF000000 0x7F000000 0x80000000 0x81000000 0x7F800000 0x00400000 0x007FFFFF Ox7F7FFFFF co 10101 Q0 PO E25 CO X 0X 0X F X X HF X ARGUMENT ASSIGNMENTS ARGUMENT FUNCTION RO NUMBER TO BE CONVERTED AR1 POINTER TO TABLE WITH CONSTANTS F xo x d GISTERS USED AS INPUT RO AR1 EGISTERS MODIFIED RO R1 EGISTER CONTAINING RESULT RO d x d OTE SINCE THE STACK POINTER SP IS USED MAKE SURE TO INITIALIZE IT IN THE CALLING PROGRAM CYCLES 23 WORST CASE WORDS 34 F F HF X global FMIEEEI FMIEEEL LDI RO R1 AND AR1 5 R1 BZ UNNORM H If e 0 number is either 0 or H denormalized XOR AR1 5 R1 BNZ NORMAL gt If e lt 255 use regular routine 3 24 IEEE TMS320C3x Floating Point Format Conversion Example 3 12 IEEE to TMS320C3x Conversion Complete Version Continued HANDLE NaN AND INFINITY TSTB AR1 7 RO RETSNZ Return if NaN LDI RO RO LDFGT AR1 8 RO If positive infinity mo
14. Fr Perform first and second FFT loops _ RAR1 gt I1 0 X I1 X I2 I X I3 X I4 d AR2 I2 1 X I1 X I2 Fr AR3 gt I3 2 x 11 X I2 IX I3 X I4 ARA gt 14 3 X I3 X 14 ARI 4 v START LDI DEST_ADDR AR1 LDI AR1 AR2 LDI AR1 AR3 LDI AR1 AR4 ADDI 1 AR2 ADDI 2 AR3 ADDI 3 ARA LDI 4 IRO LDI QFFT SIZE RC LSH 2 RC SUBI 2 RC LDF AR2 RO RO X I2 LDF AR3 R1 Rl X I3 ADDF3 R1 AR4 R4 RA X I3 X 14 SUBF3 R1 AR4 IRO R5 RS X I3 X I4 SUBF3 RO AR1 R6 R6 X I1 X I2 ADDF3 RO AR1 IRO R7 R7 X I1 X I2 ADDF3 R7 R4 R2 R2 R7 RA SUBF 3 R4 R7 R3 R3 R7 R4 RPTB LOOP1 2 i LDF AR2 IRO RO i LDF AR3 IRO R1 ADDF3 R1 AR4 R4 STF R3 AR3 IRO X I3 4 SUBF3 R1 ARA IRO R5 STF R5 AR4 IRO X 14 SUBF3 RO AR1 R6 STF R6 AR24 IRO X I2 lt 4 ADDF3 R0 AR1 IR0 R7 STF R2 AR1 IRO X I1 lt 4 ADDF3 R7 R4 R2 LOOP1_2 SUBF3 R4 R7 R3 STF R3 AR3 STF R5 AR4 IRO STF R6 AR2 STF R2 AR1 IRO DSP Algorithms 6 49 Fast Fourier Transforms FFTs Example 6 16 Real Forward Radix 2 FFT Continued Perform third FFT loop Part A AR1 AR2 AR3 AR1 LOOP3_A I1 I2 I3 I4 DI DI
15. Note Cl Memory bank 8 bits wide The boottable memory used by the on chip boot loader should be connected to the C32 with no address shift regardless of the width of the memory bank 4 100 Booting a TMS320C32 Target System in a C Environment Figure 4 43 Boot Table Memory Configuration 32 bit data bus W 22 bye bo D Data A14 1 tC A14 Data Tl A14 Data LH A14 Data A13 D C A13 T A13 lJ A13 e oe gt p g e gt b o o o e o Qe o TMS320032 e e 5 ue 5 e 5 A2 tL A2 A2 A2 A1 1 0D Al A1 r1 AO _J AO cs T A0 cs T A0 csp
16. DSP102 202 TRANSFER TWO SIXTEEN BIT WORDS REPRESENTING BOTH CHANNELS IN ONE THIRTYTWO BIT WORD EXTRACT INTO a A THE INPUT_XFER BUFFERS temp intval SERIAL PORT ADDR SER NUM r data input xferO r index temp bitval chan0 input xferl r index temp bitval chanl WRITE OUTPUT XFER BUFFER VALUE BY CASCADING BOTH CHANNELS temp bitval chanO0 output xferO t index temp bitval chanl output xferl t index SERIAL PORT ADDR SER NUM x data temp intval CHECK IF BUFFERS ARE FULL if r index r buffer CHECK CPU SYNCHRONIZATION FLAG if ERROR CHECK if buffer rcvd TRUE error in real time if buffer rcvd TRUE for fendif swap input0 inputO0 input xfer0 input xferO0 swap swap inputl inputl input_xferl input_xferl swap r index 0 buffer rcvd TRUE if t_index t buffer CHECK CPU SYNCHRONIZATION FLAG if ERROR CHECK if buffer xmtd TRUE error in real time if buffer xmtd TRUE for fendif swap output0 output0 output xfer0 output xferO0 swap swap outputl outputl output_xferl output_xferl swap t_index 0 buffer_xmtd TRUE Analog Interface Peripherals and Applications 8 15 Burr Brown DSP101 2 and DSP201 2 Interface to TMS320C3x E
17. LDI 0 RO STI RO QG first half C int asm POP ARO POPF RO POP RO POP ST RETI Analog Interface Peripherals and Applications 8 43 CS4215 Interface to the TMS320C3x Example 8 12 General h KK IK IK kk kk kk kk kk kk I kk kk kk kk kk I kk kk kk I kk I kc kk I I I ko ko ko ko ke ko k koe ko ke koe ke ke ke ke e e kx general h v4 2 if Copyright c 1991 Texas Instruments Incorporated s RK KK HK kk kk kk kk kk kk kk kk ke kk kk kk kk kk kk kk Ck ke kk kk kk kk ke ke kc ke kc ke kc ke ck ke kc ke kc ke kc ko kk kk ke ke ke ke e e e e k A ifndef _GENERAL define _GENERAL BK KK HK kk ck kk kk kk ko kk kk kk kk kk kk kk kk I kk kk ke kk kk I kk ko kc I I ke kk kk ke ke ke ke ke e e x f COMMON MACRO DEFINTIONS KK IK IK I kk kk kk kk kk kk kk kk kk kk kk kk kk kk kk I kk I I kc kc kc ko kc I I I I I I I I ke e ke x f ifndef OFF define OFF 0x00 endif ifndef ON define ON 0x01 endif ifndef FALSI define FALSI endif G nj 0x00 ifndef TRU define TRUI endif AE 0x01 ifndef CLEAR define CLEAR 0x00 endif ifndef S define S endif AE 0x01 8 44 CS4215 Interface to the TMS320C3x Example 8 12 General h Continued BRK KK KK CK KK KCk kCk kCk kCK KCK kCK KCK kCK KCK KCKCKCKCKCK KCK KCK KCKCKCK KCK KCK KCK Ck k k ck k ck ck ck ck ckckckck ck ks
18. BZ read sO wait for receive buffer full AND OFDFh IF reset interrupt flag LDI AR7 4Ch R1 read data gt GR RETSU read mc LDI 3 R3 data size 32 3 R3 read mb LDI 1 BK 00000001 ex mem width 8 LSH R5 BK 00000100 SUBI 1 BK 000000FF mask gt BK LDI R3 AR6 0 1 000 EXPAND ADDI 1 AR6 F I 10 000 DATA gt AR6 LSH 3 AR6 11 100 000 SIZE LDI R5 RO loop3 CMP I 1 R0 BEQ exitl DATA SIZE LSH 1 R0 br eR E mol gt AR6 LSH 1 AR6 MEM WIDTH BU loop3 exitl SUBI 1 AR6 LDI 0 RO init shift value LDI O R1 init accumulator loopl ADDI 3 SP 808027h gt SP CALLU read_m read memory once gt R6 SUBI 3 SP 808024h gt SP AND3 R6 BK R7 apply mask LSH RO R7 shift OR R7 R1 accumulate ec RL ADDI R5 RO increment shift value DBU AR6 loop1 P decrement of chunks gt AR6 RETSU Perform a single memory read from the source boot table Handshake enabled if IOXFO bit of IOF reg is set disabled when reset IACK will pulse continuously if handshake enabled and data not ready to achieve zero glue interface when connecting to a C40 comm port read m TSTB 2 IOF handshake mod nabled STI R2 AR2 Set road strobe hh iret BNZ loop5 yes jump over LDI AR3 R6 no just read memory amp return RETSU B 12 C40 loop5 loop6 IACK TSTB BNZ LDI LDI TST
19. Data A14 A13 TMS320C32 A12 e e e A1 AO A 1 STRBO B2 STRBO B1 STRBO BO N A14 A138 STRBO B1 m E l o N EE 4 STRBO BO b8 b7 e e e e e b65530 b65529 b65532 b65531 b65534 b65533 b65535 Oh 1h 2h 3h 7FFCh 7FFDh 7FFEh 7FFFh Memory address space Physical address shift 1 bit Notes 1 The amount of shift between logical and physical addresses depends only on the size of data being transferred connection between the C32 and the external memory depends only on the width of the memory bank 2 The amount of shift in the physical uoge sueJ sseJppy pue eoejie u AIOWAyy cra Figure D 9 Address Translation for 32 Bit Data Stored in 8 Bit Wide Memory CPU instruction STI RO 1FFFh DP 90h Memory map Boi 5 STRB0 wi 900000h w2 900001h w3 900002h i w4 900003h uis 8 o i w8189 901FFCh w8190 901FFDh ek w8191 901FFEh STRET KOCH Logical address shift 0 bits 32 bit data size Notes 1 The amount of shift between logical and physical addresses d
20. else Second half of transmission SERIAL PORT ADDR SER NUM r data SERIAL PORT ADDR SER NUM x data data control intval 1 first half TRUE endif C ISR f xy INIT ARRAYS INITIALIZE DATA ARRAY PARAMETERS f gt void init arrays int buffer size int i Es INITIALIZE AND ZERO FILL ARRAYS A as if inputO float calloc buffer_size sizeof float heap_overflow if outputO float calloc buffer_size sizeof float heap_overflow if input xfer0 float calloc buffer_size sizeof float heap_overflow if output xfer0 float calloc buffer_size sizeof float heap_overflow if inputl float calloc buffer size sizeof float heap_overflow if outputl float calloc buffer_size sizeof float heap_overflow if input_xferl float calloc buffer_size sizeof float heap_overflow if output xferl float calloc buffer_size sizeof float heap_overflow for i 0 i lt buffer size i outputO i output xferO i 0 0 outputl i output xferl i 0 0 Analog Interface Peripherals and Applications 8 61 CS4215 Interface to the TMS320C3x Example 8 16 CS4215 c Continued void init 4215 int crystal VI i j dummy
21. 16 bit data tds a aa Q Q 32 bit wide data bus 16 bit memory 32 bit program TMS320C32 8 bit data 8 bit data i He 16 bit wide data bus 8 bit memory TMS320C32 16 bit data a Hle 8 bit wide data bus NOTE 8 bit programs are not supported Memory Interface and Address Translation Figure D 2 Data and Program Packing Program and Two Different Data Sizes 32 bit memory 8 bit data 8 bit data 8 bit data 8 bit data TMS320C32 32 bit program 16 bit data 16 bit data amp 0 OG g 32 bit wide data bus 16 bit memory 16 bit or 32 bit data
22. TMS320C32 32 bit program 8 bit data 8 bit data ls Heo N 16 bit wide data bus 8 bit memory 8 bit data TMS320C32 16 bit data Q 8 bit wide data bus NOTE 8 bit programs are not supported Memory Interface and Address Translation D 3 Memory Interface and Address Translation Since there are two strobes that support flexible memory STRBO and STRB1 they each can be programmed for a different data size using the re spective strobe control registers By setting the strobe configuration bit in one control register both STRBO and STRB1 strobes can be mapped to STRBO control signals This creates a section of physical memory that is mapped into the same address range as another section of memory with a hardware switch to determine which range is active In this overlay mode data accesses to and from the STRBO and STRB1 portions of the memory map drive the STRBO sig nals to control a single memory bank The access to the program and to two different data sizes from a single memory bank with no additional logic devices is a powerful C32 feature that minimizes system cost
23. C3x RESET 5V 74ALS34 R4 100 kQ TAN e o Cy 4 7 pF S l O Processor Initialization 1 3 How to Initialize the Processor 1 3 How to Initialize the Processor 1 3 1 After reset the C3x jumps to the address stored in the reset vector location and starts execution from that point The reset vector normally contains the ad dress of the system initialization routine The initialization routine typically performs several tasks Sets the data page pointer DP register Sets the stack pointer Sets the interrupt vector table Sets the trap vector table Sets the external memory control register Clears enables cache O O O O O L Note When running under microcomputer mode MCBL MP 1 the on chip boot loader automatically initializes the external memory control register values from the bootloader table LLLl X The C3x can be initialized using assembly language or C Processor Initialization Under Assembly Language If you are running under an assembly only environment Example 1 1 on page 1 5 provides a basic initialization routine This example shows code for initializing the C3x to the following machine state All interrupts are enabled The overflow mode is disabled The program cache is enabled The DP register is initialized to 0 The memory mapped control registers are initialized
24. C_INT99 ERRONEOUS INTERRUPT SERVICE ROUTINE THIS ROUTINE IDLES AFTER RECEIVING AN UNEXPECTED INTERRUPT void c int99 void for KKK KK KK KK KK ECKCECK A AA AA AAA AAA A AIA ke ko ke ke ke oe e e x x f HEAP_OVERFLOW NOT ENOUGH MEMORY IN THE HEAP has THIS ROUTINE IS AN ERROR HANDLER FOR WHEN MEMORY a CANNOT BE ALLOCATED FROM THE HEAP void heap_overflow void for INIT_C30
25. SRAM2 File1 data bss section File2 data bss section 32 bits wide JueuiuoJ4Au3 2 e ul uiejs4s 196181 ZEJ0ZESWL e 6unoog Booting a TMS320C32 Target System in a C Environment 4 8 4 EPROM Boot Booting a DSP target board from C code stored in nonvolatile memory and ac cessible to the DSP can be done in two ways If the DSP is powered up in the microprocessor mode the reset causes the program to start execution from 32 or 16 bit EPROM by fetching the reset vector from memory address 000000h and branching to the reset interrupt service routine ISR pointed to by that vector On the other hand if the DSP is powered up in the microcomputer boot loader mode program execution starts with the on chip boot loader program The boot loader reads the COFF file from an 8 bit EPROM and expands it to the system SRAM from which it can be executed 16 or 32 bits wide In either case program entry occurs at the beginning of the boot asm library routine to initialize the C environment prior to execution of the C code 4 8 4 1 Microprocessor Mode Linker c Option Before the binary COFF file can be burned into an EPROM it must be con verted to an ASCII format that an EPROM programmer can recognize see Figure 4 40 on page 4 97 The hex conversion utility converts COFF files to a programmer object
26. TITLE FIR FILTER SUBROUTINE FIR EQUATION y n h 0 x n h 1 x nt1l h Nt1 x nt Nt1 TYPICAL CALLING SEQUENCE LOAD ARO LOAD ARI LOAD RC LOAD BK CALL FIR ARGUMEN ASSIGNMENTS ARGUMEN FUNCTION 2d ARO ADDRESS OF h N 1 ARI ADDRESS OF x n N 1 RC ENGTH OF FILTER 2 N 2 BK ENGTH OF FILTER N REGISTERS USED AS INPUT ARO AR1 RC BK REGISTERS MODIFIED RO R2 ARO AR1 RC REGISTER CONTAINING RESULT RO CYCLES 11 N 1 WORDS 6 global FIR A Initialize RO FIR MPYF3 ARO 1 AR1 1 RO h Nt1 x nt Nt1 gt RO LDF 0 0 R2 x Initialize R2 FILTER 1 lt i N 6 8 FIR IIR and Adaptive Filters Example 6 5 FIR Filter Continued RPTS RC 3 Set up the repeat cycle MPYF3 ARO 1 AR1 1 RO h Nflfi x nt Ntiti t RO ADDF3 RO R2 R2 Multiply and add operation ADDF RO R2 R0 Add last product RETURN SEQUENC RETS Return end end 6 2 2 IIR Filters The transfer function of the IIR filters has both poles and Os Its output depends on both the input and the past output As a rule the IIR filters need less com putation than an FIR with similar frequency response but the filters have the drawback of being sensitive to coefficient quantization Most often the IIR fil ters ar
27. D 10 Address Translation for 8 Bit Data Stored in 16 Bit Wide Memory D 11 Address Translation for 32 Bit Data Stored in 8 Bit Wide Memory D 12 Address Translation for 16 Bit Data Stored in 8 Bit Wide Memory D 13 Address Translation for 8 Bit Data Stored in 8 Bit Wide Memory D 14 cR Bank Switching Interface Timing for the TMS320C3x 33 i 4 20 STRBO and STRB1 Data Access Data Size Memory Width usus 4 25 STRBO and STRB1 Data Access Data Size zz Memory Width 4 27 Program Fetch From 16 Bit STRBO Memory i 4 29 Program Fetch From 32 Bit STRB1 Memory i 4 31 ROY Signal Generation cR caaieaku OC RUHTRER CR RR ARR 4 59 Data Sizes Supported by Sections Created by the C Compiler 4 69 TMS320C3x Application Benchmarks i 6 78 TMS320C3x FFT Timing Benchmarks Assumes Data On Chip and No Bit Reversing idco eret ese ev e Dele n edie i Lp d eda bad Reed 6 79 Key Timing Parameters for DAC Write Operation i 8 9 Primary Communications Mode Selection i 8 25 Control Register Bit Fields pp 8 26 Master Clock to Sample Rate Conversion pp 8 31 Comparison of Resonator Types pp 9 4 Oscillator Solutions by Frequency pp 9 22 12 Pin Header Signal Descriptions and Pin Numbers eee ee ee 10 2 Emulator Cable Pod Timing Parameters 9 10 4 TMS320C38x Digital Signal Processor Part Numbers 000 cec
28. Get the sign Divisor dividend If so return 0 DIFFERENCE IN EXPONENTS AS SHIFT COUNT FOR DIVISOR AND AS R EAT COUNT FOR SUBC Normalize dividend PUSH as float POP as int Get dividend exponent 3 8 Integer and Floating Point Division Example 3 5 Integer Division Continued FLOAT R1 TEMPE Normalize divisor PUSHE EMPE PUSH as float POP EMP POP as int SH 24 TEMP Get divisor exponent SUBI EMP COUNT Get difference in exponents LSH COUNT R1 Align divisor with dividend N DO COUNT 1 SUBTRACT amp SHIFTS RPTS SUBC COUNT R1 RO0 MASK OFF THE LOWER COUNT 1 BITS OF RO CHI SUBRI LSH NEGI LSH NEGI ASH LDINZ CMPI RETS ETURN O0 LDI end 31 COUNT COUNT RO COUNT COUNT RO Shift count is 32 COUNT 1 Shift left Shift right to get result ECK SIGN AND NEGAT ESULT IF NECESSARY RO R1 31 SIGN R1 RO 0 RO 0 RO Negate result Check sign If set use negative result Set status from result If the dividend is less than the divisor and you want fractional division you can perform a division after you determine the desired accuracy of the quotient in bits If the desired accuracy is k bits shift the dividend left by k positions Then apply the algorithm described above with i re
29. Buipusdeq on Yorum uo 1l9sey lasey ualsMS dwa 13S3d U9euM MO S XLNI lasad INOHd3a 1q 8 ue poo 10Sseooid 214 Ios v SOH euJol xeU 1elul lo4uoo Jonuoo Japeollo0g Jepeo oog elep Blep Zell cella elep ejep Loma SITE louoo loJluoo Jepeolloog9 Jepeolloog9 epoo Jeuuwei6oid 4 po 4 zeli epee WOHd3 p Zalld cel opoo opoo apoo bella Leia bells sesocan ee opoo Wse 009 use1009 1008 9 apoo 9poo 100g 9 1008 5 HAVHS Ionuoo loQuoo uod Aue Jepeonoog Japeo joog uonnoexe WOHd3 Laal y s 00u 9 N iepeo A ooq y JO Suorponjsul Jo uo suen ufiu oi Mo bug dd LILLLLLI Jo4uoo jep ds snd elep X NI euo uo Mo e pue dWAgON uo UBIY x pezyeniu sepoodo wei6od Aq pele66W si uonrioexe Jepeol 100g uod lallered 40 Sjsisuoo slqel 100q eui YIM eowep NOH d 10 8 eut sung Jeunuejboud WOHd3 eur uod noo ndo rues INVHS pod Jepeojooq N 19 c8oINOHd3l9 8 leuaS diuo uo N WO e qei 100g eui A Kdoo ol epoo sapeo dsa 100q diuouo eu c 90c SIA L sae Ndo eur etj Areuiq yewo JJOO UOnoes jul eel 100q juIo Uoloas HUI 1009 13xer suonoeg bella uonoes xer s calls uones 1xer bell wse 00
30. main or GIE ST Turn on INTS ldi 0x3 IE Enable XINT RINT call INIT b main Do it again r DAC2 push ST DAC Interrupt service routine push R3 SLE RAMPEN If RAMPEN 1 assemble this code ldi GRAMP R3 addi 256 R3 Add a value to RAMP sti R3 RAMP else Else assemble this ldi ADC_last R3 5 endif gt andn 3 R3 1 sti R3 SO_xdata Output the new DAC value pop R3 pop ST reti ADC2 push ST push R3 ldi 8S0 rdata R3 sti R3 QG0ADC last F pop R3 i pop ST i reti pOCKCKCKCKCk kk kk ke RK RRR KKK ko k RK KEK KKK KK kk koc kk ko ke kk ke ke koe ke ke ke e ke The startup stub is used during initialization only and can be safely overwritten by the stack or data 7 ER entry ST_STUB Debugger starts here INIT ldp TO ctrl Use kernel data page and stack ldi 0 RO Halt TIMO amp TIM sti RO TO_ctrl gt sti RO GTO count Set counts to 0 ldi 1 R0 Set periods to 1 sti RO GTO prd H ldi 0x2C1 RO0 Restart both timers in pulse mode sti RO GTO ctrl H tai 8S0 xctrl val RO sti RO SO_xctrl transmit control ldi 8S0 rctrl val R0 sti RO SO_retrl receive control idi 0 RO E sti RO SO_xdata DXR data value ldi QS0 gctrl val R0 Setup serial port sti RO SO_gctrl i global control 8 28 TLC32040 Interface to the TMS320C3x Example 8 6 Setting the TA and TB Registers Continued This section of code initialize
31. SINE TABLE 0 P sin 0 2 pi FFT SIZE sin 1 2 pi FFT SIZE sin FFT SIZE 2 2 2 pi FFT SIZI SINE TABLE FFT SIZE 2 1 s P in FFT SIZE 2 1 2 pi FFT SIZE FH NOTE The table is the first half period of a sine wave Stack structure upon call FP 7 BIT REVERSE FP 6 SINE TABLE FP 5 DEST ADDR FP 4 SOURCE ADDR FP 3 LOG SIZE FP 2 FFT SIZE FP 1 returne FP 0 addr old FP OX 0X 0X 0X 0X 0X 0X FF F F FF F F 0X 0X HF 0X F 0X 0X 0X 0X F 0X 0X F OX 0X X F X X F X XO X X F F F Xo F KF FH Ck Ck ck ck Ck ck ck ck ck ck kk Ck Sk Ck Ck Sk ck Ck ck ck ck ck ck kk ck ck ck Ck ck ck KK ck ck Sk ck ck ck KK KKK KKK KKK KKK KKK ck kk ko kk kk KKK KKK KKK KK 6 62 Fast Fourier Transforms FFTs Example 6 17 Real Inverse Radix 2 FFT Continued NOTE Calling C program can be compiled using either large or small model WARNING DP initialized only once in the program Be wary with interrupt service routines Make sure interrupt service routines save the DP pointer WARNING The SOURCE_ADDR must be aligned such that the first LOG_SIZE bits are zero this is not checked by the program Se 4 3 He O5 Se
32. Bit I O External DMA interface Primary bus Interrupt interface External flags Expansion bus Timer interface Peripherals I O devices me This block diagram represents a fully expanded system In an actual design you System Serial Serial control ports ports Clock and TLC3204x reset AIC generators Bic analog I O TCM29C13 codec can use any subset of the illustrated configuration that is appropriate 4 2 External Interfaces External Interfaces The C3x interface type depends on the device to which it is to be connected Each interface comprises one or more signal lines that transfer information and control its operation Figure 4 2 shows the signal line groupings for each of these interfaces Figure 4 2 External Interfaces on the TMS320C3x TMS320C3x Data 22 p31 Do HOLD Address 24 A23 A0 HOLDA gt p External DMA interface Primary 4 bus t RW INT3 0 7 External interrupt Control STRB IACK interface gt RDY XF1 0 4 5 External flags 4 RESET Systomreset S Te lt lt 7 Timer interface tM X1 Master clock 1 p X2 CLKIN CLKXOHE a H1 DX0 Hd ystem Clock outputs FSX0 4 control H3 t Serial port 0 ROM enable MC MP CLKRO C30 only DRO F4 FSRO 4 Boot l
33. Analog Interface Peripherals and Applications 8 33 TLC320AD58 Interface to the TMS320C3x Example 8 7 Interfacing the 18 bit TLC320AD58 to TMS320C3x Continued asm ldi 1000h ST clear and enable cache asm ldi Oh IE clear all interrupt masks asm ldi 0h IF clear all pending interrupt init BONG Generate AD58 MCLK if required init_sl Initialize serial port 1 init_ad58 asm ldi ERINT1 CPU IE enable serial port 1 receive int asm or _GIEBIT ST global enable interrupts while 1 wait on interrupt yet Subroutine to initialize Serial Port 1 to communicate with TLC320AD58 7 fe x void init s1 void serial port l1 X PORT X1 MODE serial port 1 R PORT R1 MODE serial port 1 GLOBRL S1 CONFIG Subroutine to initialize Timer 0 to generate TLC320AD58 MCLK ay void init tO vord timer 0 GLOBAL TO HOLD timer 0 T_COUNTER 0X0 timer 0 T PERIOD TO PERIOD timer 0 GLOBAL TO HOLD Serial Port Receive Interrupt Service Routine uA void c int08 void reconfigure serial port to receive both channels within one frame sync if serial_port 1 GLOBAL amp Ox0C00 read LEFT channel and normalize within 1 0 1 0 1 channel float serial port 1 R DATA gt gt 14 4 0 65536 switch to burst
34. Write out control word twice with the dcb bit high temp control bitval dcb out temp r for i 0 i lt 2 i nw WwW SI ERIAL hile SERIAL PORT ADDR SI PORT ADDR SE I R NUM 1 gcontrol 0x0 ER NUM gcontrol bit xsrempty See note on XR for j 0 j 3 j SERIAL PORT ADDR dummy S n ERIAL_PO RT_ADDR See note on XR for j 0 j 3 j ET RRES ES SE I R NUM gcontrol XCLKSRCE XLEN RFSM RLEN 32 ET and three cycle delay in C3x U G 32 XINT Xf XFSM RINT FSXOUT RRESET XRESE ERIAL PORT ADDR SER NUM r data SER NUM x data out intval 0 DY and three cycle delay in C3x U G wW ERIAL hile SERIAL PORT ADDR SI PORT ADDR SER NUM while SERIAL PORT ADDR SI x data ER NUM gcontrol bit xrd out intval 1 ER NUM gcontrol bit rrdy ERIAL PORT ADDR S ERIAL PORT ADDR SI in intval 0 S See note on RR for j 0 j 3 j t ERIAL PORT ADDR SER NUM r data DY and three cycle delay in C3x U G while SERIAL PORT ADDR SER NUM gcontrol bit rrdy in intval 1 S ER NUM gcontrol ER NUM gcontrol ERIAL PORT ADDR SER NUM r data 0x0 XLEN 32 RRESET No ET 32
35. 10 5 10 5 Mechanical Dimensions for the 12 Pin Emulator Connector ssue 10 8 10 6 Diagnostic Applications 300 0 er i ete ee etai awa iii ede a ea AE Ea 10 10 Development Support and Part Ordering Information 11 1 Describes C3x support available from TI and third party vendors 11 1 Development Support en ren 11 2 11 1 1 Development Tools 0 a a e men 11 2 11 1 2 TMS320 Third Parties a0 re i teens 11 4 11 1 8 Technical Training Organization TTO TMS320 Workshop 11 5 11 1 4 TMS320 Literature eeoa n 11 5 11 1 5 DSP Hotline essen da aaier ere iren a Te o OM P i eae 11 5 11 1 6 Bulletin Board Service BBS i 11 6 11 2 TMS320C3x Part Ordering Information 0 11 7 11 2 1 Device and Development Support Tool Prefix Designators 11 9 11 2 2 Device SufflX68 Loscskolse RR x Rx e ERRARE ERR PR E RES PARE 11 10 TMS320C30 Power Dissipation sseeeeeeee n III 12 1 Explains the current consumption of the TMS320C30 under different operating conditions 12 1 Power Dissipation Characteristics es 12 2 12 1 1 Power Supply Factors sas Se ed ccc aee i na nee es 12 2 12 1 2 Power Supply Consumption Dependencies pp 12 2 12 1 3 Determining Algorithm Partitioning pp 12 4 12 1 4 Test Setup Description 0 12 4 12 2 Current Requirements for Internal Circuitry 0 0000 c eee eee 12 5 12 2 4 Quiescent Current 0 00 teen eens 12
36. 73 102 Clock Oscillator and Ceramic Resonators 9 11 Pierce Oscillator Circuit When a square wave output is desired such as for a microprocessor clock source the Pierce circuit sometimes is implemented in the manner shown in Figure 9 9 The crystal and load capacitances are in the same configuration as the circuit shown in Figure 9 8 with the exception that Ri is replaced with the output impedence of the inverter In the linear region the inverter behaves like a linear inverting amplifier The resistor R4 is introduced across the invert er to bias it into the linear region This is the transition region between the two digital states as shown in Figure 9 11 on page 9 14 Otherwise the inverter output moves toward one of its two stable digital states and oscillation does not start because there is no gain in these regions the output characteristic shown in Figure 9 11 on page 9 14 is flat Figure 9 9 Pierce Circuit for Square Wave Output gt o Ki V V a i a Output Rf NAVV e i1 Cy aR x The removal of R from the circuit improves the loop gain and thus improves the likelihood of oscillation However removing R also increases the drive lev el power dissipation on the crystal The power dissipation limit of the crystal must not be exceeded under these conditions power dissipation issues are discussed in section 9 4 4 on page 9 18 Otherwise the circuit operation is
37. BEEZ T t FFFh Memory address space Physical address shift 1 bit 16 bit memory width 1 The amount of shift between logical and physical addresses depends only on the size of data being transferred connection between the C32 and the external memory depends only on the width of the memory bank uoge sueJ sseJppy pue eoejie u AIOWAyy Figure D 7 Address Translation for 0r d 16 Bit Data Stored in 16 Bit Wide Memory Oh 1h 2h 3h 7FFCh 7FFDh 7FFEh 7FFFh T eo e a CPU instruction STI RO 7FFFh DP 88h o o a a STRB Memory Data EE STRBO config width size no n Memory mai Logical address control eee o eee y p 9 space register 0 0 4 4 STRBO EWI 880000h STRBO 16 bits 16 bits EN hw2 880001h hw2 mes BEBO Logical address 23 to 0 PES w w aalala 4 4 4 4 4 4 4 1 Sie ees PERET ORG msm NS e e UUDEDHEEOE ERE ccc hw32765 88FFFCh Physical address 23 to 2 hw32765 hw32766 88FFFDh hw32766 Memory address 14 to 0 STRBO h
38. SUBF3 R3 AR1 R1 R1 X Il X I3 34 LDF AR4 R2 STF RO AR1 IRO X I1 lt 4 MPYF 2 0 R2 R2 2 X 14 LDF AR2 R3 STF R1 AR3 IRO X 13 4 MPYF 2 0 R3 R3 2 X I2 LOOP3 A STF R3 AR2 IRO X I2 4 STE R2 AR4 IRO X I4 t 6 68 Example 6 17 Real Inverse Radix 2 FFT Continued Fast Fourier Transforms FFTs M Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Part B AR3 v v vy v y Il I2 13 I4 LDI LDIA LDIA LDIA ADDI ADDI ADDI ADDI LDI LDI LSH LDI SUBI WO OO oO i WNE c X I1 X I2 X I1 X I3 X I1 X I2 J COS X I3 X I4 SIN x 11 X I2 J SIN X I3 X I4 COS NOTE COS 2 pi 8 SIN 2 pi 8 SOURCE_ADDR AR1 R1 AR2 R1 AR3 R1 AR4 1 AR1 3 AR2 5 AR3 7 AR4 SINE_TABLE AR7 AR7 points at SIN COS table FFT_SIZE RC eS RC RC IR1 2 RC DSP Algorithms 6 69 Fast Fourier Transforms FFTs Example 6 17 Real Inverse Radix 2 FFT Continued LDF AR2 R6 R6 X I2 LDF AR3 RO RO X I3 ADDF3 R6 AR1 R5 R5 X I1 4X I2 SUBF3 R6 AR1 R4 R4 X I1 X I12 SUBF3 RO R4 R3 R3 X I1 X I2 X I3 ADDF3
39. i 0 X I1 dl 2 3 4 5 6 7 8 X I1 9 10 11 12 X I4 13 14 15 16 17 DEST_ADDR AR1 AR1 AR2 R1 AR 8 AR2 12 AR 16 IR QFFT 4 RC 2 RC AR2 AR2 AR3 LOOP 4_ AR2 R2 A RO A R1 A RO A R3 A AR3 R2 A R1 A R3 A 3 3 0 SIZI E Q AR1 R1 AR1 R2 R3 A IRO RO R1 IRO R1 R1 R2 IRO R1 R2 R3 IRO R3 R1 R2 R3 X I3 X 13 RO X I3 Rl XI1 X I13 7 R2 X I1 X 13 J R3 X I4 X I1 X I3 4 DSP Algorithms 6 53 Fast Fourier Transforms FFTs Example 6 16 Real Forward Radix 2 FFT Continued Part B ARO AR1 AR2 AR4 AR3 ARO Il 3rd I1 2nd TI 1st I2 1st I2 2nd I2 3rd L3 3rd I3 2nd I3 1st I4 1st I4 2nd I4 3rd DI SH DI DI UBI DI DI DI DI DI DDI DDI DDI DDI DDI DI DF Pe PprPrPrrPrrPretrPMNrPeee p DI DF p Ce gie e J1O0 01 4 QC Pon c YHA OPWBNEF CO A X B2 X I3 COS X I3 COS X I3 COS X I3 SIN QFFT SIZE RC 4 RC RC IR1 2 IR 3 RC 0 DEST_ADDR ARO ARO AR1 ARO AR2 ARO AR3 ARO ARA 1 AR 7 AR 0 i 9 AR2 15 A 11 A R3 R4 SINE
40. Analog Interface Peripherals and Applications 8 13 Burr Brown DSP101 2 and DSP201 2 Interface to TMS320C3x Example 8 2 TMS320C3x BB DSP102 202 Driver J KOKCKCECK Ck Ck Ck Ck Ck Ck IA Kk Ck Ck Kk Ck Ck Ck Ck Ck kk kk kk kk kk kk kc ko ke ko ke ke ke ke ke ke ke ee eoe ee ee e e kx x f J BBDRVR C TMS320C3x BB DSP102 202 DRIVER f include math h include lt stdlib h gt include lt bb h gt KK KK Ck kk A A A Ek Ck Ck kk kk kk kk ke ko ke ke ke ke ke ke ke e ke ke e e e x x f GLOABL VARS oy 8K KK kk a kk a Ck A A Ek kk Ck kk kk kk kk ke ke ke ko ke ke ke ke ke eoe e e e e kx x f int t buffer BLOCK SIZE OUTPUT BUFFER SIZE int r buffer BLOCK SIZE INPUT BUFFER SIZE VPVF output0 OUTPUT DATA BUFFER FOR PROCESSOR EJ VPVF input0 INPUT DATA BUFFER FOR PROCESSOR VPVF output xfer0 OUTPUT DATA BUFFER FOR ISR BB y VPVF input xfer0 INPUT DATA BUFFER FOR ISR BB VPVF outputl OUTPUT DATA BUFFER FOR PROCESSOR VPVF input
41. 4 26 STRBO and STRB1 Data Access Data Size zz Memory Width 4 28 Program Fetch From 16 Bit STRBO Memory i 4 30 Program Fetch From 32 Bit STRB1 Memory i 4 32 Description of Terms Involved In TMS320C32 Memory Interface 4 34 32 Bit Memory Configuration STRBO and IOSTRB i 4 36 32 Bit Memory Configuration STRBO and IOSTRB i 4 37 32 Bit Memory Configuration STRBO and STRB1 i 4 39 32 Bit Memory Address Translation Data Size lt Memory Width 4 40 16 Bit and 8 Bit Memory Configuration A Complete Minimum Design 4 42 16 Bit and 8 Bit Memory Address Translation Data Size Memory Width 4 44 16 Bit and 8 Bit Memory Address Translation Data Size gt Memory Width 4 46 16 Bit and 8 Bit Memory Address Translation Data Size Memory Width 4 48 One Bank Two Strobes Memory Configuration Memory Width 32 Bits 4 50 One Bank Two Strobes Address Translation Data Size 16 and 8 Bits 4 52 One Bank Two Strobes Address Translation Data Size 32 and 8 Bits 4 54 One Bank Two Strobes Address Translation Data Size 16 and 32 Bits 4 56 RDY Signal Timing for STRBO and STRB1 Cycles cece cence ences 4 59 RDY Signal Generation for STRBO Cycles i 4 61 RDY Signal Generation Timing Waveforms i 4 63 Contents xxi Figures 4 31 4 32 4 33 4 34 4 35 4 36 4 37 4 38 4 39 4 40 4 41 4
42. STRB1 control register A0 A23 STRBO B3 STRBO B2 STRBO B1 STRBO BO IOSTRB STRB1 B3 STRB1 B2 STRB1 B1 STRB1 BO D0 D31 Physical memory Logical memory map U Heavy lines indicate multiple signals m External gt memory gt bank p 1 STRBO External lOSTRB gt memory p bank p 2 u u u STRBO External STRB1 memory bank we 3 Oh 7FFFFFh 810000h 82FFFFh 880000h 8FFFFFh 900000h FFFFFFh dS ZED0ZESWL 94 0 iowayy Bureau Interfacing Memory to the TMS320C32 DSP 4 6 14 Functional Description of the Enhanced Memory Interface The enhanced memory interface controls all data and program traffic between data buses inside the chip and the 32 bit external memory bus as shown in Figure 4 10 through Figure 4 13 For any bus cycle involving a logical memory address range mapped to IOSTRB the memory interface simply con nects the external data bus with an appropriate internal data bus without fur ther data manipulation The memory interface is much busier when the C32 is accessing logical memory addresses mapped to STRBO and STRB1 Depending on the data size and external memory width as defined by corresponding strobe control registers data can be packed unpacked truncated or shifted on its way to and from the chip Section 4 6 1 1 through
43. TA R7 I AR7 AR6 R6 I AR6 AR5 A 16 1 R5 I R1 BLE ART ART7 AR6 AR5 R1 R7 R7 R1 R6 R6 RI R5 R5 X I4 SIN X I4 SIN X I4 COS X I4 COS SIN 1 2 pi 16 COS 3 2 pi 16 SIN 2 2 pi 16 COS 2 2 pi 16 SIN 3 2 pi 16 COS 1 2 pi 16 6 54 Example 6 16 Real Forward Radix 2 FFT Continued Fast Fourier Transforms FFTs MPYF3 AR7 AR4 RO MPYF3 AR2 IRO R5 R4 MPYF3 AR3 IRO R5 Rl1 MPYF3 AR7 AR3 RO ADDF3 RO R1 R2 MPYF3 AR6 AR4 RO SUBF3 R4 RO R3 SUBF3 ARI IRO R3 R4A ADDF3 AR1 R3 R4 STF R4 AR2 SUBF3 R2 ARO IRO R4 STF R4 AR3 ADD F3 ARO R2 R4 STF R4 AR1 MPYF3 AR3 R6 R1 STF R4 ARO ADDF3 RO R1 R2 MPYF3 AR5 AR4 IRO RO SUBF3 RO R1 R3 SUBF3 AR1 R3 R4 ADDF3 AR1 R3 R4 STF R4 AR2 SUBF3 R2 ARO R4 STF STF R4 AR1 MPYF3 AR2 R7 R4 STF R4 ARO MPYF3 AR3 R7 R1 MPYF3 AR5 AR3 RO ADDF3 RO R1 R2 MPYF3 AR7 AR4 IR1 RO SUBF3 R4 RO R3 SUBF3 AR1 R3 R4 ADDF3 AR1 R3 R4 STF R4 AR2 IR1 SUBF3 R2 ARO R4 STF R4 AR3 IR1 ADDF3 ARO R2 R4 STF R4 AR1 IR1 RPTB LOOPA4 B MPYF3 AR2 IRO R5 R4 STF R4 ARO IR1 MPYF3 AR3 IRO R5 R1 MPYF3 AR7 AR3 RO ADDF3 RO R1 R2 MPYF3 AR6 AR4 RO SUBF
44. AR7 IR1 R7 R7 COS 2 pi 8 AR7 COS 2 pi 8 AR7 AR2 RO RO X I3 COS AR3 R7 R1 R5 X I4 COS RO R1 R2 R2 X I3 COS X I4 COS AR7 AR2 IRO RO RO R1 R3 R3 X I3 COS X I14 COS AR1 R3 R4 RA X I2 R3 AR1 R3 R4 R4 X I2 R3 RA AR2 IRO X I3 lt _ R2 ARO R4 R4 X Il R2 RA AR3 IRO X I4 ARO R2 R4 R4 X I1 R2 RA AR1 IRO X I2 LOOP3 B i AR3 R7 R1 R4 ARO IRO X I1 4 RO R1 R2 AR7 AR2 IRO RO DSP Algorithms 6 51 Fast Fourier Transforms FFTs Example 6 16 Real Forward Radix 2 FFT Continued SUBF3 RO R1 R3 SUBF3 AR1 R3 R4 ADDF3 AR1 R3 R4 STF R4 AR2 IRO SUBF3 R2 ARO R4 STF R4 AR3 IRO LOOP3 B ADDF3 ARO R2 R4 STF R4 AR1 IRO MPYF3 AR3 R7 R1 STF R4 ARO IRO ADDF3 RO R1 R2 SUBF3 RO R1 R3 SUBF3 AR1 R3 R4 ADDF3 AR1 R3 R4 STE R4 AR2 SUBF3 R2 ARO R4 STE R4 AR3 ADDF3 ARO R2 R4 STE R4 AR1 STF R4 ARO 6 52 Example 6 16 Real Forward Radix 2 FFT Continued Fast Fourier Transforms FFTs H Perform fourth FFT loop Part A 4 ARI gt r 7 i i i i i i AR2 i 7 i ARS gt i i i L ARI gt g i i 7 i LOOP4_A Il I2 I3 I4 I5
45. lq liops libus I 110 mA 55 mA 55mA 0 8 209 mA 12 5 2 Data Output Example Supply Current Calculations The portion of the FFT corresponding to writing out data is approximately 596 ofthe total processing time Again the data being written is assumed to be ran dom From Figure 12 3 on page 12 7 and Figure 12 8 on page 12 15 scale factors of 0 80 and 0 85 are used for derating from data value dependency for internal and primary buses respectively During the data dump portion of the code a load and store are performed every cycle The parallel load store instruction is in an RPTS loop so there is no contribution from internal opera tions because the instruction is fetched only once The only internal contribu tions are from quiescent current and internal bus operations Figure 12 5 on page 12 12 indicates a 170 mA current contribution from back to back zero wait state writes and Figure 12 7 on page 12 14 indicates a 80 mA con tribution when the expansion bus is idle that is with more than 18 H1 cycles between writes The total contribution from this portion of the code is lq libus Ixbus or 110 55 mA 0 8 60 mA 80 mA 170 mA 0 85 278 5 mA 12 5 3 Average Current The average current is derived from the two portions of the FFT The proces sing portion takes 95 of the time and requires about 210 mA and the data dump portion takes the other 596 and requires about 280 mA T
46. Time slo unsigned in unsigned in unsigned in unsigned in unsigned in Time slo unsigned in unsigned in unsigned in unsigned in Time slo unsigned in unsigned in unsigned in Time slo unsigned in Time slo unsigned in unsigned in Time slo unsigned in Time slo unsigned in unsigned in _bitval CONTROL ct cr ct ct ct ct at bou ct ct ct ct ct ct cg chet ct ct ct choc ct ct ct ct ct 4 adl enl d r5 3 xen xcdlle bsel mckf d r4 2 df st dfr d_r3 1 acu dcb da rz j M Oo VY YDH EM NWR M EM e M Loopback mode Enable loopback testing Unused don t care bits 2 7 Transmitter enable Transmit clock Select bit rate Clock source select Unused don t care bits 6 7 Data format selection Stereo bit O mono l1 stereo Data conversion freq selection Unused don t care bits 6 7 Unused don t cares bits 0 1 Data control handshake bit Unused don t cares bits 3 7 Unused don t care bits 0 7 Revision level of the CS4215 Unused don t care bits 4 7 Unused don t care bits 0 7 Unused don t care bits 0 5 Parallel port control RK HK IK kk I kk I kk I kk I kk I kk kk kk kk kk I kk kk kk ck kc kc kc kc kc kc I I I ck ck ok ck ck ckok ckok koe ke
47. e e i hw16381 903FFCh hw16382 903FFDh STREG hw16383 903FFEh STRBT B 903FFFh Logical address shift 1 bit 16 bit data size Memory Data STRB1 width size control register pic 0 0 0 MIS 8bits 16 bits Logical address 23 to 0 Physical address 23 to 2 HASSE Memory address 14 to 0 BODUDDEEEE 55e SSO SS UUCODDDEDED B ae 8 bit data bus oo TMS320032 9 KT S A14 A13 A12 e e e A1 AO A 1 A 2 STRBO BT STRBO BO E Toggle o a a E CD 4 wi hw1 Is hw1 ms hw2 Is hw2 ms hw16383 hw16383 Oh ih 2h 7FFCh 7FFDh gt BI ALENE7FFEh Beez 7FFFh Memory address space Physical address shift 2 bits 8 bit m Notes 1 The amount of shift between logical and physical addresses depends only on the size of data being transferred 2 The amount of shift in the physical connection between the C32 and the external memory depends only on the width of the memory bank emory width uoge sueJ sseJppy pue eoejieju AIOWAyy A R Figure D 11 Address Translation for
48. f XFSM XCLKSRCE I RFSM 8 64 CS4215 Interface to the TMS320C3x Example 8 16 CS4215 c Continued hile SERIAL PORT ADDR SER NUM gcontrol bit xrdy 0 ERIAL PORT ADDR SER NUM x data 0 See note on XRDY and three cycle delay in C3x U G or j 0 j lt 3 j mn WD while SERIAL_PORT_ADDR SER_NUM gt gcontrol_bit xrdy 0 SERIAL PORT ADDR SER NUM x data data_control _intval 1 dummy SERIAL PORT ADDR SER NUM r data SERIAL PORT ADDR SER NUM gcontrol XINT RINT SERIAL PORT ADDR SER NUM gcontrol amp XCLKSRCE SERIAL PORT ADDR SER NUM s rxt control 0 CL INT FL REG if SER NUM F SER_PORT_RCV_INT_1 else F SER PORT RCV INT 0 fendif Ei N GLOBAL INTS DCB HI Analog Interface Peripherals and Applications 8 65 Software UART Emulator for the TMS320C3x 8 7 Software UART Emulator for the TMS320C3x 8 7 4 Hardware 8 7 2 Software 8 66 By using the general purpose I O pins in conjunction with two timers and an external interrupt you can develop a very flexible full duplex universal asyn chronous receive transmit UART emulator in software This solution dis cusses the implementation of an interrupt driven 9 600 baud UART with eight data bits one stop bit and no parity This solution was contributed by T
49. 30 62 ARAM X I4 ist 31 63 Lo 32 64 AR1 gt 33 65 i LDI 1 IRO LDI 4 R5 LDI QFFT SIZE R7 LSH 2 R7 SUBI 1 R7 LDI FFT_SIZE R6 LSH 1 R6 LDI SOURCE_ADDR AR5 LDI SOURCE_ADDR AR1 LSH 1 R6 LDI AR1 AR4 ADDI R7 AR1 onwards XP 2 X I4 X I1 X I1 X X I4 X I2 X Step between two consecutive sines Stage number from 4 to M R7 is FFT SIZE 4 1 and will be used to point at A amp D R6 will be used to point at D R6 is FFT SIZE at the lst loop AR1 points at A 2 X 13 X I3 I2 COS X I3 X 14 SIN 2 12 SIN X I3 X 1I4 COS ie 15 for 64 pts DSP Algorithms 6 65 Fast Fourier Transforms FFTs Example 6 17 Real Inverse Radix 2 FFT Continued DI DDI DDI UBI DI SUBI to m Pe E LDI INLOP ADDF3 E Og H wn m i uU NNEPNERNPHNEY ZSPN WE UO Iw hr Co AR1 AR2 2 AR2 AR2 points at B R6 ARA R7 AR4 ARA points at D ARA AR3 2 AR3 AR3 points at C R7 IR1 R7 RC ARI IR1 AR3 IR1 R0 RO X Il X I3 4 AR3 AR1 R1 R1 X I1 X I3 7 ARA R2 RO AR1 X I1 2 0 R2 R2 2 X I4 AR2 R3 1 AR3 X 13 4 2 0 R3 R3 2 X I2 7 R3
50. BANKSEL BSTRB CS cst BSTRBI CS BSTRB CS CS CS2 CS2 CS WE WE WE WE y 9 awp v F ano y 9E GND y OE GND Eee y y v BANKSELO BSTRB e BR W Bank 0 C0 J 2 BANKSELT Bank 1 DE BANKSEL2 Bank 2 BANKSEL3 Bank 3 D31 DO Wait States and Ready Signal Generation Figure 4 8 Bank Memory Control Logic 4 18 UT 74ALS254 A0 a1 YI BAO A8 a1 Y1L BAB Rb AR Yr BAI A9 A2 Y2 BAY A2 A3 Y8 BA2 A10 As Y3 BA10 VPE Lo WB A11 A4 YAL BAM D S AX Noe A12 a5 Y5 BA12 A5 6 Y6 BAS RW A6 Y6 BRW A6 A7 Y7 BA6 A7 Y A7 a8 Y8 BA7 AB Y8 Gi Ge Gr G2 e v V 74ALS138 A15 c y10 BANKSELO A14 B Y2b BANKSEL1 A13 a Y30 BANKSEL2 74AS04 Y40 BANKSEL3 Y5 0 STRB gt BSTRB Y6 p A23 G1 Y7p G2A Y8p G2B G2p The C3x rated capacitive loading is 80 pF The 74AL S254 buffers used on the address lines are necessary in this design because the total capacitive load presented to each address line is a maximum of 16 x 10 pF or 160 pF bank memory plus zero wait state static RAM Using the manufacturer s derating curves for these devices at a load of 80 pF the load
51. CALL OR INTERRUPT register TITLE CONTEXT RESTORE FOR THE TMS320C3x global RESTR CONTEXT RESTORE AT THE ND OF A SUBROUTINE ESTR RESTORE THE REST REGISTERS FROM THE REGISTER FIL POP RC Restore repeat counter POP RE k Restore repeat end address POP RS Restore repeat start address POP IOF R Restore I O flag register POP IF Restore interrupt flag register POP IE E Restore interrupt enabl POP BK B Restore blocktsize register POP IR1 Restore index register IR1 POP IRO H Restore index register IRO POP DP Restore data page pointer RESTORE THE AUXILIARY REGISTERS POP AR7 A Restore AR7 POP AR6 A Restore AR6 POP AR5 A Restore AR5 POP AR4 H Restore AR4 POP AR3 Restore AR3 POP AR2 gt Restore AR2 POP AR1 Restore AR1 POP ARO A Restore ARO RESTORE THE EXTENDED PRECISION REGISTERS Program Control 2 15 Context Switching in Interrupts and Subroutines Example 2 5 Context Restore for the TMS320C3x Continued POPF POP POPF POP POPF POP POPF POP POPF POP POPF POP POPF POP POPF POP POP ESTORE R7 R7 R6 R6 R5 R5 R4 R4 R3 R3 R2 R2 R1 R1 RO RO ST IS COMPL tore th the lower 32 tore the upp the lower 32 tore the upp the lower 32 tore the upp the lower 32 tore the upp the lower 32 tore the upp th
52. Clock Oscillator and Ceramic Resonators 9 15 Pierce Oscillator Circuit For the Pierce circuit used on the C3x this attenuation of the fundamental fre quency is achieved by capacitively coupling an inductor Li in parallel with the load capacitor C4 as shown in Figure 9 13 The value of L is chosen to reso nate with C1 at some intermediate frequency between the frequency of the de sired overtone and the next lower odd overtone At the desired overtone fre quency the impedance of L4 is high enough compared to C thatL is neglected and the network of C and the inverter s output impedance provides the near 90 phase lag desired Since the phase conditions are met the circuit oscillates at this frequency At all lower overtones L is a lower impedance than C4 and causes a 90 phase lead instead of phase lag At any of these low er frequencies the total phase shift around the feedback loop is 180 not 360 which is negative feedback and stabilizes the circuit and prevents oscillation L is coupled with a 0 1 uF capacitor which prevents the inductor from altering the dc bias of the inverter while causing negligible additional impedance at the oscillation frequency Figure 9 13 Oscillator Circuit for Overtone Crystal Operation C3x i Se mmc 9E MEM L QE E X2 CLKIN X1 4 4 eT 04uF Co zm S C1 As an example assume a 60 MHz third overtone crystal is
53. Figure 4 31 illustrates the logical to physical address translation for the three memory banks used in the RDY signal generation example in section 4 6 6 Each memory bank is a different physical width as shown by the physical ad dress column on the right side of the figure The left side of the figure repre sents the internal logical address ranges for each ofthe three memory banks Logical to physical address translation is controlled by strobe control registers and by their data size and memory width fields The middle column of Figure 4 31 shows the logical address field top row over the physical ad dress bottom row for each address translation case The active address fields are shaded gray and the inactive address bits are white The black fields are special address bits that can selectively control multiple strobe lines or choose between individual portions of a data word that is larger than the physi cal memory it is accessing For example in bank 2 the right side of the figure indicates that the physical memory width for this bank is 16 bits The left side indicates that regardless of the physical memory width 32 16 and 8 bit data can be moved by pro gramming the STRBO control register The low order shaded bits of logical physical address rows show how many bits are actually used for addresses so that the correct high order address bits can be assigned to bank decode Physical address bits A17 and A18 are chosen f
54. SPCL STF R6 AR1 IRO PYF R1 AR4 R7 SUBF R7 R6 PYF R1 AR4 IR1 R6 STF R6 AR2 PYF R3 AR4 R7 ADDF R7 R6 PYF R4 AR6 IR1 R6 STF R6 AR2 IRO PYF R2 AR6 R7 SUBF R7 R6 PYF R2 AR6 IR1 R6 STF R6 AR3 PYF R4 AR6 R7 ADDF R7 R6 STF R6 AR3 IRO CMPI LPCNT RO BP INLOP BR CONT ECIAL BUTTERFLY FOR W LDI IR1 AR4 LSH 1 AR4 ADDI SINTAB AR4 RPTB BLK3 ADDF AR2 ARO R1 SUBF AR2 ARO R2 ADDF AR2 ARO0 R3 SUBF AR2 AR0O R4 ADDF AR3 AR1 R5 SUBF R1 R5 R6 ADDF R5 R1 ADDF AR3 AR1 R5 SUBF R5 R3 R7 ADDF R5 R3 STF R3 AR0 STF R1 ARO IRO SUBF AR3 AR1 R1 SUBF AR3 AR1 R3 STF R6 AR1 X I1 R1 CO2 R3 SI2 R7 R1 SI1 R6 R3 CO1ER1 SI1 R6 R1 COl Y I2 R3 CO1 tR1 SI1 R7 R3 SI1 R6 R1 C O1 R3 SI1 R6 R4 CO3 X I2 R1 CO1 R3 SI1 R7 R2xSI3 R6 R4 CO3tR2 S13 R6 R2 CO3 Y I3 R4 CO3tR2 SI3 R7 R4 SI3 R6 R2 CO3 R4 S13 x i3 R2 CO3 R4 SI3 Loop back to the inner loop Point to SIN 45 Create cosine index AR4 CO21 R1 X I 4X I2 R2 X I X X I2 R3 Y I 4Y I2 R4 Y I XY I2 R5 X I1 X I3 R6 R5tR1 R1 R1 R5 R5 Y I1 Y I3 R7 R3tR5 R3 R3 R5 Y I R3 R5 X I R1 R5 R1 X 1I1 X 13 R3 Y I1 tY I13 Y I1 R5tR1 6 40 Example 6 15 Fast Fourier Transforms FFTs Complex Radix 4 DIF FFT Continued
55. TITLE DMA TRANSFER WITH SERIAL PORT TRANSMIT INTERRUPT 5 GLOBAL START DATA DMA WORD 808000H DMA GLOBAL CONTROL REG ADDRESS CONTROL WORD OE13H DMA GLOBAL CONTROL REG INITIALIZATION SOURCE WORD _ARRAY 1 DATA SOURCE ADDRESS DESTIN WORD 80804CH DATA DESTIN ADDRESS SERIAL PORT OUTPUT REG COUNT WORD 127 NUMBER OF WORDS TO TRANSFER MSG LENGHT 1 IEVAL WORD 00100400H IE REGISTER VALUE BSS _ARRAY 128 DATA ARRAY LOCATED IN BSS SECTION THE UNDERSCORE USED IS JUST TO MAKE IT ACCESSIBLE FROM C OPTIONAL RESET1 WORD OE10H DMA RESE SPORT WORD 808040H SERIAL PORT GLOBAL CONTROL REG ADDRESS SGCCTRL WORD 04880044H SERIAL PORT GLOBAL CONTROL REG INITIALIZATION SXCTRL WORD 111H SERIAL POR X PORT CONTROL REG INITIALIZA TION STCTRL WORD OOFH SERIAL POR IMER CONTROL REG INITIALIZATION STPERIOD WORD 00000002H SERIAL POR IMER PERIOD SPRESET WORD 00880044H SERIAL PORT RESET RESE WORD OH SERIAL POR IMER RESET TEXT START LDP DMA LOAD DATA PAGE POINTER Programming the DMA Channel 7 7 DMA Assembly Programming Examples Example 7 3 DMA Transfer With Serial Port Transmit Interrupt Continued
56. ed define X1 MODE 0x000000111 FSX DX CLKX are serial port pins define R1 MODE 0x000000111 FSX DX CLKX are serial port pins J define S1 CONFIG 0x00EBC3COO SerialPort Configutration FSX FSR input FSX FSR signals active high external CLKX R CLIM CLKR active low fixed data rate mode wv 32 bit data width TX RX interrupts are enabled EJ XRESET RRESET set to O a take out of reset Jm ay Timer 0 Initialization F T TOUT Frequency clock mode 1 8 CLKIN TO PERIOD if TO PERIOD period gt 0 1 4 CLKINI if TO PERIOD period 0 ff define TO_PERIOD 0 TOUTO 12 288 MHz for 49 152 MHz CLKIN define TO HOLD 0x0301 clock mode 50 duty cycle define TO GO 0x03C1 JR kf Interrupt Mask asm ERINT1 CPU Set 80h enable serial port 1 receive int asm GIEBIT Set 2000n global enable interrupts 8 36 TLC320AD58 Interface to the TMS320C3x Example 8 8 C3x h Header File Listing Continued TMS320C3X CONTROL REGISTER LOCATIONS af Serial Ports SERIAL PORT BASE LOCATION volatile int serial port 16 volatile int 16 0x808040 SERIAL PORT CONTROL REGISTERS define GLOBAL 0 GLOBAL CONTROL x define
57. p 0 7 0 STRBO B1 STRBO BO D 31 24 lt D 23 16 L D 15 8 lq D 7 0 lg STRB1 B3 A 4 STRB1 B2 A 2 lt STRB1 BO In Figure 4 33 a bank of 32K x 32 bits is mapped to STRBO and a bank of 32K x 8 bits is mapped to STRB1 For this configuration the programmer must set the following D STRBOocontrol register physical memory width to 32 bits and the data type size to 32 bits D STRB config bit field to 0 that is STRBO control register 000F0000h banks are separate D STRB1 control register physical memory width to 8 bits and the data type size to 8 bits that is STRB1 control register 00000000h Additionally the PRGW pin must be pulled low to indicate 32 bit program memory width Memory Interfacing 4 75 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface Figure 4 33 also maps the 32 bit wide bank s external memory address pins A44443 A4A9 tothe C32 sA44A43A40 A4Agopins Conversely the8 bit wide bank s memory address pins A14A13 A1Ao are mapped to the C32 s A12 A4A9A 1 pins Because STRB1 is configured for 8 bit memory width the external address presented on C32 pins is shifted right by two bits As a result of this mapping external memory accesses in the range Oh through 7FFFh read or write 32 bit data to the 32 bit wide bank STRBO Memory accesses in the range 900000h through 907FFFh read or write 8 bit data to the 8 bit wide bank STRB1
58. wait state STRB devices AS ia A23 Other 0 ansan pos Q 5V N j PRE A23 2 74AS20 4 7 kQ 74A821 74ACT112 K CLR RDY J PRE a o 74ACT112 F 4 5 5 Example Circuit 4 14 In the circuit in Figure 4 6 full speed devices drive ready signals directly through the 74AS21 NOR gate and the two flip flops delay wait state devices select signals one or two H1 cycles to provide one or two wait states Considering the C3x 33 s ready signal delay time of 8 ns following the ad dress zero wait state devices mustuse ungated address lines directly to drive the input of the 74AS21 since this gate contributes a maximum propagation delay of 6 ns to the RDY signal Zero wait state devices must be grouped to gether within a memory address range if other devices in the system require wait states With this circuit devices requiring wait states might take up to 36 ns to provide inputs to the 74AS20 OR gate s inputs from a valid address on the C3x This usually allows sufficient time for any decoding required in generating select signals for slower devices in the system For example the 74ALS138 multi Wait States and Ready Signal Generation plexer driven by the address bus and STRB pin can generate select decodes in 22 ns which easily meets the C3x 33 s timing requirements With this circuit unused inputs to either the 74AS20 OR gates or the 74AS21 NOR gate must be tied to a logic high level
59. 6 6 4 Real Radix 2 FFT In many cases the data to be transformed is usually a sequence of real num bers This real input data has properties that reduce the computational load of the FFT algorithm even further The FFT algorithm that exploits such properties is called a real radix 2 FFT Example 6 16 shows the generic implementation of areal valued forward radix 2 FFT For such an FFT the total storage required for a length N transform is only N locations in a complex FFT 2N locations are necessary Recovery of the rest of the points is based on the symmetry condi tions Example 6 16 Real Forward Radix 2 FFT Ck Ck ck ck Ck ck ck ck ck ce ck ck Ck ck ck Ck Sk KKK KKK KKK KK KKK KKK ck ck KKK KKK KKK KKK KKK ck kk ck ck ck ck ck ck kk Sk kk ko kk KKK ko kock KKK FILENAME ffft rl asm WRITTEN BY Alex Tessarolo i Texas Instruments Australia DATE 23rd July 1991 VERSION 2 0 ck ck 0k ck ck 0k ck kk ck 0k ck ck ck ck Ck ck ck 0k ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck kc ck ck ck ck ck ck kc ck ck ck ck ck ck ck ck ck ock ok ck ck ck ko ck ko Sk kv kx ko kA kx ko i VER DATE COMMENTS A0 18th July 91 Original release EO 220 23rd July 91 Most stages modified Minimum FFT size increased from 32 to 64 Faster in place bit reversing algorithm Program size increased by about 100 wor
60. AR1 LAST X I1 6 72 Fast Fourier Transforms FFTs Example 6 17 Real Inverse Radix 2 FFT Continued Check bit reversing mode on or off BIT REVERSING 0 then OFF no bit reversing BIT REVERSING 0 then ON LDI BIT_REVERSE RO CMP I 0 RO BZ MOVE DATA Check bit reversing type If SourceAddr DestAddr then in place bit reversing If SourceAddr lt gt DestAddr then standard bit reversing LDI SOURCE_ADDR RO CMPI DEST_ADDR RO BEQ IN_PLACE Bit reversing type 1 from source to destination NOTE abs SOURCE_ADDR DEST ADDR must be gt FFT SIZE this is not checked LDI FFT_SIZE RO SUBI 2 R0 LDI FFT_SIZE IRO LSH 1 IR0 IRO half FFT size LDI SOURCE_ADDR ARO LDI DEST_ADDR AR1 LDF ARO R1 RPTS RO LDF ARO R1 STE R1 AR1 IRO B STF R1 AR1 IRO B BR DIVISION DSP Algorithms 6 73 Fast Fourier Transforms FFTs Example 6 17 Real Inverse Radix 2 FFT Continued Fr In place bit reversing i Bit reversing on even locations 1st half H only IN PLACE DI GFFT SIZE IRO LSH 2 IRO0 IRO quarter FFT size LDI 2 IR1 LDI QGFFT SIZE RC LSH 2 RC SUBI ZERE LDI DEST_ADDR ARO LDIA RO ARL LDIA RO AR2 NOP AR1 IRO B NOP AR2 IRO B LDF ARO IR1 RO LDF AR
61. AR2 IR1 I2 s R2 AR4 IR1 x 14 lt _ FFT_SIZE IR1 IRl separation between SIN COS this SINE_TABLE ARO ARO points at SIN COS table 27 IR1 3 RC AR2 AR1 R3 R3 X I1 X I2 AR1 AR2 R2 R2 X I1 X I2 R3 ARO IRO R1 R1 R3 SIN AR4 R4 RA X I4 R3 ARO IR1 RO RO R3 COS AR3 R4 R3 R3 X I4 X 13 R4 AR3 R2 R2 X I3 X I4 R2 AR1 X ILl R2 ARO IR1 R4 R4 R2 COS R3 AR2 gt X I2 lt R4 R1 R3 R3 R3 SIN R2 COS R2 ARO R1 R1 R2 SIN R3 AR4 X I4 lt R1 R0 R4 R4 R3 COS R2 SIN IN_BLK 6 66 Example 6 17 Real Inverse Radix 2 FFT Continued Fast Fourier Transforms FFTs IN BLK AR2 AR1 R3 AR1 AR2 R2 AR4 R4 R3 AR2 R4 R1 R3 R3 AR4 R1 R0 R4 AR4 R4 R2 AR1 R3 AR2 R6 IR1 R4 R1 R3 R2 ARO R1 RO R4 AR1 1 AR5 ARI1 QFFT SIZI INLOP R3 ARO IRO R1 RA AR3 R3 ARO IR1 RO AR3 R4 R3 R4 AR3 R2 R2 AR1 R2 AR0 IR1 R4 R2 ARO R1 AR2 AR1 R3 AR1 AR2 R2 R3 ARO IRO R1 R4 AR3 R3 ARO IR1 RO AR3 R4 R3 R4 AR3 R2 R2 AR0 IR1 R4 R1 R3 AR4 IR1 R1 R2 R4 AR3 IR1 RO E RO AR2 44 I R7 IRl R7 RC IRS GLOG SIZI
62. C C C C C t C t C C t t t c x RoOwWTtONrS aQooaoaooaoaad 7 8 X YZE NVHS MN O DONONTIMONTO C C C C C C C C C t T t t t ax KONVINT 8 x ze NVHS e repu SDDS QUO E CO QN I CO IILLLLLILLILLILT KOON TO o oQaoaaadodaaa 8 x 2 NVHS FMN O OVONONTINONTO C C C C C t C tC t t T t t c ax NF CO QI CO O0 O0 F CO LO x CO QU OD XXXXX C C C C eL t uL sca MCBL MP 5 IS IS STRBO_B2 STRBO B1 STRBO BO STRBO B3 Interfacing Memory to the TMS320C32 DSP OwWtONr dS S88888858 8 X M26 WOud3 o SN TUT TT O 00 l O10 sr C2 QI CO C C C C C C C t t t t t t c s NF CO QV CO O OO l CO LO s CO QN ZSEZZ9322912242 OFN oo o B88a888858 8 x YZE NOHd3 TOMON O OVONONTION O C C C C C C C C C t wt et t st EOVESLAR LIARS xc l6 aqggg0006 gxyze Wouda l TON e TC C OOrQOQD40N o C C C C C t C t C t t t t st zoUceSSESOI9SZS CES x Dio st COQN 7 CO S88888858 8 x 26 WOud3 ZOSLTPTooroosoa o C C C C tC t C t C t et uL t st 22222222222222 ENTE onre c Memory Interfacing STRB1 BO D0 D31 TUN Interfa
63. I e r roo ooo oo Ti 1111 1111 P COCOA COBMEREMEREMERE Physical address Ae 13 AQ STRBO 16382 16382 STRBT 10383 vy 16383 c 16384 923FFFh 7FFFh 16384 STRB0_B3 STRBO B2 STRBO B1 STRBO BO dS ZED0ZESWL eui 0 Aiowayy Buroeueju Interfacing Memory to the TMS320C32 DSP 4 6 5 4 Example Summary The one bank two strobes memory interface to the C32 supports any com bination of data size pairs 16 8 32 8 and 16 32 bits with no speed penalty The strobe control registers do not have to be reconfigured each time the data size changes Likewise 16 bit external memory can be divided into two halves each containing data of a different size 8 16 or 32 bits The same holds true for 8 bit external memory All address translation information given in section 4 6 1 through section 4 6 4 also applies to the one bank two strobes examples To configure the external memory for one bank two strobes access mode use the following steps 1 Setthe strobe configuration field in the STRBO control register to 1 2 Setthe memory width field in both the STRBO and STRB1 control registers to reflect the width of the physical memory 3 Setthe data size field in both the STRBO and STRB1 control registers to reflect the size of the data portions chosen for each strobe 4 Choose one ofthe high physical address bits to split the physical memory into two halves 5
64. IN THE TMS320C3x HE PROGRAM IS TAKEN FROM THE BURRUS AND PARKS BOOK P 117 HE COMPLEX DATA RESIDE IN INTERNAL MEMORY AND THE COMPUTATION IS DONE IN PLACE HE TWIDDLE FACTORS ARE SUPPLIED IN A TABLE THAT IS PUT IN A DATA SECTION THIS DATA IS INCLUDED IN A SEPARATE FILE TO PRESERVE THE GENERIC NATURE OF THE PROGRAM FOR THE SAME PURPOSE THE SIZE OE HE FFT N AND LOG4 N ARE DEFINED IN A GLOBL DIRECTIVE AND SPECIFIED DURING LINKING ui IN ORDER TO HAVE THE FINAL RESULT IN BITEREVERSED ORDER THE TWO is MIDDLE BRANCHES OF THE RADIX 4 BUTTERFLY ARE INTERCHANGED DURING STORAGE NOTE THIS DIFFERENCE WHEN COMPARING WITH THE PROGRAM IN P 117 OF THE BURRUS AND PARKS BOOK globl FFT Entry point for execution globl N FFT size globl M i LOG4 N globl SINE Address of sine table usect IN 1024 Memory with input data text p INITIALIZE TEMP word 42 STORE word FFTSIZ Beginning of temp storage area word N word M word SINE word INP 6 36 Fast Fourier Transforms FFTs Example 6 15 Complex Radix 4 DIF FFT Continued BSS BSS BSS FFTSIZ 1 LOGFF1 SINTAB 1 Li BSS INPUT 1 BSS STAGE RPTCN BSS IEINDX 1 LPCNT BSS BSS BSS JT 1 BSS IA1 1 FFT 1 r1 1 x INITIALIZE DATA LOCATIONS LDP LDI LDI LDI STI LDI STI LDI STI LDI STI LDP LDI LDI LDI LDI STI LSH LSH LDI STI
65. LDI QFFT SIZE RC LSH 1 RC LDI DEST_ADDR ARO ADDI RC ARO ADDI 1 ARO LDI ARO AR1 LDI ARO AR2 LSH 1 RC SUBI 3 RC NOP AR1 IRO B NOP AR2 IRO B LDF ARO IR1 RO LDF AR1 R1 CMP I AR1 ARO H Xchange locs only if ARO ARI1 LDFGT RO R1 LDFGT AR1 IRO B R1 RPTB BITRV2 LDF ARO IR1 RO MI STF RO ARO LDF AR1 R1 B STF R1 AR2 IRO B CMPI AR1 ARO0 LDFGT RO R1 BITRV2 LDFGT AR1 IRO B RO STF RO ARO STF R1 AR2 Perform bit reversing on odd z locations lst half only DSP Algorithms 6 47 Fast Fourier Transforms FFTs Example 6 16 Real Forward Radix 2 FFT Continued MOVI P BITRV3 DATA LDI QFFT SIZE RC LSH 1 RC LDI RC IRO LDI DEST_ADDR ARO LDI ARO AR1 ADDI 1 ARO0 ADDI IR0 AR1 LSH 1 RC LDI RC IRO SUBI 2 RC LDF ARO RO LDF AR1 R1 RPTB BITRV3 LDF ARO IR1 RO STF RO AR1 IRO B LDF AR1 R1 STF R1 ARO IR1 STF RO AR1 STF R1 ARO BR START Check data source locations If SourceAddr DestAddr then do nothing If SourceAddr lt gt DestAddr then move data LDI SOURCE_ADDR RO CMPI DEST_ADDR RO BE STAR LDI FFT_SIZE RO SUBI 2 R0 LDI SOURCE_ADDR ARO LDI DEST_ADDR AR1 LDF RRO R1 RPTS RO LDF ARO R1 STF R1 AR1 STF R1 AR1 6 48 Fast Fourier Transforms FFTs Example 6 16 Real Forward Radix 2 FFT Continued
66. R1 LOOP SOURCE_ADDR AR1 1 IRO 1 R7 E R5 R3 X I1 X I2 R2 X I1 4X I2 Rl R3 SIN X 13 RA X I4 RO R3 COS R3 X 14 X 13 R2 X I3 X I4 X I1 4 R4 R2 COS x 12 lt R3 R3 SIN R2 COS R1 R2 SIN X I4 lt R4 R3 COS R2 SIN R3 X I1 X I2 R2 X I1 4X I2 R1 R3 SIN X I3 RA X I4 RO R3 COS R3 X I4 X I13 4 R2 X I3 X I4 X I1 lt R4 R2 COS X 12 4 Get prepared for the next R3 R3 SIN R2 COS Rl R2 SIN x 14 4 R4 R3 COS R2 SIN Dummy X 13 Loop back to the inner loop Dummy Next stage if any left Double step in sinus table DSP Algorithms 6 67 Fast Fourier Transforms FFTs Example 6 17 Real Inverse Radix 2 FFT Continued Perform third FFT loop Part A i AR1 gt Il 0 X I1 X I3 f 1 AR2 gt 12 2 lt 2 X I2 i 3 AR3 gt 13 4 4 X I1 X I3 5 ARS gt 14 6 lt 2 X 14 r 7 ARl gt 8 f 9 1 v LDI SOURCE_ADDR AR1 LDI AR1 AR2 LDI AR1 AR3 LDI AR1 AR4 ADDI 2 AR2 ADDI 4 AR3 ADDI 6 ARA LDI 8 IRO LDI FFT_SIZE RC LSH 3 RC SUBI 1 RC LDI SINE_TABLE ARO ARO points at SIN COS table RPTB LOOP3_A LDF AR3 R3 ADDF3 R3 AR1 RO RO X I1 X I3
67. R7 irx counter imer go AR6 R6 QtimerO control POP AR6 POP AR7 RETI are we at start bit nope check for stop bit check rx bit IOF1 if less than 80h IOF1 0 bad start bit reenable go back to main decrement rx counter update counter in memory load bit time into rx timer start rx timer if rx count 0 get next bit check rx bit IOF1 GO TO INVALID STOP BIT MODULE shift rx byte 24 bits right TRAP RECEIVED BYTE reenable INTON check rx bit IOF1 force carry flag to 1 if rx bit 1 set carry flag shift in carry update rx byte to 0 bit in memory update counter start rx timer in memory 8 68 Software UART Emulator for the TMS320C3x Example 8 17 Full Duplex UART Emulator for TMS320C3x Continued Transmit byte main subroutine TX MAIN PUSH AR7 LDI whole bit time AR7 STI AR7 Qtimerl period load timer period LDI timerl vector AR7 STI AR7 timerl_int_vect tx timer int vector LDI tx_byte AR7 E OR OFFOOh AR7 mask stop bit to tx byte STI AR7 QGtx byte update tx byte AND OFBh IOF send out 0 to IOFO LDI OAh AR7 STI AR7 Qtx counter load counter in memory LDI timer go AR7 H STI AR7 Qtimerl control Start tx timer POP AR7 RETS Timerl interrupt service routine for byte transmission TX INT PUSH ART LDI Qtx_ counter AR7 load in tx counter fro
68. bss CONST 2 d Tr sect N seine ys word 2 CONST s word X ys word _y 7s Programming Tips 5 9 Sharing Header Files in C and Assembly 5 5 Sharing Header Files in C and Assembly Sometimes it is useful to be able to define named constants that can be used in both C and assembly language One method is to have separate header files that define the same symbols aC include file with define directives and an assembler include file with set or asg directives However it is more convenient to have a single shared header file that defines symbols once for C and assembly Figure 5 2 shows how a file can be used normally as a C include file and also to generate an assembler include file By compiling it and defining ASMDEFS an assembler include file is generated from this file with the following com mand C130 dASMDEFS k defs h Figure 5 2 Input File defs h define PI 3 14 define E 2 72 ifdef ASMDEFS IF DEFINED CREATE asg DIRECTIVES define ASM ASG sym asm Nt asgNt VAL sym sym define VAL sym Sym ASM_ASG PI ASM ASG E endif ASMDEFS The output is the file defs asm which contains asg directives for your symbols see Figure 5 3 Figure 5 3 Output File defs asm j o lt compiler generated header stuff asg 3 14 PI asg 2 72 E You can then use include in your assembly modules The same technique
69. 0000008d 0000008e 0000008 f 00000090 00000091 00000092 00000093 00000094 00000095 00000096 00000097 00000098 00000099 0000009a 00000095 0000009c TMS320C32 Boot Loader Opcodes OPCODE 1a660001 6a060004 09e6ffff O9eeffff 09e50001 6a00fffa 186e0002 04ee0000 6a070002 72000053 6 80fffe 70000008 15410704 70000008 15410706 70000008 15410708 70000008 08010001 6a060007 08400704 15400760 08400706 15400764 08400708 15400768 68000012 081b0001 187b0001 70000008 080d0001 4 100000 5312000d 53710000 70000008 08040001 02e1006c 258c010f 09e4fff8 08030004 09e3fff0 02e30003 1a61000c 52e30003 04e50000 52e900a7 536900ad 6400009b 70000009 1544c400 0c800000 15412501 6a00ffdc ADDRESS 0000009d 0000009e 0000009 f 000000a0 000000a1 000000a2 000000a3 000000a4 000000a5 000000a6 000000a7 000000a8 000000a9 000000aa 000000ab 000000ac 000000ad 000000ae 000000af 000000b0 000000b1 000000b2 000000b3 000000b4 000000b5 000000b6 000000b7 000000b8 000000b9 000000ba 000000bb 0000005bc 000000bd 000000be 000000bf 000000c0 000000c1 000000c2 000000c3 000000c4 000000c5 000000c6 000000c7 000000c8 000000c9 000000ca 000000cb 000000cc 000000cd 000000ce 000000cf 000000d0 000000d1 000000d2 OPCODE 086800a7 08650000 08620000 080a000 f 08600111 15400743 08670a30 09e70010 15470740 6a00ffcc 1a770020 6a05fffe 02 70fdf 0841074c 78800000 08630003 08730001 09930005 18730001
70. 08060003 026e0001 09ee0003 08000005 04e00001 6a050003 09e0ffff O9eeffff 6a00fffb 186e0001 08600000 08610000 02740003 72000007 18740003 21871306 09870000 10010007 02000005 6 80fff8 78800000 1a780002 1542c200 6a060002 08462301 78800000 1b40c700 1a780080 6a06fffd 08462301 08780002 1a780080 6a05fffe 08780006 78800000 TMS320C32 Boot Loader Program B 5 Boot Loader Source Code Listing B 3 Boot Loader Source Code Listing Ck Ck ck ck ck ck ck ck ck ck kk ck kk Ck Ck ck Ck Ck kk Ck ck kk ck kk Ck ck kk ck kk ck ck kk ck ok kk ck ck Sk ck ck kk ck ck Sk ko ck Sk Sk ck ck Sk Sk Mk kv kv ko kx X C32BOOT TMS320C32 BOOT LOADER PROGRAM 143 words March 96 C COPYRIGHT TEXAS INSTRUMENTS INCORPORATED 1994 v 27 NOT 1 FF x F F oko Xo F oxX X Xo OF w Xo F Xo F FF Xo X xXx ox xXx X xXx F ox OF N 2 D Following device reset the program waits for an external interrupt The interrupt type determines the initial address from which the boot loader starts loading the boot table to the destination memory 80804Ch sport0 Rx SERIAL INTRO and INT 1000h STRBO ASYNC PPORT XF0 XF1 3 INTR1 and INT3 810000h IOSTRB ASYNC PPORT XFO XF1 900000h STRB1 ASYNC PPORT XFO XFl If INT3 is asserted together with INT2 or INT1 or INTO following reset that indicates that the boot table is to be read asynchronously from E
71. 11 1 Development Supports ce ee P PISIS 11 2 11 2 TMS320C3x Part Ordering Information 11 7 11 1 Development Support 11 1 Development Support This section describes the development support provided by Texas Instru ments 11 1 1 Development Tools Texas Instruments offers an extensive line of development tools for the C3x generation of DSPs including tools to evaluate the performance of the proces sors generate code develop algorithm implementations and fully integrate and debug software and hardware modules These tools are described below Code Generation Tools There are two types of code generation tools J Optimizing ANSI C compiler Translates ANSI C language directly into highly optimized assembly code You can then assemble and link this code with the Tl assembler linker which is shipped with the compiler It supports both C3x and C4x assembly code This product is currently available for the PC DOS DOS extended memory and OS 2 VAX VMS and SPARC workstations See the 7MS320 Floating Point DSP Optimizing C Compiler User s Guide for detailed information Assembler linker Converts source mnemonics to executable object code It supports both C3x and C4x assembly code This product is currently available for the PC DOS DOS extended memory and OS 2 The C3x CAx assembler for the VAX VMS and SPARC workstations is only available as part of the optimizing C3x C4x compiler S
72. 4409 AeulqeylsheAuoD 7 ZINI A 6uimollo nao nd5 eui seop An uolsJeAUoo xey eu dW 19oW 1soH Jepeollooq 7 INVHS 13S3u Ido uO IIQ 2 0 yotel Hq9 8 Woy slqel 100q eu Adoo 0 E opoo Jepeo 100g diuo uo eui sein2exe Nd I eu dsa cEDOZESINL uondo 19 4exur1 uoi 1 119 8 ue BuIsN 10H Wo 100g G t ainbl4 4 105 Memory Interfacing 9pIM shq 8 opoo INOHd3 19 8 ue JOSSseoojd etu OSV UlM pueog d SQ 01 peyeduioo se 1s00 uiejs s psonpa JO 1SOH jyeuuo xeu lelul 9 qe1100g 94 9401s 01 I NOH d3 S0y sesn welshs dSd eu TENES ely Lreuiq TI 7 epm shq Ze apmsiaze Jepeolloog pital ich pewno 4409 elep elep uonoes julio cala 2a zalld erep Gag UOIJ oes lulo Loi balls
73. 813 3457 0972 Fax 03 3457 1259 or INTL 813 3457 1259 DSP Hotline 03 3769 8735 or INTL 813 3769 8735 Fax 03 3457 7071 or INTL 813 3457 7071 DSP BBS via Nifty Serve Type Go TIASP Documentation When making suggestions or reporting errors in documentation please include the following information that is on the title page the full title of the book the publication date and the literature number Mail Texas Instruments Incorporated Email dsph gti com Technical Documentation Services MS 702 P O Box 1443 Houston Texas 77251 1443 Note When calling a Literature Response Center to order documentation please specify the literature number of the book Read This First xiii xiv Contents Processor Initialization eese III IH Ihn 1 1 Provides examples for initializing the processor 1 4 Reset Process 2 nexus donet dono doeet aa dedo deos bed PR Reli a eer 1 2 1 2 Reset Signal Generation sssiiissssssssssssesses see 1 3 1 3 Howto Initialize the Processor sssssseeeee eee 1 4 1 8 1 Processor Initialization Under Assembly Language 1 4 1 8 2 Processor Initialization Under C Language pp 1 8 1 4 Low Power Mode Interrupt pp 1 9 Program Control only eee netted eee ae See eee eae 2 1 Provides examples for initializing the processor and discusses program control features 2 1 SUBKOUTINGS me RR ERR eU ERR ade deri e accede dou dae ace eR ME RR RR A a s 2 2 2 2
74. 87FE83h PC FRY 32 bits FLOAT RO R1 87FE84h L1 STF R1 AR1 87FE85h 910003h IOSTRB i Physical memory Logical address y 16 bits Ravo P STRET TT data write T 32 bits 91 Apts 102 0 910002h 910003h STRBO MOI Data 104 0 910004h I STRB1 wi Size 105 0 910005h emm control ERE 003510 7 o register 16 bits 16 bits e dS ZED0ZESWL eui 0 Aiowayy Buroeuelu Interfacing Memory to the TMS320C32 DSP 4 6 1 2 STRBO0 and STRB1 Data Access Data Size Memory Width The input and or output data does not have to be the same size as the memory itis being read to or written from see Table 4 3 The data size and memory width for STRBO and STRB1 data access cycles are configured in the corre sponding strobe control registers The short program stored in the RAM1 memory begins with the LDI instruction reading an 8 bit integer from 16 bit wide STRBO memory see Figure 4 12 Since each address contains two data bytes the memory interface uses differ ent STRBO lines to differentiate between the high byte and the low byte Both STRBO and STRB1 comprise four signals each one for each byte of the 32 bits Next the FLOAT instruction converts the integer in RO to a 40 bit floating point number and loads itto R1 Finally the STF instruction stores the contents of R1 to 16 bit wide memory as a 32 bit number Before the data arrives at the memory interface the 32 bit mantissa is
75. 9 shows the timing of this circuit for read operations using bank switching With the BNKCMPR register setto OBh when a bank switch occurs the bank address on address lines A23 A13 is updated during the extra H1 cycle while STRB is high Then after chip select decodes have stabilized and the previously selected bank has disabled its outputs STRB goes low for the next read cycle Further accesses occur at normal bus timings with one wait state as long as another bank switch is not necessary Write cycles do not re quire bank switching because of the inherent address setup provided in their timings This timing is summarized in Table 4 1 Figure 4 9 Timing for Read Operations Using Bank Switching A23 A13 X Valid STRB X BANKSELO t 5 ERR BANKSEL1 k t3 6 D31 DO Bank 0 on bus Bank 1 on bus Memory Interfacing 4 19 Wait States and Ready Signal Generation Table 4 1 Bank Switching Interface Timing for the TMS320C3x 33 Timer Interval Event Time Period t H1 falling to address valid STRB rising 14 ns t2 Address valid to select delay 10 ns t3 Memory disable from STRB 10 ns t4 H1 falling to STRB 10 ns tb STRB to select delay 4 5 ns t6 Memory output enable delay 3 ns 4 20 Interfacing Memory to the TMS320C32 DSP 4 6 Interfacing Memory to the TMS320C32 DSP The C32 accesses external memory with one 24 bit address bus one 32 bit data bus and three strobes IOSTRB STRBO and STRB1
76. A14 selects between the two halves of the memory For this example the C32 address pin A17 drives the memory pin A14 The state of the A17 bit of the physical address is derived from the logical ad dress logical as seen by the instruction The state of the A17 bit also depends on the logical physical address shift as determined by the size of the program data that is being accessed In this case the logical STRBO address range drives the physical address bit A17 to 0 after accounting for a 1 bit address shift due to the 16 bit width of the data Similarly the logical STRB1 range drives the physical address bit A17 to 1 after accounting for a 2 bit address shift due to the 8 bit width of the data The logical STRBO and STRB1 address ranges selected to drive the physical address pin A17 to 0 and 1 respectively must still conform to the logical memory map that assigns fixed blocks of ad dresses to different strobe spaces An STI RO ARO instruction with ARO 887FFFh results in a STRBO data ac cess data size 16 bits driving the STRBO B2 and STRBO B3 control pins to write the contents of the 32 bit register RO into a 16 bit data location in the lower half of the external memory addressed by 3FFFh Similarly an LDI AR1 R1 instruction with AR1 98FFFFh results in a STRB1 data access data size 8 bits driving the STRBO B3 control pin STRB CONFIG 1 to read the contents of an 8 bit data location in
77. ADDI 2 AR3 ADDI 3 AR4 LDI 4 IRO LDI FFT_SIZE RC LSH 2 RC SUBI 2 RC DSP Algorithms 6 71 Fast Fourier Transforms FFTs Example 6 17 Real Inverse Radix 2 FFT Continued LDF ARA R6 R6 X I4 LDF AR2 R7 R7 X I2 LDF ARI R1 Rl XLI MPYF 2 0 R6 R6 2 X I14 MPYF 2 0 R7 R7 2 X I2 SUBF3 R6 AR3 R5 R5 X I3 2 X I4 SUBF3 R5 R1 R4 R4 X I1 X I3 2X 14 SUBF3 R7 AR3 R5 R5 X I3 2 X I2 STF R4 AR4 IRO x 14 4 ADDF3 R5 R1 R3 R3 X I1 X 1I3 2X I2 ADDF3 R6 AR3 R4 R4 X I3 2 X I4 STF R3 AR2 IRO X I2 4 SUBF3 R4 R1 R4 R4 X I1 X 13 2X 14 ADDF3 R7 AR3 RO RO X I3 2 X I2 STE R4 AR3 IRO X i3 4 ADDF3 RO R1 RO RO X I1 X 13 2X 12 RPTB LOOP1_2 LDF AR4 R6 R6 X I4 STE RO AR1 IRO X I1 MPYF 2 0 R6 R6 2 X I4 LDF AR2 R7 R7 X I2 LDF AR1 R1 Rl X I1 MPYF 2 0 R7 R7 2 X I2 SUBF3 R6 AR3 R5 R5 X I3 2 X I4 SUBF3 R5 R1 R4 R4 X I1 X I3 2X 14 SUBF3 R7 AR3 R5 R5 X I3 2 X I2 STE R4 AR4 IRO X 14 im ADDF3 R5 R1 R3 R3 X I1 X I3 2X I2 ADDF3 R6 AR3 R4 RA X I 2 X I4 STF R3 AR2 IRO X I2 SUBF3 R4 R1 R4 R4 XE X I3 2X I4 ADDF3 R7 AR3 RO RO X I 3 2 X I2 STF R4 AR3 IRO X I3 4 LOOP1 2 ADDF3 RO R1 RO RO X I1 X 1I3 2X I2 STF RO
78. C C t t t t t s c c ax 9 00 l XO LO st CO QU CO C C C C t t t t c ax x lo a8888888 a8888888 B 8 x 2 NVHS 8 x 42 NOHd3 TON O FMON O OQ 00 l COLO st CO QI CO XXXXXEXZXXAiuduuR PEPE Eee Parad 1 2 STRBO B2 STRBO B1 STRBO BO STRBO B3 STRB1 B2 A STRB1 B3 A TMS320C32 CCCCCCC CCCCCCCE RESET SHZ MCBL MP Figure 4 16 32 Bit Memory Configuration STRBO and IOSTRB LEE LLL see NULLLL T oo o Buioejuaju AIOwayy LE v Figure 4 17 32 Bit Memory Configuration STRBO and IOSTRB Logical memory map y STRBO IOSTRB STRBO STRB1 Note 32 bit memory address translation data size memory width STRB Memory Data Logical 2 CONFIG width size Physi ysical address STRBO address control 0 11 11 eee register STRB0 32 bits 32 bits far gt 1 Oh Oh 1 2 2 3 4 io 5 Logical address m Pioo 0000 o E e e 1001 0000 0 Physical address A14 AQ 32766 32766 32767 v 32767 32768 7FFFh 7FFFh 32768 32 bit data size address not shifted IOSTRB address not shifted 810000h Oh 1 2 Logical physical address 3 m gt oeo ooo o a e e
79. C3x uses modular port scan device MPSD technology to allow complete emulation through a serial scan path of the C3x To communicate with the emulator your target system must have a 12 pin header 2 rows of 6 pins with the connections that are shown in Figure 10 1 To use the target cable supply the signals shown in Table 10 1 to a 12 pin header with pin 8 cut outto provide keying For the latest information see the JTAG MPSD Emulation Technical Reference Although you can use other headers the recommended header is the un shrouded straight header having the following DuPont connector systems part numbers 65610 112 65611 112 37996 112 67997 112 Figure 10 1 12 Pin Header Signals and Header Dimensions EMUIT 1 2 GND EMUOT 3 4 GND Header dimensions EMU2t 5 6 GND Pin width 0 095 h square post PD VcO 7 ENIM pin key t Pin length 0 235 in nominal EMUS 9 10 GND H3 11 12 GND t These signals must be pulled up with separate 20 kQ resistors to VCC t While the corresponding female position on the cable connector is plugged to prevent improper connection the cable lead for pin 8 is present in the cable and is grounded as shown in the schematics and wiring diagrams in this document Table 10 1 12 Pin Header Signal Descriptions and Pin Numbers XDS510 Signal Description C30 Pin Number C31 Pin Number EMUO Emulation pin 0 F14 124 EMU1 Emulation pin 1 E15 125 EMU2 Emul
80. CS4215 WORD RESET COD WAIT 50 in temp in out EC t sample rate R ES INIT 4215 INITIALIZE COMMUNICATIONS TO CS4215 NOTE i IS A VOLATILE TO FORCE TIME DELAYS AND TO FORCE READS OF SERIAL PORT DATA RECEIVE REGISTER TO CLEAR THE RECEIVE INTERRUPT FLAG KE EP RE P SET LOW FOR SOME RIOD OF TIME KK KK Ck kk Ck kk Ck Ck kk Kk Kk Ck Ck Ck Ck Ck Ck Ck Ck kk Kk Ck Ck kk kk kk kk ke ke ke ke ke ke ke ke e e ke e e e e kx x f a7 af Kf AU TR Kk kk Ck kk kk kk kk kk kk kk kk ke ke ke ke ke ke ke ke e e e e e e e x x f ET AIC Xf CONFIGURE SE RT 1 RIAL PO KOR KK EK kk ke KG ke ke ke Ge SERIAL POR S S ERIAL PO ERIAL PO Rd RT SERIAL POR d THE FOL SERIAL POR SERIAL POR OWING P ADD ER NUM gcon ADD RN ADD RN ADD RN trol UM s x control UM s r control UM s rxt control I RIOD R EGIST ER VALUE 0x0 C G LKXFUNC LKRFUNC
81. DI DDI DDI DI DI n d UBI L L L A A L L L S SUBF3 ADDF3 N R L S S S A S N 1 2 3 4 lt X I1 5 6 X 14 5 8 9 DEST_ADDR AR1 AR1 AR2 AR1 AR3 4 AR2 6 AR3 8 IRO QFFT SIZE RC 3 RC 2 RC AR2 AR1 R1 AR2 AR1 R2 AR3 R3 LOOP3 A AR2 IRO RO R2 AR1 IRO RO AR1 R1 R1 AR2 IRO RO AR1 R2 R3 AR3 IRO AR3 R3 R2 AR1 R1 AR2 R3 AR3 X I3 X 13 RO X I3 SRI X Il X I3 R2 X I1 X I3 7 R3 X 14 7 x 11 4 x 13 6 50 Example 6 16 Fast Fourier Transforms FFTs Real Forward Radix 2 FFT Continued H Part B 2 ARO AR1 AR2 AR3 ARO nel r2 I3 I4 v v v vyv y LDI LSH LDI SUBI LDI LDI LDI LDI LDI ADDI ADDI ADDI ADDI LDI MPYFE3 MPYFE3 ADDF3 MPYFE3 SUBF3 SUBF3 ADDF3 UBF3 E DDF3 Po RPTB MPYFE3 STF ADDF3 MPYF 3 0 1 X I1 X I3 COS X I4 COS 2 3 X I1 X I3 COS X I4 COS 4 5 X I2 X I3 COS X I4 COS 6 7 X I2 X I3 COS X I4 COS 8 9 NOTE COS 2 pi 8 SIN 2 pi 8 QFFT SIZE RC 3 RC RC IR1 3 RC 8 IRO DEST_ADDR ARO ARO AR1 ARO AR2 ARO AR3 1 AR0 3 AR1 5 AR2 7 AR3 QSINE TABLE AR7 Initialize table pointers
82. GLOBAL VARIABLES Le f extern int buffer size SIZE OF I O BUFFER S extern VPVF output0 OUTPUT DATA BUFFER FOR PROCESSOR extern VPVF input0 INPUT DATA BUFFER FOR PROCESSOR extern VPVF output xfer0 OUTPUT DATA BUFFER FOR ISR AIC extern VPVF input xfer0 INPUT DATA BUFFER FOR ISR AIC extern VPVF outputl OUTPUT DATA BUFFER FOR PROCESSOR extern VPVF inputl INPUT DATA BUFFER FOR PROCESSOR K extern VPVF output xferl OUTPUT DATA BUFFER FOR ISR AIC extern VPVF input xferl INPUT DATA BUFFER FOR ISR AIC extern VI buffer rdy CPU ISR COMM FLAG INPUT KJ extern VI buffer_index INDEX INTO INPUT AND OUTPUT DATA ARRAYS extern VI i GENERIC COUNTER VARIABLE extern VI first half extern CS4215 WORD data control BK KK HK IK kk kk kk kk kk kk kk kk kk kk kk kk kk kk kk kk kk ck kk kk kk kc ke kc I kc ke kk koe kk ke ke ke ke e e e x f FUNCTION PROTOTYPES ay OK IK IK I I IK I I I I I I kk I kk I kk I kk I I I I I kc I I I I I I I I I ke ke ke x f KK IK kk IK I IK I ke ke ke ke ke e e e x x CS4215 DRIVER FUNCTIONS BRK KK kk kk ke ke ke ko ke kc ke ko ke ke ke e e e e x void init arrays int buffer size void init 4215 int crystal int sample rate if SER NUM void c int07 void else void c_int05 void endif RK KK HK Ck Ck kk kk kk kk ke kk kk kk kk kk kk kk kk kk kk ke kc ke kc kk ke kc ke ke ke kc ke kc ke kc ko kc k kc ke ko I k
83. IE OR 2000H ST LDI CONTROL RO STI RO ARO SERIAL PORT INITIALIZATION LDI SRCTRL RO sS STI RO AR1 3 LDI STPERIOD RO sS STI RO AR1 6 LDI STCTRL RO sS STI RO AR1 4 LDI SGCCTRL RO S STI RO AR1 BU END ERIAL PORT RECEIVE INT RRUPT DMA GLOBAL CONTROL REG ADDRESS DMA GLOBAL CONTROL REG INITIALIZATION DATA SOURCE ADDRESS SERIAL PORT INPUT REG DATA DESTINATION ADDRESS NUMBER OF WORDS TO TRANSFER IE REGISTER VALUE DMA RESET DATA ARRAY LOCATED IN BSS SECTION THE UNDERSCORE USED IS JUST TO MAKE IT ACCESSIBLE FROM C OPTIONAL LOAD DATA PAGE P OINTER SPORT DMA SPORT iT ZE IA TIME DMA S POINT TO DMA GLOBAL CONTROL REGISTER OURCE ADDRESS REGISTER IALIZE ESTINATION ADDRESS REGISTER IALIZE c D ENABLE IN CGH ENABLE CP ERIAL PORT ERIAL PORT ERIAL PORT INITIALIZ RRUP INTERRUPTS GLOBALLY D RANSFER COUN ER REGISTER OBAL CONTRO B EGISTER START DMA T ER ERIAL PORT RECEIVE CONTROL REG INI IALIZATION IMER P ERIOD INITIALIZATION IM ER CONTROL
84. INITIALIZE TMS320C30 u void init c30 void Analog Interface Peripherals and Applications 8 47 CS4215 Interface to the TMS320C3x Example 8 14 Commarvr c Continued ERROR_IN_REA BUS_ADDR gt exp_gcontrol 0x0 BUS_ADDR gt prim_gcontrol INIT_XF_PINS NABLE_CACHE 0x0 TIM EQ ER PROCI ERROR HANDLI I O for IM F Be BKK HK kk kk kk kk kk kk kk kk kk kk kk kk kk kk kk kk kk ke kk kk ke kk ke kk kk kc ko kc ko kc k kc ko kc k kc k kk ke ke ke ke ke e e x f void error in real time void ESSING TIME IS GR EATER J KCKCKCKCkCkCk kk kk kk I kk kk kk I kk kk kk kk kk kk kk kk kk kk kk ck kc kc kc kc I I ok ckok ck ok ck ok ckok ckok koe ke ke x 8 48 CS4215 Interface to the TMS320C3x Example 8 15 CS4215 h KR KK KR A A A KCkCkCk kCk KCk KCKCKCk A KCKCKCk KCKCKCk KCKCKCk KCkCKCk KCk Ck Ck K ck k ck k ckck ck ck ck ck ck k ok sk e sk X ke x ke I f CS4215 H TMS320C3x CRYSTAL 4215 MM CODEC x fe TMS320C3x CODE Leor B
85. R2 STF R4 AR4 X I4 ADDF3 AR1 R2 R4 RA X I1 R2 STF R4 XAR2 3 X I2 tM RPTB IN BLK LDF ARO IR1 R3 PYF3 AR4 R3 R4 STF R4 AR1L X I1 4 MPYF3 AR3 R3 R1 MPYF3 ARO AR3 RO SUBF3 R1 R0 R3 PYF3 ARO IRO AR4 RO ADDF3 RO R4 R2 SUBF3 AR2 R3 R4 ADDF3 AR2 R3 R4 STF R4 AR3 SUBF3 R2 AR1 R4 STF RA AR4 DSP Algorithms 6 59 Fast Fourier Transforms FFTs Example 6 16 Real Forward Radix 2 FFT Continued IN BLK ADDF3 AR1 R2 R4 STE RA AR2 LDF ARO IR1 R3 MPYF3 AR4 R3 R4 STE R4 AR1 MPYF3 AR3 R3 R1 MPYF3 ARO AR3 RO SUBF3 R1 R0 R3 LDI R6 IR1 ADDF3 RO R4 R2 SUBF3 AR2 R3 R4 ADDF3 AR2 R3 R4 STF RA AR3 IR1 SUBF3 R2 AR1 R4 STE R4 AR4 IR1 ADDF3 AR1 R2 R4 STF RA AR2 IR1 STF RA AR1 IR1 SUBI3 AR5 AR1 RO CMPI QFFT_SIZE RO BLTD INLOP LOOP BACK TO THE INNER LOOP LDI QSINE TABLE ARO ARO POINTS TO SIN COS TABLE LDI R7 IR1 LDI R7 RC ADDI 1 R5 CMPI QLOG SIZE R5 BLE LOOP LDI DEST_ADDR AR1 LSH 1 IRQ LSH L R7 Return to C environment POP DP Restore C environment variables POP AR7 POP AR6 POP AR5 POP ARA POPF R7 POP R7 POPF R6 POP R6 POP R5 POP R4 POP FP RETS end 6 60 Fast Fourier Transforms FFTs Example 6 17 shows the implementation of a radix 2 real inverse F
86. RAM ma 0x900000 0x8000 RAM 7 OxF0000 H 0x00000 E Define memory configuration Inform debugger that this section holds code text No code here STRBO On chip Peripheral Bus Control DMA Peripheral Bus Control Timers Peripheral Bus Control Serial Port 0 Peripheral Bus Control External Memory Interface STRB1 Make emulator aware of this memory configuration Set STRBO control register to 32 bit memory width 32 bit data size Set STRB1 control register to 8 bit memory width 8 bit data size Configure STRBO and STRB1 control registers before loading code 8 Bit Static Memory Allocation 4 78 This section provides examples of 8 bit static buffer allocation and associated linker configuration The debugger batch file is identical to the batch file in Example 4 3 and therefore is not shown The C code in Example 4 4 demonstrates the static allocation of two buffers 1K and 4K 8 bit words by defining a user section called mydata8 This sec tion is used to hold a structure consisting of two arrays of data values How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface Example 4 4 8 Bit Static Buffer Allocation pragma DATA SECTION buffer8 mydata8 struct bufferStruct in 1024 out 4096 buffer8 void main Configure the STRBO control register for 32 bit wide memory 32 bit data size 0x808064 OxF0000 C
87. STRBO_B3 A 1 STRBO_B2 A 2 STRBO B1 STRBO BO 16 bit data bus Memory bank 32 bits wide ii 16 i 8 ip 8 Data A14 A14 Data Al14 Data A13 A13 A13 s spas TMS320C32 e e 5 E A2 A2 2 n c a2 So Al Al A1 AO AO cs H c Ao CS m bank STRBO B3 A 1 L1 16 bits wide STRBO B2 A 2 STRBO B1 STRBO BO 8 bit data bus Q Memory bank Data A14 lt 8 bits wide A13 e e TMS320C32 A2 A1 AO STRBO B3 A 1 STRBO B2 A 2 STRBO B1 STRBO BO Note For external memory used during normal program execution the amount of external address shift depends only on the width of the memory bank Memory Interfacing 4 101 Booting a TMS320C32 Target System in a C Environment 4 8 6 Host Load While some DSP systems stand alone others may be embedded DSPs con trolled by a host such as a microcontroller or another DSP During system power up the DSP boot table may be transferred from the host to the DSP through a serial port or through a byte wide latch This eliminates the need for a dedicated boot EPROM on the DSP side of the system On the host side the DSP boottable may be temporarily stored in an EPROM priortothe DSP boot Following
88. Speech Communication Reading MA Addison Wesley 1987 References Image Processing Andrews H C and Hunt B R Digital Image Restoration Englewood Cliffs NJ Prentice Hall Inc 1977 Gonzales Rafael C and Wintz Paul Digital Image Processing Reading MA Addison Wesley Publishing Company Inc 1977 Pratt William K Digital Image Processing New York NY John Wiley and Sons 1978 Multirate DSP Crochiere R E and Rabiner L R Multirate Digital Signal Processing Englewood Cliffs NJ Prentice Hall Inc 1983 Vaidyanathan P P Multirate Systems and Filter Banks Englewood Cliffs NJ Prentice Hall Inc Digital Control Theory Dote Y Servo Motor and Motion Control Using Digital Signal Processors Englewood Cliffs NJ Prentice Hall Inc 1990 Jacquot R Modern Digital Control Systems New York NY Marcel Dek ker Inc 1981 Katz P Digital Control Using Microprocessors Englewood Cliffs NJ Prentice Hall Inc 1981 Kuo B C Digital Control Systems New York NY Holt Reinholt and Winston Inc 1980 Moroney P ssues in the Implementation of Digital Feedback Compensa tors Cambridge MA The MIT Press 1983 Phillips C and Nagle H Digital Control System Analysis and Design Englewood Cliffs NJ Prentice Hall Inc 1984 Adaptive Signal Processing Haykin S Adaptive Filter Theory Englewood Cliffs NJ Prentice Hall Inc 1991 Widrow B and Stear
89. TLC320AD58 Interface to the TMS320C3x 8 5 TLC320AD58 Interface to the TMS320C3x The TLC320AD58C serial interface provides several master and slave modes for 16 bit or 18 bit data output This allows it to be compatible to a wide range of DSPs To interface with the C3x 32 bit floating point DSP the 18 bit master mode 100 was chosen to get an 18 bit resolution result and meet the C3x serial port requirements The timing diagram is shown in Figure 8 9 Figure 8 9 TLC320AD58C Serial Interface 18 bit Master Mode 100 Timing Diagram E 64 SCLKs S INNZNVZAUN VA TDS FSYNC N Right channel MSB LRCLK y Left channel MSB f pour X39X s COGN COGN X Sg2SCLKs 8 30 f C3x serial port receive interrupt C3x serial port 32ScCLKsT receive interrupt The frame sync signal FSYNC is then used to designate valid data from the ADC and is active for one shift clock period After the falling edge of FSYNC the left channel data is shifted out on the falling edge of SCLK with the MSB D17 first When the last data bit is shifted out the output remains low for another 14 SCLKs to get a total of 32 SCLK periods each channel After 32 SCLKs LRCLK goes low and the right channel data is then shifted out FSYNC and LRCLK frequency are fixed to the sampling frequency Fs MCLK 256 or MCLK 384 depending on the status ofthe CMODE input pin The conversi
90. The strobes are mapped to selected portions of the memory map as shown in Figure 4 10 on page 4 23 For example if the CPU is reading data from location 881234h the active strobe during the read bus cycle is STRBO Unlike the other two strobes STRBO is assigned to two noncontiguous address spaces within the memory map to provide extra flexibility in address decoding for glueless memory inter faces The behavior of IOSTRB is similar to that of its counterpart in the C30 Its tim ing characteristics are slightly relaxed in comparison with STRBO and STRB1 cycles to better accommodate slower O peripherals In contrast to STRBO and STRB1 IOSTRB uses a single signal line and accesses the external data one full 32 bit word at a time STRBO and STRB1 are composed of four signal lines each The multiple signal lines per strobe enable the STRBO and STRB1 Cycles to access external memory one byte one half word or one full word at atime For example to read a single byte from a 32 bit wide external memory location mapped to STRBO the address on the address bus points to the se lected 32 bit word and only one STRBO signal is activated driven low to select the desired byte To access two bytes of data at the memory location mapped to STRB1 two STRB1 signal lines are asserted during the bus cycle Full 32 bit bus cycles involving STRBO or STRB1 memory space result in four strobe signals simultaneously accessing four bytes of data The 3
91. Time slo signed in Time slo unsigned in unsigned in Time slo unsigned in unsigned in unsigned in unsigned in Time slo unsigned in unsigned in unsigned in ct ct ct ct ct ct ct ct ct ct ct ck ct intval 2 ct ct ct ct ct ct ck cb cr ck ct GE GE Et oct 7 lg is ovr pio 6 ro se d rz 5 lo le he s 4 d x2 3 7 right s 2 d r1 1 left 8 rg ma 7 lg is ovr pio 6 ro se d r3 NRPS EM NRPS EM RO M89 Left input gain settings Input selection Overange Parallel I O bits Right output attenuation setting Speaker output enable control Unused don t care bit 7 Left output attenuation setting Parallel output enable control Headphone output enable control Unused don t care bits 0 7 Right channel 8 bit Unused don t care bits 0 7 Left channel 8 bit Right input gain settings Monitor path selection Left input gain settings Input selection Overange Parallel I O bits Right output attenuation setting Speaker output enable control Unused don t care bit 7 kf S xj A xf 8 52 Example 8 15 CS4215 h Continued CS4215 Interface to the TMS320C3x Time slot 5 unsigned int lo 26 Left output attenuation setting x unsig
92. Two banks of different memory widths must not be connected to the same STRB without external decode logic Different memory widths require STRBx Bx signals to be configured as address pins These address pins are active for any external memory access that is STRBO STRB1 IOSTRB and program fetches 8 bit Dynamic Memory Allocation This section contains C code examples of 8 bit dynamic buffer allocation link er configuration and a debugger batch file Example 4 1 demonstrates the allocation of two buffers 1K and 4K 8 bit words using the 8 bit dynamic memory allocation routines Example 4 1 8 Bit Dynamic Buffer Allocation void main int bufferl float buffer2 Configure the STRBO control register for 32 bit wide memory 32 bit data_size 0x808064 OxF0000 Configure the STRB1 control register for 8 bit wide memory 8 bit data size 0x808068 0x00000 Allocate 1K 8 bit words in the 8 bit memory pool bufferl malloc8 1024 sizeof int Allocate 4K 8 bit floats in the 8 bit memory pool buffer2 malloc8 4096 sizeof float Process buffers callDSPoperation bufferl buffer2 Free buffers free8 buffer2 free8 bufferl p BB e leelelrl Note The TMS320 floating point C compiler sizeoffunction returns 1 for both inte ger and float data types 4 76 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory I
93. You need a JTAG emulation conversion cable See the TMS320C3x C Source Debugger User s Guide for detailed information on the C3x emulator Evaluation module EVM Each EVM comes complete with a PC halfcard and software package The EVM board contains the following B A C30 and a 33 MFLOPS 32 bit floating point DSP B A16K word zero state SRAM allowing coding of most algorithms di rectly on the board B A speaker microphone ready analog interface for multimedia speech and audio applications development B A multiprocessor serial port interface for connecting to multiple EVMs B A host port for PC communications The system also comes with all the software required to begin applications development on a PC host Equipped with a C and assembly language source level debugger for the DSP the EVM has a window oriented mouse driven interface that enables the downloading executing and de bugging of assembly code or C code Development Support and Part Ordering Information 11 3 Development Support The C3x assembler linker is also included with the EVM For users who prefer programming in a high level language an optimizing ANSI C com piler and an Ada compiler are offered separately Lj Emulation porting kit EPK Enables you to integrate emulation technolo gy directly into your system without the need of an XDS510 board The EPK is intended to be used by third parties and high volume board manufacturers and requires a l
94. generating 4 86 assembler 4 87 compiler 4 87 linker 4 88 out file 4 90 loading to the target system 4 91 communications primary 8 25 secondary 8 25 companding 6 2 to 6 6 compiler 11 2 compression A law 6 5 u law 6 3 computed GOTO 2 22 connector 12 pin header 10 2 mechanical dimensions 10 8 to 10 9 context switching 2 11 context restore for C3x 2 15 to 2 17 context save for C3x 2 13 to 2 14 control registers STRBO and STRB1 4 23 conversion time to frequency domain 6 28 converters A D AD1678 8 2 interface to the C30 expansion bus 8 210 8 5 read operations timing between the C30 and AD1678 8 4 Burr Brown DSP101 2 and DSP201 2 interface to C3x 8 10 to 8 20 D A interface to the C30 expansion bus 8 6 timing diagram for write operation 8 8 CS4215 interface to the C3x 8 39 to 8 65 current calculations 12 24 to 12 26 average 12 25 12 26 data output 12 25 processing 12 24 Index data objects linking C separate from bss 5 13to 5 15 DATA SECTION pragma directive 4 70 debugger 11 3 boot 4 91 RAM model linker cr option 4 92 ROM model linker c option 4 92 configuration for C32 external memory 4 73 delayed branches 2 17 development support 11 1 to 11 10 development support tools 11 2 to 11 6 bulletin board service 11 6 code generation tools 11 2 assembler linker 11 2 C compiler 11 2 linker 11 2 documentation 11 5 hotline 11 5 literature 11 5 seminars 11 5 System integration and de
95. high because when outputs are in the logic 0 state the device is sinking cur rent that is supplied from an external source The power dissipation from this current factor does not have a contribution through Ipp but contributes to pow er dissipation with a magnitude of P VoL x lor where Voy low level output voltage lo current being sunk by the output as shown in Figure 12 13 The power dissipation factor from outputs that are driven low must be calcu lated and added to the total power dissipation When outputs with dc loads are switched the power dissipation factors from outputs being driven high and outputs being driven low are averaged and add ed to the total device power dissipation You should calculate power factors from dc loading of the outputs separately for each program segment before you calculate average power Any unused inputs that are left disconnected may float to a voltage level that causes input buffer circuits to remain in the linear region and therefore contrib ute a significant factor to power supply current Accordingly you should deacti vate any unused inputs by grounding them or pulling them high if you desire absolute minimum power dissipation If you must pull several unused inputs high pull them high together using one resistor to minimize component count and board space Calculation of Total Supply Current When you use power dissipation values to determine thermal requirements
96. n 1 h n N 1 x n N 1 The filter coefficients are time dependent and updated through LMS algo rithms In a LMS algorithm the coefficients are updated by an equation in this form h n 1 i h nii Be n x n i i 0 1 N 1 where c n d n y n B is a constant for the computation and d n is the de sired signal You can interleave the updating of the filter coefficients with the computation of the filter output so that it takes three cycles per filter tap to do both The updated coefficients are written over the old filter coefficients DSP Algorithms 6 15 FIR IIR and Adaptive Filters Example 6 8 shows the implementation of an adaptive FIR filter on the C3x The memory organization and the positioning of the data in memory follows the same rules that apply to the FIR filter described in section 6 2 1 on page 6 7 Example 6 8 Adaptive FIR Filter LMS Algorithm LMS LMS ADAPTIVE FILTER EQUATIONS y n h n 0 x n h n 1 x n 1 h n NE1 x nt NE1 e n d n y n for i 0 i lt N i h n 1 i h n i mu e n x nti TYPICAL CALLING SEQUENCE load R4 load ARO load ARI load AR6 load RC load BK CALL FIR ARGUMEN ASSIGNMENTS ARGUMEN FUNCTION R4 scale factor 2 mu err ARO address of h n N 1 AR1 address of x nt Nt1 AR6 address of d n RC length of f
97. read data prg pointer AR5 write data prg pointer read gt R1 gt write IRO EXEC start flag stack 808024h TIMO cnt reg IR1 EXEC start address 808028h TIMO per reg IOSTRB 808004h DMAO dst reg R3 data size STRBO 808006h DMAO dst reg R5 mem width STRB1 808008h DMAO cnt reg TMS320C32 Boot Loader Program B 7 Boot Loader Source Code Listing R6 memory read value F Xx AR6 R7 R0 BK scratch registers reset word start Space 44h reset vector program starts 45h Initialize registers 808000h gt AR7 808023h gt SP I TRO AR start LDI 4040h AR7 load peripheral memory map LSH 9 AR7 base address 808000n LDI 23h SP initialize stack pointer to OR AR7 SP 808023h timer counter 1 LDI 1 IRO0 reset exec start addr flag Test for INT3 and if set exclusively proceed with serial boot load Else load AR3 with 1000h if INTO 810000h if INT1 900000h if INT2 Also load the appropriate boot strobe pointer and force the boot strobe value to reflect 32 bit memory width If INTO or INT1 or INT2 and INT3 turn on the handshake mode waitl LDI IF RO AND OFh RO Clean CMPI 8 RO0 test for INT3 BEQ serial 7 serial boot load mode LDI AR7 AR2 ADDI 60h AR2 808060h IOSTRB gt AR2 TSTB 2 R0 test for INT1 LDINZ 4080h AR3 810000h 2 9 BNZ exi
98. the requirement for generating an analog output signal is a consequence of sampling an analog waveform with an ADC so that it can be processed digitally This digitally processed signal is then reproduced with a digital to analog converter DAC Interfacing the DAC to the C30 on the expansion I O bus is also straightforward Various types of DACs may be distinguished by whether or not the converters include Latches to store the digital value to be converted to an analog quantity The interface to control those latches When latches and control logic are included interface design is often simpli fied however internal latches are often included only in slower DACs Although slower converters limit signal bandwidth the converter design described in Figure 8 3 allows a reasonably wide range of signal frequencies to be processed and illustrates the technique of interfacing to a converter that uses external data latches Figure 8 3 shows an interface to an Analog Device AD565A DAC This device is a 12 bit 250 ns current output DAC with an on chip 10 V reference Using an off chip current to voltage conversion circuit connected according to the manufacturer s specifications the converter exhibits output signal ranges of 0 10 V which is compatible with the conversion range of the ADC discussed in the previous section Because this DAC essentially performs continuous conversions based on the digital value provided at its input
99. 1 C Compiler Interaction With the TMS320C32 Memory Interface The C32 s internal 32 bit architecture allows the C compiler s data types to re main 32 bits wide However the C compiler s runtime support library includes pragma directives and new dynamic allocation routines malloc realloc cal loc bmalloc free etc that support the creation of data sections These data sections serve as memory pools for storing 8 and 16 bit data These sections can reside in 8 16 and 32 bit wide memory The programmer must ensure that the appropriate strobe control register is loaded with the correct data size and memory width The C32 s memory interface truncates packs or unpacks the data in the manner specified by the settings of the strobe control register Table 4 7 lists the data sizes supported by the sections created by the C com piler Table 4 7 Data Sizes Supported by Sections Created by the C Compiler Section Type Initialized Uninitialized 32 Bits 16 Bits 8 Bits text user section user section Cinit const user section bss sysm16 SYSm8 Stack user section user section Sysmem User_section Memory Interfacing 4 69 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface The contents of the named sections are as follows text executable code and or string literals Cinit tables for variable and constant initialization const string literals and switch tables bss glob
100. 12 23 Example Supply Current Calculations 12 5 Example Supply Current Calculations 12 5 1 Processing 12 24 A fast Fourier transform FFT is a typical DSP algorithm The FFT code in the example calculation processes data in the RAM blocks and writes the result out to zero wait state external SRAM on the primary bus The program executes out of zero wait state external SRAM on the primary bus and enables the C30 s cache The entire algorithm consists mainly of internal bus operations and includes quiescent current and internal operations At the end of processing the 1024 results are written to the primary bus Therefore the algorithm exhibits a higher current requirement during the write portion where the external bus is used significantly The processing portion of the algorithm is 9596 of the FFT execution During this portion the power supply current is required only for the internal circuitry Data is processed in several loops During these loops two operands are transferred on every cycle The current required for internal bus operations is 55 mA see section 12 2 2 on page 12 5 The data is assumed to be ran dom A data value scale factor of 0 8 is used from Figure 12 3 on page 12 7 This value scales 55 mA yielding 44 mA for internal bus operations Adding 44 mA to the quiescent current requirement and internal operations current requirement yields a current requirement of 209 mA for the major portion ofthe algorithm
101. 15 8 lt D 7 0 r The external memory address pins A414443 A1A9 are mapped to the C32 s A22A13A12 A1Ao pins This mapping was selected to position the system stack immediately after the C32 s internal RAM Performance is improved be cause the top of the stack resides in internal RAM and the stack is allowed to grow into external RAM With this mapping external memory accesses in the range 4000h through 7FFFh read or write 16 bit data memory accesses in the range Oh through 3FFFh read or write 32 bit data The PRGW pin controls the program fetches Figure 4 35 shows the contents of external memory Because of the address shift of the C32 s external memory interface the memory map for the C32 CPU is slightly different see Figure 4 36 Memory Interfacing 4 81 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface Figure 4 35 External Memory Map Physical address Contents Oh System stack area 1FFFh 8K x 32 bits 2000h Program word 0 Program word 1 3FFFh Program word 8191 4000h Datat Data 4001h Data3 Data2 7FFFh Data32767 Data32766 Note For 32 bit data physical address logical address For 16 bit data physical address logical address shifted left by 1 4 82 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface Figure 4 36 TMS320C32 Memory Map s Contents Oh 2000h Program
102. 18 SFFT ASM Continued bigval SOrctrl word 0x00000111 7 NewMnsOld word 0 K1 Set 0 99995 K2 float pow K1 N E FILTEROUT float 0 0 F Scale float 4 0 N REAL VEC float cos pi ANGLE 180 0 IMAG VEC float sin pi ANGLE 180 0 FLOG2SC float pow 2 0 24 0 A word 0x00010000 Use a value slightly less than 1 0 K1 N oldest sample scale factor Temp storage for SFFT filter output SFFT growth scale factor filtered REAL scale factor filtered IMAG scale factor Scale factor for log2 calculations Used in overflow mode saturation When an receiv data delay line buffer The main loop consists of waiting for interrupt occurs the followed by the SFFT and output routines 7 Four dummy writes to the external bus have been added in the main loop to allow real time benchmarking of the three functions using a new ADC sample 7 new data is loaded into the and oscilloscope to monitor the address bus LSB s f T Start CODE 0x809E40 Start in last 512 words of RAMO Sect CODE also includes DSK kernel main ldi OxE4 IF E Enable XINT RINT INT2 idle 7 Wait for Receive Interrupt ldi SO_rdata RO The first interrupt occurs shortly ldi O RO after AIC init is complete which Sti RO SO_xdata will not leave enough time for SFFT rd loop idle Wait for Receive Interrupt sti RO Ox80
103. 3 1 Use of TSTB for Software Controlled Interrupt TITLE USE OF TSTB FOR SOFTWAREtCONTROLLED INTERRUPT IN THIS EXAMPLE ALL INTERRUPTS HAVE BEEN DISABLED BY RESETTING THE GIE BIT OF THE STATUS REGISTER WHEN AN INTERRUPT ARRIVES IT IS STORED IN THE IF REGISTER THE PRESENT EXAMPLE ACTIVATES THE INTERRUPT SERVICE ROUTINE INTR WHEN IT DETECTS THAT INT2 HAS OCCURRED TSTB 0100b IF Check if bit 2 of IF is set CALLNZ INTR H and if so call subroutine INTR 3 2 Bit Manipulation Example 3 2 Copy a Bit From One Location to Another TITLE COPY A BIT FROM ONE LOCATION TO ANOTHER BI I OF R1 NEEDS TO BE COPIED TO BI J OF R2 ARO POINTS TO A LOCATION HOLDING I AND IT IS ASSUMED THAT THE NEXT MEMORY LOCATION HOLDS THE VALUE J L R1 R2 I ARO J ARO 1 LDI 1 R0 LSH ARO RO H Shift 1 to align it with bit I TSTB R1 RO Test the Ith bit of R1 BZD CONT H If bit 0 branch delayed LDI 1 R0 LSH ARO0 1 RO Align 1 with Jth location ANDN RO R2 B If bit 0 reset Jth bit of R2 OR R
104. 32 use the above memory e e e b LINKER command file e e e heap 0x4000 set the size of the dynamic 32 bit memory section e e e STRB_RAM org 0x1000 len 0x8000 define physical 32 bit memory e e e sysmem gt STRB_RAM assign logical section to physical memory e e e TMS320C32 C31 C30 Deun 32 bit wide STRB memory bss text C 4 Memory Access for C Programs Figure C 3 Dynamic Memory Allocation for TMS320C32 One Block of 16 Bit Memory a C code e e int BUFFER_16 declare a pointer to a pool of 16 bit memory e e 0x808064 0x5000 STRBO control register data size 16 memory width 16 eo e BUFFER_16 MALLOC16 1024 sizeof int allocate 2K half words of memory dsp_func4 BUFFER_16 use the above memory e e e BUFFER_16 MALLOC16 512 sizeof int allocate 1K half words of memory dsp func5 BUFFER 16 use the above memory e e e BUFFER_16 MALLOC8 2048 sizeof int allocate 4K half words of memory dsp func6 BUFFER 16 use the above memory L e e b LINKER command file e e e heap 16 0x4000 set the size of the dynamic 16 bit memory section e LJ L STRBO RAM org 0x880000 len 0x8000 define physical 16 bit memory e e SYSm16 gt STRBO RAM assign logical section to physical memory e e c C32 external memory
105. 4X for 1 5 V analog in put 1 1 1X for 6 V analog input Format D7 D6 D5 D4 D3 i X TA register value unsigned X RA register value unsigned o 0 RA register value signed 2s complement RB register value unsigned 4 39 Control register AUX IN pins 0 disables 1 enables Loopback function 0 disables 1 enables D2 D 1 DO 1 0 1 1 Bandpass filter 0 deletes 1 inserts The assembly code in Example 8 6 sets the TA and TB registers of the AIC This code transmits a 16 bit word to the AIC and then waits until the transmit interrupt is generated by the serial port Four commands are transmitted start ing with a 0 then the TB and RB values followed by the TA and RA values and finally the control word TA and RA values should be the last values trans mitted since they change the AIC sample rate By transmitting these values last the sample rate is not changed until the AIC receives the last program word In this way very high sample rates can be achieved Each command transmits three 16 bit words a primary communication a secondary commu nication and a zero data word 8 26 Example 8 6 Setting the TA and TB Registers TLC32040 Interface to the TMS320C3x the TLC32040 RAMPEN 1 LOOPAIC ASM is an example program which shows how to initialize and use The analog output or a loopback of the analog input DAC output RAMPEN 0 is ei
106. 5 12 2 8 Internal Operations nan ei a tenes 12 5 12 2 3 Internal Bus Operations ss crisi aisir crn nee ees 12 5 12 3 Current Requirement for Output Driver Circuitry 000 e eee eee 12 9 12 3 4 Primary Bus Current 4 12 10 12 3 2 Expansion Bus Current eT i eens 12 13 12 3 8 Data Dependency Factors pp 12 14 12 3 4 Capacitive Load Dependence pp 12 16 12 4 Calculation of Total Supply Current es 12 17 12 4 4 Combining Supply Current from All Factors si 12 17 12 4 2 Supply Voltage Operating Frequency and Temperature Dependencies c cece eee eens 12 18 12 4 3 Total Current Equation Example 00 cece eee ees 12 19 12 4 4 Peak Versus Average Current pp 12 20 12 4 5 Thermal Management Considerations pp 12 21 Contents xix Contents XX 12 5 Example Supply Current Calculations pp 12 24 12 5 1 Processing 4 iod oci ev eich de diode Ro oe ens E en aes Peele UR E ende EA 12 24 12 5 2 Data Output sr nai nn R eee WO ARR Rot uas 12 25 12 5 8 Average Current i 12 25 12 5 4 Experimental Results 0 12 26 TMS320C32 Boot Table Examples nnne A 1 Provides boot table examples for the C32 TMS320C32 Boot Loader Operations 4 B 1 Describes the on chip boot loader program that initializes the DSP system after power up or reset of the C32 B 1 TMS320C32 Boot Loader Source Code Description i B 2 B 2 TMS320C32 Boot Loader Opcodes pp B 4 B 3 Boot Loader Source Code Listing pp B
107. 5 Address Translation for 8 Bit Data Stored in 32 Bit Wide Memory a amp a CPU instruction STI RO FFFh DP 01 9 m o STRB Memory Data EE STRBO config width size 00 o n 0o 0 i 01 Memory ma Logical address contro eee 0 rrr TTHSP d space register uL 0 0 10 Y TRB 2 bi i 11 STRBO Oh S 0 32 bits 8 bits b3 Bs pi Oh w STRB enable b7 b6 b5 th 2h Logical address 23 to 0 bit bio b9 2h EM n EEEEEEREEEE b15 b14 b13 an b4 olololololol o o oI ETE 1 IOSTRB m PES B e e e TTY a o EH TT fa a 4 a 4 a a a a alalajia lb131069 1FFFCh b131060 b131059 b131058 b131057 7FFCh i b131070 1FFFDn Physical address 23 to 72 b131064 b131063 b131062 b131061 7FFDh STRBO 1 B131071 1FFFEh Memory address 14 to 0 EHREBBHBHBEEEEREB b131068 b131067 b131066 b131065 7FFEh STRB1 LTFFFFP L SEIZ b131071 b131070 b131069 7FFFh Memory address space 32 bit data bus Logical address d shift 1 bit N A13 A13 A13 8 bit data size m z A 4 e o o o S e E e E e E e o o o Bo A2 A2 A2 dg A1 A1 A1 m AO CS A0 CS A0 CS g STRBO B3 D g STRBO B2 HB g STRBO B1 H STRBO B0 O nuuuu Note The amount of shift between logical and physical addresses depends only on the size of data bein
108. 6 Memory Access for C Programs sseseeeeeeeee een nn nnn nnn C 1 Describes two memory models used to access data when programming in C Memory Interface and Address Translation 4 D 1 Describes the memory interface and address translation for the C32 Ld d odd dg o d N Figures Reset CIrCult 00 1 3 Interrupt Generation Circuit for Use With IDLE2 Operation i 1 9 System Stack Configuration er ee a eee 2 5 Implementations of High to Low Memory Stacks i 2 7 Implementations of Low to High Memory Stacks i 2 7 Long Division and SUBC Method i 3 7 Possible System Configurations 1 4 2 External Interfaces on the TMS320C3x i 4 3 TMS320C3x Interface to Cypress Semiconductor s CY7C186 CMOS SRAM 4 7 Read Operations Timing 0 0 c cece cece nee eee naene 4 8 White Operations TIMING ius seek eR RR RE eed RR beeen nated ee E a d A es 4 8 Circuit for Generation of Zero One or Two Wait States for Multiple Devices 4 14 Bank Switching for Cypress Semiconductor s CY7C185 SRAM 4 17 Bank Memory Control Logic a 0 0 c cece teen eee eee 4 18 Timing for Read Operations Using Bank Switching i 4 19 STRBO and STRB1 Control Registers and the PRGW Pin i 4 23 STRBO and STRB1 Data Access Data Size Memory Width
109. 800 336 5236 ext 3904 11 1 4 TMS320 Literature 11 1 5 DSP Hotline Extensive DSP documentation is available including data sheets user s guides and application reports In addition DSP textbooks that aid research and education have been published by Prentice Hall John Wiley and Sons and Computer Science Press To order literature or to subscribe to the DSP newsletter Details on Signal Processing for up to date information on new products and services call the Literature Response Center at 800 477 8924 or log on to the DSP Solutions web site at http Avww ti com dsps For answers to TMS320 technical questions on device problems develop ment tools documentation upgrades and new products you can contact the DSP hotline by Phone at 281 274 2320 Monday through Friday from 8 30 a m to 5 00 p m Central Time Fax at 281 274 2324 Electronic mail at dsph 2ti com European fax at 33 1 3070 1032 L L L L Semiconductor Product Information Center PIC at 214 644 5580 Development Support and Part Ordering Information 11 5 Development Support To ask about third party applications and algorithm development packages contact the third party directly See the TMS320 Third Party Support Refer ence Guide for addresses and phone numbers The DSP hotline does not provide pricing information Contact the nearest TI field sales office orthe TI PIC for prices and availability of TMS320 devices and suppo
110. 900 028 4 900 001 o0 900 029 0 900 002 pg 900 02A 0 900 003 o0 900 02B 0 900 004 Fg 900 02C 900 900 005 900 900 02D 904 900 006 00 900 02E 81 900 007 49 900 O2F 00 900 008 rg 900 030 60 900 009 49 900 031 rg 900 00A 05 900 032 900 900 00B F 900 033 oo Block 2 900 00C rg 900 034 ital 810 400 BBCC DDI 900 00D 10 900 035 DD 810 401 BBCC DD22 900 O0E 00 900 036 cc 810 402 BBCC DD33 900 00F 30 900 037 BB 810 403 BBCC DD44 900 010 6 900 038 22 900 011 0 900 039 DD 900 012 0 900 03A cc 900 013 0 900 03B BB 900 014 00 900 03C 33 900 015 14 900 O3D DD 900 016 oo 900 03E CC 900 017 00 900 03F BB 900 018 64 900 040 44 900 019 rg 900 041 DD 900 01A 190 900 042 GIG 900 01B 05 Block 1 900 043 BB 900 O1C 44 001 400 AA11 900 044 6 900 01D aA 001 401 AA22 900 045 0 900 O1E 22 001 402 AA33 900 046 0 900 O1F aA 001 403 AA44 900 047 0 900 020 33 001 404 AA55 900 048 00 900 021 l 001 405 AA66 900 049 01 900 022 44 900 04A 88 900 023 nA 900 04B 00 900 024 55 900 04C 64 900 025 aa 900 O4D F8 900 026 66 900 04E 10 900 027 aA 900 04F 05 Source Boot Destination Block address table address data Block 3 900 050 d 880 400 AA11 900 051 EE 880 401 AA22 900 052 22 880 402 AA33 900 053 EE 880 403 AA44 900 054 33 880 404 AA55 900 055 EE 880 405 AA66 900 056 44 900 057 EE 900 058 55 9
111. 910005h e e e dS ZED0ZESWL eui oi Aiowayy Duroeuelu Interfacing Memory to the TMS320C32 DSP 4 6 2 Logical Versus Physical Address The C32 is a 32 bit processor Its instruction set operates on 32 bit registers the CPU alone does not read 8 or 16 bit data or data transfers When a C32 instruction writes to a physical address it sends all 32 bits of data to the memory interface unit through an internal bus Itis only in the memory interface that the internal 32 bit data can assume 8 bit or 16 bit form provided that the address is in the STRBO or STRB1 range of the memory map The data size field of the STRBO or STRB1 control register determines the actual size of the data portion that is placed on the external memory bus of the C32 Likewise when a C32 instruction reads a portion of data from external memory the memory interface always converts itto 32 bits as it enters the chip What hap pens to the external data as it goes through the memory interface on the way to the CPU depends on the contents of the STRBO and STRB1 control regis ters Again only the data whose address falls within the STRBO or STRB1 range of the memory map can be manipulated inside the memory interface unit Throughout this document the term logical address applies to a memory loca tion that is referenced by C32 instructions the logical address is a part of the processor s logical memory map The physical address refers to the
112. Applications 8 41 CS4215 Interface to the TMS320C3x Example 8 11 C int asm Continued ck ck Ck Sk ck Ck ck KK KKK KKK KKK ck ck ck ck ck ck ck ck ck ck ck KKK ck kk KKK KK ck kk ck kk ck kk ko kk kk KKK ko ko kc KKK KKK if this is the first half of the transmission then goto FRST HALF EDI Q first half RO BNZ FRST HALF kk ck Ck ck ck Ck ck ce ck Ck Ce Sk ck Ck ck KKK ck ck ck KK KKK KKK ck kk KKK KK KKK KKK KK KK else this the second half of the transmission SCND_HALE kk ck Ck ck ck CK ck KKK KK KKK ck Ck Sk KKK KK KKK KKK KKK ck kk KK KKK KKK KKK ck ck ck ck kk ko kk kk KKK KKK KK KKK load ARO with serial port base address do dummy read of serial port to empty control info from serial port LDI Q
113. BR WAIT TSKSEQ word TASK5 Address of TASK5 word TASK4 z Address of TASK4 word TASK3 Address of TASK3 word TASK2 Address of TASK2 word TASK1 A Address of TASK1 word TASKO Address of TASKO ADDR word SKSEQ 2 22 Chapter 3 Logical and Arithmetic Operations This chapter describes the C3x instruction set which supports both integer and floating point arithmetic and logical operations These instructions can be com bined to form more complex operations Topic Page 3 IS BIti Manipulationi Te EeePC EET rece Tee 3 2 3 2 M BIOCK MOVES E E E E 3 4 3 3 Bit Reversed Addressing ssssnsssnsnnnssnnsnnnnnnnnnn 3 5 3 4 Integer and Floating Point Division su 3 6 3 5 Square Root Computation se eee aeee e ea 3 13 3 6 Extended Precision Arithmetic 0 cc cece eee eee eee 3 16 3 7 IEEE TMS320C3x Floating Point Format Conversion 3 20 3 1 Bit Manipulation 3 4 Bit Manipulation Instructions for logical operations such as AND OR NOT ANDN and XOR can be used with the shift instructions for bit manipulation A special instruction called TSTB tests bits TSTB performs the same operation as AND but the result of the logical AND is only used to setthe condition flags and is not written anywhere Example 3 1 and Example 3 2 demonstrate the use of these in structions for bit manipulation and testing Example
114. COFF format and it contains all the sections listed in the linker SECTIONS directive It contains information about the program information about how to load it into the target DSP system and symbol information for the debugger that is later used to verify the code All C and assembly symbols such as subroutine labels etc can be made visible in the debugger window by embedding them in the COFF file provided thatthey are declared as global symbols and the appropriate op tions are used with the code generation tools Some out sections contain only the starting addresses and no code or data They include the stack section for the system stack the sysmem section for dynamically allocated memory and the bss section for uninitialized data The boot process also uses the bss section as a destination for the initialized vari ables that are originally stored in the cinit section of the out file Although they contain no data the stack and sysmem sections are included in out to allow the debugger tools to verify that the physical memory for those sections exists on the target board Other sections in the COFF file such as vectors const and text contain the starting addresses and the contents of the sections When the debugger loads the text section into the target system for example the opcodes for all assembly instructions for the entire program are copied be ginning at the section starting address The cinit section is di
115. Dequeue A double ended queue for which insertions and deletions are made at either end of the list System Stacks A stack in the C3x fills from a low memory address to a high memory address as shown in Figure 2 1 A system stack stores addresses and data during sub routine calls traps and interrupts Figure 2 1 System Stack Configuration Bottom of stack SP Top of stack Free High memory The stack pointer is a 32 bit register that contains the address of the top of the system stack The SP always points to the last element pushed onto the stack A push performs a preincrement and a pop performs a postdecrement of the SP Make provisions to accommodate your software s anticipated storage re quirements The stack pointer can be read from as well as written to multiple stacks can be created by updating the SP The SP is notinitialized by the hardware during Program Control 2 5 Stacks and Queues 2 2 2 User Stacks 2 6 reset itis important to remember to initialize its value so that it points to a pre determined memory location Example 1 1 on page 1 5 shows how to initial ize the SP You must initialize the stack to a valid free memory space Other wise use of the stack can corrupt data or program memory The program counter is pushed onto the system stack on subroutine calls traps and interrupts Itis popped from the system stack on returns The PUSH POP PUSHF and POPF instr
116. Do XD1 16 4 EI uh BIPOFF XD3 12 8 Da 200 Q XD4 9 11 XD4 9 2Y1 2A1 D4 XD5 7 B AD1678 XD6 5 15 a 17 D7 AN Analog 1G DG D8 input D9 5V gt D10 D11 74LS244 20K Q XD8 18 4y4 m E EOC INTO XD9 16 4 XD10 14 6 PGND VEE AGND XD11 12 8 J J 19 I ONE 1G 12 V XD bus As with many A D converters the AD1678 data output lines enter a high impedance state atthe end of a read cycle This occurs after the output enable OE or read control line goes inactive Furthermore the data output buffer of ten requires a substantial amount of time to actually attain a full high impe dance state When used with the C30 33 device output must be fully disabled no later than 65 ns following the rising edge of IOSTRB This is because the C30 begins driving the data bus at this point if the next cycle is a write If this timing is not met bus conflicts between the C30 and the AD1678 can occur This degrades system performance and may cause failure due to damaged data bus drivers The actual disable time for the AD1678 can be as long as 80 ns therefore 74L S244 buffers are used to isolate the converter outputs Analog Interface Peripherals and Applications 8 3 Analog to Digital Converter Interface to the TMS320C30 Expansion Bus from the C30 The buffers are enabled when the AD1678 is read and are turned off 30 8 ns after IOSTRB goes high meeting the C30 33 requirement of 65 ns When data is rea
117. H E TMS320C3x COMMOM DRIVER HEADER FILE 5 TMS320C3x CODE Compile and archive into appropriate driver library af p C 1991 TEXAS INSTRUMENTS HOUSTON KKK KR RAR AR kCk kCk kCk KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCk kc k k ck ck ck ko kck ck ck kk ck k sk e ke X amp I f KKK KR Kk KCkCKCKCKCkCkCk kk kCkCKCk KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCK KCk KCK Ck Ck k Ck k ck k ck ck ck ko kck ck ck ck sk kk sk e ke x e I f ard BORK RK KK C kCk kCk kCK kCK KCK CkCK KCK CKCKCKCKCKCK KCKCKCK KCKCKCK KCKCKCK KCK KCK KCKCKCK KCK KCk KCk k ck k ck k ck ck ck ck ckck ck sk OR ke x amp f VIS typedef volatile float VF typedef VF volatile VPVF typedef VI volatile VPVI FUNCTION PROTOTYPES f KKK IK RR AR A KCk kCk kCK kCk KCKCKCk KCk KCk KCKCKCk KCK KCk KCKCKCk KCKCkCk KCk k ck k ck ck ck ck ckck ck ck ck sk kc k s sk e ke x amp I f void heap overflow void void error in real time void 8 46 CS4215 Interface to the TMS320C3x Example 8 14 Commarvr c
118. Hardware UART for TMS320C3x Figure 8 13 shows a 9 600 baud UART with one stop bit and one start bit The clock signal H3 is supplied to the circuit from the C3x The DSP uses a 25 MHz clock Figure 8 13 Transmit Circuitry CLKXO H3 DXD H3 XEN FSXD XEN Stop bit EE x ammi pue NEC xen D Q H3 D Q pP H3 ds XEN CE E FSXR R Modulus 8 binary counter H3 t gt Q1 4 d 2 CE Q2 5 t D Q Stop bit Q3 34 FSXR R H3 CE FSXR R The C3x serial port transmit circuitry shown in Figure 8 13 is configured to output eight bits of data at a rate of approximately 9 6 kHz This is achieved by using one of the C30 s internal timers and programming it to the desired 9 6 kHz frequency The transmitting port is configured in the first burst mode This allows the leading FSX signals to help initiate a start bit for the UART protocols The stop bit is generated at the end of the eighth bit by the UART circuitry The receive circuitry of the UART shown in Figure 8 14 is activated when the circuit detects the start bit The start bit is a logical 0 The delay circuit is acti vated on the falling edge of the start bit The delay causes sampling of the incoming data bits to occur in the middle of each bit thus increasing the UART s noise immunity Analog Interface Peripherals
119. I Y I pointer X L Y L pointer RC should be 1 less than desired i R6 SIN R2 X I X L Rl Y I Y L RO R2 SIN and R3 Y I Y L R R3 R1 COS and YII Y I Y L R4 R1 COS R2 SIN F RO R1 SIN and 6 32 Fast Fourier Transforms FFTs Example 6 13 Complex Radix 2 DIF FFT Continued BLK2 ADDF AR2 ARO R3 R3 X I X L MPYF R2 AR4 IR1 R3 R3 R2 COS and STF R3 ARO IRO X I X I X L and ARO ARO 2 N1 ADDF RO R3 R5 RS R2 COS R1 SIN STF R5 AR2 IRO A X L R2 COS R1 SIN H incr AR2 and STF R4 AR2 Y L R1 COStR2 SIN CMP I R7 AR1 BNE INLOP Loop back to the inner loop LSH 1 AR7 gt Increment loop counter for next time BRD LOOP Next FFT stage delayed LSH 1 AR5 IE 2 IE LDI R7 IRO Nl N2 LSH 1 R7 N2 N2 2 STORE RESULT OUT USING BIT REVERSED ADDRESSING END DI FFTSIZ RC H RC N SUBI 1 RC H RC should be one less than desired f LDI FFTSIZ IRO IRO size of FFT N LDI 2 IR1 LDI INPUT ARO LDI OUTPUT AR1 RPTB BITRV LDF ARO 1 R0 LDF ARO IRO B R1 BITRV STF RO AR1 1 STF R1 AR1 IR1 SELF BR SELF Branch to itself at the end end DSP Algorithms 6 33 Fast Fourier Transforms FFTs Example 6 14 Table With Twiddle Factors for a 64 Point FFT E FACT
120. If SourceAddr lt gt DestAddr then move data DSP Algorithms 6 75 Fast Fourier Transforms FFTs Example 6 17 Real Inverse Radix 2 FFT Continued MOVE DATA DI PT EOD DI UBI DI DI ww B Bb B uub b Wor HU J B fj n n H hj DIVISION OU HH LOAT USHF Im ET H UM q U Ay mH UBI PYF3 PTB PYF3 TFRI LAST_LOOP PYF3 YOEnNEW EMH H nj MPYF3 STF STF SOURCE_ADDR RO DEST_ADDR RO IVISIO QFFT SIZ 2 R0 E RO SOURCE_ADDR ARO DEST_ADDR AR1 ARO R1 RO R1 AR1 2 IRO QFFT SIZI RO 32 RO RO RO s RO RO exp LOG SIZE ARO R1 R1 AR1 E RO MSB S saved RO Neg exponent 1 FFT SIZ fl DEST_ADDR AR1 DEST_ADDR AR2 AR2 44 QFFT SIZI 1 RC 2 RC RO AR1 RO AR2 AR1 I RO AR1 RO AR2 R1 AR1 R2 AR2 LAST LOOE E RC R1 H p R2 H RO R1 R2 AR2 IRO R2 A 1st location 2nd 4th 6th location 3rd 5th 7th location Last location 6 76 Fast Fourier Transforms FFTs Example 6 17 Real Inverse Radix 2 FFT Continued Return to C environment POP DP Restore C environment variables POP AR7 POP AR6 POP AR5 POP ARA POPF R7 POP R7 POPF R6 POP R6 POP R5 POP R4 POP FP RETS end No more
121. Interaction With the TMS320C32 Memory Interface 4 69 4 7 2 C Compiler and Assembler Switch i 4 72 4 73 Linker Switches isses ese a ded X dun Fase edad d Ree 4 73 4 7 4 Debugger Configuration pp 4 73 4 7 5 TMS320C32 Configuration Examples i 4 74 4 8 Booting a TMS320C32 Target System in a C Environment Lu 4 86 4 8 1 Generating a COFF File 7 4 86 4 8 2 Loading the COFF File to the Target System i 4 91 48 9 Debugger BOOt s sae i on bee edad Vane Pea pe e n ek e ees 4 91 48 4 EPROM BOOU sessi reser Rr E ERE TERR ER XE ER UE 4 95 4 8 5 Boot Table Memory Considerations i 4 99 Sa 4 102 4 9 TMS320C30 Addressing up to 68 Gigawords pp 4 107 Contents 5 Programming Tips se Provides hints for writing more efficient C and assembly language code 5 1 Hints for Optimizing C Code sses siia a de 5 2 Hints for Assembly Coding 2 00sec eee i i Eae 5 3 Low Power Mode Wakeup Example i 5 4 Bit Reversed Addressing in C 7 5 5 Sharing Header Files in C and Assembly i 5 6 Addressing Peripherals as Data Structures in C i 5 7 Linking C Data Objects Separate From the bss Section iii 5 8 Interrupts G0 mm iet exceder dese dee d doge de o dr d dod rede una DSP Algorithms 2 2 2 on o ex de cee teen tas dee dene seeds eee Describes common algorithms and provides code for implementing them Gil Compandno ee rM 6 2 FIR IIR and Adaptive Filters os 6 2 1 FIR Filters uiis lees cerrado deca aedi ha kaw X deor aka
122. LDI IA1 AR7 LDI IA1 AR4 ADDI SINTAB AR4 SUBI 1 AR4 ADDI AR4 AR7 AR5 SUBI 1 AR5 ADDI AR7 AR5 AR6 SUBI 1 AR6 SECOND LOOP RPTB BLK2 ADDF AR2 ARO0 R3 ADDF AR3 AR1 R5 ADDF R5 R3 R6 SUBF AR2 ARO R4 SUBF R5 R3 ADDF AR2 ARO R1 ADDF AR3 AR1 R5 MPYF R3 AR5 IR1 R6 N STF R6 ARO ADDF R5 R1 R7 SUBF AR2 ARO R2 SUBF R5 Rl MPYF R1 AR5 R7 N STF R7 ARO IRO SUBF R7 R6 SUBF AR3 AR1 R5 MPYF R1 AR5 IR1 R7 STF R6 AR1 MPYF R3 AR5 R6 ADDF R7 R6 ADDF R5 R2 R1 SUBF R5 R2 SUBF AR3 AR1 R5 SUBF R5 RA4 R3 ADDF R5 R4 MPYF R3 AR4 IR1 R6 IA1 IAI1 IE X I Y I pointer X I1 Y I1 pointer X I2 Y I2 pointer X I3 Y I3 pointer RC should be one less than desired 4 If LPCNT JT go to special butterfly Create cosine index AR4 Adjust sine table pointer IA2 IA1 IA1 1 IA3 IA2 IA1 1 R3 Y I Y I2 R5 Y I1 Y I3 R6 R3 R5 RA Y I tY I2 R3 R3tR5 R1 X I 4X I2 R5 X I1 X I3 R3 CO2 Y I R3 R5 R7 R1 R5 R2 X 1I X 1I2 Rl R1ER5 R7 R1 SI2 X I R1 R5 R6 R3 CO2tR1 SI2 R5 Y I1 XtY 13 R7 R1 C02 Y I1 R3 CO2EtR1 SI2 R6 R3 SI2 R6 R1 CO2 R3 SI2 R1 R2 R5 R2 R2tR5 R5 X I1 tX 13 R3 R4 R5 R4 R4 R5 R6 R3 COl DSP Algorithms 6 39 Fast Fourier Transforms FFTs Example 6 15 Complex Radix 4 DIF FFT Continued BLK2
123. Microcomputer Boot Loader Mode Linker cr Option 4 96 The C32 features an on chip hardwired boot loader program in the internal programmable logic array PLA The boot loader reduces the DSP target board cost by replacing multiple fast EPROMSs with a single 8 bit slow inex pensive EPROM Because the C32 cannot execute code from memory that is only 8 bits wide the on chip boot loader program reads the boot table from the byte wide EPROM and reconstructs all sections of the original COFF file one byte at a time before placing the program data in SRAM see Figure 4 41 on page 4 98 To power up the DSP in the boot loader mode the MCBL MP pin must be held high when the RESET signal is deasserted At that stage the DSP starts executing the boot loader code from internal address 000045h Immediately after it starts execution the boot loader checks the interrupt flag IF register All interrupts are disabled and remain disabled until the application program enables them Depending on which external interrupt is asserted the boot loader looks for the boot table at one of three external memory locations or at the serial port The interrupt pins carry a message to the boot loader telling it where to get the boot table after reset The boot table structure resembles the COFF file from which it was derived by the hex conversion utility The main feature that distinguishes the boot table from a regular hex utility output such as the microp
124. Polling of Interrupts The interrupt flag register can be polled and action can be taken depending on whether an interrupt has occurred This is true even when maskable inter rupts are disabled This can be useful when an interrupt driven interface is not implemented Example 2 2 shows the case in which a subroutine is called when external interrupt 1 has not occurred Example 2 2 Use of Interrupts for Software Polling TITLE INTERRUPT POLLING TSTB 40H IF Test if interrupt 1 has occurred CALLZ SUBROUTINE If not call subroutine When interrupt processing begins the program counter PC is pushed onto the stack and the interrupt vector is loaded into the PC Interrupts are then disabled by clearing the GIE bit to 0 and the program continues from the address loaded in the PC Since all interrupts are disabled interrupt processing can proceed without further interruption unless the interrupt service routine reenables inter rupts Program Control 2 9 Interrupt Service Routines 2 3 3 Interrupt Priority Interrupts on the C3x are automatically prioritized This allows interrupts that occur simultaneously to be serviced in a predefined order Infrequent but lengthy interrupt service routines ISRs might need to be interrupted by more frequently occurring interrupts In Example 2 3 the ISR for INT2 temporarily modifies the IE register to permit interrupt processing when an interrupt to INTO b
125. R1 87FF84h IR f O STF R1i ARis 87FF85h 32 bits A 3 Physical memory Logical address Et v 16bits zm z gt So x 104 0 oh 32 bits E 16 bits 40 bits 3 010 910001h emory Data wh size 402 0 910002h E oi 16 bits 32 bits 1030 910003h 4 START D T 910004h data write L quam 910005h e e e adSd ZED0ZESWL 94 0 Aowa Buroeueju Interfacing Memory to the TMS320C32 DSP 4 6 1 3 Program Fetch From 16 Bit STRBO Memory Table 4 4 shows program memory mapped to 16 bit wide STRBO or STRB1 memory By hardwiring the PRGW pin to a high state 32 bit data transfers to and from the 32 bit wide external memory do not involve any data operations in the memory interface The short program stored in STRBO memory begins with the LDI instruction reading a 32 bit integer from 32 bit wide IOSTRB memory and loading it to RO see Figure 4 13 Next the FLOAT instruction converts the integer in RO to a 40 bit floating point number and loads it into R1 Finally the STF instruction truncates the 40 bit contents of R1 to 32 bits and stores it in the 32 bit wide STRB1 memory The data is not modified as it passes through the memory in terface The program controlling the data conversion in this example is stored in the 32 bit wide memory bank mapped to STRBO As discussed earlier program fetch cycles do not reference the strobe control register to determine the width of the program memory Instead the memo
126. R5 AR1 R7 AR3 AR1 R3 R5 ARO R1 R1 AR1 R3 R1 R6 R5 ARO R2 R6 ARO IRO R3 R1 AR3 AR1 R6 R7 AR3 R3 R1 AR1 IRO R6 R4 R5 R6 R4 R5 AR2 R4 AR3 R3 R2 R5 R3 R2 R5 AR2 IRO STF R2 AR3 IRO IF THIS IS THE LAST STAG LDI ADDI CMPI BZD STI MAIN INN LDI STI LDI STI LDI ADDI LDI LDI STAGE AR7 1 AR7 LOGFFT ART END AR7 STAG Lu ER LOOP 1 AR7 AR7 QIAl 2 AR7 AR7 QLPCNT 2 AR6 LPCNT AR6 LPCNT ARO IA1 AR7 RL Y I 4Y I2 R3 Y I1 Y I3 R6 R1 R3 R4 Y I XY I2 Y I R1 R3 Rl R1 R3 R5 X I2 R7 Y I1 R3 X I1 X 13 Rl X I X I2 Y Il1 R1tR3 R6 R1 R3 R2 X I XX I2 X I R1 R3 R1 R1tR3 R6 X I1 tX 13 RI Y I1 tY 13 I X Il R1tR3 RS R4 R6 R4 R4 R6 Y I2 R4tR6 Y I3 R4 R6 R5 R2 R3 R2 R2 R3 X I2 R2tR3 X I3 R2 R3 YOU ARE DONE Current FFT stage gt Init IAl index Init loop counter for inner loop INLOP Increment inner loop counter 6 38 Fast Fourier Transforms FFTs Example 6 15 Complex Radix 4 DIF FFT Continued ADDI IEINDX AR7 ADDI INPUT ARO STI ART IA1 ADDI RO ARO AR1 STI AR6 LPCNT ADDI RO AR1 AR2 ADDI RO AR2 AR3 LDI RPTCNT RC SUBI 1 RC CMPI JT AR6 BZD SPCL
127. REG INITIALIZATION GLOBAL CONTROL REG INITIALIZATION 7 6 DMA Assembly Programming Examples Example 7 3 sets up the DMA to transfer data 128 words from an array buff er to the serial port 0 output register with serial port transmit interrupt XINTO The DMA sends an interrupt to the CPU when the data transfer completes Serial port 0 is initialized to transmit 32 bit data words with an internally generated frame sync and a bit transfer rate of 8H1 cycles bit The receive bit clock is inter nally generated and equal in frequency to one half of the C3x H1 frequency This program assumes previous initialization of the CPU interrupt vector table specifically the DMA to CPU interrupt The serial port interrupt directly affects only the DMA therefore no CPU serial port interrupt vector setting is required M MM M 71 Note Serial Port Transmit Synchronization The DMA uses serial port transmit interrupt XINTO to synchronize transfers Because the XINTO is generated when the transmit buffer has written the last bit of data to the shifter an initial CPU write to the serial port is required to trigger XINTO to enable the first DMA transfer LLLLLLL Example 7 3 DMA Transfer With Serial Port Transmit Interrupt
128. REGISTERS MODIFIED RO R1 R2 R3 R4 ARO AR1 REGISTER CONTAINING RESULT RO R1 3 18 Extended Precision Arithmetic Example 3 10 32 Bit by 32 Bit Multiplication Continued CYCLES 28 WORST CASE WORDS 25 global EXTMPY EXTMPY XOR3 RO R1 ARO0 Store sign ABSI RO A Absolute values of X ABSI R1 and Y SEPARATE MULTIPLIER AND MULTIPLICAND INTO TWO PARTS LDI 16 AR1 LSH3 AR1 RO R2 H R2 X1 upper 16 bits of X AND OFFFFH RO H RO X0 lower 16 bits of X LSH3 AR1 R1 R3 R3 Y1 upper 16 bits of Y AND OFFFFH R1 R1 YO lower 16 bits of Y CARRY OUT THE MULTIPLICATION MPYI3 RO R1 R4 XO YO Pl MPYI R3 R0 H XO Y1 P2 MPYI R2 R1 H X1 YO P3 ADDI RO R1 P2 P3 MPYI R2 R3 Xl Y1 P4 LDI R1 R2 LSH 16 R2 Lower 16 bits of P2 P3 CMPI 0 ARO i Check the sign of the product BGED DONE H If 0 multiplication complete delayed LSH 16 R1 H Upper 16 bits of P2 P3 ADDI3 R4 R2 RO0 WO RO lower word of the product ADDC3 R1 R3 R1 s Wl R1 upper word of the product NEGATE THE PRODUCT IF THE NUMBERS ARE OF OPPOSITE SIGNS NOT RO ADDI 1 R0 NOT R1 ADDC O R1 DONE RETS end Logical and Arithmetic Operations 3 19 IEEE TMS320C3x Floating Point Format Conversion 3 7 3 20 IEEE TMS320C3x Floating Point Format Conversion The fast ver
129. RO R4 R2 R2 X I1 X I2 X I3 SUBF3 RO AR4 R1 R1 X I14 X 13 STF R5 AR1 IRO X I1 ADDF3 R2 ARA R5 RS X I1 X I2 X I3 X 14 STF R1 AR2 IRO X I2 MPYF3 R5 AR7 IR1 R1 R1 R5 SIN SUBF3 AR4 R3 R2 R2 X I1 X I2 X I3 X I4 MPYF3 R2 AR7 RO RO R2 SIN STF R1 AR4 IRO X I4 RPTB LOOP3 B LDF AR2 R6 R6 X I2 STF RO AR3 IRO X I3 ADDF3 R6 AR1 R5 RS X I1 4X I2 LDF AR3 RO RO X I3 SUBF3 R6 AR1 R4 R4 X I1 X 12 SUBF3 RO R4 R3 R3 X I1 X I2 X I3 ADDF3 RO R4 R2 R2 X I1 X I2 X I3 SUBF3 RO AR4 R1 R1 X I4 X 13 STF R5 AR1 IRO s X I11 4 ADDF3 R2 ARA R5 RS X I1 X I2 X I3 X 14 STF R1 AR2 IRO X I2 lt 4 MPYF3 R5 AR7 R1 R1 R5 SIN SUBF3 AR4 R3 R2 R2 X I1 X 12 X 13 X 14 LOOP3_B MPYF3 R2 AR7 RO RO R2 SIN STF R1 AR4 IRO X I4 STF RO AR3 X 13 6 70 Fast Fourier Transforms FFTs Example 6 17 Real Inverse Radix 2 FFT Continued Perform first and second FFT loops RS A AR1 gt Il 0 X I1 X I3 2 X I2 AR2 gt T2 1 X I1 X I3 2 X I2 AR3 gt 13 2 X I1 X I3 2 xX T4 ARA gt I4 3 X I1 X I3 2 X I14 AR1 gt 4 i 1 Y H LDI SOURCE_ADDR AR1 LDI AR1 AR2 LDI AR1 AR3 LDI AR1 AR4 ADDI 1 AR2
130. S jabiel ZEQOZESWL e 6unoog Emulation cable file out C boot text section boot asm File1 text section File2 text section File1 cinit section File2 cinit section COFF format binary file Figure 4 39 Loading C Object File into TMS320C32 Memory Linker c Option and pod Cii The debugger s loader program uses the on chip emulation logic to load the out file to the target The program data is transferred over the emulation cable from the PC to the target system Oo A z On chip P gt EMU emulation oo RE scan chain oo MPSD emulation CPU msc connector bs TMS320C32 DSP The emulator uses CPU write cycles to load the program code into SRAM1 The CPU executes the C boot code to copy initialized variables from cinit to bss spaces c intOO is the execution entry point SRAM1 C boot text section boot asm File1 text section File2 text section File1 data cntrl File2 data cntrl 32 bits wide The CPU executes the C boot code to copy initialized data from Cinit to bss section spaces
131. STRB term of the chip select input Because the RAM s output drivers are disabled whenever the WE inputis low regardless ofthe state of the OE input bus conflicts with the C3x are automatically avoided with this interface The circuits data setup and hold times ty and to in Figure 4 5 of approximately 50 ns and 20 ns easily meet the RAM s minimum timing requirements of 10 ns and 0 ns Figure 4 5 Write Operations Timing H1 N NEZ N A YW CS1 STRB ZN WE R W le ty gt 1t be 4 8 Zero Wait State Interface to Static RAMs If you require more complex chip select decode than can be accomplished in time to meet zero wait state timing you can use wait states see section 4 5 Wait States and Ready Signal Generation or bank switching techniques see section 4 5 6 The CY7C186 SRAM s OE control is gated internally with a CS pin the RAM s outputs are not enabled unless the device is selected This is critical if there are any other devices connected to the same bus If there are no other devices connected to the bus OE does not need not to be gated internally with a chip select pin To interface RAM without OE controls to the C3x with a single memory bank and no other devices present on the bus connect the memory s CS input to STRB directly If several devices must be selected an additional gate is re quired to AND the device select and STRB pins in order to drive the CS input that generates the chip s
132. Segmenting the address space to distinguish fast and slow devices 2 Generating properly timed ready indications 3 Logically ORing all of the separate ready timing signals together to con nect to the physical ready input Segmenting the address space which is commonly performed by chip select generation is required to obtain a unique indication of each area within the address space that requires wait states You can use chip select signals to initiate wait states however chip select decoding considerations may occasionally provide signals that do not meet ready input timing requirements In this case you can use a small number of address lines to segment coarse address space The simpler gating allows signals to be generated more quickly In either case the signal that indicates a particular area of memory is being addressed normally initiates a ready or wait state indication Once the region of address space being accessed has been established a timing circuit provides a ready indication to the processor at the appropriate point in the cycle Finally since indications of ready status from multiple devices are typically present the signals are logically ORed by using a single gate to drive the RDY input Wait States and Ready Signal Generation 4 5 4 Ready Control Logic You can take one of two basic approaches to implement ready control logic depending on the state of the ready input between accesses If RDY is low between
133. Stacks and QUeles uxo eux Ta Lage aces e LR EG doe xu ns URN RO a M qud 2 5 2 2 1 System SIacks ssni Te Red dub bats dada dai eden ee 2 5 2 2 2 USEF SLACKS ioci Een eR REA RR E DU RUE A AUR RUD E RR NUR eee 2 6 2 2 3 Queues and Double Ended Queues pp 2 8 2 3 Interrupt Service Routines A nee 2 9 2 3 1 Correct Interrupt Programming i 2 9 2 3 2 Software Polling of Interrupts 9 2 9 23 3 Interrupt PNOY vu ie en 2 10 2 4 Context Switching in Interrupts and Subroutines i 2 11 2 5 Delayed Branches i 2 icter Qi ed xdg es uveg dee donee ee a ied d 2 17 2 6 Repeat Modes suuussssssslsllss sss hn 2 18 261 JBlock Hepeat erra REPRE an Fe ee nese Ses et vade iE 2 18 2 6 2 Single Instruction Repeat 1 2 20 2 7 Computed GO TOS ases sipu sema ot bsc RE ette dade dicbus UNUS alana ek 2 22 Logical and Arithmetic Operations 4 3 1 Provides examples for performing logical and arithmetic operations 3 1 Bit Manipulation 5 2222 x RR ed sei eysee ey net ed iedey yee ee VERAT UE dass 3 2 32 Block MOVES ure e Rer RR EUER wns Pada sade aaa bm ER RUD ME 3 4 3 3 Bit Reversed Addressing sn 3 5 3 4 Integer and Floating Point Division isisssssssssseee RII 3 6 39 44 Integer DIVISION 3 6 3 4 2 Floating Point Inverse and Division 9 3 10 XV Contents xvi 3 5 Square Root Computation sssssssssssssesssse aa A a 3 13 3 6 Extended Precision Arithmetic i 3 16 3 7 IEEE TMSS320C3x Floating Point Format Conve
134. TMS320 DSP Interrupts in C Application Report literature number SPRAO036 describes methods of setting up interrupts for the TMS320 family of processors in C programming language Sample code segments are provided along with complete examples of how to set up interrupt vectors TLC32040C TLC32040I TLC32041C TLC32041I Analog Interface Circuits literature number SLASO14E data sheet contains the electrical and timing specifications for these devices as well as signal descriptions and pinouts for all of the available packages TMS320C3x C4x Assembly Language Tools User s Guide literature num ber SPRU035 describes the assembly language tools assembler link er and other tools used to develop assembly language code assembler directives macros common object file format and symbolic debugging directives for the C3x and C4x generations of devices TMS320C3x C4x Code Generation Tools Getting Started Guide literature number SPRU119 describes how to install the TMS320C3x C4x assembly language tools and the C compiler Installation instructions are included for MS DOS Windows 3 x Windows NT Windows 95 SunOS Solaris and HP UX systems TMS320C3x C4x Optimizing C Compiler User s Guide literature number SPRUO34 describes the TMS320 floating point C compiler This C com piler accepts ANSI standard C source code and produces TMS320 as sembly language source code for the C3x and C4x generations of de vices TMS
135. TYPICAL CALLING SEQUENCE load R2 load ARO e load AR load BK CALL IIRL ARGUMEN ASSIGNMENTS ARGUMEN FUNCTION R2 INPUT SAMPLE X N ARO ADDRESS OF FILTER COEFFICIENTS A2 ARI ADDRESS OF DELAY MODE VALUES D N 2 BK BK 3 FIR IIR and Adaptive Filters Example 6 6 IIR Filter One Biquad Continued REGISTERS USED AS INPUT R2 ARO BK REGISTERS MODIFIED RO R1 R2 ARO REGISTER CONTAINING RESULT RO CYCLES 11 WORDS 8 FILTER global IIR1 IIR1 PYF3 ARO AR1 RO a2 d nt2 gt RO PYF3 ARO 1 AR1 1 R1 b2 d nt2 t R1 PYF3 ARO 1 ARI RO al d ntl gt RO ADDF3 RO R2 R2 a2 d nt2 x n t R2 PYF3 ARO 1 AR1 1 2 R0 bl d ntl1 gt RO ADDF3 RO R2 R2 al d n 1 a2 d nt2 x n gt R2 PYF3 AR0O 1 R2 R2 bO d n gt R2 STF R2 AR1 1 Store d n and point to d ntl ADDF RO R2 bl d ntl 4b0 d n t R2 ADDF R1 R2 R0 b2 d n 2 b1 d ntl b0 d n gt RO RETURN SEQUENCE RETS Return end end DSP Algorithms FIR IIR and Adaptive Filters In the more general case the IIR filter contains N 1 biquads The equations for its implementation are given by the following pseudo C language code y 0 n x n for i 0 i lt N i d i n a2 i d i n 2 al i d
136. The minimum gain measured for the C3x inverter is 5 6 To maintain an overall loop gain of 1 the external component network of C1 crystal C2 must not introduce a loss of greater than 5 6 For this reason the values of the load ca pacitance and crystal series resistance have a strong effect on whether the cir cuit oscillates 9 4 4 Drive Level Power Dissipation Another parameter specified when ordering a crystal is the drive level or power dissipation Higher frequency crystals generally have lower power dissipation ratings because the crystal is physically thinner and is damaged by excessive voltages Power dissipation also affects frequency stability because the crys tal s frequency of operation is dependent on temperature Excessive power dissipation causes crystal heating and results in frequency drift There is not a convenient way to measure the power dissipation in the crystal The series resistance Ry is the only power dissipating component in the crys tal Measuring the external voltage on the crystal includes the voltage across Ly and Cy Therefore the power dissipation in Ry cannot be easily calculated directly from the voltage on the crystal It is necessary to measure the current through the crystal using a current probe or to indirectly measure the current by measuring the voltage across a small resistor in series with the crystal You can then calculate the power by using I R Design Considerations Once the drive level i
137. Trans on ASSP Bit reversal is optionally implemented at the begin ning of the function If bit reversal is selected bit reverse 0 the data input is expected in bit reverse order The sine cosine table for the twiddle factors is ex pected to be supplied in the following format SINE TABLE 0 s P gt sin 0 2 pi FFT SIZE sin 1 2 pi FFT SIZE sin FFT SIZE 2 2 2 pi FFT SIZI SINE TABLE FFT SIZE 2 1 gt sin FFT SIZE 2 1 2 pi FFT SIZI m P NOTE The table is the first half period of a sine wave Stack structure upon call FP 7 BIT REVERSE FP 6 SINE TABLE FP 5 DEST ADDR FP 4 SOURCE ADDR FP 3 LOG SIZE FP 2 FFT SIZE FP 1 returne FP 0 addr old FP OR A DSP Algorithms 6 43 Fast Fourier Transforms FFTs Example 6 16 Real Forward Radix 2 FFT Continued Calling C program can be compiled using either large or small model DP initialized only once in the program Be wary with interrupt service routines Make
138. Transfer a 256 word block of data from off chip memory to on chip memory and generate an interrupt on completion Maintain the memory order DMA source address 800000h DMA destination address 809800h DMA transfer counter 00000100h DMA global control 00000C53h CPU DMA interrupt enable IE 00000400h DMA Assembly Programming Examples Transfer a 128 word block of data from on chip memory to off chip memory and generate an interrupt on completion Invert the order of memory the highest addressed member of the block becomes the low est addressed member DMA source address 809800h DMA destination address 800000h DMA transfer counter 00000080h DMA global control 00000C93h CPU DMA interrupt enable IE 00000400h Transfer a 200 word block of data from the serial port 0 receive register to on chip memory and generate an interrupt on completion Synchronize the transfer with the serial port 0 receive interrupt DMA source address 80804Ch DMA destination address 809C00h DMA transfer counter 000000C8h DMA global control 00000D43h CPU DMA interrupt enable IE 00200400h Transfer a 200 word block of data from off chip memory to the serial port 0 transmit register and generate an interrupt on completion Synchronize the transfer with the serial port 0 transmit interrupt DMA source address 809C00h DMA destination address 808048h DMA transfer counter 000000C8h DMA global control 00000E13h CPU DMA interrupt enable IE 00400400h Transf
139. Version ok F Xo X F Ro F HF Xo ox F x oR FF 0E F F F X X ox F ox HF 0X TITLE IEEE TO TMS320C3x CONVERSION FAST VERSION SUBROUTINE FMIE BE CONVERTED I FUNCTION CONVERSION BETWEEN THE IEEE FORMAT AND THE TMS320C3x FLOATI NG POINT FORMAT THE NUMBER TO S IN THE LOWER 32 BITS OF RO HE RESULT IS STORED IN THE UPPER 32 BITS OF RO UPON ENTERING FOLLOWING TABLE 0 OxFF800000 1 OxFF000000 2 0x7F000000 3 0x80000000 4 0x81000000 ARGUMEN ASSI HE ROUTINE AR1 POINTS TO THE m lt AR1 GNMENTS ARGUMEN E UNCTION PGISTERS USED EGISTERS MODI RO NUMBER TO BE CONVERTE AR1 POINTER TO TABLE WITH CONSTANTS EGISTER CONTAINING RESULT RO D AS INPUT RO AR1 FIED RO R1 OTE SINCE THE STACK POINTER SP IS USED MAKE SURE TO INITIALIZE CYCLES 12 WO IT IN THE CALLING PROGRAM RST CASE WORDS 12 global FMIEEE 3 22 IEEE TMS320C3x Floating Point Format Conversion Example 3 11 IEEE to ITMS320C3x Conversion Fast Version Continued FMIEBEE AND3 D DDI DIZ UBI US
140. Versus Average Current 12 20 If currentis observed over the course of an entire program some segments usu ally exhibit significantly different levels of current required for different durations of time For example a program may spend 80 of its time performing internal operations drawing a current of 250 mA it may spend the remaining 20 of its time performing writes at full speed to the expansion bus drawing 300 mA While knowledge of peak current levels is important in order to establish power supply requirements some applications require information about average current This is particularly significant if periods of high peak current are short in duration Average current can be obtained by performing a weighted sum of the currents from the various independent program segments over time In the example above the average current can be calculated as follows 0 8 x 250 mA 0 2 x 300 mA 260 mA Using this approach you can calculate average current for any number of pro gram segments Calculation of Total Supply Current 12 4 5 Thermal Management Considerations Heating characteristics of the C30 depend on power dissipation which in turn depends on power supply current When you make thermal management cal culations you must consider how power supply current contributes to power dissipation and to the time constant of the C30 package thermal characteris tics Depending on sources and destinations of current on th
141. WOr dint WOr T AND RESET VECTORS t vecs interrupt and reset vectors c int00 compiler defined C initialization reset e int06 Serial port transmit interrupt service routine C int08 Serial port transmit interrupt service routine c int99 unexpected interrupt handler d c intO00 d c int99 d c int99 d c int99 d c int99 d c int99 d c int06 d c int99 d c int08 d c int99 d c int99 d c int99 8 40 CS4215 Interface to the TMS320C3x Example 8 11 C int asm pOCKOUCKCKCk kk ko KKK RK KK ke kk RK KKK KK KKK koc kk koc ke kk KER KR KKK ke kk ek koc ke ko ke ec ke ke e KKK c int asm Leor Brenman 03 16 92 i A C Texas Instruments Inc 1992 E Refer to the file license txt included with this this package for usage and license information ck ck ck ck Ck ok ck kk KK KKK KKK KKK KK KKK KKK KKK ck ck Sk ck kk ck ck ck Ck ck ck KKK K ko kk kk KKK KKK KKK kk ck Ck ck ck Ck Sk KKK ck Ck KKK KKK KEK KKK ck ck ck ck ck KKK KKK ck kk ck kk kk ck kk KKK KKK KK KK C INTO0S8 VOID Hand coded assembly language interrupt service routine This serial port transmitt ISR supports the CS4215 zero chip I F to the C3x serial port This ISR has been hand
142. X I4 COS 32 64 ARI gt 33 65 L Li v LDI QFFT SIZE IRO LSH 2 IRO0 SIII RO SEPARATION LSH 2 IR0 LDI dys LDI 3 R7 LDI 16 R6 LDI DEST_ADDR AR5 LDI DEST_ADDR AR1 LSB 1 IRO LSH 1 R7 6 58 Fast Fourier Transforms FFTs Example 6 16 Real Forward Radix 2 FFT Continued LOOP ADDI 1 R7 LSH 1 R6 LDI AR1 AR4 ADDI R7 AR1 AR1 points at A LDIA R1 AR2 ADDI 2 AR2 AR2 points at B ADDI R6 AR4 SUBI R7 AR4 AR4 points at D LDI AR4 AR3 SUBI 2 AR3 AR3 points at C LDI SINE_TABLE ARO ARO points at SIN COS table LDI R7 IR1 LDI R7 RC INLOP ADDF3 AR1 IR1 AR2 IR1 RO RO X I1 X I3 SUBF3 AR3 IR1 AR1 R1 Bl X Il X I3 NEGF ARA R2 R2 X I4 STF RO AR1 X I1 4 STF R1 AR2 X I3 4 STE R2 AR4 IR1 X I4 lt LDI SEPARATION IR1 IR1L SEPARATION BETWEEN SIN COS TBLS SUBI 3 RC MPYF3 ARO IRO AR4 R4 R4 X I4 SIN MPYF3 ARO AR3 R1 R1 X I3 SIN MPYF3 ARO IR1 ARA RO RO X I4 COS MPYF3 ARO AR3 RO RO X I3 COS SUBF3 R1 R0 R3 R3 X I3 SIN X I4 COS MPYF3 ARO IRO ARA RO ADDF3 RO R4 R2 R2 X I3 COS X I4 SIN SUBF 3 AR2 R3 R4 R4 R3 X I2 ADDF3 AR2 R3 R4 RA R3 X I2 STF R4 AR3 X I3 lt SUBF3 R2 AR1 R4 RA X I1
143. a different combination of C32 silicon features software and hardware tools Each combination forms an integrated development envi ronment that includes features to support most system boot requirements A boot development flow includes two major tasks 1 Use C source debugger and assembly level tools to compile assemble and link the boot code data to create a binary common object file format COFF executable object 2 Load the COFF file into the DSP target system Generating the COFF file linker output out file uses the same flow for all boot methods Generating a COFF File Generating a COFF file requires compiling the source code with the C compil er then assembling and linking the resulting assembly files with the assembly level tools A text editor creates additional assembly files or the files are ex tracted from the RTS30 library The linking process resolves all external refer ences between program files and generates the out COFF file subject to spe cified options such as c or cr boot options 4 8 1 1 Compiler 4 8 1 2 Assembler Booting a TMS320C32 Target System in a C Environment Figure 4 37 on page 4 89 shows how one or more C files are compiled into multiple assembly files Each assembly file is constructed from former C func tions that were individually decomposed into standard logical sections J The program code is assigned to text The stack is assigned to stack Dynamically allocat
144. address shift is needed for connecting 32 bit wide memory or boot table memory regardless of its width The C32 can access data of any size regardless of the physical width of an external memory bank For example byte wide data can be packed in 16 bit memory or 32 bit data can be accessed from 8 bit wide memory The latter takes four cycles The variable data size feature is made possible by dividing the STRBO or STRB1 controls into four signals each The four control signals in addition to being strobes serve a byte enable function Figure D 1 shows examples of three C32 systems each connected to a memory bank of a different width Regardless of memory width the data inside each bank can be 8 16 or 32 bits wide Before data of a particular size can be accessed the respective strobe control register must be programmed for that size While the data size can vary the program is always 32 bits wide Even if they are different sizes program and data can reside within the same physical bank of memory Up to two data sizes can reside simultaneously alongside the 32 bit program in a single bank see Figure D 2 on page D 3 D 1 Memory Interface and Address Translation Figure D 1 Data and Program Packing Program and a Single Data Size 32 bit memory 32 bit program TMS320C32 16 bit data
145. and Applications 8 71 Hardware UART for TMS320C3x Figure 8 14 Receive Circuitry RSDO lt Qq C256BCR DIN 4 D Q D a H3 r H3 Qt Q4 B5 Q2 C88CR H3 Pc Ge De Q3 ON104U H3 2 EE m CE as Re232BTN d ror RS232BITIN L 5 D Q D Q RSEND E xd Is asat H3 2 H3 2 Qt Q2 H3 2 Qo s ON104U CE Q1 de RSDD R DIN 1D as H3 2 P Qe DRO mn all Gera Mm H3 2 Qo DSR SEND RS232BITIN DEM Q1 cL LL CE Q2 H3 2 gt C RS232BITIN D GH FSRO BTC D H3 2 gt RS232BITIN 4 R oM RSEND 9 omes s H3 2 Q0 acm 5v ce a1 RO gt 8 72 After the delay is performed the timer is activated The timer has a period of 104 us which corresponds to a baud rate of approximately 9 6 KHz At each bit time a data value is sampled into an 8 bit shift register After all eight bits are received the data is passed to the C30 over the serial port at 1 8 of the H3 clock rate The FPGA circuitry interfaces the C30 in the fixed burst mode of operation to the serial port Both the clock and the frame sync signals are generated by the FPGA circuitry This UART circuitry can also ea
146. and N columns is multiplied by an N x 1 vector to produce a K x 1 result The multiplier vector has elements v j and the product vector has elements p i Each one ofthe product vector elements is computed by the following expres sion p i m i 0 v 0 m i1 v 1 m N 1 v N 1 i 0 1 K 1 This is essentially a dot product and the matrix vector multiplication contains as a special case the dot product presented in Example 2 1 on page 2 3 In pseudo C format the computation of the matrix multiplication is expressed by for i O i lt K i p i 0 for j O j lt N j p i p i m ij v j Figure 6 7 shows the data memory organization for matrix vector multiplica tion and Example 6 11 shows the C3x assembly code that implements it Note that in Example 6 11 K number of rows must be greater than 0 and N number of columns must be greater than 1 Figure 6 7 Data Memory Organization for Matrix Vector Multiplication 6 24 Input Result Matrix storage vector Eo vector m Biden NE 0 m NE 1 e e e V N 1 p K 1 m 1 0 High address Example 6 11 Matrix Times a Vector Multiplication Matrix Vector Multiplication TITLE MATRIX TIMES A VECTOR MULTIPLICATION SUBROUTINE MA MAT MATRIX TIMES A VECTOR OPERATION TYPICA
147. and the system waits for the next start bit The transmit routine begins when the main program loads a byte into the hold ing register and then calls TX MAIN This procedure loads timer1 with the full bit time value resets the transmit counter sets the start bit and enables the timer s interrupt The routine then exits back to the main program The main program does not call for another byte transmit until it finds the transmit count er equal to 0 On each subsequent timer1 interrupt T INT the routine shifts out the transmit byte including the stop bit until the transmit counter is 0 Software UART Emulator for the TMS320C3x Example 8 17 Full Duplex UART Emulator for TMS320C3x half bit time set O1ADh assume 33 MHz TMS320C3x whole bit time set 0358h timer go set O3Clh timer setup set O D1h int setup sec O301h iof setup set 06h timerO0 vector word RX TMR INT interrupt vector addresses timerl vector word TX TN rx int vector word RX INTO timer0 period word 0808028h on chip RAM locations timerl period word 0808038h timerO0 control word 0808020h timerl control word 0808030h timerO0 int vect word 0809FC9h timerl int vect word 0809FCAh intO vector word O809FCih rx byte word 0809FF8h tx byte word 0809FF9h rx counter word 0809FFAh tx counter word 0809FFBh Main setup for asynchronous serial interface to be run at powerup SETUP ASYNCH PUSH AR7 OR iof setup IOF
148. be transformed is in the correct order the final result of the FFT is presented in bit reversed order To recover the frequency domain data in the correct order you must swap certain memory locations The bit reversed addressing mode makes swapping unnecessary The next time data needs to be accessed the access is performed in a bit reversed manner rather than sequentially The base address of bit reversed addressing must be located on a boundary the size of the table For example if IRO 2771 the n least significant bits LSBs of the base address must be 0 In bit reversed addressing IRO holds a value equal to one half the size of the FFT if real and imaginary data are stored in separate arrays During accessing the auxiliary register is indexed by IRO but with reverse carry propagation Example 3 4 illustrates a 512 point complex FFT being moved from the place of computation pointed at by ARO to a location pointed at by AR1 In this ex ample real and imaginary parts XR i and XI i of the data are not stored in separate arrays They are interleaved as XR 0 XI 0 XR 1 XI 1 XR N 1 XI N 1 Because of this arrangement the length of the array is 2N instead of N and IRO is set to 512 instead of 256 Example 3 4 Bit Heversed Addressing ITLE BITtREVERSED ADDRESSING HIS EXAMPLE MOVES THE RESULT OF THE 512 POINT FFT COMPUTATION POINTED AT BY ARO TO A LOCATION
149. bit SRAMs with 16 and 32 bit data accesses 4 81 cache 5 5 interfacing to the C32 4 21 to 4 22 D 1 to D 5 out COFF file 4 90 1 bank 2 strobes 32 bit wide design examples 4 49 1 bank 2 strobes address translation for data size equal to 16 and 32 bits 4 55 1 bank 2 strobes address translation for data size equal to 16 and 8 bits 4 51 1 bank 2 strobes adaress translation for data size equal to 32 and 8 bits 4 53 16 8 bit memory configuration design examples 4 41 16 bit data stored in 16 bit wide memory D 10 16 bit data stored in 32 bit wide memory D 7 16 bit data stored in 8 bit wide memory D 13 32 bit data stored in 16 bit wide memory D 9 32 bit data stored in 32 bit wide memory D 6 32 bit data stored in 8 bit wide memory D 12 Index 5 Index 32 bit memory configuration design examples 4 35 8 bit data stored in 16 bit wide memory D 11 8 bit data stored in 32 bit wide memory D 8 8 bit data stored in 8 bit wide memory D 14 booting in a C environment 4 86 data and program packing D 2 debugger boot 4 91 EPROM boot 4 95 generating a COFF file 4 86 loading a COFF file to the target system 4 91 logical versus physical address 4 33 microcomputer boot loader mode 4 96 microprocessor mode 4 95 program fetch from 16 bit STRBO memory 4 29 program fetch from 32 bit STRB1 memory 4 31 RAM model 4 92 RDY signal generation 4 57 ROM model 4 92 STRBO and STRB1 data access 4 25 4 27 TMS320 tools 4 67 variable memory width D 4 interfaci
150. bit reversed buffers a pointer to the allocated space is returned SYSMEMSB SIZE an external label that contains the size in words of the 8 bit system memory pool 4 7 1 3 MEMORY16 C Module The MEMORY16 C module contains functions that implement dynamic memory management routines for the C32 s 16 bit data See the TMS320C3x C4x Optimizing C Compiler User s Guide for more information on 16 bit runtime support functions The pragma directive in the MEMORY 16 C module defines a sysm16 section The size of this memory pool in words system memory or heap is set at link time by using the heap16 option If the heap16 option is not used the compiler does not allocate a 16 bit system memory area If arguments are not used in conjunction with this switch the size of the 16 bit system memory area Memory Interfacing 4 71 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface defaults to 1K 16 bit words The following functions operate in the 16 bit Sysm16 section minit16 initializes and resets the 16 bit dynamic memory management system D malloc16 allocates 16 bit words from the 16 bit memory pool and re turns a pointer to the allocated space Lj calloc16 allocates 16 bit words from the 16 bit memory pool clears al located memory locations and returns a pointer to the allocated space realloc16 reallocates 16 bit words from previously unallocated areas in the 16 bit memory pool a point
151. calls or interrupts It can be extensive or simple depending on system require ments On the C3x the program counter is automatically pushed onto the stack Important information in other C3x registers such as the status auxilia ry or extended precision registers must be saved by special commands To preserve the state of the status register push it first and pop it last This keeps the restoration of the extended precision registers from affecting the status register Example 2 4 on page 2 13 and Example 2 5 on page 2 15 show saving and restoring the context of the C3x In both examples the stack expands towards higher addresses and is used for saving the registers If you do not wantto use the stack pointed at by SP you can create a separate stack by using an auxilia ry register as the stack pointer Registers saved in these examples are Extended precision registers R7 through RO Auxiliary registers AR7 through ARO Data page pointer DP Index registers IRO and IR1 Block size register BK Status register ST Interrupt related registers IE and IF I O flag IOF Repeat related registers RS RE and RC O D DU DC D D LU L You must preserve only the registers that are modified inside of your subrou tine or interrupt trap service routine and that could potentially affect the pre vious context environment Program Control 2 11 Context Switching in Interrupts and Subroutines If the previous context
152. can be used to create set directives rather than asg 5 10 Addressing Peripherals as Data Structures in C 5 6 Addressing Peripherals as Data Structures in C A data structure is usually assigned to the bss section by the C compiler A bss section stores global and statically allocated variables A peripheral such as a serial port has memory mapped control registers with addresses differ entfrom bss To manipulate a memory mapped peripheral register in C follow one of the methods listed below Lj Method 1 Use a pointer to the peripheral Pointer Address 0x808000 Peripheral as memory locations 1 Declare a structure that logically represents the memory locations of the peripheral struct controller unsigned int status 2 Declare a pointer to the structure and initialize it to the peripheral s ad dress struct controller IFperipheral struct controller 0x808000 3 In your code access the peripheral s memory values indirectly IFperipheral status 0 Method 2 Place the structure in its own section 1 Declare a peripheral instead of a pointer struct controller IFperiph 2 Use inline assembly to give the structure its own section asm IFperiph usect periph 128 128 is size of struct This creates a user defined section that can be linked to any ad dress 3 Use your linker command file to map the section to memory periph load 0x80800
153. coded for speed optimization Leor Brenman DSP Applications C 1991 TEXAS INSTRUMENTS HOUSTON globl c int08 global variables ck ck ck ck ck ck ck kk ck Sk ko A ko ko ok global first half input xfer0 input xferl buffer size global buffer index output xferO0 global output xferl _output0 outputl data control global buffer rdy inputO inputl global variables data ER 1 word 808050h place in same page as bss to eliminate push pop of DP when loading serial port one s base address n Fi Ck Ck ck ck Ck Sk ck ck ck ce Sk ck C Sk ck Ck Sk ck Ck ck ck ck ck ck ck ck ck ck ck Ck ck ck Ck ck KKK ck kk kk KKK KKK KKK KKK FUNCTION DEF c int08 text C int08 PUSH ST PUSH RO PUSHF RO PUSH ARO Analog Interface Peripherals and
154. coefficients propagation terms Low k 1 b 0 n 1 address i k 2 b 1 n 1 e e e e e e High k p b p 1 n 1 address Example 6 9 shows the implementation of an inverse lattice filter Example 6 9 Inverse Lattice Filter 0X A 0X F F X X F HF 0X TITLE INVERSE LATTICE FILTER SUBROUTINE LA LATIN TYPICAL CA INV AT ICE FILTER LPC INVERSE FILTER ANALYSIS LING SEQUENCE load R2 load ARO load AR1 load RC CALL LATINV ARGUMEN ASSIGNMENTS ARGUMEN FUNCTION R2 f 0 n x n ARO ADDRESS OF FILTER COEFFICIENTS k 1 AR1 ADDRESS OF BACKWARD PROPAGATION VALUES b 0 nt1 RC RC pt2 REGISTERS USED AS INPUT R2 ARO AR1 RC REGISTERS MODIFIED RO R1 R2 R3 RS RE RC ARO ARI REGISTER CONTAINING RESULT R2 f p n DSP Algorithms 6 19 Lattice Filters Example 6 9 Inverse Lattice Filter Continued PROGRAM SIZE 10 WORDS EXECUTION CYCLES 13 3 ptl global LATINV Gel LATINV MPYF3 ARO AR1 RO ky b 0 nt1 gt RO Assume 0 n gt R2 LDF R2 R3 Put b 0 n 0 n R3 MPYF3 ARO 1 R2 R1 k 1 0 n gt R1 RPTB LOOP MPYF3 ARO AR1 1 RO k i b itl ntl1 RO ADDF3 R2 R0 R
155. cycle s RDY setup requirement 33 18 15 ns if not modified To deactivate the RDY signal sooner a single register circuit is added to generate the RDY B23NOT which when ORed with the RDY B23YES yields the RDY_BANK23 signal that satisfies the RDY setup time for the next cycle Fi nally RDY BANK1 and RDY BANK23 are ANDed together to produce the fi nal RDY signal that is wired to the processor s RDY pin Figure 4 30 RDY Signal Generation Timing Waveforms Owait V 1 wait state v 3 wait states Y Owait V Owait bank 1 bank 2 bank 3 bank 1 bank 1 NL AA No ONLUS NN NA 8ns Ww STRBO BX 8ns q b dh 8ns M 8ns 8ns 4 gt 8ns gt k 5ns STRBO_Bank23 N 5ns j p e 5ns M 5ns RDY_Bank1 N TM m gt 10 ns f 10ns k P lt 10ns gt W 10 ns RDY B23YES NY 5 ns lq 9 M 5ns 5ns e M 5ns RDY B23NOT _ No 10 ns gt M 10ns RDY Bank23 N I N l RDY x 20ns 20ns 23ns 23ns 33 ns 33 ns 23 ns 20 ns 33 ns 4 4 s Actual RDY 33 ns cycle 17 ns RDY a Setup time time 60 MHz setup required Buioejuaju AIowayy 9 7 dS ZED0ZESWL 94 0 Aowa Bureau Interfacing Memory to the TMS320C32 DSP 4 6 7 Address Decode for Multiple Banks 4 64
156. data size 32 bits driving the STRBO BO STRBO B1 STRBO B2 and STRBO B3 control pins because STRB CONFIG 1 to read the contents of a 32 bit data location in the upper half of the external memory addressed by 7FFFh to the 32 bit R1 register The C32 automatically performs all address translation the programmer merely monitors the logical memory map and the two strobe control registers Memory Interfacing 4 55 amp Figure 4 27 One Bank Two Strobes Address Translation Data Size 16 and 32 Bits o STRB Memory Data Ph configuration width size ysica Logical Logical 9 p address memory STRBO amp 1 32 bits 16 bits map address STRBO control register sew 14 Ta E PE STRB1 control register SI 14 m DOG Li 32 bits 32 bits v vy y y vy x o oe o o T T T n to i 880000h Oh 2 1 j A18 A14 A 1 Logicaladdress B 5 STRBO p rooo tofoj rrr iiti siii iin e 1000 10 o o i Physical address A17 A43 Ao 32766 32767 32764 32763 EN corre y 32766 027e 16 bit data size address shifted by 1 bit 3FFFh 32767 IOSTRB 32 bit data size address not shifted 4000h 1 J 1 920000h 2 I A A A 2 3 3 Logical address
157. design from both the hardware and software ad dressing perspectives Figure 4 20 contains a schematic diagram of the external memory interface consisting of two banks each controlled by a separate strobe Two of four STRBO signal lines are assigned to the chip select pins of two 32K x 8 15 ns SRAMs one of four STRB1 signals is connected to a chip enable pin of one 32K x 8 30 ns EPROM For the 60 MHz version of the C32 the 15 ns SRAMs operate at zero wait states and the 30 ns EPROMs require one wait state Software wait states can be programmed in strobe control registers Any time the external memory is less than 32 bits wide some of the strobe pins switch functions and become additional address pins For 16 bit wide memory STRBO B3becomes A 4 for 8 bit wide memory STRB1 B3and STRB1 B2 become A 4 and A_ respectively This is the only external change that differ entiates the 32 bit wide memory interface from the 16 and 8 bit wide memory interfaces This feature can be considered transparent to the software pro grammer except that the programmer must configure the strobe control regis ters appropriately The memory interface automatically drives the additional address lines with correct values depending on the size of the data being transferred Thefollowing three sections illustrate how the physical addresses are derived from the logical addresses when the data size is equal to greater than and less thanthe width ofth
158. destination for the first and third block of each boot table is 16 bit STRBO memory The second block is booted to the 32 bit IOSTRB memory Block 4 is destined for the 8 bit memory in the STRB1 por tion of the memory map Each figure represents a boot from a different source medium In Figure A 1 the boot table resides in the 32 bit IOSTRB memory Itis pointed to by the INT1 pin low after reset in the microcontroller boot loader mode The boot table in Figure A 2 is stored in the 16 bit STRBO memory pointed to by INTO The boot table in Figure A 3 resides in the 8 bit STRB1 memory pointed to by INT2 The final example shown in Figure A 4 represents the boot table stored in the host memory before being sent to the C32 over the serial port Unlike the boot from memory the serial port boot table omits the memory width control word from the beginning of the table The shaded areas of the boot table examples represent the contents of the in dividual blocks of code or data The unshaded portions are the control words that instructthe boot loader program to transfer the blocks to the memory map A 1 TMS320C32 Boot Table Examples Figure A 1 Boot From a 32 Bit Wide ROM to 8 16 and 32 Bit Wide RAM A 2 Source Boot Destination Block address table address data 810 000 0000 0020 810 001 1000 00F8 810 002 2005 10F8 810 003 3000 10F8 810 004 6 810 005 0000 1400 810 006 0510 F864 Block 1 16 bit wide exter
159. e e gt e X 5 wO e gt gt X 6 LM e X 7 wO0 DSP Algorithms 6 29 Fast Fourier Transforms FFTs Figure 6 9 Decimation in Frequency for 8 Point FFT Stage 1 Stage 2 Stage 3 6 6 2 Complex Radix 2 DIF FFT 6 30 Example 6 13 and Example 6 14 show the implementation of a complex radix 2 DIF FFT on the C3x Example 6 13 contains the generic code of the FFT which can be used with a FFT of any length However for the complete implementation of an FFT you need a table of twiddle factors sines cosines the length of the table depends on the size of the transform A table with twiddle factors containing 1 1 4 complete cycles of a sine is presented separately in Example 6 14 as a 64 point FFT This retains the generic form of the radix 2 DIF FFT in Example 6 13 A full sine wave must have an equal number of samples as the length of the FFT Example 6 14 uses two variables N which is the FFT length and M which is the logarithm of N to a base equal to the radix In other words M is the number of stages of the FFT For example in a 64 point FFT M 6 when using a radix 2 algorithm and M 3 when using a radix 4 algorithm If the table with the twiddle factors and the FFT code are kept in separate files they will be connected at link time Fast Fourier Transforms FFTs Example 6 13 Complex Radix 2 DIF FFT
160. eee Z E 1 q 0 S3Aczd AQU goued ady ao Ono JON8zg AGH t 4 Adu OXS4 pueg qd ojels m oxa lem fore IBM p OYTO H 0HS li 1 E ee I ji I ru mW ZHW 09 NM d Hd Hd Hd Di IS o0 4 o 4 HEISE TOL D0 o a ONG ONE to ap OX 10L u19 u19 u19 H19 0H iguls i 4 Lg Lays ifa zyueg ogHlS 8cyueg ogdis evyzg ays ONW3 i t a6 semis vied 18u1S a Sueg ogus A enna 8uisol E A O f CR ww CES H Cry apoosp bey apooap fey f 1 opener y 8 yueg z yueg xueg 0d 0gdlS P 4 id 0gy1S ETE 43X v ed 0gdlS 04x vied oguis ovi ELNI ZLNI e B gt 30 ai 30 30 a0 3o i LINI me 1 0 Mud 39 bry a so so so so OLNI el Oy 3M 3M 3M 3M vI 0y GOH va10H dW 18OW 29A ZHS e e e NH cv ov idSdu NOHd3 8 X 2 ueg INv HS Z X 8 X JZE z ueg INVHS t X 8 X YZE yueg n ZED0ZESNL sejo 2 0gH1S 40J uoieeues eU IS AGY 6Z r e1nDi 4 61 Memory Interfacing Interfacing Memory to the TMS320C32 DSP 4 62 Figure 4 30 contains timing waveforms for RDY signal generation It illus trates how the RDY signal is generated for a series of external back to back memory read cycles in which the first cycle accesses bank 1 zero wait states the second cycle accesses bank 2 one wait state the third cycle accesses bank 3 three wait states and the fourth and fifth cycles access bank 1 zero wait states For each read cycle the RDY waveform is marked w
161. effect on the circuit Figure 8 4 shows the timing diagram of a write operation to the DAC latches Analog Interface Peripherals and Applications 8 7 Digital to Analog Converter Interface to the TMS320C30 Expansion Bus Figure 8 4 Timing Diagram for Write Operation to the DAC 8 8 MN QN XA12 IN to I k t4 IOSTRB N IOW N ts k te Because the data is written to the latches rather than to the DAC the timing requirements for these devices are fundamental to the operation of the inter face At a minimum these latches require Data setup time of 20 ns Enable setup time of 25 ns Disable setup time of 10 ns Data and enable hold times of 5 ns This design provides approximately 60 ns of enable setup 30 ns of data setup and 7 2 ns of data hold time Therefore the setup and hold times provided by this design exceed those required by the latches The key timing parameters for this interface are summarized in Table 8 1 Digital to Analog Converter Interface to the TMS320C30 Expansion Bus Table 8 1 Key Timing Parameters for DAC Write Operation Time Interval ty t2 ts t4 t5 t6 t Timing for the C30 33 Event H1 falling to address valid XA12 to XA12 delay H1 rising to lOSTRB falling TOSTRB to IOW delay Data setup to TOW Data hold from IOW Time Periodt 10 ns 5 ns 10 ns 5 8 ns 30 ns 7 2 ns Analog Interface Peripherals and Appli
162. environment was in C then your program must perform one of two tasks Ifthe program is in a subroutine it must preserve the dedicated C registers as follows Save as Integers Save as Floating Point R4 RS R6 R7 AR4 AR5 AR6 AR7 FP DP small model only SP Lj Ifthe program is in an interrupt service routine it must preserve all of the C3x registers see Example 2 6 on page 2 17 If the previous context environment was in assembly language you must de termine which registers to save based on the operations of your assembly language code Note The status register must be saved first and restored lastto preserve the proc essor status without further change caused by other context switching in structions l M M J Context Switching in Interrupts and Subroutines Example 2 4 Context Save for the TMS320C3x SAVE ts bits ts bits ts bits ts bits ts bits ts bits ts bits ts bits TITLE CONTEXT SAVE FOR THE TMS320C3x global SAVE CONTEXT SAVE ON SUBROUTINE CALL OR INTERRUPT E PUSH SI z Save status register SAVE TH EXTENDED PRECISION REGISTERS PUSH RO A Save the lower 32 bi PUSH RO and the upper 32 PUSH R1 x Save the lower 32 bi PUSH R1 H and the upper
163. for C30 12 1 to 12 26 characteristics for C30 12 2 to 12 4 dependency 12 2 photo of Ipp for FFT 12 26 test setup description 12 4 to 12 5 power supply current factors of 12 2 internal circuitry 12 5 prefix designators 11 9 primary bus interface 4 4 C30 addressing up to 68 gigawords 4 107 bank switching techniques 4 15 ready generation 4 10 to 4 20 ANDing of the ready signals 4 11 example circuit 4 14 external ready generation 4 11 ORing of the ready signals 4 10 ready control logic 4 13 zero wait state to static RAMs 4 5 to 4 9 primary communications 8 25 data format 8 25 mode selection 8 25 processor initialization 1 2 program control 2 1 to 2 22 computed GOTOs 2 22 delayed branches 2 17 interrupt service routines 2 9 to 2 10 context switching 2 11 example 2 10 priority 2 10 to 2 18 repeat modes 2 18 to 2 21 block repeat 2 18 single instruction repeat 2 20 Software stack 2 5 to 2 8 subroutines 2 2 to 2 4 programming tips 5 1 to 5 18 C callable routines 5 2 to 5 4 DMA 7 2 hints for assembly coding 5 5 to 5 6 low power mode wakeup example 5 7 to 5 8 queues 2 8 RDY signal generation C32 4 57 STRBO signals 4 60 timing parameters for STRBO and STRB1 4 58 ready control logic 4 13 ready generation 4 10 to 4 20 ANDing of the ready signals 4 11 example circuit 4 14 external ready generation 4 11 functions 4 12 ORing of the ready signals 4 10 Index ready control logic 4 13 repeat mode 2 18 to 2 21 b
164. from crystal manufacturers Design Considerations Figure 9 16 Example Frequency Temperature Characteristic of AT Cut Crystals 9 4 7 Crystal Aging 30 20 Fi Frequency Shift ppm 55 45 35 25 15 5 5 15 25 35 45 55 65 75 85 95 105 Temperature C Crystal aging is the gradual change in the frequency of acrystal over time This change occurs due to stress relief between the mounting structure and the electrodes and absorption or deabsorption of contaminants from the resona tor surfaces Changes in temperature accelerate both of these mechanisms The major mechanism for aging in crystals above 1 MHz is mass transfer to and from the resonator surfaces The most rapid aging occurs early in the crys tal s lifetime and then aging tends to stabilize For example acrystal that ages 10 60 parts per million ppm in a year experiences 5 ppm of that aging in the first month Crystals are available at additional expense that have very low aging rates due to cleaner fabrication and packaging processes These crys tals have aging characteristics as low as 1 x 10 8 ppm per year Complete in formation on aging characteristics is available from crystal manufacturers Clock Oscillator and Ceramic Resonators 9 21 Oscillator Solutions for Common Frequencies 9 5 Oscillator Solutions for Common Frequencies The oscillator solutions in this section were built and tested with samples from the manuf
165. i n 1 y i 1 n y i n b2 i d i 2 bl i d i n 1 bO i d i n y In y IN 1 n Figure 6 3 shows the corresponding memory organization while Example 6 7 shows the C3x assembly language code Figure 6 3 Data Memory Organization for N Biquads Filter Initial delay Final delay coefficients node values node values Newest delay d 0 n d 0 n 1 Oldest delay _d 0 n 2 Low address Circular queue e d N 1 n 1 d N 1 n 2 Circular queue d N 1 n address You must initialize the block register BK to 3 the beginning of each set of d val ues that is d in i 0 N 1 must be at an address that is a multiple of 4 where the last two bits are 0 6 12 Example 6 7 IIR Filters N gt 1 Biquads FIR IIR and Adaptive Filters TITLE IIR FILTERS N 1 BIQUADS SUBROUTINE IIR2 EQUATIONS y 0 n x n FOR i O i lt N itt d i n a2 i d i nt2 al i d i ntl y itl n y i n b2 i d i nt2 bl i d i ntl bO i d i n TYPICAL CALLING SEQUENCE ui y n y N 1 n TYPICAL CALLING SEQUENCE load R2 load ARO load AR1 load IRO load IR1 load BK load RC m CALL IIR2 ARGUMEN ASSIGNMENT ARGUMEN FUNCTION t R2 INPUT SAMPLE x n ARO ADDR
166. identical In this example STRBO also operates on 32 bit data since the memory width field of the STRBO control register contains a binary value of 11 Since the STRBO physical memory width is also 32 bits see data size field in Figure 4 17 there is no need for address translation from the logical address to its physical representation Memory Interfacing 4 35 Interfacing Memory to the TMS320C32 DSP T OLO0 st COGN T CO RoOwtTONrd RoOwWTONTrS oaQoaoaooaoaag a oaa8 e 8xyzg Wvus IS 8 x yze NOHd3 TON O FON or 0 C C C C C t C C t t t t t x x C C C X C C C C t t T t t x dx St CO QN CO O 00 P CO LO E CO QN CO C C C t C t t t t wt OFN LeLTOO oQoaoaoaoaoaaoao KONVINT o oQoaoaooaoaag aj a oaa8 w B O 8 x YZE NVHS 8 x 42 NOHd3 TON O FON O v c c o0 0 O 00l O10 st CO QN COD v7 0707 3 OD OO l CO LO SF CO QN CO C C C C C t C C C t t t t x x C C C C C C C C C C t t t t ax RoOwtTONrd I OL0 sF CO QN CO OQoaoaooaoaag aooaoooaao IS Is 8 x 42 NVHS 8xyzg NOHda lo ZOjTPTooroosoa o SOS TP ooroosoa o C C C C C C C t t t t t t sa C C C C
167. indicate registers TMS320C32 Boot Loader Program B 3 TMS320C32 Boot Loader Opcodes B 2 TMS320C32 Boot Loader Opcodes B 4 Table B 1 lists the C32 bootloader opcodes shown in boldface type In most cases an opcode is the first byte of the machine code that describes the type of operation and combination of operands interpreted by the central proces sing unit CPU Table B 1 ADDRESS 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 00000008 00000009 0000000A 0000000B 0000000C 0000000D 0000000E 0000000F 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 Ej O OQ UB D w 0 100 50 MNH O o F 00000020 00000021 00000022 00000023 00000024 00000025 00000026 00000027 00000028 00000029 0000002A 0000002B 0000002C 0000002D 00000025 0000002F 00000030 00000031 00000032 00000033 TMS320C32 Boot Loader Opcodes OPCODE 00000045 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0000
168. interrupt processing INTO word IMEO Timer 0 interrupt processing INT1 word IME1 Timer 1 interrupt processing DINT word DMA DMA interrupt processing Space 20 H Reserved space TRAPO word TRPO Trap 0 vector processing begins TRAP1 word TRP1 Trap 1 vector processing begins TRAP2 word TRP2 Trap 2 vector processing begins Space 29 Leave space for the other 29 traps IN THE FOLLOWING SECTION CONSTANTS THAT CANNOT BE REPRESENTED IN THE SHORT FORMAT ARE INITIALIZED THE NUMBERS IN PARENTHESES AT THE END OF EACH COMMENT REPRESENT THE OFFSET OF THE REGISTER FROM 808000H CTRL Processor Initialization 1 5 How to Initialize the Processor Example 1 1 TMS320C3x Processor Initialization Continued data MASK word OFFFFFFFFH BLKO word 0809800H Beginning address of RAM block 0 BLK1 word 0809C00H Beginning address of RAM block 1 STCK word 0809F00H Beginning of stack CTRL word 0808000H Pointer for peripheraltbus memory map DMACTL word 0000000H Init for DMA control 0 TIMOCTL word 0000000H Init of timer 0 control 32 TIMICTL word 0000000H Init of timer 1 control 48 SERGLOBO word 0000000H Init of serial 0 glbl contro
169. iof seetup and iof0 1 LDI timer setup AR7 setup timerO and timerl STI AR7 QGtimer0O control A STI AR7 timerl_control LDI rx_int_vector AR7 load intO interrupt vector STI AR7 QGintO0 vector OR int setup IE enable interrupts POP AR7 RETS Start bit received external interrupt service routine RX INTO USH AR7 XOR Lh Ie disable int0 LDI alf bit time AR7 SII R7 Gtimer0O period rx timer period imerO0 vector AR7 H R7 8 timer0 int vect rx timer int vector imer go AR7 R7 timer0_control Start rx timer Ah AR7 R7 8irx counter reset rx counter R7 cn t H DoD Oct ra Potty Analog Interface Peripherals and Applications 8 67 Software UART Emulator for the TMS320C3x Example 8 17 Full Duplex UART Emulator for TMS320C3x Continued Timer0 interrupt service routine for byte reception RX TMR INT LDI CMPI BNE CMPI BLT OR INTO OK SUBI STOP ONE RORC LDI STI CLEANUP CLEANUP2 PUSH AR7 Grx counter AR7 09h AR7 OP Oh IOF Cocoon FR oH wo fl h Il EANUP2 h AR7 R7 rx_counter hole bit time AR7 R7 Qtimer0 period imer go AR7 R7 timerO_crontrol R7 p pptpip poo AR6 Qrx byte AR6 AR7 NEXT 080h IOF BAD STOP BIT 24 AR6 AR6 Q8rx byte Olh IE CLEANUP 080h IOF Olh ST ONE Olh ST A A A t A R6 R6 Qrx byte
170. k e e x amp f GENERAL C3x MACROS BRK KK KC KC kCk kCk kCK kCK CKCKCKCK KCKCKCK KCK CKCK KCK CKCK KCK KCK KCKCKCK KCKCKCK KCK KCK KCK CK k kk k ck ck ck ck ckck ck ck kc k kx k x e x ifndef INIT XF PINS define INIT XF PINS asm LDI 00h IOF endif ifndef CL INT FL REG define CL INT FL REG asm LDI Oh IF endif ifndef EN_GLOBAL_INTS define EN GLOBAL INTS asm OR 2000h ST endif ifndef EN_SER_PORT_XMT_I 0 define SER PORT XMT I 0 asm OR 10h IE endif ifndef EN SER PORT RCV INT O define EN SER PORT RCV INT 0 asm OR 20h IE endif ifndef EN SER PORT XMT I define SER_PORT_XMT_I 1 asm OR 40h IE endif ifndef EN_SER_PORT_RCV_INT_1 define EN SER PORT RCV INT 1 asm OR 80h IE endif ifndef ENABLE CACHE define ENABLE CACHE asm OR 800h ST endif endif ifndef GENERAL Analog Interface Peripherals and Applications 8 45 CS4215 Interface to the TMS320C3x Example 8 13 Commarvr h finclude c30 per h COMMON STRUCTURES typedef volatile int void c int99 void void init c30 void BORK RK KK KK kCk kCKCKCKCkCK KCKCKCK KCKCKCK KCK KCK KCKCKCK KCKCKCKCKCKCKCK KCKCKCK KCK KCk KCk k ck k ck ck ck ck ck ck ck ck kc k OR x k f COMMDRVR
171. ke ko ke ke ke ke ke ke ke ke ke ke e ee e e e e x f general h v4 2 Copyright c 1991 Texas Instruments Incorporated KK Ck Ck Ck kk Ck Ck Ck Ck A EC KC ECKE KC Ck Kk Ck Ck A I Ck Ck Ck Kk kk kk kk kc ko kk kc ke ke ke ke ke ke ke e ke e ee e e e e x ifndef GENERAL define _GENERAL KK HK Ck Ck Ck Ck I A IA I A IA A I I IA IA I IA A IA A ke ko ke ke ke ke ke ke e e e ee e e e e x f COMMON MACRO DEFINTIONS J KOECKCECK Ck Ck kk Ck kk Ck Ck Kk Ck Ck Ck Kk Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck kk kk kk kk kk ke ko ke ko ke ke ke ke ke e e e e e e ifndef OFF define OFF 0x00 endif ifndef ON define ON 0x01 endif ifndef FALSE define FALSE endif 0x00 ifndef TRUI define TRUE 0x01 endif E ifndef CLI define CLEAR 0x00 endif ifndef S define S endif El Dj 0x01 8 18 Burr Brown DSP101 2 and DSP201 2 Interface to TMS320C3x Example 8 3 General Macro Definitions Continued BORK KK KK kCk kCkCkCK kCK KCK kCKCKCK CkCK KCK KCKCKCK CKCK KCKCKCK KCK KCK KCK KCK KCK KCK KCK KCK CK K k ck k ck k ck ck ck ck ckck kk e k A ke x GENERAL C3x MACROS uu BRK KR RA RAR AR kCk KCKCKCK KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCk k ck k ck ck ck ck ckck ck ck ck ck ck ks sk e ke X ke I f ifndef INIT XF PINS define INIT
172. ke x 4 7 RK HK IK kk I kk I kk kk kk kk kk I kk kk kk kk kk kk kk ck kc kk ck kc kc I I I ck ck ok ckck ck ck ck ck ckok ck ck ko ko ke x a E ky x suf A Ry xJ u EJ RUE 8 50 CS4215 Interface to the TMS320C3x Example 8 15 CS4215 h Continued J KOKCKCECK Ck Ck kk Ck Ck Ck Ck Ck Ck Ck Ck Ck Kk Ck Ck Ck Kk Ek kk Kk kk kk kk kk kk kk ke ke ke ke ke ke ke ke ke eoe ee e e kx x f DATA COMMANDS J KOKCKCKCK Ck Ck kk Ck Ck Ck IA A IA I IA I A I IA A IA I kc ko ke ke ke ko ke ke ke ke ke ee eoe ee e e ee kx x f typedef union unsigned int _intval 2 struct Time slots 3 amp 4 signed int right i165 Right channel 16 bit ay Time slots 1 amp 2 signed int left Log Left channel 16 bit Time slot 8 unsigned int rg 24 Right input gain set
173. memory When evaluating external write activity in a given program segment you must consider whether a particular level of external write activity is significant If writes are performed at very slow rates on both the primary and the expansion buses the current from external writes can be ignored If writes are performed at high speed on only one of the two external buses you should calculate cur rent requirements Although you can obtain negative incremental current values under some circumstances the total contribution for external buses including baseline current is always positive When external buses are not used much the total current requirements approach the current contribution from the internal fac tors which is solely a function of internal activity This places a lower limit on current contributions from the primary and expansion buses because the total current from external buses is the sum of the 60 mA baseline value and the primary and expansion bus factors This effect is discussed in further detail in the rest of this section Once you establish bus write cycle timing use Figure 12 4 to determine the contribution to supply current from this bus activity Figure 12 4 shows current contributions from the primary bus for various numbers of wait states and H1 cycles between writes This current contribution is exhibited when writes of al ternating 55555555h and AAAAAAAAh are performed at a capacitive load of 80 pF per ou
174. mode serial port 1 GLOBAL serial port 1 GLOBAL amp OxFFFFF3FF if transmitting to DAC make sure to write to the transmit register no later than 3 SCLK CLKX cycles before the rising edge of FSYNC 8 34 TLC320AD58 Interface to the TMS320C3x Example 8 7 Interfacing the 18 bit TLC320AD58 to TMS320C3x Continued else read RIGHT channel and normalize within 1 0 1 0 r channel float serial port 1 R DATA 14 4 0 65536 switch to continuous made serial port l1l1 GLOBAL serial port 1 GLOBAL 0x0C00 if transmitting to DAC make sure to write to the transmit register no later than 3 SCLK CLKX cycles before the next transfer ur Subroutine to initialize TLC320AD58 a void init_ad58 void asm ldi 0010b IOF reset XF0 power down AD58 asm rpts 2500 ys wait for 100 usee before asm 7 nop ir asserting DigPwd asm ldi 0110Db IOF AD58 normal operation Analog Interface Peripherals and Applications 8 35 TLC320AD58 Interface to the TMS320C3x Example 8 8 C3x h Header File Listing p FILE C3X H EJ TMS320C3X CONTROL REGISTER SETTINGS TO SETUP INTERFACE WITH ad TLC320AD58 18 BIT MASTER MODE i Ej Serial Port 1 Initialization
175. number ABSI RO RO CMPI 1FDEH RO i If RO gt Ox1FDE LDIG 1FDEH RO saturate the result ADDI 33 R0 Add bias FLOAT RO s Normalize seg 5 OWXYZx x MPYF 0 03125 R0 Adjust segment number by 2 t5 LSH 1 R0 seg WXYZx x PUSHF RO POP RO E Treat number as integer LSH t20 R0 Right justify LDI 0 R2 LDI R1 R1 E If number is negative LDILT 80H R2 f set sign bit ADDI R2 R0 H RO compressed number NOT RO Reverse all bits for transmission RETS DSP Algorithms Companding Example 6 2 u Law Expansion TITLE U LAW EXPANSION k SUBROUTINI E UXPND ARGUMENT ASSIGNMENTS ARGUMENT FUNCTION ni RO NUMBER TO BE CONVERTED REGISTERS USED AS INPUT RO REGISTERS MODIFIED RO R1 R2 SP REGISTER CONTAINING RESULT RO CYCLES 20 WORST CASE WORDS 14 global MUXPND MUXPND NOT RO RO H Complement bits LDI RO R1 AND OFH R1 Isolate quantization bin LSH IRI ADDI 33 R1 i Add bias to introduce 1xxxxl LDI RO R2 Store for sign bit LSH 4 R0 AND 7 RO n Isolate segment cod LSH3 RO R1 RO Shift and put result in RO SUBI 33 R0 A Subtract bias TSTB 80H R2 Test sign bit RETSZ NEGI RO Negate if a negative number RETS 6 4 Example 6 3 A Law Compression Companding TIIL n ARGU UBROUTINE ACMPR EN ASSIG E
176. olt donee 6 22 IIR Filters ioi aei iieaeoe ea rer ude CE a Eo C ede does 6 2 8 Adaptive Filters Least Mean Squares Algorithm i 6 3 Lattice Fillers sretala ntra Phera AAEN AEA Use pas vos wide paruus 6 4 Matrix Vector Multiplication ssssssseeee IRR 6 5 Vector Maximum Search i 6 6 Fast Fourier Transforms FFTs 0 6 6 1 FFT Definition ei eme Ree RR anaes hye e aes cuca es meas 6 6 2 Complex Radix 2 DIF FFT i 6 6 8 Complex Radix 4 DIF FFT i annoi Da i uiii aieea 6 6 4 Real Radix 2 FFT ei tha wins bi adie enka op edhe eee en 6 7 TMS320C3x Benchmarks 0000 c cece ssh 6 8 Sliding FET so oe pe Ierker ue reU REX Rx YU heey PEUPLE 6 8 1 SFFT Theory A Better Way to Use the Impulse Response 6 8 2 Frequency Response Calculation i 6 83 Visualizing the SFFT epes wo eee da ed a 6 8 4 Fbin Convergence and Stability i 6 85 SFFT Windowing was so ed a de da a ed ead 6 8 6 Using SFFT ASM for Spectrum Analysis i 6 8 7 Using SFFT ASM for Hilbert Transforms and Arbitrary Phase Angles Filters i 6 8 8 Raised Cosine Windowed Filters i 6 89 Non Windowed SFFT 0000 cece cece enn 06 8 10 Performance ces oer aided ath RUE RE weep dead ERA ER DRE 6 8 11 Loop Unrolling for High Speed Filtering i 6 8 12 Fitting the Code and Data Into Memory i 6 8 13 Using This Code With C ae ee en ee nenia ni a eai 6 8 14 TLC32040 ADC and DAC Considerations i 6 8 15 SEE T Summary sari ee bed a eae i e
177. presented by the bank memory predicts propagation delays atthe output of the buffers to a maximum of 16 ns The access time of a read cycle within a bank of the memory is the sum of the memory access time and the maximum buffer propagation delay 25 16 41 ns Since this propagation delay falls between 30 and 90 ns it requires only one wait state on the C3x 33 The 74ALS254 buffers offer an additional system performance enhance ment they include 25 0 resistors in series with each buffer output These re sistors greatly improve the transient response characteristics of the buffers especially when driving CMOS loads such as the memories used here The effect of these resistors is to reduce overshoot and ringing which are common Wait States and Ready Signal Generation when driving predominantly capacitive loads such as for CMOS devices The result is reduced noise and increased immunity in the circuit which in turn results in a more reliable memory system Having these resistors included in the buffers eliminates the need to put discrete resistors in the system which is often required in high speed memory systems This circuit cannot be implemented without bank switching because the data output s turn on and turn off delays cause bus conflicts The propagation delay of the 74ALS138 multiplexer is involved only during bank switches when there is sufficient time between cycles to allow new chip selects to be decoded Figure 4
178. produce a crystal that meets both of these requirements The oscillator circuit used on the C3x devices requires a parallel resonant crystal 9 2 2 Crystal Response to Square Wave Drive Figure 9 5 a shows the equivalent circuit model of a crystal driven by a step function voltage source in series with a resistive load In this figure the capaci tance or Co of the crystal model is ignored because it is usually considered part of the load on the crystal and does not strongly affect the series resonant frequency When a step function excites a crystal the crystal produces damped sinusoidal oscillation at its series resonant frequency as shown in Figure 9 5 b The magnitude of the damping on the output waveform is pro portional to the magnitude of Ry The lowest natural frequency of the crystal is the fundamental frequency De pending on the design of the crystal it can also have contributions to its output waveform from odd multiples of the fundamental frequency or overtones However if the response at the fundamental frequency is considerably stron ger than the response at these overtone frequencies the contribution of the overtones to the output waveform is negligible If the step function input is changed to a square wave drive a periodic set of step functions at the frequency of the fundamental the output of the crystal is sinusoidal as shown in Figure 9 5 c The source of the square wave pro vides enough energy to over
179. prog AIC ldi SO_xdata R1 Use original DXR data during 2 ndy sti R1 SO_xdata A idle H ldi 8S0 xdata R1 Use original DXR data during 2 ndy or Bx RL Request 2 ndy XMIT sti R1 SO_xdata n idle H sti RO GSO xdata Send register valu idle andn 3 R1 sti R1 SO_xdata Leave with original safe value in DXR ldi SO_rdata RO Fix receiver underrun by dummy read rets H 6 100 Sliding FFT Example 6 18 SFFT ASM Continued By placing the stack at the end of the users runtime code the maximum space is made available for applications Essentialy once used initialization code or data can be reclaimed after it is used However use this configuration for debug purposes i Start STACK This is a reminder to put the stack Sect STACK Stack in a safe place places stack word stack Section at the current assy address i Install the XINT RINT ISR branch vectors Start SPOVECTS 0x809FC5 Place ISR returns directly into Sect SPOVECTS Secondary branch table reti XINTO reti RINTO DSP Algorithms 6 101 6 102 Chapter 7 Programming the DMA Channel The direct memory access DMA coprocessor is an on chip peripheral that can read from or write to any location in the memory map without interfering with the CPU operation The DMA channel contains its own address genera tors source and destin
180. receive interrupt service routine is sufficient for parsing and transferring data between the serial ports and memory Source code for setting up the serial port and timers of the C3x for interfacing to the DSP102 and DSP202 can be found on the TI BBS file name C3XBB EXE This code is listed in Example 8 1 through Example 8 4 Analog Interface Peripherals and Applications 8 11 Burr Brown DSP101 2 and DSP201 2 Interface to TMS320C3x Example 8 1 TMS320C3x BB DSP102 202 Driver Header File f BB H xy TMS320C3x BB DSP102 202 DRIVER HEADER FILE x RK AK HK kk kk kk kk kk kk kk ke kk kk kk kc kk kk kk kk kk kk ke kc kk ke kc kk ke kc ke kc ke kc ko kc k kc ko kc ke kc kk ke ke ke ke e e e x f include lt serprt30 h gt include lt timer30 h gt include lt dma30 h gt include lt bus30 h gt include lt general h gt 8K KK HK kk KI kk I kk kk kk kk ke kk Sk kk kk kk kk kk kk ke kk ko ke kc ko kc ke kc kc I I I ke ke ke ke ke ke x f COMMON STRUCTURES
181. register RO F Repeat 1024 times Zero out location in RAM block 0 and E Zero out location in RAM block 1 1 6 How to Initialize the Processor Example 1 1 TMS320C3x Processor Initialization Continued THE PROCESSOR IS INITIALIZED THE REMAINING APPLICATION DEPENDENT PART OF THE SYSTEM BOTH ON AND OFF CHIP SHOULD NOW BE INITIALIZED FIRST INITIALIZE THE CONTROL REGISTERS IN THIS EXAMPLE EVERYTHING IS INITIALIZED TO 0 SINCE THE ACTUAL INITIALIZATION IS APPLICATION DEPENDENT LDI CTRL ARO H Load in ARO the pointer to control H registers LDI DMACTL RO STI RO ARO 0 Init DMA control LDI TIMOCTL RO STI RO ARO 32 F Init timer 0 control LDI TIM1CTL RO STI RO ARO 48 A Init timer 1 control LDI 8 SERGLOBO RO STI RO ARO 64 w Init serial 0 global control LDI SERPRTXO RO STI RO ARO 66 H Init serial 0 xmt control LDI 8 SERPRTRO RO STI RO ARO 67 Init serial 0 rcv control LDI SERTIMO RO STI RO ARO 68 Init serial 0 timer control LDI SERGLOB1 RO STi RO ARO 80 Init serial 1 global control LDI SERPRTX1 RO STI RO ARO 82 A Init serial 1 xmt control LDI SERPRTR1 RO STI RO ARO 83 s Init serial 1 rcv control LDI SERTIM1 RO STI RO ARO
182. sure interrupt service routines save the DP pointer The D EST ADDR must be aligned such that the first LOG SIZE bits are zero this is not checked by the program kk Ck Ck ck ck Ck Sk ck Ck Sk ck Ck KKK KKK KKK KKK ck ck ck KK KKK ck Ck ck KKK ck ck ck KKK KKK ck ck KKK ck ck ck ck kk kk ko kk Sk kk KKK KKK KKK R2 R3 R4 R5 R6 R7 AR1 AR2 AR3 AR4 AR5 AR6 ART IR1 RE Program Data Stack 405 Words approximately 7 Words 12 Words kk Ck Ck KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK kk KKK KKK KKK KKK Program in RAMO Reserved data in RAMO Stack on primary expansion bus RAM Sine cosin tables in RAMO Processing and data destination in RAMI Primary expansion bus RAM 0 wait state Bit Reversing Data Source Cycles C30 OFF AR3 EIft rl H NOTE WARNING WARNING REGISTERS USED RO R1 ARO IRO RC RS DP MEMORY REQUIREMENTS BENCHMARKS Assumptions FFT Size 1024 FP met global FFT SIZE usect LOG SIZE usect SOURCE ADDR usect DEST ADDR usect SINE TABLE usect BIT REVERSE Jisect SEPARATION USect iftdata i 3 tfideta fftdata 1 fftdata 1 fftdata 1 fftdata 1 fftdata 1 RAM1 19816 approx N
183. that is 32 16 and 8 bits wide The three data sizes and three memory widths comprise the nine cases that cover all possible combinations Memory Interface and Address Translation D 5 Figure D 3 Address Translation for 32 Bit Data Stored in 32 Bit Wide Memory CPU instruction STI RO 7FFFh Memory map STRBO IOSTRB STRBO V STRB1 Note Logical address shift 0 bits 32 bit data size Logical address Space w1 w2 w3 w4 w32765 w32766 w32767 w32768 q e T eo wa Im m m o o o o STRB Memory Data en E e e STREO config width size I5 I5 I5 m ono MESSEN oo NND RN ttv register 3 oh STRB0 32 bits 32 bits wi Oh th w2 1h 2h Logical address 23 to 0 w3 2h an gt Lolololololol ol o ORR elk e olol olololo of of ccc 7FFCh Bh 5 w32765 7FFCh n 7FFDh das c MES w32766 7FFDh eee e a 4 4 414 4 4 4 4 4 4 4 1 4 w32767 7FFEh 7FFFh w32768 7FFFh Memory address space 32 bit data bus o0o0000000000 A13 A13 A13 e e e gt e mm e e e G o a e e E e E CD o 3 A2 A2 A2 A1 A1 A1 AO AO CS A0 CS STRBO B3 STRBO B2 HB STRBO B1 H STRBO B0 A 00000 The amount of shift between logical and physical addresses depends only on the size of data being transferred UOREJSUeIL sseJppy pue eoejieju AIOWAyy uoie sueJ s
184. the frequency variance due to changes in the load capacitance This derivative is applied to find the frequency range implied by a load capacitance with a given tolerance Also if there is a need to adjust the operating frequency use this formula to determine the appropriate value of a variable load capacitor AG LG Af BAGS OF Clock Oscillator and Ceramic Resonators 9 17 Design Considerations 9 4 3 Loop Gain Crystal manufacturers often accommodate requests for specific values for load capacitance to be used with their crystals Values of 20 pF and 30 pF are commonly available These load capacitance values are represented by Cz Co so for a crystal designed for load capacitance of 20 pF C1 C 10 pF is used Capacitance values higher than 30 pF increase attenuation lowering the overall loop gain Capacitance values this high can cause the circuit to stop oscillating A load capacitance of 20 30 pF is recommended for high frequen Cy crystals Ceramic resonators usually require higher load capacitance than high frequency crystals see the manufacturer s recommendations Load ca pacitance values are included in Table 9 2 on 9 22 Loop gain primarily affects the startup time of the oscillator Overall loop gain must be greater than 1 for oscillation to be sustained Higher loop gain causes the oscillation amplitude to increase rapidly therefore reducing the time nec essary for the oscillator to reach its steady state
185. the resulting output is a square wave with a frequency of half that of pulse mode A period of 0 is allowed in clock mode resulting in a 12 5 MHz clock Initializing the TMS320C31 Serial Port This section explains how to initialize the C31 serial port C31 serial port control register memory mapped to 0x808040 DD FSX DX CLKX control register memory mapped to 0x808042 j FSR DR CLKR control register memory mapped to 0x808043 For a detailed description of the C31 serial port see the TMS320C3x User s Guide Example 8 5 shows the assembly code to initialize the serial port global con trol register SGCRO for the C31 in the following manner 1 Issue transmit and receive resets 2 Enable receive and transmit interrupts 3 Set 16 bit receive and transmit transfers 4 Set FSX and FSR CLKX and CLKR active low 5 Set continuous mode 6 Set variable data rate transfers See the example code supplied with the DSP for help on setting up the AIC Example 8 5 Initialize the Serial Port Global Control Register SGCRO SPCXO SPCRO SINIT SINIT H O Set Set word word ldp ldi sti ldi sti sti ldi sti 808040h Serial port 0 global control register 808042h Serial port 0 FSX DX CLKX control reg 808043h Serial port 0 FSR DR CLKR control reg 0e973300n Enable RINT amp 16 bit transfers 111h Configure as serial port pins SGCRO Set Data Page Oh R4 In
186. the application needs a large address reach compact code size and fast execution The MALLOC function from the runtime support library RTS can be called at run time to reserve a block of memory in the SYSMEM section Upon return MALLOC returns a pointer to the newly allocated block Any reference to that block of memory results in assembled code using indirect addressing in which the opcode contains a pointerto the auxiliary register that holds the address of the operand see Figure C 1 Code referring to the dynamically allocated memory is fast and has a 16M word address reach 24 bits The price is a one time call to MALLOC for each dynamically allocated array For that reason MALLOC is most efficient with large data arrays where the overhead associated with the call is insignificant when compared to a large number of data accesses that use the big arrays C 1 Memory Access for C Programs Figure C 1 Memory Allocation in C Programs a Small model default e Static memory assigned at compile time Maximum size 64K words e Fast execution TMS320C32 Memory C statement Equivalent assembly code LDI OFFFDh RO C A B LDI OFFFEh R1 STRB ADDI RO R1 STI R1 OFFFh bss small text b Big model mb option e Static memory assigned at compile time Maximum size 64M words Slow execution TMS320C32 Memory C statement Equiv
187. the dividend is shifted left i j times to align it with the dividend Using SUBC the shifted divisor is subtracted from the dividend For each subtraction that does not produce a negative an swer the dividend is replaced by the difference It is then shifted to the left and a1 is putin the LSB If the difference is negative the dividend is simply shifted left by 1 leaving a zero in the LSB This operation is repeated i j 1 times Integer and Floating Point Division As an example consider the division of 33 by 5 using both long division and the SUBC method see Figure 3 1 In this case i 6 and j 3 so that the SUBC operation is repeated 6 3 1 4 times Figure 3 1 Long Division and SUBC Method Long division 00000000000000000000000000000110 Quotient 00000000000000000000000000000101 00000000000000000000000000100001 101 1101 101 11 Remainder SUBC method 00000000000000000000000000100001 Dividend 00000000000000000000000000101000 Divisor aligned First SUBC command Negative E 00000000000000000000000000100010 New dividend quotient 00000000000000000000000000101000 Divisor 90000000000000900000000000011010 Difference gt 0 second SUBC command 00000000000000000000000000110101 New dividend quotient 00000000000000000000000000101000 Divisor 90000000000000900000000000001101 Difference gt 0 third SUBC command 00000000000000000000000000011011 New dividend quotie
188. the left channel or right channel the program reads from the serial port receive register and converts the input signal into a floating point number with in the range of 1 0 and 1 0 It then changes the serial port configuration from burst to continuous mode when the right channel has been received or from continuous to burst mode when the left channel has been received The trans mit port is configured as the receive port for connection to the 18 bit TMS57014A stereo DAC Remember that the data has to be written to the data transmit register no later than three CLKX cycles before the FSYNC pulse occurs in burst mode or the next transfers starts in continuous mode Example 8 7 Interfacing the 18 bit TLC320AD58 to TMS320C3x f File AD58 C interfacing the 18 Bit TLC320AD58 to TMS320C3x BRK KK RAR KC KC kCk kCKCkCk kCKCKCk KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCk Ck Ck k ck k ck ko kck ck ck ck sk kc k kk e ke x kx x f include files pe xy include vectors h include c3x h global variables float Ichannel float r channel pe oy main program d wy void main void
189. the rules of superposition The spectra of Figure 6 10c the new old sample window is added to the spectra of Figure 6 10b the original windowed signal to create the new spectra of Figure 6 10d The difference is that complex data is used in the frequency domain to represent the phase information of the individual component frequencies 4 The summation of a series of simple impulse transforms which have cor respondingly simple frequency domain transforms results in the compos ite frequency domain transform of the signal 5 Asliding rectangular window is created by subtracting the Nth oldest sam ple which in the frequency domain will have gone through a multiple of 2 x pi radian rotations p TS AS TE Note In some applications complex time domain inputs may also useful For this application only the REAL data from an ADC is used LLLLLLLLL LLL A 3Am 6 8 2 Frequency Response Calculation 6 82 If an impulse sample occurs at T 0 the frequency response calculation is fur ther simplified since the response contains only REAL and no IMAG compo nents The transform of an impulse at T 0 is simply to store the magnitude of the impulse into each REAL bin and zero the IMAG bin If T 0 the time shift creates a phase shift or complex vector rotation within each frequency bin The phase rotation angle is pr
190. the upper half of the external memory addressed by 7FFFh to the 32 bit R1 register The C32 automatically performs all address translation the programmer merely monitors the logical memory map and the two strobe control registers Memory Interfacing 4 51 Figure 4 25 One Bank Two Strobes Adaress Translation Data Size 16 and 8 Bits MU pee i i RS d m 3 Physical Re address STRBO amp RT 32 bits 16 bits address STRBO control register e ee 11 01 sisis STRB1 control register O09 11 00 OOD il p LI 32 bits 8 bits ese RENS v v CD N a eo m m a m eo e eo a a a a a rd tc ra D D D 1 880000h Oh 2 1 2 4 3 3 Aig A14 A1 6 5 I Logical address STRBO I e p P1000 too ofi tu 1111 1111 d l 1000 1fjoo o porem Physical address A17 A3 AQ 32766 i 32767 32764 32763 j 387Frrn M 32766 32765 I 16 bit data size address shifted by 1 bit 3FFFh 32767 IOSTRB 8 bit data size address shifted by 2 bits 4000h 4 3 2 1 j 1 980000h 8 7 6 5 2 I 3 A19 A15 A2 12 1 10 9 j Logical address 1001 ooo EEEEBEEEEBUEEEREEE M i 1001 lf
191. traditional block style FFT or filter may be more practical For example in a filter application only a few frequency bins may be required the unused bins are zero since they are not needed for reconstruction The maximum sampling rate or the number of bins that can be calculated is shown in the following equation Ts min SFFT cycles per bin bins loop overhead nS cycle Ts min 7 N 2 52 40 nS Sliding FFT p _ aaoeoouou Qnaoaa Note The loop overhead value is the time consumed by interrupt routines data for matting input and output SFFT ASM is not highly optimized since it is for educational purposes The loop can be optimized by inlining the three major functions Input SFFT and Output to remove 3 calls and 3 returns or 24 cycles from the loop overhead ee 6 8 11 Loop Unrolling for High Speed Filtering The inner loop of the SFFT consumes 5 computational cycles but executes in 6 cycles The conflict occurs from a data bus bandwidth limitation and results from the STF STF operation immediately preceding a double load of data for the MPYF3 instruction This null cycle is filled by moving the filter summations within the loop The summation can be done entirely within registers and requires no data path access The 1 1 convolutional filter coefficients for raised cosine windowing can be hard coded within the loop by performing subtractions that invert the su
192. 0 Execute next instruction 40x ldi 2h IOF Pull AIC into reset ldi 6h IOF H Pull AIC out of reset Analog Interface Peripherals and Applications 8 21 TLC32040 Interface to the TMS320C3x 8 4 2 8 22 Initializing the TMS320C31 Timer The C31 s timer TCLKO signal is connected to the AIC s master clock MCLK signal The MCLK signal drives all the key logic signals of the AIC such as the shift clock the switched capacitor filter clocks and the ADC and DAC timing signals The timer pulses the TCLKO signal whenever the C31 tim er counter register which is memory mapped to 0x808024 counts up to the value in the timer period register which is memory mapped to 0x808028 Then the timer counter register resets to 0 and repeats For a detailed description of the C31 timer see the TMS320C3x User s Guide Because of differences between the maximum frequency of the C31 s timer and the maxi mum and minimum frequencies of the AIC observe the following constraints J Minimum Timer Period Register Value The C31 running at 50 MHz can generate a maximum timer frequency of 12 5 MHz CLKIN 4 which is above the AIC s tested master clock frequency maximum of 10 MHz If you use frequencies beyond those listed in the TLC32040 Data Sheet the re sulting performance can be unpredictable If the timer is run in pulse mode control value is OX2C1 the minimum period of 1 results in 12 5 MHz mas ter pulse rate and a period of 2 results in 6
193. 0 4 Address the structure elements directly IFperiph status 0 Programming Tips 5 11 Addressing Peripherals as Data Structures in C 5 12 Method 1 is very useful for addressing peripheral or memory buffers that are device specific Method 2 is preferred for addressing peripherals or memory buffers which are not device specific that is peripherals are user specified This method ensures the task of mapping and aligning user specific peripher als and or memory buffers to the linker The choice depends on your individual application See section 5 7 for another method of placing the structure in its own section using pragma directives Linking C Data Objects Separate From the bss Section 5 7 Linking C Data Objects Separate From the bss Section The TMS320 DSP C compilers produce several relocatable blocks of code and data when C code is compiled These blocks are called sections and can be allocated into memory in a variety of ways to conform to a variety of system configurations The bss section is used by the compiler for global and static variables itis one of the default COFF sections that is used to reserve a speci fied amount of space in the memory map that can later be used for storing data It is normally unitialized All global and static variables in a C program are placed in the bss section For example on the floating point DSPs you might want to link all of your variables into off chip memory but place a frequ
194. 00 0 R Physical address A A STRBO 30766 s 32766 erer STRB1 Y iei E ee zrn 22768 STRB1 BO dSd ZED0ZESWL eui 0 Aiowayy Bureau Interfacing Memory to the TMS320C32 DSP 4 6 4 2 16 Bit and 8 Bit Memory Address Translation for Data Size gt Memory Width Figure 4 22 depicts what happens when data is transferred that is larger than the physical memory in which it is to reside As shown by the contents of the strobe control registers STRBO controls transfers of 32 bit data to and from 16 bit wide physical memory and STRB1 controls transfers of 16 bit data to and from byte wide memory When an instruction stores 32 bit data to logical address Oh the memory interface must perform two write cycles to 16 bit wide external memory These two write cycles involve two consecutive addresses Oh and 1h A 16 bit portion of data logically referenced with a single address actually requires two physical addresses to be stored in 8 bit wide physical memory as is the case with the STRB1 transfer shown at the bottom of Figure 4 22 To implement these extra bus cycles the memory interface ap pends an extra address bit to the least significant end of both addresses As in section 4 6 4 1 the LSBs of the STRBO and STRB1 addresses appear at pins A_ and A respectively because they represent 16 and 8 bit wide me mories Memory Interfacing 4 45 Figure 4 22 16 Bi
195. 00 059 EE 900 05A 66 900 05B EE 900 05C 8 900 05D 0 900 05E 0 900 05F 0 900 050 00 900 051 04 900 052 90 900 053 00 900 054 68 900 055 F8 900 056 10 900 057 00 Block 4 900 058 F1 900 400 Fl 900 059 F2 900 401 F2 900 05A F3 900 402 F3 900 05B F4 900 403 F4 900 05C ES 900 404 F5 900 05D F6 900 405 F6 900 05E F7 900 406 F7 900 05F F8 900 407 F8 900 050 0 900 051 0 900 052 p 900 053 p sejduiex3 ejqe 1008 ZEDOZESNL Figure A 4 Boot From Serial Port to 8 16 and 32 Bit Wide RAM TMS320C32 Boot Table Examples Source Boot Destination Block address table address data 808 04C 1000 OOF8 808 04C 2005 10F8 808 04C 3000 10F8 808 04C 6 808 04C 0000 1400 808 04C 0510 F864 Block 1 808 04C 0000 BB1D 001 400 BB1D 808 04C 0000 BB2D 001 401 BB2D 808 04C 0000 BB3D 001 402 BB3D 808 04C 0000 BB4D 001 403 BB4D 808 04C 0000 BB5D 001 404 BB5D 808 04C 0000 BB6D 001 405 BB6D 808 04C 4 808 04C 0081 0400 808 04C 0000 F860 Block 2 808 04C DDCC BBIE 810 400 DDCC BBIE 808 04C DDCC BB2E 810 401 DDCC BB2E 808 04C DDCC BB3E 810 402 T E EIS 508 808 04C DDCC BB4E 810 403 DDCC BB4E 808 04C 6 808 04C 0088 0400 808 04C 0510 F864 Block 3 808 04C 0000 BB1F 880 400 BB1D 808 04C 0000 BB2F 880 401 BB2D 808 04C 0000 BB3F 880 402 BB3D 808 04C 0000 BB4F 880 403 BB4D 808 04C 0000 BB5F 880 404 BB5D 808 04C 0000 BB6F 880 405 BB6D 808 04
196. 000 0x2000 R W TX Inform debugger that this section holds code text ma Ox87FE00 0x2000 RAM ma 0x900000 0x8000 RAM map on Make emulator aware of this memory configuration 0x808064 0Ox2F0000 Set STRBO control register to STRBO and STRB1 overlay 32 bit memory width 32 bit data size 0x808068 OxD0000 Set STRB1 control register load sample out 32 bit memory width 16 bit data size Configure STRBO STRB1 control registers befor loading code Memory Interfacing 4 85 Booting a TMS320C32 Target System in a C Environment 4 8 Booting a TMS320C32 Target System in a C Environment 4 8 1 4 86 A DSP system uses a boot procedure following power up or reset to initialize the system volatile memory such as SRAM with the application program data and to start execution of the application code The SRAM loads from a nonvol atile medium EPROM or from a PC development platform using a debugger loader program The loader uses an emulator cable to move the load file from the PC hard disk to the SRAM on the DSP target board An EPROM boot causes the DSP to start program execution directly from 16 or 32 bit EPROM microprocessor mode A hard wired on chip boot loader program copies the boot table from the 8 bit EPROM to internal or external SRAM and then starts execution from the SRAM microcomputer boot loader mode TI supports four ways to boot a DSP system following power up reset Each boot procedure uses
197. 0000 00000000 ADDRESS 00000034 00000035 00000036 00000037 00000038 00000039 0000003A 0000003B 0000003C 0000003D 0000003E 0000003F 0000004 0000004 0000004 0000004 0000004 0000004 0000004 0000004 0000004 0000004 0000004 0000004 0000004 0000004 0000004 0000004 00000050 00000051 00000052 00000053 00000054 00000055 00000056 00000057 00000058 00000059 0000005a 0000005b 0000005c 0000005d 0000005e 0000005 f 00000060 00000061 00000062 00000063 00000064 00000065 00000066 00000067 0 Q0 TM vw 0 200 5 Q l9 Oo Hh OPCODE 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 086 4040 09ef0009 08740023 1014000f 0871ffff 08000017 02e0000 04e00008 6a05004 f 080a000 026a0060 1a600004 53654080 6a060008 026a0004 1a600001 53650008 6a060004 026a0004 1a600004 536b4800 6a05ffef 1a600008 62050002 1a780080 08780006 0862000 09e20010 1042c200 1542c200 09eb0009 086800ac 08650001 086e0020 7200005d ADDRESS 00000068 00000069 0000006a 00000060 0000006c 0000006d 0000006e 0000006 f 00000070 00000071 00000072 00000073 00000074 00000075 00000076 00000077 00000078 00000079 0000007a 00000070 0000007c 0000007d 0000007e 0000007 f 00000080 00000081 00000082 00000083 00000084 00000085 00000086 00000087 00000088 00000089 0000008a 0000008b 0000008c
198. 1 001 00 001 023 0 001 002 00F8 001 024 0400 001 003 1000 001 025 0088 001 004 10F8 001 026 F864 001 005 2005 001 027 0510 Block 3 001 006 10F8 001 028 EEI11 880 400 EE11 001 007 3000 001 029 EE22 880 401 EE22 001 008 6 001 02A EES33 880 402 EE33 001 009 0 001 02B EE44 880 403 EE44 001 00A 1400 001 02C EE55 880 404 EE44 001 00B 0000 001 02D EE66 880 405 EE55 001 00C F864 001 O2E 8 001 00D 0510 Block 1 001 02F 0 001 00E AA11 001 400 AAll 001 030 0400 001 00F AA22 001 401 AA22 001 031 0090 001 010 AA33 001 402 AA33 001 032 F868 001 O11 AA44 001 403 RAE 001 033 0010 Block 4 001 012 AA55 001 404 RASS 001 034 900 400 F1 001 013 AA66 001 405 AA66 nom wee 900 401 F2 001 014 4 001 036 900 402 F3 001 015 0 001 037 900 403 FA 001 016 0400 001 038 900 404 FS 001 017 0081 001 039 900 405 F6 001 018 F860 001 03A 900 406 E 001 019 0000 Block2 001 03B 900 407 F8 001 01A DD11 810 400 BBCC DD11 001 03C 001 01B BBCC 810 401 BBCC DD22 001 03D 001 01C DD22 810 402 BBCC DD33 001 01D BBCC 810 403 BBCC DD44 001 01E DD33 001 01F BBCC 001 020 DD44 001 021 BBCC TMS320C32 Boot Table Examples A 3 sajdwiexy ejqe 100g ZEOOZESWL Figure A 3 Boot From a Byte Wide ROM to 8 16 and 32 Bit Wide RAM Source Boot Destination Block Source Boot Destination Block address table address data address table address data 900 000 gg
199. 1 R1 CMPI AR1 ARO Xchange locations only if ARO lt AR1 LDFGT RO R1 LDFGT AR1 IRO B R1 RPTB BITRV1 LDF ARO IR1 RO STE RO ARO LDF AR1 R1 STF R1 AR2 IRO B CMP I AR1 ARO LDFGT RO R1 BITRV1 LDFGT AR1 IRO B RO STF RO ARO SIF R1 AR2 Perform bit reversing on odd locations x 2nd half only LDI QFFT_SIZE RC LSH 1 RC LDI DEST_ADDR ARO ADDI RC ARO ADDI 1 AR0 LDI ARO AR1 LDI ARO AR2 LSH 1 RC SUBI SERG NOP AR1 IRO B NOP AR2 IRO B LDF ARO IR1 RO 6 74 Fast Fourier Transforms FFTs Example 6 17 Real Inverse Radix 2 FFT Continued CMPI LDFGT LDFGT RPTB STF LDF STF CMP I LDFGT LDFGT BITRV2 STF STF LDI LSH LDI LDI LDI ADDI ADDI LSH DI UBI E n RPTB STF BITRV3 LDF STF STF STF BR AR1 R1 AR1 ARO RO R1 AR1 IRO B R1 BITRV2 ARO IR1 RO RO ARO AR1 R1 R1 AR2 IRO B AR1 ARO RO R1 AR1 IRO B RO RO ARO R1 AR2 QFFT SIZE RC 1 RC RC IRO DEST_ADDR ARO ARO AR1 1 ARO IRO AR1 1 RC RC IRO 2 RC ARO RO AR1 R1 BITRV3 ARO IR1 RO RO AR1 IRO B AR1 R1 R1 ARO IR1 RO AR1 R1 ARO DIVISION Xchange locations only if ARO AR1 Perform bit reversing on odd locations lst half only Check data source locations If SourceAddr DestAddr then do nothing
200. 10 parts per million ppm of the intended frequency Ceramic resonators are similar to quartz crystal resonators in physical struc ture but they are made from a polycrystalline ceramic instead of monocrystal line quartz The production process for the ceramic is much less expensive than for quartz reducing the final cost of the resonator However the polycrys talline structure of the ceramic vibrates within a wider range of frequency than aquartz crystal does and consequently the frequency control is not as precise as itis with quartz While quartz crystal resonators can operate within 10 ppm of the intended frequency ceramic resonators generally operate within 5000 ppm However if accuracy greater than 5000 ppm is not necessary ce ramic resonators are a cost effective alternative Table 9 1 shows a compari son of three types of resonators Table 9 1 Comparison of Resonator Types Frequency Long Term Type Relative Price Adjustment Tolerance Stability LC Very low Necessary 20000ppm Fair Ceramic Low Not necessary 5000 ppm Excellent Crystal High Not necessary 10 ppm Excellent This document assumes that a quartz crystal is being used as the resonator however the information applies equally to ceramic resonators unless other wise specified Figure 9 2 shows a circuit model that is equivalent to a crystal The graphs il lustrate the behavior of the magnitude of the crystal impedance and the reac tance of the crystal
201. 100q 1Xel yee TEUER suonoeg L e 1opeonoog SS 9 uonoes 1xer 9poo lt sowuesBod apoo 4 lt Mri Zell de WOHd3 Sd zelld z l d uonoes ssq ejep gt lt po P E UOI oes X9 z l d Lelld Y leid bolls t 3 mn nypt t n 2 i Usenooq Cs S Loss E use1009 E i epoo use4ooq use41ooq uoqoss er 2 Leid 100q 9 spoo spoo 100q 9 1008 9 1ooq 9 zWvus HNvds di Rt Ionuoo loquoo Oo NVHS olul ANoeup lulod Aqua Jepeolloog Japeojjoog WAU peol ol pue slqel 100g eui jo uonnoexe z ol wa c selhq jenpiirpui ejquiesse ol Nd PUNSO 9 WO um epeo peol oi nn Sure God E eu sesn jepeo 100q diuo uo au mm looq y J0 suononusui Jepeo 100q diuo uo 5 LASAY o uonsuegn Jojuoo leloeds snid y jnujsu oj suomnoes 5 SepKo J9ysueh uBiu or wo Bulinp uid XINI euo eyep pezi eniur sepoodo esou ol spiom Ionuoo elep eziuoiuou s uo MOJ B pue AWON uo Gely e T weiBod jo sisisuoo eJixesppe pue palooq eq u ol YOYI pue LIX pe 9 on 9exe peolloog LI oda ei alqel1009 eul YUM oap O suonoes eui segnuep 7 S SC usn epou c diks dh NOHd3 110 8 eu suing puelsiepun S Buiyeyspuey eui ui ST XvOO0cESWL 1eunreJj 0JCWOHd39Ul ueojeuurJDoJd I NOHd3 a qel100q Sy spee J ejepig g j ue ey OSY EWO GD Jepeol 100q eui nao KM OH uod uuoo piepueis e ol l 4400 Q peuesse aie XINI dW 185W Aeulq eu shexuoo0 N 1eujoue pu NI jl 6ulwmollol 65 Jepeollooq P
202. 17 N V STRBO STRB1 read cycle Table 4 6 RDY Signal Generation H3 17 li k 18 RDY Parameter number Description 11 td H1L SL Delay time H1 low to STRBx low 12 td H1L SH Delay time H1 low to SRBx high 14 td H1L A Delay time H1 low to A valid 17 tsu RDY Setup time RDY before H1 low 18 th RDY Hold time RDY after H1 low MOE O ua STRBO STRB1 write cycle C32 40t C32 50t C32 e0t 50 ns 40 ns 33 ns Min Max Min Max Min Max 0 11 0 9 0 8 11 0 9 11 0 9 21 19 17 0 0 0 11 9 8 Unit ns ns ns ns ns ns T These timing specifications are subject to change without notice See the TMS320C32 Digital Signal Processor data sheet for current timing information Memory Interfacing 4 59 Interfacing Memory to the TMS320C32 DSP 4 6 6 2 RDY Signal Generation for STRBO Signals 4 60 Figure 4 29 shows three memory banks controlled by a single strobe STRBO The first bank is composed of four 8 bit wide SRAMs requiring zero wait states to operate at 60 MHz 15 ns devices Bank 2 is composed of two 1 wait state SRAMs and bank 3 contains one 3 wait state EPROM which is 8 bits wide The RDY pin is normally high indicating a not ready state It goes low if either RDY BANK1 or RDY BANK23 goes low The RDY BANK1 signal is asserted only if two conditions are satisfied D Atleast one of the four STRBO signal lines must be active DD The three address decode
203. 2 it1 1 n k it1 PO b ifltl ntl s tel eS R2 b itlt1 btl k i1 it1 1 n ADDF3 tAR1 1 R1 R3 gt b itl n gt R3 BI STFR3 AR1 1 b itltl n t b itl 1 n 1 3 LOOP MPYF3 ARO 1 R2 R1 k i it1 n R1 I P 1 CLEANUP ADDF3 R2 R0 R2 o f ptl n k p b pti ntl f p n t R2 A b ptl ntl k p f ptl n ADDF3 AR1 R1 R3 b p n t R3 Wi STF R3 AR1 b ptl n t b ptl ntl RETURN SEQUENCE RETS RETURN 6 20 Lattice Filters The forward lattice filter is similar in structure to the inverse filter as shown in Figure 6 6 Figure 6 6 Structure of the Forward Lattice Filter Lib n y n These corresponding equations describe the lattice filter f i 1 n f i n k i b i 1 n 1 b in 2b i 1 n 1 k i f i 1 n Initial conditions f pn 2 x n b in 1 20 fori 1 p Final conditions y n f 0 n The data memory organization is identical to that of the inverse filter as shown in Figure 6 5 on page 6 19 Example 6 10 shows the implementation of the lattice filter on the C3x DSP Algorithms 6 21 Lattice Filters Example 6 10 Lattice Filter TITLE LATTICE FILTER SU
204. 2 5 directly As with internal bus operations data dependencies for the external buses are well defined but accurate prediction of data patterns is often impractical Un less you have precise knowledge of data patterns you should use an estimate of a median or average value for scale factor If you assume that data is neither 5s and As nor all Os and varies randomly a value of 0 85 is appropriate Otherwise if you prefer a conservative approach you can use a value of 1 0 as an upper bound Current Requirement for Output Driver Circuitry Figure 12 8 Primary Bus Current Versus Data Complexity Derating Curve As to 5s 7 1 0 95 0 9 ternating data 0 85 0 8 0 75 Same data primary bus data scale factor 0 7 0 65 Do 0 6 0 01 02 03 04 05 06 07 08 09 1 Data complexity Figure 12 9 Expansion Bus Current Versus Data Complexity Derating Curve 0 95 Iternating data 0 9 0 85 0 8 0 75 0 7 0 65 expansion bus data scale factor 0 6 Da3 0 55 0 01 02 03 04 05 06 07 08 09 1 Data complexity TMS320C30 Power Dissipation 12 15 Current Requirement for Output Driver Circuitry Regardless of the approach you take for scaling once you determine the scale factors for primary and expansion buses apply these scale factors to the cur rent values found by usin
205. 2 bit STRBO and STRB1 bus cycles are no different functionally from the IOSTRB cycles but simply have tighter timing parameters The STRBO and STRB1 cycles are not limited to just selecting bytes out of 32 bit memory locations There are two strobe control registers that configure the data size and memory width for STRBO and STRB1 bus cycles one control register per strobe With proper initialization ofthe strobe control registers the bus cycles can be configured to encompass any combination of data size and physical memory width For example a byte can be read from a 16 bit wide memory or a 32 bit word can be written to an 8 bit wide memory by configuring the memory width and data size fields of the corresponding strobe control reg isters see Figure 4 10 Like other members of the C3x generation the C32 program as well as the data can reside in any portion of the memory map The C32 program fetches from address space mapped to IOSTRB are indistinguishable from IOSTRB data reads or writes However the STRBO and STRB1 cycles are configured slightly differently for program fetches than for data accesses Program and data can still share the same portions of the memory map but instead of set Memory Interfacing 4 21 Interfacing Memory to the TMS320C32 DSP 4 22 ting the memory width and data size fields in STRBO and STRB1 control regis ters the program fetch cycles from the memory spaces m
206. 20 family device and development support tool prefix and suffix designators fol lows the two tables to assist in understanding the TMS320 product numbering system Technology 0 8 um CMOS 0 8 um CMOS 0 8 um CMOS 0 8 um CMOS 0 8 um CMOS 0 8 um CMOS 0 8 um CMOS 0 8 um CMOS 0 8 um CMOS 0 8 um CMOS Operating Frequency 33 MHz 40 MHz 33 MHz 40 MHz 33 MHz 50 MHz 28 MHz 33 MHz 28 MHz 25 MHz TMSS320C3x Digital Signal Processor Part Numbers Package Type Ceramic 181 pin PGA Ceramic 181 pin PGA Plastic 132 pin QFP Plastic 132 pin QFP Plastic 132 pin QFP Plastic 132 pin QFP Ceramic 141 pin PGA Ceramic 132 pin QFP Ceramic 141 pin PGA Ceramic 132 pin PGA Ceramic 181 pin PGA Ceramic 196 pin QFP Ceramic 181 pin PGA Ceramic 196 pin QFP Ceramic 181 pin PGA Ceramic 196 pin QFP Typical Power Dissipation 1 00W 1 25 W 0 75 W 0 90 W 0 50 W 1 00 W 0 60 W 0 60 W 0 75 W 0 75 W 1 10 W 1 00 W 1 00 W 1 00 W 1 00 W Development Support and Part Ordering Information 11 7 TMS320C3x Part Ordering Information Table 11 2 TMS320C3x Support Tool Part Numbers a Software Tool Description C Compiler amp Macro Assembler Linker Assembler Linker Simulator Digital Filter Design Package TMS320C3x Emulation Porting Kit b Hardware Tool Description XDS510 Emulator Evaluation Module EVM Operating System VAX VMS PC DOS MS DOS SPARC Sun OS t PC DOS MS DOS
207. 24 complex radix 2 DIF 6 30 complex radix 4 DIF 6 36 definition 6 29 real radix 2 6 42 filters 6 7 to 6 17 adaptive 6 15 Index 4 FIR 6 7 circular addressing 6 7 IIR 6 9 lattice 6 18 LMS algorithm 6 15 floating point division 3 6 3 10 format IEEE definition 3 21 IEEE to TMS320C3x conversion 3 22 TMS320C3x definition 3 20 TMS320C3x to IEEE conversion 3 26 IEEE to TMS320C3x conversion 3 20 to 3 29 inverse 3 10 square root 3 13 GOTO 2 22 hardware applications primary bus interface 4 4 bank switching techniques 4 15 ready generation 4 10 to 4 20 zero wait state to static RAMs 4 5 to 4 9 system configuration options categories of external interfaces 4 3 typical block diagram 4 2 System control functions 1 4 to 1 8 reset signal generation 1 3 to 1 4 XDS target design considerations connections between emulator and target system 10 5 to 10 7 diagnostic applications 10 10 mechanical dimensions for emulator connector 10 8 to 10 9 MPSD emulator cable signal timing 10 4 MPSD emulator connector 10 2 hardware reset 1 2 header 12 pin 10 2 dimensions 12 pin header 10 2 mechanical 10 8 to 10 9 files sharing in C and assembly 5 10 signal descriptions 12 pin header 10 2 hints for assembly coding 5 5 to 5 6 hotline 11 5 IIR filters 6 9 initialization processor 1 2 input clock 1 3 integer division 3 6 interfaces external 4 3 primary bus See also primary bus interface bank switching techniques 4 15 ready g
208. 25 MHz See the TLC32040 Data Sheet for more information J Maximum Timer Period Register Value The AIC s minimum master clock frequency is 75 kHz Taking into account the C31 maximum timer frequency of 12 5 MHz and the AIC s minimum master clock frequency the maximum value in the C31 s timer counter register must be 165 12 5 MHz 75 kHz 166 7 The C31 s timer counts down to 0 therefore you must subtract 1 from this number 166 1 165 The TLC32040 specification describes a minimum clock frequency since the internal sig nals of the AIC are stored in capacitors that must be periodically updated The following C31 assembly code initializes the timer in clock mode with a tim er period of 1 The following code initializes timer 0 to generate a square wave clock mode on the TCLKO pin at a frequency of 6 25 MHz timer period 1 TGCRO Set 808020h TCNTO set 808024h Timer 0 global control register Timer 0 counter register TPRO Set 808028h Timer 0 period register TIMVAL word 3clh Timer global control register value ldp TGCRO Set Data Page ldi Oh R4 Initialize R4 to zero ldi 1h RO Initialize RO to 1 sti R4 TGCRO Reset timer0 sti RO TPRO Store timer0O period sti R4 TCNTO Reset timerO counter Td TIMVAL R7 Load timer control value sti R7 TGCRO Start timer 0 8 4 3 TLC32040 Interface to the TMS320C3x A period of 0 is not allowed in pulse mode If the timer is run in clock mode
209. 3 AR7 R1 AR4 LSH 8 R4 dest memory strobe gt R4 LDI R4 R3 LSH 16 R3 B 10 Boot Loader Source Code Listing AND 3 R3 dest data size R3 TSTB OCh R1 IOSTRB case LDIZ 3 R3 Look at R5 and choose serial or memory read for block data program CMPI 0 R5 LDIEQ read sO AR1 read serial port0 LDINE read mb ARI1 read memory Transfer one block of data or program RPTB loop4 CALLU AR1 read data prg STI RA AR4 Set write strobe NOP pipeline loop4 STI R1 AR5 Write data prg 1111111 BU block P r process next block Load R5 with 0 load read sO0 to ARO and initialize serial port O0 serial LDI read sO ARO use serial to read cntrl words LDI 0 R5 memory WIDTH serial LDI O R dummy LDI AR7 AR2 dummy LDI 111h R0 0000111h RO STI RO x AR7 43h set CLKR DR FSR as serial LDI 0A30h R7 A port pins LSH 16 R7 A300000h R7 STI R7 AR7 40h set serial global cntrl reg BU strobes P process first block Read a single value from serial or boot memory The number of memory reads depends on memory width and data size R1 returns the read value Serial sim NOP BZ read s0 amp LDI 84000H R1 LIDI cAR7 4Ch R1 read s0 TSTB 20h IF look at RINTO flag TMS320C32 Boot Loader Program B 11 Boot Loader Source Code Listing
210. 3 RA RO R3 SUBF3 AR1 IRO R3 R4 ADDF3 AR1 R3 R4 RO X I3 COS 3 RA X I3 SIN 3 Rl X I4 SIN 3 RO X I4 COS 3 R2 X I3 COS X I4 SIN R3 X I3 SIN X I4 COS RA X I2 R34 RA X I2 R3 X I3 4 RA XI1 R2 X I4 RA XI1 R2 X I12 4 X I1 DSP Algorithms 6 55 Fast Fourier Transforms FFTs Example 6 16 Real Forward Radix 2 FFT Continued STF R4 AR2 SUBF3 R2 ARO IRO R4 STF R4 AR3 ADDF3 BRO R2 R4 STF R4 AR1 MPYF3 AR3 R6 R1 STF R4 ARO ADDF3 RO R1 R2 MPYF3 AR5 AR4 IRO RO SUBF3 RO R1 R3 SUBF3 AR1 R3 R4 ADDF3 AR1 R3 R4 STF R4 AR2 SUBF3 R2 ARO R4 STF R4 AR3 ADDF3 BRO R2 R4 STF R4 AR1 MPYF3 AR2 R7 R4 STF R4 ARO MPYF3 AR3 R7 R1 MPYF3 AR5 AR3 RO ADDF3 RO R1 R2 MPYF3 AR7 AR4 IR1 RO SUBF3 R4 RO R3 SUBF3 AR1 R3 R4 ADDF3 AR1 R3 R4 STF R4 AR2 IR1 SUBF3 R2 ARO R4 STF R4 AR3 IR1 LOOPA B ADDF3 ARO R2 R4 STF R4 AR1 IR1 MPYF3 AR2 IRO R5 R4 STF R4 ARO IR1 MPYF3 AR3 IRO R5 R1 MPYF3 AR7 AR3 RO ADDF3 RO R1 R2 MPYF3 AR6 ARA RO SUBF3 R4 RO R3 SUBF3 AR1 IRO R3 R4 ADDF3 AR1 R3 R4 STF R4 AR2 SUBF3 R2 ARO IRO R4 STF R4 AR3 ADDF3 ARO R2 R4 STF R4 AR1 MPYF3 AR3 R6
211. 32 PUSH R2 Save the lower 32 bi PUSH R2 and the upper 32 PUSH R3 3 Save the lower 32 bi PUSH R3 E and the upper 32 PUSH R4 s Save the lower 32 bi PUSH R4 E and the upper 32 PUSH R5 E Save the lower 32 bi PUSH R5 and the upper 32 PUSH R6 Save the lower 32 bi PUSH R6 H and the upper 32 PUSH R7 Save the lower 32 bi PUSH R7 H and the upper 32 SAVE THE AUXILIARY REGISTERS PUSH ARO 3 Save ARO PUSH AR1 Save AR1 PUSH AR2 E Save AR2 PUSH AR3 Save AR3 PUSH AR4 Save AR4 PUSH AR5 3 Save AR5 PUSH AR6 Save AR6 PUSH AR7 E Save ART of of of of of of of of RO R1 R2 R3 R4 R5 R6 R7 Program Control 2 13 Context Switching in Interrupts and Subroutines Example 2 4 Context Save for the TMS320C3x Continued SAVE THE REST REGISTERS FROM THE REGISTER FILE PUSH DP H Save data page pointer PUSH IRO Save index register IRO PUSH IR1 Save index register IR1 PUSH BK Save blocktsize register PUSH IE Save interrupt enable register PUSH IF Save interrupt flag register PUSH IOF Save I O flag register PUSH RS Save repeat start address PUSH RE A Save repeat end address PUSH RC H Save repeat counter SAVE IS COMPLETE 2 14 Context Switching in Interrupts and Subroutines Example 2 5 Context Restore for the TMS320C3x
212. 320C3x C Source Debugger literature number SPRUO53 describes the C3x debugger for the emulator evaluation module and simulator This book discusses various aspects of the debugger interface including window management command entry code execution data manage ment and breakpoints It also includes a tutorial that introduces basic de bugger functionality Read This First vii Helated Documentation From Texas Instruments viii TMS320C3x C4x Assembly Language Tools User s Guide literature number SPRUO35 describes the assembly language tools assembler linker and other tools used to develop assembly language code assembler directives macros common object file format and symbolic debugging directives for the C3x and C4x generations of devices TMS320C3x User s Guide literature number SPRUO31 describes the C3x 32 bit floating point microprocessor developed for digital signal proces sing as well as general applications its architecture internal register structure instruction set pipeline specifications and DMA and serial port operation Software and hardware applications are included TMS320C3x C4x Code Generation Tools Getting Started Guide literature number SPRU119 describes how to install the TMS320C3x C4x assembly language tools and the C compiler Installation instructions are included for MS DOS Windows 3 x Windows NT Windows 95 SunOS Solaris and HP UX systems TMS320C30 Digital Signal P
213. 42 4 43 4 44 4 45 4 46 4 47 IL d DL dL dod do td RWONM WNDN E did usu d hus d dre d NOOR WMP OO LE dL dog ROT rrr rT Qe mo QE eic ex c e 0x e oio ec qaco tn ene oo xxii Address Decode for Multiple Memory Banks i 4 65 TMS320C32 Memory Address Spaces pp 4 69 Zero Wait State Interface for 32 Bit and 8 Bit SRAM Banks i 4 75 Zero Wait State Interface for 32 Bit SRAMs with 16 and 32 Bit Data Accesses 4 81 External Memory Map 0 000 cece cece e rh 4 82 TMS320C32 Memory Map sn ose de oa de eens 4 83 Compile Assemble and Link Flow i 4 89 Loading C Object File into TMS320C32 Memory Linker cr Option 4 93 Loading C Object File into TMS320C32 Memory Linker c Option 4 94 32 Bit EPROM Boot in the Microprocessor Mode Linker c Option 4 97 8 Bit EPROM Boot Using the On Chip Boot Loader Linker cr Option 4 98 Memory Configuration for Normal Program Execution 0c eee eens 4 100 Boot Table Memory Configuration pp 4 101 Boot From Host Using Serial Port Linker cr Option pp 4 104 Boot From Host Using an 8 Bit Latch Linker cr Option i 4 105 Boot From Host Using Asynchronous Communications Port Linker cr Option 4 106 TMS320C30 Combination of Primary and Expansion Busses to Address 68 Gigawords 2 254 208 x barn pares teres sOetaagatawenrseaeeawe d ea 4 107 Bit Reversed Addressing in C Code pp 5 9 Input File dets Ti e
214. 6 79 Sliding FFT 6 8 Sliding FFT SFFT ASM uses a technique known as a sliding FFT SFFT to calculate the spectrum of a signal on a sample by sample basis The SFFT is particularly well suited for applications where signal analysis filtering modulation demodulation or other forms of signal manipulation in the frequency domain must be performed in real time The SFFT algorithm is similar to the discrete Fourier transform DFT The SFFT is equivalent to overlapped FFTs with an overlap of 1 sample in that the past frequency data is reused to calculate the frequency spectra of the next sample window The calculation is performed by adding the frequency domain spectra of a new sample while simultaneously subtracting the frequency domain spectra of the oldest sample The SFFT does not require first hand knowledge of the DFT or FFT In addition the SFFT can be used to derive the DFT equation which can be used by DSP beginners or by DSP experts looking for a different approach to solve a problem 6 8 1 SFFT Theory A Better Way to Use the Impulse Response 6 80 The SFFT is based on the following simple concepts 1 The property of superposition allows two or more signals to be added lin early to create a new signal A sampled time domain signal is the summa tion of a series of individual input samples or impulses of varying magni tude Figure 6 10a Similarly signals or impulses can be subtracted If an input signal sample buffe
215. 6 bit memory pool buffer2 malloci16 4096 sizeof float Process buffers callDSPoperation bufferl buffer2 Free buffers freel6 buffer2 freel6 bufferl 4 84 The linker command file in Example 4 7 allocates sections of the preceding C code into the memory configuration depicted in Figure 4 35 on page 4 82 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface Example 4 7 Linker Command File sample obj heapl6 32768 stack 8704 o sample out m sample map MEMORY STRBORAM STACKRAM STRB1RAM SECTIONS text gt STRBORAM cinit gt STRBORAM Const gt STRBORAM bss STRBORAM Stack STACKRAM Sysm16 gt STRB1RAM Input filename Set 16 bit memory pool size Set C system stack size E Specify output file Specify map file org 0x2000 len 0x2000 org 0x87Fe00 len 0x2200 org 0x900000 len 0x8000 32 bit data section 32 bit data section 32 bit data section 32 bit data section 32 bit data section ju 16 bit memory pool mapped to STRB1 xt The debugger batch file in Example 4 8 executes initialization commands that configure the C source debugger to handle a C32 with the memory configura tion shown in Figure 4 36 on page 4 83 Example 4 8 Debugger Batch File mr sconfig init clr Define memory configuration ma 0x2
216. 7107 773010 831470 881921 923880 956940 980785 0 995185 1 000000 0 995185 980785 956940 923880 881921 831470 773010 707107 634393 9955570 471397 382683 290285 195090 098017 000000 098017 195090 290285 382683 471397 555570 634393 707107 773010 831470 881921 923880 956940 980785 995185 X C3 C3 CK c oO OOOoOodoccc OOOOOOOOOOOOOOOOOOOOOOOOEOOOOOO DSP Algorithms 6 35 Fast Fourier Transforms FFTs 6 6 3 Complex Radix 4 DIF FFT The radix 2 algorithm has tutorial value because the functioning of the FFT algorithm is relatively easy to understand However radix 4 implementation can increase execution speed by reducing the amount of arithmetic required Example 6 15 shows the generic implementation of a complex DIF FFT in radix 4 A companion table such as the one in Example 6 14 must have a value of M equal to the logN where the base of the logarithm is 4 Example 6 15 Complex Radix 4 DIF FFT TITLE COMPLEX RADIX 4 DIF FFT GENERIC PROGRAM TO PERFORM A LOOPEDECODE RADIX 4 FFT COMPUTATION
217. 8 6 7 TMS320C3x Benchmarks 6 78 6 8 Sliding FEM 95 90 59 e peer esse eee cen decr S 6 80 6 1 Companding 6 1 Companding 6 2 In telecommunications conserving channel bandwidth while preserving speech quality is a primary concern This is achieved by quantizing the speech samples logarithmically An 8 bit logarithmic quantizer produces speech quali ty equivalent to a 13 bit uniform quantizer The logarithmic quantization is achieved by companding COMpress exPANDing Two international stan dards have been established for companding the h law standard used in the United States and Japan and the A law standard used in Europe Detailed descriptions of u law and A law companding are included in Volume 1 of the book Digital Signal Processing Applications With the TMS320 Family During transmission logarithmically compressed data in sign magnitude form is transmitted along the communications channel If any processing is neces sary you must expand this data to a 14 bit for u law or 13 bit for A law linear format This operation is performed when the data is received at the digital sig nal processor DSP After processing the result is compressed back to 8 bit format and transmitted through the channel to continue transmission Example 6 1 and Example 6 2 show u law compression and expansion that is linear to u law and u law to linear conversion while Example 6 3 and E
218. 8 Bit Data Stored in 8 Bit Wide Memory CPU instruction STI RO 7FFFh DP 90h Memory map Bi OTeSS STRED b1 900000h i b2 900001h b3 900002h i b4 900003h IOSTRB C e e i b32765 907FFCh b32766 907FFDh STABO b32767 907FFEh STRB1 B 907FFFh Logical address shift 2 bits 8 bit data size Memory Data STRB1 width size control ooo register 899 9 8bits 8 bits Logical address 23 to 0 m gt 1 0 0 1 0 0 0 0 1 1 1 0 0 1 0 0 Physical address 23 to 2 Memory address 14 to 0 8 bit data bus Oo TMS320C32 9 CT D A14 A13 A12 e o e A1 AO A 1 A 2 STRBO B1 STRBO BO STRB1 BO b32765 b32766 b32767 Oh ih 2h 3h 7FFCh 7FFDh 7FFEh Bx ru FFFh Memory address space Physical address shift 2 bits 8 bit memory width Notes 1 The amount of shift between logical and physical addresses depends only on the size of data being transferred 2 The amount of shift in the phys
219. 84 A Init serial 1 timer control LDI PARINT RO STI RO ARO 100 A Init parallel interface s control C30 only LDI IOINT RO STI RO ARO 96 A Init I O interface control LDI STCK SP Init the stack pointer OR 2000H ST s Global interrupt enable BR BEGIN Branch to the beginning of application end Processor Initialization 1 7 How to Initialize the Processor 1 3 2 Processor Initialization Under C Language If you are running under a C environment your initialization routine is typically boot asm from the RTS30 LIB library that comes with the floating point com piler In addition to initializing global variables boot asm initializes the DP reg ister pointing to the bss section and the stack pointer SP register pointing to the stack section You must enable the cache as shown in Example 1 2 and set up your interrupts inside your main routine before you enable inter rupts See the application report Setting Up TMS320 DSP Interrupts in C for more information Example 1 2 Enabling the Cache main asm or 1800 st enable cache asm or 3800 st enable cache and interrupts Low Power Mode Interrupt 1 4 Low Power Mode Interrupt This section explains how to generate interrupts when the IDLE2 power down mode is used The execution of the IDLE2 instruction causes the H1 and H3 processor clocks to be held at a constant level until the occurrence of an exte
220. 8K x 32 bits 3FFFh 4000h 87FE00h Internal RAM 512 x 32 bits 87FFFFh 880000h System stack 8K x 32 bits 881FFFh 900000h Data buffers 32K x 16 bits 907FFFh FFFFFFh Note For 32 bit data physical address logical address For 16 bit data physical address logical address shifted left by 1 Memory Interfacing 4 83 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface 16 Bit Dynamic Memory Allocation This section contains C code examples of 16 bit dynamic buffer allocation linker configuration and a debugger batch file The following C code demonstrates the allocation of two buffers 1K and 4K 16 bit words using the 16 bit dynamic memory allocation routines provided by the runtime support library Example 4 6 16 Bit Dynamic Buffer Allocation include lt bus30 h gt void main int bufferl float buffer2 Configure the STRBO control register to STRBO and STRB1 overlay 32 bit wide memory 32 bit data size If using the PRTS30 headers BUS_ADDR gt STRBO_gcontrol STRBO 1 CNFG MEMW 32 DATA 32 0x808064 0x2F0000 Configure STRB1 control register to 32 bit wide memory 16 bit data size If using the PRTS30 headers BUS_ADDR gt STRB1_gcontrol MEMW 32 DATA 16 0x808068 0OxD0000 Allocate 1K 16 bit words in the 16 bit memory pool bufferl mallocl6 1024 sizeof int Allocate 4K 16 bit floats in the 1
221. A 7 AA 7FFFh 8 bits wide Note Active address fields are shaded gray inactive address bits are white The black fields are special address bits that con trol multiple strobe lines or choose between portions of a data word that is larger than the physical memory it is accessing Memory Interfacing 4 65 Interfacing Memory to the TMS320C32 DSP 4 66 Each memory bank actually has three logical memory maps depending on the size ofthe data being accessed and the setting of the corresponding bits in the STRBO control register The address ranges in these logical memory maps are all different yet all three maps translate perfectly into a single physical address map that identifies the bank In using the three logical memory maps the programmer must exercise caution to prevent overwriting 8 bit data with 16 bit data or 16 bit data with 32 bit data that may have a different logical address but still occupy the same place in physical memory To be certain that the logical address maps associated with 8 16 and 32 bit data sizes do not overlap within a single physical memory bank the three logical maps must be further divided into mutually exclusive areas before they are used by the programmer Further more when a program jumps from one physical memory bank to another of a different width the memory width configuration bits in the appropriate strobe register must be changed How TMS320 Tools Interact With the TMS320C32 s Enhanced
222. A000 lt 1 call Input H Put ADC sample in delay buffer sti RO Ox80AF03 lt 2 call SFFT H Calculate SFFT sti RO G0x80AFOF 3 call Output Output result sti RO Ox80AF3F lt 4 b loop Loop back and do forever r r The ADC data is read and buffered here H Input ldi SO_rdata RO get ADC data ash 16 R0 Sign extend previous sample in MSB s float RO RO Convert the ADC data to float ldi CircAddr ARO Load present circ buf address ldf ARO R7 Multiply by K2 for bin stability mpyf K2 R7 see text SUE RO ARO E cmpi BUFEND ARO If at end of buffer point to start ldige BUFSTART ARO gt subrf RO R7 R7 X N X 0 sti ARO CircAddr save new circular modified ptr stf R7 NewMnsOld rets H 6 96 Example 6 18 SFFT ASM Continued Sliding FFT 3 1 3 of 7 cycles per bin calculation REAL and IMAG filter summations The forward and reverse SFFT are calculated within this one loop E The loop itself is unrolled to achieve an inner loop cycle count The inner loop contains both the so if the output is for spectrum analysis or only one filter sum is required one or both summations EndSFFT can be removed giving an inner loop speed of 6 cycles bin r r SFFT ldi Tbase ARO R I twiddle ptr Tai Bbase AR1 R I SFFT array ptr ldi Bbase AR2 SFFT output usualy in place ldi SFFTBINS 1 RC N
223. A14 Ao 32766 32766 32767 v 32767 32768 817FFFh 7FFFh 32768 dSG ZED0ZESWL 941 0 iowayy bureau Interfacing Memory to the TMS320C32 DSP 4 6 3 2 32 Bit Memory Address Translation for Data Size lt Memory Width 4 38 One memory location can store 2 or 4 data values Therefore if the data re quires 16 or 8 bits of precision the effective addressing range of the same physical 32 bit memory is doubled or quadrupled by simply changing the data size field of the appropriate strobe control register before the transfers begin The logical to physical address translation involves a 2 bit address shift if the data size is 8 bits and a 1 bit shift if the data size is 16 bits The memory inter face automatically performs address shifts and the activation of selected ex ternal memory bytes with appropriate strobe control lines as directed by the strobe control registers Figure 4 18 is the schematic diagram of a 32 bit interface consisting of two memory banks each controlled by a separate strobe The four signal lines of STRBO are assigned to the chip select pins of four 32K x 8 15 ns SRAMs and the four signal lines of STRB1 are connected to the chip enable pins of four 32K x830 ns EPROMsS For the 60 MHz version of the C32 the 15 ns SRAMs operate at zero wait states and the 30 ns EPROMs require one wait state Software wait states can be programmed in strobe control registers Figure 4 19 illustrates the pr
224. AtLAW COMPRESSION Ej NTS D RGU EN FUNCTION 0 NU R R R R NOTE ROUTINE ACMPR CALLING PROGRA CYCLI BER TO BE CONV EGISTERS USED AS INPUT RO EGISTERS MODIFI EGIS ED RO R1 R CONTAINING RESULT SINCE THE ES 22 WORDS global ACMPR ACMPR LDI ABSI CMP I BLED C L L PT IGT STACK POINT R2 RO ER SP SP IS USED IN THE COMPRESSION MAKE SURE TO INITIALIZE IT IN THI 19 R0 R1 RO RO 1FH RO END OFFFH RO OFFFH RO 1 RO RO 0 125 R0 1 R0 RO RO t20 R0 0 R2 R1 R1 80H R2 R2 RO0 OD5H RO E Save sign of number If RO lt 0x20 do linear coding If RO gt OXxFFF saturate the result Eliminate rightmost bit ormalize seg 3 OWXYZx x Adjust segment number by 2 3 seg WXYZx x Treat number as integer Righttjustify If number is negative set sign bit RO compressed number Invert even bits for transmission DSP Algorithms Companding Example 6 4 A Law Expansion TITLE A LAW EXPANSION SUBROUTINE AXPND ARGUMENT ASSIGNMENTS ARGUMENT FUNCTION RO NUMBER TO BE CONVERTED REGISTERS USED AS INPUT
225. B BZ LDI RETSU AR7 80h IOF loop5 AR3 R6 2 1OF 80h IOF loop6 6 IOF Boot Loader Source Code Listing intrnl dummy read pulses IACK wait for data ready XFl low from host read memory once R6 assert data acknowledge XFO low to host wait for data not ready XF1 high from host deassert data acknowledge XFO high to host TMS320C32 Boot Loader Program B 13 Appendix C Memory Access for C Programs This appendix describes the two memory models that can be used to access data when programming in C Two memory models can be used to access data when programming in C In the small model default the external bus cycles use direct addressing to ac cess data from memory Direct addressing uses 16 bits of address in the instruction opcode The address is combined with the 8 bit data page defined beforehand to access the data from memory The 16 bit address limits the number of words that the small model can access to 64K words However this mode produces fast and compact code because each data access uses only a single instruction see Figure C 1 The big model is not limited to 64K words because each data access in C ex plicitly sets the data page pointer DP register The 8 bit data page and 16 bit direct address are combined for a total address reach of 16M words but at a price of two instructions per data access see Figure C 1 Dynamically allocated memory can be used if
226. BROUTINE LATICE LOAD ARO LOAD AR1 LOAD RC CALL LATICE ARGUME ASSIGNMENTS ARGUME FUNCTION L R2 F P N E N EXCITATION ARO ADDRESS OF FILTER COEFFICIENTS K P ARI ADDRESS OF BACKWARD PROPAGATION VALUES B P 1 N 1 IRO 3 RC RC P t 3 REGISTERS USED AS INPUT R2 ARO AR1 RC REGISTERS MODIFIED RO R1 R2 R3 RS RE RC ARO ARI REGISTER CONTAINING RESULT R2 f 0 n STACK USAGE NONE PROGRAM SIZE 12 WORDS EXECUTION CYCLES 15 3 P42 global LATICE LATICE MPYF3 ARO AR1 RO K P B P 1 N 1 t RO Assume F P N t R2 SUBF3 RO R2 R2 JO F P N TK P B PE1 NET1 F P 1 N gt R2 BI MPYF3 ARO 1 AR1 1 R0 K P 1 B P 2 N 1 t RO SUBF3 RO R2 R2 F P 1 N TK P 1 B PX2 NXT1 F PE2 N gt R2 6 22 Example 6 10 Lattice Filter Continued Lattice Filters B MPYF3 ARO 1 AR1 1 R0 MPYF3 R2 ARO 1 R1 ADDF3 R1 AR1 1 R3 RPTB LOOP SUBF3 RO R2 R2 Nee Ne Ne Ne B MPYF3 ARO 1 AR1 1 STF R3 AR1 IRO HI MPYF3 R2 ARO 1 R1 LOOP ADDF3 R1 AR1 1 R3 STF R3 AR1 2 STF R2 AR1 1 RETURN SEQUENCE RETS end B I l N 1 gt R2 DSP Algorithms 6 23 Matrix Vector Multiplication 6 4 Matrix Vector Multiplication In matrix vector multiplication a K x N matrix of elements m i j having K rows
227. C LOW temp for 1 0 i lt 5 i while SERIAL_PORT_ADDR SI wn See note on XR for j 0 j lt 3 j n dummy S n ERIAL_PO See note on XRDY and for j 0 j lt 3 j ERIAL_PORT_ADDR SER_NUM gt gcontrol ERIAL_PORT_ADDR SE RT_ADDR SER_NUM gt x_data PULL 4215 0x0 ET RR ES ES R_NUM gt gcontrol ER_NUM gt gcontrol_bit xsrempty ET and three cycle delay in C3x U G XCLKSRCE OUT OF R ES ud XLEN 32 XFSM RFSM RLEN 32 XINT RINT FSXOUT ERIAL PORT ADDR SER NUM r data while SERIAL PORT ADDR SER NUM gcontrol bi SERIAL PORT ADDR SER NUM x data out int while SERIAL PORT ADDR SER NUM gcontrol bi in intval 0 S See note on RRDY and for j 0 j lt 3 j while SERIAL PORT in intval 1 S while in control bitval dcb ADDR SI ERIAL PORT ADDR SER NUM r three cycle delay in 0 out _intval 0 three cycle delay in C3x U G _ data ER NUM gt gcontrol_bit rrdy ERIAL PORT ADDR SER NUM r data RRESET XRESET xf t xrdy val 1 t rrdy C3x U Analog Interface Peripherals and Applications 8 63 CS4215 Interface to the TMS320C3x Example 8 16 CS4215 c Continued
228. C 8 808 04C 0090 0400 808 04C 0010 F868 Block 4 808 04C 0000 0010 900 400 10 808 04C 0000 0020 900 401 20 808 04C 0000 0030 900 402 30 808 04C 0000 0040 900 403 40 808 04C 0000 0050 900 404 50 808 04C 0000 0060 900 405 60 808 04C 0000 0070 900 406 70 808 04C 0000 0080 900 407 80 808 04C 0000 0000 TMS320C32 Boot Table Examples A 5 A 6 Appendix B TMS320C32 Boot Loader Operations This appendix contains the source code and boot loader opcodes for the C32 It also describes the on chip boot loader program that initializes the DSP sys tem following power up or reset Topic Page B 1 TMS320C32 Boot Loader Source Code Description B 2 B 2 TMS320C32 Boot Loader Opcodes sss B 4 B 3 Boot Loader Source Code Listing sess B 6 B 1 TMS320C32 Boot Loader Source Code Description B 1 TMS320C32 Boot Loader Source Code Description B 2 Figure B 1 shows the boot loader program flowchart The shaded areas re present portions of code the square shapes depict registers containing data The boot loader reads the boot table from one of three memory locations 1000h 810000h 900000h or from the serial port The boot loader processes each block of the boot table separately First the words of the program or data are assembled from bytes or half words The assembled words are then writ ten to their destinations one at a time Each block can be trans
229. C3x serial port configuration is toggled between con tinuous mode and burst mode In burst mode FSYNC indicates the start of a new data transfer In continuous mode the new data transfer starts immedi ately after the last bit of the previous transfer has been shifted out Both the serial port and the timer registers are memory mapped Eight memory mapped registers are provided for each serial port DD One global control register defines the serial port configuration Two control registers set the function of the CLKX CLKR and FSX FSR pins D Three receive transmit timer registers DD One data receive register One data transmit register If the serial port shift clock CLKR CLKX is generated externally the corre sponding timer can be used as a general purpose timer See the TMS320C3x User s Guide for more information on the C3x serial port TLC320AD58 Interface to the TMS320C3x Example 8 7 shows the C code for interfacing a TLC320AD58 to the C3x Example 8 8 page 8 36 shows the header file for the C code of Example 8 7 Example 8 9 page 8 38 shows the interrupt table vector list ing These examples perform the following tasks Initialize the TLC320AD58C and the C30 serial port 1 to meet the TLC320AD58C serial interface timing requirements Set up the timer O period register to generate the required MCLK frequency On a serial port 1 receive interrupt which occurs after receiving 32 bits from either
230. ESS OF FILTER COEFFICIENTS a2 0 ARI ADDRESS OF DELAY NODE VALUES d 0 n 2 BK BK 3 IRO IRO 4 IR1 IR1 4 Nt4 RC NUMBER OF BIQUADS N 2 REGISTERS USED AS INPUT R2 ARO AR1 IRO IR1 BK RC B REGISTERS MODIFIED RO R1 R2 ARO AR1 RC REGISTERS CONTAINING RESULT RO DSP Algorithms FIR IIR and Adaptive Filters Example 6 7 IIR Filters N 1 Biquads Continued LOOP global IIR2 PYF3 PYF3 PYF3 ADDF PYF3 ADDF3 PYF3 STF RPTB MPYF3 ADDF3 MPYE3 ADDF3 MPYF3 ADDF3 MPYF3 ADDF3 STF MPYFE3 ARO ARI ARO 1 CYCLES 17 6N WORDS 17 RO AR1 1 ARO 1 ARI RO RO R2 R2 ARO 1 AR1 1 R0 RO R2 R2 x ARO 1 R2 R2 AR1 1 LOOP R1 x ARO 1 AR1 IRO RO RO R2 R2 ARO 1 AR1 1 R1 R1 R2 R2 ARO 1 ARI RO RO R2 R2 ARO 1 AR1 1 R0 RO R2 R2 R2 AR1 1 x ARO 1 FINAL SUMMATION R2 R2 a2 0 d 0 nt2 t RO b2 0 d 0 nt2 t R1 al 0 D 0 nt1 gt RO First sum term of d 0 n b1 0 d 0 nt1 gt RO Second sum term of d 0 n 5b0 0 d 0 n t R2 Store d 0 n point to d 0 nt2 Loop for 1 ic n a2 i d i nt2 t RO First sum term of y itl n b2 i D i nt2 t
231. Example 8 16 CS4215 c Continued C_INT06 OR C INTO8 SERIAL PORT 0 1 RECEIVE INTERRUPT SERVICE ROUTINE if SER_NUM void c_int06 void void c_int08 void else void c int08 void void c_int06 void endif VPVF swap CS4215 WORD in out if first half First half first half FALSE of the 64 bit transmission in intval 0 SERIAL PORT ADDR SER NUM r data input xferO buffer index in stereo 16 bitval right in stereo 16 bitval left input xferl buffer index out stereo 16 bitval left out stereo 16 bitval right output xferl buffer index output xferO buffer index SERIAL PORT ADDR SER NUM x data out intval 0 if buffer_index buffer size swap input0 input0 input_xfer0 input_xfer0 swap swap inputl inputl input_xferl input_xferl swap swap output0 output0 output xfer0 output xfer0 swap swap outputl outputl output xferl output xferl swap buffer_index 0 buffer_rdy TRUE J KOKCKCKCK Ck Ck Ck A A A IA I IA IA IA I A I IA A IA ke ko A ke ke ke ke ee ee ee ee ee kx x f 7 a7 A KK Ck Ck Ck Ck Ck Ck A IA A IA I I IA A IA I IA IA I A I A ke ko ke ke ke ke ke ke ke ee eoe eoe ee ee kx x f 8 60 CS4215 Interface to the TMS320C3x Example 8 16 CS4215 c Continued
232. FT The in verse transformation assumes that the input data is in the same order as the output of the forward transformation It also produces a time signal in the proper order In other words bit reversing takes place at the end of the program Example 6 17 Real Inverse Radix 2 FFT Real Inverse FFT FILENAME E ifft rl asm WRITTEN BY E Daniel Mazzocco Texas Instruments Houston DATE 18th Feb 1992 VERSION 1 0 F VER DATE COMMENTS 1 0 18th Feb 92 Original release Started from forward real FFT routine written by Alex Tessarolo rev 2 0
233. FZ AR1 4 RO BND NEG R ABSF RO LSH 1 R0 A PUSHF RO POP RO ADDI AR1 2 RO0 LSH 1 R0 R RETS NEG POP RO 7 Fr ADDI AR1 2 R0 LSH 1 R0 A ADDI AR1 3 RO RETS 15 Determine the sign of the number If 0 load appropriate number Branch to NEG if negative delayed Take the absolute value of the number Eliminate the sign bit in RO Place number in lower 32 bits of RO Add exponent bias 127 Add the positive sign Place number in lower 32 bits of RO Add exponent bias 127 Make space for the sign Add the negative sign Logical and Arithmetic Operations 3 27 IEEE TMS320C3x Floating Point Format Conversion Example 3 14 TMS320C3x to IEEE Conversion Complete Version X FF X Ro F 0X X HF X x F Ro X Xo Xo F HF X o X 0X Xo F FH 0X 0X X TITLE TMS320C3x TO IEEE CONVERSION COMPLETE VERSION SUBROUTINE TOIEEE1 FUNCTION CONVERSION BETWEEN THE TMS320C3x FORMAT AND THE IEEE FLOATING POINT FORMAT THE NUMBER TO BE CONVERTED IS IN THE UPPER 32 BITS OF R0 THE RESULT WILL BE IN THE LOWER 32 BITS OF RO UPON ENTERI
234. For the two memory halves choose the STRBO and STRB1 logical ad dress ranges to drive the chosen bit to 0 and 1 respectively The chosen STRBO and STRB1 address ranges must fit inside the legal STRBO STRB1 address spaces as defined by the memory map 4 6 6 RDY Signal Generation The C32 uses the RDY pin to determine whether the current bus cycle finishes atthe end of the current clock cycle or requires additional clock cycles to com plete Even though the C32 can fetch instructions and access data in one clock cycle a slow memory may need additional clock cycles wait states to complete the bus cycle The RDY signal can be handled in one of three ways The RDY pin can be permanently grounded indicating to the CPU that the external memory is always ready for the next cycle This is used where all external memory is fast enough to preclude wait states The wait states can be programmed in software by setting bits in corre sponding strobe control registers if there is only one device per strobe This method can be used even if there are external devices that require wait states The RDY pin must be permanently grounded Memory Interfacing 4 57 Interfacing Memory to the TMS320C32 DSP The active generation of the RDY signal is required only if a single strobe controls two or more external memory banks or peripherals requiring dif ferent numbers of wait states The remainder of this section describes the active gene
235. GISTER CONTAINING RESULT RO global DOT DOT PUSH SE H Save status register PUSH R2 A Use the stack to save R2 s PUSHF R2 Lower 32 and upper 32 bits PUSH ARO Save ARO PUSH ARI H Save AR1 PUSH RC H Save RC Program Control Subroutines Example 2 1 Subroutine Call Dot Product Continued H Initialize RO MPYF3 ARO ARI1 RO al 0 b 0 gt RO LDF 0 0 R2 H Initialize R2 SUBI 2 RC Set RC N 2 DOT PRODUCT 1 lt i lt N RPTS RC Setup the repeat single MPYF3 ARO 1 AR1 1 RO a i b i t RO ADDF3 RO R2 R2 a itl b itl R2 gt R2 ADDF3 R0 R2 R0 a Nt1 b Nt1 R2 gt RO RETURN SEQUENCE POP RC H Restore RC POP AR1 Restore AR1 POP ARO x Restore ARO POPF R2 Restore top 32 bits of R2 POPR2 H Restore bottom 32 bits of R2 POPST H Restore ST RETS Return A end end 2 4 Stacks and Queues 2 2 Stacks and Queues 2 2 1 The C3x provides a dedicated stack pointer SP register for building stacks in memory Also the auxiliary registers can be used to build user stacks and a variety of more general linear lists This section discusses the implementa tion of the following types of linear lists Stack A linear list for which all insertions and deletions are made at one end of the list Queue A linear list for which all insertions are made at one end of the list and all deletions are made at the other end
236. H OPF ETS TD tya E TU USH OPF EGF RETS TU RO AR1 R1 Replace fraction with 0 NEG Test sign RO R1 Shift sign and exponent inserting 0 If all 0 generate C30 0 Unbias exponent AR1 1 R1 AR1 2 z RL Ne Ne Ne Ne Ne Ne Rl RO H Load this as a flt pt number R1 RO Load this as a flt pt number RO RO Negate if orig sign is negative Example 3 12 shows the complete conversion between the IEEE and C3x formats In addition to the general case and the Os ithandles the special cases as follows LJ If NaN e 255 f lt gt 0 the number is returned intact D Ifinfinity e 255 f 0 the output is saturated to the most positive or negative number respectively Lj If denormalized e 0 f lt gt 0 two cases are considered If the MSB of fis 1 the number is converted to C3x format Otherwise an underflow oc curs and the number is set to O Logical and Arithmetic Operations 3 23 IEEE TMS320C3x Floating Point Format Conversion Example 3 12 IEEE to TMSS20C3x Conversion Complete Version TITLE IE T T TO TMS320C3x CONVERSION COMPLETE VERSION SUBROUTI FMIEEE1 fl FUNCTION CONVERSION BETWEEN THE IEEE FORMAT AND THE TMS320C3x FLOATING POINT FORMAT THE NUMBER TO BE CONVERTED IS IN THE LOWER 32 BITS OF RO THE RESULT IS STORED IN THE UPPER 32 BITS OF RO
237. Interface to the TMS320C3x Example 8 15 CS4215 h Continued define ATT 62 62 TN 93 0 wy define ATT_63 63 94 5 define HEADPHONE OFF 0 define HEADPHONE ON 1 define LINE_OUT_OFF 0 define LINE_OUT_ON 1 define SPEAKER_OFF 0 define SPEAKER_ON 1 Input gain is 1 5 dB per unit integer value Di Gain dB 4 define GAIN O0 0 0 0 define GAIN 1 1 145 define GAIN 2 2 F 30 Kf define GAIN_3 3 5 4 5 define GAIN 4 4 6 0 define GAIN 5 5 7 5 define GAIN_6 6 9 0 Sf define GAIN_7 7 8 10 5 define GAIN_8 8 12 0 define GAIN 9 9 13 5 define GAIN 10 10 15 0 wef define GAIN_11 Lll aa 16 5 define GAIN_12 12 18 0 define GAIN 13 13 19 5 define GAIN 14 14 21 0 define GAIN 15 15 22 5 xy define LINE IN 0 define MIKE IN define OVERANGE ENABLE 1 define OVERANGE CLEAR 0 Monitor path attenuation 6 dB per unit integer value zy Gain dB f mam define MATT O0 0 6 0 define MATT 1 all 12 0 sy define MATT_2 2 p 18 0 define MATT_3 3 24 0 ur define MATT 4 4 30 0 define MATT_5 5 36 0 define MATT 6 6 42 0 wy define MATT_7 7 JE 48 0 define MATT 8 8 54 0 define MATT 9 9 60 0 wy define MATT_10 10 66 0 bh Anal
238. KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCK Ck Ck K ck k ck k ck ck ck ck kk kc k kk e ke X ke A ke I f include lt math h gt include lt stdlib h gt include lt string h gt include lt cs4215 h gt BORK KK KK kCk kCk kCK kCK KCK CKCK KCKCKCKCKCK KCKCKCK KCK KCK KCK KCK KCK KCK KCK KCK KCK KCK CK k KC k k ck k ck ck ckck ck ck OR eR f GLOBAL VARIABLES y BRK IK RR Kk RA KC kCk kCkCkCk KCkCKCk KCKCKCk KCKCKCk KCKCKCk KCK KCk KCKCKCk KCK Ck ck k ck ck ck k ckck ck ck ck ck kc k ck e ke A ke x ke I f int buftfer size BLOCK SIZE SIZE OF I O BUFFER S VPVF output0 OUTPUT DATA BUFFER FOR PROCESSOR i VPVF input0 INPUT DATA BUFFER FOR PROCESSOR wy VPVF output xfer0 OUTPUT DATA BUFFER FOR ISR CODEC xg VPVF input xfer0 INPUT DATA BUFFER FOR ISR CEDEC VPVF outputl OUTPUT DATA BUFFER FOR PROCESSOR R VPVF inputl INPUT DATA BUFFER FOR PROCESSOR A VPVF output xferl OUTPUT DATA BUFFER FOR ISR CEDEC ay VPVF input_xferl INPUT DATA BUFFER FOR ISR CODEC 4 VI buffer rdy FALSE CPU ISR COMM FLAG INPUT VI buffer index 0 INDEX INTO INPUT AND OUTPUT DATA ARRAYS VI first half TRUE VI is GENERIC COUNTER VARIABLE CS4215 WORD data control if C ISR Analog Interface Peripherals and Applications 8 59 CS4215 Interface to the TMS320C3x
239. L CALLING SEQUENCE load ARO load ARI load AR2 load AR3 load RI CALL MAT ARGUMENT ASSIGNMENTS ARGUMEN FUNCTION ARO ADDRESS OF M 0 0 BRI ADDRESS OF V 0 AR2 ADDRESS OF P 0 AR3 NUMBER OF ROWS 1 Kt1 RI NUMBER OF COLUMNS 2 N 2 REGISTERS USED AS INPUT ARO AR1 AR2 AR3 R1 REGISTERS MODIFIED RO R2 ARO AR1 AR2 AR3 IRO RC RSA REA PROGRAM SIZE 11 XECUTION CYCLES 6 10 K K N1 global MAT SETUP MAT LDI R1 IRO Number of columnst2 gt IRO ADDI 2 IRO IRO N FOR i 0 i lt K i LOOP OVER THE ROWS DSP Algorithms 6 25 Matrix Vector Multiplication Vector Maximum Search Example 6 11 Matrix Times a Vector Multiplication Continued ROWS LDF D OU R2 H Initialize R2 MPYF3 ARO 1 AR1 1 RO a m i 0 v 0 gt RO m FOR j 1 j lt N j DO DOT PRODUCT OVER COLUMNS RPTS R1 F Multiply a row by a column MPYF3 ARO 1 AR1 1 RO0 m i j v j gt RO ADDF3 RO0O R2 R2 gt om i jt1 v jtl R2 t R2 DBD AR3 ROWS a Counts the no of rows left a ADDF RO R2 Last accumulate STF R2 AR2 1 Result t p i NOP AR1 IRO Set AR1 to point to v 0 DELAYED BRANCH HAPPENS HERE RETURN SEQUENCE RETS H Return end end 6 5 Vector Maximum Search 6 26 In vector maximum s
240. M whose physical width is less than 32 bits the physical interface of the EPROM device s to the processor must be the same as that of the 32 bit interface This involves a specific connection to the C32 s strobe and address signals The reason for such an arrangement is that to function properly the boot loader program always expects 32 bit data from 32 bit wide memory during the boot load operation Valid boot EPROM widths are 1 2 4 8 16 and 32 bits A single source block cannot cross STRB boundaries For example its destination cannot overlap STRBO space and IOSTRB space Additionally all of the destination addresses of a single source block must reside in physical memory of the same width It is not permitted to mix program and data in the same source block The boot loader stops boot operation when it finds a 0 in the block size control word Therefore each boot table must end with a 0 prompting the boot loader to branch to the first address of the first block and start program execution from that location C32 boot loader program register assignments and altered memory locations AR7 peripheral memory map IOF XFO handshake data acknowledge ARO read cntrl data subr pointer IOF XF1 handshake data ready AR1 read block data prg subr pointer R2 read STRB value R4 write STRB value AR2 read STRB pointer ARA write STRB pointer AR3
241. MA on chip access happens dur ing the H3 phase Refer to the Pipeline Operation chapter in the TMS320C3x User s Guide for details on CPU accesses If a conflict occurs during CPU DMA access on the C32 the priority set between the CPU and DMA is used to arbitrate conflicts If the DMA chan nel has lower priority than the CPU the DMA may fail to finish a block transfer if conflicts occur To avoid this condition use CPU DMA rotating priority in the corresponding DMA control register i aaea Note Expansion and Peripheral Buses The expansion and peripheral buses on the C30 cannot be accessed simul taneously because they are multiplexed into a common port Therefore DMA access to the peripheral bus along with CPU access to the expansion bus can cause CPU DMA conflicts See the TMSS320C3x User s Guide for more information DD When you use interrupt synchronization ensure that interrupts are actual ly generated otherwise the DMA will never complete the block transfer Use read write synchronization when reading from or writing to serial ports to guarantee data validity When a DMA Channel Finishes a Transfer 7 2 When a DMA Channel Finishes a Transfer Many applications require that you perform certain tasks after a DMA channel has finished a block transfer The following are indications that the DMA has finished a set of transfers d The DINT bit in the IIF register is set to 1 interrupt polling This re qui
242. MAKE SURE RESET IS HELD LOW SUFFICIENTLY RESET BB WAIT 50 dif GEN OSC CONFIGURE C3X TIMER AS BB A D OSC IMER ADDR OSC TIMER NUM gcontrol 0x0 TIMER ADDR OSC TIMER NUM counter 0x0 IMER ADDR OSC TIMER NUM period 0x0 IMER ADDR OSC TIMER NUM gcontrol FUNC GO HLD KK Ck Ck Ck Ck Ck kk Ck Ck Kk Ck Kk Ck Ck Ck Ck Kk Ck kk Kk kk kk kk kk kc ko ke ke ke ke ke ke ke ke ke ke e ke e eoe ee ee kx x f DATA ARRAY PARAMET J ECKCK Ck kk Ck ok Ck kk ok kk kk III ek kk Ck ke k Ck Kk Ck Ck kk Kk ok Ck Kk ko I Ck kk ek Ok kk ko kk I ke kk Kok kk ee int r buffer RE float fFloat float fFloat Float float fFloat Float f INIT_BB J KOKCKCKCK Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Kk Ck Ck Ck Ck Ck Kk Ck kk kk kk kk kk kk kc ko ke ko ke ke ke ke ke ke ke ee ee e e e e kx x f i LONG CP CLKSRC 8 16 Burr Brown DSP101 2 and DSP201 2 Interface to TMS320C3x Example 8 2 TMS320C3x BB DSP102 202 Driver Continued CONFIGURE SERIAL PORT SERIAL PORT ADDR SER NUM gcontrol 0x0 SE
243. Memory Banks The C32 s external memory interface allows the use of two zero wait state ex ternal memory banks with different widths without requiring additional logic or incurring access penalty costs These external memory banks provide flexibil ity in balancing performance and system cost performance and system cost increase with wider memory chips For example the programmer can execute code from 32 bit wide memory while storing data in 8 bit memory see Figure 4 33 This approach is advantageous for applications with large amounts of 8 bit data that require execution at the fastest speed of the device 4 74 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface Figure 4 33 Zero Wait State Interface for 32 Bit and 8 Bit SRAM Banks TMS320C32 32 bit wide memory banks 8 bit wide A14 gt A14 gt A14 14 gt A14 memory bank A13 Pp As mA 9 3 A A12 gt A12 gt A12 H A12 gt A12 gt A14 A11 gt A1 mA H 1 mA I 3 13 Ai gt A4 gt A4 H A gt A4 m Ag Ao gt Ao gt Ao Ao gt Ao m Ao E EP mE mA RW gt We WE WE gt WE gt A0 gt CS ules T5 T5 N STRB1_B3 O 7 0 O 7 0 O 7 0 O 7 0 CS STRBO B2
244. Memory Interface 4 7 3 Linker Switches To support the C32 s 8 and 16 bit memory pools the linker uses the following switches heap8 heap16 and heap These switches set the size in words of the respective 8 16 and 32 bit memory system areas sysm8 sysm16 and sysmem The user must link these sections into the appropriate address es thereby activating strobes that are configured to access 8 16 or 32 bit data The following example demonstrates the link time sizing of an 8 bit memory pool to 256K words lnk30 heap8 0x4000 The linker creates these memory system areas using an input file that contains the sysmem sysm8 and sysm16 data section definitions If the input file does not exist the linker is unable to perform memory area processing The linker also creates the global symbols SYSMEM SIZE SYS MEMS SIZE and SYSMEM 16 SIZE and subsequently assigns each a val ue equal to the respective heap heap8 and heap16 size The default size for each memory system area is 1K words word size depends on system memory width 4 7 4 Debugger Configuration For the debugger to properly disassemble and read write external memory the user must configure the strobe control registers before loading and execut ing code Because the C32 supports code execution from 16 or 32 bit memory the debugger may need to temporarily set the strobe control register to a 32 bit data size in order to write an instruction eith
245. Memory Interface 4 7 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface The C32 s memory interface accesses external memory through one 24 bit address bus and one 32 bit data bus The data bus is shared by three mutually exclusive strobes STRBO STRB1 and IOSTRB Depending upon the ad dress accessed the C32 activates one of these strobes See the TMS320C3x User s Guide for more information about memory maps STRBO and STRB1 can access 8 16 or 32 bit data quantities from 8 16 or 32 bit wide memory Access is achieved by four signals within each strobe These signals are STRBx B3 A 4 STRBx B2 A 2 STRBx B1 STRBx BO The listed signals serve as byte enable pins for accessing a byte half word or full word from external memory The first two signals also serve as addition al address pins when performing two or four consecutive accesses in 8 or 16 bit wide external memory The data accessed is truncated packed or un packed accordingly with no additional overhead The following list shows the behavior of these pins as dictated by the data size and memory width bit fields The default value of a strobe control register depends on the program memory width select PRGW pin level 8 bit wide memory B SIRBx BS3 A 4 and STRBx B2 A are address pins B SIRBx BO is a byte enable chip select signal B STRBx_B1 is not used Lj 16 bit wide memory B STRBx_B3 A_ are ad
246. NG THE ROUTINE AR1 POINTS TO THE FOLLOWING TABLE 0 OxFF800000 AR1 1 OxFF000000 2 0x7F000000 3 0x80000000 4 0x81000000 5 0x7F800000 6 0x00400000 7 0Ox007FFFFF 8 Ox7F7FFFFF ARGUMEN ASSIGNMENTS ARGUMEN FUNCTION RO NUMBER TO BE CONVERTED AR1 POINTER TO TABLE WITH CONSTANTS REGISTERS USED AS INPUT RO AR1 REGISTERS MODIFIED RO REGISTER CONTAINING RESULT RO OTE SINCE HE STACK POINTER SP IS USED MAKE SURE TO INITIALIZE IT IN THE CALLING PROGRAM CYCLES 31 WORST CASE WORDS 25 global TOIEEE1 3 28 IEEE TMS320C3x Floating Point Format Conversion Example 3 14 TMS320C3x to IEEE Conversion Complete Version Continued TOIEEEI1 LDF RO RO Determine the sign of the number LDFZ AR1 4 RO0 E If 0 load appropriate number BND NE Branch to NEG if negative delayed ABSF RO Take the absolute value H of the number LSH 1 R0 x Eliminate the sign bit in RO PUSHF RO POP RO Place number in lower 32 bits of RO ADDI AR1 2 R0 Add exponent bias 127 LSH 1 R0 Add the positive sign CONT STB AR1 5 RO RETSNZ Ife 0 return STB AR1 7 RO RETSZ Ife 0 amp f 0 return PUSH RO POPF RO LSH 1 R0 Shift f right by one bit PUSHF RO POP RO ADDI AR1 6 RO Add 1 to the MSB of f RETS NEG POP RO Place number in lower 32 bits of RO BRD CONT ADDI ARI 2 R0 Add exponent bias 127 LSH 1 R0 M
247. NTS ARGUMEN FUNCTION RO v NUMBE UPON THE CALL RO SORT v UPON THE RETURN R TO FIND THE SQUARE ROOT OF EGISTERS MODIFIED RO R1 R2 R3 EGISTER CONTAINING RESULT RO R R CYCLES 50 WORDS 39 REGISTER USED AS INPUT RO global SQRT EXTRACT THE EXPONENT OF v SQRT LDF RO R3 H Save v RETSLE Return if number is nontpositive PUSHF RO POP R1 ASH 24 R1 The 8 LSBs of R1 contain exponent of v ADDI 1 R1 Add a rounding bit in the exponent ASH 1 RL P e 2 X 0 FORMATION GIVEN THE EXPONENT OF v NEGI R1 ASH 24 R1 PUSH R1 POPF R1 Now R1 x 0 1 0 2 te 2 3 14 Square Root Computation Example 3 7 Square Root of a Floating Point Number Continued GENERATE v 2 MP YF 0 5 R0 A v 2 and take rounding bit out NOW THE ITERATIONS BEGIN PYF R1 R1 R2 R2 x 0 x 0 PYF RO R2 R2 v 2 x 0 x 0 SUBRF 1 5 R2 R2 1 5 v 2 x 0 x 0 PYF R2 R1 R1 x 1 x 0 1 5 t v 2 x 0 x 0 RND R1 PYF RI RI R2 3 R2 x 1 x 1 PYF RO R2 R2 v 2 x 1 x 1 SUBRF 1 5 R2 R2 1 5 4 v 2 x 1 x 1 PYF R2 R1 Rl x 2 x 1 1 5 c v 2 x T x L RND R1 PYF RI R1 R2 R2 x 2 x 2 PYF RO R2 R2 v 2 x 2
248. No Reference Description Min Max Unit _ 1 tH3 min H3 period 35 200 ns tH3 max 2 tH3 high min H3 high pulse duration 15 ns 3 tH3 low min H3 low pulse duration 15 ns 4 tg EMUO 1 2 EMUO 1 2 valid from H3 low 7 23 ns 5 tsu EMUS EMUS setup time to H3 high 3 ns 6 thd EMUS EMU3 hold time from H3 high 11 ns 10 4 Connections Between the Emulator and the Target System 10 4 Connections Between the Emulator and the Target System Itis extremely important to provide high quality signals between the emulator and the C3x on the target system In many cases the signal must be buffered to produce high quality The need for signal buffering can be divided into three categories depending on the placement of the emulation header Lj Nosignals buffered In this situation the distance between the emulation header and the C3x should be no more than 2 inches see Figure 10 4 Figure 10 4 Connections Between the Emulator and the TMS320C3x With No Signals Buffered k 2 inches or less TMS320C3x Emulator header Voc A 3 Pp 2 EMUO EMUO 2 EMU1 1 EMUT GND f EMU2 5 EMU2 D T GND e GND 5 6 10 EMU3 3 Emus GND 77e H3 1 hs GND V GND XDS510 Emulator Design Considerations 10 5 Connections Between the Emulator and the Target System Transmission signals buffered In this situation the distance between the emulation header and the C3x is greater than 2 in
249. O R2 If bit 1 set Jth bit of R2 CONT Logical and Arithmetic Operations Block Moves 3 2 Block Moves Since the C3x addresses a large amount of memory blocks of data or pro gram code can be stored off chip in slow memories and then loaded on chip for faster execution Data can also be moved from on chip to off chip memory for storage or for multiprocessor data transfers You can use direct memory access DMA in parallel with CPU operations to accomplish such data transfers The DMA operation is explained in detail in Programming the DMA Coprocessor chapter later in the book An alternative to DMA is to perform data transfers under program control using load and store instructions in a repeat mode Example 3 3 shows the transfer of a block of 512 floating point numbers from external memory to block 1 of the on chip RAM Example 3 3 Block Move Under Program Control TITLE BLOCK MOVE UNDER PROGRAM CONTROL extern word 01000H blockl word 0809C00H EDI extern ARO A Source address LDI block1 AR1 A Destination address LDF ARO RO H Load the first number RPTS 510 H Repeat following instruction 511 times LDF ARO RO A Load the next number and STF RO AR1 store the previous one STF RO AR1 Store the last number Bit Reversed Adaressing 3 3 Bit Reversed Addressing The C3x can implement fast Fourier transforms FFTs with bit reversed addressing If the data to
250. ORS FOR A 64tPOINT FFT TITLE TABLE WITH TWIDDLI FILE TO BE LINKED WITH THE SOURCE CODE globl SINE globlN globlM N Set 64 M Set 6 data SINE float 0 000000 float 0 098017 float 0 195090 float 0 290285 float 0 382683 float 0 471397 float 0 555570 float 0 634393 float 0 707107 float 0 773010 float 0 831470 float 0 881921 float 0 923880 float 0 956940 float 0 980785 float 0 995185 COSINE float 1 000000 float 0 995185 float 0 980785 float 0 956940 float 0 923880 float 0 881921 float 0 831470 float 0 773010 float Q 707107 float 0 634393 float 0 555510 float 0 471397 float 0 382683 float 0 290285 float 0 195090 float 0 098017 FOR A 64 POINT RADIX 2 FFT 6 34 Fast Fourier Transforms FFTs Example 6 14 Table With Twiddle Factors for a 64 Point FFT Continued Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh Fh loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat loat I I HH 000000 098017 195090 290285 382683 0 471397 0 555570 634393 70
251. OS 2 VAX VMS PC DOS MS DOS SPARC SUN OS t PC DOS PC SPARC Operating System PC MS DOS PC MS DOS Part Number TMDS3243255 08 TMDS3243855 02 TMDS3243555 08 TMDS3243850 02 TMDS3243251 08 TMDS3243851 02 TMDS3243551 09 DFDP TMDX3240030 Part Number TMDS3240130 TMDS3260030 T Note that SUN UNIX supports C3x software tools on the 68 000 family based SUN 3 series workstations and on the SUN 4 series machines that use the SPARC processor but not on the SUN 386i series of workstations TMS320C3x Part Ordering Information 11 2 1 Device and Development Support Tool Prefix Designators Prefixes to TI part numbers designate phases in the product s development stage for both devices and support tools as shown in the following definitions Device Development Evolutionary Flow J TMX Experimental device that is not necessarily representative of the final device s electrical specifications D TMP Final silicon device that conforms to the device s electrical specifica tions but has not completed quality and reliability verification DD TMS Fully qualified production device Support Tool Development Evolutionary Flow D TMDX Development support product that has not yet completed TI s internal qualification testing for development systems Jg TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped with the following disclaimer Developmental produ
252. POINTED AT BY AR1 REAL AND IMAGINARY POINTS ARE ALTERNATING LDI 512 1IRO0 LDI 2 IR1 LDI 511 RC H Repeat 511 1 times LDF AR0 1 R1 A Load first imaginary point RPTB LOOP LDF ARO IRO B RO Load real value and point Ii STF R1 AR1 1 to next location and store E the imaginary value LOOP LDF ARO 1 R1 H Load next imaginary point and store STF RO AR1 IR1 H previous real value Logical and Arithmetic Operations 3 5 Integer and Floating Point Division 3 4 3 4 1 3 6 Integer and Floating Point Division Although division is not implemented as a single instruction in the C3x the instruction set can perform an efficient division routine Integer and floating point division are examined separately because a different algorithm is used for each Integer Division Division is implemented on the C3x by repeated subtractions using SUBC a special conditional subtract instruction Consider the case of a 32 bit positive dividend with i significant bits and 32 i sign bits as well as a 32 bit positive divisor with j significant bits and 32 j sign bits The repetition of the SUBC command i j 1 times produces a 32 bit result in which the lower i j 1 bits are the quotient and the upper 31 i j bits are the remainder of the division SUBC implements binary division in the same manner as long division The divisor which is assumed to be smaller than
253. PROM using pins XFO and XF1 for handshaking The handshaking protocol assumes that the data ready signal generated by the host arrives through pin XF1 The data acknowledge signal is output from the C32 on pin XFO Both Signals are active low The C32 continuously toggles the IACK signal while waiting for the host to assert data ready signal pin XF1 The boot operation involves transfer of one or more source blocks from the boot media to the destination memory The block structure of the boot table serves the purpose of distributing the source data program among different memory spaces Each block is preceded by several 32 bit control words describing the block contents to the boot loader program When loading from the serial port the boot loader reads the source data program and writes it to the destination memory There is only one way to read the serial port When loading from EPROM however there are 4 ways to read and assemble the Source contents depending on the width of boot memory and the X X OX X Xo Ro X Xo x HF F X X o X F OX OX F Xo Xo X OX X F Xo X X X X X Xo X F xXx X F xS X KF OF 5 Boot Loader Source Code Listing size of the program data being transferred Because there is a possibility that reads and writes can span the same STRB space the boot loader loads the appropriate STRB control registers befor ach read and write If the boot source is an EPRO
254. PU to transfer data to internal memory before you operate on it Avoid pipeline conflicts For time critical operations make sure you do not miss any cycles because of pipeline conflicts Programming Tips 5 5 Hints for Assembly Coding 5 6 The preceding checklist is not exhaustive and it does not address the detailed features outlined in other chapters of this manual To learn how to exploit the full power of the C3x study the architecture hardware configuration and instruction set of the device described in the TMS320C3x User s Guide Low Power Mode Wakeup Example 5 3 Low Power Mode Wakeup Example There are two instructions by which the C31 LC31 and C32 are placed in the low power consumption mode IDLE2 LOPOWER The LOPOWER instruction slows down the H1 H3 clock by a factor of 16 dur ing the read phase of the instruction The MAXSPEED instruction wakes the device from the low power mode and returns it to full frequency during MAXSPEED s read cycle However the H1 H3 clock may resume in the phase opposite to the one it was in before the clocks were shut down The IDLE2 instruction has the same functions that the IDLE instruction has except that the clock is stopped during the execute phase of the IDLE2 instruc tion The clock pin stops with H1 high and H3 low The status of all the signals remains the same as in the execute phase of the IDLE2 instruction In emula tion mode however the clocks continue t
255. Pod Interface i Emulator Cable Pod Timings ss ee Connections Between the Emulator and the TMS320C3x With No Signals Buffered 2c ne eb LIE UU ate E RU act ae Connections Between the Emulator and the TMS320C3x With Transmission Signals Buffered ees Connections Between the Emulator and the TMS320C3x With All Signals Buffered casses needed bal be d ee Pod Connector Dimensions 0 12 Pin Connector Dimensions 00 cc cc ee eee een E ENE TBC Emulation Connections for TMS320C3x Scan Paths i TMS320 Device Nomenclature 0 Current Measurement Test Setup for the TMS320C30 i Internal Bus Current Versus Transfer Rate AAAAAAAAR to 55555555h Internal Bus Current Versus Data Complexity Derating Curve ii Primary Bus Current Versus Transfer Rate and Wait States 9 Primary Bus Current Versus Transfer Rate at Zero Wait States Contents Figures 12 6 12 7 12 8 12 9 12 10 12 11 12 12 12 13 12 14 A 1 A 2 pope qe Rony AOO ce ak YT Pr uu OOOO0U T Co a ON OD Xxiv Expansion Bus Current Versus Transfer Rate and Wait States 12 13 Expansion Bus Current Versus Transfer Rate at Zero Wait States 12 14 Primary Bus Current Versus Data Complexity Derating Curve 2045 12 15 Expansion Bus Current Versus Data Complexity Derating Curve 12 15 Current Versus Output Load Capacitance 4 12 16 Cur
256. R 2 R2 addf 6 98 Sliding FFT Example 6 18 SFFT ASM Continued mpyf RO RO Calculate REAL 2 IMAG 2 magnitude mpyf R2 R2 gt addf R2 R0 A call FLOG2 Convert to log2 then scale mpyf 32 R0 and shift for best display mpyf 32 R0 H subf MAX RO E endif H Out fix RO RO Convert to integer DAC output mpyi bigval RO Use Overflow mode ALU saturation ash 16 R0 andn 3 R0 Do not request a 2nd xmit sti RO SO_xdata Output DAC value to serial port rets i i i FLOG2 Ultra Fast LOG2 function gt Computes log2 R0 and returns e8 sl m4 accuracy float value in RO FLOG2 cmpf 0 0 R0 Exit if value is lt Zero ldfle 1 R0 if x 0 return 1 error retsle return if X lt 0 lsh 1 R0 Concatenate mantissa to exponent pushf RO Convert fast log to int then float pop RO Value is accurate but scaled by 2 24 float RO RO mpyf FLOG2SC RO Mpy by scale factor rets i The startup stub is used during initialization only and can be overwritten by the stack or data after initialization is complete Note A DSK or RTOS communications kernel may also use the stack In this case be sure to not put the stack here during debug r entry SI STUB Debugger starts here ST STUB ldp TO ctrl Use kernel data page and stack ldi stack SP ldi 0 RO Halt TIMO amp TIM1 sti RO TO_ct
257. R SYSTEMS OR OTHER CRITICAL APPLICATIONS Inclusion of TI products in such applications is understood to be fully at the risk of the customer Use of TI products in such applications requires the written approval of an appropriate TI officer Questions concerning potential risk applications should be directed to TI through a local SC sales office In order to minimize risks associated with the customer s applications adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards TI assumes no liability for applications assistance customer product design software performance or infringement of patents or services described herein Nor does TI warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Copyright 1997 Texas Instruments Incorporated About This Manual Preface Read This First This user s guide serves as a reference book for the TMS320C3x generation of digital signal processors which includes the TMS320C30 TMS320C31 TMS320LC31 and TMS320C32 Throughout the book all references to C3x refer collectively to C30 C31 and C32 and the TMS320C30 TMS320C31 and TMS320C32 refer to all speed variations unless an exception is n
258. R1 STF R4 ARO ADDF3 RO R1 R2 MPYF3 AR5 AR4 IRO RO 6 56 Fast Fourier Transforms FFTs Example 6 16 Real Forward Radix 2 FFT Continued SUBF3 RO R1 R3 SUBF3 AR1 R3 R4 ADDF3 AR1 R3 R4 STE R4 AR2 SUBF3 R2 ARO R4 STE R4 AR3 ADDF3 ARO R2 R4 STF R4 AR1 MPYF3 AR2 R7 R4 STF R4 ARO MPYF3 AR3 R7 R1 MPYF3 AR5 AR3 RO ADDF3 RO R1 R2 SUBF3 R4 RO R3 SUBF3 AR1 R3 R4 ADDF3 AR1 R3 R4 STF R4 AR2 SUBF3 R2 ARO R4 STF R4 AR3 ADDF3 ARO R2 R4 STF R4 AR1 STF R4 ARO DSP Algorithms 6 57 Fast Fourier Transforms FFTs Example 6 16 Real Forward Radix 2 FFT Continued Perform remaining FFT loops loop 4 onwards i LOOP lst 2nd v v f X I1 0 0 Xx I1 X 13 r AR1L X I1 1st 1 1 4 x 11 X I3 COS X I4 SIN r X I1 2nd 2 P f x I1 3rd 3 3 A X I2 8 16 B s X I2 3rd 13 29 r X 12 2nd 14 30 f AR2 Xx I2 1st 15 31 X I1 x 13 COS X I4 SIN f X I3 16 32 x 11 X 13 f AR3 x 13 1st 17 33 X I12 X I3 SIN X I4 COS X I3 2nd 18 34 X 13 3rd 19 35 Me wa Na NaS C X 14 24 48 X 14 7 D X I4 3rd 29 61 r X I4 2nd 30 62 i r ARA Xx I4 1st 31 63 X I2 X I3 SIN
259. R1 Second sum term of y itl n al i d i ntl t RO First sum of d i n bl i d i ntl t RO Second sum term of d i n Store d i n point to d i nt2 bO i d i n t R2 FIR IIR and Adaptive Filters Example 6 7 IIR Filters N 1 Biquads Continued ADDF RO R2 First sum term of y ntl n ADDF3 R1 R2 R0 H Second sum term of y ntl n NOP ARI IR1 H Return to first biquad NOP AR1 1 Point to d 0 nt1 RETURN SEQUENCE RETS H Return end end 6 2 3 Adaptive Filters Least Mean Squares Algorithm In some applications in digital signal processing you must adapt a filter over time to keep track of changing conditions This is accomplished by adapting a coefficient to a filter and creating a new coefficient by means of a least mean squares LMS algorithm The equations for this process are described below The book Theory and Design of Adaptive Filters presents the theory of adap tive filters Although in theory both FIR and IIR structures can be used as adaptive filters the stability problems and the local optimum points that the IIR filters exhibit make them less attractive for such an application Hence until further research makes IIR filters a better choice only the FIR filters are used in adaptive algorithms of practical applications In an adaptive FIR filter the filtering equation takes this form y n h n 0 x n h n 1 x
260. RIAL PORT ADDR SER NUM s x control CLKXFUNC DXFUNC FSXFUNC SERIAL PORT ADDR SER NUM s r control CLKRFUNC DRFUNC FSRFUNC SERIAL PORT ADDR SER NUM s rxt control OxO0F SERIAL PORT ADDR SER s rxt period 0x0 SERIAL PORT ADDR SER NUM gcontrol XCLKSRCE XLEN 32 RLEN 32 XINT XRESET RRESET CLEAR SERIAL TRANSMIT DATA SERIAL PORT ADDR SER NUM x data 0x0 TAKE A D D A OUT OF RESET OPTIONALY CLEAR THE INT FLAG REG ENABL HE APPROPRIATE SERIAL PORT TRANSMIT INT AND ENABL GLOBAL INTERRUPTS G UN RESET BB CL INT FL REG if SER NUM N SER PORT XMT INT 1 I else EN SER PORT XMT INT 0 endif EN_GLOBAL_INTS dif GEN CC CONFIGURE C3X TIMER 1 AS BB A D D A CONVERT CLOCK IMER ADDR CC TIMER NUM gcontrol 0x0 IMER ADDR CC TIMER NUM counter 0x0 IMER ADDR CC TIMER NUM period period value IMER ADDR CC TIMER NUM gcontrol FUNC GO HLD_ CLKSRC endif Analog Interface Peripherals and Applications 8 17 Burr Brown DSP101 2 and DSP201 2 Interface to TMS320C3x Example 8 3 General Macro Definitions KK KK Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Kk KC KC Ck Ck Ck Ck Ck kk kk kk kk kc ko
261. RO REGISTERS MODIFIED RO R1 R2 SP REGISTER CONTAINING RESULT RO CYCLES 25 WORST CASE WORDS 16 global AXPND AXPND XOR D5H RO Invert even bits LDI RO R1 AND OFH R1 Isolate quantization bin LSH 1 RL LDI RO R2 Store for bit sign LSH 4 R0 AND 7 R0 Isolate segment cod BZ SKIP1 SUBI 1 R0 ADDI 32 R1 Create 1xxxxl SKIP1 ADDI 1 R1 OR Oxxxxl LSH3 RO R1 RO Shift and put result in RO TSTB 80H R2 E Test sign bit RETSZ NEGI RO Negate if a negative number RETS 6 6 FIR IIR and Adaptive Filters 6 2 FIR IIR and Adaptive Filters 6 2 1 Figure 6 1 FIR Filters Digital filters are a common requirement for DSPs There are two types of digi tal filters finite impulse response FIR and infinite impulse response IIR Both of these types can have either fixed or adaptable coefficients This sec tion presents the fixed coefficient filters first followed by the adaptive filters Ifthe FIR filter has an impulse response h 0 h 1 h N 1 and x n repre sents the input of the filter at time n the output y n at time n is given by this equation y n h 0 x n h 1 x n 1 h N 1 x n N 1 Two features of the C3x that facilitate the implementation of the FIR filters are parallel multiply add operations and circular addressing The former permits the performance of a multiplication and an addition in a single machine cycle whi
262. SER 1 ARO0 LDI ARO 12 RO kk ck Ck Sk ck CK ck KKK KK KKK KKK KKK KK ck Ck ck ck ck ck KKK KKK KKK KK KKK KKK KK KKK KKK KKK KK KKK ck ko kc KKK KKK KK get control value and write to serial port while branching to end of ISR and set first_half flag to TRUE EDI _data control 1 RO BD FIN S STI RO ARO 8 LDI 1 R0 STI RO _first_half This the second half of the transmission KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK FRST_HALF push remaining registers PUSH R1 PUSHF R1 PUSH AR1 PUSH TRO 8 42 CS4215 Interface to the TMS320C3x Example 8 11 C int asm Continued Ck Ck ck ck KKK KK kk KKK KKK KKK KKK KKK KK KK set first_half flag to FALSE
263. STI LSH ADDI STI SUBI LSH TEMP QTEMP ARO STORE AR1 ARO RO RO AR1 ARO RO RO AR1 ARO RO RO AR1 ARO RO RO AR1 FFTSIZ FFTSIZ RO FFTSIZ IRO FFTSIZ IR1 0 AR7 AR7 STAG 1 IRO 2 IR1 1 AR7 AR7 RPTCNT AR7 IEINDX 2 R0 2 R0 RO JT 2 R0 1 RO a OUTER LOOP LOOP LDI ADDI ADDI ADDI LDI SUBI INPUT ARO RO ARO AR1 RO AR1 AR2 RO AR2 AR3 RPTCNT RC 1 RC FFT size LOG4 FFTSIZ Sine cosine table bas Area with input data to process FFT stage Repeat counter IE index for sine cosine Secondtloop count JT counter in program P 117 IA1 index in program P 117 Command to load data page counter Xfer data from one memory to the other Command to load data page pointer STAGE holds the current stage number IRO 2 N1 because of real imag IRI N 4 pointer for SIN COS table Init repeat counter of first loop Init IE index JT RO 2 2 ARO points to AR1 points to AR2 points to AR3 points to RC should be one less than desired DSP Algorithms 6 37 Fast Fourier Transforms FFTs Example 6 15 Complex Radix 4 DIF FFT Continued FIRST LOOP RPTB BLK1 ADDF ARO AR2 R1 ADDF ADDF S i NANNPNNNNNNN PWN PPE i ce nr w tz UBF ADDF BLK1 STF AR3 AR1 R3 R3 R1 R6 AR2 AR0 R4 R6 ARO R3 R1 AR2
264. Start computing SFFT at this bin BIN END set 96 End computing SFFT at this bin ANGLE Set 90 0 Filter reconstruction angle degrees SPECT EN set 1 Enable spectrum analyzer output RATE set 2 Write display points RATE times each TIMO prd set 2 AIC reference clock is TIMO TA Set 6 DAC setup TB Set 25 RA Set 10 ADC setup RB Set 15 H PARAMETERS BELOW THIS LINE ARE COMPUTED FROM THE INFORMATION ABOVE THERE IS NO NEED TO MODIFY ANYTHING BELOW THIS POINT FK BIN LEN set BIN END BIN START Filter length in bins SFFTBINS Sset BIN LEN 1 H N Set SFFTSIZE N used as shorthand for SFFTSIZE TR Set 0 Real twiddle offset in each cell TI Set I Imag DR Set 0 Real data offset in each cell DI Set T Imag RIBINSIZE set 2 Size of R I element pair pi Set 3 14159265 Useful in making apple pie wW set 2 0 pi N angle F 2 pi Fs OVM Set 0x80 Use overflow mode to saturate results 6 94 Sliding FFT Example 6 18 SFFT ASM Continued If the input parameters won t work generate a descriptive error for the user letting them know what to look for and maybe fix i if BIN_LEN lt 1 APP MESSAGE Calculated BIN_LEN must be gt 1 endif if SFFIBINS 4 SFFTSIZE gt 0xE40 0x800 APP MESSAGE The Fbin and data storage buffers are too big for
265. TEXAS INSTRUMENTS TMS320C3x General Purpose Applications User s Guide 1998 Digital Signal Processing Solutions 3 TEXAS INSTRUMENTS Printed in U S A January 1998 SPRU194 SDS TMS320C3x General Purpose User s ip Guide Applications 1998 TMS320C3x General Purpose Applications User s Guide Literature Number SPRU194 y 1998 43 Texas ds INSTRUMENTS PM am TEE IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice and advises its customers to obtain the latest version of relevant information to verify before placing orders that the information being relied on is current Tl warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Certain applications using semiconductor products may involve potential risks of death personal injury or severe property or environmental damage Critical Applications TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED INTENDED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS DEVICES O
266. TSIZ R7 R7 N2 LDI 1 AR7 z Initialize repeat counter gt of first loop LDI 1 AR5 Initialize IE index AR5 IE DSP Algorithms 6 31 Fast Fourier Transforms FFTs Example 6 13 Complex Radix 2 DIF FFT Continued MAIN INNER LOOP OUTER LOOP LOOP NOP AR6 1 LDI INPUT ARO ADDI R7 ARO AR2 LDI AR7 RC SUBI 1 RC FIRST LOOP RPTB BLK1 ADDF ARO AR2 RO0 SUBF AR2 ARO R1 ADDF AR2 ARO R2 SUBF AR2 ARO R3 STF R2 AR0 STF R3 AR2 BLK1 STF RO ARO IRO HI STF R1 AR2 IRO IF THIS IS THE LAST STAGE YOU AR CMPI LOGFFT AR6 BZD END LDI 2 AR1 LDI QSINTAB ARA INLOP ADDI AR5 AR4 LDI AR1 ARO ADDI 2 AR1 ADDI INPUT ARO ADDI R7 ARO AR2 LDI AR7 RC SUBI 1 RC LDF AR4 R6 SECOND LOOP RPTB BLK2 SUBF AR2 ARO R2 SUBF AR2 ARO R1 MPYF R2 R6 RO ADDF AR2 AR0 R3 MPYF R1 AR4 IR1 R3 HI STF R3 ARO SUBF RO R3 R4 MPYF R1 R6 RO Current FFT stage ARO points to X I AR2 points to X L RC should be one less than desired RO X I X L R1 X 1I X L R2 Y I Y L R3 Y 1I Y L Y I R2 and Y L R3 X I RO and X L R1 and ARO 2 ARO 2 2 n DONE Init loop counter for B inner loop Initialize IA index AR4 H IA IA IE ARA points to 7 cosine TA Increment inner loop counter X
267. The internal memory is filled with Os O O O O O L How to Initialize the Processor Example 1 1 TMS320C3x Processor Initialization TITLE PROCESSOR INITIALIZATION global RESET INIT BEGIN global INTO INT1 INT2 INT3 global ISRO ISR1 1SR2 ISR3 global DINT DMA global INTO TINT1 XINTO RINTO XINT1 RINT1 global IMEO TIME1 XMTO RCVO XMT1 RCV1 global RAPO TRAP1 TRAP2 TRPO TRP1 TRP2 PROCESSOR INITIALIZATION FOR THE TMS320C3x m RESE AND INTERRUPT VECTOR SPECIFICATION THIS ARRANGEMENT ASSUMES HAT DURING LINKING THE FOLLOWING K TEXT SEGMENT WILL BE PLACED TO START AT MEMORY LOCATION 0 sect init Named section RESET word INIT RSt load address INIT to PC INTO word ISRO INTOt loads address ISRO to PC INT1 word ISR1 INT1t loads address ISR1 to PC INT2 word ISR2 INT2t loads address ISR2 to PC INT3 word ISR3 INT3 loads address ISR3 to PC XINTO word XMTO H Serial port 0 transmit interrupt processing RINTO word RCVO Serial port 0 receive interrupt processing XINT1 word XMT1 F Serial port 1 transmit interrupt processing RINT1 word RCV1 r Serial port 1 receive
268. The series resonant frequency corresponds to the natu ral mechanical vibration frequency of the crystal The parallel resonant fre quency is basically an electrical measurement phenomenon that results from the resonance between Ly and Coin the electrical model of the crystal and does not occur naturally Consequently all crystal oscillators operate at or near their series resonant frequency Figure 9 3 Impedance Characteristics of Crystal Impedance Frequency Notes 1 fs series resonant frequency 2 fp parallel resonant frequency Clock Oscillator and Ceramic Resonators 9 5 Quariz Crystal and Ceramic Resonators The graph in Figure 9 3 illustrates the behavior of the magnitude of the imped ance ofthe crystal butthe crystal s phase response is also important in oscilla tor design Figure 9 4 shows the reactance of the crystal with frequency The reactance and consequently the phase is 0 at the series resonant frequency fs because at this frequency the reactances of Lx and C cancel each other At this frequency the total impedance of the crystal is equal to the resistance Ry Figure 9 4 Reactance Characteristics of Crystal Frequency Reactance e Notes 1 fs series resonant frequency 2 fp parallel resonant frequency Below f the crystal appears capacitive negative reactance Between fs and fp the crystal appears inductive positive reactance and above f the crystal appear
269. Vus Hq ze ol od eyes seop n uolsleAuoo XUL S 9OA diuo uO eu1uloJj ejqe1100g ay do jo4uoo is E Buake s l3SaH ol opoo Jepeo 100q diuo uo 9euspueH t POE dsa eui semoexe dsq eui ZEI0ZESWL 2 yy i S MAIOVI 04X LAX a uodo 42 4exurT UO suogeaiunuiuo snouo4gou sy Duisf ISOH Woy 100g oJnDi Q i h h 4 106 TMS320C30 Addressing up to 68 Gigawords 4 9 TMS320C30 Addressing up to 68 Gigawords The C30 primary bus has 24 address lines which allow addressing up to 16 megawords of memory The C30 expansion bus has 13 address lines addressing 8K words These two busses expansion bus address lines XA 12 0 and the primary lines A 23 0 can be used simultaneously to extend the address to 36 bits This is accomplished by using the feature of the C3x family that holds the past address bits on an external bus until a new external access occurs That means the address bus works as a latch Figure 4 47 shows how these two busses are combined together The following parallel instruction accomplishes this task STI Rx ARn address MSTRB while loading a value from STRB memory LDI ARp Rq where Rx and Rq designate registers RO to R7 but not the same register ARn and ARp designate auxiliary registers ARO to AR7 but notthe same register Tr eee AAAAAAAAAALILLLLLLIL HL L L L O LUAAOAOCCCZqT Note ARn contains the 8 Mword segment address plus 800000h ARp contains the address within the 8 Mword segme
270. XF PINS asm LDI 00h IOF endif ifndef CL INT FL REG define CL INT FL REG asm LDI Oh IF endif ifndef EN GLOBAL INTS define EN GLOBAL INTS asm OR 2000h ST endif ifndef E SER PORT XMT I 0 define EN_SER_PORT_XMT_I O asm OR 10h IE endif ifndef SER PORT RCV INT O0 define SER PORT RCV INT 0 asm OR 20h IE endif ifndef E SER PORT XMT I 1 define PORT XMT I 1 asm OR 40h IE endif E ca al ifndef E SER PORT RCV INT 1 define SER PORT RCV INT 1 asm OR 80h IE endif zl ifndef ENABLE CACH define ENABLE CACHE asm OR 800h ST endif endif ifndef GENERAL Analog Interface Peripherals and Applications 8 19 Burr Brown DSP101 2 and DSP201 2 Interface to TMS320C3x Example 8 4 Common Driver Header File J KOKCKCECK Ck Ck Ck Ck Ck Ck Ck Ck ECKE A I A KC I Ck Ck Ck A kk kk kk kk kc ke ke ko ke ke ke ke ke ke ke eoe ee e e ee kx x f fre COMMDRVR H Js Es TMS320C3x COMMOM DRIVER HEADER FILE KK Ck Ck kk Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck kk Kk kk kk kk kk kk kk ke ke ke ko ke ke ke ke ke e ke e e e e x x f include lt c30_per h gt J KCKCKOECK KK Ck A Kk I A I I A I IA I A A I IA I kc ko A IA ke ke ke ke ke ke e ke e ee ee e e kx x f COMMON STRUCTURES KK KK kk Ck kk Ck Ck Ck kk Ek Ck Ck kk Ck Ck Ck Ck Ck
271. XGO L HAS BE EN T ES ADDR SE R NUM s rxt period bit x period ADDR SER NUM gcon BUILD CONTROL WORDS trol XL XINT XCLKSRCE RLEN 32 D DXFUNC DRFUNC EN 32 XCP_ 0x3 XFSM RINT FSXOUT RRESET ALL BITS temp intval temp control temp control temp control temp control temp control BUILD DAT data_control data_control data_control data_control data_control ARE 0 EXC EPT THOSE DEFIN ED OTH 7 ERWISE L 0 temp intval 1 0 st STE l bitval R EO MOD l bitval dfr l bitval xclk l bitval mckf l bitval pio 1 cry 3 TA CONTROL WORD _intval 0 l stereo 16 bitval l stereo 16 bitval l stereo 16 bitval l stereo 16 bitval data control l stereo 16 bitval stal lo le ro ovr ma data_control _intval 1 ON sample rate 0 ATT 0 ATT ON MATT 15 0 XRESET FSXFUNC FSRFUNC ard XCKCKCkCKCk kk kk kk kk kk kk kk kk kk kk kk kk kc ko ke ko ke ke ke ke ke ke ke ke ke ke e e e e e e e x XCLKSRC RESM ED ON A 50 MHz C30 8 62 Example 8 16 CS4215 c Continued CS4215 Interface to the TMS320C3x do UN R DCB_1 Write out control word until dcb bit is low out S T COD E
272. X_PORT 2 TRANSMIT CONTROL define R_PORT 3 RECEIVE CONTROL Rdefine X_DATA 8 TRANSMIT DATA xy define R DATA 12 RECEIVE DATA y Timer Vs TIMER BASE LOCATION yh volatile int timer 16 volatile int 16 0x808020 define T COUNTER 4 define T PERIOD 8 Analog Interface Peripherals and Applications 8 37 TLC320AD58 Interface to the TMS320C3x Example 8 9 TMS320C3x Interrupt Vector Table Listing J R JE f Filename vectors h Defines interrupt vectors and trap vectors for C programs f Usage include vectors h Modifications If you add interrupt service routines modify xf this file to insert the vectors at the proper location in the vector table aa asm global c int00 Hy asm global _c_int08 ya asm Sect V vectorsV d asm RESET WOrd c int00 external RESET Ws asm INTO word _c_int99 external INTO yd asmi INT1 Word c int99 external INT1 yos asm INT2 Word c int99 external INT2 yg asm INT3 word c int99 external INT3 udi asm XINTO word c int99 Serial port 0 XMT asm RINTO word c int99 Serial port 0 RCV asm XINT1 word c int99 Serial port 1 XMT asm RINT1 word c int08 Serial port 1 RCV asm TINTO word c int99 Timer 0 oss asm TINT1 Word
273. Y DD Logical AND or OR of the two When enabled internally generated wait states affect all external cycles regardless of the address accessed If different numbers of wait states are required for various external devices the external RDY input may be used for wait state generation to specific system requirements If the logical AND electrical OR of the wait count and external ready signals is selected the latter of the two signals controls the internal ready signal Both signals must occur Accordingly external ready control must be implemented for each wait state device and the wait count ready signal must be enabled If the logical OR or electrical AND since the signals are low true of the exter nal and internal wait count ready signals is selected the earlier of the two sig nals generates a ready condition and allows the cycle to be completed Both signals do not need to be present ORing the Ready Signals Performing an OR of the two ready signals can implement wait states for de vices that require a greater number of wait states than are implemented with external logic up to seven This is useful for example if a system contains both fast and slow devices In this case fast devices can externally generate a ready signal with a minimum of logic and slow devices can use the internal wait counter for larger numbers of wait states When fast devices are ac cessed the external hardware responds promptly with a ready sig
274. Y John Wiley and Sons Inc 1990 Digital Signal Processing Applications with the TMS320 Family Vol l Texas Instruments 1986 Prentice Hall Inc 1987 Digital Signal Processing Applications with the TMS320 Family Vol Il Texas Instruments 1990 Prentice Hall Inc 1990 Digital Signal Processing Applications with the TMS320 Family Vol Ill Texas Instruments 1990 Prentice Hall Inc 1990 Gold Bernard and Rader C M Digital Processing of Signals New York NY McGraw Hill Company Inc 1969 Hamming R W Digital Filters Englewood Cliffs NJ Prentice Hall Inc 1977 Hutchins B and Parks T A Digital Signal Processing Laboratory Using the TMS320C25 Englewood Cliffs NJ Prentice Hall Inc 1990 IEEE ASSP DSP Committee Editor Programs for Digital Signal Processing New York NY IEEE Press 1979 Read This First ix Heferences Jackson Leland B Digital Filters and Signal Processing Hingham MA Kluwer Academic Publishers 1986 Jones D L and Parks T W A Digital Signal Processing Laboratory Using the TMS32010 Englewood Cliffs NJ Prentice Hall Inc 1987 Lim Jae and Oppenheim Alan V Editors Advanced Topics in Signal Processing Englewood Cliffs NJ Prentice Hall Inc 1988 Morris L Robert Digital Signal Processing Software Ottawa Canada Carleton University 1983 Oppenheim Alan V Editor Applications of Digital Signal Processing Englewood Cliffs NJ Prenti
275. a pragma DATA SECTION Consider the example described in Meth od A The following code segment uses the DATA SECTION pragma to declare a 32 word array tapDelay that is placed separate from the other global and static variables File TEST C pragma DATA SECTION tapDelay tapdelayline int tapDelay 32 void main void int ij tapDelay i 0 End of file 5 14 Linking C Data Objects Separate From the bss Section 2 Inthelinker command file use the section name tapdelayline to place the array tapDelay in RAM block 0 Separate it from the other global and static variables that are in the bss section as follows File TEST CMD test obj array obj MEMORY EXTO origin 0x100 len 0x3f00 RAMO origin 0x809800 len 0x400 SECTIONS bss EE EXTO tapdelayline RAMO End of file Method B is available in the floating point DSP C compiler version 4 60 or greater It is described in the TMS320 Floating Point DSP Code Generation Tools Release 4 70 Getting Started Guide Programming Tips 5 15 Interrupts in C 5 8 5 16 Interrupts in C To use interrupts in C you must write an interrupt service routine ISR initial ize the interrupt vector table and link these parts with the linker command file These steps are described below Step 1 Step 2 Write a C language interrupt service routine ISR The C compiler r
276. accesses the processor is always ready unless a wait state is required Control of full speed devices is straightforward no action is necessary be cause the ready signal is always active unless otherwise programmed Devices requiring wait states however must drive ready high fast enough to meet the input timing requirements Then after an appropriate delay a ready indication must be generated This can be difficult in many circum stances because wait state devices are inherently slow and often require complex select decoding If RDYishigh between accesses the processor enters a wait state unless a ready indication is generated Zero wait state devices which tend to be inherently fast can usually re spond immediately with a ready indication Wait state devices can delay their select signals to generate a ready indication Typically this approach results in the most efficient implementation of ready control logic Figure 4 6 shows a circuit of this type which can be used to generate Zero one or two wait states for multiple devices in a system Memory Interfacing 4 13 Wait States and Ready Signal Generation Figure 4 6 Circuit for Generation of Zero One or Two Wait States for Multiple Devices Other 2 wait state devices ER H1 Reset 74ALS138 A C30 J address bus STRB Device selects V Other 1 74A832
277. acturers listed in Table 9 2 These circuits were tested at room tem perature and verified to operate correctly within the recommended range of Vpp 4 75 5 25 V Table 9 2 Oscillator Solutions by Frequency Frequency Mode Type Supplier Part Number C4 Co Rg L 40 MHz Fundamental Crystal SaRonix HFX series crystals 10pF 0 33f 40 MHz Third overtone Crystal Anderson 011 668 04663 10pF 0 331 33 gH 50 MHz Fundamental Crystal SaRonix HFX series crystals 10pF 0O 33f 50 MHz Third overtone Crystal SaRonix SRX5223 10pF 0 331 3 3uH 60 MHz Third overtone Crystal Anderson 011 668 04725 10pF 0 33t 3 3 uH t Whenthese circuits are operated without Rg they yield crystal power dissipation measurements near 1 mW Differences in circuit and crystal parameters can cause the power dissipation in the crystal to slightly exceed 1 mW If crystal power dissipation is criti cal itis recommended that 33 O of Rd be added to limit the crystal power dissipation or obtain crystals with power dissipation ratings higher than 1 mW When operated with Rd 33 Q each of the circuits shown exhibited less than 1 mW crystal power dis sipation The following circuits are used for ceramic resonators and fundamental mode crystal resonators The circuit in Figure 9 17 is used for all circuits marked fun damental mode in Table 9 2 The circuit in Figure 9 18 is used for all circuits marked third overtone mode in Table 9 2 Crystals used in these circuits must
278. address that appears at the C32 address pins The valid ranges of the logical memory map that the program instructions can reference are determined by DD The external memory available in the system D The manner in which the external memory address pins are matched with the C32 address pins which depends on physical memory width The contents of the STRBO and STRB1 registers which define physical memory width and the data size The logical memory map shown in Figure 4 15 always contains 32 bit data as far as the CPU is concerned It is only when the data passes through the memory interface block that the data size can actually change to 8 or 16 bits as directed by the appropriate strobe control register For example when the processor reads a byte eight bits from external memory the 8 bit data is sign extended or padded with Os as it passes through the memory interface so that it becomes 32 bit data inside the C32 Likewise when the processor writes the contents of a 32 bit register to 16 bit wide external memory the internal 32 bit data is truncated to 16 bits as it passes through the memory interface The dashed lines inside the logical memory map in Figure 4 15 show the inter nal 32 bit representation of the external data that has a physical size of 8 or 16 bits Figure 4 15 explains logical physical addresses and other terms related to the C32 memory interface Memory Interfacing 4 33 v v Figure 4 15 D
279. ain of greater than 1 then the circuit meets both oscillation conditions and oscillates This explanation however is unrealistic because it ignores too many aspects of real world circuit effects Figure 9 8 illustrates a more typical example ofthe circuit behavior In this case the inverting amplifier has some phase delay which causes it to produce a phase shift somewhat longer than 180 depend ing on the frequency of operation If oscillation is to occur the passive compo nents are forced to compensate for this phase difference The only way the im pedance of the load capacitances can change is when the frequency of opera tion changes The frequency of operation tends to move above the series res onant frequency lowering the impedance of the load capacitances and raising the impedance ofthe crystal as it goes from being purely resistive to being both resistive and inductive see Figure 9 2 c on page 9 5 When the frequency changes such that the loop phase shift once again equals 360 the circuit os cillates atthe higher frequency For this reason most Pierce circuits operate 5 40 ppm above the series resonant frequency This explanation clearly il lustrates the circuit s actual behavior and explains why a parallel resonant crystal always operates slightly above the series resonant frequency Figure 9 8 Pierce Circuit Actual Operation R4 Crystal v o Inverting amplifier Cy 7S Co
280. ake space for the sign ADDI AR1 3 RO Add the negative sign RETS Logical and Arithmetic Operations 3 29 3 30 Chapter 4 Memory Interfacing The C3x interfaces connect to many device types Each of these interfaces is tailored to a particular family of devices Topic Page 4 1 System Configuration see eee eee e l 4 2 428 Externallinterfaces s 1 0 EE REEET CERTI ITE 4 3 4 3 Primary BUs Interface 1 0 1 19 1 5 1 1 0 2 2 2 1 2 2 stele 4 4 4 4 Zero Wait State Interface to Static RAMs 4 5 4 5 Wait States and Ready Signal Generation 4 10 4 6 Interfacing Memory to the TMS320C32 DSP 4 21 4 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface 0cce eee e eee eee e eens 4 67 4 8 Booting a TMS320C32 Target System in a C Environment 4 86 4 9 TMS320C30 Addressing up to 68 Gigawords 4 107 System Configuration 4 1 System Configuration The devices that can be interfaced to the C3x include memory DMA devices parallel and serial peripherals and I O devices Figure 4 1 illustrates a typical configuration of a C3x system with various external devices and the interfaces to which they are connected Figure 4 1 Possible System Configurations 4 2 Memory Peripherals Peripherals DMA devices TMS320C3x Memory
281. al variables and statically allocated variables LI L O L Stack system stack used to pass function arguments and to allocate local function variables sysmem memory pool for dynamic allocation of 32 bit data sysm16 memory pool for dynamic allocation of 16 bit data sysm8 memory pool for dynamic allocation of 8 bit data oo O L user section section created using the Zpragma DATA SECTION di rective The following sections describe the C compiler s preprocessor pragma and modules in the runtime support library that support 8 and 16 bit memory pools The 32 bit memory pools are handled through the standard minit mal loc smalloc calloc realloc and free routines which operate on the sysmem section 4 7 1 1 DATA SECTION Pragma Directive 4 70 To support additional memory pools the C compiler uses a data section prag ma directive This directive instructs the C compiler to allocate space for sym bol namein the section specified by section name of size symbol size See the TMS320 Floating Point DSP Optimizing C Compiler User s Guide for addi tional information The syntax for DATA SECTION is as follows pragma DATA SECTION symbol name section name type symbol name For example define a new section called mydata as an array of 1K integer values in the following manner pragma DATA SECTION dataBuf mydata int dataBuf 1024 How TMS320 Tools Interact With the TMS320C32 s Enhance
282. alent assembly code LDP 880001h DP LDI 880001h RO C A B LDP 9 1002h DP LDI 1002h R1 LDP 8A0003 DP ps STI R1 8A0003 STRB bss big c RTS library MALLOC Dynamic memory assigned at execution time e Maximum size 64M words e Fast execution e Best for big arrays one time overhead MALLOC call TMS320C32 Memory C statement Equivalent assembly code LDI ARO RO C A B LDI AR1 R1 STRB SYySmem ADDI RO R1 STI R1 AR2 text C 2 Memory Access for C Programs Figure C 2 shows how to use MALLOC to allocate a block of 32 bit memory at run time In this example MALLOC is called three times to allocate memory from the heap After each MALLOC call the newly allocated block of memory can be used by other program functions by using the pointer BUFFER_32 The size of the heap representing all of dynamically allocated memory is defined in the linker command file by using the HEAP keyword followed by the size of the block Any portion of the heap allocated with the MALLOC call is added to the SYSMEM section The SECTIONS directive can then be used to map the dynamically allocated sections to an address range in the physical memory For more information see the TMS320C3x C4x Assembly Language Tools User s Guide or TMS320C3x C4x Optimizing C Compiler User s Guide Dynamically allocated memory provide
283. alizes a 128 element array to 0 The DMA sends an interrupt to the CPU after the transfer is completed This program assumes previous initialization of the CPU interrupt vector table specifically the DMA to CPU interrupt The ST and IE registers are initialized for interrupt processing In Example 7 2 the serial port O is initialized to receive 32 bit data words with an internally generated receive bit clock and a bit transfer rate of 8H1 cycles bit This program assumes previous initialization of the CPU interrupt vector table specifically the DMA to CPU interrupt The serial port interrupt directly affects only the DMA therefore no CPU serial port interrupt vector setting is required Programming the DMA Channel 7 5 DMA Assembly Programming Examples Example 7 2 DMA Transfer With Serial Port Receive Interrupt TITLE DMA TRANSFER WITH Sl GLOBAL START DATA DMA WORD 808000H CONTROL WORD 0D43H SOURCE WORD 80804CH DESTIN WORD _ARRAY COUNT WORD 128 IEVAL WORD 002000400H RESET1 WORD OD40H BSS _ARRAY 128 START LDP DMA DMA INITIALIZATION LDI DMA ARO LDI SPORT AR1 LDI RESET RO STI RO AR1 4 LDI RESET1 RO STI RO ARO LDI SPRESET RO STI RO AR1 LDI SOURCE RO STI RO ARO 4 LDI DESTIN RO STI RO ARO 6 LDI COUNT RO STI RO ARO 8 OR IEVAL
284. ank Two Strobes 32 Bit Wide Memory Design Examples This section describes how to use two strobes in interfacing the C32 to a single physical bank of memory Such configuration enables the access to 32 bit pro grams and to two differently sized portions of data out of the same bank of memory with no speed penalty This feature is implemented by internally AND ing STRBO and STRB1 and outputting the combined strobes on STRBO a total of four lines The one bank two strobes memory configuration is useful in sys tems in which for example the program requiring 32 bit instruction words for maximum execution speed operates on data that needs only 16 bits of preci sion see Figure 4 27 on page 4 56 Figure 4 24 is the schematic diagram of a 32 bit wide external memory con figuration arranged as one bank with two separate logical control strobes shar ing the same STRBO physical signal lines The four STRBO signals are as signed to the chip select pins of four 32K x 8 15 ns SRAMS one signal per chip For the 60 MHz version of the C32 the 15 ns SRAMs operate at zero wait states For slower devices additional software wait states can be pro grammed in the appropriate fields of the strobe control registers Because the total memory width is 32 bits there is no mismatch between the processor s and the memory s address pins Therefore the C32 pin AO is matched with memory pin AO A1 is matched with A1 and so on As mentioned ear
285. apped to STRBO and STRB1 are configured by hardwiring the PRGW program memory width se lect pin There is no need to use the data size fields because all program fetches apply only to instruction words that are 32 bits wide The memory width field of the strobe control register is useless at reset when the processor is fetching the reset vector from memory At that point the strobe control register is always configured in the same way but different systems can have different memory widths The PRGW pin indicates to the memory interface whether the program memory is 16 or 32 bits wide Program memory that is 8 bits wide is not supported because four cycles per instruction degrade the performance too much for it to be useful for most applications Buioejuaju AIOwayy c Figure 4 10 STRBO and STRB1 Control Registers and the PRGW Pin Applies only to data access cycles to from memory addresses mapped to STRBO TMS320C32 enhanced memory interface 16 bit program memory VCC Applies only to program fetch cycles from memory addresses mapped to STRBO STRB1 2 32 bit program memory Applies only to data access cycles to from memory addresses mapped to STRBO STRB Memory Data config width size STRBO control register IOSTRB cycles PRGW pin are always 32 bits wide data access or program fetch Memory Data width size Note
286. are root of a number v 1 SQRT v To derive SQRT v mul tiply this result by v Since in many applications division by the square root of a number is desirable the output of the algorithm saves the effort to compute the inverse of the square root At the ith iteration the estimate x i of 1 SQRT v is computed from v and the previous estimate x i 1 according to this formula x i x i 1 x 1 5 v 2 x x i 1 x x i 1 To start the operation an initial estimate x 0 is needed If v a x 2 a good initial estimate is x 0 10x 2 amp 2 Example 3 7 shows the implementation of this algorithm on the C3x where the iteration is applied five times Both accuracy and speed are affected by the number of iterations If you want more accuracy and less speed increase the number of iterations If you want less accuracy and more speed reduce the number of iterations Logical and Arithmetic Operations 3 13 Square Root Computation Example 3 7 Square Root of a Floating Point Number TITLE SQUARE ROOT OF A FLOATINGEPOINT NUMBER SUBROUTINE SQRT THE FLOATING POINT NUMBER v IS STORED IN RO AFTER TH COMPUTATION IS COMPLETED SQRT v IS ALSO STORED IN RO NOTE THAT THE ALGORITHM ACTUALLY COMPUTES 1 SQRT v TYPICAL CALLING SEQUENCE LDF v RO CALL SORT ARGUMEN ASSIGNME
287. ary bus is always greater than or equal to 20 mA This ensures thatthe correcttotal current value is obtained when summing external bus fac tors Once a current value has been obtained from Figure 12 4 or Figure 12 5 this value can if necessary be scaled by a data dependency fac tor as described in section 12 3 3 on page 12 14 This scaled value is then summed along with several other current values to determine the total supply current Current Requirement for Output Driver Circuitry 12 3 2 Expansion Bus Current Currents from the primary and expansion buses differ slightly for several rea sons including the fact that the expansion bus has 11 fewer address outputs than the primary bus 13 rather than 24 This overall current contribution is slightly lower from the expansion bus than from the primary bus Determining the expansion bus current uses the same premise as determining the primary bus current Figure 12 6 and Figure 12 7 show the same current relationships for the expansion bus as Figure 12 4 and Figure 12 5 show for the primary bus The total external buses current contributions must be posi tive if the primary bus is not used and the expansion bus is not used much the minimum current contribution from the expansion bus is 30 mA The cur rent values obtained from these figures must be scaled by a data dependency factor as described in section 12 3 3 on page 12 14 Figure 12 6 Expansion Bus Current Versus Tran
288. at conversion complete C3x to IEEE format conversion fast C3x to IEEE format conversion complete FIR filter IIR filter one biquad IIR filter N 1 biquads LMS adaptive FIR filter Matrix vector multiplication Vector dot product Vector maximum Forward LPC lattic filter Inverse LPC lattice filter u law A law compression u law A law expansion Words 31 38 2 24 12 33 14 24 5 16 10 16 18 13 15 Cycles 31 46 24 19 10 27 6 N 7 13 6N 13 3N 2 10K K N 1 N 4 2 3N 5 3P 6 3P 16 18 16 21 TMS320C3x Benchmarks Table 6 2 TMS320C3x FFT Timing Benchmarks Assumes Data On Chip and No Bit Reversing Number of Points 64 128 256 512 1024 512 1024 2048 4096 Radix 2 Complex 1481 3445 7865 17 709 17 709 C31 42 210 C32 39 600 C30 40 100 C31 94 519 C32 25 688 C32 64 781 C32 11 611 C30 117 400 C31 280 800 C30 283 600 C31 Radix 4 Complex 2050 10400 50 670 Number of CPU Clock Cycles Radix 2 Real 791 1746 3925 8840 19 820 Radix 2 Real Inverse 1064 2369 5282 11731 25 900 These benchmarks include C overhead they represent the number of cycles between the standard C compiler main and exit labels These benchmarks do not include the final bit reversing stage If bit reversing is required it is implemented in a serial fashion in off chip memory DSP Algorithms
289. atement For example asm 7 Sect vectors A C function that is an ISR Step 3 Interrupts in C Link the interrupt service routine ISR and the initialized interrupt vector table with the linker command file The linker command file provides the mechanism for including the vectors asm object and the ints c object file name mylink cmd vectors obj ints obj The MEMORY section needs to identify the location of the int vec tors MEMORY VECTORS origin 0h length 40h The SECTIONS section needs to map the user defined section called vectors to the memory location SECTIONS Vectors gt VECTORS Programming Tips 5 17 5 18 Chapter 6 DSP Algorithms Certain features of the C3x architecture and instruction set facilitate the solu tion of numerically intensive problems This chapter presents examples of applications using these features such as companding filtering fast Fourier transforms FFTs and matrix arithmetic Topic Page 6 1 Companding 6 2 6 2 FIR IIR and Adaptive Filters 6 7 6 3 Lattice Filters 6 18 6 4 Matrix Vector Multiplication 6 24 6 5 Vector Maximum Search 6 26 6 6 Fast Fourier Transforms FFTs 6 2
290. ation pin 2 F13 126 EMU3 Emulation pin 3 E14 123 H3 C3x H3 A1 82 Presence detect Indicates that the emulation cable is connected and that the target is powered up PD must be tied to Vcc in the PD target system 10 2 Emulator Cable Pod Logic 10 2 Emulator Cable Pod Logic Figure 10 2 shows a portion of logic in the emulator cable pod The 33 Q resis tors have been added to the EMUO EMU1 and EMU2 lines to minimize cable reflections Figure 10 2 Emulator Cable Pod Interface 74LVT240 A EMU1 pin 1 33 Q EMUO pin 2 33 Q EMU2 pin 3 5V A V 180 Q 2700 74F175 a EMU3 pin 9 i 5VA ow 180 Q 270 Q JP2 74AS1004 PD Vcc pin 7 P 100 Q Q GND pins 2 4 6 8 10 12 iis pins 2 4 6 8 10 12 3 H3 pin 11 XDS510 Emulator Design Considerations 10 3 MPSD Emulator Cable Signal Timing 10 3 MPSD Emulator Cable Signal Timing Figure 10 3 shows the signal timings for the emulator cable pod Table 10 2 defines the timing parameters The timing parameters are calculated from val ues specified in the standard data sheets for the emulator and cable pod and are for reference only Texas Instruments does not test or guarantee these tim ings Figure 10 3 Emulator Cable Pod Timings H3 A A _ K 2 h 3 EMU1 EMU2 le 4 3 6 EMU3 X X Table 10 2 Emulator Cable Pod Timing Parameters
291. ation registers and transfer counters The DMA chan nel can be easily programmed in C or in assembly language The C30 and C31 coprocessors each have one DMA channel while the C32 coprocessor has two DMA channels Each channel of the C32 DMA channel is similar to those of the C30 and C31 with the addition of user configurable priorities This chapter provides examples for programming the DMA for the C3x Topic Page 7 1 Hints for DMA Programming eese RI 7 2 7 2 When a DMA Channel Finishes a Transfer 7 3 7 3 DMA Assembly Programming Examples e 7 4 7 1 Hints for DMA Programming 7 1 Hints for DMA Programming 7 2 The Peripherals chapter of the TMS320C3x User s Guide describes the DMA channel and its operation in detail Use the following techniques to program your DMA more efficiently and to avoid unexpected results DD Resetthe DMA register before starting it This clears any previously latched interrupts that may no longer exist Lj After starting the DMA set the IE register to enable interrupts for sync transfer D Ifa conflict occurs when the CPU and DMA access the memory simulta neously on the C30 or C31 the CPU always prevails Carefully allocate the sections of the program in memory for faster execution If a CPU pro gram access conflicts with a DMA access enabling the cache helps if the program is located in external memory D
292. ay to visualize the SFFT is to consider that each new sample occurs at T 0 making each new sample all REAL in the frequency domain Then since the past summation is time shifted by one sample a vector rota tion proportional to the frequency is applied A schematic representation for an SFFT bin is shown in Figure 6 11 Figure 6 11 Frequency Bin Diagram Equivalent to an IIR Filter IN zA More bins N delay 7 d K2 K12 N d K1 x exp x Complex vector rotation rate Twiddle etc v Fbin OUT Where Vector rotation rate n th Freq 2 PI n N Fs K1 amp K2 force convergence see section 6 8 4 DSP Algorithms 6 83 Sliding FFT 6 8 4 Fbin Convergence and Stability One aspect of the SFFT is thatthere is afeedback loop which affects the stabil ity of the bin values This is similar to an IIR filter where in the Z domain a pole sites on the unit circle To maintain stability and keep the bin values from grow ing out of control the magnitude of the complex vector rotation twiddles must be setto slightly less than 1 placing the pole inside the unit circle This causes the impulse energy magnitude in each bin to decay exponentially towards zero By adding a stability factor by Nth bin rotation an impulse decays to K1N of its original magnitude To subtract the Nth oldest sample the Nth oldest sample is scaled by a second coefficient K2 K1N A side effect of the exp
293. b bw oe Db adea d ad 6 38 16 SFFT AGO Contents Contents 7 8 xviii Programming the DMA Channel i 7 1 Provides examples for programming on chip peripherals for the TMS320C3x 7 4 Hints for DMA Programming sen ei 7 2 7 2 When a DMA Channel Finishes a Transfer 0 7 3 7 3 DMA Assembly Programming Examples i 7 4 Analog Interface Peripherals and Applications 4 8 1 Describes the analog input output devices that interface to the C3x 8 1 Analog to Digital Converter Interface to the TMS320C30 Expansion Bus 8 2 8 2 Digital to Analog Converter Interface to the TMS320C30 Expansion Bus 8 6 8 3 Burr Brown DSP101 2 and DSP201 2 Interface to TMS320C3x 8 10 8 4 TLC32040 Interface to the TMS320C3x i 8 21 8 4 1 Resetting the Analog Interface Circuit i 8 21 8 4 2 Initializing the TMS320C31 Timer 0 8 22 8 4 3 Initializing the TMS320C31 Serial Port i 8 23 8 4 4 Initializing the AIC 5 8 24 85 TLC320AD58 Interface to the TMS320C3x i 8 30 8 6 CS4215 Interface to the TMS320C3x i 8 39 8 7 Software UART Emulator for the TMS320C3x i 8 66 84 1 HardWal6 sies Re bU eR na eA RM Raha Res anda aa Baw s RR SERES AURIS 8 66 8 7 2 Software 2 0 sese a 8 66 8 8 Hardware UART for TMS320C3x 0 sa 8 70 Clock Oscillator and Ceramic Resonators 200 cece eee eee eee 9 1 Provides general background on oscillators and resonators and their frequency characteristics 9 OSCOS eair de dtes m dece icr tete Gt dd Cath sat Ad
294. be parallel resonant with a series resistance of 40 ohms or less and must have a power dissipation rating of 1 mW or greater Figure 9 17 Fundamental Mode Circuit C3x LLL O PE 2 X2 CLKIN X1 Rd CE i 9 22 Oscillator Solutions for Common Frequencies Figure 9 18 Third Overtone Circuit Xo CLKIN Y E Clock Oscillator and Ceramic Resonators 9 23 9 24 Chapter 10 XDS510 Emulator Design Considerations This chapter explains the design requirements of the XDS510TM emulator and discusses the Extended Development System XDS cable manufacturing part number 2617698 0001 This cable is identified by a label on the cable pod marked JTAG3 5V and supports both standard 3 V and 5 V target system power inputs The term JTAG emulation as used in this book refers to TI scan based emula tion which is based on the IEEE 1149 1 standard Topic Page 10 1 Designing the MPSD Emulator Connector 12 Pin Header 10 2 1029Emulator Gable Podl ogic t ecg rr eI 10 3 10 3 MPSD Emulator Cable Signal Timing 10 4 10 4 Connections Between the Emulator and the Target System 10 5 10 5 Mechanical Dimensions for the 12 Pin Emulator Connector 10 8 10 6 Diagnostic Applications en 10 10 10 1 Designing the MPSD Emulator Connector 12 Pin Header 10 1 Designing the MPSD Emulator Connector 12 Pin Header The
295. bit CMOS static RAM with the OE control input tied low and a CS controlled write cycle Zero Wait State Interface to Static RAMs Figure 4 3 TMS320C3x Interface to Cypress Semiconductor s CY7C 186 CMOS SRAM 4 x CY7C186 25 Primary address bus 8 D15 D8 74AS04 Primary data bus D31 DO In this circuit the two chip select pins on the RAM are driven by the STRB and A23 pins which are ANDed together internally A23 locates the RAM at ad dresses 00000h through OSFFFh in external memory and STRB establishes the CS controlled write cycle The WE control input is then driven by the C3x R W signal The OE input is not used and is connected to ground Memory Interfacing 4 7 Zero Wait State Interface to Static RAMs The timing of read operations shown in Figure 4 4 is very straightforward because the two chip select inputs are driven directly The read access time of the circuit is the inverter propagation delay added to the RAM s chip select access time t4 to 2 5 25 30 ns This access time meets the C3x 33 s specified 30 ns read access time requirement Figure 4 4 Read Operations Timing H1 E CE amm o o CS1 STRB N CS2 N ke ty 4 k p During write operations shown in Figure 4 5 the RAM s outputs do not turn on at all because of the chip select controlled write cycles The chip select controlled write cycles are generated because R W goes active low before the
296. bits must match the bank 1 space Since no wait states are involved the RDY BANK 1 signal does not have to be synchronized with the H1 H3 clocks and therefore it can directly drive the RDY pin after being gated with its bank 2 bank 3 counterpart The STRBO BANK23 signal becomes active high if the three address de code bits match bank 2 or bank 3 address spaces while STRBO BO and or STRBO B1 are active low The STRBO BANK23 signal when high sets a high data state in a synchronous progression through a chain of four registers Depending on which point in the chain is tapped a RDY signal delay ranging from zero to three wait states can be achieved In this case both 1 wait state and 3 wait state taps assert the RDY B23YES signal to reflect bank 2 or bank 3 access Finally a 2 register circuit removes the trailing active low edge of the RDY B23YES signal by ORing it with RDY 23NOT see Figure 4 30 The resulting RDY_BANK23 is ANDed with its bank 1 counterpart to drive the RDY pin Interfacing Memory to the TMS320C32 DSP 2 0q
297. bits wide binary file ASCII file TMS320C32 DSP Grounding the MCBL MP pin while coming out of reset causes the processor to start operation in the microprocessor mode The CPU executes the C boot code to copy variables from cinit to bss section spaces SRAM File1 data bss section File2 data bss section 32 bits wide ueuiuoJiAu3 2 e ui Wa sXs jabiel ZEQOZESWL e Buljoog o co Figure 4 41 8 Bit EPROM Boot Using the On Chip Boot Loader Linker cr Option The hex conversion utility does the following m m Converts the binary COFF file to a standard format ASCII file that an EPROM programmer can understand Identifies the sections to be booted and adds extra control words to those sections to instruct the on chip boot loader TMS320C32 DSP The CPU executes the on chip boot loader code to copy the boot table from 8 bit EPROM to 32 bit SRAM The EPROM programmer burns the 8 bit EPROM device with the boot table consists of program opcodes initialized data plus Special control instructions for the boot loader Pd RESET On chi bootloader MCBL MP System Reset Vcc Depending on which INTx is low when RESET goes high boot load
298. buffer xmtd FALSE define INIT ARRAYS init arrays t buffer r buffer if XF NUM define RESET BB asm AND 2Fh IOF asm OR 20h IOF define UN RESET BB asm OR 60h IOF else define RESET BB asm AND OF2h IOF asm OR 2h IOF define UN RESET BB asm OR 6h IOF endif 8 12 Burr Brown DSP101 2 and DSP201 2 Interface to TMS320C3x Example 8 1 TMS320C3x BB DSP102 202 Driver Header File Continued TIMER PERIOD VALUES ARE BASED ON AN INPUT CLOCK OF 30 MHz define CD OxAA define DAT Ox9C define TIMER PERIOD CD define WAIT A for i 0 i lt A i J KCKCKCECK Ck kk RR kk a a A Ck Ck Ck Ck Ck Ck Ck A Ck Ck Ek kk Ck kk kk ke ke ke ko ke ke ke ke ke ke ke e e e e STRUCTURES x KK I KK Ck A I A IA A IA A I A I IA A A A A IA A IA ke ke ke ke ke ke ke ke e ee ee e x f typedef union unsigned int _intval struct signed int chan0 16 signed int chanl 16 bitval BB CASC WORD KK KKK Ck Ck Ck Ck kk Ck Ck Ck Ck Kk Ck Ck Ck Ck Ck Ck Ck Ck kk kk kk kk kk kc ko kc ko ke ke ke ke ke koe ke e ee e e e e x GLOBAL VARIABLES 4 J KCECKCECK Ck kk Ck kk Ck kk Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Ek Ck Ck Ck Ck Ck Ck kk kk kk kk kk ke ko ke ke e ke e ke e e e e e extern int t buffe
299. bug tools 11 3 debugger 11 3 emulation porting kit EPK 11 4 emulator 11 3 evaluation module EVM 11 3 simulator 11 3 XDS510 emulator 11 3 technical training organization TTO work shop 11 5 third parties 11 4 workshops 11 5 device nomenclature TMS320 11 10 suffixes 11 10 diagnostic applications 10 10 digital to analog converters DAC interface to the C30 expansion bus 8 6 to 8 9 dimensions 12 pin header 10 8 to 10 9 division floating point 3 10 DMA block moves 3 4 programming hints 7 2 setup and use examples 7 4 to 7 10 documentation 11 5 Index 3 Index emulation porting kit EPK 11 4 emulator 11 3 cable signal timing MPSD 10 4 connection to target system 10 5 to 10 7 MPSD mechanical dimensions 10 8 to 10 9 MPSD connector 12 pin header 10 2 pod MPSD timing 10 4 parameters 10 4 pod interface 10 3 signal buffering 10 5 enhanced memory interface C32 functional description 4 24 evaluation module EVM 11 3 example circuit for wait states and ready generation 4 14 expansion A law 6 6 u law 6 4 expansion bus interface ready generation 4 10 to 4 20 functions 4 12 extended precision addition example 3 16 arithmetic 3 16 multiplication example 3 18 subtract example 3 17 external buses expansion primary bank switching 4 15 primary bus interface 4 4 ready generation 4 10 to 4 20 wait states 4 10 to 4 20 devices 4 2 interfaces 4 3 ready generation 4 11 fast Fourier transforms FFT 3 5 6 28 12
300. c int99 Timer 1 i Be asm DINT word c int99 DMA complete asm Space 20 Reserved space i E asm TRAPO s asm loop 28 TRAPS 0 27 are my asm 7 word c int99 undefined traps A EE asm endloop mx asm Space 4 TRAPS 28 31 reserved NOTE Put all interrupt handlers AFTER this next statement j asm text y3 void c int99 Spurious interrupt handler 8 38 CS4215 Interface to the TMS320C3x 8 6 CS4215 Interface to the TMS320C3x Figure 8 11 shows how to interface the C3x with zero glue logic to Crystal Semiconductor s CS4216 16 bit stereo codec Figure 8 11 TMS320C3x to CS4216 Interface C3x ko CS4215 SDOUT c gt SDN e SCLK FSX 9 t FSYNC FSR TSIN XF0 DIC TCLK J RESET Example 8 10 through Example 8 16 show the assembly and C language codes with their respective header files that program and interface the C3x to the CS4215 Example 8 10 shows the CS4215 driver interrupt vector table Example 8 11 page 8 41 shows the C3x serial port transmit interrupt service routine Example 8 12 page 8 44 and Example 8 13 page 8 46 display the C code header files Example 8 14 page 8 47 shows the C language common driver routines Example 8 15 page 8 49 is the C code header file for Example 8 16 page 8 59 which displays the C language driver routines for the CS4215 These files can be
301. cH lgHlS 8 0g9H1S 89 LEYS 0g oguis ig 0gH1S za 0gHlS d 0gd1S xq uonean amp iuoo 8uls XI LEX 498 691 01 U09 0gH1S KONVINT Do el COO TO alalalalalalale De COO Dad aQoaoaoaaoaoaoaa RoOWTONTS ELNI ZLNI LNI OLNI W o No Tc 0 O0 00rl O10 st CO QU CO REECE ECKL LAL ODON OOTAN O S2222242222 O CO l XO LO st CO C eo DQERLPQQZRAQG4a Moron st CO C Q NE Se REL CEL Ease MMN o Tc 0 O 00rl 010 st CO QU CO AREEXXRAZAAA44 Moron xt CO C Q CAFS2222242222 d 1222222222 2227 diN 189N ZHS 13834 4223227 ee 2722222 2 00cESIN L lt 4 lt SIIg Z UPM Aiowayy uoyeinByuoy Aiowayy saq9ols om yueg aug rz r 31N 4 50 Interfacing Memory to the TMS320C32 DSP 4 6 5 1 One Bank Two Strobes Address Translation for Data Size 16 and 8 Bits Figure 4 25 illustrates how a single physical block of memory can be split into two separate logical halves one with 16 bit data and the other with 8 bit data The access to each half is controlled by a separate strobe control register with corresponding memory width and data size fields Another STRBO control reg ister field STRB CONFIG strobe configuration is setto 1 to indicate that both STRBO and STRB1 are mapped to the same set of four STRBO pins The high memory address pin in this case
302. cations 8 9 Burr Brown DSP101 2 and DSP201 2 Interface to TMS320C3x 8 3 Burr Brown DSP101 2 and DSP201 2 Interface to TMS320C3x Figure 8 5 shows how to interface the C3x with zero glue logic to Burr Brown s DSP201 2 and DSP101 2family of 16 bit DAC and ADC Using a C3x and the DSP202 and DSP102 dual channel DAC and ADC chips provides an efficient low cost stereo digital audio interface Figure 8 5 TMS320C31 Zero Glue Logic Interface to Burr Brown ADC and DAC Burr Brown DSP102 ADC Burr Brown DSP202 DAC CASC 5V 5V CASC XCLK gt CLKRO CLKXO XCLK 3 V _ 2 75 V VINA TMS320C31 VOUTA SOUTA DRO DXO gt SINA SINB 3V 2 75 V VINB vOUTB gt Use TCLK1 ESL SYNC FSRO FSX0 lt SYNC V SSF OSCO TCLKO i SSF 5V 5V SWL OSC1 CONV CONV 8 10 1Q Q9 6 e 1229 MHz 22pF s s 22pF V V The DSP102 ADC is interfacedto the C3x serial port receive side the DSP202 DAC is interfaced to the transmit side The ADC and DAC are hard wired to run in cascade mode In this mode when the C3x initiates a convert command CONV to the ADC through its TCLKO pin both analog inputs are converted into two 16 bit words that are concatenated to form one 32 bit word The ADC signals the C3x that serial data from the last conversion is being transmitted thro
303. ccurs one wait state is generated Wait States and Ready Signal Generation Figure 4 7 Bank Switching for Cypress Semiconductor s CY7C 185 SRAM Each of the four banks in this circuit is selected by decoding signals A15 A13 generated by the 74ALS138 multiplexer see Figure 4 8 With the BNKCMPR register set to OBh the banks are selected on even 8K word boundaries starting at location 080A000h in external memory space Memory Interfacing 4 17 2 EUM TET T d 5 V E V 5 V 15 V V V VCC Voc BA12 j CC BA12 Aj2VCC BA12 A12 BA12 A12 BAM A11 BAM Aii BATT A11 BAM A11 BA10 A10 BA10 A10 _BA10 A10 BA10 A10 Ba9 Ag DO0 Bag lhg DO BA9 lhg D0 A Bag lig D0 3 BA8 lag Di Bas las DI Bas dag D I BAB As Dit BAZ lay D2 BAZ D2 BAZ D2 BAZ a D2 3 BA6 Ac D3 BAG las D3 Bas As D3 Bas lie D3 BAS A5 D4 BAS he D4 BAS D4 UBAS h D4 BAS A D5 BA4 A D5 4 Baa A D5 Baa D5 3 BA3 As Dem BA3 lig D6 Bas lag D6 BA3 lags D6 311 BA2 D7 BA2 D7 4 BA2 D7 4 _ BA2 D7 A2 A2 A2 A2 BAT BAT A BAT BAI A BAO A0 8 BAO 5 8 BAO ho g BAO Ao Ji BANKSEL BANKSEL BANKSEL
304. ce Hall Inc 1978 Oppenheim Alan V and Schafer R W Digital Signal Processing Engle wood Cliffs NJ Prentice Hall Inc 1975 Oppenheim Alan V and Schafer R W Discrete Time Signal Process ing Englewood Cliffs NJ Prentice Hall Inc 1989 Oppenheim Alan V and Willsky A N with Young I T Signals and Systems Englewood Cliffs NJ Prentice Hall Inc 1983 Parks T W and Burrus C S Digital Filter Design New York NY John Wiley and Sons Inc 1987 Rabiner Lawrence R and Gold Bernard Theory and Application of Digital Signal Processing Englewood Cliffs NJ Prentice Hall Inc 1975 Sorensen H V et al Real Valued Fast Fourier Transform Algorithms IEEE Transform on ASSP June 1987 Treichler J R Johnson Jr C R and Larimore M G Theory and Design of Adaptive Filters New York NY John Wiley and Sons Inc 1987 Speech Gray A H and Markel J D Linear Prediction of Speech New York NY Springer Verlag 1976 Jayant N S and Noll Peter Digital Coding of Waveforms Englewood Cliffs NJ Prentice Hall Inc 1984 Papamichalis Panos Practical Approaches to Speech Coding Engle wood Cliffs NJ Prentice Hall Inc 1987 Parsons Thomas Voice and Speech Processing New York NY McGraw Hill Company Inc 1987 Rabiner Lawrence R and Schafer R W Digital Processing of Speech Signals Englewood Cliffs NJ Prentice Hall Inc 1978 Shaughnessy Douglas
305. ches but less than 6 inches The transmission signals H3 and EMUS are buffered through the same package see Figure 10 5 Figure 10 5 Connections Between the Emulator and the TMS320C3x With Transmission Emulator header Signals Buffered k4 2 to 6 inches TMS320C3x EMUO 3 EMU1 EMU2 2 OON 1 9 EMU3 H3 gt EMUO EMUI1 EMU2 EMU3 H3 PD GND GND GND GND GND GND Voc A 10 6 Connections Between the Emulator and the Target System Allsignals buffered The distance between the emulation header and the C3x is greater than 6 inches but less than 12 inches All C3x emulation signals EMUO EMU1 EMU2 EMUS and H3 are buffered through the same package see Figure 10 6 Figure 10 6 Connections Between the Emulator and the TMS320C3x With All Signals Emulator header Buffered kd 6 to 12 inches TMS320C3x EMUO B g L 1 EMU1 T i 5 EMU2 LI LI i i LI LI EMU3 L7 11 H3 gt e LI LI CAUTION EMUO EMU1 EMU2 EMU3 H3 PD GND GND GND GND GND GND Vcc A H3 buffer restrictions of the signal Do not connect any devices between the buffered H3 output and the header Otherwise you will degrade the quality XDS510 Emulator Design Considerations 10 7 Mechanical D
306. cing Memory to the TMS320C32 DSP pm v 0H i8 cH 2g luis 18HIS I HHIS says 6901 L JOLOLEL zore AT u7 GOOLEL 9901 1 Z9OLEL 890LEL A L9IOLEL COOLEL EGOLEL POOLEL 6 OL tt eL S 9 L 8 L 4 v uo U3334l6 E Ov tly SseJppe eois ug 000 1001 LE EEEL FELE EEEL F000 roo SsoJppe e91601 ey Sly 4000006 shq Z Aq paylys sseJppe ezis ejep Hq 8 LZOLEL OZOLEL Iguls 0gH1S ug Aq payiys ssejppe ezis eyep 110 91 Oy bly Sseppe jeoishyd SseJppe eors ug 88999 ty8999 A 18999 zess9 e S 9 v 0000 0000 ssaippe e2180 ly Sly uo shq8 shqee 00 m JeisifeJ joujuoo gH1S LO L 191sI689 01 U09 0gH1S SIq91 Sshqee 0guls ozis Ulpim uolyesnByuoo eea Ajoway auis S8ulsol 09HJS Sseippe 89160 dew Klowew e21601 UIpIM Aiowayy gt ezig geq uoinejsueJ ssejppy Aioweay Jlg Z 61 r einbl4 4 40 Interfacing Memory to the TMS320C32 DSP 4 6 4 16 Bit and 8 Bit Memory Configuration Design Examples This section describes how to interface the C32 to both 8 and 16 bit wide ex ternal memories in the same
307. cknowledge signal it stops driving the data bus and brings the data ready line high To complete the handshaking transaction the DSP brings the data acknowledge signal high to request the next byte from the host The boot table for this type of boot opera tion is created with the linker cr option RAM model and hex conversion utility SECTIONS directive boot keyword the same options used for other boot load procedures involving the on chip boot loader program Memory Interfacing 4 103 Booting a TMS320C32 Target System in a C Environment ULM pJeoq dS 0 peyeduioo se 1s09 uselsAs peonpei 10 9 qe1100q 94 eJ01s 01 I NOHd3 1804 sesn welshs JSd eu uonoes ssq Blep Zelld uonoes ssq elep Lalld ZNVHS NvHS olul Anoeurp Wey peo oj pue slqel 100q y 40 seq jenpiaipul jqw sse 0 1d2 eui sesn Jepeo 100q diuyo uo eu uod jenas eui U104J JO Suolleool Aowaw ssJUl Jo euo WO 9lqel jooq eui Bulpea syes Jepeo 100q yy seo6 9pIM Sq 8
308. come the damping in each cycle Although a square wave has a high content of odd overtones the crystal resonates at its fundamental frequency and strongly attenuates all other frequencies Conse quently the output of a crystal driven by a square wave is sinusoidal If this sinusoidal output is fed back to the input of an appropriately designed amplifier as shown in Figure 9 5 d sustained oscillation is generated Clock Oscillator and Ceramic Resonators 9 7 Quariz Crystal and Ceramic Resonators Figure 9 5 Crystal Response to a Square Wave Drive Crystal model i Ly Ry Cy a Circuit Aa nm 1 IN T C GG HP T T vi D Plload Vo Co b Step function Vi 0 Vo 0 d Amplifier Notes 1 Cg is the capacitance of the two electrodes 2 Lx Rx and Cx model the electrical behavior related to the mechanical vibration of thecrystal Ly and Cy controlthe resonant frequency according to the same equation shown in Figure 9 1 and Ry models the mechanical energy loss in the crystal 9 8 Pierce Oscillator Circuit 9 3 Pierce Oscillator Circuit Figure 9 6 shows an oscillator circuit in its simplest form an amplifier and a feedback network This circuit must meet two requirements to sustain oscilla tion The circuit must have positive feedback DD The open loop gain must be greater than 1 In Figure 9 6 A is the gai
309. contents TMS320C32 STRBO sysm16 16 bit wide memory IOSTRB bse ast STERRI bit wide memor STRB1 TR y Memory Access for C Programs C 5 Memory Access for C Programs Figure C 4 Dynamic Memory Allocation for TMS320C32 One Block Each of 32 16 and 8 Bit Memory a C code e int BUFFER 32 declare a pointer to a pool of 32 bit memory int BUFFER 16 declare a pointer to a pool of 16 bit memory int BUFFER 08 declare a pointer to a pool of 8 bit memory e e 0x808064 0x5000 STRBO control register data size 16 memory width 16 0x808068 0x0000 STRB1 control register data size 8 memory width 8 e BUFFER 32 MALLOC 1024 sizeof int allocate 1K words of memory BUFFER 16 MALLOC16 1024 sizeof int allocate 2K halfwords of memory BUFFER 08 MALLOC8 1024 sizeof int allocate 4K bytes of memory dsp funcl BUFFER 32 BUFFER 16 BUFFER 08 use the above memory e BUFFER 32 MALLOC 2048 sizeof int allocate 2K words of memory BUFFER 16 MALLOC16 512 sizeof int allocate 1K half words of memory dsp func2 BUFFER 32 BUFFER 16 use the above memory e e BUFFER_08 MALLOC8 4096 sizeof int allocate 16K bytes of memory dsp func3 BUFFER 08 use the above memory e e b LINKER command file e e heap 0x4000 set the size of the dynamic 32 bi
310. cs dsps support htm North America South America Central America Product Information Center PIC 972 644 5580 TI Literature Response Center U S A 800 477 8924 Software Registration Upgrades 214 638 0333 Fax 214 638 7742 U S A Factory Repair Hardware Upgrades 281 274 2285 U S Technical Training Organization 972 644 5580 DSP Hotline 281 274 2320 Fax 281 274 2324 Email dsph ti com DSP Modem BBS 281 274 2323 DSP Internet BBS via anonymous ftp to ftp ftp ti com pub tms320bbs Europe Middle East Africa European Product Information Center EPIC Hotlines Multi Language Support 33 1 30 70 11 69 433130701032 Email epic ti com Deutsch 49 8161 80 33 11 or 33 1 30 70 11 68 English 33 1 30 70 11 65 Francais 33 1 30 70 11 64 Italiano 33 1 30 70 11 67 EPIC Modem BBS 33 1 30 70 11 99 European Factory Repair 33 4 93 22 25 40 Europe Customer Training Helpline 49 81 61 80 40 10 Asia Pacific Literature Response Center 852 2956 7288 Fax 852 2 956 2200 Hong Kong DSP Hotline 852 2956 7268 Fax 852 2 956 1002 Korea DSP Hotline 48225512804 Fax 822 551 2828 Korea DSP Modem BBS 82 2 551 2914 Singapore DSP Hotline Fax 65 390 7179 Taiwan DSP Hotline 886 23771450 Fax 886 2 377 2718 Taiwan DSP Modem BBS 886 2 376 2592 Taiwan DSP Internet BBS via anonymous ftp to ftp dsp ee tit edu tw pub Tl Japan Product Information Center 0120 81 0026 in Japan Fax 0120 81 0036 in Japan 03 3457 0972 or INTL
311. ct is intended for internal evaluation purposes rr Note Prototype Devices Tl recommends that prototype devices TMX or TMP not be used in produc tion systems Their expected end use failure rate is undefined but predicted to be greater than standard qualified production devices LLLLLLL L LLL L v TMS devices and TMDS development support tools have been fully character ized and their quality and reliability have been fully demonstrated Tl s stan dard warranty applies to TMS devices and TMDS development support tools TMDX development support products are intended for internal evaluation pur poses only They are covered by TI s warranty and update policy for micropro cessor development systems products however they should be used by cus tomers only with the understanding that they are developmental in nature Development Support and Part Ordering Information 11 9 TMS320C3x Part Ordering Information 11 2 2 Device Suffixes The suffix indicates the package type for example N FN or GE and temper ature range for example L Figure 11 1 presents a legend for reading the complete device name for any TMS320 family member Figure 11 1 TMS320 Device Nomenclature TMS 320 C 30 GE L Prefix Temperature Range TMX Experimental device H 0to 50 C TMP Prototype device L Oto 70 C TMS Qualified device S 55 t
312. current and are considered insignificant This figure rep resents the incremental Ipp from internal bus operations andis added to quies cent and internal operations current values Figure 12 3 Internal Ipp internal bus data scale factor D1 Normalized Current Requirements for Internal Circuitry For example the maximum transfer rate corresponds to three accesses every cycle or one third H1 transfer cycle time At this rate 85 mA is added to the quiescent 110 mA and internal operation 55 mA current values for a total of 250 mA Figure 12 3 shows the data dependence of the internal bus current require ment when the data is other than As followed by 5s The shaded trapezoidal region represents the internal bus current consumed for all possible data val ues transferred The lower line represents the scale factor for transferring the same data all Os or all Fs The upper line represents the scale factor for trans ferring alternating data all Os to all Fs or all As to all 5s Bus Current Versus Data Complexity Derating Curve Alternating data Same data Fs to Fs 0 0 1 02 03 04 05 06 07 O8 0 9 1 Relative data complexity The number of possible permutations of data values is quite large The extent to which data varies is referred to as relative data complexity This term refers to a relative measure of the extent to which data values are changing and the extentto which the n
313. current consumption depends on many factors Four are system related DD Operating frequency Supply voltage Operating temperature Output load Several other factors are related to C30 operation They include Duty cycle of operations Number of buses used Wait states Cache usage Data value of internal and external bus O O O O L 12 2 Power Dissipation Characteristics The total power supply current for the device is described in the following equa tion which applies the four basic power supply current factors and the depen dencies described above lg liops ibus lxpus X FV x T where lg quiescent current liops Current from internal operations linus Current from internal bus usage including data value and cycle time dependencies lxbus current from external bus usage including data value wait state cycle time and capacitive load dependencies FV scale factor for frequency and supply voltage T scale factor for operating temperature The application of this equation and the determination of all of the dependen cies are described in detail in this chapter If aless detailed analysis is sufficient use the minimum typical and maximum values to determine a rough estimate of the power supply current require ments D The minimum power supply current requirement is 110 mA The typical and average current consumption is 200 mA as described in the TMS320C30 Di
314. d Memory Interface 4 7 1 2 MEMORYS C Module The MEMORY8 C module contains functions that implement dynamic memory management routines for using 8 bit data with the C32 See the TMS320C3x C4x Optimizing C Compiler User s Guide for more information on 8 bit runtime support functions The pragma directive in the MEMORY8 C module defines a sysm8 section The size of this memory pool in words system memory or heap is set at link time by using the heap8 option If the heap8 option is not used the compiler does not allocate an 8 bit system memory area If arguments are not used in conjunction with this switch the size of the 8 bit system memory area defaults to 1K 8 bit words The following functions operate in the 8 bit sysm8 section minit8 initializes and resets the 8 bit dynamic memory management system j malloc8 allocates 8 bit words from the 8 bit memory pool and returns a pointer to the allocated space Lj calloc8 allocates 8 bit words from the 8 bit memory pool clears allo cated memory locations and returns a pointer to the allocated space D realloc8 reallocates 8 bit words from previously unallocated areas in the 8 bit memory pool a pointer to the allocated space is returned D free8 frees previously allocated space from the 8 bit memory pool D bmalloc8 allocates 8 bit words from the 8 bit memory pool The allo cated words are aligned to a boundary that is suitable for the C32 s circu lar and
315. d following a conversion the AD1678 takes 100 ns after its OE control line is asserted to provide valid data at its outputs Thus including the propagation delay of the 74L S244 buffers the total access time for reading the converter is 118 ns This requires two wait states on the C30 33 expansion I O bus The two wait states required in this case are implemented using software wait states However depending on the overall system configuration you can im plement a separate wait state generator for the expansion bus for example in a case where multiple devices that require different numbers of wait states are connected to the expansion bus See section 4 5 Wait States and Heady Generation on page 4 10 Figure 8 2 shows the timing for read operations between the C30 33 and the AD1678 At the beginning of the cycle the address and XR W lines become valid at 10 ns t4 following the falling edge of H4 Then after 10 ns t2 from the next rising edge of H4 IOSTRB goes low This begins the active portion of the read cycle After the control logic propagation delay at 5 8 ns t3 the IOR signal goes low asserting the OE input to the AD1678 The 74LS244 buff ers take 30 ns t4 to enable their outputs Then after the converter access delay and the buffer propagation delay at 118 ns ts which equals 100 18 data is provided to the C30 This provides approximately 46 ns of data setup time before the rising edge of IOSTRB Therefore this de
316. d transistor feedback network so an external feed back resistor is unnecessary This feedback network ensures that the inverter l4 is biased in its linear region Figure 9 10 TMS320C3x Oscillator Circuitry p To C3x internal clock circuitry Transistor feedback network Xo CLKIN Co zx S Ci The inverters in the oscillator circuitry differ from the usual CMOS inverter con figuration shown in Figure 9 11 in that the p channel transistor is biased as an active load instead of having the gate connected as the input of the inverter This difference is part of the biasing scheme which helps to ensure that the oscillator starts when power is applied This design causes the rise and fall Clock Oscillator and Ceramic Resonators 9 13 Pierce Oscillator Circuit times to be asymmetrical for example the rise time is longer than fall time but since the oscillator outputis divided by 2 before driving the internal proces sor circuitry the duty cycle of the final clock H1 or H3 is 5096 Figure 9 11 Digital Inverter Circuit and Its Transfer Characteristic VDD VOUT d VIN 9 9 VOUT L 9 3 3 Overtone Operation of the Oscillator Although crystals are usually considered to vibrate at only one frequency they also resonate at odd multiples or overtones of the series resonant frequency The series resonant frequency is the fundamen
317. data size fields Another STRBO control reg ister field STRB CONFIG is set to 1 to indicate that both STRBO and STRB1 are mapped to the same set of four STRBO pins The high memory address pin in this case A14 selects between the two halves of the memory For this example the C32 address pin A17 drives the memory pin A14 The state of the A17 bit of the physical address is derived from the logical ad dress logical as seen by the instruction The state of the A17 bit also depends on the logical physical address shift as determined by the size of the program data that is being accessed In this case the logical STRBO address range drives the physical address bit A17 to 0 after accounting for a 1 bit address shift due to the 16 bit width of the data Similarly the logical STRB1 range drives the physical address bit A17 to 1 The logical STRBO and STRB1 ad dress ranges that drive the physical address pin A17 to 0 and 1 respectively must still conform to the logical memory map that assigns fixed blocks of ad dresses to different strobe spaces An STI RO ARO instruction with ARO 887FFFh results in a STRBO data ac cess data size 16 bits driving the STRBO B2 and STRBO B3 control pins to write the contents of the 32 bit register RO into a 16 bit data location in the lower half of the external memory addressed by 3FFFh Similarly an LDI AR1 R1 instruction with AR1 923FFFh results in a STRB1 data access
318. ddress of the call Example 2 10 shows a computed GOTO for a task controller Example 2 10 Computed GOTO X ITLE COMPUTED GOTO z TASK CONTROLLER zi THIS MAIN ROUTINE CONTROLS THE ORDER OF ASK EXECUTION 6 TASKS I THE PRESE EXAMPLE TASKO THROUGH TASK5 ARE THE NAMES OF SUBROUTINES TO BE CALLED THEY ARE EXECUTED IN ORDER TASKO TASK1 TASK5 WHEN AN INTERRUPT OCCURS THE I ERRUPT SERVICE ROUTINE IS EXECUTED AND THE PROCESSOR CONTINUES WITH THE INSTRUCTION FOLLOWING THE IDLE INSTRUCTION HIS ROUTINE SELECTS HE TASK APPROPRIATE FOR THE CURRENT CYCLE CALLS HE ASK AS A SUBROUTINE AND BRANCHES BACK TO HE IDLE TO WAIT FOR THE NEXT SAMPLE I ERRUPT WHEN THE SCHEDULED TASK HAS COMPLETED EXECUTION RO HOLDS THE OFFSE FROM THE BASE ADDRESS OF THE TASK TO BE EXECUTED LDI 5 R0 Initialize RO LDI ADDR AR1 AR1 holds base address of the table WAIT IDLE Wait for the next interrupt ADDI3 AR1 R0O AR2 H Add the base address to the table Entry number SUBI 1 R0 Decrement RO LDILT 5 RO0 If RO lt O reinitialize it to 5 LDI AR2 R1 Load the task address CALLU R1 j Execute appropriate task
319. dering does not require extra cycles because the device has a special mode of indirect addressing bit reversed addressing for accessing the FFT output in the original order The examples in this section are based on programs contained in the DFT FFT and Convolution Algorithms book and in the paper Heal Valued Fast Fourier Transform Algorithms Fast Fourier Transforms FFTs 6 6 1 FFT Definition The FFT is an efficient implementation of the discrete fourier transform DFT equation N 1 XN gt x n e o n 0 The inverse DFT equation is N 1 x n i XQ ewe k 0 The FFT takes advantage of the periodic nature of the complex exponential ei n to reduce redundancy and number of calculations The FFT expresses the original DFT using two smaller DFTs of length M This definition is applied until the original DFT has been expressed in terms of a 2 point DFT which is nor mally referred to as radix 2 FFT There are two ways this decomposition process occurs L Bydecimation in time where the signals are split into several shorter inter leaved sequences see Figure 6 8 By decimation in frequency where the signals are split into several smaller interleaved frequency components see Figure 6 9 Figure 6 8 Decimation in Time for an 8 Point FFT Stage 3 Stage 2 Stage 1 e gt gt e X 0 CT e gt gt e X 1 wO e gt gt e X 2 LU e e X 3 wO e gt gt e X 4
320. downloaded from Texas Instrument s BBS or ftp site file name C3x4215 EXE Analog Interface Peripherals and Applications 8 39 CS4215 Interface to the TMS320C3x Example 8 10 vecs asm pk e kk x x M KKK KKK KKK KK VECS ASM C3x CS x 0 F HD C 1991 kk ck ck ck ck Ck Sk KKK KKK ck ck ck Ck Sk ck Ck Sk KKK ck Ck ck ck kk ck ck ck KK KKK KKK ko ko kc KKK KKK vecs asm staff 01 03 92 C Texas Instruments Inc 1992 Refer to the file license txt included with this this package for usage and license information kk ck ck ck ck Ck Sk ck Ck KKK KKK Ck ck ck Ck Sk KKK ck Ck ck ck kk ck ck ck ko kk kk kk ck KKK KKK KKK 4215 DRIVER INTERRUPT VECTOR TABLE bi TEXAS INSTRUMENTS HOUSTON m INTERRUP Sec ref ref ref ref reset WOr into WOr intl WOr int2 WOr int3 WOr xintO0 WOr rinto WOr xintl WOr rinti WOr tint0 WOr tinti
321. dress pins B STRBx_B1 and STRBx BO are byte enable signals B STIRBx B2 A are not used Lj 32 bit wide memory B SIHBx B3 A 4 STRBx B2 A STRBx B1 and STRBx BO are byte enable signals Memory Interfacing 4 67 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface 4 68 J Data size B 8 bit data The physical address is the logical address shifted right by 2 B 16 bit data The physical address is the logical address shifted right by 1 B 32 bit data The physical address is the logical address IOSTRB can access 32 bit data from 32 bit wide memory However IOSTRB does not have the flexibility of STRBO and STRB1 because it is composed of asingle signal IOSTRB bus cycles differ from STRBO and STRB1 bus cycles See the nterlocked Operations section in the Program Flow Control chapter of the TMS320C3x User s Guide for more information This timing difference accommodates slower I O peripherals The C32 also supports program execution from 16 and 32 bit external memory widths Execution is controlled through the status of the PRGW pin When this pin is pulled high the C32 executes from 16 bit wide memory When the PRGW pin is pulled low the C32 executes from 32 bit wide memory For 16 bit wide zero wait state memory the C32 takes two instruc tion cycles to fetch a single 32 bit instruction The lower 16 bits of the instruc tion are obtained during the first cycle the upper 16 b
322. ds Ly One extra data word required ck ck ck 0k ck ck 0k ck Sk ck ck 0k ck kk ck KK KKK kk ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck kc ck ck ck ck ck ck ck ck ck ck ck ck ck ck kk ko ko kv Sk ko kA kx kx SYNOPSIS int ffft rl FFT SIZE LOG SIZE SOURCE ADDR DEST ADDR SINE TABLE BIT REVERSE int FFT SIZE 64 128 256 512 1024 int LOG SIZE gt 6 p 8 9 10 float SOURCE ADDR Points to location of source data i float DEST ADDR Points to where data will be i operated on and stored float SINE TABLE Points to the SIN COS table int BIT REVERSE 0 bit reversing is disabled lt gt 0 input bit is provided reversed is enabled NOTE 1 If SOURCE ADDR DEST_ADDR then in place bit reversing is performed if enabled mor processor intensive 2 FFT SIZE must be 64 this is not checked 0X 0X F FH 6 42 Fast Fourier Transforms FFTs Example 6 16 Real Forward Radix 2 FFT Continued c ESCRIPTION Generic function to do a radix 2 FFT computation on the C30 The data array is FFT SIZE long with only real data The out put is stored in the same locations with real and imaginary points R and I as follows DEST ADDR 0 D R FFT SIZE 2 I FFT SIZE 2 1 I 2 DEST ADDR FFT SIZE 1 gt r The program is based on the FORTRAN program in the paper by Sorensen et al June 1987 issue of
323. dth The example in Figure 4 23 is in a way an inverse of thatin Figure 4 22 The 8 bit data is transferred to and from 16 bit wide external memory To put this example in perspective assume that the data transfer is triggered by the fol lowing C32 instruction STI RO 7FFFh While in RO the data is sized at 32 bits but when it arrives at the memory interface the STRBO control register data size field indicates 8 bit wide data So the 32 bit data is truncated to 8 bits The now byte sized data is transferred to address 7FFFh of the 16 bit wide external memory In this case the LSB of the logical address as refer enced by the instruction is actually rerouted to control one of the two STRBO lines assigned to the 16 bit physical memory If the LSB is 1 as in this case STRBO B1 is asserted during the write cycle If the LSB is 0 STRBO BOis as serted during the write cycle The remaining bits of the original logical address are placed on the external address bus starting at pin A 4 because the memory width is 16 bits 4 6 4 4 Design Considerations While designing the external memory interface to the C32 a hardware engi neer must remember to match address pin A 4 with the AO pin of a 16 bit wide memory or to match the A address pin with the AO pin of a byte wide memory If the external memory is 32 bits wide the pins are not shifted relative to each other and therefore match perfectly at AO When writing code fo
324. e C30 Therefore you must determine the algorithm s internal usage in order to accurately calculate the power supply current requirements The C30 software simulator and XDS emulator both provide benchmarking and timing capabilities that help you determine bus usage The current resulting from internal bus usage varies exponentially with transfer rates Figure 12 2 shows the internal bus current requirements for transfer ring alternating data AAAAAAAAh to 55555555h A transfer rate less than 1 implies multiple accesses per single H1 cycle thatis using direct memory ac cess DMA etc Transfer cycle times greater than 1 refer to single cycle transfers with one or more cycles between them The minimum transfer cycle time is one third which corresponds to three accesses in a single H1 cycle Figure 12 2 Internal Bus Current Versus Transfer Rate AAAAAAAAh to 55555555h 12 6 T 100 ES 8 80 as CY am 60 dz a 40 5 E 2 5 2 5 2 20 mi re 0 20 0 2 4 6 8 10 12 14 Transfer cycle time H1 cycles The data set AAAAAAAAh to 55555555h exhibits the maximum current for these types of operations Less current is required for transferring other data patterns and current values can be derated accordingly As the transfer rate decreases transfer cycle time increases the incremental Ipp approaches 0 mA Transfer rates corresponding to more than seven H1 cycles do not add any
325. e derated according to manufacturer specifica tions to accommodate a wide variety of memory array sizes The circuit shown in Figure 4 7 illustrates the use of bank switching with Cypress Semiconductor s CY7C185 25 ns 8K x 8 bit CMOS static RAM This circuit implements 32K 32 bit words of memory with one wait state accesses for each bank The bank memory requires a wait state with this implementation because of the added propagation delay presented by the address bus buffers used in the circuit The wait state is not a function of the memory organization of multiple banks or the use of bank switching Memory access speeds are the same with and without bank switching once bank boundaries are crossed No speed penalty is incurred by using bank switching except for the occasional extra cycle inserted when bank boundaries are crossed If this extra cycle impacts software performance significantly you can often restructure code to minimize bank boundary crossings and reduce the effect of these boundary crossings on software performance The wait state forthis bank memory is generated by using the wait state gener ator circuit described in section 4 5 5 on page 4 14 Because the A23 signal enables the entire bank memory system the inverted version of this signal is ANDed with STRB to derive a one wait state device select This signal is then connectedin the circuit along with the other one wait state device selects Any time a bank memory access o
326. e device some current contributions to IDD do not constitute a factor of power dissipation at 5 V Accordingly if you use the total current flowing into Vpp to calculate power dis sipation at 5 V you obtain erroneously large values for power dissipation Power dissipation is defined as PelxVv where P power current V voltage If device outputs are driving any dc load to a logic high level only a minor con tribution is made to power dissipation because CMOS outputs typically drive to a level within a few tenths of a volt of the power supply rails If this is the case subtract these current factors out of the total supply current value then calcu late their contribution to power dissipation separately and add it to the total power dissipation see Figure 12 13 If this is not done these currents result ing from driving a logic high level into a dc load cause unrealistically high power dissipation values The error occurs because the currents resulting from driv ing a logic high level into a dc load appears as a portion of the current used to calculate power dissipation from Vpp at 5 volts TMS320C30 Power Dissipation 12 21 Calculation of Total Supply Current Figure 12 13 Load Currents 12 22 Yoo n Y IOH TMS320C30 Device output driven high Y Iss Yoo Ibo v IOL TMS320C30 Device output driven low vss Furthermore external loads draw supply only current when outputs are driven
327. e ee em 6 3 TEE EXPANSION sie e m T PDT 6 4 A Eaw CompressiOn ue es cree eee el oa ee ele d esos Pru ua led eee 6 5 A Law EXpanslOln sensies ai gisis aiia t edidere hed edP adea d adv o i d iUnd aede 6 6 FIP PINE m c a a ed a a DA 6 8 IIR Filter One Biquad 7 Oo RIAM 6 10 IIR Filters N 1 Biquads sa on DD a BRI 6 13 Adaptive FIR Filter LMS Algorithm ssssssssesssm II 6 16 Inverse Lattice Filter a 0 00 cece eee eee nn 6 19 Lattice Filth iia EM 6 22 Matrix Times a Vector Multiplication i 6 25 VECMAXASM PRETI 6 27 Complex Radix 2 DIF FFT oo sasini siie en gaian ern 6 31 Table With Twiddle Factors for a 64 Point FFT i 6 34 Complex Radix 4 DIF FFT 1 2 od i a a E EENAA E 6 36 Real Forward Radix 2 FFT ee A nn 6 42 Real Inverse Radix 2 FFT ss nD ed ed spa ete nn 6 61 SFELASM Som eo oo ed esas sid Mie ide thay be becca ve be PIU EE 6 94 Array Initialization With DMA sss III Hh 7 4 DMA Transfer With Serial Port Receive Interrupt i 7 6 DMA Transfer With Serial Port Transmit Interrupt i 7 7 TMS320C3x BB DSP 102 202 Driver Header File i 8 12 TMS320C3x BB DSP102 202 Driver i 8 14 General Macro Definitions oiec cions risainia ai eet e 8 18 Common Driver Header File pp 8 20 Initialize the Serial Port Global Control Register i 8 23 Setting the TA and TB Registers 0 8 27 Interfacing the 18 bit TLC320AD58 to TMS320C3x i 8 33 C3x h Header File Listing os 8 36 TMS320C3x Interru
328. e eens 11 7 TMS320C3x Support Tool Part Numbers 0 000 c cece eee eee tenes 11 8 Current Equation Variables 4 12 20 TMS320C32 Boot Loader Opcodes pp B 5 Variable Memory Width 000 er RII hn D 4 Variable Data Size 7 a se oa me tenet eee di A D 5 Contents XXV Examples Ld dE 4 dod 4 4 1 ODD I oe eI 1 d I RO O ONO OC D ROwoONM Oo Jude Ne od M 45d d tn lI Ir Kon 4 5 4 6 4 7 4 8 xxvi TMS320C3x Processor Initialization so era eee 1 5 Enabling the Cache onion de e hn 1 8 State Machine and Equations for the Interrupt Generation 16R4 PLD 1 10 Subroutine Call Dot Product gr cent nn 2 3 Use of Interrupts for Software Polling ot 2 9 Interrupt Service Routine 0 2 10 Context Save for the TMS320C3x 0 0 eee 2 13 Context Restore for the TMS320C3x 0 2 15 Delayed Branch Execution ssia Dna 2 17 Loop Using Block Repeat sn 2 19 Use of Block Repeat to Find a Maximum i 2 20 Loop Using Single Repeat 9 2 21 Computed GO TO i iita ated ane Pied ese ie Meda dae tele aid ad see ates 2 22 Use of TSTB for Software Controlled Interrupt i 3 2 Copy a Bit From One Location to Another i 3 3 Block Move Under Program Control pp 3 4 Bit Reversed Addressing pp 3 5 Integer DIVISION iex E TRE ERREUR GR MEG RUE RUE ERR RUE HEURE ee Re Re 3 8 Inverse of a Floating Point Number 7 3 11 Square Root of a Floating Point Number 00 cece cece eee een
329. e glue logic must also be connected to the host side of the latch to ensure proper data transfer synchronization be tween two asynchronous systems see Figure 4 45 on page 4 105 At power up the DSP boot table most likely resides in the host s EPROM and the host outputs the boot table to the latch one byte at a time following reset Creating the boot table for this operation uses the same linker COFF options as for the host serial boot and the direct EPROM boot Booting a TMS320C32 Target System in a C Environment 4 8 6 3 Asynchronous Boot From a Communications Port If the host processor has an asynchronous communications capability then the C32 can make a glueless connection to the host s communication port see Figure 4 46 on page 4 106 In addition to the data bus three C32 pins are involved in the asynchronous boot XFO XF1 and IACK The XF1 pin serves as the data ready input to the C32 and XFO is the data acknowledge The IACK pin pulses when there is no valid data present on the data lines which are needed for the C4x comm port interface For boot loader mode itis assumed that the host such as a C4x connects directly to the data ready and data acknowledge control lines The host drives the data ready signal low to indicate to the DSP that the next byte of the boot table has been placed on the data lines The DSP responds by pulling the data acknowledge signal low after reading the data When the host sees the data a
330. e implemented as a cascade of second order sections called biquads Example 6 6 shows the implementation for one biquad This is the equation for a single biquad y n a1 y n 1 a2 y n 2 bOx n b1 x n 1 b2 x n 2 However the following two equations are more convenient and have smaller storage requirements d n a2d n 2 at d n 1 x n y n b2d n 2 bt d n 1 bO d n Figure 6 2 shows the memory organization for this two equation approach and Example 6 7 shows the implementation for any number of biquads DSP Algorithms 6 9 FIR IIR and Adaptive Filters Figure 6 2 Data Memory Organization for a Single Biquad Filter Newest delay Newest delay low coefficients node values node values address Newest delay Circular queue Oldest delay address As in the case of FIR filters the address for the start of the d values must be a multiple of 4 that is the last two bits of the beginning address must be 0 The block size register BK must be initialized to 3 Example 6 6 IIR Filter One Biquad TITLE IIR FILTER SUBROUTINE IIR 1 IIR1 IIR FILTER ONE BIQUAD EQUATIONS d n a2 d nt2 al d nt1 x n y n b2 d nt2 bl d nfl b0 d n OR y n al y ntl a2 y nt2 b0O x n bl x n t1 b2 x nt2
331. e ke e e x f CS4215 DATA COMMAND BIT FIELD MACROS yA RK IK IK kk kk I I I kk I I I I I kk I I kk I I I I I I I I I I I I I I I ko ke ke x f BK HK HK kk kk ck kk kk kk Ck kk kk kk kk kk kk kk kk kk kk kk kk kk ke kk kc ke kc k kc I ko kc kc I ke ke ke ke e e e x f CONTROL COMMAND MACROS xy KK IK IK I kk kk kk I kk kk kk kk kk kk kk kk kk kk kk I I ko I kc kc I A ck ck ck ck ck ck ck ck ck ck ck ck ck ckok kok ko ke x f define DATA 1 define COMM define SIXTEEN_BIT_LINEAR define EIGHT_BIT_U_LAW define EIGHT_BIT_A_LAW define MONO_MODE define STEREO MODE 2 c HRS p oO oe 8 54 CS4215 Interface to the TMS320C3x Example 8 15 CS4215 h Continued Data conversion Frequency Selections Assumes that XTAL1 24 576 MHz And XTAL2 16 9344 MHz XTAL1 kHz XTAL2 kHz define CONV FREQ 0 0 JE 8 00000 5 5125 define CONV FREQ 1 1 16 00000 11 0250 define CONV FREQ 2 2 27 42857 18 9000 define CONV FREQ 3 3 32 00000 22 0500 define CONV FREQ 4 4 NA 37 8000 define CONV FREQ 5 5 NA 44 1000 define CONV FREQ 6 6 48 00000 33 0750 define CONV FREQ 7 7 9 60000 6 6150 y define CS_ENABLE 0 Data output enabled define CS DISABLE 1 Data output disabled define CS_TCLOCK_E 0 FSYNC and SCLK are inputs d
332. e lower 32 tore the upp the lower 32 tore the upp the lower 32 bi upper 32 CS r 32 bi LS r 32 bi LS E 32 bi CS D 32 bi LS r 32 bi CS r 32 bi CS r 32 bi CS bi of bi ot bi of bi of bi of bi of bi of ts and R7 ts and R6 ts and R5 ts and RA ts and R3 ts and R2 ts and R1 bi of tore status register ts and RO 2 16 Delayed Branches 2 5 Delayed Branches The C3x uses delayed branches to create single cycle branching The delayed branches operate like regular branches but do not flush the pipeline Instead the three instructions following a delayed branch are also executed As discussed in the Program Flow Control chapter of the TMS320C3x User s Guide the only limitations are that none of the three instructions following a delayed branch may be a j Branch standard or delayed J Call to a subroutine Return from a subroutine J Return from an interrupt Repeat instruction D TRAP instruction D IDLE instruction Conditional delayed branches use the conditions that exist at the end of the instruction immediately preceding the delayed branch Sometimes a branch is necessary in the flow of a program but fewer than three instructions can be placed after a delayed branch For faster execution it is still advantageous to use a delayed branch T
333. e manner as data dependencies discussed in other sections Figure 12 11 shows the relative scale factors for the supply current values as a function of both Vpp and operating frequency Power supply current consumption does not vary significantly with operating temperature However a scale factor of 2 normalized IDD per 50 C change in operating temperature may be used to derate current within the specified range noted in the 7MS320C30 Digital Signal Processor data sheet This tem perature dependence is shown graphically in Figure 12 12 A temperature scale factor of 1 0 corresponds to current values at 25 C which is the tempera ture for all references in the document Current Versus Frequency and Supply Voltage frequency supply voltage scale factor FV 1 2 VDD 5 5 V VDD 5 25 V VDD 5 0 V VDD 4 75 V VDD 4 5 V VDD increments in 0 25 V 0 5 10 15 20 25 30 f CLKIN MHz Calculation of Total Supply Current Figure 12 12 Current Versus Operating Temperature Change 1 03 _ 1 02 9 o S gt 1 01 oO D 9 1 2 5 2 0 99 9 ll 0 98 0 97 80 60 40 20 0 20 40 60 80 Change in operating temperature C 12 4 3 Total Current Equation Example The procedure for determining the power supply current requirement is sum marized in the following equation Iq liops libus Ixbus x FVxT where
334. e of the mantissa with the most significant 1 implied The binary pointis after this most significant 1 The mantissa actually has 24 bits Several special cases are summarized below These are the values of the numbers represented in the IEEE floating point format 1 8 x 28 1 7 01 f if 0 lt e lt 255 Special cases 71 5 X 0 0 if e 0 and f 0 zero 1 8 x 2 7126 0 f if e 0 and f lt gt 0 denormalized 1 x infinity if e 255 and f 0 infinity NaN not a number ife 2255andf 0 Based on these definitions of the formats two versions of the conversion rou tines were developed One version handles the complete definition of the for mats The other ignores some of the special cases typically the ones that are rarely used but has the benefit of executing faster than the complete conver sion For this discussion the two versions are referred to as the complete ver sion and the fast version respectively Logical and Arithmetic Operations 3 21 IEEE TMS320C3x Floating Point Format Conversion 3 7 1 IEEE to TMS320C3x Floating Point Format Conversion Example 3 11 shows the fast conversion from IEEE to C3x floating point for mat It properly handles the general case when 0 e 255 and also handles Os that is e 0 and f 0 The other special cases denormalized infinity and NaN are not treated and if present give erroneous results Example 3 11 IEEE to TMS320C3x Conversion Fast
335. e physical memory Though address translation is com pletely automatic these cases provide insight into the range of physical ad dresses actually affected during transfer of 32 16 and 8 bit data Memory Interfacing 4 41 ev Figure 4 20 16 Bit and 8 Bit Memory Configuration A Complete Minimum Design TMS320C32 AO A2 AN System reset RESET 0 3 R W Boot loader SHZ HOLDA WE configuration V o MCBL MP HOLD jumpers Ce Ald A14 mw Voc PRGW 4 A13 OE A13 O O e INTO AT L7 A12 A12 wo RDY NA11 A11 2 O O e INT1 Si A10 A10 wo Ie A9 A9 o lo bd INT2 I A8 A8 poo A7 D7 A7 D7 O O e INT3 GS A6 D6 D15 A6 D6 a Aas D5 D14 A5 D5 IACK a A4 D4 D13 A4 D4 H x Hes Bes E 2 V A1 D1 D10 A1 D1 XF1 AO DO re AO DO Oscillator LKIN Emulator 60 MHz A4 cable ae header H3 STRBO_B2 STRBO B1 STRBO BO IOSTRB D7 D6 D5 D4 D2 a D1 e O O d e O O e O O e O O STRB1 B1 e O O STRB1 BO LL UL wee DULL h ader Note The EPROM is connected for data access shifted address and not for boot table access This system is booted from the serial port see INT3 signal dSG ZED0ZESWL 94 o Aiowayy Bureau Interfacing Memory to the TMS320C32 DSP 4 6 4 1 16 Bit and 8 Bit Memory Address Translation for Data Size Memory Width As shown in Figure 4 21 when the external memory width matches the size of da
336. e range of clocking frequencies The C3x allows considerable flexibility in meeting these clocking requirements The C3x provides two modes for clock generation and control for use with dif ferent application needs These include J External clock input with the capability to divide the clock frequency by 2 Internal clock generation from an on board oscillator with no external clock necessary C30 and C31 only The built in oscillator provides a method for accurate clock generation that re quires few external components a crystal or ceramic resonator and two load capacitors This saves board space and reduces system cost On the C3x devices the on board oscillator operates in a divide by 2 mode In this mode the frequency of H1 or H3 which indicates the actual machine cycles of the processor is one half of the oscillator frequency 9 1 1 Recommendations for Oscillator Use 9 2 The C3x family of devices provides several clock generation options based on cost component count and the required clock frequency for the applica tion The oscillator clocking option on the C3x provides a low cost method of clock generation with as few as three external components one crystal and two load capacitors which helps to minimize board space consumed for clock generation The crystal or ceramic resonator used determines the frequency of operation This frequency can extend up to 60 MHz with third overtone crys tals CMOS com
337. e wid bs Sota Le wae 9 2 9 1 1 Recommendations for Oscillator Use i 9 2 9 2 Quartz Crystal and Ceramic Resonators i 9 3 9 2 1 Behavior and Operation of Quartz Crystal and Ceramic Resonators 9 4 9 2 2 Crystal Response to Square Wave Drive i 9 7 9 3 Pierce Oscillator Circuit ss ss 9 9 9 3 1 Oscillator Operation ss a ssa ees nn 9 10 9 3 2 Pierce Oscillator Configuration for the TMS320C30 and TMS320C31 9 13 9 3 3 Overtone Operation of the Oscillator i 9 14 9 4 Design Considerations pp 9 17 9 4 1 Crystal Series Resistance Ry 9 9 17 9 42 Load Capacitors sn bn a A nent eee 9 17 94 9 Loop Gall 3 24208 tes Do Ted Ria SachTieetagerhreeetebesieade 9 18 9 4 4 Drive Level Power Dissipation i 9 18 9 4 5 Startup TMC cs ote ol eo Deo lle dnd oed aU de eal ine 9 20 9 4 6 Frequency Temperature Characteristics of Crystals 9 20 9 4 7 Crystal Aging ss ns sn sn A eet eee eee 9 21 9 5 Oscillator Solutions for Common Frequencies pp 9 22 10 11 12 Contents XDS510 Emulator Design Considerations LLuueses 10 1 Describes the JTAG emulator cable Tells you how to construct a 12 pin connector on your target system and how to connect the target system to the emulator 10 1 Designing the MPSD Emulator Connector 12 Pin Header i 10 2 10 2 Emulator Cable Pod Logic ii ene Tor nn 10 3 10 3 MPSD Emulator Cable Signal Timing i 10 4 10 4 Connections Between the Emulator and the Target System
338. earch a vector of N elements is searched for its greatest element max p i In pseudo C format the search is expressed by max 0 max location 0 for i20 i lt N itt if max lt p i max p i max location i Example 6 12 shows an example Vector Maximum Search Example 6 12 vecmax asm Vector maximum search EQUATIONS max max p i TYPICAL CALLING SEQUENCE E load ARO H load RC load R1 CALL vecmax gt ARGUMENT ASSIGNMENTS A argument function H x ARO address of vector ORC length of filter 2 N 2 A R1 length of filter 1 N 1 H REGISTERS USED AS INPUT ARO R1 RC H REGISTERS MODIFIED RO R1 ARO RC REGISTER CONTAINING RESULT RO maximum value R1 index of maximum value H PROGRAM SIZE 5 words XECUTION CYCLES 2 3N text vecmax ldf ar r0 last value rptb loop cmpf3 ar0 r0 Compare input value to maximum ldile ro rl Write index of loop loop ldfle ar r0 Load new max value end DSP Algorithms 6 27 Fast Fourier Transforms FFTs 6 6 Fast Fourier Transforms FFTs 6 28 Fourier transforms are an important tool often used in digital signal processing DSP systems The purpose of the transform is to convert information from the time domain to the frequency domain The inverse Fourier tra
339. ed Fried of Advanced Computer Communications The hardware interface is relatively straightforward see Figure 8 12 The re ceive line is connected to both the INTO and IOF1 pins This triggers an inter rupt on the falling edge of the start bit The transmit line is connected to the IOFO pin and a pullup resistor As shown in Example 8 17 the receive sequence begins when the start bit triggers the external interrupt At the interrupt service routine Ry INTO timerO is loaded with a value that results in a delay of one half of the bit time The rou tine then loads the timer s interrupt vector enables it then exits to the main program When the timer triggers its interrupt Ry TMR INT the main body of the receive code executes Atthis time the line is in the middle of the start bit The CPU then samples IOF1 and verifies that the start bit has been read in If the start bit is verified the timer is then loaded with the full bit time and started The procedure then exits to the main program On successive timerO interrupts RyINTO the received bits are shifted into a storage area in memory until a byte is read in On the ninth interrupt if the stop bit is verified the routine executes a software trap to inform the main program ofthe byte reception If the stop bit is not verified the BAD STOP BIT subrou tine is called where the appropriate action is taken After the received byte is processed the external interrupt is then reenabled
340. ed memory is assigned to sysmem The switch tables are assigned to const Uninitialized variables are assigned to bss J initialized variables are assigned to cinit uH E E d If following system reset the program executes directly out of EPROM micro processor mode a separate assembly file holds the reset vector and possi bly other interrupt vectors The reset vector points to the address contained in the c_intOO symbol that the linker resolves with the beginning of the BOOT ASM routine from the RTS30 library The assembler assembles all asm files into their respective obj files Since each asm file may have a text section fragment for each function in the file its obj counterpart groups all the fragments into a single text section This ap plies to all sections in that file The results of the assembler process are multi ple obj files composed of single instances of all standard C sections In addi tion to the object files generated by the user the subsequent boot procedures require another obj file The boot asm file can be extracted from the RTS30 library and assembled separately into boot obj The boot obj is the first routine executed following reset It initializes the C environment by setting up the sys tem stack processing initialized variables setting up the page pointer and calling the main function While boot asm file is required for a C program other files may be extracted from the library such a
341. ee the 7MS320 Floating Point DSP Assembly Language Tools User s Guide for detailed information Development Support System Integration and Debug Tools There are four types of system integration and debug tools Simulator Simulates through software the operation of the C3x and can be used in C and assembly software development This productis current ly available forthe PC DOS and Windows and SPARC workstations See the TMS320C3x C Source Debugger User s Guide for detailed informa tion D XDS510emulator Performs full speed in circuit emulation with the C3x providing access to all registers as well as to internal and external memory It can be used in C and assembly software development and has the capa bility of debugging multiple processors This product is currently available for the PC DOS Windows and OS 2 and SPARC workstations This product includes the emulator board emulator box power supply and small computer system interface SCSI connector cables in the SPARC version the C3x C source debugger software and the JTAG cable Because C3x and C5x XDS510 emulators also come with the same emulator board or box you can buy the C3x C source debugger soft ware as a separate product called the C3x C Source Debugger Conver sion Software This enables you to debug C3x C4x C5x applications with the same emulator board The emulator cable that comes with the C5x XDS510 emulator is not compatible with the C3x
342. efine CS TCLOCK INT 1 FSYNC and SCLK are outputs define BPF_64 0 64 bits per frame define BPF_128 1 128 bits per frame define BPF_256 2 256 bits per frame define CS_CLOCK_SCLK 0 Clock source select SCLK define CS CLOCK XTAL1 1 Clock source select XTAL1 define CS CLOCK XTAL2 2 Clock source select XTAL2 define CS CLOCK EXT 3 Clock source select Ext define DIGITAL LOOPBACK 0 define ANALOG LOOPBACK 1 define LOOP_ENABLE 1 define LOOP_DISABLE 0 f DATA COMMAND MACROS BORK KK KK RK A kCK kCK KCK KCKCKCK KCK KCK KCK KCK KCK KCKCKCK KCKCKCK KCK KCK KCK KC k kk k ck k ck ck ck ck ckck OR sk x e x k amp f Output attenuation is 1 5 dB per unit integer value ui Attenuation dB pe ud define ATT O0 0 0 0 define ATT 1 B 1 5 define ATT 2 2 3 0 xf define ATT_3 3 4 5 define ATT 4 4 p 6 0 define ATT 5 5 7 5 define ATT 6 6 9 0 x define ATT 7 7 1045 if define ATT_8 8 yF 120 wy define ATT_9 9 1355 ae define A 10 10 fe T1520 Ef Analog Interface Peripherals and Applications 8 55 CS4215 Interface t
343. elect controlled write cycles In either case the WE input is driven by the C3x R W signal If sufficient fast gating is used 25 ns RAMs can be used As with RAM with OE control lines this approach works well only if a few banks of memory are implemented and if the chip select decode can be accom plished with only one level of gating If many banks are required to implement very large memory spaces bank switching can be used to provide for multiple bank select generation and still maintain full speed accesses within each bank Bank switching is discussed in detail in section 4 5 6 on page 4 15 Memory Interfacing 4 9 Wait States and Ready Signal Generation 4 5 Wait States and Ready Signal Generation 4 5 1 4 10 Wait states can greatly increase system flexibility and reduce hardware requirements The C3x can generate wait states on either the primary bus or the expansion bus both buses have independent sets of ready control logic This section discusses ready signal generation from the perspective of the primary bus interface However since wait state operation on the expansion bus is similar to that on the primary bus these discussions also pertain to expansion bus operation Ready signal generation is not included in discussions of the expansion bus interface See the TMS320C3x User s Guide for more information Wait states are generated on the basis of the Internal wait state generator DD External ready input RD
344. eneration 4 10 to 4 20 zero wait state to static RAMs 4 5 to 4 9 system control clock circuitry 1 3 internal circuitry current requirement factors of 12 5 internal bus operations 12 5 internal operations 12 5 quiescent 12 5 interrupt context switching 2 11 to 2 16 context restore for C3x 2 15 context save for C3x 2 13 correct programming of 2 9 prioritizing 2 10 service routines 2 9 5 16 example 2 10 software polling of 2 9 interrupts in C 5 16 to 5 18 inverse floating point 3 10 lattice filter structure of 6 18 lattice filters 6 18 linker 11 2 c option 4 92 4 95 cr option 4 92 4 96 switches to support C32 memory pools 4 73 literature 11 5 LMS algorithm filters 6 15 logical address 4 33 logical operations bit manipulation 3 2 bit reversed addressing 3 5 block moves 3 4 Index extended precision arithmetic 3 16 floating point format conversion 3 20 integer and floating point division 3 6 square root 3 13 looping 2 18 to 2 21 block repeat 2 18 single instruction repeat 2 20 low power mode wakeup example 5 7 to 5 8 MALLOC function C 1 matrix vector multiplication 6 24 memory C32 enhanced memory interface functional description 4 24 memory pool limitations 4 72 access C32 C 1 to C 6 allocation 16 bit dynamic 4 84 8 bit dynamic 4 76 8 bit static 4 78 in C programs C 2 banks address decode for multiple 4 64 4 65 zero wait state interface for 32 and 8 bit SRAM 4 75 zero wait state interface for 32
345. ent for the C30 equals 110 mA 12 2 2 Internal Operations Internal operations include register to register multiplication ALU operations and branches It does notinclude external bus usage or significant internal bus usage Internal operations add a constant 55 mA above the quiescent current Therefore the total contribution of quiescent current 110 mA and internal operations 55 mA is 165 mA During an RPTS instruction repeat single instruction activity other than the instruction being repeated is suspended therefore internal power supply current is related only to the operation per formed by the instruction being executed 12 2 3 Internal Bus Operations Internal bus operations include all operations that use the internal buses extensively such as internal RAM access every cycle No distinction is made between internal reads such as instruction or operand fetches from internal ROM or internal RAM banks and internal writes such as operand stores to internal RAM banks internally they are equal Since power consumption depends on the data value in the internal bus significant use of internal buses adds a data dependent factor to the power supply current TMSS320C30 Power Dissipation 12 5 Current Requirements for Internal Circuitry Pipeline conflicts use of cache fetches from external wait state memory and writes to external wait state memory all affect the internal and external bus cycles of an algorithm executing on th
346. ently used array in on chip RAM block 0 Method A Declare variable in a separate section 1 Declare the variable that is to be separated from the bss section in a separate file For example declare a 32 word array tapDelay in a file called array c as follows File ARRAY C int tapDelay 32 End of file 2 Declare the variable as extern in any file that makes a reference to it Consider the following file test c that makes a reference to the array declared in file array c as follows File TEST C extern int tapDelay void main void int i tapDelay i 0 End of file Programming Tips 5 13 Linking C Data Objects Separate From the bss Section 3 In the linker command file link this variable separate from the bss section in the SECTIONS section The following linker command file segment illustrates how to link the array tapDelay onto the C3x on chip dual access data RAM block 0 while linking the rest of the global and static variables into part of a similar data RAM block 1 File TEST CMD test obj array obj MEMORY RAMBO origin 0x809800 length 0x400 RAMB1 origin 0x809c00 length 0x400 SECTIONS bss gt RAMB1 tapdelayline array obj bss gt RAMBO End of file DD Method B Declare variable in a pragma DATA SECTION 1 Declare the variable that is to be separated from the bss section in
347. epends only on the size of data being transferred Memory Data STRB1 width size eem 9e ofa REI register 8bits 32 bits Logical address 23 to 0 Physical address 23 to 2 Memory address 14 to 0 8 bit data bus A14 A13 A12 e e e A1 NR A 1 A 2 STABO BT STRBO BO TMS320C32 9 S Oo lolol ofo olofo o o MA UDCHCDEDUDD 55555 ccc Toggle e E Ms tc CD wi b1 oh w1 b2 1h w1 b3 2h wi b4 3h e e e ENG Fc ERE 7FFDh gt 7FFEh ETE rr Memory address space Physical address shift 2 bits 8 bit memory width 2 The amount of shift in the physical connection between the C32 and the external memory depends only on the width of the memory bank uone sueJ sseJppy pue eoejieju AIOWAyy uoije sueJ sseyppy pue eoejiaju A10ul8JAl l d Figure D 10 Address Translation for 16 Bit Data Stored in 8 Bit Wide Memory CPU instruction STI RO 9 3FFFh DP 90h Memory map nogica aeg s Siny hw1 900000h i hw2 900001h hw3 900002h hw4 900003h IOSTRB e
348. equires that each ISR be named as follows void c intOn void n is the int number a C function that is an ISR The interrupt routine must not return a value and has no arguments The C compiler recognizes this naming convention and treats it as a normal ISR This means it performs a context save of the neces sary registers and returns from the routine via an RETI instruction A good practice is to include the interrupts in a separate file called ints c or something similar This allows a modular style simpler maintenance and software that is easy to understand Initialize the interrupt vector table using either C or assembly lan guage In microprocessor mode of C30 and C31 the first 0x40 addresses are reserved for the interrupt and trap vectors Address 0 zero holds the address of the reset routine If using the C linker option the RTS30 lib function boot asm takes care of defining the reset function but the vector table initialization is left to the user An assembly language routine might look like this file name is vectors asm Sect vectors a new section begins here word c int00 the address of the reset vector word c int01 the ISR for interrupt 0 Word c int02 the ISR for interrupt 1 etc end This routine creates a new section that is merely a list of addresses where the interrupt routines can be found It can be written in C by encapsulating each line in an asm st
349. er hand in the case of a very large number with e 127 the exponent of x 0 is 127 1 128 This causes the algorithm to yield 0 which is reasonable for handling that boundary condition Example 3 6 Inverse of a Floating Point Number Integer and Floating Point Division TITLE INVERSE OF A FLOATINGtPOINT NUMBER SUBROUTINE INVF THE FLOATING POINT NUMBER v IS STORED IN RO AFTER THE COMPUTATION IS COMPLETED 1 v IS ALSO STORED IN RO TYPICAL CALLING SEQUENCE LDF v RO CALL INVF ARGUMEN ASSIGNMENTS ARGUMENT FUNCTION mid RO v NUMBER TO FIND THE RECIPROCAL OF UPON THE CALL RO 1 v UPON THE RETURN X REGISTER USED AS INPUT RO REGISTERS MODIFIED RO R1 R2 R3 id REGISTER CONTAINING RESUL RO i CYCLES 35 WORDS 32 global INVF INVF LDF RO R3 gt V is saved for later ABSF RO 1 The algorithm uses v v EXTRACT THE EXPONENT OF v PUSHF RO POP R1 ASH 24 R1 The 8 LSBs of R1 contain the exponent of v x 0 FORMATION IS GIVEN THE EXPONENT OF v NEGI R1 SUBI 1 R1 Now we have tetl th xponent of x 0 ASH 24 R1 PUSH R1 POPF RI Now R1 x 0 1 0 2 tet1 Logical and Arithmetic Operations 3 11 Integer and Fl
350. er by loading code or patching code or to read an instruction with the objective of disassembling a range of program memory To support code execution from 16 and 32 bit memory the memory map add ma command includes a new type parameter that directs the debugger to treat text sections as 32 bit data While reading or writing text sections the debugger does the following Temporarily stores the configuration of the appropriate strobe control register Temporarily sets the data size to 32 bits E Reads or writes the targeted portion of the text section DD Restores the strobe control register to its previous value Memory Interfacing 4 73 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface The syntax for the memory map add command is ma address length type where address defines the starting address of a range of memory length defines the length of the memory range type identifies the read write characteristic of the memory range de pending upon one or more of the following keywords O R read only W write only WR or RAM read write PROTECT no access memory TX memory that stores text code section d m m m 4 7 5 TMS320C32 Configuration Examples Ths section describes the possible C32 memory interface configurations in cluding instructions on how to allocate buffers build link files and configure the debugger for each memory configuration 4 7 5 1 Two External
351. er data continuously between the serial port 0 receive register and the serial port 0 transmit register to create a digital loop back Synchro nize the transfer with the serial port 0 receive and transmit interrupts DMA source address 80804Ch DMA destination address 808048h DMA transfer counter 00000000h DMA global control 00000303h CPU DMA interrupt enable IE 00300000h Programming the DMA Channel 7 9 7 10 Chapter 8 Analog Interface Peripherals and Applications Analog interface peripherals are analog input output devices that interface di rectly to the C3x This chapter describes these devices and their applications in C3x based systems Topic Page 8 1 Analog to Digital Converter Interface to the TMS320C30 Expansion BUS 8 2 8 2 Digital to Analog Converter Interface to the TMS320C30 Expansion BUS 8 6 8 3 Burr Brown DSP101 2 and DSP201 2 Interface to TMS320C3x 8 10 8 4 TLC32040 Interface to the TMS320C3x 8 21 8 5 TLC320AD58 Interface to the TMS320C3x 8 30 8 6 CS4215 Interface to the TMS320C3x 8 39 8 7 Software UART Emulation for TMS320C3x 8 66 8 8 Hardware UART for TMS320C3x 8 70 8 1 Analog to Digital Converter Interface to the TMS320C30 Expansion Bus 8 1 Analog to Digital Converter Interface to the TMS320C30 Expansion Bus 8 2 Analog to digital co
352. er starts Boot loader execution is triggered by a high state on MCBL MP and a low on one low to high transition of RESET program how to load them to SRAM file out C Boot text section boot asm File1 text section File2 text section File1 Cinit section File2 Cinit section COFF format binary file o Sections text boot Cinit boot file b1 Bootloader control C boot code boot asm Bootloader control File1 data Bootloader control Intel hex format ASCII file EPROM ms EPROM Bootloader control C boot code boot asm File1 code File2 code Bootloader control File1 data File2 data Bootloader control 8 bits wide INTx pin during c intOOisthe execution entry point SRAM1 C boot code boot asm reading the boot table from one of three memory locations or from the serial port The on chip boot loader uses the CPU to assemble X individual bytes of the boot table and to load them directly into SRAM SRAM2 File1 data bss section 32 bi
353. er to the allocated space is also returned D free16 frees previously allocated space from the 16 bit memory pool DD bmalloc16 allocates 16 bit words from the 16 bit memory pool The al located words are aligned to a boundary that is suitable for the C32 s cir cular and bit reversed buffers a pointer to the allocated space is also re turned Lj SYSMEM16 SIZE an external label that contains the size in words of the 16 bit system memory pool 4 7 1 4 Memory Pool Limitations The C32 has only three strobes STRBO STRB1 and IOSTRB This means a programmer cannot have more than three memory pools one memory pool assigned to each strobe IOSTRB can hold only 32 bit data and can only ac commodate the 32 bit memory pool sysmem Conversely STRBO and STRB 1 can hold 8 16 and 32 bit data and can accommodate the 8 16 and 32 bit memory pools sysm8 sysm16 and sysmem All pointers and constants must be stored in memory configured to hold 32 bit data Hence the bss stack cinit and const sections mustreside in memory with data size configured to 32 bits 4 7 2 C Compiler and Assembler Switch 4 72 To create code forthe C32 the assembler and C compiler use the v32 version specification switch The following example demonstrates the use of this switch with the assembler and C compiler respectively asm30 v32 myfile asm cl130 v32 myfile c How TMS320 Tools Interact With the TMS320C32 s Enhanced
354. escription of Terms Involved In TMS320C32 Memory Interface For 16 bit wide memory 24 bit logical Multiple strobe signals STRBx B3 pin is assigned address as can select individual to address bit A 1 Logical memory map Seen by the bytes from physical For 8 bit wide memory addresses as seen CPU memory STRBx B3 and STRBx B2 by the 32 bit CPU pins are assigned to address Physical memory map valid addresses as presented on the proc essor s address pins 24 bit physical ad dress as present ed on the proces Sor s address pins i PRGW pin STRBO STRB1 control registers B RI and the PRGW pin control logical 32 bits wide to physical address mapping and data packing unpacking Address CS 16 bits TMS320C32 bits A 1 and A 2 Strobes Data size o Address bus SENS Address S Address 0 gt Address 5 o S E E CS z g i o x Data size 9 8 bits d a Data bus Dalai size Byte wide external 16 bits External data bus can memory devices STRBO control register be 32 16 or 8 bits wide STRB1 control register Memory width 16 bits for this example dSG ZED0ZESWL 8ui 0 Aowa Bureau Interfacing Memory to the TMS320C32 DSP 4 6 3 32 Bit Memory Configuration Design Examples The following sections describe examples of interfacing the C32 to 32 bit wide external memory from both the hardwa
355. f devices is not enabled until STRB goes low again In general bank switching is not required during writes because write cycles always exhibit an inherent one half H1 cycle setup of address information be fore STRB goes low When you use bank switching for read write devices a minimum of one half H1 cycle of address setup is provided for all accesses Therefore large amounts of memory can be accessed without requiring wait states or extra hardware for isolation between banks Access time for cycles with bank switching is the same as that for cycles without bank switching Ac cordingly full speed accesses can still be accomplished within each bank Memory Interfacing 4 15 Wait States and Ready Signal Generation 4 16 When you use bank switching to implement large multiple bank memory sys tems you must consider address line fanout loading Besides parametric specifications which must be accounted for ac characteristics are crucial in memory system design With large memory arrays which commonly require large numbers of address line inputs to be driven in parallel capacitive loading of address outputs is often quite large Because all C3x timing specifications are guaranteed upto a capacitive load of 80 pF using greater loads invalidates guaranteed ac characteristics It is often necessary to provide buffering for ad dress lines when using large memory arrays The ac timing specifications for buffer performance can then b
356. ferred to any memory address range within the memory map The blocks in the boot table are preceded by three control words block size destination address and strobe control register value The boot loader ends execution when it finds a 0 for the size of the next block At that point it initializes the three strobe control registers and branches to the first instruction of the first block For that reason the first boot table block always contains program information and not data For information about the boot loader operation see section B 3 Boot Loader Source Code Listing on page B 6 and the TMS320C3x User s Guide TMS320C32 Boot Loader Source Code Description Figure B 1 TMS320C32 Boot Loader Program Flowchart Boot loader execution entry caused by MCBL MP high after reset Peripheral pure AR7 Ad Stack is only two words deep and Exemifianctort Initialize I SP resides in the peripheral area of the xecull ar IR address flag PM memo map Y F A specific interrupt tells the bootloader where Senes IF to loo
357. fferent because it contains initialized variables Once the out file is generated it can be burned into a 16 or 32 bit wide EPROM and the program can start executing directly from that EPROM following reset in the microprocessor mode But if the initialized variables reside in the same EPROM they are not really variables since one cannot write to an EPROM device and actually change the values of those variables For that reason be fore user program execution begins the boot asm library routine copies the initialized variables from the EPROM cinit section to the SRAM bss section one array of data at a time Figure 4 37 on page 4 89 shows that the cinit sec tion is divided into individual array records each array has a length data con tent and destination address in the SRAM bss section The bss section is the final destination for initialized variables while the cinit EPROM section is a temporary holding place for use before power up reset The cinit section also stores the c cr linker option selection for use in the later stages of the boot process Booting a TMS320C32 Target System in a C Environment 4 8 2 Loading the COFF File to the Target System When the COFF file is loaded into the DSP target system program and data content as well as control information are extracted Then the control infor mation is usedto place the program data content in target memory Some con trol information embedded in the COFF file ma
358. file format such as Intel Hex The EPROM programmer uses the converted files to program one or more EPROMSs that can be inserted into the DSP target board If the linker c option is used to create the COFF file ROM model the hex utility copies the cinit section directly into the programmer object file without processing its content In other words the cinit section in the programmed EPROM contains the initialized data as well as destination addresses and lengths in bss for individual cinit data arrays To start program execution from EPROM at power up the DSP must be configured in the microprocessor mode by pulling the MCBL MP pin low Triggered by the low to high transition of the RESET pin the DSP executes the reset vector fetch read cycle The reset vec tor points to the boot asm routine which is executed next The linker c option sets a control bit in the cinit section of the COFF file When the boot asm program executes the cinit section it checks the c cr control bit The c option ROM model causes boot asm to copy the contents of each array within the cinit section to its destination in the bss section mapped to SRAM The initialized variables must be copied from EPROM to SRAM at the beginning of program execution because they cannot be modi fied in EPROM variable data must be changeable during program execution Memory Interfacing 4 95 Booting a TMS320C32 Target System in a C Environment 4 8 4 2
359. fooo 11717 ip Physical address STAEG A17 A13 Ao 65534 65528165527 65526 65525 STRAT K 65535 w 6553265531 65530 65529 ERS ree 7FFFh 6553565534165533 amp a a amp o o o o a a a a ra tc tc ra E m E E CD CD CD CD RI dSd ZED0ZESWL eui 0 Aiowayy Bureau Interfacing Memory to the TMS320C32 DSP 4 6 5 2 One Bank Two Strobes Address Translation for Data Size 32 and 8 Bits Figure 4 26 illustrates how a single physical block of memory can be split into two separate logical halves one with 32 bit data and the other with 8 bit data The access to each half is controlled by a separate strobe control register with corresponding memory width and data size fields Another STRBO control reg ister field STRB CONFIG is set to 1 to indicate that both STRBO and STRB1 are mapped to the same set of four STRBO pins The high memory address pin in this case A14 selects between the two halves of the memory For this example the C32 address pin A17 drives the memory pin A14 The state of the A17 bit of the physical address is derived from the logical ad dress logical as seen by the instruction The state of the A17 bit also depends on the logical physical address shift as determined by the size of the program data that is being accessed In this case the logical STRBO address range drives the physical address bit A17 to 0 Similarly the logical STRB1 range drives the physical address bit A17
360. format that differs from the IEEE standard This section briefly describes the two formats and presents software routines that show how to make conversions between the two formats C3x floating point format 8 1 23 e S f IEEE TMS320C3x Floating Point Format Conversion In a 32 bit word representing a floating point number in the C3x the first eight bits correspond to the exponent expressed in twos complement format There is one bit for sign and 23 bits for the mantissa The mantissa is ex pressed in twos complement form with the binary point after the most signifi cant nonsign bit Since this bit is the complement of the sign bit s it is sup pressed the mantissa actually has 24 bits A special case occurs when e 128 In this case the number is interpreted as 0 independently of the values of s and f which are set to 0 by default The values of the represented numbers in the C3x floating point format are as follows 2 x 01 f ifs 0 2 x 10 f ifs 1 0 ife 128 IEEE floating point format 1 8 23 S e f The IEEE floating point format uses sign magnitude notation for the mantissa and the exponent is biased by 127 In a 32 bit word representing a floating point number the first bit is the sign bit The next eight bits correspond to the exponent which is expressed in an offset by 127 format the actual exponent is e 127 The following 23 bits represent the absolute valu
361. g the graphs in the previous two sections For exam ple if a nominal scale factor of 0 85 is used and the system uses zero wait states with two cycles between accesses on both the primary and expansion buses the current contribution from the two buses is as follows Primary 0 85 x 80 mA 68 mA Expansion 0 85 x 40 mA 34 mA 12 3 4 Capacitive Load Dependence Once you account for cycle timing and data dependencies calculate and apply the capacitive loading effects Figure 12 10 shows the scale factor to apply to the current values obtained above as a function of actual load capacitance if the load capacitance presented to the buses is less than 80 pF In the previous example if the load capacitance is 20 pF instead of 80 pF a scale factor of 0 84 is used yielding Primary 0 84 x 68 mA 2 57 12 mA Expansion 0 84 x 34 mA 28 56 mA The slope of the load capacitance line in Figure 12 10 is 26 normalized IDD per pF While this slope may be used to interpolate scale factors for loads greater than 80 pF the C30 is specified to drive output loads of less than 80 pF Interface timings cannot be ensured at higher loads Figure 12 10 Current Versus Output Load Capacitance 12 16 g 100 o S 9 S 95 oO g 90 S g 3 85 o Il 80 ko c s B 75 0 10 20 30 40 50 60 70 80 Output load capacitance pF Calculation of Total Supply Current 12 4 Calculation of T
362. g transferred uoge sueJ sseJppy pue eoejie u LOWW uoije sueJ sseyppy pue eoejiaju AIOWAyy e a Figure D 6 Address Translation for 32 Bit Data Stored in 16 Bit Wide Memory CPU instruction STI RO 3FFFh DP 88h Memory map d UM uus SR wi 880000h i w2 880001h w3 880002h i w4 880003h IOSTRB e Oo 2 e w16381 88FFFCh w16382 88FFFDh STRBO w16383 88FFFEh emm o ES rrr Logical address shift 0 bits 32 bit data size Notes 2 The amount of shift in the physical STRB STRBO config control register STRBO Logical address 23 to 0 Physical address 23 to Memory Data FIDE BDDDUDECDE i 2 width size 16 bits 32 bits ES Noc oc EE HE d ule HE Data A14 A14 Data A A13 A13 amp A12 e eb eo e e E 3 e m S 8 me A1 A1 AO AO csp Ato STRBO_B2 STRBO_B1 STRBO_BO T e en a o o tn a oc ia bE bE ep CD wi Is Oh w1 ms th w2 Is 2h w2 ms 3h e e e w16383 Is 7FFCh w16383 ms 7FFDh A 7FFE
363. gital Signal Processor data sheet These are associated with most algorithms running on the device unless data output is excessive lfanextremely conservative approach is desired use the maximum value Maximum Current Requirement The maximum current requirement is 600 mA and occurs only under worst case conditions These include writing alternating data AAAAAAAAh to 55555555h out of both external buses simultaneously every cycle with 80 pF loads and running at 33 MHz TMS320C30 Power Dissipation 12 3 Power Dissipation Characteristics 12 1 3 Determining Algorithm Partitioning Each part of an algorithm has its own pattern with respectto internal and exter nal bus usage To analyze the power supply current requirement you must partition an algorithm into segments with distinct concentrations of internal or external bus usage Analyze each program segment to determine its power supply current requirement You can then calculate the average power supply current from the requirements of each segment of the algorithm 12 1 4 Test Setup Description All C30 supply current measurements were performed on the test setup shown in Figure 12 1 The test setup consists of a C30 8K words of zero wait state Cypress Semiconductor SRAMs CY7C186 25PC and resistor capacitor RC loads on all data and address lines A Tektronix current probe P6042 measures the power supply current in all Vpp lines of the device The supply
364. he DSP by a system reset after all supply voltages are stable The digital function blocks are initialized by pulling down DIGPD for several microseconds After the rising edge of DIGPD the device resumes normal operation When DIGPD is low the TLC320AD58C digital function blocks are shut down and power con sumption is reduced However if power down mode is not required this signal can be tied to ANAPD In both cases refer to the TI Data Acquisition Circuits Data Book for setup timing requirements All digital inputs and outputs of the C3x and the TLC320AD58C are 5 V TTL compatible To reduce ringing and overshot a serial damping resistor 50 Q is recommended for the master clock signal Analog Interface Peripherals and Applications 8 31 TLC320AD58 Interface to the TMS320C3x Figure 8 10 Interface Between the TMS320C3x and the TLC320AD58C 8 32 RESET ANAPD RESET 12 288 MHz D MCLK lt TOUTO VSS n DIGPD lt XFO CMODE CLKIN 49 152 MHZ Dypp O SYNC CLUKX Dypp OQO MODEO SCLK CLKR TEST1 2 LRCLK FSX MODE1 FSYNC gt FSR MODE2 DOUT gt DR m TLC320AD58 TMS320C3x Dyss The C3x can be configured to receive a maximum of 32 bits of data per word But the TLC320AD58C transmits a total of 64 bits after the FSYNC pulse appears This forces the DSP to read the left and right channels back to back To accomplish this the
365. he average is calculated as lavg 0 95 210 mA 0 05 280 mA 213 5 mA From the thermal characteristics specified in the C30 data sheet it can be shown that this current level corresponds to a case temperature of 43 C This temperature meets the maximum device specification of 85 C and hence requires no forced air cooling TMS320C30 Power Dissipation 12 25 Example Supply Current Calculations 12 5 4 Experimental Results A photograph of the power supply current for the FFT is shown Figure 12 14 During the FFT processing the measured current varies between 180 and 220 mA The peak of the current during external writes is 270 mA and the average current requirement as measured on a digital multimeter is 200 mA The calculations yield results that are extremely close to the actual measured power supply current Figure 12 14 Photo of Ipp for FFT 400 300 200 100 mA 500 us div Note Input clock frequency 33 MHz voltage level 5 0 Vpp 12 26 Appendix A TMS320C32 Boot Table Examples The C32 boot loader loads programs received from standard memory devices orthrough the serial port These programs have a particular data stream struc ture called a boot table This appendix shows examples of different C32 boot tables in 32 16 and 8 bit wide ROM that are transmitted through the serial port Figure A 1 through Figure A 4 show four instances of the boot table each containing four blocks The
366. he crystal at a low power level This is important at higher frequencies where crystals are physical ly thinner and therefore have lower power dissipation limits Thelow pass RC networks formed by the crystal and load capacitors tend to filter transient noise spikes giving the circuit good noise immunity Figure 9 7 Pierce Circuit Ideal Operation P4 Crystal e o Inverting amplifier Cy 7m zx Co l l 180 90 I gt 90 above series resonance 90 at series resonance lt 90 above series resonance 9 3 1 Oscillator Operation The ideal circuit operates in the following manner An input signal to the amplifi er appears at the output phase shifted by approximately 180 If itis assumed that at a certain frequency the impedance of C is much greater than R4 then the phase shift of this RC network introduces another approximately 90 phase shift Atthe series resonant frequency the crystal appears to be a resistor and forms another RC network with Co If the impedance of C is much greater than Pierce Oscillator Circuit the series resistance Ry of the crystal this network provides another 90 phase shift The total phase shift around the loop is now 180 90 90 360 This phase shift meets one of the conditions for os cillation If the gain of the amplifier is high enough to overcome the losses in the R4 C crystal Ry C2 network for a total loop g
367. he expansion bus Although you can use both the primary bus and the expansion bus to inter face to a wide variety of devices those most commonly interfaced to these buses are memory devices This section presents detailed examples of memory interface Zero Wait State Interface to Static RAMs 4 4 Zero Wait State Interface to Static RAMs Zero wait state read access time for the C3x is determined by the difference between the cycle time and the sum of the delay time for the interface signal H1 low to address valid and the data setup time before the next H1 low For more information see the appropriate TMS320C3x Digital Signal Processor data sheet tc H l en suya where tc H H1 H3 cycle time ld H1L A H1 low to address valid tsu D R data valid before next H1 low read For example for full speed zero wait state interface to any device the 60 ns C3x requires a read access time of 30 ns from address valid to data valid For most memories access time from a chip select pin is the same as access time from address valid therefore itis possible to use 30 ns memories at full speed with the C3x 33 This requires that there are no delays between the processor and the memories However because of interconnection delays and because some gating is normally required for chip select generation this is usually not the case Slightly faster memories are required in most systems There are two distinct categories amo
368. his is shown in Example 2 6 with no operations per formed NOPs taking the place of the unused instructions The trade off is more instruction words for less execution time Example 2 6 Delayed Branch Execution TITLE DE SKIP LAY LDF BGED LDFN SUBF NOP MPYF LDF S R 3 1 R ED BRANCH EXECUTION AR1 5 R2 H Load contents of memory to R2 KIP If loaded number gt 0 branch delayed 2 R1 If loaded number 0 load it to R1 0 R1 Subtract 3 from R1 Dummy operation to complete delayed branch 5 R1 E Continue here if loaded number 0 1 R3 n Continue here if loaded number gt 0 Program Control 2 17 Repeat Modes 2 6 Repeat Modes 2 6 1 Block Repeat The C3x supports looping without any overhead For that purpose there are two instructions RPTB which repeats a block of code and RPTS which re peats a single instruction There are three control registers repeat start ad dress RS repeat end address RE and repeat counter RC These contain the parameters that specify loop execution See the Program Flow Control chapter in the TMS320C3x User s Guide for a complete description of RPTB and RPTS The code automatically sets RS and RF registers RPTB and RPTS when instructions are excluded however you must set the repeat counter reg ister Example 2 7 shows an application of the block repeat construct In this exam ple an array of 64 elemen
369. his value is reused for all bin calculations and is kept in a register Cd If circular or bit reversed data storage is used the data and twiddle buffers are forced to 2N word boundaries In addition the circular addressing registers are consumed Since the overhead of checking and reloading the buffer pointers is minimal and allows non 2N sizes explicit pointer testing is used in SFFT ASM 6 8 13 Using This Code With C To use the functions in this code with a high level language such as C you must perform context save and restore operations at the beginning and end of each function 6 8 14 TLC32040 ADC and DAC Considerations The application file SFFT ASM is written to use a TLC32040 analog interface chip AIC connected as used in a TMS320C31 DSP Starter Kit or DSK TMDS3200031 Further documentation for the DSK is available in the DSK or by downloading from the Texas Instruments FTP site Files Location Main TMS320 FTP mirror site ftp ftp ti com mirrors tms320bbs C3x DSK files subdirectory ftp ftp ti com mirrors tms320bbs c3xdskfiles 6 8 15 SFFT Summary L A time signal is comprised of a series of samples Each sample is an impulse Li The time signal is a time summation of a series of impulses Li The frequency spectra of a single impulse at T 0 is trivial to calculate since it is only a REAL component in each frequency bin whose magnitude is that of the impulse The frequency spectra of a signa
370. hmetic The carry bit is affected by the arithmetic operations of the arithmetic logic unit ALU and by the rotate and shift instructions It can also be manipulated direct ly by setting the status register to certain values For proper operation the overflow mode bit should be reset OVM 0 so that the accumulator results are not loaded with the saturation values Example 3 8 and Example 3 9 show 64 bit addition and 64 bit subtraction The first operand is stored in regis ters RO low word and R1 high word The second operand is stored in R2 and R3 The result is stored in RO and R1 Example 3 8 64 Bit Addition ITLE 64 BIT ADDITION TWO 64XBIT NUMBERS ARE ADDED TO EACH OTHER PRODUCING A 64tBIT RESULT THE NUMBERS X R1 RO AND Y R3 R2 ARE ADDED RESULTING IN W Rl1 R0 R1 RO R3 R2 _ M R1 RO ADDI R2 RO ADDC R3 R1 Extended Precision Arithmetic Example 3 9 64 Bit Subtraction ITLE 64 BIT SUBTRACTION TWO 64 BIT NUMBERS ARE SUBTRACTED FROM EACH OTHER PRODUCING A 64 BIT RESULT THE NUMBERS X R1 R0 AND Y R3 R2 ARE SUBTRACTED RESULTING IN W Rl R0 R1 RO R3 R2 R1 RO SUBI R2 RO0 SUBB R3 R1 When two 32 bit numbers are multiplied a 64 bit product results The proce dure for multiplication i
371. i Gi Clock Oscillator and Ceramic Resonators 9 19 Design Considerations 9 4 5 Startup Time Figure 9 15 shows that when the oscillator starts low amplitude oscillations gradually build until the linearity limit of the amplifier is reached You experi ence this startup time at power up Maximizing loop gain minimizes the startup time for the oscillator Startup time depends on the external components used but generally requires at least 100 ms after power up for the oscillator to stabilize For this reason a reset delay of 150 200 ms is recommended following power up Figure 9 15 Oscillator Startup Power applied VDD VDD OV Oscillator output 9 4 6 Frequency Temperature Characteristics of Crystals 9 20 The actual operating frequency of a crystal depends on temperature The ex tent to which frequency changes with respect to temperature strongly relates to the cut of the crystal AT and SC cut crystals behave differently from DT CT and BT cut crystals Even slight changes in the cut angle of the crystal can strongly affect the frequency temperature characteristics Most crystals available in the frequency range of interest for DSPs are AT cut crystals The frequency temperature characteristic for AT cut crystals is a third order function similar to that shown in Figure 9 16 This graph shows the general temperature frequency behavior of AT cut crystals Similar informa tion is readily available
372. ible the block repeat is interruptible Example 2 9 shows an application of the single repeat construct In this ex ample the sum of the products of two arrays is computed The arrays are not necessarily different If the arrays are a i and b i each of length N 512 then register RO contains this quantity after computation a 1 b 1 a 2 b 2 a N b N The value of the RC is specified to be 511 in the instruction If RC contains the number N the loop is executed N 1 times Repeat Modes Example 2 9 Loop Using Single Repeat ITLE LOOP USING SINGLE REPEAT d THIS CODE SEGMENT COMPUTES SUM a i b i FOR i 1 to N LDI ADDR1 ARO E ARO points to array a i LDI ADDR2 AR1 AR1 points to array b i LDF 0 0 RO0 H Initialize RO MPYF3 ARO 1 AR1 1 R1 Compute first product RPTS 511 H Repeat 512 times MPYF3 ARO 1 AR1 1 R1 Compute next product ADDF3 R1 R0O RO H and accumulate the H previous one ADDF R1 RO j One final addition Program Control 2 21 Computed GOTOs 2 7 Computed GOTOs Itis occasionally convenient to select the subroutine to be executed during run time and not during assembly The C3x s computed GOTO instruction sup ports this selection The computed GOTO is implemented using the CALLcond instruction in the register addressing mode This instruction uses the contents of the register as the a
373. ical connection between the C32 and the external memory depends only on the width of the memory bank uoge sueJ sseJppy pue eoejieju AIOWAyy 12 pin connector dimensions 10 9 16 8 bit memory configuration design examples 4 41 data size equals memory width 4 43 data size is greater than memory width 4 45 data size is less than memory width 4 47 16 bit dynamic memory allocation 4 84 32 bit memory configuration design examples 4 35 data size equals memory width 4 35 data size is less than memory width 4 38 8 bit static memory allocation 4 78 A law compression 6 5 expansion 6 6 adaptive filters 6 15 addition example extended precision arithmetic 3 16 address space segmentation 4 12 AIC initialization AIC reset 8 21 C31 timer initializing 8 22 initializing AIC 8 24 primary communications 8 25 data format 8 25 mode selection 8 25 secondary communications 8 25 control register bit fields 8 26 data format 8 26 serial port initializing 8 23 algorithm partitioning to determine power supply requirement 12 4 algorithms DSP 6 1 to 6 102 analog to digital converters ADC interface to the C30 expansion bus 8 2 to 8 5 Index ANDing of the ready signals 4 11 application oriented operations adaptive filters 6 15 companding 6 2 to 6 6 fast Fourier transforms FFT 6 28 FIR filters 6 7 IIR filters 6 9 lattice filters 6 18 matrix vector multiplication 6 24 arithmetic operations bit manipulation 3 2 bit reversed addressing 3 5 b
374. icensing agreement with Texas Instru ments The kit contains host or PC source and object code which lets you tailor C30 EVM like capabilities to your C3x system through the SM74ACT8990 test bus controller TBC The EPK can be used in such applications as program download for system self test and initialization or system emulation and debug to feature resident emulation support EPK software includes the TI high level language HLL debugger in object as well as source code for the TBC communication interface The HLL code is the windowed debugger found with many TI DSP simulators EVMs and emulators With the EPK the HLL user interface can be ported directly to the system board The source code for the TBC communication interface consists of such commands as read write memory run stop and reset that communicate with the C3x device Using the EPK reduces system and development cost and speeds time to market For more information on the kit call the DSP hotline at 281 274 2320 11 1 2 TMS320 Third Parties The TMS320 family is supported by product and service offerings from more than 100 independent vendors and consultants known as third parties These support products take various forms both software and hardware from cross assemblers simulators and DSP utility packages to logic analyzers and emu lators Additionally TI third parties offer more than 150 algorithms that are available for license through the TMS320 software coope
375. identical to that described for Figure 9 8 The second inverter is added as a buffer and a waveshaping device Since the output of the crystal is sinusoidal the output of the first inverter also is sinusoi dal The second inverter provides a rail to rail square wave output at the oscillation frequency to drive the microprocessor clock Pierce Oscillator Circuit 9 3 2 Pierce Oscillator Configuration for the TMS320C30 and TMS320C31 The C3x DSPs have two options for clocking the processor Lj Divide by 2 operation of an externally supplied clock L Divide by 2 operation using the internal oscillator To use the C3x internal oscillator connect the crystal across the X2 CLKIN and X1 pins of the C30 and C31 the C32 does not support the internal oscil lator option The C3x oscillator circuitry with the exception of the crystal and the load ca pacitors is integrated into the processor Figure 9 10 shows the C3x oscilla tor circuitry which is similar to the Pierce integrated circuit oscillator shown in Figure 9 9 On the C3x the waveshaping inverter l2 takes its input from the input side of the inverter being used as the amplifier I4 rather than from the output as in the Pierce oscillator This has little effect on the oscillator other than generating the digital complement of the clock that is generated in the cir cuit of Figure 9 9 Also the feedback resistor in Figure 9 9 is integrated into the C3x as an active loa
376. ilter 2 Nt1 BK length of filter N REGISTERS USED AS INPUT R4 ARO AR1 RC BK REGISTERS MODIFIED RO R1 R2 R5 ARO AR1 RC REGISTER CONTAINING RESULT RO PROGRAM SIZE 11 words EXECUTION CYCLES 13 3N FIR IIR and Adaptive Filters Example 6 8 Adaptive FIR Filter LMS Algorithm Continued H setup i 0 Uext LMS ldf ar6t r5 Get desired sample mpyf3 ar0 arlt 1 r0 h n N 1 x n N 1 RO E subf Et2 X2 T 2 init 52 Initialize RO LMS MPYF3 ARO AR1 RO h n Nt1 x nt Nt1 gt RO LDF 0 0 R2 Initialize R2 E Initialize R1 MPYF3 AR1 1 R4 R1 x nt Nt1 tmuerr R1 ADDF3 ARO 1 R1 R1 h n Nt1 x nt Nt1 tmuerr gt R1 FILTER AND UPDATE 1 lt I lt N RPTB LOOP 7 Set up the repeat block Filter MPYF3 AR0 1 ARI1 RO h n Nflti x nt Ntiti gt RO B ADDF3 RO R2 R2 Multiply and add operation B H UPDATE MPYF3 AR1 1 R4 R1 x n Nt Ntlti tmuerr gt R1 B STF R1 ARO 1 R1 t h nt 1 Nt1 it1 LOOP ADDF3 ARO 1 R1 R1 A h n N t1 ti x nt N 14i 3 tmuerr t R1 ADDF3 R0O R2 R0 H Add last product STF R1 tARO 1 h n 0 x n tmuerr gt h n 1 0 RETURN SEQUENCE RETS H Return end end DSP Algorithms 6 17 Lattice Filters 6 3 Lattice Filters The lattice form is an alternative way
377. imensions for the 12 Pin Emulator Connector 10 5 Mechanical Dimensions for the 12 Pin Emulator Connector The C3x emulator target cable consists of a 3 foot section of jacketed cable an active cable pod and a short section of jacketed cable that connects to the target system The overall cable length is approximately 3 feet 10 inches Figure 10 7 and Figure 10 8 show the mechanical dimensions for the target cable pod and short cable Note that the pin to pin spacing on the connector is 0 10 inches in both the X and Y planes The cable pod box is nonconductive plastic with four recessed metal screws Figure 10 7 Pod Connector Dimensions Emulator cable pod p Connector Short jacketed cable See Figure 10 8 Note All dimensions are in inches and are nominal unless otherwise specified 10 8 Mechanical Dimensions for the 12 Pin Emulator Connector Figure 10 8 12 Pin Connector Dimensions gt 0 20 A Cable y Connector side view 0 10 k Key pin 8 1 1 A Blocked Pd key 0 70 Cable L 0 10 y Connector front view Pins 1 3 5 7 9 11 Pins 2 4 6 8 10 12 Note All dimensions are in inches and are nominal unless otherwise specified XDS510 Emulator Design Considerations 10 9 Diagnostic Applications 10 6 Diagnostic Applications For system diagnostic application
378. ing this information you can deter mine the device s power dissipation and in turn calculate thermal manage ment requirements Topic Page 12 1 Power Dissipation Characteristics sees 12 2 12 2 Current Requirement for Internal Circuitry 12 5 12 3 Current Requirement for Output Driver Circuitry 12 9 12 4 Calculation of Total Supply Current i 12 17 12 5 Example Supply Current Calculations eee 12 24 12 4 Power Dissipation Characteristics 12 1 Power Dissipation Characteristics Generally power supply current requirements are related to the system for ex ample operating frequency supply voltage temperature and output load As devices become more complex the specification must also be based on what the device does CMOS devices inherently draw current only during switching through the linear region Therefore the power supply current is related to the rate of switching Furthermore since the output drivers of the C30 are specified to drive direct current dc loads the power supply current resulting from exter nal writes depends not only on switching rate but also on the value of data writ ten 12 1 1 Power Supply Factors The power supply current consists of four basic factors D Quiescent current Internal operations Internal bus operations DD External bus operations 12 1 2 Power Supply Consumption Dependencies The power supply
379. inker c Option System reset RESET Low to high transition of the RESET pin while in microprocessor mode causes the MP CPU to execute a single read cycle to fetch A CPU VERENE the reset vector i NC N X MX The hex utility converts the The EPROM programmer burns The CPU uses the reset vector to binary COFF filetoa standard the 32 bit EPROM device with branch to the reset routine the C format ASCII file that an the EPROM programmer object boot code in a C program EPROM programmer can file understand file out file b1 EPROM Ne g c_int00 Reset vector File0 File0 vectors vectors 4 File0 vectors C Boot C Boot c intOO is the C Boot l text section code execution code boot asm boot asm entry point boot asm Filet Filet Filet text section code code i EPROM i File2 c c File2 programmer gt File2 text section code code File1 File1 File1 Cinit section data cntrl data cntrl File2 File2 File2 Cinit section data cntrl data cntrl COFF format Intel hex format 32
380. ipped to provide a ready signal but cannot respond quickly enough to meet the C3x s timing requirements Specifically if these devices normally indicate a ready condition and respond when accessed with a wait state until they are ready using the logical AND of the two ready signals lowers the chip count in the system In this case the internal wait counter provides wait states initially and becomes ready after the external device has had time to send a not ready indication The internal wait counter then remains ready until the external device also becomes ready which terminates the cycle In addition performing an AND of the two ready signals can extend the number of wait states for devices that already have external ready logic implemented but require additional wait states under certain circumstances 4 5 3 External Ready Signal Generation The technique for implementing external ready generation hardware depends on the characteristics of the system The optimum approach to ready signal generation varies depending on the relative number of wait state and non wait state devices in the system and on the maximum number of wait states required for any one device The approach discussed here is general enough for most applications and can easily be modified and applied to many different System configurations Memory Interfacing 4 11 Wait States and Ready Signal Generation 4 12 Ready signal generation involves the following steps 1
381. irely to Ry The voltage divider formed by the crystal and C influences the loop gain As the impedance of the crystal becomes larger the loss of gain due to the voltage divider becomes greater Low loop gain causes the oscillator to take longer to start up and prevents oscillation if the overall loop gain falls below 1 Higher crystal series resistance also reduces the overall oscillator circuit Q resulting in poorer frequency stability For these reasons itis desirable to use the lowest Rx possible Crystals with series resistance of 40 ohms or less are recom mended 9 4 2 Load Capacitors In the Pierce circuit used on the C3x the load capacitors have a strong effect on how far above the series resonant frequency the crystal oscillates The crystal s shunt terminal capacitance Co is considered part of the crystal s external load capacitance as far as the frequency controlling elements C and Ly are concerned A parallel resonance oscillator circuit operates at the frequency where the reactances of the crystal Cx and Ly cancel the reactances from the load Co C4 Cz Consequently changes in the external load capacitance cause the oscillator to change frequency to compensate for the phase change The following formula gives an approximate value for the frequency shift from the series resonant frequency fsCo where r Co and C Ci C At 370 6 C The derivative of this formula as shown below is useful for determining
382. ith a resulting setup time For the 60 MHz device the RDY signal must become valid at least 17 ns before every falling edge of the H1 clock In the 0 wait state cycle the address and strobe signals become valid 8 ns from the falling edge of H1 An additional 5 ns are needed for a single pass through a fast combinational logic device for a total setup time of the resulting RDY signal equal to 20 ns This leaves 3 ns for board delays and a modest safety factor For the 1 and 3 wait state cycles the bank decode and strobe signals do not directly drive the RDY signal They are instead combined into the STRBO BANK23 signal that when active releases the clear condition on the 3 register delay chain driven by the H3 clock The register chain is then free to propagate a high state at the rate of one register per clock cycle The two taps in the register chain at the first and third registers representing one wait state and three wait states respectively are ORed with their corresponding bank select signals to resultin the RDY B23YES signal synchronous to H1 H3 clocks The RDY B23YES leading edge 10 ns delay is caused by two passes through a fast PAL9 device such as a 22V10 The trailing edge of this signal is caused by bank 2 or bank 3 decode circuits going inactive after the RDY sig nalis recognized by the processor The address decode 8 ns plus two passes through the PAL 5 5 ns combine for a total delay of 18 ns that can cut into the next
383. itialize R4 to zero R4 SGCRO SINIT1 R7 Reset and R7 SPCXO A initialize serial port R7 SPCRO initialize serial port SINITO R7 Reset and R7 SGCRO initialize serial port Analog Interface Peripherals and Applications 8 23 TLC32040 Interface to the TMS320C3x 8 4 4 Initializing the AIC Once the C31 supplies MCLK initializes its serial port and resets the AIC you caninitialize the AIC to a specified sample rate The AIC sampling rate is deter mined by the values of two registers Tx counter A and Tx counter B in the AIC s transmit and receive sections These values are loaded into the respec tive counter whenever the counter counts down to 0 The Tx counters A and B determine the D A conversion timing The Rx counters A and B determine the A D conversion timing For more information see the TLC32040 AIC Data Sheet The formula for the conversion frequency is given in Equation 8 1 Equation 8 1 Conversion Frequency MCLK Conversion frequency 2XA XB To ensure that the switched capacitor lowpass and bandpass filters meet their transfer function characteristics the frequency of the clock inputs of the switched capacitor filter must be 288 kHz Otherwise the upper and lower cut off frequencies of the lowpass and bandpass are scaled accordingly Equation 8 2 shows the switched capacitor filter frequency Equation 8 2 Switched Capacitor Filter Frequency 8 24 SCF Clock _ freq
384. its are retrieved and con catenated with the lower 16 bits during the second cycle The C32 s 32 bit memory fetches are identical to those of the C30 and C31 In summary the C32 memory interface parallel bus implements three mutual ly exclusive address spaces that are distinguished through the use of three separate control signals see Figure 4 32 STRBO and STRB1 support 8 16 and 32 bit data access in 8 16 and 32 bit wide external memory and 32 bit program access in 16 32 bit wide external memory IOSTRB address space supports 32 bit data program access in 32 bit wide external memory Internally the C32 has a 32 bit architecture accordingly the memory inter face packs and unpacks the data accessed Three strobe control registers ma nipulate the variable width memory interface of the C32 See the TMS320C3x User s Guide for a detailed description of the C32 memory inter face How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface Figure 4 32 TMS320C32 Memory Address Spaces 32 bit CPU Strobe control registers 8 16 32 bit data in TMS320C32 STRBO 8 16 32 bit wide memory Program in 16 32 bit wide memory peeps 8 16 32 bit data in STRB1 8 16 32 bit wide memory __ Program in 16 32 bit wide memory Memory gt interface IOSTRB 32 bit data in 32 bit wide memory Program in 32 bit wide memory 4 7
385. k for the boot table N v pl AR3 Current boot table read pointer Subroutine Pr Tiens pointer for SESS UTE t Read strobe pointer reading boot set handshake flag Pm AR2 table control force boot strobe Read str words R2 strobe value m e as x Itlallz 5 Process first byte serial port P Rs M A A f SRC Strobes are saved in three DMA peripheral memory eae ee rope registers and are not loaded until the end of the width registers bootload process Branch to user program Y v Y first instruction of the Process block size 9 RC 9 Se first boot table block Read 22 Current 0 2s cas a Load three Y NA eng o strobe control Sissi o E 5 registers N z 3 I Block destination g Execution Start e One word address flag lq amp of program IRO Y a or data o 4 Destination Memory co E N address 5 fend v S value www IR1 M Eus ARS wd a ums z IR1 4 AR5 5 2o tir g Execution ARN w ES g start address Destination 5 aS STRB go 5 AR4 pointer y is 22 E v Best 8 c Ka E TRB ead m 2 ol me d Destination STRB 9 R4 Value E SRC 7 memory p R3 Data ae width Vv size R5 Select read ARI gt R3 R5 x Data SRC size memory width t Handshake mode is enabled by setting the IOXFO bit of IOF register to 1 when INT3 and any of INT2 INT1 or INTO signals are asserted following reset Note Shaded boxes indicate operations white boxes
386. kk Ck kk kk kk kk kk kk ke ke ke ko ke ke ke ke e eoe ee e e x x f typedef volatile int VI typedef volatile float VF typedef VF volatile VPVF typedef VI volatile VPVI KK AK KK kk kk Ck Ck Ck Ck Ck kk Kk Ck Ck Kk Ck Ck Ck Ck Ck Kk Ck kk Ck kk kk kk kk ke ke ke ke ke ke ke ke ke eoe ee e e x x f FUNCTION PROTOTYPES f A KK Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Kk Ck Kk Ck Kk Ck Kk kk kk kk kk I kk kc ko ke ke ke ko ke ke ke ke ke koe eoe ee ee ee kx x f void c int99 void void heap overflow void void init c30 void void error in real time void 8 20 TLC32040 Interface to the TMS320C3x 8 4 TLC32040 Interface to the TMS320C3x Figure 8 6 shows how to interface the C3x with zero glue logic to a Texas Instruments TLC32040 14 bit analog interface circuit AIC The following sections describe the steps required to initialize and set up the C3x timer and serial port and to reset and program the TL C32040 Figure 8 6 TM320C3x to TLC32040 Interface C3x TLC32040 TCLKO MCLK XFO RESET DRO DR Out gt DX0 DX Analog out Out FSX0 FSX In FSRO FSR Analog in In CLKXO i SCLK CLKRO 8 4 1 Resetting the Analog Interface Circuit The C31 s XFO signal is connected to the RESET signal of the AIC By toggling the RESET signal the C31 can reset the AIC This is achieved by executing the following instructions rpts 4
387. l INPUT DATA BUFFER FOR PROCESSOR VPVF output xferl OUTPUT DATA BUFFER FOR ISR BB VPVF input xferl INPUT DATA BUFFER FOR ISR BB E VI buffer rcvd FALSE CPU ISR COMM FLAG INPUT VI buffer_xmtd FALSE CPU ISR COMM FLAG OUTPUT VI r index 0 INDEX INTO INPUT AND OUTPUT DATA ARRAYS VI t index 0 INDEX INTO INPUT AND OUTPUT DATA ARRAYS VI i GENERIC COUNTER VARIABLE KK KK kk kk kk kk Ck kk Ck ECKE KC Ck Ck Ck Ck Ck Ck Kk Ck Ck Kk Ck kk kk kk kk kk kk ke ke ke ke ke ke ke e ke e e e e kx x f FUNCTION DECLARATIONS n KK Ck Ck Ck Ck Ck Ck Ck Ck A KC KC ECKE A Ck Kk Ck Kk Ck kk kk kk kk kk kk kc ko ke ko ke ke ke ke ke ke ke ke e ee eoe ee kx x f KK Ck Ck kk Ck Ck Ck kk Ck kk Kk Ck Ek Ck Ck Kk Ck Ck Ek Ck Kk kk kk kk kk kk kk ke ke ke ko ke ke ke ke e ke ke ee e e kx x f VOID C INTO5 OR C INTO7 ISR FOR HANDLING DATA TRANSFER BETWEEN C3X SERIAL PORT ONE AND THE A D D A ASSUMES SYNCHRONOUS OPERATION KK KK Ck kk Ck kk Ck Ck Ck Kk Kk Ck Ck Ck Ck Ck Ck Ck Kk Kk Kk Ck Ck kk kk kk kk kk ke ke ke ke ke ke ke ke ke ke e e e kx x f if SER NUM void c intO05 void void c_int07 void else void c_int0O7 void void c_int05 void endif T BB_CASC_WORD temp VPVF swap Burr Brown DSP101 2 and DSP201 2 Interface to TMS320C3x Example 8 2 TMS320C3x BB DSP102 202 Driver Continued
388. l 64 SERPRTXO word 0000000H Init of serial 0 xmt port control 66 SERPRTRO word 0000000H Init of serial 0 rcv port control 67 SERTIMO word 0000000H Init of serial 0 timer control 68 SERGLOB1 word 0000000H Init of serial 1 glbl control 80 SERPRTX1 word 0000000H Init of serial 1 xmt port control 82 SERPRTR1 word 0000000H Init of serial 1 rcv port control 83 SERTIM1 word 0000000H Init of serial 1 timer control 84 PARINT word 0000000H Init of parallel interface control 100 IOINT word 0000000H Init of I O interface control 96 Lext THE ADDRESS AT MEMORY LOCATION 0 DIRECTS EXECUTION TO BEGIN HERE FOR RESET PROCESSING THAT INITIALIZES THE PROCESSOR WHEN RESET IS APPLIED THE FOLLOWING REGISTERS ARE INITIALIZED TO 0 ST CPU STATUS REGISTER IE CPU DMA INTERRUPT ENABLE FLAGS IF CPU INTERRUPT FLAGS IOF I O FLAGS THE STATUS REGISTER HAS THE FOLLOWING ARRANGEMENT BITS 31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FUNCTION RESRV GIE CC CE CF RESRV RM OVM LUF LV UF N Z V G INIT LDP 0 DP H Point the DP register to page 0 LDI 1800H ST Clear and enable cache and disable OVM LDI MASK IE Unmask all interrupts INTERNAL DATA M LDI LDI LDF RPTS STF STF BLKO ARO BLK1 AR1 0 0 RO0 1023 RO ARO 1 RO AR1 fa EMORY INITIALIZATION TO FLOATING POINT 0 ARO points to block 0 ARI points to block 1 F 0
389. l is the summation of the individual im pulse responses 6 90 Sliding FFT D Ashiftintime is a shiftin phase or phase rotate in the frequency domain 1 Consider each new impulse as occurring at T 0 and perform the time shift on the past summation of samples as a whole Ateach bin the amount of phase rotation or twiddle factor that is applied to each bin is proportional to the frequency of the bin The phase shift is zero at DC n 0 and pi radians at Fnyq n N 2 After phase rotating each bin simply add the new sample impulse value Don t forget to start with each bin magnitude as zero D At this point the Fourier transform is a forever expanding series in both the time and frequency domains DD The Nth oldest sample is rotated n multiples of 2 x pi radians making the Nth oldest sample completely REAL with no IMAG component D AtN samples of age phase rotation N x n x 2 x pi N n x 2 x pi D Asliding rectangular window is created by subtracting the T Nth oldest sample while adding the newest T 0 sample At T N each frequency bin has rotated N times and is back to 0 radians of phase and can be prop erly subtracted 6 8 16 SFFT Algorithm SFFT ASM Example 6 18 on page 6 94 is written for the DSP beginner but contains features that also make it useful to the experienced DSP program mer SFFT ASM implements a continuous time Fourier transform which can be used to construct filters and ana
390. ld 250 mA Current Requirement for Output Driver Circuitry 12 3 Current Requirement for Output Driver Circuitry The output driver circuits on the C30 are required to drive significantly higher dc and capacitive loads than internal device logic Therefore they are de signed to drive larger currents than internal devices Because of this output drivers impose higher supply current requirements than other sections of cir cuitry on the device Accordingly the highest values of supply current are required when external writes are performed at high speed During reads or when the external buses are not in use the C30 does not drive the data bus this eliminates the most significant factor of output buffer current Furthermore in typical cases only a few address lines change or the whole address bus is static Under these conditions an insignificant amount of supply current is consumed When no external writes are performed or when writes are performed infrequently cur rent from output buffer circuitry can be ignored When external writes are performed the current required to supply the output buffers depends on several factors Data pattern transferred DD Rate at which transfers are made J Number of wait states implemented because wait states affect rates at which bus signals switch External bus dc and capacitive loading External operations involve writes external to the device and constitute the major power suppl
391. le the latter makes a finite buffer of length N sufficient for the data x Figure 6 1 shows the arrangement of memory locations necessary to imple ment circular addressing while Example 6 5 presents the C3x assembly code for an FIR filter Data Memory Organization for an FIR Filter Impulse Initial Final Low sponse input samples input samples address h N 1 Oldest input xin N 1 x n h N 2 x n N 2 xin N 1 e e e e id Circular queue h 1 x n 1 x n 2 High h 0 Newest input x n x n 1 address To set up circular addressing initialize the block size register BK to block length N Start the locations for signal x from a memory location whose ad dress is a multiple of the smallest power of 2 that is greater than N For instance if N 24 the first address for x is a multiple of 32 the lowest five bits of the beginning address are 0 See the Circular Addressing section in the Addressing chapter of the TMSS320C3x User s Guide for more information DSP Algorithms 6 7 FIR IIR and Adaptive Filters In Example 6 5 the pointer to the input sequence x is incremented and is as to be moving from an older input to a newer input At the end of the sub routine sumed Example 6 5 FIR Filter AR1 points to the position for the next input sample
392. lier both STRBO and STRB1 signals appear together on the four STRBO control pins This behavior is selected by setting the strobe configuration bit of the STRBO control register to 1 see Figure 4 24 Since both STRBO and STRB1 are mapped to different ranges of the logical memory map the strobe that actually appears on the physical STRBO pins depends on the internal address of the data program being accessed The two strobes effectively split the physical memory into two with the high memory address bit selecting either the STRBO or STRB1 address space For example if all program instructions are fetched from logical addresses 880000h 881 000h and all data reads writes are con fined between 980000h and 981000h the program fetches are associated with STRBO and all data accesses are driven by STRB1 see Figure 4 10 on page 4 23 for strobe memory mapping Since the behavior of each strobe is determined by a different control register the program fetches and data reads writes in each case can vary in the number of STRBO lines that are simulta neously driven and in the number of bus cycles required per access This is shown on the following pages Memory Interfacing 4 49 Interfacing Memory to the TMS320C32 DSP nessun 0g rgy1S LEq oq 0x10 els 0XS4 yzg rayls L v eg ays Oa ouyno 0uS4 oud OL OTOL HANE onna eniN3 enna Od 0gH1S 3 0H lgHlS ig OgHIS 9 g I8HIS zg 0gHlS 3
393. lock moves 3 4 extended precision arithmetic 3 16 floating point format conversion 3 20 integer and floating point division 3 6 square root 3 13 assembler linker 11 2 assembly language instructions parallel instructions advantages 5 5 SUBC instruction integer division 3 6 bank memory control logic 4 18 bank switching external bus 4 15 for Cypress Semiconductor s CY7C185 SRAM 4 17 techniques 4 15 timing for read operations 4 19 benchmarks for common C3x operations 6 78 biquad 6 9 bit manipulation 3 2 bit reversed addressing 3 5 bit reversed addressing inC 5 9 Index 1 Index block moves 3 4 repeat 2 18 inaloop 2 19 using to find a maximum 2 20 boot from a byte wide ROM A 4 from serial port to 8 16 and 32 bit wide RAM A 5 boot loader program C32 B 1 to B 14 flowchart B 3 opcodes B 5 source code description B 2 source code listing B 6 boot table C32 examples A 1 C32 host load 4 102 memory configuration 4 100 4 101 memory considerations 4 99 branches delayed 2 17 breakdown of numbers 11 10 bss section linking C data objects separate from 5 13 to 5 15 buffered signals 10 7 MPSD 10 6 buffering 10 5 bulletin board service BBS 11 6 Burr Brown DSP 101 2 and 201 2 interface to C3x 8 10 to 8 20 C compiler 11 2 C30 power dissipation 12 1 to 12 26 photo of Ipp for FFT 12 26 primary bus addressing up to 68 giga words 4 107 C31 serial port initializing 8 23 timer initializi
394. lock repeat 2 18 single instruction repeat 2 20 inaloop 2 21 RESET signal generation 1 3 reset vector 1 2 resonators comparison of types 9 4 crystal response to square wave drive 9 7 quartz crystal and ceramic 9 3 to 9 8 behavior and operation 9 4 to 9 7 scan paths TBC emulation connections for C3x 10 10 secondary communications 8 25 control register bit fields 8 26 data format 8 26 seminars 11 5 signals buffered 10 2 10 7 buffering for emulator connections 10 5 to 10 7 description 12 pin header 10 2 no buffering 10 5 timing 10 4 simulator 11 3 single instruction repeat 2 20 inaloop 2 21 software applications 3 1 to 3 29 application oriented operations adaptive filters 6 15 companding 6 2 to 6 6 fast Fourier transforms FFT 6 28 FIR filters 6 7 IIR filters 6 9 lattice filters 6 18 logical and arithmetic operations bit manupulation 3 2 bit reversed addressing 3 5 block moves 3 4 extended precision arithmetic 3 16 floating point format conversion 3 20 integer and floating point division 3 6 square root 3 13 processor initialization 1 2 Index 7 Index program control computed GOTOs 2 22 delayed branches 2 17 interrupt service routines 2 9 to 2 10 repeat modes 2 18 to 2 21 software stack 2 5 to 2 8 subroutines 2 2 to 2 4 programming tips C callable routines 5 2 to 5 4 hints for assembly coding 5 5 to 5 6 low power mode wakeup example 5 7 to 5 8 software development tools 11 2 to 11 6 bulletin board se
395. lq 110 mA libus D1 X f4 see Table 12 1 on page 12 20 lxbus lbase lprim exp with lbase 60 mA lorim D2 X C2 x Fo see Table 12 1 lexp D3 X Cg x Fg see Table 12 1 FV scale factor for frequency and supply voltage T scale factor for operating temperature Table 12 1 describes the variables used in the power supply current equation The table displays figure numbers from which the value can be obtained TMS320C30 Power Dissipation 12 19 Calculation of Total Supply Current Table 12 1 Current Equation Variables Variable Description Graph Value la Quiescent current 110 mA liops Internal operations current 55 mA libus Internal bus operations current t D1 Internal bus data scale factor Figure 12 3 f4 Internal bus current requirement Figure 12 2 lxbus External bus operations current t Ipase External bus base current 60 mA lprim Primary bus operations current T Do Primary bus data scale factor Figure 12 8 Co Primary bus capacitance load scale factor Figure 12 10 fo Primary bus current requirement Figure 12 4 or Figure 12 5 lexp Expansion bus operations current Li D3 Expansion bus data scale factor Figure 12 9 C3 Expansion bus capacitance load scale factor Figure 12 10 f3 Expansion bus current requirement Figure 12 6 or Figure 12 7 FV Frequency supply voltage scale factor Figure 12 11 T Temperature scale factor Figure 12 12 t See power supply current equation on page 12 19 12 4 4 Peak
396. lyze spectra It can also be used as a gener al purpose DSP teaching platform SFFT ASM uses a technique known as a sliding FFT SFFT to efficiently cal culate the spectrum of a signal on a sample by sample basis The SFFT is par ticularly well suited for applications where signal analysis filtering modula tion demodulation or other forms of signal manipulation in the frequency domain must be performed in real time The SFFT algorithm is similar to the DFT Further reading and other information includes Lj Designer Notebook page 22 Fast Logrithms on a Floating Point Device APPHELP1 TXT and APPHELP2 TXT included with the DSK software DSP Algorithms 6 91 Sliding FFT 6 92 Texas Instruments FTP site Files Location Main TMS320 FTP mirror site ftp ftp ti com mirrors tms320bbs C3x DSK files subdirectory ftp ftp ti com mirrors tms320bbs c3xdskfiles TMS320C3x code examples ftp ftp ti com mirrors tms320bbs c3xfiles TMS320C4x code examples ftp ftp ti com mirrors tms320bbs c4xfiles The following section sets the SFFT parameters which determine the SFFT output characteristics The following rules apply J BIN LEN BIN END BIN START gt 0 DD SFFTBINS x 4 SFFTSIZE lt Free data space D Sampling period lt time to compute all bins Be careful not to set the sampling rate too high while calculating many bin values The SFFT must finish calculating all of its bin values within the time span of one
397. m each time it goes through the loop This avoids fetching coefficients from the data bus Overall the forward and reverse SFFT are computed at 6 7 cycles per bin depending on whether both REAL and IMAG outputs are required The gener al case educational example SFFT ASM is slightly slower while SFFT2 ASM which is written for filtering 6 8 12 Fitting the Code and Data Into Memory If the effective desired SFFT FFT size is 512 points then only 256 positive fre quencies need to be computed With P I twiddle and R I SFFT data associated with each bin 1024 words of memory are required In addition 512 words of input buffer data are needed To maximize speed the inner loop of the SFFT uses dual access on chip memory to access data at the rate of two data moves per CPU cycle To avoid program fetch conflicts the SFFT code is loaded into the second on chip SRAM block which also holds the data buffer If off chip memory is available excellent performance is achieved by placing as much SFFT bin data on chip as possible The input window sample buffer and code can be external since the main code loop easily fits inside the cache and the sample buffer is only accessed twice per SFFT cycle DSP Algorithms 6 89 Sliding FFT VREEEPNPNEEEPNEUNEENENENEENENENEENENENEM EE QQdQdddl d 1 l q d Ql Ql 1111 Note The SFFT only needs to calculate the difference of the input of the most recent and the oldest data sample one time T
398. m mem DBNZ AR7 NEXT OUT if tx counter not zero POP AR7 RETI NEXT OUT PUSH AR6 LDI timer go AR7 STI AR7 QGtimerl control Start tx timer LDI tx byte AR6 load in tx byte from mem RORC AR6 next bit out is in carry BNC OUT ZERO carry 0 then send out 0 OR 04h IOF send out 1 to IOFO BR CLEANUP 3 H OUT ZERO AND OFBh IOF send out 0 to IOFO CLEANUP3 STI AR6 Gtx byte update byte in memory STI AR7 Qtx counter update counter in memory POP AR6 POP AR7 RETI Analog Interface Peripherals and Applications 8 69 Hardware UART for TMS320C3x 8 8 Hardware UART for TMS320C3x Section 8 7 discusses a software UART emulator which allows the C3x to per form asynchronous communication There are some applications that require a hardware UART This section describes one possible design for a hardware UART see Figure 8 12 This design originally done in a field programmable gate array FPGA can be easily transferred to an application specific inte grated circuit ASIC You can modify this design to accommodate faster data rates or different communication protocols Figure 8 12 TMS320C3x Serial Port to UART Interface 8 70 25 MHz Oscillator TMS320C30 UART logic RS 232 driver CLKXO p DXO Transmit D out FSXO logic Serial port CLKRO lt DRO Receive Din FSRO logic lt A H3 TX RX
399. n Example 3 13 TMS320C3x to IEEE Conversion Fast Version TITLE TMS320C3x TO IEEE CONVERSION FAST VERSION SUBROUTINE TOIEEE FUNCTION CONVERSION BETWEEN THE TMS320C3x FORMAT AND THE IEEE FLOATING POINT FORMAT THE NUMBER TO BE CONVERTED IS IN THE UPPER 32 BITS OF RO THE RESULT WILL BE IN THE LOWER 32 BITS OF RO UPON ENTERING THE ROUTINE AR1 POINTS TO THE FOLLOWING TABLE 0 OxFF800000 ARI 1 OxFF000000 2 0x7F000000 3 0x80000000 4 0x81000000 ARGUMENT ASSIGNMENTS ARGUMENT FUNCTION RO NUMBER TO BE CONVERTED ARI POINTER TO TABLE WITH CONSTANTS REGISTERS USED AS INPUT RO AR1 REGISTERS MODIFIED RO REGISTER CONTAINING RESULT RO NOTE SINCE THE STACK POINTER SP IS USED MAKE SURE TO INITIALIZE IT IN THE CALLING PROGRAM 3 26 IEEE TMS320C3x Floating Point Format Conversion Example 3 13 TMS320C3x to IEEE Conversion Fast Version Continued CYCLES 14 WORST CASE WORDS global TOL TOIEEE LDE RO RO gt LD
400. n Figure 2 2 b the AR always points to the next free location on the stack Stacks and Queues Figure 2 2 Implementations of High to Low Memory Stacks a Store to memory using ARn and b Store to memory using ARn and read from memory using ARn read from memory using ARn Low memory Low memory Free ARn Free ARn Top of stack Top of stack Bottom of stack Bottom of stack High memory High memory You can implement stack growth from low to high memory in two ways 1 Store to memory using ARn to push data onto the stack and read from memory using ARn to pop data off the stack 2 Store to memory using ARn to push data onto the stack and read from memory using ARn to pop data off the stack Figure 2 3 illustrates these two cases In Figure 2 3 a the AR always points to the top of the stack and in Figure 2 3 b the AR always points to the next free location on the stack Figure 2 3 Implementations of Low to High Memory Stacks a Store to memory using ARn and b Store to memory using ARn and read from memory using ARn read from memory using ARn Low memory Low memory Bottom of stack Bottom of stack ARn Top of stack Top of stack Free ARn Free High memory High memory Program Control 2 7 Stacks and Queues 2 2 3 Queues and Double Ended Queues 2 8 The implementation of que
401. n be read or written to by the CPU without further initialization steps by boot asm at the beginning of C program execution 4 8 3 2 ROM Model Linker c Option 4 92 If the COFF file is created with the linker c option the loader places the cinit section in the target memory according to the ROM model The ROM model copies the cinit section as one block to the address specified at the beginning of the same cinit section Following the load operation the ROM model expects the boot asm routine at the beginning of the C program to further process the cinit section by copying its contents to the SRAM bss section one array atatime Afterthe COFF load operation the memory contentis the same as that created by the RAM model with one exception the target SRAM still contains the temporary cinit section which serves no purpose after it is processed by boot asm The ROM model can still be useful for example it is useful to simulate the microprocessor mode EPROM boot see Figure 4 39 During the development cycle instead of burning a new EPROM each time the code is modified the EPROM can be removed and replaced with an equivalent SRAM device by reconfiguring jumpers The ROM model allows use of the loader to quickly load and debug the modified code while preserving the bus activity at power up to simulate an EPROM boot Buioejuaju AIowayy 6 v Figure 4 38 Loading C Object File into TMS320C32 Memory Linker cr Option
402. n of the amplifier and B is the gain of the feedback network For the circuit to have open loop gain greater than 1 A x B must be greater than 1 Forthe circuitto have positive feedback the phase shift around the loop must be 0 degrees or n360 where n 0 1 2 3 If these condi tions are met the outputoscillates at a frequency determined by the frequency selective feedback network and the amplitude increases until it reaches the linearity limitation of the amplifier Figure 9 6 Simple Form of an Oscillator Circuit Amplifier A e O Output Feedback network Clock Oscillator and Ceramic Resonators 9 9 Pierce Oscillator Circuit There are many possible combinations of amplifiers crystals and phase shifting components inductors and capacitors that meet the above specified conditions for oscillation One of the most common is a circuit based on the Pierce oscillator Figure 9 7 shows an ideal version of this circuit The Pierce oscillator uses an inverting amplifier a parallel resonant crystal as a resonator and two capacitors as phase shifting elements and load for the crystal This circuit is used for several reasons D It has a large frequency range from approximately 1 kHz to 200 MHz Lj lthashigh Q because the load impedances are mostly capacitive and not resistive and consequently exhibits very good stability D It maintains a high output signal while driving t
403. nal RAM 810 007 0000 BB1D 001 400 BB1D 810 008 0000 BB2D 001 401 BB2D 810 009 0000 BB3D 001 402 BB3D 810 00A 0000 BB4D 001 403 BB4D 810 00B 0000 BB5D 001 404 BB5D 810 00C 0000 BB6D 001 405 BB6D 810 OOD 4 810 OOF 0081 0400 810 OOF 0000 F860 Block 2 32 bit wide on chip RAM 810 010 DDCC BB1E 810 400 DDCC BB1E 810 011 DDCC BB2E 810 401 DDCC BB2E 810 012 DDCC BB3E 810 402 DDCC BB3E 810 013 DDCC BB4E 810 403 DDCC BB4E 810 014 6 810 015 0088 0400 810 016 0510 F864 Block 3 16 bit wide external RAM 810 017 0000 BBIF 880 400 BB1D 810 018 0000 BB2F 880 401 BB2D 810 019 0000 BB3F 880 402 BB3D 810 O1A 0000 BB4F 880 403 BB4D 810 01B 0000 BB5F 880 404 BB5D 810 01C 0000 BB6F 880 405 BB6D 810 01D 8 810 O1E 0090 0400 810 O1F 0010 F868 Block 4 8 bit wide external RAM 810 020 0000 0010 900 400 10 810 021 0000 0020 900 401 20 810 022 0000 0030 900 402 30 810 023 0000 0040 900 403 40 810 024 0000 0050 900 404 50 810 025 0000 0060 900 405 60 810 026 0000 0070 900 406 70 810 027 0000 0080 900 407 80 810 028 0 TMS320C32 Boot Table Examples Figure A 2 Boot From a 16 Bit Wide ROM to 8 16 and 32 Bit Wide RAM Source Boot Destination Block Source Boot Destination Block address table address data address table address data 001 000 10 001 022 6 00
404. nal that ter minates the cycle When slow devices are accessed the external hardware does not respond and the cycle is terminated after the internal wait count Wait States and Ready Signal Generation You can perform an OR of the two ready signals if conditions require the ter mination of bus cycles before the number of wait states implemented when ex ternal logic takes place In this case the wait count that is specified internally is shorter than the number of wait states implemented with the external ready logic and the bus cycle is terminated after the wait count This technique can also safeguard against inadvertent accesses to nonexistent memory that would never respond with a ready signal and would lock up the C3x If an OR of the two ready signals is used and the internal wait state count is less than the number of wait states implemented externally the external ready generation logic resets its sequencing to allow a new cycle to begin immediate ly following the end of the internal wait count This requires that consecutive cycles come from independently decoded areas of memory and that the exter nal ready generation logic restarts its sequence as soon as a new cycle begins Otherwise the external ready generation logic can lose synchronization with bus cycles and generate improperly timed wait states 4 5 2 ANDing the Ready Signals Performing an AND of the two ready signals can implement wait states for de vices that are equ
405. nant fre quency and is determined by SO o Although oscillators frequently consist of different combinations of inductors and capacitors as resonating elements the accuracy of the frequency control with these components is limited Changes in the values of L and C due to tol erance limitations and changes in the environment such as temperature strongly affect the frequency of the oscillator Many applications in digital sys tems require precise clock timing and need more accurate resonators Quartz crystal and ceramic resonators can provide a more stable and precise fre quency control Clock Oscillator and Ceramic Resonators 9 3 Quariz Crystal and Ceramic Resonators 9 2 1 Behavior and Operation of Quartz Crystal and Ceramic Resonators The oscillator circuitry built into the C3x devices is designed for use with a quartz crystal or ceramic resonator as the frequency controlling element Quartz crystal and ceramic resonators are resonating components made with materials that have specific piezoelectric properties Piezoelectric materials deform mechanically in the presence of an electric potential this mechanical stress on the material produces a voltage This property makes a very stable resonator since the frequency of mechanical vibration is controlled precisely by the size shape and material properties of the crystal or ceramic used In fact many quartz crystal resonators are so precise that they operate within
406. nd facilitate all types of high speed processing These instructions handle B Software stack n L Delayed branches Single and multiple instruction loops without any overhead Topic Page 2 1 Subroutines e rrt EEE a EAE 2 2 2 2 Stacks and Queues eer EEUU EET 2 5 2 3 Interrupt Service Routines ee e 2 9 2 4 Context Switching in Interrupts and Subroutines 2 11 2 50 DelayediBrancheSs ee sneferetetsie edetenarsreteretfenersteratey 2 17 2 69 hepeati Modes 1 779 E EIS 2 18 2 7 Gomputed GOTOSs ee RAEE EAEE ES EEA SE 2 22 2 1 Subroutines 2 4 Subroutines 2 2 The C3x has a 24 bit program counter PC and a practically unlimited soft ware stack The CALL and CALL cond instructions cause the stack pointer to increment and store the contents of the next value of the program counter on the stack At the end of the subroutine the RETScond instruction performs a conditional return Example 2 1 illustrates how to use a subroutine to determine the dot product between two vectors Given two vectors of length N represented by the arrays a 0 a 1 a N 1 and b 0 b 1 b N 1 the dot product is computed from the expression d a 0 b 0 a 1 b 1 a N 1 b N 1 Processing proceeds in the main routine to the point at which the dot product is to be computed It is assumed that the arguments of the subroutine have been ap
407. ndard bit reversing r DSP Algorithms 6 45 Fast Fourier Transforms FFTs Example 6 16 Real Forward Radix 2 FFT Continued LDI SOURCE ADDR RO CMPI DEST_ADDR RO BEQ IN PLACE Bit reversing Type 1 from source to destination NOTE abs SOURCE ADDR DEST ADDR must be gt FFT_SIZE this is not checked i LDI FFT_SIZE RO SUBI 2 R0 LDI FFT_SIZE IRO LSH 1 IRO IRO half FFT size LDI SOURCE_ADDR ARO LDI DEST_ADDR AR1 LDF ARO R1 RPTS RO LDF ARO R1 STF R1 AR1 IRO B STE R1 AR1 IRO B BR START F In place bit reversing Bit reversing on even locations A lst half only IN PLACE DDI FFT_SIZE IRO LSH 2 IRO IRO quarter FFT size LDI 2 IR1 LDI FFT_SIZE RC LSH 2 RC SUBI 3 RG LDI DEST_ADDR ARO LDI ARO AR1 LDI ARO AR2 NOP AR1 IRO B NOP AR2 IRO B LDF ARO IR1 RO LDF AR1 R1 CMP I AR1 ARO Xchange locs only if ARO lt AR1 LDFGT RO R1 LDFGT AR1 IRO B R1 6 46 Fast Fourier Transforms FFTs Example 6 16 Real Forward Radix 2 FFT Continued RPTB BITRV1 LDF ARO IR1 RO M STF RO ARO LDF AR1 R1 I STF R1 AR2 IRO B CMPI AR1 ARO LDF GT RO R1 BITRV1 LDFGT AR1 IRO B RO STF RO ARO STF R1 AR2 Perform bit reversing on odd i locations 2nd half only
408. ne Name Substitutions for Test Vectors and Equations gH Pk u0 1 0 X 5 Source lintsro Sync sync sro samesrc same c3xint lintx state bits outstate samesrc sync idle b00 sync st b01 synchronize state wait bl0 wait for interrupt source to go inactive State diagram outstate Low Power Mode Interrupt Example 1 3 State Machine and Equations for the Interrupt Generation 16R4 PLD Continued state idle if source then sync st else idle state sync st if source then wait else idle state wait if source then wait else idle equations lintx source sync amp samesrc page Test interrupt generation logic test_vectors he source gt outstate c3xint Cc L gt idle L check start from idle L H gt idle H test normal interrupt operation C H gt sync st H Qu di idle L H C L idle L L H gt idle H test coming out of idle2 operation du H gt idle H C H gt sync st H Qu d idle L A C H gt sync st H test same sourc c H wait L H C H gt wait L A C L idle L H L H gt idle H test idle2 operation L H gt idle H H li H gt idle H z end interrupt_generation Processor Initialization 1 11 Chapter 2 Program Control This chapter discusses a group of C3x instructions that provide program control a
409. ned int le zis Parallel output enable control unsigned int he 1 Headphone output enable control x bitval STEREO 8 typedef union unsigned int _intval 2 struct Time slots 2 4 signed int d r1 24 Unused don t care bits 0 23 Time slot 1 signed int left 8 Left channel 8 bit Time slot 8 unsigned int d r3 4 Unused don t care bits 0 3 unsigned int ma 4 Monitor path selection Time slot 7 unsigned int lg sd Left input gain settings xf unsigned int is eqs Input selection unsigned int ovr S5 Overange unsigned int pio 25 Parallel I O bits Time slot 6 unsigned int ro 67 Right output attenuation setting xf unsigned int se 217 Speaker output enable control unsigned int d_r2 eus Unused don t care bit 7 Time slot 5 unsigned int lo 2565 Left output attenuation setting unsigned int le Fis Parallel output enable control unsigned int he sls Headphone output enable control x bitval MONO 8 typedef union unsigned int _intval 2 CONTROL control STEREO_16 stereo_16 MONO_16 mono_16 STEREO_8 stereo_8 MONO_8 mono_8 CS4215 WORD Analog Interface Peripherals and Applications 8 53 CS4215 Interface to the TMS320C3x Example 8 15 CS4215 h Continued
410. ng 8 22 maximum timer period register value 8 22 minimum timer period register value 8 22 Index 2 C32 boot loader program B 1 to B 14 boot table examples A 1 hostload 4 102 memory configuration 4 101 memory considerations 4 99 booting in a C environment 4 86 configuration examples 2 external memory banks 4 74 single external memory bank 4 80 interfacing memory to 1 bank 2 strobes 32 bit wide memory 4 49 1 bank 2 strobes adaress translation for data size equal to 16 and 32 bits 4 55 1 bank 2 strobes adaress translation for data size equal to 16 and 8 bits 4 51 1 bank 2 strobes adaress translation for data size equal to 32 and 8 bits 4 53 16 8 bit memory configuration design examples 4 41 32 bit memory configuration design examples 4 35 logical versus physical address 4 33 program fetch from 16 bit STRBO memory 4 29 program fetch from 32 bit STRB1 memory 4 31 RDY signal generation 4 57 STRBO and STRB1 data access 4 25 4 27 memory address spaces 4 69 memory configuration for normal program execution 4 100 TMS320 tools interaction with enhanced memory interface 4 67 C compiler 4 69 C compiler and assembler switch 4 72 configuration examples 4 74 debugger configuration 4 73 linker switches 4 73 calculation of TMS320 power dissipation photo of Ipp for FFT 12 26 C callable routines 5 2 ceramic resonators 9 1 to 9 24 circular addressing FIR filters 6 7 clock oscillator 9 1 to 9 24 circuitry 1 3 COFF file
411. ng currently available RAMs DD RAMs without output enable OE control lines which include the 1 bit wide organized RAMs and most of the 4 bit wide RAMs RAMs with OE controls which include the byte wide RAMs and a few of the 4 bit wide RAMs Many of the fastest RAMs do not provide OE control they use chip select CS controlled write cycles to ensure that data outputs do notturn on for write operations In CS controlled write cycles the write control line WE goes low before CS goes low and internal logic holds the outputs disabled until the cycle is completed Using CS controlled write cycles is an efficient way to interface fast RAMs without OE controls to the C30 at full speed Memory Interfacing 4 5 Zero Wait State Interface to Static RAMs 4 6 In the case of RAMs with OE controls using this signal can add flexibility to many systems Additionally many of these devices can be interfaced by using CS controlled write cycles with OE tied low in the same manner as with RAMs without OE controls There are however two requirements for interfacing to OE RAMs in this manner D The RAM s OE input must be gated internally with the chip select pin and WE so that the device s outputs do not turn on unless a read is being per formed The RAM must allow its address inputs to change while WE is low some RAMs specifically prohibit this Figure 4 3 shows the C3x interface to Cypress Semiconductor s CY7C186 25 ns 8K x 8
412. ng to the C3x 4 1 to 4 22 quick access 5 5 MEMORY16 C module 4 71 MEMORY8 C module 4 71 MPSD emulator buffered transmission signals 10 6 cable signal timing 10 4 connector 10 2 no signal buffering 10 5 multiplication example extended precision arithmetic 3 18 ordering information 11 7 ORing of the ready signals 4 10 oscillators clock 9 2 design considerations 9 17 to 9 21 crystal aging 9 21 crystal series resistance 9 17 drive level power dissipation 9 18 frequency temperature characteristics 9 20 load capacitors 9 17 Index 6 loop gain 9 18 startup time 9 20 operation 9 10 overtone operation 9 14 Pierce circuit 9 9 to 9 16 Pierce configuration 9 13 recommendations for use 9 2 to 9 3 solutions for common frequencies 9 22 to 9 24 Out COFF file 4 90 output driver circuitry capacitive load dependence 12 16 to 12 17 current requirement 12 9 to 12 16 data dependency factors 12 14 to 12 16 expansion bus 12 13 to 12 14 primary bus 12 10 to 12 12 parallel instructions advantages in using 5 5 partnumbers 11 7 breakdown of numbers 11 10 device suffixes 11 10 prefix designators 11 9 part ordering 11 1 to 11 10 peripherals addressing as data structures inC 5 11 to 5 12 analog interface 8 1 to 8 72 DMA controller hints for programming 7 2 programming examples 7 4 to 7 10 physical address 4 33 pipeline conflicts avoiding 5 5 pod interface emulator 10 3 power dissipation algorithm partitioning 12 4 calculation
413. ns S D Adaptive Signal Processing Englewood Cliffs NJ Prentice Hall Inc 1985 Array Signal Processing Haykin S Justice J H Owsley N L Yen J L and Kak A C Array Signal Processing Englewood Cliffs NJ Prentice Hall Inc 1985 Hudson J E Adaptive Array Principles New York NY John Wiley and Sons 1981 Monzingo R A and Miller J W ntroduction to Adaptive Arrays New York NY John Wiley and Sons 1980 Read This First xi Trademarks Trademarks ABEL is a trademark of DATA I O CodeView MS MS DOS MS Windows and Presentation Manager are registered trademarks of Microsoft Corporation DEC Digital DX Ultrix VAX and VMS are trademarks of Digital Equipment Corporation HPGL is registered trademark of Hewlett Packard Company Macintosh and MPW are trademarks of Apple Computer Corp Micro Channel OS 2 PC DOS and PGA are trademarks of International Business Machines Corpora tion SPARC Sun 3 Sun 4 Sun Workstation SunView and SunWindows are trademarks of Sun Microsys tems Inc UNIX is a registered trademark in the United States and other countries licensed exclusively through X Open Company Limited Xii If You Need Assistance If You Need Assistance World Wide Web Sites TI Online http www ti com Semiconductor Product Information Center PIC http www ti com sc docs pic home htm DSP Solutions http www ti com dsps 320 Hotline On line http www ti com sc do
414. nsform con verts information back to the time domain from the frequency domain Imple mentation of Fourier transforms that are computationally efficient are known as fast Fourier transforms FFTs The theory of FFTs can be found in books such as DFT FFT and Convolution Algorithms and Digital Signal Processing Applications With the TMS320 Family Fast Fourier transform is a label for a collection of algorithms that implement efficient conversion from time to frequency domain Distinctions are made among FFTs based on the following characteristics Radix 2 or radix 4 algorithms depending on the size of the FFT butterfly D Decimation in time or frequency DIT or DIF D Complex or real FFTs gj FFT length etc Certain C3x features that increase the efficiency of numerically intensive algo rithms are particularly well suited for FFTs The high speed ofthe device 33 ns cycle time makes implementation of real time algorithms easier while float ing point capability eliminates the problems associated with dynamic range The powerful indirect addressing indexing scheme facilitates the access of FFT butterfly legs with different spans The repeat block implemented by the RPTB instruction reduces the looping overhead in algorithms heavily depen dent on loops such as FFTs This construct provides the efficiency of in line coding in loop form The FFT reverses the bit order of the output therefore the output must be reordered This reor
415. nt 00000000000000000000000000101000 Divisor Fourth SUBC command Negative difference 00000000000000000000000000110110 Y Remainder Quotient Final result When the SUBC command is used both the dividend and the divisor must be positive Example 3 5 shows an example of integer division in which the sign of the quotient is properly handled The last instruction before returning modi fies the condition flag in case subsequent operations depend on the sign of the result Logical and Arithmetic Operations 3 7 Integer and Floating Point Division Example 3 5 Integer Division ER DIVIDEND IN RO IRO IR1 IZE DIVISOR WITH DIVIDEND SUBC ENT IS IN LSBs OF RESULT ENDS ON AMOUNT OF NORMALIZATION DIVI SIGNED DIVISION TITLE INTEGER DIVISION SUBROUTINE DIVI INPUTS SIGNED INTEG SIGNED INTEGER DIVISOR IN R1 OUTPUT RO R1 into RO REGISTERS USED RO R3 OPERATION dis 2 EA X 3 UOTII CYCLES 31462 D globl DIVI SIGN Set R2 EMPF set R3 EMP Set IRO COUNT set IR1 is DETERMINE SIGN OF RESULT GET ABSOLUTE VALUE OF OPERANDS XOR RO R1 SIG ABSI RO ABSI R1 CMPI RO R1 BGTD ZERO NORMALIZE OPERANDS FLOAT RO TEMPE PUSHF TEMPF POP COUNT LSH 24 COUNT
416. nt and is between 0 and 7FFFFFh LLLLLLLLLLLL Figure 4 47 TMS320C30 Combination of Primary and Expansion Busses to Address 68 Gigawords C30 A 23 No connect 22 0 gt A 22 0 _STRB CS Memory array MSTRB XA 12 0 A 12 0 Memory Interfacing 4 107 4 108 Chapter 5 Programming Tips Programming style reflects personal preference The purpose of this chapter is not to impose any particular style but to highlight features of the C3x that can produce faster and or shorter programs The tips cover the C compiler as sembly language programming and low power mode wakeup Topic Page 5 1 Hints for Optimizing C Code 5 2 5 2 Hints for Assembly Coding 5 5 5 3 Low Power Mode Wakeup Example 5 7 5 4 Bit Reversed Addressing in C 5 9 5 5 Sharing Header Files in C and Assembly 5 10 5 6 Addressing Peripherals as Data Structures in C 5 11 5 7 Linking C Data Objects Separate From the bss Section 5 13 5 8 Interrupts in C 5 16 5 1 Hints for Optimizing C Code 5 1 Hints for Optimizing C Code The C3x was designed with a large register file software stack and memo
417. nterface Example 4 2 allocates sections of the preceding code into the desired memory configuration Example 4 2 Linker Command File sample obj Input filename Ef heap8 32768 Set 8 bit memory pool size Ef stack 8704 Set C system stack size a o sample out Specify output file 3 m sample map Specify map file Hi MEMORY PRGRAM org 0x0000 len 0x2000 STRBORAM org 0x2000 len 0x6000 ONCHIRAM org 0x87Fe00 len 0x200 STRB1RAM org 0x900000 len 0x8000 SECTIONS text gt PRGRAM 32 bit data section Cinit gt STRBORAM 32 bit data section const STRBORAM 32 bit data section bss STRBORAM 32 bit data section Stack STRBORAM 32 bit data section SYSm8 gt STRBIRAM 8 bit memory pool mapped to STRB1 The debugger batch file shown in Example 4 3 executes initialization com mands that configure the C source debugger to handle a C32 with the memory configuration shown in Figure 4 33 on page 4 75 Memory Interfacing 4 77 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface Example 4 3 Debugger Batch File mr sconfig init clr ma 0x0000 0x2000 ma 0x2000 0x6000 ma Ox87FE00 0x200 ma 0x808000 0x10 ma 0x808020 0x20 ma 0x808040 0x10 ma 0x808060 0x10 reset map on 0x808064 0x808068 i load sample out R W TX RAM RAM E RAM RAM A RAM A
418. nterface 0 8 21 amp om o dd 5d abs Ld dd O Sm lL t dg og NO CO co 00120 n o PPPPPPPPPPPPPPPPPPPPPPPPY T 10 1 i ine Figures Primary Communication Data Format 000 cece eee eects Secondary Communication Data Format i TLC320AD58C Serial Interface 18 bit Master Mode 100 Timing Diagram Interface Between the TMS320C3x and the TLC320AD58C ssssss TMS320C3x to CS4216 Interface i TMS320C3x Serial Port to UART Interface i Transmit Circuitry siede riisi iia e s Receive Circuitry PUT Series LC Schematic 0 Crystal Equivalent Circuit Model i Impedance Characteristics of Crystal i Reactance Characteristics of Crystal i Crystal Response to a Square Wave Drive i Simple Form of an Oscillator Circuit i Pierce Circuit Ideal Operation 0 Pierce Circuit Actual Operation 0 Pierce Circuit for Square Wave Output a TMS320C3x Oscillator Circuitry 0 c sm i eens Digital Inverter Circuit and Its Transfer Characteristic i Impedance Characteristics of a Crystal i Oscillator Circuit for Overtone Crystal Operation i Addition of Rd to Limit Drive Level of the Crystal i Oscillator Start p sorer i n x ek TRAE ged ee ee cellos Sage et UR Rd E Example Frequency Temperature Characteristic of AT Cut Crystals Fundamental Mode Circuit sssi 238 00 3 De tenets Third Overtone Circuit ss se ds e n 12 Pin Header Signals and Header Dimensions i Emulator Cable
419. nterface to the C3x 8 21 to 8 29 TLC320AD58 interface to the C3x 8 30 to 8 38 TMS320 tools interaction with C32 enhanced memory interface 4 67 C32 configuration examples 4 74 C compiler 4 69 C compiler and assembler switch 4 72 debugger configuration 4 73 linker switches 4 73 total supply current calculation 12 17 to 12 23 average current versus peak current 12 20 combining 12 17 dependencies 12 18 to 12 19 design equation 12 19 to 12 20 thermal management considerations 12 21 to 12 23 12 pin header MPSD 10 2 u law compression 6 3 u law expansion 6 4 UART emulator hardware 8 70 to 8 72 software 8 66 to 8 69 user stacks 2 6 wait states circuit for generation of 4 14 external bus 4 10 to 4 20 zero 4 5 to 4 9 workshops 11 5 Index XDS target design considerations connections between emulator and target system 10 5 to 10 7 designing MPSD emulator connector 10 2 diagnostic applications 10 10 mechanical dimensions of emulator connector 10 8 to 10 9 MPSD emulator cable signal timing 10 4 XDS510 emulator 11 3 zero wait states C3x interface to CY7C 186 CMOS SRAM 4 7 interface to static RAM 4 5 to 4 9 read operations timing 4 8 write operations timing 4 8 Index 9 Index 10
420. nts by a complex vector determined by the ANGLE parameter If ANGLE 90 the Hilbert transform is recon structed from the pass band SFFT bins covering BIN START to BIN END If ANGLE 0 0 no phase shift occurs DSP Algorithms 6 85 Sliding FFT The 0 and matched 90 phase shift Hilbert transform is useful in telecommu nications applications where the quadrature outputs are used to shift the spectrum of a signal or in radio and modem modulation schemes 6 8 8 Raised Cosine Windowed Filters By applying the raised cosine window to the summation of bin values the REAL or IMAG filter response ripple is improved The method implemented uses a series of coefficients that are applied to each frequency bin and then added much like an FIR filter except in the frequency domain The coefficient values result from both DD The convolution of the response of a raised cosine function with the signal response D The multiplication of a rectangular bandpass filter also applied in the frequency domain A group delay or time shift is also seen which is equal to N 2 plus the time it takes a signal to make it through the ADC DAC conversion process In Figure 6 13 through Figure 6 16 the number of bins required is actually WIDTH 2 for a given pass band bandwidth and the signs of the coefficients alternate The endpoints which are also scaled by 5096 are the result of the window coefficients and define the edge cha
421. nverters ADCs and digital to analog converters DACs are commonly required in DSP systems and interface efficiently to the I O expansion bus These devices are available in many speed ranges and with a variety of features While some might require one or more wait states on the MO bus others can be used at full speed Figure 8 1 illustrates a C30 interface to an Analog Device s AD1678 ADC The AD1678 is a 12 bit 5 us converter that allows sample rates up to 200 kHz and has an input voltage range of 10 V bipolar or unipolar The converter is connected according to manufacturer s specifications to provide 0 10 V operation This interface illustrates a com mon approach to connecting such devices to the C30 Note that the interface requires only a minimum amount of control logic The AD1678 is a very flexible converter and is configurable in a number of dif ferent operating modes These operating modes include Byte or word data format D Continuous or noncontinuous conversions D Enabled or disabled chip select function Programmable end of conversion indication This interface uses a data format of 12 bit words rather than a byte format to be compatible with the C3x Noncontinuous conversions are selected so that variable sample rates can be used continuous conversions occur at a fixed rate of 200 kHz With noncontinuous conversions the host processor deter mines the conversion rate by initiating conversions through write
422. o nential decay is that the SFFT is now windowed by an exponentially decaying window To minimize this effect keep K1 close to 1 000 0 999 for example 6 8 5 SFFT Windowing 6 84 Unlike the FFT and DFT SFFT windowing cannot be performed in the time do main the input window is moving in time and therefore the window function must also move in time The SFFT windowing operation is performed in the frequency domain using a technique known as convolution The desirable effect of windowing is a multiplicative process in the time domain whereby the sharp discontinuities at the endpoints that accompany a rectangular data win dow are smoothed out Without a smoothing window these abrupt changes smear the frequency spectrum over many bins In the frequency domain the coefficients of most windowing functions are simple and do not require large storage arrays Forthe raised cosine window function the coefficients are par ticularly simple 5 1 0 5 and are easily imbedded into the code as addi tion and subtraction However frequency domain or convolutional window filtering is applied to the REAL and IMAG data separately before the REAL IMAG data is combined into a magnitude The operation is fast and only occurs during output Furthermore other window functions are rapidly and easily implemented by selecting different convolution coefficients Sliding FFT Figure 6 12 Raised Cosine Window Time domain Frequenc
423. o 100 C SMJ MIL STD 883C M 55 to 125 C At 40 to 85 C Device Family Package Type 320 TMS320 family FD Leadless ceramic chip carrier Technology FJ Ceramic leaded chip carrier C CMOS FN Plastic leaded chip carrier E CMOS EPROM FZ Ceramic leaded chip carrier P OTPEPROM GB Ceramic pin grid array No letter NMOS GE Ceramic pin grid array glass seal Device HT Ceramic quad flatpack F i gull wing oe DSP HU Ceramic quad flatpack JD Ceramic dual in line 14 package side brazed 15 N Plastic dual in line package 16 PQ Plastic quad flatpack 17 2nd generation DSP 20 25 26 3rd generation DSP 30 31 32 4th generation DSP 40 5th generation DSP 50 51 T See electrical specifications for C31 PQA case temperature ratings 11 10 Chapter 12 TMS320C30 Power Dissipation This chapter presents the information necessary to determine the require ments for the power supply current for the C30 under different operating conditions As device sophistication and levels of integration increase with evolving semi conductor technologies actual levels of power dissipation vary widely These levels depend heavily on the particular application in which the device is used and the nature of the program being executed In addition due to the charac teristics of CMOS technology power requirements vary according to clock rates and data values being processed Us
424. o run and IDLE2 operates identically to IDLE The external interrupts INT 0 3 are the only signals that start up the processor from the mode the device was in Therefore you must enable the external interrupt before going to IDLE2 power down mode see Example 5 4 If the proper external interrupt is not set up before executing IDLE2 to power down the only way to wake up the processor is with a device reset Programming Tips 5 7 Low Power Mode Wakeup Example Example 5 4 Setup of IDLE2 Power Down Mode Wakeup 5 8 ITLE IDLE2 POWER DOWN MODE WAKEUP ROUTINE SETUP il HIS EXAMPLE SETS UP THE EXTERNAL INTERRUPT 0 INTO BEFORE EXECUTING HE IDLE2 INSTRUCTION WHEN THE INTO SIGNAL IS RECEIVED x ATER THE PROCESSOR WILL RESUME FROM ITS PREVIOUS STATE NOTE HE INTRPT SECTION IS MAPPED FROM THE ADDRESS 0 FROM THE RESET AND INTERRUPT VECTORS Sect INTRPT RESET word START Reset vector INTO word INTO ISR INTO interrupt vector INTL word INT1 ISR INT1 interrupt vector INT2 word INT2 ISR INT2 interrupt vector INT3 word INT3 ISR INT3 interrupt vector text LDP QSP ADR LDI SP_ADR SP Set up stack pointer OR Olh IE s Enable INTO IDLE2 Set GIE 1 and stop clock INTO ISR RETI E Return to ins
425. o the TMS320C3x Example 8 15 CS4215 h Continued define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define gd Us Us D Us ms p m gs gs m p m pg ggg gy ggg ggg gpugggg gg ggg ggg H Ch am BB DB BA aS BD Oo ww w O1 O1 w wn Oonan eNA coo G 01 5 CO PO ES QO 000 1001 CQ ho ES Oo e _ O LI 12 13 14 15 16 Ay 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 29 34 35 36 9d 38 39 ce Cn am aA GP BB A BA OB aS CQ 000 1001 4 CQ ho F2 OY OY O1 O1 O1 O1 O1 O1 O1 O1 vo F2 0o 000 10 0 15 CO No F2 16 18 19 21 22 24 25 4 2T 28 30 31 395 34 36 SW s 39 40 42 43 45 46 48 49 5l B2 54 55 Ss 58 60 61 63 64 66 67 69 TO T25s diss 74 Tas TT 78 80 81 83 84 87 88 90 91 Ordo oUr c o uUrco Uro rc oro OS UO o oco orc Owvorcocurcoowvoso o cunrot co uro corio Uc o 8 56 CS4215
426. oad enable gt MCBL MP nod ii CLKX1H only 3 DX1 4 Data 7T P XD31 XD0 pex e bh Serial port 1 Address XA12 XA0 CLKR1 H4 C30 only Expansion bus XR W DR1 Hx C30 only gt XRDY 4 Control FSR1 tM IOSTRB MSTRB All of the interfaces are independent of one another and you can perform dif ferent operations simultaneously on each interface The primary and expansion buses implement the memory mapped interface to the device The external direct memory access DMA interface allows ex ternal devices to cause the processor to relinquish the primary bus and allow direct memory access Memory Interfacing 4 3 Primary Bus Interface 4 3 Primary Bus Interface 4 4 The C3x uses the primary bus to access the majority of its memory mapped locations When a large amount of external memory is required in a system it is interfaced to the primary bus The C30 expansion bus discussed in the Ex ternal Memory Interface chapter of the TMS320C3x User s Guide actually comprises two mutually exclusive interfaces controlled by the MSTRB and IOSTRB signals Cycles on the expansion bus that are controlled by the MSTRB signal are equivalent to cycles on the primary bus except that bank switching is not implemented on the expansion bus Accordingly the discussion of primary bus cycles in this section applies equally to MSTRB cycles on t
427. oating Point Division Example 3 6 Inverse of a Floating Point Number Continued NOW THE ITERATIONS BEGIN MPYF RI RO R2 R2 v x 0 SUBRF 2 0 R2 R2 2 0 v x 0 PYF R2 R1 Rl x 1 x 0 2 0 t v x 0 MPYF RI BO R2 R2 v x 1 SUBRE 2 0 R2 R2 2 0 v x 1 PYF R2 R1 H Rl x 2 x 1 2 0 t v x 1 MPYF RLI BO RZ 3 R2 v x 2 SUBRF 2 0 R2 R2 2 0 t v x 2 PYF R2 R1 4 Rl x 3 x 2 2 0 t v x 2 MPYF R1 RO R2 3 R2 v x 3 SUBRF 2 0 R2 R2 2 0 tv x 3 PYF R2 R1 Rl x 4 x 3 2 0 t v x 3 RND R1 H This minimizes error in the LSBs FOR THE LAST ITERATION WE USE THE FORMULATION x 5 x 4 1 0 v x 4 x 4 MPYF RI RBO R2 3 R2 v x 4 1 0 01 gt 1 SUBRF 1 0 R2 gt RZ T0 ow x 4 0 0 01 e 0 PYF R1 R2 H R2 x 4 1 0 t v x 4 ADDF R2 R1 R2 x 5 x 4 1 04 v x 4 x 4 RND R1 RO H Round since this is followed by a MPYF NOW THE CASE OF v 0 IS HANDLED NEGF R0 R2 LDF R3 R3 This sets condition flags LDFN R2 R0 If v lt 0 then RO RO RETS END end 3 12 Square Root Computation 3 5 Square Root Computation An iterative algorithm is used to compute a square root on the C3x and is simi lar to the one used for computation of the inverse This algorithm computes the inverse of the squ
428. ocumentation outlines seminars and the university program and provides factory repair and exchange information References Related Documentation from Texas Instruments Heferences TMS320 Third Party Support Reference Guide literature number SPRUO520C alphabetically lists over 100 third parties who supply vari ous products that serve the family of TMS320 digital signal processors including software and hardware development tools speech recogni tion image processing noise cancellation modems etc The publications in the following reference list contain useful information re garding functions operations and applications of digital signal processing DSP These books also provide other references to many useful technical papers The reference list is organized into categories of general DSP speech image processing and digital control theory and is alphabetized by author J General Digital Signal Processing Antoniou Andreas Digital Filters Analysis and Design New York NY McGraw Hill Company Inc 1979 Bateman A and Yates W Digital Signal Processing Design Salt Lake City Utah W H Freeman and Company 1990 Brigham E Oran The Fast Fourier Transform Englewood Cliffs NJ Prentice Hall Inc 1974 Burrus C S and Parks T W DFT FFT and Convolution Algorithms New York NY John Wiley and Sons Inc 1984 Chassaing R and Horning D Digital Signal Processing with the TMS320C25 New York N
429. of implementing digital filters It has found applications in speech processing spectral estimation and other areas In this discussion the notation and terminology from speech processing applications are used If H z is the transfer function of a digital filter that has only poles A z 1 H z is a filter having only Os and is called the inverse filter The inverse lattice filter is shown in Figure 6 4 These equations describe the filter in mathematical terms f in f i 1 n k i b i 1 n 1 b in b i 1 n 1 k i f i 1 n Initial conditions f 0 n b 0 n x n Final conditions y n f p n In the above equation f i n is the forward error b i n is the backward error k i is the i th reflection coefficient x n is the input and y n is the output signal The order of the filter that is the number of stages is p In the linear predictive coding LPC method of speech processing the inverse lattice filter is used during analysis and the forward lattice filter during speech synthesis Figure 6 4 Structure of the Inverse Lattice Filter x n f p 1 n 6 18 f 0 n f 1 n f p n y n gt p 96 gt b Ki K2 Kp K1 K2 Kp b 0 n b 1 n b p 1 n Figure 6 5 shows the data memory organization of the inverse lattice filter on the C3x Lattice Filters Figure 6 5 Data Memory Organization for Forward and Inverse Lattice Filters Reflection Backward
430. og Interface Peripherals and Applications 8 57 CS4215 Interface to the TMS320C3x Example 8 15 CS4215 h Continued define define define define define MA MA MA MA MA 11 l2 13 14 15 11 12 13 14 LS T2 78 84 90 96 Q Oo oco c Mute Monitor Path 8 58 CS4215 Interface to the TMS320C3x Example 8 16 CS4215 c cs4215 c staff 05 13 92 C Texas Instruments Inc 1992 Refer to the file license txt included with this this package for usage and license information KR KK KR A RA KCkCkCk kCKCkCk KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCK KCk KCK KCk K ck k ck k ckck ck ck kk ck k ok sk e ke X ke x e I f pe CS4215 C al ey x TMS320C3x CRYSTAL 4215 MM CODEC 4 p TMS320C3x CODE wy 5 Compile and archive into CS4215 1lib x y Leor Brenman DSP Applications EJ C 1991 TEXAS INSTRUMENTS HOUSTON BRK IK KR RR A KC kCk kCKCkCk kCKCKCk
431. ogrammer s view of the hardware memory con figuration depicted in Figure 4 18 The logical addresses appearing in pro gram instructions are represented in the context of the entire memory map to identify the respective strobes In this case the STRBO memory transfers op erate on 16 bit data to and from 32 bit wide memory as defined in the STRBO control register STRB1 accesses 8 bit data to and from 32 bit wide memory as defined by the STRB1 control register Since two 16 bit data types can fit in a single 32 bit wide memory location referenced by a single physical ad dress a mechanism is needed to distinguish between the 16 bit data portions This is accomplished by using the least significant bit LSB of the logical ad dress to activate a different pair ofthe four STRBO signal lines for each access leaving the second LSB of the logical address to become the LSB of the physi cal address and effectively shifting the logical address by one bit Similarly STRB1 8 bit data transfers to the 32 bit wide external memory cause the ad dress to be shifted by two bits because the two LSBs of the logical address are used to select one out of four bytes sharing the same physical 32 bit memory location Figure 4 18 32 Bit Memory Configuration STRBO and STRB1 TMS320C32 CCCCCCC eee CCCCCCCL RESET SHZ O10 st COQN CO a amp aaaaaa8 8 X YZE NVHS e TON DooNop oOQN
432. ommand you might enter C csr a user ti simuboard utilities Any string within angle brackets is considered to be a variable In syntax descriptions the variable is written in a typeface similar to that of the text The following is an example of a variable syntax file name Path name of a UNIX file signal Name of a signal In syntax descriptions the instruction command or directive is in a bold typeface font and parameters are in an italic typeface Portions of a syntax that are in bold should be entered as shown below Portions of a syntax that are in italics describe the type of information that should be entered The following is an example of a directive syntax asect section name address In the preceding example asect is the directive This directive has two parameters indicated by section name and address When you use asect the first parameter must be an actual section name enclosed in double quotes the second parameter must be an address Square brackets and identify an optional parameter If you use an optional parameter you must specify the information within the brackets you must not enter the brackets themselves The following is an example of an instruction that has an optional parameter LALK 16 bit constant shift Notational Conventions The LALK instruction has two parameters The first parameter 16 bit con stant is required The second parameter
433. ompile file1 c CCompile file2 c file1 asm sysmem ASCII format file2 asm rts30 lib malloc obj text boot obj text Assemble file0 asm Assemble file1 asm Assemble file2 asm file0 obj vectors file1 obj vectors Stack sysmem COFF format file2 obj heap C cr Cum D boot obj malloc obj file0 obj file1 obj file2 obj Global symbol c intOO defined in boot asm may be used by file0 asm to represent the reset vector file out Vectors section starting address const EUR lon starting address data text section starting address Cinit section starting address length address data length address data length address data bss section starting address Stack section starting address sysmem section starting address COFF format Ink cmd vectors obj Ink cmd file1 obj file2 obj Ink cmd boot obj file1 obj file2 obj Ink cmd file1 obj file2 obj Ink cmd Ink cmd Ink cmd JUBWUOIIAUF 2 e ul uiejs4S Jabiel ZEQOZESWL e bullo0g Booting a TMS320C32 Target System in a C Environment 4 8 1 4 The out COFF File 4 90 After resolving the external references among all program sections the linker builds the out file The out file is constructed in the binary
434. on cycle is synchronized to the rising edge of LRCLK and therefore to the falling edge of FSYNC Although data is shifted out in two separate time packets rep resenting the left and right channel digital outputs the analog inputs are sampled and converted simultaneously In the master mode SCLK FSYNC and LRCLK are generated internally from MCLK depending on the status of the CMODE input pin as shown in Table 8 4 TLC320AD58 Interface to the TMS320C3x Table 8 4 Master Clock to Sample Rate Conversion MCLK Sample Rate MHz CMODE SCLK MHz kHz 12 288 Low 3 072 48 18 432 High 11 290 Low 2 8224 44 1 16 934 High 8 129 Low 2 048 32 12 288 High 0 256 Low 0 064 1 0 384 High The C30 uses two bidirectional serial ports the C31 and C32 each have one Each serial port controls six port pins for receiving transmitting data FSR FSX CLKR CLKX and DR DX Figure 8 10 shows the glueless inter face to the TLC320AD58C using the SCLK FSYNC and DOUT signals Mode 100 is set by pulling the MODE1 and MODE2 pins low and the MODEO pin high The master clock is derived from the C3x to make sure all clock signals are synchronized The C3x is running at 49 152 MHz and provides the required MCLK frequency of 12 288 MHz at the timer 0 output pin in order to get a 48 kHz sample rate CMODE must be pulled low If other sample rates are required see Table 8 4 The TLC320AD58C analog function blocks are initialized together with t
435. on With DMA text section into RAMO data section into RAM1 bss section into RAM1 TITLE ARRAY INITIALIZATION WITH DMA GLOBAL START DATA DMA WORD 808000H DMA GLOBAL CONTROL REG ADDRESS RESET WORD 0C40H DMA GLOBAL CONTROL REG RESET VALUE CONTROL WORD 0C43H DMA GLOBAL CONTROL REG INITIALIZATION SOURCE WORD ZERO DATA SOURCE ADDRESS DESTI WORD _ARRAY DATA DESTINATION ADDRESS COUNT WORD 128 NUMBER OF WORDS TO TRANSFER ZERO FLOAT 0 0 ARRAY INITIALIZATION VALUE 0 0 0X80000000 BSS ARRAY 128 DATA ARRAY LOCATED IN BSS SECTION TEXT START LDP DMA LOAD DATA PAGE POINTER LDI DMA ARO POINT TO DMA GLOBAL CONTROL REGISTER LDI RESET RO RESET DMA STI RO ARO LDI SOURCE RO INITIALIZE DMA SOURCE ADDRESS REGISTER STI RO ARO 4 LDI DESTIN RO INITIALIZE DMA DESTINATION ADDRESS REGISTE STI RO ARO 6 LDI COUNT RO INITIALIZE DMA TRANSFER COUNTER REGISTER STI RO ARO 8 OR 400H IE ENABLE INTERRUPT FROM DATA TO CPU OR 2000H ST ENABLE CPU INTERRUPTS GLOBALLY LDI CONTROL RO INITIALIZE DMA GLOBAL CONTROL REGISTER BU END DMA Assembly Programming Examples In Example 7 1 the DMA initi
436. onfigure the STRB1 control register to 8 bit wide memory 8 bit data size 0x808068 0x00000 Process buffers callDSPoperation buffer8 in buffer8 out The linker command file in Example 4 5 allocates sections of the above C code into the desired memory configuration Example 4 5 Linker Command File sample obj Input filename A stack 8704 Set C system stack size o sample out Specify output file xy m sample map Specify map file x MEMORY PRGRAM org 0x0000 len 0x2000 STRBORAM i org 0x2000 len 0x6000 ONCHIRAM t org 0x87Fe00 len 0x200 STRB1RAM org 0x900000 len 0x8000 SECTIONS text gt PRGRAM 32 bit data section Cinit gt STRBORAM 32 bit data section const STRBORAM 32 bit data section bss STRBORAM 32 bit data section stack gt STRBORAM 32 bit data section f mydata8 gt STRB1RAM 8 bit memory pool mapped to STRB1 ff Memory Interfacing 4 79 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface 4 7 5 2 Single External Memory Bank 4 80 Consider the case of a typical audio compression application written in C that requires 32 bit data for the system stack and 16 bit data for the audio buffers In this case the programmer can interface the C32 as shown in Figure 4 34 This example assumes 32K 32 bit words of external memory This memory is further defined as c
437. ontaining 8 5K 32 bit words of stack and 8K 32 bit words of program space both areas are mapped to STRBO program space includes constants and global static variables Also external memory contains 32K 16 bit word data buffers that are mapped into STRB1 Due to this mapping the programmer must set the following D STRBO control register physical memory width to 32 bits and the data type size to 32 bits DD STRB configuration bit field to 1 STRBO control register 002F0000h D STRB1 control register physical memory width to 32 bits and the data type size to 16 bits that is STRB1 control register 000D0000h Additionally the PRGW pin must be pulled low to indicate 32 bit program memory width How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface Figure 4 34 Zero Wait State Interface for 32 Bit SRAMs with 16 and 32 Bit Data Accesses TMS320C32 lt 32 bit wide memory banks gt A22 Pm A14 Pm A14 m gt A14 Pm A14 A13 gt A13 gt A13 gt A13 gt A13 A12 gt A12 gt A12 gt A12 Pm A12 A11 gt A11 gt A11 gt At gt An A gt A4 gt A H A gt A RW We gt YE w gt WE p CS 3 4 CS m CS rJ CS STRBO B3 l O 7 0 l O 7 0 l O 7 0 l O 7 0 STRBO B2 A A STRBO Bi STRBO BO D 31 24 lt D 23 16 amp D
438. operations to the converter The chip select input must be active when accessing the device Enabling the chip select function is necessary to isolate the AD1678 from other peripheral devices connected to the expansion bus To establish the desired operating modes the SYNC and 12 8 inputs to the converter are pulled high and EOCEN is grounded as specified in the AD1678 Data Sheet In this application the converter s chip select is driven by XA12 which maps this device at 804000h in I O address space Conversions are initiated by writ ing any data value to the device The conversion results are obtained by read ing from the device after the conversion is complete To generate the device s start conversion SC and output enable OE inputs the 74AS32 performs an AND operation on IOSTRB and R W see Figure 8 1 Therefore the conver ter is selected whenever XA12 is low OE is driven when reads are performed and SC is driven when writes are performed Analog to Digital Converter Interface to the TMS320C30 Expansion Bus Figure 8 1 Interface Between the TMS320C30 and the AD1678 XA12 12V 5V IOSTRB XR W e lH d low 74AS32 74AS04 ior Ycc VDD OR OE REFOUT XA12 SC CS 500 12 8 REFIN ONE SYNC 74AS32 74LS244 EOCEN V XD0 18 iy 1A1 2
439. oportional to the time shift and the frequency of interest If the time shift is one sample period as used in the SFFT special conditions can be applied At low frequencies the amount of phase shift from sample to sample is low or in the case of 0 Hz zero radians of phase At higher frequen cies the phase rotation is greatest At the Nyquist frequency the vector rota tionis pi 2 radians per sample which corresponds to 2 samples per sine wave cycle Vector rotation for bins between DC and the Nyquist rate are proportion al to the bin frequency Sliding FFT A Fourier transform also produces both negative and positive frequencies which are mirror images of each other Only positive frequencies need to be computed This is suitable for spectrum analysis and filtering The ranges for n and the resulting complex rotation vectors twiddle factors for each bin are Positive frequencies 0 lt n lt N 2 Negative frequencies N 2 lt n lt 0 complex R phase I phase exp J 2 pi n N REAL tw n cos n 2 pi N IMAG tw n sin n 2 pi N The basic SFFT operation is a vector rotate of each previous bin value that is add the newest sample and subtract the oldest sample Although it is a sim ple operation all bins must be computed before the next input sample is ready NewBinVal New Old OldBinval vect rotate Bin n Sample 0 Sample N 1 Bin n exp J 2 pi n N 6 8 3 Visualizing the SFFT The easiest w
440. or bank decode because they lie outside the used address bits A17 and A18 decode between banks 1 2 and 3 with A18 A17 0 1 assigned to bank 1 1 0 assigned to bank 2 and 1 1 assigned to bank 3 Address bit A23 is set to 0 to isolate the STRBO ad dress space from the STRB1 and IOSTRB memory maps The dotted lines bounding the bank decode bits allow you to see that the exter nal address bits A18 A17 line up perfectly but their logical address counter parts do not The amount of reverse shift between the logical and physical ad dresses depends on the size of the data being accessed and the width of the physical memory Each of the three address translation cases for each of the three banks translates physical address bits A18 A17 into two contiguous logical address bits that can lie anywhere between A20 and A17 Once the log ical images of the external bank decode bits are identified along with low order address bits and the A23 strobe decode bit they define the final logical memory map for the three STRBO banks together Interfacing Memory to the TMS320C32 DSP Figure 4 31 Adaress Decode for Multiple Memory Banks
441. ory interface to fetch instructions in one bus cycle per instruction 32 bits at a time Table 4 5 Program Fetch From 32 Bit STRB1 Memory Data Access Strobe Data Size Memory Width Input Data STRBO 32 32 Output Data STRB1 32 32 Program IOSTRB 32 32 Memory Interfacing 4 31 Figure 4 14 Program Fetch From 32 Bit STRB1 Memory 32 bits Logical memory map U STRBO R IOSTRB STRBO STRB1 gt TMS320C32 e STRB Memory Data s STRBO configuration width size control is register STRBO i g STRBO 32 bits 32 bits 1003h g E 10058 5 Q 105 SURE 32bits 32 bits A ROL 108 25 EA a Sa STRBO 5 E data read s go A z Physical memory Logical address vy 32bits e o Be e v TASTE 101 0 820001h IOSTRB NL 1003h ARo daa rite 102 0 820002h ALU Control 820003h 910003h PC FPU F 32 bits 104 0 820004h 105 0 820005h H820003h AR1 CE aiie A e e i T Physical memory Logical address 0 9 pm S STRBi 32 bits 2m program D fetch R1 103 0 S to M 40 bit 32 bits 5 77 32 bits LDI 4 RC 910001h ix i RPTB Li 910002h LDI ARO RO 910003h PRGW pin Float RO R1 910004h L1 STF R1 AR1
442. otal Supply Current The previous sections discuss currents contributed by several sources on the C30 Because actual current values are unique and independent for each source each current source is discussed separately In an actual application however the sum of the independent contributions from each current deter mines the total current requirement for the device This current value is the total current supplied to the device through all of the Vpp inputs and returned through the Vss connections Note that numerous Vpp and Vss pins on the device are routed to a variety of internal connections not all of which are common Externally however all of these pins must be connected in parallel to a 5 volt source and use ground planes with as little impedance as possible 12 4 1 Combining Supply Current from All Factors To determine the total supply current requirements for any given program activity calculate each of the appropriate factors and combine them in the fol lowing sequence 1 Start with 110 mA quiescent current 2 Add 55 mA for internal operations unless the device is dormant Dormant periods occur during the execution of IDLE NOPs branches to self or performance of internal and or external bus operations using an RPTS instruction see section 12 2 2 on page 12 5 Internal or external bus operations executed through RPTS do not contribute an internal opera tions power supply current factor However current factors in
443. ote This number does not include the C callable overheads Add 57 cycles for these overheads Entry execution point Reserve memory for arguments 6 44 Fast Fourier Transforms FFTs Example 6 16 Real Forward Radix 2 FFT Continued F Initialize C function sect ffttext EEFE rl PUSH FP Preserve C environment LDI SP FP PUSH R4 PUSH R5 PUSH R6 PUSHF R6 PUSH R7 PUSHF R7 PUSH AR4 PUSH AR5 PUSH AR6 PUSH AR7 PUSH DP LDP FFT SIZE Init DP pointer LDI FP 2 R0 Move arguments from stack STI RO QFFT SIZE LDI FP 3 RO STI RO LOG_SIZE LDI FP 4 RO0 STI RO SOURCE_ADDR LDI FP 5 RO STI RO DEST_ADDR LDI FP 6 RO STI RO SINE_TABLE LDI FP 7 RO0 STI RO BIT_REVERSE i Check bit reversing mode on or off y BIT REVERSING 0 then OFF no bit reversing BIT REVERSING 0 Then ON i LDI BIT_REVERSE RO CMP I 0 RO BZ MOVE_DATA i Check bit reversing type r If SourceAddr DestAddr then in place bit reversing If SourceAddr DestAddr then sta
444. oted This document provides information to assist managers and hardware soft ware engineers in application development Specifically this book complements the TMS320C3x User s Guide by provid ing information to assist you in application development It includes example code and hardware connections for various appliances This guide presents examples of frequently used applications and discusses more involved examples and applications It also defines the principles in volved in many applications and gives the corresponding assembly language code for instructional purposes and for immediate use Whenever a detailed explanation of the underlying theory is too extensive to be included in this manual appropriate references are given for further information Notational Conventions Notational Conventions This document uses the following conventions E Program listings program examples and interactive displays are shown ina special typeface thatis similar to that of a typewriter Examples use a bold version of the special typeface for emphasis Interactive displays use a bold version ofthe special typeface to distinguish com mands that you enter from items that the system displays such as prompts command output error messages etc The following is a sample program listing 0011 0005 0001 field I 2 0012 0005 0003 field 3 4 0013 0005 0006 field 65 3 0014 0006 even The following is an example of a system prompt and a c
445. patible integrated circuit crystal oscillators are available across a wide frequency range These are more expensive than the internal oscillator and usually consume more space on the board CMOS oscillators also be come more expensive with higher operating frequency Quartz Crystal and Ceramic Resonators 9 2 Quartz Crystal and Ceramic Resonators All oscillators require resonating components to determine the frequency of oscillation A resonating component reacts more strongly within a certain fre quency range than at other frequencies outside that range A simple resonator consists of an inductor L and a capacitor C These components resonate or favor the frequency at which their individual reactances cancel each other Figure 9 1 shows a simple series LC resonator with impedance equations Figure 9 1 Series LC Schematic Lx Cx The impedance equations for the series LC schematic are as follows ZL joL Ze 1 jaC Zt ZL Zcz j oL 1 wC Zis minimum where oL 1 wC 1 1 gt Ws LC LC Consider the impedance of the series combination of these components The impedance ofthe inductor Z joL where o is the angular frequency w 2zf and the impedance of the capacitor Ze 1 jwC The total impedance of the inductor capacitor combination is Z ZL Ze j WL 1 wC Therefore the magnitude of the combined impedance of these two components is a minimum at the frequency where oL 1 wC This frequency ws is the reso
446. perfor mance depends on many factors experimentation may be required Sliding FFT AIC setup registers are programmed into the AIC using a data word which is tagged with xxxx11b in the bottom 2 LSBs to signal the AIC to accept a secon dary transmit or register program word The DAC switch cap filter rate high is set by the TA divisor A low TA value used to overclock the DAC reconstruction filter trades signal fidelity for faster impulse response times This application was designed and tested using a 50 MHz TMS320C31 DSP Starter Kit TMDS3200031 which includes a TLC32040 14 bit ADC DAC DSP Algorithms 6 93 Sliding FFT Example 6 18 SFFT ASM SFFT2 ASM Keith Larson TMS320 DSP Applications C Copyright 1996 1997 1998 Texas Instruments Incorporated liabilities See This is unsupported freeware with no implied warranties or the C3x DSK disclaimer document for details SPECT EN E Fs H Hz bin Range s If this fil Default setup 20 40 1 3 Khz 3 9 Khz 8 khz 4 8 uS 7 hz is r assembled with SP ECT EN set to 0 this will give a bandpass filter from 1 3 3 9 Khz having 90 degrees phase shift at all frequencies SFFTSIZE set 512 Sample Window length FFT size BIN START set 32
447. pin con nector that routes the signals to the DSP s emulation pins The emulation pins control the operation of the modular port scan device MPSD scan chain in the processor Depending on the command issued by the debugger the emulation circuitry in the scan chain stops or resumes processor operation examines loads registers or memory sets breakpoints or executes code one instruction at a time called single step execution The debugger LOAD com mand reads the COFF file from the PC hard drive extracts program data con tent and transfers it through the emulator cable to the target board s memory Memory Interfacing 4 91 Booting a TMS320C32 Target System in a C Environment 4 8 3 1 RAM Model Linker cr Option When the COFF file is loaded into the target board s memory most sections in the file are processed by copying the program data to the address defined at the beginning of each section however the initialized variables in the cinit section are processed differently If the COFF file is generated by the linker us ing a cr option the cinit section of the file is loaded using the RAM model see Figure 4 38 The RAM model assumes that the target memory is composed exclusively of SRAM devices Thus the initialized variables can be directly co pied to the SRAM bss section one array at a time without first placing them in a temporary EPROM cinit section Once the initialized variables have been loaded into SRAM they ca
448. placed by i k It is assumed that i kis less than 32 Logical and Arithmetic Operations Integer and Floating Point Division 3 4 2 Floating Point Inverse and Division This section explains how to implement floating point division on the C3x Since the algorithm outlined here computes the inverse of a number v to perform y v multiply y by the inverse of v The computation of 1 v is based on the following iterative algorithm At the ith iteration the estimate x i of 1 vis computed from v and the previous esti mate x i 1 according to the following formula x i x i 1 x 2 0 v x x i 1 To start the operation an initial estimate x 0 is needed If v 2 a x 29 a good initial estimate is x 0 1 0 x 2 e 1 Example 3 6 shows the implementation of this algorithm on the C3x where the iteration has been applied five times Both accuracy and speed are af fected by the number of iterations The accuracy offered by the single preci sion floating point format is 2 23 1 192E 7 If you want more accuracy use more iterations If you want less accuracy reduce the number of iterations to decrease the execution time This algorithm properly treats the boundary conditions when the input number either is O or has a very large value When the input is 0 the exponent e 128 Then the calculation of x 0 yields an exponent that is equal to 128 1 127 and the algorithm overflows and saturates On the oth
449. propriately initialized At this point a CALL is made to the subroutine transfer ring control to that section of the program memory for execution then returning to the calling routine through the RETS instruction when execution has com pleted For Example 2 1 it would suffice to save only register R2 However many registers are saved for demonstration purposes The saved registers are stored on the system stack This stack must be large enough to accommodate the maximum anticipated storage requirements You can use other methods of saving registers also Example 2 1 Subroutine Call Dot Product Subroutines TITLE SUBROUTINE CALL DOT PRODUCT MAIN ROUTINE THAT CALLS THE SUBROUTINE DOT TO COMPUTE THE DOT PRODUCT OF TWO VECTORS LDI b1k0 ARO P ARO points to vector a LDI b1k1 AR1 H AR1 points to vector b x LDI Ny RG H RC contains the number of elements CALL DOT SUBROUTINE DOT EQUATION d a 0 b 0 a 1 b 1 a Nt1 b Nt1 THE DOT PRODUCT OF a AND b IS PLACED IN REGISTER RO N MUST BE GREATER THAN OR EQUAL TO 2 ARGUMEN ASSIGNMENTS ARGUMENT FUNCTION ARO ADDRESS OF a 0 AR1 ADDRESS OF b 0 RC LENGTH OF VECTORS N REGISTERS USED AS INPUT ARO AR1 RC REGISTER MODIFIED RO RE
450. pt Vector Table Listing i 8 38 Vemm 8 40 8 41 General ht eT oo e E E e a e E E NRS 8 44 GommldrvEh nere rt i iea R a RE RA 8 46 reip cR 8 47 CoO42190 MR 8 49 CS4215 6 225 2 et es 8 59 Full Duplex UART Emulator for TMS320C3x i 8 67 Contents xxvii xxviii Chapter 1 Processor Initialization Before you execute a DSP algorithm you must initialize the processor Initializa tion brings the processor to a known state Generally this occurs anytime after the processor is reset This chapter reviews the concepts of processor initializa tion explained in the user s guide and provides examples Topic Page Wal Reset Process qr SEES EPI 1 2 129 nesetiSignaliGenerationr perpe a 1 3 1 3 How to Initialize the Processor ccee cence eee eens 1 4 1 4 Low Power Mode Interrupt 00 ccc eee eee eee eee eee 1 9 Reset Process 1 1 Reset Process You can reset the processor by applying a low level to the RESET input for atleast ten H4 cycles The C3x terminates execution and puts the reset vector the contents of memory location 0 in the program counter The reset vector nor mally contains the address of the system initialization routine The hardware reset also initializes various registers and status bits In order to reset the C3x correctly you need to comply with several hardware and software requirements lfthe C31 or C32 is in microcomputer mode set the INTx pins as dis cussed in U
451. q uoroes 1xer 1000 ino 9 y INVHS ol Wau peol ol Mou ueJ6od Japeo joog diuo uo y jonusul 0 Suonoes ssoul oj spjow 0431009 amp 1xe Sppe pue pe1ooq aq ol suonoes eui seynuep C puejsiepun ueo Jeuuwuei6oid NOHd3 ue ey ei OSV 1euuoj pyepuels e 0 l 4400 AeulqeylsheAuo0 7 Buimollo eui seop AlIqn UOISJBAUOD xeu eu uondQ 42 4exur UO Jeues Buisf S0H Wo 100g pp p o1n614 4 104 Booting a TMS320C32 Target System in a C Environment UUM pJeoq dSq 0 pejeduioo selsoo uaelsAs peonpei 104 e qe1100q eui 9104S 01 NOHd31S0U sesn uiejs s dS eu 9pI SYA ZE uonoes ssq Blep z l d uonoes ssq ejep Helld ZNVHS NvHS ou Apop Way peol o pue alqel 100q y 40 selhqIenplAIpul jqw sse 0 f1d2 eui sesn Jepeol jooq diuo uo ayy Jod jenas au Woy JO Suolleool jouieul 99JU Jo ouo wo e qe1100q eui Bulpeel Suejs Jepeo 1009 ubiu seob 3s3u u ym Mol SI XINI ylym uo Buipuddeq 99A jeseu Jasay uels g
452. r OUTPUT BUFFER SIZE extern int r buffer INPUT BUFFER SIZE extern VPVF output0 OUTPUT DATA BUFFER FOR PROCESSOR extern VPVF input0 INPUT DATA BUFFER FOR PROCESSOR extern VPVF output xfer0 OUTPUT DATA BUFFER FOR ISR BB extern VPVF input xfer0 INPUT DATA BUFFER FOR ISR BB extern VPVF outputl OUTPUT DATA BUFFER FOR PROCESSOR extern VPVF inputl INPUT DATA BUFFER FOR PROCESSOR extern VPVF output_xferl OUTPUT DATA BUFFER FOR ISR BB extern VPVF input xferl INPUT DATA BUFFER FOR ISR BB extern VI buffer rcvd CPU ISR COMM FLAG INPUT extern VI buffer xmtd CPU ISR COMM FLAG OUTPUT extern VI r index INDEX INTO INPUT AND OUTPUT DATA ARRAYS extern VI t index INDEX INTO INPUT AND OUTPUT DATA ARRAYS extern VI Big GENERIC COUNTER VARIABLE 8 KK Ck Ck kk kk Ck kk Ck Ck Ck Ck Ck Kk Ck Ck Ck Ck Ck Ck Ck Ck Ck kk Ck kk kk kk ke ko ke ke ke ko ke ke ke ke ke eoe e e e e FUNCTION PROTOTYPES J KCKCKCKCK Ck kk kk kk Ck Ck Ck Ck Ck Ck Ek Ck Ek Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck kk kk kk ke ko ke ke ke ke ke ke ke ke ke ke e e e e e BB DRIVER FUNCTIONS JC Kk e ke e ke e ke e ke e ke e ee e e e x void init arrays int t buffer size int r buffer size void init bb int period value if SER NUM void c int07 void else void c_int05 void endif
453. r Figure 6 10a of data is kept in memory a sliding rectangular window of data samples Figure 6 10b and Figure 6 10d can be constructed by adding the newest sample and subtracting the oldest sample Figure 6 10c from the previous original windowed signal Figure 6 10b The following diagram shows how the addition and subtraction of samples can slide a window of data samples from those shown in Figure 6 10b to those shown in Figure 6 10d Sliding FFT Figure 6 10 Input Signal Sample Buffer Older Newer a Input signal sample buffer ene AULT ATL UTI b Original windowed signal Ue eee c New old sample window Subtract old T N T 0 Add new d Next windowed signal t AT Window is time shifted 1 sample Note T time 2 The frequency domain response of an impulse or single sample point where all other data points are zero results in a flat frequency response with a magnitude in each frequency bin equal to the impulse input magni tude Conversely the impulse is the additive result of many sinusoidal fre quency components The time when the impulse occurs within the sample window is determined by the phase angles of the individual component frequencies An impulse s time of arrival is determined by a linear phase shift between each frequency bin DSP Algorithms 6 81 Sliding FFT 3 In the frequency domain the addition of frequency samples also follows
454. r the C32 the programmer does not have to be con cerned aboutthe structure of the physical memory The programmer must sim ply be aware of the logical memory map and the configuration of the two strobe control registers The C32 memory interface automatically performs all of the address translation tasks and byte packing unpacking necessary to match variable size data with physical memories of different widths they are con trolled by the data size and memory width fields of the STRBO and STRB1 con trol registers Memory Interfacing 4 47 Figure 4 23 16 Bit and 8 Bit Memory Address Translation Data Size lt Memory Width dSd ZED0ZESWL eui 0 Aiowayy Bureau STRB Memory Data configuration width size Physical Logical Logical STABO address pou Rods control eee 0 0 1 11 eoo register STRBO 16 bits 8 bits MU D U Y e CN eo EE EE a a e a Cr Cr Cr a eo 1 Oh 5 l D D Oh 2 1 STRBO 2 A15 f S b 3 Logical address e r M ooo 0000 oo ia dao al 6 5 n 0000 0000 1 e Physical address e e N A14 A 1 e x 65534 65535 65532 65531 IOSTRB mn FFFFh Y 6553465533 8 bit data size address shifted by 2 bits 7FFFh 65536 65535 STRBO STRB1 Interfacing Memory to the TMS320C32 DSP 4 6 5 One B
455. racteristics of the filter Figure 6 13 Raised Cosine Window Function Length 1 Bin 6 86 Sliding FFT Figure 6 14 Raised Cosine Window Function Length 2 Bins 10 ft Figure 6 15 Raised Cosine Window Function Length 3 Bins 1 0 1 0 Lol l I Figure 6 16 Raised Cosine Window Function Length 4 Bins 1 0 1 0 I 1 0 DSP Algorithms 6 87 Sliding FFT 6 8 9 Non Windowed SFFT A special case occurs when the SFFT is used to compute the all pass 0 and 90 Hilbert transforms of a non windowed synchronized signal Frequency bin spreading occurs if the signalis not harmonically related to the sample window For REAL summations the input is reconstructed by scaling the 0 or DC bin by 50 This scaling compensates for a 2 1 rise in signal level since all bin data energy except for the 0 bin is split equally between the positive and negative frequencies At the 0 bin there is no IMAG information since no phase shift is applied to that bin A DC component for an IMAG reconstruction therefore does not exist Figure 6 17 N 2 SFFT P I Bins 6 8 10 Performance 6 88 IMAGSUM Since the SFFT needs only to compute the bins of interest within the span of one time sample narrow band analysis or filtering is very efficient even when the effective FFT size is very large If large numbers of bins and or high sam pling rates are impractical for a single processor a
456. ram counter is modified at the end of the loop Therefore no operation should attempt to modify the repeat counter or the pro gram counter at the end of the loop It is possible to nest repeat blocks however there is only one set of control registers RS RE and RC It is necessary to save these registers before entering an inside loop You can implement a nested loop by using a register as a count er and then using a delayed branch rather than using the nested repeat block approach Example 2 8 shows how to use the block repeat to find a maximum of 147 numbers Program Control 2 19 Repeat Modes Example 2 8 Use of Block Repeat to Find a Maximum ITLE USE OF BLOCK REPEAT TO FIND A MAXIMUM EDI LDI LD RPTB CMPF LOOP LDFLT THIS ROUTINE FINDS THE MAXIMUM OF N 147 NUMBERS 146 RC Initialize repeat counter to 147 1 ADDR ARO ARO points to beginning of array ARO 1 RO Initialize MAX to the first value LOOP ARO 1 RO Compare number to the maximum tARO 1 RO0 If greater this is a new maximum 2 6 2 Single Instruction Repeat 2 20 The single instruction repeat uses the control registers RS RE and RC in the same way as the block repeat The advantage over the block repeat is that the instruction is fetched only once and then the buses are available for moving operands The single instruction repeat construct is not interrupt
457. ration of the RDY sig nal The example involves three memory banks controlled by STRBO each re quiring a different number of wait states This example directly applies to RDY signal generation involving STRB1 andis similartothe case of IOSTRB which involves a more relaxed set of timing parameters 4 6 6 1 RDY Signal Timing Parameters for STRBO and STRB1 4 58 Figure 4 28 and Table 4 6 contain STRBO and STRB1 timing parameters that are typically used to generate the RDY signal As evident in the read and write timing waveforms the RDY signal generated by the external logic is clocked into the C32 on the falling edge of the H1 clock The associated setup time is represented by parameter 17 and the hold time by parameter 18 Thus for the 60 MHz C32 the RDY signal must arrive at the RDY pin at least 17 ns before the falling edge of H1 and remain valid at least until H1 goes low Timing pa rameters 11 and 12 representthe STRBO and STRB1 low and high delays from the falling edge of H1 Timing parameter 14 represents the address valid delay from the falling edge of H1 For back to back write cycles timing parameter 22 represents the address valid delay from the rising edge of H1 Parameters 11 12 14 and 22 do not directly apply to RDY setup and hold but are never theless involved in the generation of the RDY signal Interfacing Memory to the TMS320C32 DSP Figure 4 28 RDY Signal Timing for STRBO and STRB1 Cycles
458. rative These algo rithms can greatly reduce development time and decrease time to market The expertise of those involved in support services ranges from speech encoding and vector quantization to software hardware design and system analysis For a more detailed description of services and products offered by third par ties See the TMS320 Third Party Support Reference Guide and the TMS320 Software Cooperative Data Sheet Packet Call the Literature Response Cen ter at 800 477 8924 to request a copy Development Support 11 1 3 Technical Training Organization TTO TMS320 Workshop The C3x DSP design workshop is tailored for hardware and software design engineers and decision makers who design and use the C3x generation of DSP devices Hands on exercises throughout the course give participants a rapid start in using C3x design skills Microprocessor assembly language ex perience is required Experience with digital design techniques and C lan guage programming experience is desirable The following topics are covered in the C3x workshop C3x architecture instruction set Use of the PC based C3x software simulator and EVM Floating point and parallel operations Use of the C3x assembler linker C programming environment System architecture considerations Memory and I O interfacing C3x development support O O O O O O O L For registration pricing or enrollment information on this and other TTO TMS320 workshops call
459. re and software addressing view points 4 6 3 1 32 Bit Memory Address Translation for Data Size Memory Width When both data size and memory width are 32 bits the STRBO memory inter face behaves like the IOSTRB memory interface The only difference between the two is the number of strobe lines connected to the respective memory banks four for STRBO and one for IOSTRB Figure 4 16 is a schematic diagram of a 32 bit interface consisting of two memory banks each controlled by a separate strobe The four signal lines of STRBO are assigned to the chip select pins of four 32K x 8 15 ns SRAMs The single IOSTRB signal line is connected to the chip enable pins of four 32K x8 30 ns EPROMs For the 60 MHz version of the C32 the 15 ns SRAMs operate with zero wait states and the 30 ns EPROMs require one wait state Software wait states can be programmed in the strobe control regis ters The hardware memory configuration is depicted in Figure 4 16 Figure 4 17 illustrates the programmer s view of the hardware memory configuration The logical addresses appearing in program instructions are represented in the context of the entire memory map to identify the respective strobes The physi cal addresses are the values that actually appear at the pins of the processor Since IOSTRB operates exclusively on 32 bit data types the memory inter face does not modify the address going in and out of the CPU the logical and physical addresses are
460. reau STRB Memory Data Logical Logical configuration width size Physical memory dd Address map address STRBO amp 1 32 bits 32 bits STRBO control register ee 1 1 1 1 1 OOO STRB1 control register eee 11 00 eee ipl Il un 32 bits 8 bits CA a ae a a a a 2 2 g g red fe EE oc D 5 iz t 1 880000h Oh 1 2 2 3 M7 it o 3 I Logical address STRBO l e ag top Mo Pad Vida Taide l Pa 1000 10o 00 e Physical address j 7 A ho 16382 16383 16382 I 32 bit data size address not shifted 3FFFh 16384 IOSTRB 8 bit data size address shifted by 2 bits 4000h 4 3 2 1 I jy J 980000h 8 7 6 5 l j Alg A15 Ao 12 11 10 9 2 Logical address I e 1001 io o o BIER RE LJ 1001 000 11 4 PI Physical address 9 saan A17 A13 Ao STRBO 65534 65528165527 65526 65525 STRBT 65539 v 65532165531 65530 65529 BN 65536 98FFFFh 7FFFh 65535 65534 65533 B1 STRBO B2 STRBO BO STRBO B3 STRBO Le Interfacing Memory to the TMS320C32 DSP 4 6 5 3 One Bank Two Strobes Address Translation for Data Size 16 and 32 Bits Figure 4 27 illustrates how a single physical block of memory can be split into two separate logical halves one with 16 bit data and the other with 32 bit data The access to each half is controlled by a separate strobe control register with corresponding memory width and
461. renman DSP Applications I C 1991 TEXAS INSTRUMENTS HOUSTON KR KKK RR IR AR kCk kCkCkCk KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCKCKCk KCKCk Ck K ck k ck kc kck ck ck ckck ck k kk e ke X sk x e I f include lt math h gt include lt stdlib h gt include lt c30_per h gt include lt commdrvr h gt p MACROS a A define BLOCK SIZE 64 define SER NUM SERIAL PORT ONE define TIMER NUM TIMER ONF define XF NUM 1 define INIT ARRAYS init arrays buffer size define WAIT BUFFERS while buffer rdy define RESET FLAGS buffer rdy FALSE define RESET CODEC IMER ADDR TIMER NUM gcontrol I O HLD_ define UN RESET CODEC IMER ADDR TIMER NUM gcontrol I O HLD DATOUT if XF NU define DCB LOW asm AND 2fh IOF asm OR 20h IOF define DCB HI asm OR 60h IOF else define DCB LOW asm AND OF2h IOF asm OR 2h IOF define DCB HI asm OR 6h IOF endif define WAIT A for i20 i A i 4 define C ISR ON Analog Interface Peripherals and Applications 8 49 CS4215 Interface to the TMS320C3x Example 8 15 CS4215 h Continued unsigned int intval 2 CS4215 DATA COMMAND BIT FIELD DATA STRUCTURES CONTROL COMMAND typedef union struct Time slo unsigned in unsigned in unsigned in
462. rent Versus Frequency and Supply Voltage pp 12 18 Current Versus Operating Temperature Change i 12 19 La 12 22 Photo of Ipp 12 26 Boot From a 32 Bit Wide ROM to 8 16 and 32 Bit Wide RAM A 2 Boot From a 16 Bit Wide ROM to 8 16 and 32 Bit Wide RAM A 3 Boot From a Byte Wide ROM to 8 16 and 32 Bit Wide RAM uuuuuus A 4 Boot From Serial Port to 8 16 and 32 Bit Wide RAM i A 5 TMS320C32 Boot Loader Program Flowchart i B 3 Memory Allocation in C Programs pp C 2 Dynamic Memory Allocation for TMS320C32 One Block of 32 Bit Memory C 4 Dynamic Memory Allocation for TMS320C32 One Block of 16 Bit Memory C 5 Dynamic Memory Allocation for TMS320C32 One Block Each of 32 16 and Bi Memlory uus chat a data ed x uS aka pee hada ae eum e su UR ARR C 6 Data and Program Packing Program and a Single Data Size iss D 2 Data and Program Packing Program and Two Different Data Sizes D 3 Address Translation for 32 Bit Data Stored in 32 Bit Wide Memory D 6 Address Translation for 16 Bit Data Stored in 32 Bit Wide Memory D 7 Address Translation for 8 Bit Data Stored in 32 Bit Wide Memory D 8 Address Translation for 32 Bit Data Stored in 16 Bit Wide Memory D 9 Address Translation for 16 Bit Data Stored in 16 Bit Wide Memory
463. res that the TCINT bitin the DMA control register be set first This inter rupt polling method does not cause any additional conflict during CPU DMA access The transfer counter has a zero value The transfer counter is decrem ented after the DMA read operation finishes not after the write operation Nevertheless a transfer counter with a zero value can be used as an in dication of a transfer completion The STAT bits in the DMA channel control register are set to 009 You can poll the DMA channel control register for this value However because the DMA registers are memory mapped into the peripheral bus address space this option can cause further conflicts during CPU DMA access Programming the DMA Channel 7 3 DMA Assembly Programming Examples 7 3 DMA Assembly Programming Examples Example 7 1 Example 7 2 and Example 7 3 illustrate how to program the DMA channel using assembly language When linking the examples allocate section memory addresses carefully to avoid CPU DMA conflict In the C30 or C31 the CPU always prevails in cases of conflict If a conflict occurs between a CPU program and DMA data you can enable the cache if the text section is in external memory For example when linking the code in Example 7 1 Example 7 2 and Example 7 3 allocate the following sections into memory RAMO corresponds to on chip RAM block 0 and RAM corresponds to on chip RAM block 1 m Example 7 1 Array Initializati
464. reset the host transfers the boot table to the DSP to initialize it and start program execution 4 8 6 1 Boot From Serial Port If the DSP powers up in the microcomputer boot loader mode MCBL MP high the low on the INT3 pin and high on all other INTx pins causes the on chip boot loader program to read the boot table from the serial port Most mi crocontrollers also feature a serial port and in many cases the two ports can be connected directly without additional glue logic for an economical host DSP interface Following the boot the serial channel can also be used by the host to send receive data and to control the operation of the DSP see Figure 4 44 on page 4 104 Generating the boot table requires linking the object files with the cr option RAM model and then appending the hex utility s SECTIONS directive with the boot keyword to identify the COFF sections to be included in the boot table 4 8 6 2 Boot From a Laich 4 102 If the host processor does not have a serial port the DSP can be booted from the host using an 8 bit latch During the boot operation the host feeds the boot table bytes to the latch on one side while the DSP reads the data from the oth er Following reset interrupts 0 1 and 2 direct the DSP boot loader to the latch address The same interrupts cause the boot loader to read from the parallel port so some control decode logic is required to make the DSP read from memory instead of from a latch The sam
465. rl sti RO GTO count Set counts to 0 ldi TIMO prd RO Set period sti RO TO_prd H ldi Ox2C1 R0 Restart both timers sti RO TO_ctrl E DSP Algorithms 6 99 Sliding FFT Example 6 18 SFFT ASM Continued ldi SOxctrl1l RO sti RO SO_xctrl transmit control ldi SOrctrl1 RO sti RO SO_rctrl receive control ldi 0 RO sti RO SO_xdata DXR data value ldi SOgctrl RO Setup serial port sti RO SO_gctrl global control r This section of code initializes the AIC n Fr AIC INIT LDI 0x10 IE Enable only XINT interrupt andn 0x34 IF ldi 0 RO sti RO SO_xdata n RPTS 0x040 LDI 2 IOF XF0 0 resets AIC rpts 0x40 LDI 6 IOF XF0 1 runs AIC idi C_REG RO Setup control register call prog AIC ldi Oxfffc RO Program the AIC to be real slow call prog AIC ldi Oxfffc 2 R0 call prog AIC ldi B_REG RO Bump up the Fs to final rate call prog_AIC smaller divisors should be sent last ldi A_REG RO gt call prog AIC or OVM ST Use the overflow mode for fast saturate b main the DRR before going to the main loop i prog AIC is used to transmit new timing configurations to the AIC If you single step this routine the AIC timing will be corrupted causing AIC programming to fail STEP OVER THIS ROUTINE USING THE F10 FUNCTION STEP r
466. rnal interrupt To use the IDLE2 power management feature effectively interrupts must be gen erated with or without the presence of the H1 clock For normal non IDLE2 operation however the interrupt inputs must be synchronized with the falling edge of the H1 clock An interrupt must satisfy the following conditions It must meet the setup time on the falling edge of H1 D It must be at least one cycle and less than two cycles in duration Foraninterruptto be recognized during IDLE2 operation and to turn the clocks back on it must first be held low for one H1 cycle The logic in Figure 1 2 can be used to generate an interrupt signal to the C3x with the correct timing dur ing non IDLE2 and IDLE2 operation Figure 1 2 shows the interrupt circuit which uses a 16R4 programmable logic device PLD to generate the ap propriate interrupt signal Figure 1 2 Interrupt Generation Circuit for Use With IDLE2 Operation C3x TIBPAL16R4 Interrupt INTx lt source Pe 12 H1 P CLK Example 1 3 shows the PLD equations for the 16R4 using the ABEL lan guage This implementation makes the following assumptions regarding the interrupt source The interrupt source is a low going pulse or a falling edge If the interrupt Source stays active for more than one H1 cycle itis regarded as the same interrupt request and not a new one The interrupt source is at least one H1 cycle in d
467. rocessor literature number SPRS032A data sheet contains the electrical and timing specifications for this device as well as signal descriptions and pinouts for all of the available packages TMS320C31 TMS320LC31 Digital Signal Processors literature number SPRS035 data sheet contains the electrical and timing specifications for these devices as well as signal descriptions and pinouts for all of the available packages TMS320C32 Digital Signal Processor literature number SPRS027C data sheet contains the electrical and timing specifications for this device as well as signal descriptions and pinouts for all of the available packages TMS320 DSP Development Support Reference Guide literature number SPRUO 11 describes the TMS320 family of digital signal processors and the tools that support these devices Included are code generation tools compilers assemblers linkers etc and system integration and debug tools simulators emulators evaluation modules etc Also covered are available documentation seminars the university program and factory repair and exchange TMS320 Family Development Support Reference Guide literature number SPRUO 11E describes the TMS320 family of digital signal processors and the various products that support it This includes code generation tools compilers assemblers linkers etc and system integration and debug tools simulators emulators evaluation modules etc This book also lists related d
468. rocessor mode boot exam ple is that in addition to the contents of the COFF sections the boot table in cludes special control words for the on chip boot loader program to instruct it on how to assemble and load those sections Each section is built into a block preceded by three control words block size destination address and destina tion memory width data size Multiple blocks can be transferred to selected parts of the DSP memory map To format the COFF file into the boot table the program section to be booted must be identified to the hex conversion utility with the SECTIONS directive The boot table is constructed of the COFF sec tions identified in the SECTIONS directive and marked with the boot option see Figure 4 41 Ifthe linker usesthe cr option to create the COFF file the hex utility processes the COFF cinit section and assigns the addresses in the bss section to the corresponding cinit arrays in the boot table Every C program starts execution with the boot asm routine but because one of the boot asm control flags indi cates that the COFF file was created with the linker cr option the code skips transfer of cinit contents to bss The hex utility performs that task by placing all the initialized variables in bss while creating the boot table without relying on boot asm to make the transfer at run time see Figure 4 41 Buioejuaju AIowayy Lev Figure 4 40 32 Bit EPROM Boot in the Microprocessor Mode L
469. rsion si 3 20 3 7 4 IEEE to TMS320C3x Floating Point Format Conversion 3 22 3 7 2 TMS320C3 x to IEEE Floating Point Format Conversion 3 26 Memory Interfacing ee sre III III III III 4 1 Provides examples for C3x system configuration memory interfaces and reset 41 System Configuration 0 0 0 cect a a eee 4 2 4 2 External Interfaces 20 2 c ee nnn 4 3 43 Primary Bus Interface a a 00 ec eens 4 4 4 4 Zero Wait State Interface to Static RAMS se 4 5 4 5 Wait States and Ready Signal Generation pp 4 10 4 5 1 ORing the Ready Signals i 4 10 4 5 2 ANDing the Ready Signals or eee ees 4 11 4 5 8 External Ready Signal Generation i 4 11 4 5 4 Ready Control Logic 0 cece ccc teens 4 13 45 5 Example Circutt s decenca dace cent ld euenire e edie a aaa adn 4 14 4 5 6 Bank Switching Techniques i 4 15 4 6 Interfacing Memory to the TMS320C32 DSP i 4 21 4 6 1 Functional Description of the Enhanced Memory Interface 4 24 4 6 2 Logical Versus Physical Address i 4 33 4 6 3 32 Bit Memory Configuration Design Examples i 4 35 4 6 4 16 Bit and 8 Bit Memory Configuration Design Examples 4 41 4 6 5 One Bank Two Strobes 32 Bit Wide Memory Design Examples 4 49 4 6 6 ROY Signal Generation i 4 57 4 6 7 Address Decode for Multiple Banks i 4 64 4 7 How TMS320 Tools Interact With the TMS320C32 s Enhanced Memory Interface 4 67 4 7 1 C Compiler
470. rt tools 11 1 6 Bulletin Board Service BBS The TMS320 DSP Bulletin Board Service BBS is a telephone line computer service that provides information on TMS320 devices specification updates for current or new devices and development tools The BBS also gives infor mation about silicon and development tool revisions and enhancements new DSP application software as it becomes available and source code for pro grams from any TMS320 user s guide You can access the BBS by DD Modem 300 1200 or 2400 bps dial 713 274 2323 Set your modem to 8 data bits 1 stop bit no parity D Internet Use anonymous ftp to stp ticom Internet port address 192 94 94 1 The BBS content is located in the subdirectory called mir rors To find out more about the BBS see the TMS320 Family Development Support Reference Guide 11 2 TMS320C3x Part Ordering Information Table 11 1 Device TMS320C30GEL TMS320C30GEL40 TMS320C31PQL PQA TMS320C31PQL40 TMS320LC31PQL TMS320C31PQL50 SMJ320C316FA27 SMJ320C31HF627 SMJ320C316FA33 SMJ320C316HF633 SMJ320C306BM33 SMJ320C30HF633 SMJ320C30GBM28 SMJ320C30HF628 SMJ320C30HTM28 SMJ320C30GBM25 SMJ320C30HF625 SMJ320C30HTM25 TMS320C3x Part Ordering Information This section provides device and support tool part numbers Table 11 1 lists the part numbers for the C30 and C31 Table 11 2 gives ordering information for C3x hardware and software support tools An explanation of the TMS3
471. rvice BBS 11 6 code generation tools 11 2 assembler linker 11 2 C compiler 11 2 compiler 11 2 linker 11 2 documentation 11 5 hotline 11 5 literature 11 5 seminars 11 5 system integration and debug tools 11 3 debugger 11 3 emulation porting kit EPK 11 4 emulator 11 3 evaluation module EVM 11 3 simulator 11 3 XDS510 emulator 11 3 technical training organization TTO work shop 11 5 third parties 11 4 workshops 11 5 software stack 2 5 to 2 8 square root 3 13 stack 2 5 to 2 8 subroutines computed GOTO 2 22 context switching 2 11 to 2 16 context restore for C3X 2 15 to 2 17 context save for C3X 2 13 to 2 14 dot product 2 3 interrupt priority 2 10 to 2 18 program control 2 2 to 2 4 runtime select 2 20 subtract example extended precision arithmetic 3 17 Index 8 supply current calculations 12 24 to 12 26 average 12 25 data output 12 25 experimental results 12 26 processing 12 24 system configuration block diagram 4 2 categories of external interfaces 4 3 control functions 1 4 to 1 8 reset signal generation 1 8 to 1 4 stacks 2 5 target cable 10 2 10 8 target system connection to emulator 10 5 to 10 7 technical training organization TTO work shop 11 5 test bus controller 10 10 test setup description for C30 power supply current measurements 12 4 third parties 11 4 timer period register value maximum 8 22 minimum 8 22 timing waveforms RDY signal generation 4 63 TLC32040 i
472. ry space that easily supports the floating point C compiler The C compiler trans lates ANSI C programs into assembly language source code It also increases code portability and decreases application porting time After writing your application in C language debug the program and determine whether it runs efficiently If the program does not run efficiently Use the optimizer with o2 or 03 options when compiling Use registers to pass parameters ms compiling option Use inlining x compiling option Remove the g option when compiling Follow some of the efficient code generation tips listed below O O O O L Identify places where most of the execution time is spent and optimize these areas by writing assembly language routines that implement the functions Call the rou tines from the C program as C functions The efficiency of the code generated by the floating point compiler depends to a large extent on the compiler options used when writing your C code There are specific constructs that can vastly improve the compiler s effectiveness Lj Use register variables for often used variables This is particularly true for pointer variables Example 5 1 shows a code fragment that ex changes one object in memory with another Example 5 1 Exchanging Objects in Memory 5 2 register float src dest temp do temp tSrC SEC dest dest temp while n Precompute subexpression
473. ry interface checks the state of the PRGW pin to determine the memory width Because the program memory is 16 bits wide the PRGW pin should be pulled up to Vcc effectively directing the memory interface to fetch instructions in two bus cycles per instruction 16 bits at a time Table 4 4 Program Fetch From 16 Bit STRBO Memory Data Access Strobe Data Size Memory Width Input data STRBO 32 32 Output data STRB1 32 32 Program IOSTRB 32 16 Memory Interfacing 4 29 0 v Figure 4 13 Program Fetch From 16 Bit STRBO Memory Logical memory map U STRBO IOSTRB STRBO STRB1 16 bits VCC ow Q TMS320C32 2 LDI 4 RC 1001h PRGW pin RPTB L1 1002h y LDI AR0 RO 1003h 4 0 i S RO R1 32 bits 32 bits E 16 bits Float RO 1004h RO 2 a STRBO L1 STF R1 AR1 1005h am program B fetch BEES D ysical memory Logical address 32bits e e e v 101 820001h IOSTRB FL JARO 32 bits data read 102 ore 820003h i x ALU IR 32 bits 104 820004h 1003h PC FPU Control 105 820005h e A 910003h AR1 e l e 1 Physical memory Logical address S 32 bits Sc e Em STRB1 e gt data write R1 103 0 5
474. s the AIC A AIC INIT LDI 0x10 IE andn 0x34 IF ldi 0 RO sti RO SO_xdata A RPTS 0x040 9 LDI 2 IOF H rpts 0x40 E LDI 6 IOF ldi C_REG RO call prog AIC ldi Oxfffc RO call prog_AIC ldi Oxfffc 2 RO0 E call prog AIC ldi B_REG RO call prog_AIC ldi QA REG RO call prog AIC b main prog AIC ldi SO_xdata R1 sti R1 SO_xdata R idle ldi SO0_xdata R1 or 3 R1 3 sti R1 0S0 xdata idle H sti RO S0_xdata A idle andn 3 R1 E sti R1 SO_xdata A a ldi SO_rdata RO rets PRR RRR KER RK KKK RK KER koe sk KKK KR ke kk koe ke xk main Enable only XINT interrupt XFO 0 resets AIC XFO 1 runs AIC Setup control register Program the AIC to be real slow Bump up the Fs to final rate smallest divisor should be last Use original DXR data during 2 ndy Use original DXR data during 2 ndy Request 2 ndy XMIT Send register valu Leave with original safe value in DXR Fix the receiver underrun by reading the DRR before going to the main loop Fe HE eR Re RO OK e de es Install the XINT RINT ISR handler directly into the vector RAM location it will be used for 7 EEKE AE PR IEE ETE IE FIR ETE ibo dede EF de ek dede EPR de boe e qe deg dede ee vede start SPOV sect B B SPOVECTS DAC2 ADC2 i ECTS 0x809FC5 XINTO RINTO Analog Interface Peripherals and Applications 8 29
475. s CALLU ARO OTI R1 AR7 4 IOSTRB gt DMA src CALLU ARO SEL R1 AR7 6 STRBO gt DMA dst CALLU ARO SLL R1 AR7 8 STRB1 gt DMA cnt TMS320C32 Boot Loader Program B 9 Boot Loader Source Code Listing Process block size of bytes half words or words after STRB entr block CALLU ARO read boot memory cntrl word LDI R1 R1 is this the last block BNZ label2 PERRERA Wo GO around LDI AR7 4 RO DMA src STI RO AR7 60h restore IOSTRB LDI AR7 6 RO0 DMA dst STI RO AR7 64h restore STRBO LDI AR7 8 RO DMA cnt STI RO AR7 68h restore STRB1 BU IR1 px xx x X branch to start of program label2 LDI R1 RC setup transfer loop SUBI 1 RC RC 1 gt RC Process block destination address save start address of first block CALLU ARO read boot memory cntrl word LDI R1 AR5 set dest addr AR5 CMPI 0 IRO look at EXEC start addr flag LDINZ AR5 IR1 if l EXEC start addr gt IRI LDINZ 0 IRO set EXEC start addr flag For internal destination this word must be 0 or 60h The first case results in 0 gt DMA control register in second case 0 IOSTRB register Process block destination strobe control sss sss 0110 xx00 X strb value 00 IOSTRB X 01 STRBO CALLU ARO A 10 STRB1 LDI R1 R4 AND 6Ch R1 dest mem strb pntr AR4 OR
476. s This especially applies to array refer ences in loops Assign commonly used expressions to register variables where possible Use to step through arrays rather than using an index to recalculate the address each time through a loop Hints for Optimizing C Code As an example of the previous two points consider the loops in Example 5 2 Example 5 2 Optimizing a Loop loop 1 main float a 10 b 10 int i for x 0 xXx 10 afi afi 20 loop 2 main float a 10 b 10 int i register float p for i 0 i lt 10 pi p 20 i a i xatt bli kg b Loop 1 executes in 19 cycles Loop 2 which is the equivalent of loop 1 exe cutes in 12 cycles Use structure assignments to copy blocks of data The compiler gen erates very efficient code for structure assignments so nest objects within structures and use simple assignments to copy them Avoid large local frames and declare the most often used local vari ables first The compiler uses indirect addressing with an 8 bit offset to access local data To access objects on the local frame with offsets greater than 255 the compiler must first load the offset into an index register This requires one extra instruction and incurs two cycles of pipeline delay Programming Tips 5 3 Hints for Optimizing C Code Avoid the large model The large model is inefficient because
477. s periodic sampling is maintained by updating the value stored in the external latches at regular intervals Therefore between updates the digital value is stored and maintained at the latch out puts that provide the input to the DAC This results in a stable analog output until the next sample update is performed Digital to Analog Converter Interface to the TMS320C30 Expansion Bus Figure 8 3 Interface Between the TMS320C30 and the AD565A 12V Vcc REF OUT 12 V 500 VEE 20 V SPAN y REF IN REF GND 74LS377 Y 10 V AGND SPAN XDO 3 1D 1Q 2 Bit 12 LSB 10 pF XDi 4 5 t 12V XD2 7 6 10 DACOUT XD3 8 li s 9 9 LM318 Analog XD4 13 12 8 ou XD5 14 15 a heen XD6 17 16 6 12V XD7 18 19 5 24K CLK EN 4 3 2 Bit 1 MSB 74LS377 t1 MSB Power XD8 3 2 GND XD9 4 5 XD10 7 U26 6 AGND XD11 8 9 CLK EN e XA12 XD bus IOW The external data latches are 74LS377 devices that have both clock and enable inputs These latches serve as a convenient interface with the C30 the enable inputs provide a device select function and the clock inputs latch the data The enable input driven by inverted XA12 and the clock input driven by IOW which is the AND of IOSTRB and XR W Therefore data is stored in the latches when a write is performed to I O address 805000h Reading this address has no
478. s 3 14 64 Bit AddiliOli 425 a os er gue he a true e REP amus Ue eT ubex ed da aea gad vs 3 16 64 Bit Subtraction s sacri didaa aiii a iiai i nna 3 17 32 Bit by 32 Bit Multiplication js 3 18 IEEE to TMS320C3x Conversion Fast Version i 3 22 IEEE to TMS320C3x Conversion Complete Version pp 3 24 TMS320C3x to IEEE Conversion Fast Version i 3 26 TMS320C3x to IEEE Conversion Complete Version pp 3 28 8 Bit Dynamic Buffer Allocation ssssssssssssssee eee eee 4 76 Linker Command File e spya s epi dy eaaa maida de a atar aoha ed dei a n mh 4 77 Debugger Batch File tn a ERE eens 4 78 8 Bit Static Buffer Allocation 0 ccc cee nett eee 4 79 Linker Command File a sass ones Rer er RE teeter a eia a ari a bie RES ERE Rd 4 79 16 Bit Dynamic Buffer Allocation 0 00 cece e 4 84 Linker Command File ss ea io i a Rm 4 85 Debugger Batch File ss 4 85 Eod d to P Ld d bL dg d hid l i D M l OO Qo ON OD ON oOoaRWN CO w N hp 69 Logd d P to LO P gd dd NO of AL oot ot ttt CO co co co co CO co co co CHO co co co co co WA WW OA NNNDADWAAMVWAAVWAAVWAAVNWAVNAAANAAAHAAMDHAAaAMAHA MH IODOJI om Examples Exchanging Objects in Memory 000 3 a eieren si eee eee tees 5 2 Optimizing a LOO ose greta ee eee erin ee RUE ER eee ee dee eee sede behead 5 3 Allocating Large Array Objects 0 5 4 Setup of IDLE2 Power Down Mode Wakeup pp 5 8 u Law Compression esei ceri 0000 L
479. s capacitive again In an oscillator circuit the crystal is always operated at or slightly above the series resonant frequency in the inductive region The capacitance Cg has little effect on the series resonant point fs but in combina tion with the external load on the crystal the capacitance Cy affects the paral lel resonant point fp For simplification of the circuit analysis Co is sometimes considered part of the external load on the crystal When ordering a crystal you must tell the manufacturer whether a series resonant or parallel resonant crystal is required The nature of these terms is slightly different from the serial and parallel resonant frequency terms fs and fp previously described A series resonant crystal is intended to operate in a circuit with a low load impedance across its terminals and consequently resonates very close to the series resonant frequency fs A parallel resonant crystal is intended to operate in a circuit with a high impedance load across its terminals and operates at some frequency slightly above fs where the crystal s reactance is inductive In this case the Quartz Crystal and Ceramic Resonators crystal attempts to resonate at the frequency at which its own inductive reactance exactly cancels the capacitive reactance of the combination of Co and an external capacitive load If supplied with the desired frequency and the external load to which the crystal will be connected the manufacturer can
480. s known if itis necessary to limit the drive level to the crys tal one of the simplest ways to do so is shown in Figure 9 14 A resistor Rg is added in series between X and the external components This resistor drops part of the voltage driven by the C3x and consequently lowers the drive voltage on the crystal The disadvantage to this method is that the voltage drop reduces the overall loop gain of the oscillator circuit The value of Rd must be large enough to bring the power dissipation of the crystal within the manufac turer s specification but Rg must not be so large that the loop gain drops below 1 or the circuit no longer oscillates Using crystals with minimum power dis sipation ratings of 1 mW is recommended The oscillator circuit solutions in Table 9 2 when operated without Rg have yielded crystal power dissipation measurements near 1 mW Differences in circuit and crystal parameters can cause the power dissipation in the crystal to slightly exceed 1 mW If crystal power dissipation is critical adding a resistor Ra with a value of 33 Q to limit the crystal power dissipation or obtaining crys tals with power dissipation ratings higher than 1 mW is recommended When operated with Rg 33 Q each of the circuit solutions shown in Table 9 2 have exhibited less than 1 mW crystal power dissipation Figure 9 14 Addition of Ry to Limit Drive Level of the Crystal C5x ELI E E ee X2 CLKIN Xi Rd Co H
481. s malloc asm which is used to allocate additional memory at run time Memory Interfacing 4 87 Booting a TMS320C32 Target System in a C Environment 4 8 1 3 Linker 4 88 The linker assigns physical addresses to logical program sections from obj files A linker command file defines the available physical memory segments using the MEMORY directive assigns one or more sections to individual memory segments using the SECTIONS directive and lists all object files con taining sections to be processed The order in which object files are listed is important and reflects the order in which individual sections are stacked in physical memory For that reason the boot obj file must always be the first one listed since it represents the execution entry point for every C program The boot obj global symbol c_int00 provides the entry address that can be resolved to otherfiles that are linked with boot obj for example the vector file that needs an address for the reset vector Depending on the method the linker can be invoked with the c or cr option These two options control how a C program s initialized variables are handled during the later stages of the boot process See the TMS320C3x C4x Assembly Language Tools User s Guide for more information Buioejuaju AIowayy 68 7 Figure 4 37 Compile Assemble and Link Flow file1 c funci funcN ASCII format file2 c file0 asm Vectors CC
482. s or to embed emulation compatibility on your target system connect a C3x device directly to a TI ACT8990 test bus controller TBC as shown in Figure 10 9 The TBC is described in the Texas Instruments Advanced Logic and Bus Interface Logic Data Book A TBC can connect to only one C3x device Figure 10 9 TBC Emulation Connections for TMS320C3x Scan Paths Vcc b TBC 22 kQ 22 ko 22 kQ TMSO TMS1 TDO e TCKO TCKI TDIO TDH TMS2 EVNTO TMS3 EVNT1 TMS4 EVNT2 TMS5 EVNT3 Notes C3x EMUO EMU1 EMU2 EMUA C30 only H1 clock EMU3 EMU5 C30 only EMU6 C30 only 1 In a C3x design the TBC can connect to only one C3x device 2 The C3x device s H1 clock drives TCKI on the TBC This is different from the emulation header connections where H3 is used 10 10 Chapter 11 Development Support and Part Ordering Information This chapter provides development support information device part numbers and support tool ordering information for the C3x Each C3x support product is described in the TMS320 Family Development Support Reference Guide In addition more than 100 third party developers offer products that support the TI TMS320 family For more information refer to the TMS320 Third Party Reference Guide For information on pricing and availability contact the nearest TI field sales office or authorized distributor Topic Page
483. s the only method for a C program to access 8 or 16 bit wide memory This means that physical memory that is less than 32 bits wide cannot be accessed using small or big model addressing Instead the MALLOC8 and MALLOC16 RTS library functions can allocate blocks of 8 and 16 bit wide memory These routines work like the 32 bit MALLOC by returning pointers to 8 or 16 bit memory blocks These can be used by code that follows the MALLOC call to access that memory see Figure C 3 and Figure C 4 The 8 bit data allocated by MALLOC8 is placed in the SYSM8 section by the linker while the 16 bit data is deposited in the SYSM16 section HEAP8 and HEAP16 linker keywords limit the total amount of 8 or 16 bit memory thatthe C compiler can allocate into those sections For more information see the TMS320C3x C4x Optimizing C Compiler User s Guide Memory Access for C Programs C 3 Memory Access for C Programs Figure C 2 Dynamic Memory Allocation for TMS320C32 One Block of 32 Bit Memory a C code e int BUFFER_32 declare a pointer to a pool of 32 bit memory e e e e e e BUFFER_32 MALLOC 2048 sizeof int allocate 2K words of memory dsp func4 BUFFER 32 use the above memory e e BUFFER_32 MALLOC 512 sizeof int allocate 0 5K words of memory dsp_func5 BUFFER_32 use the above memory e e e BUFFER_32 MALLOC 1024 sizeof int allocate 1K words of memory dsp func6 BUFFER
484. s to split the 32 bit magnitude values of the multiplicand X and the multiplier Y into two parts X1 X0 and X3 X2 respectively with 16 bits each The operation is done on unsigned numbers and the product is adjusted for the sign bit Example 3 10 shows the implementation of a 32 bit by 32 bit multiplication Logical and Arithmetic Operations 3 17 Extended Precision Arithmetic Example 3 10 32 Bit by 32 Bit Multiplication 9b o3RO e ORoO3 e e OR OONX Ro oR o o3 x R3 3E Go a TITLE 32 BIT X 32 BIT MULTIPLICATION SUBROUTINE EXTMPY FUNCTION WO 32XBIT NUMBERS ARE MULTIPLIED PRODUCING A 64tBIT RESULT THE TWO NUMBERS X and Y ARE EACH SEPARATED INTO TWO PARTS X1 X0 AND Y1 YO WHERE XO X1 YO AND Y1 ARE 16 BITS THE TOP BIT IN X1 AND Y1 IS THE SIGN BIT THE PRODUCT IS IN TWO WORDS WO AND W1 THE MULTIPLICATION IS PERFORMED ON POSITIVE NUMBERS AND THE SIGN IS DETERMINED AT THE END X1 X0 BITS OF PRODUCTS X YL YO NOT COUNTING SIGN PRODUCT XO YO 16 16 Pl XO Y1 16 16 P2 X1 Y0 16416 P3 X1 Y1 16 416 P4 W1 WO ARGUMEN ASSIGNMENTS ARGUMEN FUNCTION T RO MULTIPLIER AND LOW WORD OF THE PRODUCT R1 MULTIPLICAND AND UPPER WORD OF THE PRODUCT REGISTERS USED AS INPUT RO R1
485. sample The effective Fourier series size is determined by the size of the time window of samples Although this does not affect the calculation rate it does consume internal memory Creating a pass band around a particular signal is easy since the signal can be viewed either in frequency or time by changing the setting of SPECT EN With practice you can you can zoom in on particular segments of frequency by changing the start and stop bins window size and sampling rate The DAC output signal fidelity is largely determined by the TA register value that is programmed into the AIC No one value seems to fit all applications However the following rules generally apply If TA is small the DAC recon struction filter is clocked at a faster rate This pushes the upper pass band limit higher in frequency resulting in faster slew times This is desireable for a spec trum analyzer output where fast impulse response to frequency peaks are needed for suitable viewing For audio applications a larger TA value is desired sincethe overclocking of the DAC reconstruction filter results in signif icant distortions The AIC master clock input is derived from the timer output pin of internal timer 0 If the timer reference is set higher than the TLC32040 maximum clock rate of 10 MHz additional distortion occurs A TLC32040 analog interface circuit is used on the DSK since it responds favorably when used beyond its tested limits However predicting
486. se Re EUER E Ee epe Rem RN DRR RUNE TA RES EUER NE AE 5 10 Output File defs asm 030 Rn 5 10 Data Memory Organization for an FIR Filter 0 ccc ccc eee ee eee eee 6 7 Data Memory Organization for a Single Biquad pp 6 10 Data Memory Organization for N Biquads i 6 12 Structure of the Inverse Lattice Filter 0 0 0 cece eee eee 6 18 Data Memory Organization for Forward and Inverse Lattice Filters 6 19 Structure of the Forward Lattice Filter i 6 21 Data Memory Organization for Matrix Vector Multiplication sss 6 24 Decimation in Time for an 8 Point FFT 4 6 29 Decimation in Frequency for 8 Point FFT 7 6 30 Input Signal Sample Buffer i 6 81 Frequency Bin Diagram Equivalent to an IIR Filter 0 0 22 cece eee eee 6 83 Raised Cosine Window oy 6 85 Raised Cosine Window Function Length 1 Bin 0 0 eee cece eee 6 86 Raised Cosine Window Function Length 2 Bins i 6 87 Raised Cosine Window Function Length 3 Bins i 6 87 Raised Cosine Window Function Length 4 Bins 0 2 2 0 cce eee eee ee 6 87 N 2 SFFT RA Bins ctr a 6 88 Interface Between the TMS320C30 and the AD1678 i 8 3 Read Operations Timing Between the TMS320C30 and the AD1678 8 4 Interface Between the TMS320C30 and the AD565A i 8 7 Timing Diagram for Write Operation to the DAC i 8 8 TMS320C31 Zero Glue Logic Interface to Burr Brown ADC and DAC 8 10 TM320C3x to TLC32040 I
487. se angle Scale factor is also applied since the summation occurs over N data points EAL IMAG sums are scaled A growth mpyf mpyf addf3 mpyf stf rets REAL_VEC R4 Rotate to desired output phase IMAG VEC R5 H R4 R5 RO Sum the R I into a REAL output Scale RO inverse of N 2 growth RO FILTEROUT as well as R The output section is written for both Spectrum analyzer output EAL IMAG filter sum outputs r Output df ldf else SPECT EN 0 If SPECT EN 0 disable output either FILTEROUT RO Output REAL IMAG bin sum The Spectrum analyzer output section is bypassed if the spectrum analyzer is not enabled r d ldf GOutBin RO Point to next output bin addf 1 0 RATE RO increment analyzer output pointer cmpf BIN LEN RO ldfge 0 RO stf RO OutBin H fix RO RO H bzd Out mpyi RIBINSIZE RO Fbins are 2 words R I per bin ldfz MAX RO If at base Fbin 0 Hz output a synch ldi Bbase ARO A subi 2 ARO0 point to output bin 1 to perform addi RO ARO 5 1 0 5 convolutional window r ldf ARO DI 0 RO Perform convolutional window filter ldf ARO DR 0 R2 on the R I pairs for this output addf ARO DI 4 RO addf ARO DR 4 R2 mpyf 0 5 R0 Scaling coefficient for 1 1 bins mpyf 20 5 R2 addf ARO DI 2 RO H ARO D
488. se the information on this curve to obtain more precise values of current if zero wait states are used and the number of cycles between writes does not fall on one of the curves in Figure 12 4 TMS320C30 Power Dissipation 12 11 Current Requirement for Output Driver Circuitry Figure 12 5 Primary Bus Current Versus Transfer Rate at Zero Wait States 12 12 200 T E S TE 150 e c 2 s E 100 o 8 9 50 5 8 E gt Il g Es a 50 H1 cycles between writes Although these graphs contain negative current values negative current has not necessarily actually occurred The negative values exist because the graphs representa current offsetfrom the previously computed current value Using this approach to depict current contributions from different factors breaks down the current calculations to allow you to make calculations inde pendently Figure 12 4 and Figure 12 5 show that the current consumption during exter nal bus writes is negative if writes are performed at intervals of more than 18 cycles Under these conditions use the incremental value of 30 mA current contribution from the primary bus You should use a value of 30 mA only if the expansion bus is used extensively because the total contribution for external buses including baseline current must always be positive If the expansion bus is not used and the primary bus is not used much the current contribution from the prim
489. section 4 6 1 4 illustrate how the data is manipulated whenthe interface has to match variable size data with 8 16 and 32 bit wide physical memories In these sections five lines of code are included in the pro gram space in each figure LDI 4 RC RPTB Ll LDI AROt RO FLOAT RO R1 L1 STF Rl AR1 These lines of code read five integers from one data space convert them to floating point format and write them to another memory space that is assigned to a different strobe Each example has a different combination of data sizes and external memory widths to illustrate the range of possible combinations For data access and program fetch cycles in which the data size exceeds the physical memory width the least significant bytes half words are always transferred first 4 24 Interfacing Memory to the TMS320C32 DSP 4 6 1 1 STRBO and STRB1 Data Access Data Size Memory Width In the case of STRBO and STRB1 data access where data size equals memory width the data size and memory width for STRBO and STRB1 data access cycles are configured in the corresponding strobe control registers see Table 4 2 The short program stored in the internal RAMO memory begins with the load integer LDI instruction reading an 8 bit integer from 8 bit wide STRBO memory see Figure 4 11 As the integer data passes through the memory interface it is sign extended to 32 bits and loaded to RO as a 32 bit integer Next the integer
490. seyppy pue eoejigju A10ul8JAI 4 a Figure D 4 Address Translation for 16 Bit Data Stored in 32 Bit Wide Memory CD CN T eo amp fo CPU instruction STI RO OFFFFh 2 2 2 2 sees STRB Memory Data E E STRBO config width size o W o W 1 control wen gil RI a STRBO STRBO 32 bits 16 bits Rw STRB enable 1 wa Logical address 23 to 0 hw5 m hw4 hw7 w DEODBDDEED RRR w NSN SDS yD B 1 4f4 4 4 4f a a a 4 4 4 af a eee o ojo ojojo of ofo O oH ness hw65534 Physical address 14 to 0 hw65532 hw65531 STREBO hw65535 Memory address 14 to 0 hw65534 hw65533 STRBO STRB1 hw65536 LEER GE hw65535 Memory address space 32 bit data bus Data 2 o E o al CD Logical address g Data A14 A14 Data A14 Data A14 Data A14 shift 1 pit T A13 A13 A13 A13 A13 16 bit data size e e e gt e gt e gt e 2 e e G e o e o e N e e e e e GD o o o B o A2 A2 z A2 A2 A2 ag A1 Al A1 A1 A1 g AO A0 CS A0 CS A0 CS A0 g STRBO B3 H g STRBO B2 H g STRBO B1 H g STRBO B0 H 00000 Note The amount of shift between logical and physical addresses depends only on the size of data being transferred Oh th 2h 3h 7FFCh 7FFDh 7FFEh 7FFFh uoge sueJ sseJppy pue eoejieju AIOWAyy Figure D
491. sfer Rate and Wait States q Number of cycles between writes TT E Q a amp og 9 4 8 o 98 E o o zy o a E C 7 2 1 2 amp els 89 Wait states TMS320C30 Power Dissipation 12 13 Current Requirement for Output Driver Circuitry Figure 12 7 Expansion Bus Current Versus Transfer Rate at Zero Wait States 200 150 mA 100 IDD expansion bus operations factor 50 Incremental 50 lexp 100 150 H1 cycles between writes 12 3 3 Data Dependency Factors 12 14 Data dependency of current for the primary and expansion buses is expressed as a scale factor that is a percentage of the maximum current of either of the two buses Data dependencies are shown in Figure 12 8 for the primary bus and in Figure 12 9 for the expansion bus These two figures show normalized weighting factors that you can use to scale current requirements on the basis of patterns in data being written on the exter nal buses The range of possible weighting factors forms a trapezoidal pattern bounded by extremes of data values As can be seen from Figure 12 8 and Figure 12 9 the minimum current is exhibited by writing all Os while the maxi mum current occurs when writing alternating 55555555h and AAAAAAAAh This condition results in a weighting factor of 1 which corresponds to using the values from Figure 12 4 and or Figure 1
492. shift is optional As this syntax shows if you use the optional second parameter you must precede it with a comma Square brackets are also used as part of the pathname specification for VMS pathnames In this case the brackets are actually part of the path name they are not optional In assembler syntax statements column 1 is reserved for the first char acter of a label or symbol If the label or symbol is optional it is usually not shown If it is a required parameter it is shown starting against the left margin of the shaded box as in the example below No instruction com mand directive or parameter other than a symbol or label can begin in column 1 symbol usect section name size in bytes alignment The symbolis required for the usect directive and must begin in column 1 The section name must be enclosed in quotes and the parameter size in bytes must be separated from the section name by a comma The align ment is optional and if used must be separated by a comma Braces and indicate alist The symbol read as or separates items within the list The following is an example of a list RE fee po This provides three choices or Unless the list is enclosed in square brackets you must choose one item from the list Some directives can have a varying number of parameters For example the byte directive can have up to 100 parameters The syntax for this directive is b
493. sign easily satisfies the C30 33 s requirement of 15 ns of data setup time for reads Figure 8 2 Head Operations Timing Between the TMS320C30 and the AD1678 a a A Ce CC YX XA12 XA0 LLL t2 IOSTRB t3 IOR o y 8 4 READO DATA AERE LRI Analog to Digital Converter Interface to the TMS320C30 Expansion Bus Unlike the primary bus read and write cycles on the I O expansion bus are timed the same but have the following exceptions XR W is high for reads and low for writes The data bus is driven by the C30 during writes reads are the same When writing to the AD1678 the 74LS244 buffers do not turn on and no data is transferred The purpose of writing to the converter is only to generate a pulse on the converter s SC input which initiates a conversion cycle When a conversion cycle is completed the AD1678 s end of conversion EOC output generates an interrupt on the C30 to indicate that the converted data can be read The TLC1225 is a self calibrating 12 bit plus sign bipolar or unipolar conver ter which features 10 hs conversion times The TLC1550 is a 10 bit 6 us con verter with a high speed DSP interface Both converters are parallel interface devices Analog Interface Peripherals and Applications 8 5 Digital to Analog Converter Interface to the TMS320C30 Expansion Bus 8 2 Digital to Analog Converter Interface to the TMS320C30 Expansion Bus 8 6 In many DSP systems
494. sily be designed to function as an ASIC or can be incorporated into a custom digital signal processor cDSP Modification to this circuit can be done for different serial communication protocols or even higher baud rates Chapter 9 Clock Oscillator and Ceramic Resonators This chapter provides a general background on oscillators as well as informa tion regarding crystal and ceramic resonators their frequency characteristics and the type of oscillator circuit used on the C3x Also covered are design as pects of the C3x oscillator including appropriate configuration of the external components measured parameters for the on board portion of the circuitry use of the oscillator with overtone crystals and general design considerations for choosing the external components for the oscillator Finally this chapter shows some design solutions for common frequencies Topic Page 93 s Oscillators Se Ier e E e E 9 2 9 2 Quartz Crystal and Ceramic Resonators 9 3 9 3 Pierce Oscillator Circuit 5 e TETTE ESTIS ELS 9 9 9 4 Design Considerations IEEE 9 17 9 5 Oscillator Solutions for Common Frequencies 9 22 9 1 Oscillators 9 1 Oscillators The C3x is a member of the Texas Instruments family of high speed DSPs The C3x is capable of performing operations at a rate of up to 30 million instructions per second MIPS The wide variety of DSP applications requires a wid
495. sing the TMS320C31 and TMS320C32 Boot Loaders chapter of the TMS320C3x User s Guide so that the boot loader works properly Provide the correct reset vector value the reset vector normally contains the address of the system initialization routine B In microcomputer mode the reset vector is initialized automatically by the processor to point to the beginning of the on chip boot loader code No user action is required m In microprocessor mode the reset vector is typically stored in an EPROM Example 1 1 on page 1 5 shows how you can initialize that vector J Apply a low level to the RESET input see section 1 2 Reset Signal Generation 1 2 Reset Signal Generation The reset input controls the initialization of internal C3x logic and also causes the execution of the system initialization software For proper system initializa tion the reset signal must be applied for at least ten H1 cycles that is 600 ns for a C3x operating at 33 33 MHz Upon power up however it can take 20 ms or more before the system oscillator reaches a stable operating state There fore the power up reset circuit should generate a low pulse on the reset line for 100 to 200 ms Once a proper reset pulse has been applied the processor fetches the reset vector from location 0 which contains the address of the system initialization routine Figure 1 1 shows a circuit that generates an appropriate power up reset circuit Figure 1 1 Reset Circuit
496. sion of the IEEE to C3x conversion routine was originally devel oped by Apollo Computer Inc Other routines are based on this algorithm In fixed point arithmetic the binary point that separates the integer from the fractional part of the number is fixed at a certain location For example if a 32 bit number has the binary point after the most significant bit MSB which is also the sign bit only fractional numbers numbers with absolute values less than 1 can be represented A number having 31 fractional bits is called a Q31 number All operations assume that the binary point is fixed at this location The fixed point system although simple to implement in hardware imposes limitations in the dynamic range of the represented number This causes scal ing problems in many applications You can avoid this difficulty by using float ing point numbers In a floating point system each integer or fraction is represented by three fixed point numbers that constitute a floating point number Therefore a float ing point number consists of a mantissa m multiplied by base b raised to an exponent e m x be To provide the greatest resolution the mantissa is typically a normalized num ber with an absolute value between 1 and 2 Although the mantissa is repre sented as a fixed point number the position of the actual value is determined by the exponent e To achieve greater efficiency in hardware implementation the C3x uses a floating point
497. st positive number LDFN AR1 5 RO If negative infinity RETS most negative number RETS HANDLE Os AND UNNORMALIZED NUMBERS UNNORM TSTB AR1 6 RO Is the MSB of f equal to 1 LDFZ AR1 3 RO If not force the number to 0 RETSZ and return XOR AR1 6 RO H If MSB of f 1 make it 0 BND NEG1 LSH 1 R0 E Eliminate sign bit amp line up mantissa SUBI AR1 2 RO Make e 4127 PUSH RO POPF RO 4 Put number in floating point format RETS NEG1 POPF RO NEGF RO RO If negative negate RO RETS HANDLE THE REGULAR CASES NORMAL AND3 RO AR1 R1 gt Replace fraction with 0 BND NEG Test sign ADDI RO R1 Shift sign and exponent inserting 0 SUBI AR1 2 R1 p Unbias exponent PUSH R1 POPF RO Load this as a flt pt number RETS NEG POPF RO 7 Load this as a flt pt number NEGF RO RO gt Negate if original sign negative RETS Logical and Arithmetic Operations 3 25 IEEE TMS320C3x Floating Point Format Conversion 3 7 2 TMS320C3x to IEEE Floating Point Format Conversion The majority of the numbers represented by the C3x floating point format are covered by the general IEEE format and the representation of Os The only special case is e 127 in the C3x format this corresponds to a denormal ized number in IEEE format It is ignored in the fast version buttreated properly in the complete version Example 3 13 shows the fast version and Example 3 14 shows the complete version of the C3x to IEEE conversio
498. t and 8 Bit Memory Adaress Translation Data Size Memory Width STRB Memory Data Physical address Mii icd width size Logical memory bd STRBO 16bits 32 bits JH map STRBO control register eee 0 0 1 11 ecc 5 STRB1 control register eleje 00 0 1 eee m a Lt ll 8bits 16 bits a g E E e no P 1 Oh Oh 1 Iw A 2 1h 1 hw ae A13 Ao 2 Iw 3 Logical address 2 hw STRBO e p P9900 0000 ookin e N 0000 0000 0 r ET Physical address A A 16382 5 f 16383 Iw 16383 hw 16383 gt 7FFEh MADSSERUUM 16384 3FFFh 7FFFh 16384 hw 32 bit data size address not shifted IOSTRB 16 bit data size address shifted by 1 bit 1 900000h Oh 1 Ib 2 th 1 hb j 3 A13 Ao 2 Ib Logical address 2 hb e gt 001 0000 0 o Ie EE e 1001 0000 0 Physical address eh a A A STRBO 12 2 16383 16382 16383 16383 STRB1 7FFEh 16384 Ec 16384 903FFFh Le7FFFh 16384 e c Note Iw low word hw high word Ib low byte hb high byte dSd ZED0ZESWL eui 0 Aiowayy Bureau Interfacing Memory to the TMS320C32 DSP 4 6 4 3 16 Bit and 8 Bit Memory Address Translation for Data Size Memory Wi
499. t memory section heap 16 0x4000 set the size of the dynamic 16 bit memory section heap 8 0x4000 set the size of the dynamic 8 bit memory section e e IOSTRB_RAM org 0x810000 len 0x8000 define physical 32 bit memory SA STRBO RAM org 0x880000 len 0x8000 define physical l6 bit memory STRB1 RAM org 0x900000 len 0x8000 define physical 8 bit memory e e ey SES d IOSTRB RAM assign logical section to physical memory sysm16 di STRBO RAM assign logical section to physical memory Sysm8 me gt STRBl RAM assign logical section to physical memory c C32 external memory contents TMS320C32 32 bit wide memory STRBO sysm16 16 bit wide memory sysmem IOSTRB STRB1 Sysm8 8 bit wide memory Appendix D Memory Interface and Address Translation This appendix describes how to use the C32 s memory interfaces to connect to various external devices The C32 memory interface supports variable width memory and variable size data The physical width of a memory bank connected to the C32 can be 8 16 or 32 bits wide When connecting 16 bit external memory the A 4 address pin must be connected to the Ag pin of the memory device causing a 1 bit shift in the connection of the remaining address lines For 8 bit memory two extra address pins are used A 4 and A 5 effectively shifting the external address by two bits No external
500. t3 ADDI 4 AR2 808064h STRBO AR2 TSTB 1 R0 test for INTO LDINZ 8 AR3 001000h 2 9 BNZ exit3 PRAERERA KS ADDI 4 AR2 808068h STRB1 AR2 TSTB 4 R0 test for INT2 LDINZ 4800h AR3 900000h 2 9 BZ waitl Boot Loader Source Code Listing exit3 TSTB 8 RO0 test l INT3 asserted BZ exit2 test 2 INXF1 low not used TSTB 80h IOF enable handshake mode if LDI 6 IOF P test l passed exit2 LDI OFh R2 LSH 16 R2 force boot data size to 32 OR AR2 R2 force boot mem width to 32 STL R2 AR2 LSH 9 AR3 boot mem start addr AR3 xx000001 1 bit xx000010 2 bit Process MEMORY WIDTH control word 32 bits long xx000100 4 bit xx001000 8 bit xx010000 16 bit xx100000 32 bit LDI read mc ARO use memory to read cntrl words F read mc gt ARO LDI 1 R5 mem width 1 init LDI 32 AR6 mem reads 32 init CALLU read_m read memory once lst read loop2 TSTB 1 R6 BNZ label4 LSH 1 R6 look at next bit LSH 1 AR6 decr mem reads LSH 1 R5 incr mem width gt R5 BU loop2 label4 SUBI 2 AR6 CMPI 0 AR6 Set flags BN strobes total of mem reads 32 R5 label5 CALLU read m read memory once DBU AR6 label5 Read and save IOSTRB STRBO amp STRB1 to be loaded at end of boot load strobe
501. ta being transferred the physical address also matches the logical ad dress with one exception the physical address is shifted relative to the logical address by one bit for 16 bit transfers and by two bits for 8 bit transfers This means that the address bit that would normally be expected on pin AO actually appears on pin A 4 or A As Figure 4 21 shows there is one to one corre spondence between logical data and its counterpart in physical memory Memory Interfacing 4 43 Figure 4 21 16 Bit and 8 Bit Memory Adaress Translation Data Size Memory Width STRB Memory Data i configuration width size Physical Logical Logical c memory pre ae STRBO 16 bits 16 bits map STRBO control register eee 0 01 01 eco Li STRB1 control register eoe 00 00 eco m ig 8bits 8 bits m Je 9 g amp ra o b om oh 1 gH 2 2 mc 3 A14 Ao 3 STRBO Logical address N e p 50000 000 0 ofi ta 1111 1111 1111 e N 0000 0000 0 Physical address e N A13 A4 32766 32766 ES 32767 Y 32767 16 bit data size address shifted by 1 bit IOSTRB 8 bit data size address shifted by 2 bits 900000h Oh 1 2 2 j 3 A14 Ag 3 Logical address P 91001 0000 OLEEBEEEEZEEEGEEEEEE 1001 00
502. tal frequency of the crystal and the odd overtones are odd multiples of the fundamental frequency for ex ample 3x 5x 7x For low frequencies it is common to operate crystals at their fundamental frequency For higher frequencies the crystal is made thin ner The thinner the crystal is the more fragile and expensive it becomes Thin ner crystals also have a low power dissipation limit and damage easily when overdriven Most fundamental mode crystals operate at frequencies of 40 MHz or less To generate frequencies higher than 40 MHz it is common to use overtone crys tals Overtone crystals are optimized for operation at an overtone frequency with the fundamental frequency attenuated Figure 9 12 illustrates the imped ance of a crystal with respect to frequency The strongest change in imped ance is at the fundamental frequency but there is also a response at the third and fifth overtones If a crystal with the properties in Figure 9 12 is used in a Pierce circuit it oscillates at the fundamental frequency However if the funda mental frequency is attenuated the crystal circuit oscillates at the next higher odd overtone in this case the third overtone High frequency operation is achieved by using an overtone crystal and attenuating the fundamental fre quency Pierce Oscillator Circuit Figure 9 12 Impedance Characteristics of a Crystal A Impedance p Frequency Fundamental Third Fifth overtone overtone
503. ter A lt TA Rx counter A lt RA Tx counter B lt TB Rx counter B RB The second and third modes use the TA and RA registers to advance or slow down the sampling frequency by respectively shortening or lengthening the sample period This is particularly useful in modem applications where it can enhance the signal to noise performance perform frequency tracking func tions and generate nonstandard modem frequencies 8 4 4 2 Secondary Communications Secondary communication follows a primary communication that has the two LSBs set to 11 together This secondary communication programs the AIC by loading the A A B or control registers Figure 8 8 shows the secondary com munication data format The TA RA TB and RB values are unsigned The TA and RA values are in signed 2s complement format The control register enables bandpass filters and asynchronous transmit receive enables and disables auxiliary inputs and changes input gain Analog Interface Peripherals and Applications 8 25 TLC32040 Interface to the TMS320C3x Table 8 3 describes the control register bit fields Figure 8 8 Secondary Communication Data D15 D14 D13 D12 D11 D10 D9 D8 TB register value unsigned C ISTSTEETSES Table 8 3 Control Register Bit Fields TA register value signed 2s X complement D7 D6 D5 Input gain Transmit receive 0 0 1X for 6 V analog input 0 asynchronous 0 122Xfor 3 V analog input 1 enables 1 0
504. the DSK endif i The SFFT twiddles data and input buffer arrays are allocated to be placed into RAMO to avoid bus conflicts with program fetching include C3XMMRS ASM s start DATA 0x809800 Data arrays are placed at start of RAMO Sect DATA TWIDCOEF n Set BIN_START H loop SFFTBINS R I phase or twiddle coefficients float Kl cos n w s float Kl sin Nn w n Sdef n 1 0 next n endloop SFFTDATA loop SFFTBINS R I frequency bin data float 0 0 Pre Zeroing bin data removes endloop startup glitches BUF Loop N 2 N samples of ADC input delay data float 0 0 endloop i i The application code begins here beginning with constants that are used in various routines Tbase word TWIDCOEF Location of twiddle coefficients Bbase word SFFTDATA Location of R I SFFT Bin data CircAddr word BUF Current pointer into sample data BUFSTART word BUF Start address of sample data BUFEND word BUF N End address of sample data OutBin float 0 Current spectrum analyzer bin MAX float 32000 0 Used synch pulse and scaling A REG word TA lt lt 9 RA lt lt 2 0 Packed AIC register values B REG word TB lt lt 9 RB lt lt 2 2 C REG word 00000011b 0gctrl word 0x0E970300 Sport setup noninverted clkx clkr S0gctrl word 0x0E973300 Sport setup inverted clkx clkr SOxctrl word 0x00000111 H DSP Algorithms 6 95 Sliding FFT Example 6
505. the compil er reloads the data page pointer DP before each access to a global or static variable If you have large array objects use malloc to dynamically allocate them and access them via pointers rather than declaring them globally Example 5 3 illustrates two methods for allocating large array objects Example 5 3 Allocating Large Array Objects Inefficient Method int a 1000000 1 Inefficient atii 10 Efficient Method int a init malloc 1000000 Efficient ali 10 Hints for Assembly Coding 5 2 Hints for Assembly Coding Each program has unique requirements Not all possible optimizations are appropriate in every case You can use the suggestions in this section as a checklist of available software tools m Use delayed branches Delayed branches execute in a single cycle reg ular branches execute in four cycles The next three instructions are exe cuted whether the branch is taken or not If fewer than three instructions are required use the delayed branch and append No operation instruc tions NOPs A reduction in machine cycles still occurs Apply the repeat single block construct In this way loops are achieved with no overhead Nesting such constructs does not normally increase efficiency so try to use the feature on the most often performed loop Note that the RPTS instruction is not interruptible and the executed instruction is not refetched for e
506. the next two steps may still be required even though the 55 mA is omitted 3 If significant internal bus operations are performed add the calculated cur rent value See section 12 2 3 on page 12 5 4 If external writes are performed at high speed add 60 mA and then add the values for primary and expansion bus current factors See sec tion 12 3 on page 12 9 If only one external bus is used the appropriate incremental current for the unused bus must still be included because the current offsets include factors required for operating both buses The total current contribution for external buses including baseline is always posi tive The current value obtained from summing these factors is the total device current requirement for a given program activity TMS320C30 Power Dissipation 12 17 Calculation of Total Supply Current 12 4 2 Supply Voltage Operating Frequency and Temperature Dependencies Figure 12 11 12 18 Current dependencies specific to each supply current factor such as internal or external bus operations are discussed in section 12 1 2 on page 12 2 Supply voltage level operating temperature and operating frequency affect the requirements for the total supply current and must be maintained within the required device specifications Once you determine the total current for a particular program segment the dependencies that affect the total current requirements are applied as a scale factor in the sam
507. ther a ramp signal Define constants used by program RAMPEN TO ctrl TO count TO prd S0 gctrl S0 xctrl S0 roctrl SO xdata SO rdata TA TB RA RB Set Bet Set Set BEL Set Bet Set Set Bet Set Set Set 8e0t 1 0x808020 0x808024 0x808028 0x808040 0x808042 0x808043 0x808048 0x80804C 12 Ls 12 T5 0x2000 Set to 1 to generate ramp at AOUT TIMO TIMO TIMO SP 7 SP z SP POE SP This bit in ST turns on interrupts Define some constant storage data d A REG B REG C REG RAMP ADC last S0 gctrl val SO xctrl val S rctrl val word word word word word word word word TA 9 RA lt lt 2 0 TB lt lt 9 RB lt lt 2 2 10000011b 0x0E970300 0x00000111 0x00000111 0 0 0 0 0 0 0 gl control count prd global control FSX DX CLKX port ctl FSR DR CLKR port ctl Data transmit Data receive AIC timing register values A registers B registers control Serial port control register values RAMP count value Last received ADC value Analog Interface Peripherals and Applications 8 27 TLC32040 Interface to the TMS320C3x Example 8 6 Setting the TA and TB Registers Continued pORKCKCKCKCk kk kk ke kk RR KK KKK ke kk koc RK koc kk KKK kc kk koc ke kc ko ke kc ke kc ke ke ke ke e ke ek Begin main code loop here
508. tings f unsigned int ma 45 Monitor path selection Time slot 7 unsigned int lg 4 Left input gain settings XJ unsigned int is ziy Input selection unsigned int ovr si Overange unsigned int pio i2 Parallel I O bits Time slot 6 unsigned int ro 365 Right output attenuation setting E unsigned int se sd Speaker output enable control unsigned int d r1 els Unused don t care bit 7 Time slot 5 unsigned int lo 365 Left output attenuation setting unsigned int le es Parallel output enable control unsigned int he 1 Headphone output enable control xJ _bitval STEREO_16 typedef union unsigned int _intval 2 Struct Time slots 3 amp 4 signed int d_rl 16 Unused don t care bits 0 15 Time slots 1 amp 2 signed int left 16 Left channel 16 bit at Time slot 8 unsigned int d_r3 24 Unused don t care bits 0 3 unsigned int ma eas Monitor path selection Analog Interface Peripherals and Applications 8 51 CS4215 Interface to the TMS320C3x Example 8 15 CS4215 h Continued Time slo unsigned in unsigned in unsigned in unsigned in Time slo unsigned in unsigned in unsigned in Time slo unsigned in unsigned in unsigned in _bitval MONO_16 typedef union unsigned int struct Time slo signed in Time slo signed in Time slo signed in
509. to 1 after accounting for a 2 bit address shift due to the 8 bit width of the data Additionally the logical STRBO and STRB 1 address ranges that drive the physical address pin A17 to 0 and 1 re spectively must still conform to the logical memory map that assigns fixed blocks of addresses to different strobe spaces An STI RO ARO instruction with ARO 883FFFh results in a STRBO data ac cess data size 32 bits driving the STRBO BO STRBO B1 STRBO B2 and STRBO B3 control pins to write the contents of the 32 bit register RO into a 32 bit data location in the lower half of the external memory addressed by 3FFFh Similarly an LDI AR1 R1 instruction with AR1 98FFFFh results in a STRB1 data access data size 8 bits driving the STRBO B3 control pin because STRB CONFIG 1 to read the contents of an 8 bit data location in the upper half of the external memory addressed by 7FFFh to the 32 bit R1 register The C32 automatically performs all address translation the program mer merely monitors the logical memory map and the two strobe control regis ters Memory Interfacing 4 53 Figure 4 26 One Bank Two Strobes Address Translation Data Size 32 and 8 Bits dS ZED0ZESWL eui 0 Aiowayy Bu
510. to floating point conversion FLOAT instruction converts the integer in RO to a 40 bit floating point number and loads it into R1 Finally the store floating point value STF instruction truncates the 40 bit contents of R1 to 32 bits and stores it in the 16 bit wide STRB1 memory As the data passes through the memory interface the 24 bit mantissa is truncated to eight bits the 8 bit exponent remains unmodified Table 4 2 STRBO and STRB1 Data Access Data Size Memory Width Data Access Strobe Data Size Memory Width Input data STRBO 8 8 Output data STRB1 16 16 Program RAMO 32 32 Memory Interfacing 4 25 9c v Figure 4 11 STRBO and STRB1 Data Access Data Size Memory Width 8 bits TMS320C32 e STRB Memory Data x STRBO config width size s control m 0 m 0 ol olo 101 1001h Logical register 102 1002h EM STRBO 8bits 8 bits do map 104 1004h 105 1005h T1 E S2bis S ze STRBO Bu data read e en P f Physical memory Logical address STRBO RAMO program E Control fetch LDI 4 RC 87FE81h N 1003n ARO 32 bits RPTB L1 87FE82h ALU IR LDI ARO RO 87FE83h
511. to prevent noise from generating spurious wait states If more than two wait states are required by devices within a system other ap proaches can be used for ready signal generation If between three and seven wait states are required additional flip flops can be included in the same man ner shown in Figure 4 6 or internally generated wait states can be used in conjunction with external hardware If more than seven wait states are re quired an external circuit using a counter can be used to supplementthe capa bilities of the internal wait state generators 4 5 6 Bank Switching Techniques The C3x s programmable bank switching feature can greatly ease conflicts on system design circuits when large amounts of memory are required Nor mally devices take longer to release the bus than they take to drive the bus bank switching provides a period of time for disabling all device selects that are not present otherwise During this interval slow devices are allowed time to turn off before other devices have the opportunity to drive the data bus thus avoiding bus contention See the TMS320C3x User s Guide for further infor mation on bank switching When a portion ofthe high order address lines changes as defined by the con tents of the BNKCMPR register and bank switching is enabled STRB goes high for one full H1 cycle If STRB is included in chip select decodes this causes all devices to be disabled during this period The next bank o
512. tput signal line This condition exhibits the highest current values on the device The curve in the figure represents incremental or additional cur rent contributed by the primary bus output driver circuitry while writing alternat ing 55555555h and AAAAAAAAR Current values obtained from this graph are scaled and added to several other current values to calculate the total current forthe device As indicated in the figure the lower curve represents the current contribution for 18 or more cycles between writes Current Requirement for Output Driver Circuitry Figure 12 4 Primary Bus Current Versus Transfer Rate and Wait States 200 q Number of cycles between writes mA IDD primary bus operations factor Incremental lprim Wait states The number of cycles between writes refers to the number of H1 cycles be tween the active portion of the write cycles as defined in the TMSS320C30 Digi tal Signal Processor data sheet that is when STRB MSTRB or IOSTRB and R W or XR W as the case may be are low between H1 cycles As shown in Figure 12 4 the minimum number of cycles between writes is 1 because with back to back writes there is one H1 cycle between active portions ofthe writes To further illustrate the relationship between current and write cycle time Figure 12 5 shows the characteristics of current for various numbers of cycles between writes for zero wait states You can u
513. truction after IDLE2 define N 16 There is one cycle of delay while waking up the processor from the IDLE2 power down mode before the clocks start up This adds one extra cycle from the time the interrupt pin goes low until the interrupt is taken The interrupt pin needs to be low for at least two cycles The clocks may start up in the phase opposite the phase that they were in before the clocks were stopped Bit Reversed Adaressing in C 5 4 Bit Reversed Addressing in C The C language does not have any construct to take advantage of the bit reversed addressing feature of the C3x To take advantage of this feature Figure 5 1 shows the assembly instructions added to the C code to use bit reversed addressing Figure 5 1 Bit Reversed Addressing in C Code define N 16 int x N 0 8 4 12 2 10 6 14 1 9 5 13 3 11 7 15 int YIN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 int bitrev int m intn void main Ene i asm PUSH AR5 asm PUSH ARO asm LDI 8 IRO Initialize IRO TO 1 2 N asm LDI CONST 0 AR5 ARS lt address of X asm LDI CONST 1 ARO ARO lt address of Y for i O i n i y bitrev i N x i asm 7 LDI AR5 IRO b RO asm STI RO ARO asm POP ARO asm POP AR5 These statements place x and y in bss and make their addresses available via the CONST table
514. truncated to 24 bits the 8 bit expo nent remains unmodified The memory interface then stores the 24 bit man tissa and the 8 bit exponent in 16 bit wide memory two bytes at a time using two cycles and two physical memory addresses Table 4 3 STRBO and STRB1 Data Access Data Size Memory Width Data Access Strobe Data Size Memory Width Input data STRBO 8 16 Output data STRB1 32 16 Program RAM1 32 32 Memory Interfacing 4 27 8c Logical memory map U IOSTRB RAM1 STRB0 STRB1 y STRBO fe TMSS320C32 STRBO control EXEN 0 HH 01 1 010 register 1004h 87FF83h 910004h RO ARO PC AR1 R1 STRB1 control register STRB Memory Data config width size STRBO 16 bits 8 bits 32 bits 104 B Figure 4 12 STRBO and STRB1 Data Access Data Size Memory Width 16 bits e e e 102 101 1001h MEM 103 1003h 105 1005h e e e o oO 32 bits 5 48 bits m STRBO 5 data read ED oO Logical address v prse DL 4RC 87FF81h program RPTB L1 87FF82h dud Control fetch LDI ARO RO 87FF83h FPU 32 bits FLOAT RO
515. ts is flipped over by exchanging the elements that are equidistant from the end of the array In other words the original array is a 1 a 2 a 31 a 32 a 64 The final array after the rearrangement is as follows a 64 a 63 a 32 a 31 a 1 Because the exchange operation is performed on two elements simultaneously it requires 32 operations The repeat counter register is initialized to 31 In gener al if RC contains the number N the loop is executed N 1 times The loop is defined by the RPTB instruction and the EXCH label Repeat Modes Example 2 7 Loop Using Block Repeat i ITLE LOOP USING BLOCK REPEAT THIS CODE SEGMENT EXCHANGES THE VALUES OF ARRAY ELEMENTS THAT ARE E SYMMETRIC AROUND THE MIDDLE OF THE ARRAY LDI ADDR ARO ARO points to the beginning of the array LDI ARO AR1 ADDI 63 AR1 7 AR1 points to the end of the 64telement array LDI 31 RC H Initialize repeat counter RPTB EXCH Repeat RC 1 times between here and EXCH LDI ARO RO Load one memory element in RO LDI AR1 R1 and the other in R1 EXCH STI R1 ARO 1 Then exchange their locations I STI RO AR1 1 The Program Flow Controlchapter in the TMS320C3x User s Guide discusses restrictions in the block repeat construct According to the contents of regis ters RS RE and RC the prog
516. ts wide File2 data bss section 32 bits wide JueuiuoJ4Au3 2 e ul uiejs4s jabiel ZEOOZESWL e 6unoog Booting a TMS320C32 Target System in a C Environment 4 8 5 Boot Table Memory Considerations There is a significant difference in the methods of interfacing the external memory holding the boottable and the program data memory used during nor mal code execution The address presented on the C32 s pins may be shifted by one or two bits depending on the size of the memory bank see Figure 4 42 but the external memory holding the boot table must have no ad dress shift relative to the C32 address pins regardless of the width of the boot memory see Figure 4 43 The boot loader program reads the boot table memory width from the first word of the boot table It reads the boot table con tents as 32 bit data and depending on the memory width it reconstructs the program and data before sending them to the memory map Because of this difference in the address shift the byte wide EPROM containing the boot table is not best suited to store normal data unless special hardware is added to han dle the address shift Memory Interfacing 4 99 Booting a TMS320C32 Target System in a C Environment Figure 4 42 Memory Configuration for Normal Program Execution 32 bit data bus t 8 8
517. uctions push and pop the system stack The stack can be used inside subroutines for temporary storage of registers as in Example 2 1 on page 2 3 Two instructions PUSHF and POPF are for floating point numbers These instructions can pop and push floating point numbers to registers RO R7 This feature is very useful for saving the extended precision registers see Example 2 1 and Example 2 2 PUSH saves the lower 32 bits of an extended precision register and PUSHF saves the upper 32 bits To recover this extended precision number execute a POPF followed by POP It is important to perform the integer and floating point PUSH and POP in the above order since POPF forces the last eight bits of the extended precision registers to 0 User stacks can be built to store data from low to high memory or from high to low memory Two cases for each type of stack are shown You can build stacks by using the preincrement decrement and postincrement decrement modes of modifying the auxiliary registers AR You can implement stack growth from high to low memory in two ways 1 Store to memory using AhRnto push data onto the stack and read from memory using ARn to pop data off the stack 2 Store to memory using ARn to push data onto the stack and read from memory using ARn to pop data off the stack Figure 2 2 illustrates these two cases The only difference is that in Figure 2 2 a the AR always points to the top of the stack and i
518. uency Ls XA For example using this equation for an 8 kHz sampling rate with an MCLK of 6 25 MHz results in a Tx counter A of 11 A MCLK 2 x SCF Using Equation 8 2 Tx counter B results in 36 B MCLK 2 x A x Conver sion Frequency To initialize the AIC s Tx counter A and B registers you must send a primary communication followed by a secondary communication as explained in the following sections Primary communications load values into the D A while secondary communications load A D internal registers such as the control register Tx counters A and B and Rx counters A and B TLC32040 Interface to the TMS320C3x 8 4 4 1 Primary Communications Primary communications have a data value in the 14 MSBs D15 D2 of data and a mode selection in the two least significant bits LSBs D1 D0 This for mat is shown in Figure 8 7 The AIC sends the data value to the DAC and enables one of the modes shown in Table 8 2 depending on the two LSBs Figure 8 7 Primary Communication Data Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 DI DO DAC value Mode selection Table 8 2 Primary Communications Mode Selection LSBs Mode 00 Tx counter A lt TA Rx counter A RA Tx counter B lt TB Rx counter B RB 01 Tx counter A TA TA Rx counter A lt RA RA Tx counter B lt TB Rx counter B RB 10 Tx counter A lt TA TA Rx counter A RA RA Tx counter B TB Rx counter B RB 11 Tx coun
519. ues and double ended queues is based on the ma nipulation of the auxiliary registers for user stacks For queues two auxiliary registers are used one to markthe front ofthe queue from which data is popped and the other to mark the rear ofthe queue to where data is pushed For double ended queues two auxiliary registers are also necessary One register marks one end of the double ended queue and the other register marks the other end Data can be popped from or pushed onto either end Interrupt Service Routines 2 3 Interrupt Service Routines Interrupts on the C3x are prioritized and vectored When an interrupt occurs the corresponding flag is set in the interrupt flag IF register If the correspond ing bit in the interrupt enable IE register is set and interrupts are enabled by having the global interrupt enable GIE bit in the status register set to 1 interrupt processing begins You can also write to the IF register allowing you to force an interrupt by software or to clear interrupts without processing them 2 3 1 Correct Interrupt Programming For interrupts to work properly you must execute the following sequence of steps as shown in Example 1 1 1 Create and place an interrupt vector table in the appropriate memory location 2 Initialize the ITTP bit field C32 only 3 Create a software stack 4 Enable the specific interrupt 5 Enable global interrupts 6 Generate the interrupt signal 2 3 2 Software
520. ugh the ADC s SYNC signal The 32 bit word is then serially transmitted most significant bit MSB first through the SOUTA serial pin of the DSP102 to the DRO pin of the C3x serial port The C3x is programmed to drive the ana log interface bit clock from its CLKXO pin The bit clock drives both the ADC and DAC XCLK input The C3x transmit clock can also act as the input clock on the receive side of the C3x serial port Since the receive clock is synchronous to the C3x s inter nal clock the receive clock can run at full speed even though it is an external clock Burr Brown DSP101 2 and DSP201 2 Interface to TMS320C3x Similarly upon receiving a convert command CONV the DAC converts the last word received from the C3x It signals the C3x through the SYNC signal to begin transmitting a 32 bit word representing the two channels of data to be converted The data transmitted from the C3x DXO pin is input to both the SINA and SINB inputs of the DAC The C3x is set up to transfer bits at the maximum rate of about 8 Mbytes s It uses a dual channel sample rate of about 44 1 KHz by setting the following registers assuming a 32 MHz CLKIN Serial Port Port global control register OxOEBCO0040 FSX DX CLKX port control register 0x00000111 FSR DR CLKR port control register 0x00000111 Receive transmit timer control register 0x0000000F Timer Timer global control register 0x000002C1 Timer period register 0x000000B5 A synchronous
521. umber of bins to calculate ldi RIBINSIZE IRO Size of R I pair in array ldf NewMnsOld R7 R7 New K2 Old F ldf 0 R4 Zero the REAL filter sum ldf 0 R5 Zero the IMAG filter sum r mpyf3 ARO TR AR1 DR RO TR DR lt unroll from main loop rptb EndSFE R r Loop mpyf3 ARO TR AR1 DI R1 TR DI mpyf3 ARO TI AR1 DI RO TI DI addf3 R7 RO 1R3 TR DR DELTA mpyf3 ARO TI AR1 DR RO TI DR subf3 RO R3 R3 TR DR TI DI DELTA mpyf3 ARO IRO AR1 IRO RO TR DR used in next loop addf3 R1 R0 R2 TR DI TI DR stf R2 AR2 DI Save the new Fbin values SCE R3 AR2 IRO r subf3 R4 R3 R4 REAL sum sum R sum alternates sign of subf3 R5 R2 R5 IMAG sum raised cosine window coeficients For raised cosine window filters the endpoint bin values to the pass bins are scaled to 1 2 relative addf addf subf subf ldi ldf ldf if mpyf mpyf endif addf addf R4 R4 R5 RS R3 R4 R2 R5 GBbase ARI AR1 DI R2 AR1 DR R3 SFFTBINS amp 1 1 R4 l R5 R3 R4 R2 R5 Double inner 1 sum loop Subtract endpoints at 50 ptr to start of R I SFFT array If the loop count was odd the sum result is negative DSP Algorithms 6 97 Sliding FFT Example 6 18 SFFT ASM Continued ExitSFFT When the SFFT is finished the R accordingly for the desired output pha
522. umber of bits are changing state Relative data complexity ranges from 0 signifying minimal variation of data to a normalized value of 1 signifying greatest data variation TMS320C30 Power Dissipation 12 7 Current Requirements for Internal Circuitry 12 8 If a statistical knowledge of the data exists Figure 12 3 can be used to deter mine the exact power supply requirement according to internal bus usage For example Figure 12 3 indicates a 63 scale factor when all Fs are moved in ternally every cycle with two accesses per cycle This scale factor is multiplied by 55 mA from Figure 12 2 at one half H1 cycle transfer time yielding 34 65 mA because of internal bus usage Therefore an algorithm running under these conditions requires about 200 mA of power supply current 110 55 34 65 Since a statistical knowledge of the data may not be readily available a nomi nal scale factor may be used The median between the minimum and maxi mum values at 5096 relative data complexity yields a value of 0 80 and can be used as an estimate of a nominal scale factor You can use this nominal data scale factor of 80 for internal bus data dependency adding 44 mA to 110 mA quiescent current and 55 mA internal operations to yield 210 mA As an up per bound assume worst case conditions of three accesses of alternating data every cycle adding 85 mA from Figure 12 2 to 110 mA quiescent current and 55 mA internal operations to yie
523. uration One H1 cycle is required to turn the H1 clock on again Processor Initialization 1 9 Low Power Mode Interrupt The interrupt is driven active as soon as the interrupt source goes active It goes inactive again on detection of two H3 rising edges These two rising edges ensure that the interrupt is recognized during normal operation and af ter the end of IDLE2 operation when the clocks turn on again The interrupt goes inactive after the two H3 clocks are counted and does not go inactive again until after the interrupt source again goes inactive and returns to active Example 1 3 State Machine and Equations for the Interrupt Generation 16R4 PLD MODULE INTERRUPT GENERATION TITLE INTERRUPT GENERATION FOR IDLE2 AND NON IDLE2 TMS320C31A TMS320C31 c3xu5 device P16R4 inputs h3 Pin 1 intsrc Pin 2 Interrupt source output intx_ Pin 12 Interrupt input signal to the TMS320C31 sync src Pin 14 Internal signal used to synchronize the input to the H1 clock same Pin 15 Keeps track if the new interrupt source has occurred If active no new interrupt has occurred This logic makes the following assumptions The duration of the interrupt source is at least one H1 cycle in duration It takes one H1 cycle to turn the H1 clock on again The interrupt source is pulse or level triggered If the source stays active after being asserted it is regarded as the same interrupt request and not a new o
524. used with 10 pF load capacitors The fundamental for this crystal is at 60 3 20 MHz L must be chosen to resonate with C at a frequency between 20 and 60 MHz If you choose the frequency halfway in between 40 MHz the value of L is calculated as follows Ly 1 o2C1 1 An f2C4 1 472 40 x 106 2 10 x 10712 1 58 uH Since the value of this inductance is not critical the closest conveniently avail able inductor is used as long as the resonant frequency of L C falls between the desired overtone and the next lower overtone A variety of crystals have been evaluated in this circuit Although at higher fre quencies fifth overtone crystals are more commonly available they are not recommended for this circuit The available gain from the internal inverting am plifier limits this configuration to third overtone crystals Several third overtone crystal solutions for this circuit up to 60 MHz are listed in Table 9 2 on page 9 22 Design Considerations 9 4 Design Considerations This section discusses some of the aspects of the design of the oscillator and their effects on its operation 9 4 1 Crystal Series Resistance Ry The series resistance of the crystal has a strong effect on the design of the os cillator primarily in loop gain R limits the crystal s minimum impedance value seen at series resonance Since the impedances of Ly and C cancel each other at this frequency the impedance of the crystal is due ent
525. ut no other interrupt occurs When the routine finishes processing the IE register is restored to its original state The RETIcond instruction not only pops the next program counter address from the stack but also sets the GIE bit of the status register This enables all interrupts that have their interrupt en able bit set Example 2 3 Interrupt Service Routine TITLE INT ERRUPT SERVICE ROUTINI global ENABLE set 2 10 Set ISR2 2000 1 ERRUPT P P P P P P P L O MAIN PROC XOR POPF POP POPF POP POP POP POP RETI PROCESSING FOR ERNAL INTERRUPT INT2 ST Save status register DP Save data page pointer IE Save interrupt enable register RO Save lower 32 bits and RO A upper 32 bits of RO R1 Save lower 32 bits and R1 upper 32 bits of R1 IASK IE H Unmask only INTO ENABLE ST Enable all interrupts ESSING SECTION FOR ISR2 Disable all interrupts Restore upper 32 bits and lower 32 bits of R1 Restore upper 32 bits and lower 32 bits of RO IE Restore interrupt enable register DP Restore data page register ST Restore status register Return and enable interrupts Context Switching in Interrupts and Subroutines 2 4 Context Switching in Interrupts and Subroutines Context switching is commonly required during the processing of subroutine
526. voltage on the output load is 2 15 V Unless otherwise specified all measurements are made at a DD Supply voltage of 5 0 V D Input clock frequency of 33 MHz Capacitive load of 80 pF Operating temperature of 25 C Figure 12 1 Current Measurement Test Setup for the TMS320C30 VDD CY7C186 25PC Tektronix current probe P6042 SRAM 2 15V R 8250 253 TMS320C30 32 D O 1 Y e l OA A Primary Expansion 12 4 2 15 V R 8250 32D 13A 1 LJ Current Requirements for Internal Circuitry 12 2 Current Requirements for Internal Circuitry The power supply current requirement for internal circuitry consists of the fol lowing factors quiescent current internal operations and internal bus opera tions Quiescent current and internal operations are constants but the internal bus operations vary with the rate of internal bus usage and the data values be ing transferred 12 2 1 Quiescent Current Quiescent current refers to the baseline supply current drawn by the C30 dur ing minimal internal activity It includes the current required to fetch an instruc tion from on or off chip memory Examples of quiescent current include D Maintaining timers and serial ports Executing the IDLE instruction C30 in HOLD mode pending external bus access C30 in reset Branching to self Li Li Li Li The quiescent requirem
527. w32767 88FFFEh hw32767 STABI EPI 387FFFh hw32768 Memory address space 16 bit data bus Qi Q Q Logical address Data A14 Ai4 Datan 11A14 Data Physical address shift 1 bit Ai A13 A13 A13 shift 1 bit 16 bit data size e A12 e 2 He gt 16 bit memory width e e o e 5 S e e Ep ude E 5 7 e A2 z 11 A2 A1 A1 t At AO ee A0 CSH udA0 CS A 1 D STRBO B2 STRBO B1 STRBO BO Notes 1 The amount of shift between logical and physical addresses depends only on the size of data being transferred 2 The amount of shift in the physical connection between the C32 and the external memory depends only on the width of the memory bank uone sueJ sseJppy pue eoejiaju LOWW uoije sueJ sseyppy pue eoejiaju AIOWayy LL G Figure D 8 Address Translation for 8 Bit Data Stored in 16 Bit Wide Memory CPU instruction STI RO OFFFh DP 90h Memory map Logical address space shed b1 880000h Fi b2 880001h b3 880002h b4 880003h IOSTRB e e o b65533 88FFFCh b65534 88FFFDh STRBO b65535 88FFFEh eum Ea BU Logical address shift 2 bits 8 bit data size STRBO control eee 0 register STRB Memory Data config width size o 1 o o eee STRBO 16 bits 8 bits STRB enable Logical address 23 to 0
528. with frequency The three components Ly Ry and Cy model the electrical behavior related to the mechanical vibration of the crystal Lx and C control the resonant frequency according to the same equation shown in Figure 9 1 Rx models the mechanical energy loss in the crystal and Quartz Crystal and Ceramic Resonators is related to the power dissipation in the crystal Co is the capacitance of the two electrodes The dielectric of the quartz physically separates the two elec trodes Together these components are a reasonably accurate electrical mod el for the behavior of the crystal Values for these component models are usu ally available from the crystal manufacturer Figure 9 2 Crystal Equivalent Circuit Model Lx Rx Cx Co Notes 1 Cg is the capacitance of the two electrodes 2 Ly Rx and Cy model the electrical behavior related to the mechanical vibration of the crystal Ly and Cy control the resonant frequency according to the same equation shown in Figure 9 1 and Ry models the mechanical energy loss in the crystal Like the series LC resonator crystals have an impedance minimum at a fre quency determined by Lx and Cx This is the series resonant frequency fs The presence of Co also introduces an impedance maximum at a frequency determined by Lx and Co This frequency is the parallel resonant frequen cy fp A graph of impedance magnitude that illustrates this behavior is also shown in Figure 9 3
529. with no performance penalty See the 7MSS320C3x User s Guide for more information on the C32 enhanced external memory interface The translation starts when an instruction requests a data read from a certain external address Address locations referenced by program instructions are logical addresses Before the logical address shows up on the external pins of the C32 it may undergo a 1 or 2 bit shift to the right that depends only on the size of the data being accessed The address at the pins is a physical address Before it is presented at the pins of the memory device the physical address may again be shifted this time to the left if the memory is other than 32 bits wide The physical to memory address shift is one bit for 16 bit wide memory and two bits for 32 bit memory The Table D 1 and Table D 2 sum marize the rules that apply to the variable data size and memory width for any C32 system Table D 1 Variable Memory Wiath D 4 Physical Address to Memory Physical Address Memory Address Shift Width Strobes Valid Lines Valid bits 32 STRBx B3 A23 A0 0 STRBx_B2 STRBx_B1 STRBx BO 16 STRBx B1 A23 A0 1 STRBx BO A 1 8 STRBx BO A23 A0 2 A 1 A 2 Memory Interface and Address Translation Table D 2 Variable Data Size Logical to Physical Data Size Address Shift bits 32 0 16 1 8 2 Figure D 3 through Figure D 11 show how the address changes when acces sing data of varying size from memory
530. wn Y 40 bits 32 bits 5 77 32 bits 101 0 910001h 102 0 910002h 910003h Seely ete 104 0 910004h 105 0 910005h STRB1 ccs FREE e control register 32 bits 32 bits e e dSd ZED0ZESWL eui 0 Aiowayy Bureau Interfacing Memory to the TMS320C32 DSP 4 6 1 4 Program Fetch From 32 Bit STRB1 Memory Table 4 5 shows program memory mapped to 32 bit wide STRBO or STRB1 memory By hardwiring the PRGW pin to a low state 32 bit data transfers to and from the 32 bit wide external memory do not involve any data operations in the memory interface The small program stored in STRB1 memory begins with the LDI instruction reading a 32 bit integer from 32 bit wide STRBO memory and loading it into RO see Figure 4 14 Next the FLOAT instruction converts the integer in RO to a 40 bit floating point number and loads it into R1 Finally the STF instruc tion truncates the 40 bit contents of R1 to 32 bits and stores it in the 32 bit wide IOSTRB memory The data is not modified as it passes through the memory interface The program controlling the data conversion in this example is stored in the 32 bit wide memory bank mapped to STRB1 Program fetch cycles do not ref erence the strobe control register to determine the width of the program memory Instead the memory interface checks the state of the PRGW pin to determine the memory width Because the program memory is 32 bits wide the PRGW pin should be grounded effectively directing the mem
531. x 2 SUBRF 1 5 R2 R2 1 5 v 2 x 2 x 2 PYF R2 R1 R1 x 3 x 2 1 5 t v 2 x 2 x 2 RND R1 PYF R1 R1 R2 R2 x 3 x 3 PYF RO R2 R2 v 2 x 3 x 3 SUBRF 1 5 R2 R2 1 5 v 2 x 3 x 3 PYF R2 R1 R1 x 4 x 3 i 1 5 t v 2 x 3 x 3 RND R1 MPYF RI RI R2 R2 x 4 x 4 MPYF RO R2 R2 v 2 x 4 x 4 SUBRF 1 5 R2 R2 1 5 v 2 x 4 x 4 MPYF R2 R1 R1 x 5 x 4 1 5 v 2 x 4 x 4 RND R1 RO Round MPYF R3 R0 Sqrt v from sqrt v 1 RETS end end Logical and Arithmetic Operations 3 15 Extended Precision Arithmetic 3 6 Extended Precision Arithmetic The C3x offers 32 bits of precision for integer arithmetic and 24 bits of preci sion in the mantissa for floating point arithmetic For higher precision in float ing point operations the eight extended precision registers R7 to RO contain eight additional bits of accuracy Since no comparable extension is available for fixed point arithmetic this section shows how you can achieve fixed point double precision by using the processor The technique consists of performing the arithmetic by parts which is similar to performing longhand arithmetic In the instruction set operations ADDC add with carry and SUBB subtract with borrow use the status carry bit for extended precision arit
532. xample 6 4 show A law compression and expansion For expansion using a look up table is an alternative approach A look up table trades memory space for speed of execution Since the compressed data is eight bits long you can construct a table with 256 entries containing the expanded data If the compressed data is stored in the register ARO the following two instructions put the expanded data in register RO ADDI TABL ARO TABL BASE ADDRESS OF TABLE LDI ARO RO PUT EXPANDED NUMBER IN RO You could use the same look up table approach for compression but the re quired table length would be 16384 words for u law and 8192 words for A law If this memory size is not acceptable use the subroutines presented in Example 6 1 or Example 6 3 Example 6 1 u Law Compression Companding TITLE U LAW COMPRESSION SUBROUTINE MUCMPR ARGUMENT ASSIGNMENTS ARGUMEN FUNCTION RO NUMBER TO BE CONVERTED REGISTERS USED AS INPUT RO REGISTERS MODIFIED RO R1 R2 SP REGISTER CONTAINING RESULT RO NOTE SINCE THE STACK POINTER SP IS USED IN THE COMPRESSION ROUTINE MUCMPR MAKE SURE TO INITIALIZE IT IN THE CALLING PROGRAM CYCLES 20 WORDS 17 global MUCMPR MUCMPR LDI RO R1 H Save sign of
533. xample 8 2 TMS320C3x BB DSP102 202 Driver Continued INIT ARRAYS void ini int 4 INITIALIZE void init arrays int t buffer 1 KK ck kk kk kk ke ko ke ko ke ke ke ke ke ke ke ke e ke e e e ee e x f INITIALIZE AND Z ERO FILL ARRAYS if inputO float heap overflow if outputO float heap overflow if input xfer0 float heap overflow if output_xfer0 float heap overflow if inputl float heap_overflow if outputl float heap_overflow if input_xferl float heap overflow if output xferl float heap overflow for i 0 i lt t buffer i outputO i output xferO i outputl i output xferl i INITIALIZI P Cali Cali Cali Cali Cali Cali Cali Cali eo O O ERS loc r bu Loe t bu loc r bu loc t bu Loc r bu loc t bu loc r bu loe t bu ffer sizeo ffer sizeo ffer sizeo ffer sizeo ffer sizeo ffer sizeo ffer sizeo ffer sizeo COMMUNICATIONS TO DSP102 202 t bb int period value dendif H Ft H mh Fh Fh Fh Fh RESET D A
534. xecution This frees the buses for operand fetches Use parallel instructions It is possible to perform a multiply in parallel with an add or subtract and to execute stores in parallel with any multiply or arithmetic logic unit ALU operation This increases the number of operations executed in a single cycle For maximum efficiency observe the addressing modes used in parallel instructions and arrange the data appropriately It is possible to have loads in parallel with any multiply or add or subtract by multiplying by 1 or adding a 0 Therefore to implement parallel instructions with a data load substitute a multiply or an add instruction with one extra register containing 1 or 0 respectively in place of a load instruction Maximize the use of registers The registers are an efficient way to access scratch pad memory Extensive use of the register file facilitates the use of parallel instructions and helps avoid pipeline conflicts when you use the registers in addressing modes Usethe cache This is especially important in conjunction with slow exter nal memory The cache is transparent to the user so make sure that it is enabled Use internal memory instead of external memory The internal memory 2K x 32 bits RAM and 4K x 32 bits ROM is considerably faster to access In a single cycle two operands can be brought from internal memory You can maximize performance if you use the direct memory ac cess DMA in parallel with the C
535. y current factor The power supply current for the external buses is made up of three factors and is summarized in the following equation Ibase lprim lexp power supply current for the external buses where lbase 60 mA baseline current lprim primary bus current lexp expansion bus current The remainder of this section describes in detail the calculation of external bus current factors TMSS320C30 Power Dissipation 12 9 Current Requirement for Output Driver Circuitry 12 3 1 Primary Bus Current 12 10 The current from primary bus writes varies with both wait states and write cycle time Current factors from output driver circuitry are represented as offsets from the previously computed value quiescent internal operations internal bus Since the baseline value is related to internal current factors negative values for current offset are obtained under some circumstances However negative current does not occur To obtain accurate current values you must first establish the timing of write cycles of the buses To determine the rate and timings at which write cycles to the external buses occur you must analyze program activity including any pipeline conflicts that may exist Information from this manual and the C30 emulator or simulator is useful in making these determinations You must account for the effects of cache use in these analyses because the cache can affect whether instructions are fetched from external
536. y domain 1 0 1 0 0 5 gt l 0 0 0 71 0 0 0 0 N d ana oN N WIn 1 cos 2 5 b 2 2 6 8 6 Using SFFT ASM for Spectrum Analysis If the SPECT_EN variable is set to 1 true the DSK analog output is config ured to be the computed spectrum of the analog input beginning at BIN START andending atBIN END The outputisthen viewed using an oscil loscope which is triggered on a positive synch pulse The DAC output voltage is proportional to the log magnitude of each frequency bin To help pass impulses with minimal magnitude errors each DAC output sam ple can be repeated upto DAC RPT times Also the AIC TA register value can be programmed to have a very high pass band This increases the DAC output distortion which is a problem if used for audio applications but is acceptable for visual purposes Also the BIN START and BIN END values do not need to begin at zero or end at SFFTSIZE 2 This can be used to show that the frequency bins repeat in the frequency domain as predicted by the discrete Fourier transform The only restrictions are the availability memory and CPU processing power 6 8 7 Using SFFT ASM for Hilbert Transforms and Arbitrary Phase Angles Filters If SPECT EN is set to 0 the output is configured to be the summation of the reconstructed REAL and IMAG components An arbitrary output phase angle is implemented by performing a complex mul tiplication ofthe REAL and IMAG compone
537. y execution point FFT SIZE usect ifftdata l Reserve memory for arguments LOG SIZE usect ifftdata l SOURCE ADDR usect ifftdata 1 DEST ADDR usect ifftdata 1 SINE TABLE usect ifftdata 1 BIT REVERSE usect ifftdata 1 SEPARATION usect ifftdata 1 DSP Algorithms 6 63 Fast Fourier Transforms FFTs Example 6 17 Real Inverse Radix 2 FFT Continued Initialize C Function sect iffttext fft rli PUSH FP Preserve C environment LDI SP FP PUSH R4 PUSH R5 PUSH R6 PUSHF R6 PUSH R7 PUSHF R7 PUSH AR4 PUSH AR5 PUSH AR6 PUSH AR7 PUSH DP LDP FFT SIZE Initialize DP pointer LDI FP 2 R0 Move arguments from stack SII RO GFFT SIZE LDI FP 3 R0 STI RO GLOG SIZE LDI FP 4 RO0 SIT RO SOURCE_ADDR LDI FP 5 RO0 STI RO DEST_ADDR LDI FP 6 RO STI RO SINE_TABLE LDI FP 7 RO STI RO BIT_REVERSE 6 64 Example 6 17 Real Inverse Radix 2 FFT Continued Fast Fourier Transforms FFTs LOOP Perform last FFT loops first loop 2 LOOP lst 2nd v v KF I1 0 0 AR1 gt X I1 1st 1 1 X I1 2nd 2 2 X I1 3rd 3 3 A X I2 8 16 B X I2 3rd 13 29 X I2 2nd 14 30 AR2 gt X I2 ist 15 31 lt X 13 16 32 AR3 gt X 13 Ist 17 33 X I3 2nd 18 34 X I13 3rd 19 35 C X 14 24 48 D X I4 3rd 29 61 X I4 2nd
538. y not apply directly to the pro gram data content For example the COFF file may include a symbol table for the debugger or a memory width control word for the on chip boot loader Using the debugger to load the COFF file to target memory requires connect ing the target board to the PC on which the debugger is running with an emu lator cable and pod and then transferring the COFF file with the LOAD com mand The linker c cr options control processing of the cinit section during the load operation The COFF file can also be loaded to a target system from an EPROM The Hex30 utility converts the COFF file to an EPROM programmer compatible file that can be programmed to the EPROM In the microprocessor mode the program executes directly from the EPROM In the microcontroller boot loader mode the on chip boot loader first expands the EPROM contents into target SRAM and the program executes from SRAM In either case the C program begins execution at the start of the boot asm library routine to initialize the C environment before the rest of the C program runs 4 8 3 Debugger Boot Figure 4 38 on page 4 93 and Figure 4 39 on page 4 94 show how to load the COFF file into the target system using the debugger load command The debugger is a standard TI software development tool that runs on a PC platform The debugger accesses the target board through the PC emulator card and cable The cable connects to the target board through a 12
539. you should use the average power unless the time duration of individual pro gram segments is long The thermal characteristics of the C30 in the 181 pin grid array PGA package are exponential in nature with a time constant of t 4 5 minutes When subjected to a change in power the temperature of the device package will after 4 5 minutes reach approximately 63 of the total temperature change Accordingly if the time duration of program segments exhibiting high power dissipation values is short on the order of a few seconds you can use average power calculated in the same manner as aver age current as described in section 12 4 4 on page 12 20 Otherwise you should calculate maximum device temperature on the basis of the actual time duration of the program segments involved For example if a particular program segment lasts for seven minutes you can calculate that a device will reach approximately 8096 of the temperature change from the total power dissipation during the program segment You can determine average power by calculating the power for each program segment including the previous considerations and performing a time aver age of these values rather than simply multiplying the average current as de termined in the previous section by Vpp Specific device temperature calculations are made using the C30 thermal impedance characteristics in the TMS320C30 Digital Signal Processor data sheet TMS320C30 Power Dissipation
540. yte value values Note that byte does not begin in column one This syntax shows that byte must have at least one value parameter but you have the option of supplying additional value parameters each sepa rated from the previous one by a comma Read This First V Information About Cautions and Warnings Information About Cautions and Warnings This book may contain cautions and warnings This is an example of a caution statement A caution statement describes a situation that could potentially damage your software or equipment This is an example of a warning statement A warning statement describes a situation that could potentially cause harm to you The information in a caution or a warning is provided for your protection Please read each caution and warning carefully vi Related Documentation From Texas Instruments Related Documentation From Texas Instruments The following books describe the TMS320 floating point devices and related support tools To obtain a copy of any of these TI documents call the Texas Instruments Literature Response Center at 800 477 8924 When ordering please identify the book by its title and literature number JTAG MPSD Emulation Technical Reference literature number SPDUO79 provides the design requirements of the XDS510 emulator controller discusses JTAG designs based on the IEEE 1149 1 standard and modular port scan device MPSD designs Setting Up

TMS320C3x GENERAL-PURPOSE APPLICATIONS USER'S GUIDE

Contents

Download Pdf Manuals

Related Search

Related Contents