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FIFO Generator Core v3.3 User Guide

1. 54 Chapter 4 Designing with the Core e Single threshold constant e Single threshold with dedicated input port e Assert and negate threshold constants provides hysteresis e Assert and negate thresholds with dedicated input ports provides hysteresis Note The built in FIFOs only support single threshold constant programmable full These options are available in the CORE Generator GUI and accessed within the programmable flags window Figure 3 4 The programmable empty flag PROG_EMPTY is asserted when the number of entries in the FIFO is less than or equal to the user defined assert threshold If the number of words in the FIFO is greater than the negate threshold the flag is deasserted Note f a read operation occurs on a rising clock edge that causes the number of words in the FIFO to be equal to or less than the programmable empty threshold then the programmable empty flag will assert on the next rising clock edge The deassertion of the programmable empty flag has a longer delay and depends on the read and write clocks Programmable Empty Single Threshold This option enables the user to set a single threshold value for the assertion and deassertion of PROG_EMPTY When the number of entries in the FIFO is less than or equal to the threshold value PROG_ EMPTY is asserted When the number of entries in the FIFO is greater than the threshold value PROG_EMPTY is deasserted There are two options for implementing this th
2. Table 2 5 Write Interface Signals for FIFOs with Independent Clocks Name Direction Re Description quired WR_CLK Input Write Clock All signals on the write domain are synchronous to this clock DIN N 0 Input Data Input The input data bus used when writing the FIFO WR_EN Input Write Enable If the FIFO is not full asserting this signal causes data on DIN to be written to the FIFO FULL Output Optional Full Flag When asserted this signal indicates that the FIFO is full Write requests are ignored when the FIFO is full initiating a write when the FIFO is full is non destructive to the contents of the FIFO ALMOST_FULL Output Almost Full When asserted this signal indicates that only one more write can be performed before the FIFO is full PROG_FULL Output Programmable Full This signal is asserted when the number of words in the FIFO is greater than or equal to the assert threshold It is deasserted when the number of words in the FIFO is less than the negate threshold WR_DATA_COUNT D 0 Output Write Data Count This bus indicates the number of words stored in the FIFO The count is guaranteed to never under report the number of words in the FIFO to ensure the user never overflows the FIFO The exception to this behavior is when a write operation occurs at the rising edge of WR_CLK that write operation will only be reflected on WR
3. Independent Clocks Built in FIFO page 42 This implementation is only available when using Virtex 5 or Virtex 4 architectures This implementation optionally supports first word fall through selectable in the second GUI screen shown in Figure 3 2 Performance Options and Data Port Parameters This screen provides performance options and data port parameters for the core amp Fifo Generator v3 3 E us logi PF Fifo Generator v3 3 Al Read Mode Standard FIFO DIN O 0 DOUT First Word Fall Through bat Data Port Parameters Write Width 1 v FULL L RD_EN Write Depth 1024 y Read Width 1 Read Depth 1024 CLK Built in FIFO Options Read Clock Frequency MHz 100 Range 1 1000 EMPTY Write Clack Frequency MHz 100 Range 1 1000 Enable ECC 5 Y lt gt IP Symbol View Data Sheet Page 2 of 6 lt Back N 1 Finish Cancel Figure 3 2 Performance Options and Data Port Parameters Screen FIFO Generator v3 3 User Guide www xilinx com 31 UG175 April 2 2007 7 XILINX Chapter 3 Generating the Core Performance Options Only available when Virtex 5 built in FIFO or independent clock FIFO with block RAM or distributed RAM FIFOs is selected For more information see Read Operation page 46 Standard FIFO Implements a FIFO with standard latencies and without using output registers First word Fall through FIFO Implements a FIFO with registered outputs For
4. The user can either choose to set the assert and negate threshold to the same value using PROG EMPTY THRESH or the user can control these values independently using PROG EMPTY THRESH ASSERT and PROG EMPTY THRESH NEGATE PROG EMPTY THRESH Input Programmable Empty Threshold Assert This signal ASSERT is used to set the lower threshold value for the programmable empty flag which defines when the signal is asserted The threshold can be dynamically set in circuit during reset PROG EMPTY THRESH Input Programmable Empty Threshold Negate This signal NEGATE is used to set the upper threshold value for the programmable empty flag which defines when the signal is deasserted The threshold can be dynamically set in circuit during reset 24 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 FIFO Interfaces 7 XILINX Table 2 6 Read Interface Signals for FIFOs with Independent Clocks Continued Name Direction Description SBITERR Output Single Bit Error Indicates that the ECC decoder detected and fixed a single bit error on a Virtex 5 built in FIFO macro See Built in Error Correction Checking page 60 DBITERR Output Double Bit Error Indicates that the ECC decoder detected a double bit error ona Virtex 5 built in FIFO macro and data in the FIFO core is corrupted See Built in Error Correction Checking page 60 FIFO Generator v3 3 User Guid
5. Component Name fifo generator v3 3 FIFO Implementation DIN 0 0 DOUTI Choose the FIF implementation from one of the following WR EN Supported Features DUE Read Write Clock Domains Memory Type 1 2 3 4 RD EN A Common Clock CLK Block RAM Common Clock CLK Distributed RAM CLK Common Clock CLK Shift Register Common Clock CLK Built in FIFO x Independent Clocks RD CLK WR CLK Block RAM x X EMPTY Independent Clocks RD CLK WR CLK Distributed RAM x Independent Clocks RD CLK WR_CLK Built in FIFO x 1 Non symmetric aspect ratios different read and write data widths 2 First Word Fall Through 3 Uses Virtex 4 and Virtex 5 built in FIFO primitives 4 ECC support 5 2 v 3 IP Symbol a View Data Sheet Page 1 of 6 Back Nest Finish Cancel Figure 3 1 Main FIFO Generator Screen Component Name Base name of the output files generated for this core The name must begin with a letter and be composed of the following characters a to z 0 to 9 and _ FIFO Implementation This section of the GUI allows the user to select from a set of available FIFO implementations and supported features The key supported features that are only available for certain implementations are highlighted by checks in the right margin The available options are listed below with cross references to additional information Common Clock CLK Block
6. Generating the Core Overflow Write Error Generates overflow flag which indicates when the previous write operation was not successful This signal can be configured to be active high or low default active high Read Port Handshaking Valid Read Acknowledge Generates valid flag which indicates when the data on the output bus is valid This signal can be configured to be active high or low default active high Underflow Read Error Generates underflow flag to indicate that the previous read request was not successful This signal can be configured to be active high or low default active high Initialization Reset Pin For FIFOs implemented with block RAM or distributed RAM a reset pin is not required and the input pin is optional For a common clock FIFO implemented using distributed or block RAM the user has the option to generate a synchronous or asynchronous reset 34 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 Programmable Flags XILINX Programmable Flags Use this screen to select the programmable flag type when generating a specific FIFO Generator configuration Fifo Generator v3 1 lagi PE Fifo Generator v3 3 Programmable Flags Programmable Full Type No Programmable Full Threshold Full Threshold Assert Value 4095 Range 0 4096 Full Threshold Negate Value 4095 Range 0 4096 Programmable Empty Type No Programmable Empty Threshold Empty Threshold Assert
7. and Initialization 0 33 Optional Flags seien penite ree desde 33 Almost Full Flap o seia iaai tala A dee pl eet det ode d MER Yeas 33 Almost Empty Flag s Lies ue Eee eat edes e eer be sai 33 Write Port Handshaking irer errodiiei tirua hiiia ie e 33 Write Acknowledge viii ei pd iae e ede ma Stag eas 33 Overflow Write Error 0 0 ec hmm n 34 Read Port Handshaking 0 occ eee 34 Valid Read Acknowledge sees n 34 Uniderflow Read Error 22 d dare e ea ende ede a teca Qe sow kde Re ec t e P 34 Initialization 4 ect A eee aee Ege epe ee Lee ques Y pa 34 CA AA O oes apr endete ice tre tete m e aes eet te te eee 34 Programmable Plas 22r e RECO ici ECRIRE OA Re e oe 35 Programmable Flags 252 22 rk Lek 4 eR e x d lee tha 35 Programmable Full Type 24 52 22 ii ee ee Yd E ORE ER 35 Programmable Empty Type sepias cee bet cece cee eee eee hn 35 Data Count and Reset 0 020350 nc anciagakin dates acces k a sees GRUT wens 36 Data Count and Reset Options a 0 66 ene eee 36 Data Count cat pb hoes AA ace E ee ake AA Fee i ee eg eee eae 36 Rest 2 63 20 4000 aserrada aa 37 SII ni a Ego EPOR POETE OE 37 Chapter 4 Designing with the Core General Design Guidelines iiv pda texkR ERRARE e RARO ERA Rd ER RE Re d e 39 Know the Degree of Difficulty ooooooooooccccoconroononnnrrra e 39 Understand Signal Pipelining and Synchronization 6 6 00 cee eee 39 Synchr
8. 11 Handshaking Signals for a FIFO with Common Clocks Programmable Flags The FIFO supports programmable flags to indicate that the FIFO has reached a user defined fill level e Programmable full PROG_FULL indicates that the FIFO has reached a user defined full threshold e Programmable empty PROG_EMPTY indicates that the FIFO has reached a user defined empty threshold FIFO Generator v3 3 User Guide www xilinx com 51 UG175 April 2 2007 7 XILINX 52 Chapter 4 Designing with the Core For these thresholds the user can set a constant value or choose to have dedicated input ports enabling the thresholds to change dynamically in circuit Hysteresis is also optionally supported by providing unique assert and negate values for each flag Detailed information about these options are provided below Programmable Full The FIFO Generator supports four ways to define the programmable full threshold e Single threshold constant e Single threshold with dedicated input port e Assert and negate threshold constants provides hysteresis e Assert and negate thresholds with dedicated input ports provides hysteresis Note The built in FIFOs only support single threshold constant programmable full These options are available in the CORE Generator GUI and accessed within the programmable flags window Figure 3 4 The programmable full flag PROG_FULL is asserted when the number of entries in the FIFO is greater than or equal
9. 3 Generating the Core CORE Generator Graphical User Interface 0 0 0 e eee 29 FIFO Implementation ci 52 bere Rage tide Qi RE adr donde Ra docte doe dog 30 Component Name cese RE pa EE OR tea bra age Redes qo 30 FIFO Implementation 4i secs a EX ar e exe ERR d Oa Ware 30 Common Clock CLK Block RAM sseeeeeeee Ie 30 Common Clock CLK Distributed RAM 1 0 0 cece eee eee 30 Common Clock CLK Shift Register 6 eee eee ens 30 Common Clock CLK Built in FIFO 0 0 cece eect eee 31 Independent Clocks RD_CLK WR_CLK Block RAM 6 6 cece cece eee 31 FIFO Generator v3 3 User Guide www xilinx com UG175 April 2 2007 7 XILINX Independent Clocks RD_CLK WR_CLK Distributed RAM oooocoocm omo o o 31 Independent Clocks RD CLK WR CLK Built in FIFO 0 2 0 2 00 00000 31 Performance Options and Data Port Parameters 0004 31 Performance Opts cinc e adi e oa 32 Standard FIFO 44 cd A ea ace P bis 32 First word Fall through FIFO meae e edan k n e a hn 32 Data Port Parameters croci ce iieiea ae hh hrs 32 Input Data Width oces sicpi erens eie pegia i ge tee eye o ig Steen ee 32 Inp t Depth sr a ee i dace itd E E a edens 32 O tput Data Widthi i iota 2 ahead aad e lence gh needle e aei o dede aad 32 Output Depth iir e id A A did a 32 Built in FIFO Options 0 n erp er Reb ee que gea ve gest aaa 32 Optional Flags Handshaking
10. Clock Table 4 6 defines the values of the output ports during power up and the reset state DOUT reset value is supported for all architectures with the exception of Virtex and Spartan II If the user does not specify a DOUT reset value it defaults to 0 The FIFO requires a reset pulse of only 1 clock cycle FULL and ALMOST FULL flags are asserted during reset to ensure that no write operations occur and handshaking signals are deasserted during reset Note that the power up values for asynchronous reset are different than the reset state value The FIFO requires a reset pulse of at least three clock cycles in length Independent clock FIFOs require four cycles post reset prior to FIFO write availability this is necessary for proper reset synchronization Common clock FIFOs however require three cycles after reset prior to FIFO write availability For the built in FIFO the RE EN and WR EN signal is required to be deasserted during reset Table 4 6 FIFO Reset Values Block Memory Signal Distributed Memory Built in FIFO Power up 9 amp Shift Register Reset Values Values Values DOUT DOUT Reset Value Content of Same as reset or 0 memory at values location 0 FULL 12 0 0 ALMOST FULL 12 N A 0 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 FIFO Usage and Control XILINX Table 4 6 FIFO Reset Values Continued EMPTY 1 0 1 ALMOST EMPTY 1 N A 1 VALID
11. Parameters Appendix B FIFO Parameters Table B 1 describes the FIFO core parameters including the XCO file value and the default settings Table B 1 FIFO Parameter Table Parameter Name Component Name XCO File Values instance name ASCII text starting with a letter and using the following character set a z 0 9 and _ Default GUI Setting fifo_generator_v3_3 FIFO Implementation Common_Clock_Block_RAM Common Clock Distributed RAM Common Clock Shift Register Common Clock Builtin FIFO Independent Clocks Block RAM Independent Clocks Distributed RAM Independent Clocks Builtin FIFO Common Clock Block RAM Input Data Width Integer in range 1 to 256 16 Output Data Width Integer in range 1 to 256 16 Input Depth 2N where N is an integer 4 to 24 1024 Output Depth 2M where M is an integer 4 to 24 1024 Data Count Width Integer in range 1 to log Output Depth 2 Read Clock Frequency Integer 1 to 1000 MHz 100 Write Clock Frequency Integer 1 to 1000 MHz 100 Almost Full Flag true false false Almost Empty Flag true false false Enable ECC true false false Programmable Full Type No Programmable Full Threshold No Programmable Full Threshold Single Programmable Full Threshold Constant Multiple Programmable Full Threshold Constants Single Programmable Full Threshold Input Port Multiple Programmable Full Threshold Input Ports Full Threshold Assert Value See range unde
12. RAM For details see Common Clock FIFO Block RAM and Distributed RAM page 44 Common Clock CLK Distributed RAM For details see Common Clock FIFO Block RAM and Distributed RAM page 44 Common Clock CLK Shift Register For details see Common Clock FIFO Shift Registers page 44 This implementation is only available in Virtex II and newer architectures 30 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 Performance Options and Data Port Parameters XILINX Common Clock CLK Built in FIFO For details see Common Clock Built in FIFO page 44 This implementation is only available when using the Virtex 5 or Virtex 4 architectures This implementation optionally supports first word fall through selectable in the second GUI screen shown in Figure 3 2 Independent Clocks RD_CLK WR CLK Block RAM For details see Independent Clocks Block RAM and Distributed RAM page 41 This implementation optionally supports asymmetric read write ports and first word fall through selectable in the second GUI screen shown in Figure 3 2 Independent Clocks RD_CLK WR_CLK Distributed RAM For more information see Independent Clocks Block RAM and Distributed RAM page 41 This implementation optionally supports first word fall through selectable in the second GUI screen shown in Figure 3 2 Independent Clocks RD_CLK WR_CLK Built in FIFO For more information see
13. Read Flag Logic PROG_EMPTY RD_DATA_COUNT Read Counter Binary to Gray Converter Gray to Binary Converter LI i I LI i i r MEMORY WRITE PORT READPORT j I OPTIONAL 1 l Write Counter ADDRA DOUT First Word Fall e 1 Through Logic I SS a aa d WR_EN RD_EN DIN Read Counter Gray to Binary Converters Binary to Gray Converters Write Counter FULL ALMOST_FULL PROG_FULL WR_DATA_COUNT Write Flag Logic Figure 4 2 Functional Implementation of a FIFO with Independent Clock Domains FIFO Generator v3 3 User Guide www xilinx com 41 UG175 April 2 2007 XILINX Chapter 4 Designing with the Core This FIFO is designed to support an independent read clock RD_CLK and write clock WR_CLK in other words there is no required relationship between RD_CLK and WR_CLK with regard to frequency or phase The FIFO interface signals are only valid in their respective clock domains and are summarize in Table 4 1 Table 4 1 Interface Signals and Corresponding Clock Domains WR_CLK RD_CLK DIN DOUT WR_EN RD_EN FULL EMPTY ALMOST_FULL ALMOST_EMPTY PROG_FULL PROG_EMPTY WR_ACK VALID OVERFLOW UNDERFLOW WR_DATA_COUNT RD_DATA_COUNT For FIFO cores using independent clocks the timing relationship between the write and read operations and the status flags is affected by the relationship of the two clocks For example the timing between writing
14. The FIFO Generator provides a single reset input that resets all counters output registers and memories when asserted For block RAM or distributed RAM implementations resetting the FIFO is not required and the reset pin can be disabled in the FIFO There are two reset options asynchronous and synchronous Asynchronous Reset The asynchronous reset RST input asynchronously resets all counters output registers and memories when asserted When reset is implemented it is synchronized internally to the core with each respective clock domain for setting the internal logic of the FIFO to a known state This synchronization logic allows for proper timing of the reset logic within the core to avoid glitches and metastable behavior Due to the synchronization logic used there is a latency in the deassertion of the FULL ALMOST_FULL and PROG_FULL signals Figure 4 23 illustrates the reset behavior for a FIFO with an independent clock and Figure 4 23 illustrates the reset behavior for a FIFO with a common clock FIFO Generator v3 3 User Guide www xilinx com 61 UG175 April 2 2007 7 XILINX 62 Chapter 4 Designing with the Core WR_CLK PN Ve e A 2 pum RST 1 Eu 1 1 1 N ALMOST_FULL PROG_FULL Figure 4 22 Synchronous Reset FIFO with Independent Clock FULL I l ALMOST_FULL l PROG_FULL l Figure 4 23 Asynchronous Reset FIFO with Common
15. defined thresholds In addition optional handshaking and error flags are supported write acknowledge overflow valid and underflow and an optional data count provides the number of words in the FIFO For block RAM and distributed RAM implementations optional synchronous or asynchronous reset pin is available FIFO Generator v3 3 User Guide www xilinx com 19 UG175 April 2 2007 7 XILINX Chapter 2 Core Overview Common Clock Virtex 5 and Virtex 4 Built in FIFO This implementation category allows you to select the built in FIFO that is available in the Virtex 5 and Virtex 4 architectures and supports a common clock for write and read data accesses The feature set supported for this configuration includes status flags full and empty and optional programmable full and empty flags with user defined thresholds In addition optional handshaking and error flags are available write acknowledge overflow valid and underflow The built in FIFO configuration also supports the built in ECC feature FIFO Generator Features Table 2 3 summarizes the FIFO Generator features supported for each clock configuration and memory type Table 2 3 FIFO Configurations Summary Independent Clocks Common Clock FIFO Feature ilio TM Distributed n Distribute Built in Built in Block RAM RAM FIFO Block RAM RAM Shift FIFO Register Non symmetric v Aspect Ratios Symmetric v v v v v v Aspect Ratios Almo
16. full almost full empty and almost empty as well as programmable full and empty flags generated with user defined thresholds Optional read data count and write data count indicators provide the number of words in the FIFO relative to their respective clock domains In addition optional handshaking and error flags are available write acknowledge overflow valid and underflow Independent Clocks Virtex 5 and Virtex 4 Built in FIFO This implementation category allows you to select the built in FIFO that is available in the Virtex 5 and Virtex 4 architectures Operations in the read domain are synchronous to the read clock and operations in the write domain are synchronous to the write clock The feature set supported for this configuration includes status flags full and empty and programmable full and empty flags generated with user defined thresholds In addition optional handshaking and error flags are available write acknowledge overflow valid and underflow The Virtex 5 built in FIFO configuration also supports the built in ECC feature Common Clock Block RAM Distributed RAM Shift Register This implementation category allows the user to select block RAM distributed RAM or shift register and supports a common clock for write and read data accesses The feature set supported for this configuration includes status flags full almost full empty and almost empty and programmable empty and full flags generated with user
17. is selected Enter a user defined value or select a preset value from the drop down menu The valid range for this threshold is provided in the GUI When using a single threshold constant only the assert value is used Empty Threshold Negate Value Available when Programmable Empty with Multiple Threshold Constants is selected Enter a user defined value or select a preset value from the drop down menu The valid range for this threshold is provided in the GUI Data Count and Reset Use this screen to set data count and reset parameters Fifo Generator v3 2 Fifo Generator v3 3 Data Count Synchronized With Clk Data Count Width 2 Range 1 12 Write Data Count Synchronized With Write Clk Write Data Count Width 2 Range 1 12 Read Data Count Synchronized With Read Cik Read Data Count Width Range 1 12 Resets Dout Reset Value 0 Ie IP Symbol View Data Sheet Page 5 of 6 lt Back Next gt Finish Cancel Figure 3 5 Data Count and Reset Screen 36 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 Summary 7 XILINX Data Count and Reset Options Data Count Use Extra Logic For More Accurate Data Counts Only available for independent clocks FIFO with block RAM or distributed RAM and when using first word fall through This option uses additional external logic to generate a more accurate data count See First Word Fall Through Dat
18. more information about FWFT functionality see First Word Fall Through FIFO Read Operation page 48 Data Port Parameters Input Data Width Valid range is 1 to 256 Input Depth Valid range is 16 to 4194394 Only depths with powers of 2 are allowed Output Data Width Available if independent clocks configuration with block RAM is selected Valid range must comply with asymmetric port rules See Non symmetric Aspect Ratios page 58 Output Depth Automatically calculated based on Input Data Width Input Depth and Output Data Width Built in FIFO Options The Read Clock Frequency and Write Clock Frequency fields can be any integer from 1 to 1000 They are used to determine the optimal implementation of the domain crossing logic in the core This option is only available for built in FIFOs with independent clocks If the desired frequency is not within the allowable range scale the read and write clock frequencies so that they fit within the valid range while maintaining their ratio relationship The ECC feature enables built in error correction in the Virtex 5 built in FIFO macro When this feature is enabled the built in FIFO is set to the full ECC mode where both the encoder and decoder are enabled 32 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 Optional Flags Handshaking and Initialization XILINX Optional Flags Handshaking and Initialization This screen allows you to select th
19. operation is ignored the underflow flag is asserted and there is no change in the state of the FIFO underflowing the FIFO is non destructive ALMOST_EMPTY and EMPTY Flags Note The Virtex 5 and Virtex 4 built in FIFO does not support the ALMOST_EMPTY flag The almost empty flag ALMOST_EMPTY indicates that the FIFO will be empty after one more read operation This flag is active high and synchronous to RD_CLK This flag is asserted when the FIFO has one remaining word that can be read The empty flag EMPTY indicates that the FIFO is empty and no more reads can be performed until data is written into the FIFO This flag is active high and synchronous to the read clock RD_CLK If a read is initiated when EMPTY is asserted the request is ignored and UNDERFLOW is asserted Common Clock Note When write and read operations occur simultaneously while EMPTY is asserted the write operation is accepted and the read operation is ignored On the next clock cycle EMPTY is deasserted and UNDERFLOW is asserted 46 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 FIFO Usage and Control XILINX Modes of Read Operation The FIFO Generator supports two modes of read options standard read operation and first word fall through FWFT read operation The standard read operation provides the user data on the cycle after it was requested The FWFT read operation provides the user data on the same cycle in which it is requeste
20. reset providing the user the flexibility to change the programmable full threshold in circuit without re generating the core Note Refer to the CORE Generator GUI for valid ranges for each threshold Figure 4 12 shows the programmable full flag with a single threshold The user writes to the FIFO until there are seven words in the FIFO Since the programmable full threshold is set to seven the FIFO asserts PROG_FULL once seven words are written into the FIFO www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 FIFO Usage and Control 7 XILINX Note that both write data count WR DATA COUNT and PROG FULL have one clock cycle of delay Once the FIFO has six or fewer words in the FIFO PROG_FULL is deasserted A a a a a STL LIA Y a WR_EN WR_ACK WR_DATA_COUNT PROG_FULL o e o o ace e LLL y Figure 4 12 Programmable Full Single Threshold Threshold Set to 7 Programmable Full Assert and Negate Thresholds This option enables the user to set separate values for the assertion and deassertion of PROG_FULL When the number of entries in the FIFO is greater than or equal to the assert value PROG_FULL is asserted When the number of entries in the FIFO is less than the negate value PROG_FULL is deasserted There are two options for implementing these thresholds e Assert and negate threshold constants User specifies the threshold values through the CORE Generator GUI Once the core is generated th
21. s performance data Appendix B Core Parameters provides a comprehensive list of the parameters set by the CORE Generator GUI for the FIFO Generator FIFO Generator v3 3 User Guide www xilinx com 11 UG175 April 2 2007 7 XILINX Chapter About This Guide Additional Resources For additional information go to www xilinx com support The following table lists some of the resources you can access from this website or by using the provided URLs Resource Description URL Tutorials Tutorials covering Xilinx design flows from design entry to verification and debugging www xilinx com support techsup tutorials index htm Database of Xilinx solution records Answer Browser www xilinx com xlnx xil ans browserjsp Data Sheets Device specific information on Xilinx device characteristics including readback boundary scan configuration length count and debugging www xilinx com xlnx xweb xil publications index jsp Problem Solvers Interactive tools that allow you to troubleshoot your design issues www xilinx com support troubleshoot psolvers htm Tech Tips Latest news design tips and patch information for the Xilinx design environment www xilinx com xlnx xil tt home jsp Conventions This document uses the following conventions An example illustrates each convention Typographical The following typographical conventions are u
22. to an empty FIFO and the deassertion of EMPTY is determined by the phase and frequency relationship between the write and read clocks For additional information refer to the Synchronization Considerations page 39 Independent Clocks Built in FIFO 42 Figure 4 3 illustrates the functional implementation of FIFO configured with independent clocks using the Virtex 5 built in FIFO primitive This design implementation consists of cascaded built in FIFO primitives and handshaking logic The number of built in primitives depends on the FIFO width and depth requested The Virtex 4 built in FIFO implementation allows generation of a single primitive The generated core includes a FIFO flag patch defined in Solution 1 Synchronous Asynchronous Clock Work Arounds in the Virtex 4 User Guide FIFO Generator v3 3 User Guide UG175 April 2 2007 www xilinx com FIFO Implementations XILINX WRITE DOMAIN READ DOMAIN Cascaded Built in FIFO Primitives Logic For Optional Flags PROG_FULL Write Domain SBITERR DBITERR OVERFLOW UNDERFLOW Logic For Optional Flags Read Domain PROG_EMPTY Figure 4 3 Functional Implementation of Built in FIFO This FIFO is designed to support an independent read clock RD_CLK and write clock WR_CLK in other words there is no required relationship between RD_CLK and WR_CLK with regard to frequency or phase The FIFO interface signals are only valid in their respectiv
23. v3 3 User Guide UG175 April 2 2007 XILINX Chapter 6 Simulating Your Design The FIFO Generator is provided as a Xilinx technology specific netlist and as a behavioral or structural simulation model This chapter provides instructions for simulating the FIFO Generator in your design Simulation Models The FIFO Generator supports two types of simulation models based on the Xilinx CORE Generator system project options The models are available in both VHDL and Verilog Both types of models are described in detail in this chapter To choose a model do the following Open the CORE Generator Select Options from the Project drop down list Click the Generation tab Pom Choose to generate a behavioral model or a structural model Behavioral Models Important The behavioral models provided are designed to reproduce the behavior and functionality of the FIFO Generator but are not cycle accurate models except for the common clock FIFO with block RAM distributed RAM or shift registers If cycle accurate models are required and common clock FIFO with block RAM distributed RAM or shift registers is not selected it is recommended to use the structural model The behavioral models are considered to be zero delay models as the modeled write to read latency is nearly zero The behavioral models are functionally correct and will represent the behavior of the configured FIFO although the write to read latency and the be
24. write and read widths are set to the same value providing a 1 1 aspect ratio but any ratio between 1 8 to 8 1 is supported and the output depth of the FIFO is automatically calculated from the input depth and the write and read widths For non symmetric aspect ratios the full and empty flags are active only when one complete word can be written or read The FIFO does not allow partial words to be accessed For example assuming a full FIFO if the write width is 8 bits and read width is 2 bits the user would have to complete four valid read operations before full deasserts and a write operation accepted Write data count shows the number of FIFO words according to the write port ratio and read data count shows the number of FIFO words according to the read port ratio Note For non symmetric aspect ratios where the write width is smaller than the read width 1 8 1 4 1 2 the most significant bits are read first refer to Figure 4 17 and Figure 4 18 Figure 4 17 is an example of a FIFO with a 1 4 aspect ratio write width 2 read width 8 In this figure four consecutive write operations are performed before a read operation can be performed The first write operation is 10 followed by 11 00 and finally 01 The memory is filling up from the right to the left LSB to MSB When a read operation is performed the received data is 01 00 11 10 Write Read Operation Operat
25. 0 active high or 0 active high or 0 active high or 1 active low 1 active low 1 active low UNDERFLOW 0 active high or 0 active high or 0 active high or 1 active low 1 active low 1 active low WR_ACK 0 active high or 0 active high or 0 active high or 1 active low 1 active low 1 active low OVERFLOW 0 active high or 0 active high or 0 active high or 1 active low 1 active low 1 active low PROG_FULL 12 0 0 PROG_EMPTY 1 1 1 RD_DATA_COUNT 0 N A 0 WR_DATA_COUNT 0 N A 0 1 The ability to set DOUT to a user defined value is not available for block RAM implementations in Virtex Spartan ll and Spartan IIE DOUT resets to 0 when this feature is unavailable 2 When reset is asserted the FULL flags are asserted to prevent writes to the FIFO during reset 3 The underflow signal is dependent on RD_EN If RD_EN is asserted and the FIFO is empty underflow is asserted 4 The overflow signal is dependent on WR_EN If WR_EN is asserted and the FIFO if full overflow is asserted Synchronous Reset The synchronous reset SRST input is only available for the Block and Distributed RAM implementation of the common clock FIFO It synchronously resets all counters output registers and memories when asserted Because the reset pin is synchronous to the input clock and there is only one clock domain in the FIFO no additional synchronization logic is necessary Figure 4 24 illustrates the flags f
26. 16 Virtex 4 200 MHz 64 43 1 0 0 neem Virtex II 175 MHz 64 43 1 0 0 Virtex 5 350 MHz 84 57 2 0 0 Synchronous FIFO 4096 x 16 Virtex 4 225 MHz 80 55 4 0 0 PO Virtex II 175 MHz 80 55 4 0 0 Synchronous Virtex 5 475 MHz 48 61 0 0 32 FIFO Distributed 64 x 16 Virtex 4 250 MHz 89 47 0 0 128 RAM Virtex II 225 MHz 89 47 0 0 128 Synchronous Virtex 5 375 MHz 85 80 0 0 256 FIFO Distributed 512 x 16 Virtex 4 200 MHz 340 59 0 0 1024 RAM Virtex II 150 MHz 340 59 0 0 1024 Virtex 5 350 MHz 105 124 1 0 0 Independent Clocks FIFO 512x 16 Virtex 4 250 MHz 103 105 1 0 0 Block RAM Virtex II 200 MHz 103 105 1 0 0 FIFO Generator v3 3 User Guide www xilinx com 69 UG175 February 15 2007 XILINX Appendix A Performance Information Table A 1 Benchmarks FIFO Configured without Optional Features Continued Resources Depth x Performance anes Width dais MHz LUTs FFs BlockRAM Shift Distributed Register RAM Virtex 5 350 MHz 147 163 2 0 0 Independent Clocks FIFO 4096 x 16 Virtex 4 250 MHz 134 138 4 0 0 Block RAM Virtex II 175 MHz 134 138 4 0 0 DECEM Virtex 5 475 MHz 76 104 0 0 32 a SERES MEE 112 100 0 0 128 Distributed RAM Virtex II 225 MHz 112 100 0 0 128 Independent Virtex 5 350 MHz 126 148 0 0 256 Clocks FIFO np 512 x 16 Virtex 4 225 MHz 382 139 0 0 1024 Distributed RAM Virtex II 150 MHz 382 139 0 0 1024 Virtex 5 450 MHz 59 50 0 32 0 o 64x16 Virtex 4 200 MHz
27. 3 10 4 FIFO Generator v3 3 User Guide UG175 February 15 2007 www xilinx com 71 XILINX Table A 3 Benchmarks FIFO Configured with Virtex 5 FIFO36 Resources Appendix A Performance Information Resources FIFO Type Depth x Width Read Mode a MHz LUTs FFs FIFO36s Standard 500 2 6 1 512 x 72 Synchronous FIFO36 FWFT 400 4 6 1 with handshaking Standard 350 12 12 4 16k x 8 FWFT 375 16 13 4 Standard 500 0 2 1 512 x 72 Independent Clocks FWFT 500 0 2 1 FIFO36 basic Standard 375 6 2 4 16k x 8 FWFT 375 6 2 4 Standard 500 2 6 1 512 x 72 Independent Clocks FWFT 500 2 4 4 FIFO36 with handshaking Standard 350 8 8 4 16k x 8 FWFT 350 9 5 4 Table A 4 provides results for FIFOs configured to use the Virtex 4 built in FIFO with patch The benchmarks were performed using a Virtex 4 4vlx15 11 target device Table A 4 Benchmarks FIFO Configured with Virtex 4 FIFO16 Patch co g p Resources Depth x N FIFO T lock Ratio EI O Type Width Clock Ratios se istribute e LUTs FFs RAMs FIFO16s WR CLK RD CLK 375 110 129 72 1 Built in FIFO basic 512 x 36 RD CLK WR CLK 400 92 115 72 1 Built in FIFO WR_CLK gt RD_CLK 375 113 134 72 1 ith h haki 512 x 36 with handshaking RD CLK WR CLK 400 95 120 72 1 72 www xilinx com FIFO Generator v3 3 User Guide UG175 February 15 2007 XILINX Core
28. 3 User Guide www xilinx com UG175 April 2 2007 7 XILINX www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 XILINX Preface About This Guide The LogicCORE FIFO Generator User Guide v3 3 describes the function and operation of the FIFO Generator as well as information about designing customizing and implementing the core Guide Contents The following chapters are included Preface About this Guide describes how the user guide is organized the conventions used in the guide and information about additional resources Chapter 1 Introduction describes the core and related information including recommended design experience additional resources technical support and submitting feedback to Xilinx Chapter 2 Core Overview describes the core configuration options and their interfaces Chapter 3 Generating the Core describes how to generate the core using the Xilinx CORE Generator Graphical User Interface GUI Chapter 4 Designing with the Core discusses how to use the core in a user application Chapter 5 Special Design Considerations discusses specific design features that must be considered when designing with the core Chapter 6 Simulating Your Design provides instructions for simulating the design with either behavioral or structural simulation models Appendix A Performance Information provides a summary of the core
29. 68 43 0 64 0 Virtex II 150 MHz 68 43 0 64 0 Virtex 5 275 MHz 159 67 0 256 0 Shift Register FIFO 512x16 Virtex 4 200 MHz 312 82 0 512 0 Virtex II 150 MHz 312 82 0 512 0 Table A 2 provides results for FIFOs configured with multiple programmable thresholds The benchmarks were performed using Virtex II 2v3000 Virtex 4 4v1x15 11 and Virtex 5 5v1x50 2 target devices Table A 2 Benchmarks FIFO Configured with Multiple Programmable Thresholds Resources Depth x z Performance FIFO Type E Family ietri m Width MHz LUTs FFs BlockRAM Shift Distributed Register RAM Virtex 5 350 MHz 91 70 1 0 0 Synchronous FIFO 512 x 16 Virtex 4 200 MHz 109 68 1 0 0 lees hen Virtex Il 175 MHz 109 68 1 0 0 Virtex 5 350 MHz 124 88 2 0 0 Synchronous FIFO 4096 x 16 Virtex 4 225 MHz 135 86 4 0 0 nora Virtex II 175 MHz 135 86 4 0 0 Synchronous Virtex 5 475 MHz 75 90 0 0 32 FIFO Distributed 64x 16 Virtex 4 250 MHz 112 66 0 0 128 RAM Virtex II 225 MHz 112 66 0 0 128 70 www xilinx com FIFO Generator v3 3 User Guide UG175 February 15 2007 Resource Utilization and Performance 7 XILINX Table A 2 Benchmarks FIFO Configured with Multiple Programmable Thresholds Continued Resources Depth x Performance diis Width ki MHz LUTs FFs BlockRAM Shift Distributed Regi
30. 7 Core Overview Memory Configuration Benefits ccce esee 18 FIFO Configurations ssec eR RR RIP ie 18 FIFO Configurations Summary 20 Reset Signal for FIFOs with Independent ClockS oooooooo 21 Write Interface Signals for FIFOs with Independent Clocks 22 Read Interface Signals for FIFOs with Independent Clocks 23 Interface Signals for FIFOs with a Common Clock 26 Designing with the Core Interface Signals and Corresponding Clock Domains 42 Interface Signals and Corresponding Clock Domains 43 Implementation Specific Support for First Word Fall Through 47 Implementation specific Support for Data Counts 0 56 Implementation specific Support for Non symmetric Aspect Ratios 58 FIFO Reset Values suuuesseseeseslsseeee ern 62 FIFO Reset and Power up Values ssssssseseeeeeeeeeeeeee 64 Appendix A Performance Information Table A 1 Benchmarks FIFO Configured without Optional Features 69 Table A 2 Benchmarks FIFO Configured with Multiple Programmable Thresholds 70 Table A 3 Benchmarks FIFO Configured with Virtex 5 FIFO36 Resources 71 Table A 4 Benchmarks FIFO Configured with Virtex 4 FIFO16 Patch 72 Appendix B Core Parameters Table B 1 FIFO Parameter Table sseeeeeee RR Rh nen 73 FIFO Generator v3
31. AS IS WITH ALL FAULTS AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE WHETHER GIVEN BY XILINX OR ITS AGENTS OR EMPLOYEES XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DESIGN INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN WHETHER IN CONTRACT OR TORT OR OTHERWISE WILL INNO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN YOU ACKNOWLEDGE THAT THE FEES IF ANY REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY The Design is not designed or intended for use in the development of on line control equipment in hazardous environments requiring fail safe controls such as in the operation of nuclear facilities aircraft navigation or communications systems air traffic control life support or weapons systems High Risk Appl
32. D V a f IA i l I l UNDERFLOW l l t7 f l EMPTY I E ALMOST_EMPTY l mo Y l i l l l 1 0 t t Figure 4 7 Standard Read Operation for a FIFO with Independent Clocks FIFO Generator v3 3 User Guide www xilinx com 47 UG175 April 2 2007 7 XILINX 48 Chapter 4 Designing with the Core First Word Fall Through FIFO Read Operation The first word fall through FWFT feature provides the ability to look ahead to the next word available from the FIFO without issuing a read operation When data is available in the FIFO the first word falls through the FIFO and appears automatically on the output bus DOUT Once the first word appears on DOUT EMPTY is deasserted indicating one or more readable words in the FIFO and VALID is asserted indicating a valid word is present on DOUT Figure 4 8 shows a FWFT read access Initially the FIFO is not empty the next available data word is placed on the output bus DOUT and VALID is asserted When the user asserts RD EN the next rising clock edge of RD CLK places the next data word onto DOUT After the last data word has been placed on DOUT an additional read request by the user causes the data on DOUT to become invalid as indicated by the deassertion of VALID and the assertion of EMPTY Any further attempts to read from the FIFO results in an underflow condition VALID I I I I I n I I I I I I I I I I I I I I UNDERFLOW I I I l l J I I I I I
33. DATA COUNT at the next rising clock edge If D is less than log2 FIFO depth 1 the bus is truncated by removing the least significant bits WR ACK Output Write Acknowledge This signal indicates that a write request WR EN during the prior clock cycle succeeded OVERFLOW Output Overflow This signal indicates that a write request WR EN during the prior clock cycle was rejected because the FIFO is full Overflowing the FIFO is non destructive to the contents of the FIFO 22 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 FIFO Interfaces XILINX Table 2 5 Write Interface Signals for FIFOs with Independent Clocks Continued Name PROG_FULL_THRESH Direction Input Description Programmable Full Threshold This signal is used to input the threshold value for the assertion and deassertion of the programmable full PROG_FULL flag The threshold can be dynamically set in circuit during reset The user can either choose to set the assert and negate threshold to the same value using PROG_FULL_THRESH or the user can control these values independently using PROG_FULL_THRESH_ASSERT and PROG_FULL_THRESH_NEGATE NEGATE PROG FULL THRESH Input Programmable Full Threshold Assert This signal ASSERT is used to set the upper threshold value for the programmable full flag which defines when the signal is asserted The threshold can be dynamica
34. FO RD_EN Input Read Enable If the FIFO is not empty asserting this signal causes data to be read from the FIFO output on DOUT EMPTY Output Empty Flag When asserted this signal indicates that the FIFO is empty Read requests are ignored when the FIFO is empty initiating a read while empty is non destructive to the FIFO Optional DATA_COUNT C 0 Output Data Count This bus indicates the number of words stored in the FIFO If C is less than log2 FIFO depth 1 the bus is truncated by removing the least significant bits ALMOST_FULL Output Almost Full When asserted this signal indicates that only one more write can be performed before the FIFO is full www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 FIFO Interfaces Table 2 7 7 XILINX Interface Signals for FIFOs with a Common Clock Continued Name PROG_FULL Direction Output Description Programmable Full This signal is asserted when the number of words in the FIFO is greater than or equal to the assert threshold It is deasserted when the number of words in the FIFO is less than the negate threshold WR_ACK Output Write Acknowledge This signal indicates that a write request WR_EN during the prior clock cycle succeeded OVERFLOW Output Overflow This signal indicates that a write request WR_EN during the prior clock cycle was rejected because th
35. FULL_THRESH RST Figure 2 1 7 XILINX DOUT M 0 RD_EN RD_CLK A EMPTY ALMOST_EMPTY Write Clock Read Clock Domain Domain PROG_EMPTY VALID UNDERFLOW SBITERR DBITERR PROG_EMPTY_THRESH_ASSERT c 6 PROG_EMPTY_THRESH_NEGATE PROG_EMPTY_THRESH e Note Optional ports represented in italics FIFO with Independent Clocks Interface Signals Interface Signals FIFOs With Independent Clocks The RST signal as defined in Table 2 4 causes a reset of the entire core logic both write and read clock domains It is an asynchronous input which is synchronized internally in the core before being used The initial hardware reset should be generated by the user When the core is configured to have independent clocks the reset signal should be High for at least three read clock and write clock cycles to ensure all internal states are reset to the correct values Table 2 4 Reset Signal for FIFOs with Independent Clocks FIFO Generator v3 3 User Guide UG175 April 2 2007 Name Direction Description RST Input Reset An asynchronous reset signal that initializes all internal pointers and output registers www xilinx com 21 7 XILINX Chapter 2 Core Overview Table 2 5 defines the signals for the write interface for FIFOs with independent clocks The write interface signals are divided into required and optional signals and all signals are synchronous to the write clock WR_CLK
36. I I I I EMPTY uf I I I I I I I 1 j j Figure 4 8 FWFT Read Operation for a FIFO with Independent Clocks Common Clock FIFO Simultaneous Read and Write Operation Figure 4 9 shows atypical write and read operation A write is issued to the FIFO resulting in the deassertion of the EMPTY flag A simultaneous write and read is then issued resulting in no change in the status flags Once two or more words are present in the FIFO the ALMOST_EMPTY flag is deasserted Write requests are then issued to the FIFO resulting in the assertion of ALMOST_FULL when the FIFO can only accept one more write without a read A simultaneous write and read is then issued resulting in no change in the status flags Finally one additional write without a read results in the FIFO asserting FULL indicating no further data can be written until a read request is issued www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 FIFO Usage and Control XILINX WR_EN HA RAS mui y Ro H y Noi 1 ev NC Eo pp E po y ALMOST EMPTY t t n did l l FULL 1 fit ALMOST_FULL 4 1 L L Figure 4 9 Write and Read Operation for a FIFO with Common Clocks Handshaking Flags Handshaking flags valid underflow write acknowledge and overflow are supported to provide additional information regarding the status of the write and read operations The handshaking flags are optional and can be configured as active hi
37. IFO page 42 for more information Common Clock FIFO Block RAM and Distributed RAM Figure 4 4 illustrates the functional implementation of a FIFO configured with a common clock using block RAM or distributed RAM for memory All signals are synchronous to a single clock input CLK This design implements counters for write and read pointers and logic for calculating the status flags An optional synchronous SRST or asynchronous RST reset signal is also available MEMORY WRITE PORT READ PORT Read Counter Counter ALMOST_EMPTY PROG_EMPTY DATA_COUNT ALMOST_FULL PROG_FULL Figure 4 4 Functional Implementation of a Common Clock FIFO using Block RAM or Distributed RAM Common Clock FIFO Shift Registers Figure 4 5 illustrates the functional implementation of a FIFO configured with a common clock using shift registers for memory All operations are synchronous to the same clock input CLK This design implements a single up down counter for both the write and read pointers and logic for calculating the status flags 44 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 FIFO Usage and Control XILINX MEMORY WRITE PORT READ PORT DIN WE A DDR Pointer ALMOST_EMPTY PROG_EMPTY DATA_COUNT ALMOST_FULL PROG_FULL Flag Logic Figure 4 5 Functional Implementation of a Common Clock FIFO using Shift Registers FIFO Usage and Control Write
38. L_THRESH p DBITERR D PROG EMPTY THRESH ASSEHT PROG EMPTY THRESH NEGATE ca PROG_EMPTY_THRESH ui RST Note Optional ports represented in italics Figure 4 1 FIFO with Independent Clocks Write and Read Clock Domains For write operations the write enable signal WR EN and data input DIN are synchronous to WR CLK For read operations the read enable RD EN and data output DOUT are synchronous to RD CLK All status outputs are synchronous to their respective clock domains and can only be used in that clock domain The performance of the FIFO can be measured by independently constraining the clock period for the WR_CLK and RD CLK input signals The interface signals are evaluated on their rising clock edge WR CLK and RD CLE They can be made falling edge active relative to the clock source by inserting an inverter between the clock source and the FIFO clock inputs This inverter is absorbed into the internal FIFO control logic and does not cause a decrease in performance or increase in logic utilization Initializing the FIFO Generator 40 When designing with the built in FIFO or common clock shift register FIFO the FIFO must be reset after the FPGA is configured and before operation begins An asynchronous reset pin RST is provided which is an asynchronous reset that clears the internal counters and output registers For FIFOs implemented with block RAM or distributed RAM a reset is not re
39. LogiCORE FIFO Generator v3 3 User Guide UG175 April 2 2007 XILINX XILINX Xilinx is disclosing this Document and Intellectual Property hereinafter the Design to you for use in the development of designs to operate on or interface with Xilinx FPGAs Except as stated herein none of the Design may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of the Design may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes Xilinx does not assume any liability arising out of the application or use of the Design nor does Xilinx convey any license under its patents copyrights or any rights of others You are responsible for obtaining any rights you may require for your use or implementation of the Design Xilinx reserves the right to make changes at any time to the Design as deemed desirable in the sole discretion of Xilinx Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design THE DESIGN IS PROVIDED
40. O Dimensions White Width 1 Read Width 1 Write Depth 1024 Read Depth 1024 Estimated BlockRAM Usage 1 Additional Features Almost Full Empty Flags Not Selected Not Selected Programmable Full Empty Flags Not Selected Not Selected Data Count Outputs Not Selected Handshaking Not Selected Read Mode Standard FIFO Reset Asynchronous Consult Data Sheet for Performance Resource impact of each feature IP Symbol Figure 3 6 Summary Screen 38 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 XILINX Chapter 4 Designing with the Core This chapter describes the steps required to turn a FIFO Generator core into a fully functioning design integrated with the user application logic It is important to note that depending on the configuration of the FIFO core only a subset of the implementation details provided are applicable For successful use of a FIFO core the design guidelines discussed in this chapter must be observed General Design Guidelines Know the Degree of Difficulty A fully compliant and feature rich FIFO design is challenging to implement in any technology For this reason it is important to understand that the degree of difficulty can be significantly influenced by e Maximum system clock frequency e Targeted device architecture e Specific user application Ensure that design techniques are used to facilitate implementation including pipelining and u
41. Operation This section describes the behavior of a FIFO write operation and the associated status flags When write enable is asserted and the FIFO is not full data is added to the FIFO from the input bus DIN and write acknowledge WR_ACK is asserted If the FIFO is continuously written to without being read it fills with data Write operations are only successful when the FIFO is not full When the FIFO is full and a write is initiated the request is ignored the overflow flag is asserted and there is no change in the state of the FIFO overflowing the FIFO is non destructive ALMOST_FULL and FULL Flags Note The Virtex 5 and Virtex 4 built in FIFO does not support the ALMOST_FULL flag The almost full flag ALMOST_FULL indicates that only one more write can be performed before FULL is asserted This flag is active high and synchronous to the write clock WR_CLK The full flag FULL indicates that the FIFO is full and no more writes can be performed until data is read out This flag is active high and synchronous to the write clock WR_CLK If a write is initiated when FULL is asserted the write request is ignored and OVERFLOW is asserted Important For the Virtex 4 built in FIFO implementation the Full signal has an extra cycle of latency User Write Acknowledge to verify success or Programmable Full for an earlier indication FIFO Generator v3 3 User Guide www xilinx com 45 UG175 April 2 2007 XILINX Chapter 4 Designi
42. P core included in the latest IP Update on the Xilinx IP Center The core is free of charge and no license is required For detailed information about the core see www xilinx com xInx xebiz designResources ip_product_details jsp key FIFO_Generator Recommended Design Experience The FIFO Generator is a fully verified solution and can be used by all levels of design engineers Important When implementing a FIFO with independent write and read clocks special care must be taken to ensure the FIFO Generator is correctly used Synchronization Considerations page 39 provides important information to help ensure correct design configuration Similarly asynchronous designs should also be aware that the behavioral models are not cycle accurate across clock domains See Chapter 6 Simulating Your Design for details Technical Support For technical support visit www support xilinx com Questions are routed to a team of engineers with FIFO Generator expertise Xilinx will provide technical support for use of this product as described in the LogiCORE FIFO Generator User Guide Xilinx cannot guarantee timing functionality or support of this product for designs that do not follow these guidelines FIFO Generator v3 3 User Guide www xilinx com 15 UG175 April 2 2007 7 XILINX Feedback 16 Chapter 1 Introduction Xilinx welcomes comments and suggestions about the FIFO Generator and the documentation suppli
43. Programmable Full with Assert and Negate Thresholds Assert Set to 10 and Negate Set to7 0 0 eee eee 53 Figure 4 14 Programmable Empty with Single Threshold Threshold Set to 4 54 Figure 4 15 Programmable Empty with Assert and Negate Thresholds Assert Set to 7 and Negate Setto10 0 0 eee eee ee 55 Figure 4 16 Write and Read Data Counts for FIFO with Independent Clocks 57 Figure 4 17 1 4 Aspect Ratio Data Ordering 00 00 0 00 00008 58 Figure 4 18 1 4 Aspect Ratio Status Flag Behavior 00000008 59 Figure 4 19 4 1 Aspect Ratio Data Ordering 0 0 0 0 c eee eee ee 59 Figure 4 20 4 1 Aspect Ratio Status Flag Behavior 0000008 60 Figure 4 21 SBITERR and DBITERR Outputs in the FIFO Generator Core 61 Figure 4 22 Synchronous Reset FIFO with Independent Clock 62 Figure 4 23 Asynchronous Reset FIFO with Common Clock 62 Figure 4 24 Synchronous Reset FIFO with a Common Clock 63 FIFO Generator v3 3 User Guide www xilinx com UG175 April 2 2007 7 XILINX 8 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 Schedule of Tables Chapter 2 Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 2 7 Chapter 4 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4
44. Value 4095 Range 0 4096 Empty Threshold Negate Value 4095 Range 0 4096 IE IP Symbol View Data Sheet Page 4 of amp lt Back Next gt Einish Cancel Figure 3 4 Programmable Flags Screen Programmable Flags Programmable Full Type Select a programmable full threshold type from the drop down menu The valid range for each threshold is displayed and will vary depending on options selected elsewhere in the GUI Full Threshold Assert Value Available when Programmable Full with Single or Multiple Threshold Constants is selected Enter a user defined value or select a preset value from the drop down menu The valid range for this threshold is provided in the GUI When using a single threshold constant only the assert threshold value is used Full Threshold Negate Value Available when Programmable Full with Multiple Threshold Constants is selected Enter a user defined value or select a preset value from the drop down menu The valid range for this threshold is provided in the GUI FIFO Generator v3 3 User Guide www xilinx com 35 UG175 April 2 2007 7 XILINX Chapter 3 Generating the Core Programmable Empty Type Select a programmable empty threshold type from the drop down menu The valid range for each threshold is displayed and will vary depending on options selected elsewhere in the GUI Empty Threshold Assert Value Available when Programmable Empty with Single or Multiple Threshold Constants
45. a Count page 57 for details Write Data Count Available when an independent clocks FIFO with block RAM or distributed RAM is selected Valid range is from 1 to log write depth Read Data Count Available when an independent clocks FIFO with block RAM or distributed RAM is selected Valid range is from 1 to log read depth Data Count Available when a common clock FIFO with block RAM distributed RAM or shift registers is selected Valid range is from 1 to log of input depth Resets Dout Reset Value Available in Virtex II and newer architectures for all implementations using block RAM distributed RAM or shift register memory This text box indicates the hexidecimal value which is asserted on the output of the FIFO when RST is asserted Summary This screen summarizes the FIFO type dimensions and any additional features selected In the Additional Features section most features display either Not Selected if the feature is not used or Selected if the feature is used FIFO Generator v3 3 User Guide www xilinx com 37 UG175 April 2 2007 7 XILINX Chapter 3 Generating the Core Note Write depth and read depth provide the actual FIFO depths for the selected configuration These depths may differ slightly from the depth selected on page 2 of the FIFO GUI Fifo Generator v3 2 Fifo Generator v3 3 FIFO Generator Summary Selected FIFO Type Clocking Scheme Common Clock Memory Type Block RAM FIF
46. a Count i cerasi apare iaie e i i E E e en E Write Data Count saca a a First Word Fall Through Data Count 0 06 c eee eee eee Example Operation 6 0 c ccc tee ee Non symmetric Aspect Ratios 6 cece eee eee ee Built in Error Correction Checking oooooooocoooorrommm Reset Behavior 0 c ccc ce eee ae Asynchronous Reset leen Synchronous Reset lessen Chapter 5 Special Design Considerations Resetting the FIFO is ids ct Ce HR CERE EA HE Ce Ce ae aet Continuous Clocks eee to he hern Pessimistic Full and Empty 0 0 0 e cece eee Programmable Full and Empty 0 0 05 Write Data Count and Read Data Count Setup and Hold Time Violations 0 0 Chapter 6 Simulating Your Design Simulation Models use esee Appendix A Performance Information Resource Utilization and Performance Appendix B Core Parameters FIFO Parameters s esee RR n FIFO Generator v3 3 User Guide www xilinx com UG175 April 2 2007 XILINX 7 XILINX www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 Schedule of Figures Chapter 2 Core Overview Figure 2 1 FIFO with Independent Clocks Interface Signals 21 Chapter 3 Generating the Core Figure 3 1 Main FIFO Generator Screen 66 60 c ccc ccc c
47. ailable 2 The underflow signal is dependent on RD EN If RD EN is asserted and the FIFO is empty underflow is asserted 3 The overflow signal is dependent on WR EN If WR EN is asserted and the FIFO if full overflow is asserted 64 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 XILINX Chapter 5 Special Design Considerations This chapter provides additional design considerations for using the FIFO Generator core Resetting the FIFO The FIFO Generator must be reset after the FPGA is configured and before operation begins Two reset pins are available asynchronous RST and synchronous SRST and both clear the internal counters and output registers e For asynchronous reset internal to the core RST is synchronized to the clock domain in which it is used to ensure that the FIFO initializes to a known state This synchronization logic allows for proper reset timing of the core logic avoiding glitches and metastable behavior e For synchronous reset because the reset pin is synchronous to the input clock and there is only one clock domain in the FIFO no additional synchronization logic is needed The generated FIFO core will be initialized after reset to a known state For details about reset values and behavior see Reset Behavior in Chapter 4 of this guide Continuous Clocks The FIFO Generator is designed to work only with free running write and read clocks Xilinx does not re
48. cc cece eee 30 Figure 3 2 Performance Options and Data Port Parameters Screen 31 Figure 3 3 Optional Flags Handshaking and Initialization Options Screen 33 Figure 3 4 Programmable Flags Screen 0 0000s 35 Figure 3 5 Data Count and Reset Screen 2 0 66 36 Figure 3 6 Summary cree 37 Chapter 4 Designing with the Core Figure 4 1 FIFO with Independent Clocks Write and Read Clock Domains 40 Figure 4 2 Functional Implementation of a FIFO with Independent Clock Domains 41 Figure 4 3 Functional Implementation of Built in FIFO 00 43 Figure 4 4 Functional Implementation of a Common Clock FIFO using Block RAM or Distributed RAM 0 0 0 0 eee eee eens 44 Figure 4 5 Functional Implementation of a Common Clock FIFO using Shift Registers iiic ii COP EC ND EC RE 45 Figure 4 6 Write Operation for a FIFO with Independent Clocks 46 Figure 4 7 Standard Read Operation for a FIFO with Independent Clocks 48 Figure 4 8 FWFT Read Operation for a FIFO with Independent Clocks 48 Figure 4 9 Write and Read Operation for a FIFO with Common Clocks 49 Figure 4 10 Handshaking Signals for a FIFO with Independent Clocks 50 Figure 4 11 Handshaking Signals for a FIFO with Common Clocks 51 Figure 4 12 Programmable Full Single Threshold Threshold Setto7 53 Figure 4 13
49. commend controlling the core by manipulating RD_CLK and WR_CLK If this functionality is required to gate FIFO operation we recommend using the write enable WR_EN and read enable RD_EN signals Pessimistic Full and Empty When independent clock domains are selected the full flag FULL ALMOST_FULL and empty flag EMPTY ALMOST_EMPTY are pessimistic flags FULL and ALMOST_FULL are synchronous to the write clock WR_CLK domain while EMPTY and ALMOST_EMPTY are synchronous to the read clock RD_CLK domain The full flags are considered pessimistic flags because they assume that no read operations have taken place in the read clock domain ALMOST_FULL is guaranteed to be asserted on the rising edge of WR_CLK when there is only one available location in the FIFO and FULL is guaranteed to be asserted on the rising edge of WR_CLK when the FIFO is full There may be a number of clock cycles between a read operation and the deassertion of FULL The precise number of clock cycles for FULL to deassert is not predictable due to the crossing of clock domains and synchronization logic The EMPTY flags are considered pessimistic flags because they assume that no write operations have taken place in the write clock domain ALMOST_EMPTY is guaranteed to be FIFO Generator v3 3 User Guide www xilinx com 65 UG175 April 2 2007 XILINX Chapter 5 Special Design Considerations asserted on the rising edge of RD_CLK when there is only one more word i
50. d Table 4 3 details the supported implementations for FWFT Table 4 3 Implementation Specific Support for First Word Fall Through FIFO Implementation FWFT Support Block RAM v Independent Clocks Distributed RAM v Built in v Block RAM Distributed RAM Common eds Shift Register Built in y 1 Only supported in Virtex 5 built in FIFO Standard FIFO Read Operation For a standard FIFO read operation after read enable is asserted and if the FIFO is not empty the next data stored in the FIFO is driven on the output bus DOUT and the valid flag VALID is asserted Figure 4 7 shows a standard read access Once the user writes at least one word into the FIFO EMPTY is deasserted indicating data is available to be read The user asserts RD_EN causing a read operation to occur on the next rising edge of RD_CLK The FIFO outputs the next available word on DOUT and asserts VALID indicating a successful read operation When the last data word is read from the FIFO the FIFO asserts EMPTY If the user continues to assert RD_EN while EMPTY is asserted the read request is ignored VALID is deasserted and UNDERFLOW is asserted Once the user performs a write operation the FIFO deasserts EMPTY allowing the user to resume valid read operations as indicated by the assertion of VALID and deassertion of UNDERFLOW l l RD EN f t AA t 1 i I l I DOUT bo DC or X 0 X3 X853 VALI
51. deassert value is set to ten PROG_EMPTY is deasserted when there are more than ten words in the FIFO Once the FIFO contains less than or equal to the programmable empty negate value set to seven PROG_EMPTY is asserted Both read data count RD DATA COUNT and PROG EMPTY have one clock cycle of delay Lil PAPA PARA AAA eh l l I I RD_EN 1 I l l l l l l I I I GNE NNNM LL EE RES 2 O a in a ee ge mee I RD_DATA_COUNT jj 8 jf e Kioii uu w0 9 jJ 38 71 I I PROG EMPTY I l I Figure 4 15 Programmable Empty with Assert and Negate Thresholds Assert Set to 7 and Negate Set to 10 Programmable Empty for First Word Fall Through For FWFT FIFOs PROG_EMPTY is guaranteed to be asserted when the number of words in the FIFO is less than or equal to the programmable empty assert threshold Under certain conditions it is possible for PROG_EMPTY to violate this rule but only while EMPTY is asserted PROG_EMPTY should be assumed to be asserted whenever EMPTY is asserted Data Counts DATA_COUNT tracks the number of words in the FIFO You can specify the width of the data count bus with a maximum width of log2 FIFO depth If the width specified is smaller than the maximum allowable width the bus is truncated by removing the lower FIFO Generator v3 3 User Guide www xilinx com 55 UG175 April 2 2007 7 XILINX 56 Chapter 4 Designing with the Core bits These signals a
52. e UG175 April 2 2007 www xilinx com 25 XILINX Chapter 2 Core Overview Interface Signals FIFOs with Common Clock 26 Table 2 7 defines the interface signals of a FIFO with a common write and read clock The table is divided into standard and optional interface signals and all signals except reset are synchronous to the common clock CLK Users have the option to select synchronous or asynchronous reset for the distributed or block RAM FIFO implementation Table 2 7 Interface Signals for FIFOs with a Common Clock Name Direction Required Description RST Input Reset An asynchronous reset that initializes all internal pointers and output registers SRST Input Synchronous Reset A synchronous reset that initializes all internal pointers and output registers CLK Input Clock All signals on the write and read domains are synchronous to this clock DIN N 0 Input Data Input The input data bus used when writing the FIFO WR_EN Input Write Enable If the FIFO is not full asserting this signal causes data on DIN to be written to the FIFO FULL Output Full Flag When asserted this signal indicates that the FIFO is full Write requests are ignored when the FIFO is full initiating a write when the FIFO is full is non destructive to the contents of the FIFO DOUT M 0 Output Data Output The output data bus driven when reading the FI
53. e false false Write Data Count Width Integer in range 1 to log input depth 10 Data Count true false false Performance Options First_Word_Fall_Through Standard_Fifo Standard_Fifo Read Latency integer range 0 to 1 1 Reset Pin true false true 1 User customized core should not exceed the number of shift registers built in FIFOs block RAM or distributed RAM primitives avail able in the targeted architecture It is the user s responsibility to know the resource availability in the targeted device 74 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007
54. e FIFO is full Overflowing the FIFO is non destructive to the contents of the FIFO PROG_FULL_THRESH Input Programmable Full Threshold This signal is used to set the threshold value for the assertion and deassertion of the programmable full flag PROG_FULL The threshold can be dynamically set in circuit during reset The user can either choose to set the assert and negate threshold to the same value using PROG_FULL_THRESH or the user can control these values independently using PROG FULL THRESH ASSERT and PROG FULL THRESH NEGATE ASSERT PROG FULL THRESH Input Programmable Full Threshold Assert This signalis used to set the upper threshold value for the programmable full flag which defines when the signal is asserted The threshold can be dynamically set in circuit during reset NEGATE PROG FULL THRESH Input Programmable Full Threshold Negate This signal is used to set the lower threshold value for the programmable full flag which defines when the signal is deasserted The threshold can be dynamically set in circuit during reset ALMOST EMPTY Output Almost Empty Flag When asserted this signal indicates that the FIFO is almost empty and one word remains in the FIFO PROG EMPTY Output Programmable Empty This signal is asserted after the number of words in the FIFO is less than or equal to the programmable threshold Itis deasserted when the number of word
55. e clock domains and are summarized in Table 4 2 Table 4 2 Interface Signals and Corresponding Clock Domains WR_CLK RD_CLK DIN DOUT WR_EN RD_EN FULL EMPTY PROG_FULL PROG_EMPTY WR_ACK VALID OVERFLOW UNDERFLOW N A SBITERR N A DBITERR For FIFO cores using independent clocks the timing relationship between the write and read operations and the status flags is affected by the relationship of the two clocks For example the timing between writing to an empty FIFO and the deassertion of EMPTY is determined by the phase and frequency relationship between the write and read clocks For additional information see Synchronization Considerations page 39 For Virtex 5 built in FIFO configuration the built in ECC feature in the FIFO macro is provided For more information see Built in Error Correction Checking page 60 FIFO Generator v3 3 User Guide www xilinx com 43 UG175 April 2 2007 7 XILINX Chapter 4 Designing with the Core Common Clock Built in FIFO The FIFO Generator supports FIFO cores using the built in FIFO primitive with a common clock This provides users the ability to use the built in FIFO while requiring only a single clock interface The behavior of the common clock configuration with built in FIFO is identical to the independent clock configuration with built in FIFO except all operations are in relation to the common clock CLK See Independent Clocks Built in F
56. e following when using the WR DATA COUNT or RD DATA COUNT ports e TheWR DATA COUNT and RD DATA COUNT outputs are not an instantaneous representation of the number of words in the FIFO but can instantaneously provide an approximation of the number of words in the FIFO e WR DATA COUNT and RD DATA COUNT may skip values from clock cycle to clock cycle e Using non symmetric aspect ratios or running clocks which vary dramatically in frequency will increase the disparity between the data count outputs and the actual number of words in the FIFO Note The WR DATA COUNT and RD DATA COUNT outputs will always be correct after some period of time where RD EN20 and WR EN O generally just a few clock cycles after read and write activity stops See Data Counts in Chapter 4 of this guide for details about the latency and behavior of the data count flags Setup and Hold Time Violations 66 When generating a FIFO with independent clock domains the core internally synchronizes the write and read clock domains For this reason setup and hold time violations are expected on certain registers within the core In simulation warning messages may be issued indicating these violations If these warning messages are from the FIFO Generator core they can be safely ignored The core is designed to properly handle these conditions regardless of the phase or frequency relationship between the write and read clocks www xilinx com FIFO Generator
57. e optional status flags and set the handshaking options Fifo Generator v3 2 Fifo Generator v3 3 Optional Flags Almost Full Flag Almost Empty Flag Handshaking Options Write Port Handshaking Write Acknowledge Overtlow write Error Write Acknowledge Flag Overflow Flag Active High Active High Active Low Active Low Read Port Handshaking Valid Read Acknowledge Underflow Read Error O Valid Flag C Underflow Flag Active High Active High Active Low Active Low Initialization v Reset Pin Asynchronous Reset Synchronous Reset IP Symbol Figure 3 3 Optional Flags Handshaking and Initialization Options Screen Optional Flags Almost Full Flag Available in all FIFO implementations except those using Virtex 5 or Virtex 4 built in FIFOs Generates an output port that indicates the FIFO is almost full only one more word can be written Almost Empty Flag Available in all FIFO implementations except in those using Virtex 5 or Virtex 4 built in FIFOs Generates an output port that indicates the FIFO is almost empty only one more word can be read Write Port Handshaking Write Acknowledge Generates write acknowledge flag which reports the status of a write operation This signal can be configured to be active high or low default active high FIFO Generator v3 3 User Guide www xilinx com 33 UG175 April 2 2007 7 XILINX Chapter 3
58. ed with the core FIFO Generator For comments or suggestions about the FIFO Generator please submit a WebCase from www support xilinx com Be sure to include the following information Document Product name Core version number Explanation of your comments For comments or suggestions about this document please submit a WebCase from www support xilinx com Be sure to include the following information Document title Document number Page number s to which your comments refer Explanation of your comments www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 XILINX Chapter 2 Core Overview This chapter provides an overview of the FIFO Generator configuration options and interfaces System Overview Clock Implementation Operation The FIFO Generator enables FIFOs to be configured with either independent or common clock domains for write and read operations The independent clock configuration of the FIFO Generator enables the user to implement unique clock domains on the write and read ports The FIFO Generator handles the synchronization between clock domains placing no requirements on phase and frequency relationships between clocks A common clock domain implementation optimizes the core for data buffering within a single clock domain Built in FIFO Support in Virtex 5 The FIFO Generator supports the Virtex 5 built in FIFO modules enabling large FIFOs to be created by cascading the b
59. ented with block RAM that are configured to have independent write and read clocks Core Configuration and Implementation 18 Table 2 2 provides a summary of the supported memory and clock configurations Table 2 2 FIFO Configurations Clock Domain Memory Type Configuration Aspectiatios Fall Through Common Block RAM v Common Distributed RAM v Common Shift Register v Common Built in FIFO v v FIFO Generator v3 3 User Guide UG175 April 2 2007 www xilinx com Core Configuration and Implementation XILINX Table 2 2 FIFO Configurations Continued Supported Non symmetric First Word Configuration Aspect Ratios Fall Through Clock Domain Memory Type Independent Block RAM v v v Independent Distributed RAM v v Independent Built in FIFO v v 1 The built in FIFO primitive is only available in Virtex 5 and Virtex 4 architectures 2 Only valid in Virtex 5 built in FIFO primitives Independent Clocks Block RAM and Distributed RAM This implementation category allows the user to select block RAM or distributed RAM and supports independent clock domains for write and read data accesses Operations in the read domain are synchronous to the read clock and operations in the write domain are synchronous to the write clock The feature set supported for this type of FIFO includes non symmetric aspect ratios different write and read port widths status flags
60. ese values can only be changed by re generating the core This option consumes fewer resources than the assert and negate thresholds with dedicated input ports e Assert and negate thresholds with dedicated input ports User specifies the threshold values through input ports on the core These input ports can be changed while the FIFO is in reset providing the user the flexibility to change the values of the programmable full assert PROG FULL THRESH ASSERT and negate PROG FULL THRESH NEGATE thresholds in circuit without re generating the core Note The full assert value must be larger than the full negate value Refer to the CORE Generator GUI for valid ranges for each threshold Figure 4 13 shows the programmable full flag with assert and negate thresholds The user writes to the FIFO until there are 10 words in the FIFO Because the assert threshold is set to 10 the FIFO then asserts PROG FULL The negate threshold is set to seven and the FIFO deasserts PROG FULL once six words or fewer are in the FIFO Both write data count WR DATA COUNT and PROG FULL have one clock cycle of delay WR EN WR ACK WR DATA COUNT Figure 4 13 Programmable Full with Assert and Negate Thresholds Assert Set to 10 PROG FULL and Negate Set to 7 Programmable Empty The FIFO Generator supports four ways to define the programmable empty thresholds FIFO Generator v3 3 User Guide UG175 April 2 2007 www xilinx com 53 7 XILINX
61. ew functionality provides low latency access to data This is ideal for applications that require throttling based on the contents of the data that are read See Table 2 2 for FWFT availability The use of this feature impacts the behavior of many other features such as e Read operations see First Word Fall Through FIFO Read Operation page 48 e Programmable empty see Programmable Empty for First Word Fall Through page 55 e Data counts see First Word Fall Through Data Count page 57 Memory Types The FIFO Generator implements FIFOs built from block RAM distributed RAM shift registers or the Virtex 4 and Virtex 5 built in FIFOs The core combines memory primitives in an optimal configuration based on the selected width and depth of the FIFO Table 2 1 provides best use recommendations for specific design requirements Table 2 1 Memory Configuration Benefits Independent Common Small medium High Minimal Large Clocks Clock Buffering Performance Resources Buffering Built in v v v v v FIFO Block RAM v v v v v Shift v v v Register Distributed v v v v RAM Non Symmetric Aspect Ratio The core supports generating FIFOs whose write and read ports have different widths enabling automatic width conversion of the data width Non symmetric aspect ratios ranging from 1 8 to 8 1 are supported for the write and read port widths This feature is available for FIFOs implem
62. gh or active low through the CORE Generator GUI see Handshaking Options in Chapter 4 for more information These flags configured as active high are illustrated in Figure 4 10 Write Acknowledge The write acknowledge flag WR ACK is asserted at the completion of each successful write operation and indicates that the data on the DIN port has been stored in the FIFO This flag is synchronous to the write clock WR CLK Valid The operation of the valid flag VALID is dependent on the read mode of the FIFO This flag is synchronous to the read clock RD CLK Standard FIFO Read Operation For standard read operation the VALID flag is asserted at the rising edge of RD CLK for each successful read operation and indicates that the data on the DOUT bus is valid When a read request is unsuccessful when the FIFO is empty VALID is not asserted FWFT FIFO Read Operation For FWFT read operation the VALID flag indicates the data on the output bus DOUT is valid for the current cycle A read request does not have to happen for data to be present and valid as the first word fall through logic automatically places the next data to be read on the DOUT bus VALID is asserted if there is one or more words in the FIFO VALID is deasserted when there are no more words in the FIFO Example Operation Figure 4 10 illustrates the behavior of the FIFO flags On the write interface FULL is not asserted and writes to the FIFO are successful as
63. havior of the status flags will differ from the actual implementation of the FIFO design To generate behavioral models select Behavioral and VHDL or Verilog in the Xilinx CORE Generator project options Behavioral models are the default project options The following considerations apply to the behavioral models e Write operations always occur relative to the write clock WR CLK or common clock CLK domain as do the corresponding handshaking signals e Read operations always occur relative to the read clock RD CLK or common clock CLK domain as do the corresponding handshaking signals The delay through the FIFO write to read latency will differ between the VHDL model the Verilog model and the core The deassertion of the status flags full almost full programmable full empty almost FIFO Generator v3 3 User Guide www xilinx com 67 UG175 April 2 2007 XILINX 68 Chapter 6 Simulating Your Design empty programmable empty will vary between the VHDL model the Verilog model and the core Note If independent clocks or common clocks with built in FIFO is selected it is strongly recommended to use the structural model as the behavioral model does not correctly model the behavior of the status flags full programmable full empty and programmable empty Structural Models The structural models are designed to provide a more accurate model of FIFO behavior at the cost of simulation time These models w
64. he state of the FIFO it is non destructive 50 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 FIFO Usage and Control XILINX Overflow The overflow flag OVERFLOW is used to indicate that a write operation is unsuccessful This flag is asserted when a write is initiated to the FIFO while FULL is asserted The overflow flag is synchronous to the write clock WR_CLK Overflowing the FIFO does not change the state of the FIFO it is non destructive Example Operation Figure 4 11 illustrates the Handshaking flags On the write interface FULL is deasserted and therefore writes to the FIFO are successful indicated by the assertion of WR_ACK When a write occurs after FULL is asserted WR_ACK is deasserted and OVERFLOW is asserted indicating an overflow condition On the read interface once the FIFO is not EMPTY the FIFO accepts read requests Following a read request VALID is asserted and DOUT is updated When a read request is issued while EMPTY is asserted VALID is deasserted and UNDERFLOW is asserted indicating an underflow condition Write Interface T IMn I l l WREN IJ t tH oa oe l l l DIN iX D X o2 X o X X wR Ack Ji t t h A h l l l l l l I l I FULL yA 4 I I OVERFLOW l l l H Read Interface l l l i 1 l l l l CLK RD EN i l dup 1 i l DOUT EMPTY l l l l l I i l UNDERFLOW y l l l l l l y I I I l I I LI I Figure 4
65. hreshold value for the programmable empty flag which defines when the signal is deasserted The threshold can be dynamically set in circuit during reset SBITERR Output Single Bit Error Indicates that the ECC decoder detected and fixed a single bit error on a Virtex 5 built in FIFO macro See Built in Error Correction Checking page 60 DBITERR Output Double Bit Error Indicates that the ECC decoder detected a double bit error on a Virtex 5 built in FIFO macro and data in the FIFO core is corrupted See Built in Error Correction Checking page 60 28 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 XILINX Chapter 3 Generating the Core This chapter contains information and instructions for using the Xilinx CORE Generator system to customize the FIFO Generator CORE Generator Graphical User Interface The FIFO Generator GUI includes six configuration screens FIFO Implementation Performance Options and Data Port Parameters Optional Flags and Handshaking Options Programmable Flags e Data Count and Reset e Summary FIFO Generator v3 3 User Guide www xilinx com 29 UG175 April 2 2007 7 XILINX Chapter 3 Generating the Core FIFO Implementation The main FIFO Generator screen is used to define the component name and provides configuration options for the core Fifo Generator v3 3 ES lagiC PE Fifo Generator v3 3 F
66. ications Xilinx specifically disclaims any express or implied warranties of fitness for such High Risk Applications You represent that use of the Design in such High Risk Applications is fully at your risk 2007 Xilinx Inc All rights reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc All other trademarks are the property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 04 28 05 1 1 Initial Xilinx release 8 31 05 2 0 Updated guide for release v2 2 added SP3 to ISEv7 1i incorporated edits from engineering specific for this release including FWFT and Built in FIFO flags etc 1 11 06 3 0 Updated for v2 3 release ISE v8 1i 7 13 06 4 0 Added Virtex 5 support reorganized Chapter 5 added ISE v8 2i version to 3 1 9 21 06 5 0 Core version updated to v3 2 support added for Spartan 3A 2 15 07 6 0 Core version updated to 3 3 Xilinx tools updated to 9 1i 4 02 07 6 5 Added support for Spartan 3A DSP devices FIFO Generator v3 3 User Guide www xilinx com UG175 April 2 2007 Table of Contents Preface About This Guide Guide Contents aa 11 Additional Resources ccc cece cece e 12 Conventions usse res 12 Typographical iederien RR Een HIR ee RR Eee bic beds p cel s 12 Online Document e rr res 13 Chapter 1 Introduc
67. ill provide a closer approximation of cycle accuracy across clock domains for asynchronous FIFOs No asynchronous FIFO model can be 100 cycle accurate as physical relationships between the clock domains including temperature process and frequency relationships affect the domain crossing indeterminately To generate structural models select Structural and VHDL or Verilog in the Xilinx CORE Generator project options Note Simulation performance may be impacted when simulating the structural models compared to the behavioral models www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 XILINX Appendix A Performance Information Resource Utilization and Performance Performance and resource utilization for a FIFO varies depending on the configuration and features selected when customizing the core The tables below provide example FIFO configurations and the maximum performance and resources required Table A 1 provides results for a FIFO configured without optional features The benchmarks were performed using Virtex II 2v3000 Virtex 4 4vlx15 11 and Virtex 5 5v1x50 2 target devices Table A 1 Benchmarks FIFO Configured without Optional Features Resources Depth x F Performance FIFO Type Famil ietri di Width MHz LUTs FFs BlockRAM M Distributed Register RAM Virtex 5 350 MHz 62 45 1 0 0 Synchronous FIFO 512 x
68. indicated by the assertion of WR ACK When a write occurs after FULL is asserted WR ACK is deasserted and OVERFLOW is asserted indicating an overflow condition On the read interface once the FIFO is not EMPTY the FIFO accepts read requests In standard FIFO operation VALID is asserted and FIFO Generator v3 3 User Guide www xilinx com 49 UG175 April 2 2007 7 XILINX Chapter 4 Designing with the Core DOUT is updated on the clock cycle following the read request In FWFT operation VALID is asserted and DOUT is updated prior to a read request being issued When a read request is issued while EMPTY is asserted VALID is deasserted and UNDERFLOW is asserted indicating an underflow condition Write Interface l l DIN X DI X D2 X D3 XN l I l l l l FULL l l OVERFLOW l l l l 1 i Standard Read Interface l l l J l l l HQ Nee O A l l l l l ROJEN l l l l l I l I l Nain i l I l i l I l DOUT i i i I EMPTY i I l I UNDERFLOW l l l l l l l RD_CLK 1 l l l l l l piti EN l l l l l m i l i l l l l l DOUT l l I l l EMPTY I I i I UNDERFLOW l l l y l l l i Figure 4 10 Handshaking Signals for a FIFO with Independent Clocks Underflow The underflow flag UNDERFLOW is used to indicate that a read operation is unsuccessful This occurs when a read is initiated and the FIFO is empty This flag is synchronous with the read clock RD_CLK Underflowing the FIFO does not change t
69. ion MSB LSB 01 01 OOOO 00 01 00 Time 11 01 00 11 10 gt 01 00 11 10 Figure 4 17 1 4 Aspect Ratio Data Ordering 58 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 FIFO Usage and Control XILINX Figure 4 18 shows DIN DOUT and the handshaking signals for a FIFO with a 1 4 aspect ratio After four words are written into the FIFO EMPTY is deasserted Then after a single read operation EMPTY is asserted again DOUTI7 0 CAE l EMPTY l l l l n 1 l l l H l l l l l Figure 4 18 1 4 Aspect Ratio Status Flag Behavior Figure 4 19 shows a FIFO with an aspect ratio of 4 1 write width of 8 read width of 2 In this example a single write operation is performed after which four read operations are executed The write operation is 11_00_01_11 When a read operation is performed the data is received left to right MSB to LSB As shown the first read results in data of 11 followed by 00 01 and then 11 Write Read Operation Operation MSB LSB 11 00 O1 11 00 01 11 11 01 11 00 Time 11 gt 01 gt 11 Figure 4 19 4 1 Aspect Ratio Data Ordering FIFO Generator v3 3 User Guide www xilinx com 59 UG175 April 2 2007 7 XILINX Chapter 4 Designing with the Core Figure 4 20 shows DIN DOUT and the handshaking signals f
70. ion e 45524943h An _n means the signal is active low usr teof nisactive low Online Document The following linking conventions are used in this document Convention Blue text Meaning or Use Cross reference link to a location in the current document Example See the section Additional Resources for details See Title Formats in Chapter 1 for details Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest speed files FIFO Generator v3 3 User Guide UG175 April 2 2007 www xilinx com 13 XILINX Chapter About This Guide 14 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 XILINX Chapter 1 Introduction The FIFO Generator core a fully verified first in first out memory queue for use in any application requiring in order storage and retrieval enables high performance and area optimized designs This core can be customized using the Xilinx CORE Generator system as a complete solution with control logic already implemented including management of the read and write pointers and the generation of status flags This chapter introduces the FIFO Generator and provides related information including recommended design experience additional resources technical support and submitting feedback to Xilinx About the Core The FIFO Generator is a Xilinx CORE Generator I
71. lly set in circuit during reset PROG FULL THRESH Input Programmable Full Threshold Negate This signal is used to set the lower threshold value for the programmable full flag which defines when the signal is deasserted The threshold can be dynamically set in circuit during reset Table 2 6 defines the signals on the read interface of a FIFO with independent clocks The read interface signals are divided into required signals and optional signals and all signals are synchronous to the read clock RD CLK Table 2 6 Read Interface Signals for FIFOs with Independent Clocks Name Direction Description Required RD CLK Input Read Clock All signals on the read domain are synchronous to this clock DOUT M 0 Output Data Output The output data bus is driven when reading the FIFO RD EN Input Read Enable If the FIFO is not empty asserting this signal causes data to be read from the FIFO output on DOUT EMPTY Output Empty Flag When asserted this signal indicates that the FIFO is empty Read requests are ignored when the FIFO is empty initiating a read while empty is non destructive to the FIFO Optional ALMOST EMPTY Output Almost Empty Flag When asserted this signal indicates that the FIFO is almost empty and one word remains in the FIFO FIFO Generator v3 3 User Guide UG175 April 2 2007 www xilinx com 23 7 XILINX Chapter 2 C
72. n occurs on the third rising clock edge and is not reflected on WR_DATA_COUNT until the next full clock cycle is complete Similarly RD_DATA_COUNT transitions one full clock cycle after a successful read operation Write Interface wa a ES sane J l l l J ween I l l l l i l l l WR_DATA_COUNT 12 15 ET l l l A l l l Read Interface Roue A XL OF AF Rod NOE NCC NN i mp EN L 3 1 i RD DATA COUNT 3 0 empty I l l l l l l Figure 4 16 Write and Read Data Counts for FIFO with Independent Clocks FIFO Generator v3 3 User Guide www xilinx com 57 UG175 April 2 2007 XILINX Chapter 4 Designing with the Core Non symmetric Aspect Ratios Table 4 5 identifies the FWFT support for non symmetric aspect ratios Table 4 5 Implementation specific Support for Non symmetric Aspect Ratios FIFO Implementation FWFT Support Block RAM v Independent Clocks Distributed RAM Built in Block RAM Common Clock Distributed RAM Shift Register Built in This feature is supported for FIFOs configured with independent clocks implemented with block RAM Non symmetric aspect ratios allow the input and output depths of the FIFO to be different The following write to read aspect ratios are supported 1 8 1 4 1 2 1 1 2 1 4 1 8 1 This feature is enabled by selecting unique write and read widths when customizing the FIFO using the CORE Generator By default the
73. n the FIFO and EMPTY is guaranteed to be asserted on the rising edge of RD_CLK when the FIFO is empty There may be a number of clock cycles between a write operation and the deassertion of EMPTY The precise number of clock cycles for EMPTY to deassert is not predictable due to the crossing of clock domains and synchronization logic See Chapter 4 Designing with the Core for detailed information about the latency and behavior of the full and empty flags Programmable Full and Empty The programmable full PROG_FULL and programmable empty PROG_EMPTY flags provide the user flexibility in specifying when the programmable flags assert and deassert These flags can be set either by constant value s or by input port s These signals differ from the full and empty flags because they assert one or more clock cycle after the assert threshold has been reached These signals are deasserted some time after the negate threshold has been passed In this way PROG_EMPTY and PROG FULL are also considered pessimistic flags See Programmable Flags in Chapter 4 of this guide for more information about the latency and behavior of the programmable flags Write Data Count and Read Data Count When independent clock domains are selected write data count WR_DATA_COUNT and read data count RD_DATA_COUNT signals are provided as an indication of the number of words in the FIFO relative to the write or read clock domains respectively Consider th
74. nd Control XILINX Programmable Empty Assert and Negate Thresholds This option enables the user to set separate values for the assertion and deassertion of PROG_EMPTY When the number of entries in the FIFO is less than or equal to the assert value PROG_EMPTY is asserted When the number of entries in the FIFO is greater than the negate value PROG_EMPTY is deasserted There are two options for implementing the assert and negate thresholds e Assert and negate threshold constants The threshold values are specified through the CORE Generator GUI Once the core is generated these values can only be changed by re generating the core This option consumes fewer resources than the assert and negate thresholds with dedicated input ports e Assert and negate thresholds with dedicated input ports The threshold values are specified through input ports on the core These input ports can be changed while the FIFO is in reset providing the user the flexibility to change the values of the programmable empty assert PROG EMPTY THRESH ASSERT and negate PROG EMPTY THRESH NEGATE thresholds in circuit without regenerating the core Note The empty assert value must be less than the empty negate value Refer to the CORE Generator GUI for valid ranges for each threshold Figure 4 15 shows the programmable empty flag with assert and negate thresholds The user writes to the FIFO until there are eleven words in the FIFO Since the programmable empty
75. ng with the Core Example Operation Figure 4 6 shows a typical write operation The user asserts WR_EN causing a write operation to occur on the next rising edge of the WR_CLK Since the FIFO is not full WR_ACK is asserted acknowledging a successful write operation When only one additional word can be written into the FIFO the FIFO asserts the ALMOST_FULL flag When ALMOST_FULL is asserted one additional write causes the FIFO to assert FULL When a write occurs after FULL is asserted WR_ACK is deasserted and OVERFLOW is asserted indicating an overflow condition Once the user performs one or more read operations the FIFO deasserts FULL and data can successfully be written to the FIFO as is indicated by the assertion of WR_ACK and deassertion of OVERFLOW Note The Virtex 4 built in FIFO implementation shows an extra cycle of latency on the FULL flag LANAS DIN ALMOST_FULL AA A a WRACK YO OVERFLOW J Figure 4 6 Write Operation for a FIFO with Independent Clocks Read Operation This section describes the behavior of a FIFO read operation and the associated status flags When read enable is asserted and the FIFO is not empty data is read from the FIFO on the output bus DOUT and the valid flag VALID is asserted If the FIFO is continuously read without being written the FIFO empties Read operations are successful when the FIFO is not empty When the FIFO is empty and a read is requested the read
76. of clock cycles before being reflected in the Rb DATA COUNT Write Data Count Write data count WR DATA COUNT pessimistically reports the number of words written into the FIFO The count is guaranteed to never under report the number of words in the FIFO although it may temporarily over report the number of words present to ensure that the user never overflows the FIFO The user can specify the width of the write data count bus with a maximum width of log2 write depth If the width specified is smaller than the maximum allowable width the bus is truncated with the lower bits removed For example you can only use two bits out of a maximum allowable three bits provided a FIFO depth of eight These two bits indicate the number of words in the FIFO with a quarter resolution This provides a status of the contents of the FIFO for the write clock domain Note f a write operation occurs on a rising clock edge of wR crx that write will be reflected on the WR DATA COUNT signal following the next rising clock edge A read operation which occurs on the RD CLK Clock domain may take a number of clock cycles before being reflected in the WR DATA COUNT www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 FIFO Usage and Control XILINX First Word Fall Through Data Count By providing the capability to read the next data word before requesting it FWFT implementations increase the depth of the FIFO This depth increase cau
77. ollowing the release of SRST CLK Be eet a a ae as E SRST I FULL POS ALMOST_FULL 509990 PROG FULL 00001 Figure 4 24 Synchronous Reset FIFO with a Common Clock Table 4 7 defines the values of the output ports during power up and the reset state DOUT reset value is supported for all architectures with the exception of Virtex and Spartan II If the user does not specify a DOUT reset value it defaults to 0 The FIFO requires a reset pulse of only 1 clock cycle The FIFOs are available for transaction on the clock cycle after FIFO Generator v3 3 User Guide www xilinx com 63 UG175 April 2 2007 7 XILINX Chapter 4 Designing with the Core the reset is released The power up values for the synchronous reset are the same as the reset state Table 4 7 FIFO Reset and Power up Values Block Memory and Signal Distributed Memory Values of Output Ports During Reset and Power up DOUT DOUT Reset Value or 0 FULL 0 ALMOST FULL 0 EMPTY 1 ALMOST EMPTY 1 VALID 0 active high or 1 active low UNDERFLOW 0 active high or 1 active low WR ACK 0 active high or 1 active low OVERFLOW 0 active high or 1 active low PROG FULL 0 PROG EMPTY 0 RD DATA COUNT 0 WR DATA COUNT 0 1 The ability to set DOUT to a user defined value is not available for block RAM implementations in Virtex Spartan ll and Spartan IIE DOUT resets to 0 when this feature is unav
78. onization Considerations 6 6 en 39 Initializing the FIFO Generators iesu dies cas deed redada 40 FIFO Implementations redet ECC EeEE CIE ERI CER een e d 41 Independent Clocks Block RAM and Distributed RAM ooo o o ococccccoo 41 Independent Clocks Built in FIFO 0 6 66 42 Common Clock Built in FIFO 0 0 0 6 6 eee eee eee 44 Common Clock FIFO Block RAM and Distributed RAM ooooooocooomoooo 44 Common Clock FIFO Shift Registers ssssss e 44 FIFO Usage and Control cerit ERECTO COR bei 45 Witte OperatiOn sss xeesmte rcp ERE QUE Da Ee STi pda spa d eaten pietra 45 ALMOST FULLand FULLFlags see I 45 Example Operation cyssegru deyas eek p E ea E EE RR eT EY des 46 Read Operation coss toL cpccUp NM UL LN EA toe 46 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 ALMOST_EMPTY and EMPTY Flags 0 2 0 000s eee eee Modes of Read Operation llle Handshaking Flags siessetek bpi trii or eens Write Acknowledge cat nid aE N EEE EE E ee Valid 522a avete x a a a bal nae gees a Example Operation 6 esses ne Undertlow gt 0er x Sia tds e ne Ru OvertflOW 3 hes eh aoe ad tele bee RAR E deca A da Example Operations see esed suus Rr arb e EAR rede a Programmable Flags 0 0000 e eee eee Programmable Full srece 6 cece eee eens Programmable Empty esee Data Counts uode pr ek peed eet oe bale eet pere aye kinds Read Dat
79. or a FIFO with an aspect ratio of 4 1 After a single write the FIFO deasserts EMPTY Since no other writes occur the FIFO reasserts empty after four reads l l l l EMPTY l l l l l l l l l l l l I Figure 4 20 4 1 Aspect Ratio Status Flag Behavior Built in Error Correction Checking 60 Built in ECC is supported for FIFOs configured with independent or common clock built in FIFOs targeting Virtex 5 When ECC is enabled the built in FIFO primitive used to create the FIFO is configured in the full ECC mode both encoder and decoder enabled providing two additional outputs to the FIFO Generator core SBITERR and DBITERR These outputs indicate three possible read results no error single error corrected and double error detected In the full ECC mode the read operation does not correct the single error in the memory array it only presents corrected data on DOUT Figure 4 21 shows how the SBITERR and DBITERR outputs are generated in the FIFO Generator core The output signals are created by combining all the SBITERR and DBITERR signals from the FIFO primitives using an OR gate Because the FIFO primitives may be cascaded in depth when SBITERR or DBITERR is asserted the error may have occurred in any of the built in FIFO macros chained in depth Hence these flags are not correlated to the data currently being read from the FIFO Generator core or to a read operation For this reason when the DBITERR is flagged the user should as
80. ore Overview Table 2 6 Read Interface Signals for FIFOs with Independent Clocks Continued Name Direction Description PROG_EMPTY Output Programmable Empty This signal is asserted when the number of words in the FIFO is less than or equal to the programmable threshold It is deasserted when the number of words in the FIFO exceeds the programmable threshold RD_DATA_COUNT C 0 Output Read Data Count This bus indicates the number of words available for reading in the FIFO The count is guaranteed to never over report the number of words available for reading to ensure that the user does not underflow the FIFO The exception to this behavior is when the read operation occurs at the rising edge of RD_CLK that read operation will only be reflected on RD_DATA_COUNT at the next rising clock edge If C is less than log2 FIFO depth 1 the bus is truncated by removing the least significant bits VALID Output Valid This signal indicates that valid data is available on the output bus DOUT UNDERFLOW Output Underflow Indicates that the read request RD_EN during the previous clock cycle was rejected because the FIFO is empty Underflowing the FIFO is not destructive to the FIFO PROG_EMPTY_THRESH Input Programmable Empty Threshold This signal is used to input the threshold value for the assertion and deassertion of the programmable empty PROG_EMPTY flag The threshold can be dynamically set in circuit during reset
81. quired and the input pin is optional For these FIFO configurations users have the option of asynchronous or synchronous reset only in common clock implementations When asynchronous reset is implemented it is synchronized to the clock domain in which it is used to ensure that the FIFO initializes to a known state This synchronization logic allows for proper reset timing of the core logic avoiding glitches and metastable behavior For independent clock implementations the synchronization process mandates a 3 cycle delay post reset prior to writing to the FIFO For common clock implementations a 2 cycle delay post reset prior to writing to the FIFO is mandated For synchronous reset no additional www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 FIFO Implementations XILINX synchronization is required and the FIFO is available for writing in the next cycle after reset FIFO Implementations Each FIFO configuration has a set of allowable features as defined in Table 2 3 page 20 Independent Clocks Block RAM and Distributed RAM Figure 4 2 illustrates the functional implementation of a FIFO configured with independent clocks This implementation uses block RAM or distributed RAM for memory counters for write and read pointers conversions between binary and Gray code for synchronization across clock domains and logic for calculating the status flags WRITE CLOCK DOMAIN READ CLOCK DOMAIN EMPTY ALMOST_EMPTY
82. r Programmable Flags 768 Full Threshold Negate Value See range under Programmable Flags page 51 768 FIFO Generator v3 3 User Guide www xilinx com UG175 April 2 2007 73 XILINX Appendix B Core Parameters Table B 1 FIFO Parameter Table Continued Parameter Name Programmable Empty Type XCO File Values No_Programmable_Empty_Threshold Sigle_Programmable_Empty_Threshold_Constant Multiple_Programmable_Empty_Threshold_Constants Single_Programmable_Empty_Threshold_Input_Port Multiple_Programmable_Empty_Threshold_Input_Ports Default GUI Setting No_Programmable_Empty_Threshold Empty Threshold Assert Value See range under Programmable Flags page 51 256 Empty Threshold Negate Value See range under Programmable Flags page 51 256 Write Acknowledge Flag true false false Write Acknowledge Sense Active_High Active_Low Active_High Overflow Flag true false false Overflow Sense Active_High Active_Low Active_High Valid Flag true false false Valid Sense Active_High Active_Low Active_High Underflow Flag true false false Underflow Sense Active_High Active_Low Active_High Dout Reset Value Hex value in range of 0 to output data width 1 0 Primitive Depth 512 1024 2048 4096 1024 Read Data Count true false false Read Data Count Width Integer in range 1 to log output depth 10 Write Data Count tru
83. re optional outputs of the FIFO Generator and are enabled through the CORE Generator GUI Table 4 4 identifies FWFT support for each FIFO implementation Table 4 4 Implementation specific Support for Data Counts FIFO Implementation FWFT Support Block RAM v Independent Clocks Distributed RAM v Built in Block RAM v Common Clock Distributed RAM v Shift Register v Built in Read Data Count Read data count RD DATA COUNT pessimistically reports the number of words available for reading The count is guaranteed to never over report the number of words available in the FIFO although it may temporarily under report the number of words available to ensure that the user never underflows the FIFO The user can specify the width of the read data count bus with a maximum width of log2 read depth If the width specified is smaller than the maximum allowable width the bus is truncated with the lower bits removed For example the user can specify to use two bits out of a maximum allowable three bits provided a FIFO depth of eight These two bits indicate the number of words in the FIFO with a quarter resolution This provides a status of the contents of the FIFO for the read clock domain Note f a read operation occurs on a rising clock edge of RD crk that read is reflected on the RD DATA COUNT Signal following the next rising clock edge A write operation on the wR_cLK clock domain may take a number
84. reshold e Single threshold constant User specifies the threshold value through the CORE Generator GUI Once the core is generated this value can only be changed by re generating the core This option consumes fewer resources than the single threshold with dedicated input port e Single threshold with dedicated input port User specifies the threshold value through an input port PROG_EMPTY_THRESH on the core This input can be changed while the FIFO is in reset providing the user the flexibility to change the programmable empty threshold in circuit without re generating the core Note Refer to the CORE Generator GUI for valid ranges for each threshold Figure 4 14 shows the programmable empty flag with a single threshold The user writes to the FIFO until there are five words in the FIFO Since the programmable empty threshold is set to four PROG_EMPTY is asserted until more than four words are present in the FIFO Once five words or more are present in the FIFO PROG_EMPTY is deasserted Both read data count RD_DATA_COUNT and PROG_EMPTY have one clock cycle of delay A ESE PLA l l l l l l RD_EN l l l y l l l l l l I l l l l i VALID 1 l I y I l I I I l l l l l RD DATA coUNT AYNA j l l l l l PROG EMPTY l l l 1 1 1 Figure 4 14 Programmable Empty with Single Threshold Threshold Set to 4 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 FIFO Usage a
85. s in the FIFO exceeds the programmable threshold FIFO Generator v3 3 User Guide UG175 April 2 2007 www xilinx com 27 7 XILINX Chapter 2 Core Overview Table 2 7 Interface Signals for FIFOs with a Common Clock Continued Name VALID Direction Output Description Valid This signal indicates that valid data is available on the output bus DOUT UNDERFLOW Output Underflow Indicates that read request RD_EN during the previous clock cycle was rejected because the FIFO is empty Underflowing the FIFO is not destructive to the FIFO PROG_EMPTY_THRESH Input Programmable Empty Threshold This signal is used to set the threshold value for the assertion and deassertion of the programmable empty flag PROG_EMPTY The threshold can be dynamically set in circuit during reset The user can either choose to set the assert and negate threshold to the same value using PROG_EMPTY_THRESRH or the user can control these values independently using PROG_EMPTY_THRESH_ASSERT and PROG_EMPTY_THRESH_NEGATE PROG_EMPTY_THRESH_ ASSERT Input Programmable Empty Threshold Assert This signal is used to set the lower threshold value for the programmable empty flag which defines when the signal is asserted The threshold can be dynamically set in circuit during reset PROG_EMPTY_THRESH_ NEGATE Input Programmable Empty Threshold Negate This signal is used to set the upper t
86. se of constraints timing constraints and placement and or area constraints Understand Signal Pipelining and Synchronization To understand the nature of FIFO designs it is important to understand how pipelining is used to maximize performance and implement synchronization logic for clock domain crossing Data written into the write interface may take multiple clock cycles before it can be accessed on the read interface Synchronization Considerations FIFOs with independent write and read clocks require that interface signals be used only in their respective clock domains The independent clocks FIFO handles all synchronization requirements enabling the user to cross between two clock domains that have no relationship in frequency or phase Important FIFO Full and Empty flags must be used to guarantee proper behavior Figure 4 1 shows the signals with respect to their clock domains All signals are synchronous to a specific clock with the exception of RST which performs an asynchronous reset of the entire FIFO FIFO Generator v3 3 User Guide www xilinx com 39 UG175 April 2 2007 7 XILINX Chapter 4 Designing with the Core DOUT M 0 ALMOST EMPTY ALMOST FULL Write Clock Read Clock Domain Domain PROG_FULL PROG_EMPTY OVERFLOW UNDERFLOW m SBITERR PROG FULL THRESH ASSEHT LA PROG FULL THRESH NEGATE E _ _ _E A j gt gt PROG_FUL
87. sed in this document Convention Meaning or Use Example Messages prompts and Courier font program files that the system speed grade 100 displays and signal names Courier bold Lateral a ee ngdbuild design name a syntactical statement Variables in a syntax See the Development System statement for which you must Reference Guide for more supply values information Italic font References to other manuals See the User Guide for details If a wire is drawn so that it Emphasis in text overlaps the pin of a symbol the two nets are riot connected Dark Shading DEG Eh bene niet supporiee This feature is not supported or reserved 12 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 Conventions XILINX Convention Square brackets Meaning or Use An optional entry or parameter However in bus specifications such as bus 7 0 they are required Example ngdbuild option name design name Braces A list of items from which you must choose one or more lowpwr on off Vertical bar Separates items in a list of choices lowpwr on off Vertical ellipsis Repetitive material that has been omitted IOB 1 IOB 2 Name Name QOUT CLKIN Horizontal ellipsis Omitted repetitive material allow block block name Notations loci loc2 locn 4 A read of address The prefix 0x or the suffix h p E indicate hexadecimal notat
88. ses the FWFT data counts to be estimates of the number of words in the FIFO not exact representations of the number of words in the FIFO By selecting Use extra logic for more accurate Data Counts on page 4 of the CORE Generator GUI an extra bit is added to WR_DATA_COUNT and RD_DATA_COUNT to allow them to accurately express the full depth of the FIFO When this option is selected RD_DATA_COUNT and WR_DATA_COUNT behave as described in the sections above When this option is not selected the write and read data counts are only estimates of the contents of the FIFO For example an independent clocks FIFO with a user selected input and output depth of eight has an actual depth as reported on the summary page of the GUI of seven If FWFT is selected the additional register stages increase the FIFO s effective depth to nine In this case selecting use extra logic for more accurate data counts will increase the data count counter sizes to display the full range of the FIFO zero to nine words Note For FWFT implementations WR_DATA_COUNT is guaranteed to be accurate when words are present in the FIFO but may be incorrect by 2 at or near empty Example Operation Figure 4 16 shows write and read data counts When WR_EN is asserted and FULL is deasserted WR DATA COUNT increments Similarly when RD_EN is asserted and EMPTY is deasserted RD DATA COUNT decrements Note In the first part of Figure 4 16 a successful write operatio
89. st Full v v v v Almost Empty v v v v Handshaking v v v v v v Data Count v v v v Programmable v v v v v v Empty Full Thresholds First Word Fall v v v v Through Synchronous v v3 Reset Asynchronous v y v y d v Reset DOUT Reset v v v5 v Value ECC v6 v6 1 For applications with a single clock that require non symmetric ports use the independent clock configuration and connect the write and read clocks to the same source A dedicated solution for common clocks will be available in a future release Contact your Xilinx representative for more details FWFT is only supported for the Virtex 5 built in FIFOs Synchronous reset is available for common clock configurations using distributed and block RAM only Asynchronous reset is optional for all FIFOs built using distributed and block RAM All architectures except for Virtex Virtex E Spartan ll and Spartan llE ECC is only supported for the Virtex 5 built in FIFOs DNA 20 www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 FIFO Interfaces FIFO Interfaces The following two sections provide definitions for the FIFO interface signals Figure 2 1 illustrates these signals both the standard and optional ports for a FIFO core that sup ports independent write and read clocks DIN N 0 WR_EN FULL WR_CLK ALMOST_FULL PROG_FULL WR_ACK OVERFLOW PROG_FULL_THRESH_ASSERT PROG_FULL_THRESH_NEGATE AAA gt PROG_
90. ster RAM Synchronous Virtex 5 375 MHz 115 105 0 0 256 FIFO 7 Distributed 512 x 16 Virtex 4 200 MHz 370 84 0 0 1024 RAM Virtex II 150 MHz 370 84 0 0 1024 Virtex 5 350 MHz 132 143 1 0 0 Independent Clocks FIFO 512x 16 Virtex 4 250MHz 163 126 1 0 0 Block RAM Virtex II 200 MHz 163 126 1 0 0 Virtex 5 350 MHz 185 186 2 0 0 Independent Clocks FIFO 4096 x 16 Virtex 4 250 MHz 214 165 4 0 0 Block RAM Virtex II 175 MHz 214 165 4 0 0 Independent Virtex 5 475 MHz 96 123 0 0 32 NET vrea MER 134 115 0 0 128 Distributed RAM Virtex II 225 MHz 134 115 0 0 128 Independent Virtex 5 350 MHz 154 168 0 0 256 Clocks FIFO a KERS 512 x 16 Virtex 4 225 MHz 412 160 0 0 1024 Distributed RAM Virtex II 150 MHz 412 160 0 0 1024 Virtex 5 450 MHz 68 63 0 32 0 ee 64x16 Virtex 4 200 MHz 97 62 0 64 0 Virtex II 150 MHz 97 62 0 64 0 Virtex 5 275 MHz 174 91 0 256 0 Shift Register FIFO 512x16 Virtex 4 200 MHz 355 106 0 512 0 Virtex II 150 MHz 355 106 0 512 0 Table A 3 provides results for FIFOs configured to use the Virtex 5 built in FIFO The benchmarks were performed using a Virtex 5 5v1x50 2 target device Table A 3 Benchmarks FIFO Configured with Virtex 5 FIFO36 Resources FIFO Type Synchronous FIFO36 basic Resources Depth x Width Read Mode _ Pervnrmance aH LUTs FFs FIFO36s Standard 500 0 2 1 512x 72 FWFT 400 2 4 1 Standard 350 10 6 4 16kx 8 FWFT 375 1
91. sume that the data in the entire FIFO has been corrupted and the user logic needs to take the appropriate action As an example when DBITERR is flagged an appropriate action for the user logic is to halt all FIFO operation reset the FIFO and restart the data transfer The SBITERR and DBITERR outputs are not registered and are generated combinatorially If the configured FIFO uses two independent read and write clocks the SBITERR and DBITERR outputs may be generated from either the write or read clock domain The signals generated in the write clock domain are synchronized before being combined with the SBITERR and DBITERR signals generated in the read clock domain Note that due to the differing read and write clock frequencies and the OR gate used to combine the signals the number of read clock cycles that the SBITERR and DBITERR flags assert is not an accurate indicator of the number of errors found in the built in FIFOs www xilinx com FIFO Generator v3 3 User Guide UG175 April 2 2007 FIFO Usage and Control XILINX Write Domain Read Domain Cascaded Built in FIFO Primitives I E 1 FULL AMM WR_EN E Built In FIFO DIN gt bin D Y 1 i WR_ACK i UNDERFLOW OVERFLOW Logic For Optional Logic For Optional VALID Flags Write Domain Flags Read Domain t PROG FULL PROG_EMPTY Figure 4 21 SBITERR and DBITERR Outputs in the FIFO Generator Core Reset Behavior
92. tion Abo t CONC den prin Dies a RDA E A DEPT 15 Recommended Design Experience oooocooccccoccocccccccncr rr 15 Technical Support iore CE e e e a EY PCR Vea lee don ada 15 Feedback D 16 FFO Generol resors cee ved Veet YR RR PERETE EEN a re ga 16 Document i e x hg dae dieses PAA EEE EREA EEA Ra id end ob e tege has 16 Chapter 2 Core Overview Systein Overview a i sdi cerkerandui haa dE anise CE CERE E AAA 17 Clock Implementation Operation 0666 17 Built in FIFO Support in Virtex 5 20 eee eee 17 Built in FIFO Support in Virtex 4 2 0 eee 17 First W ord Fall Through ie ede Re kara ha b ce RE he 17 Memory Types ii cus sce itd ebbe ce e e OY e ae de E RR a 18 Non Symmetric Aspect Ratio 6 6 cence nne 18 Core Configuration and Implementation 0 0 0 e eee 18 Independent Clocks Block RAM and Distributed RAM 00 00000 19 Independent Clocks Virtex 5 and Virtex 4 Built in FIFO 004 19 Common Clock Block RAM Distributed RAM Shift Register 19 Common Clock Virtex 5 and Virtex 4 Built in FIFO o o oooooooooooooo 20 FIFO Generator Features 20 FIFO Interfaces iii is aur naive bile a Ee S dina o ea e Rae 21 Interface Signals FIFOs With Independent Clocks 0 00 cece eee ee 21 Interface Signals FIFOs with Common Clock ooooooococooccccoomomm m o 26 Chapter
93. to the user defined assert threshold When the programmable full flag is asserted the FIFO can continue to be written to until the full flag FULL is asserted If the number of words in the FIFO is less than the negate threshold the flag is deasserted Note If a write operation occurs on a rising clock edge that causes the number of words to meet or exceed the programmable full threshold then the programmable full flag will assert on the next rising clock edge The deassertion of the programmable full flag has a longer delay and depends on the relationship between the write and read clocks Programmable Full Single Threshold This option enables the user to set a single threshold value for the assertion and deassertion of PROG_FULL When the number of entries in the FIFO is greater than or equal to the threshold value PROG_FULL is asserted When the number of entries in the FIFO is less than the threshold value PROG_ FULL is deasserted There are two options for implementing this threshold e Single threshold constant User specifies the threshold value through the CORE Generator GUI Once the core is generated this value can only be changed by re generating the core This option consumes fewer resources than the single threshold with dedicated input port e Single threshold with dedicated input port User specifies the threshold value through an input port PROG_FULL_THRESH on the core This input can be changed while the FIFO is in
94. uilt in FIFOs in both width and depth The core expands the capabilities of the built in FIFOs by utilizing the FPGA fabric to create optional status flags not implemented in the built in FIFO macro The built in Error Correction Checking ECC feature in the built in FIFO macro is also available to the user Built in FIFO Support in Virtex 4 The FIFO Generator supports a single instantiation of the Virtex 4 built in FIFO module The core also implements a FIFO flag patch Solution 1 Synchronous Asynchronous Clock Work Arounds defined in the Virtex 4 User Guide based on estimated clock frequencies This patch is implemented in fabric See Appendix A Performance Information for resource utilization estimates First Word Fall Through The first word fall through FWFT feature provides the ability to look ahead to the next word available from the FIFO without having to issue a read operation The FIFO accomplishes this by using output registers which are automatically loaded with data when data appears in the FIFO This causes the first word written to the FIFO to automatically appear on the data out bus DOUT Subsequent user read operations cause the output data to update with the next word as long as data is available in the FIFO The use of registers on the FIFO DOUT bus improves clock to output timing and the FWFT FIFO Generator v3 3 User Guide www xilinx com 17 UG175 April 2 2007 7 XILINX Chapter 2 Core Overvi

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