ATD_10B8C Block User Guide V02.08
Contents
1. 20 3 3 7 ATD Status Register 0 ATDSTATO 22 M MOTOROLA 3 ATD 10B8C Block User Guide V02 08 3 3 8 Reserved Register 5 0 23 3 3 9 AID lest Register TOR DBTEST massaiset Bee ee sku DEEN 24 3 3 10 Status Register 1 1 25 3 3 11 Input Enable Register 25 3 3 12 Port Data Register PORTAD nme kx eR xe E Ger ga ee 26 3 3 13 Conversion Result Registers ATDDRx 26 Section 4 Functional Description Za Generale ee aote adus ee E Lt D don 29 42 Analog Sub Dloole iua fed re at E Em d Tete 29 4 2 1 Sample and Hold Machine ouo pr eret go tar ui E Mare ode HD 29 4 2 2 Analog Input Multiplexer sere nee re 29 4 2 3 Sample B lTer AmplilloE ter het bot tie ek EP SR Re 29 4 2 4 Analeg 10 Digital A D 29 4 3 Digital Sub block 2 222 222 22 Las oeste tae P PAITA K iB egit diae he 30 4 3 1 External Trigger Input ETRIG cuoc ac een 30 4 3 2 General Purpose Digital Input Port 31 4 3 3 Low Power Modes sen eae G1 bebe hee ieee rain 31 Section 5 Res2. 10B8C is structured in an analog and a digital sub block 4 2 Analog Sub block The analog sub block contains all analog electronics required to perform a single conversion Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub block 4 2 1 Sample and Hold Machine The Sample and Hold S H Machine accepts analog signals from the external surroundings and stores them as capacitor charge on a storage node The sample process uses a two stage approach During the first stage the sample amplifier is used to quickly charge the storage node The second stage connects the input directly to the storage node to complete the sample for high accuracy When not sampling the sample and hold machine disables its own clocks The analog electronics still draw their quiescent current The power down ADPU bit must be set to disable both the digital clocks and the analog power consumption The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA 4 2 2 Analog Input Multiplexer The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold machine 4 2 3 Sample Buffer Amplifier The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly charged to the sample potential 4 2 4 Analog to Digital A D Machine The A D Machine performs analog to digital conversions The reso
3. Conversion Result Register High Byte ATDDRxH 27 Left Justified ATD Conversion Result Register Low Byte ATDDRxL 27 Right Justified ATD Conversion Result Register High Byte ATDDRxH 27 Right Justified Conversion Result Register Low Byte ATDDRxL 28 5 ATD 10B8C Block User Guide V02 08 6 M MOTOROLA ATD_10B8C Block User Guide V02 08 List of Tables Table 0 1 Revision History 0 e ae NE VERDE engere 2 Table 3 1 Module Memory gt see er es ecu Ren RES 13 Table 3 2 External Trigger 16 Table 3 3 Conversion Sequence Length Coding 17 Table 3 4 ATD Behavior in Freeze Mode breakpoint 17 Table 3 5 Sample Time Select ss nn a et 18 Table 3 6 Clock Prescaler Values 2 22 24 2 Re aa a 19 Table 3 7 Available Result Data Formats 21 Table 3 8 Left Justified Signed and Unsigned Output Codes 21 Table 3 9 Analog Input Channel Select 0 22 Table 3 10 Special Channel Select 24 Table 4 1 External Trigger Control Bits s Ben Dr 30 Table 6 1 10B8C Interrupt 35 M MOTOROLA 7 ATD_10
4. ATD 10B8C Block User Guide V02 08 e Wait Mode Entering Wait Mode the ATD conversion either continues or aborts for low power depending on the logical value of the AWAIT bit Freeze Mode In Freeze Mode the 10B8C will behave according to the logical values of FRZ1 FRZO bits This is useful for debugging and emulation 1 4 Block Diagram ATD 10B8C Bus Clock Clock ATD clock Prescaler Conversion NN Complete Interr Mode and Timing Control Comparator PAD1 X ANO PADO X VRHK Aa X Ven and DAC AN7 PAD7 AN6 PAD6 K AN5 PAD5 BR 4 AN4 PADA X wi AN3 PAD3 E Analog ATD Input Enable Register MUX gt Port AD Data Register Figure 1 1 ATD_10B8C Block Diagram 10 MOTOROLA ATD_10B8C Block User Guide V02 08 Section 2 Signal Description 2 1 Overview The ATD 10B8C has a total of 12 external pins 2 2 Detailed Signal Descriptions 2 2 1 AN7 ETRIG PAD7 This pin serves as the analog input Channel 7 It can be configured to provide an external trigger for the ATD conversion It can be configured as general purpose digital input 2 2 2 AN6 PAD6 This pin serves as the analog input Channel 6 It can be configured as general purpose digital input 2 2 3 AN5 PAD5 This pin serves as the analog input Channel 5 It can be configured as general purpose digital input 2 2 4 AN4 PADA This pin serves as the analog input Channel 4 I
5. ASCIE ATD Sequence Complete Interrupt Enable 1 ATD Interrupt will be requested whenever ASCIF 1 is set 0 ATD Sequence Complete interrupt requests are disabled ASCIF ATD Sequence Complete Interrupt Flag If ASCIE 1 the ASCIF flag equals the SCF flag see 3 3 7 else ASCIF reads zero Writes have no effect 1 ATD sequence complete interrupt pending 0 No ATD interrupt occurred 3 3 4 ATD Control Register 3 ATDCTL3 This register controls the conversion sequence length FIFO for results registers and behavior in Freeze Mode Writes to this register will abort current conversion sequence but will not start a new sequence 03 7 6 5 4 3 2 1 0 p S8C S4C S2C S1C FIFO FRZ1 FRZO RESET 0 0 1 0 0 0 0 0 Unimplemented or Reserved Figure 3 4 ATD Control Register 3 ATDCTL3 Read anytime Write anytime 16 M MOTOROLA ATD_10B8C Block User Guide V02 08 S8C 54 S2C SIC Conversion Sequence Length These bits control the number of conversions per sequence Table 3 3 shows all combinations At reset S4C is set to 1 sequence length is 4 This is to maintain software continuity to HC12 family Table 3 3 Conversion Sequence Length Coding Number of Conversions per Sequence o oo 0 0 0 0 1 Oo O N OI ol A OI NI x x x FIFO Result Register FIFO Mode If this bit is zero non FIFO mode the A D
6. These 3 read only bits are the binary value of the conversion counter The conversion counter points to the result register that will receive the result of the current conversion E g CC2 1 CC1 1 0 indicates that the result of the current conversion will be in ATD Result Register 6 If in non FIFO mode FIFO 0 the conversion counter is initialized to zero at the begin and end of the conversion sequence If in FIFO mode FIFO 1 the register counter is not initialized The conversion counters wraps around when its maximum value is reached 3 3 8 Reserved Register ATDTESTO This register is reserved for factory testing and is not available in normal modes _08 7 6 5 4 3 2 1 0 EE NN R ESET 0 0 0 0 0 0 0 0 lt Unimplemented or Reserved Figure 3 8 Reserved Register ATDTESTO Read always read 00 in normal modes M MOTOROLA 23 ATD_10B8C Block User Guide V02 08 Write unimplemented in normal modes NOTE Writing to this registers when in special modes can alter functionality 3 3 9 ATD Test Register 1 ATDTEST1 This register contains the SC bit used to enable special channel conversions _09 7 6 5 4 3 2 1 0 Pe U O a a R E 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 9 ATD Test Register 1 ATDTEST1 Read anytime Write anytime SC Special Channel Conversion Bit If this bit is set then special
7. ETRIGLE ETRIGP ETRIGE SCAN Description Ignores external trigger Performs one X X 0 0 conversion sequence and stops x X 0 1 Ignores external trigger Performs continuous conversion sequences 0 0 4 X Falling edge triggered Performs one conversion sequence per trigger 0 1 4 X Rising edge triggered Performs one conversion sequence per trigger Trigger active low Performs 1 0 1 X continuous conversions while trigger is active Trigger active high Performs 1 1 1 X continuous conversions while trigger is active During a conversion if additional active edges are detected the overrun error flag ETORF is set In either level or edge triggered modes the first conversion begins when the trigger is received In both cases the maximum latency time is one Bus Clock cycle plus any skew or delay introduced by the trigger circuitry NOTE The conversion results for the external trigger ATD channel 7 have no meaning while external trigger mode is enabled 30 M MOTOROLA ATD_10B8C Block User Guide V02 08 Once ETRIGE is enabled conversions cannot be started by a write to ATDCTLS but rather must be triggered externally If the level mode is active and the external trigger both de asserts and re asserts itself during a conversion sequence this does not constitute an overrun Therefore the flag is not set If the trigger is left asserted in level mode while a sequence is completing another sequence will be triggered im
8. Register 5 ATDCTL5 Read anytime Write anytime DJM Result Register Data Justification This bit controls justification of conversion data in the result registers See 3 3 13 ATD Conversion Result Registers ATDDRx for details 1 Right justified data in the result registers 0 Left justified data in the result registers DSGN Result Register Data Signed or Unsigned Representation This bit selects between signed and unsigned conversion data representation in the result registers Signed data is represented as 2 s complement Signed data is not available in right justification See 3 3 13 Conversion Result Registers ATDDRx for details 1 Signed data representation in the result registers 0 Unsigned data representation in the result registers Table 3 7 summarizes the result data formats available and how they are set up using the control bits Table 3 8 illustrates the difference between the signed and unsigned left justified output codes for an input signal range between 0 and 5 12 Volts 20 M MOTOROLA ATD_10B8C Block User Guide V02 08 Table 3 7 Available Result Data Formats Result Data Formats SRES8 DJM Description and Bus Bit Mapping 8 bit left justified unsigned bits 8 15 8 bit left justified signed bits 8 15 8 bit right justified unsigned bits 0 7 8 bit right justified signed bits 0 7 10 bit left justified unsigned bits 6 15 10 bit left justified signed
9. bits 6 15 10 bit right justified unsigned bits 0 9 10 bit right justified signed bits 0 9 lt lt dt O 0 0 0 Table 3 8 Left Justified Signed and Unsigned ATD Output Codes Input Signal Unsigned Signed Unsigned Vrl 0 Volts 8 Bit 10 Bit 10 Bit Vrh 5 12 Volts Codes Codes 5 120 Volts FFCO 5 100 FFOO 5 080 FEOO 2 580 8100 2 560 8000 2 540 7F00 0 020 0100 0 000 0000 SCAN Continuous Conversion Sequence Mode This bit selects whether conversion sequences are performed continuously or only once 1 Continuous conversion sequences scan mode 0 Single conversion sequence MULT Multi Channel Sample Mode When MULT is 0 the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence The analog channel is selected by channel selection code control bits CC CB CA located in ATDCTL5 When MULT is 1 ATD sequence controller samples across channels The number of channels sampled is determined by the sequence length value S8C S4C S2C S1C The first analog channel examined is determined by channel selection code CC CA control bits subsequent channels sampled in the sequence are determined by incrementing the channel selection code 1 Sample across several channels 0 Sample only one channel CC CB CA Analog Input Channel Select Code These bits select t
10. channel conversion can be selected using CC CB and CA of ATDCTLS Table 3 10 lists the coding 1 Special channel conversions enabled 0 Special channel conversions disabled NOTE Always write remaining bits of ATDTESTI Bit7 to zero when writing SC bit Not doing so might result in unpredictable ATD behavior Read of ATDTESTI returns unpredictable values on Bit7 to Bitl Table 3 10 Special Channel Select Coding Analog Input sc Channel Reserved VRH VRL VRH VR 2 Reserved 24 M MOTOROLA ATD_10B8C Block User Guide V02 08 3 3 10 ATD Status Register 1 ATDSTAT1 This read only register contains the Conversion Complete Flags 0B 7 6 5 4 3 2 1 0 R YE 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 10 ATD Status Register 1 ATDSTAT1 Read anytime Write anytime no effect CCFx Conversion Complete Flag x x 7 6 5 4 3 2 1 0 A conversion complete flag is set at the end of each conversion in a conversion seguence The flags are associated with the conversion position in a seguence and also the result register number Therefore CCFO is set when the first conversion in a sequence is complete and the result is available in result register ATDDRO CCF1 is set when the second conversion in a sequence is complete and the result is available in ATDDRI and so forth A flag CCFx x 7 6 5 4 3 2 1 0 is cleared when one of the following occurs A Write to ATD
11. B8C Block User Guide V02 08 8 M MOTOROLA ATD_10B8C Block User Guide V02 08 Section 1 Introduction 1 1 Overview The 10B8C is an 8 channel 10 bit multiplexed input successive approximation analog to digital converter Refer to device electrical specifications for ATD accuracy The block is designed to be upwards compatible with the 68HC11 standard 8 bit A D converter In addition there are new operating modes that are unique to the HC12 design 1 2 1 3 Features 8 10 Bit Resolution 7 usec 10 Bit Single Conversion Time Sample Buffer Amplifier Programmable Sample Time Left Right Justified Signed Unsigned Result Data External Trigger Control Conversion Completion Interrupt Generation Analog Input Multiplexer for 8 Analog Input Channels Analog Digital Input Pin Multiplexing 1 to 8 Conversion Sequence Lengths Continuous Conversion Mode Multiple Channel Scans Modes of Operation 1 3 1 Conversion modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels 1 3 2 MCU Operating Modes M MOTOROLA Stop Mode Entering Stop Mode causes all clocks to halt and thus the system is placed in a minimum power standby mode This aborts any conversion sequence in progress During recovery from Stop Mode there must be a minimum delay for the Stop Recovery Time before initiating a new ATD conversion sequence
12. CTLS a new conversion sequence is started B If AFFC 0 and read of ATDSTATI followed by read of result register ATDDRx C If AFFC 1 and read of result register ATDDRx 1 Conversion number x has completed result ready in ATDDRx 0 Conversion number x not completed 3 3 11 ATD Input Enable Register ATDDIEN OD 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 11 ATD Input Enable Register ATDDIEN Read anytime Write anytime M MOTOROLA 25 ATD 10B8C Block User Guide V02 08 IENx ATD Digital Input Enable on channel x x 7 6 5 4 3 2 1 0 This bit controls the digital input buffer from the analog input pin ANx to PTADx data register 1 Enable digital input buffer to PTADx 0 Disable digital input buffer to PTADx NOTE Setting this bit will enable the corresponding digital input buffer continuously If this bit is set while simultaneously using it as an analog port there is potentially increased power consumption because the digital input buffer maybe in the linear region 3 3 12 Port Data Register PORTAD The data port associated with the ATD is input only The port pins are shared with the analog A D inputs AN7 0 OF 7 6 5 4 3 2 1 0 R wo Pin Func AN7 AN6 AN5 AN4 AN3 AN2 AN1 ANO tion lt Unimplemented or Reserved Figure 3 12 Port Data Register PORTAD Read anytime Write anytime no effect The A D input channels may be used for general purpos
13. DCTLS a new conversion sequence is started C If AFFC 1 and read of a result register 1 Conversion sequence has completed 22 M MOTOROLA ATD_10B8C Block User Guide V02 08 0 Conversion sequence not completed ETORF External Trigger Overrun Flag While in edge trigger mode ETRIGLE 0 if additional active edges are detected while a conversion sequence is in process the overrun flag is set This flag is cleared when one of the following occurs A Write 1 to ETORF B Write to ATDCTL2 ATDCTL3 or ATDCTL4 a conversion sequence is aborted C Write to ATDCTLS a new conversion sequence is started 1 External trigger over run error has occurred 0 No External trigger over run error has occurred FIFOR FIFO Over Run Flag This bit indicates that a result register has been written to before its associated conversion complete flag CCF has been cleared This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels However it is also practical for non FIFO modes and indicates that a result register has been over written before it has been read i e the old data has been lost This flag is cleared when one of the following occurs A Write 1 to FIFOR B Start a new conversion sequence write to ATDCTLS or external trigger 1 An over run condition exists 0 No over run has occurred CC2 CC1 CCO Conversion Counter
14. DOCUMENT NUMBER S12ATD10B8CV2 D 10B8C Block User Guide V02 08 Original Release Date 27 OCT 2000 Revised 16 Aug 2002 Motorola Inc Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part M MOTOROLA ATD 10B8C Block User Guide V02 08 Revision History NOE en is Au
15. General At reset the ATD 10B8C is in a power down state The reset state of each individual bit is listed within the Register Description section see Section 3 Memory Map and Register Definition which details the registers and their bit fields 33 M MOTOROLA ATD_10B8C Block User Guide V02 08 34 M MOTOROLA Section 6 Interrupts 6 1 General ATD_10B8C Block User Guide V02 08 The interrupt requested by the 10 8 is listed in Table 6 1 Refer to MCU specification for related vector address and priority Table 6 1 ATD_10B8C Interrupt Vectors CCR Interrupt Source Mask Local Enable Seguence Complete bit ASCIE in ATDCTL2 Interrupt See register descriptions for further details M MOTOROLA 35 ATD_10B8C Block User Guide V02 08 36 M MOTOROLA User Guide End Sheet M MOTOROLA ATD_10B8C Block User Guide V02 08 37 ATD_10B8C Block User Guide V02 08 FINAL PAGE OF 38 PAGES 38 M MOTOROLA
16. ce Any access to a result register will cause the associate CCF flag to clear automatically 0 ATD flag clearing operates normally read the status register ATDSTATI before reading the result register to clear the associate CCF flag AW AI ATD Power Down in Wait Mode When entering Wait Mode this bit provides on off control over the 10 8 block allowing reduced MCU power Because analog electronic is turned off when powered down the ATD requires a recovery time period after exit from Wait mode 1 Power down ATD during Wait mode 0 ATD continues to run in Wait mode ETRIGLE External Trigger Level Edge Control This bit controls the sensitivity of the external trigger signal See Table 3 2 for details ETRIGP External Trigger Polarity This bit controls the polarity of the external trigger signal See Table 3 2 for details M MOTOROLA 15 ATD 10B8C Block User Guide V02 08 Table 3 2 External Trigger Configurations ETRIGLE ETRIGP Trigger 0 0 falling edge 0 1 rising edge 1 0 low level 1 1 high level ETRIGE External Trigger Mode Enable This bit enables the external trigger on ATD channel 7 The external trigger allows to synchronize sample and ATD conversions processes with external events 1 Enable external trigger 0 Disable external trigger NOTE The conversion results for the external trigger ATD channel 7 have no meaning while external trigger mode is enabled
17. conversion results map into the result registers based on the conversion sequence the result of the first conversion appears in the first result register the second result in the second result register and so on If this bit is one FIFO mode the conversion counter 15 not reset at the beginning or end of a conversion sequence conversion results are placed in consecutive result registers between sequences The result register counter wraps around when it reaches the end of the result register file The conversion counter value in ATDSTATO can be used to determine where in the result register file the current conversion result will be placed Finally which result registers hold valid data can be tracked using the conversion complete flags Fast flag clear mode may or may not be useful in a particular application to track valid data 1 Conversion results are placed in consecutive result registers wrap around at end 0 Conversion results are placed in the corresponding result register up to the selected sequence length FRZI FRZO Background Debug Freeze Enable When debugging an application it is useful in many cases to have the ATD pause when a breakpoint Freeze Mode is encountered These 2 bits determine how the ATD will respond to a breakpoint as shown in Table 3 4 Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze pe
18. e digital input PTADx A D Channel x ANx Digital Input x 7 6 5 4 3 2 1 0 If the digital input buffer on the ANx pin is enabled IENx 1 read returns the logic level on ANx pin signal potentials not meeting VIL or VIH specifications will have an indeterminate value If the digital input buffers are disabled IENx 0 read returns a 1 Reset sets all PORTAD bits to 1 3 3 13 ATD Conversion Result Registers ATDDRx The A D conversion results are stored in 8 read only result registers The result data is formatted in the result registers based on two criteria First there is left and right justification this selection is made using the DJM control bit in ATDCTLS Second there is signed and unsigned data this selection is made using the DSGN control bit in ATDCTLS Signed data is stored in 2 s complement format and only exists in left justified format Signed data selected for right justified format is ignored 26 M MOTOROLA ATD_10B8C Block User Guide V02 08 Read anytime Write anytime no effect 3 3 13 1 Left Justified Result Data 10 ATDDROH 12 ATDDR1H 14 ATDDR2H 5 16 ATDDR3H 18 ATDDR4H 1A ATDDR5H 1C ATDDR6H 1E ATDDR7H 15 14 13 12 11 10 9 8 R BIT 9 MSB BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT2 10 bit data W BIT7 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 8 bit data RESET U U U U U U U U 10 bit data Ss Unimplemented or Reserved Figure 3 13 Left Justified ATD Co
19. ets 5 1 Geel discs ee ee 33 Section 6 Interrupts 6 1 Genbral cu Qus us 4 Le std fe Piet eid oh ee 35 M MOTOROLA ATD_10B8C Block User Guide V02 08 List of Figures Figure 1 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 M MOTOROLA ALD TOBSC Block Diagram 10 Reserved Register ATDGTLO quu E er RIVER rear dee ke 14 Reserved Register ATDCTL1 14 ATD Control Register 2 12 15 ATD Control Register 16 ATD Control Register 4 4 18 ATD Control Register 5 ATDCTL5 20 ATD Status Register 0 22 Reserved Register 5 23 ATD Test Register 1 ATDTESTT 244 EY 6 ie 24 ATD Status Register 1 1 25 ATD Input Enable Register ATDDIEN 25 Port Data Register 26 Left Justified
20. he analog input channel s whose signals are sampled and converted to digital codes Table 3 9 lists the coding used to select the various analog input channels In the case of single channel scans MULT 0 this selection code specified the channel examined In the case of M MOTOROLA 21 ATD 10B8C Block User Guide V02 08 multi channel scans MULT 1 this selection code represents the first channel to be examined in the conversion sequence Subsequent channels are determined by incrementing channel selection code selection codes that reach the maximum value wrap around to the minimum value Table 3 9 Analog Input Channel Select Coding c EIL 0 0 0 ANO 0 1 0 0 0 1 1 0 1 1 1 0 1 1 3 3 7 ATD Status Register 0 ATDSTATO This read only register contains the Sequence Complete Flag overrun flags for external trigger and FIFO mode and the conversion counter 06 7 6 5 4 3 2 1 0 SCF ETORF FIFOR 2 C SSI CCS RESET 0 0 0 0 0 0 0 0 me Unimplemented or Reserved Figure 3 7 ATD Status Register 0 ATDSTATO Read anytime Write anytime No effect on CC2 CC1 SCF Sequence Complete Flag This flag is set upon completion of a conversion sequence If conversion sequences are continuously performed SCAN 1 the flag is set after each one is completed This flag is cleared when one of the following occurs A Write 1 to SCF B Write to AT
21. ime consists of two phases The first phase is two ATD conversion clock cycles long and transfers the sample quickly via the buffer amplifier onto the A D machine s storage node The second phase attaches the external analog signal directly to the storage node for final charging and high accuracy Table 3 5 lists the lengths available for the second sample phase Table 3 5 Sample Time Select SMP1 SMPO Length of 2nd phase of sample time 0 0 2 A D conversion clock periods 18 M MOTOROLA ATD_10B8C Block User Guide V02 08 Table 3 5 Sample Time Select SMP1 SMPO Length of 2nd phase of sample time 4 A D conversion clock periods 8 A D conversion clock periods 16 A D conversion clock periods PRS4 PRS3 PRS2 51 PRSO ATD Clock Prescaler These 5 bits are the binary value prescaler value PRS The ATD conversion clock frequency is calculated as follows BusClock ATDclock IPRS 1 x 0 5 Note that the maximum ATD conversion clock frequency is half the Bus Clock The default after reset prescaler value is 5 which results in a default ATD conversion clock frequency that is Bus Clock divided by 12 Table 3 6 illustrates the divide by operation and the appropriate range of the Bus Clock Table 3 6 Clock Prescaler Values Total Divisor Prescale Value Value Max Bus Clock Min Bus Clock divide by 2 4 MHz 1MHz divide by 4 8MHz 2 MHz divide by 6 12 MHz 3 MHz divide by 8 16 MHz 4 MHz di
22. lution is program selectable at either 8 or 10 bits The A D machine uses a successive approximation architecture It functions by comparing the stored analog sample potential with a series of digitally generated analog potentials By following a binary search algorithm the A D machine locates the approximating potential that is nearest to the sampled potential M MOTOROLA 29 ATD 10B8C Block User Guide V02 08 When not converting the A D machine disables its own clocks The analog electronics still draws quiescent current The power down ADPU bit must be set to disable both the digital clocks and the analog power consumption Only analog input signals within the potential range of Vp to A D reference potentials will result in a non railed digital output codes 4 3 Digital Sub block This subsection explains some of the digital features in more detail See register descriptions for all details 4 3 1 External Trigger Input ETRIG The external trigger feature allows the user to synchronize ATD conversions to the external environment events rather than relying on software to signal the ATD module when ATD conversions are to take place The input signal ATD channel 7 is programmable to be edge or level sensitive with polarity control Table 4 1 gives a brief description of the different combinations of control bits and their affect on the external trigger function Table 4 1 External Trigger Control Bits
23. mediately 4 3 2 General Purpose Digital Input Port Operation The input channel pins can be multiplexed between analog and digital data As analog inputs they are multiplexed and sampled to supply signals to the A D converter As digital inputs they supply external input data that can be accessed through the digital port register PORTAD input only The analog digital multiplex operation is performed in the input pads The input pad is always connected to the analog inputs of the 10B8C The input pad signal is buffered to the digital port registers This buffer can be turned on or off with the ATDDIEN register This is important so that the buffer does not draw excess current when analog potentials are presented at its input 4 3 3 Low Power Modes The 10B8C can be configured for lower MCU power consumption in 3 different ways Stop Mode Wait Mode with AWAI 1 e Power down by writing ADPU 0 Note that all ATD registers remain accessible Note that the reset value for the ADPU bit is zero Therefore when this module is reset it is reset into the power down state Once the ATD 10B8C is configured for low power it aborts any conversion seguence in progress When ATD 10B8C powers up again exit Stop Mode exit Wait Mode with AWAI 1 or set ADPU 1 it requires a recovery time period M MOTOROLA 31 ATD_10B8C Block User Guide V02 08 32 M MOTOROLA ATD_10B8C Block User Guide V02 08 Section 5 Resets 5 1
24. mented in normal modes NOTE Writing to this registers when in special modes can alter functionality 3 3 2 Reserved Register ATDCTL1 This register is reserved for factory testing and is not available in normal modes 01 7 6 5 4 3 2 1 0 HP e a RUE R ERES 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 2 Reserved Register ATDCTL1 Read always read 00 in normal modes Write unimplemented in normal modes NOTE Writing to this registers when in special modes can alter functionality 14 M MOTOROLA ATD_10B8C Block User Guide V02 08 3 3 3 ATD Control Register 2 ATDCTL2 This register controls power down interrupt and external trigger Writes to this register will abort current conversion sequence but will not start a new sequence _02 7 6 5 4 3 2 1 0 ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE AS RESET 0 0 0 0 0 0 0 0 mn Unimplemented or Reserved Figure 3 3 ATD Control Register 2 ATDCTL2 Read anytime Write anytime ADPU ATD Power Down This bit provides on off control over the 10 8 block allowing reduced MCU power consumption Because analog electronic is turned off when powered down the ATD requires a recovery time period after ADPU bit is enabled 1 Normal ATD functionality 0 Power down ATD AFFC ATD Fast Flag Clear AII 1 Changes all ATD conversion complete flags to a fast clear sequen
25. need 11 2 2 Detailed Signal Descriptions 4 2 05 task hehe date tad dee 11 2 2 1 vss eat eur E esas e s 11 2 2 2 ANO PADO iae x ost Aus Gu ae Ot Don pee Re Ose acer pi huge he 11 2 2 3 PINS pq 11 2 2 4 ANA PADRE ue a br see dee eet E Mu tuque senes C tk ioe 11 2 2 5 PANS PADS 62 0 2 09222 ee Reet tC eet SEDI LI de REPRE 11 2 2 6 taedet 11 2 2 7 ANTA PADI de p oct pt EN QUE ev t P xa us pd 11 2 2 8 PNO Sb oot Ere eere oerte Nat E EE 11 2 2 9 detto e toot deti dA eau usa E Sd 12 22410 VODA S V SD D a meta st r LA Bia bee dee dane 12 Section 3 Memory Map and Register Definition SU MEC uU ccc 13 3 2 Module Memory 13 3 3 Register Descriptions oto re een cte e rbd eto 14 3 3 1 Reserved Register 0 14 3 3 2 Reserved Register 14 3 3 3 ATD Control Register 2 12 15 3 3 4 ATD Control Register 3 ATDGTLS PY 16 3 3 5 ATD Control Register 4 4 18 3 3 6 ATD Control Register 5 15
26. nversion Result Register High Byte ATDDRxH 11 ATDDROL 13 ATDDRIL 15 ATDDR2L 17 ATDDR3L 19 ATDDRAL 1B ATDDR5L 10 ATDDR6L ATDDR7L 15 14 13 12 11 10 9 8 R BIT 1 BIT 0 0 0 0 0 0 0 10 bit data W U U 0 0 0 0 0 0 8 bit data RESET U U 0 0 0 0 0 0 10 bit data Unimplemented or Reserved Figure 3 14 Left Justified ATD Conversion Result Register Low Byte ATDDRxL 3 3 13 2 Right Justified Result Data 10 ATDDROH 12 ATDDR1H 14 ATDDR2H 16 ATDDR3H 18 ATDDR4H 1A ATDDR5H 1C ATDDR6H ATDDR7H 15 14 13 12 11 10 9 8 R BIT 9 MSB BIT 8 10 bit data W 0 0 8 bit data RESET At reset the data format is left justified Unimplemented or Reserved Figure 3 15 Right Justified ATD Conversion Result Register High Byte ATDDRxH M MOTOROLA 27 ATD 10B8C Block User Guide V02 08 11 ATDDROL 13 ATDDRIL 15 ATDDR2L 17 ATDDR3L 19 ATDDRAL 1B ATDDR5L 10 ATDDR6L ATDDR7L 15 14 13 12 11 10 9 8 R BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 10 bit data W BIT 7 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT O 8 bit data RESET At reset the data format is left justified Unimplemented or Reserved Figure 3 16 Right Justified ATD Conversion Result Register Low Byte ATDDRxL 28 M MOTOROLA ATD_10B8C Block User Guide V02 08 Section 4 Functional Description 4 1 General The
27. riod Table 3 4 ATD Behavior in Freeze Mode breakpoint FRZ1 FRZO Behavior in Freeze mode 0 0 Continue conversion 17 M MOTOROLA ATD_10B8C Block User Guide V02 08 Table 3 4 ATD Behavior in Freeze Mode breakpoint Behavior in Freeze mode Reserved Finish current conversion then freeze Freeze Immediately 3 3 5 ATD Control Register 4 ATDCTL4 This register selects the conversion clock frequency the length of the second phase of the sample time and the resolution of the A D conversion i e 8 bits or 10 bits Writes to this register will abort current conversion sequence but will not start a new sequence _04 7 6 5 4 3 2 1 0 SRES8 SMP1 SMPO PRS4 PRS3 PRS2 PRS1 PRSO RESET 0 0 0 0 0 1 0 il us Unimplemented or Reserved Figure 3 5 ATD Control Register 4 ATDCTL4 Read anytime Write anytime SRES8 A D Resolution Select This bit selects the resolution of A D conversion results as either 8 or 10 bits The A D converter has an accuracy of 10 bits However if low resolution is reguired the conversion can be speeded up by selecting 8 bit resolution 1 8 bit resolution 0 10 bit resolution SMPI SMPO Sample Time Select These two bits select the length of the second phase of the sample time in units of ATD conversion clock cycles Note that the ATD conversion clock period is itself a function of the prescaler value bits PRS4 0 The sample t
28. st Register 0 ATDTESTO R ATD Test Register 1 ATDTEST1 R W 0A Unimplemented ATD Status Register 1 ATDSTAT1 R Unimplemented 00 ATD Input Enable Register ATDDIEN R W Unimplemented Port Data Register PORTAD R 10 5 11 ATD Result Register 0 ATDDROH ATDDROL R W ATD Result Register 1 ATDDR1H ATDDR1L R W ATD Result Register 2 ATDDR2H ATDDR2L R W 16 17 ATD Result Register 3 ATDDR3H ATDDR3L R W ATD Result Register 4 ATDDR4H ATDDR4L R W ATD Result Register 5 ATDDR5H ATDDR5L R W 10 1D ATD Result Register 6 ATDDR6H ATDDR6L R W ATD Result Register 7 ATDDR7H ATDDR7L R W NOTES 1 ATDCTLO is intended for factory test purposes only 2 ATDCTL1 is intended for factory test purposes only 3 ATDTESTO is intended for factory test purposes only NOTE Register Address Base Address Address Offset where the Base Address is defined at the MCU level and the Address Offset is defined at the module level M MOTOROLA 13 ATD 10B8C Block User Guide V02 08 3 3 Register Descriptions This section describes in address order all the 10B8C registers and their individual bits 3 3 1 Reserved Register ATDCTLO This register is reserved for factory testing and is not available in normal modes 00 7 6 5 4 3 2 1 0 0 R eee 0 0 0 0 0 0 0 0 i Unimplemented or Reserved Figure 3 1 Reserved Register ATDCTLO Read always read 00 in normal modes Write unimple
29. t can be configured as general purpose digital input 2 2 5 AN3 PAD3 This pin serves as the analog input Channel 3 It can be configured as general purpose digital input 2 2 6 AN2 PAD2 This pin serves as the analog input Channel 2 It can be configured as general purpose digital input 2 2 7 AN1 PAD1 This pin serves as the analog input Channel 1 It can be configured as general purpose digital input 2 2 8 ANO PADO This pin serves as the analog input Channel 0 It can be configured as general purpose digital input M MOTOROLA 11 ATD 10B8C Block User Guide V02 08 2 2 9 VRH VRL VRH is the high reference voltage and VRL is the low reference voltage for ATD conversion 2 2 10 VDDA VSSA These pins are the power supplies for the analog circuitry of the ATD 10B8C block 12 M MOTOROLA ATD_10B8C Block User Guide V02 08 Section 3 Memory Map and Register Definition 3 1 Overview This section provides a detailed description of all registers accessible in the ATD 10B8C 3 2 Module Memory Map Table 3 1 gives an overview on all ATD 10B8C registers Table 3 1 Module Memory Map arte Use Access ATD Control Register 0 ATDCTLO R _01 ATD Control Register 1 ATDCTL1 R 02 ATD Control Register 2 ATDCTL2 RAN ATD Control Register 3 ATDCTL3 R W 04 ATD Control Register 4 ATDCTL4 RAN ATD Control Register5 ATDCTL5 R W ATD Status Register 0 ATDSTATO R W 07 Unimplemented ATD Te
30. thor Description of Changes 00 00 27 10 2000 Initial SRS2 release 01 00 06 06 2001 N Updated the description of ATDDIEN and PORTAD1 register 01 10 16 06 2001 Made SRS2 Compliant V02 00 a Reworked whole document to make it more user friendly WOOT and nales have been hidden V02 02 5 Sept 2001 Corrected sampling phase description other minor corrections V02 03 8 Nov 2001 8 Nov 2001 Corrected AWAI bit description V02 04 16 Jan 2002 Syntax corrections V02 05 8 Mar 2002 Removed document number from all pages except cover sheet V02 06 11 Apr 2002 11 Apr 2002 Documented special channel conversion in ATDTEST1 register V02 07 22 Apr 2002 22 Apr 2002 Corrected Table Available Result Data Formats V02 08 16 Aug 2002 FIFOR flag corrected clearing mechanism B Table 0 1 Revision History 2 M MOTOROLA ATD_10B8C Block User Guide V02 08 Table of Contents Section 1 Introduction MEC i11 Orat 9 1 2 Kes Oe ee OP Tea Ted RORIS bee Ree EE ey Esai S on Geese 9 1 3 Mod s OF Operation sa 2 05 dae SLU obe eov eu tie eA eM a rM ed 9 1 3 1 Conversion MONS Da is 9 1 3 2 MCU Operating Modes een dust eR nhe ab bape 9 War Block Te eet Re CE ee ee d 10 Section 2 Signal Description JOVODIBW SIAN qe PIE ee eee
31. vide by 10 20 MHz 5 MHz divide by 12 24 MHz 6 MHz divide by 14 28 MHz 7 MHz divide by 16 32 MHz 8 MHz divide by 18 36 MHz 9 MHz divide by 20 40 MHz 10 MHz divide by 22 44 MHz 11 MHz divide by 24 48 MHz 12 MHz divide by 26 52 MHz 13 MHz divide by 28 56 MHz 14 MHz divide by 30 60 MHz 15 MHz divide by 32 64 MHz 16 MHz divide by 34 68 MHz 17 MHz divide by 36 72 MHz 18 MHz divide by 38 76 MHz 19 MHz divide by 40 80 MHz 20 MHz divide by 42 84 MHz 21 MHz divide by 44 88 MHz 22 MHz divide by 46 92 MHz 23 MHz divide by 48 96 MHz 24 MHz divide by 50 100 MHz 25 MHz divide by 52 104 MHz 26 MHz divide by 54 108 MHz 27 MHz divide by 56 112 MHz 28 MHz divide by 58 116 MHz 29 MHz divide by 60 120 MHz 30 MHz divide by 62 124 MHz 31 MHz divide by 64 128 MHz 32 MHz M MOTOROLA 19 ATD 10B8C Block User Guide V02 08 NOTE 1 Maximum ATD conversion clock frequency is 2MHz The maximum allowed Bus Clock frequency is shown in this column 2 Minimum ATD conversion clock frequency is 500KHz The minimum allowed Bus Clock frequency is shown in this column 3 3 6 ATD Control Register 5 ATDCTL5 This register selects the type of conversion sequence and the analog input channels sampled Writes to this register will abort current conversion sequence and start a new conversion sequence 05 7 6 5 4 3 2 1 0 s DJM DSGN SCAN MULT CB CA RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 6 ATD Control
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