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C6713Compact-2 micro-line Busmaster User's Guide

1. H Date 25 June 2012 y USER S GUIDE Doc no C6713Cpt 2_ml_bm_ug MICRO LINE BUSMASTER BSP Iss Rev 1 0a OPSys FOR THE C6713COMPACT 2 Page 37 while 1 int iPackets packet counter display iteration count DebugOutWordHex uiTxTestCount DebugOutConstString Nr DebugFlush causes a gap in the data stream between each packet burst uiTxTestCount The small gaps between the packets show the amount of bus time that is kept free for asynchronous transactions Please note when running continuous receive operation the incoming bandwidth must be limited by using a smaller packet size e g 256 quadlets when a second C6713Compact 2 running isotst is used as data generator Otherwise FIFO overflow errors will occur llrirespy Recorder E E Ee x File Search FireSpy Recorder View OOO T e sn o c mm 20312368 ot 128 MB A Q 1365 zie 12695975 vf it Is KS ee Time View X HH D poit E E E s u3 eg Packets View X packet event size source destination label Packet Type wem Bil Streaming 4108 ch 1 SE GEET EE E Wi Streaming 4108 ch 1 SB ream 4108 ch 1 C 300b C 200M A00Mb C 800M Wi Streaming ch Bi Streaming 4108 chi Wi Streaming 4108 ch1 Fields Layout B Streaming 4108 ch 1 Bi Streaming 4108 ch 1 data length fes channel ode sy Bi Streaming 4108 ch 1 01000 D 0x01 Dx 0x0 Bi Streaming 410
2. Date 25 June 2012 Doc no C6713Cpt 2_ml_bm_ug Iss Rev 1 0a orsys Page i4 Q User s Guide micro line Busmaster BSP For the C6713Compact 2 Orsys Orth System GmbH Am Stadtgraben 25 88677 Markdorf Germany http www orsys de fy USER S GUIDE Date 25 June 2012 A MICRO LINE BUSMASTER BSP Hadr d E orsys FOR THE C6713COMPACT 2 Page 2 Contents MELIUS HQ 5 1 1 Document OrgantzatiQli iso cero rar Fami eege ebe E Re uaa iir sanpun unne Gao x dUKR RM E CREE DA E dada 5 1 2 DOCUMENTATION e ET 5 1 3 Notational Conventions ausis cenco cnra ed in ROLE GO E SER EE RE REOR ERR ODDO DEREN EAD EO D 5 UE Trademarks EE 6 Lea Revision PISTONS sinsntnteaiiinsiedanccdeweivaenicaseteualit CREER FER UID DER ca EE Eege 7 Z INTRODUCTION e 8 3 FUNCTIONAL OVER VIEW cinaee esca ctas tapa ea gue rH oes Saa pa eo na eH See 9 3 4 micro line Peripheral Interface EEN 9 3 2 Host Port Interface HPl iiiter cibi o Ria EO CO I rni e Rb n a Edo Kino ad nd 11 3 3 IEEET394 Data Streaming anres ess cix bikes da dis er pond ana EE Ra ERE D ra KE dE End b io e e ew li Dena 13 4 ADDRESS MAP 52 23 AIR ARRA IRONIA RA RAM CPAADEM M a Aa AA eee 15 4 31 C 6713Compact 2 Address Map erre nne n terni r rana rr ra ra En nara n E Ren FR R3 FRE an R oan 15 4 2 Address Map of the micro line Busmaster BSP c
3. Keys to type on the keyboard are shown with a surrounding frame e g F 10 If a sequence of keys is to be typed the keys are separated by commas F10 Ld If two keys must be pressed simultaneously the key combination is shown with a plus sign Alt F The members of a bit field or a group of signals are numbered starting at zero which is the least significant bit Example CFG 4 0 identifies a group of five signals where CFGO is the least significant bit and CFGA is the most significant bit If necessary numbers are represented with a suffix that specifies their base Example 12AB46 is a hexadecimal number base 16 hexadecimal and is equal to 477940 The bit fields of a register are displayed with the most significant bit to the left Below each bit field is a description of its read write accessibility and its default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C D E F G H l J K L N O r w Q r w 0 r w 0 r w 0 r w 0 r w 0 r w 0102 r 0 r wc 0 w r w 0 rc 0 r w 0 r w 0 accessibility and default value legend r bit is readable rc this bit is cleared after a read rw bitis readable and writeable reading yields the previously written value unless otherwise specified Ww bit is writeable read value is undefined wc writing a 1 to this bit clears it w 0 bitis write only reading always yields 0 0 default value 1 4 Trademarks Tl Co
4. Modified address map with CE2 configured for 16 bit Usage notes e Each of CS1 CS3 is organized as 64K by 16 bit e EEE1394 data streaming is not possible 32 bit wide data register can t be accessed A000 0010 A000 FFFF GE 0000 A001 FFFF GE 0000 A002 EE CE2 S RUE A EEE 0000 A003 FFFF A004 0000 A004 FFFF __ A005 0000 AFFF FFFF 256M 320K Table 7 Modified address map with CE2 configured for 8bit Usage notes e Each of CS1 CS3 is organized as 64K by 8 bit e EEE1394 data streaming is not possible in 8 bit mode e Setting up timing of the peripheral interface must be done before changing bus width CE2 must be configured for 16 or 32 bits VE RUE BOR FERE 0000 B007 FFFF BOO 0000 008 FFFF 0000 BOOB FFFF BOOC 0000 DOE FFFF Joes E010 0000 801s FEFE 0000 B013 FFFF EE 0000 BO1F FFFF 768K reserved B0 0000 8020 660 0000 B020 000F E 0010 BFFF FFFF Table 8 Modified address map with CE3 configured for 32 bit Usage notes e Each of CS4 CS7 is organized as 64K by 32 bit e FPGA registers are intersected with 16 bits of unused data Q USER S GUIDE MICRO LINE BUSMASTER BSP rsys FOR THE C6713COMPACT 2 Date 25 June 2012 Doc no C6713Cpt 2 ml bm ug Iss Rev 1 0a Page 17 micro line CS4 16 bit micro line CS5 16 bit B003 0000 B004 FFFF Jor micro line CS6 16 bit B004 0000 B005 FFFF B005 0000 B007 F
5. O IIS AM D22 I O Z A22 O HRD I INR O SE D23 l O Z A23 O HWR I RSV R W O EPO DU 2472 4441 61 P D24 VO VAI FRN OZ ETEO ME D25 VO Z VIGO IHINT O Z RSV ZZ A D27 VO Z IDLO RSV RSV CO i MAGEE D28 l O Z ISHII RSV RSV A709 VPI D29 VO Z VIGGO RSV RSV RDY I WMH M D30 OG Eat RSV RSV HOLD l 32 D31 VO Z ZG AUG RSV RSV HOLDA OZ Table 14 Pinout of micro line connectors A through E EM C5 o no h5 5 NINN h9 h5b ND 2 2 a clr oo 1 O O1 BH OO NP O O Co H O O1 A Co ho O e Connector Table 15 Pinout of micro line connector X fy Date 25 June 2012 USER S GUIDE Doc no C6713Cpt 2 ml bm ug MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 23 8 Individual Signal Description This chapter describes each signal that is defined by the micro line busmaster BSP The remaining signals shaded entries in Table 14 are described in the C6713Compact 2 hardware reference guide 1 8 1 micro line Peripheral Interface 8 1 1 Connector A D 31 0 These are the bi directional data bus lines of the micro line peripheral interface They are activated during the strobe phase of an access to the micro line peripheral interface When inactive the data bus is in high impedance state 8 1 2 Connector B A 15 0 These are the address bus output lines of the micro line
6. 0a orsys FOR THE C6713COMPACT 2 Page 22 7 Signals on the micro line Connector This chapter lists the signals on the micro line connectors that are defined by this BSP For a description of the remaining signals and connector locations please refer to 1 Entries labeled RSV are connected to the FPGA but are not used They have pull up termination in the FPGA Shaded entries are provided by basic board hardware independent of the micro line busmaster BSP BB C DO I O Z A0 O HDO O Z RSV Eeer D1 I O Z A1 O HD1 1 0 2 RSV Fouer D2 I O Z A2 O HD2 UO RSV Wwe aAA D3 I O Z A3 O HD3 1 0 2 RSV WAKO D4 I O Z A4 O HD4 1 0 2 RSV MAGI D5 I O Z A5 O HD5 1 0 2 RSV MAES D6 I O Z A6 O HD6 UO RSV Ee D7 l O Z A7 O HD7 1 012 RSV FARII D8 I O Z A8 O HD8 VO Z RSV EE D9 I O Z AQ O HD9 O Z ICS1 O A D10 VO Z A10 O HD10 I O Z ICS2 O LM RAT D11 VO Z A11 O HD11 VO Z CS3 O A D12 VO Z A12 O HD12 V O Z ICS4 O EAT WI AAA D13 O Z A13 O HD13 uo ICS5 O BI AGOR MA D14 VO Z A14 O HD14 O Z ICS6 O ESM D15 VO Z A15 O HD15 V O Z ICS7 O A D16 VO Z A16 O HAO 1 EST INTA LB AAA D17 VO Z A17 O HA1 I JET WI 777 IBM INL D18 O Z A18 O HA2 I EXT_INT6 0 VAALA CIEL D19 O Z A19 O RSVD IEXT INTT 0 LLLA EAD A D20 V O Z __A20 O HR W I NMI I LIL OLLIE A D21 VO Z __A21 O HCS I RD
7. 2012 fy USER S GUIDE Doc no C6713Cpt 2 ml bm ug MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 30 11 2 1 Host Port Connection with Common Strobe and Direction Select An example for connecting a CPU with common strobe signal to the C6713Compact 2 is shown below C6713Compact 2 CPU amp glue logic with common strobe host port interface CS decoded STRB Figure 7 Host port connections when using a single strobe The following steps have to be performed e All signals must be connected directly to the respective signal of the C6713Compact 2 except STRB which must be connected to HRD e HWR must be pulled high e HRDY might need to be inverted depending on the host CPU type e Address offset between HPI registers depends on the host CPU type The host CPU uses the following address map Table 19 HPI register address map 11 2 2 Host Port Connections with Separate Strobe Signals An example for connecting a CPU with separate strobe signals to the C6713Compact 2 is shown below C6713Compact 2 CPU amp glue logic with separate strobe host port interface CS decoded Figure 8 Host port connections when using separate strobe signals fy J Date 25 June 2012 M USER S GUIDE Doc no C6713Cpt 2 ml bm ug MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page WEN The following st
8. BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 25 has small delay to the DSP s EMIF clock and switches at the same time as all other outputs of the peripheral interface see section 10 1 for timing specifications Please note that the frequency of this signal does not affect any timing of the TMS320C6713 EMIF 8 2 Host Port Interface 8 2 1 Connector BB HD 15 0 These pins are the bi directional data bus of the host port interface Data can be directly written to or read from the whole address space of the TMS320C6713 DSP The data lines are only activated when a valid host port access is detected see Table 2 Otherwise HD 15 0 are in high impedance state HA 2 0 These pins are the host port address inputs They select which 16 bit halfword and which HPI register is currently accessed by the host The register map of the host port is given in Table 3 Connection examples for the host port can be found in chapter 11 2 HCS This pin is the chip select input of the host port The host must set HCS low in order to enable host port accesses HCS must be low during the whole access HRD This pin is the read strobe input of the host port It should be connected either to the host s read strobe or to the host s common strobe Please refer to HPI access decoding in Table 2 and the connection examples in chapter 11 2 for details HWR This pin is the write strobe input of the host port It should
9. Dorada e ib ERR DEED RR C E Eau 28 11 CONNECTION EXAMPLES 5602 62s Rn ERS n RR FH REDE ERO RARUS ono REX XR REP RRDR Rer nnmnnn nnmnnn nenn 29 11 1 Peripheral Interface ET 29 11 2 Host Port Interface useassiciasesexbUsk PR ek S us seet DUI Ra dr LIS UFNEINP DEAE UE Mc EEN ren Ra EE 29 11 2 1 Host Port Connection with Common Strobe and Direction Select 30 11 2 2 Host Port Connections with Separate Strobe Signals seoeeseseeeeeseesseereernesesrrerrrrresssene 30 11 2 3 Host Port Connections with Separate Strobe Signals Alternative Method 31 12 APPLICATION EXAMPLES eeeesseseeeseeeeeeeeee eee nnn nnn n nnne n nnn nnn nnn nnn nnn nnns 32 12 4 Default FFS Application toggle led eeeeeeeeeeeeeerrneneeeeeeenennnnnnn 32 12 1 1 Loading and Accessing the FPGA toggle led Tool e sessesseseeeeeesessseererrnessssrsrrrrrenssene 32 12 1 2 Micro line Peripheral Interface tte tente ttn tn ean 32 12 1 3 General IEEE1394 Operation asynctst eeeeeessseeeeeeseeenenne 33 12 1 4 Software Streaming isotst cctciccicaracachetueotnch xadaiunuunteeensntenradasmonte asa i Te atun Seduta crab 35 13 LIST OF ABBREVIATIONS AND ACRONYMS USED IN THIS DOCUMENT 38 14 LITERATURE REFERENCES icis eu tie tia SS LEE ti MD MIS UR CAS Es DAI aM cA RM M DE 40 my USER S GUIDE is no v o e MM A
10. GUIDE Doc no C6713Cpt 2 ml bm ug MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsySs FOR THE C6713COMPACT 2 Page 5 1 Preface 1 1 Document Organization This document is organized as follows e Chapter 1 gives some general information such as notational conventions and documentation overview Chapter 2 introduces the micro line busmaster BSP Chapter 3 gives an overview of the components that make up the BSP Chapter 4 lists the address ranges implemented by the FPGA Chapter 5 describes the FPGA registers Chapter 6 explains the required EMIF settings Chapter 7 gives an overview of the signals available at the micro line connector Chapter 8 describes each signal in detail Chapter 9 lists the electrical characteristics of the available signals Chapter 10 lists signal timings Chapter 11 gives examples for connecting hardware to the C6713Compact 2 Chapter 12 describes the application examples available with this BSP Chapter 13 lists abbreviations and acronyms used in this document Chapter 14 lists further documentation 1 2 Documentation Overview This chapter lists the documentation from Orsys that is shipped together with software development kits that contain the micro line busmaster BSP Further documents from other vendors are listed in chapter and are referenced throughout the document in square brackets C6713Compact 2 Hardware Reference Guide 1 ce713cpt 2 nrg pat Describes the basic hardware without any FPGA functionality of th
11. Rev 1 0a fy USER S GUIDE Date 25 June 2012 orsys FOR THE C6713COMPACT 2 Page 26 8 3 Other Signals ISHZ Test pin for factory tests When SHZ is activated driven low below listed micro line pins are switched to high impedance state D 31 0 A 23 0 CS 7 1 RD WR R W STRB EMIF_CLK HRDY HINT HOLDA The SHZ input is not designed for use during normal operation and should be left unconnected A pull up resistor is implemented by the FPGA RSV Signals listed as RSV in Table 14 and Table 15 are FPGA UO pins not used by this BSP The FPGA pulls these pins high regardless whether the FPGA is configured or not Customers should leave these pins unconnected fy d USER S GUIDE Date 25 June 2012 d Doc no C6713Cpt 2_ml_bm_ug A MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 27 9 Signal Levels All signals described in this document use LVTTL signal levels The recommended operating conditions are listed below parameter value min max logic low input voltage 0 5V 08V logic high input voltage 20V 36V logic low output voltage 0 4 V logic high output voltage 24V Table 16 Recommended operating conditions 1 at 8mA load 12mA for EMIF_CLK oy J Date 25 June 2012 a D USER S GUIDE Doc no C6713Cpt 2_ml_bm_ug AU MICRO LINE BUSMASTER BSP Iss Rev 1 0a rsys FOR THE C6713COMPACT 2 Page 28 10
12. Signal Timings All timing specifications in this chapter apply to FPGA version 3 0 The timings are based on the FPGA design and also include some margin for PCB trace delay 10 1 micro line Peripheral Interface All inputs and outputs of the micro line peripheral interface are synchronized to the EMIF clock This gives a well defined timing with minimum skew min 2ns 2ns 81ns E HEN p 23 ns Parameter EMIF_CLK valid after rising edge of DSP s ECLKOUT all other outputs valid after rising edge of DSP s ECLKOUT read data setup relative to rising edge of STRB RD WR read data hold relative to rising edge of STRB RD WR RDY setup relative to rising edge of STRB RD WR 2 ns 48 ns RDY hold relative to rising edge of STRB RD WR 42 ns delay from EXT_INT 7 4 NMI to DSP interrupts delay between DSP and HOLD HOLDA Total EMIF cycle time for 1 1 1 setup strobe hold access Total EMIF cycle time for 7 7 7 access immediate ready Total EMIF cycle time for 7 7 7 access 1 clock not ready 23 ns 120 ns 300 ns 310 ns Table 17 Peripheral interface timings 10 2 Host Port Interface The host port interface is handled by pure combinational logic Therefore the timings of the DSP s HPI must be considered in conjunction with the timings specified below Parameter min Delay HPI strobe signals from connector to DSP Skew between strobe signals Delay HPI select signals from connector to DSP Skew bet
13. accesses are not supported Therefore no byte select control signal is provided on the micro line bus Furthermore no multiplexed data and address busses are supported The DSP s control signal HAS is not used The FPGA connects the HPI signals form the micro line connectors to the DSP s HPI using combinational logic adding some delay The resulting host port timings of the C6713Compact 2 are described in chapter 10 2 Further details about TMS320C67 13 HPI can be found in 11 C6713Compact 2 data lines HD 15 0 A address lines HA 2 0 Control signals host port HCS interface interrupt HINT _ gt Figure 4 Available HPI signals The host port interface on the micro line connectors consists of the following signals HDS 2 1 read access only HDS 2 1 write access only host port ready output HRDY host port interrupt output HINT Table 1 HPI signals F Date 25 June 2012 USER S GUIDE Doc no C6713Cpt 2 ml bm ug ND MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 13 There are two different host port hardware operation modes possible The first one allows to connect a host with separate strobe signals to the board using the signals HCS chip select HRD read and HWR write while HR W read write must also be connected to HWR The second one allows to connect a host with common strobe to the board usi
14. and a direction select signal should be used with R W and STRB instead R W STRB These are the read write R W and the active low strobe STRB output lines of the micro line peripheral interface They indicate a read cycle R W high and STRB low or a write cycle R W low and STRB low R W is valid throughout the entire access cycle from start of setup phase until end of hold phase STRB is valid during the strobe phase of an access These signals should be used to connect peripherals that require a common strobe signal and a direction select signal Peripherals with separate read and write strobes should be used with RD and WR instead RDY fy USER S GUIDE Date 25 June 2012 d Doc no C6713Cpt 2_ml_bm_ug A MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 24 This pin is the active high ready input of the micro line peripheral interface RDY is sampled 4 clocks before the end of the strobe phase If RDY is sampled low the strobe period is extended by one EMIF clock and RDY is sampled again If RDY is sampled high the strobe period ends If no bus cycle extension is required RDY should be left unconnected The necessary pull up resistor is provided on the C6713Compact 2 This input can be used by e very slow hardware whose timing exceeds the maximum timing adjustable in the CSCTL register e amixture of fast and slow peripherals where the access timing is
15. be connected either to the host s write strobe or to a permanent high level when using a common strobe Please refer to HPI access decoding in Table 2 and the connection examples in chapter 11 2 for details HR W This pin is the host read write select input The host must set HR W high in order to read and low in order to write on the HPI A host without a read write select output can connect HR W to HWR or use an address line for this function Please refer to HPI access decoding in Table 2 and the connection examples in chapter 11 2 for details HRDY This pin is the ready output of the host port When active high HRDY indicates that the HPI is ready for a transfer to be performed When inactive low HRDY indicates that the HPI is busy completing a read access a previous HPI data register read pre fetch or a write access HRDY is always high when HCS is high Please note that HRDY is inverted with respect to the DSP s low active ready output HINT This pin is the interrupt output of the host port interface This interrupt is controlled by the HINT bit in the HPI control register It is cleared set to high level when the processor is reset The TMS320C6713 DSP can trigger an interrupt to the host by setting the HINT bit in the HPIC register An interrupt is pending when HINT is low The host can clear the interrupt after processing by writing a 1 to the HINT bit Doc no C6713Cpt 2_ml_bm_ug MICRO LINE BUSMASTER BSP Iss
16. busmaster BSP however using the default setting does not give optimum performance so the user may want to modify EMIF settings How to program this is shown in the examples on the distribution media and in the board library documentation The actual timings depend on which parts of the BSP are being used There is an absolute minimum which can be used for register accesses only excluding the peripheral interface and streaming data When using this setup accesses to the FPGA may include a one clock wait cycle which slows down operation There is also a recommended minimum which allows register accesses without wait states and also allows accessing the peripheral interface which always inserts waitstates For reading streaming data from the FIFO the entire cycle time must be increased by 1 clock to allow FIFO data to update in time when doing back to back read cycles Table 13 lists the default timings set up by the Flash File System and the timings required for operation of the micro line busmaster BSP Required setting in EMIF clocks Ls UE EE parameter minimum peripheral interface read sep 5 1 2 2 04D 0 3 29 a a a Table 13 Timings for the CE2 and CE3 address spaces Note Setting up EMIF timings is done together with setting up the memory type which in turn defines the actual bus width fy j USER S GUIDE Date 25 June 2012 d Doc no C6713Cpt 2_ml_bm_ug AU MICRO LINE BUSMASTER BSP Iss Rev 1
17. configured in CSCTL for the fast peripherals but the slow peripherals can extend the access for their timing requirements This way the slow peripherals don t slow down accesses to the fast ones HOLD HOLDA These signals can be used by an external busmaster to access on board peripherals The busmaster function is not supported by this BSP Therefore these signals should be left unconnected EXT_INT 7 4 These are the four maskable interrupt input lines of the micro line peripheral interface They can be used as interrupts or for DMA synchronization In default configuration all interrupts are triggered on the falling edge of the interrupt signal in contrast to the default polarity of the DSP interrupt lines They can be individually configured to be either falling edge triggered or rising edge triggered This is described in chapter 5 2 5 Level triggering is not possible at the TMS320C6713 DSP To enable interrupts from the micro line peripheral interface the interrupts must be enabled by the DSP Further EXT_INT6 and EXT_INT7 are routed over the PLD of the C6713Compact 2 and must also be enabled there This is described in 1 The line status of EST INT7 and EXT_INT6 can be polled by PLD status bits see also 1 for a description Please note that other interrupt sources exist on the C6713Compact 2 for EXT_INT6 and EXT_INT7 Before designing peripheral hardware to use a specific micro line interrupt please check whic
18. depend on the micro line busmaster BSP It can also run on the basic board hardware without the FPGA being loaded To start this example you have to e Connect the RS 232 interface of the C6713Compact 2 to your development PC Load the asynctst example to the C6713Compact 2 using the fload6x utility see 2 Power off the C6713Compact 2 Start a terminal program such as Hyperterminal Power on the C6713Compact 2 Now you see the startup message of asynctst in the terminal window and the red LED of the C6713Compact 2 starts to toggle asynctst consists of 3 modules e asynctst c contains initialization command interpreter main loop and the asynchronous transactions e init c contains initialization of the C6713Compact 2 e cfgrom c IEEE1394 configuration ROM contents for this example The example initializes the C6713Compact 2 reads the board serial number from the EEPROM and initializes the IEEE1394 API API operation is started and an address range for incoming transactions is allocated Then a main loop is entered The main loop handles bus resets and user commands from RS 232 Supported commands are 1 20r 4 set the speed to S100 S200 or S400 b generate a bus reset C switch between counter data and random data list available IEEE1394 devices S set up remote device and packet size r reset random number generator hor display help page all others start a data transfer Incoming transactions are displayed using the notificat
19. peripheral interface They are always active and carry a valid address during the entire access cycle from start of setup phase until end of hold phase A 23 16 These address lines are not used in this BSP They are always driven low by the FPGA 8 1 3 Connector D CS 7 1 These are the seven active low chip select output lines of the micro line peripheral interface They pre select which external peripheral component is accessed and are valid during all three phases of the access from start of setup phase until end of hold phase The seven peripheral address spaces are located in the processors CE2 and CE3 address spaces The chip select lines CS1 CS3 refer to the EMIF CE2 area of the processor and CS4 CS7 refer to the EMIF CE3 area of the processor This allows to connect two different I O areas with different bus width The locations of the seven peripheral address spaces are shown in chapter 4 2 RD WR These are the active low read strobe RD and write strobe WR output lines of the micro line peripheral interface They indicate a read cycle RD or a write cycle WR The strobe signals are active during the strobe phase of an access In case of a read cycle data is sampled at the rising edge of RD Write data is valid throughout the entire access cycle from start of setup phase until end of hold phase These signals should be used when separate read and write strobes are required Peripherals with a common strobe
20. 8 ch1 header CRC Bi Streaming 4108 ch 1 SE OxECD998F5 Bi Streaming 4108 ch 1 SB data E Streaming 4108 ch 1 000000400 B Streaming 4108 ch 1 data Bi Streaming 4108 ch 1 D 00000401 Bi Streaming 4108 ch 1 HN Bi Streaming 4108 ch 1 e Gtreamina Aina ch D Acknowledge code none Figure 13 Recorded isotst data Modifications in isotst cdb tcf isotst cdb tcf is derived from C6713CPT_225MHz_32MB cdb tcf Scheduling HWI Hardware Interrupt Service Routine Manager HWI INT6 function _LynxHALNode lSR Dispatcher Use Dispatcher not selected Scheduling TSK Task Manager Insert a task with the following properties General comment task containing the main loop Function Task function _TASK_WorkingThread task object renamed to TSK_work 2 Orsys H Date 25 June 2012 USER S GUIDE Doc no C6713Cpt 2_ml_bm_ug MICRO LINE BUSMASTER BSP Iss Rev 1 0a FOR THE C6713COMPACT 2 Page 38 13 List of Abbreviations and Acronyms Used in This Document API ASCII ATF BSP CCS CE space COM configuration ROM CPU CRC CSL CSR CTS DCAM DM port DMA DSP DSP BIOS e g EDMA EMI EMIF FFS FIFO Flash FPGA GEL HPI I F I O i e IEEE IEEE1394 ISR IIDC IIDC DCAM isochronous JTAG KB application programming interface american standard code for information interchange a simple widely us
21. ASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 233 e A peripheral device is connected to CS1 e Two locations are decoded by using the micro line address bus AO 0 control and status register 8 bit wide DO indicates data is available AO 1 data register 16 bit wide CS1 is located within the CE2 address space which is by default configured for 32 bit wide memory Therefore each address within CS1 contains 32 bits and the DSP address offset between subsequent locations is 4 bytes The code example below shows how to define access macros to the peripheral and how to access the peripheral include C6713Cpt 2 ml bm h micro line busmaster BSP definitions define MY CSR volatile char C6713Cpt_CS1 BASE 0 define MY DATA volatile short C6713Cpt CS1 BASE 4 if MY CSR amp 1 check some status bit for data availability pData MY DATA read some data 12 1 3 General IEEE1394 Operation asynctst The distribution media of development kits with IEEE 1394 support contains an application example called asynctst This example shows how to do incoming and outgoing asynchronous transactions An overview of asynchronous transactions can be found in 5 The user interface of the application example is realized over the RS 232 interface A terminal e g a PC running Hyperterminal must be connected to the RS 232 interface Please note that this application example does not
22. CLK B0100004 RESERVED CLK_EN RESERVED INT_CTL B0100006 RESERVED STR INTSEL ENZ POL EINT6 POL EINT5 POL ENT4 POL NMI POL RESERVED Table 11 FPGA register bit summary in default EMIF configuration 5 2 1 Chip Select Control Register This register controls timing of the peripheral interface 15 14 13 12 11 10 9 8 6 5 7 RESERVED SETUP r 0000000 r w 001 r w 001 r w 001 fy USER S GUIDE Date 25 June 2012 d Doc no C6713Cpt 2_ml_bm_ug A MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 19 SETUP controls the number of EMIF clocks for the setup phase Default value is 1 clock a value of 0 is treated as a value of 1 Allowable range is 1 to 7 STROBE controls the number of EMIF clocks for the strobe phase Default value is 1 clock a value of 0 is treated as a value of 1 Allowable range is 1 to 7 HOLD controls the number of EMIF clocks for the hold phase Default value is 1 clock a value of 0 is treated as a value of 1 Allowable range is 1 to 7 5 2 2 FPGA Version Register This register describes the FPGA version and revision Application software can use this register to check if the correct FPGA code is loaded This register is read only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VERSION REVISION r 0000001 1 r VERSION This bit field describes the FPGA version Each BSP has a unique version This BSP uses version number 3 The ver
23. FFF B008 0000 B008 0003 B008 0004 BFFF FFFF Table 9 Modified address map with CE3 configured for 8 bit Usage notes Each of CS4 CS7 is organized as 64K by 8 bit Access to FPGA registers is limited The following bit fields are no longer accessible O O Register VERSION bit field VERSION Register INT_CTL bit field DM_INT fy 7 Date 25 June 2012 USER S GUIDE Doc no C6713Cpt 2 ml bm ug LJ MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 18 5 Register Description 5 1 IEEE1394 Streaming Registers The registers used for IEEE 1394 streaming are documented in 3 One additional register provides access to streaming data This register must always be accessed as 32 bits The table below shows the register locations Address hex A000 0000 A000 0004 A000 0008 STR HDR H A000000C 16 bit A000 0010 A000 0014 A000 0018 A000 001C A000 0020 A000 0024 A000 0028 A000 002C A000 0030 A000 0034 STR DATA A000 0038 A000 003C 5 2 FPGA Registers Table 10 lists the register addresses Default configuration is listed in bold description 8 bit bus width 16 bit bus width controls chip select timing FPGA version LED control controls clock output Table 10 FPGA register locations TESTOR Li Eee Ee ee Sa HEH CSCTL 0100000 RESERVED SETUP STRB VERSION B0100000 VERSION REVISION B0100002 RESERVED LED GREEN LED RED RESERVED EMIF_
24. FOR THE C6713COMPACT 2 Page 32 12 Application Examples The following application examples are provided with the micro line busmaster BSP toggle_led Basic example which is also the default application in FFS placed in the BSP for historical reasons only toggle_led_fpga Toggles all four user controllable LEDs 2x PLD and 2x FPGA and shows how to configure load the FPGA asynctst Shows how to implement IEEE1394 asynchronous transactions isotst Shows how to implement IEEE1394 isochronous streaming 12 1 Default FFS Application toggle_led This application example is not really specific to the micro line busmaster BSP It was put into the BSP distribution for historical reasons toggle_led is the default application that is stored in the FFS during production It simply enables CTS resets for connecting with the FFS utilities and toggles the red LED 12 1 1 Loading and Accessing the FPGA toggle_led_fpga The distribution media contains an application example called toggle_led_fpga This example shows e How to load the FPGA from within application software using the board library e How to access the FPGA registers using the LED control register Please note The FPGA can also be loaded through the Flash File System see 2 for details To start this example you have to e Connect the RS 232 interface of the C6713compact 2 to your development PC e Load the toggle_led_fpga example to the C6713Compact 2 using th
25. Figure 27 shows a sample session where isotst is set up for a frame of 10 packets with maximum size and then a single transmission is started 1394 embedded API test application C6713Compact ISOTST Vr 1 1 Nov 21 2003 18 49 38 CPU clock 0227174400Hz FPGA Version 003 revision 000 OK HAL version 17030523 API version 17030523 Default packet size is 0001h quadlets Default frame size is 0001h quadlets Default speed is S100 Node vendor ID and serial number 00B02A00 000019AF select speed 1 2 or 4 4 new packet size in quadlets 1024 new frame size in quadlets 10240 speed 400MBIT Quadlets per Packet 0400 Quadlets per Frame 2800 Setup finished transmit test 0000 transmit operation finished Atygrtsoo Figure 12 Sample isotst session Examples for setting up the streaming registers are given in 4 Figure 13 shows a recording of the generated data on the bus recorded with a bus analyzer from an earlier version of isotst The data was generated with the same settings as the sample session from Figure 12 with the difference that counter data and repetitive transmit key T is used Random data would have caused larger gaps between the bursts since it is calculated anew for each iteration Each of the displayed packet bursts was generated by one execution of the transmit loop The gaps between the bursts are caused by the iteration count display at the beginning of the transmit loop transmit loop
26. NTSEL interrupt line EXT INT4 EXT INT5 EXT INT6 EXT INT7 EINT4 POL EINT7 POL NMI POL These bits control the polarity of the interrupt inputs at the micro line connector This gives the user more flexibility in connecting peripherals to the C6713Compact 2 By default all bits are O which selects falling edge triggered interrupts in contrast to the DSP interrupts which are rising edge triggered by default If an interrupt source with rising edge triggered interrupts is connected to the micro line bus the corresponding polarity bit needs to be set Please do not change the interrupt polarity in the DSP s registers The micro line interrupts trigger the corresponding interrupts on the DSP However some more interrupt sources exist on the C6713Compact 2 Therefore application software must check all possible interrupt sources The other interrupt sources are described in 1 EINTx POL NMI POL micro line interrupts falling edge triggered g ccr e rising edge triggered fy d USER S GUIDE Date 25 June 2012 d Doc no C6713Cpt 2_ml_bm_ug A MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 21 6 Setting up EMIF Timings This chapter shows how the EMIF must be set up for using the micro line busmaster BSP By default the Flash File System sets up the EMIF timings for the CE2 and CE3 address space to a slow and safe default This default works with the micro line
27. S 232 interface DSP peripherals These signals are always present independent of this BSP e micro line peripheral interface e host port interface HPI With the micro line peripheral interface peripherals can be easily connected to the C6713Compact 2 using no or only minimal glue logic The HPI allows other CPUs to access the C6713Compact 2 as a peripheral e g for inter processor communication The software interface is similar to those of the C6x1xCPU and the SC1394a so software can be easily ported from the micro line C6x1xCPU or the Complete II to the C6713Compact 2 This BSP should be chosen for e migration from previous micro line CPU modules to the C6713Compact 2 migration from the micro line Complete II to the C6713Compact 2 accessing micro line peripheral modules using the micro line peripheral interface to connect custom hardware software access to IEEE 1394 streaming data connecting the C6713Compact 2 to a host CPU using the DSP s HPI This document describes the features of the BSP solely The basic features FPGA independent of the C6713Compact 2 are documented in 1 Please note To use this BSP the FPGA must first be loaded with the appropriate code How to do this is shown in the application examples see chapter 12 1 1 gt Date 25 June 2012 LY USER S GUIDE Doc no C6713Cpt 2_ml_bm_ug MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 9 3 F
28. at www ti com TMS320C6000 Technical Brief Tl spru197 TMS320C6713 floating point digital signal processor data sheet Tl sprsise TMS320C6000 CPU and instruction set reference Tl seRu189 TMS320C6000 peripherals reference guide Tl sprui90 TMS320C6000 DSP Host Port Interface HPI Reference Guide Tl sprus7s TMS320C6000 DSP Multichannel Audio Serial Port McASP Reference Guide Tl spruo41 TMS320C6000 DSP Software Programmable Phase Locked Loop PLL Controller Reference Guide Tl spru233 TMS320C6000 DSP Inter Integrated Circuit I2C Module Reference Guide Tl spru175 TMS320C6713 Errata Sheet Tl sprzi91 Manual Update Sheet for TMS320C6000 Peripherals Reference Guide SPRU190 Tl sprzi22 application report Applications Using the TMS320C6000 Enhanced DMA Tl seRAese application report TMS320C621x TMS320C671x EDMA Queue Management Guidelines Tl SPRA720 How to Begin Development Today With the TMS320C6713 Floating Point DSP Tl sprasos Optimizing C Compiler user s guide Tl spruis7 TMS320C6000 Assembly Language Tools User s Guide Tl sPRu186 TMS320C62x C67x Programmer s Guide Tl spruigs TSB12LV32 data manual Tl suus336 IEEE Standard for a High Performance Serial Bus IEEE 1394 1995 IEEE Standard for a High Performance Serial Bus Amendment 1 IEEE 1394a 2000 Miska Kane Computing Ltd 1 Verdin Street Northwich Cheshire CW9 7BX Tel 44 0 1606 351006 Email sales kanecomputing com Web www kanecomput
29. ation By default the CE2 address space is configured for 32 bit bus width and CE3 is configured for 16 bit bus width This configuration allows a wide range of peripherals to be connected and can be used in almost any cases However in some special situations it may be necessary to change the bus width e g when e more than three 32 bit chip select lines are needed then CE3 must be configured to 32 bit so that CS 7 4 are also available for 32 bit peripherals e 8 bit peripherals are used and their registers must be accessible as a contiguous address space then one of the CE spaces must be configured for 8 bit width fy J Date 25 June 2012 T4 USER S GUIDE Doc no C6713Cpt 2 ml bm ug A MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsySs FOR THE C6713COMPACT 2 Page 16 Changing the bus width is done together with setting up EMIF timings see chapter 6 When the bus width is changed the address map base addresses and size of the address range also changes The resulting addresses are listed in the following tables Please note that reconfiguration of the bus width can disable access to IEEE1394 data streaming or to the FPGA registers as shown in the tables below address range hex size bytes A000 0000 A000 001F A000 0020 A001 FFFF 128K 16 CE2 POTAE 0000 A003 FFFF animo hs rrr 0000 A005 FFFF E 0000 A007 FFFF A008 0000 A009 FFFF ATOR Q009 AFFF FFEF 0000 AFFF FFFF Table 6
30. crocontroller interface Date transfers are buffered by an 8Kbyte FIFO The DSP accesses FIFO data through the STR_DATA register see chapter 5 1 for details Date 25 June 2012 UsER S GUIDE Doc no C6713Cpt 2 ml bm ug BJ MICRO LINE BUSMASTER BSP pp aped orsys FOR THE C6713COMPACT 2 Page 14 C6713Compact 2 TMS320C6713 DSP FPGA Xilinx Spartan 6 LX45 LX150 TSB41AB2 PHY TSB12LV32 LLC 1394 connector port 0 1394 connector port 1 Figure 5 IEEE1394 data streaming block diagram data mover The default transfer method for data streaming is isochronous streaming see 24 for details The FPGA can be set up to receive data payload only from the LLC so that user data can be transferred transparently without the need to insert or remove protocol information into or from the data stream On the other hand the FPGA can be configured for complete packet information This allows for example synchronization information to be inserted into the data stream or to synchronize an incoming image data stream to a frame boundary The respective data formats are shown in 4 For setting up and controlling data streaming the FPGA provides a set of registers These are summarized in chapter 5 1 and described in detail in 4 Please note that data streaming also requires set up of the LLC which is usually done using the IEEE1394 embedded API 5 How to set up isochronous streaming is shown
31. de Composer DSP BIOS and TMS320C6000 are registered trademarks of Texas Instruments Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries Hyperterminal is a trademark of Hilgraeve Inc oy J Date 25 June 2012 A USER S GUIDE Doc no C6713Cpt 2 ml bm ug MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 7 All other brand or product names are trademarks or registered trademarks of their respective companies or organizations 1 5 Revision History Changes First official release Examples BIOS configuration documented fy USER S GUIDE Date 25 June 2012 d Doc no C6713Cpt 2_ml_bm_ug A MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 8 2 Introduction This board support package allows to use the C6713Compact 2 as a conventional micro line CPU board It defines the function of the signals on the micro line connector similar to those of other micro line CPU modules such as the micro line C6211CPU board providing an easy to use peripheral interface Further this BSP provides FIFO buffered access to the data mover port of the IEEE1394 chipset for high speed IEEE 1394 data streaming The functions provided on the micro line connectors are e micro line bus master signals as mentioned in 1 reset outputs external flag I O R
32. e C6713Compact 2 Flash File System User s Guide 2 s us pat Documents the Flash File System Utilities Use this document for information on how to store files in Flash memory Board Library User s Guide 3 boardlib pae Describes the board library for the C6713Compact 2 Use this document for information on basic software development C6713Compact 2 DM Port Streaming Core User s Guide 4 cez13cpt 2 str core ug Describes the FPGA function block for IEEE 1394 software streaming IEEE1394 embedded API User s Guide 5 eubeaaea Ap ug Describes the software interface to IEEE 1394 1 3 Notational Conventions Names of registers bit fields and single bits are written in capital letters Example LLC VERSION Names of signals are also given in capital letters active low signals are marked with a at the beginning of the name Example RESETIN fy USER S GUIDE Date 25 June 2012 d Doc no C6713Cpt 2_ml_bm_ug A MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 6 Configuration parameters function names path names and file names are written in italic typeface Example dev id Source code command line examples and text to be entered are given in a small fixed width typeface Example int a 10 Menus and commands from menus and submenus are enclosed in double quotes Example Create a new project using the Create Project command from the File menu
33. e fload6x utility How to do this is described in the Getting started section of the respective development kit user s guide and also in 2 power off the C6713Compact 2 Start a terminal program such as Hyperterminal power on the C6713Compact 2 Now you see the startup message of toggle_led_fpga in the terminal window and the LEDs of the C6713Compact 2 start to toggle C6713Compact 2 application example toggle_led_FPGA Feb 12 2012 15 55 58 FPGA loaded Figure 10 Startup message of toggle_led_fpga This example contains two modules toggle_led_fpga c which contains example code itself and the FPGA code for the micro line busmaster BSP which is contained in ml_bm_foga_Ix lt DEV gt c where lt DEV gt is for the respective FPGA type e g 75 for an LX75 The project that builds the example has different configurations one for each supported FPGA type The generated code is therefore specific to a certain FPGA type 12 1 2 Micro line Peripheral Interface There is no specific application example for accessing peripherals because it would require some peripheral connected to the C6713Compact 2 However accessing peripherals is straightforward and is described below The base addresses of each chip select are defined in C headers that are delivered together with the C6713Compact 2 To access a peripheral device consider the following example Sw Date 25 June 2012 USER S GUIDE Doc no C6713Cpt 2 ml bm ug MICRO LINE BUSM
34. ect lines CS1 CS7 control lines micro line peripheral f interface interrupt lines EXT_INT4 EXT_INT7 INMI clock signals Provided by PLD reset signals gt independent of RESETOUT ML busmaster BSP HOLD E Provided for gt compatbility HOLDA _ J reasons do not use Figure 2 micro line peripheral interface Figure 2 gives an overview of the available signals and their direction For a detailed description of the individual signals please refer to chapter 8 1 Chip select lines CS1 CS3 are mapped into CE space 2 of the TMS320C6713 DSP This CE space is configured for 32 bit accesses by default The remaining chip select lines CS4 CS7 are mapped into CE3 which is configured for 16 bit bus width by default For further details on address mapping and bus width configuration please refer to chapter 4 Access cycles The peripheral interface generates a 3 phase bus cycle independent of the EMIF settings The list below shows the steps being performed e When the peripheral interface is accessed the DSPs ready line is deactivated to hold the current EMIF cycle until the peripheral interface has finished its access e Atthe beginning of the setup phase o D 31 0 is driven with the current write data for write accesses only o A 23 16 stay driven low o A 15 0 are driven with the current address with in the addressed chip select range o The CS ou
35. ed character coding standard asynchronous transmit FIFO a function block within the IEEE 1394 chipset board support package a combination of software and FPGA design that provides further functionality to the C6713Compact 2 Code Composer Studio TI s development environment chip enable space an address range of a TBD TMS320Cxxxx DSP associated with a specific CE signal COM port name of the serial RS 232 interface of a PC a dedicated area in the IEEE1394 address space for device identification central processing unit processor cyclic redundancy check a checksum method with high error detection probability chip support library a library with DSP specific functions provided by TI control and status register clear to send a handshake line of the RS 232 interface digital camera data mover port an interface of the IEEE1394 chipset for fast data transfers direct memory access a fast data transfer method digital signal processor a scalable real time kernel for TI DSPs with preemptive multitasking exempli gratia Latin for example enhanced DMA a specific kind of DMA used in C6000 DSPs electromagnetic interference external memory interface a peripheral of the TMS320C6713 DSP flash file system a proprietary file system which is integral part of some Orsys products first in first out a specific kind of sequential memory a specific kind of non volatile memory field programmable gate ar
36. eps have to be performed All signals must be connected directly to the respective signal of the C6713Compact 2 HR W must also be connected to the hosts WR output HRDY might need to be inverted depending on the host CPU type Address offset between HPI registers depends on the host CPU type Register address map is the same as shown in Table 19 11 2 3 Host Port Connections with Separate Strobe Signals Alternative Method If timing issues prohibit the use of the host s WR signal HR W can also be connected to the host s OE output if present or to an additional address bit table below shows the resulting register address map when using the host s A3 line for direction selection CAUTION When connecting an address bit to HR W invalid accesses can cause bus contention on HD 15 0 Please make sure that the register address corresponds with the access direction C6713Compact 2 CPU amp glue logic with separate strobe host port interface HCS CS decoded HRD HWR HR W HA 2 0 HD 15 0 HINT HRDY Figure 9 Host port connections when using address bit for direction selection Wie only Table 20 HPI register address map using address bit for direction select host port interface control HPIC 1st halfword host port interface control HPIC 2nd halfword read only fy USER S GUIDE Date 25 June 2012 d Doc no C6713Cpt 2_ml_bm_ug A MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys
37. erface HPI which can be used by a host processor to directly access the memory of the DSP Here the host device accesses the HPI fy d USER S GUIDE Date 25 June 2012 d Doc no C6713Cpt 2_ml_bm_ug A MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 12 as a master and the DSP acts as a slave The host processor and the DSP can exchange information via DSP internal and on board memory The host also has direct access to memory mapped peripheral registers of the DSP Connectivity to the DSP memory space is automatically provided through a DMA mechanism The host device controls the HPI transfers via dedicated HPI address and data registers which are not accessible for the DSP Here the DMA auxiliary channel connects the HPI to the DSP memory space Both the host and the DSP can access the HPI control register HPIC The host can access the HPI address register HPIA the HPI data register HPID and the HPIC by using the external host port data and control signals The host can also access the HPI data register in an auto increment mode HPIDA which allows to read a contiguous block of data without writing to the HPIA register each time The TMS320C6713 can trigger interrupts on the host processor to initiate data transfers This avoids unnecessary status polling by the host processor The host port data and control signals are available on the micro line bus at connector BB Host port byte
38. g diagrams can be found in chapter 10 1 The timing parameters of the peripheral interface can be adjusted by writing to the CSCTL register see chapter 5 2 1 Peripheral devices may extend the strobe phase of a peripheral interface access by hardware using the RDY input This allows e to access very slow peripherals that require even slower timings than the peripheral interface supports e to access slow peripherals with the correct timing while faster peripherals are accessed with unexpanded bus cycles De asserting the ready RDY input line of the micro line peripheral interface during an UO access will keep the processor in a permanent wait state as long as the RDY input line will remain inactive Only the assertion of the RDY input line will finalize the pending I O bus cycle and allow the processor to continue operation If external hardware controlled I O access timings are not required the RDY input line of the micro line peripheral interface should be left unconnected How to access peripherals from application software is described in chapter 12 1 2 3 2 Host Port Interface HPI C6713Compact 2 TMS320C6713 DSP FPGA Xilinx Spartan 6 LX45 LX150 micro line connector HPI control 9 control lines connector BB 10 control lines host port interface HPI data 16 data lines 16 data lines connector BB Figure 3 HPI block diagram The TMS320C6713 DSP provides a 16 bit wide host port int
39. ge 36 e Power on the C6713Compact 2 e Now you see the startup message of isotst in the terminal window isotst consists of 3 modules e isotstc contains initialization command interpreter main loop and the asynchronous transactions e init c contains initialization of the C6713Compact 2 e cfgrom c IEEE1394 configuration ROM contents for this example The example initializes the C6713Compact 2 with the minimum allowed EMIF timing so that software streaming can be performed with maximum speed The FPGA is checked to be present previously loaded from FFS The board serial number is read from the EEPROM and the IEEE1394 API is initialized API operation is started and a main loop is entered The main loop handles user commands from RS 232 generate a bus reset switch between counter data and random data or display help page initialize packet data random number generator and counter receive one data block Receive continuously transmit one block transmit continuously Pressing the s key on the terminal starts an interactive setup Here the speed and size of a single isochronous packet can be set up as well as the frame size which determines the number of packets that are transferred as a contiguous sequence The example is optimized for transmit speed by implementing QDMA transfers and single stage pipelining where test data generation QDMA transfers and transmit form the FPGA s FIFO buffer can run in parallel
40. h on board interrupt sources of the C6713Compact 2 are used Shared interrupts can be used but avoiding them makes the system easier and faster NMI This is the non maskable interrupt input line of the micro line peripheral interface Activation of NMI causes an interrupt at a high priority level which can not be masked by software In default configuration NMI is triggered on the falling edge of the interrupt signal in contrast to the DSP s NMI signals which is rising edge triggered It can be configured to be either falling edge triggered or rising edge triggered This is described in chapter 5 2 5 Level triggering is not possible RESETOUT and RESETOUT These signals are always provided by the C6713Compact 2 independent of this BSP Please refer to 1 for a description HOLD HOLDA 8 1 4 Connector E UART CLK This signal is always provided by the C6713Compact 2 independent of this BSP Please refer to 1 for a description EMIF CLK This pin is the clock output for the micro line peripheral interface This clock is generated from the DSP s external memory interface clock The clock output on this pin is software programmable By default the DSP EMIF clock divided by 4 is available on this signal See chapter 5 2 4 for details In order to reduce EMI it is recommended to switch off this signal if it is not used The clock output fy USER S GUIDE Date 25 June 2012 d Doc no C6713Cpt 2_ml_bm_ug A MICRO LINE
41. ical layer transceiver e g for IEEE1394 or Ethernet programmable logic device defines a 32 bit data word a group of 4 bytes frequently used in IEEE1394 terminology random access memory read only memory recommended specification 232 A widespread standard for serial communication synchronous dynamic random access memory to be changed value not 100 tested and may change in future to be defined value is not yet specified Texas Instruments universal asynchronous receiver transmitter e y Date 25 June 2012 UsER S GUIDE Doc no C6713Cpt 2 ml bm ug MICRO LINE BUSMASTER BSP Iss Rev 1 0a rsys FOR THE C6713COMPACT 2 Page 40 14 Literature references Further information that is not covered in this user s guide can be found in the documents listed below References to this list are given in square brackets throughout this document The documents are listed by title author and literature number or file name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 C6713Compact 2 hardware reference guide OrSys ce713cpt 2 hrg Flash File System User s Guide Orsys rrs ug Board Library Documentation for the micro line C6713Compact 2 OrsyS boardlib pdf C6713Compact 2 DM Port Streaming Core Orsys cez1acpt 2 str core ug IEEE1394 embedded API User Guide Orsys embedded API ug Texas Instruments website
42. in application example sotst Please refer to chapter 12 1 4 and the example s source code for further information fy j USER S GUIDE Date 25 June 2012 4 Doc no C6713Cpt 2_ml_bm_ug MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 115 4 Address Map 4 1 C6713Compact 2 Address Map The table below shows how the 4Gbyte address space of the C6713Compact 2 is used From this address space CE spaces CE2 and CE3 are used by the micro line busmaster BSP address range hex size bytes 0000 0000 7FFF FFFF internal memory and on chip peripherals 8000 0000 8FFF FFFF 256M external memory SDRAM 9000 0000 9FFF FFFF 256M on board peripherals A000 0000 AFFF FFFF CE2 256M FPGA registers and B000 0000 BFFF FFFF 256M micro line peripheral interface C000 0000 FFFF FFFF Table 4 C6713Compact 2 address map 4 2 Address Map of the micro line Busmaster BSP The table below show how the CE2 and CE3 address spaces are used by this BSP Please note that the addresses refer to the default EMIF configuration where CE2 is configured for 32 bit accesses and CE3 is configured for 16 bit accesses A000 0000 A000 003F reserved A004 0000 A007 FFFF A008 0000 AO00BFFFF CE2 AO0C 0000 AOOF FFFF A010 0000 A013 FFFF A014 0000 AFFF FFFF 128K CE3 8 FPGA registers Table 5 Default address map of this BSP 4 2 1 Bus Width Configur
43. ing co uk
44. ion callback for the allocated address range Outgoing transactions are triggered by the user over the RS 232 interface by pressing any unallocated key e g the space bar A packet with random data or counter data is then sent to the remote device using an asynchronous write transaction Then the packet is read back using an gt Date 25 June 2012 fy USER S GUIDE Doc no C6713Cpt 2 ml bm ug MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 34 asynchronous read transaction Finally the data written to the remote device is compared to the data that was read back Figure 11 shows a sample session where e the start up message is shown e an outgoing asynchronous transaction sequence to the default remote device is started which results in an error response e asynctst is set up to address another remote device and to use the maximum packet size e a second outgoing asynchronous transaction sequence write read back is started which is done successfully e an incoming asynchronous transaction read access from the remote device with 10 quadlets 40 28h bytes is displayed Note When asynctst displays an address error then the remote device does not allow incoming transactions on targeted address range 2048 bytes at address 0 This is the case when asynctst accesses the IEEE1394 interface of a PC where no special application is running To enable this address range you have to run a suitable a
45. mple asynctst session Modifications in the DSP BIOS configuration files asynctst cdb tcf is derived from C6713CPT 225MHz 32MB cdb tcf Scheduling HWI Hardware Interrupt Service Routine Manager HWI INT6 function _LynxHALNodelSR Dispatcher Use Dispatcher not selected Scheduling TSK Task Manager Insert a task with the following properties General comment task containing the main loop Function Task function TASK WorkingThread task object renamed to TSK work 12 1 4 Software Streaming isotst The distribution media contains an application example called isotst This example shows how to do software streaming using isochronous transactions An overview of isochronous transactions can be found in 5 The user interface of the application example is realized over the RS 232 interface A terminal e g a PC running Hyperterminal must be connected to the RS 232 interface To start this example you have to e Connect the RS 232 interface of the C6713Compact 2 to your development PC e Load the isotst example to the C6713Compact 2 using the fload6x utility see 1 e Load the micro line busmaster FPGA to the C6713Compact 2 using the fpgaload utility see 1 e Power off the C6713Compact 2 e Start a terminal program such as Hyperterminal Date 25 June 2012 USER S GUIDE Doc no C6713Cpt 2_ml_bm_ug BJ MICRO LINE BUSMASTER BSP GE orsys FOR THE C6713COMPACT 2 Pa
46. ng the signals HCS chip select HR W read write and a strobe signal which must be connected to both HRD while HWR must be connected to 1 Chapter 11 2 contains connection examples Access type ignored ignored write access common strobe configuration read access both configurations ie Bero GRUSS CES 0 O0 write access separate strobe configuration ie eas Ee ame ignored ignored ignored ignored Table 2 Valid HPI access combinations The functions of the host port addresses are specified in Table 3 Description host port interface control register HPIC 1 halfword host port interface control register HPIC 277 halfword host port interface address register HPIA 1 halfword host port interface address register HPIA 2 halfword host port interface data register with auto increment HPIDA 1 halfword host port interface data register with auto increment HPIDA 2 halfword host port interface data register HPID 1 halfword host port interface data register HPID 2 halfword Table 3 HPI registers The HPI data are only driven in the respective direction when a valid access is detected This helps to avoid bus contention 3 3 IEEE1394 Data Streaming The IEEE1394 chipset of the C6713Compact 2 provides a direct access to IEEE1394 data through the data mover port of the link layer controller LLC The data mover port can operate in parallel with software accesses to the LLC s mi
47. pplication e g another asynctst running on another C6713Compact 2 Date 25 June 2012 USER S GUIDE Doc no C6713Cpt 2_ml_bm_ug BJ MICRO LINE BUSMASTER BSP m Med orsys FOR THE C6713COMPACT 2 Page 35 1394 embedded API test application C6713Compact ASYNCTST Vr 1 1 Nov 21 2003 18 38 00 CPU clock 0225792000Hz FPGA Version 003 revision 000 OK HAL version 17030523 API version 17030523 Node vendor ID and serial number 00B02A00 000019AF press to get help page BR Bus reset 400000001 nodes on the network own node has index o idx cur vendor ser number status node H L 000 000 081443 53 0000166B present 001 001 00B02A 00 00001A15 present Oo 002 00B02A 00 000019AF local node press for help page space to start a transaction handle of remote node 0003672C vendor amp S N 081443 53 0000166B writing 0004 bytes response code 7 address error test setup nodes on the network own node has index o idx cur vendor ser number status node H L 000 000 081443 53 0000166B present 001 001 00B02A 00 00001A15 present o 002 00B02A 00 000019AF local node Select partner device for test idx column 1 adjust packet sizes new packet size in quadlets 512 Quadlets per Packet 0200 handle of remote node 00036774 vendor amp S N 00B0O2A 00 00001A15 writing 0800 bytes reading 0800 bytes comparing done NFY W 0028 bytes addr 0000 node 001 NFY R 0028 bytes addr 0000 node 001 Figure 11 Sa
48. ray generic extension language a file format for CCS initialization files host port interface a peripheral of the TMS320C6713 DSP interface input output id est Latin that is Association for advancement of technology formerly named Institute of Electrical and Electronics Engineers Inc specification of a high speed serial bus interrupt service routine the part of the software that handles interrupts 1394 Trade Association Instrumentation and Industrial Control Working Group Digital Camera Sub Working Group publisher of a standard for IEEE1394 based digital cameras refers to devices that use the IIDC standard for IEEE1394 based digital cameras at constant time intervals a transfer method used in IEEE1394 communications Joint Test Action Group name of an interface for testing and debugging hardware 1024 byte Date 25 June 2012 USER S GUIDE Doc no C6713Cpt 2_ml_bm_ug MICRO LINE BUSMASTER BSP Iss Rev 1 0a FOR THE C6713COMPACT 2 Page 39 quadlet RAM ROM RS 232 SDRAM TBC TBD TI UART light emitting diode IEEE 1394 link layer controller least significant bit 1204 KB 1048576 byte transfer speed in bits per second 1Mbps 1000kbps 10 bps most significant bit microcontroller interface an interface of the IEEE1394 chipset used for register access and basic operation not available not applicable not available not applicable not connected phys
49. sion field can be used by application software to verify that the correct BSP is loaded REVISION This bit field describes BSP revision The revision can change due to product improvement 5 2 3 LED Control Register This register controls the two LEDs that are connected to the FPGA The LEDs can be used as status indicators by application software e g the green LED is switched on during signal processing to show activity the red LED can be switched on when errors are detected 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED LED GREEN LED RED RESERVED r 00000000 r w 0 r w 0 r 000000 LED GREEN This bit controls the green LED Setting this bit to 1 will cause the green LED to light By default the green LED is off LED RED This bit controls the red LED Setting this bit to 1 will cause the red LED to light By default the red LED is off 5 2 4 Clock Control Register This register controls the EMIF_CLK output on the micro line connector This signal is generated from the DSP s EMIF clock Please note that changing the EMIF CLK on the micro line amp connector does not change the EMIF clock of the DSP All timings based on the EMIF clock such as SDRAM timings or the asynchronous timings of the seven micro line chip select lines remain unchanged 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CLK EN DIV RESERVED r 000000000 r CLK EN If this bit is set the EMIF CLK output is dri
50. ssccssssssssssssseeessesecseseseeaeseeeeseeeeees 15 4 2 1 Bus Width oni Viris Em 15 5 REGISTER DEES HEH 18 5 1 IEEE1394 Streaming Registers eren trn dnas nan in EO p Rd da ie ERR daga da EN EUR ARR 18 5 2 FPGA Registers P RM 18 5 2 1 Chip Select Control e EE 18 5 2 2 FPGA Version EE 19 5 2 3 LED eege Ne 19 5 2 4 Clock Control ROO NEUES 19 5 2 5 Interrupt Le 20 6 SETTING UP EMIF TIMINGS eg 21 7 SIGNALS ON THE MICRO LINE CONNECTOR ccce nnne 22 8 INDIVIDUAL SIGNAL DESCRIPTION s eseeseeeeeeeeeeeeenennn nennen nnn nennt 23 8 1 micro line Peripheral Interface nennen nnne tnnt nnn nnns 23 8 112 Connector EE 23 fp UsER s GUIDE NE AI A MICRO LINE BUSMASTER BSP po ure emen orsys FOR THE C6713COMPACT 2 Page 3 81 27 Connector B T u 23 8 1 3 Connector D essere erTi ni nva E EE Er ku du E EEA 23 8 124 Conhector E 24 8 2 Host Port IMC ACS uisi sanns enses en Scr secte ra REpRUS EDU UE LEM ERREUR E LUUQebXirR anaa mA E UCKES VEA UdE 25 8 2 1 Connector BB eoe terrd tele ie en dee iors ees ca db e a den oe ees 25 8 3 Other E 26 9 SIGNAL LEVELS casiscsvacececccecsccasicnavetetece a eaa aaaea aaae eaaa aE Raa a aa Eei 27 10 SIGNAL TIMINGS coscsssaisestseseceticececadevenntettedenesaepevebttedecelteeaevetncetevecuecnaebteaadbetienteaeets 28 10 1 micro line Peripheral Interface uk 28 10 2 Host Port Interface iios esten rin eu a
51. tput of the addressed chip select is driven low while the other CS lines stay high o R Wis driven low for write cycles and high for read cycles e The setup phase has a programmable width of 1 to 7 EMIF clocks resulting in a setup period of 10 to 70 ns Date 25 June 2012 UsER S GUIDE Doc no C6713Cpt 2 ml bm ug A MICRO LINE BUSMASTER BSP GE orsys FOR THE C6713COMPACT 2 Page 11 e The setup phase is followed by the strobe phase At the beginning of the strobe phase o RDis driven low in case of a read cycle o WRis driven low in case of a write cycle o STRB is driven low o All other signals remain unchanged e The strobe phase has a programmable width of 1 to 15 EMIF clocks resulting in a strobe period of 10 to 150 ns e RDY is sampled 4 EMIF clocks before the end of the strobe phase see chapter 10 1 for timing details RDY allows slow peripherals to extend the strobe phase beyond 15 clocks e The strobe phase is followed by the hold phase At the beginning of the hold phase o read data is sampled in case of a read cycle o RD WR and STRB are driven high e The hold phase has a programmable width of 1 to 15 EMIF clocks resulting in a hold period of 10 to 150 ns e Atthe end of the hold phase o D 81 0 are switched to high impedance o CS 7 1 are all driven high switching off the activated chip select line o the ARDY line of the DSP is released so that the DSP can finish the current EMIF access cycle Timin
52. u MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 4 List of Tables Tabl 1 el I SUG rial m 12 Table 2 Valid HPI access cormbinaltlons orte rente thx tn etapa btc uocnthecenexsnsstaannticereedareaiacniceers 13 Wel oe AP PEGS STS SRI NOR 13 Table 4 C671 3Compact 2 address map 15 Table 5 Default address map of this Bb 15 Table 6 Modified address map with CE2 configured for 16 bn 16 Table 7 Modified address map with CE2 configured for bt 16 Table 8 Modified address map with CE3 configured for 32 Dm 16 Table 9 Modified address map with CE3 configured for 8 bt 17 Table 10 FPGA register locations sssssssssssssss eere 18 Table 11 FPGA register bit summary in default EMIF configuration eeeeeeeeeeeeeeeeeeeeeeerenen 18 Table 12 Possible EMIF CUR Setting ESbEREAEER eu ue tha Etpa E nre RU c In x RRP ERAS PEMSRU DE RPM KIM NAR N MARNE RR RGUIS 20 Table 13 Timings for the CE2 and CE3 address spaces cccccccccceceeeeeeeeeeeceeeeeeeeeeeeeeesteeeteeess 21 Table 14 Pinout of micro line connectors A through E 22 Table 15 Pinout of micro line connector X entren ces 22 Table 16 Recommended operating conditions eeeeeeeeeeeessssseeeee enenatis 27 Table 17 Peripheral interface UIDES caia e emask oen ee E PR ee Seier 28 Table 18 HPI Timings FPGA part only nennen tup nnt ete take ek kan rb
53. unctional Overview C6713Compact TMS320C6713 DSP FPGA micro line Xilinx Spartan 6 connector LX45 LX150 peripheral interface connectors A B D E host port interface host port interface connectors BB TSB12LV32 LLC data mover Figure 1 Block diagram of the busmaster BSP 3 1 micro line Peripheral Interface The micro line peripheral interface provides a straightforward connection to up to seven peripheral boards or custom hardware devices without glue logic Its functionality is basically the same as the direct connection to the TMS320C6713 EMIF in asynchronous operation mode or to the parallel bus of many other standard DSPs or micro controllers Each bus cycle consists of a setup a strobe and a hold phase Timing of each phase can be programmed to 1 to 15 EMIF clocks On the C6713Compact 2 the micro line peripheral interface basically consists of 32 data bus lines 24 address bus lines only the lower 16 are actually used 7 chip select lines 5 interrupt lines a number of control lines Connection examples for the micro line peripheral interface can be found in chapter 11 1 gt Date 25 June 2012 fy USER S GUIDE Doc no C6713Cpt 2 ml bm ug MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 10 C6713Compact 2 data lines N D 31 0 address lines N A 23 0 A 23 16 are always driven low chip sel
54. unu EK Gu ge x cnS dE dk RR xK EAS 28 Table 19 HPI register En DEE 30 Table 20 HPI register address map using address bit for direction select 31 List of Figures Figure 1 Block diagram of the busmaster BSP 2 ccccesceceeeeesseeceeeeneeeeeeeeeesesaneneeeeeneeeseeneneeee 9 Figure 2 micro line amp peripheral interface cccccccccecccceccceecceeeceeeeeeeeeeeeneeeeeseeaessaeeaaeseaeenaaeaaaeass 10 Figure 3 HPI block CIBO PII qua ance ee EE dies eda orae e Pea ENS DOES NIE dra PR EDS er D ere ree E UAE 11 Figure 4 Available HPI signals E 12 Figure 5 IEEE1394 data streaming block diagram sse 14 Figure 6 Peripheral interface connection example sssssssssssseeeseserrrsrrrrrrrrrrrrrrrrrrrrrrrrreerrtertrerttent 29 Figure 7 Host port connections when using a single strobe 30 Figure 8 Host port connections when using separate strobe signals seeeeeesesseneeeeeeeeeeeeee 30 Figure 9 Host port connections when using address bit for direction selection 31 Figure 10 Startup message of toggle led fpga cecceccccceceeeeeeeeeseeceeneeeeeeeseeeesnenseeeeeeeeeenenenneeee 32 Figure 11 le EE 37467287 o ME 35 Figure 12 Sample isotst SOS SII dossatiub tre ida dins Mops du cin osi open dade au nD tie eu m UM Ut aped 36 Figure 13 Recorded isotst EE 37 Sw Date 25 June 2012 USER S
55. ven If this bit is set to 0 the EMIF CLK line is in high impedance state This bit can be used to reduce EMI when EMIF CLK if it is not used Changing CLK EN is synchronized to the clock output to allow glitch free switching DIV A USER S GUIDE Date 25 June 2012 A d y Doc no C6713Cpt 2 ml bm ug MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 20 This bit field controls the frequency of the EMIF_CLK output By default DIV is set to 3 which selects a frequency of a quarter of the EMIF clock 25 MHz at a default EMIF clock of 100 MHz Changing DIV is synchronized to the clock output to allow glitch free switching Together with CLK_EN the following selections are possible CLK_EN EMIF clock output don t care ID O undivided EMIF clock _ undivided EMIF clock EMIF clock Cea EE a 5 2 EMIF clock END LEI A Table 12 Possible EMIF_CLK settings 5 2 5 Interrupt Control Register This register has two purposes e it controls the polarity for the interrupt sources on the micro line bus e it selects the interrupt line that is used for IEEE1394 data streaming 15 10 9 8 7 6 5 4 3 2 0 RSV STR_INTSEL EINT7 POL EINT6 POL EINT5 POL EINT4 POL NMIPOL RSV r 000000 r w 00 r w 00000 r 000 STR_INTSEL This bit field selects the interrupt line for streaming Default value is 0 so DSP external interrupt 4 is used STR I
56. ween select signals HPI data tristate delay from connector to DSP HPI data delay from connector to DSP Skew between HPI data connector to DSP Table 18 HPI Timings FPGA part only fy USER S GUIDE Date 25 June 2012 d Doc no C6713Cpt 2_ml_bm_ug A MICRO LINE BUSMASTER BSP Iss Rev 1 0a orsys FOR THE C6713COMPACT 2 Page 29 11 Connection Examples 11 1 Peripheral Interface Peripheral devices can be easily connected to the micro line peripheral interface of the C6713Compact 2 An example of connecting the 16C550 UART to the C6713Compact 2 is shown below For this connection example e EXT_INT4 must be configured to be rising edge triggered see section 5 2 5 e timing of the peripheral interface must be set up to 2 clocks setup 4 clocks strobe and 2 clocks hold see 5 2 1 and e the high active reset output must be used 16C550 UART peripheral interface A 2 1 RD IWR D 7 0 EXT_INT4 UART_CLK RESETOUT Figure 6 Peripheral interface connection example 11 2 Host Port Interface A master device e g another CPU can be easily connected to the host port interface of the C6713Compact 2 Depending on the host processor two different connections variants are possible which will be shown below Note TI describes the host port timing behavior in 8 10 and 15 Please be sure to fulfill the timing requirements described in these documents Date 25 June

C6713Compact-2 micro-line Busmaster User's Guide

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