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Interlaken MegaCore Function v12.0 User Guide

1. Individual Reset Signals __ p Ems 9 T X m Application Calendar Transceiver D Interlaker i 9 gt 6 Interface Status Interface Link 9 i c i Packet Filter Channel 0 lt Regroup and 4 ds Buffer 1 Packet Filter J Channel 1 Hegroup I and NC Buffer gt TX Out of Band Flow Control Out of Band Calendar and lane link status Flow Control 4 RX Out of Band Interface Flow Control OOB FC Block This appendix describes the external transceiver interface External Transceiver Interface Clocks If you turn on Exclude transceivers your Interlaken MegaCore function exposes the interface to the transceivers With this parameter setting the Interlaken MegaCore function has the following external transceiver interface input clocks B rx lane clkN export M 0 these N x M input clocks each clock a distinct Interlaken receive lane The Interlaken MegaCore function derives an RX PCS block clock from these input clocks The grouping of these clocks indicated by the use of N and M is based on the connections to transceivers when they are included N is the number of transceiver blocks required for this variation minus 1 and M is the number of lanes per transceiver block minus 1 For the 10 lane and 20 lane variations M is five For the remaining variations M is four For an illustration of this nu
2. takta netaa oitti ek 4 23 Transceivers Hv E EE EEE E E EE E 4 23 Out of Band Flow Control Block 2 steriet epi ini Ei e ia 4 24 RX Out of Band Flow Control Block lt iceri sceri eee eens 4 24 TX Out of Band Flow Control Block 0 4 25 Out of Band Flow Control Block Signals 2 0 666 nee eens 4 25 Chapter 5 Signals Interlaken Interface and External Transceiver Interface Signals 5 1 Interlaken Interface Data and Clock Signals 6 5 2 Interlaken Interface Status Signals 0 0 ene eee 5 3 Interlaken MegaCore Function Reset Signals 0 5 4 Application Interface Signals 0 0 66 5 5 RX Application Interface Signals 2 0 ck nn 5 5 TX Application Interface Signals nee ene teens 5 6 Out of Band Flow Control Interface Signals 0 6 eens 5 8 RX Out of Band Flow Control Signals 2 5 8 TX Out of Band Flow Control Interface Signals 0 0 cee ees 5 10 Interlaken MegaCore Function June 2012 Altera Corporation User Guide Contents Chapter 6 Qsys Design Examples Design Examples epe qu ri eene a eee whip acd nip ns AEREE 6 1 Interlaken Sample Channel Client Component sssssseeseseeeeee eee 6 2 Design Ex
3. High Speed Memory 2 Memory Controller Interlaken interiaker Link Interlaken Optical S MegaCore MegaCore Ethernet MAC gt Module 5 Function Function 5 Stratix IV GX Stratix IV GT FPGA FPGA Features The Interlaken MegaCore function has the following features m Compliant with the Interlaken Protocol Specification Rev 1 2 m Supports 4 8 10 12 and 20 serial lanes in configurations that provide nominal bandwidths of 20 Gbps 40 Gbps and 100 Gbps m Supports per lane data rates of 3 125 6 25 6 375 and 10 3125 Gbps using Altera on chip high speed transceivers June 2012 Altera Corporation Interlaken MegaCore Function User Guide Chapter 1 About This MegaCore Function Device Family Support m Supports fast simulation by allowing configuration without high speed transceivers calendar pages Supports up to 127 5 Gbps raw bandwidth Supports dynamically configurable BurstMax and BurstShort values Provides Avalon ST interfaces on the transmit and receive datapaths Supports two logical channels in out of the box configuration Supports optional user controlled in band flow control with 1 8 or 16 16 bit m Supports optional out of band flow control blocks for lane status link status and one calendar page Table 1 1 lists the theoretical raw bandwidth of the Interlaken MegaCore function in the supported combinations of lane rate and number of lanes Table 1 1 Theoretical Raw Aggregate Bandwidth in G
4. p rx mac clk TX lane cIk 3 0 ag Interlaken Function i tx_data 159 80 ______ 1 common_rx_coreclk tx_data 159 80 4 rx lane Interlaken MegaCore Function June 2012 Altera Corporation User Guide Appendix B Excluding Transceivers for Faster Simulation B 5 External Transceiver Interface Data and Clock Signals External Transceiver Interface Data and Clock Signals If you turn on Exclude transceivers your Interlaken MegaCore function does not include high speed transceivers In that case the data for the Interlaken link appears on the external transceiver interface Table B 1 lists the external transceiver interface data and clock signals in Interlaken MegaCore function variations that do not include high speed transceivers Table B 1 External Transceiver Interface Signals Part 1 of 2 Signal tx dataN export 5 0 Direction Output Description Parallel transmit data interface N 0 for 4 lane variations N 0 1 for 8 and 10 lane variations N 0 1 2 for 12 lane variations and N 0 1 2 3 for 20 lane variations The width of the port for each value of N is the transceiver datapath width times the number of channels used on an Altera device transceiver in variations that include the transceivers For the 12 lane 10 Gbps variation the transceiver datapath width is 40 For all the other va
5. ref clk ett gt clk in rx data 199 100 tx datain 99 0 1 I 1 1 9 common rx clk 1 rx dataout 99 0 rx_clk 9 5 i f i ih 1 1 1 1 1 tx data 199 100 1 1 1 1 1 i i 1 1 clk in ix datain 99 0 tx data 299 200 1 common_rx_corec Iki TX data 299 200 1 4 rx dataout 99 0 rx_clk 3 0 rx_clk 14 10 1 1 and PCS tx data 399 300 1 1 common rx clk J 1 1 1 cal ref clk clk in Jj rx data 399 300 pi ix datain 99 0 1 common rx clk rx dataout 99 0 rx_clk 19 15 i rx_clk 4 0 in PMA Direct mode tx_pin 4 0 Lanes 10 to 14 rx_pin 4 0 HSIO Bank 2 in PMA Direct mode tx_pin 4 0 Lanes 5 to 9 rx pin 4 0 HSIO Bank 3 in PMA Direct mode ix pin 4 0 Lanes 0 to 4 rx_pin 4 0 irs ref_clk 48 1 38 TH i I s Be IX coreclkout Interlaken MegaCore Function Recommended Clock Rates This section describes the recommended frequencies for the Interlaken MegaCore function clocks MAC Clock Verified Frequency The Altera Interlaken MegaCore function supports the number of lanes and lane rate combinations shown in Table 3 1 on page 3 2 The verified MAC clock rates for each variation depend on the lane rate Ta
6. Burst Parameters This section lists the parameters that affect the value and dynamic configurability of the BurstMax and BurstShort Interlaken parameters June 2012 Altera Corporation Interlaken MegaCore Function User Guide 3 4 Chapter 3 Parameter Settings Burst Parameters Enable Dynamic Configuration of BurstMax and BurstShort Parameters Turn on the Enable dynamic burst parameters parameter to enable dynamic configuration of the BurstMax and BurstShort Interlaken parameters If you turn on this option your Interlaken MegaCore function has additional input ports you set dynamically to the desired values of the two Interlaken parameters Supported values are BurstMax values of 128 and 256 bytes and BurstShort values of 32 and 64 bytes Dynamic configuration of BurstShort is restricted to 12 lane 10 3125 Gbps and 20 lane Interlaken MegaCore function variations that is the variations with a 512 bit wide channel datapath In other variations whether you turn on Enable dynamic burst parameters or not BurstShort has a static value Refer to Table 5 8 on page 5 7 for information about the input ports for dynamic configuration of BurstMax and BurstShort Parameterized Static BurstMax Value If you disable dynamic configuration of the BurstMax and BurstShort parameters you can specify the static value of BurstMax that is configured in your Interlaken MegaCore function with the BURST MAX length in bytes parameter This parameter i
7. Lane rate Meta frame length Whether the MegaCore function includes or excludes the transceiver Whether the MegaCore function enables out of band flow control Number of pages of in band flow control calendar bits Whether the BurstMax and BurstShort parameters are dynamically configurable BurstMax value if not dynamically configurable BurstShort value in variations with a datapath width of 512 bits if not dynamically configurable General Parameters This section lists the basic parameters that affect the configuration of the Interlaken MegaCore function Operational Mode The Operational mode parameter specifies whether the MegaCore function is configured to support simultaneous bidirectional communication The operational mode with simultaneous bidirectional communication is called duplex mode The current version of the MegaCore function supports only Duplex mode Number of Lanes The Number of lanes parameter specifies the number of lanes available for Interlaken communication Supported values are 4 8 10 12 and 20 June 2012 Altera Corporation Interlaken MegaCore Function User Guide 3 2 Chapter 3 Parameter Settings General Parameters The Interlaken MegaCore function supports only some combinations of number of lanes and lane rate Table 3 1 shows the supported combinations Table 3 1 Supported Combinations of Numher of Lanes and Lane Rate Lane Rate Gbps Number of Lanes
8. clk ref _clk gt tx_mac_clk rx data 79 0 rx mac clik prx mec ck rx lane 3 0 tx coreclkout pnoe M HSIO Bank 0 low latency PCS mode ix lane clik tx data 79 0 TX MAC and PCS 5 1 1 ji 1 f inia gt ix datain 79 0 tx pin 3 0 In H x4 1 master TX clock nx pint m common rx clk x_dataout 79 0 common_rx_coreclk rx_coreclkout Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 4 Functional Description Clocking and Reset Structure 4 1 Figure 4 3 shows the clock diagram for an eight lane Interlaken MegaCore function Figure 4 3 Clock Diagram for 8 Lane Interlaken MegaCore Function cal gt cal ref clk ref Rc i 1 ck in TX MAC and PCS 4 T ipu tx data 79 0 tx mac tx mac ck TX mac ck p rx mac clk 1 RX MAC and PCS TX data 79 0 rx lane clk 3 0 ix datain 79 0 1 out master TX clock gt common_rx_clk rx dataout 79 0 rx clk 3 0 1 L cal bk clk gt ref 1 LL clk in tx data 159 80 common rx coreclk 2 tx datain 79 0 1 1 1 1 common rx clk rx data 159 80
9. For Node name type clock_crossing_fifo Click OK In the LogicLock Regions Properties dialog box click Apply On the Size amp Origin tab under Size turn off Auto and set the Width to 3 and the Height to 129 Under Origin turn off Floating and set Location string to X3_Y1 Click Apply Click OK Repeat step 7 for a new region lt IGX_IF gt that includes the nodes that match launch or rx capture or rx_dataout_to_fifo with Width 5 Height 129 and Origin X1 Y1 June 2012 Altera Corporation Appendix C Closing Timing on 10 and 20 lane Designs C 3 9 10 11 June 2012 Altera Corporation You must ensure that all Interlaken MegaCore transceiver channels are placed to one side of the device You can enforce this placement in your Quartus II project with pin location constraints However if your project does not already include existing pin location constraints that place all transceiver channels to one side of the device you must force the transceivers to one side of the device using the Assignment Editor To force the transceivers to the left edge of the device using the Assignment Editor perform the following steps a On the Assignments menu click Assignment Editor b In the Assignment Editor click lt lt new gt gt c In the new row click the Assignment Name column and select Location d Double click the Value column and click the Browse icon e In the Location dialog box for Element select
10. cent 3 4 Chapter 4 Functional Description Architecture Overview ccc ee he ree hne s een 4 2 Interfaces Overview edet et er e DR bp Hee er ara e derer d ne ceci 4 2 Interlaken Interface 2 b reme cm De ERR ena End c de qe rs 4 2 Application Interface i Ea KO esaet Va dere e Edo ete a e deg 4 4 June 2012 Altera Corporation Interlaken MegaCore Function User Guide iv Contents Avalon ST Interface cc nga pr cidade EPI ES REIS 4 4 Optional In Band Flow Control and Dynamic Configuration Signals 4 4 Out of Band Flow Control Interface 00 4 4 Clocking and Reset Structure xe be Re ee ea der E ear ba e RH E Rcg 4 5 MegaCore Function MAC Clock Domains sssssssseeee e 4 5 Interlaken Interface Clocks eraat s e bea aeta bec sib e ad ee A 4 5 Out of Band Flow Control Block Clocks 4 6 Clock Diagrams for the Interlaken MegaCore Function eee 4 6 Interlaken MegaCore Function Recommended Clock Rates 4 9 MAC Clock Verified Frequency 6 6 6 e 4 9 PCS Clock Frequencies i ma sisii E Ra we RI Eas a ya are eI Oe eee REPE EE 4 10 Transceiver Reference Clock Recommended Frequency and Source 4 10 Out of Band Flow Control Blo
11. p To TX Transceiver TX PCS Block ES Buffer tx clkout PCLK GCLK from core To lt q 3 4 From RX Transceiver RX PCS Block FIFO Buffer rx _clkout PCLK GCLK from core The pipelines are clocked by a global clock on the PCS side and a periphery clock on the transceiver side Transceivers In 10 and 20 lane Interlaken MegaCore function variations the Stratix IV transceivers are configured in PMA Direct mode In all the other variations the transceivers are configured in low latency PCS mode Refer to the clock diagrams in Clock Diagrams for the Interlaken MegaCore Function on page 4 6 for information about how the transceiver bank clock and data lines are connected in the different variations Figure 4 18 and Figure 4 19 show how the Interlaken MegaCore function uses the individual transceivers in each transceiver block depending on the variation Figure 4 18 Transceiver Block Use in 4 8 and 12 lane Variations 20 lane ALTGX 20 E M lane ALTGX 20 lane ALTGX 20 FPGA lane ALTGX June 2012 Altera Corporation Interlaken MegaCore Function User Guide 4 24 Chapter 4 Functional Description Out of Band Flow Control Block The 12 lane 10 3125 Gbps variations use four PMAs in each of three transceiver blocks with datapath width 40 bits rather than the 20 bits shown in Figu
12. page 2 3 5 If you intend to simulate your Qsys system on the Generation tab set Generate simulation model to Verilog to generate a functional simulation model in Verilog HDL 6 Click Generate to generate the system Osys generates the system and produces a system qip file system name gt qip that contains the assignments and information required to process the IP cores and system in the Quartus II Compiler The file is located in the project name synthesis subdirectory 7 In the Quartus II software in the Project menu click Add Remove Files in Project and add the system name gt qip file to the project Simulating the System During system generation Osys optionally generates various IEEE encrypted functional simulation models for the Interlaken MegaCore function and functional simulation models for other components in the Qsys system You can use these simulation models to simulate your system with your supported simulation tool In addition you can simulate the static design example that is provided in Verilog HDL The static design example is available for several Interlaken MegaCore function variations Refer to Chapter 6 Osys Design Examples The design examples are located in the design examples subdirectory of the alt interlaken installation directory Each testbench provides some basic stimulus to the user interfaces of the Interlaken MegaCore function You can use the example as a basis for your own system
13. tx control channel enable 1 0 has value 1 The tx coreclkout clock signal drives the tx mac c clkclock which is shown in the waveforms Figure 4 7 shows the beginning of the packet transfer on channel 0 illustrating the interaction between the tx ch0 datain validand tx ch0 datain ready signal behavior at the beginning of a packet transfer Figure 4 8 shows a point partway through the packet transfer in which the application is utilizing the Interlaken link fully The Interlaken MegaCore function backpressures the channel to prevent overflow Figure 4 9 shows a different point partway through the packet transfer at which the application deasserts the valid signal when it does not have data ready for the arbiter This delay causes the June 2012 Altera Corporation Interlaken MegaCore Function User Guide 4 14 Chapter 4 Functional Description Transmit Path MegaCore function to insert idle symbols on the Interlaken link Figure 4 10 shows the end of the 1016 byte packet tx ch0 datain data and the resulting non zero value of tx ch0 datain empty This example does not illustrate use of a non zero empty signal partway through a packet transfer although the arbiter does check the empty signal on every clock cycle in which valid data is transfered Figure 4 7 Beginning of 1016 Byte Packet Transfer on Channel 0 ix mac c ix ch0 datain ready ix ch0 datain val
14. you should observe the behavior described in Expected Behavior at Initialization Expected Behavior at Initialization After the internal reset sequence completes as your Interlaken MegaCore function initializes and establishes an Interlaken link with its link partner you should observe the following changes on the output signals 1 For each lane i status signals change in the following order a rx_status_per_lane_word_lock i is asserted This signal indicates the lane has locked onto the three bit synchronization header which occurs when 64 consecutive legal sync patterns have been observed This state is 64B 67B Word Lock shown in Figure 13 in the Interlaken Protocol Definition Revision 1 2 b rx status per lane sync lock i is asserted This signal indicates the lane has locked onto the meta frame boundary and recovered the scrambler seed from incoming traffic This state is RX LaneValid shown in Figure 8 in the Interlaken Protocol Definition Revision 1 2 2 After rx status per lane word lock i is asserted for every lane i every lane has achieved the 64B 67B Word Lock state the rx status all word locked signal is asserted 3 Afterrx status per lane sync lock 1 is asserted for every lane i every lane has achieved the RX LaneValid state the xx status all sync locked signal is asserted June 2012 Altera Corporation Interlaken MegaCore Function User Guide 4 Appendix A Initializing the Int
15. 3 125 6 25 6 375 10 3125 4 v v v 8 v v v 10 v v 12 v v v 20 v Y The Interlaken parameter editor does not enforce the license restrictions If you specify a supported combination that your set of licenses does not allow compilation does not generate a programming file For information about the lane number and lane rate combinations supported by the different Interlaken IP licenses refer to Installation and Licensing on page 1 4 Lane Rate The Lane rate parameter specifies the data rate on each lane All lanes have the same data rate The Interlaken MegaCore function supports only certain combinations of number of lanes and lane rate Refer to Table 3 1 For information about the device support for different combinations refer to Table 1 3 on page 1 3 57 The Interlaken parameter editor does not enforce the license restrictions If you specify a supported combination that your set of licenses does not allow compilation does not generate a programming file For information about the lane number and lane rate combinations supported by the different Interlaken IP licenses refer to Installation and Licensing on page 1 4 Number of Words in Meta Frame The Meta frame length in words parameter specifies the length of the meta frame in 64 bit 8 byte words In the Interlaken specification this parameter is called the MetaFrameLength parameter Smaller values for this paramete
16. 32 10 32 32 12 32 32 32 or 64 20 32 or 64 32 or 64 Note to Table 4 1 1 The BurstShort value for Interlaken MegaCore function variations with a 128 bit wide datapath increases link utilization while preventing multiple burst control words in the same clock cycle The Interlaken MegaCore function does not support BurstMin If you do not expose the in band flow control calendar bits the Interlaken MegaCore function supports the following in band flow control format for the RX and TX calendar bits m Bit 0 XON XOFF bit for Channel 0 m Bit1 XON XOFF bit for Channel 1 If you expose the calendar ports the application determines the use of the in band flow control bits the MegaCore function receives on the incoming Interlaken link and the application is responsible for specifying the values of the in band flow control bits the MegaCore function transmits on the outgoing Interlaken link In this case you can configure your MegaCore function to use 1 8 or 16 pages of 16 calendar bits For more information refer to Calendar and Status Block on page 4 20 T The Interlaken Protocol Definition Revision 1 2 is available from the Interlaken Alliance website at www interlakenalliance com June 2012 Altera Corporation Interlaken MegaCore Function User Guide 4 4 Chapter 4 Functional Description Interfaces Overview If you turn on the Exclude transceiver parameter to generate a faster simulation model yo
17. EP4SGX530NF45C2 and EP4SGX530KH40C2 Resource utilization is shown for variations that include the transceiver and do not include the out of band flow control block Table 1 4 Interlaken MegaCore Function FPGA Resource Utilization June 2012 Altera Corporation Parameters Resource Utilization Device of ids Rate Logic Registers Stratix IV GX 4 6 25 12 229 16 774 52 EP4SGX530NF45C2 8 6 25 24 825 31 776 68 Stratix IV GX 10 6 25 29 949 38 033 96 EP4SGX530KH40C2 20 6 25 63 033 77 806 159 Stratix IV GT 12 10 3125 50 164 56 948 84 4510065 4511 Interlaken MegaCore Function User Guide 1 4 Chapter 1 About This MegaCore Function Release Information For all Interlaken MegaCore function variations that target a Stratix IV GX device Altera recommends that you target a C2 speed grade device For all variations that target a Stratix IV GT device Altera recommends you target an I1 speed grade device In all cases Altera recommends that you set the Optimization Technique in the Analysis amp Synthesis Settings dialog box to Speed For information about how to apply the Speed setting refer to volume 1 of the Quartus II Handbook Release Information Table 1 5 and Table 1 6 provide information about this release of the Interlaken MegaCore function Table 1 5 lists the release information common to all Interlaken MegaCore function licenses Table 1 5 Interlaken MegaCore
18. Functional Description Receive Path 4 17 m Performs 64 67 encoding The input to this function is 65 bits wide the most significant bit is an Altera defined control bit that indicates whether a word is a control word or a data word The control bit has value 1 if the current word is a control word and value 0 if the current word is a data word m Performs 67 20 gearboxing For the 12 lane 10 Gbps variation performs 67 40 gearboxing Figure 4 12 shows the flow through the Interlaken TX PCS block Figure 4 12 Data Flow Through Interlaken MegaCore Function TX PCS Block Scrambler 7 32 64 Framing Scheduler Receive Path 64 67 Encoder 67 Gearbox puce 20 or 40 The Interlaken MegaCore function receives data on the Interlaken link and sends it through to the two application channels The RX PCS and MAC blocks retrieve the data and calendar information from the incoming Interlaken link and send it out to two RX channel filtering blocks The RX channel filtering blocks separate the data for the two channels and the packet regroupers regroup each channel s data in the word format expected on the channels RX PCS To retrieve the data the PCS block reverses the gearboxing and 64 67 encoding then descrambles the data and validates the CRC 32 bits and the meta frame The RX PCS block also sends lane status information to the calendar and st
19. Functional Description 4 5 Clocking and Reset Structure Clocking and Reset Structure The Interlaken MegaCore function has a variable number of clock domains depending on whether the MegaCore function includes or excludes transceivers and on whether it includes or excludes the out of band flow control block In addition to the high speed clock domains inside the device transceivers some of which also clock the PCS lanes the Interlaken MegaCore function contains two MAC clock domains for the receive and transmit directions four out of band flow control block clocks and clocks for the Interlaken interface For information about the clocks visible in your Interlaken IP core functional simulation model if you turn on Exclude transceivers refer to Appendix B Excluding Transceivers for Faster Simulation For recommended clock rates refer to Interlaken MegaCore Function Recommended Clock Rates on page 4 9 MegaCore Function MAC Clock Domains The Interlaken MegaCore function MAC blocks have the following two clock domains rx mac c clk clocks the RX MAC block B tx mac c clk clocks the TX MAC block Altera recommends that the same clock drive the rx mac c clkand tx mac c clk clocks Interlaken Interface Clocks If you turn off Exclude transceiver your Interlaken MegaCore function has the Interlaken interface clocks shown in Table 4 2 Table 4 2 Interlaken Interface Clocks Clock Name Description ref clk Re
20. Qsys in volume 1 of the Quartus II Handbook Quartus 11 software Quartus Il Help System interconnect Qsys tool Specifying Parameters To specify Interlaken MegaCore function parameters using the Osys flow perform the following steps 1 Create a new Quartus II project using the New Project Wizard available from the File menu 2 On the Tools menu click Osys 3 Onthe Component Library tab expand Interface Protocols Interlaken and highlight Interlaken 4 Click Add to add an Interlaken MegaCore function to your system The Interlaken parameter editor appears 5 Specify the parameters in the Interlaken parameter editor For detailed explanations of these parameters refer to Chapter 3 Parameter Settings June 2012 Altera Corporation Interlaken MegaCore Function User Guide Chapter 2 Getting Started Qsys Design Flow 6 Click Finish to complete the Interlaken MegaCore function and add it to the system Completing the Qsys System To complete the Osys system perform the following steps 1 Add and parameterize any additional components 2 Connect the components using the Connection panel on the System Contents tab 3 If some signals are not displayed click the Filter icon to display the Filters dialog box In the Filter list click All Interfaces 4 Ensure your Qsys system meets the connection and assignment requirements listed in Specifying Parameters and Generating the MegaCore Function on
21. Setup Guide chapter in volume 3 of the Stratix IV Device Handbook For information about high speed transceiver blocks refer to volume 2 and volume 3 of the Stratix IV Device Handbook Out of Band Flow Control Block Recommended Clock Frequencies The recommended frequency for the rx oob in fc clkand the tx oob out clk clocks is 100 MHz which is the maximum frequency allowed by the Interlaken specification The rx oob in sys clk frequency must be at least twice the rx oob in fc clk frequency and the tx oob in double fc clk frequency must be twice the tx oob out clk frequency In consequence the recommended frequency for the rx in sys clkand tx in double fc clkis 200 MHz Reset for Interlaken MegaCore Functions The Interlaken MegaCore function has a single asynchronous reset the reset export signal You must assert the reset export signal for at least four full cal blk clk clock cycles to ensure complete reset of your Interlaken MegaCore function Following completion of the reset sequence internally the Interlaken MegaCore function begins link initialization If your Interlaken MegaCore function and its Interlaken link partner initialize the link successfully you can observe the assertion of the lane and link status signals according to the Interlaken specification For information about the internal reset sequence that you intiate when you assert the reset export signal refer to Required Reset Sequence on page
22. and 12 lane variations and 5 M 4 for 10 and 20 lane variations Lane 0 holds the MSB of the input data which is input to the HSIO bank with the highest number Refer to Figure 4 2 on page 4 6 through Figure 4 6 on page 4 9 In an 8 lane variation xx serial datal export 3 connects to lane 0 rx serial datal export 2 connects to lane 1 and so on rx serial data0 export 2 connects to lane 5 rx serial data0 export 1 connects to lane 6 and rx serial data0 export 0 connects to lane 7 In a 20 lane variation xx serial data3 export 4 connects to lane 0 rx serial data3 export 3 connects to lane 1 and so on rx serial data2 export 4 connects to lane 5 rx serial data2 export 3 connects to lane 6 and so on rx serial datal export 4 connects to lane 10 rx serial datal export 0 connects to lane 14 rx serial data0 export 4 connects to lane 15 and rx serial data0 export 0 connects to lane 19 tx serial dataN export M 0 Input Differential high speed serial output data from the transceiver It is connected to the corresponding receive data lines of the Interlaken link partner N corresponds to the HSIO bank number N 0 for 4 lane variations N 0 1 for 8 and 10 lane variations N 0 1 2 for 12 lane variations and N 0 1 2 3 for 20 lane variations The width of the port is 4 M 3 for 4 8 and 12 lane variations and 5 M 4 for 10 and 20 lane variation
23. band RX block Indicates a new value without CRC 4 errors is present on at least one Output Ofrx out lane status Of rx_oob out link status inthe P current rx oob in sys 1 cycle The value is ready to be read by the application logic Lane status bits received from an upstream out of band TX block on rx out lane status 1 0 Output rc oob in fc data Width is the number of lanes L num lanes 1 Link status bit received from an upstream out of band TX block on rx oob out link status Output x 5 E rc oob in fc data Indicates corrupt lane or link status A new value is present on at least eT eee Output one of rx out lane status Of rx_oob_out_link status the current rx in sys clk cycle but the value has at least one CRC 4 error Calendar bits received from an upstream out of band TX block on rx oob out calendar 15 0 Output rc in fc data Indicates a new value without CRC 4 errors is present on rx oob out calendar update Output rx out calendar in the current xx in sys 1 cycle The value is ready to be read by the application logic Indicates corrupt calendar bits A new value is present on rx oob out calendar error Output rx out calendar in the current xx in sys clk cycle but the value has at least one CRC 4 error Note to Table 5 10 1 Altera recommends that you run rx in sys clkat200 MHz to support the recomm
24. c clk Refer to Figure B 5 for a circuit that shows how to enforce synchronous deassertion of tx mac r reset To reset the Interlaken MegaCore function completely you must assert all the reset signals in Table B 2 as described in Required Reset Sequence You can assert all the reset signals asynchronously to any clock However each reset signal must be asserted for at least one full clock period of a specific clock and be deasserted synchronously to the rising edge of that clock For example the RX MAC reset signal rx mac r reset should be deasserted on the rising edge of rx mac c clk You must implement logic to ensure the minimal hold time and synchronous deassertion of each reset input signal to the Interlaken MegaCore function Figure 5 shows a circuit that ensures these conditions for a reset signal Figure B 5 Circuit to Ensure Synchronous Deassertion of Asynchronous Reset Signal arst arst Interlaken MegaCore Vcc Function ars ars arst Zn clk June 2012 Altera Corporation Interlaken MegaCore Function User Guide Appendix B Excluding Transceivers for Faster Simulation Reset in Interlaken MegaCore Functions Without Transceivers 57 Insystems generated by Osys if you turn on Global reset on the Project Settings tab these circuits are generated automatically However Altera recommends that you turn off Global reset in a Osys system that includ
25. files The models appear in a set directory hierarchy in the project directory The functional simulation model is a cycle accurate VHDL or Verilog HDL model produced by the Quartus II software A Use the simulation models only for simulation and not for synthesis or any other purposes Using these models for synthesis creates a nonfunctional design If you generate the Interlaken MegaCore function instance in a Quartus II project you are prompted to add the Quartus IL IP File qip to the current Quartus project You can also turn on Automatically add Quartus IP Files to all projects The qip contains information about the generated IP core In most cases the qip contains all of the necessary assignments and information required to process the MegaCore function or system in the Quartus II compiler The MegaWizard Plug In Manager generates a single qip for each MegaCore function Click Exit to close the MegaWizard Plug In Manager You can now simulate your custom MegaCore function variation integrate it in your design and compile Simulating the Interlaken MegaCore Function You can simulate your Interlaken MegaCore function variation using any of the vendor specific IEEE encrypted functional simulation models which are generated in the new instance name sim subdirectory of your project directory June 2012 Altera Corporation Interlaken MegaCore Function User Guide 2 4 Chapter 2 Getting Started Qsys Design Flo
26. for channel 0 and bit 1 is a XON XOFF bit for channel 1 To indicate to the Interlaken link partner that channel 0 or channel 1 cannot accept more data the Interlaken MegaCore function sets TX calendar bit 0 or 1 to zero The TX calendar control block sets all the TX calendar bits to 1 at initialization after the RX lanes and link are fully locked in other words the RX Operational state specified in the Interlaken specification is reached The TX calendar control block holds all 16 of the TX calendar bits at value 1 for the duration of IP core operation because the RX datapath can handle all incoming traffic and does not need to backpressure its Interlaken link partner June 2012 Altera Corporation Interlaken MegaCore Function User Guide 4 22 Chapter 4 Functional Description High Speed 1 0 Block The calendar and status block sends the RX calendar bits to the enable logic for the arbiter These bits contain the XON XOFF status for the channels in the Interlaken link partner Behavior with Exposed Calendar Ports If you turn on Expose calendar ports in the Interlaken parameter editor the calendar and status block provides the RX calendar bits to the application on the rx status calendar bus and receives the TX calendar bits from the application on the tx control status calendar bus rather than from the lane status block The calendar and status block sends the RX calendar bits to the enable logic for the arbiter as it does whe
27. function You can adapt these steps for different locations and region sizes if you are having difficulty closing timing for your 10 lane Interlaken MegaCore function The steps described in this appendix use the Quartus II software LogicLock feature to lock the Interlaken MegaCore function on the left edge of the Stratix IV GX device and ensure that the various blocks are shaped so that all the transceiver assignments are on the same edge After you use the LogicLock feature to lock the Interlaken IP core in a set location on the device you compile your design and start working to close timing on the remaining failing paths identified by the TimeQuest Timing Analyzer To help close the timing gap for your 20 lane Interlaken MegaCore function perform the following steps before compiling your design 1 In the Quartus II software on the File menu click Open Project and select your Quartus II project 2 On the Processing menu point to Start and click Analysis amp Synthesis Analysis and synthesis may take several minutes 3 After Analysis and Synthesis completes on the Assignments menu click LogicLock Regions Window The LogicLock Regions window opens 4 Tocreate LogicLock regions for the RX and TX paths perform the following steps a In the Compilation Hierarchy window navigate to the top level of the Interlaken RX hierarchy instance name gt irx b Right click the top level of the Interlaken RX hierarchy select Logi
28. invalid bytes on the rx chX dataout data bus in any rx mac c clk clock cycle in which it asserts the rx chX dataout validsignal not just in clock cycles in which it asserts rx chX dataout endofpacket This feature supports the transmission of data to the application interface in the arrangement that most closely reflects the format of this data on the Interlaken link For more information about the RX channel interface signals refer to RX Application Interface Signals on page 5 5 Calendar and Status Block The calendar and status block collects and disseminates in band calendar information and lane and link status bits from the RX PCS to the TX path Figure 4 15 shows the calendar and status block and its sub blocks in an Interlaken MegaCore function with Expose calendar ports turned off Figure 4 15 Calendar and Status Block with Hidden Calendar Ports Interlaken MegaCore Function data Channel 0 channel TX TX Arbiter PCS pm KK Channel 1 eop ys enable TX calendar x HSIO Calendar TX Calendar and Block Status Control locked status e Status Lane meneh Status Crc24 error RX PCS Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 4 Functional Description 4 21 Calendar and Status B
29. low Figure 4 9 Non optimal Link Utilization Caused During 1016 Byte Packet Transfer on Channel 0 tx mac c clk ix chO datain ready tx chO0 datain valid i ix chO datain data 127 0 tx ch0 datain empty 3 0 410 4 0 J 40 4n 0 40 ix chO datain startofpacke ix chO datain endofpacke ix datain error Figure 4 10 shows the end of the 1016 byte packet transfer and the beginning of a new packet transfer Because the 1016 byte packet transfer uses only 64 bits of the final 128 bit application data word on the channel the tx ch0 datain empty signal has value eight to indicate that the least significant eight bytes in this word are invalid Only the eight most significant bytes hold valid data Figure 4 10 End of 1016 Byte Packet Transfer and Beginning of New Packet Transfer on Channel 0 tx chO datain ready tx chO datain valid B992 B1008 tx chO datain data 127 0 B1007 A B1016 ABO B15 B16 B31 tx ch0 datain 0 4 0 4hO 410 4hO 4n8 ano ano ano ano tx chO datain startofpacket tx chO datain endofpacket tx chO datain error Interlaken MegaCore Function June 2012 Altera Corporation User Guide 4 16 TX MAC Chapter 4 Functional Description Transmit Path The Interlaken MegaCore fun
30. lt Ix lane 7 4 rx dataout 79 0 rx clk 3 0 HSIO Bank 0 low latency PCS mode ix pin 8 0 Lanes 4 to 7 rx_pin 3 0 HSIO Bank 1 low latency PCS mode tx_pin 3 0 Lanes 0 to 3 TX pin 3 0 tx coreclkout gt h a P rx coreclkout Figure 4 4 shows the clock diagram for a 10 lane Interlaken MegaCore function This variation uses the transceivers in PMA Direct mode For more information refer to High Speed I O Block on page 4 22 Figure 4 4 Clock Diagram for 10 Lane Interlaken MegaCore Function 1 clk gt cal bk ck see Ss SSS SS gt ref_clk I tx_lane_clk i cl in TX MAC tx_data 99 0 tx datain 99 0 andPCS out master TX clock i y common rx clk rx data 99 0 rx dataout 99 0 x_ol 4 0 e 1 1X cIK 4 0 ix mac c as 7 01 _ pan ck L gt cal ck ref clk LL clk in RX MAC ix data 199 100 gt tx_datain 99 0 common_rx_coreclk 1 1 and PCS 1 1 1 1 gt common rx clk rx_data 199 100 34 1x dataout 99 0 TX C K 9 5 rx_clk 4 0 HSIO Bank 0 in PMA Direct mode 1 rx pin 4 0 HSIO Ba
31. menu point to Utility Windows and click Tcl Console 3 In the Tcl Console change directory to your new design example working directory alt interlaken 8lane 6g 4 Type the following command source setup proj tcl The Tcl script creates a Quartus II project and adds some required assignments to the Quartus II Settings File qsf 5 Onthe File menu click Open Project and open the alt interlaken 8lane 6g qpf project 6 Onthe File menu click Open and open the alt interlaken 8lane 6g qsys file The alt interlaken 8lane 6g Osys system opens in the Osys tool 7 In Osys on the Generation tab set Create simulation model to Verilog and turn on Create HDL design files for synthesis 8 Click Generate The Osys system is generated and the project is ready to simulate in a supported simulator and to compile in the Quartus II software Simulating the System Osys generates vendor specific IEEE encrypted functional simulation models for all the supported simulators Refer to Simulating the System on page 2 6 However the design examples includes a simulation script only for the ModelSim simulator This section shows you how to simulate your system using that script with the currently supported ModelSim SE simulator To simulate your system in the ModelSim simulation tool perform the following steps 1 Start the ModelSim software Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 6 Qsys
32. simulation T For information about simulating Osys systems refer to the Creating a System with Qsys chapter in volume 1 of the Quartus II Handbook Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 2 Getting Started 2 1 Specifying Constraints Specifying Constraints Altera provides a Synopsys Design Constraints sdc file that you must apply to ensure that the Interlaken MegaCore function meets design timing requirements The script automatically constrains the system clocks and the reference clock based on the data rate you specify If your design includes multiple instances of the Interlaken MegaCore function you must edit the sdc file to ensure that each instance name appears correctly in the file The Quartus II software v12 0 requires that you add the following additional constraints manually m Hard PLL Assignment Constraints m I O Standard Constraints The following sections describe the constraints you must add manually Hard PLL Assignment Constraints The sdc script provided with the Quartus II software v12 0 requires that you add hard PLL assignment constraints to the Quartus Settings File qsf before you compile your design You can add these constraints directly to the qsf or you can use the Quartus II Assignment Editor You must add the following hard transceiver PLL assignments before compilation set location assignment IOBANK quad location to PLL path where q
33. steps a Open the existing IP core for editing in the MegaWizard Plug In Manager The Interlaken parameter editor appears b Click Finish If the Interlaken IP core was generated using the Osys system integration tool originally perform the following steps a Open the Osys system b Toedit the Interlaken IP core double click its name in Osys The Interlaken parameter editor appears c Click Finish d In Osys regenerate the project Proceed with simulation specifying the Interlaken timing constraints and compilation as described in Chapter 2 Getting Started Interlaken MegaCore Function User Guide Interlaken MegaCore Function User Guide Appendix D Porting an Interlaken Design from the Previous Version of the Software June 2012 Altera Corporation JA DTE RA Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table shows the revision history for this user guide Date Version Changes Made m Maintenance release updated Appendix D Porting an Interlaken Design from the May 2012 12 0 Previous Version of the Software to describe porting from the 11 1 release to the 12 0 release m Added parameterizable or dynamically configurable BurstMax m Added parameterizable or dynamically configurable BurstShort m Added parameterizable exposed calendar pages and number of pages m Added global reset signal m Update
34. where you can sign up to receive update notifications for Altera documents Lj The feedback icon allows you to submit feedback to Altera about the document Methods for collecting feedback vary as appropriate for each document June 2012 Altera Corporation Interlaken MegaCore Function User Guide Mid Additional Information Typographic Conventions Interlaken MegaCore Function June 2012 Altera Corporation User Guide
35. 012 Altera Corporation Chapter 1 About This MegaCore Function 1 3 MegaCore Verification Table 1 3 shows the level of support offered by the Interlaken MegaCore function for each Altera device family Table 1 3 Device Family Support Device Family Support Stratix IV GT 1 Final Stratix IV GX Final Note to Table 1 3 1 Altera supports the 12 lane 10 Gbps configuration in Stratix IV GT devices only MegaCore Verification Before releasing a version of the Interlaken MegaCore function Altera runs comprehensive regression tests in the current version of the Quartus II software These tests use standalone methods and the Osys system integration tool to create the instance files These files are tested in simulation and hardware to confirm functionality Altera tests and verifies the Interlaken MegaCore function in hardware for different platforms and environments Constrained random techniques generate appropriate stimulus for the functional verification of the MegaCore function Functional coverage metrics measure the quality of the random stimulus and ensure that all important features are verified Performance and Resource Utilization Table 1 4 lists the resources and expected performance for different Interlaken MegaCore function variations Table 1 4 shows results obtained using the Quartus II software for the following devices m Stratix IV GT device EP4S100G5F45I1 m Stratix IV GX devices
36. 318 75 10 312 50 318 75 12 312 50 318 75 257 81 20 Interlaken MegaCore Function User Guide 312 50 318 75 For all variations except the 8 lane 3 125 Gbps variation Altera recommends that you drive the MAC clocks at the same frequency as the PCS clock In the 8 lane 3 125 Gbps variation the recommended MAC frequency is faster than the PCS frequency Transceiver Reference Clock Recommended Frequency and Source The transceiver reference clock ref_clk is the incoming reference clock for the Stratix IV GX transceiver s PLL To achieve the recommended PCS block operating frequency re clk must have the following recommended frequency m For all variations except the 10 3125 Gbps variation the recommended ref_clk frequency is lane rate divided by 20 For the 10 3125 Gbps variation the recommended ref frequency is 322 265625 MEZ to achieve the correct lane rate of 10 3125 Gbps The ref clk source affects the jitter performance of the system For high data rate applications your system may require that ref_clk be generated by a GPLL on the device For more information about driving the transceiver reference clock refer to AN580 Achieving Timing Closure in Basic PMA Direct Functional Mode June 2012 Altera Corporation Chapter 4 Functional Description 4 11 Transmit Path For more information about the transceiver reference clock frequency refer to the ALTGX Transceiver
37. B 8 This section describes the required reset sequence to reset the full Interlaken MegaCore function except the high speed transceivers However the internal reset signals the sequence drives do not appear as top level signals in an Interlaken MegaCore function variation that includes the high speed transceivers When you assert the reset export signal this sequence is driven internally and the high speed transceivers are reset Altera recommends that you turn off Global reset in a Qsys system that includes an Interlaken MegaCore function Instead export the reset export signal and assert it from outside the Osys system For more information about the link initialization sequence refer to Table 5 2 on page 5 3 and to Appendix A Initializing the Interlaken MegaCore Function For more information about the global reset signal refer to Interlaken MegaCore Function Reset Signals on page 5 4 Transmit Path The Interlaken MegaCore function receives application data on two application channels It combines the data from the two channels into a single data stream in which data is labeled with its source channel The Interlaken TX MAC and PCS blocks format the data in protocol compliant bursts and insert Idle words where required June 2012 Altera Corporation Interlaken MegaCore Function User Guide 4 12 Chapter 4 Functional Description Transmit Path Arhiter The channel arbiter arbitrates between the two incoming channels channe
38. C SOP ch0 Data 0 Data 1 Data 2 Data 3 Data 4 BC EOP chO 12 um um 23 E E E m t 0 t 1 BC SOP ch1 Data 5 t 2 Data 6 Data 7 Data 8 Data 9 t 3 Data 10 Data 11 IDLE EOP ch1 Packet Regrouper June 2012 Altera Corporation The packet regrouper for each channel receives the filtered data and rearranges each channel data sample so that the valid bytes are the most significant bytes removing all control words The information is instead conveyed by using the rx chX dataout empty vector to indicate the number of invalid bytes on the rx chX dataout data bus in the current rx mac clock cycle Any start of packet and end of packet information is likewise conveyed in separate signals rx chX dataout startofpacket and rx chX dataout endofpacket which are asserted during the clock cycle in which the appropriate condition holds The packet regrouper signals the application channel that it has data ready for transmission on the channel by asserting the rx chX dataout valid signal after it loads the data on the rx chX dataout data bus Refer to Table 4 5 on page 4 12 for the channel data bus width Interlaken MegaCore Function User Guide 4 20 Chapter 4 Functional Description Calendar and Status Block The packet regrouper implements an Avalon ST interface with one important modification the rx chX dataout empty vector can indicate the number of
39. Design Examples 6 5 Running a Design Example 2 Change directory to the testbench subdirectory of your design example working directory alt interlaken 8lane 6g testbench 3 Type the following command at the ModelSim command prompt do run simulation do The design example runs and displays a waveform showing the signals as the design example implements the sequence described in Design Example Simulation Sequence on page 6 3 The simulation run completes successfully with the following message Test complete Received 100 packets on channel 0 4 Received 100 packets on channel 1 Simulation success 57 When simulation completes you are prompted to quit the ModelSim software If the Modelsim Transcript tab is not currently active click No and then click the Transcript tab to view the transcript and ensure the preceding message appears 4 Onthe File menu click Quit to close the ModelSim software and return to the Quartus II software to compile your system Compiling and Programming the Device The Osys system files are now ready for compilation in the Quartus II software If you have acquired a license for this design example variation compilation generates an sof for device programming To compile your system design in the Quartus II software perform the following steps 1 Open the Quartus II project you created in Creating the Quartus II Project and Generating the Osys System on page 6 4 2 On the Process
40. Edge f For Location select EDGE LEFT g Click OK h Double click the To column and click the Node Finder icon The Node Finder appears i For Named type serial data export j Click List k Click the double right arrow to move all the found nodes to the Selected Nodes list l Click OK To optimize the Fitter settings for the 10 or 20 lane Interlaken MegaCore function perform the following steps a On the Assignments menu click Settings b Inthe Settings dialog box under Category click Fitter Settings c Turn on Optimize hold timing and select All Paths d Turn on Optimize multi corner timing select Standard Fit and turn on Limit to one fitting attempt e Click More Settings f For Name select Placement Effort Multiplier g For Setting type 4 0 h Click OK i Click Apply j Click OK Perform the following iterative process a Compile your design b Turn off Global Signal to all tx 1aunch registers with failing paths Depending on your paths you might add a line similar to the following example assignment to your qsf file Interlaken MegaCore Function User Guide c 4 Interlaken MegaCore Function User Guide Appendix C Closing Timing on 10 and 20 lane Designs Set instance assignment name GLOBAL SIGNAL OFF from transmit pma0 clockout to tx launch c Make PCLK assignments on remaining failing tx launch registers Depending on your paths you might add a line simila
41. Function Release Information Item Value Version 12 0 Release Date June 2012 Vendor ID 6AF7 License Ordering Codes and Product IDs are listed in Table 1 6 Table 1 6 lists the license information for this release of the Interlaken MegaCore function Tahle 1 6 Interlaken MegaCore Function License Ordering Codes and Product IDs License Ordering Code Product ID 20G License IP INTLKN 20G 4L 00DA 40G License IP INTLKN 40G 8L 00D5 IP INTLKN 100G 20L 00D6 100G Licenses IP INTLKN 100G 12L 00D4 Note to Table 1 6 1 For information about the different licenses refer to Interlaken MegaCore Function Licenses on page 1 5 Altera verifies that the current version of the Quartus II software compiles the previous version of each MegaCore function Any exceptions to this verification are reported in the MegaCore IP Library Release Notes and Errata Altera does not verify compilation with MegaCore function versions older than the previous release Installation and Licensing The Interlaken MegaCore function is part of the MegaCore IP Library which is distributed with the Quartus II software and downloadable from the Altera website wwvw altera com Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 1 About This MegaCore Function 1 5 Installation and Licensing Figure 1 2 shows the directory structure after you install the Interlaken MegaCore functio
42. Hz Interlaken MegaCore Function User Guide June 2012 Altera Corporation 6 Qsys Design Examples JA DTE RA Design Examples Overview The Interlaken MegaCore function includes four demonstration design examples Each license allows you to program a Stratix IV device with one of the four design examples Table 6 1 lists the design example available for each license The design example names specify the Interlaken MegaCore function variations they test Table 6 1 Interlaken MegaCore Function Design Examples License Design Example IP INTLKN 20G AL alt interlaken 4lane 3g IP INTLKN 40G 8L IP INTLKN 100G 12L alt interlaken 8lane 6g alt interlaken 12lane 10g IP INTLKN 100G 20L alt interlaken 20lane 6g For information about acquiring the license required to program each design example variation refer to Installation and Licensing on page 1 4 Figure 6 1 shows a block diagram correct for each design example Figure 6 1 Qsys Interlaken Design Example Quartus 11 Project Transceiver Banks Interlaken MegaCore Function Qsys System Avalon Streaming Connection Avalon Streaming Connection Interlaken Channel 0 Client Interlaken Channel 1 Client 1 1 Testbench Glue Logic The design examples each demonstrate a system that combines an Interlaken MegaCore function with two channel clien
43. Interlaken MegaCore Function User Guide A The Interlaken MegaCore function is scheduled for product obsolescence and discontinued support as described in PDN1410 Therefore Altera does not recommend use of this IP in new designs For more information about Altera s current IP offering refer to Altera s Intellectual Property website RA 101 Innovation Drive San Jose CA 95134 www altera com UG 01092 1 3 Document last updated for Altera Complete Design Suite version 12 0 Document publication date June 2012 Feedback Subscribe 2012 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks zi Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specificat
44. MegaCore function If you turn off Exclude transceivers your Interlaken MegaCore function includes high speed transceivers Table 5 1 lists the Interlaken interface data signals in that case If you turn on Exclude transceivers your Interlaken MegaCore function does not include high speed transceivers In that case the data for the Interlaken link appears on the external transceiver interface Table B 1 on page B 5 lists the external transceiver interface signals Table 5 2 and Table 5 3 describe the Interlaken interface status signals These signals are available whether or not you turn on Exclude transceivers June 2012 Altera Corporation Interlaken MegaCore Function User Guide 5 2 Chapter 5 Signals Interlaken Interface and External Transceiver Interface Signals Interlaken Interface Data and Clock Signals Table 5 1 lists the Interlaken interface data and clock signals when you turn off Exclude transceivers Table 5 1 Interlaken Data Interface Signals Part 1 of 2 Signal rx serial dataN export M 0 Direction Input Description Differential high speed serial input data to the transceiver It is connected to the corresponding transmit data lines of the Interlaken link partner N corresponds to the HSIO bank number N 0 for 4 lane variations N 0 1 for 8 and 10 lane variations N 0 1 2 for 12 lane variations and N 0 1 2 3 for 20 lane variations The width of the port is 4 M 3 for 4 8
45. OpenCore evaluation feature you can perform the following actions m Simulate the behavior of a megafunction Altera MegaCore function or AMPPSM megafunction in your system using the Quartus II software and Altera supported VHDL and Verilog HDL simulators m Verify the functionality of your design and evaluate its size and speed quickly and easily For more information about installation and licensing refer to Altera Software Installation and Licensing Interlaken MegaCore Function June 2012 Altera Corporation User Guide AA OTE PYA 2 Getting Started Design Flows 57 You can customize the Interlaken MegaCore function to support a wide variety of applications You use the MegaWizard Plug In Manager or the Osys system integration tool to instantiate this MegaCore function The MegaWizard Plug In Manager flow offers the following advantages m Allows you to parameterize the MegaCore function to create a variation that you can instantiate manually in your design The Osys flow offers the following advantages m Allows you to integrate other Altera provided custom components such as DMA controllers on chip memories and FIFOs in your design m Provides visualization of hierarchical designs m Allows customization of interconnect elements and pipelining June 2012 Altera Corporation Interlaken MegaCore Function User Guide 2 2 Chapter 2 Getting Started Design Flows Figure 2 1 shows the stages for creating a syst
46. TX MAC and PCS 5 ix coreclkout HSIO Bank 0 low latency PCS mode 1 1 I gt p m tx datain 79 0 tx pin 3 0 ipa P 1 f i lane tx_data 79 0 7 2 inI3 2 out master TX clock rx pin 3 0 KEE 2 m commn rx clk Ix data 79 0 1 1 rx dataout 79 0 1 rx lane 3 0 e a x 0103 0 1 t Exposed Interface ip Tipnsceivers common_rx_coreclk gt rx coreclkout Figure B 3 shows the clock diagram for a four lane variation that does not include transceivers Figure B 3 Clock Diagram for 4 lane Interlaken MegaCore Function Without Transceivers lane clkag tx data 79 0 g MegaCore Function p tx mac clk rx data 79 0 g P rx mac clk rx lane clk 3 0 ag i Interlaken common rx coreclk 1 c bate E EEE E June 2012 Altera Corporation Interlaken MegaCore Function User Guide B 4 Appendix B Excluding Transceivers for Faster Simulation External Transceiver Interface Clocks Figure B 4 shows the clock diagram for an eight lane variation that does not include transceivers Figure B 4 Clock Diagram for 8 lane Interlaken MegaCore Function Without Transceivers 4 lane tx_data 79 0 ___ e rx data 79 0 ag
47. a when both tx chX datain valid and tx chX datain ready are asserted Figure 4 7 shows an example of the required behavior The application should hold tx chx datain validand current data values on tx chX datain data steady fora full tx mac c cl1k clock cycle in which both the valid and ready signals are asserted because otherwise the arbiter does not read this data The application need not wait for the ready signal to be asserted before presenting the initial data to the tx chX datain data bus and asserting the valid signal The channel deasserts its valid signal when it has no more valid data to present on tx chX datain data It must maintain the current data on the data bus while it asserts the valid signal until one full clock cycle after the arbiter asserts the ready signal This behavior is compliant with the Avalon ST interface specification with ready latency 0 St For more information refer to the Avalon Interface Specifications Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 4 Functional Description 4 13 Transmit Path In addition to incoming data the arbiter receives start of packet and end of packet indicators whose values apply to the data on tx chX datain data in the current tx mac c clkclock cycle and an error indicator whose value is valid on the end of packet clock cycle and which refers to the current packet The empty vector tx chX datain empty indicates the number of i
48. ames To fill the Named field follow one of these steps m Ifthe number of lanes in your Interlaken MegaCore function is 10 or 20 in the Named field type tx 11 edgeO m Ifthe number of lanes in your Interlaken MegaCore function is 4 8 or 12 in the Named field type tx p110 Click List Highlight each node found and click the right arrow icon to move it from the Nodes Found list to the Selected Nodes list Click OK All the selected nodes appear in separate rows in the Assignment Editor with Assignment Name set to Location For each new row perform the following steps a Double click the new row in the Value column and click the Browse icon A Location dialog box appears b For Element select I O bank c For Location select IOBANK_Q lt m gt for your preferred value lt m gt You must preserve the lane order in assigning IO banks keeping in mind the requirement that 10 and 20 lane variations use five transceivers in each transceiver block and the other variations use four transceivers in each transceiver block Refer to High Speed I O Block on page 4 22 d Click OK The value you selected appears in the Value column For more information about timing analyzers refer to the Quartus II Help and The Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook 1 0 Standard Constraints The Interlaken MegaCore function implements the transceivers with the programmable transmitte
49. ample Simulation Sequence nn 6 3 Running a Design Example he nnn 6 3 Setting Up the Design ecce E EORR de ERI a ae Pee pared e 6 4 Creating the Quartus II Project and Generating the Osys System 6 4 Simulating the System serri cers ies ek a mes PERS pip uk e e ka be e AR Cer C aid ad ke eo cere 6 4 Compiling and Programming the Device sssssse nn 6 5 Appendix A Initializing the Interlaken MegaCore Function Configuration and 2 tete prete he ette puer pre er GP eee e E oes A 1 Expected Behavior at Initialization e A 1 Troubleshooting an Interlaken Link I A 2 Appendix B Excluding Transceivers for Faster Simulation External Transceiver Interface Clocks ere B 2 External Transceiver Interface Data and Clock Signals B 5 Reset in Interlaken MegaCore Functions Without Transceivers B 6 Reset Signals ttes thee as ote tt etary We B 7 Required Reset Sequence ic ds Ae teret ed ene ea e od ice ace ded eae c B 8 Appendix C Closing Timing on 10 and 20 lane Designs Appendix D Porting an Interlaken Design from the Previous Version of the Software Additional Information Document Revision History isa key ek p
50. annot occur The Interlaken MegaCore function has TX underflow protection enabled and the TX FIFO cannot actually underflow in response to a near underflow condition indicated by tx status hungry the PCS TX block inserts IDLE words in the outgoing data stream on tx serial dataN export Ortx dataN export Note to Table 5 3 1 All of the TX status signals are clocked by tx mac c clk Interlaken MegaCore Function Reset Signals If you turn off Exclude transceivers your Interlaken MegaCore function includes a reset controller block that implements the full MegaCore function reset sequence after the application asserts a single global reset signal Table 5 4 lists the Interlaken MegaCore function global reset signal If you turn on Exclude transceivers your Interlaken MegaCore function does not include a reset controller In that case you must control multiple reset signals for individual blocks to enforce the correct reset sequence for the Interlaken MegaCore function Table B 2 on page B 7 lists the individual reset signals visible when you turn on Exclude transceivers and Required Reset Sequence on page B 8 describes the required reset sequence Table 5 4 Global Reset Signal Signal reset export Direction Input Description Asynchronous reset for the full Interlaken MegaCore function including the RX and TX MAC blocks the full TX FIFO the RX and TX PCS blocks and the transceivers This reset sig
51. ations Altera recommends that rx mac c clk be driven by the same clock that drives the tx mac c 1 For recommended frequencies refer to Interlaken MegaCore Function Recommended Clock Rates on page 4 9 Table 5 6 RX Application Data Interface Signals Part 1 of 2 Signal Direction Description Channel X data out Streams the data received on the Interlaken interface out on channel X Width is 128 bits for variations that require the 20G 4L rx chX dataout data W 0 Output license 256 bits for variations that require the 40G 8L license and 512 for variations that require one of the 100G licenses For details refer to Table 4 5 on page 4 12 W width 1 Indicates data out on the current channel rx chX dataout data is valid in the current xx mac c clk cycle rx chX dataout valid Output Indicates data out on the current channel in the current xx mac c clk cycle includes a start of packet Indicates data out on current channel in the current xx mac c clk cycle includes an end of packet Indicates an error occurred during transmission of the current packet on rx chX dataout error Output rx chx datain data This signal is valid only in an end of packet cycle rx chX dataout startofpacket Output rx chX dataout endofpacket Output June 2012 Altera Corporation Interlaken MegaCore Function User Guide 5 6 Chapter 5 Signals Application Interface Signals Table 5 6 RX A
52. atus block June 2012 Altera Corporation Interlaken MegaCore Function User Guide 4 18 Chapter 4 Functional Description Receive Path Figure 4 13 shows the flow through the RX PCS block The width of the output from this block is 65 bits the most significant bit is an Altera defined control bit that indicates whether a word is a control word or a data word The control bit has value 1 if the current word is a control word and value 0 if the current word is a data word Figure 4 13 Data Flow Through Interlaken MegaCore Function RX PCS Block CRC32 Gearbox F7 67 64 Decoder gt 67 65 65 Word Aligner Framing Scheduler amp pescrampler RX MAC To recover a packet or burst the RX MAC takes data from each of the PCS lanes and reassembles the packet or burst The MSB of the incoming data is on lane 0 For more information about the correspondence between lane numbers and data bit order refer to Table 5 1 on page 5 2 The RX MAC then validates the CRC 24 bits and recovers the in band flow control calendar bits It sends the calendar bits to the calendar and status block and sends the raw data it retrieves to the RX channel filtering blocks Figure 4 14 shows the flow through the RX MAC block Figure 4 14 Data Flow Through Interlaken MegaCore Function RX MAC Block Lane Alignment Destriping CRC 24 Validation La
53. ble 4 3 shows the MAC clock frequencies at which the Interlaken MegaCore function was verified The MAC clocks are the tx mac c clkand rx mac c clk clocks Table 4 3 Verified MAC Block Frequencies in MHz Part 1 of 2 Lane Rate Gbps Number of Lanes 3 125 6 25 6 375 10 3125 156 25 312 50 318 75 200 00 312 50 318 75 June 2012 Altera Corporation Interlaken MegaCore Function User Guide 4 10 Chapter 4 Functional Description Clocking and Reset Structure Tahle 4 3 Verified MAC Block Frequencies in MHz Part 2 of 2 Lane Rate Gbps Numher of Lanes 3 125 6 25 6 375 10 3125 10 312 50 318 75 12 312 50 318 75 257 81 20 312 50 318 75 The MAC block must run at an aggregate frequency greater than the PCS block frequency to support the overhead of striping and destriping PCS Clock Frequencies The lane rate determines the operating frequency of the TX and RX PCS blocks For all variations except the 10 3125 Gbps variation the PCS frequency is lane rate divided by 20 For the 10 3125 Gbps variation because the transceiver datapath width is 40 rather than 20 the PCS frequency is lane rate divided by 40 The PCS clocks are tx coreclkout and rx coreclkout Table 4 4 MegaCore Function PCS Block Frequencies in MHz Number of Lanes Lane Rate Gbps 3 125 156 25 6 25 312 50 6 375 318 75 10 3125 156 25 312 50
54. ble B 2 Individual Reset Signals that Replace the reset export Signal Reset Signal Clock Domain Description Asynchronous reset for the Interlaken MegaCore function PCS TX block Asserting this reset signal resets all the TX PCS internal registers but does not reset the TX FIFO pointers which are in the TX MAC Instead it clears the internal overflow bit so the TX FIFO continues to empty but deasserts the internal FIFO write enable You must hold this reset signal asserted for 256 clock tx lane reset tx lane Clk cycles to completely clear the TX FIFO This reset signal can be asserted asynchronously but must stay asserted at least one clock cycle and must be de asserted synchronously with the rising edge of tx 1ane c 1 Refer to Figure B 5 for a circuit that shows how to enforce synchronous deassertion of tx 1ane r reset Asynchronous reset for the Interlaken MegaCore function MAC RX block This reset signal can be asserted asynchronously but must stay asserted at least one rx mac reset mac clk clock cycle and must be de asserted synchronously with xx mac c clk Refer to Figure B 5 for a circuit that shows how to enforce synchronous deassertion of rx mac reset Asynchronous reset for the Interlaken MegaCore function MAC TX block This reset signal can be asserted asynchronously but must stay asserted at least one tx mac reset mac c clk clock cycle and must be de asserted synchronously with tx mac
55. bps Lane Rate Gbps Numher of Lanes 3 125 6 25 6 375 10 3125 4 12 50 25 00 25 50 8 25 00 50 00 51 00 10 62 50 63 75 12 75 00 76 50 123 75 20 125 00 127 50 Device Family Support Table 1 2 defines the device support levels for Altera IP cores Table 1 2 Altera IP Core Device Support Levels FPGA Device Families Preliminary support The core is verified with preliminary timing models for this device family The IP core meets all functional requirements but might still be undergoing timing analysis for the device family It can be used in production designs with caution HardCopy Device Families HardCopy Companion The IP core is verified with preliminary timing models for the HardCopy companion device The IP core meets all functional requirements but might still be undergoing timing analysis for the HardCopy device family It can be used in production designs with caution Final support The IP core is verified with final timing models for this device family The IP core meets all functional and timing requirements for the device family and can be used in production designs HardCopy Compilation The IP core is verified with final timing models for the HardCopy device family The IP core meets all functional and timing requirements for the device family and can be used in production designs Interlaken MegaCore Function User Guide June 2
56. cLock Region and click Create New LogicLock Region The new LogicLock region appears in the LogicLock Regions window c Repeat steps a and b for the Interlaken TX hierarchy instance name gt itx 5 Toset the parameters of the new Interlaken RX hierarchy LogicLock region perform the following steps a Inthe LogicLock Regions window right click the new RX hierarchy LogicLock region row and click LogicLock Regions Properties b On the Size amp Origin tab under Size turn off Auto and set the Width to 55 and the Height to 64 c Under Origin turn off Floating and set Location string to X7 Y64 d Click Apply e Click OK June 2012 Altera Corporation Interlaken MegaCore Function User Guide C 2 Appendix C Closing Timing on 10 and 20 lane Designs 6 Tosetthe parameters of the new Interlaken TX hierarchy LogicLock region repeat step 5 with Width 58 Height 63 and Origin X7 Y1 Interlaken MegaCore Function User Guide To create a LogicLock region for the clock crossing FIFOs in the HSIO block perform the following steps Bh om i j k In the LogicLock Regions window in the Region Name column double click lt lt new gt gt to create a new region In the new row in the Region Name column type a name for your new region lt FIFO_LLR gt Right click the lt FIFO_LLR gt row and click LogicLock Regions Properties On the General tab click Add The Add Node dialog box appears
57. chieve timing closure Refer to Appendix C Closing Timing on 10 and 20 lane Designs for a list of steps you can implement to improve timing After successfully compiling your design program the target Altera device with the Programmer and verify the design in hardware Programming the device requires that you have a license for your Interlaken MegaCore function variation Refer to Interlaken MegaCore Function Licenses on page 1 5 u For Information About Compiling your design Refer To Quartus Il Incremental Compilation for Hierarchical and Team Based Design chapter in volume 1 of the Quartus II Handbook Programming the device Quartus Il Programmer chapter volume of the Quartus II Handbook June 2012 Altera Corporation Interlaken MegaCore Function User Guide 2 10 Chapter 2 Getting Started Compiling the Full Design and Programming the FPGA Interlaken MegaCore Function June 2012 Altera Corporation User Guide N DTE SYN 3 Parameter Settings Customize the Interlaken MegaCore function by specifying parameters in the Interlaken parameter editor which you access from the MegaWizard Plug In Manager or from the Qsys tool in the Quartus II software This chapter describes the parameters and how they affect the behavior of the MegaCore function To customize your Interlaken MegaCore function you can modify parameters to specify the following properties Operational mode Number of lanes
58. ck Recommended Clock Frequencies 4 11 Reset for Interlaken MegaCore ene 4 11 Transmit Path ceci ve es ee eed ceeded ee bee yv ee d ue ee e ea Void exa ta rede artes 4 11 Arbiter RR bac UR Pewee diab Peed ae Se Des i dee eee eae Tees 4 12 Arbiter and Application Behavior 0 2 0 ooo ene eee nes 4 12 Application Data Transfer Example 000 6066s 4 13 TA MA uL 4 16 TA POS ica he ae eed ease dee cease deed se ede 4 16 Receive exisse cs ba nk RE Ed p ede b ci eee steadier ey ase dee 4 17 RX PCS 4 17 BAMA serpere teh rev aad seus equae eee dO le C enc Ae lee ed lege Meng S Peace t 4 18 Channel Filtering Blocks 4 et s uote Cs ete eae 4 19 Packet ceclskeu e ne ex be ges niga Ri G4 pei RA LA I sagan aged bees Dee 4 19 Calendar and Status Block ccc ee nee e e eee newbs 4 20 Lane Status Block 122 d bre Rte ber RE Ra wx xe EE RE EE SoS 4 21 TX Calendar Control Block and In Band Flow Control Calendar Bits 4 21 Behavior with Hidden Calendar Ports 6 ccc eens 4 21 Behavior with Exposed Calendar Ports 0 0 2 ccc nets 4 22 Status Counters une pes a reg ee Ud E E EE E E ied 4 22 High Speed I O Block 23 seesi noris niir ine EAE EE ee EERE E EDERE EAER eS 4 22 FIFO Buffers and Pipeline Registers
59. cket on tx chX datain data This signal is valid only in an end of packet cycle tx chX datain empty T 0 Input Indicates the number of invalid bytes on the tx chx datain data bus in the current tx mac c clik cycle starting from the least significant byte The value 1 indicates that bits 7 0 are invalid the value 2 indicates bits 15 0 are invalid and so on Width is 4 bits for variations with a 128 bit wide channel 20G 4L license 5 bits for variations with a 256 bit wide channel 40G 8L license and 6 bits for variations with a 512 bit wide channel either of the 100G licenses For details refer to Table 4 5 on page 4 12 T width 1 tx control force transmit Input RX calendar override If this signal is asserted the MegaCore function accepts data on tx chX datain data for every enabled channel irrespective of the in band RX calendar values tx control channel enable 1 0 Input Channel enable vector If the bit that corresponds to channel X bit 0 for channel 0 and bit 1 for channel 1 is deasserted the arbiter prevents the transfer of data on the corresponding channel by not asserting the tx chX datain ready signal for that channel in response to its tx chX datain valid signal tx control tx calendar P 0 Input TX calendar bits to send in the next outgoing Interlaken link control word s Each 16 bit calendar page is transferred to the downstream Interlaken pa
60. ction User Guide Chapter 5 Signals Interlaken MegaCore Function Reset Signals Table 5 2 Interlaken RX Status Interface Signals 1 Part 2 of 2 Signal rx status overflow Output Direction Description Indicates that the RX MAC and channel filter blocks are unable to process data as fast as it arrives on the Interlaken link and data is lost or corrupted You can use the out of band flow control block to backpressure the Interlaken link partner Note to Table 5 2 1 All of the RX status signals are clocked by xx mac c clk Table 5 3 Interlaken TX Status Interface Signals 1 Signal tx status hungry tx status overflow Direction Output Output Description Indicates that the TX FIFO in the MAC TX block is close to underflow By default the Interlaken MegaCore function has TX underflow protection enabled and the TX FIFO cannot actually underflow in response to a near underflow condition the PCS TX block inserts IDLE words in the outgoing data stream on tx serial dataN export Of tx dataN export The application can monitor or ignore this signal The signal warns the monitoring application that data density on the incoming channels is not ideal Indicates that the TX FIFO in the MAX TX block has overflowed Data has been lost or corrupted tx status underflow Output Indicates that the TX FIFO in the MAC TX block has underflowed By default this condition c
61. ction TX MAC performs the following functions Inserts burst and idle control words in the incoming data stream Repacks the data to ensure the maximum number of words is available on each valid clock cycle Calculates and inserts CRC 24 bits in all burst and idle words Inserts calendar data in all burst and idle words Stripes the data across the PCS lanes The MSB of the data goes to lane 0 Buffers data between the application and the TX PCS block in the TX FIFO buffer The TX PCS block uses the FIFO buffer to recover bandwidth when the number of words delivered to the transmitter is less than the full width Figure 4 11 shows the flow through the Interlaken TX MAC block Figure 4 11 Data Flow Through Interlaken MegaCore Function TX MAC Block Striping gt L3 TX FIFO Burst Control Word Repacking CRC 24 Buffer Insertion gt gt m LI For more information about the correspondence between lane numbers and output signals refer to Table 5 1 on page 5 2 TX PCS The Interlaken MegaCore function TX PCS block performs the following functions for each lane Interlaken MegaCore Function User Guide Inserts the meta frame words in the incoming data stream Calculates and inserts the CRC 32 bits in the meta frame diagnostic words Scrambles the data according to the scrambler seed and the protocol specified polynomial June 2012 Altera Corporation Chapter 4
62. d description of tx chX datain ready signal in Arbiter on page 4 12 and in Table 5 8 on page 5 7 November 2011 11 1 m Updated Appendix B Excluding Transceivers for Faster Simulation to clarify global reset signal not relevant when transceivers are excluded m Moved block specific reset signal descriptions from Chapter 5 Signals to Appendix B Excluding Transceivers for Faster Simulation m Moved reset sequence description from Appendix A Initializing the Interlaken MegaCore Function to Appendix B Excluding Transceivers for Faster Simulation m Added Appendix D Porting an Interlaken Design from the Previous Version of the Software m Added information about lane ordering May 2011 11 0 m Added information about in band calendar bits m Removed Appendix D Connecting to User Defined Arbitration and Regrouping December 2010 10 1 Initial release How to Contact Altera To locate the most up to date information about Altera products refer to the following table June 2012 Altera Corporation Contact 1 Contact Method Address Technical support Website www altera com support 2 Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Nontechnical support general Email nacomp altera com Interlaken MegaCore Function User Guide Info 2 Additional Information Typographic Conventions Contact 1 software
63. dee gestore se penu b sqb ep ida esci o Ree a eoe ede uis 2 4 Specifying Parameters ped Sep E DPI rd e deed teret 2 5 Completing the Osys System a esee En eee e degens ed Peer a 2 6 Simulating the System siise hiiri iire ti eii e A hne 2 6 Speci yine COristralnts etate pereen ree Mic oed d e r e a rite a eios 2 7 Hard PLL Assignment Constraints neriie kiei eE E ei pie raa ase 2 7 I OStandard Constraints ee ci eresia eunin ette ee arae cte ed eter atur 2 8 Compiling the Full Design and Programming the FPGA 6 6 6 ccc eee nee 2 9 Chapter 3 Parameter Settings General Parameters he bu ale le 3 1 Operational Mode ier dade RR E E ER pa EORR Exon ec 3 1 horde dog PR ram 3 1 Lane Rate pem 3 2 Number of Words in Meta Frame 0 6 een 3 2 Excl ude Trarisceiver 2 1 e E Hebe ree dote ble de e e ot ies 3 2 Enable Out of Band Flow Control ssssssssseeeee nn 3 3 In Band Flow Control Parameters ssse e en 3 3 Expose Calendar ette eterne egent een 3 3 Number of Sixteen Bit Calendar Pages 066 eee 3 3 Burst Parameters M 3 3 Enable Dynamic Configuration of BurstMax and BurstShort Parameters 3 4 Parameterized Static BurstMax Value 1 ees 3 4 Parameterized Static BurstShort Value 0
64. distinct signal names one with cho and one with ch1 corresponding to the two channels channel 0 and channel 1 TX Application Interface Signals The TX application interface provides two channels through which the application sends data to the Interlaken link Table 5 7 and Table 5 8 describe the TX application interface signals For more information about these signals refer to Arbiter on page 4 12 Table 5 7 TX Application Interface Clock Signal Signal Direction Description Clocks the Interlaken MegaCore function MAC TX block and therefore also the TX application interface For all MegaCore function variations except the 8 lane 3 125 Gbps variations Altera recommends that you drive this signal with the tx_coreclkout signal in variations with transceivers or that you drive this signal with the same clock that drives the tx mac c clk Input tx lane c clksignal in variations without transceivers For the 8 lane 3 125 Gbps variations the tx mac c 1 clock should be driven by a faster clock than the TX PCS clock For these variations Altera recommends that tx mac c clk be driven by the same clock that drives the xx mac c 1 For recommended frequencies refer to Interlaken MegaCore Function Recommended Clock Rates on page 4 9 Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 5 Signals Application Interface Signals 5 7 Table 5 8 TX Application Inter
65. em with the Interlaken MegaCore function and the Quartus II software Each stage is described in detail in subsequent sections Figure 2 1 Interlaken MegaCore Function Design Flow Select Design Flow MegaWizard Plug in Manager Flow Qsys Flow Y Specify Parameters Specify Parameters Y Y Generate Complete Qsys System MegaCore Function Uo s Y ee E Simulate with Testbench Y Y Instantiate MegaCore In Design Generate Qsys System Simulate System y Specify Constraints y Compile Design y Program Device MegaWizard Plug In Manager Design Flow Summary You can use the MegaWizard Plug In Manager in the Quartus II software to parameterize a custom MegaCore function variation The Interlaken parameter editor lets you interactively set parameter values and select optional ports This flow is best for manual instantiation of a MegaCore function in your design Qsys Design Flow Summary The Qsys design flow enables you to integrate an Interlaken component in a Qsys system The Osys design flow allows you to connect component interfaces with the system interconnect eliminating the requirement to design low level interfaces and significantly reducing design time When you add an Interlaken MegaCore function instance to your design an Interlaken parameter editor guides you in selec
66. ended and maximum allowed xx oob in fc clk frequency of 100 MHz June 2012 Altera Corporation Interlaken MegaCore Function User Guide 5 10 Chapter 5 Signals Out of Band Flow Control Interface Signals TX Out of Band Flow Control Interface Signals The transmit out of band flow control interface receives calendar and status information and transmits flow control clock data and sync signals Table 5 11 describes the transmit out of band flow control interface signals specified in the Interlaken Protocol Definition Revision 1 2 Table 5 12 describes the signals on the application side of the TX out of band flow control block Table 5 11 TX Out of Band Flow Control Interface Signals Signal Direction Description Output reference clock for a downstream out of band RX block This signal clocks the tx out data and tx out sync tx oob out clk 1 Output signals You must connect this signal to a device pin Refer to Out of Band Flow Control Block Recommended Clock Frequencies on page 4 11 A eka Output Output serial data pin for a downstream out of band RX block You x oen must connect this signal to a device pin ee Output Output sync control pin for a downstream out of band RX block You must connect this signal to a device pin Note to Table 5 11 1 The maximum tx oob out clk frequency allowed by the Interlaken specification is 100 MHz Altera recommends that you run
67. erface Signals Part 1 of 2 Signal Direction Description Input reference clock from an upstream out of band TX block This signal clocks the xx oob in fc dataand rx oob in fc sync rx in fc clk U Input signals You must connect this signal to a device pin Refer to Out of Band Flow Control Block Recommended Clock Frequencies on page 4 11 Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 5 Signals Out of Band Flow Control Interface Signals 5 9 Table 5 9 RX Out of Band Flow Control Interface Signals Part 2 of 2 Signal Direction Description Input serial data pin from an upstream out of band TX block You UE ipur must connect this signal to a device pin Brad in Input Input sync control pin from an upstream out of band TX block You must connect this signal to a device pin Note to Table 5 9 1 The maximum rx in frequency allowed by the Interlaken specification is 100 MHz Altera recommends that you run the rx oob in clk clock at 100 MHz Table 5 10 RX Out of Band Flow Control Block Signals for Application Use Signal Direction Description Reference clock for capturing RX calendar lane status and link rx in sys clk Input status Frequency must be at least double the frequency of rx oob in fc clk rx oob in sys arst Input Asynchronous reset for the out of
68. erlaken MegaCore Function Troubleshooting an Interlaken Link After both rx status all word lockedand rx status all sync locked are asserted the rx status fully lockedsignalis asserted This signal indicates lane alignment and meta frame alignment are complete and the Interlaken receiver is fully locked This state is RX Operational shown in Figure 9 in the Interlaken Protocol Definition Revision 1 2 The rx status fully locked signal is asserted four meta frames after the rx status all word locked and rx status all sync locked signals are asserted All of the signals are expected to remain high after they are first asserted during initialization Now your Interlaken IP core is ready to start sending and receiving packets 57 The TX status signals might toggle during initialization Their values are not valid until after initialization completes when the rx status fully locked signal is asserted By default an internal parameter setting ensures that the TX FIFO never underflows so the application can choose to monitor or to ignore the tx status hungry and tx status underflow signals During initialization the application should ignore all the TX status signals Refer to Table 5 3 on page 5 4 Troubleshooting an Interlaken Link If your application cannot establish an Interlaken link check for the following symptoms that indicate specific potential root causes Interlaken MegaCore Function User Guide Ifthe rx status pe
69. es an Interlaken MegaCore function without high speed transceivers because the Osys generated reset sequence does not meet the reset sequence requirements for this MegaCore function Required Reset Sequence To reset your Interlaken MegaCore function perform the following reset sequence 1 2 3 4 Assert the MAC resets rx mac r reset and tx mac r reset and the lane reset tx lane r reset De assert the tx lane reset reset signal Wait 256 tx mac c clk cycles De assert the rx mac r reset and tx mac r reset signals Ensure that you enforce the minimum hold time and synchronous deassertion requirements for each reset signal as described in Reset Signals Following MAC deassertion if your Interlaken MegaCore function initializes and establishes an Interlaken link with its link partner in simulation you should observe the behavior described in Expected Behavior at Initialization on page A 1 Interlaken MegaCore Function User Guide June 2012 Altera Corporation C Closing Timing on 10 and 20 lane ANU S RAN Designs I O timing is critical for Interlaken MegaCore functions Achieving timing closure for 10 and 20 lane Interlaken MegaCore function designs can be difficult because these variations use the transceivers in Basic PMA Direct mode in which the transceiver block PCS blocks are not utilized This appendix provides guidance to help achieve timing closure for your 20 lane Interlaken MegaCore
70. face Signals Part 1 of 2 Signal tx chX datain data W 0 Direction Input Description Channel X data in Streams in the channel X data to be transmitted on the Interlaken interface Width is 128 bits for variations that require the 20G 4L license 256 bits for variations that require the 40G 8L license and 512 for variations that require one of the 100G licenses For details refer to Table 4 5 on page 4 12 W width 1 The arbiter reads data from this bus when both the tx chX datain validand tx chX datain ready Signals are asserted For more information refer to Arbiter on page 4 12 tx chX da tain valid Input Indicates data in on the current channel tx chX datain data is valid in the current tx mac cycle tx chX da tain ready Output Indicates the arbiter is ready to receive data on channel X This signal is the Avalon ST protocol ready output flag The input data stream for the current channel tx chx datain data is backpressured until this signal is asserted tx chX da tain startofpacket Input Indicates data in on the current channel in the current tx mac c clk cycle includes a start of packet symbol tx chX da tain endofpacket Input Indicates data on current channel in the current tx mac c clk cycle includes an end of packet symbol tx chX da tain error Input Indicates an error occurred during transmission of the current pa
71. face to device pins On the application side the out of band flow control block can receive link status lane status and calendar bits from the application and transmit them on the TX out of band flow control interface to a downstream RX out of band flow control block associated with the Interlaken link partner It can also transmit link status lane status and calendar bits to the application after it receives them on the RX out of band flow control interface from an upstream TX out of band flow control block associated with the Interlaken link partner RX Out of Band Flow Control Block The RX out of band flow control block can receive calendar bits from an upstream TX out of band flow control block associated with the Interlaken link partner and transmit link status lane status and the original calendar bits to the application Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 4 Functional Description 4 25 Out of Band Flow Control Block TX Out of Band Flow Control Block The TX out of band flow control block can receive link status lane status and calendar bits from the application and transmit them on the TX out of band flow control interface to a downstream RX out of band flow control block associated with the Interlaken link partner Out of Band Flow Control Block Signals Figure 4 20 shows the out of band flow control block Figure 4 20 Out of Band Flow Control Block
72. ference clock for the RX and TX transceiver PLLs cal blk clk Transceiver calibration block clock rx coreclkout Clocks the RX PCS block This clock is derived from the physically central RX lane clock tx coreclkout Clocks the TX PCS block This clock is derived from the master TX clock from transceiver block 0 It drives all the transceiver block c1k in clocks as well as the transmit lanes from the TX PCS block to the HSIO block Ss Gy For all Interlaken MegaCore variations except the 8 lane 3 125 Gbps variation Altera recommends that you drive the rx mac c clkand tx mac c clk clocks with the tx coreclkout clock Refer to Interlaken MegaCore Function Recommended Clock Rates on page 4 9 For information about the Interlaken link facing clocks if you turn on Exclude transceiver refer to Appendix B Excluding Transceivers for Faster Simulation June 2012 Altera Corporation Interlaken MegaCore Function User Guide 4 6 Chapter 4 Functional Description Clocking and Reset Structure Out of Band Flow Control Block Clocks If you turn on Enable out of band flow control your Interlaken MegaCore function has the following four additional clock domains rx in fc clk clocks the incoming out of band flow control interface signals described in the Interlaken specification This clock is received from an upstream TX out of band flow control block associated with the Interlaken link partner tx o
73. h supported variation Table 1 7 Interlaken MegaCore Function License Support Number of Lane Rate Gbps Lanes 3 125 6 25 6 375 10 3125 4 IP INTLKN 20G 4L IP INTLKN 20G 4L IP INTLKN 20G 4L 8 IP INTLKN 20G 4L IP INTLKN 40G 8L IP INTLKN 40G 8L 10 IP INTLKN 40G 8L IP INTLKN 40G 8L 12 IP INTLKN 40G 8L IP INTLKN 40G 8L IP INTLKN 100G 12L 20 IP INTLKN 100G 20L IP INTLKN 100G 20L After you acquire a license you can compile and program your device with all the variations that require that license However to program a variation that requires a different license you must acquire the additional license You can generate simulate and compile all MegaCore function supported variations without a license because the Interlaken MegaCore function supports the Altera OpenCore evaluation feature June 2012 Altera Corporation Interlaken MegaCore Function User Guide Chapter 1 About This MegaCore Function Installation and Licensing OpenCore Evaluation The Altera OpenCore evaluation feature allows you to generate RTL files and simulation models to simulate and to compile to validate timing but requires that you acquire a license to generate a programming file with which to configure an FPGA Therefore without a license for the variation your design includes you cannot create an SRAM Object File sof or Programmer Object File pof for programming a device with your design With the free
74. he meta frame boundary and recovered the scrambler seed from incoming traffic Rx LaneValid in the Output Interlaken specification This signal is deasserted when sync lock is lost according to the Interlaken specification Width is the number of lanes L num lanes 1 rx status all word locked rx status all sync locked Output Indicates all lanes are word locked Output Indicates all lanes are sync locked Indicates the Interlaken receiver is fully locked This signal is asserted when rx status all word lockedis high rx status all sync lockedis high and lane alignment is rx Status fully locked Output complete RX Operational in the Interlaken specification The signal is deasserted when any of these three conditions no longer holds according to the Interlaken specification iz status locked Pine 0 Output Counter that tracks the time elapsed since xx status fully locked is asserted Increments once every 318 x 106 xx mac c clk cycles rx status error count 15 0 Output Counter that tracks the number of CRC 24 errors encountered rx status per lane crc32 errs 0 0 Output Per lane 8 bit counters for tracking the number of CRC 32 errors encountered Width is 8 x num lanes Q 8 x num lanes 1 Bits 7 0 track the CRC 32 errors on RX lane 0 bits 15 8 track the CRC 32 errors on RX lane 1 and so on June 2012 Altera Corporation Interlaken MegaCore Fun
75. ia opad eE nnn Info 1 How to Contact Altera RARE RAS ESSO EA ESCAS EA ER EAE Info 1 Typographic ConventionS i i m isesi ee eb es pe IR er er her Wd eere Info 2 June 2012 Altera Corporation Interlaken MegaCore Function User Guide vi Interlaken MegaCore Function User Guide Contents June 2012 Altera Corporation NBT amp BYN 1 About This MegaCore Function Interlaken is a high speed serial communication protocol for chip to chip packet transfers The Altera Interlaken MegaCore function implements the Interlaken Protocol Specification Revision 1 2 It supports specific combinations of number of lanes from 4 to 20 and lane rates from 3 125 to 10 3125 gigabits per second Gbps on Stratix IV GT devices and lane rates from 3 125 to 6 375 Gbps on Stratix IV GX devices providing raw bandwidth of 12 50 Gbps to 127 50 Gbps Interlaken provides low I O count compared to earlier protocols supporting scalability in both number of lanes and lane speed Other key features include flow control low overhead framing and extensive integrity checking The Interlaken MegaCore function incorporates a physical coding sublayer PCS a physical media attachment PMA and a media access control MAC block The MegaCore function transmits and receives Avalon Streaming Avalon ST data on its FPGA fabric interface Figure 1 1 shows an example system implementation Figure 1 1 Typical Interlaken Application
76. id BO B15 2i B48 B63 4h 0 4h 0 J J am ix chO datain data 127 0 tx ch0 datain startofpacke ix chO datain endofpacke gt USA UP m DU Em ix ch0 datain error Figure 4 8 shows the application utilizing the Interlaken link fully The Interlaken MegaCore function backpressures the application to prevent overflow by deasserting the tx ch0 datain ready signal When it is ready to accept data again it reasserts the tx ch0 datain ready signal and the channel can resume sending new data Figure 4 8 Full Link Utilization During 1016 Byte Packet Transfer on Channel 0 e LE LILES LILI LILI Le tx_ch0_datain_ready o ae ee n tx_ch0_datain_data 127 0 X X Y 85 X X 3 tx ch0 datain empty 3 0 4h 0 4h 0 4h 0 4h 0 4h 0 4h 0 4h 0 4h 0 tx_ch0_datain_startofpacke M ix chO datain endofpacke M ix ch0 datain error M Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 4 Functional Description 4 15 Transmit Path Figure 4 9 shows non optimal utilization of the Interlaken link In this case the application deasserts its valid signal when it does not have data ready to transfer Asa result of this gap in incoming data the Interlaken MegaCore function inserts Idle symbols on the Interlaken link In this example multiple Idle symbols are inserted as a result of the three cycles in which the application holds the valid signal
77. ing menu click Start Compilation to compile your system After you compile the design example you can program your target Altera device and verify the design in hardware using the appropriate Interlaken MegaCore function license The alt interlaken 20lane 6g design example requires some additional steps to ensure it achieves timing closure Refer to Appendix C Closing Timing on 10 and 20 lane Designs for a list of steps you can implement to improve timing June 2012 Altera Corporation Interlaken MegaCore Function User Guide 6 6 Interlaken MegaCore Function User Guide Chapter 6 Qsys Design Examples Running a Design Example June 2012 Altera Corporation A Initializing the Interlaken MegaCore JN DTE RAN Function This appendix describes a basic reset sequence for the Interlaken MegaCore function describes the expected sequence of signal assertions during initialization and provides some troubleshooting tips for the Interlaken link Configuration and Reset This section describes the most basic initialization sequence for an Interlaken system that contains two Interlaken MegaCore functions connected through their Interlaken interfaces To initialize the system perform the following steps 1 Configure the devices with the two Interlaken MegaCore functions 2 For each Interlaken MegaCore function assert the reset export signal to initiate the internal reset sequence After the internal reset sequence completes
78. ion describes the following steps for running the alt interlaken 8lane 6g design example 1 Setting Up the Design Example 2 Creating the Quartus II Project and Generating the Osys System 3 Simulating the System 4 Compiling and Programming the Device Appendix C Closing Timing on 10 and 20 lane Designs includes additional steps you must follow to ensure that the alt interlaken 20lane 6g design example achieves timing closure on a Stratix IV GX FPGA June 2012 Altera Corporation Interlaken MegaCore Function User Guide 6 4 Chapter 6 Qsys Design Examples Running a Design Example Setting Up the Design Example The design example files are located in the design examples subdirectory of your Interlaken MegaCore function installation directory Refer to Installation and Licensing and Figure 1 2 on page 1 5 for the location of the MegaCore function installation directory in your Altera installation To set up the alt interlaken 8lane 6g design example the design examples alt interlaken 8lane 6g directory to your working directory The new subdirectory alt interlaken 8lane 6g is your design example working directory Creating the Quartus Il Project and Generating the Qsys System To create the Quartus II project for the design example perform the following steps 1 On the Windows start menu click Programs Altera Quartus II version Quartus II version to run the Quartus II software 2 Onthe View
79. ions before relying on any published information and before placing orders for products or services ISO 9001 2008 Registered June 2012 Altera Corporation Interlaken MegaCore Function User Guide N SYN Contents Chapter 1 About This MegaCore Function Features prse acera t Irae nett hd e Eae db e Rated rede a P Ea deed o vd oggi 1 1 Device Family Support hehe er Rte PT a 12 MeegaCore Verification sedato ERE bep bah de ES Me Eder Fr paa es 1 3 Performance and Resource Utilization 06 6 enn 1 3 Release Information igen ee e ieee epe ei d oe Ded Pe Ld ped a Eu n gis 1 4 Installation and Licensing 2 5 5 ete eme eR dane eR i Ee m ee Ya E e Ee 1 4 Interlaken MegaCore Function Licenses 0 0 0 6c ccc eh 1 5 OpenGore Ey ala HON sarera facto ete s UTI eM He dte Lp cae 1 6 Chapter 2 Getting Started Design FLOWS mr P 2 1 MegaWizard Plug In Manager Design Flow Summary 0 0000 00 2 2 Osys nnn 2 2 MegaWizard Plug in Manager Design 1 2 3 Specifying Parameters and Generating the MegaCore Function 2 3 Simulating the Interlaken MegaCore Function 00 2 3 Instantiating the MegaCore Function in Your Design 888 2 4 Osys Desien PlOW cendres dene ee mer
80. ix oob out clk TX Out of Band Boob Se ut of Ban Xx oob out data ____ L x oob out Calendar and Flow Control Out of Band lane link status C ON EUM RX Out of Band IX oob in fc a e i LIVIR Flow Control rx oob in fc sync rx oob in fc data Out of Band Flow Control Block For clock constraints and comprehensive information about the signals of this block refer to Out of Band Flow Control Interface Signals on page 5 8 June 2012 Altera Corporation Interlaken MegaCore Function User Guide 4 26 Chapter 4 Functional Description Out of Band Flow Control Block Interlaken MegaCore Function June 2012 Altera Corporation User Guide N DTE RYN 5 Signals This chapter describes the Interlaken MegaCore function signals 5 Qsys allows you to export signals with different names or prefixes Refer to the Osys System Contents tab for the signals that support this capability and to the Osys HDL Example tab for the list of signals that are exported with predefined names The default prefix for a newly exported signal is the MegaCore function instance name in the Osys system However you can overwrite the name with which any signal is exported After you export a signal it is added in the HDL Example tab with the name you specify Interlaken Interface and External Transceiver Interface Signals Table 5 1 through Table 5 3 list the pins related to the Interlaken interface of the Interlaken
81. l For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI angled arrow instructs you to press the Enter key 1 2 3 and Numbered steps indicate a list of items when the sequence of the items is important a b and so on such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important 57 The hand points to information that requires special attention The question mark directs you to a software help system with related information p The feet direct you to another document or website with related information The multimedia icon directs you to a related multimedia presentation CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or your work WARNING A warning calls attention to a condition or possible situation that can cause you injury Interlaken MegaCore Function User Guide June 2012 Altera Corporation Additional Information Typographic Conventions Info 3 Visual Cue The envelope links to the Email Subscription Management Center page of the Altera website
82. l 0 and channel 1 using a round robin arbitration scheme It implements an Avalon ST interface in communication with the channel with one important modification that involves the tx chX datain empty signal Arhiter and Application Behavior In the round robin arbitration scheme if data is available on both channels and the Interlaken IP core is not backpressuring either channel the arbiter accepts data from the two channels on alternating cycles The application can enforce full packet mode operation by forcing each channel to wait until the other channel completes sending a packet before it asserts its own valid signal You can use the tx control channel enable 1 0 bits to selectively disable a channel temporarily The channel width depends on the Interlaken MegaCore function variation Both channels have the same width Table 4 5 shows the channel width for each supported variation Table 4 5 Application Channel Width in Bits for Supported Variations Lane Rate Gbps Number of Lanes 3 125 6 25 6 375 10 3125 4 128 128 128 8 128 256 256 10 256 256 12 256 256 512 20 512 512 The arbiter asserts the tx chX datain ready signal to indicate it is ready to receive new data on channel X The application indicates to the arbiter that valid data is available on channel X by asserting the tx chX datain validsignal and holding valid data on tx chX datain data The arbiter reads dat
83. l Client Component The design examples implement each channel client with an Interlaken Sample Channel Client component The Interlaken Sample Channel Client is a component in the Component Library panel in the Osys system integration tool The only parameter available in its parameter editor is Width of datapath in bits which must match the datapath width of the Interlaken MegaCore function to which it connects However its instantiation relies on values being assigned to the additional parameters shown in Table 6 2 Table 6 2 Interlaken Sample Channel Client Hidden Parameters Parameter Description Default Value Number of 64 bit words in each data sample Not all bits need WORDS be valid Value is one of 2 4 or 8 depending on the DUT 8 variation Size of the internal register that holds the number of valid words in the current transmission in or out Value is 2 3 or 4 4 depending on the DUT variation because holding a number from 0 to WORDS requires logs WORDS 1 bits Size of the internal register that holds the number of empty bytes in transmissions in and out of the Interlaken Sample EMPTY BITS Channel Client Value is 4 5 or 6 depending on the DUT 6 variation because holding a number from 0 to 8 0 to 16 or 0 to 64 requires 4 5 or 6 bits LOG WORDS Number of 64 bit words in TX STRING and RX STRING WORDS x 2 vectors Default value is WORDS x 2 BUFFER WORDS String from which outgoing data sam
84. licensing Contact Method Email Address authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Bold Type with Initial Capital Letters bold type Indicate command names dialog box titles dialog box options and other GUI labels For example Save As dialog box For GUI elements capitalization matches the GUI Indicates directory names project names disk drive names file names file name extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters italic type Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines Indicates variables For example n 1 Variable names are enclosed in angle brackets gt For example file name and lt project name gt poft file Indicate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Courier type Quotation marks indicate references to sections in a document and titles of Quartus Help topics For example Typographic Conventions Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signa
85. lock Figure 4 16 shows the calendar and status block and its sub blocks in an Interlaken MegaCore function with Expose calendar ports turned on Figure 4 16 Calendar and Status Block Connections with Exposed Calendar Ports Interlaken MegaCore Function data 0 Arbiter Channel 1 TX calendar TX PCS L TX calendar HSIO TX Calendar Block Control locked status RX calendar Counters iatis Crc24 error RX pcs NES Lane Status Block The lane status block monitors the health of the Interlaken RX PCS lanes and delivers the status information to output status signals for use by the application It also passes the lane status information to the TX calendar control block TX Calendar Control Block and In Band Flow Control Calendar Bits The calendar and status block handles the in band flow control calendar bits differently depending on whether you configure your Interlaken MegaCore function with Expose calendar ports turned on or turned off The following sections describe the MegaCore function behavior in the two cases Behavior with Hidden Calendar Ports If you turn off Expose calendar ports in the Interlaken parameter editor the Interlaken MegaCore function uses only two of the 16 available in band calendar bits Bit 0 is a XON XOFF bit
86. lock you can rule out gross physical connection issues Instead focus on analog signal integrity causes June 2012 Altera Corporation Appendix A Initializing the Interlaken MegaCore Function A 3 Troubleshooting an Interlaken Link m Ifthelanes are locked and not generating CRC 32 errors you can exchange traffic If IDLE symbols pass but regular traffic generates numerous CRC 24 errors the lanes might be out of order IDLE symbols are single word messages and therefore not subject to ordering issues However multi word messages generate CRC 24 errors when the lanes are out of order Due to manufacturing constraints boards and adapters are often designed with scrambled lane order Check that your physical connections take these lane order differences into account June 2012 Altera Corporation Interlaken MegaCore Function User Guide 4 Interlaken MegaCore Function User Guide Appendix A Initializing the Interlaken MegaCore Function Troubleshooting an Interlaken Link June 2012 Altera Corporation B Excluding Transceivers for Faster JN DTE RAN Simulation The external transceiver interface is the interface that connects the Interlaken MegaCore function to a transceiver if you turn on the Exclude transceiver parameter You might choose to turn on this parameter to increase the simulation speed of your design However excluding the transceivers from the Interlaken MegaCore function removes them from both the func
87. mbering scheme refer to Clock Diagrams for the Interlaken MegaCore Function on page 4 6 m tx lane c clk clocks the TX PCS block and the Interlaken transmit lanes Interlaken MegaCore Function June 2012 Altera Corporation User Guide Appendix B Excluding Transceivers for Faster Simulation B 3 External Transceiver Interface Clocks 57 For all Interlaken MegaCore variations except the 8 lane 3 125 Gbps variation Altera recommends that the same clock drive the rx mac c clk tx mac c clk and tx lane c clk clocks Because the Interlaken MegaCore function does not include the high speed transceivers in this case the ref_clk and cal blk clkinput clocks to the transceivers which are input signals to the Interlaken MegaCore function if it includes transceivers are not included in the MegaCore function that excludes transceivers The reset controller is excluded from these variations because it runs on the cal blk clk clock which is not available Figure B 2 illustrates how you can derive the external transceiver interface signal and clock information by simply removing the HSIO banks from the corresponding variation with transceivers Figure B 3 and Figure B 4 show the four lane and eight lane variations without transceivers Figure B 2 Clock Diagram for 4 lane Interlaken MegaCore Function with Transceivers TT ic bk chk X ref clk r ix mac clik p x mac
88. n where lt path gt is the installation directory The default installation directory on Windows is C NalteraN version number on Linux it is opt altera lt version number gt Figure 1 2 Directory Structure au path Installation directory ip Contains the Altera MegaCore IP Library and third party IP cores altera Contains the Altera MegaCore IP Library common Contains shared components e alt interlaken Contains the Interlaken MegaCore function files You can use Altera s free OpenCore evaluation feature to evaluate the MegaCore function in simulation before you purchase a license You must purchase a license for the MegaCore function only when you are satisfied with its functionality and you want to check performance in hardware and take your design to production After you purchase a license for the Interlaken MegaCore function you can request a license file from the Altera website at www altera com licensing and install it on your computer When you request a license file Altera emails you a license dat file If you do not have internet access contact your local Altera representative Interlaken MegaCore Function Licenses The Altera Interlaken MegaCore function is available to you through several different licenses depending on the variation you wish to generate Licensing is based primarily on aggregate bandwidth Table 1 7 shows the license required to program a device with eac
89. n Band Flow Control Parameters This section lists the parameters that affect the in band flow control configuration Expose Calendar Ports Turn on the Expose calendar ports parameter to specify that the in band flow control calendar bits are available on input and output signals of the Interlaken MegaCore function If you expose the calendar ports you are able to view the in band flow control RX calendar bits and you are responsible for specifying the values of the in band flow control TX calendar bits that appear in bits 55 40 of the control words you transmit on the Interlaken link If you turn off the Expose calendar ports parameter a single 16 bit page of in band flow control calendar information is included in the Interlaken control words and the Interlaken MegaCore function uses only two of those bits For more information about the Interlaken MegaCore function behavior when calendar ports are configured and when they are not refer to Calendar and Status Block on page 4 20 For information about the calendar port signals refer to Table 5 6 on page 5 5 and Table 5 8 on page 5 7 Number of Sixteen Bit Calendar Pages The Width of calendar ports in 16 bit pages parameter specifies the number of 16 bit pages of in band flow control data your Interlaken MegaCore function supports Supported values are 1 8 and 16 You can modify this number from its default value of 1 only if you turn on the Expose calendar ports parameter
90. n calendar ports are not exposed but the application controls any additional use of these bits The arbiter enable logic interprets RX calendar bits 0 and 1 as XON XOFF status for the two channels exactly as it does when calendar ports are not exposed However you can modify the RTL to change this behavior in addition to using the exposed RX calendar ports in any way you choose In this case you can specify 1 8 or 16 pages of 16 calendar bits in the Interlaken parameter editor The Interlaken MegaCore function receives in band flow control bits in the control words from the Interlaken link and makes them available to the application on the rx status calendar output signals The MegaCore function receives outgoing in band flow control bits from the application on the tx control tx calendar signal and inserts them in bits 55 40 of the outgoing control words as required by the Interlaken specification The Interlaken MegaCore function does not insert any in band flow control calendar bits in the multiple use bits 31 24 of the outgoing control words For information about the rx status calendar and tx control status calendar signals refer to Table 5 6 on page 5 5 and Table 5 8 on page 5 7 Status Counters The status counters count the time and the number of CRC 24 errors encountered so far since the RX Operational state was achieved The time counter increments every 318 x 106 rx mac c clk cycles The locked time appears on the rx stat
91. nal can be asserted and deasserted asynchronously but must remain asserted at least four cal blk clk clock cycles Interlaken MegaCore Function User Guide June 2012 Altera Corporation Chapter 5 Signals 5 5 Application Interface Signals Application Interface Signals The application interface provides two channels through which the application receives data from and sends data to the Interlaken link Table 5 5 through Table 5 8 describe the application interface signals RX Application Interface Signals The RX application interface provides two channels through which the application receives data from the Interlaken link Table 5 5 and Table 5 6 describe the RX application interface signals For more information about these signals refer to Packet Regrouper on page 4 19 Table 5 5 RX Application Interface Clock Signal Signal Direction Description Clocks the Interlaken MegaCore function MAC RX block and therefore also the RX application interface For all MegaCore function variations except the 8 lane 3 125 Gbps variations Altera recommends that you drive this signal with the tx_coreclkout signal in variations with transceivers or that you drive this signal with the same clock that drives the rx mac c clk Input tx lane c clksignal in variations without transceivers For the 8 lane 3 125 Gbps variations the xx mac c 1 clock should be driven by a faster clock than the RX PCS clock For these vari
92. ne FIFO Block ue Aligner Buffer p l Calendar Recovery L Block Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 4 Functional Description Receive Path Channel Filtering Blocks 4 19 Each channel filtering block identifies the data that targets the channel with which it is associated It identifies the target channel of a burst from the burst control words The channel filtering block passes that data through to a regrouper filtering out the data that targets the other channel As the channel filter filters the data it rearranges each data sample so that the valid data and idle bytes for its associated channel are the most significant bytes The following example illustrates the function of the channel filtering blocks in a variation with a 256 bit channel width Table 4 6 shows example four word wide raw data output from the RX MAC block Each table cell represents a 64 bit word Table 4 6 Example Raw Data Output From RX MAC Block t 0 BC SOP cho Data 0 Data 1 Data 2 t 1 Data 3 Data 4 BC EOP ch0 SOP ch1 Data 5 t 2 Data 6 Data 7 Data 8 Data 9 t 3 Data 10 Data 11 IDLE EOP ch1 Table 4 7 shows the resulting output stream from the RX channel 0 filter and Table 4 8 shows the resulting output stream from the RX channel 1 filter Table 4 7 Output Stream From RX Channel 0 Filter t 0 B
93. nk 1 in PMA Direct mode ix coreclkout ix pin 4 0 Lanes 5 to 9 Te x5 Li tx pin 4 0 gt Lanes 0 to 4 x5 gt Ix coreclkout June 2012 Altera Corporation Interlaken MegaCore Function User Guide 4 8 Chapter 4 Functional Description Clocking and Reset Structure Figure 4 5 shows the clock diagram for a 12 lane 6 Gbps variation In this variation the transceiver datapath width is 20 The clock diagram for a 12 lane 10 Gbps variation is identical except that the transceiver datapath width is 40 Figure 4 5 Clock Diagram for 12 Lane 6 Gbps Interlaken MegaCore Function cal blk clk 1 gt gt cal bk ref clk ix mac ck gt mac cik rx mac clk gt 1 ck ref clk 1 ix data 79 0 i TX MAC and PCS RX and PCS 1 1 TX data 79 0 jt p x datain 79 0 1 e 1 out master TX clock 1 gt i common rx clk 1 TX dataout 79 0 rx lane clk 3 0 4 1 1 1 1 1 1 1 1 1 1 tx data 159 80 i 1 1 1 1 common rx coreclk _ rx data 159 80 14 rx lane clk 7 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 tx data 239 160 HSIO Bank 0 low latency PCS mode tx pin 3 0 Lanes 8 to 11 TX pin 3 0 gt ix coreclkout 1H gt rx coreclkout P ix datain 79 0 1 common r
94. nterlaken MegaCore function Interlaken link partners to generate and check data samples at opposite ends of the link In that case you would define the TX STRING in each to be identical to the RX STRING in the other Design Example Simulation Sequence The design example performs the following transactions Activates the Interlaken Sample Channel Client on each of the two channels to send data samples to the RX application interface of the Interlaken MegaCore function The channel client actions are described in Interlaken Sample Channel Client Component m Confirms valid data is received by the sample channel client from the relevant channel of the RX application interface of the Interlaken MegaCore function m Keeps track of the count stamp of the latest incoming data sample received and checks that the current data sample count stamp is equal to the previous stamp incremented by one m Monitors the output from each channel of the RX application interface of the Interlaken MegaCore function for CRC 24 and CRC 32 errors After the design example sends and receives 100 packets on each channel with no CRC 24 or CRC 32 errors it declares success and terminates Running a Design Example The steps for running each design example are identical Simply substitute the name of your preferred example from Table 6 1 For purposes of illustration the steps in this chapter refer to the alt interlaken 8lane 6g design example This sect
95. nvalid bytes in the incoming data on tx chX datain datain the current tx mac clk clock cycle The valid data must be in the most significant bytes of the data bus Use of the tx chX datain empty signal on non end of packet cycles is a modification of the Avalon ST interface protocol This modification allows the application to provide the Interlaken MegaCore function with incomplete words of valid data mirroring the same capability on the Interlaken link A two bit signal tx control channel enable allows the application to specify independently for each channel whether the arbiter should accept or ignore its data The application can assert the tx control force transmit signal to tell the arbiter to ignore the RX calendar value when accepting or ignoring input data from the application These two signals provide input to an enable indicator for the channel The arbiter sends its interleaved stream of data to the TX MAC block The information sent out every tx mac c clkclock cycle includes the data start of packet and end of packet indicators and an indicator of the source channel for this data For more information about the arbiter signals refer to TX Application Interface Signals on page 5 6 Application Data Transfer Example Figure 4 7 to Figure 4 10 show an example of a 1016 byte packet transfer on channel 0 For purposes of the example assume that channel 1 is not in use tx ch1 datain validis not asserted or is disabled
96. ob out clk clocks the outgoing out of band flow control interface signals described in the Interlaken specification This clock is generated by the out of band flow control block and sent to a downstream RX out of band flow control block associated with the Interlaken link partner rx in sys clk clocks the outgoing calendar and status information on the application side of the block The frequency of this clock must be at least double the frequency of rx oob in fc clk tx oob in double fc clocks the incoming calendar and status information on the application side of the block The frequency of this clock must be double the frequency of tx oob out clk Clock Diagrams for the Interlaken MegaCore Function Figure 4 2 to Figure 4 6 show the clock diagrams for the Interlaken MegaCore function variations with the supported numbers of lanes The figures show variations with transceivers For figures that show variations without transceivers refer to Appendix B Excluding Transceivers for Faster Simulation The 10 lane and 20 lane variations use the transceivers in PMA Direct mode These variations incorporate five lanes in a single transceiver block The other variations use the transceivers in low latency PCS mode incorporating four lanes in each transceiver block Figure 4 2 shows the clock diagram for a four lane Interlaken MegaCore function Figure 4 2 Clock Diagram for 4 Lane Interlaken MegaCore Function cal
97. ples are derived Length is TX STRING BUFFER WORDS x 64 String against which to check Interlaken RX incoming data PUE samples after they pass through the channel interface The Interlaken Sample Channel Client sends data samples on the channel to which it is connected in the RX application interface Each data sample is some number of bits that fits in WORDS number of 64 bit 8 byte words These are the valid bits in the transmission An internal register of size LOG WORDS holds the number of 64 bit words with at least one valid bit in them and an internal register of size EMPTY BITS holds the number of bytes with no valid bits in them The LOG WORDS and EMPTY BITS parameters can be derived from the value of WORDS but are provided as separate parameters for legibility Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 6 Qsys Design Examples 6 3 Design Example Simulation Sequence The Interlaken Sample Channel Client maintains a string TX STRING from which it generates the data samples It compares the returning data samples against another string of the samelength RX STRING In the design examples the data passes through an Interlaken link external loopback path and so the two strings are identical However the Interlaken Sample Channel Client component is useful in additional testing configurations For example you could create two instances of this component connected to two I
98. pplication Data Interface Signals Part 2 of 2 Signal Direction Description Indicates the number of invalid bytes on the xx chx dataout data bus in the current xx mac c 1 cycle starting from the least significant byte The value 1 indicates that bits 7 0 are invalid the value 2 indicates bits 15 0 are invalid and so on Width is 4 bits for variations with a 128 bit wide channel 206 41 license 5 bits for variations with a 256 bit wide channel 40G 8L license and 6 bits for variations with a 512 bit wide channel either of the 100G licenses For details refer to Table 4 5 on page 4 12 T width 1 RX calendar bits from the recent incoming Interlaken link control word s Each 16 bit calendar page is transferred from the upstream Interlaken partner in bits 55 40 of a single control word The width of the rx status calendar signal is 16 x the number of calendar pages rx status calendar P 0 Output you specified in the Interlaken parameter editor width is 16 128 or 256 bits P width 1 This signal is present only if you expose the calendar pages in the Interlaken parameter editor Refer to In Band Flow Control Parameters on page 3 3 and Calendar and Status Block on page 4 20 rx chX dataout empty T 0 Output Note to Table 5 6 1 The Interlaken MegaCore function supports two channels on the application interface The string chx in a signal name indicates two
99. r lane word lock i signalis not asserted for some lane i this lane has not achieved word lock The RX lanes can establish word lock in the presence of very high bit error rates so bit errors are unlikely to be the cause of the problem Instead focus on the consistency between your MegaCore function data rate and the different clock rates and whether you have an extreme cabling error such as TX RX reversal For information about the recommended clock rates for different Interlaken data rates refer to Clocking and Reset Structure on page 4 5 If the rx status per lane sync lock i signal is not asserted for some lane i this lane has not achieved meta frame lock or has not recovered the scrambler seed successfully Meta frame lock requires a moderate quality connection to the transceiver If the lane does not achieve lock check that the same meta frame length is specified for the two Interlaken link partners and that the cables that connect to your board s transceiver pins meet the requirements of your board specification If the lock is intermittent recheck the physical connection of the link cables to the transceiver and confirm that the analog settings of the transceiver remain at the default values for the Interlaken MegaCore function If the value of rx status per lane crc32 errsis high for any lane while rx status per lane sync lock remains asserted the lane is experiencing CRC 32 errors Because the lane achieved meta frame
100. r output buffer power VCCH TX set to 1 4 V Therefore the MegaCore function requires that you connect the Interlaken interface signals to pins that implement the 1 4 V PCML I O standard This setting increases the data rate range of the Interlaken interface On a Stratix IV GX device this requirement might not be implemented automatically If your design includes high speed transceivers you should enforce this requirement manually To enforce this requirement after you generate the system perform the following steps 1 Interlaken MegaCore Function User Guide In the Quartus II window on the Assignments menu click Assignment Editor June 2012 Altera Corporation Chapter 2 Getting Started Compiling the Full Design and Programming the FPGA 2 9 2 Foreach N perform the following steps a In the lt lt new gt gt cell in the To column type the top level signal name for your Interlaken MegaCore function instance rx serial dataN export signal b Double click in the Assignment Name column and click I O Standard c Double click in the Value column and click 1 4 V PCML 3 Repeat step 2 for your Interlaken MegaCore function instance tx serial dataN export signals Compiling the Full Design and Programming the FPGA You can use the Start Compilation command on the Processing menu in the Quartus II software to compile your design The 10 and 20 lane Interlaken MegaCore function variations require fine tuning to a
101. r shorten the time to achieve lock Larger values reduce overhead while transfering data after lock is achieved For information about achieving lock refer to Appendix A Initializing the Interlaken MegaCore Function Exclude Transceiver Turn on the Exclude transceiver parameter to specify that your Interlaken MegaCore function does not include an HSIO block By default this parameter is turned off Interlaken MegaCore Function User Guide June 2012 Altera Corporation Chapter 3 Parameter Settings 3 3 In Band Flow Control Parameters If this parameter is turned on the Interlaken MegaCore function simulation model and the Interlaken MegaCore function generated RTL both exclude the transceivers This option is available to you for faster simulation However if you exclude the transceivers from your Interlaken MegaCore function you must regenerate and compile with the parameter turned off to create your programming file Enable Out of Band Flow Control Turn on the Enable out of band flow control parameter to specify that your Interlaken MegaCore function includes out of band flow control functionality By default this parameter is not turned on Turning off out of band flow control decreases the resource utilization of your Interlaken MegaCore function and excludes this optional specification feature For more information about the out of band flow control block refer to Out of Band Flow Control Block on page 4 24 I
102. r to the following example assignment to your qsf file Set instance assignment name GLOBAL SIGNAL PERIPHERY CLOCK from transmit pma0 clockout to tx prelaunch d Check the remaining failing paths and force manual placement if needed e Repeat as needed For more information about LogicLock regions refer to the Quartus II Incremental Compilation for Hierarchical and Team Based Design chapter in volume 1 of the Quartus II Handbook For more information about the TimeQuest Timing Analyzer refer to the Quartus II Help and The Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook June 2012 Altera Corporation D Porting an Interlaken Design from the JN DTE RAN Previous Version of the Software This appendix describes how to port your Interlaken design from the previous version of the Interlaken MegaCore function and Quartus II software To upgrade your Interlaken design that you developed and generated using the Interlaken MegaCore function v11 1 to the Interlaken MegaCore function v12 0 perform the following steps 1 2 3 June 2012 Altera Corporation Open the Quartus II software v12 0 On the File menu click Open Project Navigate to the location of the qpf file you generated with the Quartus II software v11 0 Select the qpf file and click Open If the Interlaken IP core was generated using the MegaWizard Plug In Manager originally perform the following
103. ransceiver on chip termination resistors are calibrated by a single calibration cal blk clk Input block which requires a calibration clock The frequency range of cal blk clk is 10 125 MHz For more information refer to the Stratix IV Transceiver Architecture chapter in volume 2 of the Stratix IV Device Handbook pi RS Output Master TX clock from transceiver block 0 Clocks the transmit lanes of all p transceiver blocks internally The physically central clock from among the rx 1 clocks output from the rx coreclkout Output transceiver blocks Drives the common rx c1k input clock to all transceiver blocks internally You can use this clock to drive the xx mac c 1 input clock Interlaken Interface Status Signals Table 5 2 and Table 5 3 describe the Interlaken interface status signals These signals are available whether or not you turn on Exclude transceivers Table 5 2 Interlaken RX Status Interface Signals 1 Part 1 of 2 Signal rx status per lane word lock L 0 Direction Description Indicates lane has locked onto the three bit synchronization header Sixty four consecutive legal sync patterns have been observed Output 64B 67B Word Lock in the Interlaken specification This signal is deasserted when lane word lock is lost according to the Interlaken specification Width is the number of lanes L num lanes 1 rx status per lane sync lock L 0 Indicates lane has locked onto t
104. re 4 18 Figure 4 19 Transceiver Block Use in 10 and 20 lane Variations lane lane lane lane 20 lane ALTGX PCS PMA 20 ALTGX PCS PMA 20 ALTGX PMA 20 FPGA ALTGX PMA 20 ALTGX PCS PMA PCS PMA A four lane variation is configured with a single transceiver block an eight lane variation is configured with two transceiver blocks and a 12 lane variation is configured with three transceiver blocks These variations use four out of the six PMA blocks in each transceiver block A 10 lane variation is configured with two transceiver blocks and a 20 lane variation is configured with four transceiver blocks These variations use five out of the six PMA blocks in each transceiver block Because using five of the PMA blocks requires that one CMU channel be used the transceivers are configured in PMA Direct mode When only four of the PMA blocks are used the transceivers are configured in low latency PCS mode Out of Band Flow Control Block Altera supports the optional inclusion of an out of band flow control block in your Interlaken MegaCore function If you turn on Enable out of band flow control the block is configured in your MegaCore function The block has an out of band flow control interface as defined in Section 5 3 4 2 of the Interlaken Protocol Definition Revision 1 2 You must connect the six signals in this inter
105. rface N 0 for 4 lane variations N 0 1 for 8 and 10 lane variations N 0 1 2 for 12 lane variations and N 0 1 2 3 for 20 lane variations The width of the port for each value of N is the transceiver datapath width times the number of channels used on an Altera device transceiver in variations that include the transceivers For the 12 lane 10 Gbps variation the transceiver datapath width is 40 For all the other variations the transceiver datapath width is 20 The number of channels is 4 for 4 8 and 12 lane variations and 5 for 10 and 20 lane variations S calculated port width 1 Lane 0 holds the MSB of the input data which is input to xx dataN export with the highest value of N Refer to Figure 4 2 on page 4 6 through Figure 4 6 on page 4 9 ignoring the transceivers in the figures In an 8 lane variation xx 1 export 79 60 connects to lane 0 rx datal export 59 40 connects to lane 1 and so on rx data0 export 59 40 connects to lane 5 rx data0 export 39 20 connects to lane 6 and rx data0 export 19 0 connects to lane 7 In a 20 lane variation xx data3 export 99 80 connects to lane 0 rx data3 export 79 60 connects to lane 1 and so on rx data2 export 99 80 connects to lane 5 rx data2 export 79 60 connects to lane 6 and so on rx datal export 99 80 connects to lane 10 rx datal export 19 0 connects to lane 14 rx data0 export 99 80 connects to lane 15 and
106. riations the transceiver datapath width is 20 The number of channels is 4 for 4 8 and 12 lane variations and 5 for 10 and 20 lane variations S calculated port width 1 Lane 0 holds the MSB of the output data which is output on tx dataN export With the highest value of N Refer to Figure 4 2 on page 4 6 through Figure 4 6 on page 4 9 ignoring the transceivers the figures In an 8 lane variation lane 0 is output on tx 1 export 79 60 lane 1 is output tx datal1 export 59 40 and so on lane 5 is output on tx data0 export 59 40 lane 6 is output on tx data0 export 39 20 and lane 7 is output on tx data0 export 19 0 In a 20 lane variation lane 0 is output on tx data3 export 99 80 lane 1 is output on tx data3 export 79 60 and so on lane 5 is output on tx data2 export 99 80 lane 6 is output on tx data2 export 79 60 and so on lane 10 is output on tx_datal_export 99 80 lane 14 is output on tx 1 export 19 0 lane 15 is output on tx data0 export 99 80 and lane 19 is output on tx datao export 19 0 June 2012 Altera Corporation Interlaken MegaCore Function User Guide Appendix B Excluding Transceivers for Faster Simulation Reset in Interlaken MegaCore Functions Without Transceivers Table B 1 External Transceiver Interface Signals Part 2 of 2 Signal rx dataN export S 0 Direction Input Description Parallel receive data inte
107. rtner in bits 55 40 of a single control word The width of the tx control tx calendar signal is 16 x the number of calendar pages you specified in the Interlaken parameter editor width is 16 128 or 256 bits P width 1 This signal is present only if you expose the calendar pages in the Interlaken parameter editor Refer to In Band Flow Control Parameters on page 3 3 and Calendar and Status Block on page 4 20 June 2012 Altera Corporation Interlaken MegaCore Function User Guide 5 8 Chapter 5 Signals Out of Band Flow Control Interface Signals Table 5 8 TX Application Interface Signals Part 2 of 2 Signal Direction Description Holds the next value of the BurstMax Interlaken parameter for dynamic configuration The Interlaken MegaCore function supports the following valid values for BurstMax tx control burst max in 3 0 Input m 128 bytes specified with tx control burst max in 2 m 256 bytes specified with tx control burst max 4 This signal is present only if you enable dynamic configuration of the Interlaken burst parameters in the Interlaken parameter editor Holds the next value of the BurstShort Interlaken parameter for dynamic configuration The Interlaken MegaCore function supports the following valid values for BurstShort in Interlaken variations that support dynamic configuration of BurstShort m 32 bytes specified with tx control burst short 2 tx control b
108. rts the following interfaces m Interlaken Interface m Application Interface m Out of Band Flow Control Interface Interlaken Interface The Interlaken interface complies with the Interlaken Protocol Definition Revision 1 2 It provides a high speed transceiver interface to an Interlaken link Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 4 Functional Description Interfaces Overview 4 3 The Interlaken MegaCore function value for the Interlaken BurstMax parameter is configurable You can specify BurstMax to be dynamically configurable or you can configure a static value in the Interlaken parameter editor as described in Chapter 3 Parameter Settings The Interlaken MegaCore function supports two values for BurstMax 128 bytes and 256 bytes The default static value is 128 bytes for all variations The default value of BurstShort in Interlaken MegaCore function variations with a 512 bit wide datapath is 32 bytes However for these variations you can specify BurstShort to be dynamically configurable to 32 bytes or 64 bytes or you can configure a static value of 32 bytes or 64 bytes as described in Chapter 3 Parameter Settings Table 4 1 shows the Interlaken MegaCore function values for the Interlaken BurstShort parameter Table 4 1 BurstShort Value in Bytes Lane Rate Gbps Number of Lanes 3 125 6 25 6 375 10 3125 4 16 0 16 0 16 0 8 16 0 32
109. rx data0 export 19 0 connects to lane 19 Ter tx lane c clk Input Clocks the Interlaken transmit lanes rx lane clkN export M 0 Input Clock inputs from external transceivers N 0 for 4 lane variations N 0 1 for 8 and 10 lane variations N 0 1 2 for 12 lane variations and N 0 1 2 3 for 20 lane variations The width of the port is 4 M 3 for 4 8 and 12 lane variations and 5 M 4 for 10 and 20 lane variations common rx Output This signal is tied to 0 when the external transceiver interface is exposed Reset in Interlaken MegaCore Functions Without Transceivers If you turn on Exclude transceivers your Interlaken MegaCore function does not include a reset controller block Therefore you must implement the required reset sequence yourself This section lists the individual reset signals available in these variations and describes the reset sequence your testbench must enforce Interlaken MegaCore Function User Guide June 2012 Altera Corporation Appendix B Excluding Transceivers for Faster Simulation B 7 Reset in Interlaken MegaCore Functions Without Transceivers Reset Signals In an Interlaken MegaCore function that excludes transceivers the reset export signal is not available Table 2 lists the individual reset signals that are available to your testbench to reset the Interlaken MegaCore function with their associated clock domain Ta
110. s Lane 0 holds the MSB of the output data which is output on the HSIO bank with the highest number Refer to Figure 4 2 on page 4 6 through Figure 4 6 on page 4 9 In an 8 lane variation lane 0 is output on tx serial datal export 3 lane 1 is output on tx serial datal export 2 and so on lane 5 is output on tx serial data0 export 2 lane 6 is output on tx serial data0 export 1 0 lane 7 is output on tx serial data0 export 0 In a 20 lane variation lane 0 is output on tx serial data3 export 4 lane 1 is output on tx serial data3 export 3 and so on lane 5 is output on tx serial data2 export 4 lane 6 is output on tx serial data2 export 3 lane 10 is output on tx serial datal export 4 lane 14 is output on tx serial datal export 0 lane 15 is output tx serial data0 export 4 lane 19 is output on tx serial data0 export 0 and so on and Interlaken MegaCore Function User Guide June 2012 Altera Corporation Chapter 5 Signals 5 3 Interlaken Interface and External Transceiver Interface Signals Table 5 1 Interlaken Data Interface Signals Part 2 of 2 Signal Direction Description Main transceiver reference clock Refer to Transceiver Reference Clock ref clk Input P Recommended Frequency and Source on page 4 10 Calibration clock for transceiver on chip termination resistors The Stratix IV GX t
111. s available if you turn off Enable dynamic burst parameters Supported static BurstMax length values are 128 bytes and 256 bytes Parameterized Static BurstShort Value If you turn off Enable dynamic burst parameters you can specify the static value of BurstShort that is configured in your 12 lane 10 3125 Gbps or 20 lane Interlaken variation In these Interlaken variations the default value of the BurstShort Interlaken parameter is 32 bytes but you can specify with the BURST SHORT length in bytes parameter that it be set to 64 bytes instead In other Interlaken MegaCore variations if you turn off Enable dynamic burst parameters the static value of BurstShort is 16 bytes in variations with a 128 bit datapath and 32 bytes in variations with a 256 bit datapath as shown in Table 4 1 on page 4 3 Interlaken MegaCore Function June 2012 Altera Corporation User Guide N D SYAN 4 Functional Description The Interlaken MegaCore function provides the functionality described in the Interlaken Protocol Definition Revision 1 2 and arbitration between two incoming user defined channels and regroups received data to two outgoing user defined channels This chapter describes the individual interfaces and main blocks of the Interlaken MegaCore function and how data passes between them This chapter contains the following sections June 2012 Altera Corporation Architecture Overview Interfaces Overview Clocking and Reset S
112. s to set the parameter Add this parameter to the parameter list in your HSIO bank instances with the value 1 b1 The HSIO bank instances for the different variations are instantiations of the modules alt ntrlkn hsio bank bpcs4 alt ntrlkn hsio bank 10g alt ntrlkn hsio bank bpcs 3g oralt ntrlkn hsio bank pmad5 Qsys Design Flow You can use Osys to build a system that contains your customized Interlaken MegaCore function You can easily add other components and quickly create a Osys system Osys can automatically generate HDL files that include all of the specified components and interconnections The HDL files are ready to be compiled by the Quartus II software to produce output files for programming an Altera device Interlaken MegaCore Function User Guide June 2012 Altera Corporation Chapter 2 Getting Started 2 5 Qsys Design Flow Figure 2 2 shows a block diagram of an example Osys system Figure 2 2 Qsys System Interlaken Link Partner i Interlaken MegaCore Function Avalon Streaming m Streaming Connection Interlaken Interlaken Client Client System Interconnect EE DMA On Chip On Chip Controller FIFO Buffer Memory Qsys System UT For Information About Refer To Qsys Interconnect chapter in volume 1 of the Quartus II Handbook and the Avalon Interface Specifications Creating a System with
113. te words mirroring the same capability on the Interlaken link For more information about the application interface refer to Arbiter on page 4 12 and Packet Regrouper on page 4 19 St For more information about the Avalon ST interface refer to Avalon Interface Specifications Optional In Band Flow Control and Dynamic Configuration Signals Depending on the parameter values you set in the Interlaken parameter editor the application interface may include additional signals that the application controls to dynamically configure the BurstMax and BurstShort signals or receives and controls to manage the in band flow control bits on the Interlaken link For more infomation about BurstMax and BurstShort configuration refer to Interlaken Interface and to Table 5 8 on page 5 7 For more information about the in band flow control signals refer to Calendar and Status Block on page 4 20 and to Table 5 6 on page 5 5 and Table 5 8 on page 5 7 Out of Band Flow Control Interface The out of band flow control interface conforms to the out of band requirements in Section 5 3 4 2 Out of Band Flow Control of the Interlaken Protocol Definition Revision 1 2 This interface is included in the Interlaken MegaCore function if you turn on the Enable out of band flow control parameter For more information refer to Out of Band Flow Control Block on page 4 24 Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 4
114. the tx oob out clk clock at 100 MHz Table 5 12 TX Out of Band Flow Control Block Signals for Application Use Signal tx in double fc clk Direction Input Description Reference clock for generating the flow control output clock tx oob out clk The frequency of the tx oob in double fc clk clock must be double the intended frequency of tx oob out clk tx oob in double fc arst Input Asynchronous reset for the out of band TX block tx oob in ena status Input Enable transmission of the lane status and link status to the downstream out of band RX block If this signal is asserted the lane and link status information is transmitted on tx oob out data If this signal is not asserted only the calendar information is transmitted on tx oob out data tx oob in lane status L 0 Input Lane status to be transmitted to a downstream out of band RX block if tx in ena status is asserted Width is the number of lanes L num lanes 1 tx oob in link status Input Link status to be transmitted to a downstream out of band RX block if tx oob in ena status is asserted tx in calendar 15 0 Input Calendar status to be transmitted to a downstream out of band RX block Note to Table 5 12 1 Altera recommends that you run tx oob in double fc clk at 200 MHz to support the recommended and maximum allowed tx oob out clk frequency of 100 M
115. ting the properties of the Interlaken MegaCore function instance Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 2 Getting Started 2 3 MegaWizard Plug in Manager Design Flow MegaWizard Plug in Manager Design Flow The MegaWizard Plug in Manager flow allows you to customize the Interlaken MegaCore function and manually integrate the function in your design Specifying Parameters and Generating the MegaCore Function To specify Interlaken MegaCore function parameters using the MegaWizard Plug In Manager perform the following steps 1 6 Create a Quartus II project using the New Project Wizard available from the File menu Ensure that you target a device family supported by the Interlaken MegaCore function Launch the MegaWizard Plug in Manager from the Tools menu and follow the prompts in the MegaWizard Plug In Manager interface to create a custom megafunction variation To select the Interlaken MegaCore function click Installed Plug Ins gt Interfaces gt Interlaken gt Interlaken v lt version gt Specify the parameters in the Interlaken parameter editor For details about these parameters refer to Chapter 3 Parameter Settings Click Finish to generate the MegaCore function and supporting files IEEE encrypted functional simulation models for the simulators listed in the Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook are included in the supporting
116. tional simulation model and the synthesizable RTL Therefore you should expect to regenerate your Interlaken IP core with the transceivers after you verify your design in simulation Excluding the transceivers from the Interlaken MegaCore function also excludes the reset controller Therefore if you exclude transceivers from your Interlaken MegaCore function your testbench must control the individual resets for the different internal blocks of the Interlaken MegaCore function The external transceiver interface provides parallel transmit and receive datapaths plus the necessary clock signals to allow you to connect the Interlaken MegaCore function to high speed transceivers in your design In addition it provides reset signals to reset the individual MegaCore function blocks An Interlaken MegaCore function that excludes transceivers can include or exclude the out of band flow control block June 2012 Altera Corporation Interlaken MegaCore Function User Guide B 2 Appendix B Excluding Transceivers for Faster Simulation External Transceiver Interface Clocks Figure B 1 illustrates how the external transceiver interface is derived from the full Interlaken MegaCore function Figure B 1 Interlaken MegaCore Function Block Diagram Showing the External Transceiver Interface Interlaken MegaCore Function Channel 0 _ TX TX MAC PCS S Arbiter Channel 1
117. tructure on page 4 5 Transmit Path on page 4 11 Receive Path on page 4 17 Calendar and Status Block on page 4 20 High Speed I O Block on page 4 22 Out of Band Flow Control Block on page 4 24 Interlaken MegaCore Function User Guide 4 2 Chapter 4 Functional Description Architecture Overview Architecture Overview Figure 4 1 shows the main blocks of the Interlaken MegaCore function Figure 4 1 Interlaken MegaCore Function Block Diagram Interlaken MegaCore Function HSIO Block Channel 0 TX TX Arbiter MAC PCS z gt 5 Channel 1 I 2 5 S p amp 9 g E Calendar s m Application 1 Z Interlak and e o nterlaken Interface ee i 2 BEEN Interface o o o 2 Es i oc Packet Filter 2 Channel 0 c RX RX 2 Rearoi and a egroup Buffer PCS E lt o Filter i Channel 1 4 4 4 and Buffer TX Out of Band Flow Control Out of Band Calendar and lane link status E Flow Control 4 RX Out of Band Interface Flow Control Out of Band Flow Control Block The following sections describe the individual interfaces clocks and blocks Interfaces Overview The Altera Interlaken MegaCore function suppo
118. ts that generate input to the application interface and check the resulting output The Interlaken link transmit lines are connected to the receive lines creating an external feedback loop From the Qsys system provided with each design example Osys automatically generates Verilog HDL files that include all the required components and interconnections Qsys also generates IEEE encrypted functional simulation models for some third party simulation tools as described in Simulating the System on page 2 6 The Verilog HDL files that generates are ready to be compiled in the Quartus II software for programming an Altera device June 2012 Altera Corporation Interlaken MegaCore Function User Guide 6 2 Chapter 6 Qsys Design Examples Interlaken Sample Channel Client Component a For more information about the interconnect fabric that Osys generates refer to the Osys Interconnect chapter in volume 1 of the Quartus II Handbook For more information about Osys refer to the Creating a System with Osys chapter in volume 1 of the Quartus II Handbook The design example files are provided in the Interlaken IP core installation directory You can use them as a basis for developing your own testbench for your Interlaken MegaCore function variation Based on the example you can create your own stimuli and verification criteria using the Interlaken Sample Channel Client component available in the Osys tool Interlaken Sample Channe
119. uad location is any valid quad location on your device It may be any of QLn or ORn for n in 0 1 2 3 depending on the device PLL path is lt ntrlkn hsio bank alt ilk hsio bank n tx 11 0 for any valid high speed I O HSIO bank number n The valid HSIO bank numbers depend on the number of lanes in your Interlaken MegaCore function variation Table 2 1 shows the valid HSIO bank numbers Table 2 1 Valid HSIO Bank Numhers Depending on Number of Lanes Valid HSIO Bank Numbers Number of Lanes 0 1 2 3 4 v 8 v v 10 v v 12 Y v v 20 v Y v v To add the constraint using the Assignment Editor perform the following steps 1 Open your Quartus II project in the Quartus II software 2 On the Processing menu point to Start and click Start Analysis amp Elaboration The analysis and elaboration process might take several minutes to complete June 2012 Altera Corporation Interlaken MegaCore Function User Guide 2 8 Sog OO U d ft 10 11 12 13 Chapter 2 Getting Started Specifying Constraints On the Assignments menu click Assignment Editor Click lt lt new gt gt to edit a new assignment Double click the new row in the Assignment Name column and select Location Double click the new row in the To column Click the Node Finder icon The Node Finder dialog box appears Ensure that Filter is set to Design Entry all n
120. ur functional simulation model s interface to and from the Interlaken link transceivers presents the data in slightly different format and exposes different clocks In addition the application or testbench must implement the reset sequence For more information refer to Appendix B Excluding Transceivers for Faster Simulation Application Interface The application interface provides two channels of communication to and from the Interlaken link Each channel in each direction is implemented as an Avalon ST interface with one modification The width of the Avalon ST interfaces depends on the number of lanes in the Interlaken MegaCore function instance Depending on the parameter values you set in the Interlaken parameter editor additional signals may be available to the application Avalon ST Interface The Avalon ST interface provides a standard flexible and modular protocol for data transfers from a source interface to a sink interface The Avalon ST interface protocol allows you to easily connect components to the Interlaken MegaCore function The application interface implements an Avalon ST interface with a modification in how the empty signal is used and monitored In the Avalon ST interface the empty signal is monitored only when end of packet is asserted However the application interface asserts and monitors this signal during other data valid clock cycles as well This modification allows the application to provide data in incomple
121. urst short in x 3 0 Input m 64 bytes specified with tx control burst short 4 This signal is present only if you enable dynamic configuration of the Interlaken burst parameters in the Interlaken parameter editor For information about the Interlaken variations that support enabling BurstShort dynamic configuration refer to Burst Parameters on page 3 3 and Interlaken Interface on page 4 2 Note to Table 5 8 1 The Interlaken MegaCore function supports two channels on the application interface The string chx in a signal name indicates two distinct signal names one with cno and one with ch1 corresponding to the two channels channel 0 and channel 1 Out of Band Flow Control Interface Signals The out of band flow control interface is present only in Interlaken MegaCore function variations that include an out of band flow control block Table 5 9 and Table 5 11 describe the out of band flow control interface signals RX Out of Band Flow Control Signals The receive out of band flow control interface receives input flow control clock data and sync signals and sends out calendar and status information Table 5 9 describes the receive out of band flow control interface signals specified in the Interlaken Protocol Definition Revision 1 2 Table 5 10 describes the signals on the application side of the RX out of band flow control block Table 5 9 RX Out of Band Flow Control Int
122. us locked time status signal bus For information about the individual output status signals refer to Table 5 2 on page 5 3 High Speed 1 0 Block The high speed I O HSIO block comprises multiple ALTGX megafunction blocks and an optional FIFO and pipeline registers block The FIFO and pipeline registers block is instantiated only when the ALTGX megafunction operates in PMA Direct mode The ALTGX megafunction is configured in PMA Direct mode in 10 and 20 lane Interlaken MegaCore function variations and in low latency PCS mode in the other variations Interlaken MegaCore Function June 2012 Altera Corporation User Guide Chapter 4 Functional Description 4 23 High Speed 1 0 Block FIFO Buffers and Pipeline Registers Achieving timing closure can be difficult for the 10 and 20 lane Interlaken variations which use the Stratix IV transceivers in PMA Direct mode To resolve timing issues between the PMA Direct SERDES block in the transceiver and the Interlaken MegaCore function the FIFO buffer and pipeline registers block is instantiated for variations that use PMA Direct mode The block includes a two stage register pipeline and a clock crossing FIFO buffer Figure 4 17 shows the receive and transmit paths through this block Figure 4 17 FIFO Buffer and Pipeline Registers Block From EL I I
123. w You cannot simulate the Interlaken MegaCore function in the ModelSim Altera ModelSim AE simulator ModelSim AE is the simulation tool provided with the Quartus II software For Information About Quartus software MegaWizard Plug In Manager Refer To See the Quartus II Help topics About the Quartus Software About the MegaWizard Plug In Manager Functional simulation models for Altera IP cores Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook Instantiating the MegaCore Function in Your Design After you generate your Interlaken MegaCore function variation you can instantiate it in the RTL for your design When you integrate your Interlaken MegaCore function variation in your design note the following connection and assignment requirements and recommendations m If you turn off Exclude transceiver when you parameterize your Interlaken MegaCore function you must ensure that you connect the calibration clock cal blk clkto a clock signal with the appropriate frequency range of 10 125 MHz The cal blk clk ports on other components that use the same transceiver block must be connected to the same clock signal m Ifyou turn off Exclude transceiver when you parameterize your Interlaken MegaCore function you should set the RTL parameter SIM FAST RESET to 1 to improve your transceiver simulation time In this version of the Interlaken MegaCore function you must modify your RTL file
124. x clk 1 IX dataout 79 0 X cli 3 0 DNE p 2 bp HSIO Bank 1 eL low latency PCS mode e p clk in tx pin 3 0 gt x datain 79 0 Lanes 4 to 7 1X pin 3 0 1 common rx clk i X dataout 79 0 1 rx_clk 3 0 E SCA 4 i ur eee ADI tU a a HSIO Bank 2 gt cal bk low latency PCS mode Lp ref clk 1 tx pin 3 0 Lanes 0 to 3 TX pin 3 0 Interlaken MegaCore Function User Guide June 2012 Altera Corporation Chapter 4 Functional Description Clocking and Reset Structure Figure 4 6 shows the clock diagram for a 20 lane Interlaken MegaCore function This variation uses the transceivers in PMA Direct mode For more information refer to High Speed I O Block on page 4 22 Figure 4 6 Clock Diagram for 20 Lane Interlaken MegaCore Function tx coreclkout HSIO Bank 0 in PMA Direct mode tx pin 4 0 rx_pin 4 0 HSIO Bank 1 1 cal clk P gt ref_clk LS tp ref clk 1 tx gt clk in TX MAC tx data 99 0 gt ix datain 99 0 PCS 1 out master TX clock Lanes 15 to 19 i gt common rx clk 1 rx data 99 0 lt lt 1 X dataout 99 0 rx_clk 4 0 1 rx_clk 4 0 1 tx mac c I tx mac clk rx mac c clk I p rx mac i cal

Interlaken MegaCore Function v12.0 User Guide

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