EB675001DIP User Guide
Contents
1. lt VL when nwait_i 0 or user wait 0 else 0 user wait n lt 11 8 or the schematic fragment Figure 4 8 Webpack XWAIT schematic fragment xwait_oy ORZ user n any user design must include this or something very similar or the module will appear to stop on any IO access The CPLD is intended to be accessed as a memory mapped device using the OKI processors external memory controller The ML675001 has four external I O regions these are decoded into 64MB regions at OxF0000000 OxF4000000 0xF8000000 and A read or write by the CPU to these regions causes a full external I O cycle to be per formed qualified by the appropriate chip select lines CSO CS1 CS2 or CS3 The OKI manual contains full information on how to adjust timing cycles and access type as appropriate The user CPLD has access to half of the CSO area and all of CS2 and CS3 The CSO signal presented to the user CPLD sometimes referred to as CPLD ENABLE has already been decoded by the system CPLD and is active only for the first Simtec Electronics 21 Chapter 4 Design Guide 32MB of the region the other 32MB being decoded to the Ethernet controller The CSO area is provided address space OxF0000000 to OXFODFFFFF because only in this region can the I O Wait line be used to delay an IO cycle CPLD If the user design needs to generate interrupts an interrupt line one of IRQI IRQ2 and IRQ3 on pins A12 11 10 should2. SIMTEC ELECTRONICS EB675001DIP User Guide Simtec Electronics V R Sanders EB675001DIP User Guide Simtec Electronics by B J Dooks and V Sanders Copyright O 2005 Simtec Electronics is a registered trademark of ARM Limited LINUXO is a registered trademark of Linus Torvalds UNIX is a registerd trademark of The Open Group All other trademarks are acknowledged The product described in this document is under continuous development and improvement All descriptions of usage and particulars of the product are given in good faith by Simtec Electronics However all warranties expressed or implied including but not limited to implied warranties or merchantabil ity or fitness for purpose are excluded While every precaution has been taken in the preparation of this book the publisher assumes no responsibility for errors or omissions or for damages resulting from the use of the information contained herein Revision History Revision 1 00 20th July 2005 VRS Initial Release Revision 1 01 27th July 2005 VRS Formatting updates and improvements Revision 1 1 9th January 2006 VRS Improve design guide section Revision 1 11 4th April 2006 VRS Formatting updates and improvements Revision 1 2 12th April 2007 VRS Fix user CPLD pin numbering in Table 2 1 60 way PTH connector PL3 Revision 1 3 5th October 2007 VRS Clarify IRQO use on the Section 2 6 DM9000 Network controller and Section 2 5 R
3. selected all wr for console write stream selected all rd for console read stream DRAM 128 Mb 134217728 bytes BASIS PMU version 1502 ID Q0 S01 0 5 000 11 929 Nas 2206 oaie e Ager aite mei Aor 1635 25 BSL 2005 hdc TOSHIBA MK1003MAV ATA PIO mode 4 hdc Diagnosing disc drive ok hdc 1GB hd0 on hdc1 ext2 moll hele2 MESS Chis wil 00 20 1 5 1 COs Os dar jolay Jta Ok dimisi wil cuales E2000 ne0 ISA Generic 00 01 3d 00 01 6b EEPROM Invalid Missing MENE OEA exzeor ys autoshadow unset automatically shadowing 0 Example 3 2 Serial display after starting ABLE EB2410ITX SuperIO controller fitted 2 1 SIS GT Detecting SDRAM size SDRAM BANK6 size 04000000 SDRAM BANK7 size 04000000 13 Chapter 3 Bootloader ABLE 2 08 s3c2410x vince gerald Fri Apr 8 16 35 26 BST 2005 Processor Samsung 3C2410A arm920 System Machine bast s3c2410x Linux id 0x014b JSSC24105 RITCS 1 46 54 00 01 2003 NAND configured boot slot is 0 card slot NAND found Samsung K9F1208u0a 131072 32 512 flash0 on 1 flashl on nand0p2 jffs2 EPROM 24cXX 1024 bytes single byte addressed nvram0 on 24cxx sys speed is unset Setting CPU Speed to 266MHz no configuration defaulting to VGA X Y values invalid configuring automatically Chrontel CH7006 detected Screen mode is 640
4. E He mee hee he he rhe rre rennen 25 vi Simtec Electronics List of Tables 2 1760 Way PTH connector PEZ eed tere ep ert ata tasses 9 2 260 way PTHscopnnector PLA Baii o DRUSI ope eU bou 11 vil viii Simtec Electronics List of Examples 3 1 Video display after starting ABLE on EB2410ITX 3 2 Serial display after starting ABLE on EB2410ITX Simtec Electronics EB675001DIP Development Board About this document This document describes the Simtec EB675001DIP Development board which provides a flexible devlopemnt system for both experimentation and intergrator solutions Intended Audience This document is aimed at experienced engineers Related documents Some additional documents which may be useful Bootstraping EB675001DIP http www simtec co uk products EB675001DIP files EB675001DIP bootstrap html Connector and link pinouts http www simtec co uk products EB675001DIP files pinlist html Memory map and control registers http www simtec co uk products EB675001DIP files mmap html Mechanical Drawing http www simtec co uk products EB675001DIP files EB675001DIP mechanical pdf Feedback Any suggestions comments or corrections concerning this document are welcomed please contact Simtec Electronics giving The document title The document revision A clear explanation of your comments and how they apply xi xii Simtec Electronics Chapter 1 Ove
5. connector with a simple IDC cable Figure 4 2 EB675001DIP header to multi ICE JTAG cable schematic GND NRST TRST This schematic of the cable while accurate does not make the simplicity of the cable immediately obvious An image of a completed IDC cable gives a better representation Figure 4 3 EB675001DIP header to multi ICE JTAG cable 18 Simtec Electronics Power Supply 4 3 Power Supply The first and perhaps most obvious requirement is the power supply to the module The designer has two choices either to use the modules on board linear power regulator or to supply a suitably regulated 3 3V supply If the designer chooses to use the on board regulation a simple supply providing 5 12V DC is required although there is adequate smoothing on board an additional 47uF electrolytic type capacitor will ensure any transient power sags will be dealt with If using this supply method the modules 3 3V rails can supply 50mA or so of additional current to external devices such as buffers or small logic devices Good decoupling and grounding must be used if the module supplies ex ternal devices Figure 4 4 Schematic fragment using on board EB675001DIP power regulation DC21P GND GND 3V3 CPLD PIN94 CPLD PIN93 CPLD PIN96 CPLD PIN95 CPLD PINO 1 CPLD PIN97 CPLD_PINO4 CPLD_PINO3 CPLD_PINO8 CPLD_PINO6 On board regulation is not efficient the exact power usage is outlined in Figure 2 9 Graph of EB675
6. 001DIP power us age If the on board regulation will not meet the designers power requirement a 3 3V off board regulator can be used to supply power to both the module and the other application hardware Because the user CPLD can alter the required power provi sion for a maximum current of 0 5A 1 6W should be made for the module The circuit outlined in Figure 4 5 Schematic fragment of flexible EB675001DIP power supply provides for both on board or off board regulation Only one of the zero ohm resistors R1 and R2 should be fitted R1 for off board regulation and R2 with REGI omitted if on board regulation is to be used R1 should be used in off board mode to ensure the internal regulator is not placed in parallel with the extern al one Figure 4 5 Schematic fragment of flexible EB675001DIP power supply GND Simtec Electronics 19 Chapter 4 Design Guide The linear regulator methods both on board and external work well for low input voltages and can produce adequate power for small circuits without requiring extensive heatsinks and cooling For higher power or input voltage requirements a DC to DC converter can be used to generate 3 3V with much greater efficiencies One possible circuit is outlined here this is a simple step down switcher arrangement capable of producing 3W from a wide input voltage The example circuit shown here can be built from simple through hole components and is generally in sensitive to layout
7. Ann gos da aa 13 Ene un FM EE 13 3 2 Getting Started E LEER la EST E e at pes ODE dK Gate a Patte tale E a OIX dee 13 3 2 1 Using hyperterm as a serial console eee HH erre 14 3 2 2 Using minicom as a serial console eei ette Eee robes io at sa e riendas 15 4 Design Guide Solace enge ipte rte sooo uie t aa va Sabana ver ety cundi ione ate aa ree ep ue aaa 17 4 Overview itti tote don te Re Potete Or ob c vas O nea Bta heb Getestet ra rez aed 17 4 2 ConnectIons eaa eoo veces ate pres ope Dee te Suede pepe E rt une deat geek iata Uie Eo ede 17 AS Power Supply ss oe eU eo eben teur teet be chives Erbe ob ver EE ree ai 19 4 45 User CBED eee tool Bu neto Uer deese rin ann da edet oua det e doe eae dee eR d 20 A Board Layout it DUE eo ee tu aa aaa ade Sek o Eee dec ed 23 Mechanical drawing e sasea erede Pop erp sone Ree iar ela ores uec ee payne Use Fe Xeno ser e Ra Er dor qe e Oaie ea 25 lil iv Simtec Electronics List of Figures 2 1 Detailed block diagram of the EB675001DIP eee nene eee eee aan an 3 2 2 NOR flash to ML675001 attachment sise 5 2 3 SRAM ME673001 attachment sia mata yas Pet di a a ls tienne ent a URS ra 5 2 4 SDRAM to ML675001 attachment ee enm en he mene eere nee ana 6 2 5 J T AG COBn6CIOE aoi tee etr rtr PRO PR Rr Pepe PRO ss Maa d
8. G sab ala nn ai sta aliate ami 6 2 6 DM9000 to ML675001 attachment a em emm ent ent e mee he eme he rhe ree renes 7 2 7 Xilinx XL9572XL to ML675001 attachment e e m e HH mH men en he mee ree reete 7 2 8 Serial veniri 8 2 9 Graph of EB675001DIP power usage c HH e e ee ent e thee ene en aaa ana 8 2 10 Expansion connector placement centre e besten owes Oued ov unter net nr is 9 3 1 Hypertermset ngs Window ose ve REN ve Ee eR 14 3 2 Hyperterm displaying ABLE output iret re po i p EE ee ppi E VEES E sede 15 3 3 Minicorm settings WINdOW MM rea alaltaieri 15 4 1 Schematic fragment using EB675001DIP Ethernet header 17 4 2 EB675001DIP header to multi ICE JTAG cable schematic eme 18 4 3 EB675001DIP header to multi ICE JTAG cable eee eee em eher 18 4 4 Schematic fragment using on board EB675001DIP power regulation e eee 19 4 5 Schematic fragment of flexible EB675001DIP power supply sse 19 4 6 Schematic fragment of DC DC converter EB675001DIP power supply eee nene 20 4 7 Pseudo schematic fragment of EB675001DIP user CPLD c semen 20 4 8 Webpack XW AIT schematic fragment sise 21 A 1 EB675001DIP board layout top side e em e mme mH III Hn emm mee rene ree 23 A 2 EB675001DIP board layout bottom side issues 23 B 1 EB675001DIP Mechanical Drawing e me E
9. NOR flash device This device typically contains the bootloader and uC Linux image to boot though it can contain anything the user requires The flash is implemented as a single sixteen bit wide device which is selected by use of the nROMCS chip select from the ML675001 This memory appears in bank 25 of the ML675001 memory map Figure 2 2 NOR flash to ML675001 attachment NOR Flash SST39VF640XQBGA 16Mbit U13 A O 21 A 1 22 D 0 15 D 0 15 nWE nXWE nOE nXOE nCE nROMCS nRESET nRST 2 3 2 SRAM OKI ML675001 The EB675001DIP has provision for an SRAM device this is in addition to the 32KB of internal zero wait state memory that is internal to the ML675001 This memory is typically only fitted in the silver configuration of the board The SRAM is implemented as a single sixteen bit wide device which is selected by use of the nRAMCS chip select from the ML 675001 This memory appears in bank 26 of the ML675001 memory map Figure 2 3 SRAM to ML675001 attachment SRAM K6F1616U6A F 2Mbit U12 A 0 19 A 1 20 D 0 15 D 0 15 nWE nXWE nOE nXOE nCS1 nRAMCS nUB nXBYTESEL1 nLB nXBYTESELO Simtec Electronics OKI ML675001 U11 Chapter 2 Hardware Description 2 3 3 SDRAM The EB675001DIP has provision for a single SDRAM device with either the default 256MBit capacity or a 512MBit capa city This memory where fitted is ac
10. TAG cable is documented in the PlayXSVF User Guide ht tp www simtec co uk products EB675001DIP files playxsvf book The user CPLD is connected to the OKI processors external data address and control lines as shown in Figure 4 7 Pseudo schematic fragment of EB675001DIP user CPLD There are 40 uncommitted CPLD pins available on the expan sion headers The schematic fragment does show all the lines and the CPLD pins they are connected to however the EB675001DIP resources User CPLD section http www simtec co uk products EB675001DIP resources html usercpld contains some examples and template projects for use with Xilinx webpack software These examples include a suitable constraints and pin naming file so the signals can be referred to with meaningful symbolic names Figure 4 7 Pseudo schematic fragment of EB675001DIP user CPLD Simtec Electronics User CPLD USER_CPLD XC9572XL TQ100 The user CPLD is coupled into the CPU IO XWAIT signal on CPLD pin 25 which allows I O cycles to be extended by slow peripherals The XWAIT is only used by the CPU within the first external chip select region CSO The inverted I O wait request from the Ethernet controller is also brought to the CPLD pin 20 The designer must ensure the relevant logic is used to combine the nWAIT input and any internal I O wait requirement to generate a correct XWAIT output The sup plied templates include the VHDL xwait
11. Unbuffered UART CTS signal or CPU GPIO PIOA 2 Analog inputs ground ANALOG GND A24 B24 TX Unbuffered UART TX reference signal or CPU GPIO PIOA 1 Analog inputs supply VDD ANALOG A25 B25 RX Unbuffered UART RX reference signal or CPU GPIO PIOA 0 Buffered RS232 level RS232 DCD A26 26 RS232_DSR Buffered RS232 level UART DCD signal UART DSR signal Buffered RS232 level RS232 RX A27 B27 RS232_RTS Buffered RS232 level UART RX signal UART RTS signal Buffered RS232 level RS232 TX A28 B28 RS232_CTS Buffered RS232 level UART TX signal CTS signal Buffered RS232 level RS232 A29 B29 RS232 RI Buffered RS232 level UART DTR signal UART RI signal Serial port ground GND A30 B30 SERIAL EN RS232 buffer enable Simtec Electronics Chapter 3 Bootloader 3 1 Overview The Simtec Electronics Advanced Boot Load Environment ABLE is a portable modular boot loader for use in applica tions where an OS must be retrieved and started ABLE provides extended functionality providing modules for a command line video consoles serial consoles network booting and numerous other facilities ABLE is a powerful tool and provides a very flexible environment useful for both development and deployment of sys tems ABLE is a boot loader not an Operating System this distinction can sometimes lead to misunderstandings about the capabilities provided by ABLE A boot loader in this context 15 a self contained program which retrieves a
12. be connected to a CPLD nearby pin A3 to A7 The IRQO should not be used as this is shared with the Ethernet controller and unless specially coded for will prevent correct network operation The CLK input is connected to the OKI CPU CKO clock output pin this clock runs at the CPU HCLK frequency which is typically configured to 58 976MHz 7 372MHz baud rate clock with PLL multiplier of 8 The reset line is the global system reset and should be used to reset any internal state The signal is active low and is typic ally held for several ms The numerous application notes that accompany the EB675001DIP web resources should give some further ideas to a de signer 22 Simtec Electronics Appendix A Board Layout Figure A 1 EB675001DIP board layout top side 000000000000000 00 0 0 0 9 0 0 0 0 0 0 00 0 0 0 9 0 qudm mni oe m 23 24 Simtec Electronics Appendix B Mechanical drawing Figure B 1 EB675001DIP Mechanical Drawing aan D a E Da 4 1 i A03 88 loo 28 0039 ei a 38 0 075 23 2 00 85 o 28 88 9 x ojo 0000 Qu SA 000 OJO 99 gg za sslst de A ENS 4 dar se Roo ge E oo oo Scale 1 1 MES oo All measurements i
13. c ument Figure 2 8 Serial connector DCD RX TX DTR GND DSR RTS CTS RI 2 9 Power Supply The module may be powered either with a direct regulated 3 3V supply capable of providing 0 5A or by a linearly regu lated input with a range of 4 5V 15V Practical measurements taken from a gold specification module running uCLinux with active networking serial and basic user CPLD code loaded gives a baseline current draw of 0 39A at 3 3V 1 29W Measurements using the linearly regulated input give the expected results of a 0 39A current usage at any point of the ac ceptable input voltage range the excess power being dissipated as heat into the modules ground plane figures are subject to a 1 measurement accuracy and are for guidance purposes only Figure 2 9 Graph of EB675001DIP power usage 8 Simtec Electronics Expansion connectors 7 Regulated Power Usage Power Usage at 3 3V Power W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Voltage V 2 10 Expansion connectors The EB675001DIP has two rows of standard 0 linch Plated Through Hole PTH connectors sometimes referred to as a QDIP configuration Figure 2 10 Expansion connector placement Oe ii i d 0 09990080 6 K PL7 PL1 o o o ojo 00000 oo o o oja 11 N A Ad ci dq bd iei bau si d Ed lt lo lo o ocooooooooosooooooooooool
14. cessed using the ML675001 SDRAM controller and appears in bank 24 of its memory map Figure 2 4 SDRAM to ML675001 attachment A 0 12 A 1 13 BA O A 15 SDRAM A 14 OKI ML675001 K4S5616320 DI0 15 010 15 256Mbit WE E DQMH DQMIOI DQML DQM 1 ncs nSDCS nRAS nSRAS nCAS nSCAS CLK SCLKO CKE SCKE U25 U11 2 3 4 EEPROM There is provision for a single EEPROM connected via the PC bus specification boards have 8KBit 1 device fitted as standard but up to 256KBit can be accommodated The device is typically used to hold the non volatile settings in the ABLE bootloader 2 4 JTAG The ML675001 system CPLD and user CPLD are all connected to the JTAG chain The JTAG chain is available from this connector and allows reprogramming of the user CPLD and ICE debugging of the processor Figure 2 5 JTAG connector GND TDI 3 3V JSEL RST RCLK TMS TRST The JTAG chain on the EB675001DIP is connected to the ML675001 the system CPLD and the user CPLD Because of this care should be taken to ensure other devices are placed in bypass as required BSDL files are available from OKI for the ML675001 and Xilinx for the CPLD devices 6 Simtec Electronics DM9000 Network controller 2 5 Real Time Clock The Real Time Clock RTC is connected to the ML675001 on the PC bus The RTC is a Ricoh R2051 with a 32KHz crystal attached This device has
15. connectors a designer might be interested in the pinouts are detailed in Sec tion 2 10 Expansion connectors The two main sixty way expansion headers PL3 and PLA are on a standard 0 linch 2 54mm grid the Appendix B Mechanical drawing has details of the exact dimensions for all connectors These connectors carry the signals from the CPU and User CPLD these signals are fully buffered and are 5V tolerant The buffered RS232 serial signals are replicated on PLA pins A26 to B29 if the 9way D connector isn t used The SERIAL EN signal on B30 allows the serial buffer to be disabled which allows the unbuffered serial signals to be used on B16 to B25 The Ethernet header PL7 is again a standard 0 linch 2x5 header which is only available if the module is purchased without the Ethernet jack fitted A suitable RJ45 jack with integral magnetics and LEDs is the Bothhand L5041 which may be obtained along with the module if desired The Ethernet expansion connector allows the connector to be placed in a more convenient position within a larger design Figure 4 1 Schematic fragment using EB675001DIP Ethernet header cr ACT GND SPEED HAD TAD BAD AGND AVCC 17 Chapter 4 Design Guide The JTAG header PL6 gives access to the on board JTAG chain comprising the OKI CPU system CPLD and the user CPLD The layout is a 2x5 0 linch 2 54mm pitch header which can be connected to a standard multi ICE 2x10
16. deo framebuffer Enough signals are directly connected from the CPU to the CPLD to allow for eight or sixteen bit wide accesses in three chip select regions CSO must be treated with care because it is pre decoded by the system CPLD to attach the DM9000 Ethernet controller The system wait line is also taken through the user CPLD to allow the CPLD to force I O wait in CSO if necessary More details on the CPLD use and configuration can be found in the User CPLD guide ht tp www simtec co uk products EB675001DIP files cpld cpld guide html Figure 2 7 Xilinx XL9572XL to ML675001 attachment Simtec Electronics 7 Chapter 2 Hardware Description PIN 49 ALO PIN 50 52 53 A 21 23 CPLD PIN 18 11 010 7 OKI ML675001 XC9572XL PIN 33 35 37 39 42 018 15 PIN 29 nCS 0 PIN 10 ncs 2 PIN 9 ncs 3 PIN 25 XWAIT PIN 22 NXWE PIN 23 nXOE PIN 27 CLK_OUT PIN 32 nXBS 0 PIN 30 nXBS 1 U4 U11 2 8 Serial port The ML675001 has a single 16550 type serial port complete with FIFO This port is used as a console port by the boot loader and uCLinux The port is level translated to RS232 signals by a MAX3243 device The port is switchable from the buffered outputs to the unbuffered LVTTL levels by using the SERIAL EN line For more details on this ports usage refer to the EB675001DIP Connector and link pinouts http www simtec co uk products EB675001DIP files pinlist html do
17. eal Time Clock Table of Contents EB675001DIP Development Board a e e eee en he he mre xi O MES 1 LiL IEEE 1 1 1 4 MEE 1 1 1 2 EB675001DIP Development board sun 1 1 2 Development Tools Rer PR RE ERRARE PIS REP URS sat dal EPI UAE nies ER des 2 1 3 Using the development board 5 a x eot bett na oaie oaia ua ae o teste beans 2 1 4 Handling precautions A A SOR ea D OO FE ERE nai 2 2 Hardware Description eo re oe eater setae n tbi er tede rm Epp ese ss ee eoo Pe tuus 3 PAN ODE 3 22 0KT ME675001 rente hue an ea tes dae E RED ER al ae e Re gob AE R oe Ide d du deber da 4 223 x oes c doe Eee ee ee E t I eii 5 2 3 I NOR boot flash sii reiecit ri E ERR REPE RS ERR TER dr REP RR ERR ao dai 5 232 SRAM cuci a ao ia il 5 2 3 3 SDRAM Li edet t bete ati a DERE cata patet etre Pe REDEEM 6 2 34 EEPROM ww M 6 2A JTAG HS EE 6 2 5 Real Time Clock re p DEE ne hoes dois Sonar SER leds a 7 2 6 DM9000 N twork controll r cuie ai ere d e E ada eh id 7 21 MANX CRED ie NN 7 2 Seal port zise inca Tie ca a calare Dr A Nei NU iu SP M 8 2 9 POWet SUPPLY dei teste doi are RSR E pi e ae SR E A E dedu er aia t Es 8 2 10 Expansion Connectors aaa O roi a DR 9 3 Bootloadet ss starter anders setae eo ed ate suns reste ste
18. h and SRAM 32 KBytes built in zero wait state SRAM One fast interrupt source e 23 internal interrupt sources 4 external interrupt sources Independent masking and priority settings for all interrupt sources Two DMA channels with external access One 16 bit system timer Six 16 bit auto reload timers with independent clock settings One flexible 16 bit dual stage watchdog timer Two 16 bit PWM channels GPIO 42 bits Four 10 bit Analog channels A single synchronous serial controller with master or slave operation Master mode controller A 16550 compatible asynchronous communications controller UART with integral baud rate generator Simple serial controller with built in baud rate generator Flexible power management including standby and halt operation modes Built in boot ROM accommodates in circuit Flash ROM re programming and field updates Most of these features are directly available to the user of the EB675001DIP and where appropriate have suitable external devices connected for extended functionality The connection of the external devices are described in the remainder of this chapter For further details on the ML675001 please consult the ML675001 User manual ht tp www 2 okisemi com site productscatalog armsolutions mcumpu availabledocs Intro 9980 html 4 Simtec Electronics NOR boot flash 2 3 Memory 2 3 1 NOR boot flash The EB675001DIP has provision for a single
19. ice 1 4 Handling precautions This development board is intended for use either within a workshop laboratory environment or as an integrator solution within a larger product Because of this the EB675001DIP board is supplied without an enclosure The lack of an enclos ure means that standard electrostatic control procedures should be used when handling the board When using the EB675001DIP outside an enclosure the following is recommended Only hold the board by the edges Always use proper static handling equipment as a minimum an earth strap 2 Simtec Electronics Chapter 2 Hardware Description 2 1 Overview The EB675001DIP is a complete system that includes a large number of Input Output facilities The addition of the user programmable logic in the form of the 64 Macrocell Xilinx CPLD provides for an extremely large number of applica tions This logic may be used to create quite complex designs relatively easily using freely available Xilinx tools Simtec Electronics provide a number of application notes accessible via the EB675001DIP resources page or on the supplied CD ROM several of which demonstrate the use of the CPLD Figure 2 1 Detailed block diagram of the EB675001DIP Ethernet 10 100MBit 16MBit NOR Flash 4MBit SRAM 512MBit SDRAM System CPLD User CPLD XC9572XL CPLD 1 0 Ethernet c 2004 Sim
20. issues providing the leads are kept short The Texas Instruments MC33063 15 a simple eight pin device which can be configured for several modes of operation in addition to the step down configuration shown here The inductor L2 is a 220uH a suitable part might be a 822LY 221K this part would limit the output current It is of course possible to create this circuit using surface mount components MC33063AD and A814AY 221K would be the major parts although circuits and devices with superior performance may be selected in SMT designs Figure 4 6 Schematic fragment of DC DC converter EB675001DIP power supply eo gt ale cc O 1 de EAS Era DRVCOL cs g vb 5 a TIMECAP U 5 wer gt 2 INVIN O C6 MC33063AD ANS 470pF g GT GND There exist a large number of component and circuit choices for DC to DC converters and the user should select the appro priate one for their needs 4 4 User CPLD 20 The Xilinx XC9572XL user CPLD means the EB675001DIP often requires very little external logic to implement a large variety of tasks The EB675001DIP has the ability to program the user CPLD with an XSVF file from the ABLE command prompt The Xilinx tools can be used to generate an XSVF programming file of the user CPLD code The PlayXSVF utility is executed from the ABLE command line which reconfigures the on board JTAG chain and programs the user CPLD without the use of external J
21. n 76 Xilinx XC9572XL I O CPLD PIN71 C10 D10 CPLD_PIN72 Xilinx XC9572XL I O Pin 71 Pin 72 Xilinx XC9572XL I O CPLD_PIN68 C11 CPLD_PIN70 Xilinx XC9572XL I O Pin 68 Pin 70 Xilinx XC9572XL I O CPLD_PIN66 C12 D12 CPLD_PIN67 Xilinx XC9572XL I O Pin 66 Pin 67 Xilinx XC9572XL I O CPLD PIN64 C13 D13 CPLD_PIN65 Xilinx XC9572XL I O Pin 64 Pin 65 Xilinx XC9572XL I O CPLD PIN61 C14 D14 CPLD_PIN63 Xilinx XC9572XL I O Pin 61 Pin 63 Buffered CPU address SA 23 C15 D15 CPLD_PIN60 Xilinx XC9572XL I O line Pin 60 Buffered CPU address SA 22 C16 D16 CPLD_PINS9 Xilinx XC9572XL I O line Pin 59 Buffered CPU address SA 21 C17 D17 GND Signal ground line Buffered CPU address SA 20 C18 DI8 CPLD PINS8 Xilinx XC9572XL I O line Pin 58 Buffered CPU address SA 19 C19 D19 CPLD PIN56 Xilinx XC9572XL I O line Pin 56 Buffered CPU address SA 18 C20 D20 CPLD_PINS5 Xilinx XC9572XL I O line Pin 55 Buffered CPU address SA 17 C21 21 SA 8 Buffered CPU address line line Buffered CPU address SA 16 C22 D22 SA 7 Buffered CPU address line line Buffered CPU address SA 15 C23 D23 SA 6 Buffered CPU address line line Buffered CPU address SA 14 C24 D24 SA 5 Buffered CPU address line line Buffered CPU address SA 13 C25 D25 SA 4 Buffered CPU address line line Buffered CPU address SA 12 C26 D26 SA 3 Buffered CPU address line line Buffered CPU address SA 11 C27 D27 SA 2 Buffered CPU address line line Buffered CPU addre
22. n inches oS bracketed values converted to mm oo Id EB675001DIP mechanical svg 6573 2006 04 04 13 19 112 vince oo oo aro 12 30 48 8 0 8 0 470 11 93 1250 31 75 38 gk 33 3d gt 0 236 2 00 25 26 Simtec Electronics Colophon This Document was prepared in Docbook XML http www docbook org using the GNU emacs text editor The source was combined with DocBook XSL Stylesheets http docbook sourceforge net projects xsl using an XSLT processor to produce output in various formats For web output the Saxon XSLT processor http saxon sourceforge net was used to convert the docbook XML directly to HTML For print output the Saxon XSLT processor http saxon sourceforge net was used to convert the docbook XML to Formatting Objects FO XML For general print documents the FO XML is converted to PDF and Postscript with the Apache project FOP ht tp xmlgraphics apache org fop utility For six by nine inch book output the Render X XEP digital typography tool was used to convert the FO XML to print ready PDF output The URW Nimbus Sans font families were used to perform this typesetting The cover designs were developed in the GNU Image Manipulation Program http www gimp org GIMP 27 28 Simtec Elec
23. nd starts execu tion of an Operating System It does not execute user programs itself all the CLI commands are built in and does not provide services to an Operating System once started PC BIOS perform this role The modular nature of ABLE allows the use of the same building blocks for every supported platform The integration and omission of various modules allow for specific driver sets depending on the peripherals of a platform The flexibility of this approach allows for a common familiar environment across all supported platforms while still supporting a complete feature set This chapter only provides a brief introduction to ABLE Full documentation can be found in the ABLE user guide ht tp www simtec co uk products SW ABLE files able set book userguide html 3 2 Getting Started When a platform is initially powered or a hard reset performed the ABLE environment will be started and each compon ent module will be loaded in turn The last module loaded is the ABLE shell which will present the user with a command line interface ABLE has the ability to use a combination of input and output sources to interact with a user The default is to use all the input and output devices available For example on the EB2410ITX both the console serial port and the video display will be used to output and the serial port for input future versions may support USB keyboards for input Example 3 1 Video display after starting ABLE on EB2410ITX
24. onoool 16 swt These connectors provide all the I O signals to expand the use of the module For full details the EB675001DIP Connector and link pinouts http www simtec co uk products EB675001DIP files pinlist html document should be consulted this contains addition information and comments relevant to using this product Table 2 1 60 way PTH connector PL3 Description Name Pin Pin Name Description 3 3V output from on 3 3V Cl DI GND Signal Ground board regulator or ex ternal 3 3V regulated smoothed supply Supply Ground GND C2 D2 EXT_BAT Supply for the Real Time Clock Simtec Electronics 9 Chapter 2 Hardware Description 10 Description Name Pin Pin Name Description Xilinx XC9572XL I O CPLD PIN92 C3 D3 CPLD PIN91 Xilinx XC9572XL I O Pin 92 Pin 91 Xilinx XC9572XL I O CPLD_PIN89 C4 D4 CPLD_PIN90 Xilinx XC9572XL I O Pin 89 Pin 90 Xilinx XC9572XL I O CPLD_PIN86 C5 DS CPLD_PIN87 Xilinx XC9572XL I O Pin 86 Pin 87 Xilinx XC9572XL I O CPLD_PIN82 C6 D6 CPLD_PIN85 Xilinx XC9572XL I O Pin 82 Pin 85 Xilinx XC9572XL I O CPLD_PIN79 C7 D7 CPLD_PIN81 Xilinx XC9572XL I O Pin 79 Pin 81 Xilinx XC9572XL VO CPLD_PIN77 C8 D8 CPLD_PIN78 Xilinx XC9572XL I O Pin 77 Pin 78 Xilinx XC9572XL I O CPLD PIN74 C9 D9 CPLD_PIN76 Xilinx XC9572XL I O Pin 74 Pi
25. r CPU GPIO PI DMA Chanel 0 or CPU OE 7 GPIO PIOB 5 Second CPU interrupt IRQI 12 B12 DACKI DMA acknowledge line or CPU GPIO 6 clear for channel 1 or CPU GPIO PIOB 3 First CPU interrupt line IRQO A13 B13 DREQ1 DMA request for chan or CPU GPIO 5 nel 1 or CPU GPIO PI OB 2 I2C Serial Clock or SCL 14 14 DACKO DMA acknowledge CPU GPIO PIOE 4 clear for channel or CPU GPIO PIOB 1 I2C Serial Data or CPU SDA 15 15 DREQO DMA request for chan GPIO PIOE 3 nel 0 or CPU GPIO PI 0 Synchronous serial SDO 16 B16 SRXD Simple serial port SIO SSIO data output data receive not the UART port or CPU GPIO PIOB 7 Synchronous serial SDI A17 B17 STXD Simple serial port SIO SSIO data input data transmit or CPU GPIO PIOB 6 Synchronous serial SCK A18 B18 RI Unbuffered UART RI SSIO clock signal or CPU GPIO PIOA 7 Simtec Electronics 11 Chapter 2 Hardware Description 12 Description Name Pin Pin Name Description Signal ground GND 19 19 RTS Unbuffered UART RTS signal or CPU GPIO PIOA 6 Fourth analog input ANALOG 3 A20 B20 Unbuffered UART signal or CPU GPIO PIOA 5 Third analog input ANALOG 2 A2 B21 DCD Unbuffered UART DCD signal or CPU GPIO PIOA 4 Second analog input ANALOG 1 A22 B22 DSR Unbuffered UART DSR signal or CPU GPIO PIOA 3 First analog input ANALOG 0 A23 B23 CTS
26. rial console To access the serial console from LINUX the minicom program can be used Identify which serial port the EB675001DIP is connected to and ensure a note is made of the correct device node e g something like dev ttySO or dev ttyUS BO Figure 3 3 Minicom settings window Welcome to minicom 2 1 r Comm Parameters 4 OPTIONS History Buf Compiled on Mar 29 2 Current 115200 8N1 Press CTRL A Z for Speed Parity Data A 300 L None S 5 B 1200 M Even T 6 C 2400 N Odd uU 7 D 4800 0 Mark v 8 E 9600 P Space F 19200 Stopbits G 38400 W 1 H 57600 2 I 115200 Q 8 N 1 J 230400 R 7 E 1 Choice or lt Enter gt to exit CTRL A Z for help 115200 8N1 Minicom 2 1 Offline Simtec Electronics 15 Chapter 3 Bootloader Start minicom and ensure the correct settings are selected Default is Ctrl A p These settings are 115200 baud 8 data bits no parity and 1 stop bit as shown in Figure 3 3 Minicom settings window Obviously Minicom should be using the correct serial port as noted earlier 16 Simtec Electronics Chapter 4 Design Guide 4 1 Overview The EB675001DIP is designed to be used as component within a larger system This chapter describes some of the design considerations which might be useful when embedding the module 4 2 Connections The EB675001DIP has four expansion
27. rview This chapter describes The kit contents Development tools Use of the development board Handling precautions 1 1 Kit contents The EB675001DIP is a comprehensive ARM computing platform The Kit contains The EB675001DIP user guide A CD ROM containing development software and documents relevant to the EB675001DIP The EB675001DIP board 1 1 1 CD ROM The CD ROM contains A copy of all the freely available documentation including this user guide Datasheets for all major components used uCLinux distribution x86 cross building toolchain for GNU Linux ABLE bootloader The toolchain contains a GCC compiler assembler and linker suitable for cross compiling ARM binaries from an x86 ma chine running GNU Linux 1 1 2 EB675001DIP Development board The EB675001DIP board gold specification has the following major components OKIML675001 MCU 32MB SDRAM 16MBit NOR Flash 8Kbit LC EEPROM Xilinx XL9572XL CPLD 10 100MBit Ethernet controller 9pin D sub RS232 port Chapter 1 Overview header 30 5V tolerant GPIO or special function lines e 401O lines from Xilinx XL9572XL CPLD Wide input voltage regulator 1 2 Development Tools The development tools provided must be installed and run on a PC with a GNU Linux Operating system e g Debian Ubuntu or Redhat distributions The GCC toolchain provided creates executables that can be run on the EB675001DIP This
28. s gy Party None y Stop bis y Flow control Restore Defaults ETE Start HyperTerminal and create a new connection When prompted for which modem to use instead choose the appropri Simtec Electronics Using minicom as a serial console ate COM port as noted earlier Then the appropriate settings for your platform please refer to platform specific document ation typically these settings are 115200 bits per second 8 data bits no parity 1 stop bit and no flow control as shown in Figure 3 1 Hyperterm settings window Figure 3 2 Hyperterm displaying ABLE output Hype Terminy oki_eb67dip_bus_init done oki ml67x init scanning for ML67X device oki ml67x scan bus 8 fc7el deu 80fc7de4 i installed routines single byte addressed crc does not match 74 vs ff oki ml67x timer registering timers oki ml67x timer add with ira 1 oki ml67x timek set tmr 800f16d98 scaler 1 period x8fff selected all wr for console write stream 009000 def r1 00 02 04 06 08 0a int phy link down failed to find cpu device dcum unset defaulting to rom1 root dev mtdblock3 ro console ttyS88 1920 Rutoboot in 12 seconds attempt 1 Press any key to abort gt IConnected 009 31 VIE 115200 69 1 Once the connection is established the output from ABLE should be seen in the hyperterm window as in Figure 3 2 Hyperterm displaying ABLE output 3 2 2 Using minicom as a se
29. ss SA 10 C28 D28 SA 1 Buffered CPU address line line Buffered CPU address SA 9 C29 D29 CPLD_PIN54 Xilinx XC9572XL I O line Pin 54 Simtec Electronics Expansion connectors Description Name Pin Pin Name Description Signal Ground GND C30 D30 GND Signal Ground Key pin Table 2 2 60 way PTH connector PL4 Description Name Pin Pin Name Description 4 5 15V DC power VIN Al Bl GND Power ground supply Power ground GND A2 B2 3 3V 3 3V output from on board regulator or ex ternal 3 3V regulated smoothed supply Xilinx XC9572XL I O CPLD PIN94 A3 B3 CPLD PIN93 Xilinx XC9572XL I O Pin 94 Pin 93 Xilinx XC9572XL I O CPLD PIN96 A4 B4 CPLD_PIN95 Xilinx XC9572XL I O Pin 96 Pin 95 Xilinx XC9572XL I O CPLD PINOI A5 B5 CPLD_PIN97 Xilinx XC9572XL I O Pin 1 Pin 97 Xilinx XC9572XL I O CPLD_PINO4 B6 CPLD PINO3 Xilinx XC9572XL I O Pin 4 Pin 3 Xilinx XC9572XL I O CPLD PINOS A7 B7 CPLD PINO6 Xilinx XC9572XL I O Pin 8 Pin 6 Inverted module reset RST A8 B8 PWMI Second Pulse Width output Modulator output or CPU GPIO PIOC 1 Inverted CPU fast in A9 B9 PWMO First Pulse Width Modu terrupt line lator output or CPU GPIO 0 Fourth CPU interrupt IRQ3 10 B10 TCI Terminal count for line or CPU GPIO 8 DMA Chanel 1 or CPU GPIO PIOB 4 Third CPU interrupt IRQ2 All BIl TCO Terminal count for line o
30. tec Electronics http www simtec co uk Id detailed block svg 6568 2006 03 27 09 44 03Z vince bevice size and availability dependant on configuration DIP Switches OKI ML675001 u Mem Control Data Address FC RS232 Analo RTC 16KBit DIP headers JTAG RS232 Chapter 2 Hardware Description 2 2 OKI ML675001 MCU The ML675001 is a 144 pin plastic LFBGA System on Chip from OKI Semiconductor The large number of peripherals within the device give flexibility to the user and the ability to use numerous I O solutions without additional controllers The ML675001 does not have a traditional MMU and lacks the ability to operate with virtual memory because of this only Operating systems which do not require an MMU such as uCLinux are suitable for use with this processor To improve performance the ML675001 has a cache controller which allows for greatly improved performance over devices without such capabilities The ML675001DIP has a number of flexible peripherals and interfaces these are summarised as follows ARM7TDMI 32 bit RISC CPU 32 bit mode ARM and or 16 bit mode Thumb Built in SDRAM external memory controller supports glueless connectivity to memory External memory controller supporting external NOR flas
31. the capacity to hold the date and time and keep time using a minimum of power typically 0 4uA with 3V supply There is also the ability to set alarms which may generate interrupts this may be used to perform repeating tasks with long intervals without consuming large amounts of power The R2051 interrupt is connected to the ML675001 IRQO This IRQ is shared with the Davicom ethernet controller and is also present on A13 of the PLA connector 2 6 DM9000 Network controller The DM9000 network controller provides 100Mbit Ethernet connectivity to the system It is decoded into the CSO address space by the system CPLD as it uses the WAIT line to extend I O cycles as necessary The DM9000 may interrupt the ML675001 The IRQ is connected to the ML675001 IRQO signal The interrupt is shared with the Real Time Clock and is also presented on pin A13 of the PL4 connector Figure 2 6 DM9000 to ML675001 attachment nADR DAT A 18 0 15 D O 15 Ethernet Controller IRQ IRQIO OKI ML675001 0509000 IOCHRDY WAIT nRESET nRST now nWE System 5 0 CPLD 2 7 Xilinx CPLD The EB675001DIP has a powerful addition to a development system in the form of a user programmable CPLD This device can be programed to perform a large number of logic functions The application notes contain several examples of its flexibility in everything from a simple address decoder to a TV resol ution vi
32. toolchain is also required to build uCLinux Full details of building uCLinux are provided in notes ht tp www simtec co uk products EB675001DIP files uclinux 20041215 notes html on the EB675001DIP resources page In order to run the development tools the host PC requires e 500MHz or faster processor Installed GNU Linux distribution 128MB RAM e IGB of hard disk space 3GB if building uCLinux CD ROM Drive In addition to the development tools the module usually requires serial communications to access its bootloader and booted system Most modern PC have serial ports however increasingly only USB ports are provided most typical USB gt Serial converters appear to work with the EB675001DIP 1 3 Using the development board The EB675001DIP is a complete system With the addition of a suitable power supply and PC the Kit provides everything required to start producing the desired solution There are generally two modes of operation The first most basic method of using the EB675001DIP and indeed only method on boards other than the gold specific ation is to use the in built OKI downloader utility to transfer programs to be executed using raw hex records The second method uses a full ABLE bootloader install and allows much more flexible use of the EB675001DIP ABLE can start uCLinux images from a variety of sources including the network In this mode of usage the serial port is used as a console to communicate with the dev
33. tronics
34. x480 Hz Hz HSync video video size 300K configuring ch7006 vga selected all wr for console write stream selected all rd for console read stream DRAM 128 Mb 134217728 bytes BASIS PMU version 1 02 ID 00501 s See 00 g 01 ABLE 2 08 s3c2410x vince gerald Fri Apr 8 16 35 26 BST 2005 hdc TOSHIBA MK1003MAV ATA PIO mode 4 hdc Diagnosing disc drive ok hdc 1GB hd0 on hdc1 ext2 hd1 on hdc2 DMOO cm0 zi OWsOlssesOOsOlLsGa ame pay link OK dimos iwi NE2000 ne0 ISA Generic 00 01 3d 00 01 6b EEPROM Invalid Missing e 12C error sys autoshadow unset automatically shadowing gt The input devices are controlled by using the cons read parameter and similarly the cons write parameter controls which output devices are used Typically the console serial port is used to interact with the ABLE CLI Unless the boot parameters are altered from their default settings the autoboot process will commence To manually start an Operating System the command line must be used 3 2 1 Using hyperterm as a serial console 14 To access the serial console from windows the hyperterm program can be used Identify which serial port the platform is connected to and ensure a note is made of the correct COM port e g COMI or COM2 Figure 3 1 Hyperterm settings window Port Settings Bits per second 115200 y Data bit
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