EDOC 237 Clover Card User Guide v1
Contents
1. 4 ADC chip To FIFO Includes Sliding Scale Peak time TAC FT TAC Readout Validation x5 for 5 Ge channels Ge CFD outputs 5 BGO Veto and other control logic Test pulser BGO Veto in 4 dual line receivers Nac 8 inputs lt lt with LE from charge discriminators reamps for each Shaping shield pair Amplifier of BGO p 8 2us elements Suns the 81 88 8 inputs Logical OR of all LE discriminators Inspection Points Local Trigger To VXI Multiplicity Current source Fast Trigger Hold Veto pattern Pattern Unit and deadtime generator Includes parallel to serial conversion ROCI Channel Readout Chip 4 ADC chip T FIFO Includes Sliding Scale Readout Validation Fig 1 Block diagram of Eurogam Phase 2 Detector Card 2 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England Ge Signal Processing Input 200mV MeV 10 pre amp signal with 500 pre amp output impedance 50us fall time constant 5 1K input impedance approx Signal Shaping Unipolar output from 6th order quasi triangular filter Peaking time of 4 4us and FWHM 5 us Pulse width at 0 1 is I lus Output amplifier stage generates 4MeV and 20MeV ranges Bipolar differentiated outputs available for crossover timing Timing CFD min threshold 20keV pulse pair resolution better than lus timing walk 3ns for 200 1 dynamic ra2. Mark mode AND either there is pre pulse pileup in one of the 5 Ge channels OR there is a Veto from the Sumbus Veto LookUp Table The duration of the card level inhibit 1s set by 1 the duration of the system s Inhibit Action signal until end of readout in CDT mode 2 the duration of the pre pulse pileup 7us or the Veto until LT reset If both conditions are true then the duration is set by the longer The front edge of the card level inhibit is also used to enable the serialisation of the status of the input pattern by the pattern unit M30 This level must be maintained until parallel to serial conversion is finished The inhibit to each of the LT circuits has an inhibit over ride using that LT s LtStartN signal which prevents the application of an inhibit once the LT is busy If Inhibit is applied to a busy LT and the LT s CFD fires again then that LT will be reset prematurely The sumbus drivers are controlled by a PAL which gates the LUT output with a delayed version of the OR of the Ge CFD outputs Whenever the CFD s fire the current pattern of local trigger LtStart signals and BGO line receivers which is applied to the LUT will determine whether or not the sumbuses are driven In the case of the Ge LT s this will be stale latched information if there is a card level inhibit preventing changes in LT state In parallel mode the InhAction signal will be short but the card level inhibit will be extended to 7us by the pre pul
3. menu are shown in fig 5 and fig 6 respectively These 2 menus are very much the same as used for the phase 1 Ge and BGO cards Note that for each Ge channel the PZ adjustment must be made for the specific detector pre amp attached and should be checked before an experiment Similarly the FT sample and Val sample points trigger timing should be checked before each experiment The sample points should be placed in the middle of the FT and Validation pulses respectively The Ge channels have a common FT sample control but the BGO channel has its own independent control to cope with the different characteristics of the two types of detector The user controls which of the parameters are read out using the RO ticks at the top of each screen fig 5 and fig 6 The sliding scale SS item should always be ticked except for the pattern for which the SS must never be enabled The pattern includes not only the BGO but also the Ge hit pattern To help in setting up and checking the cards some typical shapes of the signals on the inspection lines are shown in fig 7 to 10 8 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England p Y VXI Base Frame ET Missile Cats d SEEN 2 m VXI Module Setup Spectrum Viewer l mE VXI Module Setup Histogrammer xj Clover Card Setup Channel _ D Acton all Channels Mal sno EN EN ERN ESI Suppression Mode E Simple Spare Channel Unused Tape C
4. 1 000 eas ie BGO input e Je Y T pl Fig 2 Front Panel for Clover Card EX R H 5 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England Operating Modes for the Clover Detector The anti Compton veto system and sumbuses become more complex with a Clover detector than a conventional tapered detector in deciding what combination of detector hits comprises a clean hit whether only 1 Ge may be hit i e the Ge s veto each other or whether a combination of Ge hits is allowed and which parts of the BGO shield veto which Ge detectors All possible combinations of Ge BGO hit pattern are programmable in an 8kx4 memory using the 13 bit hit pattern as an address with the 4 data bits determining which if any of the sumbuses Raw Ge Clean Ge BGO are to be turned on and whether or not to reject the event in hardware or to mark it depending on whether the card is in mark or reject mode Three of the most useful modes of operation are available from the MIDAS software in the top level of the Clover card control menu These modes are as follows Typical Modes of operation these are all available from MIDAS software 1 Simple In this case all 5 Ge inputs 4 real inputs 1 spare are treated as a single detector with a single BGO shield When 1 or more Ge element fires a multiplicity of 1 is indicated on the Raw Ge sumbus regardless of what happens in the BGO The Clean Ge sumbus
5. Addresses for Software Developers Address Space offset into VXI address space Name 0x0000 to 0x00fe Ge Common parameters Channel 0 0x0100 to Ox0 fe Channel 1 Parameters Ge A x0200 to 0x02fe Channel 2 Parameters Ge B x0300 to 0x03fe Channel 3 Parameters Ge C 0x0400 to 0x04fe Channel 4 Parameters Ge D 0x0500 to 0x05fe Channel 5 Parameters Ge Spare 0x0600 to 0x06fe Channel 6 Parameters BGO 0x0700 to 0x07fe BGO Common parameters Channel 7 0x2000 to Ox3ffe Veto Pattern logic Table Channel 0 Sub Address Spaces 0x0000 to 0x002e Ge Common Parameters 0x0030 to 0x00fe Module Parameters common to Ge amp BGO Ge Common Parameters Name Offset Access Old Ge offset CFD Width DAC 8 bits 0x0000 0x0000 FT Sample Point DAC 8 bits 0x0002 0x0002 Validation Sample Point DAC 8 bits 0x0004 0x0004 LT watchdog DAC 8 bits 0x0006 0x0006 Test Generator Amplitude DAC 16 bits 0x0010 0x0010 Module Parameters Common to Ge and BGO parts Module Control Register 0x0038 dis 8 x d7 d6 o jw d3 jd 0x38 Test Att CDF on notused notused 1 Reset not used 0 Rej LastCard on 1 FIFO 1 mark 1 16 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England Channels 1 6 The addresses within the spaces allocated to channels 2 to 5 Ge A to Ge E are the same as on the phase 1 Ge Card The addresses within channel 6 BGO are the same as those within channe
6. EDOC237 EUROGAM Clover Card User Guide Version 1 0 July 1994 updated August 1999 Author Ian Lazarus Introduction The EUROGAM EUROBALL Clover card fully instruments a EUROGAM Clover Ge detector and its associated BGO suppression shield The inputs come from the Ge and BGO pre amps and after analogue signal processing the output from the card is a series of energy and timing data words plus a hit pattern The analogue signal processing is the same as used in the EUROGAM phase 1 Ge and BGO cards full details are given later except that there is no ballistic deficit correction in the Ge channels This is not necessary since the crystals in the Ge detectors are smaller than those used in EUROGAM phase 1 and so ballistic deficit does not have such a significant effect on their resolution For each Ge channel there is a high and a low gain 4MeV and 20MeV energy measurement and 2 timing measurements the peaking time and the difference in time between this channel and a global timing reference derived from the trigger system The BGO channel provides a single energy measurement typically 8MeV range and a single timing measurement the difference in time between this channel and a global timing reference derived from the trigger system There is also a hit pattern to show which Ge detectors and which BGO elements are involved in the event There are 4 Ge electronics channels plus an additional spare channel which can be cabled in and then rec
7. FT sample points it is not unreasonable to keep the two sets of inspection lines entirely as they are now This has the advantage also that all the phase 1 inspection line software can be re used The BGO elements s1 s8 map onto the old a h inspection lines analogue and digital the old i and j inspection lines are not used on phase 2 The address mapping is not exactly as phase 1 and is shown in detail later along with the Voltage Inspection lines Veto Pattern Look up Table The pattern for Veto generation is loaded into a 8Kx4 memory array whose inputs are the pattern from the 8 BGO and 5 Ge discriminators and outputs are signals to determine the following Veto the event Drive Raw Ge sumbus Drive Clean Ge sumbus Drive BGO sumbus This table is controlled by word access at addresses from offsets 0x4000 0x7ffe each address corresponding to one possible pattern of discriminators The pattern will be not not not De Ge Ge Ge Ge s8 s7 s6 s5 s4 s3 s2 sl used used used Sp D C B A pup qr E EE tese The data at each location 1s not used not used not used not used 1 BGO 1 Cl Ge 1 Raw Ge l Veto sumbus on sumbus on sumbus on Gees a7 d o jd 14 et 18 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England Multiplexors and Voltage Inspection Lines di4 di3 di2 dil aio do9 dos o d06 dos do4 do3 d02 dol doo Multiplex analogue and digital l
8. dures Jumpers These adjustments should not be attempted by a user Please contact an engineer ST 1 2 3 4 5 must always be inserted to ground the positive input to the shaping amplifiers SIS controls whether the sliding scale is on or off Shipped in the on position Top On Bottom Off ST20 controls whether the BGO channel is started by just the OR of the 5 Ge CFDs or the OR of the BGO inputs OR ed with the 5 Ge CFDs Shipped in the BGO or Ge position Top Ge only Bottom Ge OR BGO Adjustments There are no user adjustments on the card itself The ADC sliding scale is set during commissioning and should not be changed On the ADC there are 2 pots 47k sets DC level and 1k sets gain for SS adjustment The sumbus current output levels are set during commissioning and should not be changed R244 sets BGO sumbus R274 sets Clean Ge sumbus R300 sets Raw Ge sumbus Power supplies ge pp eneren amp _ Typical current amps ope Per imis Power Watts Total 89 Watts End of document 24 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England
9. er card readout is as follows Qi jQo 5 m 8 D nm 67 166 GS G4 63 G2 Io GO Qualifiers Item Group See below Identifies parameter within clover MIDAS sets this within range allocated to clovers The top 16 data bits always look like this and are followed by 16 bits of data as follows Pattern word not not not Ge Ge D Ge C Ge B Ge A s8 s7 s6 s5 s4 s3 s2 sl used used used E DI5 DI4 DI3 DI2 D11 DIO D09 Dos D07 D06 DOS D04 D03 D02 Dor DOO Energy Data Words all types fd ied ae ws LR RR RUNE DI5 DI4 DI3 DI2 To DIO D09 D08 D07 D06 DoS D04 D03 D02 Dor TAC Data Words all types not not not T T T T T T T T T T T T T used used used MSB LSB DI5 DI4 DI3 DI2 D11 DIO D09 Dos D07 D06 DOS D04 D03 D02 Dor DOO Qualifiers The Ge qualifiers have the following meanings depending on which data word they come with Q1 Q0 20MeV FT TAC CO TAC 00 q0 glean dan den data al data nopilup post pulse pileup pre or post pre or post Veto Veto i dd The BGO qualifiers are always set to 1 1 for compatibility with the EG 1 BGO cards 23 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England Warning Users must not remove the shields from the cards There are no user serviceable parts inside There are however static sensitive components which can be easily damaged by incorrect handling proce
10. imilar in shape to the unipolar signals but includes voltage limiting to avoid saturating oscilloscopes Fig 7 Ge Analogue inspection line signals 12 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England CFD delayed Pileup MEE PDSgae JP e CFD direct FT sample FT exists Oo FT sample no FT Val sam ple Val exists Valsample no val LT reset reset if no FT m if end no val r o cmas if FT pulse Val Pulse fe End of Conversion ROCI data ack ROCI data available 4MHz Last Pass Or of ADC deadtimes Fig 8 Ge Logic inspection signals 13 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England TAC Shaping amplifier PDS a Test ER OOO O RR Line receiver output a h fig 9 BGO Analogue Inspection Lines 14 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England BGO disable high for normal operation BGO valak T BGO Encode LP Validation Pulse Inhibit AR LT reset assuming FT and Val sample don t cause resets Start me LE FT pulse PDS gate FT au cu Val sam ple Do Discdeadtime LT start BGO Disc a h Width of pulse depends on time taken by input to drop below threshold fig 10 BGO logic inspection lines 15 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England Details of registers and
11. indicates a multiplicity of 1 if no element in the BGO shield has fired If 1 or more BGO element does fire then a multiplicity of 1 is indicated on the BGO sumbus and the Clean Ge sumbus current driver is inhibited 2 Exactly One Ge In this case exactly 1 of the 4 Ge inputs must fire with the other 3 Ge inputs being used along with the whole BGO shield as anti Compton vetos The Raw Ge sumbus sees a multiplicity of 1 when 1 or more Ge elements fires even though the 2nd Ge is part of the veto but the Clean Ge sumbus indicates a multiplicity of 1 only if exactly 1 Ge has fired and no BGO element has fired If 1 or more BGO element fires then a multiplicity of 1 is indicated on the BGO sumbus and the Clean Ge sumbus current driver is inhibited 3 Ignore Opposite Corner This mode is similar to the Exactly One Ge mode except that intelligence is applied to the processing of the BGO shield The 4 BGO elements in the opposite corner are ignored for example Ge A is clean if there are no hits in any of the BGO pairs s1 s2 s3 s4 s7 s8 or Ge B D i e BGO elements i j k and I in s5 and s6 are ignored The Raw Ge sumbus sees a multiplicity of 1 when 1 or more Ge elements fires but the Clean Ge sumbus indicates a multiplicity of 1 only if exactly 1 Ge has fired and there have been no BGO hits in the 12 relevant elements in the shield If one or more BGO element from the whole 16 element shield fires then a multiplicity of 1 is i
12. ine 2 Multiplex analogue and digital line 1 OZ Adjust A MeV Unipolar y O 220 MeV Unipolar 0 y O 4 MeV Dier HR TACempumWall no rnsouputlmall aana output maT 4 ere 5 frenoui active LY G 0 frifodwek aetie sO Input Ha fp A 19 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England OD Delayed Output 4 OT reset 0 OBO Disable mid Be DE 8 E TAC Stat Pulse mid fast Trigger Pulse SSS C a DoS ValdwonPuse a5 LL ROCDamaAdmowedge 4 foral6ROG Data Available Active Low REES T E DEE 20 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England Voltage Inspection Lines d7 do dS 144 d ja di Pt V Select 4 V Select 3 V Select 2 V Select I Mux Sel 3 Mux Sel 2 Mux Sel 1 Voltage Inspection Lines Bottom 3 lines select the Mux chip and next 4 lines address it Voltage Inspection Code Data 7 0 x1001 001 73 Ge 3 CFD Output Delay VO2 2 21 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England Inhibit and Sumbus System description added April 1996 The Inhibit system logic applies a card level inhibit signal name inhibecom whenever one of these 2 conditions is true using a logic OR IC 17 27 and 28 on page 11 of circuits 1 The system s Inhibit Action VXI line is true 0v on backplane 2 The card is set to Reject not
13. l 6 of the phase 1 BGO card This permits the software to treat these channels exactly as at present which means that the EUROGAM Register Server software and the EG Session Ge and BGO windows can be used with few changes Ge channel Parameters Channels 1 5 Old Ge offset CED Threshold 8 bits 0x0100 etc 0x0000 CFD Delay 8 bits 0x0102 etc 0x0002 PZ adjust DAC 8 bits 0x0104 etc 0x0004 PDS gate width DAC 8 bits 0x0106 etc 0x0006 Channel Control Register 0x0120 etc Ge Channel control register D MG E NE ox 120 etc not used not used CFD 1 Test not used TFA gain not used not eo G Mode 1 low BGO channel Parameters Channel 6 Old BGO offset BGO Threshold 12 bits 0x0600 0x0000 BGO Test Pulser 12 bits 0x0602 0x0002 Channel Control Register 0x0620 r w 0x0020 Ben Channel I register 0x620 s fae Jebs foo a fa eee BGO Common Parameters Channel 7 Old BGO offset Discriminator DeadTime DAC 8 bits 0x0702 0x0002 FT Sample point DAC 8 bits 0x0706 0x0006 Validation Sample Point DAC 8 bits 0x0708 0x0008 LT Watchdog 8 bits 0x070a 0x000a PDS Gate Width DAC 8 bits 0x070c 0x000c 17 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England Inspection Lines The Ge and BGO inspection lines are combined as follows Channels 6 and 7 overlap on certain signals such as Fast Triggers and Validations but since the Ge and BGO use different
14. m is the VXI backplane as for phase 1 The inputs from the Ge pre amps are connected to the front panel by BNC sockets The BGO input is a 20 way IDC using similar LEMO IDC cards to phase 1 but smaller to prevent mis connection of phase 1 shields to phase 2 electronics and vice versa LEDs are provided to indicate that BGO discriminators and Ge CFDs are firing as used in phase 1 A further LED is used to record FIFO errors indicating readout problems Front panel rate monitoring is provided via a 34 way IDC connector 13 differential ECL signal pairs are available from 5 CFDs and 8 BGO line receivers Backplane sumbuses and all other VXI connections are retained for full compatibility with phase 1 When the clover card is adjacent to phase 1 cards the BGO local bus veto signals will be ignored and the Ge local bus Veto inputs will not be driven There are no external Veto inputs or outputs or external amplifier inputs Pinouts for connectors are given in fig 2 on the next page 4 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England FIFO error Readout problems Ge A LED for CFD on Ge A Ge B Ge C Ge D Ge E Pins 1 2 are ground Pins 3 5 7 9 11 are ve Ge A E Pins 4 6 8 10 12 are ve Ge A E Pins 14 16 18 20 22 24 26 28 are ve BGO A H Pins 13 15 17 19 21 23 25 27 are ve BGO A H Pins 29 34 areunused Pin 34 Detail of BGO Pinout Rate monitoring outputs XX Gai Pin
15. ndicated on the BGO sumbus Clean Gez 1 BGO z 1 Simple Ti X z1Ge amp notAC gt 1BGO 16 BGO 0 Ge Exactly 1 Ge 1Ge amp notAC gt 1 BGO 16 BGO 3 Ge Ignore Opp Corner Ge amp not AC gt 1BGO 12 BGO 3 Ge 6 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England Fig 3 Naming scheme for Clover Ge and BGO elements showing the mapping from 16 BGO elements to 8 BGO signals for the phase 2 electronics Drawn I L Nov 1992 y Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England MIDAS Software Interface For Clover Card The following pages show typical screens from MIDAS software used in Euroball to control the Clover Card Fig 4 shows the Base Frame and indicates that you should select the Card Setup menu where you will find an entry for the Clover Card The result of selecting this is shown in the same diagram The enable buttons toggle the on off function for each channel also available from within the Ge and BGO sub menus This is the point at which the Suppression mode is selected see page 6 and in the event of a malfunction in one of the Ge channels the spare channel configured The Clover Card s Engineering menu and Readout button are for use by engineers only and contain no user controllable functions The more detailed Ge and BGO menus accessed from the Clover Card Setup menu or directly from the Base Frame s VXI Module Setup
16. nge 25ns for 1000 1 200ns Tr Figures from phase 1 Ge with 50ns delay need to re measure using new 27ns CFD TFA with 50ns integration and 180ns differentiation Gain x3 or x10 TAC 0 2us FWHM 0 6ns INL 596 Outputs for coding 4 MeV Unipolar signal 20 MeV Unipolar signal TAC measuring peaking time CFD firing to bipolar crossover TAC measuring channel firing time before reference pulse CFD to FT ADC 13 bits resolution 8192 channels Sliding scale Conversion time A us DNL lt 1 INL lt 250ppm 3 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England BGO Signal Processing Input 1000mV MeV pre amp signal with approx 5Q pre amp output impedance Phototube voltage must be adjusted to give 1000mV MeV level 30ns rise time constant 10 10us fall time constant 1 5 50Q input impedance Signal Shaping Bipolar output from 4th order semi gaussian filter CR RC4 RC 2us Peaking time of 5 2us and FWHM 5 5 us Pulse width at 0 1 is 12 x t 24us Output 8 MeV full scale Amplifier resolution is 3keV fwhm Outputs for coding 8 MeV Energy signal TAC measuring channel firing time before reference pulse disc to FT Also a serial bit stream indicating the hit pattern from BGO and Ge ADC 13 bits resolution 8192 channels Sliding scale Conversion time A us DNL lt 1 INL lt 250ppm Clover Detector Card Interconnections Primary interconnection mechanis
17. onfigured from software to take the place of any of the other 4 channels should a problem arise during an experiment The BGO channel accepts signals from the 16 element shield in 8 pairs each pair of phototubes driving its own pre amplifier Acknowledgements The Clover card is a collaborative project and the following people have been involved Engineer responsible for overall design lan Lazarus Daresbury Lab VXI interface and Readout design Patrick Coleman Smith Daresbury Lab CAD work including PCB design Jim Thornhill Liverpool University Assembly work Manchester University Dept of Physics Electronics Workshop Ge BGO signal processing components Alphonse Richard Zdravko Zojceski M Engrand IPN Orsay Germain Bosson ISN Grenoble Nabil Karkour CSNSM Orsay Michel Goyot IPN Lyon Charles Ring CRN Strasbourg MIDAS and other software Vic Pucknell Simon Letts Peter Owens Daresbury Laboratory For further help and information please contact Ian Lazarus at Daresbury Laboratory email Lazarus dl ac uk fax 0 1925 603173 telephone 0 1925 603433 l Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England Test pulser Tp Ge Pre amp signal Shaping amplifier Quasi triangular 20MeV Uni 20 MeV Bip CFD Inspection Points Local Trigger To VXI Multiplicity Current Fast Trigger sources BGO Veto BGO Veto out ROCI Channel Readout Chip
18. ontrol Diagnostics Exception Monitor Options E Hard Copy Experiment Control Help Ge Channel BGO Chanel Engineering RdOu Quit Redisplay Go From the base frame select the VXI module Setup menu and the Clover Card item Fig 4 MIDAS Base Frame and Clover card menu selection 9 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England L TUD Current Segment _ A SS Address ov Mp ess Mev ME ess Fast Trigger E D gum 0 ii sss Cross Over WO i 0 M 1e CFD Width ns o 0 of 20 CFD Delay ns 00 of 1200 Fast Trigger Sample ns K fT 2000 Validation Sample ns 0 of 1 16000 LT Watchdog Timeout ns o ol 125000 PDS Gate ns o I 10000 CFD Threshold keV 0 iT 2600 Pole Zero 0 D J 255 Fig 5 Clover Card Ge channel control window 10 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England Version 1 0 RO Energy m BE I p JN esse no Mp og ess pen Mp os Dead Time Width ns jo of 20000 Fast Trigger Sample ns n I G 2000 E Cem of 10000 LT Watchdog Timeout ns jo MM 16000 Disc ThesholdkeV jo0 ff 1 90 Fig 6 Clover Card BGO channel control window 11 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England PDS eg TFA in TFA out 4 Mev Bipolar FT TAC Unipolar 4 MeV 20MeV PZ adjust output looks very s
19. se pileup amplifier busy signals if the reject mode is enabled Check how long it takes to serialise the LtStart pattern maybe we need to stretch the InhAction locally to make a proper card deadtime signal Sumbus deadtime Added August 1999 The sumbus inhibit problem described above has a second effect which is to disable the sumbus Ge outputs while Inhibit Action is asserted regardless of whether this clover is part of the event The problem can be overcome for the Raw Ge sumbus only in the LUT by programming the all the RawGe entries to be always 1 so that the Raw Ge sumbus is driven whenever the OR of the Ge CFDs is true regardless of the Ge pattern bits from the LT Start signals This method can be extended to a simple suppression on the Clean Ge sumbus too by programming the LUT with a don t care state in all the 5 Ge bits and using the OR of the Ge CFDs to indicate that one or more of the Ge channels has been hit The Clean sumbus output from the LUT would be driven then whenever all 8 BGO bits are 0 and the OR of the Ge CFDs is true regardless of the state of the 5 Ge LT start LUT inputs NB this LUT configuration is incompatible with the complex Ge pattern based Vetos but these are rarely never used anyway so it is not really a problem that they are unavailable 22 Version 1 0 CCLRC Daresbury Laboratory Warrington Cheshire WA4 4AD England Data Format Description Added August 1999 The data format produced from the Clov
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