Altera Temperature Sensor IP Core User Guide
Contents
1. FF 127 E4 100 D5 85 DO 80 B2 50 9E 30 8A 10 80 0 76 10 Altera Temperature Sensor IP Core User Guide G Send Feedback Altera Corporation UG 01074 10 Altera Temperature Sensor Prototypes and Component Declarations 2015 05 04 6C 20 62 30 4E 50 3A 70 C Altera Temperature Sensor Prototypes and Component Declarations Verilog HDL Prototype The Verilog HDL prototype is located in the lt Quartus II installation directory gt eda synthesis altera_mf v VHDL Component Declaration The VHDL component declaration is located in the lt Quartus II installation directory gt libraries vhdl altera_mf directoryaltera_mf_components vhd Document Revision History This table lists the changes made to the document Table 7 Document Revision History Document Changes Made Version May 2015 2015 05 04 Added a link on how to calculate the temperature from the tempout 9 0 value e Editorial updates December 2014 2014 12 15 Added Arria 10 Arria V and Arria V GZ devices to the Device Support section e Editorial changes to the warning message in Temperature Sensing Operation section e Added Arria 10 devices information e Updated template Altera Corporation Altera Temperature Sensor IP Core User Guide CJ Send Feedback UG 01074 2015 05 04 Document Revision History 11 Document Changes Made Version June 2013 3 1 e Updated the2. Altera Temperature Sensor IP Core User Guide Altera Corporation G Send Feedback 8 Altera Temperature Sensor Signals Create an On Off asynchronous clear port Altera Temperature Sensor Signals Legal EZEN Values Values clr UG 01074 2015 05 04 Description Specifies whether to turn on the asynchronous clear clr port Turn on this option when you want to reset the Altera Temperature Sensor IP core When you turn off this option the clear port automatically connects to GND The following tables list the Altera Temperature Sensor IP core signals Table 4 Altera Temperature Sensor IP Core Signals for Arria 10 Devices corectl Input Enables the temperature sensing feature by the IP core reset Input 1 Resets the temperature sensing block tempout 9 0 Output 10 10 bit output data from internal ADC circuitry of temperature sensor block eoc Output 1 Indicates end of internal ADC conversion This signal goes high for one clock cycles and you can latch the data on tempout at the falling edge of EOC Table 5 Altera Temperature Sensor IP Core Signals for Suppported Devices Input Input clock signal that runs at a frequency of 80 MHz and below The internal clock divider reduces the frequency of the c1k signal to 1 MHz or less before clocking the ADC ce Input 1 The asynchronous clock enable signal for the c1k signal This signal turns on of
3. 4 To generate the Altera Temperature Sensor IP core variation file based on the ports and parameter settings in the text file type the following command clearbox alttemp_sense f txt For example clearbox alttemp_sense f sample_param_test txt 5 After the clear box generator generates the IP core variation files you can instantiate the IP core module in a HDL file or a block diagram file in the Quartus II software 6 To view the estimated hardware resources that the Altera Temperature Sensor IP core uses type the following command clearbox alttemp_sense f sample_param_test txt resc_count Note This command does not generate a HDL file Altera Temperature Sensor Device Support The Altera Temperature Sensor IP core supports the following device family e Stratix V e Stratix IV e Arria 10 e Arria V e Arria V GZ Altera Temperature Sensor Parameters The parameters are applicable for all supported devices except Arria 10 devices There are no available parameters for Arria 10 devices You can parameterize the Altera Temperature Sensor IP core using the IP Catalog and parameter editor or with the command line interface CLI Use the parameter editor to quickly specify parameters in a GUI Expert users may choose to instantiate and parameterize the IP core through the command line interface using the clear box generator command This method requires you to have command line scripting knowledge Altera Corporation
4. contains the input and output assignments and a placeholder for the tsa_s4 module To insert the tsad_s4 module double click on the Block Editor window The Symbol window appears Under Name browse to the tsd_s4 bsf file Click OK Place the tsd_s4 module onto the INSERT TSD_S4 BLOCK HERE placeholder so that the module aligns with the input and output ports a A W N Altera Corporation Altera Temperature Sensor IP Core User Guide GJ Send Feedback UG 01074 2015 05 04 Figure 3 Complete Desi Using Clear Box Generator 5 gn File This figure shows the complete design file tsd_s4 oet sa dk ie l ee clk tsdcaldone ene INPUT _ ce inst1 6 On the Processing menu click Start Compilation 7 When the Full Compilation was successful message box appears click OK Using Clear Box Generator Altera Temperature Sensor IP Core User Guide You can use clear box generator a command line executable to configure parameters that are in the Altera Temperature Sensor IP core parameter editor The clear box generator creates or modifies custom IP core variations which you can instantiate in a design file The clear box generator generates IP core variation file in Verilog HDL or VHDL format Note Arria 10 Altera Temperature Sensor IP core does not support clear box generation format To generate the Altera Temperature Sensor IP core using the clear box generator perfor
5. Altera Temperature Sensor IP Core User Guide GJ Send Feedback UG 01074 2015 05 04 Altera Temperature Sensor Parameters 7 This table lists the parameter editor and CLI parameter settings for the Altera Temperature Sensor IP core Table 3 Altera Temperature Sensor IP core Parameter Settings Parameter CLI Parameter Legal Legal Description Values Values General Options Tab What is the 1 0 80 0 clk_frequency 1 0 80 0 Specifies the input frequency input MHz of the c1k signal The input frequency frequency value is type string and the value must be less than or equal to the clock divider value The default value is 1 0 What is the 40 80 clock_divider_value 40 80 Specifies the clock divider clock divider value The IP core divides the value clock frequency value with the clock divider value before feeding the ADC This option is only enabled when the clk signal frequency is more than 1 MHz Altera recommends clocking the ADC with a 500 kHz signal The CLI parameter is type integer Ensure that you enable the clock divider by setting the clock_divider_ enable parameter value to on The default value is 40 Create a clock On Off ce Specifies whether to turn on enable port the asynchronous clock enable ce port Turn on this option when you want to enable the Altera Temperature Sensor IP core When you turn off this option the clock enable port automatically connects to VCC
6. Temperature Sensing Operation on page 3 1 to clarify that enabling the ADC allows you to measure the temperature of the device only once and to include a warning about a minimum pulse violation when input clock derived from a PLL e Updated Features on page 1 1 to notify that this IP core does not provide simulation feature September 2010 3 0 e Updated the Parameter Settings chapter e Added the Prototypes and Component Declarations section e Added the Clear Box Generator chapter February 2010 2 0 Updated the Temperature Sensing Operation section November 2009 1 0 Initial release Altera Temperature Sensor IP Core User Guide G Send Feedback Altera Corporation
7. Altera Temperature Sensor IP Core User Guide 2015 05 04 UG 01074 GX subscribe _ Send Feedback The Altera Temperature Sensor IP core configures the temperature sensing diode TSD block to utilize the temperature measurement feature in the FPGA Note Beginning from the Quartus II software version 14 0 the name of this IP core has been changed from ALTTEMP_SENSE to Altera Temperature Sensor IP core Related Information Introduction to Altera IP Cores Provides general information about Altera IP cores Altera Temperature Sensor Features The following table lists the Altera Temperature Sensor IP core features Table 1 Altera Temperature Sensor Features DISE Features Stratix V Stratix IV Arria V and Arria An internal TSD with built in 8 bit analog to digital V GZ converter ADC circuitry to monitor die temperature e A clock divider to reduce the frequency of the clock signal to 1 MHz or less before clocking the ADC e An asynchronous clear signal to reset the TSD block Arria 10 e An internal TSD with built in 10 bit ADC circuitry clocked by 1 MHz internal oscillator to monitor die temperature e Does not require external clock source e An asynchronous clear signal to reset the TSD block Note The Altera Temperature Sensor IP core does not have simulation model files and cannot be simulated 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX
8. MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO TS RYA 101 Innovation Drive San Jose CA 95134 N UG 01074 2 Altera Temperature Sensor Functional Description 2015 05 04 Altera Temperature Sensor Functional Description Temperature Sensing Operation for Arria 10 Devices Figure 1 Altera Temperature Sensor IP Core Top Level Diagram for Arria 10 Devices The following lists the features for Altera Temperature Sensor IP core for Arria 10 devices e For Arria 10 devices the Altera Temperature Sensor IP core supports the instantiation of temperatur
9. e sensor block in your design from the IP Catalog e The Arria 10 temperature sensor block runs at 1 MHz where the clock signal is coming from the internal oscillator Within the block 10 bit ADC circuitry is included for converting sensor s reading to digital output e The corect1 signal is used as an enable signal When asserting the corect1 signal the ADC starts the conversion and 10 bit data is available at tempout after 1 024 clock cycles The eoc signal goes high for one clock cycle indicating end of conversion You can latch the data on tempout at the falling edge of eoc e You can reset the temperature sensor anytime by asserting the reset signal Related Information Transfer Function for Internal TSD Provides more information on how to calculate the temperature from the tempout 9 0 value Altera Corporation Altera Temperature Sensor IP Core User Guide GJ Send Feedback UG 01074 2015 05 04 Temperature Sensing Operation for Arria V Arria V GZ Stratix IV and Stratix V 3 Devices Temperature Sensing Operation for Arria V Arria V GZ Stratix IV and Stratix V Devices Figure 2 Altera Temperature Sensor Block Diagram This figure shows the top level ports and the basic building blocks of the Altera Temperature Sensor IP core Altera Temperature Sensor IP Core CLOCK DIVIDER oe ce TEMPERATURE SENSOR The Altera Temperature Sensor IP core runs at the frequency of the c1x signal The c1xk signal can run at a
10. f the Altera Tempera ture Sensor IP core that implements the TSD block This is an active high signal By default this port connects to VCC Altera Corporation Altera Temperature Sensor IP Core User Guide GJ Send Feedback UG 01074 2015 05 04 Altera Temperature Sensor Signals 9 Input The asynchronous clear signal When you assert the clr signal the IP core sets the tsdcalo 7 0 signal to 11010101 0xD5 and the tsdcaldone signal to 0 This is an active high signal By default this port connects to GND csdcaloly 204 Output 8 bit output signal that contains the analog to digital conversion temperature value The 8 bit value maps to a unique temperature value During device power up or when you assert the clr signal the IP core sets the tsdcalo 7 0 to 11010101 0xD5 tsdcaldone Output This signal indicates the completion of the tempera ture sensing process The IP core asserts this signal when the process is complete During device power up or when you assert the clr signal the IP core sets the tsdcaldone to 0 Table 6 The Mapping of tsdcalo 7 0 Value to Arria V Arria V GZ Stratix IV and Stratix V Devices Temperature This table shows the value of tsdcalo 7 0 that corresponds to the device temperature range The temperature specification ranges from 70 C to 127 C Value of tsdcalo 7 0 in Hexadecimal Temperature in Degree Celsius C
11. frequency of 80 MHz and below The clock divider divides the c1k signal to 1 MHz or less to feed the ADC You can set the value of the clock divider using the Altera Temperature Sensor IP core parameter editor dk adcclk tsdcalo 7 0 tsdcaldone The ce signal connects to the output enable oe port of the clock divider block Assert the ce signal to enable the Altera Temperature Sensor IP core When you deassert the ce signal the IP core disables the ADC and maintains the previous values of the tsdcalo 7 0 and tsdcaldone signals unless you assert the clr signal or reset the device The cir signal is asynchronous and you must assert the cir signal at least one clock cycle of the adcc1k signal to clear the output ports Enabling the ADC allows you to measure the device temperature only once To perform another tempera ture measurement assert the clr signal or reset the device The clr signal is asynchronous and you must assert the clr signal at least one clock cycle of the ADC c1k signal to clear the output ports Note When you choose not to create the ce port the IP core connects the ce port to VCC In this case the ADC circuitry is always enabled Altera recommends that you disable the ADC by deasserting the ce signal when the ADC is not in use to reduce power consumption During device power up or when you assert the asynchronous c1r signal the Altera Temperature Sensor IP core sets the tsdcaldone p
12. k divider to reduce the clock frequency to be less than or equal to 1 0MHz Related Information Altera Temperature Sensor Signals on page 8 Provides more information about the value of tsdcalo 7 0 that corresponds to the device temperature range Generating the Altera Temperature Sensor IP To generate the Altera Temperature Sensor IP core follow these steps 1 Open the alttemp_sense_ex1 zip file and extract alttemp_sense_ex1 qar 2 In the Quartus II software open the alttemp_sense_ex1 qar file and restore the archive file into your working directory On the IP Catalog window search and click Altera Temperature Sensor In the New IP Instance dialog box type tsd_s4 as your top level file name In the Device family field select Stratix IV Then select your FPGA device family from the Device Family pull down list Click OK In the Parameter Editor set the following parameter settings NA WB WwW Table 2 Configuration Settings for the Altera Temperature Sensor IP Core What is the input frequency 40 MHz What is the clock divider value 80 MHz Create a clock enable port Turned on Create an asynchronous clear port Turned on 8 Click Finish The tsd_s4 module is built Compiling the Altera Temperature Sensor IP To compile the Altera Temperature Sensor IP core in the Quartus II software follow these steps 1 Open the top level file alttemp_sense_ex1 bdf in the Quartus II Block Editor software This file
13. m the following steps 1 Create a text file txt that contains your clear box ports and parameter settings in your working directory For example c altera 10 0 quartus work sample_param_test txt This figure shows a sample text file to generate the Altera Temperature Sensor IP core G Send Feedback Figure 4 Sample Text File for Clear Box Generator P sample_param_test Notepad loj x File Edit Format Yiew Help CBX_HDL_LANGUAGE Verilog CBX_FILE tsd_s4 v CBX_OUTPUT_DIRECTORY c altera 10 O quartus work CBX_MODULE_PREFIX UNUSED CBX_REMOVE_OPTIONAL_WIRES OFF CLK_FREQUENCY 40 0 CLOCK_DIVIDER_ENABLE on CLOCK_DIVIDER_VALUE 80 device_family stratixiy Altera Corporation UG 01074 6 Altera Temperature Sensor Device Support 2015 05 04 Note Ensure that you enclose String type values with double quotes 2 Access the command prompt of your operating system and change the current directory to your working directory by typing the following command cd c altera 10 0 quartus work The clear box executable file name is clearbox exe Note When you install the Quartus II software the QUARTUS_ROOTDIR bin is added into your system s environment variables Therefore you can run the clear box command from any directory 3 To view the available ports and parameters for this IP core type the following command at the command prompt of your operating system clearbox alttemp_sense h
14. ort to 0 and the tsdcalo 7 0 signal to 11010101 or 0xD5 After 10 clock cycles of the adcc1k signal the Altera Temperature Sensor IP core asserts the t sdcaldone signal to indicate that the temperature sensing operation is complete and that the value of the tsdcalo 7 0 signal is valid The value of the tsdcalo 7 0 signal corresponds to the device temperature range For more information about the value of tsdcalo 7 0 signals refer to the Related Information To start another temperature sensing operation assert the clr signal for at least one clock cycle of the adcc1k signal or reset the device Altera Temperature Sensor IP Core User Guide Altera Corporation G Send Feedback UG 01074 4 Generating the Altera Temperature Sensor IP 2015 05 04 Note When you choose not to create the clr port the Altera Temperature Sensor IP core connects the clr port to GND In this case you must reset the device to clear the output signals or start a temperature sensing operation Altera recommends that you generate the clr port if you are planning to run the temperature sensing operation more than once If a derived PLL output clock is used to drive the Altera Temperature Sensor IP core a minimum pulse violation might occur When using the Altera Temperature Sensor IP core you must ensure the clock applied must be less than or equal to 1 MHz If you are using a higher frequency clock the Altera Temperature Sensor IP core allows you use the 40 or 80 cloc
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